(Invited) Technology Scaling from Bulk to Fin and Nano-Sheet Transistors
Authors: Endo Kazuhiko 
Published: February 2024

In recent years, scaling of semiconductor device has progressed, leading to the development of advanced semiconductor devices with code names of below 10-nm. Various new materials and technologies have been introduced to accompany the miniaturization of semiconductor devices. First, the resistivity of aluminum became higher due to miniaturization, and aluminum was replaced by copper as the wiring metal. Then, to increase the gate capacitance of MOS field-effect transistors, the thickness of the gate insulating film (SiO2) was reduced to the limit, and as a result, gate leakage current could no longer be suppressed, which led to the introduction of a high-k gate insulating films (HfO2).
The next bottleneck in miniaturization was the suppression of short channel effects. As the gate length became smaller, the gate electrode's control over the channel decreased, resulting in the generation of a small amount of leakage current even when the transistor is turned off, and the threshold voltage also fluctuated as the gate length became shorter, which interfered with circuit operation. To suppress the short-channel effect, the conventional bulk transistor was replaced around 2011 by a transistor with an upright channel, called a fin transistor. The purpose of this is to increase the gate's dominance over the channel, suppress leakage current, and prevent the short-channel effect by having multiple opposing gate electrodes for the raised channel. However, since the channel width of a fin transistor corresponds to the sidewall height, a fin with a high height must be formed to increase the channel width and gain total current density, which has been a problem in terms of processing technology. In addition, in order to increase the current, a layout configuration with multiple fins formed horizontally had to be adopted, which increased the area of the chip, thereby hindering the integration of the chip.
This leads to an increase in the area of the chip, which in turn hinders high integration of the chip. The nanosheet transistor is a new transistor structure in which multiple 10-nm-thick "nanosheets" of silicon are stacked in the height direction to form the transistor channel. Another major feature of this nanosheet transistor is the use of a gate all-around structure, which is a further development of the gate structure of the double gate type. As a result, this structure is the most effective in suppressing short channels. Furthermore, by stacking nanosheets vertically, it is possible to increase the current density per unit area without increasing the chip area.
As a further evolution of the nanosheet transistor, a complementary FET (CFET) structure is currently being considered, in which pMOS and nMOS are stacked vertically to realize a CMOS circuit in the vertical direction. So far, CFETs with pn stacked in silicon and attempts to form CFETs by laminating silicon and germanium together have been presented.
In Japan, research and mass production of this nanosheet type transistor has recently been planned, overtaking mass production of fin transistors.