Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors
Authors: Durfee Curtis , Otto IV Ivo , Kal Subhadeep , Pancharatnam Shanti , Flaugh Matthew , Kanaki Toshiki , Rednor Matthew , Zhou Huimei , Qin Liqiao , Meli Luciana , Loubet Nicolas , Biolsi Peter , Felix Nelson 
Published: February 2024

Nanosheet (NS) gate-all-around (GAA) devices have demonstrated advantages in device performance and area scaling over finFET devices [1-11]. Enablement and future scaling of GAA devices require robust etch processes for Inner Spacer (IS) and Channel Release (CR) for well-controlled device performance and yield (Fig. 1). CR requires an isotropic, complete etch of the sacrificial SiGe layer with extremely high selectivity to the spacer (Sp0), IS, and Si channels. Furthermore, during CR, the Si channels must be released simultaneously for all sheet widths (WNS) [1], which range from 20nm to 100nm, necessitating significant over-etch (OE) on the narrowest sheets. We demonstrated excellent device performance across all WNS with more than 150 % OE on the widest sheets [1]. However, this extreme OE makes the pFET source/drain (S/D) SiGe:B especially vulnerable to damage. In this paper, we explore several mechanisms that result in SiGe:B S/D damage and demonstrate how to prevent the damage with IS, CR, and S/D epitaxial optimization.
The S/D Si:B and Si:P used in our high-performance test devices are not susceptible to damage during CR due to high etch selectivity [2]. Thus, SiGe:B S/D is required to evaluate the mechanisms causing S/D damage. To enable these studies, we developed high-quality S/D SiGe:B, which shows substantial device performance improvement over our baseline S/D Si:B, with 150% increase in peak mobility, 50% reduction in Vt, and 45% reduction in Ron (Fig. 2).
The ability to target IS thickness allows tuning of device performance through Cov and Ron and is critical for future device scaling. In addition, the IS plays a critical role as a physical barrier to prevent S/D damage during CR [1,2]; reducing IS thickness below a critical value can result in S/D damage. The optimal IS thickness is determined by balancing maximum device performance for all WNS while maintaining S/D integrity during CR. This process window can be maximized by optimizing the CR etch process, and can be further increased by integrating an Si:B buffer in the S/D epitaxy. We have developed four CR processes with different chemistries and evaluated their process windows.
We evaluated S/D damage for two CR processes versus IS thickness. We observed no S/D damage with Process A until 4nm IS thickness at 50% OE (Fig. 3a). Process C showed no damage at 4nm IS thickness, even up to 100% OE. The plan-view TEM in Fig. 3a shows that S/D damage occurs at the corners of the S/D region as well as at the center, indicating several mechanisms for S/D damage (see Fig. 4): CR etch gas permeation through the IS, exposed S/D through pinholes in the IS or at the IS edges due to rounded IS shape, and exposed S/D at the intersection of the Si/SiGe fins and gate.
To isolate and characterize permeation of the CR etch gas through the IS, we deposited various thicknesses of IS on SiGe/Si multilayers (Fig. 5a), then exposed the structures to CR Process A. The SiGe layers showed no damage until the IS layer was thinned to <1nm. The difference in critical thickness for etch gas permeation on fully integrated structures compared to these test structures (4nm compared to <1nm) could be attributed to the other mechanisms.
S/D damage due to IS permeation can be prevented by a better quality IS; by optimizing the CR chemistry to tune the selectivity between the sacrificial SiGe and the S/D SiGe:B (Fig. 5b); or by integrating a Si:B buffer prior to S/D SiGe:B deposition (Fig. 6). The process window then can be maximized by selecting the best CR process since selectivity to Si:B and permeation through the IS varies with the chemistry. Fig. 7 shows the improvement in the process window with a 2nm Si:B buffer on wafers with no IS for Processes A, B and C.
The other S/D damage mechanisms highlighted in Fig. 4 are characterized in Fig. 3b. The S/D damage starts at the corners of the active region and the extent of damage increases with CR OE. These failure modes require changes in integration to improve the Sp0 at the fin-gate corner, reducing the IS rounding, or creating a straighter etch front across the sheet [2].
S/D damage during CR is a significant issue in NS architecture. This can be mitigated by optimizing the CR etch process, incorporating an Si:B buffer layer, improving the IS quality or shape, and improved integration. Understanding these mechanisms is critical to ensure robust S/D quality with scaling for future technology nodes.

Figure 1