Degradation and Failure Mechanism of p-GaN Gate E-Mode GaN HEMTs
Authors: Mehta Abhas , Shichijo Hisashi , Joh Jungwoo , Suh Chang , Kim Moon 
Published: February 2024

GaN-based power transistors are becoming pivotal devices for high power and high voltage operation due to their higher breakdown voltage, higher carrier mobility because of two-dimensional electron gas (2-DEG), better thermal resistance, higher frequency switching, and lower on-state resistance (RON) [1]. P-GaN gate E-mode GaN HEMTs have emerged as a center of extensive research to understand their operation and reliability [2]. However, one of the reasons the E-mode GaN HEMTs are not yet successfully utilized to their maximum potential is the lack of complete understanding of gate breakdown. Gate degradation of p-GaN gate E-mode GaN HEMT is less understood because of the complexities involving the operating conditions and variables such as gate length, the acceptor doping concentration in the p-GaN layer [3], p-GaN gate thickness, and design of the device [4-5]. To outline a consistent degradation mechanism, this work aims to present an electro-physical model of gate breakdown in p-GaN gate E-mode HEMTs.
Lateral E-mode GaN HEMT devices with p-GaN gate configuration are used for this study. According to the Scanning Transmission Electron Microscopy (STEM) imaging of a new device, the AlGaN barrier is 10 nm thick, and the p-GaN cap is 65 nm. The gate-source and gate-drain lengths are 0.5 micrometer and 2.5 micrometer, respectively. The gate length defined by the p-GaN layer is 0.5 micrometer and the edges of the gate metal are pulled in from the top edge of the p-GaN layer by 40 nm. A 0.7 micrometer-long, source-connected field plate is over the p-GaN gate. The p-GaN gate is subjected to static stress to induce accelerated breakdown. Devices were stressed with HP 4155 Semiconductor Analyzer. The electrical measurements were performed with the source, drain, and substrate connected to the ground. FEI 200 Nova was used for Scanning Electron Microscopy (SEM) imaging and Focused Ion-Beam (FIB) milling. ARM JEM-200F with a Cs corrector was used for STEM.
Our results show that time-to-fail is highly dependent on device operating conditions. We found no correlation between time-to-fail and initial gate current (IG0). Instead, a higher impact of temperature was found on the gate current of the device (IG) and time-to-fail at 100 °C. Gate failure at constant voltage stress was a single-stage failure. Under constant current stress, on the other hand, the gate shows a multi-stage failure. The breakdown mechanism depends on the impact of static stress on the gate degradation, starting with increased gate current leading to Schottky barrier leakage and finally to catastrophic contact failure. Our study shows that the metal/p-GaN interface at the gate finger becomes the weakest part of the gate stack, likely to be the initiation point of degradation. Metal/p-GaN interface and surface defects develop as percolation paths acting as leakage sources, and nano-cracks have been observed in the gate cap. FA also shows physical degradation at the metal/p-GaN cap due to electrical stress. Observed physical damage in the gate region is correlated to the gate leakage characteristics to develop an electro-physical failure model for gate breakdown in p-GaN gate E-mode GaN HEMTs.
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