bluuebunny/crossref_metadata_2025_split huggingface dataset:
Perception on Collaborative Writing, Self-efficacy and Writing Achievement in Information Technology Era : A Correlational Study
Authors: Aziz Abdul , Anwar Khoirul , Asari Slamet 
Published: November 2023

This mix method study investigated the correlation among students’ perception on collaborative writing (SPoCW), students’ self-efficacy (SSE) and students’ writing achievement (SWA). The quantitative data of the study was gained from 62 students who have been taught using collaborative writing during one semester. The data included the students’ perception on collaborative writing questionnaire adapted from [1]. The questionnaire consisted of 18 statements with a five Likert scales. The reliability is 0.892. While students’ self-efficacy is measured using self efficacy questionnaire consists of 23 statements adopted from [2] with the reliability is 0.80. Using correlation Pearson Product Moment, It was found that SPoCW correlated with SSE and the score is 0.377. To investigate the correlation between independent variable (SPoCW and SSE) and dependent variable (SWA), the researcher used Analysis Model Summary, it showed that R Square value is 0.394. This mean that the effect of SPoCW and SSE toward students writing achievement is 39.4 % and the rest is influenced by another factor. While to get qualitative data, semi structure interview was randomly given to the students and it was revealed that mostly students felt confident and had a new writing experience with collaborative writing which strengthen the investigation. It is recommended to build good students’ perception and self-efficacy for best writing achievement.
PERLINDUNGAN DATA PRIBADI ANAK DALAM E-COMMERCE DI MASA PANDEMI COVID-19
Authors: Sahetapy Wilma Laura 
Published: November 2023

AbstractThe Covid-19 pandemic has become a problem for children who are studying distance learning. The existence of distance learning makes children closer and more in touch with digital technology. Information and communication technology is one of their learning tools. But without realizing it, these minors are trapped in a virtual world that they do not know the dangers of. Because not all children have the correct knowledge about the digital world. Therefore, parents who do not provide supervision to their children are prone to new problems. Many children spend this distance learning period also with entertainment using social media and online games. It is unnoticed by children that personal data such as email address, first name, last name, hobbies, photos, videos are not protected. Personal data protection needs to be considered for children, especially during the Covid-19 pandemic.Keywords: child; e-commerce; personal dataAbstrakMasa pandemi Covid-19 menjadi masalah tersendiri bagi anak-anak yang menempuh pendidikan dengan pembelajaran jarak jauh. Adanya pembelajaran jarak jauh membuat anak-anak untuk lebih dekat dan banyak bersentuhan dengan teknologi digital. Teknologi informasi dan komunikasi yang menjadi salah satu alat pembelajaran mereka. Namun tanpa disadari, anak-anak dibawah umur tersebut terjebak dalam dunia maya yang mereka tidak tahu bahaya di dalamnya. Sebab tidak semua anak mempunyai pengetahuan yang benar mengenai dunia digital tersebut. Oleh karena itu bagi orang tua yang tidak memberikan pengawasan terhadap anak-anaknya rawan bermunculan permasalahan baru. Banyak anak-anak yang menghabiskan masa pembelajaran jarak jauh ini juga dengan hiburan menggunakan sosial media dan game online. Hal ini tanpa disadari oleh anak-anak data pribadi seperti alamat email, nama depan, nama belakang, hobi, foto, video tidak terlindungi. Perlindungan data pribadi perlu diperhatikan bagi anak khususnya di masa pandemi Covid-19.
Dimensionality Reduction and Clustering by Yield Signatures to Identify Candidates for Failure Analysis
Authors: De La Torre James , Kent Don , Pivin David , St Pierre Eric 
Published: November 2023

Abstract
The job of yield and failure analysis (YA and FA) engineers is to identify the root cause of low-yielding wafers. While physical FA is the most definitive method for determining root cause, resource limitations require YA engineers to search for root cause by identifying other wafers with similar yield signatures. The immense number of yield parameters, or features, collected in modern semiconductor processes makes this a difficult task. This paper presents a workflow employing multiple AI techniques to separate groups of wafers by their distinct yield signatures and determine the parameters most important to defining each group. This aids in the disposition of new low-yield wafers, maximizes the learning from previously collected FA wafers, and allows FA resources to be allocated more effectively, prioritizing them for the highest-impact, unknown fail modes.
Multimodal Named Entity Recognition for Semiconductor Failure Analysis
Authors: Safont-Andreu Anna , Grabner Corinna , Burmer Christian , Schekotihin Konstantin 
Published: November 2023

Abstract
During the activity in the Failure Analysis (FA) laboratory, all corresponding findings and conclusions are included in a series of documents known as the FA reports. They shall, in the first place, inform the requestor about the analysis results. But additionally, they shall provide information to solve similar cases. Therefore, these documents play a key role in preserving the knowledge acquired by the engineers as they become available for consultation during future works. The different information systems in FA consist of databases, file shares, wikis, or other human-readable forms. However, the heterogeneity of these databases and the large number of independent documents make it inefficient for manual consultation. In this context, this paper proposes an application of Natural Language Processing (NLP) known as Named Entity Recognition (NER), consisting of an AI-based detection of key concepts in textual data in the form of annotations. These annotations can then be used to boost search systems or other AI models.
Fully Automated AI Based Crack Detection on Pad-Over-Active-Areas
Authors: Pfister D. , Felux F. , Hollerith C. , Jansche A. , Volman Stern M. O. 
Published: November 2023

Abstract
The goal of this work was to automate the crack detection of pads on a wafer piece. This process allows the engineer to check a huge number of pads for cracks to obtain a meaningful statistical result of the Pad-Over-Active-Areas (POAA) stability, which is a typical task in the failure analysis laboratories. It is possible that cracks in POAA appear during the electrical test or the bonding process. The current analysis process is very time consuming as thousands of pads have to be inspected for cracks by an engineer. The process starts with the chemical preparation of a wafer piece to make the crack below the pad visible. After that, the engineer examines each pad individually through the optical microscope for cracks. For the automation of this process a new workflow had to be developed and is described in this work. Moreover, it comprises the automation of a light microscope as well as an automated image evaluation based on a neural network.
Electrical Fault Isolation of Stuck at Reset Hard Failures
Authors: Sampath Amrutha , Wu Carey , Dickson Kristofor 
Published: November 2023

Abstract
Hard failures, especially the Stuck at Reset failures insensitive to voltage, frequency, and temperature, are among the toughest to debug using the conventional Electrical Fault Isolation Methodology. These types of failures have no test data and no diagnostic information. Because of the failure being stuck at the reset sequence and being a hard failure, methodologies like Laser-Assisted Device Alteration (LADA) cannot be carried out. Photon Emission Microscopy (PEM) may exhibit numerous differences for good vs. bad die, however, most emission signatures typically indicate where IP is stuck in reset but do not indicate the actual root cause. Laser Voltage Probe (LVP) is the most logical way to proceed, but since Power-on Reset (POR) signals typically transition only once per test in conjunction with hard power cycling, the LVP averaging became very difficult as the hard power cycling increased the time of the loop drastically. This paper discusses a novel methodology of modulating power supply voltages within a looping pattern to optically probe the critical internal POR signal transitions effectively and debug the power sequencing of the device. This method is carried out through a custom test setup where a particular power supply of interest is modulated within the test loop without powering down other supplies connected, thereby avoiding the time penalty required for complete power down and power up. The method also synchronizes internal signals associated with POR to a tester-generated trigger in order to successfully obtain recognizable internally extracted POR-associated waveforms. This methodology is conveyed by explaining a complex functional failure analysis case study while highlighting where conventional failure analysis methods could not be used directly to identify the root cause of failure. This paper also describes another case study to explain how parametric information, such as the current profile using the current probe obtained during the test on a pass vs. fail device, can provide valuable information and help debug stuck-in reset failures.
Enhancing Device Margins Using Double-Gate Oxide in Buried-Gate FETs
Authors: Kim Youmin 
Published: November 2023

Abstract
Device shrinkage and mitigation of off-state power consumption are crucial factors in dynamic random access memory (DRAM) product development. Given the market demand for high-quality devices, the reduction and fluctuation of DRAM cell retention time, caused by interface traps, required a suitable solution for improved product quality. In this study, we propose a device structure for the reduction of GIDL current by implementing a second gate oxide in the overlapping region of the gate and the drain, and to calculate an increment in the margin for other processes from the retention time improvements, the virtual a capacitance of the bit line/a capacitance of the storage cap(Cb/Cs) evaluation was performed. This study is expected to provide a solution to the trap-induced retention- time deterioration and assist in the development of next-generation DRAM.
Avalon-Aided Mapping of Fault-Localized Area of ADI’s RADAR Receive Path Analog Front-End (AFE) Amplifier with 0.18um 6-Metal CMOS Fab Process
Authors: Evangelista Arnulfo , Alfelor-Igtiben Janella , Mangali John David , Cajucom Khristopherson 
Published: November 2023

Abstract
Analog Devices Inc. (ADI)’s Radar Receive Path Analog Front End Amplifier (AFE) with a 0.18um 6-metal Fab Process has failures related to Power-Down and Scan test parameters which were endorsed for Failure Analysis. Fault localization is quite challenging because it involves 6 metal layers. This has been resolved with the availability of Synopsis Avalon software with capability to convert the complete Cadence schematics and layout that is usable for Failure Analysis, through cross-mapping with the fault localized area-of-interest (AOI) on the actual reject part with the die schematics and layout, and identifying the failing component and circuit block. This leads to the creation of the failure model related to the reported failure mode and the determination of the appropriate failure mechanism related to fabrication defects between the adjacent metallization layers and defects on between the polysilicon and substrate layer. This helps speed up the FA Cycle Time and achieve an accurate failure mechanism, which later resolves the fab defect issue with the Fab process owner.
A Multiscale and Multimodal Correlative Microscopy Workflow to Characterize Copper Segregations Identified in Epitaxial Layer of Power MOSFETs
Authors: Cognigni Flavio , Rossi Marco , Stegmann Heiko , Sciuto Giuseppe , Anastasi Giuseppe , Astuto Massimiliano , Bonadonna Marco , Mello Domenico 
Published: November 2023

Abstract
Power MOSFETs are electronic devices that are commonly used as switches or amplifiers in power electronics applications such as motor control, audio amplifiers, power supplies and illumination systems. During the fabrication process, impurities such as copper can become incorporated into the device structure, giving rise to defects in crystal lattice and creating localized areas of high resistance or conductivity. In this work we present a multiscale and multimodal correlative microscopy workflow for the characterization of copper inclusions found in the epitaxial layer in power MOSFETs combining Light Microscopy (LM), non-destructive 3D X-ray Microscopy (XRM), Focused-Ion Beam Scanning Electron Microscopy (FIB-SEM) tomography coupled with Energy Dispersive X-ray Spectroscopy (EDX), and Transmission Electron Microscopy (TEM) coupled with Electron Energy Loss Spectroscopy (EELS). Thanks to this approach of correlating 2D and 3D morphological insights with chemical information, a comprehensive and multiscale understanding of copper segregations distribution and effects at the structural level of the power MOSFETs can be achieved.
Inline Defect Solution to Mitigate EOL Device Failure
Authors: Guo Yong , MacDonald Brian , Guo Yanan , McEwen Nathan , Kim Juheon , Penley Christopher 
Published: November 2023

Abstract
The challenges keep rising for fault isolation and failure analysis (FIFA) for the advanced semiconductor devices fabricated via integrated processes. Perceiving that defects randomly occurred during IC manufacturing contribute primarily to the device failures in comparison to those caused by harsh service environmental, we focus our efforts on fixing the defect issues in the processes, expecting a significant portion of the device failures may be prevented. A case study here demonstrates the procedure for fixing an inline defect issue via improving tool maintenance for the chemical-mechanical polishing (CMP) process. Through a correlative physical and chemical analysis down to atomic scale, a 10 nm diamond particle and a 10 nm metallic debris damaging one of the metal interconnect layers were defined. The analysis led to pinpointing the issue to a metal CMP process. By examining the process operation and the tool configuration, we located the diamond-missing sites on a pad-conditioning disk made with embedded diamond grits in a metal matrix. Preventive countermeasure were implemented to avoid the same defect recurring via resetting the disk life and maintenance.
Implementation of RFID-based Equipment Management System for Failure Analysis Laboratory Equipment
Authors: Castillo Acer Jay , Acedillo Mark Anthony 
Published: November 2023

Abstract
Completion of failure analysis (FA) cases require a lot of expensive equipment and tools. Equipment Management System (EMS) is a must to safeguard the equipment from being down/damaged due to uncertified/untrained and high number of users and to avoid high repair cost of the FA laboratory equipment. The purpose of this paper is to present the RFID-based equipment management system for failure analysis laboratory equipment which has the capability to limit the equipment usage to authorized and certified users, locks and unlocks the equipment, and controls the real-time status of the equipment.
Photon Emission Intensity Analysis for Leakage Source Identification
Authors: Song Zhigang , Stellari Franco , Tran Phong 
Published: November 2023

Abstract
Photon Emission Microscopy (PEM) is a popular technique for microelectronics failure analysis by detecting the photon emission from a defective circuit, when a failing device is electrically exercised at certain voltage. The photon emission contains physical location information, photon emission spectral information and photon emission intensity information. People often use the physical location information to localize a defective circuit and guide the follow-up physical failure analysis to find the defects. However, this procedure does not always work. Sometimes, it shows no defect found (NDF). In this paper, we propose a new computer vision-based analysis of the photon emission intensity for identifying the root cause of the excessively high IDDQ at elevated Vdds. The procedure includes collecting photon emissions at different Vdds and a follow-up photon emission intensity analysis with computer vision techniques. The procedure was applied on a case of microprocessor chip. After analyzing the dependencies of photon emission intensity on Vdd for 4 types of circuits, it was concluded that the SRAM circuit leakage is the root cause of the excessively high IDDQ at elevated Vdd.
Fault Simulation for Dynamic Failures in Analog and Mixed Signal Circuits
Authors: Melis Tommaso 
Published: November 2023

Abstract
The localization of defects that cause dynamic electrical behavior is a constant challenge for failure analysts. Such types of failures are often present in analog circuits, and standard fault isolation techniques are constrained and not always successful. In this paper, we demonstrate a method to exploit industrial fault simulators in conjunction with standard analysis methods to solve analyses in analog circuits. In addition, we will show methods to adapt fault simulation to these dynamic electrical failure modes. Successful fault isolation results from real-world failure analyses of oscillators, which are typical inside analog and mixed-signal circuits.
A Failure Caused by Extended Cross-Defect in DRAM
Authors: Lee Jaehoon , Kim Jinseon , Han Dongguk , Lee Seunghun , Kim Sunwoo , Seol Jingyeong , Lee Seungjin , Cho Kyoungrak , Nam Incheol , Kim Daesun , Lee Beomseop , Hong Heeil , Hwang Sangjun 
Published: November 2023

Abstract
As memory devices decrease in dimensions, particles are found to be a major source of defects in unexpected DRAM failures due to their relatively large size. Among many DRAM defects, cross-defects account for the majority of system failures for a long time. Hard cross-defects are frequently observed in the first test step. Most of these defective cells are repaired with row or column redundancy resources. However, after high voltage and temperature stress, some of the cross-defects can additionally spread to adjacent rows or columns with reduced resistance. Recently, a new type of bridge cross-defect accompanied by row failures has emerged. This can be detected electrically through current measurements of 2 wordline (WL) under active mode. But, these defects are not obvious even after both high temperature and voltage stress. The bridge causes intermittent failure in the row-direction during DRAM operation. This soft 2-WL bridge is considered a serious fault source that can cause uncorrectable error (UE) at the system level even though on-die error correction code (ODECC) is introduced. Therefore, it is very important to find, improve, and develop control methods on such defects for future DRAM enhancement. In this paper, 2-WL defects or extended cross-defect were intensively analyzed through electrical failure analysis (eFA) and physical FA (pFA). Results reveal fine particles as the cause.
Application of Beam Deceleration to Improve SEM Image Quality for Physical Failure Analysis
Authors: Scott Robert , Schnutenhaus Tim , Torres Andres , McEwen Nathan , Chin Cheong Kah , Penley Christopher 
Published: November 2023

Abstract
As technology nodes continue to shrink, Scanning Electron Microscopy (SEM) inspection and electrical characterization of transistors has increased in difficultly. This is particularly true with early back end-of-line (BEOL) features like metal and via layers which are traditionally imaged at 3-5 keV. At these layers, this energy is capable of beam contamination, introducing electrical complications particularly with transistor probing. This electrical data is necessary to characterize subtle defects at front end-of-line (FEOL). Thus, the implementation of beam deceleration for the inspection of these layers provides a useful combination of low landing energy and higher image quality. This technique proves to aid in preserving the ability to electrically characterize any defect at the subsequent layers beneath. This increases the quality of the Physical Failure Analysis (pFA) workflow when implemented at early BEOL layers by providing higher quality images as well as preserving the electrical properties of the transistors for subtle FEOL defect characterization.
ICCDLAB : Silicon Chip Tooling for Failure Analysis Laboratories
Authors: Lysee Nicolas , Parrassin Thierry , Le Gloanec Céline , Borot Bertrand , Dudit Sylvain 
Published: November 2023

Abstract
The ICCDLAB (Integrated Circuit for Characterization and Debug Laboratory) test chip is a full custom silicon chip dedicated to failure analysis. This chip embeds several custom devices designed to highlight, reproduce, and simulate defects, as well as enhance the signatures obtained through failure analysis techniques that are used to locate defects in circuits. The ICCDLAB serves as a versatile tool for failure analysts, providing a “Swiss army knife” and a failure analysts’ playground at the same time. The chip offers a simple means of covering an exhaustive catalog of failure analysis techniques and approaches, allowing for equipment benchmarking, training of individuals new to the failure analysis field, understanding of failure mechanisms and signatures, simulation of defect behaviors, and support for development of new techniques.
Open Localization with LIT
Authors: van Veenhuizen Marc , Wan Jinbo , Yang Shuhan , Peters-Wu Lei 
Published: November 2023

Abstract
This paper discusses a method to observe open traces with the LIT. An overview is given of FA techniques capable of localizing high Ohmic fails. It is discussed how a wire can be made observable with LIT by injecting an AM modulated RF carrier signal. The electrical stimulus is described that excites the device and triggers the LIT. Results that demonstrate the capability of the technique are presented for several devices and the findings are evaluated.
Inverter Characterization in Advanced Process by Nanoprobing
Authors: Tsai J.S. , Yen C.H. , Tzou D.Y. , Ho K.T. 
Published: November 2023

Abstract
As the semiconductor process node enters into advanced process era, it is more challenging to extract electrical behavior of devices and circuits by nanoprobing systems. Not only probing is getting difficult at smaller contact or via, but also the deprocess tricks would have large influence on probing conditions, which could cause incorrect electrical performance and hard to explain the reasons. This research develops the technique of sample preparation to extract correct transfer curve of inverter cell in FinFET process.
Autoencoder-Based Defect Detection is Applied to CAFM Images of Periodical Structures
Authors: Solovey Alexey , Zhang Chuan 
Published: November 2023

Abstract
An autoencoder-based approach is applied to CAFM images of the chip memory. Latent features visualizing highlights the regions, that could be of the interest to estimate the typical failures: missing contact, additional contact, not sufficient contact. Preliminary results are provided.