bluuebunny/crossref_metadata_2025_split huggingface dataset:
HLS
Authors: Oskin Mark , Chong Frederic T. , Farrens Matthew 
Published: July 2004

As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and symbolic execution to evaluate design alternatives. This simulation methodology allows for quick and accurate contour maps to be generated of the performance space spanned by design parameters. We validate the accuracy of HLS through correlation with existing cycle-by-cycle simulation techniques and current generation hardware. We demonstrate the power of HLS by exploring design spaces defined by two parameters: code properties and value prediction. These examples motivate how HLS can be used to set design goals and individual component performance targets.
Additionally, these traces are not as susceptible to transient behavior because they are restricted to frequently executed code. Empirical results show that on average this mechanism can achieve better instruction fetch rates using only 12KB of hardware than a trace cache requiring 15KB of hardware, while producing long, persistent traces more suited to optimization.
Wattch
Authors: Brooks David , Tiwari Vivek , Martonosi Margaret 
Published: July 2004

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.
This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.
We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
Lx
Authors: Faraboschi Paolo , Brown Geoffrey , Fisher Joseph A. , Desoli Giuseppe , Homewood Fred 
Published: July 2004

Lx is a scalable and customizable VLIW processor technology platform designed by Hewlett-Packard and STMicroelectronics that allows variations in instruction issue width, the number and capabilities of structures and the processor instruction set. For Lx we developed the architecture and software from the beginning to support both scalability (variable numbers of identical processing resources) and customizability (special purpose resources).
In this paper we consider the following issues. When is customization or scaling beneficial? How can one determine the right degree of customization or scaling for a particular application domain? What architectural compromises were made in the Lx project to contain the complexity inherent in a customizable and scalable processor family?
The experiments described in the paper show that specialization for an application domain is effective, yielding large gains in price/performance ratio. We also show how scaling machine resources scales performance, although not uniformly across all applications. Finally we show that customization on an application-by-application basis is today still very dangerous and much remains to be done for it to become a viable solution.
A few examples of how to use a symmetrical multi-micro-processor
Authors: Mazare Guy 
Published: July 2004

This paper presents an overview of an architecture of a multi-micro-processor architecture in which all processors are equivalent. The structure is characterized by a central memory and several caches, and is designed to avoid incoherent data. A fast mechanism of “subcontracting” between one processor and another is described.
The execution of two simple programs under this architecture is studied. The parallel algorithms are described and compared with the original (sequential) algorithms; it is shown that the overhead remains small, few extra memories are necessary and synchronization do not slow down the execution unduly. Furthermore, the locality of the parallel algorithm is compared to that of the sequential algorithm and is found to be less good, but in a reasonable way. As well, an estimation of the cost of the coherence keeping mechanism is given using the difference between the miss ratio of the classical cache and the “coherence keeping cache”, respectively.
The architecture of an ALGOL 60 computer implemented with distributed processors
Authors: Haynes Leonard S. 
Published: July 2004

In conventional computer systems, the computer hardware does not actually execute the user's source program. Instead, a software compiler and link editor transform the program into low level machine code which is executed by the hardware.
This mapping from a high-level language to a von Neumann instruction set is
a. Computationally costly because compilers and link editors are big and slow.
b. Inefficient because the object code is generally poor.
c. Error prone because compilers and link editors are difficult to design, debug, and maintain.
Furthermore, diagnostic messages for execution errors (an arithmetic overflow for example) are either cryptic and require the user to be familiar with the machine language (i.e., a dump), or the object code generated must require considerable run time overhead to permit run time errors to refer back to the users source program (i.e., pointers and tables, etc.).
Information content of CPU memory referencing behavior
Authors: Hammerstrom D. W. , Davidson E. S. 
Published: July 2004

The memory reference trace of a computation is modeled as a probabilistic process and the information content of that process is derived. Techniques are developed for analyzing the effectiveness of the addressing architecture and Memory/CPU traffic of existing machines with respect to the information theoretic bound for a given trace.
Several techniques for analyzing particular aspects of addressing architecture are also developed. Possible areas of improvement for addressing architecture, compilers, and memory architecture are suggested for performance enhancement.
Interface, a dispersed architecture
Authors: Vissers Chris A. 
Published: July 2004

Past and current specification techniques use timing diagrams and written text to describe the phenomenology of an interface.
This paper treats an interface as the architecture of a number of processes, which are dispersed over the related system parts and the message path. This approach yields a precise definition of an interface. With this definition as starting point, the inherent structure of an interface is developed. A horizontal and vertical partitioning strategy, based on one functional entity per partition and described by a state description, is used to specify the structure. This method allows unambiguous specification, interpretation, and implementation, and allows a much easier judgement of the quality of an interface. The method has been applied to a number of widely used interfaces.
The architecture of a Linda coprocessor
Authors: Krishnaswamy V. , Ahuja S. , Carriero N. , Gelernter D. 
Published: July 2004

We describe the architecture of a coprocessor that supports the communication primitives of the Linda parallel programming environment in hardware. The coprocessor is a critical element in the architecture of the Linda Machine, an MIMD parallel processing system that is designed top down from the specifications of Linda. Communication in Linda programs takes place through a logically shared associative memory mechanism called tuple space. The Linda Machine, however, has no physically shared memory. The microprogrammable coprocessor implements distributed protocols for executing tuple space operations over the Linda Machine communication network. The coprocessor has been designed and is in the process of fabrication. We discuss the projected performance of the coprocessor and compare it with software Linda implementations.
This work is supported in part by National Science Foundation grants CCR-8657615 and ONR N00014-86-K-0310.
The VMP multiprocessor: initial experience, refinements, and performance evaluation
Authors: Cheriton D. R. , Gupta A. , Boyle P. D. , Goosen H. A. 
Published: July 2004

VMP is an experimental multiprocessor being developed at Stanford University, suitable for high-performance workstations and server machines. Its primary novelty lies in the use of software management of the per-processor caches and the design decisions in the cache and bus that make this approach feasible. The design and some uniprocessor trace-driven simulations indicating its performance have been reported previously.
In this paper, we present our initial experience with the VMP design based on a running prototype as well as various refinements to the design. Performance evaluation is based both on measurement of actual execution as well as trace-driven simulation of multiprocessor executions from the Mach operating system.
Banyan networks for partitioning multiprocessor systems
Authors: Goke L. Rodney , Lipovski G. J. 
Published: July 2004

This paper describes a class of partitioning networks, called banyans, whose cost function grows more slowly than that of the crossbar and whose fan-out requirements are independent of network size. Such networks can economically partition the resources of large modular systems into a wide variety of subsystems. Any possible partition can be realized by paralleling several networks or by multiplexing a single network in a manner to be described later. Results will be given indicating that a cost/performance advantage over the crossbar can be obtained for large systems and that the crossbar can, in fact, be considered a non-optimal special case of a banyan network. Inherent fail-soft capability and the existence of rapid control algorithms which can be largely performed by distributed logic within the network are also important attributes of banyans.
This paper presents fundamental properties and preliminary simulation results of banyan partitioning networks. A more detailed treatment, including proofs of theoretical properties, is reserved for reference (5).
A hardware laboratory for computer architecture research
Authors: Vaucher Jean , Rey Christian 
Published: July 2004

Because of dramatic reductions in cost of mini-computers, peripherals and logic modules, it is becoming evident that many problems confronting the computer system designer will be solved in the future by hybrid designs involving not only software but also specialized computers with architectures best suited to each application. Accordingly, hardware research must no longer be considered as a separate discipline by system programmers but as a tool in exactly the same way as languages. To illustrate this philosophy, a hardware laboratory has been set up at the University of Montreal. The primary interest of the founders was in designing and building small specialized computing systems.
This paper describes some of the aspects of the laboratory with emphasis on two major developments:
(1) The design of a programmable I/O switch between two mini-computers.
(2) The addition and monitoring of a writable control store connected to one system.
Evaluating the performance of four snooping cache coherency protocols
Authors: Eggers S. J. , Katz R. H. 
Published: July 2004

Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to achieve good bus performance across all cache configurations. In particular, write-invalidate performance can suffer as block size increases; and large cache sizes will hurt write-broadcast. Read-broadcast and competitive snooping extensions to the protocols have been proposed to solve each problem.
Our results indicate that the benefits of the extensions are limited. Read-broadcast reduces the number of invalidation misses, but at a high cost in processor lockout from the cache. The net effect can be an increase in total execution cycles. Competitive snooping benefits only those programs with high per-processor locality of reference to shared data. For programs characterized by inter-processor contention for shared addresses, competitive snooping can degrade performance by causing a slight increase in bus utilization and total execution time.
Multiple vs. wide shared bus multiprocessors
Authors: Hopper A. , Jones A. , Lioupis D. 
Published: July 2004

In this paper we compare the simulated performance of a family of multiprocessor architectures based on a global shared memory. The processors are connected to the memory through caches that snoop one or more shared buses in crossbar arrangement.
We have simulated a number of configurations in order to assess the relative performance of multiple versus wide bus machines, with varying amounts of prefetch. Four programs, with widely differing characteristics, were run on each configuration. The configurations that gave the best all-round results were multiple narrow buses with 4 words of prefetch.
An architecture framework for application-specific and scalable architectures
Authors: Mulder J. M. , Portier R. J. , Srivastava A. , in't Velt R. 
Published: July 2004

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture.
The SCalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the application-specific architecture;
This paper concentrates primarily on the architecture framework of SCARCE, but also presents briefly some software issues and outlines the process of generating VLSI processors.
A generalized object display processor architecture
Authors: Goldwasser Samuel M. 
Published: July 2004

A multiprocessor architecture has been developed which addresses the problem of the display and manipulation of multiple shaded three dimensional objects derived from emperical data on a raster scan CRT. Fully general control of such parameters as position, size, orientation, rotation, tone scale, and shading are accomplished at video rates permitting real-time interaction with the display presentation.
The GODPA architecture is based on a large number of relatively simple processing elements which access their own memory modules without input conflict. Reconstruction algorithms are used which do not require any complex arithmetic or logical high speed operations. This hardware organization is highly modular and expandible and is ideally suited for implementation with VLSI technology.
The design and implementation of a VLSI chess move generator
Authors: Ebeling Carl , Palay Andrew 
Published: July 2004

Communication is a basic problem when using VLSI technology to implement large parallel circuits. Valuable chip area must be used to run wires connecting components on a chip and current packaging technology restricts the amount of communication that can cross chip boundaries. This paper presents a large parallel architecture for generating moves in chess and shows how it can be restructured to reduce communication and permit a straightforward VLSI implementation without any performance loss. The result is a move generator comprising 64 identical custom chips performing at a rate of 500,000 moves per second, performance that is comparable to the best existing move generator.
The success of the architecture of a component module like a chess move generator depends not only on its performance but on how well it meshes with the rest of the system. We discuss the requirements of a chess move generator in the context of a chess-playing system and describe how each of these are met by our design. Details of the chip design are presented along with a description of how the move generator is built using identical chips.
Empirical analysis of the mesa instruction set
Authors: Sweet Richard E. , Sandman James G. 
Published: July 2004

This paper describes recent work to refine the instruction set of the Mesa processor. Mesa [8] is a high level systems implementation language developed at Xerox PARC during the middle 1970's. Typical systems written in Mesa are large collections of programs running on single-user machines. For this reason, a major design goal of the project has been to generate compact object programs.
The computers that execute Mesa programs are implementations of a stack architecture [5]. The instructions of an object program are organized into a stream of eight bit bytes. The exact complement into of instructions in the architecture has changed as the language and machine micro architecture have evolved.
In Sections 3 and 4, we give a short history of the Mesa instruction set and discuss the motivation for our most recent analysis of it. In Section 5, we discuss the tools and techniques used in this analysis. Section 6 shows the results of this analysis as applied to a large sample of approximately 2.5 million instruction bytes. Sections 7 and 8 give advice to others who might be contemplating similar analyses.
The data management machine, a classification
Authors: Rosenthal Robert S. 
Published: July 2004

There has been much interest in the use of special purpose processors as the data base management component of data processing systems. The generic terms “backend” and “data management machine” have been applied to such devices. Examination of the literature reveals a broad cross section of host to backend functional distribution and interconnection methodology. This discussion represents an attempt to examine and classify several of these backend data base management machine configurations in terms of their operational parameters and application constraints. A formal taxonomy of such systems remains yet to be performed.
At least three distinct classes of data management machine (DMM) are evidenced in the literature; they are the large host backend, distributed network data node and smart peripheral. The intended classes of problem that the various authors envision amenable to solution by the DMM approach exhibit overlap while the performance envelope in which each DMM architecture would provide a technically acceptable, economically sound solution to a given user requirement set varies. Some of the papers used as source for this work contained no explicit mention of either the problem classes or performance constraints that the described configuration was to address; thus liberty has been taken in interpreting the implicit application goals of these authors.
A Study of Event Traffic During the Shared Manipulation of Objects Within a Collaborative Virtual Environment
Authors: Wolff Robin , Roberts David J. , Otto Oliver 
Published: July 2004

Event management must balance consistency and responsiveness above the requirements of shared object interaction within a Collaborative Virtual Environment (CVE) system. An understanding of the event traffic during collaborative tasks helps in the design of all aspects of a CVE system. The application, user activity, the display interface, and the network resources, all play a part in determining the characteristics of event management. Linked cubic displays lend themselves well to supporting natural social human communication between remote users. To allow users to communicate naturally and subconsciously, continuous and detailed tracking is necessary. This, however, is hard to balance with the real-time consistency constraints of general shared object interaction. This paper aims to explain these issues through a detailed examination of event traffic produced by a typical CVE, using both immersive and desktop displays, while supporting a variety of collaborative activities. We analyze event traffic during a highly collaborative task requiring various forms of shared object manipulation, including the concurrent manipulation of a shared object. Event sources are categorized and the influence of the form of object sharing as well as the display device interface are detailed. With the presented findings the paper wishes to aid the design of future systems.
Stem cells and repair of lung injuries
Authors: Neuringer Isabel P , Randell Scott H 
Published: July 2004

AbstractFueled by the promise of regenerative medicine, currently there is unprecedented interest in stem cells. Furthermore, there have been revolutionary, but somewhat controversial, advances in our understanding of stem cell biology. Stem cells likely play key roles in the repair of diverse lung injuries. However, due to very low rates of cellular proliferation in vivo in the normal steady state, cellular and architectural complexity of the respiratory tract, and the lack of an intensive research effort, lung stem cells remain poorly understood compared to those in other major organ systems. In the present review, we concisely explore the conceptual framework of stem cell biology and recent advances pertinent to the lungs. We illustrate lung diseases in which manipulation of stem cells may be physiologically significant and highlight the challenges facing stem cell-related therapy in the lung.
Characterization of the GATC regulatory network in E. coli
Authors: Riva Alessandra , Delorme Marie-Odile , Chevalier Tony , Guilhot Nicolas , Hénaut Corinne , Hénaut Alain 
Published: July 2004

Abstract
Background
The tetranucleotide GATC is methylated in Escherichia. coli by the DNA methyltransferase (Dam) and is known to be implicated in numerous cellular processes. Mutants lacking Dam are characterized by a pleiotropic phenotype. The existence of a GATC regulated network, thought to be involved in cold and oxygen shift, had been proposed and its existence has recently been confirmed. The aim of this article is to describe the components of the GATC regulated network of E. coli in detail and propose a role of this network in the light of an evolutionary advantage for the organism.

Results
We have classified the genes of the GATC network according to the EcoCyc functional classes. Comparisons with all of E. coli's genes and the genes involved in the SOS and stress response show that the GATC network forms a group apart. The functional classes that characterize the network are the Energy metabolism (in particular respiration), Fatty acid/ Phospholipid metabolism and Nucleotide metabolism.

Conclusions
The network is thought to come into play when the cell undergoes coldshock and is likely to enter stationary phase.
The respiration is almost completely under GATC control and according to our hypothesis it will be blocked at the moment of coldshock; this might give the cell a selective advantage as it increases its chances for survival when entering stationary phase under coldshock. We predict the accumulation of formate and possibly succinate, which might increase the cell's resistance, in this case to antimicrobial agents, when entering stationary phase.