Reliable Direct Bonded Heterogeneous Integration (DBHi) for AI Hardware
Authors: Taneja Divya , Pilger Katherine , Jacques-Fortin Alexis , Godard Maxime , de Sousa Isabel , Kohara Sayuri , Marushima Chinami , Watanabe Takahito , Horibe Akihiro , Ross Joseph , Wassick Thomas 
Published: January 2025

AI applications are becoming pervasive, they require computational performance to grow at an annual rate of 2.5x or a decadal rate of 1000x. The front runners to keep up this trend are System on Chip (SoC) and system in package (SiP)/Heterogenous Integration (HI). While SoC has advantages in functional performance, it is more expensive to design, fabricate and package. As we increase the functionality, the cost increases and so is the package size. HI offers the possibility to integrate a variety of computing elements intoa smaller space, controlling package size with a relatively less expensive design and fabrication. Integrating and tiling chiplets from differnts silicon technology nodes reqiuire high bandwidth interconnects to achieve this seemlessly. . To address this need, several solutions have emerged in the past years such as silicon interposer [1], high-density laminate [2], silicon bridge [3-4] chip-stacked packages and Fan-out packaging. Out of these options, Si bridge offers one of the fastest lateral communications between chips. In the test configuration proposed, Si bridge connects two chips, and these two chips are connected to the laminate as shown in Fig 1. There are different approaches to make this architecture. The first approach has a laminate with an embedded chip and 2 principal chips are bonded over the laminate (and bridge) at the same time. In another approach which is called DBHI, first a subassembly is made by bonding all the 3 chips (a Si bridge with 2 principal Si chips) and subsequently bonding this chip assembly to a laminate. In the latter approach the laminate comprises a cavity where the Si bridge will be loged at chip assembly whereas in the former approach a special laminate with embedded Si bridge is required. In last few years we have presented our work on DBHI with a thick bridge in cavity. In this current work we present simpler DBHI architecture which doesn’t need a cavity in the laminate. In this novel configuration which is presented in Fig 2 , a thinner Si bridge chip (60 µm thick) is used as opposed to thicker bridge (200 µm), while the principal chips are fitted with higher Copper pillar instead of solder C4’s. The Copper pillars create a standoff between principal chips and laminate. This clears sufficient height for the bridge chip to the surface of the laminate after the chip joining operation. DBHI now offers the possibility of assembling Si bridge to principal chips at very fine pitch interconnects (30-75 µm) with the help of uC4s on regular laminate configurations. To validate process yield, JEDEC standard thermal cycling Deep thermal cycling DTC (-40C to +125C) and ATC (0C to 100C) are performed. All stress cells saw JEDEC preconditioning before starting the actual stress. The results indicate that the novel DBHI configuration comfortably passes JEDEC criteria. Extended thermal cycling up to 2000 DTC is also performed to properly assess the thermomechanical properties of these laminates. Physical analysis for the post-reliability test samples for the uC4s and C4s are also discussed in this study. In this work, we present the effects and the advantages that came with thinning down the Si bridge and the removal of cavity for the bonding and their influence on the overall thermo-mechanical performance of the package. This configuration provides flexibility for signal routing in the laminate below the bridge and eliminates any additional processing of the laminate. DBHI is therefore further enhanced and well positioned to provide high-bandwidth and low-power communication required for AI workloads. References 1. J. Knickerbocker, et.al., “Development of Next-Generation System-on-Package (SOP) Technology based on Silicon Carriers with Fine-pitch Chip Interconnection,” IBM Journal of Research and Development, 2005, Vol. 49, pp. 725 – 753 2. S. Miki, H. Taneda, N. Kobayashi, K. Oi, K. Nagai, and T. Koyama “Development of 2.3D High Density Organic Package using Low Temperature Bonding Process with Sn-Bi Solder,” Proceedings, IEEE Electronic Components and Technology Conference, pp. 1599-1605, 2019. 3. R. Mahajan et al., “Embedded Multi-Die Interconnect Bridge (EMIB) – A High Density, High Bandwidth Packaging Interconnect,” IEEE Electronic Components and Technology Conference, pp. 557-565, 2016. 4. K. Sikka et al., “Direct Bonded Heterogeneous Integration (DBHi) Si Bridge,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), pp. 136-144, 2021.”