bluuebunny/crossref_metadata_2025_split huggingface dataset:
A run time support system for multiprocessor machines
Authors: Tsoukarellas M. A. , Papatheodorou T. S. 
Published: July 2004

We report on the design and development of a Run Time Support System (RTS) which overcomes known disadvantages of other existing systems. The RTS is independent of the configuration - if the system is reconfigured there is no need to change user's processes. It supports both synchronous and asynchronous communication.
A system based on the same design philosophy with this RTS is actually implemented for messages of arbitrary length in the prototype of the PADMAVATI machine, being developed within ESPRIT Project 1219 (967). Experiments were conducted in this environment and performance measurements were obtained and are reported here.
Multiple-banked register file architectures
Authors: Cruz José-Lorenzo , González Antonio , Valero Mateo , Topham Nigel P. 
Published: July 2004

The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor generations, as they are expected to increase the issue width (which implies more register ports) and the size of the instruction window (which implies more registers), and to use some kind of multithreading. Under this scenario, the register file access time could be a dominant delay and a pipelined implementation would be desirable to allow for high clock rates.
However, a multi-stage register file has severe implications for processor performance (e.g. higher branch misprediction penalty) and complexity (more levels of bypass logic). To tackle these two problems, in this paper we propose a register file architecture composed of multiple banks. In particular we focus on a multi-level organization of the register file, which provides low latency and simple bypass logic. We propose several caching policies and prefetching strategies and demonstrate the potential of this multiple-banked organization. For instance, we show that a two-level organization degrades IPC by 10% and 2% with respect to a non-pipelined single-banked register file, for SpecInt95 and SpecFP95 respectively, but it increases performance by 87% and 92% when the register file access time is factored in.
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
Authors: Cintra Marcelo , Martínez José F. , Torrellas Josep 
Published: July 2004

Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on single-chip multiprocessors (CMPs), whose effectiveness is necessarily limited by their small size. Very few schemes have attempted this technique in the context of scalable shared-memory systems.
In this paper, we present and evaluate a new hardware scheme for scalable speculative parallelization. This design needs relatively simple hardware and is efficiently integrated into a cache-coherent NUMA system. We have designed the scheme in a hierarchical manner that largely abstracts away the internals of the node. We effectively utilize a speculative CMP as the building block for our scheme.
Simulations show that the architecture proposed delivers good speedups at a modest hardware cost. For a set of important non-analyzable scientific loops, we report average speedups of 4.2 for 16 processors. We show that support for per-word speculative state is required by our applications, or else the performance suffers greatly.
Focusing processor policies via critical-path prediction
Authors: Fields Brian , Rubin Shai , Bodík Rastislav 
Published: July 2004

Although some instructions hurt performance more than others, current processors typically apply scheduling and speculation as if each instruction was equally costly. Instruction cost can be naturally expressed through the
critical path
: if we could predict it at run-time, egalitarian policies could be replaced with cost-sensitive strategies that will grow increasingly effective as processors become more parallel.

This paper introduces a hardware predictor of instruction criticality and uses it to improve performance. The predictor is both effective and simple in its hardware implementation. The effectiveness at improving performance stems from using a dependence-graph model of the microarchitectural critical path that identifies execution bottlenecks by incorporating both data and machine-specific dependences. The simplicity stems from a token-passing algorithm that computes the critical path without actually building the dependence graph.
By focusing processor policies on critical instructions, our predictor enables a large class of optimizations. It can (i) give priority to critical instructions for scarce resources (functional units, ports, predictor entries); and (ii) suppress speculation on non-critical instructions, thus reducing “useless” misspeculations. We present two case studies that illustrate the potential of the two types of optimization, we show that (i) critical-path-based dynamic instruction scheduling and steering in a clustered architecture improves performance by as much as 21% (10% on average); and (ii) focusing value prediction only on critical instructions improves performance by as much as 5%, due to removing nearly half of the misspeculations.
A multi-microprocessor implementation of a general purpose pipelined CPU
Authors: Ramseyer Richard R. , Dam Andries van 
Published: July 2004

This paper discusses and shows by example the potential of a network of microprogrammable microprocessors as a cost-effective alternative to traditional hardwired medium- and large-scale mainframes. While biased towards vector processing, this system is not intended to compete with multi-million dollar supercomputers such as the 360/195, CDC STAR, Illiac IV, CRAY-1, TI ASC, etc., which use special algorithms and the fastest circuitry available.
The architecture incorporates pipelining, multiprocessing and distributed processing techniques with bipolar microprocessor technology. The result should be a machine which will equal or outperform most traditional third- and fourth-generation mainframes at a fraction of the CPU cost. This should be the case even for scalar, general purpose computation.
Poly-Processor System analysis and design
Authors: Hurakami K. , Nishikawa S. , Sato M. 
Published: July 2004

This paper discusses the structure and efficiency of a computer complex constructed of many small, tightly coupled, functionally dedicated processors called a Poly-Processor System (PPS). The objective of the PPS is to realize a computer system which has easier expandability, higher reliability and better cost-to-performance ratio than existing systems.
Firstly, presented are rules to assign functions among processors, memories and interconnection modules. Secondly, dynamic behavior of the system, such as the frequency of interprocesser communication and instruction occurance, is analyzed by computer simulation. Lastly, a pilot model (PPS for Research: PPS-R), developed to confirm the feasibility of the system and to acquire experience in establishing the architecture of the system, is described.
The effect of instruction fetch strategies upon the performance of pipelined instruction units
Authors: Rau Ramakrishna B. , Rossmann George E. 
Published: July 2004

The interpretation of a machine instruction requires fetching the instruction, decoding the instruction, and then executing it. In addition, if the instruction requires one or more operands, their addresses must be generated and the operands fetched. A large number of processors have been designed to perform some or all of these functions simultaneously on successive instructions.
These pipelined processor architectures would appear to permit the decoding of a new instruction each machine cycle.
The IEEE Computer Society task force on computer architecture
Authors: Rossmann George E. 
Published: July 2004

The subject of computer architecture as currently taught in most computer engineering and computer science programs is a mixture of architectural principles, organizational strategies, and implementation techniques. This blurring of the hierarchy of system levels that characterize the structure of a computer has made it very difficult for students (and often instructors as well) to determine what were the forces that led to the design decisions they have seen reflected in machines.
In view of these circumstances, a task force was established by the IEEE Computer Society to prepare a detailed specification for a course of study in computer architecture for students whose major interest is in computer engineering or computer science.
A computer simulation facility for packet communication architecture
Authors: Leung Clement K.C. , Misunas David P. , Neczwid Andrij , Dennis Jack B. 
Published: July 2004

Several proposals for computer data processing and memory systems that exploit the inherent parallelism in programs expressed in data flow form have been advanced recently. These systems have
packet communication architecture
—each system consists of many
units
that interact only through the transmission of information packets through
channels
that link pairs of units.

A simulation facility for evaluating the programmability and potential performance of these proposed data processing and memory systems has been designed. The facility uses microprocessor modules to emulate the behavior of system units or groups of units. By conducting a simulation in accurate scale time a precise extrapolation of performance of a proposed system may be obtained.
The user of the facility will specify the system to be simulated in an architecture description language. A host computer translates the system description modules into microprocessor programs and controls the loading and monitors the operation of the microprocessors. Application of the facility is illustrated by consideration of a simple data flow processor.
An input interface for a real-time digital sound generation system
Authors: Dworak Paul E. , Parker Alice C. 
Published: July 2004

A man/computer input interface is described in this paper. This interface allows human control of the frequency, amplitude, spectral content and envelope of real-time sound production.
The interface consists of a two-dimensional array of keys for entering data, latches and comparators to signal changes in key depression, hardware for scanning the keyboard and address generation logic. Both the fundamental frequency represented by each key column and the harmonics of each frequency—represented by each element in the column—are programmable. Amplitude and envelope are software controlled.
Applications of the interface instrument range From music composition to clinical use in auditory testing. The interface is part of an electronic sound generation system presently being designed and constructed.
Multiprogramming for real-time applications
Authors: Gladney H. M. , Hochweller G. 
Published: July 2004

A software system supporting multiple event-driven processes concurrently on a small process control computer is described. Each application can be programmed and tested independently. An implementation of the system, called LABS/7, has been productive for over three years.
The limits to which real-time multiprogramming may be pushed are explored.
SMS 101 - A structuredmultimicroprocessor system with deadlock-free operation scheme
Authors: Kuznia Ch. , Kober R. , Kopp H. 
Published: July 2004

The presented multimicroprocessor system has been designed to treat certain problem classes such as large systems of differential equations or online process control. It consists of a main processor and an arbitrary number of modules, each with a microprocessor, a private memory and a communication memory. The most characteristic features of the SMS 101 organization are:
- a phase structured interaction scheme (PSI-Scheme) which simplifies organizational problems
- a data communication concept, that replaces common memory by simultaneously storing data in distributed memories.
A first realization of the system comprises eight modules, but the organization allows an extension up to several hundreds of modules. Thus with present day technology a computing capacity can be achieved which is 2 or 3 magnitudes higher than that of conventional computers.
Distribution of functions and control in RPCNET
Authors: Franchi Paolo 
Published: July 2004

This paper describes the general characteristics and architecture of RPCNET, a distributed computer network for use in the Education and Research area which is being developed in Italy. This project is a joint undertaking of the National Research Council, IBM Scientific Center and a number of Universities and Research Institutes.
In order to match the variety of needs and contraints inherent in the environment in which the network must be developed and made operational, a functional rather than a system approach has been followed in the designing of the Network. The present architecture includes some modifications to the original design which were necessary in order to establish a more definite boundary between applications, interface and communication subnetwork.
The mapping of these functions into physical components is also presented as well as some types of applications.
Price/performance comparison of C.mmp and the PDP-10
Authors: Fuller Samuel H. 
Published: July 2004

The analysis in this paper shows a multiprocessor like C.mmp to have a factor of three to four cost/performance advantage over uniprocessor systems such as the PDP-10 when implementations using similar technologies are considered. This comparison is shown to be very sensitive to memory prices and considerable attention is given to normalizing memory costs between C.mmp and the PDP-10.
An important part of this analysis is a comparison of the PDP-10 architecture with the PDP-11 architecture (i.e. the architecture of the processors of C.mmp). When the limited address space of the PDP-11 is not a problem, we see that to a close approximation it takes the same number of PDP-11 instructions (average length 25 bits) as PDP-10 instructions (length 36 bits) to represent a program.
While the comparison in this paper explicitly considers multiprocessor degradation factors such as memory interference, it does not address the problem of writing software systems capable of taking full advantage of the multiprocessor structures. The comparisons in this paper are primarily ofcused on comparing the hardware structures of uniprocessors and multiprocessors. Work is now in progress at CMU that is attempting to evaluate the effectiveness of both individual multiprocessor structures application programs and multiprogrammed systems operating on C.mmp.
Trade-offs between devices and paths in achieving disk interleaving
Authors: Ng S. , Lang D. , Selinger R. 
Published: July 2004

There is a continuing need to improve the performance of disk subsystems, and one of the key factors of a disk subsystem's performance is the data transfer rate. While it is clear that increasing the data transfer rate would reduce the service time for those applications that move large amounts of data per I/O, the amount of data transferred per I/O in many of today's typical commercial applications is relatively small. The benefit of a higher data rate in these environments was not well understood, but is explored here and is found to be larger than expected.
One way to increase the data rate of the disk subsystem is through a technique generally known as striping. Using this approach, multiple conventional disks are grouped together and function as if they were a single one, with the data spread among the multiple disks and transferred in parallel. In this paper, we study four alternative implementations for achieving higher data rates in a disk subsystem, focusing on the trade-offs between the number of devices and the number of data paths, keeping the number of physical devices constant (which may keep the cost roughly constant). The performance advantages and limitations of the alternative implementations are analyzed using an analytic queuing model and compared to a conventional disk subsystem.
A characterization of sharing in parallel programs and its application to coherency protocol evaluation
Authors: Eggers S. J. , Katz R. H. 
Published: July 2004

In this paper we use trace-driven simulation to analyze the memory reference patterns of write shared data in several parallel applications. We first develop a characterization of write sharing (based on the notion of a write run), and then examine the traces, using metrics derived from the characterization. The results indicate that the amount of write sharing in all programs is small; and that it is characterized by short to medium sequences of per processor references, with little contention for either data or locks.
We determine to what extent this analysis can be used to predict the coherency overhead of write-invalidate and write-broadcast protocols. We develop a simple model of write sharing from the write run characterization. By applying the results of the sharing analysis to the model, weighted by machine-specific cycle costs for carrying out coherency-related bus operations, we can estimate relative protocol performance. We compare these results to those from detailed architectural simulations.
The simulation results indicate that (1) neither protocol dominates in performance; and that (2) the write run model is a good predictor of protocol performance when the unit of the coherency operations matches that in the sharing analysis. This is the case for the write-broadcast protocols, in which one word is broadcast for each write to shared data. However, in Berkeley Ownership, a write-invalidate protocol, the unit of coherency is an entire cache block. When the block size is large, performance for this protocol is quite sensitive to the memory reference patterns within the block.
The Wisconsin multicube: a new large-scale cache-coherent multiprocessor
Authors: Goodman J. R. , Woest P. J. 
Published: July 2004

The
Wisconsin Multicube
, is a large-scale, shared-memory multiprocessor architecture that employs a snooping cache protocol over a grid of buses. Each processor has a conventional (SRAM) cache optimized to minimize memory latency and a large (DRAM) snooping cache optimized to reduce bus traffic and to maintain consistency. The large snooping cache should guarantee that nearly all the traffic on the buses will be generated by I/O and accesses to shared data.

The programmer's view of the system is like a multi -- a set of processors having access to a common shared memory with no notion of geographical locality. Thus writing software, including the operating system, should be a straightforward extension of those techniques being developed for multis.
The interconnection topology allows for a cache-coherent protocol for which most bus requests can be satisfied with no more than twice the number of bus operations required of a single-bus multi. The total symmetry guarantees that there are no topology-induced bottlenecks. The total bus bandwidth grows in proportion to the product of the number of processors and the average path length.

The proposed architecture is an example of a new class of interconnection topologies -- the
Multicube
-- which consists of

N =n
k

processors, where each processor is connected to
k
buses and each bus is connected to
n
processors. The hypercube is a special case where
n
=2. The Wisconsin Multicube is a two-dimensional Multicube (
k
=2), where
n
scales to about 32, resulting in a proposed system of over 1,000 processors.
VDL—a Definition system for all levels
Authors: Lee John A. N. 
Published: July 2004

The VDL system for the description of programming languages which was originally used for the definition of PL/I is extended to the description of processors. This paper shows the relationship between the language of definition and the abstract machine over which the semantics of the language are specified. It is demonstrated that the level of description can be chosen to suit the various needs of the computing community, each level being well nested within its outer level, whilst using only one language of definition.
From the point of view of processor design, indications are given of the means by which a description can be transformed into an implementable system of data paths, registers and drivers.
The architecture of CASSM
Authors: Copeland George P. , Lipovski G. J. , Su Stanley Y.W. 
Published: July 2004

This paper presents the architecture of a context-addressed cellular system for non-numeric information processing, using an inexpensive, large-capacity circulating memory device. The system allows data to be represented in a structure very close to the form as the user perceives it (information structure) and allows the search operations of high level queries to be implemented directly. The information structures currently used in existing information systems are described. Then the architecture of the system as a whole is presented, as well as the implementation of these information structures as basic data types and hardware management of storage allocation and garbage collection.
The paper intends to demonstrate that distributing intelligence throughout a rotating memory device can decrease the time required for search operations in large data bases. And that the search strategy and storage management functions can be efficiently carried out in hardware, greatly simplifying the software of information systems. Thus, data not only becomes faster but easier to access, verify, insert and delete.
A fault tolerant multiprocessor architecture for real-time control applications
Authors: Fischler M. A. , Firschein O. 
Published: July 2004

This paper presents a fault tolerant multiprocessor architecture suitable for real time control applications requiring an extremely high degree of reliability. The architecture satisfies the following requirements:
l) Ability to deal with software as well as hardware faults: The proposed architecture is based on the assignment of distinct but redundant software modules to each task.
2) Efficient use of resources: The proposed architecture is a multiprocessor using time redundancy for fault correction. Thus, redundancy (beyond that needed for fault detection) is invoked only when a fault is detected. In normal operation, this extra capacity is available as an additional computing resource.
3) No hard core: In addition to the usual replication of system components, a partitioned system executive and a unique communication facility is defined which insures that the available redundancy will not be lost through a “domino” effect.
4) Interaction of computing units with sensors and effectors: The manner in which system architecture must be responsive to the amount and type of redundancy provided by the sensors and effectors is shown.
5) Use of current technology: The proposed architecture is based on the use of currently available hardware for the major system components.
After a detailed description of the architecture and the method of system operation, the system is related to existing fault tolerant systems, and unique characteristics of the present design are indicated.