(Invited) On the Advantage of Deploying ALD-Deposited Gate Oxides for 4H-Silicon Carbide MOS Applications
Authors: Renz Arne Benjamin Benjamin , Vavasour Oliver James , Cao Qinze , Shah Vishal , Antoniou Marina , Gammon Peter Michael 
Published: February 2024

The wide bandgap semiconductor material 4H-silicon carbide (SiC) has revolutionized the power electronics device market since the commercialization of the first SiC metal-oxide-semiconductor field-effect transistor (MOSFET) in 2012. In the blocking voltage range between 650V-1,700 V, SiC MOSFETs offer a higher maximum switching frequency, lower total space consumption as well as a higher temperature operation range than their silicon (Si) counterparts, e.g., the Si insulated-gate bipolar transistors (IGBT). This has led to the rapid uptake in deployment of SiC MOSFETs in main drivetrain inverter topologies in battery electric vehicles (BEVs).
Given the importance the availability of oxides play in the role of any MOS-structure, the successful implementation of SiC MOSFETs into power electronics conversion stages has in no small part been due to its native oxide, silicon dioxide (SiO2). This can easily be thermally grown at temperatures between 1,100°C-1,400°C. This advantage as well as the relatively large conduction band offset of approx. 2.7 eV between SiC and SiO2 make SiO2 the ubiquitous gate oxide in any SiC device.
However, interface defect densities are still much more prevalent in SiC/SiO2 systems than in their Si/SiO2 MOS counterparts, and most of these defects originate from the thermal oxidation process, which ends up forming carbon-rich interfaces containing carbon clusters, hydrogen (H) and oxygen (O) vacancies. These defects enhance scattering, increase leakage currents and hence reduce channel mobilities in MOSFETs. This is a major technological issue, leading to specific on-resistances (RON,SP) that are much higher than the theoretical unipolar limit of SiC would allow, hampering the further uptake of SiC MOS technology.
In this investigation, we explore the three most used deposition/growth mechanisms that will form an SiO2 layer on SiC and the impact this mechanism will have on the interface quality and high-temperature reliability of MOS-based SiC devices.
Lateral MOSFETs (LMOSFETs), metal-oxide-semiconductor capacitors (MOSCAPs) and all other mentioned device structures were fabricated on 10 μm thick, nitrogen-doped (4 x 1015 cm-3) epitaxial layers that were grown on highly nitrogen-doped SiC substrates. LMOSFET devices underwent a conventional implantation schedule for the p-base and n+-source and drain implant, both carried out at 500°C, with the post-implantation anneal carried out at 1,750°C for 45 minutes in Ar (5 slm).
Once samples had undergone an initial solvent clean/RCA 1/HF (10%)/ RCA 2/HF (10%) clean procedure, a 1 μm thick field oxide was deposited on the samples through low-pressure chemical vapour deposition (LPCVD). A gate oxide window was opened by means of photolithography, after which the oxide was thinned down to a thickness of approximately 30 nm by means of reactive ion etching (RIE). The final oxide was removed using a wet etch in diluted 10% buffered oxide etch to prevent surface exposure to heavily accelerated and charged particles. The gate oxides were then put down using one of the following oxidation routines:

ALD deposition of SiO2 using bis(diethylamino)silane (BDEAS) and an oxygen plasma at 200°C (750 cycles) or

ALD deposition of SiO2 using bis(diethylamino)silane (BDEAS) and an oxygen plasma at 200°C (750 cycles) plus a PDA in FG ambient (5 slm, 5 % H2) at 1,100°C for 1 h.

LPCVD using tetraethyl orthosilicate (TEOS) as a precursor.

Direct thermal growth at 1300°C for 5 hrs in diluted N2O (4 slm Ar: 1 slm N2O) ambient.

Since samples that had undergone routines 1 and 3 usually show a poor as-deposited oxide quality, a post-deposition anneal was performed on these samples in an oxidation furnace in N2O ambient at 1,300°C for 2 hrs. All N2O treated samples (1,3 and 4) showed an oxide thickness of approximately 60 nm, with the FG-treated sample showing a lower thickness of approx. 35 nm. Conventional metal contact formation was then carried out to finalise the devices.
In this investigation, we investigate the current-voltage (I-V), capacitance-voltage (C-V) and constant-voltage time dependent dielectric breakdown (TDDB) performance. We will present evidence that high-quality, highly reliable SiO2 layers, formed by ALD and PDA, can be created. Flatband voltage and hysteresis values will be reduced, compared to thermally grown oxides, and frequency dispersion in accumulation is negligible. The ALD oxide with forming gas PDA has the best performance across the entire dataset at all measured voltages (9.6 MV/cm, 9.3 MV/cm, 9 MV/cm, 8.5 MV/cm, 8 MV/cm). This is due to a different interface chemistry, shown by XPS, HRTEM and SIMS, where Si complexes, such as Si dimers or SixOy groups are broken down into simple Si dangling bonds, which can be readily passivated with a FG anneal. This will be discussed in detail in this talk.

Figure 1