bluuebunny/crossref_metadata_2025_split huggingface dataset:
Loop admittance matrix modification for the digital simulation of power converter circuits
Authors: Zacharias Th. , Milias‐Argitis J. , Makios V. 
Published: July 2007

AbstractThe analysis of the equivalent circuit of power converters presents unique difficulties due to the continuously changing conduction state of power semiconductor switches which introduce open‐ and short‐circuit branches. Presently available methods mainly aim at automatically assembling the loop impedance matrix describing any particular conduction pattern. In this paper a novel powerful method is developed for automatically treating this varying topology circuit analysis problem by direct modification of the corresponding loop admittance matrix. In this way the inversion of any matrix is avoided. In particular, the loop admittance matrix (the solution matrix) for an existing conducting state of the switching elements is constructed by modifying the associated matrix corresponding to the previous conduction pattern. These modifications include a change of reference frame and/or elimination and/or addition of one or more loops on a solution matrix level and are expressed in an algorithmic form suitable for digital computer simulation.
A tight clock synchronization technique for multiprocessor systems
Authors: Liu Jyh‐Charn , Hung Tzu‐Chien 
Published: July 2007

AbstractIn this paper we present a tight clock synchronization scheme for large‐scale multiprocessor systems. the proposed scheme consists of two symmetric loops for transmission of the master clock signals and askew cancellation circuit(SCC) for each node to be synchronized to the master clock. Each clocking signal generated by the master clock source is replicated into two identical copies and the twin signals are transmitted on two symmetric loops in opposite directions. to cancel the time skew between them caused by the transmission network, the time difference between the two clocks' arrival times at any node is first measured and stored in each node. Then each of the leading signals received from the loop in a node is issued to its functional units after the signal is delayed by half the measured phase difference. It is shown that the system clock skew can be made independent of the delay of the transmission lines by the proposed scheme at a low hardware cost.To explore the feasibility of the proposed scheme, the SCC is designed with a combination of programmable delay element arrays and a phase detector. the floor‐plan of the SCC is implemented by the MAGIC VLSI lay‐out tool based on MOSIS CMOS 2 μm technology and extensively simulated.
System identification using discrete orthogonal functions
Authors: Fahmy M. F. , Haweei T. I. , Elraheem G. J. M. , Gharieb R. R. 
Published: July 2007

AbstractIn this paper a novel method is described for the design of adaptive IIR filters used in system identification. the adaptive filter is implemented as a parallel connection of subsections whose transfer functions constitute a set of discrete orthogonal systems. the adaptation algorithm used, which is of the Gauss‐Newton type, adjusts the parameters of these discrete orthogonal systems in order to match the desired output data of the unknown plant in a least squares sense. Owing to the orthogonality property, which ensures complete independence of subsequent sections, convergence is very rapid. Closed‐form expressions for the gradient signals required to update the filter are given. Illustrative examples have shown that this method always results in much improved adaptation properties compared with the already existing approaches.
A new feasible method for the design of stray‐insensitive optimum switched capacitor networks
Authors: Nacaroǧlu A. , Köksal M. 
Published: July 2007

AbstractOn the basis of signal flow graphs a general method is described for the design of stray‐insensitive switched capacitor networks. to be able to choose the optimum one, the method involves the search of all possible topologies for the specially formed signal flow graph of the given z‐domain transfer function and is easily implemented by digital computer.
Analysis of noise in cascaded non‐linear stages
Authors: Larsen Torben 
Published: July 2007

AbstractThis paper presents a method to analyse noise in cascaded non‐linear stages based on Volterra series for multiport systems. the cascaded stages are partitioned such that internal noise sources from different stages are uncorrelated and linear loading between all stages can be assumed. This partitioning scheme implies that the ensemble average of the magnitude‐squared output response from the last stage in the cascade can be determined as a sum of noise contributions from the individual stages. the method allows both unmodulated (independent) and modulated (dependent) noise sources. A special case of the theory and two related examples are presented to illustrate the method.
New CMOS current mirrors with improved high‐frequency response
Authors: Di Cataldo G. , Palumbo G. , Stivala S. 
Published: July 2007

AbstractA new CMOS current mirror is presented which has the static characteristic of the cascode current mirror and a high‐frequency performance equivalent to or better than that of the simple current mirror. Moreover, the circuit proposed does not present the instability problem of the improved cascode utilized to increase the high‐frequency response.The circuit is designed using CMOS 2 μm technology with various aspect ratios and simulated with the SPICE programme.
Design of fixed point state space digital filters with low round‐off noise
Authors: Fahmy M. F. , Yassin Y. M. , Raheem G. A. , Haweel T. I. 
Published: July 2007

AbstractA simple method is described for the design of fixed‐point recursive digital filters with low round‐off noise. the method is based on reducing to zero as many as possible of the coefficients of the filter state matrices. an optimization procedure is used to get the optimum value of linear transformation that minimizes the total output round‐off noise power. Compared with the existing approaches, this method is characterized by its computational simplicity, very low output round‐off noise (if not the lowest possible) and low coefficient sensitivity. the structure of the proposed technique is modular, which makes it suitable for VLSI implementation. the technique is then employed to obtain a reduced‐order low‐round‐off‐noise filter with characteristics equivalent to some desired FIR specifications. Illustrative examples are given to verify these advantages.
Some dynamic phenomena in delayed cellular neural networks
Authors: Civalleri Pier Paolo , Gilli Marco 
Published: July 2007

AbstractIn this paper we study the dynamic behaviour of delayed cellular neural networks (DCNNs). By means of a rigorous eigenvalue and eigenvector analysis and by numerical simulations we show that simple DCNNs composed of only two cells can exhibit a large variety of dynamic phenomena: stable and unstable closed orbits and chaotic attractors.
The describing function perturbation method for the dominant behaviour analysis of adiabatic negative‐conductance oscillators
Authors: Sommariva Antonino M. 
Published: July 2007

AbstractNegative‐conductance oscillators are termed adiabatic when their transient operation signal can be represented as a narrowband‐modulated Fourier series with a finite number only of dominant components, including the DC one. the method presented here allows one to perform the complete analysis of such oscillators in a rigorous shortened manner. Indeed, it merges the approach of the describing function technique into the classical frame of perturbation theory, so as to replace the oscillator model in the instantaneous variables with a simplified one in the dominant variables, i.e. the complex envelopes of the dominant components. More precisely, the starting model comprises the input impedance and the open‐circuit voltage of the Thévenin equivalent one‐port of the linear network in the complex frequency domain and the voltage/current characteristic of the non‐linear resistor in the time domain. the final model instead comprises as many such triads as there are dominant components. Each triad is made up of an input impedance and an open‐circuit voltage in the baseband complex frequency domain and a voltage/current describing characteristic in the slow time domain. Standard circuit analysis tools are then used to obtain the equations of the dominant dynamics, steady state and dynamical stability of the oscillator.To facilitate reading the paper, as soon as a new formula is proposed or derived, the result of its application to the well‐known van der Pol oscillator is also provided. In the end, to highlight the simplicity and efficiency of the method, a much more complex case (an eighth‐order oscillator with three dominant components) is analysed in detail.
An optimized synthesis of a discrete‐time cellular neural network for parallel thinning
Authors: Ho Chun‐Ying , Mori Shinsaku 
Published: July 2007

AbstractThe paper describes a systematic synthesizing method to realize the parallel binary image‐thinning algorithm by a discrete‐time cellular neural network. In contrast with previous studies, this paper starts from very basic local rules (algorithm) and the required cloning templates are calculated step‐by‐step. Mathematical techniques of combiningcompatibletemplates are proposed and optimization of the total number of cloning templates, the operating speed and sensitivity is addressed. Finally, the speed and circuit performances are compared with other studies.
Time domain sensitivity of high‐speed VLSI interconnects
Authors: Liu Nelson , Nakhla Michel , Zhang Qi‐Jun 
Published: July 2007

AbstractAn adjoint method based on the asymptotic wave‐form evaluation (AWE) technique is described for the time domain sensitivity analysis of VLSI interconnect networks that contain linear lumped anddistributedelements. the network sensitivity, which is approximated by a set of poles and residues sensitivities, can be evaluated efficiently with respect to all network components and interconnect parameters. Owing to therecursiverelationship between the time moments of distributed networks, the conventional adjoint approach could not be applied directly. Instead, an alternative approach is presented which solves this problem by introducting the concept ofadjoint momentsfor networks with distributed elements. Examples and comparisons with the sensitivity determined by perturbation are presented. the proposed technique is useful for the identification of critical circuit elements and the performance optimization of high‐speed VLSI designs.
A fourth‐order switched capacitor cascade structure for sigma‐delta converters
Authors: Baher Hussein , Afifi Emad 
Published: July 2007

AbstractThis paper gives details of the design of a switched capacitor circuit for use in oversampling sigma‐delta analogue‐to‐digital converters. the circuit is a fourth‐order cascade of two second‐order sections. Comparison with other multistage structures is also presented. It is shown that the proposed design has advantages over the possible alternative cascade of four first‐order sections. It is also shown that it gives certain improvements in performance over the popular third‐order cascade of a second‐order and a first‐order section, thus justifying the use of a higher order under the given technology and tolerance constraints.
Hybrid notch filters
Authors: Rhodes J. D. 
Published: July 2007

AbstractNarrow bandwidth bandstop filters or ‘notch filters’ are frequently required in both communication and electronic warfare systems. In the latter case the ability to switch into an ‘allpass’ state with a minimum level of loss and time delay distortion is vital. Furthermore, in both cases a level of 20‐30 dB rejection is normally required. These factors suggest that the ‘hybrid notch filter’† proposed in this paper is an optimum solution for low‐loss designs. Design techniques and experimental results for two fixed tuned filters for cellular base station applications are presented.
Analysis of non‐linear dynamical circuits and systems under the influence of thermal noise
Authors: Finger L. , Uhlmann H. 
Published: July 2007

AbstractIn some electronic systems, such as cryoelectronic circuits, random noise has to be taken into consideration for modelling and simulation. After theoretical considerations an algorithm for the simulation of non‐linear circuits with random noise is developed. Methods for global analysis of non‐linear dynamical systems, such as Lyapunov exponents and the Poincaré map, are applied to systems with noise. the developed algorithms are applied to the cryoelectronic circuit of the ideal DC‐SQUID model. Several non‐linear effects which occur through noise are explained.
Exact solutions of cyclically symmetric oscillator equations with non‐linear coupling. Part II: Coupling with phase shift
Authors: Fox David 
Published: July 2007

AbstractSeveral authors have found very simple exact limit cycle solutions in cyclically symmetric systems of N oscillator equations with linear coupling in zero order of a perturbation parameter and non‐linear coupling in first order. In contrast with such solutions in most other non‐linear systems, each of these limit cycles is an exact normal mode of the unperturbed equations with no change in frequency or addition of higher harmonics.In Part I of this paper it was shown that the construction and analysis of such systems of equations are substantially simplified if the equations are expressed in terms of the normal mode co‐ordinates of the unperturbed system. the effects of the cyclic symmetry, as well as those of a higher symmetry shared by previous authors' models, were studied.It is shown here that similar results can be obtained in systems if the coupling involves a phase shift. the phase shift places added conditions on the systems, so that some sets of equations, shown to have the simple limit cycle solutions, no longer have them after shift is introduced. the methods of the earlier paper, however, can be used to find families of systems with phase shifts which have such solutions.A result in Part I, that frequencies in a system with the higher symmetry mentioned above are unchanged from those of the unperturbed system, is not valid if phase shifts are introduced.
A family of modular fully differential witched capacitor filters for simulating ladder filters
Authors: Said A. E. , Hosny E. A. , Sobhy M. I. 
Published: July 2007

AbstractThe switched capacitor filters proposed in this paper are based on the simulation of LC ladder filters through the state variable equations. They include all‐pole and finite transmission zero, lowpass filters, bandpass and highpass filters. the introduced family of filters has a fully differential structure; consequently it has the advantages of improved power supply and common mode rejection ratios and extended dynamic range. Since the proposed family of filters simulates LC ladder filters, it inherits their low passband sensitivities. One of the main advantages of this family of filters is that it has a modular structure composed of key and auxiliary circuits. This modular structure results in easier design and implementation procedures in VLSI fabrication. the double‐sampling concept is applied to the introduced modular blocks, which is essentially needed in high‐frequency applications. A comparison with similar published work available in the literature is presented and illustrative examples are given.
On the restrictions of the sensitivities in single‐amplifier biquadratic active filters
Authors: Leenaerts Domine M. W. , Mladenov Valeri M. 
Published: July 2007

AbstractThe paper deals with the bounds on the sensitivities of the poles and the quality factor to the gain of the amplifier in biquadratic second‐order active filters. to ensure stability, the Fialkow‐Gerst conditions are taken into account. It is not possible to realize biquad filters with a better gain‐sensitivity product not obeying the derived conditions. the result can be applied in filter synthesis and will give the designer more freedom to dimension the filter structure and its component values.
A simulation tool for the analysis and verification of the steady state of circuit designs
Authors: Brachtendorf H. G. , Welsch G. , Laur R. 
Published: July 2007

AbstractAnalogue and microwave design requires accurate and reliable simulation tools and methods to meet the design specifications. System properties are often measured in the steady state. Well‐suited algorithms for calculating the steady state can be classified into shooting methods, finite difference methods and the harmonic balance (HB) technique. Harmonic balance is a frequency domain method which approaches the problem of finding the steady state by a trigonometric polynomial. Depending on the size of the circuit and the number of Fourier coefficients of the polynomial, the resulting system of non‐linear equations can become very large. These non‐linear equations are solved by using Newton's method.The sparse linear system arising from Newton's method can be solved by direct, stationary or non‐stationary iterative solvers. Iterative methods are normally easy to parallelize or vectorize.In this paper a tool for the simulation of the steady state of electronic circuits is presented. the steady state is calculated using the harmonic balance technique. Non‐linear equations are solved by Newton's method and linear equations by preconditioned non‐stationary iterative solvers (CGS, Bi‐CGSTAB, BiCGSTAB(2), TFQMR). the run time is reduced dramatically, by up to an order of magnitude.
Symbolic analysis approach to settling time minimization in sc networks
Authors: Handkiewicz Andrzej , Śniatala Pawel 
Published: July 2007

AbstractThe paper presents a method of settling time minimization in switched capacitor (SC) circuits. This problem has been discussed in recent papers because of high‐frequency applications of SC networks. In comparison with the methods elaborated up to now and limited to biquads, the method presented in this paper can be used for an SC circuit containing an arbitrary number of operational amplifiers coupled together in each switching state and modelled as ideal transconductances. the fifth‐order ladder bilinear SC filter is considered for illustration of the method and SPICE simulations.
Swann‐a programme for analysis of switched analogue non‐linear networks
Authors: Valsa Juraj , Vlach Jiri 
Published: July 2007

AbstractThis paper describes SWANN, a programme for fast simulation of non‐linear switched analogue networks. the switches act as open and short circuits and are used to model switching diodes, transistors or thyristors. Non‐linearities of other elements such as capacitors, inductors, resistors, conductors and dependent sources, are modelled by polynomials. Possible inconsistent conditions which can appear in networks with ideal switches are correctly handled. At switching instants the values from left and right are obtained and are available for plotting. Examples show applications in communications and power electronics.
Analogue placement using guided enumeration
Authors: Abthoff Tobias H. , Johannes Frank M. 
Published: July 2007

AbstractIn this paper a new efficient approach to the placement problem of analogue circuits is presented. In the design of analogue circuits, strong interaction between humans and automatic tools is crucial to obtain good results. Hence there is a strong need for fast algorithms to support an interactive and incremental design style. In the design process, usually many geometric constraints such as symmetry or matching requirements are introduced by the designer to obtain a placement that fulfils all electrical requirements. Most state‐of‐the‐art analogue placement tools employ simulated annealing algorithms and map geometric constraints into the cost function of the annealing algorithm; thus they have to search the whole design space. In our approach an initial global placement is computed establishing neighbourhood relations between all modules. Afterwards the design space is reduced to placements that fulfil these neighbourhood relations and user‐specified geometrical constraints. the reduced design space is fully enumerated to find the optimal solution. the implemented tool achieves typical CPU times of a few seconds for designs of about 40 modules, making it an excellent choice for an interactive design process. Two examples are presented: (i) a high‐speed CMOS comparator lay‐out is compared with lay‐outs published in other papers and (ii) a BiCMOS bandpass amplifier lay‐out that has to be embedded into a mixed‐signal chip is compared with the manual lay‐out of a fabricated chip. We achieved the smallest lay‐out size published for the comparator while fulfilling all required constraints. For the amplifier the synthesized lay‐out is very similar to the manual one and about the same size.
Nullator‐norator approach to analogue circuit diagnosis using general‐purpose analysis programmes
Authors: Farchy Samuil L. , Gadzheva Elisaveta D. , Raykovska Lyudmila H. , Kouyoumdjiev Todor G. 
Published: July 2007

AbstractIn this paper a decomposition approach to diagnosis and fault prediction in large analogue and switched capacitor circuits is proposed, reduced to an analysis of the corresponding nullator‐norator models at a single test frequency. Algorithms for isolation of faulty nodes and subcircuits are presented. the topological conditions for performing diagnosis of faulty nodes and for identification of faulty elements have been considered. the element tolerance variations and measurement errors have been taken into account. the possibilities of the general‐purpose programmes for frequency and worst‐case analysis have been used in the practical implementation of diagnosis and fault prediction. Diagnosis of benchmark circuits has been performed and the results of a computer simulation using the programme PSpice are presented.
A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier
Authors: Karoubalis Theodore , Adaos Kostas , Alexiou George Ph. , Kanopoulos Nick 
Published: July 2007

AbstractThis paper describes an efficient technique for the design of fault‐secure VLSI circuits based on differential cascode voltage switch (DCVS) logic. We propose a new synthesis method for constructing DCVS circuits with a near‐optimal transistor count based on binary decision diagrams (BDDs). the time and memory resources required are very low, making the technique practical even for PC‐based synthesis tools. This method is the basis for a CAD tool that allows automatic synthesis of fault‐secure circuits based on the DCVS technology. We finally present an improved design and implementation of a 2's complement serial/parallel multiplier as an application of the proposed technique and algorithm.