bluuebunny/crossref_metadata_2025_split huggingface dataset:
An adaptive LMS algorithm with a quick tracking property for time‐varying parameter estimation
Authors: Usui Shiro , Abe Kenichi , Qiu Zhong‐Qi 
Published: July 2007

AbstractThis paper proposes a method which estimates time‐varying parameters of a nonstationary signal such as a biological one in real time. This method is based on a local quasi‐stationary concept in the block processing and on the standard LMS algorithm in the recursive processing. That is, we consider a first‐order approximation to the time‐varying parameters for a short period of time, and estimate coefficients of the constant and the first‐order variation terms by the standard LMS algorithm. At the end of each period the estimated values are renewed.This approach does not require calculating matrix inversion and It uses only input values at each time to estimate time‐varying parameters adaptively. Also, it can be implemented because of its simplicity. The most attractive point of this approach is that the coefficients of the first‐order variation terms are estimated at each time, and thus quick tracking of time‐varying parameters can be achieved. This improves the tracking performance drastically.A convergence property of the proposed algorithm is discussed theoretically. Finally, simulation results are presented to illustrate the tracking performance of the proposed algorithm compared with that of the standard LMS algorithms.
LSI logic synthesis expert system
Authors: Kurosawa Yuichi , Nishio Seiichi , Masubuchi Yoshio , Miyata Misao 
Published: July 2007

AbstractThis paper describes the expert system which automatically generates the logic circuit composed of elements registered in the cell library, receiving the functional description at the register transfer level of the hardware as the input. The features of the system are that it includes the dedicated circuit data structure, the rule description language, and the corresponding processing system, which can generate a high‐quality large‐scale circuit in a short processing time.In other words, by introducing the technology‐independent functional elements into the data structure, the circuit can be generated by effectively utilizing the high‐level functional library elements. By including the mechanism for the local transformation into the system and by other sophistications, a practical processing speed is realized. The knowledge depending on the library and the user, is formulated into rules. This is useful in providing the system with flexibility. The system has already been applied to the development of more than 30 kinds of practical products. Using a large‐scale computer with 15 MIPS, a circuit with several thousands of gates can be generated automatically in 4 to 12 min.
A knowledge based system for embedding DFT‐methodologies
Authors: Furuya Kiyoshi , Shinoda Shoji , Koguchi Kazuhito 
Published: July 2007

AbstractThe application of the DFT (design for testability) technique to VLSI circuits is a difficult procedure, since it requires the knowledge concerning the application environment, effectiveness and cost of individual techniques. This paper discusses an automatic embedding system for DFT techniques, dealing with the circuit at the functional block level. The system is constructed with the goal of easy implementation and modification of DFT functions. The use of a generalpurpose inference engine is assumed. DFT techniques as well as circuit structures are represented by a structured database, and the rules to be applied are represented by a rule base. When more than one DFT technique can be applied to a block to be tested, the one minimizing the cost function is adopted. The selection of the generator and compressor is accelerated by the use of a heuristic method. As DFT techniques, the exhaustive testing, locally exhaustive testing and random testing are implemented for combinational circuits. Universal testing, memory random testing and built‐in memory testing are implemented for PLAs. OPS83 was used as the tool for construction.
Analysis for singular equation in search process for operating state of transistor network
Authors: Mizutani Hikaru , Tanaka Mamoru 
Published: July 2007

AbstractThis paper describes a method to avoid the singular problem at the “S‐control” algorithm. The “S‐control” is proposed to determine the correct operating state in any bipolar transistor network (BTN). Each diode of the Ebers‐Moll model is replaced with a directional switch called an S‐branch which has “on” and “off” states. The switch status is changed by the S‐control algorithm. However, the matrix singular problem occurs in the process of the S‐control. The singular matrix is formed by a cutset of only current sources or a loop of only voltage sources. The singular problem is solved by the signdiscrimination method by which the sign of each node voltage is judged by the introduction of small immittances in cutset (loop) of only current (voltage) sources formed in process of the S‐control. The S‐control algorithm will be continued to obtain the next switch state unless the limit cycle is not generated.
Systolic array implementation of 2‐D digital filters using 2‐D block processing
Authors: Hirano Yasuhiro , Takebe Tsuyoshi 
Published: July 2007

AbstractThe requirements of high‐speed filtering are more serious in 2‐D digital filters than in 1‐D digital filters because the former must perform many more operations and deal with considerably more data. This paper proposes a systolic array implementation of 2‐D digital filters using 2‐D block processing.First, an extension of systolic array implementation for 1‐D block processing into 2‐D block processing is shown and then the circuit is decreased by improving it. This systolic array has a disadvantage in that the number of processing elements per sample increases in proportion to the processing speed.To improve this situation, we present an implementation method for obtaining the throughput proportional to the number of arrays by using multiple systolic arrays having multilayer structures. This circuit behaves like a 3‐D systolic array.
Design of fresnel‐zone IDT pattern and two‐dimensional acoustic field
Authors: Shiokawa Showko , Matsumoto Shigeo 
Published: July 2007

AbstractThe following theoretical results were obtained in a previous paper. A focused acoustic field can be obtained by dividing the interdigital transducer (IDT) in the form of a Fresnel‐zone type in the aperture direction. The focal point obtained by a geometric method and the computed result by the angular spectrum of plane wave (ASPW) method do not coincide. A new design method based on the clarification of the cause of disagreement was proposed. The electrode based on this design method was called the Bessel‐type Fresnel‐zone IDT. It was shown that the computed value and the design value agree.In this paper, the proposed design method is confirmed experimentally. Hence, a Fresnel‐zone IDT was fabricated on a PZT piezoelectric substrate and the amplitude was measured by an optical probe. The theoretical and experimental result agreed and the validity of the theory was confirmed. Based on these results, the characteristics of the two‐dimensional acoustic field excited by a normalized IDT were studied.
Design of three‐dimensional IIR digital filters with complex coefficients using spectral transformations
Authors: Sekiguchi Takashi , Takahashi Shin‐Ichi 
Published: July 2007

AbstractThis paper describes a design method of three‐dimensional recursive digital filters with complex coefficients by means of spectral transformations applied to one‐dimensional recursive digital filters with complex coefficients. In multidimensional filters with complex coefficients having an analytic input signal, characteristics can be made arbitrary in the regions in which an input signal frequency component does not exist. Therefore, the degrees of freedom in design increase significantly. Since complex coefficient filters are introduced in the one‐dimensional prototype filter and the spectral transformation function (subfilter), there is no restriction on the cutoff radius in the spherically symmetric filters. In three‐dimensional recursive symmetric fan filters, (cone filters) the design of a passband with an almost arbitrary solid angle becomes possible by the direct transformation from one dimension to three. Also, the stability of the resulting filters is always guaranteed.
Extended pareto optimality concept for multiobjective linear programming problems with fuzzy parameters and its properties
Authors: Sakawa Masatoshi , Takahashi Junya , Yano Hitoshi 
Published: July 2007

AbstractIn order to handle multiobjective linear programming problems containing fuzzy parameters, the authors have already proposed four kinds of α‐feasibility and β‐Pareto optimality, based on the four kinds of index introduced by Dubois et al. This paper discusses the proposed concepts of four kinds of β‐Pareto optimality in further detail, in order to indicate problems with β‐Pareto optimality. As a means of coping with those problems, four kinds of γ‐Pareto optimal solutions are introduced. Then the concept of (α, γ)‐Pareto optimal solution is introduced, by considering simultaneously the α‐feasibility and the γ‐Pareto optimality. It is shown that the set of (α, γ)‐Pareto optimal solutions, which can be regarded as the most optimistic and the most pessimistic, can be found using linear programming.
Design of separable‐denominator two‐dimensional digital filters based on the reduced‐dimensional decomposition of frequency domain specifications
Authors: Deng Tian‐Bo , Kawamata Masayuki 
Published: July 2007

AbstractThis paper proposes a new technique for design of separable‐denominator two‐dimensional digital filters (2DDF·s) in the frequency domain. The technique is based on decomposing both the transfer function of a separable‐denominator 2DDF and the given 2DDF frequency domain specification into a product of two one‐dimensional ones. By these decompositions, the design problem of a separable‐denominator 2DDF can be reduced to the design of two IDDF·s. The technique makes it possible to design separable‐denominator 2DDF·s by utilizing IDDF design techniques directly. Thus stable separable‐denominatro 2DD·s satisfying the given specifications can be designed efficiently.
Functional simulation of color signal processor for VTR by digital dynamics simulation language
Authors: Hayashi Shin‐Ichi , Watanabe Toshinori , Furihata Makoto , Yamamoto Norihisa 
Published: July 2007

AbstractWith the development of semiconductor integration, the technology has arrived at the stage of the system‐on‐chip. With the widespread use of application specific IC (ASIC), the small‐quantity production of diversified types is required. Then it is important to reduce the design period for the mixed analog/digital circuit.VTR color signal processing LSI is a typical mixed analog/digital circuit. It has the scale of 500 analog elements and 800 digital elements, and it is too time‐comsuming to simulate the operation of the whole LSI by the conventional circuit simulator. Thus, a functional simulator is required for the large‐scale mixed analog/digital LSI.This paper proposes a functional simulation, employing techniques of continuous system simulation. The technique is applied to the design of a mixed analog/digital circuit, where the conventional method has been unsatisfactory, and the method is shown to be useful in the Functional design of the circuit. The method is based on the modeling of the mixed analog function/circuit, and can be applied to the VTR color signal processing LSI.The functional simulation can easily be performed with the complete knowledge of the analog function. Consequently, the method can contribute greatly to the quality improvement of the design and the reduction of the design period.
A 64‐points switched‐capacitor discrete fourier transform circuit for high‐speed inverse discrete fourier transform circuit
Authors: Ogihara Akio , Yoneda Shojiro 
Published: July 2007

AbstractThe Discrete Fourier Transform (DFT) and Inverse Discrete Fourier Transform (IDFT) are used for solution of various problems in communications, signal processing and many fields of science. This paper proposes a new method to execute DFT which enables one to realize a high‐speed IDFT circuit with small circuit configuration. In this method, multiplying the DFT equation by the exponential term of the IDFT equation beforehand, IDFT processing is carried out only by addition without increasing the complexity of DFT processing. Using this method, a 64‐points DFT‐IDFT circuit is made on an experimental basis by the switched‐capacitor (SC) technique. In addition, the SC DFT‐IDFT circuit is applied to the recognition of Japanese vowels, and its validity is verified experimentally.
An efficient algorithm for the linear assignment problem
Authors: Yamada Shoichiro , Kasai Tamotsu 
Published: July 2007

AbstractAlthough numerous exact algorithms have been proposed so far for the linear assignment problem, they are not necessarily satisfactory from the viewpoint of computation time when considered for application to practical large‐scale problems.This paper proposes a new algorithm which can reduce the expected computation time needed to find an exact solution for the linear assignment problem by limiting the search space as much as possible within the scope in which no optimal solution is missed.Here, first, an equation is derived to give an upper bound of the search space so as not to miss an optimal solution in the process of finding an alternating path. Next, data structure is described for developing an operation to limit the search space based on this equation and an assignment algorithm is derived. As the results of experiments, the expected computation time of the algorithm O(n2) for preprocessing and 0(nl.6) for the process of finding an assignment of points were found. In addition, it was shown that the algorithm can be applied to large‐scale problems since in the planar assignment problem for which an assignment cost function is defined in the plane, the expected computation time is 0(n1.6) including preprocessing.
Problems in computer‐aided simulation and design of analog integrated circuits–stability of analog integrated circuits
Authors: Fujii Nobuo 
Published: July 2007

AbstractThis paper describes the problems, mainly from a standpoint of circuit stability, in the case in which we analyze and design analogue integrated circuits using a computer simulation program. Although a fundamental condition of an analogue circuit is whether DC bias can be determined stably or not, computer simulation is not good at this stability check and it is pointed out that an unstable circuit is sometimes checked to be stable accidentally. In the circuit partitioning process used in large‐scale integrated circuits, a risk that is shown in examples is that, depending on the manner of partition, its subcircuit may become unstable and it makes analysis of the whole circuit impossible. As an example we take SPICE, a representative program for analogue circuit simulation, to discuss the problem of default values in the program, direct current bias analysis, one that inside of a computer is assumed to be ideal, and the necessity of transient analysis. Then it clarifies the importance of correct modeling of circuit elements and careful usage of a simulation program after good understanding of its properties.
Sequential analysis for transistor networks including distributed‐constant circuits
Authors: Mizutani Hikaru , Tanaka Mamoru 
Published: July 2007

AbstractWith the recent development of integrated circuit technology, high‐density and high‐speed integrated circuits are produced. Then the wiring capacitance and wiring resistance of the circuit cannot be ignored, and it is necessary to develop a new circuit simulation method considering the parasitic effects of the wiring. The parasitic effect is represented by a distributed‐constant circuit, and a partial differential equation representing the distributed‐constant circuit must be solved to analyze the parasitic effects.When a partial differential equation is discretized by applying the finite‐element method, however, the analysis of the circuit is reduced to the analysis of the higher‐order equation which requires a tremendous computation time and memory capacity. This paper attempts to avoid this problem, and presents a method in which the circuit is analyzed equivalently without increasing the number of unknowns by applying the sequential analysis to replace the distributed‐constant circuit by three resistors and two current sources.
Analysis of switched networks based on virtual state equation for avoiding singularity problem
Authors: Mizutani Hikaru 
Published: July 2007

AbstractThis paper considers the switched (S) network obtained from the bipolar network by replacing each transistor by its Ebers‐Moll model and further replacing the diode in the model by the switch and the voltage source. The switching (S) control is proposed as a method to determine the operational state of such a network; S control is a method where the S network is analyzed under the assumed switching state S−, and the new switching state S+ is determined based on the result of analysis. The procedure is iterated until S+ = S− is valid.However, the analysis by S control contains several problems in its execution, such as the singularity problem, where the coefficient matrix of the network equation becomes singular, or the limit cycle problem, where several S states are circulated.This paper presents a method of analysis for the S network, where virtual capacitors and inductors are added between switch terminals, and the solution is obtained as the steady‐state solution obtained by the numerical integration of the state equation. The singularith problem is dissolved by the proposed method.It is shown also that some networks, in which the limit cycle phenomenon arises by the conventional method, can be analyzed by the proposed method without the problem. By appropriately setting the values of the capacitors and inductors in the proposed method, the calculation of the inverse matrix can be eliminated in the numerical integration steps, and the high‐speed computation composed only of the additions and multiplications of matrices can be realized.
Separation of mixed voices by acoustic parameter optimization
Authors: Morita Tatsuya 
Published: July 2007

AbstractThe human auditory response is highly adaptable to the environment, enabling voices to be recognized even in a noisy environment. This ability is due primarily to the language processing function in the central auditory nervous system, but the binaural sound locating function also seems to play an important role. From such a viewpoint, the author has presented a method which estimates the sound source locations and separates the voices from more than one speaker using the position information.A problem in this method is that the acoustic space is assumed as a free space, and the voice is separated based on the sound field model. Consequently, in the actual sound space, the estimation of the source location may be incorrect, thereby making the voice separation inaccurate.This study proposes a method whereby the separation index is estimated using the evaluation function based on the cross correlation of the separated voices, and the sound parameters are sought in the direction to minimize the evaluation function to improve the voice separation. The effectiveness of the method is verified by an experiment.
Stationary performance of series‐parallel‐type adaptive digital filter based on a logarithmic estimation
Authors: Kobayashi Masaki , Itoh Yosio 
Published: July 2007

AbstractThe series‐parallel ADF is constructed for the unknown system by placing the logarithmic estimation ADF in series and the transversal ADF in parallel. Its features are that the examination of the stability is unnecessary since the transfer function as well as its inverse transfer function of the logarithmic estimation ADF are stable, and the number of taps can be reduced compared to the conventional transversal ADF.This paper presents the analysis and verification for the steady‐state estimation accuracy for the tap coefficient and the echo elimination, for the case where an additive noise exists at the near end of the series‐parallel ADF. The construction of ADF and the adaptive algorithm based on the LMS method is described first. Using the Taylor series expansion near the solution, the steady‐state algorithm is discussed. Finally, the derived result is verified by a computer simulation indicating that the theory and simulation agree well.
Performance improvement of LMS algorithm
Authors: Takahashi Kiyoshi 
Published: July 2007

AbstractWith the recent rapid progress of VLSI, digital signal processing is used in a wide variety of areas. Recently, the adaptive system has been used widely in many applications.This paper describes a new algorithm to improve the rate of the adaptation of the LMS (Least Mean Square) algorithm, which is used most commonly as the adaptive filtering algorithm. The new algorithm is based on the dynamics of the network in the Hopfield model, which is the one of the neural networks.Also, in the new algorithm, the coefficients are updated a few times on each sampled datum. The rate of adaptation of the new algorithm is faster than the rate of the well‐known LMS algorithm. However, the use of the new algorithm requires more operations than the standard LMS algorithm, and it is easy to implement. A system with the rate of the adaptation which does not converge in the conventional LMS algorithm can be realized.
Floating‐point error analysis for recursive least‐square algorithm using ud factorization
Authors: Tsubokawa Hiroshi , Kubota Hajime , Tsujii Shigeo 
Published: July 2007

AbstractThe real‐time processing of the recursive least‐square algorithm is difficult to execute by the conventional Neumann‐type processor because of its large computational complexity. On the other hand, it is known that the recursive least‐square algorithm based on the UD decomposition, which is equivalent to the recursive least‐square algorithm, can be realized by the systolic array proposed by Kung. The systolic array to execute this algorithm is difficult to realize since it requires a tremendous number of elements and corrections.In the construction of the dedicated hardware, in general, the word length of the processor affects the processing speed and the hardware area. From such a viewpoint, it is important in the construction of the systolic array to execute the recursive least‐square algorithm based on the UD decomposition that the word length of the processor should be minimized. To evaluate the word length, an error analysis is required for the finite word length operation of the recursive least‐square algorithm based on the UD decomposition.This paper presents the finite word length floating‐point error analysis for the recursive least‐square algorithm, based on the UD decomposition, and evaluates the operation error. Then the convergence of the algorithm and the number of updates of the algorithm are evaluated anlytically. Finally, by a computer simulation, the validity of the theoretical analysis for the convergence and the number of updates is verified.
Number of segments of rectilinear drawings of a graph whose vertices are fixed on a plane
Authors: Takahashi Toshihiko , Kajitani Yoji 
Published: July 2007

AbstractThe graph in which vertices are assigned different coordinates on the xy‐plane is called a rivetted graph. When a rivetted graph G is drawn so that each edge is composed of horizontal and/or vertical segments, it is called a rectilinear drawing of G. This study is an attempt to evaluate the total number of segments l(G) necessary and sufficient for the rectilinear drawing of a rivetted graph G. As a major result, it is shown that l(G)⩽4m and especially, l(G)⩽3m, if a vertex pair does not exist with the same x or y coordinate, using a construction algorithm with the computational complexity of O(m + ξ), where m is the number of edges and ξ is the number of isolated vertices in the graph. For examples of G, nontrivial lower bounds for l(G) also are considered.