bluuebunny/crossref_metadata_2025_split huggingface dataset:
Design and implementation of the s & t net software
Authors: Murai Jun 
Published: July 2007

AbstractFlexibility, extensibility and reliability of a computer network are efficiently achieved by a design with hierarchical architecture. In an actual network system the network design should be implemented by modules corresponding to the layers of the hierarchical architecture in order to realize its inherent advantages. Generally, in highly modularized software the problem of overhead in transferring data between modules has to be solved. This paper presents a method of network software design which is easily implemented by a highly modularized software structure and describes implementation of the architecture through separate communication control and data processing in an operating system. These presentations are made by introducing the methods employed in constructing a local computer network called the S & T net. The methods presented in this paper can be applied generally to the design and realization of network software.
The measurement of the 3‐d position of the polyhedra
Authors: Guo Heng‐Li , Yachida Masahiko , Tsuji Saburo 
Published: July 2007

AbstractThe scene containing polyhedra has been studied as one of the interesting subjects in research on robot vision, and several methods for extracting the line drawing of the polyhedron have been proposed. However, few have dealt with estimation of the location and orientation of the polyhedron in 3‐D space. This paper proposes a method for measuring the 3‐D position (location and orienation) of the known polyhedron by effectively utilizing the shade information. In other words, the relations among the polyhedron, its image and shadow image are analyzed, by which the 3‐D coordinates of four noncoplanar vertices of the polyhedron, are determined. The candidates for mapping of the measured vertices to those of the polyhedron are found by the distance search method or by the feature reference method. Using the coordinates of the candidates, the polyhedron is reconstructed, together with its shadow. By comparing these reconstructed shadows SR' with the original shadow SP', the one providing the best fit is adopted as the solution. The method is applicable even if there is no difference among the brightness of the surfaces. The experiment shows that the error in measurement of the 3‐D location and orientation by the proposed method are within 2 and 5 percent of the visual field, respectively.
A Hierarchical General‐Purpose Pipeline System
Authors: Endo Noboru , Nakamura Tadao , Shigei Yoshiharu 
Published: July 2007

AbstractThe intelligent links that orient realization of the computer system integrating data communication and processing have been proposed. However, the practical system configuration and control have not yet been discussed. Based on the general‐purpose pipeline concept to implement the intelligent link, this paper presents the hierarchical pipeline system configuration that is designed to obtain high efficiency of the total system by overlapped data communication and processing. The decision method of the processing time in the segment at a higher level which is a processing unit in the pipeline, is shown.The decision is made independently at each segment. Therefore, this hierarchical pipeline system enables parallel processing by distributed control. The routing algorithm in the general multitrack bus is proposed as a communication medium executing high‐speed data transmission among the lower‐level pipeline processing elements in the segment.
Equilibrium point analysis of memory interference in multiprocessor systems
Authors: Fukuda Akira 
Published: July 2007

AbstractAn approximate analytic tool called equilibrium point analysis is applied to the problem of memory interference in multiprocessor systems. This is a simple and powerful analytic tool based on the fluid approximation. It has been used widely in packet broadcast systems. It is shown that quite general multiprocessor systems can be studied by this technique with amazing simplicity. For example, systems made up of many classes of processors and memory modules with arbitrary static memory reference patterns and systems with dynamic memory reference patterns are considered. In most cases, the approximation of the analysis is shown to be sufficiently good. One of the advantages of this technique is that the error is smaller for larger systems for which there have been no appropriate analytic tools thus far.
Complexity to determine containment among inequality tableau queries
Authors: Terada Tomoyuki , Hagihara Ken'Ichi , Tokura Nobuki 
Published: July 2007

AbstractTableau queries are known as abstract models of queries for relational databases. When two tableau queries are given, the problem of determining whether the result of one of the tableau queries always contains that of the other (containment decision problem), is of fundamental importance in obtaining the optimization procedure of tableau queries. The tableau queries defined by Aho et al. can express joins, projections and selections by equalities in the relational algebra. Under this definition, Aho et al. have shown that the containment decision problems are generally NP‐complete and that there exist a class of problems which can be decided in a polynomial time. In this paper, we classify the tableau queries which are obtained so as to be able to express the selections by inequalities into two groups by whether or not they are totally ordered. We show that if inequality selections are added to problems which can be solved in a polynomial time without inequality selection, then the containment decision problems are NP‐complete even though the tableau queries are totally ordered. Also, for queries which are not totally ordered, it is shown that even if stronger restriction is added, the containment decision problems are co‐NP‐complete.
Performance Evaluation for Memory Subsystem of Hierarchical Disk‐Cache
Authors: Miyachi Taizo , Mitsuishi Akitoshi , Mizoguchi Tetsuo 
Published: July 2007

AbstractThe memory subsystem hierarchical disk‐cache (MESSIAH) discussed in this paper aims at realization of high‐speed access to secondary memory. MESSIAH uses a large‐capacity buffer memory (A) for the input‐output device and a small‐capacity buffer (B) for each disk‐device. (A) realizes the traditional disk‐cache function. (B) realizes reduction of the disk‐rotations waiting time due to a miss in RPS (rotational position sensing), reduction of overlap between disk write‐in and search time, and immediate delivery of look‐ahead data. In other words, in MESSIAH (A) realizes a cache memory of sufficient capacity and (B) copes with RPS misses, which increase with size of the transfer block between disk and (A). (B) also realizes high‐speed write‐in and read‐out of the disk. Thus, MESSIAH provides greater advantage than the multiple effects of disk‐cache function and the B‐disk (buffer‐installed disk device). This paper proposes an architecture for MESSIAH and verifies its usefulness by simulation.
Performance analysis of line scheduling methods for multilink procedures
Authors: Kobayashi Tetsuji 
Published: July 2007

AbstractA data link with multiple lines can be implemented by using the standard protocol of a multilink procedure. The multilink procedure achieves performance flexibility and reliability improvement. This paper proposes line scheduling methods at a sending station, which is an important factor for implementing multilink procedures, and evaluates their performance. A line scheduling for a multilink procedure selects a line to which a multilink frame, which is the transfer data unit, is assigned. The speed of the lines may be equal or different. The following methods are studied: (1) rotational scheduling, (2) stochastic scheduling and (3) adaptive scheduling. The adaptive scheduling method is shown to have the best performance. For easy implementation it is shown that the rotational scheduling method can be applied to lines with equal speeds and that the stochastic scheduling method can be applied to the lines with equal or different speeds.
A square root hardware algorithm using redundant binary representation
Authors: Takagi Naofumi , Yajima Shuzo 
Published: July 2007

AbstractThis paper proposes a square root hardware algorithm using the redundant binary representation in the internal computation. A discussion is made for the realization of a combinational square‐rooter based on the algorithm. This paper considers the computation of the mantissa in square‐rooting for the binary normalized floating‐point representation. The proposed algorithm is a kind of subtract‐and‐shift square‐root method. Partial remainders are represented by the redundant binary representation, where each digit is an element of {‐1, 0, 1}. Then each digit of the square root is determined from {‐1, 0, 1}, by examining the upper three digits of the partial remainder. The computation for the partial remainder is affected in the redundant binary number system. Finally, the square root determined in the redundant binary representation is converted into the ordinary binary representation. In the redundant binary representation, the addition of two numbers can be effected without carry propagation. Consequently, by using the combinational circuit, each digit of the square root can be determined in a constant time, independently of the number of digits of the operand. The computation time for the n‐bit square rooter (number of stages) is proportional to n. The number of logic elements in the circuit is proportional to n2. The hardware structure is a regular cellular array, which is suited for VLSI implementation. When the circuit is implemented on a VLSI chip, the chip is proportional to n2. The proposed square rooter has nearly the same circuit structure and the hardware complexity, compared with the conventional subtract‐and‐shift square rooter using ripple carry adder. The computation time is approximately one‐fifth for 32‐bit and one‐tenth for 64‐bit, compared with earlier circuits.
Deadlock detection algorithm with level number
Authors: Eguchi Yoshikazu , Yoshinaga Tsunehiro 
Published: July 2007

AbstractThe detection of deadlock is one of the important problems in the database system. This paper proposes an efficient algorithm for detecting the deadlock in the concentrated database system, and demonstrates its correctness. The algorithm works as follows. When a process makes an access to a resource which is locked by another process, the process must wait for the resource. The algorithm detects the deadlock by tracing the edges of the resource graph, starting from the waiting process. By attaching the level number to each node, the number of edge tracings can be reduced, which helps to reduce the overhead for deadlock detection. To evaluate the efficiency of the proposed algorithm, an experiment was performed by computer simulation. The cases of the algorithm with and without the proposed level number are compared, indicating the effectiveness of the proposed method.
Transparent memory: A hardware solution to the memory conflict problem
Authors: Hisano Takumi 
Published: July 2007

AbstractThe paper proposes a memory organization aiming at reduction of memory conflict produced by the multiple access. The proposed memory organization has the effect of suppressing not only the memory conflicts but also the write memory conflicts. The conflict of read access is suppressed by using more than one memory module of the same content, and the conflict of write access is suppressed by restricting the write area and using the distributed communication mechanism. It is shown by the performance evaluation simulation that the memory conflict is sufficiently small compared with the number of multiple read memory and approaches a constant with the increase of the number of processors n. The hardware complexity is relatively large. The physical memory is n times compared with the logical address space and the number of memory control circuits is n2. There is one connection between the memory control circuit and the connection network. By specifying the area of applications and simplifying the connection configuration, the hardware complexity can be reduced.
Method of pattern positioning for automatic verification of seal imprint
Authors: Ueda Katsuhiko , Nakamura Yoshikazu 
Published: July 2007

AbstractIn automatic computer verification of seal imprints accurate positioning of an examined seal imprint over a registered imprint is of great importance. This paper proposes a method which positions an examined seal imprint in relation to a parallel shift and rotation by using the centroid of its frame figure and the pixels on a circle of a certain radius from the centroid. Since this method achieves positioning by using local features of the examined seal imprint, rapid positioning is possible. In the presence of small defects in the imprint frame this method has the advantage that the centroid of the seal imprint is accurately obtained and is not affected by distortion of the imprint frame. In a positioning experiment based on this method 240 actual seal imprints were used. All imprints were positioned within a ±0.1‐mm parallel shift error and more than 99% of the seal imprints were positioned within ±1.76° rotation angle errors. A verification experiment was conducted using a seal imprint verification system which incorporated the principles of this method. As a result, the verification error which was caused by the positioning error was found to be 0.83%. The experimental results show that the proposed positioning method is efficient for automatic verification of seal imprints.
The application of tense logic to database behavioral description
Authors: Tarabe Koichiro , Suzuki Atuyuki 
Published: July 2007

AbstractThis paper defines a presupposition‐free many‐sorted tense theory MQRT*=. This theory is applied to behavior description of historical database. Using this theory makes it possible to express clearly not only the usual schema information but also such behavioral aspects of schema as event, dynamic integrity constraint, etc. This is the first time behavior description has been provided by a complete theory. This theory is also applied to schema description of historical database. Providing both schema description and behavior description amounts to total, full description of historical database.
A restoration scheme for images with missing parts
Authors: Maeda Hiroyuki , Takahashi Kenichi , Ohta Masamitsu 
Published: July 2007

AbstractThis paper proposes a restoration scheme which restores a group of pixels by malfunctioning of imaging equipment or a part of an object hidden by another object. This restoration starts on the circumference of the group of missing pixels and proceeds to the interior to make the restored image acceptable for the human viewer. First, edges of objects in the neighborhood of the missing pixels are extracted. Second, the direction of the edge passing through a pixel to be restored is estimated by the least‐square method. The estimated edge direction is used to determine reference pixels from which the missing pixel is restored. Care is taken so that the restored gray level of the missing pixel is not extremely different from those of its neighbors. If an edge enters a missing part of an image and another edge goes out of this part, the two edges are connected to produce a single, smooth edge. Computer simulations will demonstrate the effectiveness of the proposed method.
System design of a special‐purpose computer for LSI design rule checking
Authors: Tamaru Keikichi , Onodera Hidetoshi 
Published: July 2007

AbstractThis paper describes a hardware system for pattern operations and design rule checking (DRC) in LSI layout design. This is a multimicrocomputer system which performs the parallel processing in the pattern data of each of the divided areas and the pipeline processing of input, pattern operation and output stages. The system consists of two upper‐level computers and a number of lower‐level computers. The upper‐level computers perform input/output of pattern data, control over the system and pattern operations for figures which spread over more than two divided areas. Each lower‐level computer executes pattern operations and DRC against figures of the assigned area by the sliced‐vector method.
Three‐state neumann neighbor cellular automata capable of constructing self‐reproducing machines
Authors: Serizawa Teruo 
Published: July 2007

AbstractThis paper defines the 3‐state Neumann‐neighbor cellular automata, and shows that its space is construction‐universal. The proof for this is achieved by presenting a realization of self‐reproducing machines. The state‐transition rule and the basic operations of configurations of the cellular automata are described first. Then methods are shown to construct AND circuit, pulse generator, signal‐line, delay circuit and memory circuit. Finally, the structure of the self‐reproducing machine is shown, which is realized by combining those circuits, The machine has two construction arms, a Turing tape and a timing loop. It can make a replica of its own using the Turing tape. The machine can also be operated as a universal construction machine or a universal Turing machine.
Consonant recognition methods for unspecified speakers using bpf powers and time sequence of LPC cepstrum coefficients
Authors: Niyada Katsuyuki , Hoshimi Masakatsu 
Published: July 2007

AbstractThis paper discusses the recognition of the consonant (except the consonant at the top of the word) in a word for unspecified speakers. First, the consonant section is detected based on the power dips extracted from the low‐ and high‐frequency power information, together with the nasal and unvoiced properties.Applying the discrimination diagram to the detected low‐ and high‐frequency dips, the phoneme is classified into the four phoneme classes (rough classification). Then methods are discussed which discriminate the individual phonemes in the phonemes group by pattern matching (fine classification). Using the time‐series pattern of the LPC cepstrum coefficient as the parameter, it is shown that the comparison with the standard phoneme patterns using the Bayes' discriminant and the Mahalabinos distance is the most useful. The result of recognition experiment using the segmentation, rough classification, and fine classifications is presented. For twenty subjects of both sexes, the mean recognition rate of 78.1 percent was achieved.
Parallel searches of game trees
Authors: Usui Hiromoto , Yamashita Masafumi , Imai Masaharu , Ibaraki Toshihide 
Published: July 2007

AbstractA two‐person perfect‐information game is represented by a minimax game tree and, by solving the tree, we can obtain the result of the game when both players choose perfect moves at all the positions. To this end, various search procedures have been proposed. In this paper, these procedures are modified to implement them on a parallel computer consisting of m processors, and variations of the computation time are investigated with m being a parameter. As a theoretical result, we point out that the speedup ratio of the computation time of solving a game tree by m processors to that by 1 processor may become larger than m (acceleration anomaly) or smaller than 1 (detrimental anomaly) in general. Also, we show that the detrimental anomaly does not occur as long as the five search procedures investigated in this paper are used. Next, through simulation experiments, it is shown that the speedup ratio is considerably smaller than m, and its cause is discussed. The eligible search is considered to be the best among the search procedure investigated.
Characteristics of a programmable logic unit
Authors: Member Takahiko Murayama, Associate , Yamada Hidekazu , Nakamura Tadao , Shigei Yoshiharu , Yoshioka Yoshio 
Published: July 2007

AbstractThis paper considers a programmable logic unit (PLU) which is a computing‐in‐memory device with stepwise programmable computing logics and the data transmission lines/buses, and discusses its operational characteristics. The PLU is combined with the memory device in a Neumann‐type computer with a great number of computing logics. From the viewpoint of Flynn's classification in the Neumann‐type computer, we consider the level‐1 PLU and the level‐2 PLU as structures for the PLU, and discuss their configurations in detail. First, we discuss the mapping method and the number of steps for the program of the mathematical expression. It is shown that the PLU can map directly the program written in the inverse‐Poland notion and that the connection lines/buses can easily be assigned. Second, we discuss the comparison between the computing time of the computer with the PLU and the processing time of the Neumann‐type computer. It is shown that the computer with the PLU is several times faster than the Neumann‐type computer in processing the program. On the other hand, it is seen that the level‐2 PLU with the distributed buses is suited to the general‐purpose computer, although the processing speed is somewhat low.
A built‐in test for functional testing in semiconductor random access memory
Authors: Miura Yukiya , Tamamoto Hideo , Narita Yuichi 
Published: July 2007

AbstractThe increasing time for functional testing of the logical circuit has become a problem in recent years. As a solution a built‐in test is proposed as a means to make testing easier. In the proposed method, the testing circuit is built in the IC chip, and the test is executed within the chip to verify whether the function is fault‐free. This paper proposes a new built‐in test for the semiconductor memory by considering its internal operation. In the method, all the data from memory cells on the same word‐line can be treated at the same time, using the built‐in test circuit in the chip. As a result, the length of the test sequence is of the order of N1/2, realizing a high‐speed testing. Another feature is that the tests for the memory‐cell array and the decoder can be executed independently, making it possible to cope with the multiple fault in those circuits. The built‐in test circuit can be implemented in a relatively simple way, and the extra hardware overhead becomes almost negligible with the increase of the memory capacity.
Performance evaluation of asynchronous distributed processing system with limited‐advance processing
Authors: Watanabe Takashi , Nakanishi Hikaru , Sanada Hidehiko , Tezuka Yoshikazu 
Published: July 2007

AbstractThe traditional parallel processing assumes synchronous jobs, for which the processing can easily be planned before execution. On the other hand, the parallel processing is not usually considered for asynchronous jobs of a stochastic nature, such as the queueing network simulation, since the synchronization control of the processors is a problem. The advance processing has already been proposed as a control scheme for the processors in the asynchronous job parallel processing system. In this scheme, each processor performs the processing, thereby ignoring its relation to other processors. Thus the result of the processing is cancelled when a contradiction is found. Unfortunately, the processor may be too advanced in the execution, which results in a large number of cancelling, thus decreasing the processing ability per processor. From such a viewpoint, this paper discusses the limited‐advance processing which is the improved scheme of advance processing. In this scheme, if the processor performs a certain amount of processing, it judges itself as too advanced, and awaits the progress of other processors. It is shown that there exists the optimum advance limit in this scheme, which is a function of the number of processors. The proposed scheme is analyzed to predict the optimum advance limit. In the analysis, the relation between the simulation time and the real time is specified, and the distribution overhead, cancelling time and the number of iterations are discussed. Comparing the result of numerical computation in the analysis and the result of measurement in the prototype system, the validity of the analysis is verified.