bluuebunny/crossref_metadata_2025_split huggingface dataset:
Massive MIMD neural network simulations: The connections dilemma
Authors: Tollenaere Tom , Saraiva J. Miguel , Van Hulle Marc M. 
Published: November 2006

AbstractWe present two strategies for the simulation of massive neural networks on message‐passing MIMD machines. In the first strategy all interconnections between neurons are stored explicitly in interconnection matrices. During simulation, every processor is responsible for certain submatrices of these interconnection matrices. The fact that message‐passing MIMD processors do not provide virtual memory seriously limits the size of the networks that can be simulated, since interconnection matrices require huge amounts of memory.An alternative strategy is not to store the connections explicitly, but generate the interconnections as they are needed. This circumvents memory limitations, but because interconnections need to be generated multiple times, it is inherently slower than the first implementation.This yields the connections dilemma: the choice between fast simulation of small networks as against slower simulation of massive networks.We present, analyze and bench‐mark parallel implementations for both strategies. An efficient connection‐look‐up algorithm, which can be used for any network with static interconnections, ensures that simulation times for the second strategy are only marginally longer than for the first strategy. We show that for our users the connections dilemma is no longer a dilemma: by means of our look‐up algorithm the simulation of massive networks becomes possible; furthermore the time to design and construct a network, prior to simulation, is considerably shorter than it is for the matrix version, and in addition this time is independent of network size.Although we have implemented both strategies on a parallel computer, the algorithms presented here can be used on any machine with memory limitations, such as personal computers.
Comparison of parallel Fortran environments on the AMT DAP510 for a linear algebra application
Authors: Clint M. , Bleakney C. W. , Weston J. S. 
Published: November 2006

AbstractIn the paper three distinct approaches to the implementation of an application in linear algebra on the AMT DAP 510 using the Fortran‐Plus Enhanced language and compiler are investigated. In the first the implementation is tailored to fit a virtual array processor whose edge size corresponds to that of the maximum dimension of matrix used in the application. The second approach is a special case of the first, and corresponds to a situation in which the virtual array processor is constrained to have the same dimensions as the AMT DAP 510. The third approach may be considered to be a hybrid approach. In this case an implementation of the application is constructed which incorporates the most efficient features of the first two. Finally, comparisons of the performances of the three implementations, all of which were compiled using the Fortran‐Plus Enhanced compiler, are presented.
Data management for a class of iterative computations on distributed‐memory MIMD systems
Authors: Cornea‐Hasegan M. C. , Marinescu Dan C. , Zhang Zhongyun 
Published: November 2006

AbstractThe paper discusses data management techniques for mapping a large data space onto the memory hierarchy of a distributed memory MIMD system. Experimental results for structural biology computations using the Molecular Replacement Method are presented.
Object‐based approach to programming distributed systems
Authors: Tanenbaum A. S. , Bal H. E. , Ben Hassen S. , Kaashoek M. Frans 
Published: November 2006

AbstractTwo kinds of parallel computers exist: those with shared memory and those without. The former are difficult to build but easy to program. The latter are easy to build but difficult to program. In this paper we present a hybrid model that combines the best properties of each by simulating a restricted object‐based shared memory on machines that do not share physical memory. In this model, objects can be replicated on multiple machines. An operation that does not change an object can then be done locally, without any network traffic. Update operations can be done using the reliable broadcast protocol described in the paper. We have constructed a prototype system, designed and implemented a new programming language for it, and programmed various applications using it. The model, algorithms, language, applications and performance will be discussed.
Communication system for high‐performance distributed computing
Authors: Hariri S. , Park J.‐B. , Parashar M. , Fox G. C. 
Published: November 2006

AbstractWith the current advances in computer and networking technology coupled with the availability of software tools for parallel and distributed computing, there has been increased interest in high‐performance distributed computing (HPDC). We envision that HPDC environments with supercomputing capabilities will be available in the near future. However, a number of issues have to be resolved before future network‐based applications can fully exploit the potential of the HPDC environment. In the paper we present an architecture for a high‐speed local area network and a communication system that provides HPDC applications with high bandwidth and low latency. We also characterize the message‐passing primitives required in HPDC applications and develop a communication protocol that implements these primitives efficiently.
Using Schooner to support distribution and heterogeneity in the Numerical Propulsion System Simulation project
Authors: Homer P. T. , Schlichting R. D. 
Published: November 2006

AbstractThe Numerical Propulsion System Simulation (NPSS) project has been initiated by NASA to explore the use of computer simulation in the development of new aircraft propulsion technology. With this approach, each engine component is modeled by a separate computational code, with a simulation executive connecting the codes and modeling component interactions. Since each code potentially executes on a different machine in a network, a simulation run is a heterogeneous distributed program in which diverse software and hardware elements are incorporated into a single computation. In the paper a prototype simulation executive that supports this type of programming is described. The two components of this executive are the AVS scientific visualization system and the Schooner heterogeneous remote procedure call (RPC) facility. In addition, the match between Schooner's capabilities and the needs of NPSS is evaluated based on our experience with a collection of test codes. The basic conclusion is that, while Schooner fared well in general, it exhibited certain deficiencies that dictated changes in its design and implementation. This discussion not only documents the evolution of Schooner, but also serves to highlight the practical problems that can be encountered when dealing with heterogeneity and distribution in such applications.
Configuration management in the Nexus distributed operating system
Authors: Tripathi A. , Karnik N. M. , Koneru S. P. , Nock C. , Tewari R. , Day K. , Noonan T. 
Published: November 2006

AbstractThe paper describes the approach taken for configuration management in the Nexus distributed operating system. Nexus uses kernel‐level support for monitoring the failure or termination status of distributed components of an application. Periodic user‐level messages are not required for status monitoring. Group and dependency relationships between such components can be defined by the programmer for the purpose of configuration monitoring and management. An object belonging to a distributed application can be monitored by its host kernel for system‐defined exception conditions. When any of these conditions arise, other objects are notified through signals or messages, as specified by the programmer.
Parallel transport subsystem implementation for high‐performance communication
Authors: Braun T. , Schmidt C. 
Published: November 2006

AbstractRequirements of emerging applications together with rapid changes in networking technology towards gigabit speeds require new adequate transport systems. Integrated designs of transport services, protocol architecture and implementation platforms are required by forthcoming applications in high‐speed network environments. The transport subsystem PATROCLOS (parallel transport subsystem for cel/ based high‐speed networks) is designed with special emphasis on a high degree of inherent parallelism to allow efficient implementations on multiprocessor architectures combined with specialized hardware for very time critical functions. The paper presents the new parallel protocol architecture of PATROCLOS, an appropriate implementation architecture based on transputer networks, and performance evaluation results, which indicate high throughput values.
Pumma: Parallel universal matrix multiplication algorithms on distributed memory concurrent computers
Authors: Choi Jaeyoung , Walker David W. , Dongarra Jack J. 
Published: November 2006

AbstractThe paper describes Parallel Universal Matrix Multiplication Algorithms (PUMMA) on distributed memory concurrent computers. The PUMMA package includes not only the non‐transposed matrix multiplication routine C = A ⋅ B, but also transposed multiplication routines C = AT ⋅ B, C = A ⋅ BT, and C = AT ⋅ BT, for a block cyclic data distribution. The routines perform efficiently for a wide range of processor configurations and block sizes. The PUMMA together provide the same functionality as the Level 3 BLAS routine xGEMM. Details of the parallel implementation of the routines are given, and results are presented for runs on the Intel Touchstone Delta computer.
Partitioning and mapping in embedded multiprocessor architectures in the presence of constraints
Authors: Yalamanchili S. , Winkel L. Te , Perschbacher D. , Shenoy B. 
Published: November 2006

AbstractThe paper focuses on the problem of partitioning and mapping parallel programs onto heterogeneous embedded multiprocessor architectures for real‐time applications. Such applications present unique constraints and challenges. In addition to heterogeneity, the proposed partitioning and mapping algorithms satisfy memory, task throughput, task placement, intertask communication bandwidth, and co‐location constraints. They do so for architectures that utilize circuit‐switched (rather than packet‐switched) interprocessor communication and optimize latency and throughput in addition to load‐balancing. Finally, these mapping algorithms make use of knowledge of the local scheduling discipline to accommodate real‐time scheduling constraints. Our focus is on unstructured parallel programs that fall into one of two classes: (i) the class of computations characteristic of control applications in a real‐time environment where tasks execute concurrently, periodically exchanging information, and (ii) pipelined computation graphs found in sensor data processing applications. The algorithms are implemented in a set of tools that operate with commercial CASE tools at one end, and present an interface to multiprocessor simulators at the other end. Collectively, the algorithms form a significant component of an interactive design environment for the development and mapping of real‐time embedded parallel programs. The paper describes the algorithms, the encapsulating toolset, and presents an example of their application to an existing embedded application—an Autonomous Underwater Vehicle application.
Partitioning tasks between a pair of interconnected heterogeneous processors: A case study
Authors: Lilja David J. 
Published: November 2006

AbstractWith the variety of computer architectures available today, it is often difficult to determine which particular type of architecture will provide the best performance on a given application program. In fact, one type of architecture may be well suited to executing one section of a program while another architecture may be better suited to executing another section of the same program. One potentially promising approach for exploiting the best features of different computer architectures is to partition an application program to simultaneously execute on two or more types of machines interconnected with a high‐speed communication network. A fundamental difficulty with this heterogeneous computing, however, is the problem of determining how to partition the application program across the interconnected machines. The goal of this paper is to show how a programmer or a compiler can use a model of a heterogeneous system to determine the machine on which each subtask should be executed. This technique is illustrated with a simple model that relates the relative performance of two heterogeneous machines to the communication time required to transfer partial results across their interconnection network. Experiments with a Connection Machine CM‐200 demonstrate how to apply this model to partition two different application programs across the sequential front‐end processor and the parallel back‐end array.
P3L: A structured high‐level parallel language, and its structured support
Authors: Bacci Bruno , Danelutto Marco , Orlando Salvatore , Pelagatti Susanna , Vanneschi Marco 
Published: November 2006

AbstractThe paper presents a parallel programming methodology that ensures easy programming, efficiency and portability of programs to different machines belonging to the class of the general‐purpose, distributed‐memory, MIMD architectures. The methodology is based on the definition of a new, high‐level, explicitly parallel language, called P3L, and of a set of static tools that automatically adapt the program features for each target architecture.P3L does not require programmers to specify process activations, the actual parallelism degree, scheduling, or interprocess communications, i.e. all those features that need to be adjusted to harness each specific target machine. Parallelism is, on the other hand, expressed in a structured and qualitative way, by hierarchical composition of a restricted set of language constructs, corresponding to those forms of parallelism that are frequently encountered in parallel applications, and that can be efficiently implemented.The efficient portability of P3L applications is guaranteed by the compiler along with the novel structure of the support. The compiler automatically adapts the program features for each specific architecture, using the costs (in terms of performance) of the low‐level mechanisms exported by the architecture itself. In our methodology, these costs, along with other features of the architecture, are viewed through an abstract machine, whose interface is used by the compiler to produce the final object code.
Distributed implementations of communicating objects
Authors: Jia Weijia , Libert Gaetan 
Published: November 2006

AbstractThe paper presents the design and implementation of a CSP‐based object‐oriented system. The system consists of a specification model, Communicating‐object, and a prototype system, C‐OBJECT, supporting the model. The objects execute in a set of parallel processes called actions. The dynamic communicating objects exchange messages by both data transmissions and function invocations. The C‐OBJECT prototype is constructed in a MIMD architecture (32‐node transputer) with C++ which is composed of two parts: network configuration and a Communicating‐object service subsystem (library) providing various levels of message‐passing primitives. The initial prototype with good performance has shown its availability for C and C++ programming. The integrated system facilitates application software with tools of specification, design and implementation.
The genesis distributed memory benchmarks. Part 2: COMMS1, TRANS1, FFT1 and QCD2 benchmarks on the suprenum and IPSC/860 computers
Authors: Hey A. J. G. , Hockney R. , Getov V. , Wolton I. , Merlin J. , Allwright J. 
Published: November 2006

AbstractThe Genesis benchmark suite has been assembled to evaluate the performance of distributed‐memory MIMD systems. The problems selected all have a scientific origin (mostly from physics or theoretical chemistry), and range from synthetic code fragments designed to measure the basic hardware properties of the computer (especially communication and synchronisation overheads), through commonly used library subroutines, to full application codes. This is the second of a series of papers on the Genesis distributed‐memory benchmarks, which were developed under the European ESPRIT research program. Results are presented for the SUPRENUM and iPSC/860 computers when running the following benchmarks: COMMS1 (communications), TRANS1 (matrix transpose), FFT1 (fast Fourier transform) and QCD2 (conjugate gradient kernel). The theoretical predictions are compared with, or fitted to, the measured results, and then used to predict (with due caution) how the performance might scale for larger problems and more processors than were actually available during the benchmarking.
Accelerated ray tracing using an nCUBE2 multicomputer
Authors: Grimstead I. J. , Hurley S. 
Published: November 2006

AbstractAcceleration techniques for rendering a dynamic sequence of frames (animations) and static scenes using ray tracing are presented. The first technique discusses temporal acceleration for dynamic scenes which takes advantage of ray coherence, while the second technique discusses acceleration for complex static scenes based on parallelism. Several practical aspects of the parallel implementation on an nCUBE2 hypercube computer are included.
The dynamic behaviour of parallel programs under process migration
Authors: Candlin Rosemary , Phillips Joseph 
Published: November 2006

AbstractWe have studied the interaction between process‐based parallel programs whose characteristics change in various ways at run time and the operation of load‐balancing, as implemented by process migration. In order to do this, we propose a simple performance model, whose parameters represent features of the program's execution such as the frequency and regularity of the changes in computational characteristics, and conduct a series of experiments involving simulated executions of synthetic programs with controlled parameter values. From these we can deduce the relative importance of the parameters from the point of view of their influence on performance.We can explain our observations in terms of a simplified stochastic model that relates local changes in load to global behaviour. We show that the dynamics of load‐balancing can be represented approximately by a first‐order difference equation, and that the distributed process migration algorithm is consistent with a behaviour on the global scale which can be regarded as that of a traditional feedback controller.
Dynamic scheduling techniques for heterogeneous computing systems
Authors: Hamidzadeh Babak , Atif Yacine , Lilja David J. 
Published: November 2006

AbstractThere has been a recent increase of interest in heterogeneous computing systems, due partly to the fact that a single parallel architecture may not be adequate for exploiting all of a program's available parallelism. In some cases, heterogeneous systems have been shown to produce higher performance for lower cost than a single large machine. However, there has been only limited work on developing techniques and frameworks for partitioning and scheduling applications across the components of a heterogeneous system. In this paper we propose a general model for describing and evaluating heterogeneous systems that considers the degree of uniformity in the processing elements and the communication channels as a measure of the heterogeneity in the system. We also propose a class of dynamic scheduling algorithms for a heterogeneous computing system interconnected with an arbitrary communication network. These algorithms execute a novel optimization technique to dynamically compute schedules based on the potentially non‐uniform computation and communication costs on the processors of a heterogeneous system. A unique aspect of these algorithms is that they easily adapt to different task granularities, to dynamically varying processor and system loads, and to systems with varying degrees of heterogeneity. Our simulations are designed to facilitate the evaluation of different scheduling algorithms under varying degrees of heterogeneity. The results show improved performance for our algorithms compared to the performance resulting from existing scheduling techniques.
An adaptive algorithm for resolving processor thrashing in load distribution
Authors: Lu Chin , Lau Sau‐Ming 
Published: November 2006

AbstractProcessor thrashing in load distribution refers to the situation when a number of nodes try to negotiate with the same target node simultaneously. The performance of dynamic load‐balancing algorithms can be degraded because processor thrashing can lead to receiver node overdrafting, thus causing congestion at a receiver node and reduction of workload distribution. In the paper we present an adaptive algorithm for resolving processor thrashing in load distribution. The algorithm is based on the integration of three components: (1) a batch task assignment policy, which allows a number of tasks to be transferred as a single batch from a sender to a receiver; (2) a negotiation protocol to obtain mutual agreement between a sender and a receiver on the batch size; and (3) an adaptive symmetrically‐initiated location policy to select a potential transfer partner. Simulations reveal that our algorithm provides a significant performance improvement at high system loads because the algorithm can avoid processor thrashing so that CPU capacity is more fully utilized.
A load index and a transfer policy for global scheduling tasks with deadlines
Authors: Shivaratri Niranjan G. , Singhal Mukesh , Singhal Mukesh 
Published: November 2006

AbstractTwo important components of a global scheduling algorithm are its transfer policy and its location policy. While the transfer policy determines whether a task should be transferred, the location policy determines where it should be transferred. Many global scheduling algorithms have been proposed to schedule tasks with deadline constraints. These algorithms try to transfer tasks only when task's deadlines cannot be met locally or local load is high (i.e. they take only corrective measures). However, a scheduling algorithm that takes preventive measures in addition to corrective measures can reduce potential deadline misses substantially. In this paper we present: (a) a load index which characterizes the system state and is more conducive to preventive and corrective measures; (b) a new transfer policy which takes preventive measures by doing anticipatory task transfers in addition to corrective measures. The proposed transfer policy adapts better to the workload by availing of the accurate system state made available by the proposed load index. An algorithm making use of the new transfer policy and the new load index is shown to reduce the number of deadline misses significantly when compared to algorithms taking only corrective measures.