bluuebunny/crossref_metadata_2025_split huggingface dataset:
Meditation, Compassionate Love, and Mental Health in Later Life
Authors: Lekhak Nirmala , Bhatta Tirth , Kahana Eva , Fernandes Cecilia , Snyder Joel S. 
Published: February 2024

Purpose:Understanding of the mechanisms by which meditation imparts beneficial effects on later-life mental health is limited. The current study assessed the role of compassionate love in mediating the relationship between meditation and mental health in later life.Method:Using data from a nationwide web-based survey (N= 1,861), we examined the indirect effects of meditation on depressive symptoms and anxiety via compassionate love.Results:Participants who practiced meditation (compared to those who did not) had significantly higher feelings of being loved (b= 0.11,p< 0.05); those who experienced more love had lower depressive symptoms (b= −2.10,p< 0.001) and anxiety (b= −0.99,p< 0.001). Meditation also had significant indirect effects (via compassionate love) on depressive symptoms (b= −0.23,p< 0.05) and anxiety (b= −0.11,p< 0.05).Conclusion:This study underscores the need for contemplative interventions that foster compassionate love to improve mental health in later life. [Journal of Gerontological Nursing, 50(3), 40–50.]
Solder Flux Evolution for Heterogeneous Integration
Authors: Griffith Evan 
Published: February 2024

Advanced packaging techniques continue to evolve within the semiconductor industry. Within advanced packaging, heterogeneous integration has become a solution for those wishing to integrate distinct and complex dies into smaller packages. Many application trends are emerging to meet the challenges of heterogeneous integration which are causing the assembly process to become more intricate, with these trends requiring soldering material technology, especially that of solder flux, to be up to date and cutting-edge. In this paper, three assembly processes that necessitate advanced solder flux will be discussed: flip-chip assembly, BGA ball-attach assembly, and assemblies which have advanced to necessitate fluxless component attach. First, flip-chip assembly methods will be discussed and how different assembly technologies, such as standard mass reflow, thermocompression bonding (TCB), and laser assisted bonding (LAB), require differently formulated fluxes. This paper will then discuss the ball grid array assembly process, first outlining common process steps which negatively affect the solderability of ball-grid array pads, such as flip-chip reflow and molding compound applications, then discuss advancements in ball-attach fluxes which help eliminate these extra process steps, or ‘prefluxing’ steps. Finally, this paper will then discuss assembly trends which have led to fluxless component attach, and will discuss materials designed for fluxless processes, such as formic acid reflow, and how these fluxless processes tie into flip-chip assembly.
Back End Commonality for Advanced Packaging: Large Form Factor Project
Authors: Wheeler Kirk , Anderson Steve , Harsha Chetan , Pharamond Antoine , Ross Neil , Ray Urmi 
Published: February 2024

Address key gaps for advanced packages through complex assembly processes and provides flexibility for handling different body size package • Enable new products and product segments not limited by current JEDEC body sized •Demonstrates the cost effectiveness of leveraging tool commonality • Increase Backend operational efficiency • Define large form factor product handling media that allows for flexibility and higher density • Ability to maximize footprint: # of packages in held in the “handling media” • Minimize tooling changeover times • Provide the same “outer design” for many different package sizes/types, thereby minimizing NRE and Increased Tool Flexibility
Scaling Interconnect Densities Meeting the Growing Demand for Chiplet Integration
Authors: Davis Robin , Olson Tim 
Published: February 2024

With the increasing demand for heterogenous chiplet integration, the demand for high density chip to chip interconnects grows equivalently. In 2022 there were two significant announcements on breakthroughs in chip integration. At the highest end is AMD’s v-cache, which utilizes hybrid bonding to make connections between cache and processor. Also introduced to industry, was Apple’s M1-Ultra processor which achieves advanced flip-chip pitch at 25µm x 35µm. Through teardowns it is apparent that the M1-Ultra is made up of two chips first embedded processors, a flip-chip bridge, and molded fanout technology. These silicon-based solutions are complex and costly, but they demonstrate the industry’s strong demand for high density interconnects. This paper outlines an alternate approach to achieving high density die-to-die interconnects through purely organic wafer or panel level packaging (PLP) that can meet or exceed the density provided by a silicon bridge. Deca Technologies’ Gen 2 M-Series™ fan-out with Adaptive Pattering® provides 20µm pitch capability with 2µm line and space widths. This interconnect density can match or exceed that offered by a silicon bridge, while significantly reducing the cost and yield risk. A specific 10 die test vehicle build will be presented that demonstrates this capability. This 20µm pitch is only the starting point as the technology will continue to scale. Through the new, MDX™ technology, capture pads are eliminated from all metal layers allowing unprecedented routing density increases on organic fan-out structures in combination with finer device interface pitch. While the details of this technology are still proprietary, a high-level overview will be provided.
Chiplets Integration: Simplifying the Landscape
Authors: Kelly Mike , Hiner Dave , Scott Geroge 
Published: February 2024

Heterogenous integration and the use of chiplets are the logical outcome of several factors effecting the IC industry’s drive towards higher and higher performance, and to accomplish this at minimum total product cost. This drive to heterogenous solutions has created a new development cycle in the IC Packaging industry to get ready for these product needs. The choice of which package to use for chiplet-based designs is driven by several important factors, most importantly, the type of die-to-die interface that is being used. This bus largely defines the physical structure such as line and space requirements, and the electrical performance which influences the type of materials used as dielectrics and design practices which must be enabled to permit a successfully product design. There are a growing number of package configurations to accommodate these chiplet integrations, but in vast majority of real-world applications, there are only a handful of package types, with clear rationale guiding package selection. This paper will examine the different approaches for heterogeneous packaging and try to simplify the IC packaging selection process, and provide guidance for real-world implimenations. Although there are many different trade names in the industry there are only a few basic categories, and once this is understood the package selection should seem much less daunting.
Micr -Transfer Printing for Efficient 3DHI of 100-300mm Wafers and Glass Panels
Authors: Conner Bob , Batchelor Bill , Gomez David 
Published: February 2024

This paper presents an analysis of using micro-transfer printing (MTP) for three-dimensional heterogeneous integration (3DHI) of diverse components made using 100mm, 200mm and 300mm wafers with large area glass substrates. Techniques for achieving high throughput and high wafer and substrate utilization, despite their size mis-matches, are described in detail along with MTP’s pros and cons versus alternative wafer-to-wafer and die-to-wafer 3DHI technologies. MTP, a massively parallel pick-and-place process, efficiently transfers large arrays of ultra-thin (<10 micron), small, diverse components (“x-chips”) from one or more source wafers to destination substrates. MTP enables disruptive 3DHI of compound semiconductors, including GaN, GaAs, InP, SiGe and emerging materials, silicon and passive components for wireless and optical communications, power management, sensor, photonics and other analog / mixed signal applications. Since the x-chips are ultra-thin and active side up, standard copper redistribution layer (RDL) technology may be readily used to interconnect the x-chips and destination die, resulting in very short path lengths and, hence, minimum parasitics. ASM AMICRA and X Display Company supply R&D and production MTP manufacturing systems. More than twenty MTP systems are installed worldwide at X-FAB, Micross Components, Tyndall National Institute, Teledyne, the Naval Research Laboratory, the University of Illinois Urbana Champaign, the University of Ghent / imec, UPVfab and undisclosed leading manufacturers.
RF Packaging and Design for Development of High Performance 5G mmWave Modules
Authors: Ndip Ivan , Le Thi Huyen , Murugesan Kavin , Maaß Uwe , Kaiser Michael , Schneider-Ramelow Martin 
Published: February 2024

5G sub-6GHz networks have already been deployed in many regions around the world. However, the deployment of 5G mmWave networks is yet to meet expectations. This is partly because of the challenges associated with hardware development of 5G mmWave systems. One example of such a challenge is to overcome the severe degradation of signal-to-noise (SNR) ratio due to intra- and inter-system signal losses at mmWave frequencies. This deteriorates the signal quality, limits transmission distances and may lead to unreliable mobile communication. In this work, we present RF packaging platforms and technologies as well as an approach for scalability of 5G RF frontend integrated circuits (ICs) and antennas which overcome intra- and inter-system losses. This leads to the development of high-performance and scalable 5G MIMO (multiple input multiple output) modules for reliable mobile communication at mmWave frequencies. The platforms provide very short and low-loss signal paths with few geometrical discontinuities between the frontend ICs and antennas. This leads to significant reduction in signal reflections and attenuation, thus improving the matching efficiency of the antennas and the equivalent isotropic radiated power (EIRP) of the entire system. The platforms also enable antennas to be integrated on layers directly above the ICs, and thereby ensures scalability of the ICs and antennas in both lateral dimensions for 5G mmWave massive MIMO. To demonstrate the functionality of our proposed packaging platforms, technologies and antennas, we performed in-depth RF designs, measurements and characterization of packaging materials, technologies and platforms as well as antennas for 5G mmWave applications.
Hermetic Package for MEMS Mirror
Authors: Rotta Davide , Chiesa Marco , Serrano Aina , Del Sarto Marco , Maggi Luca , Maierna Amedeo , Bogoni Antonella 
Published: February 2024

Applications for optical scanning and 3D sensing, mostly related to the consumer electronics and automotive markets, are becoming more and more demanding in terms of performance and power consumption. When using a MEMS based Laser Beam Scanning, enclosing the mirrors into a hermetic package helps to address these requirements. Two MEMS mirrors with different sizes and performance have been selected for this study. A unique package, suitable for both mirrors, has been properly designed. The package is based on a ceramic chip carrier with a soldering ring on the top surface. A metal cap with a sintered optical window is attached to the ceramic substrate. The optical window is tilted with respect to the mirror to avoid spurious reflections. The MEMS mirrors have been integrated onto the ceramic substrate by standard die attach and wirebonding technologies. Hermetic sealing has been developed under nitrogen atmosphere to guarantee the MEMS stable operation against humidity and contaminants. Flux-less SnAgCu solder preforms have been selected as sealing material. The solder reflow profile has been optimized in order to obtain a uniform solder fillet at the sealing region while minimizing the thermal stress to the mirrors. The hermeticity of the assemblies has been proved by fine and gross leak testing. The packages show a leak rate < 1.5 E-8 atm cc/s and pass the fine and gross leak test, defined accordingly to MIL-STD-883 TM 1014.18.
Novel Low Df Thermosetting Film and Photo Imageable Film
Authors: Koh Meiten 
Published: February 2024

There are various demands for interlayer insulation film. One typical demand is to interlayer insulation film with low Df for substrate to decrease transmission loss, and another typical demand is to low warpage, fine via type photo imageable interlayer insulation film for RDL. We have developed two types of the novel interlayer insulation films, one was low Dk/Df thermosetting film and another was fine via type photo imageable film. Epoxy based interlayer insulation film, which was mainly used for substrate, showed high transmission loss at mm wavelength due to its high Df, especially at high temperature. But it showed good processability and reliability due to its thermosetting property. PPE was known as low Df resin, but it had poor processability and reliability due to its thermoplastic property. Thus we have synthesized the novel curable PPE resin, and by using the resin, we have developed the novel thermosetting PPE based interlayer insulation film for substrate. It showed far lower Df and far lower transmission loss compared to the low Df type epoxy based interlayer insulation film. We have developed the novel photo imageable interlayer insulation film for RDL. Ordinally photo imageable PI solution was used for RDL, but it showed high CTE, which caused warpage and reliability issue, high surface roughness, which required post processing process, and high curing temperature. We have used the novel epoxy acrylate and developed the novel photo imageable film, which showed low CTE, low surface roughness and low curing temperature.
Driving Adoption of Advanced IC Packaging in Automotive Applications
Authors: Ziadeh Bassam 
Published: February 2024

For years automotive semiconductors, have been governed by small, low power Integrated Circuits (ICs) purpose built for specific functions. These Microcontroller Units (MCUs), deployed on the edge of the compute topology are typically low-power, low-performance parts. Built on legacy nodes (130nm+) on well-established packaging technology (often wirebond die on QFN-style packages), they demonstrated incremental improvements from a silicon and packaging perspective. With the adoption of software defined vehicles (SDV), the evolution of advanced driver assist systems (ADAS), and feature rich in-vehicle infotainment (IVI), the per vehicle compute power has grown exponentially per vehicle, colloquially, known as “data centers on wheels”. With this growth has come the need to adopt newer packaging techniques to improve system latency, bandwidth, compute power, and IP integration and reducing system footprint via 3D stacking – all fabricated on leading edge nodes. Advanced packaging has seen tremendous growth and adoption in the data center and client ecosystems – the next hurdle is addressing the safety and reliability focused requirements of automotives; extended useful lifespan of 10yrs+, and weathering harsher environmental conditions of thermal extremes, vibration, and EMC, and mixed IP integration. This talk will address the areas of focus for adopting heterogenous integration and advanced automotive packaging for automotives such as, qualification and formulation of materials to minimize traditional packaging yield concerns, introduction of new thermal interface materials aligned with new liquid cooled ECUs and testing to ensure zero defects across chiplets and memory; with broader test coverage and the adoption of Known Good Die (KGD). Additionally, the talk will cover the importance of driving industry standardization regarding die-to-die communication protocols, form factors, power delivery, system integration, and qualifying/enveloping new failure modes from the current baseline AEC-Q100 requirements brought on by various 2.5D and 3D packaging.
Advanced Glass Carriers for Buildup Structure Warp Control and Wafer Ultra-thinning
Authors: Zhang Jay , Teng Andy , Yu Christina , Brueckner Julia 
Published: February 2024

Tailorable CTE of glass carriers enables effective warp control of buildup structures such as fan-Out wafer level package and multi-layer laminates. Corning’s Advanced Packaging Carrier (APC) product family covers CTE from 4.9-12.6 ppm/C with fine granularity down to 0.2 ppm/C, and other glass types go down in CTE all the way to 0 ppm/C. We illustrate the benefits of having such CTE capabilities using several use cases. Carrier supported wafer thinning down to single digit microns is another emerging need. In addition to CTE matching, such ultra-thinning requires the carrier and the associated temporary bonding method to deliver very low total thickness variation (TTV), typically a small fraction of the final wafer thickness. We will introduce Corning’s recently announced ultra-low-TTV (ULTTV) glass carriers as well as near-zero-TTV temporary bonding methods that enable ultra-thinning of wafers of various types.
Warpage and Reliability Study of Large Size XDFOI(TM) FO-MCM fcBGA
Authors: Yang Danfeng , Islam Nokibul , Xu Allen , Xu Coco , Lin Yaojian 
Published: February 2024

XDFOI(TM) (x-Dimensional Fan-Out Integration) is a heterogeneous integration technology platform of JCET Group, which includes multiple advanced 2D/2.5D/3D chiplet and SiP (System-in-Package) integration solutions. Since the semiconductor Si node advances beyond 14 nm, the soaring cost of design and manufacture has shifted attention to advanced heterogeneous integration strategies, such as System-on-Chip (SoC) and SiP. SoC benefits from the shorter interconnections, while SiP has the advantages on cost, sourcing, cycle time and reliability. As a key member of XDFOI(TM), FO multi-chip-module (FO-MCM) and its further integration with fcBGA, is a viable and flexible technique to meet the challenge of exponentially generated date and information of our society. Meanwhile, the size of XDFOI(TM) chips and related fcBGA packages gets larger and larger, corresponding warpage and reliability issues become more and more complicated and important. In this paper, large size 2.5D FO-MCM chips (L * W ≥ 900 mm2), which were fabricated by chip-first process as S-in-1 FO types (S=2/3/4: the quantity of Si chiplets) with different Si thickness combination, together with raw Si chip (L * W) as 1-in-1 control type, were assembled with large size fcBGA (≥ 65x65 mm2) to study the impact of Si chiplet split and Si thickness on warpage. Furthermore, reliability (TC 500/1000 cycles, uHAST 96/192 hrs, and HTSL 500/1000 hrs) of these large size XDFOI(TM) fcBGA packages were also proceeded to investigate the corresponding warpage/reliability relationship.
OSAT Production Testing of 5G, Power Discretes & 3D packaged ICs
Authors: Pancholi Vineet 
Published: February 2024

The presentation will be segmented into three. OSAT production testing challenges of three vital product families that are important to our semiconductor industry will be showcased in each segment. The first segment will describe the products and impacts to RF production testing of both Sub-8GHz carrier frequency range and the mmWave frequency range of operation. The second segment will explore emerging MOSFET technologies that enable faster switching rates and higher voltage and current topologies. The third segment will describe the challenges of production test content for 3D-stacked advanced packages. 5G RF has enabled mmWave carrier frequencies, small cell deployment, massive MIMO (Multiple In, Multiple Out), beam forming, and full duplex wireless transmission and reception operations. These features require new production test methodologies. There is an astronomical rise in battery powered applications like toys, consumer goods, automotive and trains. Power path turn on/off with MOSFETs is in the critical path. The technology has advanced from the traditional Si to GaN and SiC based products that have a smaller size and allow for higher application efficiencies. Test specifications and limits are improving and production testing methods are evolving to account for these changes. Advanced packaging has enabled the path to integrate chiplets within a single package. Heterogeneous Integration (HI) is a powerful design innovation that allows tighter integration and, in some cases, improved signal and power performance at the system level. Production test methodologies are being streamlined to make test a competitive advantage for our customers.
IMAPS 2022 Conference Qorvo SHIP-RF
Authors: Jones Ted 
Published: February 2024

Presentation will describe the Department of Defense (DoD) State of the Art (SOTA) Heterogeneous Integrated Packaging (SHIP) RF program which is developing and validating a sustainable and scalable model for access to SOTA microelectronics RF packaging of customized DoD microelectronic devices produced using a standard commercial production flow. RF package platforms developed are progressing from least complex to more complex throughout the course of the program. The SHIP-RF roadmap and status will be presented and will include Qorvo’s SOTA capabilities that are being incrementally developed and deployed via the SHIP-RF Design Center 1. (DC) and the Assembly and Test Center (ATC).
Photo-Imageable Dielectrics Enabling Structured MEMS and 2.5D / 3D Bonding Systems
Authors: Danza David , Hayes Colin , Wang Kevin , Prokopowicz Greg , Berry Paul , Kondo Masaki , Gallagher Michael 
Published: February 2024

DuPont has developed a new Photo-Imageable Dielectric (PID) to complement its existing permanent bonding materials. The CYCLOTENEâ?¢ family of dielectric materials are well known for use as a permanent dielectric and have seen significant use in commercial applications including BSI CMOS image sensors, integrated passive devices and as an optical bonding adhesive. For new applications, there is a desire to have a thermal stable material that can be patterned to eliminate the material from the metal joining region or from the light path. We will demonstrate in this paper that the solvent developed PID as well as our existing aqueous developable PID are both capable of wafer to wafer bonding after photo imaging and development. In addition to bonding using a commercial wafer to wafer bonding tool, we have shown that wafer to wafer bonding is achievable using a two-stage vacuum laminator. Optimization of the curing process will be discussed to prevent any separation or reflow of the PID as well as achieving the maximum adhesion energy after full cure. Finally, we will show the use of the negative tone PID as a solder collar or polymer dam to enable high density flip chip bonding using 15?m Sn/Ag capped copper pillars with a 1:1.5 pitch to a and 18?m polymer openings with a 1:1.08 pitch in 10mm x 10mm dies as well as outline the process we will use to extend this approach to Cu-Cu hybrid bonding.