bluuebunny/crossref_metadata_2025_split huggingface dataset:
A distributed UNIX system based on a virtual circuit switch
Authors: Luderer G. W.R. , Che H. , Haggerty J. P. , Kirslis P. A. , Marshall W. T. 
Published: November 2005

The popular UNIX
TM
operating system provides time-sharing service on a single computer. This paper reports on the design and implementation of a distributed UNIX system. The new operating system consists of two components: the S-UNIX subsystem provides a complete UNIX process environment enhanced by access to remote files; the F-UNIX subsystem is specialized to offer remote file service. A system can be configured out of many computers which operate either under the S-UNIX or the F-UNIX operating subsystem. The file servers together present the view of a single global file system. A single-service view is presented to any user terminal connected to one of the S-UNIX subsystems.

Computers communicate with each other through a high-bandwidth virtual circuit switch. Small front-end processors handle the data and control protocol for error and flow-controlled virtual circuits. Terminals may be connected directly to the computers or through the switch.
Operational since early 1980, the system has served as a vehicle to explore virtual circuit switching as the basis for distributed system design. The performance of the communication software has been a focus of our work. Performance measurement results are presented for user process level and operating system driver level data transfer rates, message exchange times, and system capacity benchmarks. The architecture offers reliability and modularly growable configurations. The communication service offered can serve as the foundation for different distributed architectures.
BRUWIN
Authors: Meyrowitz Norman , Moser Margaret 
Published: November 2005

With only one process viewable and operational at any moment, the standard terminal forces the user to continually switch between contexts. Yet this is unnatural and counter-intuitive to the normal working environment of a desk where the worker is able to view and base subsequent actions on multiple pieces of information.
The window manager is an emerging computing paradigm which allows the user to create multiple terminals on the same viewing surface and to display and act upon these simultaneous processes without loss of context. Though several research efforts in the past decade have introduced window managers, they have been based on the design or major overhaul of a language or operating system; the window manager becomes a focus of—rather than a tool of—the system. While many of the existing implementations provide wide functionality, most implementations and their associated designs are not readily available for common use; extensibility is minimal.
This paper describes the design and implementation of BRUWIN, the BRown University WINdow manager, stressing how such a design can be adapted to a variety of computer systems and output devices, ranging from alphanumeric terminals to high-resolution raster graphics displays. The paper first gives a brief overview of the general window manager paradigm and existing examples. Next we present an explanation of the user-level functions we have chosen to include in our general design. We then describe the structure and design of a window manager, outlining the five important parts in detail. Finally, we describe our current implementation and provide a sample session to highlight important features.
An analysis of the performance of the page fault frequency (PFF) replacement algorithm.
Authors: Sadeh E. 
Published: November 2005

Most of the replacement algorithms devised and implemented largely depend on program behavior, in other words, to optimally select the parameters of these algorithms program behavior or at least a probability model of it should be known. The page fault frequency (PFF) algorithm adapts to dynamic changes in program behavior during execution. Therefore its performance is expected to be less dependent on prior knowledge of the program behavior during execution. Therefore its performance is expected to be less dependent on prior knowledge of the program behavior and input data.
The PFF algorithm uses the measured page fault frequency (by actually monitoring the inter-page fault interval) as the basic parameter for memory allocation decision process.
In order to analyze the performance of the PFF algorithm, a mathematical model was developed. The resultant random process is the memory space allocation for a program as a function of the processor time (virtual time). This random process can be analyzed using the method of imbedded Markov chains. The parameter obtained from this analysis are the distributions of the memory allocation during processing interval and during page waiting intervals, the average page fault rate and the expected space time product accumulated by the program.
The input parameters for the model were obtained from address traces of two programs. The results of the model were validated by simulation.
Architecture of a real time operating system
Authors: Pruitt J. L. , Case W. W. 
Published: November 2005

Architecture is receiving increasing recognition as a major design factor for operating systems development which contributes to the clarity, and modifiability of the completed system. The MOSS Operating System uses an architecture based on hierarchical levels of system functions overlayed dynamically by asynchronous cooperating processes carrying out the system activities.
Since efficient operation in a real time environment requires that the number of processes and process switches be kept to a minimum, the MOSS system uses processes only where a truly asynchronous activity is identified. The layers of the MOSS Operating System do not represent a hierarchical structure of virtual machine processes, but rather a hierarchy of functions used to create the processes.
This paper describes the layering concepts and process concepts defining the system architecture. It also presents an overview of the specific functions and processes of the MOSS Operating System.
The enforcement of security policies for computation
Authors: Jones Anita K. , Lipton Richard J. 
Published: November 2005

Security policies define who may use what information in a computer system. Protection mechanisms are built into a system to enforce security policies. In most systems, however, it is quite unclear what policies a mechanism can or does enforce.
This paper defines security policies and protection mechanisms precisely and bridges the gap between them with the concept of soundness: whether a protection mechanism enforces a policy. Different sound protection mechanisms for the same policy can then be compared. We also show that the “union” of mechanisms for the same program produces a more “complete” mechanism. Although a “maximal” mechanism exists, it cannot necessarily be constructed.
µ3L
Authors: Castan M. , Organick E. I. 
Published: November 2005

To eliminate the conceptual distance between the hardware instruction set and the user interface, some architects advocate High Level Language (HLL) machines. To obtain simple, fast and cheap machines, some architects advocate Reduced Instruction Set Computer (RISC) machines. This paper reconciles both views and presents an architecture which has both an HLL user interface and a RISC hardware. Each instance of this architecture is a module of an HLL multiprocessor system.
Functional programming languages offer a bridge between mathematical models of computation and multiprocessor system environments. We choose the language AFPL (A Functional Programming Language) as the HLL user interface. AFPL's direct execution model, based on a tree structured internal representation, takes advantage of the parallelism inherent in programs by decomposing them on the fly into tasks which can be performed concurrently.
Duplication of packets and their detection in X.25 communication protocols
Authors: Jain Bijendra N. 
Published: November 2005

In the context of X.25 communication protocols, this paper is concerned with the process of duplication of packets at the frame level, and with their detection at the packet level. With suitable constraints involving
(i) the window sizes used at both the frame and packet levels to flow control, and
(ii) the numbering scheme used to number User Data packets,
it is possible to detect and discard all duplicate copies thereof. Further, it is argued that duplication of 'messages' by a particular layer be detected at the level where these messages are generated and interpreted. Deferring this detection to higher levels is unnecessary and more difficult.
A heterogeneous multiprocessor design and the distributed scheduling of its task group workload
Authors: Miller Leslie Jill 
Published: November 2005

A multiprocessor architecture is proposed which is based on the Multics concept of having all on-line information processor-addressible. All memory management is done by an intelligent paged virtual memory system, and each processor deals only with those segments relevant to its single executing program. The processors are chosen to have different implementations of a single system-wide instruction set and the problem is to effectively schedule different categories of programs, called task groups, on the dissimilar processors.
Average weighted instruction times for each task group on every processor are defined as task/processor suitability measures, and typical values are given for different groups of programs running on IBM 370 models. Through the use of linear programming techniques, an optimal schedule for any such multiprocessor is then defined for the static case where task group loads and task/processor suitability values are known in advance. A priority-based task management scheduling algorithm is then defined which uses the optimal schedule of the formal model as a parameter, and its performance is simulated.
A dual processor VAX 11/780
Authors: Goble George H. , Marsh Michael H. 
Published: November 2005

This paper describes the design of a dual processor VAX 11/780 built at the Purdue University Electrical Engineering School. It covers the conversion of a standard single processor VAX 11/780 into a dual processor system. A detailed description of hardware modifications performed and a parts list are included.
The dual processor VAX is currently running a modified version of the UNIX (Fourth Berkeley Distribution) operating system. Because of licensing restrictions, operating system modifications will only be covered in general. Finally some performance evaluation will be discussed along with the problems encountered.
Framework for a taxonomy of fault-tolerance attributes in computer systems
Authors: Avižienis Algirdas 
Published: November 2005

A conceptual framework is presented that relates various aspects of fault-tolerance in the context of system structure and architecture. Such a framework is an essential first step for the construction of a taxonomy of fault-tolerance.
A design methodology for fault-tolerant systems is used as the means to identify and classify the major aspects of fault-tolerance: system pathology, fault detection and recovery algorithms, and methods of modeling and evaluation.
A computing system is described in terms of four universes of observation and interpretation, ordered in the following sequence: physical, logic, information, and interface, or user's. The description is used to present a classification of faults, i.e., the causes of undesired behavior of computing systems.
Caddie an interactive design environment
Authors: Pehrson Björn , Parrow Joachim 
Published: November 2005

The paper reports on a design methodology and an experimental CAD system, named Caddie, based on this methodology. Caddie supports specification, analysis and synthesis of objects that can be described as communicating processes, e.g. electronic circuits, sequential networks, digital processors and programs. Basic ideas behind Caddie are:
- top-down hierarchical design. Specifications are broken down hierarchically by stepwise refinement
- integrated design. Design objects from different design phases are described in the same formalism. This technique allows universal design operations.
- formal systems with varying descriptive and decisive powers are exploited
- incremental design. Parts can be modified separately without effect on other parts.
- interactive design, i.e. the designer can interact with the design tools in real time
Caddie is implemented in Concurrent-lisp, an extension of lisp supporting concurrent programming. Automatic programming tools have been used in the implementation. Caddie consists of
- an interactive parallel programming environment
- automatic design procedures
- a run-time system for execution of design objects (real-time and branching or exhaustive simulation)
Architecture of the PSC-a programmable systolic chip
Authors: Fisher Allan L. , Kung H. T. , Monier Louis M. , Dohi Yasunori 
Published: November 2005

In recent years, many systolic algorithms have been proposed as solutions to computationally demanding problems in signal and image processing and other areas. Such algorithms exploit the regularity and parallelism of problems to achieve high performance and low I/O requirements. Since systolic algorithms generally consist of a few types of simple processors, or systolic cells, connected in a regular pattern, they are less expensive to design and implement than more general machines.
This advantage is offset by the fact that a particular systolic system can generally be used only on a narrow set of problems, and thus design cost cannot be amortized over a large number of units. One way to approach this problem is to provide a programmable systolic chip (PSC), many copies of which can be connected and programmed to implement many systolic algorithms.
The systolic environment, by virtue of its emphasis on continuous, regular flow of data and fairly simple per-cell processing, imposes new design requirements for programmable processors which are quite different from those found in a general-purpose system. This paper describes the CMU PSC, a single-chip microprocessor suitable for use in groups of tens or hundreds for the efficient implementation of a broad variety of systolic arrays. The processor has been fabricated in nMOS, and is undergoing testing.
Performance of shared cache for parallel-pipelined computer systems
Authors: Yeh Phil C. C. , Patel Janak H. , Davidson Edward S. 
Published: November 2005

Shared-cache memory organizations for parallel-pipelined multiple instruction stream processors avoid the cache coherence problem of private caches by sharing single copies of common blocks. A shared cache may have a higher hit ratio, but suffers performance degradation due to access conflicts.
Effective shared cache organizations are proposed which retain the cache coherency advantage and which have very low access conflict even with very high request rates. Analytic expressions for performance based on a Markov model have been found for several important cases. Performance of shared cache organizations and design tradeoffs are discussed.
Very Long Instruction Word architectures and the ELI-512
Authors: Fisher Joseph A. 
Published: November 2005

By compiling ordinary scientific applications programs with a radical technique called trace scheduling, we are generating code for a parallel machine that will run these programs faster than an equivalent sequential machine—we expect 10 to 30 times faster.
Trace scheduling generates code for machines called Very Long Instruction Word architectures. In Very Long Instruction Word machines, many statically scheduled, tightly coupled, fine-grained operations execute in parallel within a single instruction stream. VLIWs are more parallel extensions of several current architectures.
These current architectures have never cracked a fundamental barrier. The speedup they get from parallelism is never more than a factor of 2 to 3. Not that we couldn't build more parallel machines of this type; but until trace scheduling we didn't know how to generate code for them. Trace scheduling finds sufficient parallelism in ordinary code to justify thinking about a highly parallel VLIW.
At Yale we are actually building one. Our machine, the ELI-512, has a horizontal instruction word of over 500 bits and will do 10 to 30 RISC-level operations per cycle [Patterson 82]. ELI stands for Enormously Longword Instructions; 512 is the size of the instruction word we hope to achieve. (The current design has a 1200-bit instruction word.)
Once it became clear that we could actually compile code for a VLIW machine, some new questions appeared, and answers are presented in this paper. How do we put enough tests in each cycle without making the machine too big? How do we put enough memory references in each cycle without making the machine too slow?
Fault diagnosis of bit-slice processor
Authors: Park Young Gil , Cho Jung Wan 
Published: November 2005

This paper proposes a microdiagnostic procedure for efficient fault diagnosis of bit-slice processors that are formed by an array of identical bit-slice processors. A test generation procedure for testing the entire array simultaneously instead of testing single slice, one after another, is presented, which is based on the high functional fault model and restricted multiple slice fault assumption within an array. Fault detection and fault location procedures using the generated test sequence are also presented.
Using these procedures, a test microprogram and diagnostic system for the bit-sliced processor constructed by the array of four Am 2901 bit-slices are developed.
Analysis of Cray-1S architecture
Authors: Srini Vason P. , Asenjo Jorge F. 
Published: November 2005

An analysis of the Cray-1S architecture based on dataflow graphs is presented. The approach consists of representing the components of a Cray-1S system as the nodes of a dataflow graph and the interconnections between the components as the arcs of the dataflow graph. The elapsed time and the resources used in a component are represented by the attributes of the node corresponding to the component. The resulting dataflow graph model is simulated to obtain timing statistics using as input a control stream that represents the instruction and data stream of the real computer system.
The Cray-1S architecture is analyzed by conducting several experiments with the model. It is observed that the architecture is a well balanced one and performance improvements are hard to achieve without major changes. Significant improvement in performance is shown when parallel instruction issue is allowed with multiple CIP/LIPs in the architecture.
Performance measurements on HEP - a pipelined MIMD computer
Authors: Jordan Harry F. 
Published: November 2005

A pipelined implementation of MIMD operation is embodied in the HEP computer. This architectural concept should be carefully evaluated now that such a computer is available commercially. This paper studies the degree of utilization of pipelines in the MIMD environment. A detailed analysis of two extreme cases indicates that pipeline utilization is quite high.
Although no direct comparisons are made with other computers, the low pipeline idle time in this machine indicates that this architectural technique may be more beneficial in an MIMD machine than in either SISD or SIMD machines.
DDDP-a Distributed Data Driven Processor
Authors: Kishi Masasuke , Yasuhara Hiroshi , Kawamura Yasusuke 
Published: November 2005

This paper describes an architecture of a data flow computer named the Distributed Data Driven Processor (DDDP), and presents an experimental system and the results of experiments using several benchmarks. The experimental system has four processing elements connected by a ring bus, and a structured data memory. The main features of our system are that each processing element is provided with a hardware hashing mechanism to implement token coloring, and a ring bus is used to pass tokens concurrently among processing elements. A hardware monitor was used to measure the performance of the experimental system.
The experimental system adopts a low key technology and yet is capable of executing about 0.7 million instructions per second through the benchmarks. This implies that data flow computers can be alternative to the conventional von-Neumann computers if state-of-the-art technologies are adequately introduced.
A data flow processor array system
Authors: Takahashi Naohisa , Amamiya Makoto 
Published: November 2005

This paper presents the architecture of a highly parallel processor array system which executes programs by means of a data driven control mechanism. The data driven control mechanism makes it easy to construct an MIMD (multiple instruction stream and multiple data stream) system, since it unifies inter-processor data transfer and intra-processor execution control. The design philosophy of the data flow processor array system presented in this paper is to achieve high performance by adapting a system structure to operational characteristics of application programs, and also to attain flexibility through executing instructions based on a data driven mechanism.
The operational characteristics of the proposed system are analyzed using a probability model of the system behavior. Comparing the analytical results with the simulation results through an experimental hardware system, the results of the analysis clarify the principal effectiveness of the proposed system. This system can achieve high operation rates and is neither sensitive to inter-processor communication delay nor sensitive to system load imbalance.
Adaptive interpretation as a means of exploiting complex instruction sets
Authors: Norton Richard L. , Abraham Jacob A. 
Published: November 2005

In this paper we concentrate on the effect of instruction set architecture on the performance potential of a computer system. These issues are key in considerations of what instruction set is most appropriate for the support of high level languages on general purpose machines. Two possible approaches are so called complex instruction sets, such as those of the VAX and IAPX 432, and the “reduced” instruction set of the RISC I [2] microcomputer, which is expected to have performance similar to that of a VAX 11-780.
We propose a method of instruction set interpretation that takes advantage of the architectural features of complex instruction sets. These methods have been simulated executing real programs and in the case of the VAX instruction set have resulted in a typical improvement of a factor of two, assuming the same cycle time as the VAX 11-780. The techniques presented exploit the context available in a complex instruction and retain this information for use in subsequent execution of that instruction. Since this context is available only within a single instruction, low level instruction sets cannot benefit from this technique. In this sense the reduced instruction set machines as implemented in RISC are at their architectural limits, while complex instruction sets such as the VAX are far from theirs. For these reasons, complex instruction sets can have a significantly greater performance potential than a RISC instruction set for a given technology.
EMMA-an industrial experience on large multiprocessing architectures
Authors: Stringa Luigi 
Published: November 2005

EMMA (1) is a multiprocessor system designed and built by ELSAG of Genoa, Italy, to solve problems of pattern recognition arising in automatic mail sorting.
The resulting architecture is modular, organizable around several levels, and offers a theoretically unlimited possibility of increasing the processor power.
EMMA runs under a simple distributed operating system, supplying process communication, synchronization primitives and some diagnostic functions that complement analysis and reconfiguration modules residing in the supervisor.