bluuebunny/crossref_metadata_2025_split huggingface dataset:
A Sensitive Fluorescence Anisotropy Method for Point Mutation Detection by Using Core–Shell Fluorescent Nanoparticles and High‐Fidelity DNA Ligase
Authors: Deng Ting , Li Jishan , Jiang Jian‐Hui , Shen Guo‐Li , Yu Ru‐Qin 
Published: July 2007

AbstractThe present study reports a proof‐of‐principle for a sensitive genotyping assay approach that can detect single nucleotide polymorphisms (SNPs) based on fluorescence anisotropy measurements through a core–shell fluorescent nanoparticles assembly and ligase reaction. By incorporating the core–shell fluorescent nanoparticles into fluorescence anisotropy measurements, this assay provided a convenient and sensitive detection assay that enabled straightforward single‐base discrimination without the need of complicated operational steps. The assay was implemented via two steps: first, the hybridization reaction that allowed two nanoparticle‐tagged probes to hybridize with the target DNA strand and the ligase reaction that generated the ligation between perfectly matched probes while no ligation occurred between mismatched ones were implemented synchronously in the same solution. Then, a thermal treatment at a relatively high temperature discriminated the ligation of probes. When the reaction mixture was heated to denature the duplex formed, the fluorescence anisotropy value of the perfect‐match solution does not revert to the initial value, while that of the mismatch again comes back as the assembled fluorescent nanoparticles dispart. The present approach has been demonstrated with the discrimination of a single base mutation in codon 12 of a K‐ras oncogene that is of significant value for colorectal cancers diagnosis, and the wild type and mutant type were successfully scored. Due to its ease of operation and high sensitivity, it was expected that the proposed detection approach might hold great promise in practical clinical diagnosis.
Efficient representation of nonreflecting boundary conditions for the time‐dependent Schrödinger equation in two dimensions
Authors: Jiang Shidong , Greengard Leslie 
Published: July 2007

AbstractWe present a fast algorithm for the evaluation of exact, nonreflecting boundary conditions for the time‐dependent Schrödinger equation in two dimensions on the unit circle. After separation of variables, the exact outgoing condition for each Fourier mode contains a nonlocal term that is a convolution integral in time. The kernel for that convolution is the inverse Laplace transform of the logarithmic derivative of a modified Bessel function, and the convolution integral can be split into two parts: a local part and a history part, which can be treated separately. The local part is easily handled by an appropriate quadrature. For the history part, we show that the convolution kernel can be well approximated by a sum of exponentials. Once such a representation is available, the convolution integrals can be evaluated recursively, reducing the cost from O(N2) work to O(N), where N is the number of time steps. The main technical development lies in the uniform rational approximation of the logarithmic derivative of the modified Bessel function Kν(√is). © 2007 Wiley Periodicals, Inc.
Time domain analysis and design of multirate wave digital filters
Authors: Fahmy M. F. , El‐Wardaney A. , El‐Gayed N. A. , Sobhy M. I. 
Published: July 2007

AbstractA generalized time domain approach is described for the analysis and design of wave digital filters capable of performing sampling rate alterations whether integer or non‐integer. It is based on sequential computation of the filter's system response; then this discrete response is reduced to a rational function form. the proposed approach is characterized by its simplicity as well as its ability to analyse and design multistage, multirate wave digital structures. Illustrative examples are also given.
Switched‐capacitor neural networks for differential optimization
Authors: Cichocki A. , Unbehauen R. 
Published: July 2007

AbstractThe primary goal of this paper is to solve some types of optimization problems whose objective functions and constraints are smooth and continuously differentiable and which are not suited for digital signal processing. the optimization problems are mapped into systems of first‐ and second‐order non‐linear ordinary differential equations and/or systems of difference equations. These systems of equations are simulated by appropriate switched‐capacitor (SC) circuits employing some neural network (neurobiological) principles. New switched‐capacitor architectures for on‐line solving of non‐linear optimization problems are proposed and their properties are investigated. Various circuit structures are investigated to find which are best suited for SC CMOS implementation. the structures developed exhibit a high degree of modularity, and a relatively small number of basic building blocks (computing cells) are required to implement effective and powerful optimization algorithms. Basic mathematical operations, e.g. multiplication, addition and non‐linear scaling transformation, are accomplished employing advanced SC techniques. the validity and performance of the circuit structures developed are illustrated by intensive computer simulations employing TUTSIM and NAP programmes.
Frequency compensation of MOS operational transconductance amplifiers
Authors: Kothapalli Ganesh 
Published: July 2007

AbstractOperational transconductance amplifiers (OTAs) can be compensated by a capacitor placed in the differential‐to‐single‐ended (D/SE) conversion stage. the concept involved in shaping the magnitude and phase‐frequency response of OTAs is to realize a low‐frequency zero such that the effects of double poles prior to unity gain are not felt. It is sometimes possible to meet the objectives of gain and phase margin by providing compensation in more than one stage. the flexibility of the scheme devised is demonstrated by suggesting alternative ways (two‐capacitor compensation) to realize desired root locations. the key point in achieving proper compensation always remains the appropriate choice of capacitor size. Thus the size of the compensation capacitor and placement of the compensation network have been presented here from the context of suitability for implementation in MOS foundries. the compensation schemes discussed are suitable in the second or additional gain stages.
Global properties of continuous piecewise linear vector fields. Part I: Simplest case in ℝ2
Authors: Lum Robert , Chua Leon O. 
Published: July 2007

AbstractAmong non‐linear vector fields, the simplest that can be studied are those which are continuous and piecewise linear. Associated with these types of vector fields are partitions of the state space into a finite number of regions. In each region the vector field is linear. On the boundary between regions it is required that the vector field be continuous from both regions in which it is linear. This presentation is devoted to the analysis in two dimensions of the simplest possible types of continuous piecewise linear vector fields, namely linear vector fields possessing only one boundary condition. As a practical concern the analysis will attempt to ask and answer questions raised about the existence of steady state solutions. Since the local theory of fixed points in a linear vector field is sufficient to determine the stability of fixed points in a piecewise linear vector field, most of the steady state behaviour to be studied will be towards limited cycles. the results will present sufficient conditions for the existence, or non‐existence as the case may be, of limit cycles. Particular attention will be paid to the domain of attraction whenever possible.With these results qualitative statements may be made for piecewise linear models of many physical systems.
Development and design of wave SC filters
Authors: Limperis A. , Haritantis I. 
Published: July 2007

AbstractA direct z‐domain simulation ofLCladder and unit‐element filters by means of wave SC circuits is presented. the development of a wave SC circuit is achieved by interconnecting a limited number of basic SC building blocks. the derived circuits are fully parasitic‐free, symmetric and can be optimally designed for dynamic range maximization and capacitance area minimization. the number of operational amplifiers in the simulated unit‐element filters is essentially low in comparison to earlier presented parasitic‐insensitive wave SC filters and to leap‐frog‐type SC filters. Four‐ and two‐phase multiplexed simulatedLCRfilters can be developed. Bilinear s‐z transformation applies for all the circuits; thus the design is exact and there is no requirement for a high clock frequency. Filters with transmission zeros can be developed. the simulated responses of various types of filters are in good agreement with the theory. Detailed examples of different designs are given.
Efficient performance function interpolation scheme and its application to statistical circuit design
Authors: Biernacki R. M. , Styblinski M. A. 
Published: July 2007

AbstractA concept of ‘maximally’ flat polynomial interpolation of circuit responses (or performance functions) is proposed, developed and exploited. This kind of simple approximation of circuit behaviour proves extremely useful for Monte Carlo statistical yield estimation and optimization. Application of the resulting interpolating polynomials may substantially reduce the number of actual, time‐consuming circuit analyses. Results of all available circuit analyses can be utilized to construct the interpolating polynomials, even if their number is not sufficient for a full unique quadratic or higher‐order interpolation. This is accomplished by selecting the maximally flat interpolation in which all higher‐order‐term coefficients are minimized in the least squares sense. More importantly, a low‐cost updating of the interpolating polynomials is developed in order to accommodate the results of additional circuit simulations as they become available. Examples of this approximation of circuit responses as well as its application to yield estimation and optimization are shown.
An optimal algorithm for rectilinear steiner trees for channels with obstacles
Authors: Chiang Charles , Sarrafzadeh Majid , Wong C. K. 
Published: July 2007

AbstractThe channel rectilinear Steiner tree problem is to construct an optimal rectilinear Steiner tree interconnectingnterminals on the upper shore and the lower shore of a channel without crossing any obstacles inside the channel. However, intersecting boundaries of obstacles is allowed. We present an algorithm that computes an optimal channel rectilinear Steiner tree inO(F1(k)n + F2(k))time, wherekis the number of obstacles inside the channel andF1andF2are exponential functions ofk. For any constantkthe proposed algorithm runs inO(n)time.
The Parametric Yield Enhancement of Integrated Circuits
Authors: Singha Miran , Spence Robert 
Published: July 2007

AbstractEven where a satisfactory circuit design has been achieved, it is often the case that, owing to variations in the manufacturing process, some of the samples of a mass‐produced circuit will violate the specifications on performance so that the manufacturing yield is less than 100%. Such an undesirable effect can, however, be minimized or even eliminated by redesign of the circuit to the extent of changing parameter values while retaining the original circuit topology. For discrete component circuits algorithms are available to achieve such redesign. the special characteristics of integrated circuits, however, are such that these methods are unsuitable as they stand. Two new algorithms for handling the yield enhancement of integrated circuits are described and their successful application is illustrated in the context of two‐stage CMOS op amps.
Transformation of the transfer function variables of the singularn‐dimensional roesser model
Authors: Galkowski Krzysztof 
Published: July 2007

AbstractA singular Roesser model is presented for a non‐causaln‐dimensional (n‐D) system described by ann‐D transfer function with non‐monic denominator. Transformations of the transfer function variables (inversion, multivariable bilinear transformation) have been used to transform the given polynomial to monic form. These transformations are also discussed in state‐space description terms. Additionally, the matrixQwhich relates the coefficients vector of the transformed polynomial to that of the original one is obtained usingn‐way matrix methods.
A method for the investigation of high‐order two‐frequency asynchronous oscillators
Authors: Calandra Enrico F. , Sommariva Antonino M. 
Published: July 2007

AbstractA general method for analysing asynchronous high‐order two‐frequency oscillators is presented. the oscillator model is made up of a GC non‐linear parallel group embedded in a linear lumped time‐invariant network of any order. the approach devised rests on the identification of a pair of narrow‐band impedance operators which permit one to derive first‐approximation steady state and dynamic equations in the phasor domain—as well as stability criteria—in a simple and expressive manner. Previous results from averaging and perturbation treatments on fourth‐order asynchronous oscillators are shown to be obtainable from this theory as particular cases. the sixth‐order oscillator chosen as an application example shows that computational efficiency and accuracy are among the features of the method.
Scheduling Algorithms For Hierarchical Data Control Flow Graphs
Authors: Potkonjak Miodrag , Rabaey Jan M. 
Published: July 2007

AbstractNew algorithms for the allocation, assignment and scheduling of a hierarchical data control flow graph (DCFG) with imposed timing constraints are presented. the hierarchical allocation environment performs a probabilistic search through the design space and converges towards a final solution by iteratively calling and interchanging resource utilisation information with the assignment and scheduling subroutines.The allocation, assignment and scheduling problem is posed in a such a way that the specific costs of all hardware elements are taken into account and simultaneously addressed. the proposed algorithms have novel constructive and rejectionless iterative improvement probabilistic components.The effectiveness of the algorithms is demonstrated with the aid of extensive experimental results. In addition to the standard benchmarks, we have studied a broad class of test examples of a very diverse nature, thus covering the global design space. We also discuss how min‐bound estimations are used to more easily and realistically assess the quality of the allocation, assignment and scheduling algorithms.
A prototype tool for the design‐oriented symbolic analysis of analogue circuits
Authors: Dorel F. , Declercq M. 
Published: July 2007

AbstractNew methodologies for the ‘design‐oriented’ symbolic analysis of analogue circuits are presented. the objective of this analysis is to obtain results that will give more insight into the circuit behaviour. the feature of the presented methods is to allow the network function to be stated in several parts, with an eventual hierarchical dependence on each other, but without loss of interpretability.Several methods are combined. the first one consists of a rule‐based algorithm for network reduction which allows significant simplification before the main analysis is performed. Initially, simple models can be used, since the effects of parasitic elements can be computed afterwards at little CPU expense, thanks to the implementation of the extra element theorem.3the network is divided into blocks by a simple decomposition algorithm. Each block is analysed and the network function is next calculated.To reduce the size of the calculated expressions, the symbolic calculator uses the concept of ‘correction factor’, based on a comparison between the orders of magnitude of the symbolic terms. A PROLOG prototype tool has been written in order to validate these methods. A simple two‐stage amplifier is taken as an example. the solution contains 11 products, to be compared with the 174 that would give a direct topological analysis.
Automation of the ic layout of continuous‐time transconductance‐capacitor filters
Authors: Daasch W. Robert , Wedlake Martine , Schaumann Rolf , Wu Pan 
Published: July 2007

AbstractTo exploit the increased circuit density available in current technologies for continuous‐time (c‐t) systems, it is proposed to extend the range of analogue design automation to the larger c‐t subsystems, specifically filters, commonly found in communications, mass storage devices and other interfaces to real‐world signals. the synthesis is based onLCladder simulation using only transconductances and grounded capacitors (TGC). the method retains many of the characteristics of digital design automation and therefore allows a direct mapping of these techniques. the TGC approach is shown to require a minimum of component types which are ideally suited to integration in MOS, bipolar or GaAs technologies. A simple example for the automation of c‐t filter designs as well as results of CMOS c‐t filters are included to demonstrate the viability of this approach. Related and equally important areas addressed are tuning, compensation for parasitics and scaling.
Computer‐aided manipulation of mason's formula and its applications
Authors: Wang Chi‐Hsu 
Published: July 2007

AbstractThis paper presents a new method to determine the symbolic gain of a linear system via Mason's formula. A combined searching algorithm based on the breadth‐first and depth‐first searching algorithms in a directed graph is devised to find the forward paths and loops in the linear system. Mason's formula is then determined via touching‐non‐touching matches of forward paths and loops in the system. A SPICE‐like system Description language (SDL) is also proposed to describe the linear system so that this new algorithm can be put into execution in a computer language. In comparison with other approaches, this method is more straightforward and needs no complicated matrix operations. the completeness of this new method had already been guaranteed by Mason's original formula. It is also believed that Mason's formula has a new interpretation through this new approach.
On symbolic dynamics of a chaotic second‐order digital filter
Authors: Galias Zbigniew , Ogorzalek Maciej J. 
Published: July 2007

AbstractThis paper presents a contribution to the symbolic analysis of fractal patterns exhibited by a second‐order digital filter with modular adder overflow characteristic. We use symbolic dynamics for the analysis of phenomena encountered in the system. We present several new results concerning the existence of admissible sequences for periodic orbits in the filter. an efficient computational algorithm based on rigorous mathematical results presented in the paper enabled us to calculate sequences with long periods, thus allowing deeper understanding of the underlying mechanisms of complex behaviour encountered in the filter.
On algorithms in the parallel design of logic and layout of circuits with functional blocks
Authors: Szolgay Peter 
Published: July 2007

AbstractSome algorithms in an experimental design methodology for circuits with combinatorial logic blocks are described in which the circuit schematics and the layout of the blocks are designed in parallel. A combinational circuit is represented by three parallel descriptions, namely the functional (truth table), the incidence (connections) and the one‐dimensional layout. to support this design method, new types of algorithms have been developed for the component extraction and interconnection phases, enabling the interactive design activity of ‘twin’ designers. the two‐dimensional layout—which is a fourth representation—of the whole circuit is generated using the one‐dimensional layout model.
Discrete‐time cellular neural networks
Authors: Harrer Hubert , Nossek Josef A. 
Published: July 2007

AbstractA network structure called a discrete‐time cellular neural network is introduced. It is derived from cellular neural networks and feedback threshold networks. the architecture is discussed and its advantages are presented. Convergence is proved for a large class of templates and applications are given for the following image‐processing tasks: linear thresholding, connected component detection, hole filling, concentric contouring, increasing and decreasing objects step by step, searching for objects with minimal distance, and oscillation.
Cellular neural networks: Theory and circuit design
Authors: Nossek Josef A. , Seiler Gerhard , Roska Tamás , Chua Leon O. 
Published: July 2007

AbstractCellular neural networks or CNNs are a novel neural network architecture introduced by Chua and Yang which is very general and flexible, has some important properties desirable for design applications and can be efficiently implemented on custom hardware based on analogue VLSI technology.In this paper an abstract normalized definition of cellular neural networks with arbitrary interconnection topology is given. Instead of stability, the property of convergence is found to be of central importance: large classes of convergent CNNs in practice always asymptotically approach some stable equilibrium where each component of the corresponding output is binary‐valued.A highly efficient CMOS‐compatible CNN circuit architecture is then presented where a basic cell consists of only two fully differential op amps, two capacitors and several MOSFETs, while a variable interconnection weight is realized with only four MOSFETs. Since all these elements are standard components in the current analogue IC technology and since all network functions are implemented directly on the device level, this architecture promises high cell and interconnection densities and extremely high operating speeds.
Design of high‐speed, high‐density CNNS in cmos technology
Authors: Cruz José M. , Chua Leon O. 
Published: July 2007

AbstractAn analogue VLSI circuit architecture for the CMOS implementation of cellular neural networks (CNNs) is presented. It is based exclusively on the use of small capacitors and operational transconductance amplifiers operating in continuous time. Integrated circuit implementations of this architecture are very well suited for processing applications requiring large array size and high speed. We describe a systematic design approach for those circuits and present the design, fabrication and testing of two chips. These chips are used for connected component detection applications and are the first working integrated circuit implementation of a CNN. They contain 2000 transistors and have been fabricated using 2 μm CMOS technology. the density is 32 cells per square millimetre of silicon and the time constant of the processing is of the order of 10−7s. Experimental results of static and dynamic tests are given, including a complete image‐processing example.