bluuebunny/crossref_metadata_2025_split huggingface dataset:
Effect of In as Surfactant on the Growth of AlN/GaN Distributed Bragg Reflectors by Metal Organic Vapor Phase Epitaxy
Authors: Rodak L E , Korakakis D 
Published: February 2009

AbstractNitride based Distributed Bragg Reflectors (DBRs) have several important applications in current nitride based optoelectronic devices. DBRs can be implemented in resonant cavity light emitting diodes (RCLEDs) to improve light extraction and obtain a more directional emission and in vertical cavity surface emitting lasers (VCSELs) to achieve a lower threshold current. Due the large contrast in refractive index, AlN/GaN DRBs are practical for obtaining high reflectivity and wide bandwidth using relatively few periods. Cracking of the samples is typical for AlN/GaN DRBs due to the tensile strain which results from the 2.4% lattice mismatch and to the difference in thermal expansion coefficients. In addition to cracks, v-shaped defects may also arise in the surface due to surface undulation from stored elastic misfit strain or from threading dislocations that result in scattering and diffraction. Several techniques to reduce the number of cracks and defects have been investigated to obtain smooth surface morphology and high reflectivity, e.g. superlattices to reduce the strain or the growth of AlInGaN/GaN DBRs that offer less lattice mismatch but also lower refractive index contrast. In this work, results of the use of Indium (In) as a surfactant in Metal Organic Vapor Phase Epitaxy (MOVPE) will be discussed. This study addresses AlN/GaN DBR structures designed for peak reflectivity around 465 nm. During the AlN layers’ growth, trimethylindium was introduced to the system and resulted in a reduction of surface cracks. Results of growths at In flow rates are reported and discussed.
Detailed Investigation of GaN Metal-Insulator-Semiconductor Structures by Capacitance-voltage and Deep Level Transient Spectroscopy Methods
Authors: Kikawa Junjiroh , Horiuchi Yuki , Shibata Eiji , Kaneko Masamitsu , Otake Hirotaka , Fujishima Tatsuya , Chikamatsu Kentaro , Yamaguchi Atsushi , Nanishi Yasushi 
Published: February 2009

AbstractInterface states produced at the interface between an insulator and GaN semiconductor determine the performance of GaN metal-insulator-semiconductor (MIS) field effect transistors. Therefore, it is important to know details of interface states characteristics to improve device performances. For above purpose, we have fabricated GaN MIS capacitors, then carried out capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) measurements, and analyzed the obtained results in detail.Wafers used in this study were n-type GaN grown on sapphire substrates by metal organic chemical vapor deposition. A film of SiN was deposited as an insulating layer using electron-cyclotron-resonance plasma-assisted deposition at room temperature, then samples were annealed at 400, 600 or 800°C in N2 atmosphere for 10 min.CV measurements were performed for all the samples at various frequencies and bias sweep rates in the dark condition. CV curves of all the samples exhibited ledges in the curves. Here, ledge indicates a region of which capacitance is independent of applied bias. Although each sample was annealed at each different temperature, it was observed at the same surface potential for all the samples. This result indicates that the Fermi level of the GaN/SiN interface is pinned by a particular trap. In addition, the shape of the CV curve depended on both frequency and bias sweep rate, and it was not observed in the results obtained by a quasi-static capacitance voltage measurement. This can be explained that the shape of ledge is determined by the quasi-equilibrium between a filling rate of traps and a bias sweep rate or test frequency.In the positive bias region of the ledge, a hysteresis window of the CV curve had some dependence on frequency but little dependence on bias sweep rate. On the other hand, in the negative bias region of the ledge, it had little dependence on frequency but obvious dependence on bias sweep rate. These dependences indicate two different traps and related to the ledge formation. The trap energy level related to the sweep rate dependence is estimated to be 0.34 eV by the temperature dependence of the width of hysteresis window.Deep level transient spectroscopy measurements were carried out to characterize the trap levels observed in the CV curves. Trap levels with activation energies of 0.32 and 0.78 eV were observed [1]. The former is almost equal to 0.34 eV obtained from the temperature dependence of the width of hysteresis window. The latter is similar to the interface trap reported by Nakano et al., which is considered to be originated from the complexes of Si and surface defect [2].[1] E. Shibata et al., Ext. Abstracts 2008 IMFEDK, Osaka, pp.69-70. (2008).[2] Y. Nakano and T. Jimbo, Appl. Phys. Lett. 80, 4756 (2002).
Characterizations of Boron Carbon Nitride and Boron Carbide Films Synthesized by PECVD
Authors: Wu Qingguo , Sriram Mandyam , Sims Jim , Fu Haiying , Varadarajan Sesha , Archer Tim , Trujillo Nathan J. , Gleason Karen K. 
Published: February 2009

AbstractThin films of boron carbon nitride (BCN) and boron carbide (BC) were synthesized by plasma enhanced chemical vapor deposition (PECVD) using two different reactant chemistries: (i) N,N’,N” – trimethylborazine (TMB); (ii) dilute diborane (5% in Ar) and hydrocarbon as precursor materials. Fourier transform infrared spectroscopy (FTIR), Raman spectroscopy, Nano-Indentor, Flexus stress instrument and x-ray photoelectron spectroscopy were used to study the deposited films. The BC films are much more stable than BCN films under high humidity (100%) environment. Both BCN and BC films are very stable under atmospheric conditions. A high compressive stress of -4.2 GPA was achieved by conventional PECVD, which show promising applications in high performance ultra large-scale integrated circuit (ULSI) devices.
Post-stress/breakdown leakage mechanism in ultrathin high-κ (HfO2)x(SiO2)1-x/SiO2gate stacks: A nanoscale conductive-Atomic Force Microscopy C-AFM
Authors: Uppal Hasan Javed , Markevich Vladimir , Volkos Stergios N , Dimoulas Athanasios , Hamilton Bruce , Peaker Anthony R 
Published: February 2009

AbstractConductive atomic force microscopy (C–AFM) in ultra high vacuum (UHV) has been used to characterize charge trapping in ultrathin as–deposited oxide films of 2–4 nm (HfO2)x(SiO2)1-x/SiO2multilayer gate stacks. Pre– and post–stress/breakdown (BD) dielectric degradation is analyzed on a nanoscale. A systematic observation probes stress induced trap generation facilitating physical stack BD. Degradation is considered in terms of the pronounced localized leakage contribution through the high–κ and interlayer SiOx. Simultaneous nanoscale current–voltage (I-V) characteristics and C–AFM imaging illlutrates charge trapping/decay from the native or stress induced traps with intrinsic charge lateral propagation. A post–stress/BD constant voltage imaging shows effects of stress bias polarity on the BD induced topography and trap assisted nano–current variations. Physical attributes of deformed artifacts relate strongly to the polarity of electron injection (gate or substrate) so discriminating the trap generation in high–κ and interlayer SiOxrevealing non–homogeneous (dynamic) nature of leakage.
3-D Finite Element Simulation of a Phase-change Random Access Memory Cell with a Self-insulated Structure
Authors: Sun Ke , Feng Wen , Lee Jae Young , Li Biyun , Xie Ya-Hong 
Published: February 2009

AbstractIn this paper, we proposed a phase-change random access memory (PCRAM) cell with a self-insulated structure (SIS), which is expected to have better thermal efficiency than the conventional structures. 3-D finite element simulation is used to study the most power consuming RESET process for both SIS and conventional normal bottom contact (NBC) cells driven by a MOSFET. Instead of programming current, power consumption is investigated to give a more fundamental comparison between the two structures. Thermal proximity effect for both kinds of cells is directly analyzed by simulating a 3×3 device array. The potential slow-quenching issue of SIS is also discussed.
Cathodoluminescence Study of Orientation Patterned GaAs Crystals for Nonlinear Optical Frequency Conversion by Quasi-Phase-Matching
Authors: Angulo Hector , Avella Manuel , Martínez Oscar , Jimenez Juan , Lynch Candace , Bliss David 
Published: February 2009

AbstractOrientation patterned (OP)-GaAs crystals show promise for use in tunable coherent light sources in the infrared (IR) and terahertz (THz). These structures consist of an alternating array of [001]/[00-1] oriented domains grown by hydride vapor phase epitaxy (HVPE). Material characteristics concerning the propagation losses, the crystal dimensions, and the grating size must be taken into account to implement optical devices for specific wavelength ranges and operating modes (CW or pulsed). The analysis of the main factors contributing to optical loss in the OP crystals is a crucial step toward their use in many promising applications. We present a cathodoluminescence study, where the main defects and their distribution over the OP-GaAs crystals are revealed, with special emphasis paid to the properties of the domain walls.
Strained Quantum Wells for P-channel InGaAs CMOS
Authors: Nagaiah Padmaja , Tokranov Vadim , Yakimov Michael , Oktyabrsky Serge 
Published: February 2009

AbstractWe present experimental results on the effect of strain on hole transport in InGaAs quantum well (QW) structures. Indium content was varied from lattice matched to high compressive stress in InGaAs/InP QW and the transport properties were analyzed at various temperatures (T = 77-300 K) using Hall measurements. The effect of QW thickness (4-20 nm) on hole transport is also presented. The current best results include room temperature mobility and sheet resistance of 390 cm2/V-s and 8500 Ω/sq., respectively. It was observed that the mobility had a T-1.8 dependence indicating similar scattering mechanism in almost all of the samples with prominent mechanism being due to interface and barrier scattering. Further optimization of p-channel for InGaAs CMOS needs to be performed using the above results as guidelines.
Nb-doped TiO2 films for transparent conductive electrodes with low resistivity deposited by dc magnetron sputtering using a TiO2-x–Nb2O5-x target
Authors: Sato Yasushi , Sanno Yuta , Oka Nobuto , Kamiyama Toshihisa , Shigesato Yuzo 
Published: February 2009

AbstractNb-doped anatase TiO2 films were deposited on unheated glass by dc magnetron sputtering using a slightly reduced TiO2-x–Nb2O5-x target with oxygen flow ratios [O2/(Ar+O2)] in the range from 0.00 to 0.20%. After post-annealing in a vacuum (6 × 10−4 Pa) at 500 and 600 °C for 1 h, the films were crystallized into the polycrystalline anatase TiO2 structure. The resistivity of the both films decreased to 6.3-6.8 × 10−4 Ω·cm with increasing [O2/(Ar+O2)] to 0.10%, where the carrier density and Hall mobility were 1.9-2.0 × 1021 cm−3 and 4.9-5.0 cm2·V−1·s−1, respectively. The films exhibited high transparency of over 60-70% in the visible region of light.
NH3 Doping in MOCVD Growth of ZnO Thin Films
Authors: Zaidi Tahir , Jamil Muhammad , Melton Andrew , Li Nola , Fenwick William E. , Ferguson Ian T. 
Published: February 2009

AbstractIn this paper effects of NH3 doping on ZnO thin films grown by metal organic chemical vapor deposition (MOCVD) on c-plane sapphire substrates using diethyl zinc (DEZn) and O2 precursors and N2 as the carrier gas have been studied. NH3 flow rates were varied from 0.1% to 4% in the growth runs. All the runs were done at 500°C at 10 Torr pressure.The XRD measurements show a single ZnO (002) peak. Raman data for the samples confirms presence of ZnO:N modes at 275cm−1, 510cm−1 and 575 cm−1 and 645cm−1. The PL results for Zn rich films show weak broad peaks centered at 480nm and 650nm with no ZnO band edge emission, while oxygen rich films show weak ZnO band edge emission and a strong broad orange peak centered at 650nm. Hall effect measurements indicate that all of the as-grown films are highly resistive. Some are weakly p-type with carrier concentration of 4.24 × 1014 cm−3 and mobility of 16.55 cm2/Vs. Annealing in N2 ambient for 60 minutes at 800°C enhances the PL band edge emission and converts all the films to highly conducting n-type, with carrier concentration on the order of 8 × 1018 cm−3, mobility on the order of 12 cm2/Vs and resistivity of 0.063 Ω-cm.
Correlation Between Ferroelectric and Fluorescent Properties by Introducing Eu Atoms Into Strontium Bismuth Tantalate Films
Authors: Aizawa Koji , Ohtani Yusuke 
Published: February 2009

AbstractElectrical and fluorescent properties of Sr-deficient strontium bismuth tantalate co-doped with excess-Bi and Eu atoms (BiEu-SBT) were investigated, in which the Eu/Bi ratio was changed between 0 and 0.1. BiEu-SBT were synthesized on Pt (200 nm)/Ti (50 nm)/SiO2/Si substrates by using Sr0.8Bi2.2Ta2O9 and Sr0.8(Bi2, Eu0.2)Ta2O9 mixed precursor solutions with a concentration of 0.33 mol/kg, in which Sr concentration was fixed at 0.8. From X-ray diffraction analysis, the diffraction peaks from Aurivillius phases were observed in the synthesized BiEu-SBT as well as in pure SBT. In BiEu-SBT, the lattice parameters along a- and c-axes at the Eu/Bi ratio of 0.1 in comparison with those of 0 decreased approximately 0.27 and 0.19 %, respectively. The remnant polarization (2Pr) values of the synthesized BiEu-SBT with Eu/Bi ratio of 0 and 0.1 were approximately 8.4 and 6.8 μC/cm2, respectively. From photoluminescence (PL) measurement at a wavelength of 615 nm as a function of Eu/Bi ratio, the PL intensity of the synthesized BiEu-SBT was proportional to the Eu/Bi ratio, whereas, the 2Pr values were slightly decreased by Eu-doping.
3D Process Integration – Requirements and Challenges
Authors: Wolf Juergen Max , Klumpp Armin , Zoschke Kai , Wieland Robert , Nebrich Lars , Klein Matthias , Oppermann Hermann , Ramm Peter , Ehrmann Oswin , Reichl Herbert 
Published: February 2009

AbstractHeterogeneous system integration is one of the key topics for future system integration. Scaling of System on Chip (SoC) alone does not address today's requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market.
The traditional microelectronic packaging will more and more convert into complex sys-tem integration. ‘More than Moore’ will be required due to tighter integration of system level components at the package level. This trend leads to advanced System in Package solutions (SiP) which require the synergy and a combination of wafer level and board integration technologies and which are rapidly evolving from a specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets especially due to the high volume and very cost competitive consumer and communication market. Advanced SiP approaches explore the third dimension which results in complex system architectures that also require, beside new technologies and improved materials, adequate system design tools and reli-ability models. One of the most promising technology approaches is 3D packaging which in-volves a set of different integration approaches including stacked packages, silicon interposer with Through Silicon Vias (TSV) and embedding technologies. The paper highlights future sys-tem and potential technical solutions.
3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces
Authors: Lu Jian-Qiang , McMahon J. Jay , Gutmann Ronald J. 
Published: February 2009

AbstractThree-dimensional (3D) integration is an emerging technology that vertically stacks and interconnects multiple materials, technologies and functional components to form highly integrated micro/nano-systems. This paper reviews the materials and technologies for three wafer bonding approaches to 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces. Similarities and differences in architectural advantages and technology challenges are presented, with recent research advances discussed.
Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits
Authors: Radisic Aleksandar , Lühn Ole , Swinnen Bart , Bender Hugo , Drijbooms Chris , Doumen Geert , Kellens Kristof , Ruythooren Wouter , Vereecken Philippe M. 
Published: February 2009

AbstractEstablishing a cost-effective technology for the metallization of through-Si vias (TSV) is an important factor in the realization and volume manufacturing of 3D-stacked integrated circuits (3D-SIC). Cu electroplating, which is the preferred technique, should provide not only a void-free TSV fill, but also short filling time and small overburden. The duration of the plating process is a significant contributor to the overall 3D process cost, and thus needs to be minimized. The overburden, the thickness of the material deposited on the top surface of the wafer, has to be limited for compatibility with the following processing steps (e.g. chemical mechanical polishing, CMP).
In this paper we report on Cu plating of TSV-s with a thin Ta film on the field. The thin Ta film is sputtered on top of the Ta barrier/Cu seed, and inhibits Cu plating outside the TSV-s. We show that the use of this Ta-cap and in situ electrochemical monitoring techniques leads to significant savings in plating and polishing time, and thus savings in manufacturing costs of 3D-stacked integrated circuits.
A Method for Die Thickness Reduction to sub-35 μm
Authors: Thompson Jeffrey , Tepolt Gary , Racz Livia , Rogers Chris , Manno Vincent , White Robert 
Published: February 2009

AbstractSignificant system performance improvements can be realized by stacking die layers. This approach, known as 3-D integration, can reduce RC delay as well as the system form factor. Die are typically thinned in wafer form prior to integration into the modules allowing even greater functional density. However, certain applications require the thinning of individual die. A detailed technique including die lamination, lapping, chemical mechanical planarization (CMP), and release has been developed to thin die to 35 μm thickness. During lamination, the die are temporarily adhered with their active side down to a glass substrate using an adhesive. Mechanical lapping is performed to remove the majority of silicon from the back side. The final thickness of approximately 35 μm is achieved using CMP. The CMP step is critical for the removal of sub-surface damage and prevention of device failure. After thinning, the adhesive is dissolved and the die are handled using porous end effectors. The process can effectively produce die thinned to 35 μm with ± 1.5 μm total thickness variation (TTV).
A Novel Method for the growth of Low Temperature Silicon Structures for 3-D Flash Memory Devices
Authors: Mih Thomas A , Cross Richard BM , Paul Shashi 
Published: February 2009

AbstractLow temperature (≤400°C) growth of polycrystalline silicon (poly-Si) is carried out using plasma-enhanced chemical vapour deposition. After an initial preparation step poly-Si was grown on the substrates. Optical band gap studies of the poly-Si films have been correlated to hydrogen content of the films as well as to their photoconductivity. Furthermore, the suitability of these films for use as information storage materials for future generation 3-D flash memory devices is investigated using capacitance-voltage (C-V) measurements via metal-insulator-semiconductor device structures. C-V analysis indicates strong charge storage behavior for the poly-Si films.
Utilizing Quantum Dots to Enhance Solar Spectrum Conversion Efficiencies for Photovoltaics
Authors: Savage Richard N , Mayer Hans , Lewis Matthew , Marrujo Dan M 
Published: February 2009

AbstractSilicon-based photovoltaics typically convert less than 30% of the solar spectrum into usable electric power. This study explores the utilization of CdSe based quantum dots as spectral converters that absorb the under utilized UV portion of the solar spectrum and fluoresce at wavelengths near the band-gap of silicon-based solar cells. A flexible 1 mm thick thin-film structure that contains an array of microfluidic channels is designed and fabricated in polydimethylsiloxane (PDMS) using soft-lithographic techniques. The channels are approximately 85 microns wide by 37 microns tall and are filled with a solution containing the quantum dots. The thin-film structure can easily be attached to the surface of a single-junction solar cell. As a result, solar energy striking the coated solar cell with wavelengths less than 450 nm, which would normally experience low conversion efficiency, are absorbed by the quantum dots which fluoresce at 620nm. The high energy photons are converted to photons near the band-gap which increase the overall conversion efficiency of the solar cell. The quantum dots employed in this study are fabricated with a CdSe core (5.2 nm) and a ZnS outer shell and they exhibit a 25 nm hydrodynamic diameter. The UV-VIS spectral transmission properties of PDMS, along with its refractive index, are determined in order to characterize the spectral conversion efficiency of the thin-film structure. A model is developed to predict the optimum path length and concentration of quantum dots required to improve the power output of an amorphous silicon solar cell by 10%.