bluuebunny/crossref_metadata_2025_split huggingface dataset:
The balance chart: A new SPC Concept
Authors: Thomas D. E. 
Published: July 2007

AbstractThis paper outlines a new technique of statistical process control which goes a considerable way to resolving several existing problems. The technique described may be of particular value to automated control, small batch control and control of gauged processes. A new charting technique is described and compared with traditional control charts. The operation of the balance chart is outlined for attribute and variable processes and in precontrol mode. A graphical system for determining estimated Cp, Cpk and process mean values from limited process data is also included.
The use of expert systems in total quality management: An exploratory study
Authors: Crossfield R. T. , Dale B. G. 
Published: July 2007

AbstractThis paper explores the potential for the use of expert systems in total quality management (TQM). The study was carried out under the auspices of the first multi‐company programme of research into TQM. Among the findings are that it is feasible to run expert systems on personal (and other) computers in order to assist with aspects of TQM such as statistical process control, quality costing, goods receiving, corrective action procedures, supplier development, quality function deployment and field failure analysis, and that the potential application of expert systems to TQM was received with some degree of enthusiasm by the personnel with whom the concept was discussed. It is also pointed out that the most difficult task in producing an expert system is acquisition of knowledge, and that knowledge elicitation can be facilitated by use of the quality assurance mapping technique—Q‐MAP.
Process monitoring in real time: Empirical bayes approach—discrete case
Authors: Yousry M. A. , Sturm G. W. , Feltz C. J. , Noorossana R. 
Published: July 2007

AbstractIn this paper an empirical Bayes model is developed to monitor and analyse discrete data generated in a manufacturing process for printed circuit boards. A key feature of this analysis is the use of the current observation at time t and the posterior estimates of the distribution of the proportion nonconforming at time t – 1 to obtain a new, updated estimate of the posterior distribution at time t. The derived approach is widely applicable to statistical process control and provides a simple and fast algorithm for updating.
Electron beam testing
Authors: Wolfgang E. , Görlich S. , Kölzer J. 
Published: July 2007

AbstractElectron‐beam testing (EBT) is currently used at two stages in the development and manufacture of integrated circuits (ICs), namely for chip verification and failure analysis. These are explained with the aid of two examples. EBT is, however, only one of many diagnostic tools. In order to classify it more usefully, a scenario is described that takes account of trends in chip development and packaging, and the linking of EBT with CAD (computer‐aided design) and CAT (computer‐aided testing). The conclusion is reached that EBT will remain an indispensable diagnostic tool. In future, it will probably be used under increasingly more difficult conditions, however, due primarily to the greater complexity of specimen preparation and test stimuli generation.
Photon emission as a tool for esd failure localization and as a technique for studying ESD phenomena
Authors: Hannemann Marcel , Amerasekera Ajith 
Published: July 2007

AbstractPhoton emission microscopy gives the opportunity for non‐destructive localization of failure sites on VLSI chips. Failures that can be detected using photon emission microscopy are gate‐oxide breakdown, latch‐up, junction breakdown and intermetal oxide failures. This makes it a valuable evaluation technique of failures in ESD protection circuits.Real‐time photon emission observations of reverse‐biased transistors showed that this technique is also an important tool in the evaluation and development of ESD protection circuits.
Hot carrier degradation in MOSFETs in the temperature range of 77–300 K
Authors: Maes H. E. , Heremans P. , Bellens R. , Groeseneken G. 
Published: July 2007

AbstractIn this paper the DC hot carrier degradation ofn‐channel andp‐channel MOSFETs is treated in the temperature range of 77–300 K. A thorough analysis of the degradation mechanisms is made possible by an extensive use of the charge pumping technique for the determination of the interface properties of the MOS devices prior to and after degradation in this temperature range, in addition to the more conventional techniques based on shifts and/or distortions of the current–voltage characteristics. The physical processes responsible for the transistor degradation are identified in each voltage regime for the two types of transistor.
The long‐term stability ofn‐AlGaAs/InGaAs/GaAs pseudomorphic HEMTs
Authors: Saunders N. L. , Rezazadeh A. A. , Morgan D. V. , Thomas H. , Hipwood L. G. 
Published: July 2007

AbstractAgeing tests on PHEMTs, ohmic contacts and heterojunction test samples have been performed. During moderate temperature life tests (< 170°C) the degradation is related to the ohmic and gate contacts. At higher test temperatures (> 210°C) a third degradation mechanism is evident, possibly attributed to field enhanced instabilities in the AlGaAs/InGaAs heterojunction or to Si diffusion, at the drain edge of the gate. A worst case activation energy of 1.49 eV has been deduced.
Degradation mechanisms in 2 W MESFETs
Authors: Canali C. , Magistrali F. , Paccagnella A. , Sangalli M. , Tedesco C. , Zanoni E. 
Published: July 2007

AbstractBiased life tests and thermal storage at different temperatures have been performed on 2 W GaAs MESFETs from two different suppliers. Failure modes and mechanisms are correlated to device technology and are thermally activated. In samples with Au/Pd/Ti gate metallization we observed a decrease of Idss current and an increase of the gate diode reverse current. The former is related to the gate‐semiconductor interaction, whereas annealing of GaAs surface states is responsible for the latter, which can cause the device burn‐out. These degradations exhibit activation energies of 1 eV and 1.5 eV, respectively. In samples with Al gate metallization, we measured an increase of parasitic resistances possibly deriving from a degradation of the ohmic contacts.
A two‐stage sampling plan for bogey tests
Authors: Wang C. Julius , Lu Ming‐Wei 
Published: July 2007

AbstractWhen accelerated life tests can be applied to simulate the normal product operating conditions, engineers usually terminate the test upon successfully running to a multiple of a prespecified bogey without any failure to demonstrate a required minimum reliability level. This testing philosophy is called ‘bogey test’ (or extended test) in the automotive industry and is a subset of type I censored tests in standard reliability literature. Sometimes engineers encounter the difficulty of using this reliability demonstration approach when incidents do occur during the test. The incident might be a legitimate failure or a withdrawal caused by external forces such as a broken fixture of a non‐functional power supply. This paper derives a two‐stage sampling plan for possible back‐up solution on planning and running a bogey test with possible occurrence of incidents. A Weibull distribution with a given shape parameter is assumed for the underlying life characteristic.
Use of a cmos static memory array as a technology test vehicle
Authors: Schmitt‐Landsiedel D. , Winnerl J. , Neuendorf G. , Kölzer J. 
Published: July 2007

AbstractA static memory array is described for use as a test vehicle in CMOS process development. Design guidelines are given for a large operating range and good testability. Address paths are defined for efficient comparison of access time measurements and simulations. the functional yield of SRAMs is correlated with defect density results from test structures to identify the relevant yield limiting defects. It is shown that an SRAM is a suitable test vehicle for yield prediction of complex CMOS random logic circuits.
Failure analysis of multilevel metallized lsi using optical beam induced current
Authors: Mitsuhashi J. , Komori S. , Tsubouchi N. 
Published: July 2007

AbstractIn order to analyse failures caused in multilevel metallized LSI devices. we developed the OBIC (optical beam induced current) observation technique using an infrared laser incident upon a backside of the chip which appears from a plastic package by being lapped and polished.We analysed the electrical rejects in the reliability stressing of surface mount plastic packages with this technique. The latch‐up phenomenon in 4Mbit dynamic RAM with retrograded‐well fabricated by a high energy (MeV) ion‐implantation was also examined. The high latch‐up immunity of the device with retrograded‐well is confirmed by this analysis.
Stability of interfaces in pseudomorphic ingaas hemts
Authors: Audren P. , Dumas J. M. , Mottet S. , Vuchener C. , Paugam J. , Favennec M. P. 
Published: July 2007

AbstractConsiderable progress is now reported on pseudomorphic InGaAs high mobility transistors (PM. HEMTs). However, structures which exhibit the best performances are thermodynamically metastable. The stabilities of commercially available devices have been studied. Investigations of both GaAs InGaAs and AlGaAs/InGaAs interface vicinities have been performed through deep level characterizations. Life‐testing experiments have then been carried out in order to assess the stability of the InGaAs buried strained layer and related interfaces during operation. Deep level studies together with electrical parameter measurements indicate that interfaces of InGaAs strained quantum well HEMTs do not induce particular degradations after 3000 hours into biased ageing tests.
Economical design of reliable systems—some practical situations
Authors: Aggarwal K. K. 
Published: July 2007

AbstractDesigning reliability into a system is one of the most important objectives of a system disigner. A system normally consists of several components, and the possibility that each component is available in the market in different categories with various specifications, reliability values and costs requires serious consideration while designing a system. Therefore, the difficulty which the system designer always comes across is how to choose an appropriate combination of components so that the achieved system reliability is maximum for the given cost.The present paper aims at investigating an efficient approach which generates directly those combinations of components which guarantee the maximum system reliability at a specified cost. Also, if the system designer wants to increase his resources, the proposed method provides a way of selecting a configuration with higher reliability if it exists. Based on the developed algorithm an interactive package has been prepared, which also permits the user to exercise options such as minimum acceptable reliability value, maximum affordable cost, duty ratios for components which work for a period less than the mission time, and criticality values for components which are not fully critical. A complete example illustrating all these features is also discussed.
Applications of hazard rate profile to software reliability prediction. Growth modelling and allocation
Authors: Friedman Michael A. 
Published: July 2007

AbstractThe concept of a computer program's ‘hazard rate profile’ is introduced. A software fault's hazard rate is the amount the fault contributes to the overall program failure rate. The hazard rate profile describes the relationship between the program's failure rate and fault content by summarizing the relative proportion of software fault hazard rates that fall into different hazard rate classes. The usefulness of the hazard rate profile concept is shown by applying it to the tasks of software reliability prediction, growth modelling and allocation.
Assuring quality of the human–computer interface
Authors: Kohoutek Henry J. 
Published: July 2007

AbstractThe issue of human–computer interface quality has been brought currently into focus due to (a) a change in the character of users who dominate the computer market, (b) the availability of expertise in design for usability and its assurance, and (c) the finally recognized business benefits for vendors of user friendly equipment. Because the underlying human factors expertise belongs to the category of enabling generic quality assurance technologies, the quality management and engineering communities must master this new issue, and related knowledge and methods. The objective of this review article is to aid the quality professionals to respond successfully to this challenge by presenting the fundamentals of human factors engineering, its role in the design for usability process, and the associated methods of assuring quality of the human–computer interface.
Using the economic point of truncation process for new product introduction
Authors: Zurn James T. 
Published: July 2007

AbstractProper validation and release of a newly developed product into the market‐place at the minimum supplier cost requires a robust deterministic system. It must characterize cost elements and recommend optimum introduction points in support of total quality management. The economic point of truncation (EPOT) process fulfils the requirements for this system. It integrates pre‐ and post‐release problem resolution costs with the rates of problem discovery, latent problems and product shipping into a product life cycle model. The model simulates the cost accrual for problem resolution during the validation, release and product shipment periods. Model execution results in a characterized life cycle indicating the optimum duration of product validation that minimizes total problem resolution costs.
Fault impact and fault tolerance in multiprocessor interconnection networks
Authors: Menezes Bernard , Johnson Allen M. , Malek Miroslaw , Jenevein Roy , Yau Kitty H. 
Published: July 2007

AbstractGrowing complexity of parallel machines coupled with increasing chip densities escalates the need for fault tolerance and recovery in these systems. In pursuit of the goal of fault‐tolerant multiprocessors, many techniques have been proposed. Since methods for designing fault‐tolerant processors and memories are relatively mature, the techniques considered in this paper focus on the interconnection network (ICN) linking the processors. The impact of faults on non‐fault‐tolerant ICNs is contrasted with that in fault‐tolerant networks. Fault tolerance in ICNs is addressed at two levels, inter‐node or switch level and system level. Inter‐node or switch level pertains to data and control integrity and system level deals with maintaining network connectivity and adequate performance levels in the presence of faults. Fault‐tolerant schemes at the switching element level warrant some form of concurrent error detection such as the use of codes usually combined with a full handshake protocol. Space–time trade‐offs involved in the use of various codes and protocols are investigated. At the system level, several augmented multi‐stage switching ICNs, tree and ring networks are studied. The combined provision for fault tolerance together with improved performance in the non‐fault condition is emphasized. Finally, strategies for network reconfiguration and rerouting after system failure are presented.
Formal methods: The next generation of system design tools
Authors: Schofield Mike 
Published: July 2007

AbstractBecause of the growing demand for increasingly complex computer‐based systems there is now an urgent need to provide tools to assist during the design of such systems.Formal specifications and formal methods provide such assistance but their widespread adoption has been hindered by the so‐called ‘math fear’ and the perception that the tools are too difficult, too time consuming and too costly to use in a commercial environment.The aim of this article is to dispel the mystery surrounding the topic and to explain what formal methods are, how and why they are used, the benefits that accrue and why the technology should be accepted on a broader front.The application of formal methods to the design of computer‐based systems will be discussed without resorting to jargon or mathematics. The discussion will concentrate more on the software content of systems but the arguments apply equally well to hardware.Some of the available tools will also be introduced.
Spc of a near zero‐defect process subject to random shocks
Authors: Xie M. , Goh T. N. 
Published: July 2007

AbstractIn this paper we study the problem of monitoring and control of a type of process in which long series with no non‐conformities are observed together with occasional samples containing a large number of non‐conformities. We call this a near zero‐defect process subject to random shocks. Such processes occur often in practice, and a model is proposed for the identification of real non‐random variations of process characteristics. Based on the statistical analysis carried out for this model, a procedure for decision‐making in the control of this type of process is suggested, and analysis of some actual cases presented.
Maximum likelihood estimation from record‐breaking data for the weibull distribution
Authors: Hoinkes Lori A. , Padgett W. J. 
Published: July 2007

AbstractIn destructive stress testing, industrial quality control, or other situations, data may consist only of record setting values, such as successive values that are smaller than all previous ones observed. Here, for a two‐parameter Weibull distribution, the performance of the maximum likelihood estimators (MLEs) from record‐breaking data is studied by computer simulations. Comparison of the biases and mean squared errors of these estimators with those of the MLEs for complete samples from the Weibull distribution is discussed and some examples are presented.
Integration of efforts for the reliability of microelectronic devices
Authors: Gerling W. 
Published: July 2007

AbstractThe expected levels of product reliability will no longer be measurable at product qualification. The control of reliability must be completely changed to proactive measures. This requires close customer‐vendor relationships in early phases of specification and qualification, basic solutions by robust design and tough manufacturing engineering with zero defect targets. This changing situation is illustrated by some examples in the very diverse field of contributions to reliability. Improved cooperation is required for more efficient reliability progress.
Testability enhancement of a basic set of CMOS cells
Authors: Rullán M. , Oliver J. , Ferrer C. , Blom F. C. 
Published: July 2007

AbstractTesting should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrònica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design.
Application of defect simulation as a tool for more efficient failure analysis
Authors: Griep S. , Khare B. , Lemme R. , Papenberg U. , Schmitt‐Landsiedel D. , Maly W. , Walker D. M. H. , Winnerl J. , Zettler T. 
Published: July 2007

AbstractIn modern VLSI processes, increasing process complexity has resulted in an exponential rise in the costs of thorough failure analysis. In this paper, we present a defect simulation‐based failure analysis methodology, which can be used to significantly reduce both costs and turn‐around time for failure analyses. The methodology is based on the ability to generate a defect dictionary, which can relate defect characteristics to some easily measurable symptoms of defect occurrence.
A practical example for reduction of the call rate level
Authors: Rimmen Peter 
Published: July 2007

AbstractThis is a description of a practical way to develop a new product with a built‐in robustness for many parameters. This has reduced the field call rate. The field call rate is measured using the superimposed renewal process M(t). This work has resulted in developing ‘stronger solder joints’ and it has also reduced the amount of resolder joints in PCB assembly.
Quantified risk assessment in railway system design and operation
Authors: Haile J. P. 
Published: July 2007

AbstractOver the last few years quantified risk assessment (QRA), a technique developed in the process industries, has moved into the railway and mass transport arenas. Many quantified risk assessments are now appearing covering varying aspects of railway operation and design.This paper highlights the strengths and weaknesses of the QRA technique, with specific reference to its use in railway system design and operation. Suggestions are made as to how best to manage and present a QRA, and these are illustrated in a section explaining the systematic approach of Cross Rail, a joint London Underground/British Rail/Railtrack £2 billion railway for London.Throughout this paper it is stressed that good QRA comes from management of the process and not of the ‘final figure’. The paper concludes with a listing of recommendations that are considered to be the minimum needed for the future progress of railway QRAs. Consequently the paper will be of special interest to those railway organizations undertaking or managing a QRA for the first time. Special reference is made to the use of QRAs in the presentation of Railway Safety Cases and project design.
A fast algorithm for template pattern matching based on probability of occurrence of subpatterns
Authors: Shima Yoshihiro , Kashioka Seiji , Ejiri Masakazu 
Published: July 2007

AbstractThe template matching method is utilized in the document information processing and industrial visio n. It is a method to extract from the given image patterns similar to the specified patter n. With the increase of the size of the image and the kinds of template patterns, however, the high‐speed realization of the method becomes a proble m. In this paper, a new high‐speed pattern matching method is described for the binary image, based on the sequential similarity detection algorithm (SSDA), which is known as a means of high‐speed realizatio n. In the first part, the expected computation time by SSDA is calculated using the occurrence probability of the subpattern in the templat e. Then a method is proposed in which the order of pixel comparison is determined based on the occurrence probability of the blockwise subpatterns in the given image .A detailed discussion is made for the case where no matching error is permitted in the metho d. The method is applied to the case of two‐dimensional IC chip pattern, indicating the effectiveness of the method in the high ‐speed realization of the pattern matching.