bluuebunny/crossref_metadata_2025_split huggingface dataset:
Verification of progress property of algebraically specified communication protocols
Authors: Higashino Teruo , Taniguchi Ken'Ichi , Kasami Tadao , Fujii Mamoru , Mori Masaaki 
Published: July 2007

AbstractThis paper considers the communication protocol whose specification is described algebraically in a style of an “abstract sequential machine.” A method is presented to verify the progress property of the protocol, such that the transmitted data will eventually be received. First, by the algebraic method, we verify some static properties (invariants) which hold in any state reachable by the execution of the state transitions permitted by the protocol. Also, we verify the relations which hold between the states before and after the execution of each state transition. These relations are transformed into the formulas of the temporal logic by using some transformation rules. At the same time, the formulas of the temporal logic are provided as the assumptions for the stations and communication lines, which are needed in the discussion of progress property of the protocol, such that the communication lines are not functionally cut off. Using these formulas and standard axioms in the temporal logic (inference rules), it is shown that the predicates representing the progress property of the protocol are true. The foregoing is the outline of the discussions in this paper. This paper applies the method to Stenning's data transfer protocol, and the progress property is verified.
A single public‐key authentication scheme for multiple users
Authors: Okamoto Tatsuaki 
Published: July 2007

AbstractThis paper proposes a new user authentication scheme, which does not require a management file for users' passwords. It has a high security, realizing the authentication of a large number of users by a single public key. Because of this property, the proposed system has merits in the application to off‐line and mutual authentication. The scheme is also useful in the authentication in a large system with a large number of users. The system is constructed using the public‐key digital signature and a oneway function with the commutative property. An example is presented where RSA is employed as the digital signature and the congruent exponential function is employed as the one‐way function. It is described that the security of the proposed system appears to be equivalent to that of RSA or the digital signature based on RSA. Following the same idea, a digital signature system is proposed, where the authentication of a large number of users can be performed by a single public‐key. A variation of the scheme is presented which has the same performance as the proposed scheme.
A built‐in testing scheme for ic memories by considering address decoder and cell array separately
Authors: Tamamoto Hideo , Sakusabe Hirotomo , Narita Yuichi 
Published: July 2007

AbstractIn the built‐in testing of the IC memory, the testing efficiency can be improved by building the testing circuit into the IC memory, that can observe and/or control the part which is difficult or impossible to be observed and/or controlled by the traditional method. From the functional viewpoint, the IC memory can be divided into the address‐part (address decoder, etc.) and the data part (memory cell, etc.). In the traditional testing, the address‐part is tested through the data part. In this paper, a built‐in testing scheme is discussed in which the testing circuit is built in so that the address and the data part can be tested separately. Restricting the faults to be the stuck‐at fault of the address decoder, the stuck‐at fault of the memory cell, and the interference fault by the 1‐neighborhood cells, those faults can be tested by compressing the response by a simple compression function, using the O(N) test sequence (where the sequence length is proportional to the memory capacity N). The test sequence generation circuit and the response compression circuit can be implemented simply by employing counters and shift registers. The extra hardware complexity becomes negligible with the increase of the memory capacity. Thus, it was proved as effective that the testing circuit is built‐in that can observe and/or control the part, which is difficult or impossible to be observed and/or controlled by the traditional method.
A color monitor system for color anomaly inspection
Authors: Yamada Kenshi , Sugie Noboru , Inaba Akira 
Published: July 2007

AbstractThis paper reports on the four kinds of inspections that can be performed by a system using a color monitor. The aim is to perform various kinds of inspection by a single system to provide a comprehensive decision for the color anomaly.The system used in this paper is a modified version of a system controlled by a minicomputer developed by Inaba et al. [1]. Measurement examples are also presented.
Data transmission and diagnosis in bus networks derived from block design
Authors: Ozawa Takao 
Published: July 2007

AbstractThis paper presents a method for constructing bus networks interconnecting a large number of data processors based on the block design. Properties of the bus networks constructed, an algorithm for finding data routing paths, and conditions for a distributed diagnostic procedure are presented. In the construction method considered, we regard a block and an object in the block design as a processor and a bus, respectively. Then two processors are either connected to the same bus or interconnected via a single intermediate processor. There are almost as many such independent data routing paths through a single intermediate processor as I/O ports of a processor. In fault diagnosis it is a general practice to assume an upper bound on the number of failed processors. For our bus network, we can show that it is possible to diagnose all the processors correctly by a distributed diagnostic method if the number of failed processors is less than min(n/2, d), where n is the number of processors and, with q and m denoting the number of I/O ports per processor and of buses, respectively, d = 4(m ‐ q)/q (q: even) or d = 4q(m ‐ q)/(q2 ‐ 1) (q: odd).
Design of a time‐optimal digital control system for a dc‐servomotor with amplitude limitation
Authors: Huang Xi Yue , Kameyama Michitaka , Higuchi Tatsuo 
Published: July 2007

AbstractThe time‐optimal control problem for a dc servomotor with an amplitude limitation in the manipulated variable is a complicated nonlinear problem. The problem has been investigated extensively from a theoretical viewpoint. However, little study has been made on the practical digital control system, even for a small‐scale controller using a microcomputer. This paper discusses the time‐optimal position control for a dc servomotor from such a viewpoint, and proposes a design method of the system based on the linear state feedback with the predetermined optimum sequence of a manipulated variable and the optimum sequence of the state trajectory. In other words, the optimal sequence of a manipulation variable and the optimum sequence of the state trajectory are predetermined by the linear programming, and the results are stored in ROM. In the actual control, the optimum sequence is read out from ROM to generate the desired sequence. The linear state feedback can reduce the effects of the external disturbance and the modeling error caused by the system fluctuation. Traditionally, the effects of the temporary disturbance and the modeling error have been a problem from the viewpoint of practical implementation, processing speed, and stability. The control minimizing these effects is the most remarkable feature of the proposed method. This method is suited to the controller using the microcomputer, and can be effective for the reduction of complexity and cost of the controller.
A fast algorithm for color image quantization using only 256 colors
Authors: Watanabe Takashi 
Published: July 2007

AbstractIn the recent workstation for CAD and CG, a color map display is often used, which can display 256 colors selected from 224 (approx. 16000000) colors using a look‐up table. Even in the computer system with such a color display with such a limited number of colors, it is desired that the continuous color image should be processed. In most cases, by determining colors which are important to the image (representative colors), the color image can approximately be displayed without much degrading the image quality. This paper proposes a new method for the approximate display of the color image by 256 colors. In the method, RGB color space is successively partitioned to determine 256 representative colors, so that the quasi‐optimum solution is obtained in the sense of the least‐mean‐square error. By the proposed method, a highly accurate approximate image is obtained with several times faster speed, compared with the traditional methods. The work memory required in the program is only 100 to 200 kBytes, which is less than in the traditional method.
Plex grammars for predicate logic programming and its application to the structural analysis of electronic circuits
Authors: Peng Ke Juan , Onda Kunio , Yamamoto Tsuyoshi , Aoki Yoshinao 
Published: July 2007

AbstractIn the syntactic analysis and recognition of patterns, the grammar to describe the pattern structure is the most basic theoretical problem. In regards to this problem, various kinds of grammars have been proposed, for example, Plex grammar which aimed at a more natural model description of the patterns. It can model a more general structure than graph grammar. On the other hand, the theory of grammar based on the logical programming such as Prolog, has recently been considered. It has advantages in that the grammatical rules can be described in the predicate form and the parsing can easily be performed using the inference mechanism. But in fact, the description by Plex grammars does not match the predicate logic, and there has been no study which combines Plex grammar and logic programming. This paper proposes C‐Plex grammar as another description of Plex grammar by the clauses of predicate logic, as well as the top‐down parsing of context‐free C‐Plex grammar based on logic programming by Prolog. C‐Plex grammar based on predicate logic programming has the advantage of high descriptive ability and easy parsing. The feature of C‐Plex grammar is demonstrated using the structural analysis of the electronic circuit as an example. By this elaboration, not only the hierarchical structure among circuit elements and the macroelements, but also the connection relation among them can be analyzed.
An implementation of multiple‐valued logic circuit with cmos multiple‐valued output gates
Authors: Sakata Izumi 
Published: July 2007

AbstractWith the progress of high‐density information handling technology, multiple‐valued logic is considered interesting. Studies have been made on the applications to the high‐density VLSI and the optimally multiple‐valued information processing systems. This paper considers the use of a CMOS multiple‐valued output gate, and proposes an implementation of the multiple‐valued logic circuit, which is suited to the integration from the viewpoints of the integration density and the power consumption. The CMOS multiple‐valued output gate produces a multiple‐valued output from the predetermined number (n ‐ 1 for n‐valued case) of binary inputs. Compared with similar multiple‐level output circuits proposed up to now, the gate has the feature of simple structure and easy correspondence to arbitrary n‐valued function. In the design of the multiple‐valued logic circuit by the proposed method, the inputs to the multiple‐valued output gate are determined first from the required multiple‐valued output. Then the logic circuit satisfying the inputs is constructed from the literal circuit with multiple‐valued inputs and binary logic circuits. Design examples by the proposed method are presented. It is shown especially for the arbitrary n‐valued case that the design is simplified since the inputs to the multiple‐valued output gate can be represented in the general form. Several rules for deriving the general form are described. Finally, it is made possible to implement the multiple‐valued logic circuit, which is simple and suited to integration.
An energy minimization approach to stereopsis: Perception of multiple interlaced surface
Authors: Sato Yoshinobu , Awaya Hideshi , Tamura Shinichi 
Published: July 2007

AbstractThis paper describes a stereo‐matching algorithm which works effectively even for a scene with a large number of discontinuities such as in the case of multiple interlaced surfaces. Prazdny [6] pointed out that the discontinuity can be handled by dissolving the ambiguity based on the facilitation by the similarity, rather than employing the discontinuity of disparity as the penalty. However, his method has a problem in that the ability to dissolve the ambiguity is decreased in correspondence to the reduction of scene restriction. In this paper, to determine the dispartity field maximizing the facilitation of similarity, several matching rules and matching primitives are combined, and the result is integrated into an energy‐minimum model of a network similar to Hopfield's neural network [7]. This resulted in a strong disambiguation power. Especially, we propose a new multiresolution processing method robust against discontinuity, in which processing of the different levels is in parallel. Only the information data concerning the image features corresponding to the same physical entity are propagated from the coarse to fine levels. By the reasonings in this paper, a natural extension is derived for the Marr‐Poggio first stereo algorithm [2]. An experiment was made for a scene through a fence, and it was verified that the interactions built in the network work effectively.
The structure of experts: A parallel processor system for 3‐dimensional graphics
Authors: Niimi Haruo , Hagiwara Hiroshi , Tomita Shinji 
Published: July 2007

AbstractA parallel processor system, called EXPERTS, is developed to generate realistic images of three‐dimensional (3‐D) scenes at a high speed. EXPERTS inputs a list of 3‐D objects defined by a polyhedron model, executes hidden surface elimination by utilizing a scan‐line algorithm, and calculates a frame of pixel values. To perform these processes efficiently, EXPERTS is constructed as a two‐level hierarchical bus‐connected multiprocessor system. This system architecture is derived from the processing scheme employed in which the scan‐line algorithm is divided into two succeeding stages and parallelism is introduced to each stage, respectively. Two types of special‐purpose processor elements were designed to speed up these two processes: that for the former stage is called Scan‐Line Processor (SLP), and that for the latter stage is called PiXel processor (PXP). This paper describes the parallel processing method of scan‐line algorithm, the interconnection scheme of the processor elements, and the details of their hardware architecture. Performance estimation of the system is also presented.
Machine parts recognition and processing using fourier descriptors
Authors: Itoh Hidetoshi , Hirata Tatsuya , Ishii Naohiro 
Published: July 2007

AbstractIn the recognition of industrial parts by image processing, one of the methods is to use the Fourier descriptor as a matching method which is invariant against rotation, expansion, contraction, and translation. This paper discusses the recognition method using the Fourier descriptor from the viewpoint of industrial applications. First, a new matching method is proposed considering the optimality and the efficiency, using, in particular, a P‐type descriptor among several Fourier descriptors. The method is to reduce the number of operations and to improve the efficiency by selecting a few coefficients with larger values from Fourier descriptors of the model, and to solve a simple algebraic equation for the object descriptor. Next, several slightly different recognition algorithms for the parts are proposed which are applicable to practical problems. Finally, the method is applied to construct an experimental system. Various kinds of automobile parts are discriminated, indicating the usefulness of the method. Further, the possibility of real‐time processing is indicated.
On‐line recognition of handwritten signatures by feature extraction of pen movements
Authors: Taguchi Hideo , Kiriyama Koichi , Tanaka Eiji , Fujii Katsuhiko 
Published: July 2007

AbstractTo establish an automatic method of signature verification, this paper presents an on‐line recognition technique of handwritten signatures by comparing the dynamic features extracted from pen movement with the reference data. In this paper, it is observed that dynamic features such as changes in pen inclination and writing force with time are different among the writers and these features are detected by various sensors attached to the pen. In other words, the pen inclination is estimated from the relationship between the pen inclination and the intensity of illumination at the paper surface of light emitted from an LED utilizing a reflective optical fiber sensor. The writing force in the axial direction of the pen is obtained from the relationship between the strain and applied force by using a force sensor installed at the central part of the pen. In comparison with the reference data, simple features such as number of pen‐ups and pen‐downs and maximum, minimum and average values of time histories of the writing force and pen inclination are considered first. If the data are rather significant, then further comparison is made with respect to the time series waves of the pen inclination and writing force before a final decision as to whether or not a signature is authentic is made. Finally, the proposed technique is applied to a set of test data consisting of autographs and forgeries and it is shown that this method distinguishes an autograph from a forgery from the changes in writing force and pen attitudes even though two signatures resemble each other.
Parallel execution on the function‐partitioned processor with multiple instruction streams
Authors: Sowa Masahiro , Arita Takaya , Kawamura Tadaaki , Takagi Hiromitsu 
Published: July 2007

AbstractThis paper proposes a parallel execution mechanism with the refinement between machine instruction level to the register transfer level. In the proposed mechanism, the processor is function‐partitioned into a number of processing units, and instruction streams are assigned independently to the processing units. According to the arc indicating the dependency in the control flow graph, the processing units exchange the asynchronous control signals at a high speed. Compared with the synchronous parallel execution mechanism such as VLIW, the proposed mechanism can extract the parallelism in a flexible and detailed way.First, the general parallel computation model based on the proposed mechanism is described. Then the basic configuration of the computer is described for the prototype model based on three classes of machine instructions. A simple evaluation is presented through execution examples of sample programs.
The generative power of multiple context‐free grammars and head grammars
Authors: Matsumura Takashi , Seki Hiroyuki , Fujii Mamoru , Kasami Tadao 
Published: July 2007

AbstractMultiple context‐free grammars (mcfg's) and head grammars (hg's) are subclasses of generalized context‐free grammars introduced by Pollard to describe the syntax of natural languages. In this paper, the following properties of mcfg's and hg's are shown: (1) the class HL of languages generated by hg's is the same as that generated by the tree adjoining grammars introduced by Joshi et al.; (2) HL is the same as that generated by left‐wrapping hg's (or right‐wrapping hg's) which is a proper subclass of hg's; (3) HL is properly included in the one generated by 2‐mcfg's, which is a proper subclass of mcfg's. As a corollary of (1), it is also shown that HL is a substitution closed full AFL.
A defect recovery method for ulsi/ wsi arithmetic operation systems based on residue number systems
Authors: Tomabechi Nobuhiro 
Published: July 2007

AbstractA method of fabrication defect recovery in ULSI (ultra‐large scale integration) and WSI (wafer‐scale integration) arithmetic operation systems involving fault tolerance based on residue arithmetic is presented. The implementation of the fault‐tolerant system, which includes a compact multiplexed error correcting circuit, is described. Analysis of the yield of redundant systems based on the proposed method indicates that the effect chip area of redundant ULSI/WSI systems can be extended to 10 to 20 times that of a nonredundant VLSI chip while maintaining a yield of 50 percent.
Hypercube Architecture with Bus Connections for Improving Communication Efficiency
Authors: Ishikawa Tsutomu 
Published: July 2007

AbstractThis paper describes a new hypercube architecture with multiple buses in which the maximum inter‐PE distance (called diameter) for any size hypercube can be shortened to two from log2N (N: the number of PEs).This architecture is obtained by partitioning all PEs of the hypercube into subsets whose PEs are far from each other using a Hamming code and its cosets, and connecting all PEs in each subset to a bus. PEs that are remote from each other communicate via this bus as a bypass route. These multiple bypass bus routes allow this architecture to improve communication efficiency. Moreover, broadcast also is executed in two communication cycles for any size hypercube.
New method of learning vector quantization using fuzzy theory
Authors: Sakuraba Yuuichi , Nakamoto Takamichi , Moriizumi Toyosaka 
Published: July 2007

AbstractBecause of its high performance, the learning vector quantization (LVQ) proposed by Kohonen is noteworthy as a method for realizing a neural network. We propose herein a new method of LVQ using fuzzy theory and call it “fuzzy learning vector quantization” (FLVQ).FLVQ algorithm is as simple as that of LVQ, and its capability of pattern recognition is higher than that of a conventional neural network. Although it is difficult for conventional neural networks to discriminate an input pattern of an unknown category from those of known ones, FLVQ can do it. Since reference vectors of FLVQ are described by use of fuzzy sets and their membership functions are obtained from learning, the data features can be effectively extracted using FLVQ.We have used FLVQ in an odor pattern recognition system and compared its capability with those of conventional neural networks. As a result, it was confirmed that FLVQ had higher ability in an odor discrimination from the known one than is the case in conventional networks and that an unknown odor was discriminated by FLVQ.
Dance and Non-Dance: Patterned Movement in Iran and Islam
Authors: Shay Anthony 
Published: July 2007

Much Scholarly Ink has been Spilled over the Question of What constitutes dance in different societies. Several attempts have been made to create a universal category for dance that would enable dance scholars to transcend this fundamental question and get down to the business of conducting research, secure in the knowledge that all of their colleagues understand the basic definitions of “dance.”None of the current definitions takes into account dance and dance events in societies such as those of the Islamic areas of the Middle East, Central Asia, and North Africa where the term for dance (usually the Arabic word raqṣ) can possibly bear powerfully negative or, at least, ambiguous connotations. While dance, and a word to denote that activity, exists and we can perhaps come to an agreement over what constitutes dance, an even more crucial issue is what dance is not in an Islamic environment.