bluuebunny/crossref_metadata_2025_split huggingface dataset:
All‐pole low‐pass digital filters with (2m‐ 1)‐th flat and r‐th equiripple group delay
Authors: Kato Kyoto , Takebe Tsuyoshi 
Published: July 2007

AbstractAs is well known, there are two kinds of constant delay all‐pole low‐pass digital filter functions: maximally flat type and equiripple type. In some cases of waveform transmission, transfer functions with inter mediate characteristics between the two forementioned types are preferable. This paper presents such transfer functions called (M‐r)FD function. In the n‐th order function, the delay flatness is reduced from the maximal order nO = (2n ‐ 1)‐th to (2m ‐ 1)‐th, where m < n. Then equiripple functions with a total of r maxima and minima of delay are derived utilizing the resulting r( = n – rn) degrees of freedom.The derivation of the transfer function is based on the method by Fettweis, i.e., in other words, the function providing the max‐ finally flat delay is obtained by forming the continued‐fraction expansion of tanh of the constant delay and truncating its expression at the n‐th‐term. Among n coefficients α2 of the expression, r from the last are given small deviations. While maintaining the (2m‐1)‐th flatness at zero frequency, an approximation is made by the traditional Newton‐Raphson method so that the delay deviation from the constant exhibits an equiripple behavior with the width of ±Δτ the (M‐r)DF function was derived for the case where the delay at τ = 0 is specified and for the case where the constant delay band width is specified. Keeping constant, the bandwidth for constant delay in the derived characteristics is increased with the increase of the number of ripples. the derived functions are summarized in a table.
Roundoff noise analysis and optimal synthesis of two‐dimensional recursive digital filters based on the fomasini‐marchesini model
Authors: Hinarnoto Takao , Hamanaka Takashi , Maekawa Sadao 
Published: July 2007

AbstractBased on the Fornasini‐Marchesini local state‐space model, a two‐dimensional round‐off‐noise analysis is carried out from which a new expression of the output‐noise variance is derived. an 12‐norm dynamic range scaling is also considered for the model. Then a general technique is developed for synthesizing the optimal model structure which minimizes the output‐noise power due to roundolf subject to a scaling constraint on the state variables. the synthesis utilizes a 2‐D similarity transformation matrix that is not block‐diagonal but general, and it requires solving only one optimization problem. Thus, the proposed synthesis is quite simple.
Finite element simulation for the design of an ultrasonic cleaning tank
Authors: Ando Ei'Ichi , Kagawa Yukio 
Published: July 2007

AbstractThis paper describes the application of the finite element method to simulation of an ultrasonic cleaning tank which consists of a liquid bath with vibrating plate walls. the vibration of a plate, from which the ultrasonic radiation takes place, is analyzed without loading, and it is shown that the location where the erosion occurs corresponds to the region of maximum stress in plate bending. Sound pressure distribution in the liquid bath, which is surrounded by the vibrating plate walls, is then considered as a two‐dimensional model in which the coupling between the plate vibration and the sound pressure in the liquid is taken into account. Some numerical demonstrations are made, which is compared with the measured results. the technique has again proved to be a useful means of solving problems of this kind.
Differential companding PCM by using optimum differential bit
Authors: Uchiyama Hiroki , Yamada Wasaku , Suzuki Masamitsu 
Published: July 2007

AbstractTwo speech coding methods combining dif ferential PCM (DPCM) with near instantaneous companding (NIC) are proposed in this paper. In general, if NIC is applied simply to DPCM, then the waveform cannot be reconstructed in the decoding process because of the bit removal during compression. to solve this problem, a method has been proposed which is based on the accumulation of the removed bits, but the companding ratio in this case is not sufficient for low bit rates.In Method I proposed in this paper the compressed differential data obtained by NIC of the differential data are modified to minimize the error between the original data and the data decoded sequentially, sample by sample, for the given number of compressed bits. Method II is similar to Method I, but an optimum scale factor is chosen from three adjacent values. Thus, the error power is minimized over the block. Segmental SNR is used as a quality measure, and the results of the computer simulation show that higher speech quality is obtained than in the case of first‐order predictive ADPCM (ADPCMf).The hardware realization of the proposed methods is extremely simple because both coding and decoding require merely additions and subtractions. This article presents the principle of the methods and the results of the simulation.
A method for designing IIR quadrature mirror filters
Authors: Takebe Tsuyoshi , Tsuji Toshiaki 
Published: July 2007

AbstractIn the subband coding system which is a low bit rate speed transmission one, a multirate quadrature mirror filter (QMF) bank is used by which voice signals are divided into two or more frequency bands and recombined. In this paper, a design method for two‐band analysis and synthesis IIR QMF is treated. For the phase characteristics being allowed to be nonlinear, the conditions to be satisfied by factors of the IIR QMF transfer function are known and, based on it, a design method of the transfer function by a successive approximation is known. the method in this paper does not use successive approximation. an analog filter with simultaneous Chebyshev characteristics in both the pass‐and stopbands is designed so that its squared magnitude response has an odd symmtry around its half‐magnitude point on the logarithmic frequency scale. Then it is bilinear transformed into a digital filter so that the analog half‐magnitude frequency is mapped onto the point with the digital frequency of w = π/2T. By combining this filter and the high‐pass filter obtained by shifting the former by w π/T, an exact QMF response can be obtained with analytical rigor. A design example is also presented.
Equivalent property between network analysis using virtual capacitors and steepest descent method
Authors: Asai Hideki 
Published: July 2007

AbstractGlobal and stable numerical analysis algorithms of nonlinear network equations, which contain functions that are not monotonically increasing or whose differential coefficients vary broadly, include the homotopic method studied in nonlinear programming and the methods based on the insertion technique of virtual capacitors developed in Circuitsimulation. This paper shows first that these methods are almost essentially equivalent, and that the standard steepest descent method is equivalent to analyze state equations constructed by the insertion of virtual capacitors by implicit numerical integration. Moreover, a backward SD method is proposed based on the implicit use of the steepest descent method. Thic method is applied to linear and nonlinear systems, and its equivalency with the algorithms in the Circuitsimulators SRP and ASTAP using the concept of virtual capacitors is investigated. Finally, this method is applied to dc analysis, etc., of nonlinear resistive networks, and its effectiveness is verified by comparison with the results of analysis by the ASTAP method.
Generalized hyperplane methods for generating Λ‐extreme points and trade‐off rates for multiobjective optimization problem
Authors: Sakawa Masatoshi , Yano Hitoshi 
Published: July 2007

AbstractThe hyperplane method is a generalized scalarization technique for the traditional typical scalarization problem to determine the Pareto‐optimal solution for the multi‐objective optimization problem. This paper presents a generalized hyperplane method to determine the A‐extreme point, which is a generalization of the Pareto‐optimal solution. A situation is considered in which the decisionmaker specifies the A‐extreme points, and his or her preference is to be estimated.‐ It is shown that the trade‐off rate, which is considered as useful information, can be represented by a Lagrange multiplier obtained by solving the generalized hyperplane problem.
Design of three‐dimensional recursive digital filters with symmetry
Authors: Hinamoto Takao , Nakatsuji Akihiro , Maekawa Sadao 
Published: July 2007

AbstractThis paper discusses a useful design method for three‐dimensional recursive digital filters approximating the desired amplitude response with spherical or cubic symmetry and the constant group delay. the filter structure is chosen so that the denominator is of a separable form, composed of one‐dimensional polynomials of the same form, and the numerator is composed of a mirror‐ image three‐dimensional polynomial with 48‐ hedral symmetry. In the filter design, the denominator and the numerator approximate the phase and the amplitude responses, respectively, which are designed independently. the proposed method is advantageous since the required computation is relatively small and the numerator is determined by solving a linear equation. the stability of the filter is ensured by its structure.
A systematic method of synthesizing systolic arrays using a data dependence graph
Authors: Iiguni Youji , Sakai Hideaki , Tokumaru Hidekatsu 
Published: July 2007

AbstractWith the recent development of VLSI technology, the systolic array is considered as practically realizable, where a large number of processors are placed on a chip to perform a parallel computation. the systolic array is a dedicated VLSI, which has a hardware structure depending on the algorithm. Consequently, a problem is how to design the systolic array corresponding to the given algorithm. This paper proposes an automatic synthesis for the systolic array using the dependence vector representing the data dependence. It is noted first that the systolic array is determined by the vector along the projection direction and the vector along the computation direction of the data dependence graph. the constraint for the forementioned two vectors is derived for the systolic graph. the constraint for the forementioned two vectors is derived for the systolic array to be realizable. Then using the constraint, the systolic array is derived systematically. A feature of the proposed method is that more than one systolic array corresponding to an algorithm can be constructed without a duplication. the systolic array in which processors operate in different ways, can also be derived. Finally, the proposed method is applied to the matrix multiplication, convolution and LD decomposition, indicating its usefulness.
Bilateral constant‐resistance active variable attenuation equalizer
Authors: Takebe Tsuyoshi , Ogawa Keiji 
Published: July 2007

AbstractConstant‐resistance active variable attentuation equalizers using a bridged T circuit are used for bilateral communication channel. Usually, the auxiliary circuits for a variable series branch impedance and a variable parallel branch impedance are constructured separately. For one variable parameter of the equalizer characteristics (such as one bump height for a bump type), one variable element is needed for series branch and the other is for parallel branch. This paper presents a method for realizing each variable impedance with a series connectio of a resistor and a variabel voltage‐controlled voltage source. From the circuit analysis, it is found that both variable voltages are always related via a constant ratio. Hence, if one of the voltage sources is constructed, the other is simply its constant multiple which results in simplification of the equalizer circuit. Finally, a switched capacitor implementatio of a bumpshaped variable attenuation equalizer is presented for illustration.
Design of narrow‐band FIR filters using interpolation technique
Authors: Hoshino Masanori , Ikehara Masaaki , Takahashi Shin‐Ichi 
Published: July 2007

AbstractIt is an important realization of digital filters to reduce the amount of hardware, notably multipliers. This paper proposes a cascade connection of IFIR (Interpolated FIR) filters by which a steep characteristic can be obtained with a small number of multipliers in most cases. the reduction of the multipliers is achieved by the determination of the transfer function of the overall cascade connection (not each element) by using the Lnorm approximation. This method also has an advantage in that its central frequency can be determined arbitrarily. the cascade connection of several elements reduces the degrading of its characteristic caused by the quantized coefficients as shown in examples, since the conditions required for each element are relaxed in this structure.
Quaternary cyclic an codes and Lee‐type modular arithmetic distance
Authors: Shimada Ryosaku , Watanabe Takashi , Tanaka Takeshi , Ohkura Yoshiteru 
Published: July 2007

AbstractThe arithmetic an codes are useful for error detection or error correction in both arithmetic operation and digital data transmission. Especially, the cyclic an codes based on an even‐radix number system are considered to be practical. This paper presents a fundamental theory of quaternary arithmetic distance and symmetric quaternary number system using five numerals, −2, −1, 0, 1, 2.Following an introduction of the cyclic an codes, we describe a modular number system and some important properties of Lee‐type modular arithmetic distance. an elementary method to calculate the minimum distance of the codes is also provided.
Algorithms for finding internally disjoint paths in a planar graph
Authors: Suzuki Hitoshi , Akama Takehiro , Nishizeki Takao 
Published: July 2007

AbstractThree efficient algorithms for finding vertex‐disjoint trees and internally disjoint paths in a planar graph are presented. Given a planar graph G and nets consisting of terminals lying on the external boundary, the first algorithm finds vertex‐disjoint trees, each of which interconnects all the terminals of a net. the second algorithm determines the maximum number k of internally disjoint paths between two specified vertices in the planar graph G. the third algorithm really finds these k paths. the time complexity of the first algorithm is O(n), those of the second and third are o(n log n). Here n is the number of vertices of the given graph G.
A hardware implementation for a fast scaling algorithm in residue number system digital signal processing
Authors: Fujita Munenori , Kunieda Hiroaki 
Published: July 2007

AbstractIn residue number system digital signal processing, one major problem is the scaling operation. the general scheme for scaling has traditionally been to convert the number into an MRS (mixed radix system) format and then perform the scaling. This method includes problems such as the large number of hardware stages in the processing circuit and constraints on the selection of the scale number. This paper proposes a new method, where a direct modification of the Chinese remainder theorem is utilized to remedy the above problems. In the proposed scheme, the scale number can be set as a divisor of the module, and the residue number after scaling is determined by the operations in each residue number system. Using these changes, the memory capacity of the ROM is reduced and the ROM can be designed with 2 stages. Through these improvements the scaling speed of the circuit will also be improved.
Analysis of piezoelectric ceramic bending vibrators using interdigital electrodes both for poling treatment and for AC excitation
Authors: Oyama Sigeru , Hirose Seiji , Shimizu Hiroshi 
Published: July 2007

AbstractThe single‐plate ceramic bending vibrator, using interdigital electrodes for poling and excitation, has the remarkable features of high performance and reliability with little spurious response. This is in sharp contrast to the traditional bending vibrators with bimorph structure. This study aims at the description of the design principle for the bending vibrator with interdigital electrodes. A theoretical analysis is made using the conformal mapping, and a detailed discussion is presented on the relation of the capacitance ratio to the electrode dimensions and the poling voltage. Then the optimum condition is derived. A good agreement was observed by comparing the result of analysis and the experiment. It is shown that the capacitance ratio is less for the transversal coupling‐type bending vibrator, with the electrode finger being parallel to the direction of elongation, than for the longitudinal coupling type with the perpendicular direction.
LSI implementation scheme for general‐purpose high‐speed and coding rate viterbi decoder LSI
Authors: Kato Shuzo , Kubota Shuji , Ohtani Kouichi , Ishitani Tsunehachi , Miyahara Norio 
Published: July 2007

AbstractThis paper discusses the selection of the optimal device for LSI implementation of Viterbi decoder. The relation between the available number of gates and the performance of the decoder is described clearly. A method of reducing the number of gates for low‐and high‐speed LSI decoders, as well as their major performance, is described.To reduce the cost for LSI as the system LSI, it is important to maintain the versatility of the developed LSI. From such a viewpoint, general‐purpose, a highly efficient Viterbi decoder is considered by using a ROM and two kinds of LSI. The construction and the performance are discussed, aiming at an LSI implementation.The developed LSI operates at the frequency of 25 MHz or higher. It is applicable generally to the error correction with (N −1)/N coding rate. Compared with the Viterbi decoder using the same kind of LSI, the proposed LSI minimizes the number of chips and improves the speed by a factor of 1.5. By this elaboration, the device can drastically be reduced in size and cost, leading to an easier realization of a high‐speed, highly efficient and high‐gain error‐correcting system.
Analysis of a single server model with two queues having different service disciplines
Authors: Ozawa Toshihisa 
Published: July 2007

AbstractThis paper analyzes a single server model with two queues using the generating‐function method. Two service‐discipline models are used: a model in which the service discipline of one queue is “exhaustive” and that of the other queue is “gated”; and a model in which the service discipline of one queue is “exhaustive” and that of the other queue is “1‐limited.” For each model, the Laplace‐Stieltjes transform (LST) of waiting time distributions and mean waiting times are derived. By using the results, the difference of the mean waiting times in the two models is shown with numerical examples. It is possible to control the characteristics (e.g., the mean waiting times in each queue and their ratio, which depend on parameters such as the traffic density) of models with mixed service disciplines by changing the combination. Therefore, it is important to analyze these models for designing an integrated system which handles different traffic characteristics and required qualities.
Circuit simulation using waveform relaxation‐newton method
Authors: Urahama Kiichi 
Published: July 2007

AbstractThe following high‐speed technique is introduced into the waveform relaxation‐Newton (WRN) method: (1) the relaxation process starts from the predicted waveform; (2) the latent property in the time and the relaxation domain is utilized; and (3) iterative step width refinement, plus the window width adjustment to minimize the computation are proposed. A CMOS inverter chain was analyzed by the proposed variable window WRN method, and it was indicated that the window size control is useful not only in the Gauss‐Seidel‐WRN method, but also in the Gauss‐Jacobi‐WRN method, as well as in the case with a feedback. It is shown further that the computational complexity of the variable window WRN method is less than that of a similar waveform relaxation method and the interated timing analysis.
LSI and IC‐implementation of TDMA system—highly reliable and maintenance‐free TDMA equipment
Authors: Kato Shuzo , Morikura Masahiro , Umehira Masahiro , Enomoto Kiyoshi , Kubota Shuji 
Published: July 2007

AbstractThis paper aims for high reliability as well as reduction of hardware size, cost and development period for the time‐division multiplex access (TDMA) equipment, and proposes a new TDMA equipment architecture and modular construction. The fundamental approach employed in this paper is the digital realization of the analog circuit and the LSI implementation of the digital circuit. Then to realize TDMA equipment with a simple architecture and to realize a widely applicable LSI, TDMA equipment is reconstructed into a hardware‐oriented architecture. Based on the new architecture and the optimal function assignment to the modules, the following LSI and IC were developed. Six types for synchronization control, 11 types of LSI and IC for modulation‐demodulation (3 LSI, 4 MIC and 4 HIC), and 1 type of terrestrial network interface. By this development of LSI and IC, the hardware scale of TDMA equipment was reduced to one‐fifth, and the development period is reduced to one‐half compared with previous equipment. The maintenance‐free property is also achieved. The developed LSI and IC can be applied to various TDMA equipment in general with different TDMA frame and rate. For TDMA equipment to be developed in the future, the hardware‐scale and the development period can be reduced as in this case.
A method to construct constant weight t‐error correcting codes
Authors: Matsumoto Tsutomu , Imai Hideki , Saitoh Yuichi , Yamaguchi Kazuhiko 
Published: July 2007

AbstractThis paper proposes a construction method for constant weight t‐error‐correcting codes. These codes are nonsystematic t‐error‐correcting and all‐unidirectional‐error‐detecting (t‐EC/AUED) codes. The format of these codes is given by generalization of the Bose‐Rao code and the Kundu‐Reddy code, and a codeword of these codes is the concatenation of constant weight codes. Concrete methods to construct 3‐ and 4‐EC/AUED codes also are given. For example, 3‐EC/AUED codes of length 80 proposed so far have at most 246 codewords, whereas the proposed method gives a code having 251 codewords when Bose's method for encoding binary information words into constant weight words is used.
An efficient integer labeling method for solving systems of nonlinear equations with separable mappings
Authors: Yamamura Kiyotaka , Ochiai Makoto 
Published: July 2007

AbstractThe integer labeling method is one of the simplicial‐type homotopy methods for solving systems of nonlinear equations. In this method, matrix operations are not necessary and an approximate solution can be generated only by function evaluations. Thus, the algorithm becomes quite simple and can easily be programmed.However, since the integer labeling method uses simplicial subdivision, the amount of computations grows exponentially with the system size.For the vector labeling method, which is another type of homotopy methods, an efficient algorithm using a rectangular subdivision has been proposed.For the integer labeling method, however, such an efficient technique has not been proposed because integer labeling on rectangles is essentially impossible.This paper proposes an efficient integer labeling method for solving systems of nonlinear equations with separable mappings. Similarly to the conventional method, the proposed method labels integers on simplices. However, by making use of the separability and the concept of the rectangular subdivision, the number of function evaluations is reduced significantly.In the proposed method, function evaluations are not necessary as long as the labeled simplex is moving in the identical rectangle, and when it moves into another rectangle, only one component of the function in that direction needs to be computed. Hence, with the increase of the system size, considerable improvements of the computational efficiency can be achieved.