bluuebunny/crossref_metadata_2025_split huggingface dataset:
Experience with the central server model on a lightly-loaded system
Authors: Agrawala A. K. , Larsen R. L. 
Published: January 2007

Analytic models potentially provide an elegant means of estimating the performance of computer systems at a rather nominal cost. The assumptions which must be made about a system in order to construct a mathematically tractable model, however, are usually severe enough to cast doubt on the validity of the results produced by such a model. Further, relaxation of an assumption often renders an analytic technique inapplicable, such that simulation becomes the preferred approach to system modeling.
To investigate the boundary between analytic models and simulation models a computer program has been developed which provides a framework within which to develop and compare both analytic and simulation models. A general queuing network architecture has been adopted. The program is extensible with respect to analytic techniques, queuing disciplines and probability density functions.
Using this program, models of a lightly loaded batch multiprogramming system were constructed. The system was viewed as a network of servers preceded by queues. The central processing unit was one server and each I/O channel was treated as a separate server. The channels were organized in parallel with respect to each other, and in series with respect to the central processing unit. Tasks were viewed as tokens flowing through the network, being delayed by each server for queuing delays and service. Delays between task termination and initiation of a new task were modeled by additional servers operating in parallel to the I/O channel servers. An analytic solution was computed for this model for the steady state case with exponentially distributed service times and the first-come-first-served queuing discipline with unlimited capacity queues. Typical errors of 18% were observed for cpu utilization and I/O activity. The model was then modified to more realistically account for the behavior of partitions. The delay servers were modeled with unit capacity queues. This model was solved by simulation, yielding errors of 4% for cpu utilization and I/O activity.
When to stop a simulation run
Authors: Schwetman Herbert D. , Bruell Steven C. 
Published: January 2007

The use of an efficient stopping rule can assist in the achievement of accurate simulation results at a reduced cost of computation. Conversely, with an inefficient stopping rule, either in-accurate results or excessive costs can occur. The problem of deciding when to stop a simulation model of a computer system is further complicated by the fact that a key parameter, response time at a service center, is not an independent random variable. In spite of this complication, procedures for determining the number of observations of response time variables required to achieve statistically valid results have been developed.
This paper presents, via the case-study approach, the effects of using an insufficient number of observations of response time and the improved accuracy which is obtained when an efficient stopping rule is used. While these results are not new, they are perhaps not widely known in the field of simulation of computer systems. We therefore view the contribution of this paper as that of demonstrating the application of such results in this field, so that other researchers can make use of them. An appendix includes a brief description of the algorithms used.
Testing of microprograms using the lockheed SUE microinstruction simulator
Authors: Davidson Scott , Tao William 
Published: January 2007

Each microinstruction of a microprogram written for a horizontally microprogrammable machine can affect the machine state in quite complex ways. A microinstruction simulator that allows a microprogrammer to examine the entire processor state is a valuable tool in the testing of microcode.
The debugging aids made available by the simulator, as well as the design technique used in the construction of a microprogram, will tend to determine the strategy used in testing the microcode.
This paper describes one such simulator and a set of testing strategies found useful in working with it. The machine simulated is the Lockheed SUE, a 16 bit microprogrammable minicomputer. The SUE Simulator not only allows the display of the processor state, but allows most of the state to be modified by the user.
A testing strategy using the features of the Simulator is presented for a microprogram written using bottom-up techniques. The Simulator is also shown to be useful in testing microprograms written using other methods, and in simplifying and speeding the testing process.
Finally, the use of the Simulator in examining the effects of modifications to the processor on the microprogramming task is discussed.
Workshop session
Authors: Segal Ronald , White Norman 
Published: January 2007

The management requirements and characteristics of large simulation projects will be explored during this session. Note that, as simulation technology matures, there is an increasing demand for the development of useful products within specified time and resource constraints - a requirement not unique to simulation. A great deal of recent attention, for example, has been devoted to the management of business data processing programming projects. Both classical methods for project management like PERT and CPM, and the newer methods such as chief programmer team organization and top down design, have been extremely useful in this area.
Unfortunately, simulation studies differ in many ways from the business data processing applications that have been described. As an example, it is not clear that a management approach suitable for the development of an accounts receivable system is best for the design and implementation of a large simulation model. Using the techniques now recognized as useful for other types of programming projects as a starting point, approaches and guidelines for managing large simulation projects will be discussed in this workshop.
Production and representation of computer system simulation models
Authors: Iazeolla Giuseppe G. , Martinelli Enrico , Tedone Orazio 
Published: January 2007

The problem of the production of computer systems simulation models is dealt with. The software production process is generally carried out without considering the performance aspects of the whole system: performance evaluation is generally made later, once the system has been implemented. In this paper the process of the development of a system simulation model which can be used to discover aspects of system behaviour before the system is completely implemented is investigated. This process starts from the knowledge of the technical specifications of the software system and then, proceeding by levels of abstraction, yields a top-down model specification in terms of resources, resource requests, resource activities, etc.
J.D. Noe and G.J. Nutt's Evaluation Nets are used for the progressive model development. E-nets provide a formal system representation which can either be supplied to a system for the automatic generation of the simulation code, or used for the straightforward coding of the simulation program in any language.
Processor System Modeling - a language and simulation system
Authors: Pfisterer Fredrick , Purdy William C. , Lehmann Leonard 
Published: January 2007

There is a need for a language and simulation system that computer systems designers (rather than programmers) can use to build and exercise models of computer systems. The major characteristics of such a language and system are presented.
A brief overview of the Processor System Modeling (PSM) system, consisting of PSM language input, translation to Simscript, execution, and interactive post processor operation on a trace of the results, is outlined.
The different types of statements in the language of the PSM system and their use are described. The major features of the language and system, which allow it to be used for constructing simple models quickly while still permitting complex systems and behavior to be simulated, are presented. Examples are used to demonstrate the use of these features, to illustrate the structure of the language, and to show its naturalness for the job of simulating computer systems.
The reasons for having a post-processor rather than statistics gathering routines are given. The two types of queries that may be made through the post-processor, about sequential events and about statistics, are described and examples given.
A proposal for a hardware text processor
Authors: Mukhopadhyay Amar 
Published: January 2007

Because of the tremendous growth in the terminal-oriented users community, software text editor is increasingly becoming a significant overhead for the computing systems. The files being manipulated by text editors are usually small but undergo rapid growth and development in its short-lived life-cycle. A look into the basic command structure of these text editors reveal that the operations performed by them fundamentally consist of pattern matching, pattern transformation, pattern deletion and insertion, and management of a set of counters and pointers.
It is proposed in this paper that a specialized front-end processor with built-in string processing hardware provide a natural solution to the problem. This paper presents a possible architecture and logical capabilities of such a machine as an embellishment of microprocessors to be used for intelligent terminals. In the process, the structure of a general purpose non-numeric processor is evolved.
Performance evaluation and improvement of a dynamically microprogrammable computer with low-level parallelism
Authors: Tomita Shinji , Shibayama Kiyoshi , Kitamura Toshiaki , Hagiwara Hiroshi 
Published: January 2007

A new microprogrammable computer with low-level parallelism was built and has been utilized as a research vehicle for solving different classes of research-oriented applications such as real-time processings on static/dynamic images, pictures and signals, and emulations of both existing and virtual machines including high (intermediate) level language machines.
The design goal of a research-oriented computer, QA-1, was to achieve a high degree of processing power and system flexibility by means of a low-level parallel processing organization combined with dynamically microprogrammable control. This paper describes the QA-1's architecture-tailorability to different classes of emulations for existing machines such as the PDP-11/40 and the HITAC-10, and for high-level language machines such as, BASIC and PASCAL machines. All the results obtained from these experiments, together with the ones from well-defined applications such as a real-time color animation presented in another paper, have clarified some drawbacks of the QA-1 in its architectural uniformity, high functionality and microprogram productivity. On the basis of these final evaluations of the QA-1, this paper proposes a new architecture for a next generation computer, QA-2.
IBM 4341 hardware/microcode trade-off decisions
Authors: Kleinsteiber James R. 
Published: January 2007

The design of IBM's 4341 Processor, as with other processors, involved many cost/performance tradeoffs. The designer is continually under pressure to increase processor speed without increasing cost or to decrease processor cost without decreasing performance.
This paper will examine some of the engineering decisions that were made in the attempt to make the 4341 a high-performing yet low cost processor. These decisions include searching for, or developing, algorithms that make the best use of hardware properties, such as data path width, arithmetic/logical operations and special functions. Functions were sought such that a small amount of added hardware would go a long way towards improving system performance. Hardware designers, microcoders and performance analysis people worked together to implement instructions, functions and algorithms with the proper mixture of hardware functions and microcode in order to build a viable processor.
Some specific functions will be covered to examine a few of the decisions. The TEST UNDER MASK performance problem will be discussed with its resulting implementation decision. The method of using EXCLUSIVE OR to clear storage and the resulting algorithm design will be shown. Other topics to be discussed include multiple hardware functions and the resulting effect on floating point, fixed point and decimal multiply; the divide function and its effect on floating point and fixed point divide; and the effect of an 8-byte data path for decimal arithmetic.
Hardware microcontrol schemes using PLAs
Authors: Papachristou Christos A. 
Published: January 2007

Four new schemes for microprogram control design with programmable logic arrays (PLAs) are proposed. The general structure of the first three schemes consists of three units namely, the microcode memory (ROM), the microsequencer PLA, and a register-counter. The basic idea is to store only branching information, by means of control constructs or transactions, in the PLA(s). These transactions have simple jump-type or continue-type formats with only the jump being embedded in PLA(s).
A more general structure, scheme 4, is also proposed with the objective to generate powerful transactions implementing complex control constructs, such as microsubroutines, nested microprogram loops, etc., in addition to multiway branch capability. These transactions contain horizontally formatted directive bits and, hence, they exhibit a measure of parrallelism. The aim is to transform the sequencing structure of a microprogram into a “program” composed of these transactions. However, a directive-driven processor is required to execute each transaction in order to produce the desired address.
PACE - a microprogram evaluation system
Authors: Skibbe Robert E. 
Published: January 2007

This paper describes PACE (Product Assurance Code Evaluation) System, a tool for evaluating microprograms. PACE incorporates both static analysis and dynamic analysis capabilities and it provides features that enable systematic and comprehensive evaluations of large-scale microcoded systems.
The PACE static analysis capability performs a control flow analysis of the code being evaluated, reports various anomalous program constructs, and generates a program flow graph that is subsequently employed by PACE's dynamic analysis procedures.
The PACE dynamic analysis capability uses encoded execution trace data to produce microcode test-coverage reports and formatted code-execution traces. The dynamic analysis capability provides quantitative code execution coverage data that enables an assessment of testing thoroughness and is useful in the identification of effective regression test cases.
Measuring simultaneous events in a multiprocessor system
Authors: Hercksen Uwe , Klar Rainer , Kleinöder Wolfgang , Kneißl Franz 
Published: January 2007

In the hierarchically organized multiprocessor system EGPA, which has the structure of a pyramid, the performance of concurrent programs is studied. These studies are assisted by a hardware monitor (ZÄHLMONITOR III), which measures not only the activity and idle states of CPU and channels, but records the complete history of processes in the CPU and interleaved I/O activities. The applied method is distinguished from usual hardware measurements for two reasons: it puts together the a priori independent event-streams coming from the different processors to a well ordered single event stream and it records not only hardware but also software events. Most useful have been traces of software events, which give the programmer insight into the dynamic cooperation of distributed subtasks of his program. This paper describes the measurement method and its application to the analysis of the behaviour of a highly asynchronous parallel algorithm: the projection of contour lines from a given point of view and the elimination of hidden lines.
This work is sponsored by the Bundesminister für Forschung und Technologie (German Federal Minister of Research and Technology).
Self assembly times in DNA-based computation
Authors: Baryshnikov Yuliy , Coffman Ed , Momčilović Petar 
Published: January 2007

Speed of computation and power consumption are the two main parameters of conventional computing devices implemented in microelectronic circuits. As performance of such devices approaches physical limits, new computing paradigms are emerging. Two paradigms receiving great attention are quantum and DNA-based molecular computing.
This paper focuses on DNA-based computing. This concept can be abstracted to growth models where computational elements called tiles are self-assembled one by one, subject to some simple hierarchical rules, to fill a given template encoding a Boolean formula. While DNA-based computational devices are known to be extremely energy efficient, little is known concerning the fundamental question of computation times. In particular, given a function, we study the time required to determine its value for a given input. In the simplest instance, the analysis has interesting connections with interacting particle systems and variational problems.
Computation with hyperexponential functions
Authors: Li Ziming , Zheng Dabin 
Published: January 2007

A multivariate hyperexponential function is a function whose
"logarithmic derivatives" are rational. Examples of
hyperexponential functions include rational functions, exponential
functions, and hypergeometric terms. Hyperexponential functions
play an important role in the handling of analytic and
combinatorial objects. We present a few algorithms applicable to
the manipulation of hyperexponential functions in an uniform
way.
Let <i>F</i> be a field of characteristic zero, on
which derivation operators
&delta;<inf>1</inf>,...,&delta;<inf>&ell;</inf>
and difference operators (automorphisms)
&sigma;<inf>&ell;+1</inf>,...,
&sigma;<inf>m</inf> act. Let <i>E</i>
be an <i>F</i>-algebra. Assume that the
&delta;<inf><i>i</i></inf> for 1
&le; <i>i</i> &le; &ell; and
&sigma;<inf><i>j</i></inf> for
&ell; + 1 &le; <i>m</i> can be extended to
<i>E</i> as derivation and difference operators.
Moreover, these operators commute with each other on
<i>E.</i> A hyperexponential element of
<i>E</i> over <i>F</i> is defined to be a
nonzero element <i>h</i> &isin;
<i>E</i> such that
&delta;<inf>1</inf>(<i>h</i>) =
<i>r</i><inf>1</inf><i>h</i>,
...,&delta;<inf>&ell;</inf>(<i>h</i>)
=
<i>r</i><inf>&ell;</inf><i>h</i>,
&sigma;<inf>&ell;+1</inf>(<i>h</i>)
=
<i>r</i><inf>&ell;+1</inf><i>h</i>,...,&sigma;<inf><i>m</i></inf>(<i>h</i>)
=
<i>r</i><inf><i>m</i></inf><i>h</i>
for some <i>r</i><inf>1</inf>,...,
<i>r<inf>m</inf></i> &isin;
<i>F</i>. These rational functions are called
(rational) certificates for <i>h.</i>
Mobile mathematics communication
Authors: Belov Nadya , Koeck Colin , Krandick Werner , Shaffer Joshua 
Published: January 2007

We present a system [1] that allows wireless smartphones to be
used for mathematics communication, that is, for the creation and
exchange of mathematical formulas, diagrams, and text between two
or more participants. The system enables two or more persons with
smartphones or traditional computers to participate in a session.
Each of the participants may convey textual, graphical and
mathematical information to the other participants. Users can draw,
edit, and label geometric shapes, send chat messages, and compose
formulas. A turn taking mechanism moderates the communication. The
system also supports the integration of services that can be used
to provide individual users with additional functionality.
Currently, a LATEX rendering service is available to allow users to
create and share mathematical formulas in typeset quality.
Wireless smartphones are becoming the medium of choice for
improvised synchronous collaboration since increasing numbers of
users carry their smartphones at all times. It is true that the
small size of the devices---while necessary for their
ubiquity---limits the complexity of collaborative tasks that can be
carried out effectively. On the other hand, there is a need to
capture inspiration, to access and evaluate information on the go,
and to make decisions on the spot.
The domain of mathematics is ideally suited to explore---and
push---the limits of smartphone communication. The challenge of
representing mathematics in typeset form has led to the development
of document preparation systems such as TEX, LATEX, and LYX which
are in widespread use today. Mathematical handwriting recognition
continues to push the limits of general handwriting recognition
[2]. Many of the cognitive challenges that arise in mathematical
collaboration also arise in intellectual teamwork in other
domains.
Some of the challenges of developing a system for mobile
mathematics communication are posed by the input and output
limitations of the devices and the enormous heterogeneity of the
available hardware platforms.
We use the Treo 600/650 as our hardware platform. Our software
is written in pure Java and can be run on any platform that
supports the Java Virtual Machine. Our software architecture makes
it easy to add new local or remote services to enhance the
communication.
The poster presents use-case diagrams, architecture diagrams,
and a series of screenshots that describe the user's interaction
with the system. The poster also shows how we solved the problems
of cross-referencing and turn-taking in mobile collaboration. A
7.5-minute video shows users interacting with the system.
A subjective judgment study of polygon based curved surface imagery
Authors: Atherton Peter R. , Caporael Linnda R. 
Published: January 2007

In the past computer graphics efforts, several researchers have demonstrated that polygon models can be used to produce images of curved surfaces that appear to be smooth and accurate. However, the authors know of no attempt to appraise such imagery by using multiple human observation ratings.
The effectiveness of curved surface imagery generated from polygon models was investigated in a judgment study. Research subjects evaluated sphere model imagery derived from several polygon densities and shading procedures including flat shading, shade interpolation (Gouraud) and normal interpolation (Phong). Results of the evaluations indicated that little was gained by reducing the average polygon areas below approximately 110 pixels per polygon for spheres of 95 pixel radii displayed on a 512 x 512 resolution monitor. Evaluations for both shade and normal interpolution placed polygon image quality reasonably close to an “ideal” image. Although the evaluations indicated that normal interpolation was slightly superior to the shade interpolation, shade interpolation required significantly less computation. Most significantly, results from this study provide strong support for the notion that polygons can be used effectively to produce smooth shaded imagery of curved surface models.
Estimating the distribution of software complexity
within
a program
Authors: Moher Thomas G. 
Published: January 2007

This paper proposes an approach to the characterization of complexity within computer software source texts. We estimate the information content of individual program tokens as the basis for a relative ordering of tokens by their 'uncertainty' or 'perculiarity' within the context of the program in which they reside. The analysis method used is in part an extension of software science methods. The information gained from the analysis highlights language usage anomalies and potential errors. This information may be useful in guiding software review activities.
More theoretical work and experimental validation will be necessary before the analysis technique may be used in a productive environment.