bluuebunny/crossref_metadata_2025_split huggingface dataset:
Constant failure rate—A paradigm in transition?
Authors: McLinn James A. 
Published: July 2007

AbstractAs a science, reliability has now entered middle age, having achieved almost 40 years of recognized modern practice. As we move into the new decade of the 1990s it is appropriate that we review the status of modern reliability. The history of science has lessons for us to learn concerning the nature of paradigm changes. Clearly some reliability practitioners have had difficulty changing their own world views as scientific knowledge has increased and the conditions of the profession have changed.The very first generalized model for reliability was based upon electron tube life data from the early 1950s. It was with these old types of complex and failure prone products upon which the original reliability model was developed and generalized. This first model dictated that the failure probability density of electronics follows the exponential law which implies that the electronics will show constant failure rates during their useful lives. To get to the constant failure rate period, an infant mortality was traversed and about 10 per cent failures observed. The reliability beliefs of the 1950s when combined with the product successes of the 1960s has created a reliability paradigm problem that first became apparent in the late 1970s. Improved quality and design effort with new technologies and knowledge about effective screening changed the conditions. Modern semiconductor electronic products do not follow the original electron tube reliability model. The applicability of this original model and the subsequent thinking that it led to must now be questioned. It is time to create a new and better paradigm to replace the defunct exponential law.
What is wrong with the existing reliability prediction methods?
Authors: Wong Kam L. 
Published: July 2007

AbstractInaccurate reliability predictions could lead to disasters such as in the case of the U.S. Space Shuttle failure. The question is: ‘what is wrong with the existing reliability prediction methods?’ This paper examines the methods for predicting reliability of electronics. Based on information in the literature the measured vs predicted reliability could be as far apart as five to twenty times. Reliability calculated using the five most commonly used handbooks showed that there could be a 100 times variation. The root cause for the prediction inaccuracy is that many of the first‐order effect factors are not explicitly included in the prediction methods. These factors include thermal cycling, temperature change rate, mechanical shock, vibration, power on/off, supplier quality difference, reliability improvement with respect to calendar years and ageing. As indicated in the data provided in this paper any one of these factors neglected could cause a variation in the predicted reliability by several times. The reliability vs ageing‐hour curve showed that there was a 10 times change in reliability from 1000 ageing‐hours to 10,000 ageing‐hours. Therefore, in order to increase the accuracy of reliability prediction the factors must be incorporated into the prediction methods.
A better method for verifying production reliability
Authors: Coppola Anthony 
Published: July 2007

AbstractVarious schemes have been created for verifying that reliability is not degraded during production. These include the periodic performance of reliability tests during production, three versions of an all‐equipment reliability test plan and Bayesian approaches. Each method has its drawbacks. The purpose of all of these is to verify that the production process is continuing to produce products of acceptable reliability, for which the long‐existing tools of statistical process control are directly applicable and advantageous. A method of verifying production reliability based on the use of a control chart for failure rate is proposed as a better way than the current standards and alternatives discussed in this paper.
Some procedures for decision making in controlling high yield processes
Authors: Xie M. , Goh T. N. 
Published: July 2007

AbstractStatistical process control based on the cumulative counts of conforming items instead of occurrences of non‐conformances has proved to be useful for the manufacture of high‐quality products. In this paper we study some interesting and useful issues of using cumulative counts in practice. The general problem in the control of high‐quality products is first discussed, which leads to the calculation of the probability that a process is out of control when a single non‐conforming item is detected. A decision graph is introduced with which we can easily judge whether the process is out of control when a non‐conforming item is observed after a number of conforming ones, accompanied by the certainty level of this judgement. Next, using the equivalence of information on one non‐conforming item found in a number of inspected items to that on zero non‐conforming items in a smaller sample, we give a method for choosing a new starting point to reset the cumulative count after the detection of the non‐conforming item. The procedures are all statistically justified and have the practical merit of simplicity in actual applications.
A comparison of control charts from the viewpoint of change‐point estimation
Authors: Nishina Ken 
Published: July 2007

AbstractISO/DIS 7870 has presented the cumulative sum chart, the moving average chart, and the exponentially weighted moving average chart as control charts using accumulated data. In this paper, we compare the three control charts in terms of change‐point estimation. We show the probability distribution, the bias and the mean square error of the change‐point estimators using a Markov process and Monte Carlo simulation. These control charts have almost equivalent performances based on average run length considerations when parameters of each control chart are set appropriately. However, from the viewpoint of change‐point estimation we recommend the CUSUM chart.
Fault and cause diagnosis of casting defects: Case study no. 2
Authors: Sweeting F. B. J. , Thorpe W. R. , Pettitt A. N. 
Published: July 2007

AbstractUnder pressure for cost reduction, a semi‐automated grey iron foundry was experimenting with alternative supply sources of the moulding sand additives, bentonite and coal dust. During a period when increasing quantities of possible replacement materials were being blended with current supplies it was noticed that the previously high or erratic level of rejects in a small group of products was progressively improving. In the absence of a real understanding of the reason for the improvement and in an endeavour to ensure that adequate safeguards were in place to avoid any relapse, a statistical examination was undertaken of the green sand and metal subsystems.The behaviour of the variables in these subsystems was analysed for a datum period before and after the decision to change the sources of supply. Using existing process records and applying appropriate statistical techniques a clear indication was obtained that factors outside those of bentonite and coal dust were also involved in the improvement.The use of factorial analysis demonstrated the relative significance of the sand and metal variables and the existence of any interactions. The use of box and whisker plots gave a good indication of the desirable control limits for the key variables. Analysis of the follow‐up period revealed a reduction of 90 per cent in the level of rejects for one high volume line.
Quality‐based design by probability optimization
Authors: Parkinson D. B. 
Published: July 2007

AbstractA primary requirement of quality‐based design and offline quality control methods is the determination of nominal design parameter values which are such as to minimize the risk that the resulting device or system will function inadequately, or fail, under specified operational conditions. It may also be desirable to control the degree of variability in certain properties or outputs of the device or system. Both requirements are to be satisfied, in the presence of unavoidable tolerances on component parameters, which may also have been optimized, using a cost balance criterion.It is shown that these requirements can be expressed in terms of constrained optimization of probability contents of defined sets in the space of the design parameters and that the probabilities can be estimated using well‐established convolution methods, permitting optimization by standard numerical methods. This procedure avoids the need for simulation or the use of specialized statistical techniques based on analysis of variance, and may permit solution of such problems by non‐specialists using available computing facilities. It does, however, require a suitable probability model to be associated with the design variables of interest. Analytic and numerical examples are presented and discussed.For those readers unfamiliar with the theoretical methods employed, Section 1.2 provides a qualitative description of the method and may be read in conjunction with the examples of Section 3.
Detecting test set hardware degradation using statistical data modelling
Authors: Potter Randall W. , Sturm George W. 
Published: July 2007

AbstractIn electronic device manufacturing, a significant amount of time is spent testing the product using sophisticated test sets. These test sets routinely develop hardware problems that cause disruption of the manufacturing process. This paper discusses how computerized networking of test sets can be used to systematically monitor and detect these hardware problems. A statistical methodology for modelling and analysing test set data is presented, along with a detailed specific example.
Reliability testing of polyimides for GaAs MMIC applications
Authors: Conlon R. F. B. , Turner J. A. 
Published: July 2007

AbstractSubmission of test components and representative MMICs to an extensive range of environmental and endurance tests has confirmed the suitability of polyimide as a dielectric layer for a high performance, reliable GaAs foundry process. In particular, the ability to withstand 1000 hours of 85 per cent RH, 85°C humidity testing has been demonstrated.
Compact electro‐thermal simulation of ESD‐protection elements
Authors: Russ C. , Gieser H. , Egger P. , Irl S. 
Published: July 2007

AbstractNumerical simulations at the circuit level can improve the understanding of the behaviour of protection structures under system aspects. Full protection circuits with the influence of HBM ESD tester parasitics and additional parasitic elements in the circuitry have been investigated. Compact electro‐thermal models for single protection elements (diodes and snapback nMOSFETs) have been developed. They help to explain differences between expected ESD‐hardness and HBM‐failure thresholds of protection structures.
Reliability prediction of pipes and valves
Authors: Strutt J. E. , Allsopp K. , Ouchet L. 
Published: July 2007

AbstractA methodology for predicting the reliability of pipes and valves and for assessing the impact of testing and inspection policy on the safe life of a component is described. The method is based on the stress‐strength interference model and enables a combination of physical models and engineering experience to be used to estimate means, variances and associated uncertainties in the life of a component. Particular attention is paid to modelling failures arising from underlying degradation processes. Bayesian routines are used to update the model parameters and to reduce uncertainties using inspection, monitoring or test data. The paper describes the principles of the method together with examples related to subsea gate valves and pipelines.
Reliability analysis for the design of an inflator
Authors: Teng Sheng‐Hsien , Ho Shin‐Yann 
Published: July 2007

AbstractProduct reliability is determined at its design stage and must be identified to adequately evaluate the feasibility of the current design. Reliability prediction provides the means to design verification and optimum modification. A design team must detect any potential reliability problems before the completion of the product design. This paper presents an approach to include the use of a reliability block diagram for reliability prediction, a fault tree analysis for detecting possible failures, and the axiomatic design procedure in the product design evaluation process. The discussion includes the reliability analysis of a passenger side airbag inflator design. The modification of the current inflator design is also discussed.
Voltage contrast studies on 0·5 μm integrated circuits by scanning force microscopy
Authors: Böhm Christoph , Sprengepiel Jörg , Kubalek Erich 
Published: July 2007

AbstractA scanning force microscope (SFM) test system is used for voltage contrast studies on 0·5 μm integrated circuits. Waveform measurements are performed on passivated 0·5 μm conducting lines up to 4 GHz. Additionally two‐dimensional measurements at 10 MHz demonstrate the potential for device internal function and failure analysis in the sub‐μm regime by direct correlation between voltage contrast and quantitative topography images.
Measuring system and software reliability using an automated data collection process
Authors: Murphy Brendan , Gent Ted 
Published: July 2007

AbstractThe factors which affect the behaviour of the customer's computing environment, which is undergoing a revolution away from a server or timeshare centric model to a client/server or distributed model, can no longer be identified solely through using traditional methods of data collection. Digital Equipment Corporation has developed an automated data collection process, collecting on‐system data logging information from customer sites that has yielded consistent, quantitative, high integrity information. This information has been used to proactively focus on direct product and process improvements. This paper describes the on‐system data logging process and analysis methodology used by Digital to measure system, product and operating system reliability with examples of the application of the techniques that provide insight into the causes of failures.
Display of drawing‐type mail by successive geometric/pattern conversion method
Authors: Hayama Satoshi , Kanada Youji , Ueda Teruo 
Published: July 2007

AbstractIn the videotex communication service system, a new matrix function is planned. The drawing pad may be used in writing the mail, where handwritten patterns can be accepted. However, this type of mail is composed of geometric information, and the conversion to pattern information (G/P conversion) is required in the communication device to produce the output processing in the communication device in the low‐level terminal. This paper proposes a G/P conversion method (successive conversion), which suffers less delay in the start of the display and preserves the order of writing. In the successive conversion, the expansion of a geometric primitive and the transmission of the result of expansion are executed alternately. Only the rectangular region containing the part for which the expansion has been made is sent as the pattern data. The proposed method is applied to the drawing mail. It is shown that the processing required in the conversion is twice that of the straight system, where the result is sent after expanding all geometric primitives. It is also shown that the adequate speed of display for the character is 2.7 character/s, if it is displayed following the writing order.
Decision problem concerning security for cryptographic protocols
Authors: Fujiwara Toru , Taniguchi Kenichi , Kasami Tadao 
Published: July 2007

AbstractThis paper discusses the decision problem concerning security for such cryptographic protocols as the cryptographic key distribution protocols and the digital signature protocols. A cryptographic protocol and its utilization environment are considered secure if an opponent cannot know the secret message or forge a signature successfully by wiretapping or communication function is secure. This paper presents a sufficient condition under which the security problem is decidable. Dolev et al. also investigated the decision problem of the security, but they discussed only the simple case where the cryptographic key is not the object of manipulation (i.e., key generation and distribution are not included in the protocol), and a decision method is presented in which the decision can be made in a polynomial time. By contrast, this paper discusses the problem including the case where the cryptographic key can be an object of manipulation. The key delivery protocol by Ehrsam et al. and the digital signature protocol by Needham et al. satisfy the sufficient condition for the decidability given in this paper. Under the sufficient condition given in this paper, the security can again be decided in a polynomial time.
Pulse‐type hardware neuron model using a lambda (Λ)‐shaped transistor and its application
Authors: Sekine Yoshifumi , Suyama Masatoshi , Noguchi Masayoshi , Ito Tohru 
Published: July 2007

AbstractInformation processing in living organisms is carried out by the nervous system. From an engineering viewpoint, the nervous system has various interesting features. Study of the hardware neuron model is necessary for its engineering applications. A hardware neuron model by lambda‐shaped transistors has been reported by the authors. This model has a voltage‐current characteristic similar to that of living neurons, suitable for engineering applications. However, this model simulates generation of only single action potential in response to constant current stimulus. It is not a sufficient hardware neuron model for transmitting information by pulse rate.This paper describes a pulse‐type hardware neuron model using a lambda‐shaped transistor and its applications in information processing. First, analysis of the early circuit leads to a model generating continuous action potential by constant current stimulus. Then it is explained that a hardware neuron model showing ON‐response and a Sequence Detector can be constructed with application to temporal feature detection.
Unification parallelism for prolog processing
Authors: Inagawa Masayuki , Baba Takanobu , Yamazaki Katsuhiro , Okuda Kenzo , Ishikawa Ken 
Published: July 2007

AbstractThe unification is a basic component of Prolog processing. However, its parallel processing has not been well studied because the number of arguments, which corresponds to the degree of the unification parallelism, is small, and a consistency check operation is necessary after a parallel unification operation. On these issues, we have implemented the following ideas: (1) enhancing the degree of parallelism by decomposing a compound term into a functor and the arguments at compile‐time; (2) allocating decomposed unification processing to multiple processor units (PUs) at run‐time; (3) decreasing the number of consistency checks by the compile‐time clustering and reducing the overhead by embedding the consistency check operations into the unification processing; and (4) stopping the operations of the other processors if the unification fails. To clarify the effect, we have developed and evaluated a Prolog processor on a multiprocessor system. The results show that statistically: (1) the decomposition of compound terms makes the number of arguments 3.2 on the average even after clustering, and that dynamically, (1) the unification parallelism performs 41 percent speed up, and the effect is evident at a small number of processors; (2) the compile‐time clustering makes the consistency check unnecessary; (3) the stop operation of processors, running in parallel, attains 0.5 – 6 percent (and 10 percent for some problems) performance improvement; and (4) the processing of clause head occupies 60 – 70 percent of dynamic microsteps and is an important object of parallel processing.
An efficient reasoning method for syllogism and its application to knowledge processing
Authors: Morita Kenichi , Nishihara Noritaka , Emura Eriko 
Published: July 2007

AbstractAristotle's syllogism is known in Japan as the “three‐stage inference.” However, it is not correctly understood in general, nor is it in the mainstream of the theory of logic now due to the widespread use of predicate logic. Syllogism is a logic system obtained by the direct analysis and description of the logical structure of linguistic knowledge and notion. Consequently, it includes several aspects suited to the knowledge information processing. The authors have proposed “tuple logic” as the logical framework for representing general knowledge described by a natural language, etc., and explored the possibility for the semantic representation and inference, which are different from those of predicate logic. This paper aims at the realization of a natural and efficient knowledge information processing by combining syllogism into tuple logic as the additional inference mechanism. The technique for efficient realization is investigated. In particular, an efficient validity‐testing procedure for syllogistic expressions is given by improving Lukasiewicz' decision method. The procedure is an application of a graph algorithm. When the set of premises is consistent, the inference can be performed in linear time, which is a useful property in the actual knowledge processing. As an example, a question‐answering system is demonstrated which can perform an inference for a certain range of Japanese sentences including negative ones.
Built—in concurrent testing for semiconductor random access memories by concurrently testing cells on a word‐line
Authors: Miura Yukiya , Tamamoto Hideo , Narita Yuichi 
Published: July 2007

AbstractWith the recent development of high‐density logical circuits with complex functions, a problem is produced in the long time for the functional testing. One method to cope with this problem is to employ builtin testing, which is one of the designs for testability. The method includes the testing circuit in the IC chip (the circuit under test), and testing is performed by the chip itself to decide whether or not the function is normal. We have already proposed new built‐in testing, which can test concurrently all memory cells on a word‐line. The pattern‐sensitive fault is one of the faults which have been difficult to detect. This paper applies the previously proposed method to such a fault, and presents the result. Using the method in this paper, testing can be performed by the near‐optimal test sequence with the complexity of 302N1/2, which is a drastic decrease compared with other testing methods reported to date. The testing circuit can easily be constructed using counters and shift‐registers. The hardware overhead as evaluated by the equivalent number of gates is almost negligible when the memory capacity is increased.