bluuebunny/crossref_metadata_2025_split huggingface dataset:
Optical Interconnection Network Co-Integration: The Potential of
Optical Polymers
Authors: Hornak L. A. , Weidman T. W. 
Published: March 2011

ABSTRACTThe explosive growth under way in the performance of digital electronic
systems is directly traceable to the impact of Si MOS device scaling and its
accompanying increase in functionality at the chip level. The increasing
data rates and chip I/O that have accompanied this scaling have driven the
evolution of both system architectures and the interconnection and packaging
technologies (i.e. chip carriers, printed circuit boards, bus structures)
that support this CMOS functionality and dominate overall system volume. The
further scaling of CMOS technology towards 0.1 – 2.5μm
minimum gate lengths coupled with modest increases in chip size (i.e. 2–4
cm), promise upwards of a 100 fold increase in chip-level complexity. The
resulting emergence of Ultra Large Scale Integrated (ULSI) processor array
chips and wafer-scale memory (solid state disks) hold the potential for
extremely compact distributed computing systems. Through a continuation of
the evolutionary trends of system scaling, application of chip level process
technology to higher system levels, and mixed technology integration (e.g.
BiCMOS); present advanced packaging technologies based upon Multi-Chip
Modules (MCM) will mature into hybrid wafer-level three-dimensional silicon
systems allowing burdensome driver and communication control functions now
designed at the chip level to move off chip into the active silicon
interconnection substrate where network transmission and control can both be
implemented. Realization of the performance potential of these silicon ULSI
systems will largely depend on the successful implementation of this
wafer-level communication network linking the high-density of processing
nodes. The role that any advanced technology (i.e. high-speed normal
electronic, superconducting, optical) will serve within this network will be
determined by the degree of connectivity it can achieve in this scaled
environment and by its ability to benignly coexist with the dominant CMOS
technology, the network's physical and functional foundation[l].
Photo-Polymerized Acrylic Waveguides for Optical
Interconnects
Authors: Krchnavek Robert R. , Lalk Gail R. , Denton Robert 
Published: March 2011

ABSTRACTWe have fabricated acrylic based optical channel waveguides using proximity
photolithography as well as laser direct writing. The cladding layer is a
photosensitive aliphatic urethane dimethacrylate and the guiding layer is a
photosensitive aromatic acrylated epoxy. This material system provides good
adhesion to a variety of substrate materials. Since both the guiding and
cladding layers are applied, these materials can be employed in several
electrical/optical applications including multi-chip modules using Si,
SiO2, and polyimide as well as high speed electronic board
technologies using teflon based substrates.Loss measurements show a guide loss of less than 0.08 dB/cm for multi-mode
waveguides fabricated using the direct write laser technique.
Lithographically defined guides have a loss of 0.3 dB/cm for similar size
waveguides.
An Atomistic Study of the Equilibrium Segregation of Hydrogen to Tilt Boundaries in Nickel
Authors: Moody N. R. , Foiles S. M. 
Published: March 2011

AbstractIn this study, Monte Carlo simulations have been combined with Embedded Atom Method (EAM) calculations to study hydrogen segregation at the atomic level in an ideal nickel lattice with a Σ9 tilt boundary. The calculations indicate that trap binding energies exceed 0.5 eV on the tilt boundary, but decrease rapidly with distance. Furthermore, the calculations show that trap site occupancy increases with trap site binding energy and hydrogen activity, and reach saturation at high hydrogen concentrations. Most importantly, significant rearrangements in tilt boundary structure are predicted to occur as hydrogen concentration increases. The results are consistent with observations that show significant hydrogen concentration enhancement at grain boundaries in nickel and palladium. They also parallel the effect of hydrogen concentration on crack growth susceptibility in nickel and iron-rich alloys. However, the change in boundary structure as hydrogen concentration increases challenges our understanding of hydrogen-induced fracture.
Interface Structure and Slip Transmission in TI-49AL-3NB
Authors: Schwartz Daniel S. , Sastry S. M. L. 
Published: March 2011

AbstractTwo types of special grain boundaries were examined in Ti-49Al-3Nb deformed at elevated temperatures. The first can be described as a Σ=2 order-changing boundary. This boundary is faceted and results from the nucleation and growth of variants of the γ phase from the parent α phase. The second type of grain boundary is a γ/α2 interphase boundary, and transmission of slip through this type of boundary was examined. Slip transmission from γ into α2 did not produce distinct slip bands in α2,. Slip transmission from γ through α2, and into the next γ lamella was possible even when the next γ lamella was in an orientation rotated relative to the first γ lamella.
Thermal Desorption of Hg Monolayers from Cu(100)
Authors: Kime Y. J. , Zhang Jiandi , Dowben P. A. 
Published: March 2011

AbstractA two dimensional phase transition from one adlayer structure to another is an inherent part of the thermal desorption of one monolayer of Hg on Cu(100). The energetics of this phase transition have been studied using thermal desorption spectroscopy (TDS). The TDS spectra reflect the coexistence of the two structural phases for a range of Hg exposures. The TDS spectra have been analyzed within a Polanyi-Wigner framework modified to account for the phase transition.
Grain Boundary Sliding Kinetics and Stress Relaxation Phenomena in Ni Alloys
Authors: Cosandey F. , Ui S. , Cao B. , Schaller R. , Benoit W. 
Published: March 2011

AbstractInternal friction measurements have been performed on Ni-20 wt% Cr alloys containing trace additions of Ce ranging from 0 to 180 at ppm, in order to determine grain boundary sliding kinetics and associated stress relaxation phenomena. Two anelastic relaxation peaks have been observed corresponding to intrinsic grain boundary sliding between carbide precipitates and to macroscopic sliding with elastic accommodation at triple points. The effects of Ce on these grain boundary phenomena and resulting alloy ductilities are also presented.
Quantitative X-Ray Structure Determination of Superlattices and Interfaces
Authors: Schuller Ivan K. , Fullerton Eric E. , Vanderstraeten H. , Bruynseraede Y. 
Published: March 2011

AbstractWe present a general procedure for quantitative structural refinement of superlattice structures. To analyze a wide range of superlattices, we have derived a general kinematical diffraction formula that includes random, continuous and discrete fluctuations from the average structure. By implementing a non-linear fitting algorithm to fit the entire x-ray diffraction profile, refined parameters that describe the average superlattice structure, and deviations from this average are obtained. The structural refinement procedure is applied to a crystalline/crystalline Mo/Ni superlattices and crystalline/amorphous Pb/Ge superlattices. Roughness introduced artificially during growth in Mo/Ni superlattices is shown to be accurately reproduced by the refinement.
Time-Resolved Si Lattic-Temperature Measurement on Wide Time Scale (10−9–100 sec.) During Laser Annealing
Authors: Murakami Kouichi , Itoh Hisayoshi , Tohmiya Yoshinori , Takita Kōoki , Masuda Kohzoh 
Published: March 2011

ABSTRACTTime-resolved Si lattice-temperature measurement has been developed on wide time scale from 10−9 to 100 sec during laser annealing, by utilizing the time-dependent optical interference in Si on sappire. This interference is due to small changes in Si refractive index induced by temporal changes in Si lattice-temperature. For ns–pulsed laser annealing, part of the absorbed photon energy is found to be transferred into lattice (phonons) in a time much shorter than 40-ns pulse duration. A new method using a microscope is demonstrated for time- and space-resolved Si latticetemperature measurements during cw laser annealing.
Reflectivity of Silicon-on-Sapphire During Pulsed Laser Annealing
Authors: Chen Y. H. , Lyon S. A. 
Published: March 2011

ABSTRACTUsing a visible probe laser (632.8 nm) we have directly observed motion of the melt front in silicon-on-sapphire during pulsed laser annealing. The average penetration and regrowth velocities have been determined to be 13 and 6.5 m/sec. respectively. These values are in agreement with recent conductivity measurements and heat flow calculations. In addition, the data demonstrate that the high-reflectivity phase can penetrate at least .5 um (Si thickness) and requires a significant amount of the time to do so. These results are further evidence that the high–reflectivity phase is molten silicon.
Optical Response of Electron-Hole Plasma in Surface Excited Semiconductors
Authors: Forchel A. , Schweizer H. , Laurich B. , Tränkle G. , Mahler G. 
Published: March 2011

ABSTRACTA unified approach is presented which reconciles contradictory results obtained in earlier studies of optical spectra of inhomogeneous electronic systems in semiconductors: A consistent analysis of the optical data implies strong deviations from quasi-equilibrium in the carrier distributions. The non-equilibrium nature of the plasma is confirmed by a Mott-transition based study of the plasma transport.
Semiconductor Processing with Excimer Lasers: An Overview
Authors: Young R. T. 
Published: March 2011

ABSTRACTThe present level of development of excimer lasers, as it relates to semiconductor processing, and the advantages of these lasers for such processing, are reviewed. Extensive comparisons of the quality of annealing of ion-implanted Si obtained with XeCl and ruby lasers are presented. Major applications in the area of solar cell fabrication, siliconon-sapphire technology, laser photochemical processing, and submicron optical lithography are outlined and discussed.
Multiple Layer Sputter Deposition and Laser Annealing of Silicon Films
Authors: Anderson W. W. , Mac Millan H. F. , Katzeff J. S. , Lopez M. 
Published: March 2011

ABSTRACTThe formation of single crystal multiple layers on silicon substrates with thicknesses in excess of 1 μm has been demonstrated to be a viable process. Film build-up is via repetitions of the steps (1) pre-deposition chemical cleaning of wafer, (2) magnetron sputter deposition of 0.3 pm thick amorphous Si, (3) interfacial mixing via 190 keV implantation of Si, and (4) film epitaxial crystallization via pulsed laser annealing. Doping has been demonstrated by both (1) P ion implantation and (2) P incorporation from PH3; included in the sputter gas ambient.
Applications of Energy Beams in Material and Device Processing
Authors: Galvin G.J. , Hung L.S. , Mayer J.W. , Nastasi M. 
Published: March 2011

ABSTRACTEnergetic ion beams used outside the traditional role of ion implantation are considered for semiconductor applications involving interface modification for self-aligned silicide contacts, composition modification for formation of buried oxide layers in Si on insulator structures and reduced disorder in high energy ion beam annealing for buried collectors in transistor fabrication. In metals, aside from their use in modification of the composition of near surface regions, energetic ion beams are being investigated for structural modification in crystalline to amorphous transitions. Pulsed beams of photons and electrons are used as directed energy sources in rapid solidification. Here, we consider the role of temperature gradients and impurities in epitaxial growth of silicon.
Large Area Continuous Electron Beam for Semiconductor Processing
Authors: Moore Cameron A. , Rocca J. J. , Collins G. J. , Russell P. E. , Geller J. 
Published: March 2011

ABSTRACTWe have achieved wide area (38 cm2) electron beam heating of semiconductor materials using a glow discharge electron beam with electron energies between 3 and 7 keV. A continuous beam 7 cm in diameter with a power density up to 90 W/cm2 was used to anneal both boron-implanted (30 keV, 5 × 1015 atoms/cm2) n-type <100> silicon wafers as well as two types of Ti-Si composite films to form this titanium disilicide Annealing of the implanted samples was obtained without redistribution of the original dopant profile using a 15-sec. electron beam exposure. Formation of TiSi2 was found to decrease the sheet resistivity of these samples a factor of ten for both 400 Å films of Ti on Si and codeposited Ti-Si mixtures of overall stoichiometry TiSi2. Due to the high electron beam power density achieved over a large area, one can uniformly anneal an entire wafer in a single exposure without sample or beam scanning.
The Effects of Thermal and Transient Annealing on the Redistribution of Indium Implanted Silicon
Authors: Katz W. , Smith G.A. , Reihl R.F. , Koch E.F. 
Published: March 2011

ABSTRACTThe redistribution of indium in silicon has been studied as a function of dose during rapid thermal annealing. The results show little redistribution of indium for doses 1×1015 cm−2. For a 350keV/5×1015 cm−2 indium implant, the annealed sample showed significant indium precipitation and near surface defects. These data are contrasted to an earlier study of a 300keV/1×1015 cm−2 indium implanted silicon sample that was furnace annealed for 30 minutes at 1050°C. The furance annealed sample showed redistribution to both implant damage and the amorphous crystalline interface as well as a tail on the backside of the implant due to interstitial diffusion. This interstitial tail is clearly minimized in the transient annealed sample.
Germanium Implantation into Silicon: An Alternate Pre-Amorphization/Rapid Thermal Annealing Procedure for Shallow Junction Technology
Authors: Sadana D.K. , Myers E. , Liu J. , Finstad T. , Rozgonyi G.A. 
Published: March 2011

ABSTRACTGermanium implantation into Si was conducted to pre-amorphize the-si surface layer prior to a shallow/high dose (42 keV, 2 × 1015 cm−2) BF2 implant. Cross-sectional transmission electron microscopy showed that rapid thermal annealing (RTA) of the amorphous layer (without BF2 ) leaves defect-free material in the implanted region. Only a discrete layer of small (∼300Å) dislocation loops due to straggling ion damage was found to be present at a depth corresponding to the amorphous/crystalline interface. RTA of the amorphous layer with the BF2 creatpd a high density of uniformly. distributed fine defect clusters (∼50Å) in the surface region (0–500Å) in addition to the straggling ion damage. Boron and F profiles obtained by secondary ion mass spectrometry from the unannealed and rapid thermally annealed samples showed the presence of high concentrations of these impurities in the surface region where the fine defect clusters were observed. A comparison of the RTA behavior of the pre-amorphized surface layers (with or without BF2 ) produced by Ge and self-implantation is presented.
Effects of Heating Samples on the Extended Defect Generation During Pulsed Electron Beam Annealing of Silicon
Authors: Pitaval M. , Ambri M. , Tholomier M. , Barbier D. , Chemisky G. , Laugier A. 
Published: March 2011

ABSTRACTA non destructive SEM observation method has been applied to investigate the extended defects created by pulsed electron beam annealing of arsenic–implanted silicon. The defect study was performed on bevelled samples after irradiation using variable beam fluences for both a 20°C or a 450°C specimen starting temperature. Dislocation generation resulting in subgrain boundaries formation occurs during regrowth of the silicon layer which has been heated up to the melt point or higher. For the rather penetrating electron beam pulse used in this work the subgrain size and their depth extent depend on the beam fluence and the substrate temperature. For 450°C pre‐heated samples, annealing of the arsenic implant is possible without any stable extended defect creation using the 1.0 – 1.2 J.cm−2 fluence range.
Zone Melting Recrystallization of Patterned Films and Low-Temperature Graphoepitaxy
Authors: Smith Henry I. , Thompson C.V. , Geis M.W. , Atwater H. , Yonehara T. , Wong C.C. 
Published: March 2011

ABSTRACTZone melting recrystallization (ZMR) of Si films on SiO2 has produced large-area films with electrical properties approaching those of bulk wafers. The mechanisms of film formation and the use of patterning to control orientation and defect distribution are briefly reviewed. Some examples of the use of patterning are: single-grain films have been produced by means of planar constrictions; subboundaries and impurities have been entrained to lie along straight lines separated by ∼100μm through the use of lithographically defined grating patterns; a vertical-constriction technique has enabled (100) texture to be achieved in 50μm-thick Si films; a lithographically-defined orientation filter, which takes advantage of growth-velocity anisotropy, has been used to select a predetermined azimuthal orientation.Patterning is also fundamental to graphoepitaxy. Current research emphasizes low temperature processes based on solid-state surface-energy-driven secondary grain growth.
Recrystallization of Polycrystalline Silicon Over SiO2 through Strip Electron Beam Irradiation
Authors: Hayafuji Y. , Yanada T. , Hayashi H. , Williams K. E. , Usui S. , Kawado S. , Shibata A. , Watanabe N. , Kikuchi M. 
Published: March 2011

ABSTRACTWe have studied the influences of substrate orientation and growth direction on laterally seeded recrystallization of poly-crystalline silicon on a SiO2; film through strip electron beam irradiation. We found that growth in a [110] direction produced films with better crystal quality than growth in a [100] direction on a (001) substrate, and that growth in a [211] direction provides better crystal quality than growth in a [011] direction on a (111) substrate. A simple model of the growth interface composed of {111} planes is proposed
Soi Technologies at the CNET
Authors: group Soi 
Published: March 2011

ABSTRACTFor the recrystallization of poly-Si films deposited on oxidized Si wafers, we focus our research on lamp and cw laser systems. We have obtained large single-crystal films using both techniques. “Selective annealing” allows localization of the remaining defects in the recrystallized films. Crystallographic as well as electrical characterization confirm the device-worthy potential of this material.
Nmos Logic Circuits in Laser-Crystallized Silicon on Quartz
Authors: Chiang A. , Zarzycki M. H. , Meuli W. P. , Johnson N. M. 
Published: March 2011

ABSTRACTDepletion mode as well as enhancement mode n-channel thin-film transistors (TFT's) have been fabricated in CO2 laser-crystallized silicon on fused quartz. Nearly defect-free islands were obtained by using an offset circular beam to form a tilted melt interface. The optimization of subsequent processing steps to achieve simultaneously low leakage currents and voltage thresholds appropriate for depletion-load NMOS circuits involved adjustments of ion implantation and high temperature cycles with the aid of simulation. The resultant high performance silicon-gate TFT's have led to NMOS ring oscillators with 2.5 ns delay/stage and dynamic shift registers with MHz clock rates. These are the first logic circuits fabricated in beam-crystallized silicon on bulk amorphous substrates.
Zone Melting Recrystallization of InSb Films on Oxidized Si Wafers
Authors: Wong C.C. , Keavney C.J. , Atwater H.A. , Thompson C.V. , Smith H.I. 
Published: March 2011

ABSTRACTInSb thin films on oxidized Si wafers have been recrystallized using a strip heater to generate and scan a narrow molten zone across the film. Grains up to 3 × 10 mm have been produced. Crystallization proceeds in a faceted cellular fashion, the excess solute (Sb) being rejected into subboundaries which often lie along low-index crystallographic directions. A InSb-Sb eutectic structure forms at the subboundaries. The width of the single-crystal InSb between subboundaries is approximately 75 μm. The techniques of planar constriction and subboundary entrainment have been extended to InSb for the selection of single grains and the orelocation of subboundaries. This technology of producing InSb thin films on oxidized Si substrates max, be extendable to other III-V materials, and could lead to novel device structures through the integration of Si and III-V compound devices on the same substrate.
Annealing of High Dose Implanted GaAs with Halogen Lamps
Authors: Nissim Y.I. , Joukoff B. , Sapriel J. , Henoc P. 
Published: March 2011

ABSTRACTHalogen lamps are used to anneal implanted GaAs. Surface protection is obtained by mouting the substrate in a sandwiched configuration between a silicon and a quartz plate. Raman scattering measurements are carried out to follow simultaneously lattice reconstruction and surface degradation due to Arsenic loss. The evolution of the Raman spectra is compared to a T.E.M. analysis carried out on the same samples.
Rapid Thermal Annealing of Ion Implanted GaAs and InP
Authors: Vaidyanathan K.V. , Dunlap H.L. 
Published: March 2011

ABSTRACTThis paper discusses the properties of high intensity lamp-annealed silicon or beryllium-implanted GaAs and InP samples. We find this annealing process can result in efficient activation of dopants. Conventional furnace annealing at the same temperature does not result in increased electrical activation of the dopants. High fluence silicon implants can be activated in anneal times as short as 2 seconds, while low fluence silicon implants require more extended annealing. Activation of low fluence implants in GaAs depends strongly on the properties of the bulk semiinsulating material.
Study of Dielectric Caps for Incoherent Lamp Annealing of InP
Authors: Soda W.J. , Lorenzo J.P. , Davifs D.F. , Ryan T.X. 
Published: March 2011

ABSTRACTA parametric study is presented of CVD and RF sputter deposited SiO2 and PSG dielectric caps for incoherent lamp annealing of InP. Both deposition and annealing parameters are studied. We observe that CVD caps provide reliable mechanical protection during lamp annealing up to maximum bulk temperatures of 830°C, while sputtered deposited SiO2 caps perform well ,up to 850°C. We find however that sputter deposited caps introduce process related conduction into both unimplanted and implanted semi-insulating InP. Electrical activation of implanted dopants is also studied as a function of capping technioue. Lamp annealing of InP protected by caps with CVD phosphorus doped SiO2 in contact with the InP surface, results in excellent activation efficiencies in Si+ implanted material. When properly capped and annealed, we observe electrical profiles whose shape more nearly approaches theoretical LSS, than those previously reported.
Dopant Redistribution in Titanium Silicide/n+ Polysilicon Bilayers During Rapid Thermal Processing
Authors: Cooper C. B. , Powell R. A. , Chow R. 
Published: March 2011

ABSTRACTThe successful use of rapid thermal processing in an isothermal mode to form Ti polycide structures is described. The silicide was sputter deposited from a composite Ti-Si target onto phosphorus-doped poly-Si. The resulting polycide structure was annealed by exposure to the blackbody radiation from a resistively-heated graphite heater. Rapid diffusion of the P into the Ti silicide is observed even for short annealing times, although resulting P concentrations in the silicide (>7 × 1018cm−3) are relatively low, about 100 times lower than in the doped poly-Si. Properly chosen RTP parameters can minimize the sheet resistance of the polycide without increasing the sheet resistance of the underlying poly-Si layer, which has not been possible for furnace-annealed samples.