bluuebunny/crossref_metadata_2025_split huggingface dataset:
A Combined-Cross Analysis Reveals Genes With Drug-Specific and Background-Dependent Effects on Drug Sensitivity inSaccharomyces cerevisiae
Authors: Kim Hyun Seok , Fay Justin C 
Published: September 2009

AbstractEffective pharmacological therapy is often inhibited by variable drug responses and adverse drug reactions. Dissecting the molecular basis of different drug responses is difficult due to complex interactions involving multiple genes, pathways, and cellular processes. We previously found a single nucleotide polymorphism within cystathionine β-synthase (CYS4) that causes multi-drug sensitivity in a vineyard strain of Saccharomyces cerevisiae. However, not all variation was accounted for by CYS4. To identify additional genes influencing drug sensitivity, we used CYS4 as a covariate and conducted both single- and combined-cross linkage mapping. After eliminating numerous false-positive associations, we identified 16 drug-sensitivity loci, only 3 of which had been previously identified. Of 4 drug-sensitivity loci selected for validation, 2 showed replicated associations in independent crosses, and two quantitative trait genes within these regions, AQY1 and MKT1, were found to have drug-specific and background-dependent effects. Our results suggest that drug response may often depend on interactions between genes with multi-drug and drug-specific effects.
Effects of Polymer Material Variations On High Frequency Dielectric Properties
Authors: Pawlikowski Gregory 
Published: September 2009

AbstractIn high frequency signal packaging, the plastic dielectric material takes on an increasingly important role in the performance of the signal transmission. Variations within the plastic can occur as a result of a number of manufacturing and environmental processes. These variations can be sufficient to change the dielectric properties. The extent of change to the dielectric properties of polymer materials as a result of controlled variations to major filler additives, moisture and temperature has been investigated. The combined effects of moisture and temperature can cause changes to the dielectric constant of certain materials by more than 30 %.
Effects of Silica Sources on Nanoporous Organosilicate Films Templated with Tetraalkylammonium Cations
Authors: Eslava Salvador , Urrutia Jone , Busawon Abheesh N. , Baklanov Mikhail R. , Iacopi Francesca , Maex Karen , Kirschhock Christine E. A. , Martens Johan A. 
Published: September 2009

AbstractNanoporous organosilicate films have been recently prepared using tetraalkylammonium cations in acid and basic media, outperforming other materials. Resulting films using basic medium were called zeolite-inspired low-k dielectrics. Here we study the dependence of the properties of these films on the used silica sources: methyltrimethoxy silane (MTMS) and tetraethyl orthosilicate (TEOS). A set of experiments varying the MTMS:TEOS ratio were prepared in acid medium and characterized. A textural, physico-chemical, mechanical, and electrical characterization of this series of experiments is presented.
A Study of Diffusion Barrier Characteristics of Electroless Co(W,P) Layers to Lead-free SnAgCu Solder
Authors: Pan Hung-Chun , Hsieh Tsung-Eong 
Published: September 2009

AbstractDiffusion barrier characteristics of amorphous and polycrystalline electroless Co(W,P) layers (α-Co(W,P) and poly-Co(W,P)) to lead-free SnAgCu (SAC) solder were investigated via the liquid- and solid-state aging tests. In the sample containing α-Co(W,P) subjected to liquid-state aging at 250°C for 1 hr, the spallation of (Co,Cu)Sn3 intermetallic compound (IMC) into the solder and formation of a polycrystalline P-rich layer in between SAC and Co(W,P) were found. Further, the α-Co(W,P) transforms into polycrystalline structure embedded with tiny Co2P precipitates As to the sample containing α-Co(W,P) subjected to solid-state aging at 150°C up to 1000 hrs, a thick (Cu,Co)6Sn5 IMC resided in between SAC and Co(W,P) and the P-rich layer beneath IMCs was similarly seen. In the samples containing poly-Co(W,P) subjected to liquid-state aging, a mixture of (Co,Cu)Sn3 and (Co,Ag)Sn3 IMCs formed in between SAC and Co(W,P). An amorphous W-rich layer formed in between SAC and poly-Co(W,P). Similar interfacial morphology was observed in the samples subjected to the solid-state aging test. Analytical results indicated the electroless Co(W,P) is in essential a combined-type, i.e., sacrificial-type plus stuffed-type, diffusion barrier. However, the α-Co(W,P) is a better diffusion barrier for under bump metallurgy (UBM) applications in flip-chip (FC) bonding since it exhibits a lower Co consumption rate in comparison with poly-Co(W,P).
Atomic Layer Deposition of Ruthenium Films on Hydrogen terminated Silicon
Authors: Park Sun Kyung , Roodenko K. , Chabal Yves J. , Wielunski L. , Kanjolia R. , Anthis J. , Odedra R. , Boag N. 
Published: September 2009

AbstractAtomic Layer deposition of thin Ruthenium films has been studied using a newly synthesized precursor (Cyclopentadienyl ethylruthenium dicarbonyl) and O2 as reactant gases. Under our experimental conditions, the film comprises both Ru and RuO2. The initial growth is dominated by Ru metal. As the number of cycles is increased, RuO2 appears. From infrared broadband absorption measurements, the transition from isolated, nucleated film to a continuous, conducting film (characterized by Drude absorption) can be determined. Optical simulations based on an effective-medium approach are implemented to simulate the in-situ broadband infrared absorption. A Lorentz oscillator model is developed, together with a Drude term for the metallic component, to describe optical properties of Ru/RuO2 growth.
Electroless Cu Deposition on Self-assembled Monolayer Alternative Barriers
Authors: Armini Silvia , Maestre Caro Arantxa 
Published: September 2009

AbstractAn alternative bottom-up Cu electro-less deposition (ELD) method without other catalyst material activation tested on blanket wafers, is the focus of this paper. The process consists in reducing the Cu ions via standard reducing agents, such as dimethylamine borane (DMAB). A wide range of experimental conditions such as pH, temperature, Cu ion concentration and time are investigated and the Cu layer nucleation and growth mechanism is evaluated on clean SiO2 and after functionalization with 3-aminopropyltrimethoxysilane (APTS) self-assembled monolayer (SAM) used as copper diffusion barrier. The barrier properties of the APTS layer after Cu ELD are also assessed by copper resistivity measurements and visual inspections as a function of the annealing temperature.
Adhesion and Cu Diffusion Barrier Properties of a MnOx Barrier Layer Formed with Thermal MOCVD
Authors: Neishi Koji , Dixit Vijay Kumar , Aki S. , Koike Junichi , Matsumoto K. , Sato H. , Itoh H. , Hosaka S. 
Published: September 2009

AbstractA thin-amorphous MnOx layer using self-forming barrier process with a Cu-Mn alloy shows good adhesion and diffusion barrier properties between copper and dielectric layer, resulting in excellent reliability for stress and electromigration. Meanwhile, chemical vapor deposition (CVD) can be employed for conformal deposition of the barrier layer in narrow trenches and vias for future technology node. In our previous research, a thin and uniform amorphous MnOx layer could be formed on TEOS-oxide by thermal metal-organic CVD (MOCVD), showing a good diffusion barrier property. In addition, a good adhesion strength is necessary between a Cu line and a dielectric layer not only to ensure good SM and EM resistance but also to prevent film delamination under mechanical or thermal stress conditions during fabrication process such as chemical mechanical polishing or high temperature annealing. To date, no information is available with regard to the adhesion property of CVD-MnOx. In this work, we report diffusion barrier property in further detail and adhesion property in PVD-Cu/CVD-MnOx/SiO2/Si. The temperature dependence of the adhesion property is correlated with the chemical composition and valence state of Mn investigated with SIMS and Raman spectroscopy.Substrates were p-type Si wafers having a plasma-TEOS oxide of 100nm in thickness. CVD was carried out in a deposition chamber. A manganese precursor was vaporized and introduced into the deposition chamber with H2 carrier gas. After the CVD, a Cu overlayer was deposited on some samples using a sputtering system in load lock chamber of the CVD machine. The diffusion barrier property of the MnOx film was investigated in annealed samples at 400 oC for 100 hours in a vacuum of better than 1.0×10-5 Pa. The Adhesion property of Mn oxide was investigated by Scotch tape test in the as-deposited and in the annealed Cu/CVD-MnOx/TEOS samples. The obtained samples were analyzed for thickness and microstructure with TEM, chemical bonding states of the MnOx layer with XPS, and composition of each layer with SIMS.In the CVD deposition below 300 °C, no Cu delamination was observed both in the as-deposited and in the annealed Cu/CVD-MnOx/SiO2 samples. On the other hand, in the CVD deposition at 400 °C, the Cu films were delaminated from the CVD-MnOx/TEOS substrates. The XPS peak position of Mn 2p and Mn 3s spectra indicated that the valence state of Mn in the as-deposited barrier layer below 400 °C was 2+. Composition analysis with SIMS as well as Raman also indicated the presence of a larger amount of carbon at 400 °C than at less than 300 °C. The good adhesion between Cu and MnO could be attributed to an amount of carbon inclusion in the CVD barrier layer.
Effect of Dielectric Capping Layer on TDDB Lifetime of Cu Interconnects in SiOF
Authors: Gambino Jeff , Chen Fen , Mongeon Steve , Pokrinchak Phil , He John , Lee Tom C. , Shinosky Mike , Mosher Dave 
Published: September 2009

AbstractIn this study, intralevel dielectric breakdown is studied for copper interconnects in an SiOF dielectric, capped with either SiN or SiCN. The leakage current is higher and the failure time of dielectric breakdown is shorter for an SiCN capping layer compared to an SiN capping layer. It is proposed that the dielectric breakdown of the integrated structure is limited by the interface between the capping layer and the SiOF dielectric. Lower lifetime for dielectric breakdown is observed for structures with an SiCN cap compared to structures with an SiN cap, due to higher leakage current in the SiCN. The higher leakage for an SiCN cap is consistent with results from planar metal-insulator-semiconductor capacitors.
Direct Metal Nano-patterning Using Embossed Solid Electrolyte
Authors: Kumar Anil , Hsu Keng , Jacobs Kyle , Ferreira Placid , Fang Nicholas 
Published: September 2009

AbstractThe recent growth in optoelectronics, nanoelectronics, nanooptics, and chemical and biological sensing has been fueled by the ability to fabricate nanostructures with ever smaller features. However, several significant constraints still remain in terms of cost, limited pattern size, processing conditions, pattern flexibility, and so on. Fabrication of features as small as 50 nm at ambient conditions with high pattern flexibility and low cost remains a serious challenge. Here we report a new solid-state electrochemical imprinting process that is carried out at ambient conditions, requires nominal pressure and very low electric potential, eliminates any liquid electrolytes, shows very high reproducibility, and promises the capability to scale up for large area patterning while retaining a significant cost advantage. Through combination of the best merits of nanoimprint lithography, micro forming, and the solid-state electrochemical imprinting technique, S4, (recently introduced by Hsu et al., Nano Lett., 2007, 7, 446; and Schultz et al., J. Vac. Sci. Techol. B, 2007, 25, 2419), we show a very high pattern flexibility to create nano-scale metallic features.As a first step, we use a micro-forming-like embossing process to engrave nano-scale features onto a solid electrolyte tool surface using an e-beam fabricated Si mold. Silver sulfide, Ag2S, is used as a solid electrolyte because of its favorable mechanical properties for micro forming and its excellent electrochemical properties. This ionic compound is ductile and has a relatively low yield stress at 80MPa. Followed by embossing, the patterned solid electrolyte surface is then used to carry out the S4 process, creating a negative image on a metallic substrate. This process eliminates the costly Focused Ion Beam milling used by Hsu et al. to create features on the electrolyte tool. It is also highly favorable for large-area patterning as well as mass-production of metallic substrates restricted only by the capability to fabricate the mold at first step. The embossed solid-electrolyte tool surface can be easily trimmed off with a microtome; the tool can then be re-used for embossing and patterning metallic substrates.Using this process we demonstrate the ability to fabricate silver nanostructures with features <15 nm. Such small features are critical in metal nanostructures for field enhancement that finds applications in SERS and other biological and chemical sensing. So far, a line edge roughness of <10 nm is observed which is significant in the sense that silver is highly mobile and has the tendency to granulate. Finally, we show how this methodology has the capability to fabricate large area patterns at low cost and ambient conditions. As a proof of concept, we demonstrate the ability to fabricate areas >30 sq. mm. Such large scale fabrication is highly desired for applications like biomimetics and patterning for superhydrophobic surfaces.
Failure Analysis and Process Improvement for Through Silicon Via Interconnects
Authors: Majeed Bivragh , Cauwenberghe Marc Van , Tezcan Deniz Sabuncuoglu , Soussan Philippe 
Published: September 2009

AbstractThis paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.
Power Delivery, Signaling and Cooling for 3D Integrated Systems
Authors: Bakir Muhannad , Huang Gang 
Published: September 2009

AbstractThree-dimensional (3D) integration of ICs provides unique opportunities to improve bandwidth, latency, and power dissipation bottlenecks of interconnects (both on- and off-chip). However, while 3D IC integration improves signal interconnection, it also presents new challenges, especially in power delivery and cooling (“thermal interconnects”). The focus of this paper is on some of the key challenges and promising technologies to address power delivery, cooling, and signaling in a 3D stack of logic ICs.
Effect of Cyclic Damage on the Constitutive Behavior & Microstructure of Sn3.0Ag0.5Cu (SAC305) Solder
Authors: Cuddalorepatta Gayatri , Dasgupta Abhijit 
Published: September 2009

AbstractThis study examines the effect of cyclic damage on the constitutive response and microstructural evolution of SAC305 solder. Cyclic damage is induced through isothermal, mechanical cycling tests at high strain rate and room temperature, using modified lap shear microscale specimens (180μm wide solder joint). The properties of interest are elastic, plastic, yield, and viscoplastic material constitutive behavior. In the current study, creep strain accumulation is accommodated when determining the constants, unlike those reported in prior studies [1]. Insights into the evolution of the measured properties are provided by correlating previously reported microstructural grain evolution of microscale SAC305 solder as a function of cyclic damage [2, 3].The hysteresis response and the elastic, plastic and yield measurements from the initial cycles show significant piece-to-piece variability (similar to prior virgin state viscoplastic measurements [3]). The scatter arises since as-reflowed SAC solder joints at length scales of 200μm consist of only a few anisotropic Sn grains that make the joint mechanically inhomogeneous. However, when subject to mechanical cycling fatigue at room temperature these joints undergo grain homogenization due to recrystallization, which is a possible explanation to the drop in scatter with progressing damage. The observed grain evolution is similar to that seen in solder joints under life-cycle loading.The elastic-plastic response and yield strength of SAC305 solder do not show significant contribution from creep deformations at the chosen load levels. The properties degrade with increasing accumulated cyclic damage, at a rate that is proportional to the severity of the cyclic load. The yield stress measurements suggest that SAC305 obeys an independent hardening rule, rather than isotropic or kinematic hardening. The performance of a continuum damage mechanics based model from prior studies in representing the measured degradation in elastic, plastic and yield properties is discussed [4,5].Comparison of the creep behavior of cycled SAC305 specimens (at 50% load drop) with that of uncycled specimens shows that the effective creep compliance and effective secondary creep strain rate increase significantly. As a point of comparison, the creep resistance of cycled SAC305 specimens is even lower than that of as-reflowed Sn37Pb specimens. Similar changes are seen in the stress relaxation behavior. Challenges and limitations of the current studies are included.
Comparison of Carbon-based Nanostructures with Commercial Products as Thermal Interface Materials
Authors: Rosshirt Michael , Fabris Drazen , Cardenas Christopher , Wilhite Patrick , Tu Thanh , Yang Cary Y. 
Published: September 2009

AbstractHeat dissipation in electronics packaging can be highly dependent on Thermal Interface Materials (TIM). TIM contact, compliance, and conductivity can be the dominant limiting factors in the overall conduction heat transfer across the interface. Mixing multiwall Carbon Nanotubes (CNTs), which have high thermal conductivity, with other thermally conducting materials holds great promise as TIM fillers and has been shown to have higher thermal performance than commercial TIM ‘1’. Such mixtures possess greater thermal conductivity as a result of increased thermal conduction paths through highly conductive, high aspect ratio CNTs.In this work, we develop and test an advanced apparatus based on the ASTM D5470-06 standard to measure thermal interface resistance. Our experimental findings quantify the thermal performance trends of industry-standard TIM Arctic Silver® 5 along with hybrid TIM mixtures of Arctic Silver®5 and varying weight ratios of CNTs. Early experimental findings show that Arctic Silver®5 mixed with 0.5 to 1% multiwall CNT by weight may improve thermal conductivity over pure Arctic Silver®5.The goal of this research is to investigate the viability of integrating CNTs with commercial products as improved TIM for electronic cooling in chip packages.