bluuebunny/crossref_metadata_2025_split huggingface dataset:
Rapid Thermal Chemical Vapor Deposition of Polycrystalline Silicon From Dichlorosilane
Authors: Kermani Ahmad , Johnsgard Kristian E. , Suthar Sailish , Kim Ki-Bum , Lam Chung 
Published: March 2011

AbstractRapid Thermal Chemical Vapor Deposition (RTCVD) of undoped and insitu doped polycrystalline silicon films has been accomplished in a cold-wall reactor. Dichlorosilane was used for the silicon source and AsH3 gas was used as the dopant source. Thedeposition kinetics of poly-silicon films on silicon dioxide over a range of deposition temperatures, pressures and carrier gas chemistries was studied. Both blanket and selective deposition modes were examined. The poly-silicon films were examined by scanning electron microscopy (SEM) and transmission electron microscopy (TEM) for morphology and grain size analysis. Using X-ray diffraction technique, preferred grain orientation dependency of poly-silicon films on growth conditions was investigated. Dopant incorporation, dopant activation and oxygen content of polysilicon films were measured by secondary ion mass spectrometry (SIMS), four point probe, and spreading resistance profiling (SRP) techniques.This paper is to report the results of material characterization of polysilicon films deposited by RTCVD, and to address the applications and advantages of ‘Integrated Processing’ technology involving deposition of polysilicon.
Impact of Polycrystalline Silicon Processing on Properties of MOS Memory Devices
Authors: Queirolo G. , Brambilla M. , Mavero C. 
Published: March 2011

AbstractIn EEPROMs mèmory devices, tunnel oxides with high fluence, and interpoly oxides with low conductivity and high breakdown field are needed. Tunnel oxide fluence is degraded by high temperature annealing after the polysilicon deposition, while interpoly oxide is degraded by low temperature oxidation, particularly on rough films. As a consequence, a process optimization, giving a good compromise between these two quantities is required. In this work we shown that if a flat polysilicon is used, an interpoly oxide of good quality can be obtained at low temperature, maintaining a high value for the tunnel oxide fluence.
Investigations of an Antimony Doped Poly-Silicon Gate Structure for P-Type JFET Applications
Authors: SÖDERBÄrg Anders , Grelsson Ö. , Magnusson U. 
Published: March 2011

AbstractA polysilicon gate structure for application as gate material in p-channel JFET's is presented. The structure was manufactured using solid-phase epitaxy of an evaporated antimony/amorphous—silicon layer. The fabrication process together with experimental evaluation of both diode and JFET characteristics is given. The structure shows near ideal n+p-junction behaviour and the fabricated JFET's are normally off with good values of subthreshold swing and transconductance.
Effect of the MOS Process on the Work-Function Difference Between the Polysilicon Gates and the Silicon Substrate
Authors: Lifshitz N. 
Published: March 2011

AbstractPolysilicon gates are an important element of modem MOS integrated circuit technology. The workfunction difference (ϕps) between the polysilicon gate and the silicon substrate is a vital parameter of the MOS system because it determines the threshold voltage of the field-effect transistor. Ideally, ϕps is determined by the doping level in both polysilicon and the substrate. In reality process variations influence the ϕPS in a tangible way. Some of these effects are reviewed in the present paper.
Post-Annealing Effect on the Reliability of Ultra-Thin Silicon Dioxide with Polysilicon Gate
Authors: Yoneda Kenji , Fukuzaki Yoshiki , Satoh Kazuo , Todokoro Yoshjhiro , Inoue Morio 
Published: March 2011

AbstractTime dependent dielectric breakdown (TDDB) characteristics and TEM observation of ultra-thin silicon dioxide with the polysilicon gate after post-annealing and oxidation at 1000-1100 °C are discussed. The high temperature post-annealing decreases the TDDB characteristics of ultra-thin oxide with polysilicon gate. The charge to breakdown is reduced drastically with increasing the annealing temperature and annealing time. The dielectric breakdown reliability degradation of ultra-thin tunneling oxide by the post-annealing can be explained as the partial oxide thinning and electric field concentration due to the increase of roughness at the polysilicon gate/ultra-thin tunneling oxide interface. This increase of roughness is due to the grain growth of polysilicon gate and viscous flow of oxide, which are enhanced with increasing the annealing temperature and time.
Comparative Studies of Gate Oxides Using Thermal, Stacked Gate, and Rapid Thermal Oxidation
Authors: Chittipeddi S. , Roy P. K. , Kannan V. C. , Singh R. , Dziuba C. M. 
Published: March 2011

AbstractIn this paper we report on the quality of gate oxides obtained using three different oxidation techniques, namely thermal oxidation, rapid thermal oxidation and stacked gate oxidation. We report on the oxide thicknesses, the flatband voltage, threshold voltage, and QSS/Q values for MOS capacitors fabricated using these three techniques. We also fabricated MOSFET's using thermal oxides and stacked gate oxides, and find that the stacked gate oxides have a lower gate oxide defect density. Lattice images have also been obtained for the Si/SiO2 interface using transmission electron microscopy (TEM). We find that stacked oxide synthesis results in lower stresses and asperities at the interface relative to thermal and rapid thermal oxidation.
Large-Grain Polysloon Films Depied by Raped Thermal IPCVD
Authors: Mitdhell S.J.N. , McNeill D.W. , Raza S.H. , Armstrong B.M. , Gemble H.S. 
Published: March 2011

AbstractRapid thermal LMVD has been applied to the deposition of polysiliccn layers. The single process wafer sits in an air—cooled quartz chamber, and is heated by tungsten—halcgen lamps. A nicrowave cavity upstrean of the hot zone may be used to introduce a remote plasma.Pblysilicon films have been deposited on ocidized suhstrates in the temperature range 590C–860C, and at pressures between 0.lmber and 10mbar. Conditions for the reduction of carbon and oxygen levels down to 5x1017 cm are presented.An in—situ CF4 plasma clean prior to polysiliccn deposition is shown to dramatically affect grain—size. At 720C and Imbar, plasma-cleaned polysilicon has a grain—size of 35Chm, whereas non—cleaned polysilicon has a grain—size of only 120nm. The CF4 schedule leaves a clean ocide surface with fewer nucleation sites, resulting in larger grains.Both types of polysilicon were used in the fabrication of TMT'S. Devices with larger grain material pass 10 times as much current as those with smaller grains, show a channel nobility of >20cm v s, and have a threshold voltage of 5V. Thus, direct deposition of polysilicon layers on a plasma—cleaned substrate is an attractive alternative to crystallization from amorphous silicon, for TFT's.
Characterization and Modeling of Polysilicon TFTs and TFT-CMOS Circuits for Integrated Driver Applications
Authors: Kim Dae M. , Qian Feng , Esralian Michael J. , Whitlow Dana E. , Culter Robert G. , Thayer Stephen C. 
Published: March 2011

AbstractPolysilicon TFTs and TFT-CMOS circuits are characterized. Circuit elements examined comprise subcircuits pertinent to integrated drivers suitable for flat panel display applications. Performance features of multistage static row drivers are also presented. Additionally, AC measurement of TFTs was performed in order to extract device parameters. The channel mobility measured in a time of flight environment is presented and discussed.
Crystal Growth Study of Silicon and Germanium Wafers Used for Photovoltaic Devices
Authors: Chibani A. , Sof S. , Hamoud M. , Gauthier R. , Pinard P. 
Published: March 2011

AbstractTo develop the EPR material quality, electrical and structural charact erizations were executed by EBIC, LBIC, TEM, ECP and X diffraction. Two interface types were observed; some interfaces parallel and constitued by Σ3 and Σ9 twins, show low electrical activity; other are curved with no defined index and higher electrical activity. Some orientations such as (111),(220),(331) appear more frequently.
The Effect of Amorphous Silicon Layer in PE-CVD Titanium Polycide Gate Dielectrics
Authors: Chen Shih-Chang , Sakamoto Akihiro , Tamura Hiroyuki , Yoshimaru Masaki , Ino Masayoshi 
Published: March 2011

AbstractTitanium silicide (TiSix), used as polycide gate consists of TiSi1.1 and amorphous silicon (a—Si), was deposited by Plasma Enhanced Chemical Vapor Deposition method (PE—CVD). The effect of a—Si layer in PE—CVD Ti polycide gate dielectrics has been studied. In order to evaluate the a—Si layer effect, three types of samples were prepared on gate SiO2 film with following structures: a) a—Si / TiSil.1 / a—Si / phosphorus (P) doped poly—Si, b) a—Si / TiSi1.1 / non—doped poly—Si / P doped poly—Si and c) a—Si / TiSi1.1 / P doped poly—Si, respectively. Furthermore, in order to avoid the influence of native oxide existence at the interface, the pre—cleaning treatment was performed in—situ on the poly—Si film surface before TiSi1.1 film deposition. The gate dielectric strengths of these samples indicate that the gate dielectric degradation in PE—CVD Ti polycide gate is greatly dependent on Si under layer crystallization. It is effective using a—Si film as the under layer in decreasing the gate dielectric degradation. This is due to the Ti oxide interlayer, formed at the interface of TiSi2.0 and poly—Si films, whichrestrains the TiSix local penetration.
High Resolution Electron Microscopy of Defects in High-Dose Oxygen Implanted Silicon-On-Insulator Material
Authors: Visitserngtrakul S. , Jung C. O. , Cordts B. F. , Roitman P. , Krause S. J. 
Published: March 2011

AbstractHigh resolution electron microscopy (HREM) has been used to study the atomic arrangement of defects formed during high-dose oxygen implantation of silicon-on-insulator material. The effect of implantation parameters of wafer temperature, dose, and current density were investigated. Wafer temperature had the largest effect on the type and character of the defects. Above the buried oxide layer in the top silicon layer, HREM revealed that microtwins and stacking faults were created during implantation from 350–450°C. From 450–550°C, stacking faults were longer and microtwinning was reduced. From 550–700°C, a new type of defect was observed which had lengths of 40 to 140 nm and consisted of several discontinuous stacking faults which were randomly spaced and separated by two to eight atomic layers. We have referred to them as “multiply faulted defects” (MFDs). Beneath the buried oxide layer in the substrate region, the defects observed included stacking faults and ( 113 ) defects. The results indicated that some parts of the ( 1131 defects can assume a cubic diamond structure created through a twin operation across (115) planes. Details of the structure and formation mechanisms of MFDs and other defects will be discussed.
Hrem Investigation on the Interface Between a Monocrystalline Substrate and a Doped Polysilicon Layer
Authors: Paul-Henri Albarede 
Published: March 2011

AbstractArsenic doped polysilicon was deposited on a <001> oriented Si wafer. Cross-section TEM specimen preparation was performed, giving the vertical structure of the stack. The observation was done with a <110> zone axis to ensure that the interface is strictly oriented under the electron beam. High resolution imaging on the very interfacial region proved the existence of an ultrathin regular amorphous layer running along the interface (thickness 1 rim). Complementary analytical investigations showed that the layer was really amorphous (EELS) and that the dopant was overconcentrated in this layer (EDXS linescan and SIMS profile). Therefore, a slight amorphization of the interface added to an abnormal migration of the dopant gives a well detectable layer separating both crystalline phases.
New Relaxation Mechanism in Short Period Si/Ge Strained-Layer Superlattices
Authors: Wegscheider Werner , Eberl Karl , Abstreiter Gerhard , Cerva Hans , Oppolzer Helmut 
Published: March 2011

AbstractHigh quality Si/Ge strained-layer superlattices composed of a sequence of alternating 3 monolayers pure Si and 9 monolayers pure Ge have been grown by molecular beam epitaxy at 310°C on Ge(001) substrates. In order to investigate the transition from coherent to incoherent growth in these tensily strained structures a set of samples with varying number of superlattice periods has been studied by transmission electron microscopy. It is found that superlattices as thick as 33 nm at least show perfect and defect-free layer growth whereas for thicker superlattices strain accommodation occurs. For this strained heteroepitaxial system we observed, to our knowledge, for the first time the formation of microtwins as the only relaxation mechanism. High-resolution lattice imaging reveals that the twin lamellae result from successive glide of 90° (a/6)<112> Shockley partial dislocations on adjacent {111} planes from the surface towards the bulk. The activation barrier which has to be overcome in the case of 90° partial dislocations is compared with the energies required for the nucleation of 60° perfect and 30° partial misfit dislocation half-loops.
HREM of Defects in GaAs/Ga1-xInxAs Strained Layer Superlatuices
Authors: Unal O. , Laurich B. K. , Mitchell T. E. 
Published: March 2011

AbstractGaAs/Gal-xInxAs strained layer superlattices with well-widths of 7nm, barrier widths of 14nm and periods of 10 to 30 have been examined by HREM both in plan view and cross section. Strain release occurs mostly by dislocation generation but twins are also observed, especially at the substrate interface. High resolution images of dislocations, twins and interfaces are analyzed to elucidate mechanisms of strain release.
Electron Microscopy of Ordering Related Defects in Alloys.
Authors: Broddin D. , Leroux C. , Tendeloo G. Van 
Published: March 2011

AbstractRecent results are presented which indicate that the core structure of anti-phase boundaries is sensitive to changes in temperature and alloy composition. Isolated anti-phase boundaries in CoPt3 are found to undergo a structural change when the order-disorder transition temperature is approached from below. Periodic anti-phase boundaries of the long period structures in Cu3Pd, Au3Zn and Au3Cu exhibit similar phenomena. Detailed results on the core structure of periodic boundaries in alloys annealed close to the order-disorder transition are compared to the results of a Monte Carlo analysis for finite temperatures of (100) anti-phase boundaries in L12 alloys.
Nanostructure Evolution During Processing of Thin-Film Gels: A High-Resolution Electron Microscopic Study. 2. The Thin-Film Gel Derived From Pb(Zr0.45Ti0.55)O2(OR)2
Authors: Kang C. , Dey S. K. , Eyring L. 
Published: March 2011

AbstractHigh-resolution electron microscopic examination of alkoxide thin-film gels has been employed to study the drying and aging of thin-film Pb(Zr0.45Ti0.55)O2(OR)2as it evolves from the gel to the ferroelectric perovskite product. The initially amorphous film is observed to aggregate to form ordered islands with inter-metal distances close to that of the final structure embedded in a highly disordered matrix. When these aggregates are at the surface they grow and decompose more rapidly to the perovskite product. The progress to a polycrystalline final state is followed and recorded in real time and in time-lapse at high resolution.
Annealing of Alpha-Recoil Damage in Natural Titanite, CaTiSiO5.
Authors: Eby Ray K. , Ewing Rodney C. 
Published: March 2011

AbstractIsothermal and isochronal annealing of alpha-recoil damage was performed on the mineral titanite, CaTiSiO5. Crushed-grain samples were heated for 21 hrs, at 100°C intervals from 300°-700°C. HRTEM imaging of alpha-recoil collision cascades (amorphized regions), after each temperature interval, showed that there was no change in the abundance or appearance of the cascades at 300°C, but an apparent decrease in cascade size occurs at 400°C (from 3.8 nm to 2.4 nm diameter). A decrease in the size of collision cascades may indicate repair of interstitial defects at cascade boundaries (where interstitials dominate), while the cascade cores remain amorphous (cores acquire more extensive knock-on damage). At 500°C, the number of collision cascades observed decreases by greater than 90%, indicating major annealing of the amorphous cascade cores, and precipitates appear on titanite grain surfaces. At 600°C, changes do not occur. At 700°C, both the cascades and precipitates are absent; the alpha-recoil damage is fully annealed.
Dynamic TEM Observation on Oxide Glass Materials
Authors: Iijima Sumio 
Published: March 2011

AbstractIntensity fluctuation in high resolution electron microscope (HREM) images of amorphous Tl-Ba-Ca-Cu-O oxide films is observed. The fluctuation with a frequency of few tens of Hertz and an amplitude of about 0.3nm, occurs under an intense electron beam irradiation. It is shown experimentally that atom migration in the films is responsible for the fluctuations. The result is also supported by computer image simulations on a model structure for amorphous film.
Structures of Nb/Al2O3 Interfaces Produced by Different Experimental Routes
Authors: Mayer J. , Mader W. , Knauss D. , Ernst F. , Rühle M. 
Published: March 2011

AbstractNb/Al2O3 interfaces were produced by (i) diffusion bonding of single crystalline Nb and Al2O3 at 1973 K, (ii) internal oxidation of a Nb-3at.% Al alloy at 1773 K, and (iii) molecular beam epitaxy (MBE) growth of 500 nm thick Nb overlayers on sapphire substrates at 1123 K. Cross-sectional specimens were prepared and studied by conventional (CTEM) and high resolution transmission electron microscopy (HREM). The orientation relationships between Nb and Al2O3 were identified by diffraction studies. HREM investigations revealed the structures of the different interfaces including the presence of misfit dislocations at or near the interface. The results for the different interfaces are compared.
Motion of Crystal/Crystal and Crystal/Amorphous Interfaces
Authors: Batstone J. L. 
Published: March 2011

AbstractMotion of ordered twin/matrix interfaces in films of silicon on sapphire occurs during high temperature annealing. This process is shown to be thermally activated and is analogous to grain boundary motion. Motion of amorphous/crystalline interfaces occurs during recrystallization of CoSi2 and NiSi2 from the amorphous phase. In-situ transmission electron microscopy has revealed details of the growth kinetics and interfacial roughness.
A Study on the Mechanism for the Influence of High Density of Defect Movement on the Leakage Current of PN Junction
Authors: Tonghe Zhang , Shenghui Zhou , Yuguang Wu , Yan Luo 
Published: March 2011

ABSTRACTThe results in the paper show that high defect density appears during rapid thermal annealing. The spreading of the defect distribution increases with increasing of the annealing time. So the leakage current increases up. It is found that the PN junction leakage current for short annealing time(5s) and for hot implantation are obviously lower than that of RT implantation. The mechanism of the leakage current reduction is discussed.
Device-Degradation in III-V Semiconductor Lasers and Led's—Influence of Defects on the Degradation—
Authors: Ueda O. 
Published: March 2011

ABSTRACTMaterial issues in III-V alloy semiconductors and our current understanding of degradation in III-V semiconductor lasers and LED's are systematically reviewed.Generation of defects and thermal instability are among these issues for these systems. Defects introduced during crystal growth are classified into two types: interface defects and bulk defects. Defects belonging to the former type are stacking faults, V-shaped dislocations, dislocation clusters, microtwins, inclusions, and misfit dislocations, and the latter group includes precipitates and dislocation loops. Defects in the substrate can also be propagated into the epi-layer. Structural imperfections due to thermal instability are also found. They ame quasi-periodic modulated structures due to spinodal decomposition of the crystal either at the liquid/solid interface or growth surface, and atomic ordering which also occurs on the growth surface through migration and reconstruction of the deposited atoms.Three major degradation modes, rapid degradation, gradual degradation, and catastrophic failure, are discussed. For rapid degradation, recombination-enhanced dislocation climb and glide are responsible for degradation. Differences in the ease with which these phenomena occur in different hetero-structures are presented. Based on the results, dominant parameters involved in the phenomena are discussed. Gradual degradation takes place presumably due to recombination enhanced point defect reaction in GaAlAs/GaAs-based optical devices. This mode is also enhanced by the internal stress due to lattice mismatch. However, we do not observe this mode in InGaAsP/InP-based optical devices. Catastrophic failure is found to be due to catastrophic optical damage at a mirror or at a defect in GaAlAs/GaAs DH lasers, but not in InGaAsP/InP DH lasers. In each degradation mode, the role of defects in the degradation and methods of elimination of degradation are discussed.
Macroscopic Stress and Device Reliability of 1.3μm and 1.5μm Wavelength GaInAsP Channeled Substrate Buried Heterostructure Lasers
Authors: Swaminathan V. , Koszi L. A. , Focht M. W. 
Published: March 2011

ABSTRACTThe macroscopic stress of 1.3μm and 1.5μm wavelength GaInAsP-InP channeled substrate buried heterostructure lasers is related with device reliability. The radius of curvature, R, of the device is taken as a measure of its macroscopic stress and the change in dc threshold current, ΔIth, after an accelerated aging test is taken as a measure of device reliability, with high ΔIth, indicating decreased reliability. R or ΔIth was changed by altering the p-side contact width or the p-side Au bonding pad thickness. No correlation was found between R and ΔIth. For example, changing the p-contact width from 6 to 125μm resulted in a reduction of ΔIth by a factor of 2 – 10 among the wafers studied. However, the change in the active layer stress, as determined by R−1, was at most only 25%. Similarly, increasing the Au bonding pad thickness from 0.6 to 9.0μm increased the active layer stress by a factor of 2, but with little change in Alt. It is concluded that the macroscopic stress does not affect device reliability for the GaInAsP lasers.
Influence of Point Defects on GaAs Devices
Authors: Look David C. 
Published: March 2011

ABSTRACTFrom electron-irriadiation studies, it is known that point defects can strongly affect the electrical properties of GaAs-based MESFET's, MODFET's, solar cells, resonant-tunneling diodes, MIMIC circuits and other devices. As an example, 1 × 1016 cm−2, 1 MeV electrons reduce the transconductance in a 1 μm by 200 μm MESFET by nearly an order of magnitude. Fortunately, annealing at 350 °C for 10 min. can largely restore the device performance, although not without some adverse effects. Point defects, or simple point defect complexes, can also exist in as-grown GaAs and affect devices in several different ways. For example, an As-rich stoichiometry can lead to an abundance of Ga vacancies, and thus to a higher Si donor activation in implanted MESFET devices; however, it can also promote an increase in unwanted impurities which sit on the Ga site. As another example, extremely high (> 3 × 1019 cm−3 ) concentrations of As arntisites, which are found in MBE GaAs grown at 200°C, lead to very unusual electrical and optical properties, and make possible a highly useful buffer material anid a very fast photoconductive switch. However, there are also adverse effects here, such as slow-transients in some MODFET devices, which may result from defect diffusion. Thus, the effects of point defects in GaAs devices must be understood.