bluuebunny/crossref_metadata_2025_split huggingface dataset:
The Evolution of Chem-Mechanical Planarization: From Aberrant to Prosaic
Authors: Renteln Peter , Coniff John 
Published: April 2011

ABSTRACTChem-Mechanical Planarization (CMP) is a rapidly growing technology in the semiconductor fabrication repertoire. Initially offering an answer to the need for truly global planarization brought about by optical steppers' ever decreasing Depth of Focus (DOF), CMP may come to stay more for its impressive ability to actually decrease defect density, as well as potentially reduce the contact resistance of Tungsten plugs. But even the use of CMP at this post-etchback step first requires a manufacturable oxide planarization CMP technology, the single most difficult challenge of all the different CMP applications. In this presentation, We will describe various remaining mysteries of some of the more fundamental questions involving the process in addition to some present manufacturing issues.
Consumables for the Chemical Mechanical Polishing (Cmp) of Dielectrics and Conductors
Authors: Jairath Rahul , Desai Mukesh , Stell Matt , Tolles Robert , Scherber-Brewer Debra 
Published: April 2011

ABSTRACTChemical mechanical polishing (CMP) is rapidly becoming the process of choice for planarizing dielectrics in very large scale integrated circuits. In addition, it is being used at an increasing rate in the removal of metals in order to define conducting levels. In the case of dielectric CMP, planarization ability is dictated by the mechanical aspects of polishing such as pad rigidity, polishing pressure and speed of the polishing platen, while inherent removal rate of the dielectric material is generally a function of the polishing chemistry. Polishing rate of both, dielectric and metallic films can be significantly increased by changing the nature of the dispersed abrasive in the slurry and that of the dispersing agent. However, such changes have profound implications to the surface quality, planarity, and cleaning of the polished surface. In addition, the polishing pad plays an important role in manufacturability of metal CMP processes. This work reviews the chemistry of polishing slurries containing silica, ceria and alumina abrasives for dielectric and metal CMP. Also, the contribution of the polishing pad to CMP processes is explained. The need for balancing the chemical and mechanical aspects of polishing in order to achieve overall planarization and pattern definition is demonstrated.
Surface Layer Formation During the Chemical Mechanical Polishing of Copper Thin Films
Authors: Steigerwald J.M. , Murarka S.P. , Duquette D.J. , Gutmann R.J. 
Published: April 2011

ABSTRACTThree chemical processes that occur during the chemical mechanical polishing (CMP) of copper are described in terms of their effect on surface planarity, polish rate, and corrosion resistance of the polished copper. These processes are surface layer formation, dissolution of mechanically abraded copper, and chemical acceleration of the polish rate. The role of these processes is demonstrated with two slurry formulations used in the CMP of copper at Rensselaer.
The Surface Damage in SiO2 Caused by Chemical Mechanical Polishing on Ic-60 Pads
Authors: Murarka Shyam , Ko Sen-Hou , Tomozawa Minoru , Ding Pei-Jun , Lanford William A. 
Published: April 2011

ABSTRACTChemical Mechanical polishing (CMP) is a useful technique for achieving global planarization in the ICs. The CMP of oxide has been used and studied for decades. Only recently the technique has been employed for planarizing the interlayer dielectric (ILD) on the silicon devices circuits. The effect of such polishing on the performance of the ILD has been the concern. This paper examines the attempts on defining the damage caused by CMP and its effect on the electrical properties after polished SiO2 wafers. In this investigation the PECVD and thermal oxide films were polished in the colloidal silica slurry on IC 60 pad. The polished oxide were then studied using I-V and nuclear reaction technique. The results show a surface damage which extends to about 800 Å in the polished oxide. The changes occurring in the concentration of hydrogenous species at the surface of SiO2 as determined by nuclear reaction technique will also be presented. It is shown that due to CMP as-deposited CVD SiO2 films loose water from surface regions whereas well annealed or dry oxides gain water at the surface. The results will be discussed and mechanisms will be presented to explain electrical results.
Growth Kinetics and Materials Properties of Cu5Si
Authors: Hymes S. , Murarka S.P. , Ding PJ. , Wang W. , Lanford W.A. 
Published: April 2011

ABSTRACTThin copper films have been passivated by exposure to a dilute silane mixture (2% SiH4/Ar) at temperatures in the range of 225 - 375 °C. Previous XRD characterization indicates the surface layer to be Cu5Si[l]. Subsequently, the growth kinetics were examined by sheet resistance (Rs), RBS and step height measurements. Two distinct growth regimes are observed. The flow rate and time dependencies of the low temperature growth indicate parabolic solid state diffusion limited growth. The corresponding activation energy is 0.7 eV. A mass transport limitation is evidenced at higher temperatures. In addition, the biaxial stress and adhesion responses have been observed using the substrate curvature technique and scotch tape peel tests, respectively. A biaxial modulus (Eb) of 2.9x1011 Pa and coefficient of thermal expansion (CTE) of 8.6xl0-6 /°C have been determined from stress temperature cycling on Si and a-quartz substrates.
Room Temperature Oxidation of Silicon Catalyzed by Cu3Si
Authors: Liu C. S. , Chen L. J. 
Published: April 2011

ABSTRACTThe dependence of room temperature oxidation of silicon catalyzed by Cu3Si on silicide thickness, silicide grain size and the substrate orientation has been investigated by transmission electron microscopy and x—ray diffractometry.The extent of oxidation was found to depend critically on the thickness of starting Cu3Si film. The oxidation was found to be more restricted on (lll)Si than that of (001)Si samples. The thickness of SiO2 layer was found to decrease with the average grain size of the starting Cu3Si layer. HRTEM revealed that the oxidation is initiated at the grain boundaries. Oxide film as thick as 4.5 μm was grown at room temperature over a period of two weeks in (001) samples. The growth of thick oxide film was achieved by minimizing the grain size of Cu3Si through a reaction between Cu and an intermediate amorphous silicon layer at 200 °C.
The Stability of Reactively Sputtered WNx Thin Films on III-V Semiconductors
Authors: Pang Zhengda , Boumerzoug Mohamed , Mascher Peter , Simmons John G. 
Published: April 2011

ABSTRACTWNX thin films were deposited at room temperature on (100) n-type GaAs substrates by rf reactive sputtering of a high purity W target in Ar/N2 gas mixtures. Deposition parameters such as the rf power, the ratio of gas flows, and the total pressure can be optimized for the preparation of uniform and low resistivity WNX thin films. The W:N ratio in the as-deposited WNX films was determined using Auger spectroscopy and the morphology was examined by scanning electron microscopy (SEM).The WNx/GaAs samples were subjected to rapid thermal annealing in an N2 atmosphere at temperatures between 400°C and 800°C. The thermal stability of these structures was examined using electrical measurements and Auger profiling . The results are correlated with the properties of as-deposited films and the influence of various processing parameters will be discussed.
The Effects of Interfacial Reactions in the Formation of Ohmic Contacts to GaAs
Authors: Fischer Verlyn , Viljoen P.E. , Ristolainen E. , Holloway P.H. , Lampert W.V. , Haas T.W. , Woodall J.M. 
Published: April 2011

ABSTRACTThe effect of heat treatments between 400°C and 500°C on electrical contacts of In, Ga, Pb, and AU to n- or p-GaAs, and Ni to n-GaAs have been studied using current-voltage (I-V), Auger electron spectroscopy and scanning electron microscopy. Ohmic contacts were formed between In and GaAs upon heating due to formation of an InGaAs surface layer with low interfacial transport barriers. The contacts between Ga or Pb and n- and p-GaAs remained rectifying due to a lack of interfacial reaction. Films of Au reacted with both n-and p-type GaAs resulting in rectangular "pits". This led to ohmic contacts only on n-type substrates due to segregation of the Si dopants to the surface of the decomposed GaAs "pits". Dopant segregation did not occur when Au reacted with p-GaAs or Ni reacted with n-GaAs, thus these contacts remained rectifying at lower doping densities (4 x 1017 cm-3).
Buried Schottky Contacts in Patterned Cobalt Silicide Layers in Silicon Using Wafer Bonding
Authors: ThungströM GöRan , FröJdh Christer , Petersson C. Sture 
Published: April 2011

ABSTRACTWe have fabricated buried cobaltdisilicide schottky contacts in silicon using wafer bonding with a patterned metal layer. The schottky contacts show good rectifying behaviour with ideality factors of 1.02-1.09 and low reverse leakage currents.
Stress-Voiding and Electromigration in Multilevel Interconnect Metallizations
Authors: Korhonen M.A. , Brown D.D. , Li C.-Y. , Rathore H.S. 
Published: April 2011

ABSTRACTStress-voiding or stress migration (SM), and electromigration (EM) are urgent problems in ULSI microcircuits with features in the submicron range. Severe stress-voiding arises in multilevel metallizations because of the high constraint offered by the refractory metal layers, the ceramic insulation, and the rigid contact and via structures which prevent plastic relaxation of the thermally induced stresses. Also, W-plugs and/or refractory barrier layers block entirely the EM flux, resulting in an enhanced probability of EM damage. We review the physical bases of a recently introduced unified SM and EM model [1,2]. We apply the model to an interconnect line confined by vias at both ends and derive equations which explicitly show the effects of external conditions and microstructural parameters on the evolution of SM and EM damage. Particularly we analyze the effects of Cu depletion on void growth rate at vias. We also show how the shifts in the line resistance are related to void growth. Finally we demonstrate that the model predictions compare well with the recently published experimental EM data.
Surface Spectroscopic Studies of the Deposition Mechanisms of TinX Films from Organometallic Precursors
Authors: Chen P. J. , Truong C. M. , Corneille J. S. , Oh W. S. , Goodman D. W. 
Published: April 2011

ABSTRACTThe adsorption and thermal behavior of tetrakis-(dimethylamido)-titaniurn (TDMAT), Ti[NMe2]4, were investigated by surface spectroscopic techniques in the temperature range 100-1100K. A metallic Ti substrate readily dissociates TDMAT even below 300 K, producing a carbon-rich interface. When the substrate is exposed to a continuous flux of TDMAT at growth temperatures (550-700K), deposition of carbon-rich TiCxNy films readily occurs with a high precursor reactive sticking coefficient. With the addition of sufficient NH3 flux, we demonstrate the existence of a direct surface-reaction-driven deposition mechanism which involves reaction(s) between adsorbed TDMAT and NHX species on the film surface and thus leads to growth of substantially cleaner TiNx films. This growth mechanism dominates at low pressures (≤10-4Torr) where gas-phase reaction between the precursor gases becomes insignificant.
Electronic Structure of Rare-Earth Pnictides for Metallization of Semiconductors
Authors: Petukhov A. G. , Lambrecht W. R. L. , Segall B. 
Published: April 2011

ABSTRACTThe results of first-principles calculations of the electronic band structures, equilibrium lattice constants, cohesive energies, bulk moduli, and magnetic moments are presented for the rare-earth pnictides with the rocksalt structure and chemical formula RX, where R = Gd, Er and X = N, P, As. Some of these materials are semimetals and are suitable for metallization of III-V semiconductors. The results for the lattice constants are in good agreement with experimental data. For ErAs, which is closely lattice-matched to GaAs, the calculated magnetic exchange splittings, electron and hole concentrations, Fermi surface cross-sectional areas and cyclotron masses are found to be in satisfactory agreement with the available experimental data.
Electron and Photon Irradiation Effects in Metal/Amorphous Chalcogenide Bilayers
Authors: Ploessl Andreas , Dhanjal B.J. , Fitzgerald A.G. , Gibson R.A.G. , Gillies A.D. 
Published: April 2011

ABSTRACTThin film bilayers of metal and amorphous chalcogenides have been prepared by evaporation. The metals were silver and zinc, while the chalcogenides were P2Se3 and arsenic sulphides, mainly As2S3. The metals dissolved into the chalcogenide films when illuminated with ultraviolet light or when irradiated with an electron beam. The changes in composition and chemical bonding which were caused by this irradiation, were investigated by x-ray photoelectron spectroscopy. The concomitant structural changes have been investigated by electron diffraction.After the metal and chalcogenide had intermixed, either due to photon or electron irradiation, the layers became sensitive to an electron beam; this sensitivity depended on the composition of the chalcogenide. Energy-dispersive x-ray microanalysis showed that the electron beam rapidly, but reversibly, depleted the irradiated areas of the dissolved metal. Very fine patterns, of better than half-micron resolution, could be written. By exposing a pure arsenic sulphide film through a shadow mask to ultraviolet light, zinc could be deposited selectively to form fine patterns. Plasma processing developed either kind of pattern reliably, thus rendering the material a dry inorganic resist for photo- and electron-beam-lithography with potential benefits in particular for GaAs.
Designing and Building Reliability Into VLSI Interconnect Systems
Authors: Graas Carole D. , Hong Qi-Zhong , L Ting Larry 
Published: April 2011

ABSTRACTThe optimization of electromigration (EM) and stress-induced voiding (SV) properties of advanced interconnects impacts many critical system design parameters. In particular, the choice of materials and manufacturing processes must be carefully planned during the early phases of product development. In layered metallizations, both the barrier and capping layers design can affect electromigration resistance and stress-relaxation behavior, while electrical performance often constitutes a trade-off. This is shown specifically in a study of titanium diffusion into Al-Cu from TiN barrier layers, and in initial stress-relaxation tests characterizing the effect of Ti addition in the capping layer. The development of advanced characterization techniques supports the trial-and-error experimental optimization process, but models predicting EM and SV reliability are needed and should include complex sets of microstructural and design parameters.
Interfacial Reactions Between Sputtered Cr-Sio2 Cermet Thin Film and Polyimide.
Authors: Yamazaki Tetsuya , Watanabe Takayoshi , Ogata Kiyoshi , Narizuka Yasunori , Inoue. Takashi 
Published: April 2011

ABSTRACTInterfacial chemical bonding states between polyimides (PI) and sputter coated Cr-SiO2 thin film have been investigated mainly by XPS to obtain a reliability basis for thin film resistor application of Cr-SiO2.We tried to leave different level of etch residue by applying two etchants of different etching power, then analyzed the etched surfaces by XPS, TEM and EXAFS. It proved that at first Cr in the sputtered Cr-SiO2 reacts with oxygen atoms which were introduced during O2 plasma treatment of the PI surface and also with original carbonyl oxygen of the PI to offer Cr-O-C bond at the Cr-SiO2/PI interface. This was concluded from the attenuation of Cls peak intensity corresponding to the carbonyl group. Then after thermal annealing, Cr extracted most of the interface oxygen to give a Cr2O3 layer of a discrete thickness. These phenomena were supported by TEM and SR-EXAFS as well.
Electronic Process of Joining Metal and Ceramic by “Surface Activated Bonding”
Authors: Ohuchi Fumio S. , Hu Xiao , Suga Tadatomo 
Published: April 2011

ABSTRACTResidual thermal stresses due to thermal expansion mismatch at dissimilar material interfaces can cause serious problems in the current bonding technology, yet this is an unavoidable consequence as long as the interfaces are fabricated at elevated temperatures. An innovative solution to this problem is that the materials be bonded without applying heat, i.e., bonding at room temperature. A new technique to join two dissimilar materials, “Surface Activated Bonding (SAB)”, has been recently developed. The basic concept underlying this technique is that two atomically clean solid surfaces under contact develop a strong adhesive force. We have recently demonstrated that this method works on various materials systems, including Al2O3, A1N, SiC and Si3N4, on which polycrystalline aluminum is bonded at room temperature. In this paper, we will describe: What is “Surface Activated Bonding”? What are the electronic and chemical driving factors for bonding? Complementary experimental and theoretical studies in elucidating the fundamental aspects of the SAB will be described.
A Multilayer Interconnect Process for 0.5um Logic Technology
Authors: Kim Donghyun , Oh H.S. , Lee K.Y. , Kim Y.S. , Kim B.S. , Kim B.G. 
Published: April 2011

ABSTRACTA submicron triple metal process for 0.5um logic CMOS is described, focusing on key process steps such as the dielectric planarization and metallization. The main emphasis has been placed on development of arcomplicated planarization process utilizing SOG (Spin on Glass) etchback. In this paper, we report process data of triple metal technology which uses aluminum alloy for interconnects and P-TEOS (Plasma Tetra Ethyl Ortho Silicate) with siloxane SOG and etchback process for planarization.
Diamond Field-Effect Transistors
Authors: Dreifus David L. , Tessmer Alison J. , Holmes Joseph S. , Kao Chien-Teh , Malta Dean M. , Plano Linda S. , Stoner Brian R. 
Published: April 2011

ABSTRACTMetal-oxide-semiconductor field-effect transistors (FETs) have been fabricated using B-doped diamond thin films deposited on polycrystalline, (100) highly-oriented, and single crystal diamond insulating substrates. Diamond films were grown using a microwave plasma chemical vapor deposition technique. Various electrical and materials characterization techniques were employed to confirm that the films exhibited properties suitable for FET fabrication. Devices with gate lengths and widths of 2 μm and 314 μm respectively, were processed using standard photolithography. Silicon dioxide was used as the gate dielectric. Current-voltage characteristics of these devices have been measured during variable temperature cycling in air. Devices fabricated on the randomly oriented polycrystalline diamond substrates have been operated to 285°C. Field-effect transistors fabricated using the highly-oriented diamond substrates have been characterized to 400°C. Single crystal diamond devices exhibited saturation and pinch-off of the channel current at temperatures up to 500°C. These devices have been biased in amplifier circuit configurations that have been characterized from 20 Hz to 1 MHz. Single crystal FETs exhibited voltage gain over an extended temperature range. Transconductances as large as 1.7 mS/mm have been observed. The electronic properties, fabrication technologies, and performance of devices fabricated on the three diamond substrate materials will be discussed and compared.
Excimer Laser Planarization of Diamond Films
Authors: Lee Dong-Gu , Harkness S. D. , Singh Rajiv K. 
Published: April 2011

ABSTRACTThe planarization of rough polycrystalline diamond films synthesized by DC arc discharge plasma jet CVD was attempted using KrF excimer laser pulses. The effects of laser incidence angle and reaction gases (ozone and oxygen) on etching rate were studied. The temperature change of diamond and graphite with different laser fluences was calculated by computer simulation to explain the etching behavior of diamond films. The calculated threshold energy density for etching of pure crystalline diamond was about 1.7 J/cm2. However, the threshold energy density was affected by the angle of laser incidence. Preferential etching of a particular crystallographic plane was observed through scanning electron microscopy. The etching rate of diamond with ozone was lower than that with oxygen. Also, the etching rate of diamond films at normal laser incidence was lower than that of films tilted at 45° for laser fluences above 2.3 J/cm2. When the angle of incidence was 80° to the diamond surface normal, the peak-to-valley surface roughness was significantly reduced, from 30 μm to 0.5μm.
Electronic and Optoelectronic Devices Based on GaN-AIGaN Heterostructures
Authors: Asif Khan M. , Kuznia J. N. , Krishnankutty S. , Skogman R. A. , Olson D. T. , Schaff W. J. , Burm J. W. , Shur M. S. , George T. 
Published: April 2011

ABSTRACTAvailability of optoelectronic components operating in the U V-Visible part of the spectrum opens several exciting and important system applications. Solid state ultraviolet and blue-green lasers can increase the optical data storage density of CDROM/WORM and magneto-optical disks by a factor of four. They are also ideally suited for environmental pollutant identification and monitoring. On the other hand, solid state ultraviolet detectors that do not respond to visible or IR radiation are highly desirable for various commercial systems. These include medical imaging, industrial boiler systems, fire/flame safeguard systems around oil and gas installations and several military applications. A key requirement for these ultraviolet laser and sensor devices is the availability of a semiconductor material system with high quality controlled doping and fabrication technology.AlxGa1−xN and InxGa1−xN for which the direct bandgap can be tailored from the visible to the deep UV is such a material system. Ours and several other research groups (nationally and internationally) have been developing AlxGa1−xN materials and processing technologies over the past several years. Recently, by employing innovative approaches, significant advances have been made in heteroepitaxy of AlxGa1−xN on sapphire substrates. Also, controlled n and p-type doping has been achieved. Several high performance devices that form the basis of exciting future research have been demonstrated. These include high responsivity visible blind ultraviolet sensors, basic transistor structures and high power blue light emitting diodes. These pave the way for future research leading to exciting products such as blue-green lasers and UV-imaging arrays. The demonstrated transistor structures are foundation for building AlxGa1−xN -GaN based high power, high frequency and high temperature electronic components. In this paper, we will summarize some of our recent work and reflect on the potential and the issues in AlxGa1−xN-InxGa1−xN based device development.
Amortization and Recrystallization of 6H-SiC by ion Beam Irradiation
Authors: Heera V. , Kögler R. , Skorupa W. , Stoemenos J. 
Published: April 2011

ABSTRACTThe evolution of the damage in the near surface region of single crystalline 6H-SiC generated by 200 keV Ge+ ion implantation at room temperature (RT) was investigated by Rutherford backscattering spectroscopy/chanelling (RBS/C). The threshold dose for amorphization was found to be about 3 · 1014 cm-2, Amorphous surface layers produced with Ge+ ion doses above the threshold were partly annealed by 300 keV Si+ ion beam induced epitaxial crystallization (IBIEC) at a relatively low temperature of 480°C For comparison, temperatures of at least 1450°C are necessary to recrystallize amorphous SiC layers without assisting ion irradiation. The structure and quality of both the amorphous and recrystallized layers were characterized by cross-section transmission electron microscopy (XTEM). Density changes of SiC due to amorphization were measured by step height measurements.