bluuebunny/crossref_metadata_2025_split huggingface dataset:
The glycerophospholipid inventory of Pseudomonas putida is conserved between strains and enables growth condition‐related alterations
Authors: Rühl Jana , Hein Eva‐Maria , Hayen Heiko , Schmid Andreas , Blank Lars M. 
Published: September 2011

SummaryMicroorganisms, such as Pseudomonas putida, utilize specific physical properties of cellular membrane constituents, mainly glycerophospholipids, to (re‐)adjust the membrane barrier to environmental stresses. Building a basis for membrane composition/function studies, we inventoried the glycerophospholipids of different Pseudomonas and challenged membranes of growing cells with n‐butanol. Using a new high‐resolution liquid chromatography/mass spectrometry (LC/MS) method, 127 glycerophospholipid species [e.g. phosphatidylethanolamine PE(32:1)] with up to five fatty acid combinations were detected. The glycerophospholipid inventory consists of 305 distinct glycerophospholipids [e.g. PE(16:0/16:1)], thereof 14 lyso‐glycerophospholipids, revealing conserved compositions within the four investigated pseudomonads P. putida KT2440, DOT‐T1E, S12 and Pseudomonas sp. strain VLB120. Furthermore, we addressed the influence of environmental conditions on the glycerophospholipid composition of Pseudomonas via long‐time exposure to the sublethal n‐butanol concentration of 1% (v/v), focusing on: (i) relative amounts of glycerophospholipid species, (ii) glycerophospholipid head group composition, (iii) fatty acid chain length, (iv) degree of saturation and (v) cis/trans isomerization of unsaturated fatty acids. Observed alterations consist of changing head group compositions and for the solvent‐sensitive strain KT2440 diminished fatty acid saturation degrees. Minor changes in the glycerophospholipid composition of the solvent‐tolerant strains P. putida S12 and Pseudomonas sp. VLB120 suggest different strategies of the investigated Pseudomonas to maintain the barrier function of cellular membranes.
Racial Profiling/Biased Policing
Authors: Mosher Clayton 
Published: September 2011

AbstractMedia and legal attention to the issue of racial profiling in the United States intensified in the 1990s, with numerous studies from a wide range of jurisdictions revealing evidence of biased policing. This article briefly examines the history of biased policing in the United States, discusses the results of some of the more recent studies as well as studies of biased policing in other countries, and also devotes considerable attention to important theoretical and methodological issues in conducting research on racial profiling. These issues include how race/ethnicity should be coded, how to establish an appropriate denominator/benchmark in racial profiling studies, and what factors in addition to race/ethnicity need to be considered in analyses of bias in citations/arrests/and searches. Although attention to racial profiling waned somewhat after the September 11, 2001, attacks, recent events suggest a renewed interest in this problem.
Work and Neoliberal Globalization: A Polanyian Synthesis
Authors: Bandelj Nina , Shorette Kristen , Sowers Elizabeth 
Published: September 2011

AbstractThis article reviews sociological research about economic globalization’s impact on work and labor in developed and developing countries since the 1980s. We find that this period of neoliberal globalization influences work because of intensified activities of multinational corporations (MNCs), financialization of the global economy, and amplified prominence of international organizations, some of which diffuse neoliberal policy scripts while others mobilize a transnational civil society. Research we review generally points to liabilities of neoliberal globalization for workers. To understand these findings, we apply Karl Polanyi’s concepts of fictitious commodities, the self‐regulating market, and the double movement. We propose that, on the one hand, the activities of MNCs, international financial organizations, and many states exemplify pushes for institutional separation of economy and society in effort to institutionalize the idea of a self‐regulating market at a global scale, which increases labor commodification and global inequalities. On the other hand, the activities of social movements, including unions and transnational actors that target globalization’s impact on work, constitute the counter movement at national and global levels resisting marketization and pushing for labor decommodification. The aftermath of the ongoing economic crisis will tell to what extent this countermovement will be successful in generating an alternative to neoliberal globalization, and more protections for workers.
Soil carbon sequestration during the establishment phase of Miscanthus × giganteus: a regional‐scale study on commercial farms using 13C natural abundance
Authors: Zimmermann Jesko , Dauber Jens , Jones Michael B. 
Published: September 2011

AbstractThe use of biomass for energy production is considered a promising way to reduce net carbon emissions and mitigate climate change. However, land‐use change to bioenergy crops can result in carbon emissions from soil and vegetation in amounts that could take decades to compensate. Perennial grasses such as Miscanthus offer a possible solution to this problem as measurements on experimental plots planted with Miscanthus have shown significant carbon sequestration in the soil. It can, however, be expected that sequestration potentials in commercial use might differ from those measured in experimental plots due to different farming practices and soil characteristics. For this study, Miscanthus plantations on 16 farms in SE Ireland as well as on‐farm controls representing the former land‐use (grassland and tillage) have been examined. The Miscanthus plantations were 2–3 years old. Soil organic carbon (SOC) content and a number of soil properties were measured and the amount of Miscanthus‐derived carbon was determined using the 13C natural abundance method. On both former tillage fields and grasslands, although there were no significant differences in SOC contents between Miscanthus and control sites, it was shown that 2–3 years after Miscanthus establishment, 1.82 ± 1.69 and 2.17 ± 1.73 Mg ha−1 of the SOC under former‐tilled and former grassland respectively were Miscanthus‐derived. Mixed‐effects models were used to link the total SOC concentrations and Miscanthus‐derived carbon to the land‐use parameters as well as to soil properties. It was shown that on control sites, pH had an effect on total SOC. In the case of Miscanthus‐derived carbon, the initial SOC content, pH, former land‐use and crop age had significant effects.
Higher temperature improves the efficacy of magnetic fluid hyperthermia for Lewis lung cancer in a mouse model
Authors: Hu Runlei , Zhang Xiaodong , Liu Xuan , Xu Bo , Yang Hongsheng , Xia Qisheng , Li Liya , Chen Chunling , Tang Jintian 
Published: September 2011

AbstractPurpose:  The aim of this study was to investigate the effect of a higher temperature on the efficacy of magnetic fluid hyperthermia for Lewis lung cancer in a mouse model.Materials and methods:  Magnetic fluids were prepared in vitro and directly injected into tumors. Twenty‐four hours later, the mice were subjected to an alternating magnetic field. The temperature in the tumor was increased to 46.0°C, higher than the usual temperature used in hyperthermia therapy. The higher temperature was maintained for 30 min with a stable strength of magnetic field.Results:  Magnetic fluid hyperthermia with a higher temperature significantly inhibited the growth of the tumors (P < 0.05). The tumors completely regressed in four out of 12 mice. Histological analysis demonstrated that the tumor cells underwent apoptosis and necrosis, and the cells were arrested at the G1/G0 phase of the cell cycle. The lifespan of the treated animals also increased significantly (P < 0.05).Conclusions:  Magnetic fluid hyperthermia with a higher temperature could improve the efficacy of this therapy on lung cancer.
Psychiatric disorder, IQ, and emotional intelligence among adolescent detainees: A comparative study
Authors: Margaret Hayes Jennifer , Reilly Gary O’ 
Published: September 2011

Objectives. To document criminality, psychiatric difficulty, IQ, EQ, and EI amongst Irish, male juvenile detainees (Detainee Group). To compare their IQ, EQ, and EI to non‐offending boys attending a child psychiatry clinic (Psychiatric Group) and boys without offending or psychiatric problems (Community Group). To compare psychiatric morbidity between the detainee and psychiatric groups.Method. Criminality levels of 30 detainees were evaluated using official court charge sheets. Psychiatric status was assessed through structured clinical interview (DISC‐IV); IQ through an individually administered IQ‐scale (WASI); EQ using the BarOn EQi:Youth Version (EQi:YV); and EI using the MSCEIT: Youth Version – Research Edition (MSCEIT:YV‐RE). IQ, EQ, and EI levels in the psychiatric and community groups were compared. Psychiatric morbidity between detainee and psychiatric groups were compared.Results. A total of 335 crimes led to the detention of detainees. Eighty‐three percent of detainees had a psychiatric disorder compared to 60% of young people in the psychiatric group. Detainees had 3.1 disorders each compared to 1.4 disorders in the psychiatric group. A total of 63.3% of detainees had an externalizing problem, 37.9% an internalizing problem, and 66.7% a substance dependency or use problem. A total of 21.4% of detainees had an IQ score below 70. The detainee and psychiatric groups had similar deficits in EI and significantly lower EI than the community groups.Conclusions. Serious levels of criminality and psychiatric disorder exist amongst Irish detainees. They have significantly lower IQ than young people attending a psychiatry clinic and both share deficits in the ability to accurately identify emotions, use emotions to guide thought processes and to prioritize thinking and to effectively regulate emotions.
REDUCING DIMENSION IN GLOBAL OPTIMIZATION
Authors: DJALIL BOUDJEHEM , BADREDDINE BOUDJEHEM , ABDENOUR BOUKAACHE 
Published: September 2011

In this paper, we propose a very interesting idea in global optimization making it easer and a low-cost task. The main idea is to reduce the dimension of the optimization problem in hand to a mono-dimensional one using variables coding. At this level, the algorithm will look for the global optimum of a mono-dimensional cost function. The new algorithm has the ability to avoid local optima, reduces the number of evaluations, and improves the speed of the algorithm convergence. This method is suitable for functions that have many extremes. Our algorithm can determine a narrow space around the global optimum in very restricted time based on a stochastic tests and an adaptive partition of the search space. Illustrative examples are presented to show the efficiency of the proposed idea. It was found that the algorithm was able to locate the global optimum even though the objective function has a large number of optima.
The gem5 simulator
Authors: Binkert Nathan , Beckmann Bradford , Black Gabriel , Reinhardt Steven K. , Saidi Ali , Basu Arkaprava , Hestness Joel , Hower Derek R. , Krishna Tushar , Sardashti Somayeh , Sen Rathijit , Sewell Korey , Shoaib Muhammad , Vaish Nilay , Hill Mark D. , Wood David A. 
Published: September 2011

The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed and exible memory system, including support for multiple cache coherence protocols and interconnect models. Currently, gem5 supports most commercial ISAs (ARM, ALPHA, MIPS, Power, SPARC, and x86), including booting Linux on three of them (ARM, ALPHA, and x86).
The project is the result of the combined efforts of many academic and industrial institutions, including AMD, ARM, HP, MIPS, Princeton, MIT, and the Universities of Michigan, Texas, and Wisconsin. Over the past ten years, M5 and GEMS have been used in hundreds of publications and have been downloaded tens of thousands of times. The high level of collaboration on the gem5 project, combined with the previous success of the component parts and a liberal BSD-like license, make gem5 a valuable full-system simulation tool.
Virtualizing performance asymmetric multi-core systems
Authors: Kwon Youngjin , Kim Changdae , Maeng Seungryoul , Huh Jaehyuk 
Published: September 2011

Performance-asymmetric multi-cores consist of heterogeneous cores, which support the same ISA, but have different computing capabilities. To maximize the throughput of asymmetric multi-core systems, operating systems are responsible for scheduling threads to different types of cores. However, system virtualization poses a challenge for such asymmetric multi-cores, since virtualization hides the physical heterogeneity from guest operating systems. In this paper, we explore the design space of hypervisor schedulers for asymmetric multi-cores, which do not require asymmetry-awareness from guest operating systems. The proposed scheduler characterizes the efficiency of each virtual core, and map the virtual core to the most area-efficient physical core. In addition to the overall system throughput, we consider two important aspects of virtualizing asymmetric multi-cores: performance fairness among virtual machines and performance scalability for changing availability of fast and slow cores.
We have implemented an asymmetry-aware scheduler in the open-source Xen hypervisor. Using applications with various characteristics, we evaluate how effectively the proposed scheduler can improve system throughput without asymmetry-aware operating systems. The modified scheduler improves the performance of the Xen credit scheduler by as much as 40% on a 12-core system with four fast and eight slow cores. The results show that even the VMs scheduled to slow cores have relatively low performance degradations, and the scheduler provides scalable performance with increasing fast core counts.
TLSync
Authors: Oh Jungju , Prvulovic Milos , Zajic Alenka 
Published: September 2011

As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament barrier, a larger number of cores results in a longer latency for each round and a larger number of rounds. Hardware barrier implementations require significant dedicated wiring, e.g., using a reduction (arrival) tree and a notification (release) tree, and multiple instances of this wiring are needed to support multiple barriers (e.g., when concurrently executing multiple parallel applications).
This paper presents TLSync, a novel hardware barrier implementation that uses the high-frequency part of the spectrum in a transmission-line broadcast network, thus leaving the transmission line network free for non-modulated (baseband) data transmission. In contrast to other implementations of hardware barriers, TLSync allows multiple thread groups to each have its own barrier. This is accomplished by allocating different bands in the radio-frequency spectrum to different groups. Our circuit-level and electromagnetic models show that the worst-case latency for a TLSync barrier is 4ns to 10ns, depending on the size of the frequency band allocated to each group, and our cycle-accurate architectural simulations show that low-latency TLSync barriers provide significant performance and scalability benefits to barrier-intensive applications.
OUTRIDER
Authors: Crago Neal Clayton , Patel Sanjay Jeram 
Published: September 2011

We present OUTRIDER, an architecture for throughput-oriented processors that provides memory latency tolerance to improve performance on highly threaded workloads. OUTRIDER enables a single thread of execution to be presented to the architecture as multiple decoupled instruction streams that separate memory-accessing and memory-consuming instructions. The key insight is that by decoupling the instruction streams, the processor pipeline can tolerate memory latency in a way similar to out-of-order designs while relying on a low-complexity in-order micro-architecture. Moreover, instead of adding more threads as is done in modern GPUs, OUTRIDER can tolerate memory latency with fewer threads and reduced contention for resources shared amongst threads.
We demonstrate that OUTRIDER can outperform single threaded cores by 23-131% and a 4-way simultaneous multithreaded core by up to 87% on data parallel applications in a 1024-core system. Moreover, OUTRIDER achieves these performance gains without incurring the overhead of additional hardware thread contexts, which results in improved area efficiency compared to a multithreaded core.
Sampling + DMR
Authors: Nomura Shuou , Sinclair Matthew D. , Ho Chen-Han , Govindaraju Venkatraman , de Kruijf Marc , Sankaralingam Karthikeyan 
Published: September 2011

With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting and isolating faulty cores, but the required fault detection coverage becomes effectively 100% as the number of permanent faults increases. Dual-modular redundancy(DMR) can provide 100% coverage without assuming device-level fault models, but its overhead is excessive.
In this paper, we explore a simple and low-overhead mechanism we call Sampling-DMR: run in DMR mode for a small percentage (1% of the time for example) of each periodic execution window (5 million cycles for example). Although Sampling-DMR can leave some errors undetected, we argue the permanent fault coverage is 100% because it can detect all faults eventually. Sampling-DMR thus introduces a system paradigm of restricting all permanent faults' effects to small finite windows of error occurrence.
We prove an ultimate upper bound exists on total missed errors and develop a probabilistic model to analyze the distribution of the number of undetected errors and detection latency. The model is validated using full gate-level fault injection experiments for an actual processor running full application software. Sampling-DMR outperforms conventional techniques in terms of fault coverage, sustains similar detection latency guarantees, and limits energy and performance overheads to less than 2%.
Releasing efficient beta cores to market early
Authors: Sudhakrishnan Sangeetha , Dicochea Rigo , Renau Jose 
Published: September 2011

Verification of modern processors is an expensive, time consuming, and challenging task. Although it is estimated that over half of total design time is spent on verification, we often find processors with bugs released into the market. This paper proposes an architecture that tolerates, not just the typically infrequent bugs found in current processors, but a significantly larger set of bugs. The objective is to allow for a much quicker time to market. We propose an architecture built around Beta Cores, which are cores partially verified. Our proposal intelligently activates and deactivates a simple single issue in-order Checker Core to verify a buggy superscalar out-oforder Beta Core.
Our Beta Core Solution (BCS), which includes the Beta Core, the Checker Core, and the logic to detect potentially buggy situations consumes just 5% more power than the stand-alone Beta Core. We also show that performance is only slightly diminished with an average slowdown of 1.6%. By leveraging program signatures,our BCS only needs a simple in-order Checker Core, at half the frequency, to verify a complex 4 issue out-of-order Beta Core. The BCS architecture allows for a decrease in verification effort and thus a quicker time to market.
Rapid identification of architectural bottlenecks via precise event counting
Authors: Demme John , Sethumadhavan Simha 
Published: September 2011

On-chip performance counters play a vital role in computer architecture research due to their ability to quickly provide insights into application behaviors that are time consuming to characterize with traditional methods. The usefulness of modern performance counters, however, is limited by inefficient techniques used today to access them. Current access techniques rely on imprecise sampling or heavyweight kernel interaction forcing users to choose between precision or speed and thus restricting the use of performance counter hardware.
In this paper, we describe new methods that enable precise, lightweight interfacing to on-chip performance counters. These low-overhead techniques allow precise reading of virtualized counters in low tens of nanoseconds, which is one to two orders of magnitude faster than current access techniques. Further, these tools provide several fresh insights on the behavior of modern parallel programs such as MySQL and Firefox, which were previously obscured (or impossible to obtain) by existing methods for characterization. Based on case studies with our new access methods, we discuss seven implications for computer architects in the cloud era and three methods for enhancing hardware counters further. Taken together, these observations have the potential to open up new avenues for architecture research.
DBAR
Authors: Ma Sheng , Enright Jerger Natalie , Wang Zhiying 
Published: September 2011

With the emergence of many-core architectures, it is quite likely that multiple applications will run concurrently on a system. Existing locally and globally adaptive routing algorithms largely overlook issues associated with workload consolidation. The shortsightedness of locally adaptive routing algorithms limits performance due to poor network congestion avoidance. Globally adaptive routing algorithms attack this issue by introducing a congestion propagation network to obtain network status information beyond neighboring nodes. However, they may suffer from intra- and inter-application interference during output port selection for consolidated workloads, coupling the behavior of otherwise independent applications and negatively affecting performance.
To address these two issues, we propose Destination-Based Adaptive Routing (DBAR). We design a novel low-cost congestion propagation network that leverages both local and non-local network information for more accurate congestion estimates. Thus, DBAR offers effective adaptivity for congestion beyond neighboring nodes. More importantly, by integrating the destination into the selection function, DBAR mitigates intra- and inter-application interference and offers dynamic isolation among regions. Experimental results show that DBAR can offer better performance than the best baseline algorithm for all measured configurations; it is well suited for workload consolidation. The wiring overhead of DBAR is low and DBAR provides improvement in the energy-delay product for medium and high injection rates.