bluuebunny/crossref_metadata_2025_split huggingface dataset:
77.4: Invited Paper: Development of Flexible Displays Driven by Organic TFTs
Authors: Nomoto Kazumasa 
Published: October 2010

AbstractWe have developed organic TFT (OTFT)‐driven flexible full‐color OLED displays and flexible electrophoretic displays driven by printed OTFTs. In this paper, we will discuss materials, structures and integration process of the display and improvement of its stability by chemical treatment of interfaces.
78.1: Ultra Compact Polarization Recycling System for White Light LED based Pico‐Projection System
Authors: Tan Li , Huang Ho‐Chi , Kwok Hoi‐Sing 
Published: October 2010

AbstractAn ultra compact polarization recycling system, for white light LED based projectors, is proposed. White light LED is applied as the light source, which is composed of blue LED die and yellow phosphor. By optimizing the illumination optics and properly placing a reflective type polarization film, the light with non‐useable polarization state will be reflected back and concentrated right on to the phosphor surface. The yellow phosphor will be reexcited by the blue spectrum component of the reflected light. More light energy will be recycled by attaching a piece of quarter wave plate before the reflective type polarization film. Experimental results show more than 30% light efficiency improvement.
78.3: Dual Mode Projection Display System for Mobile Devices
Authors: Yao Po‐Hung , Chen Wu‐Feng , Chen Chen‐Huan , Shieh Han‐Ping , Lin Wilson W. , Tung Gilbert H. , Travis Adrian 
Published: October 2010

AbstractWith removing the LC panel from a conventional portable device, we proposed an innovative dual‐mode projection display system combining pico projector technology and rear display technologies, including a wedge display feature and a reflective air chamber feature, to provide switchable display modes for front, rear or front‐rear projection operations in one portable device.
9.4:Invited Paper: EcoDesign for TV Displays
Authors: Teunissen Kees Cornelis , Schoenmakers Theo JM , de Olde Jan Leendert 
Published: October 2010

AbstractThe world population is still growing, while the consumers in the emerging markets become more affluent. The consequential environmental impact shall be assessed for the whole product lifecycle. for televisions, the displays dominate the environmental profile and therefore their energy use is one of the key priorities in our EcoDesign approach.
79.3: Effect of Surface Treatment on the Performance of TIPS Pentacene TFT by Inkjet Printing
Authors: Choi Min Hee , Lee Sun Hee , Kim Sung Hoon , Jang Jin , Kwon Soon Ki 
Published: October 2010

AbstractWe have studied the effect of self‐assembled monolayer (SAM) on the performance of printed TFT for a bottom contact, bottom gate TFT. A 6,13‐bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) was inkjet printed on the Ag source and drain electrodes. To reduce the energy barrier (1.6 eV) between the pristine Ag and TIPS pentacene, the Ag layer was treated by pentafluorothiophenol. And we controlled the physical interactions at the semiconductor/gate dielectric(photoacryl) interface by inserting a hydrophobic SAM of organoalkyl‐Silanes with octyltrichlorosilane or β‐phenethyltrichlorosilane. The results show that the TIPS pentacene TFT with PFBT/PTS treatment has field‐effect mobility of 0.18 cm2/Vs, subthreshold slope of 0.6 V/decade, and on/off current ratio of 107.
80.1: Technologies and Applications for Large Sized High Resolution Tiled Display System
Authors: Deshpande Sachin , Daly Scott 
Published: October 2010

AbstractWe have developed a large sized high resolution “SharpWall” — a tiled display system prototype with 10000 × 4500 pixel resolution and 177‐inch diagonal size. We have developed technologies which provide 4K video streaming, on‐display spatialized audio per application, and remote desktop connectivity. We have also built an application toolkit and an inter‐tile synchronization design tool which can enable building lower cost tiled display systems.
80.2: 60‐inch Highly Transparent See‐through Active Matrix Display without Polarizers
Authors: Satoh Eiji , Asaoka Yasushi , Deguchi Kazuhiro , Ihara Ichiro , Minoura Kiyoshi , Fujiwara Sayuri , Miyata Akio , Itoh Yasuhisa , Iyama Yuichi , Shibasaki Masakazu , Kikuchi Katsuhiro , Kubo Masumi 
Published: October 2010

AbstractFor the first time, we have developed a 60‐inch diagonal size see‐ through display using polymer network liquid crystal (PNLC) technology. The color display system by combination of the see‐ through display and a projector enables distinguishing eye‐catch effect. It creates new application of displays, such as information display, digital signage and substitution of window.
80.4: Interactive and Natural Viewing of Giga‐pixel Images on Large‐Size Tiled Displays
Authors: Yuan Chang 
Published: October 2010

AbstractThe increasingly popular giga‐pixel panorama images pose a new challenge for displays: how can one view them interactively and naturally? We propose a new approach for interactive viewing of giga‐pixel images on large‐Size tiled displays, where the on‐screen images are controlled by viewers' natural movement in front of the display.
P‐2: Visual Strain Evaluation of Physiological Effect by Using 3D Display
Authors: Maeda Mitomo , Tsumura Norimichi , Nakaguchi Toshiya , Okamoto Ryutaro , Simoyama Ichiro , Miyake Yoichi , Yamamoto Shoji 
Published: October 2010

AbstractWe evaluate the influences on visual strain and visually‐induced motion sickness in observing 3D image. Based on the SSQ analysis, it is clear that the correlation between visual strain and physical factors of 3D display is more than 90%.
P‐4: A Reconfigurable Stereomicroscopic Imaging System for Digital Pathology
Authors: Cheng Wei‐Chung , Gavrielides Marios A. , Badano Aldo 
Published: October 2010

AbstractA reconfigurable stereomicroscope system consisting of exchangeable light source, condenser, objectives, cameras, and 3D display was designed to allow the user to adjust the convergence angle, magnification and color rendering arbitrarily. To evaluate the depth resolution of the proposed 3D system, miniature 3D models were used as test patterns in psychophysical experiments.
P‐5: A New 360‐degree Holo‐views Display System with Multi‐vertical Views
Authors: Xia Xinxing , Wu Jiang , Van Caijie , Liu Xiangdong , Li Haifeng , Liu Xu 
Published: October 2010

AbstractA new kind of full parallax display system has been investigated with 360‐degree horizontal holo‐views and multi‐vertical views, based on a high frame rate projector. The system used a fix cylindrical direction selective diffusion screen to present a vivid 3D scene in the center of the cylindrical column. It is a possible way to get full parallax 3D holo‐view display in future.
10.2: Crosstalk Suppression by Image Processing in 3D Display
Authors: Chang YuCheng , Ma Chih‐Yao , Huang YiPai 
Published: October 2010

AbstractWe proposed a Digital Crosstalk Reduction DCR method to suppress optical crosstalk in 3D display without using any extra hardware components. Furthermore, DCR method can be applied to most of the 3D display technologies. In this paper, a 17inch pattern retarder stereoscopic display and a 12views autostereoscopic display were verified to yield less crosstalk by applying DCR method.
P‐8: Depth‐Map‐Based Multi‐View Synthesis Using Joint Bilateral Upsampling on GPUs
Authors: Wu Meng‐Sung , Chuang Yung‐Yu , Liu Yen‐Tzu , Hu Cheng‐Chung 
Published: October 2010

AbstractStereoscopic displays have become more and more common. A popular method for synthesizing 3D content is depth‐image‐based rendering, in which multi‐view images are synthesized from a color frame and an accompanying depth map. However, when the image resolution increases, it is expensive to use a full‐resolution depth map because its high storage cost and decoding overhead. In addition, since the depth map is often smooth, it is often not necessary to store the full‐resolution depth map. This paper uses a low‐resolution depth map and increases its resolution at run time using joint bilateral upsampling on GPUs. By doing so, we are able to display high‐resolution stereoscopic videos on an autostereoscopic display.
P‐12: Depth Super‐resolution for Enhanced Free‐viewpoint TV
Authors: Lim Ilsoon , Wey Hocheon , Park Dusik 
Published: October 2010

AbstractDepth maps are used in many applications, e.g. 3D television, 3D computer graphics, etc. Often, depth maps are available at a lower resolution compared to the corresponding color images. for these applications, depth maps must be scaled up to the color image resolution. We present a super‐resolution method of depth maps. The proposed method is based on the observation that significant transitions in depth intensity influence the overall quality of synthesized virtual view. In order to preserve the object boundary in depth map, we modify the interpolation weights according to object boundary. This method can improve the accuracy in depth maps for the synthesis of the virtual view. Evaluation using MPEG multi‐view videos shows significant enhancement of depth quality and synthesized video quality.
P‐13: Using Low Temperature Poly‐Silicon Thin Film Transistor as Oblique Light Sensors for 3D Interaction Display
Authors: Kuo Yan‐Fu , Lin Chih‐Jung , Chou Lu‐Sheng , Tai Ya‐Hsiang 
Published: October 2010

AbstractA three dimensional embedded optical sensor employs low temperature poly‐Silicon thin film transistor which used gate metal shielding by itself characteristics was proposed. This system provides sensing disparity characteristics of adopted devices under illumination. It's expected the integration of sensing system onto the panel without extra components sensors.
P‐16: A Novel Shift Register for Driving AMOLED Display
Authors: Liu Chun‐Yen , Wu Chia‐Lin , Wu Yuan‐Chun , Chang Lee‐Hsun , Lin Yu‐Hsin 
Published: October 2010

AbstractWe have fabricated 2.4in‐QVGA (240×320) AMOLED with 6T1C (six transistors one capacitor) Vth compensation circuit. In order to operate this pixel compensation circuit, a novel Vertical Shift Register (VSR) with the output of double‐pulse‐width and triple‐pulse‐width was investigated by using CMOS low temperature poly‐Si (LTPS) TFTs. This new VSR circuit was verified by simulation and measurement. The power consumption of the new VSR is about 1.8mW. The CR (contrast ratio) of 2.4in‐QVGA was improved by using the driving timing of triple‐pulse‐width.
P‐17: Amorphous ZTO/ITO Stacked‐Channel TFTs with Field Effect Mobility over 50 cm2/Vs and Resistant to Channel Thickness Dispersion
Authors: Wakana Hironori , Kawamura Tetsufumi , Fujii Kuniharu , Uchiyama Hiroyuki , Hatano Mutsuko 
Published: October 2010

AbstractWe have developed bottom‐gate amorphous‐oxide TFTs with ZTO/ITO channel layers. The fabricated ZTO/ITO‐TFTs demonstrated that threshold voltage (Vth) dispersion for TFTs with channel thickness dispersion was smaller one order of magnitude than that of conventional TFTs. Afield effect mobility of 52 cm2/Vs was obtained.
P‐19: The Innovative Solution for Image Defects in Non‐Rectangularly Shaped TFT‐LCDs
Authors: Lin Yung‐Sheng , Lin FY , Liu Vincent , Chan CM , Hung Owen , Yang Chiulien 
Published: October 2010

AbstractA round shape TFT‐LCD was made successfully that provides a new viewpoint on display that doesn't need to be rectangular. An unavoidable broader fanout area results in around mura and horizontal crosstalk which can be solved by design the route of sealant.
P‐20: An Efficient Method for Improving the Negative‐Bias‐Temperature‐Stress (NBTS) Stability of Amorphous In‐Ga‐Zn‐O TFT
Authors: Wu Chen‐Yi , Lin Chi‐Jui , Huang Chun‐Yao , Chen Hsin‐Li , Kao Yih‐Chyun , Hung Ming‐Chin , Lin Wei‐Ting , Chang Jiun‐Jye , Chen Po‐Lun , Chen Chien Hung 
Published: October 2010

AbstractAn efficient method of preparing a α‐IGZO TFT with better negative‐bias‐temperature‐stress (NBTS) stability is presented. When the α ‐IGZO TFT is used as the switch of a pixel, it suffers a long time NBTS. The NBTS of α ‐IGZO TFT would cause the Vth shift toward negative value, and thus increase the leakage current which leads to the pixel voltage drop when pixel is holding. In this work, some post‐IGZO plasma treatments methods are studied for the optimized NBTS stability process. with N2O plasma treatment being employed, the α ‐IGZO TFT shows excellent NBTS stability.
P‐22: Memory Effects of Solution‐processed Oxide Thin‐Film Transistor using ZnO Nanoparticles
Authors: Bae Jung Hyeon , Kim Gun Hee , Jeong Woong Hee , Kim Hyun Jae 
Published: October 2010

AbstractIn this study, we report the study on the non‐volatile memory effects of all solution‐processed oxide thin film transistor (TFT) with ZnO nanoparticles (NPs) as the charge trapping layer. The transfer characteristics of the device showed a large clockwise hysteresis which can be used to demonstrate its memory function, due to electron trapping in the ZnO NPs charge‐trapping layer.
P‐23: Solution‐processed Amorphous Lanthanum Indium Zinc Oxide Thin‐film Transistors
Authors: Kim Doo Na , Kim Dong Lim , Kim Gun Hee , Kim Si Joon , Kim Hyun Jae 
Published: October 2010

AbstractIn this work, we introduce a solution‐processed amorphous lanthanum indium zinc oxide (LIZO) TFT. From the characteristic variation of LIZO films according to La atomic percentage, it was confirmed that additive La atoms suppress the carrier generation by reducing oxygen vacancies. LIZO TFT was optimized at La 5% and its channel mobility, threshold voltage, s‐factor, and on‐off ratio were 2.64 cm2/Vs, 7.86 V, 0.6 V/dec, and ∼106, respectively. From these results, as substitution material of gallium in IGZO, lanthanum can be used for one of the candidates of carrier controller in IZO system.
P‐24: Self‐Aligned Metal Double‐Gate Low‐Temperature Poly‐Si TFTs on Glass Substrates
Authors: Hara Akito , Sato Tadashi , Sato Yasuyuki , Okuda Kenichi , Hirose Kenta , Kitahara Kuninori 
Published: October 2010

AbstractSelf‐aligned top and bottom metal double‐gate n‐ and p‐ch low‐temperature polycrystalline silicon thin‐film transistors (TFTs) were fabricated at 550°C on a glass substrate; nominal field‐effect mobility of the TFTs was 635 cm2/Vs and 150 cm2/Vs for n‐and p‐ch, respectively, and the s‐value of both TFTs was 130 mV/dec.
P‐25: New Polymer‐Capped a‐IGZO TFT with High Sensitivity to Visible Light for the Development of Integrated Touch Sensor Array
Authors: Zan Hsiao‐Wen , Hsueh Hsiu‐Wen , Kao Shih‐Chin , Chen Wei‐Tsung , Ku Ming‐Che , Tsai Wu‐Wei , Tsai Chuang‐Chuang , Meng Hsin‐Fei 
Published: October 2010

AbstractWe deposit a polymer layer (P3HT) on top of a‐IGZO thin‐film transistor (TFT) to absorbed visible light. Under white light, photoresponsivity of P3HT‐capped device is about 30 times of that of standard device. These results are important for the development ofin‐cell integrated touch sensor in a ‐IGZO TFT array.
P‐26: Self‐aligned Top‐gate ZnO Thin Film Transistor with Novel Al2O3/SiO2 Gate Insulator Structure
Authors: Chen Rongsheng , Zhao Shuyun , Zhou Wei , Kwok Hoi Sing 
Published: October 2010

AbstractA novel Al2O3/SiO2 gate insulator structure is developed for realizing a high performance self‐aligned top‐gate ZnO thin film transistor. After the sputtering of ZnO thin film, an Al2O3 protective layer is sputtered immediately on top of the ZnO layer in the same sputtering chamber without breaking the vacuum, which protects the surface of ZnO active layer from exposing to air or solution in the later process. with minimized charge trapping at the interface between the channel layer and the gate dielectric, the resulting transistor exhibits afield effect mobility of 27 cm2/Vs, a threshold voltage of 1.2 V, a subthreshold swing of 0.25 V/decade and an on/off current ratio of 106. Good short channel characteristics are also obtained with a small shift of the threshold voltages and no degradation of subthreshold swing.
P‐30: Single Cell Gap Wide‐View Transflective LCD using Twist Fringe‐Field Switch Mode
Authors: Huang Kun‐Tsai , Hung Yu‐Wen , Chen Kaey , Huang Liang‐Liang , Yu Chia‐Hau 
Published: October 2010

AbstractA novel single cell‐gap transflective liquid crystal display (LCD) with FFS mode has been proposed. The transmissive region is homogeneous aligned. And reflective region is partial twisted and tilted to reach single gap design. In addition, the VT and VR curve is similar by optima pixel width, space and tilt angle in R‐region.
P‐31: A New Threshold Voltage Compensation Technique of Poly‐Si TFTs for AMOLED Display Pixel Circuit
Authors: Pappas Ilias , Siskos Stylianos , Dimitriadis Charalambos 
Published: October 2010

AbstractA new threshold voltage compensation technique of polycrystalline silicon thin‐film transistors (poly‐Si TFTs) for Active Matrix Organic Light Emitting Diode (AMOLED) displays pixel circuits is presented. The new technique was applied on the conventional 2‐transistors‐1‐capacitor (2T1C) pixel circuit and a new voltage‐programmed pixel circuit (VPPC) is proposed. Theoretically, the proposed pixel is the fastest pixel with threshold voltage compensation reported in the literature since the new compression technique is implemented with a static circuit block which does not affect the response time of the conventional 2T1C pixel circuit. Furthermore, the new pixel exhibits all the other advantages of the 2T1C pixel, like the simplicity of the peripheral drivers and improves other characteristics like its behavior in the temperature variations. The verification of the proposed pixel is made through simulations with HSpice. In order to obtain realistic simulations, device parameters were extracted from fabricated LT poly‐Si TFTs.
P‐32: A New Driving Pixel Circuit to Alleviate AMOLED Degradation
Authors: Lee Kuei‐Yu , Chang Jui‐Hsin , Chao Paul C.‐P. , Chen Fang‐Chung 
Published: October 2010

AbstractThis study proposes a new driving pixel circuit in an active matrix organic light‐emitting diode (AMOLED). It is designed to decrease current density and supply the operation of negative bias stress for alleviating OLED degradation, while is capable of improving threshold voltage (Vth) shift of thin film transistors (TFTs) by current‐mode compensation circuit.
P‐34: Influences of Channel Deposition Conditions on Characteristics of Bottom‐Gate Oxide TFTs Adopting In‐Free Zinc‐Tin Oxides
Authors: Wu Cheng‐Han , Chien Chih‐Wei , Lin Shiuan‐Iou , Liao Chia‐Hsin , Kung Yen‐Cheng , Wu Chung‐Chih , Hsiao Chung‐Chin , Hung Ming‐Chin , Chen Po‐Lun , Lien Alan 
Published: October 2010

AbstractBottom‐gate Zinc‐Tin oxide (ZTO, ZnO: SnO2) thin film transistors were fabricated on glass substrates with fully photolithographic/etching processes and with completed passivation. The TFTs exhibit a field‐effect mobility of up to 12.1 cm2/V‐s and an on/off ratio of >107.
P‐35: 5‐Mask PMOS TFT Process Architecture for Large Size AMOLEDs
Authors: Choi JoonHoo , You Chungi , Choi Jonghyun , Cho Kyusik , Kwon Dohyun , Kim Hye Dong , Kim Sang Soo 
Published: October 2010

AbstractA 5‐mask TFT process architecture has been developed for AMOLED backplanes. The new process has 3 less photo mask steps compared to a normal 8‐mask LTPS process architecture. When compared to a TV display based on the conventional process, the 5‐mask process resulted in a 14‐inch AMOLED display with picture quality of nearly identical performance. for reduction of the photo mask count, an IOS capacitor structure was designed as a storage capacitor, for which no additional photo mask is needed. C‐V behavior of the IOS capacitor was similar to that of an MIM C‐V plot over the range of 1kHz to 1MHz. Both the integrated scan circuit and 6T‐1C Vth compensation circuits have been verified to work well. A low‐resistance metal bus line was also developed in order to be able to drive a 55‐inch FHD AMOLED at 240Hz. It is expected that these developments will enable cost‐competitive large sized AMOLED TV in the future
P‐37: Room Temperature Top‐Gate Self‐Aligned Amorphous InGaZnO TFTs Fabricated on Colorless Polyimide Substrate
Authors: Yeh Yung‐Hui , Cheng Chun‐Cheng , Lin Chang‐Yu , Ho Geng‐Tai , Yu Ming‐Jiue , Lai Benjamin Chih‐Ming , Leu Chyi‐Ming 
Published: October 2010

AbstractRoom temperature top‐gate self‐aligned amorphous InGaZnO TFTs were successfully fabricated on colorless polyimide plastic substrates for the first time. All these thin films were deposited by sputtering system at room temperature. The maximum field‐effect mobility is 48.5 cm2/V‐s, the subthreshold swing is 0.1 V/decade, and the threshold voltage is −1V.
P‐38: Unique Electrical Measurement Technology for Compensation, Inspection, and Process Diagnostics of AMOLED HDTV
Authors: Alexander Stefan , Chaji G. Reza , Dionne J. Marcel , Church Corbin , Hamer John , Nathan Arokia 
Published: October 2010

AbstractA unique measurement and compensation technology for AMOLED high definition television is presented. The technique electrically measures every TFT and OLED in the backplane, useful for inspection and diagnostics in the factory, and subsequent compensation of mura, TFT‐ and OLED‐degradation.
P‐41: Investigation of the Photon‐Enhanced Bias Instability of InGaZnO TFTs for the Application of Transparent AM‐OLED Displays
Authors: Ryu Min Ki , Park Sang‐Hee Ko , Yang Shin Hyuk , Byun Chun‐Won , Kwon Oh‐Sang , Park Eun‐Suk , Cho Kyoung Ik , Hwang Chi‐Sun 
Published: October 2010

AbstractWe investigated the effect of the light‐induced bias instability of indium‐gallium‐zinc oxide(IGZO) thin film transistors. The IGZO TFT exhibited the excellent subthreshold gate swing of 0.12V/decade, Vth of −0.5V, and high Ion/off ratio of >109 as well as a high field‐effect mobility of 26.7 cm2/Vs. The Vth is not changed after positive bias illumination stress (PBIS) for 10000sec. However, the Vth is −8V after negative bias illumination stress (NBIS)for 10000sec. This phenomenon can be attributed the trapping of the photon‐induced charges into the gate dielectric/active interface. We fabricated transparent AM‐OLED driven by highly stable bottom gate IGZO TFT array
P‐203L: Late‐News Poster: Analysis on AC Stress‐Induced Degradation Mechanism of Amorphous Indium‐Gallium‐Zinc‐Oxide Thin Film Transistor Inverters
Authors: Kim Sungchul , Jeon Yong Woo , Lee Sangwon , Kim Dong Myong , Kim Dae Hwan , Kim Sang Wook , Kim Sun Il , Park Jaechul , Chung U‐In , Kim Chang‐Jung 
Published: October 2010

AbstractThe degradation mechanism of a‐IGZO TFT‐based inverter is investigated under the toggled AC biased input (VIN), with a direct evidence of subgap density of states (DOS). The AC stress‐induced threshold voltage shift (ΔVT) of driver TFT is observed to be smaller than that of load TFT, which results in the VOH degradation during AC stress. The dominant mechanism of the toggled VIN stress‐induced ΔVT of driver TFT in a‐IGZO inverter is the increase of subgap DOS deep stats, whereas the ΔVT of load TFT during inverter operation is attributed to the electron trapping into the interface and/or a‐IGZO thin film.
P‐204L:Late‐News Poster: Subgap Density of States‐Based Amorphous Oxide Thin Film Transistor Simulator (DAOTS) for Process Optimization and Circuit Design
Authors: Jeon Yong Woo , Kim Sungchul , Lee Sangwon , Kim Dong Myong , Kim Dae Hwan , Kim Sun Il , Kim Sang Wook , Park Jae Chul , Chung U‐In , Kim Chang‐Jung , Lee Je‐Hun , Du Ahn Byung , Park Sei Yong , Park Jun‐Hyun , Kim Joo Han , Park Jaewoo 
Published: October 2010

AbstractAs the oxide TFT‐oriented simulator, the subgap density of states‐ based amorphous oxide TFT simulator (DAOTS) is proposed, implemented, and demonstrated for a‐InGaZnO TFTs. It consists of the parameters having their physical meanings. Moreover, concrete techniques for parameter extraction are supplied. Most preferably, the quantitative self‐consistency with experimental data is guaranteed in DAOTS.