bluuebunny/crossref_metadata_2025_split huggingface dataset:
Enhanced Activation of Standard and Cocktail Spike Annealed Junctions with Additional Sub-melt Laser Anneal
Authors: Severi Simone , Augendre Emmanuel , Pawlak Bartek , Eyben Pierre , Noda Taiji , Felch Susan , Falepin Annelies , Parihar Vijay , Schreutelkamp Robert , Vandervorst Wilfried , De Meyer Kristin 
Published: April 2011

AbstractThe advantages of fluorine co-implantation on reducing the deep P junction profile is investigated and commented as a possible valuable solution for further scaling of the NMOS transistors spacer length. On PMOS transistors, Ge+C+B cocktail junctions lead to improved short channel effects control, S/D resistance and performance over the conventional approaches. Additional laser annealing induces a partial dissolution of the doping clusters in the junction and lower the S/D transistors resistance. A performance improvement is demonstrated both for NMOS and PMOS with cocktail junctions activated by spike RTA and additional laser annealing.
Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator
Authors: Hamilton Justin J , Collart Erik JH , Colombeau Benjamin , Bersani Massimo , Giubertoni Damiano , Kah Max , Cowern Nicholas EB , Kirkby Karen J 
Published: April 2011

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.
Room Temperature Boron Diffusion in Amorphous Silicon
Authors: Jacques Jeannette M. , Jones Kevin S. , Law Mark E. , Robertson Lance S. , Rubin Leonard M. , Napolitani Enrico 
Published: April 2011

AbstractAs millisecond annealing is increasingly utilized, the as-implanted profile dominates the final dopant distribution. We characterized boron diffusion in amorphous silicon prior to post-implantation annealing. SIMS confirmed that both fluorine and germanium enhance boron motion in amorphous materials. The magnitude of boron diffusion in germanium amorphized silicon scales with increasing fluorine dose. Boron atoms are mobile at concentrations approaching 1x1019 atoms/cm^3. It appears that defects inherent to the structure of amorphous silicon can trap and immobilize boron atoms at room temperature, but that chemical reactions involving Si-F and Si-Ge eliminate potential trapping sites. Sequential Ge+, F+, and B+ implants result in 80% more boron motion than do sequential Si+, F+, and B+ implants. The mobile boron dose and trapping site concentration change as functions of the fluorine dose through power law relationships. As the fluorine dose increases, the trapping site population decreases and the mobile boron dose increases. This reduction in trap density can result in as-implanted “junction depths” that are as much as 75% deeper (taken at 1x1018 atoms/cm-3) for samples implanted with 500 eV, 1x1015 atoms/cm2 boron.
PN Junction Formation for High-Performance Insulated Gate Bipolar Transistors (IGBT); Double-Pulsed Green Laser Annealing Technique
Authors: Kudo Toshio Joshua , Wakabayashi Naoki 
Published: April 2011

AbstractIn order to form the deep PN junction demanded for the next generation IGBTs, the double-pulsed laser annealing technique as the low-thermal budget heat treatment has been introduced to activate a B-implant layer and a P-implant layer within the wafer surface to the depth 2μm. The double-pulsed laser annealing is characterized by the deep penetration depth due to a green wavelength of DPSS lasers and precisely and widely controlling of the annealing temperature and time. In the IGBT's structure the deep PN junction at a collector (the rear face) should be formed without damaging thermally circuit elements made of low melting point materials at a gate and an emitter (the front face).Ion-implant samples using eight-inch (100) Si wafers were prepared as follows: Boron (B) implant was performed at a dose of 1E+15/cm2 at an energy of 40keV and/or phosphorus (P) implant at 1E+13/cm2 at an energy of 400keV. The double-pulsed laser irradiation was carried out at the constant first and second pulse energy density E1=E2=1.8J/cm2 at the delay time td= 0-500ns and the overlap ratio OR=67-90%. The melt depth was up to about 0.3μm. The electrical activation ratio of the B-implant layer within the depth of about 0.6μm was improved from 91% to about 100% with the delay time increase of 0ns to 500ns. The activation ratio of the P-implant layer within the depth of about 2μm was drastically improved from 48% to 82% with the same delay time increase and the carriers in the P-implant layer were distributed deeply from the depth 1.1μm to 1.8μm. Furthermore, with the overlap ratio increase of 67% to 90% the carriers in the P-implant layer were distributed deeply from the depth 1.8μm to 1.9μm and the high activation ratio of 82% was maintained. The high ratio of electrical activation is supported by the defect-free epitaxial regrowth where the majority of the B dopants was diffused in the liquid phase and that of the P dopants in the solid phase.
Schottky Source/Drain Transistor on Thin SiGe on Insulator Integrated with HfO2/TaN Gate Stack
Authors: Gao Fei , Lee S.J. , Li Rui , Balakumar S. , Tung Chih-Hang , Chi Dong-Zhi , Kwong Dim-Lee 
Published: April 2011

AbstractWe report thin SGOI (Silicon Germanium on Insulator) with 65% Ge concentration p- MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) using Ni-germanosilicide Schottky S/D (source/drain) and HfO2/TaN gate stack integrated with conventional self-aligned top gate process. Unlike high temperature S/D activation needed for conventional transistor, low Ni-germanosilicide S/D formation temperature contributes to the excellent capacitance-voltage characteristic, low gate leakage current and hence, well-behaved transistor performance. In addition, SOI structure suppresses the junction leakage problem, resulting in good agreement between the source current and drain current of the MOSFET.
Visualisation of Ge Condensation in SOI
Authors: Fobelets Kristel , Vincent Benjamin , Ahmad Munir , Christofi Astolfi , McPhail David 
Published: April 2011

AbstractWe use a novel technique CABOOM – Characterisation of Alloy concentration via Beveling, Oxidation and Optical Microscopy – to visualize the change of the Ge concentration sandwiched between two SiO2 layers during the Ge condensation process. CABOOM is very sensitive to variations in the gradient of the Ge concentration in the SiGe layer and thus gives a fast and simple way to interpret the condensation process. We present a systematic study of Ge condensation in a 120nm thick Si0.92Ge0.08 layer on a 60 nm Si body SOI (silicon-on-insulator) as a function of oxidation temperature and time, using CABOOM, SIMS and XRD. CABOOM shows the non-linear variation of the Ge diffusion as a function of process time.
Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features
Authors: Ortolland Claude , Morin Pierre , Arnaud Franck , Orain Stephane , Reddy Chandra , Chaton Catherine , Stolk Peter 
Published: April 2011

AbstractIn this paper the impact of processed-induced stress and transistor layout on device performance in state-of-the-art 65nm CMOS technology has been studied. We have focused this analysis on different nitride liners above devices (Contact Etch-Stop Layers – CESL) which have been fabricated on two differently oriented (100) substrates: <110> and <100>. This overview permits to have a good understanding of CESL, and to choose the right strategy in terms of process induced stress in future microelectronic technologies.
Thermal Stability of Thin Virtual Substrates for High Performance Devices
Authors: Olsen Sarah H , Bull Steve J , Dobrosz Peter , Escobedo-Cousin Enrique , Agaiby Rimoon , O'Neill Anthony G , Coulson Howard , Claeys Cor , Loo Roger , Delhougne Romain , Caymax Matty 
Published: April 2011

AbstractDetailed investigations of strain generation and relaxation in Si films grown on thin Si0.78Ge0.22 virtual substrates using Raman spectroscopy are presented. Good virtual substrate relaxation (>90%) is achieved by incorporating C during the initial growth stage. The robustness of the strained layers to relaxation is studied following high temperature rapid thermal annealing typical of CMOS processing (800-1050 °C). The impact of strained layer thickness on thermal stability is also investigated. Strain in layers below the critical thickness did not relax following any thermal treatments. However for layers above the critical thickness the annealing temperature at which the onset of strain relaxation occurred appeared to decrease with increasing layer thickness. Strain in Si layers grown on thin and thick virtual substrates having identical Ge composition and epilayer thickness has been compared. Relaxation through the introduction of defects has been assessed through preferential defect etching in order to verify the trends observed. Raman signals have been analysed by calibrated deconvolution and curve-fitting of the spectra peaks. Raman spectroscopy has also been used to study epitaxial layer thickness and the impact of Ge out-diffusion during processing. Improved device performance and reduced self-heating effects are demonstrated in thin virtual substrate devices when fabricated using strained layers below the critical thickness. The results suggest that thin virtual substrates offer great promise for enhancing the performance of a wide range of strained Si devices.
Quantum Well Nanopillar Transistors
Authors: Hu Shu-Fen , Sung Chin-Lung 
Published: April 2011

AbstractWe have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.
Effect of Spacer Scaling on PMOS Transistors
Authors: Lau Wai Shing , Eng Chee Wee , Vigar David , Chan Lap , Siah Soh Yun 
Published: April 2011

AbstractOur observation is that both the on-current and off-current of state-of-the-art p-channel MOS transistors tend to become larger when the L-shaped spacer becomes smaller due to two different mechanisms: a decrease in the effective channel length Leff (Mechanism A) and a decrease in the series resistance (Mechanism B). In our analysis, we use drain induced barrier lowering (DIBL) as a measure of Leff and we assume that there is a linear relationship between the on-current, the logarithm of the off current and DIBL. Our assumption is supported by our theoretical derivations.
Low Temperature Silicon Dioxide Deposition and Characterization
Authors: Chatham Hood , Mogaard Martin , Okuyama Yoshi , Treichel Helmuth 
Published: April 2011

AbstractAlthough much effort has been expended toward developing alternate dielectrics for use in fabricating ULSI circuits, there is still a need for high quality SiO2 films. In particular, process temperature restrictions have increased the demand for high quality, low temperature SiO2 films.[1] Such films have multiple applications in microelectronics, including use as passivation coatings, interlevel dielectrics, gate dielectrics in metal oxide semiconductor field effect transistors (MOSFETs), thin film transistors, and in devices using dual spacers.[2] Advanced devices at the 65-nm node and beyond are typically fabricated with nickel silicided electrodes—which enable lower junction silicon consumption, lower sheet resistance, and reduced agglomeration, but require subsequent process temperatures to be below 550°C. Also, to prevent movement of the ultra shallow junctions (USJs) during a subsequent thermal cycle, the temperatures for process steps after USJ formation must be kept below 600°C. To meet these needs, we have developed a low temperature (<500°C) SiO2 process that results in excellent dielectric quality.This paper presents results on high-quality chemical vapor deposition (CVD) SiO2 films deposited at temperatures from 200°C to 450°C using a novel proprietary and versatile silicon precursor using oxygen as the oxidizer. Composition, film stress, deposition rate, leakage current density, and step coverage results are presented.
Introduction of Airgap Deeptrench Isolation in STI Module for High Speed SiGe : C BiCMOS Technology
Authors: Kunnen Eddy , Choi Li Jen , Van Huylenbroeck Stefaan , Piontec Andreas , Vleugels Frank , Dupont Tania , Devriendt Katia , Shi Xiaoping , Vanhaelemeersch Serge , Decoutere Stefaan 
Published: April 2011

AbstractThe impact of capacitive coupling effects increases with scaling down the dimensions and towards higher performances. For bipolar technologies, the introduction of deep trench isolation gives a substantial reduction in the collector substrate capacitance. In this paper a method for the formation of airgap deep trenches (with 1μm – depth 6 μm) is presented. The method is fully compatible with standard CMOS Shallow Trench Isolation (STI) and does not require additional masking steps. The approach is based on a partial removal of the poly-Si filling in the trench. Subsequently, inside D-shape oxide spacers are formed narrowing the opening of the trench down. An SF6 plasma is used to convert the nearly completely incorporated poly-Si to volatile SiF4, such that it desorbs through the opening. In the following steps the opening is sealed by depositing SiO2 resulting in the formation of an airgap (patent pending). The normal module for STI formation continues without any adaptation of the process steps. In total four standard additional process steps are needed.The absence of the common oxide/poly filling in the deep trench decreases the peripheral collector substrate capacitance with an order of magnitude to a value of 0.02fF/μm. As a consequence the low power available bandwidth is improved with 90%.
Low Temperature Selective Si and Si-Based Alloy Epitaxy For Advanced Transistor Applications
Authors: Kim Yihwan , Zojaji Ali , Ye Zhiyuan , Lam Andrew , Dalida Nicholas , Sanchez Errol , Kuppurao Satheesh 
Published: April 2011

AbstractWe have developed low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy processes for advanced transistor fabrications. By lowering epitaxy process temperature (≤ 700 °C), we have demonstrated elevated source/drain formation on ultra-thin (< 50 Å) body SOI transistors without Si agglomeration, smooth morphology of selective SiGe epitaxy with high [Ge] (>30 %) and [B] (>2E20 cm-3) concentrations, and selective Si:C epitaxy with high substitutional C concentration (>1 %). Also, we have increased growth rate of low temperature selective epitaxy processes by optimizing process parameters by adapting non-conventional deposition method.
TCAD Modeling of Strain-Engineered MOSFETs
Authors: Smith Lee 
Published: April 2011

AbstractThe rapid rise of standby power in nanoscale MOSFETs is slowing classical scaling and threatening to derail continued improvements in MOSFET performance. Strain-enhancement of carrier transport in the MOSFET channel has emerged as a particularly effective approach to enable significant performance improvements at similar off-state leakage. In this paper we describe how strain effects are modeled within the context of TCAD process and device simulation. We also use TCAD simulations to review some of the common approaches to engineer strain in MOSFETs and to explain how strain impacts device and circuit characteristics.
Modeling the Impact of Layout Variation on Process Stress in Cu/Low k Interconnects
Authors: Xu Xiaopeng , Pramanik Dipu , Rollins Greg 
Published: April 2011

AbstractThe layout dependence of process stress in Cu/low k interconnects are examined using various stress sources and layout patterns. The anisotropic grain growth stress model is compared with the conventional isotropic intrinsic stress model and the latter is found to underestimate stress concentrations in the dielectric regions near metal line ends. Both the grain growth stress in copper and the thermal mismatch stress in copper and low k dielectrics are considered in the layout dependence study. The results demonstrate that accurate stress evaluation in interconnect structures has to employ geometrical models that include layout variations. Capabilities are developed to extract these geometrical models directly from layout analysis.
Evaluation of Damages and Pore-sealing Capabilities of Oxidizing and Reducing Etch Plasmas for Single and Dual Damascene Patterning of Porous Ultra-Low-k Materials
Authors: Ollier Emmanuel , Clain Mathieu , Fox Robert , Brun Philippe , Jullian Stephane 
Published: April 2011

AbstractThis paper presents the evaluation of oxidizing and reducing plasmas for post etch pore-sealing treatments during patterning of interconnections in a porous Ultra Low-k (ULK) material. Morphological and chemical characterizations as well as electrical results (resistance, capacitance, leakage, yield) are presented for both single and dual-damascene integrations.
<B>In-Situ Characterizarion of Interfaces-Induced Resistivity in Nanometric Dimensions</B>
Authors: Marom Hagay , Eizenberg Moshe 
Published: April 2011

AbstractTo improve the speed of integrated circuits it is highly important to minimize the electrical resistivity of their interconnects. However, as the dimensions of the interconnects approach the mean free path of the electrons, a substantial rise in resistivity occurs due to additional electron scatterings from grain boundaries and interfaces. To investigate the role of interfaces, in-situ resistivity measurements were preformed for thin copper films on which different materials were deposited. The resistivity was monitored before and after the deposition, enabling to observe the changes as a new top interface was created. Among the materials tested, tantalum resulted in the highest resistivity increase. This fact is of special importance since this material and its nitride serve today as the common diffusion barrier for copper metallization. Titanium resulted in a smaller resistivity increase, but still higher than that of a free copper surface in vacuum. The developed approach enables to test the influence of different diffusion barriers on copper resistivity. With the continuously shrinking dimensions of copper interconnects, this factor will have an increasing importance in future technology nodes.
The Stepwise Cross-sectional Crystalline Analysis of the Stress Induced Voiding in Cu Interconnect
Authors: Lee Hyo-Jong , Han Heung Nam , Kang Suk Hoon , Sun Jeong-Yun , Oh Kyu Hwan 
Published: April 2011

AbstractIn a crystallographic study of stress induced voiding of copper interconnect, the planar electron backscattered diffraction analysis showed that the void was initiated at the triple junction of the grain boundaries, not at the junction of the twin boundary and grain boundary. By using stepwise cross-sectional crystalline investigation for the void, it was possible to rebuild 3D crystalline structure near the void. From the stress calculation based on the measured crystalline structures, the hydrostatic stress was highly concentrated at the triple junction of the twin boundary and grain boundary, but experimentally, there was no voiding at that. The voiding in the copper interconnect may depend mainly on the boundary instability.
Improvement of Barrier Properties of TaN Film by Plasma Enhanced Atomic Layer Deposition
Authors: Baek In Cheol , Lee Han Choon , Sim Cheonman , Han Jae Won , Kim Kee Ho , Kim Soo Hyun , Lee Sahng Kyoo 
Published: April 2011

AbstractThe barrier metal properties of Plasma Enhanced ALD (PEALD) TaN deposited on low-k dielectric film (SiCOH) with a k value of 3.0 at a deposition temperature of 300°C by using pentakis (ethylmethylamino) tantalum (PEMAT) and various plasma gases was investigated. The film resistivity of TaN is about 1000 μΩ.cm under the plasma power of 200 W and the frequency of 400 KHz, respectively. The resistivity was significantly reduced by approximately 360 μΩ.cm for the optimized condition of 300 W and 13.56 MHz. In addition, good uniformity was obtained by applying two-step plasma treatment process. The film thickness per cycl of the TaN using two-step plasma was decreased from 1.0 Å to 0.65 Å by reducing a base pressure, indicating the increase of the film density. The PEALD TaN with almost 100% coverage in this paper's dual damascene structure has a contact resistance of about 1.6 Ω /chain at via size of 0.19um.
Routes to the Formation of Air Gap Structures Using PECVD
Authors: Vrtis Raymond N. , Wu Dingjun , O'Neill Mark L , Haas Mary K. , Weigel Scott J. , Karwacki Eugene J. 
Published: April 2011

AbstractFabrication of air gap features have been achieved by three processes utilizing the diffusion of materials through a porous OSG layer. The first process involves the decomposition of a PECVD deposited organic material, either thermally or via UV anneal, to create a void with the decomposition by-products diffusing through the porous OSG layer. The second process uses the etch selectivity of XeF2 or BrF3 towards silicon versus OSG to diffuse through the porous OSG layer to etch the underlying silicon. Finally the water solubility of films such as GeO2 or B2O3, which can be easily deposited by PECVD, can be utilized for void formation via dissolution of the sacrificial inorganic layer through the porous OSG.