bluuebunny/crossref_metadata_2025_split huggingface dataset:
Influence of Cu Seed Deposition Temperature on Electroplated Cu Texture Formation in Damascene Structures
Authors: Jiang Qing-Tang , Mikkola Robert , Ortega Richard , Blaschke Volker 
Published: April 2011

AbstractThe deposition temperature of the PVD Cu seed layer has a critical impact on the subsequent electroplated Cu film. Sheet resistance transformation of electroplated Cu on 50°C seeded Cu was more than twice faster than on 150°C seeded Cu. X-ray pole figure analysis on a 3 mm × 3 mm dense array of 0.35 μm Cu damascene lines at spacing of 0.4 μm revealed significant grain orientation differences between directions parallel and perpendicular to the Cu lines. It was observed that for both seed process temperatures, the (II I) pole figures showed a sharper texture parallel to the trench direction than to the perpendicular direction. After annealing at 450°C for 30 minutes, a (511) secondary orientation emerged and the (111) texture along the trench direction became even sharper. Perpendicular to the trench, the (111) texture split into two peaks after anneal, exhibiting near fiber texture. The deviation of the two splits from normal was 2.40 tilt towards the trench wall indicating strong interaction between trench sidewall and electrodeposited Cu inside the trench. The (111) pole figure analysis also revealed a 20% contribution of Cu growth directly from the side walls. Although the pole figure pattern of 150°C seeded sample resembles that of the 50°C seeded sample, the (111) fiber texture of a 50°C seeded sample was always stronger and sharper.
Cu concentration dependence of the mechanical behaviour of Al-Cu alloys
Authors: Lokker J. P. , van Winden R. S. A. , Janssen A. M. , Radelaar S. 
Published: April 2011

AbstractThis paper reports on the influence of the copper concentration on the mechanical behaviour during thermal cycling and during isothermal holds of Al-Cu thin films on Si substrates. The Cu concentration has been varied in the range between 0 to 1 at.%Upon heating, the films with the larger amount of Cu showed a clear maximum in compressive stress. Moreover, during cooling these samples show a tensile stress increase at the onset precipitation temperature. Further cooling below 200 °C leads to the characteristic tensile stress increase often observed for Al-Cu thin films. An isothermal hold during cooling at 250 °C leads to temporary strengthening of all Al-Cu. The extent of the strengthening is dependent on the Cu concentration and is clearly dependent on the duration of the isothermal hold. Upon further cooling the strengthening disappears and the stress develops according to the original stress temperature dependence. The observations are discussed in terms of solid solution hardening and precipitation hardening.
Integration Issues for Low Dielectric Constant Materials in each Generation of ULSI's
Authors: Gomi Hideki , Kishimoto Koji , Usami Tatsuya , Koyanagi Ken-ichi , Yokoyama Takashi , Oda Noriaki , Matsubara Yoshihisa 
Published: April 2011

AbstractThe technologies utilizing Fluorinated Silicon Oxide (FSG, k=3.6) and Hydrogen Silsesquioxane (HSQ, k=3.0) have been established for 0.25-µm and 0.1 8-µm generation ULSIs. However, low-k materials for the next generation ULSIs, which have a dielectric constant of less than 3.0, have not become mature yet. In this paper, we review process integration issues in applying FSG and HSQ, and describe integration results and device performance using Fluorinated Amorphous Carbon (a-C:F, k=2.5) as one of the promising low-k materials for the next generation ULSIs.
Low Resistance Copper Via Technology
Authors: Ueno K. , Donnelly V. M. , Tsuchiya Y. , Aoki H. 
Published: April 2011

AbstractIn order to reduce specific contact resistance at via/interconnect interface and to avoid device degradation with Cu diffusion into dielectrics, via cleaning technology is a critical issue for a scaled down Cu multilevel metallization. Effects of cleaning processes are investigated for CHF3 plasma-etched SiO2/SiN/Cu via-structures. Effects of dilute HF (DHF) cleaning, hydrogen plasma cleaning, oxygen plasma cleaning, hexafluoroacetylacetone (H(hfac)) vapor cleaning, and vacuum anneal cleaning are investigated using an angle-resolved x-ray photoelectron spectroscopy (XPS). Cu contamination removal using dilute oxalic acid (DOA) is investigated using total reflection xray fluorescence analysis (TRXRF). Based on the results, we developed an optimized cleaning sequence which consists of a brief oxygen plasma exposure, DHF dipping, followed by exposure to H(hfac) vapors. The cleaning sequence is effective in obtaining a clean dielectric surface and an oxide-free Cu surface at via bottom. Direct-contacted via structures were fabricated by a dualdamascene process using the cleaning sequence. The specific contact resistance reduces to 20% of the reported values. We expect that the via resistance is low enough to be used in 0.13 µm generation and beyond.
Evaluation of Copper Penetration in Low-κ Polymer Dielectrics by Bias-Temperature Stress
Authors: Loke Alvin L. S. , Wong S. Simon , Talwalkar Niranjan A. , Wetzel Jeffrey T. , Townsend Paul H. , Tanabe Tsuneaki , Vrtis Raymond N. , Zussman Melvin P. , Kumar Devendra 
Published: April 2011

AbstractThe industry is strongly interested in integrating low–κ dielectrics with Damascene copper. Otherwise, with conventional materials, interconnects cannot continue to scale without limiting circuit performance. Integration of copper wiring with silicon dioxide (oxide) requires barrier encapsulation since copper drifts readily in oxide. An important aspect of integrating copper wiring with low-K dielectrics is the drift behavior of copper ions in these dielectrics, which will directly impact the barrier requirements and hence integration complexity.This work evaluates and compares the copper drift properties in six low-κ organic polymer dielectrics: parylene-F; benzocyclobutene; fluorinated polyimide; an aromatic hydrocarbon; and two varieties of poly(arylene ether). Copper/oxide/polymer/oxide/silicon capacitors are subjected to bias-temperature stress to accelerate penetration of copper from the gate electrode into the polymer. The oxide-sandwiched dielectric stack is used to overcome interface instabilities occurring when a low-κ dielectric is in direct contact with either the gate metal or silicon substrate. The copper drift rates in the various polymers are estimated by electrical techniques, including capacitance- voltage, current-voltage, and current-time measurements. Results correlate well with timeto- breakdown obtained by stressing the capacitor dielectrics. Our study shows that copper ions drift readily into fluorinated polyimide and poly(arylene ether), more slowly into parylene-F, and even more slowly into benzocyclobutene. A qualitative comparison of the chemical structures of the polymers suggests that copper drift in these polymers may possibly be retarded by increased crosslinking and enhanced by polarity in the polymer.
Reduction of The Phase Transition Temperature of TiSi2 on Si(111) Using a Ta Interlayer
Authors: Jung Bokhee , Kim Young Do , Yang Woochul , Nemanich R. J. , Jeon Hyeongtag 
Published: April 2011

AbstractThe effect of a thin Ta interlayer on the C49 to C54 phase transition of TiSi2 on Si(111) was examined. The Ta interlayered samples were prepared by depositing Ta and Ti films sequentially on Si(111) substrates in a UHV system. As control samples, 100Å Ti films were deposited directly on clean Si(111) substrates. The deposited substrates were annealed for 10 min, in-situ, at temperatures between 500°C and 750°C using 50°C increments. The TiSi2, which formed in this UHV process, was analyzed with XRD, AES, SEM, TEM, and four-point probe measurements. The control samples exhibited the C49 to C54 transition at a temperature of 750°C. However, the TiSi2 samples with 5Å and 10Å Ta interlayers displayed a significant reduction of the phase transition temperature. The XRD analysis indicated that the C49 to C54 transition temperature of TiSi2 was lowered by ∼200°C. The sheet resistance measurement showed a low resistivity characteristic of C54. The SEM and TEM micrographs showed that the Ta interlayer also suppressed the surface agglomeration of the C54 TiSi2 film. The AES analysis data indicated that the composition of the titanium silicide showed the expected Ti:Si stoichiometry of 1:2.
Comparative Study on Lateral Silicide Growth in Self-Aligned Ti and Co Silicidation: Interaction and Reactivity with SiO2 and Si3N4
Authors: Park Ji-Soo , Sohn Dong Kyun , Bae Jong-Uk , Huh Yun-Jun , Park Jin Won 
Published: April 2011

AbstractThe interaction and reactivity of Ti and Co with SiO2 and Si3N4 have been investigated. In the case of Ti salicide, SiO2 sidewall spacer showed no lateral silicide overgrowth and low leakage current between gate and source/drain up to silicidation temperature of 750 1C. However, Si3N4 sidewall spacer showed dopant dependence of the lateral silicide growth and leakage current. This discrepancy between SiO2 and Si3N4 and dopant dependence is closely related to the reactivity. For Co, lateral silicide overgrowth is greatly reduced. Instead, Co films on SiO2 and Si3N4 layer were agglomerated by annealing. An annealing at 1050°C caused not only agglomeration of Co film but penetration of Co agglomerates through the layers. Interestingly, the CoSi2 spike of B type epitaxial and twinned orientation was formed in the Si substrate by the penetrated Co source.
Characterization of Thin Dielectric Films as Copper Diffusion Barriers Using Triangular Voltage Sweep
Authors: Cohen S. A. , Liu J. , Gignac L. , Ivers T. , Armbrust D. , Rodbell K. P. , Gates S. M. 
Published: April 2011

AbstractAs technology progresses, the need for thinner Cu diffusion barrier caps is becoming more important, and it is advantageous if these barriers have low dielectric constants (κ). Towards this end, we characterized Cu penetration in several thin (35 nm to 70 nm) dielectrics, including silicon nitrides, silicon oxynitrides, an amorphous hydrogenated carbon film, and a methyl silsesquioxane layer. Metal Insulator Silicon (MIS) structures were used as the test vehicle. The barrier dielectrics were deposited on 100 nm thermal oxide which was grown on 2 Ω-cm, n-type Si wafers. After the deposition of 50 nm TEOS capping layers, both Al and Cu dots were evaporated on each wafer through a mask. Both Al and Cu dot samples were stressed at +2.7 MV/cm at 300°C for 10 minutes. For Cu dots, the applied stress pushed Cu ions into the dielectric stack. Stressing Al dots characterized the effects of the stress on the dielectric stacks and the quantity of Na ions in the films. Since C-V shifts are subject to stress-related instabilities in the interfaces as well as within the dielectrics themselves, triangular voltage sweep (TVS) was used after the applied stress to measure the concentration of Cu which reached the underlying thermal oxide film. The sensitivity of the TVS test with the structures used is about 5×109/cm2. Secondary ion mass spectroscopy (SIMS) analyses were performed on some of these samples to verify the electrical results.
A Pretreatment Technique to Improvement the Ashing Resistance of Low K Spin-On-Polymer (SOP)
Authors: Chang Kow-Ming , Yang Ji-Yi , Chang Yu-Hsun 
Published: April 2011

AbstractThe oxygen plasma via resists strip process cause significant damage to organic SOP, thus limiting its inter-level dielectric application. A simple treatment technology using reactive ion is proposed to reform the SOP surface. The reactive ion modification of the SOP can improve the resistance towards oxygen plasma. This is owing to the carbon atom absence in the SOP's surface area. The measurements of Fourier transform infrared (FTIR) spectroscopy, x-ray photoelectron spectroscopy (XPS), stress, thickness variation, Scanning Electron Microscope (SEM) cross-sectional view for gap filling and dielectric constant show that SOP with reactive ion treatment (RIT) has better quality for non-etch-back process than SOP without RIT.
Structire, Properties, and Process Characteristics of Low-K Materials Prepared by PECVD
Authors: Shimogaki Y. , Lim S. W. , Loh E. G. , Nakano Y. , Tada K. , Komiyama H. 
Published: April 2011

AbstractLow dielectric constant F-doped silicon oxide films (SiO:F) can be prepared by adding fluorine source, like as CF4 to the conventional PECVD processes. We could obtain SiO:F films with dielectric constant as low as 2.6 from the reaction mixture of SiH4/N2 O/CF4. The structural changes of the oxides were sensitively detected by Raman spectroscopy. The three-fold ring and network structure of the silicon oxides were selectively decreased by adding fluorine into the film. These structural changes contribute to the decrease ionic polarization of the film, but it was not the major factor for the low dielectric constant. The addition of fluorine was very effective to eliminate the Si-OH in the film and the disappearance of the Si-OH was the key factor to obtain low dielectric constant. A kinetic analysis of the process was also performed to investigate the reaction mechanism. We focused on the effect of gas flow rate, i.e. the residence time of the precursors in the reactor, on growth rate and step coverage of SiO:F films. It revealed that there exists two species to form SiO:F films. One is the reactive species which contributes to increase the growth rate and the other one is the less reactive species which contributes to have uniform step coverage. The same approach was made on the PECVD process to produce low-k C:F films from C2F4, and we found ionic species is the main precursor to form C:F films.
Porous Organosilicates for On-Chip Dielectric Applications
Authors: Miller R. D. , Beyers R. , Carter K. R. , Cook R. F. , Harbison M. , Hawker C. J. , Hedrick J. L. , Lee V. , Liniger E. , Nguyen C. , Remenar J. , Sherwood M. , Trollsås M. , Volksen W. , Yoon D. Y. 
Published: April 2011

AbstractPorous organosilicates useful for on-chip insulator applications can be prepared by templating the vitrification of low molecular weight silsesquioxanes (SSQs) using highly branched, thermally labile macromolecules which are subsequently removed in a thermal process to generate porosity. The process involves spin coating a mixture of the matrix material and the porogen (pore generator) followed by thermal curing to initiate vitrification and decomposition of the porogen. The morphology is fixed during the formation of the nanoscopic inorganicorganic hybrid and is maintained during foaming. This process generates controllable and stable morphologies where the void volume is determined by the porogen loading level. The porous materials are thermally robust and intrinsically hydrophobic without subsequent chemical treatment. Dielectric constants of < 2.2 are easily achieved for pore volumes of only 20%, and this porosity appears to be predominately closed cell in nature. These materials display a number of thermal mechanical and electric properties consistent with the requirements for on-chip insulator applications.
Porous Silicon Oxynitride Films Derived from Polysilazane as a Novel Low-Dielectric Constant Material
Authors: Aoki T. , Shimizu Y , Kikkawa T. 
Published: April 2011

AbstractA novel spin on material derived from perhydropolysilazane that converts into ultra-low k inorganic films is described in this paper. The obtained films, cured at 400°C in N2 atmosphere, exhibit dielectric constants as low as 1.6 which do not change after holding the wafers in a clean-room mbient for 2 months. Cross-sectional SEM images of the cured films show the aggregation of small granules with diameters ranging from 5 to 30 nm. The films can be obtained by conventional SOG process: spin-coating, baking and curing, without any additional process such as hydrophobic treatment.The average atomic compositions of the films are, Si/O/N/C = 40/55/5/0.5 (atomic %), by XPS analysis. These results indicate that the films have hydrogen silicon oxynitride structures. No evolution of H2O and NH3 was detected by TDS analysis in the temperature range of RT to 800°C. Hydrophobic Si-H and Si-H2 groups remaining in the film might prevent water absorption, resulting in the low dielectric constant.The remainder of Si-H and Si-H2 constituents in the cured films is the result of selective oxidation reactions of perhydropolysilazane in the baking process with the use of a specific catalyst. The structures of the films are tailored by altering the amount of the catalyst. In this study, we also demonstrate the relationship between the effect of the catalyst and the film properties.
Structure-Property Correlation in Low K Dielectric Materials
Authors: Morgen Michael , Zhao Jie-Hua , Hay Michael , Cho Taiheui , Ho Paul S. 
Published: April 2011

AbstractIn recent years there have been widespread efforts to identify low dielectric constant materials that can satisfy a number of diverse performance requirements necessary for successful integration into IC devices. This has led to extensive efforts to develop low k materials and the associated process integration. A particularly difficult challenge for material development has been to find the combination of low dielectric constant and good thermal and mechanical stability. In this paper recent characterization results for low k materials performed at the University of Texas will be reviewed, with an emphasis on the relationship of chemical structure to the aforementioned key material properties. For example, measurements showing the effect of film porosity on dielectric constant and thermal and mechanical properties is presented. This data, as well as that for other material types, demonstrates the tradeoffs between dielectric constant and thermomechanical properties that are often made during the course of material development.
Thermal conductivity study of porous low K dielectric materials
Authors: Hu Chuan , Morgen Michael , Ho Paul S. , Jain Anurag , Gill William. N. , Plawsky Joel L. , Wayner Peter C. 
Published: April 2011

AbstractA quantitative characterization of the thermal properties is required to assess the thermal performance of low dielectric constant materials. Recently we have developed a technique based on the 3-omega method for measuring the thermal conductivity of porous dielectric thin films. In this paper we present the results on the measurements of thermal conductivity of thin porous films using this method. A finite element method analysis is used to evaluate the approximations used in the measurement. Two porosity-weighted thermal resistor models are proposed to interpret the results. By studying the dependence of the thermal conductivity on porosity, we are able to discuss the scaling rule of thermal conductivity. Additionally, a steady state layered heater model is used for evaluating the significance of introducing porous ILDs into an interconnect structure.
ELectrical Characterization of Beryllium Doped Low Temperature MBE Grown GaAs
Authors: Cich M. J. , Zhao R. , Park Y. , Specht P. , Weber E. R. 
Published: April 2011

ABSTRACTThe electrical properties of low temperature MBE grown GaAs (LT-GaAs) in the n-i-n configuration have been studied. The mechanism of current rise in beryllium doped LT-GaAs is found to fit Frenkel-Poole type emission with a barrier height of 0.26 eV. However, this model does not fit undoped LT-GaAs. The breakdown field is considerably higher (up to 5.2* 105 V/cm) for beryllium doped films than undoped films, and depends on both growth temperature and beryllium concentration. Beryllium doping is also found to increase the resistivity of the preannealed films to values > 109 ω-cm.
Temperature Dependent Photoluminescence Study of High Silicon doped AIGaAs and the Correlation between the Photoluminescence Spectra and the Doping Level
Authors: Koley G. , Liu W. , Prasad K. , Lin M. 
Published: April 2011

ABSTRACTWe report on the room temperature and the low temperature ( 77 K ) study of highly Si doped MBE grown bulk Al.2Ga.8As layers by Photoluminescence ( PL ), Hall, X-Ray and Electrochemical Voltage Profiler ( ECV ) technique. The room temperature PL spectra shows the presence of an asymmetric broad peak in the low energy side whose Full Width at Half Maxima (FWHM) and intensity increases with the doping level. The broad peak has been found to be a combination of two individual peaks, one arising out of the DX center related recombinations and the other due to some Silicon related complex acceptor sites. The low temperature PL also shows a ‘strange peak’ near the Al2Gas8As band edge luminescence peak for wafers grown at 600°C. This peak which increases in intensity at a very rapid rate with falling temperature and shift very rapidly with temperature can be attributed to some AIGaAs growth defect related recombination center, depending on the growth temperature.
In Situ Observation of scaling Behavior During Solution-Phase Growth of Surfactant Monolayers
Authors: Schwartz Daniel K. , Doudevski Ivo 
Published: April 2011

ABSTRACT“Self-assembled” monolayers of amphiphilic surfactant molecules form spontaneously on solid surfaces by exposure to dilute solutions of the adsorbate molecules. These monolayers are shown to form via a mechanism that includes nucleation, growth, coalescence, etc. of densely- packed submonolayer islands of the long-chain organic molecules. In situ atomic force microscopy experiments allow a quantitative analysis of island nucleation and growth rates as well as determination of the island size distribution as a function of coverage. In the growth regime, the nucleation and growth rates have a power law behavior consistent with a simple point island model of 2D cluster growth. The exponents are consistent with a critical nucleus of two molecules and the 2D diffusion coefficient corresponds to a “hopping time” of about 1 microsecond. In the aggregation regime, the island size distributions are shown to scale with a single evolving length scale in accordance with the dynamical scaling approximation.
Preparation and Optical Properties of Ge and C-Induced Ge Quantum Dots on Si
Authors: Eberl K. , Schmidt O. G. , Kienzle O. , Ernst F. 
Published: April 2011

ABSTRACTPure Ge epitaxially grown on Si (100) at high temperatures forms typically 100 nm lateral size islands on top of a 3–4 monolayer thick wetting layer. In stacked layers of Ge dots pronounced vertical alignment is observed if the thickness of the Si spacer layers is smaller than about 50 nm. Pregrowth of a small amount of C on Si substrate induces very small 10 nm size Ge quantum dots after deposition of about 2 to 3 monolayers Ge. Photoluminescence (PL) studies indicate a spatially indirect radiative recombination mechanism with the no-phonon line strongly dominating. Strong confinement shift in the 1–2 nm high and 1Onm lateral size dots results in low activation energies of 30 meV, which causes luminescence quenching above 50K.For large stacked Ge islands with 13 nm thin Si spacer layers we observe a significantly enhanced Ge dot-related PL signal up to room temperature at 1.55μm wave length. This is attributed to a spatially indirect transition between heavy holes confined within the compressively strained Ge dots and two-fold degenerated Δ state electrons in the tensile strained Si between the Ge stacked dots.
Computer Simulations of Two-Dimensional Sn-Cu Alloys on (100) and (111) Cu Surfaces
Authors: Aguilar Jose F. , Ravelo R. , Baskes M. 
Published: April 2011

ABSTRACTWe have performed calculations of Sn deposition on Cu(111) and Cu(100) surfaces. The atomic interactions are described by modified embedded atom method (MEAM) potentials. This is a modification of the embedded atom method (EAM) to include higher moments in the electron density. We find the at low coverages Sn deposited on Cu(111) leads to the formation of a two-dimensional (2D) alloy phase with a p (√3 × √3)-R 30° structure which is stable up to temperatures of 900K. These results are in agreement with ion-scattering experiments of thin films of Sn on Cu(111). For deposition of Sn on Cu(100), a 0.25 monolayer (ML) coverage results in the formation of a stable 2D alloy phase with a p(2 × 2) structure. This result is also in agreement with LEED measurements.