bluuebunny/crossref_metadata_2025_split huggingface dataset:
Oxidation Resistant Dilute Copper (Boron) Alloy Films Prepared by DC-Magnetron Cosputtering
Authors: Hymes S. , Kumar K. S. , Murarka S. P. , Wang W. , Lanford W. A. 
Published: April 2011

AbstractTo enhance the corrosion resistance and reliability of the proposed copper interconnections in silicon integrated circuits, alloying with small amounts thermodynamically favorable elements has been pursued. In the present investigation dilute copper (boron) alloy thin films (in boron concentration range of 0–4 at % in copper) were deposited by DC magnetron co-sputtering using a high purity copper and Cu-4 at. % B targets. Films were then annealed in Ar-3% H2, pure Ar, vacuum, and air ambients in the temperature range of 200–500°C. Sheet resistance, Rutherford backscattering, x-ray diffraction measurements were made to characterize the films. The residual resistivity of the as-deposited alloy films was found to be 5.3 μΩ-cm/at %. To obtain sufficiently low working resistivity, an alloy content below 0.5 at % is suggested for application as a potential metallization material. The addition of boron, which is the common dopant in Si. to the copper films offers considerable oxidation protection. The resulting oxidation rates are considerably lower than that for pure copper films. All this will be presented and discussed.
The Improvement of Immunity to Electromigration by Means of Microstructural Design
Authors: Kononenko O. V. , Matveev V. N. 
Published: April 2011

AbstractIt is known from literature that the properties of thin films greatly depend on their structuare. Therefore, the microstructural design is attractive for control over the properties of thin metal films used for interconnect metallization.In this paper we discuss the potentialities of the self-ion assisted deposition technique for control over the grain and grain boundary structures of thin metal films and their properties such as resistivity and immunity to electromigration.It was found that resistivity of aluminum films deposited at the 6 kV bias was virtually equal to resistivity of bulk aluminum. Films deposited at the less bias or without it had higher resistivities. Abnormal grain growth was found in 6 kV-films. In films prepared without bias normal grain growth proceeds.
Analysis of Geometrical and Microstructural Effects on Void Formation in Metallization: Observation and Modelling
Authors: Shih W. C. , Ghiti A. , Low K. S. , Greer A. L. , O'Neill A. G. , Walker J. F. 
Published: April 2011

AbstractThis paper reports the analysis of geometrical and microstructural effects on void formation in interconnects. Ion-beam machining is used to define segments for study at the cathode end of test lines. Scanning electron microscopy is used to observe damage development, focused ion beam microscopy to observe the corresponding grain structure. Finite-element calculations of self-consistent current density and temperature distributions in the conductor are used to predict damage locations both for a continuum material and for simulated grain structures. Cross-section changes in the line give temperature variations leading to divergences in atomic flux. Regions of
high flux divergence are favoured for electromigration damage, but the precise sites of damage are determined by the grain structure, as shown both in the experiment and in the modelling.
In-Situ UHV Electromigration in CU Films
Authors: Vook R. W. , Jo B. H. 
Published: April 2011

AbstractCopper stripes, current stressed under UHV, clean surface conditions, have an activation energy Q for electromigration (EM) of 0.5 eV, significantly lower than the 0.8 eV reported when the surface has been exposed to air. Application of positive or negative potentials to the stripes during EM testing raises or lowers the clean surface Q in a linear relationship in the range of 0.2 to 1. 0 eV. These results were obtained from in-situ electrical resistance measurements during which potentials up to +/− 800 volts were applied to the stripe. Thus the rate at which surface EM takes place is influenced by the sign and magnitude of the applied potential. The low Q for the in-situ clean surface studies also implies that surface diffusion is the dominant physical mechanism whereby EM damage occurs. Ex-situ SEM studies support this conclusion. This work has important implications for ULSI since numerous recent studies have indicated that surface and/or interface diffusion are present during current stressing of passivated and unpassivated fine line stripes.
Limitations of Plasma Charging Damage Measurements Using MOS Capacitor Structures
Authors: Shawming M A , Abdel-Ati Wael L. N. , Mcvittie James P. 
Published: April 2011

AbstractThis paper investigates the sensitivity and limitation of capacitor testing for measuring potential charging damage to gate oxides in a given plasma step. While C-V measurements are the most directly related to transistor threshold voltage (Vth) and transconductance (gm), C-V measurements are slow, difficult to automate and not usable for large antenna structures without a fuse link. In contrast, ramp breakdown measurements are quick and easy to automate but lack sensitivity. Charge-to-breakdown offers better sensitivity but with long measurement times. A more promising method is the V-t measurement where the slope dV/dt after initial charging is a measure of the trapping generation rate and is found to be very sensitive to charge damage. The damage sensitivity of this method is high and involves tradeoffs between antenna ratio, testing current and testing time. All of which are critical to damage testing. Leakage measurements are another method which offers short measurement times and high sensitivity. Their limitations are the noise level of the measurement system and the making of good probe contact to the gate material.
Tunneling Current Through MIS Structures With Ultra-Thin Insulators
Authors: Fujioka H. , Wann H.-J. , Park D.-G. , King Y.-C. , Chyan Y.-F. , Oshima M. , Hu C. 
Published: April 2011

AbstractLeakage currents through MIS (Metal Insulator Semiconductor) structures with several ultra-thin (14–30Å) insulators (silicon dioxide, silicon oxynitride, and silicon nitride) have been investigated. The leakage currents through both dioxide and oxynitride films sandwiched between n-type poly-Si gates and n-type substrates can be well fitted by the equation for the electron direct tunneling mechanism using the same effective mass and barrier height. This result indicates that incorporation of a minute amount of nitrogen atoms does not seriously affect the basic electrical properties of the oxide films. Leakage currents through ultra-thin nitride can te also fitted with the equation for the direct tunneling mechanism without assuming any extra conduction mechanisms such as hopping through defects.
Electromigration and Diffusion in Pure Cu And Cu(Sn) Alloys
Authors: Hu C.-K. , Lee K. L. , Gupta D. , Blauner P. , Watson T. J. 
Published: April 2011

AbstractAtom movements of Cu in pure Cu and Cu(0.5 to 2 wt.% Sn) alloys have been investigated using drift velocity and radioactive tracer techniques. The void growth rate in pure Cu at the cathode end, as a result of electromigration driving force, linearly increases with the applied current density. A marked decrease in the Cu grain boundary diffusivity and electromigration drift velocity is attributed to Sn trapping of Cu atoms and/or binding defects at grain boundaries. The effect is more pronounced at lower temperatures. The activation energies for electromigration and diffusion of Cu in pure Cu grain boundaries were found to be in the range of 0.7 – 0.9 eV. Addition of about 0.5 to 2 wt.% Sn increased these energies to 1.1 – 1.3 eV, respectively which resulted in enhancement of electromigration resistance by several orders of magnitude over that in pure Cu at the field operation temperature.
Non-Contact Mapping of Fe Contamination in Oxidized Si Wafers with Sensitivity in Part-Per-Trillion Range
Authors: Lagowski Jacek , Edelman Piotr 
Published: April 2011

AbstractTraces of iron contamination as minute as one part per trillion atom fraction can be detrimental to the gate oxide integrity of the very thin oxides, 10 nm or less, used in the most advanced ICs. Fe contamination monitoring discussed in this paper is done with the surface photovoltage (SPV) technique which measures the minority carrier diffusion length, L, before and after the recombination efficiency of iron is enhanced by optical splitting of the iron-boron
pairs. Wafer-scale mapping of iron gives fingerprints of contaminating tools and processes. In this paper, we also present an extension of SPV to oxidized wafers. In the past, such measurements were rendered impossible due to optical interference in the SiO2.The apparatus incorporates a whole wafer, optical Fe activation station and it provides whole wafer maps of Fe in a total time of 6 to 20 minutes per wafer, depending on probing density.
The Mechanics of A Free-Standing Straitned Film/Compliant Substrate System
Authors: Freund L. B. 
Published: April 2011

AbstractThe deformation of film/substrate systems due to a through-the-thickness distribution of mismatch strain is discussed for cases when the layers are thin, compliant and freestanding. The connection between substrate curvature and mismatch strain is reviewed within the framework of small strains and small deflections. These results are applied to determine the second-order correction to the Stoney formula and to note the connection between mismatch strain distribution and curvature history. Then, for small strains but large deflections, it is observed that a symmetric system with equi-biaxial mismatch strain can undergo a bifurcation in deformation mode. It is also shown that the bifurcation response is sensitive to system imperfections. Finally, the critical condition for introduction of an interface misfit dislocation in an epitaxial system is established, thereby extending the Matthews-Blakeslee criterion to the case of free-standing compliant systems.
Relationship Between The Void And Hillock Formation And The Grain Growth In Thin Aluminum Films
Authors: Kononenko O. V. , Matveev V. N. 
Published: April 2011

AbstractVoid and hillock formation during annealing was studied depending on the deposition conditions. Aluminum films were deposited onto oxidized silicon substrates by the self-ion assisted technique. The bias 0 or 6 kV was applied to the substrate during deposition. The films were then annealed in vacuum for 1 hour in the temperature range from 1500 to 550°C. The structure of the films was investigated by transmission electron microscopy.It was found that recrystallization and void and hillock formation in the films depend on the bias during deposition. Normal grain growth occurred in the films deposited without bias. Abnormal grain growth was observed in the 6 kV-films. It was also found that the mechanism of stress relaxation during thermal cycling depends on the self-ion bombardment. In the films prepared without bias, stress relaxation proceeds by diffusion creep. In the films deposited at the 6 kV bias, stress relaxation proceeds by plastic deformation.
Processing-Induced Stresses And Curvature In Patterned Lines On Silicon Wafers
Authors: Shen Y-L. , Suresh S. , Blech I. A. 
Published: April 2011

AbstractThe evolution of stresses due to the patterning and thermal loading of thin lines on Si wafers, and the consequent changes in the overall curvature of the wafer are studied theoretically and experimentally. The analysis involves finite element simulations within the context of generalized plane strain models. The analysis is capable of predicting the wafer curvature in directions parallel and perpendicular to the lines. These predictions compare reasonably well with experimental measurements of curvature made on model systems. The thickness, width and spacing of the patterned lines have been varied systematically, and the associated changes in the evolution of stresses and curvature have been determined. The non-uniform stress field within the fine lines is also analyzed.
Submicron Resolution X-Ray Strain Measurements On Patterned Films: Some Hows And Whys
Authors: Marcus M. A. , Macdowell A. A. , Isaacs E. D. , Evans-Lutterodt K. , Ice G. E. 
Published: April 2011

AbstractAs interconnect technology moves deeper into the submicron realm, the physics governing the mechanical behavior, hence the reliability of metal lines changes. Events at the level of individual grains become more important. One would like to be able to measure the strain and orientation of single grains, and the distribution of strain across a grain. Such data may help us understand such effects as sunken grains, the erratic occurrence of stress voiding and Blechlength effects in electromigration. To get this information, techniques involving X-ray diffraction with submicron beams are being developed. These experiments involve detecting Laue spots from selected areas and energy-analyzing them to find the strain tensor. Motivations for such measurements, the specifications for a useful instrument, some designs now being developed and the intrinsic limitations of these approaches will be discussed. Design issues in the choice of focussing optics and energy measurement will be highlighted with calculations of how the Laue spots would look for different conditions of crystal perfection.
General Kinetic Rules for Rapid Thermal Processing
Authors: Ditchfield R. , Seebauer E. G. 
Published: April 2011

AbstractUp to now, kinetic effects in rapid thermal processing (RTP) have been assessed qualitatively and rather vaguely through the concept of thermal budget. We discuss the shortcomings associated with thermal budget and present an alternate conceptual framework that explicitly treats selectivity between desired and undesired physical phenomena. This framework is quite simple and is intended for rapidly assessing the qualitative effects of various heating programs. From a purely kinetic perspective, selecting the best program involves only comparing the activation energies for the desired and undesired rate phenomena. We cite examples where application of the thermal budget approach gives incorrect guidance for minimizing the undesired process. Such deficiencies are rectified by the framework presented here.
Modeling of Device Characteristics as Function of Ti Salicide Rapid Thermal Processing Parameters for Deep-Sub-Micron CMOS Technologies
Authors: Kittl J. A. , Prinslow D. A. , Misium G. , Pas M. F. 
Published: April 2011

AbstractRapid thermal processing is widely applied in self-aligned Ti silicide processes for deep-submicron devices. We investigated and modeled the effects of rapid thermal processing variables (silicide formation temperature and time, and anneal temperature and time) and Ti thickness on deep-sub-micron device characteristics. The effect of Ti thickness, formation temperature and time on diode leakage and bridging due to silicide lateral growth, and its correlation to silicide thickness was analyzed; as well as the effects of these and the anneal variables on n+ gate sheet resistance, silicide to source/drain contact resistance and transistor source-drain series resistance. An expression for n+ gate sheet resistance is given, as function of anneal temperature and time, silicide thickness, linewidth and TiSi2 C49 grain size after formation, based on a nucleation density model in agreement with measurements of TiSi2 C49 to C54 transformation kinetics. The tradeoffs and process window limits are discussed, as well as trends observed when scaling down lateral and vertical dimensions. We show that for advanced technologies, the scaling of silicide thickness and linewidth narrows the process window between full C49 to C54 transformation and agglomeration temperatures. Due to the high activation energy of the C49 to C54 transformation, a process window for low sheet resistance exists only for high temperature-short time processes.
Correlation Between the Standard Deviation of Sheet Resistance and the Temperature of Rapid Thermal Annealing
Authors: Lin X. W. , Pramanik D. 
Published: April 2011

AbstractRapid thermal annealing (RTA) induced reactions between Ti thin films and Si wafers were characterized by sheet resistance measurements. It was found that the standard deviation a of the measurements is RTA-temperature dependent, and strongly correlates with the mean sheet resistance R. A specific temperature was identified, corresponding to a sharp σ peak in the temperature regime associated with the C49-C54 TiSi2 phase transition. This temperature is characteristic of materials parameters such as Ti thickness and substrate doping species, and can be used to accurately monitor or compare the calibration of RTA systems.
In Situ Rapid Thermal Hydrogenation Pretreatment of Ti for Salicide RTA
Authors: Ando K. , Ishigami T. , Matsubara Y. , Horiuchi T. , Nishimoto S. 
Published: April 2011

AbstractAn in situ rapid thermal hydrogenation (RTH) pretreatment of titanium prior to rapid thermal annealing (RTA), or RTH/RTA, is proposed as a silicide formation annealing in a CMOS self-aligned silicide (salicide) process. The in situ RTH is found to enhance silicidation, to reduce nitridation, and even to lower the resultant sheet resistance of titanium silicide.During in situ RTH (e.g., at 550°C), amorphous Ti silicide (e.g., 15-nm thick) grows selectively on Si. Furthermore, Ti nitridation during subsequent RTA (690°C, N2, 10 Torr, 30 s) is reduced depending on RTH (H2, 10 Torr, 30 s) temperature. Accordingly, for 550°C RTH and an initial Ti thickness of 15 nm, the sheet resistance obtained at the 0.27-μm-wide n+ poly-Si gate after a phase transition annealing (800°C, Ar, 10 s) was lower (11.7 Ω /□, st. dev. = 6%) than that of conventional Ti silicide (15.8 Ω/□, st. dev. = 10%). The silicidation enhancement and nitridation reduction are related to crystal structure metamorphosis or to hydrogen interstitial incorporation in the Ti layer during RTH as observed by x-ray diffraction analysis. It is concluded that in situ RTH pretreatment before RTA is very promising as a sub-quarter-micron CMOS salicide process.
UV Photoannealing and RTP of Thin Sol-Gel Films
Authors: Leest R. E.Van de , Roozeboom F. 
Published: April 2011

AbstractVarious annealing methods for sol-gel films have been investigated. Thermal, photothermal, RTP and excimer laser annealing have been used to convert sol-gel precursor films into oxidic films. RTP annealing of sol-gel films yields better results than classical thermal annealing or excimer laser irradiation. Photochemical effects during RTP annealing contribute to obtain high-quality oxide films. The various annealing methods are illustrated by the annealing of alkoxide precursor films of tantalum, iron, nickel and yttrium.
Nitrided Gate Dielectrics and Charge-to-Breakdown Test
Authors: Dimitrijev S. , Tanner P. , Harrison H. B. , Sweatman D. 
Published: April 2011

AbstractIn this paper, the applicability of the charge-to-breakdown test for characterisation and comparison of differently grown ultra-thin gate dielectric films is considered. It is shown that the charge-to-breakdown parameter cannot be reliably used, because it is related to the electrons tunneling through the film, and not to the mechanism of positive charge accumulation which leads to time-dependent breakdown. It is found that the constant-voltage stress provides a consistent set of stress field vs time-to-breakdown data. Nitrided gate dielectrics show improved breakdown characteristics, compared to standard silicon-dioxide films.
Characterisation of Dielectric Damage in MOS Capacitors by a New Current Transient Measurement Technique
Authors: Tanner P. G. , Dimitrijev Sima , Yeow Y-T. , Harrison H. B. 
Published: April 2011

AbstractWith the requirement for reduced dielectric thickness and improved durability in silicon MOS devices, new growth techniques and material composition are constantly being developed. An important part of this development is the electrical characterisation of the dielectric material and in particular the properties of the dielectric-semiconductor interface.This paper presents a study of damage caused to the dielectrics of MOS capacitors which have been subjected to either constant current stressing or RF plasma etching. The density and energy position of fast interface states and fixed oxide charges were measured using standard capacitance-voltage techniques. These results are then compared with a new current transient technique, which has been developed to measure slow interface states having a range of response times. This new technique steps the surface Fermi level through the silicon bandgap and the resulting current transients provide information on trap response times at each energy position. The response time can then be related to the tunneling distance from the trap to the bulk silicon. This technique has provided important information about the energies and response times of traps generated in damaged dielectrics, and should prove to be a useful tool for damage evaluation in the future.
Temperature Monitoring by Ripple Pyrometry in Rapid Thermal Processing
Authors: Nguyenphu Binh , Oh Minseok , Fiory Anthony T. 
Published: April 2011

AbstractCurrent trends of silicon integrated circuit manufacturing demand better temperature control in various thermal processing steps. Rapid thermal processing (RTP) has become a key technique because its single wafer process can accommodate the reduced thermal budget requirements arising from shrinking the dimensions of devices and the trend to larger wafers. However, temperature control by conventional infrared pyrometry, which is highly dependent on wafer back side conditions, is insufficiently accurate for upcoming technologies. Lucent Technologies Inc., formerly known as AT&T Microelectronics and AT&T Bell Laboratories, has developed a powerful real-time pyrometry technique using the A/C ripple signal from heating lamps for in-situ temperature measurement. Temperature and electrical data from device wafers have been passively collected by ripple pyrometers in three RTP systems and analyzed. In this paper we report the statistical analysis of ripple temperature and electrical data from device wafers for a typical implant anneal process temperature range of 900 to 1000 °C.
Estimation of Emissivity of a Wafer in an RTP Chamber by a Dynamic Observer
Authors: Belikov Sergey , Hur David , Friedl Bernard , Ravindra N. M. 
Published: April 2011

AbstractA method of estimation of wavelength-dependent emissivity of silicon wafers using thermocouple measurements is presented here. A dynamic observer and a persistent excitation of the lamps are required for convergence of the observer's estimates to the actual values of parameters for emissivity approximation. A TI designed RTP equipment and adaptive close-loop temperature control have been used to generate the required persistent excitation. Theory of emissivity estimation by this method has been developed and illustrated by experiment with this 3- zone RTP system.
Numerical Modeling of Radiative Properties of Patterned Wafers with Sub-Micron Features
Authors: Hoppert Jeffrey B. , Miaoulis Ioannis N. , Wong Peter Y. 
Published: April 2011

AbstractDecreasing feature sizes in the microelectronics industry have led to numerous processing problems with thin film semiconductors. Non-uniform temperature distributions, due to microscale radiation effects on the radiative properties of the thin film structures, are responsible for wafer defects. These microscale radiation effects become significant as pattern spacing and film thicknesses reach the same order of magnitude as the wavelengths of the heat-source radiation. A numerical model has been developed in which normal emissivities for patterned wafers are calculated, using an effective index of refraction technique. In this study various patterns at temperatures critical to the thermal processing are examined.