bluuebunny/crossref_metadata_2025_split huggingface dataset:
Activated coagulation times in normal cats and dogs using MAX‐ACTTM tubes
Authors: See AM , Swindells KL , Sharman MJ , Haack KL , Goodman D , Delaporta A , Robertson I , Foster SF 
Published: June 2009

Objective  To establish reference values for activated coagulation time (ACT) in normal cats and dogs, by visual assessment of clot formation using the MAX‐ACTTM tube.Subjects  We recruited 43 cats and 50 dogs for the study; 11 cats and 4 dogs were excluded from the statistical analysis because of abnormalities on clinical examination or laboratory testing including anaemia, prolonged prothrombin time (PT) or activated partial thromboplastin time (APTT), or insufficient plasma volume for comprehensive laboratory coagulation testing.Procedure  Blood samples were collected via direct venipuncture for MAX‐ACT, packed cell volume/total solids, manual platelet estimation and PT/APTT measurement. Blood (0.5 mL) was mixed gently in the MAX‐ACT tube at 37°C for 30 s, then assessed for clot formation every 5 to 10 s by tipping the tube gently on its side and monitoring for magnet movement. The endpoint was defined as the magnet lodging in the clot. The technique was tested with 10 dogs by collecting two blood samples from the same needle insertion and running a MAX‐ACT on each simultaneously.Results  In normal cats the mean MAX‐ACT was 66 s (range 55–85 s). In normal dogs the mean was 71 s (range 55–80 s). There was no statistical difference between the first and second samples collected from the same needle insertion.Conclusions and Clinical Relevance  In both cats and dogs, a MAX‐ACT result >85 s should be considered abnormal and further coagulation testing should be performed. Additionally, failure to discard the first few drops of the sample does not appear to significantly affect results.
Acute toxicity in five dogs after ingestion of a commercial snail and slug bait containing iron EDTA
Authors: Haldane SL , Davis RM 
Published: June 2009

This case series of five dogs describes the effects of ingesting large amounts of an iron EDTA snail‐bait product. In all cases signs of toxicity occurred between 6 and 24 h after ingestion and included abdominal pain and haemorrhagic gastroenteritis. Two of the dogs had pretreatment serum iron levels measured and in both cases the levels were above normal limits. All of the dogs were treated with iron chelation therapy and supportive care including intravenous fluids, analgesics, gastric protectants and antibiotics. Chelation therapy with desferrioxamine mesylate did not cause adverse effects in any of the dogs and all survived to discharge. The effects of iron EDTA snail bait in dogs requires further study and minimum toxic doses need to be established.
Freezing equine semen: the effect of combinations of semen extenders and glycerol on post‐thaw motility
Authors: Scherzer J , Fayrer‐Hosken RA , Aceves M , Hurley DJ , Ray LE , Jones L , Heusner GL 
Published: June 2009

Objective  We evaluated combinations of two commercial semen extenders and three concentrations of glycerol to determine the combination that yielded the highest post‐thaw sperm motility.Design  A randomised 2 × 3 block design was used.Procedure  Semen was collected from four stallions (6 collections per stallion). The sample was diluted with either a dried skim‐milk glucose extender (EZ Mixin Original Formula) or a chemically defined, milk‐free diluent (INRA 96), and each was used in combination with 2%, 3% or 4% glycerol in standard commercial freezing medium. Sperm motility was assessed by microscopy in fresh and post‐thaw semen.Results  There was a significant difference between the two extenders in the motility of spermatozoa after cryopreservation (48.9% for INRA 96; 38.6% for EZ Mixin OF; P < 0.0001). Glycerol at 4% in freezing medium yielded the highest post‐thaw motility, significantly better than 2% (P < 0.05). Three of four stallions had significantly higher post‐thaw motility using INRA 96 relative to EZ Mixin OF (P < 0.01), and two of four stallions had significantly higher post‐thaw motility using 4% glycerol (P < 0.05). The combination of INRA 96 and 4% glycerol in freezing medium gave the highest average post‐thaw motility of 51.5%.Conclusion  In this study, INRA 96 combined with 4% glycerol yielded an average recovery of progressively motile sperm consistently above the 35% target.
Rapid, large‐scale and inexpensive genotype differentiation of Mus musculus castaneus and domesticus sub‐species
Authors: MCCORMICK HELEN M. , WILKINS RICHARD J. 
Published: June 2009

AbstractA robust rapid method is described for differentiating Mus musculus castaneus and domesticus sub‐species based on the analysis of restriction fragment length polymorphisms in three regions of the mtDNA genome.
Intraoperative floppy iris syndrome (IFIS): a practical approach to medical and surgical considerations in cataract extractions
Authors: Storr‐Paulsen Allan , Nørregaard Jens Christian , Børme Kim Kamp , Larsen Allan Boye , Thulesen Jesper 
Published: June 2009

Abstract.Intraoperative floppy iris syndrome (IFIS) during cataract surgery is characterized by iris fluttering, iris prolapse towards the incisions, and a progressive pupillary constriction leading to high rates of complications. The syndrome has been reported following the treatment of benign prostatic hyperplasia with α‐1a adrenergic receptor inhibitors, especially tamsulosin. The present paper describes the syndrome and discusses its pharmacological background. Several techniques to prevent and to deal with the syndrome are presented.
The Lausanne recommendations: a Dutch experience
Authors: Bessem B , Groot F P , Nieuwland W 
Published: June 2009

Objective:This study presents the results of 28 months of preparticipation cardiovascular screening using the Lausanne recommendations, which include a personal and family history, physical examination and electrocardiogram (ECG).Design:From January 2006 to April 2008 the data of the Lausanne screenings carried out at the University Centre of Sports Medicine in Groningen were collected.Participants:825 cardiovascular screenings were performed of which 397 were excluded. Exclusion criteria were age under 12 or over 35 years, multiple screenings (only the first was included) and known cardiovascular disease.Main outcome measures:Negative screening result, (false) positive screening result, medical consumption and number needed to screen.Results:A total of 371 (87%) athletes had a negative screening result. Fifty-five athletes (13%) underwent additional (stage 2) testing and seven (1.6%) further (stage 3) testing. Only 27 athletes (6.3%) were referred for additional testing based only on abnormalities of their ECG. Forty-seven athletes (11%) had a false-positive screening result. Ten athletes (2%) had a positive screening result and three (0.7%) were ultimately restricted from sports participation. Stage 2 medical consumption was 62%, 20% and 18% for one, two and three or more additional tests, respectively. Stage 3 medical consumption was 1.6%. The number of athletes needed to screen to find a single athlete with a potentially lethal cardiovascular disease was 143.Conclusion:This study found that when the Lausanne recommendations are implemented in The Netherlands, screening results resemble those found in previous studies. The number of athletes needed to screen to detect one athlete with a potentially lethal cardiovascular disease is also within an acceptable range.
Modulo scheduling without overlapped lifetimes
Authors: Stotzer Eric J. , Leiss Ernst L. 
Published: June 2009

This paper describes complementary software- and hardware-based approaches for handling overlapping register lifetimes that occur in modulo scheduled loops. Modulo scheduling takes the N-instructions in a loop body and constructs an M-stage software pipeline. The length of each stage in the software pipeline is the Initiation Interval (II), which is the rate at which new loop iterations are started. An overlapped lifetime has a live range longer than the II, and as a consequence, the current iteration writes a new value to a register before a previous loop iteration has fin-ished using the old value. Hardware and software solutions for dealing with overlapped lifetimes have been proposed by re-searchers and also implemented in commercial products. These solutions include rotating register files, register queues, modulo variable expansion, and post-scheduling live range splitting. Each of these approaches has drawbacks for embedded systems such as an increase in silicon area, power consumption, and code size.
Our approach, which is an improvement to the current solutions, prevents overlapped lifetimes through a combination of hardware and software techniques. The hardware element of our approach implements a register assignment latency that allows multiple in-flight writes to be pending to the same register. The software element of our approach uses dependence analysis and a constrained modulo scheduling algorithm to prevent overlapped lifetimes. We describe how to use these hardware and software techniques during modulo scheduling. Finally, we present the results of using our approach to compile embedded application code and present results in terms of modulo schedule quality and application performance.
Towards device emulation code generation
Authors: Heinz Thomas , Wilhelm Reinhard 
Published: June 2009

For non-embedded software, binary translation has shown to be a successful method for retargeting legacy software onto new platforms. To apply binary translation to embedded software, two issues must be considered. First of all, embedded software often involves real-time constraints that must still be met after translation. Secondly, embedded software contains a significant amount of code dedicated to peripheral device communication which necessitates device emulation. This paper focuses on the last aspect.
Usually, device emulation code is handcrafted which is tedious and error-prone. This paper presents a method to automatically generate device emulation code from a formal specification of source and target device operations. At the heart of the device operation semantics lie quantifier-free formulae in the theory of fixed width bit vector arithmetic which is a decidable fragment of first-order logic. To the best of our knowledge, this is the first attempt to generate device emulation code from a formal specification.
Tracing interrupts in embedded software
Authors: Gracioli Giovani , Fischmeister Sebastian 
Published: June 2009

During the system development, developers often must correct wrong behavior in the software---an activity colloquially called program debugging. Debugging is a complex activity, especially in real-time embedded systems because such systems interact with the physical world and make heavy use of interrupts for timing and driving I/O devices.
Debugging interrupts is difficult, because they cause non-linear control flow in programs which is hard to reproduce in software. Record/replay mechanisms have proven their use to debugging embedded systems, because they provide means to recreate control flows offline where they can be debugged.
In this work, we present the data tracing part of the record/replay mechanism that is specifically targeted to record interrupt behavior. To tune our tracing mechanism, we use the observed principle of return address clustering and a formal model for quantitative reasoning about the tracing mechanism. The presented heuristic and mechanisms show surprisingly good results---up to an 800 percent speedup on the selector function and a 300 percent reduction on duplicates for non-optimal selector functions---considering the leanness of the approach.
Ten ways to waste a parallel computer
Authors: Yelick Katherine 
Published: June 2009

As clock speed increases taper off and hardware designers struggle to scale parallelism within a chip, software developers and researchers must face the challenge of writing portable software with no clear architectural target. On the hardware side, energy considerations will dominate many of the design decisions, and will ultimately limit what systems and applications can be built. This is especially true at the high end, where the next major milestone of exascale computing will be unattainable without major improvements in efficiency.
Although hardware designers have long worried about the efficiency of their designs, especially for battery-operated devices, software developers in general have not. To illustrate this point, I will describe some of the top ways to waste time and therefore energy waiting for communication, synchronization, or interactions with users or other systems. Data movement, rather than computation, is the big consumer of energy, yet software often moves data up and down the memory hierarchy or across a network multiple times. At the same time, hardware designers need to take into account the constraints of the computational problems that will run on their systems, as a design that is poorly matched to the computational requirements will end up being inefficient. Drawing on my own experience in scientific computing, I will give examples of how to make the combination of hardware, algorithms and software more efficient, but also describe some of the challenges that are inherent in the application problems we want to solve. The community needs to take an integrated approach to the problem, and consider how much business or science can be done per Joule, rather than optimizing a particular component of the system in isolation. This will require rethinking the algorithms, programming models, and hardware in concert, and therefore an unprecedented level of collaboration and cooperation between hardware and software designers.
Internet-scale service infrastructure efficiency
Authors: Hamilton James 
Published: June 2009

High-scale cloud services provide economies of scale of five to ten over small-scale deployments, and are becoming a large part of both enterprise information processing and consumer services. Even very large enterprise IT deployments have quite different cost drivers and optimizations points from internet-scale services. The former are people-dominated from a cost perspective whereas internet-scale service costs are driven by server hardware and infrastructure with people costs fading into the noise at less than 10%.
In this talk we inventory where the infrastructure costs are in internet-scale services. We track power distribution from 115KV at the property line through all conversions into the data center tracking the losses to final delivery at semiconductor voltage levels. We track cooling and all the energy conversions from power dissipation through release to the environment outside of the building. Understanding where the costs and inefficiencies lie, we'll look more closely at cooling and overall mechanical system design, server hardware design, and software techniques including graceful degradation mode, power yield management, and resource consumption shaping.
Architecting phase change memory as a scalable dram alternative
Authors: Lee Benjamin C. , Ipek Engin , Mutlu Onur , Burger Doug 
Published: June 2009

Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM's scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance.
We propose, crafted from a fundamental understanding of PCM technology parameters, area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6x slower and requires 2.2x more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2x and 1.0x, using narrow rows to mitigate write energy and multiple rows to improve locality and write coalescing. Partial writes enhance memory endurance, providing 5.6 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance.
Spatio-temporal memory streaming
Authors: Somogyi Stephen , Wenisch Thomas F. , Ailamaki Anastasia , Falsafi Babak 
Published: June 2009

Recent research advocates memory streaming techniques to alleviate the performance bottleneck caused by the high latencies of off-chip memory accesses. Temporal memory streaming replays previously observed miss sequences to eliminate long chains of dependent misses. Spatial memory streaming predicts repetitive data layout patterns within fixed-size memory regions. Because each technique targets a different subset of misses, their effectiveness varies across workloads and each leaves a significant fraction of misses unpredicted.
In this paper, we propose Spatio-Temporal Memory Streaming (STeMS) to exploit the synergy between spatial and temporal streaming. We observe that the order of spatial accesses repeats both within and across regions. STeMS records and replays the temporal sequence of region accesses and uses spatial relationships within each region to dynamically reconstruct a predicted total miss order. Using trace-driven and cycle-accurate simulation across a suite of commercial workloads, we demonstrate that with similar implementation complexity as temporal streaming, STeMS achieves equal or higher coverage than spatial or temporal memory streaming alone, and improves performance by 31%, 3%, and 18% over stride, spatial, and temporal prediction, respectively.
Architectural core salvaging in a multi-core processor for hard-error tolerance
Authors: Powell Michael D. , Biswas Arijit , Gupta Shantanu , Mukherjee Shubhendu S. 
Published: June 2009

The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a priori, either at manufacture-time or in the field, cores with such errors must be disabled in the absence of hard-error tolerance. While caches, with their regular and repetitive structures, are easily covered against hard errors by providing spare arrays or spare lines, structures within a core are neither as regular nor as repetitive. Previous work has proposed microarchitectural core salvaging to exploit structural redundancy within a core and maintain functionality in the presence of hard errors. Unfortunately microarchitectural salvaging introduces complexity and may provide only limited coverage of core area against hard errors due to a lack of natural redundancy in the core.
This paper makes a case for architectural core salvaging. We observe that even if some individual cores cannot execute certain operations, a CPU die can be instruction-set-architecture (ISA) compliant, that is execute all of the instructions required by its ISA, by exploiting natural cross-core redundancy. We propose using hardware to migrate offending threads to another core that can execute the operation. Architectural core salvaging can cover a large core area against faults, and be implemented by leveraging known techniques that minimize changes to the microarchitecture. We show it is possible to optimize architectural core salvaging such that the performance on a faulty die approaches that of a fault-free die--assuring significantly better performance than core disabling for many workloads and no worse performance than core disabling for the remainder.
End-to-end register data-flow continuous self-test
Authors: Carretero Javier , Chaparro Pedro , Vera Xavier , Abella Jaume , González Antonio 
Published: June 2009

While Moore's Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort of modern computing systems, which has grown to dominate the cost of system design. On the other hand, technology scaling leads to burn-in phase out. As a result, in-the-field error rate may increase due to both actual errors and latent defects. Whereas data can be protected with arithmetic codes (like parity or ECC), there is a lack of cost-effective mechanisms for control logic.
This paper presents a light-weight microarchitectural mechanism that ensures that data consumed through registers are correct. Microarchitecture presents a new way to manage reliability and testing without significantly sacrificing cost and performance, offering a unique opportunity to detect errors in the field at low cost. Our results show a coverage around 90% for the targeted structures with a cost in power and area of about 4%. The structures protected include the issue queue logic and the data associated (i.e., tags, control signals), input multiplexors, rename data, replay logic, register free list, bypasses data and logic, MOB data and addresses, register file logic, register file storage and functional units.
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
Authors: Hong Sunpyo , Kim Hyesoon 
Published: June 2009

GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Programming thousands of massively parallel threads is a big challenge for software engineers, but understanding the performance bottlenecks of those parallel programs on GPU architectures to improve application performance is even more difficult. Current approaches rely on programmers to tune their applications by exploiting the design space exhaustively without fully understanding the performance characteristics of their applications.
To provide insights into the performance bottlenecks of parallel applications on GPU architectures, we propose a simple analytical model that estimates the execution time of massively parallel programs. The key component of our model is estimating the number of parallel memory requests (we call this the memory warp parallelism) by considering the number of running threads and memory bandwidth. Based on the degree of memory warp parallelism, the model estimates the cost of memory requests, thereby estimating the overall execution time of a program. Comparisons between the outcome of the model and the actual execution time in several GPUs show that the geometric mean of absolute error of our model on micro-benchmarks is 5.4% and on GPU computing applications is 13.3%. All the applications are written in the CUDA programming language.
Reactive NUCA
Authors: Hardavellas Nikos , Ferdman Michael , Falsafi Babak , Ailamaki Anastasia 
Published: June 2009

Increases in on-chip communication delay and the large working sets of server and scientific workloads complicate the design of the on-chip last-level cache for multicore processors. The large working sets favor a shared cache design that maximizes the aggregate cache capacity and minimizes off-chip memory requests. At the same time, the growing on-chip communication delay favors core-private caches that replicate data to minimize delays on global wires. Recent hybrid proposals offer lower average latency than conventional designs, but they address the placement requirements of only a subset of the data accessed by the application, require complex lookup and coherence mechanisms that increase latency, or fail to scale to high core counts.
In this work, we observe that the cache access patterns of a range of server and scientific workloads can be classified into distinct classes, where each class is amenable to different block placement policies. Based on this observation, we propose Reactive NUCA (R-NUCA), a distributed cache design which reacts to the class of each cache access and places blocks at the appropriate location in the cache. R-NUCA cooperates with the operating system to support intelligent placement, migration, and replication without the overhead of an explicit coherence mechanism for the on-chip last-level cache. In a range of server, scientific, and multiprogrammed workloads, R-NUCA matches the performance of the best cache design for each workload, improving performance by 14% on average over competing designs and by 32% at best, while achieving performance within 5% of an ideal cache design.