bluuebunny/crossref_metadata_2025_split huggingface dataset:
Rheed Observations of Silicon (100) Surface Reconstruction after Remote Hydrogen Plasma Cleaning
Authors: Hsu T. , Breaux L. , Anthony B. , Banerjee S. , Tasch A. 
Published: March 2011

ABSTRACTLow temperature silicon epitaxy is critical to novel silicon-based devices requiring hyper-abrupt transitions in doping profiles or heterointerfaces. Epitaxy by Remote Plasma-Enhanced Chemical Vapor Deposition (RPCVD) consists of an in situ remote hydrogen plasma clean of the silicon surface followed by growth of silicon from silane at 220° - 400°C. Reconstruction of the silicon (100) surface from a (1×1) to a (2×1) structure after cleaning at 310°C is observed by RHEED, indicating an atomically clean surface. The removal of carbon and oxygen has been further substantiated by Auger Electron Spectroscopy (AES) and growth on these atomically clean substrates has produced good quality epitaxial films. Using remote hydrogen plasma cleans at lower temperature we report the first observation of third-order silicon surface reconstruction on a Si(100) surface, where two faint fractional order streaks between the sharp integral order streaks are observed. After a short (5 minute), low temperature (300-400 °C) anneal the third order pattern transforms rather quickly to a strong (2×1) reconstruction pattern. The third order pattern can then be restored by following the anneal with a repeat of the lower temperature hydrogen clean. Although the origin of the third order pattern is unclear at this time, we believe it is due to a Si-H complex formation at the silicon surface.
Stress Gradients in SIO2 Thin Films Prepared by Thermal Oxidation and Subjected to Rapid Thermal Annealing
Authors: Bjorkman C.H. , Fitch J.T. , Lucovsky G. 
Published: March 2011

ABSTRACTWe have studied stress gradients in thermally grown SiO2 thin films and relaxation of the stress by rapid thermal annealing. These properties were examined by incrementally etching back the SiO2 films and performing infrared spectroscopy and beam-bending measurements at each thickness. The thickness-averaged values measured were then deconvoluted to obtain stress values for thin layers of the SiO2 films. We observed steep stress gradients close to the Si/SiO2 interface for wet oxides which were similar to those previously studied in dry oxides. The stress gradients were steeper for films grown or annealed at high temperatures. In addition, we have been able to show that thin films (= 200 Å) relax more freely than thicker films (= 1000 Å), in which oxide close to the interface is prevented from relaxing by the oxide on top of it.
Optimization of a Tin/TiSi2 p+ Diffusion Barrier Process
Authors: Lee S.S. , Galovich C.S. , Fuchs K.P. , Kwong D.L. , Hirvonen J. , Huang J. 
Published: March 2011

ABSTRACTThe TiN/TiSi2 structure, formed by rapid thermal nitridation of a spatter-deposited titanium film, has been demonstrated to be effective as a diffusion barrier and as a low resistance contact material for VLSI submicron metallization. An optimization experiment, designed using the RS/Discover software package, was used to identify a metallization process that minimized p+ resistance as well as maximized barrier capability. Source/drain implant doses, as-deposited titanium film thickness, and rapid thermal processing parameters were the factors varied in the experiment. Of particular significance is a comparison of the effects of a two-step versus one-step rapid thermal anneal on control of the TiN/TiSi2 thickness ratio. A TiN layer of sufficient thickness for barrier integrity and adequate consumption of implant damage in the formation of the TiSi2 layer are desired. Electrical and thermal stability measuremints of the resultant AlSiCu/TiN/TiSi2 p+ contact system are presented.
Thin Silicon Epitaxial Layer Deposition with Reduced Pressure RTP-CVD
Authors: Wong Fred , Chen Charles Y. , Ku Yen-Hui 
Published: March 2011

ABSTRACTDesigns of the advanced integrated circuit devices now require much thinner epitaxial films to achieve superior performance. The capability of depositing thin silicon epitaxial layers which have sharp transition width, well-controlled dopant level, high crystallographic quality, and good growth uniformity across the wafer is essential for high speed bipolar and submicron CMOS technologies. This paper describes a thin silicon epitaxial growth process using a recently developed low pressure CVD silicon epitaxial reactor employing rapid thermal processing with incoherent light source. Crystallographic quality, slip formation, transition width, growth uniformity, and dopant uniformity were investigated using TEM, spreading resistance measurements, SIMS, sheet resistance measurements, and FTIR. The SIMS and spreading resistance measurements revealed that auto-doping effect has been minimized. The transition width can be controlled to 10% of the film thickness while maintaining the growth rate up to 1 μm/min at a deposition temperature in the range of 900 - 1000°C. The growth and dopant uniformities across the wafer as determined by FTIR and Prometrix RS-30 Omnimap are better than 1% and 3% per sigma for epitaxial layer thickness under 2 μm. Initial results on selective epitaxial growth was discussed.
The Effect of Post-Growth Anneals on Nitroxide Films
Authors: Wright Peter J. , Kermani Ahmad , Saraswat Krishna C. 
Published: March 2011

ABSTRACTA new technique of post-oxidation annealing has been introduced to improve the properties and long term reliability of ultrathin (<100 Å) MOS gate dielectrics. In this technique, after oxidation, nitridation is done in NH3 followed by a light reoxidation in O2 and then an inert anneal in Ar or N2. Using this technique both optimum performance as well as reliability can be obtained without sacrificing either. NH3 anneal of SiO2 improved the hot electron immunity, but degraded the interface quality. Good properties could be obtained by a strong reoxidation of the nitrided films, however, at the expense of a substantial increase in the film thickness. Nitrogen and argon ambients were found to be equally effective at improving film properties. By annealing the film in an inert ambient following reoxidation of the nitroxide, fixed charge can be further decreased with little oxide grown, electron mobility in NMOS FETs increases further, and the hot electron lifetime is much longer than that of the starting oxide.
The Kinetics of Low Pressure Rapid Thermal Oxidation of Silicon
Authors: Lassig Stephan E , L John 
Published: March 2011

ABSTRACTA study of the oxidation kinetics of lightly doped (100) silicon in dry oxygen has been carried out at different pressures (0.03 atm. to 1.0 atm.) and temperatures (900ºC to 1200ºC) for short times (< 500 seconds). The data can be fit equally well to the parabolic model as it can to the linearparabolic or parallel oxidation models. The activation energy derived from analysis of the parabolic rate constant is 0.94 eVand is the same at 1.0 and 0.1 atmosphere dry O2. It was also found that the parabolic rate constant displayed a linear dependence on the O2 pressure.
Advanced Excimer Laser Annealing of Thin Poly Si Films after Solid Phase Grain Growth
Authors: Noguchi Takashi , Tajima Kazuhiro , Morita Yasushi 
Published: March 2011

ABSTRACTThin silicon films with dendritic large grains can be obtained by Si+ or P+ implantation and subsequent low temperature annealing of the silicon film. We tried further exposing the films with an excimer laser after the grain growth. As a result, improvement of electronic properties such as high carrier mobility or low resistivity were obtained. By TEM observation, polycrystalline grains with a dendritic structure did not melt after laser annealing and it was found that the improvement of electronic properties were achieved mainly due to the improvement of crystallinity by U-V(Ultra-Violet) reflectance, ESR(Electron Spin Resonance) analysis and TFT characteristics. We are convinced that this advanced laser pulse annealing method is an ideal RTA process in the near future and is expected to be applicable to ULSI processes for inter connects, high density stacked SRAM and for large area electronics on glass such as a contact line sensor or LCD(Liquid Crystal Display).
Ultra-Shallow Diffused Emitter-Base Profiles Fabricated by Rapid Thermal Processing for High Speed Bipolar Devices
Authors: Urner J. E. , Drowley C. I. , Voorde P. Vande , Kermani A. 
Published: March 2011

ABSTRACTThe development of next-generation high-speed bipolar devices depends critically on reproducible shallow dopant profiles, with base and emitter widths considerably less than 1000 Angstroms. Sequential diffusion of boron and arsenic from implanted polysilicon is a promising means of producing such shallow emitter-base profiles. The restricted thermal budget required to reproducibly form such shallow junctions severely limits the use of conventional furnaces. We report the formation of extremely shallow emitter-base profiles using rapid thermal processing (RTP) in a double-diffused polysilicon emitter process. Polysilicon was implanted with various doses of BF2 and subjected to a conventional furnace anneal at 900ºC. This process was followed by As implantation and furnace anneal at 900ºC or RTP at 10500C or 1100ºC. A range of emitter-base profiles was generated with emitter and base widths ranging from 350-800A. Emitter-base profiles were measured using low-energy Secondary Ion Mass Spectrometry (SIMS), after removal of the polysilicon to improve depth resolution. Deconvolution of the instrumental broadening function allowed extraction of base and emitter widths as well as the boron concentration in the base. Variation of the profiles is discussed as a function of anneal times and implant dose. Modified SUPREM III parameters are obtained for diffusivities under these RTP conditions. The implications for high speed bipolar device fabrication will be presented.
Pt/Ti Low Resistance Non-Alloyed Ohmic Contacts to InP-Based Photonic Devices
Authors: Katz A. , Chu S. N. G. , Thomas P. M. , Dautremont-Smith W. C. 
Published: March 2011

ABSTRACTPt/ri low resistance non-alloyed ohmic contacts to p-InP-based contact layers in photonic devices, which were formed by rapid thermal processing (RTP), were studied. E-gun evaporated Pt/Ti metallization deposited onto 1.5· 1019 cm−3 Zn doped In0.53Ga0.47 As yielded the best electrical performance. These contacts were ohmic as deposited with a specific contact resistance value of 3.0 · 10−4 Ωcm2. RTP at higher temperatures led to decrease of the specific contact resistance to 3.4 · 10−8 Ωcm2 (0.08Ωmm) as a result of heating at 450°C for 30 sec. This heat treatment caused only a limited interfacial reaction (about 20 nm thick) between the Ti and the InGaAs, resulted in a thermally stable contact and induced tensile stress of 5.6 · 109 dyne · cm−2 at the metal layer but without degrading the adhesion. Heating at temperatures higher than 500°C resulted in an extensive interaction and degradation of the contact.
Deep-Level Transient Spectroscopy Studies of Rapid Thermal Processed GaAs with Sio2 Encapsulant
Authors: Katayama Masayuki , Tokuda Yutaka , Ando Nobuo , Kitagawa Akio , Usami Akira , Inoue Yajiro , Wada Takao 
Published: March 2011

ABSTRACTEffects of rapid thermal processing (RTP) on SiO2/GaAs interfaces have been studied with X-ray photoelectron spectroscopy, capacitance-voltage measurements and deep-level transient spectroscopy. SiO2 films of 50, 200 and 1250 nim thickness have been deposited on GaAs. RTP has been performed at 760 and 910°C for 9 s. The rapid diffusion of Ga through the SiO2 film occurs, and the As loss and the formation of the As layer near the interface are observed. The decrease of the carrier concentration occurs in all RTP samples. Five electron traps EAI (Ec – 0.27 eV), EA2 (Ec – 0.32 eV), EA3 (Ec – 0.47 eV), EA4 (Ec – 0.58 eV) and EL2 (Ec – 0.78 eV) are produced by RTP. It is considered that the production of the trap EL2 is closely related to the Ga outdiffusion into the SiO2 film and the As indiffusion from the pile-up of elemental As near the interface. Effects of SiO2 film thickness on RTP-SiO2/GaAs are also reported.
Effects of Wafer Backside Emissivity Variation and System Control for Low Temperature Applications
Authors: Pelletier Jay J. , Winter Thomsa E. 
Published: March 2011

ABSTRACTRapid thermal processing technology is being investigated for many uses such as shallow junction diffusion and implant annealing. Most of these processes are done at temperatures above 700 C. It is desirable to use the rapid thermal processor for some low temperature applications such as hillock reduction because of the systems ability to heat up and cool down almost instantaneously as compared to conventional furnaces. Machine control for low temperature processing is more difficult than high temperature processing dur to the optical pyrometers inability to perform at its lower limit. Well documented nonlinear effects of wafer backside emissivity over a temperature range of 400C to 600C will also contribute to wafer to wafer temperature instability. In order to fully utilize the advantages of rapid thermal processing technology, it is imperative that the RTPs performance and repeatability at low temperatures be understood.This paper will discuss the effect of wafer to wafer backside emissivity differences on wafer temperature for low temperature applications. Typical wafer to wafer backside emissivity variation is presented as well as the measurement error of the Peak “ACE” system. “ACE” (Automatic Compensation for Emissivity) can be used to correct for emissivity differences from wafer to wafer.Effect of improper emissivity selection on actual wafer temperature is presented. Also actual wafer temperature sensitivity to changes in programmed temperature with constant, uncompensated emissivity is demonstrated.Lamp current monitoring is discussed with supporting data to show the ability of it to be used as a day to day monitor of system performance. Also, The effects of lamp problems associated with idle current.
Simulation of Temperature Effects during Rapid Thermal Processing
Authors: Kakoschek R. , BuβMann E. 
Published: March 2011

ABSTRACTA complete theory of wafer heating during rapid thermal processing (RTP) is presented. Excellent agreement with experimental results of two commercial RTP systems is obtained. The temperature uniformity is limited by radiation loss at the wafer edge in the stationary state and by nonuniform illumination of the wafer during ramp-up. Structures on wafers are also potential sources for nonuniform heating. Considerable dynamic temperature inhomogeneities during rap-up might limitfu ture applications of RTPe specially when wafer sizes become larger. Possible improvements are suggested regarding adequate process cycling, chip and equipment design.
Properties of Thin Inter-Polysilicon Reoxidized Nitrided Oxides Prepared by Rapid Thermal Processing (RTO/RTN/RTO)
Authors: Cheung Andrew W. , Lo G. Q. , Kwong Dim-Lee , Alvi N. S. , Kermani A. 
Published: March 2011

ABSTRACTIn the search of a high quality thin inter-polysilicon dielectric which has high breakdown voltage and low leakage current for high density non-volatile memory applications, thin (150±) inter-polysilicon reoxidized nitrided oxide capacitors were fabricated with multiple rapid thermal processing. While rapid thermal nitridation degraded the breakdown field if compared to the rapid thermal oxide capacitors, rapid thermal reoxidation greatly enhanced the dielectric strength of the rapid thermal nitrided samples. The short reoxidations increased the film thickness by less than 10 \. Breakdown field of optimized inter-polysilicon RTO/RTN/RTO capacitors up to 14 MV/cm has been measured.
Chemical Vapor Deposition of Polycrystalline Silicon in a Rapid Thermal Processor
Authors: Liao Jimmy C. , Crowley John L. , Kamins Ted I. 
Published: March 2011

ABSTRACTThe deposition of polycrystalline silicon in a rapid thermal processor was studied in the temperature range of 600-1100°C using a mixture of silane and argon at reduced pressures. The amorphous-to-polycrystalline transition temperature was determined by X-ray diffraction and UV-visible spectrophotometry to be between 650 and 700°C. The activation energy of the deposition was found to be approximately 1.5 eV in the temperature range of 600 to 800°C, in reasonable agreement with LPCVD and APCVD results. At 800°C and above, the deposition rate depended only weakly on temperature, as is characteristic of mass-transport-fimited processes. The partial pressure of silane was found to affect the deposition rate in both surface-limited and gas-transport-limited depositions. A UV-visible spectrophotometer was used as a reflectometer to measure the surface roughness of the samples, which in general increased with increasing deposition temperature and film thickness. At the lower deposition temperatures, the surfaces were very smooth, as is characteristic of amorphous-silicon films. Furthermore, the ability to change temperature rapidly appears to allow smoother films to be obtained by initially depositing at lower temperatures, and then ramping to a higher temperature to increase the deposition rate.
Damage Growth in Si During Self-Ion Irradiation: a Study of Ion Effects Over an Extended Energy Range
Authors: Holland O. W. , El-Ghor M. K. , White C. W. 
Published: March 2011

AbstractDamage nucleation/growth in single-crystal Si during ion irradiation is discussed. For MeV ions, the rate of growth as was well as the damage morphology are shown to vary widely along the track of the ion. This is attributed to a change in the dominant, defect-related reactions as the ion penetrates the crystal. The nature of these reactions were elucidated by studying the interaction of MeV ions with different types of defects. The defects were introduced into the Si crystal prior to high-energy irradiation by self-ion implantation at a medium energy (100 keV). Varied damage morphologies were produced by implanting different ion fluences. Electron microscopy and ion-channeling measurements, in conjunction with annealing studies, were used to characterize the damage. Subtle changes in the predamage morphology are shown to result in markedly different responses to the high-energy irradiation, ranging from complete annealing of the damage to rapid growth. These divergent responses occur over a narrow range of dose (2–3 × 1014 cm-2) of the medium-energy ions; this range also marks a transition in the growth behavior of the damage during the predamaging implantation. A model is proposed which accounts for these observations and provides insight into ion-induced growth of amorphous layers in Si and the role of the amorphous/crystalline interface in this process.
Shallow Junction Formation in As-Implanted Si by Low-Temperature Rapid Thermal Annealing
Authors: El-Ghor M. K. , Pennycook S. J. , Zuhr R. A. 
Published: March 2011

AbstractShallow junctions were formed in single-crystal Si(100) by implantation of As at energies between 2 and 17.5 keV followed by conventional furnace annealing or by rapid thermal annealing (RTA). Cross-sectional transmission electron microscopy (XTEM) showed that defect-free shallow junctions could be formed at temperatures as low as 700 °C by RTA, with about 60% dopant activation. From a comparison of short-time and long-time annealing, it is proposed that surface image forces are responsible for the efficient removal of end-of-range (EOR) dislocation loops
On the Formation of Thick and Multiple Layer Simox Structures and their Applications
Authors: Namavar F. , Cortesi E. , Soref R. A. , Sioshansi P. 
Published: March 2011

AbstractThis paper will address the formation of SIMOX structures with thick and multiple buried SiO2 layers by multiple oxygen implantation and growth of epitaxial Si by chemical vapor deposition (CVD). Our results indicate that SIMOX material can be produced with a buried layer of any thickness or with any number of distinct buried oxide layers and distinct silicon layers. Thick and double buried SiO2 layer material may be useful for high voltage isolation and electric field shielding.In addition, we have demonstrated optical waveguide action in SIMOX wafers. This suggests that in a double buried SiO2 layer system, three dimensional stacked integration of silicon waveguides is possible, including two level optical interconnects.
Study of Stress and Morphology of Silicon–On–Insulator by Means of Ultraviolet Reflectance Spectroscopy
Authors: Lacquet Bea M , Swart Pieter L 
Published: March 2011

AbstractSOI material was prepared by implanting a high dose of nitrogen into crystalline silicon at an energy of 160 keY to form a buried layer of silicon nitride. Ultraviolet reflectance spectroscopy was employed to characterize the material. In the current presentation the isothermal annealing behaviour of the surface material was investigated with regard to amorphization and stress. Measured UV–reflectance of the samples are compared to simulated reflectance data which were obtained by presenting the implanted material as a layered structure with the surface layer consisting of a mixed layer of amorphous and crystalline silicon. From these simulations the percentage amorphization at each stage during the annealing cycle is quantitatively determined. Stress is qualitatively determined by considering the shift in the position of the frequencies at which reflectance maxima associated with Van Hove singularities are observed in the ultraviolet range. The annealing cycle used in this work proved to be adequate for returning the material back to single crystal status and relieving the initial stress in this layer.
Enhanced Interdiffusion of GaAs-AlgaAs Interfaces Following Ion Implantation and Rapid Thermal Annealing
Authors: Kahen K. B. , Rajeswaran G. , Peterson D. L. , Zheng L. R. , Ott N. L. 
Published: March 2011

AbstractThe interdiffusion of GaAs-AlGaAs interfaces has been shown to be enhanced following ion implantation and rapid thermal annealing at approximately 950°C. A model is presented which explains this phenomenon. It is based on the solution of coupled diffusion equations involving the excess vacancy and Al distributions following ion implantation. Both initial distributions are obtained from the solution of a three-dimensional Monte Carlo simulation of ion implantation into a heterostructure sample. The model is found to be in excellent agreement with several sets of experimental data. More specifically, the model is shown to be valid for ions which do not diffuse appreciably in the time frame of the rapid thermal annealing and for as-implanted vacancy concentrations below ∼6×1019 cm−3. Above that concentration, some vacancies are hypothesized to coalesce, thus being unavailable to assist in the enhanced interdiffusion process.
Ion Beam Mixing of GaAs/AlGaAs Superlattice and ITS Relationship to Amorphization
Authors: Pronko P. P. , McCormick A. W. , Patrizio D. B. , Rai A. K. , Kolbas R. M. , Frank B. S. 
Published: March 2011

AbstractThis work is part of a study to understand the process by which energetic ion bombardment can be used to mix the chemical components of AlGaAs and GaAs superlattice (S/I.) layers of nominal 35 to 50Å thickness. Data reported here involve the retention and build-up of collision cascade damage in the S/I. and its relationship to amorphization and chemical mixing in these systems.