bluuebunny/crossref_metadata_2025_split huggingface dataset:
Low Temperature Deposition of Si-based Thin Films on Plastic Films Using Pulsed-Discharge PECVD under Near Atmospheric Pressure
Authors: Matsumoto Mitsutaka , Inayoshi Yohei , Suemitsu Maki , Nakajima Setsuo , Uehara Tsuyoshi , Toyoshima Yasutake 
Published: April 2011

ABSTRACTLow temperature (150 °C) deposition of doped and undoped polycrystalline Si (poly-Si) as well as SiNX films on polyethylene terephthalate (PET) films has been achieved with practical deposition rates by using pulsed-plasma CVD under near-atmospheric pressure. The precursor is SiH4 diluted in H2 for poly-Si while N2 has been additionally used for SiNx. No inert gases such as He was used. A short-pulse based power system has been employed to maintain a stable discharge in the near-atmospheric pressures. With this technique, deposition of poly-Si thin film with virtually no incubation layer is possible, which in the case of P-doped poly-Si shows a Hall mobility (μH) of 1.5 cm2/V·s.
Pulsed Laser Heating-induced Surface Rapid Cooling and Amorphization
Authors: Tian Longzhang , Wang Xinwei 
Published: April 2011

ABSTRACTIn this work, hybrid atomistic-macroscale simulation is conducted to explore the crystallization process of Si surface in the situation of fast melting and solidification induced by ultrafast laser heating and heat conduction. Using the environment-dependent interatomic potential, samples containing 2,880 and 11,520 Si atoms are modeled to provide accurate details for the relationship between the finial crystal structure and the parameters of laser pulses. For different pulsed lasers, amorphous layers are found to form when the laser fluence exceeds a certain critical value. An empirical correlation Ec = 448.76 × (tg)0.56 is obtained to relate this critical fluence to the laser pulse width. It is found that the final thickness of amorphous layer is related to the fluence of the laser pulse with the same full width at half maximum (FWHM). Employing laser pulses with FWHM = 6.67 ns, the formation and recrystallization processes of a 12 nm thick amorphous layer is further investigated, which may have great potential in laser manufacture techniques for Si-associated structures.
Polycrystalline Silicon Thin-film Solar Cells on ZnO:Al Coated Glass
Authors: Becker Christiane , Dogan Pinar , Gorka Benjamin , Ruske Florian , Hänel Tobias , Behrends Jan , Fenske Frank , Lips Klaus , Gall Stefan , Rech Bernd 
Published: April 2011

ABSTRACTThin film solar cells based on polycrystalline silicon are an appealing option combining the advantages of thin film technologies, namely low cost, and the superior electrical properties of crystalline silicon. The specific structure aimed at in this work uses the relatively simple contacting scheme used in amorphous silicon thin film solar cells which relies on a front contact consisting of a transparent conducting oxide (TCO). Electron beam evaporation is applied as preparation method for the silicon films with high deposition rate. Solid phase crystallization (SPC) is used to crystallize the silicon films after deposition.In this work the properties of as-deposited and crystallized silicon films produced by e beam evaporation are investigated as a function of deposition temperature. It is shown that the largest crystallites are obtained for deposition around 300 °C and subsequent treatment at 600 °C, while deposition at higher temperatures leads to small crystal grains which are not changed significantly during SPC.Solar cells have been prepared on TCO-coated glass and were studied by measurements of the external quantum efficiency.
Floating-Gate a-Si:H TFT Nonvolatile Memories
Authors: Kuo Yue , Nominanda Helinda 
Published: April 2011

ABSTRACTCharge and discharge phenomena of the floating-gate amorphous silicon thin film transistor have been studied under dynamic operation conditions. The charge storage capacity decreases with the increase of the drain voltage because it is easier for electrons to be transported to the drain electrode than to be injected into the gate dielectric layer. The discharge efficiency with respect to the drain voltage has been investigated using three different discharge methods: negative gate bias voltage, light exposure, and thermal annealing, separately. The channel length affected both the charge capacity and the discharge efficiency due to the charge storage mechanism and the channel resistance. Majority of the stored charges were removed with the above method through various mechanisms. The low temperature favors the charge storage but the high temperature favors the discharge. This study revealed key parameters for the optimum operation of the low temperature fabricated nonvolatile memory device.
The Positive Gate Bias Annealing Method for the Suppression of a Leakage Current in the SPC-Si TFT on a Glass Substrate
Authors: Park Sang-Geun , Park Joong-Hyun , Kuk Seung-Hee , Kang Dong-Won , Han Min-Koo 
Published: April 2011

ABSTRACTWe fabricated PMOS SPC-Si TFTs which show better current uniformity than ELA poly-Si TFTs and superior stability compare to a-Si:H TFT on a glass substrate employing alternating magnetic field crystallization. However the leakage current of SPC-Si TFT was rather high for circuit element of AMOLED display due to many grain boundaries which could be electron hole generation centers. We applied off-state bias annealing of VGS=5V, VDS=−20V in order to suppress the leakage current of SPC-Si TFT. When the off-state bias annealing was applied on the SPC-Si TFT, the electron carriers were trapped in the gate insulator by high gate-drain voltage (25V). The trapped electron carriers could reduce the gate-drain field, so that the leakage current of SPC-Si TFT was reduced after off-state bias annealing. We applied AC-bias stress on the gate node of SPC-Si TFT for 20,000 seconds in order to verify that the leakage current of SPC-Si TFT could be remained low at actual AMOLED display circuit after off-state bias annealing. The suppressed leakage current was not altered after AC-bias stress. The off-state bias annealed SPC-Si TFT could be used as pixel element of high quality AMOLED display.
Improved Photon Absorption in a-Si:H Solar Cells using Photonic Crystal Architectures
Authors: Biswas Rana , Zhou Dayu 
Published: April 2011

ABSTRACTImproved light-trapping is a major route to improving solar cell efficiencies. We design a combination of a 2-dimensional photonic crystal and a one-dimensional distributed Bragg reflector as the back reflector for a-Si:H solar cells. This configuration avoids inherent losses associated with textured back-reflectors. The photonic crystals are composed of ITO and can easily serve as a conducting back contact. We have optimized the geometry of the photonic crystal to maximize absorption using rigorous scattering matrix simulations. The photonic crystal provides strong diffraction of red and near-IR wavelengths within the absorber layer and can enhance the absorption by more than a factor of 10 relative to the case without the photonic crystal. The optical path length with the photonic crystal can improve over the limit for a random roughened scattering surface.
Impurities and Grain Size Modeling in Recrystallized Silicon
Authors: Kalinin Valeri V. , Myasnikov Alexandre M. , Zyryanov Vladislav E. 
Published: April 2011

ABSTRACTIn our previous publications [1, 2 and 3], spreading resistance probe (SRP) measurements for quality control of metal induced lateral crystallization (MILC) of amorphous silicon (a-Si) were studied, and the mechanism of nickel diffusion was simulated using technology computer-aided design (TCAD) modeling.Now, we continue to present the explanation of experimental results by modeling with the Synopsys TCAD package, whereby models for resistivity vs. grain size in implanted recrystallized silicon layers are implemented and compared with experiments.Findings show that the SRP method can be used for the characterization of the MILC process of amorphous silicon and that a comparison of experimental and calculated data allows both a turn from qualitative to quantitative analysis of recrystallized silicon film and an estimate of grain size. It has been found that grain size depends on location in the MILC region and on the time and temperature of recrystallization.
Improvement in pinpin Device Architectures for Imaging Applications
Authors: Louro P. , Fantoni A. , Fernandes M. , Lavareda G. , Carvalho N. , Vieira M. 
Published: April 2011

ABSTRACTIn this paper we present results on the optimization of device architectures for colour and imaging applications, using a device with a TCO/pinpi'n'/TCO configuration. A set of different devices with different intrinsic back layers are analysed.The effect of the applied voltage on the color selectivity is discussed. Results show that the spectral response curves demonstrate rather good separation between the red, green and blue basic colors. Combining the information obtained under positive and negative applied bias a colour image is acquired without colour filters or pixel architecture. A low level image processing algorithm is used for the colour image reconstruction.
Transient current in a-Si:H-based MIS photosensors
Authors: Fernandes Miguel , Vygranenko Yuriy , Vieira Manuela , Heiler Gregory , Tredwell Timothy , Nathan Arokia 
Published: April 2011

ABSTRACTLarge-area amorphous silicon (a-Si:H) sensor arrays are widely used for medical x-ray imaging, nondestructive testing and security screening. Most of the commercially available detectors are of the indirect conversion type, in which an x-ray phosphor screen is optically coupled to an array of a-Si:H sensors. The a-Si:H PIN photodiode and the MIS photoelectric converter are two alternative sensing elements used in these detectors. The major advantage of the MIS structure over PIN is fact that this device has the same layer sequence as the a Si:H TFT switch and therefore, they can be fabricated simultaneously resulting in an effective reduction in the lithography mask count. The main disadvantage of the MIS structure is the higher noise level due to transient dark current. The transient dark current originates from traps at the semiconductor-insulator interface and i-layer bulk defects. In this work we analyze the transient current transport in segmented-gate/SiN/a Si:H/n+/ITO structures under different biasing conditions and temperatures. Using a home-made setup the dark current decay was measured within an interval of 1 second in the temperature range from 294 to 353K. It is found that the dark current component associated with charge trapping at the insulator-semiconductor interface can be largely eliminated by adjusting the bias voltage during the refresh period. Under optimized biasing conditions and elevated temperatures the bulk current component becomes dominant.
Optimized O/Si Composition Ratio for Enhancing Si Nanocrystal Based Luminescence in Si-rich SiOx Grown by PECVD with Argon Diluted SiH4
Authors: Chang Chung-Hsiang , Hsieh Chin-Hua , Chou Li-Jen , Lin Gong-Ru 
Published: April 2011

ABSTRACTEffect of O/Si composition ratio on near-infrared photoluminescence (PL) of PECVD grown Si-rich SiOx after 1100°C annealing are analyzed by Rutherford backscattering (RBS) and Fourier-transformed infrared spectroscopy (FTIR) to show nonlinear relationship with strongest PL at 760 nm at optimized O/Si = 1.24, total Si concentration of 44.6 atom.%, and N2O/SiH4 fluence ratio of 4.5. A nearly Gaussian function of the normalized PL intensity vs. O/Si composition ratio has been observed due to the significant variation on the Si nanocrystals size with the density of the excessive Si atoms.
Atomistic Understanding of a Single Gated Dopant Atom in a MOSFET
Authors: Lansbergen Gabriel , Rahman Rajib , Wellard Cameron , Caro Jaap , Collaert Nadine , Biesemans Serge , Klimeck Gerhard , Hollenberg Lloyd , Rogge Sven 
Published: April 2011

ABSTRACTCurrent semiconductor devices have been scaled to such dimensions that we need take an atomistic approach to understand their characteristics. The atomistic nature of these devices provides us with a tool to study the physics of very small ensembles of dopants right up to the limit of a single atom. Control and understanding of a dopants wavefunction and its coupling to the environment in a nanostructure could proof a key ingredient for device technology beyond-CMOS. Here, we will discuss the eigenlevels and transport characteristics a single gated As donor. The donor is incorporated in the channel of wrap-around gate transistors (FinFETs). The measured level spectrum is shown to consist of levels associated with the donors Coulomb potential, levels associated with a triangular well at the gate interface and hybridized combinations of the two. The level spectrum of this system can be well described by a NEMO-3D model, which is based on a numerical tight-binding approximation.
Suitability of 4H-SiC Homoepitaxy for the Production and Development of Power Devices
Authors: Hecht Christian , Thomas Bernd , Stein Rene , Friedrichs Peter 
Published: April 2011

ABSTRACTIn this paper, we present results of epitaxial layer deposition for production needs using our hot-wall CVD multi-wafer system VP2000HW from Epigress with a capability of processing 6×100mm wafers per run. Intra-wafer and wafer-to-wafer homogeneities of doping and thickness for full-loaded 6×100mm runs will be shown and compared to results of the former 7×3″ setup. The characteristic of the run-to-run reproducibility for the 6×100mm setup will be discussed. To demonstrate the suitability of the reactor for device production results on Schottky Barrier Diodes (SBD) processed in the multi-wafer system will be given. Furthermore, we show results for n- and p-type SiC homoepitaxial growth on 3″, 4° off-oriented substrates using a single-wafer hot-wall reactor VP508GFR from Epigress for the development of PiN-diodes with blocking voltages above 6.5 kV. Characteristics of n- and p-type epilayers and doping memory effects are discussed. 6.5 kV PiN-diodes were fabricated and electrically characterized. Results on reverse blocking behaviour, forward characteristics and drift stability will be presented.
Lateral/vertical Homoepitaxial Growth on 4H-SiC Surfaces Controlled by Dislocations
Authors: Picard Yoosuf N. , Trunek Andrew J. , Neudeck Philip G. , Twigg Mark E. 
Published: April 2011

ABSTRACTThis paper reports the influence of screw dislocations on the lateral/vertical growth behavior of chemical vapor deposited (CVD) on-axis homoepitaxial 4H-SiC films grown on patterned mesas. Electron channeling contrast imaging (ECCI) was utilized to image both atomic steps and dislocations while the film structure/orientation was determined using electron backscatter diffraction (EBSD). The presence and position of screw dislocations within the mesa impacted the resultant film thickness, lateral shape, and atomic step morphology. Mesa side walls that incline inwards due to faceting during screw-dislocation driven vertical film growth can intersect with the dislocation step sources near the side walls. If this occurs for all screw dislocations on a mesa, we observe a transition towards laterally dominated growth that produces webbed structures and films surfaces exhibiting significantly lower step densities. Transition from vertical to lateral dominated growth is consistent with ECCI imaged dislocation very near a mesa side wall.
Propagation and Density Reduction of Threading Dislocations in SiC Crystals during Sublimation Growth
Authors: Wu Ping , Xu Xueping , Rengarajan Varatharajan , Zwieback Ilya 
Published: April 2011

ABSTRACTSiC single crystal wafers grown by sublimation exhibit relatively high dislocation densities. While it is generally known that the overall dislocation density tends to decrease throughout crystal growth, there has been a limited quantitative analysis of such trend. In this study, we measured the density of threading dislocations in the wafers sliced from several SiC boules. Although the dislocation density in the wafers sliced from different boules could differ by orders of magnitude, a consistent empirical relationship was found between the dislocation density (&#961;) and the axial wafer position within the crystal (w): &#961; is proportional to w(−0.5).Monte Carlo simulations were performed based on two assumptions: (i) during growth the threading dislocations move randomly in the lateral directions, and (ii) two dislocations of opposite sign annihilate when they come within a critical distance between them. Good agreement was achieved between the model and experimental results. The critical distance determined from the simulations was in the range between a few hundred &#258; and a micron.
Effect of Base Impurity Concentration on DC Characteristics of Double Ion Implanted 4H-SiC BJTs
Authors: Tajima Taku , Uchiumi Satoshi , Tsukamoto Kenta , Takenaka Kazumasa , Satoh Masataka , Nakamura Tohru 
Published: April 2011

ABSTRACTDouble ion implanted 4H-SiC bipolar junction transistors (BJTs) are fabricated by Al and N ion implantation to the base and emitter. The current gain of 3 is obtained at the base Al concentration of 1 × ∼ 1017 /cm3. The collector current as a function of the base Gummel number suggests that double ion implanted 4H-SiC BJT operates in the intrinsic region below the emitter in the low injection level. The high base resistance restricts the base current at VBE as low as 3 V.
MOS Capacitor Characteristics of 3C-SiC Films Deposited on Si Substrates at 1270°C
Authors: Wang Li , Dimitrijev Sima , Hold Leonie , Kong Frederick , Tanner Philip , Han Jisheng , Wagner Gunter 
Published: April 2011

ABSTRACTSiC films were deposited on Si substrate by low pressure hot-wall CVD using C3H8 (5% in H2)-SiH4 (2.5% in H2)-H2 gas system at 1270°C and 1370°C. In this paper, we compare the electrical characteristics of MOS capacitors fabricated on the 3C-SiC films grown at high and low temperatures, 1370°C and 1270°C, respectively. Although the cross-sectional TEM images indicate similar micro-structural quality of the SiC/Si interface for both temperatures, a quicker elimination rate of stacking faults with increasing thickness was observed in the films grown at 1370°C. Rocking curves from XRD measurements also indicate better crystallinity of the films grown at 1370°C. On the other hand, atomic force microscopy shows that the average surface roughness reduces with the reduction in growth temperature. MOS capacitors were made on films grown at both temperatures and characterized by high-frequency capacitance-voltage (HFCV), conductance-voltage (G-V), and current-voltage (I-V) measurements at room temperature. The MOS capacitors fabricated on both films exhibit good and almost identical C-V characteristics. Measurements of current-voltage characteristics in accumulation region showed smaller leakage for the film deposited at 1270°C. It is concluded that the decrease of the deposition temperature from 1370°C to 1270°C does not bring any remarkable negative impact on the interface properties of fabricated MOS capacitors.
Modeling and Experiments of Dopant Diffusion and Defects for Laser annealed Junctions and advanced USJ
Authors: Noda Taiji , Vandervorst Wilfried , Felch Susan , Parihar Vijay , Vrancken Christa , Hoffmann Thomas Y. 
Published: April 2011

ABSTRACTLaser annealed junctions and advanced ultra shallow junctions are studied in both atomistic modeling and experiments. SIMS and sheet resistance measurement for spike-RTA + Laser annealing show that additional laser annealing after spike-RTA (“+Laser”) improve the dopant activation level without increasing in junction depth. “+Laser” effect become effective in the combination of low spike-RTA temperature and high laser temperature. This effect is significant for As doped layer. Spike-RTA based junction has a limitation in viewpoint of Rs-Xj trade-off. Laser-only annealing is promising candidate to overcome this limitation. Boron diffusion with laser-only annealing is investigated. As atomistic kinetic Monte Carlo modeling show that BnImcomplexes and End-of-Range (EOR) defects are formed during sub-millisecond annealing time range. Impact of F co-implant on Boron diffusion and EOR defect evolution during sub-millisecond annealing are also investigated.
Experimental Investigation of the Impact of Implanted Phosphorus Dose and Anneal on Dopant Diffusion and Activation in Germanium
Authors: Mazzocchi Vincent , Koffel Stéphane , Le Royer Cyrille , Scheiblin Pascal , Barnes Jean-Paul , Hopstaken Marco 
Published: April 2011

ABSTRACTGermanium has regained attention in the semiconductor industry for MOSFET application because of the higher mobility of carriers – two times higher mobility for electrons and four times for holes – as compared to silicon. In the opposite of the Silicon, the major issue with Germanium is to limit the n-dopant diffusion. Usual n-dopants (Phosphorus and Arsenic for example) are not electrically activated at an acceptable level without a large diffusion of the doping profile and a substantial dose loss. In this work, we have studied the influence of low energy and dose implant (15KeV to 40KeV @ 8E13 to 1E15at.cm−2) and low temperature anneal (515°C to 600°C) on diffusion, exodiffusion and activation of the phosphorus dopant into Germanium. The annealing steps were made in RTP furnace, the chemical profile and electrically active profiles were extracted by using Secondary-Ion-Mass Spectroscopy (SIMS) and sheet resistance measurement (Rs). To investigate the implantation-induced defects in depth, cross-sectional micrographs were made by using Transmission Electron Microscopy (TEM). Experimental results show that we achieved an efficient activation level by tuning both dose implant and anneal temperature, limiting the exodiffusion with pratically no diffusion of the dopant. We also show that very abrupt profile can be achieved with appropriate implant and thermal annealing conditions. To limit the leakage current in devices, we suppose we have to limit the defects generated during the implantation. Specially for dopant activation temperature anneal below 550°C, we have shown and observed by cross-sectional micrograph that the defects are totally removed by addition of a pre step of annealing at 400°C.
Phosphorus diffusion and activation in silicon: Process simulation based on ab initio calculations
Authors: Sahli Beat , Vollenweider Kilian , Zographos Nikolas , Zechner Christoph , Suzuki Kunihiro 
Published: April 2011

ABSTRACTWe present the results of extensive ab initio simulations for phosphorus clustering and diffusion in silicon and the application of these results in a state-of-the-art process simulator. The specific defects and the parameters that are investigated are selected according to the needs of diffusion and activation models, taking into account the availability of experimental data, the capabilities of current ab initio methods and the requirements for advanced technology development. The calculated formation energies, binding energies and migration barriers are used to determine a good starting point for the calibration of a new charged cluster model implemented in the process simulator. The defect species V, I, P, PV, PI, PI2, P2, P2V, P2I, P3, P3V, P3I and P4V are considered in all relevant charge states. The ab initio results are discussed as well as the transfer of this information into the process simulation model and the impact on model quality.