bluuebunny/crossref_metadata_2025_split huggingface dataset:
Epitaxial Growth of 3C-SiC on T-shape columnar Si Substrates
Authors: Nishino S. , Shoji A. , Nishiguchi T. , Ohshima S. 
Published: April 2011

AbstractCubic silicon carbide (3C-SiC) is a suitable semiconductor material for high temperature, high power and high frequency electronic devices, because of its wide bandgap, high electron mobility and high saturated electron drift velocity. The usage of Si substrates has the advantage of large area substrates for the growth of 3C-SiC layers. However, large lattice mismatch between 3C-SiC and Si (>20%) has caused the generation of defects such as misfit dislocations, twins, stacking faults and threading dislocations at the SiC/Si interface. Lateral epitaxial overgrowth (ELOG) of 3C-SiC on Si substrates using SiO2 has been reported to reduce the defect density. In this report, epitaxial growth of 3C-SiC on T-shape patterned (100) Si substrates has been investigated to reduce interfacial defects.
Status of 4H-SiC Substrate and Epitaxial Materials for Commercial Power Applications
Authors: Powell A.R. , Sumakeris J.J. , Leonard R.T. , Brady M.F. , Müller St.G. , Tsvetkov V.F. , Hobgood H.McD , Burk A.A. , Paisley M.J. , Glass R.C. , Carter C.H. 
Published: April 2011

AbstractThe performance enhancements offered by the next generation of SiC high power devices offer potential for enormous growth in SiC power device markets in the next few years. For this growth to occur, it is imperative that substrate and epitaxial material quality increases to meet the needs of the targeted applications. We will discuss the status and requirements for SiC substrates and epitaxial material for power devices such as Schottky and PiN diodes. For the SiC Schottky device where current production is approaching 50 amp devices, there are several material aspects that are key. These include; wafer diameter (3-inch and 100-mm), micropipe density (<0.3 cm−2 for 3-inch substrates and 16 cm−2 for 100-mm substrates), epitaxial defect densities (total electrically active defects <1.5 cm−2), epitaxial doping and epitaxial thickness uniformity. For the PiN diodes the major challenge is the degradation of the Vf characteristics due to the introduction of stacking faults during the device operation. We have demonstrated that the stacking faults are often generated from basal plane dislocations in the active region of the device. Additionally we have demonstrated that by reducing the basal plane dislocation density, stable PiN diodes can be produced. At present typical basal plane dislocation densities in our epitaxial layers are 100 to 500 cm−2; however, we have achieved basal plane dislocation densities as low as 4 cm−2 in epitaxial layers grown on 8° off-axis 4H-SiC substrates.
The Effect of Doping Concentration and Conductivity Type on Preferential Etching of 4H-SiC by Molten KOH
Authors: Gao Ying , Zhang Zehong , Bondokov Robert , Soloviev Stanislav , Sudarshan Tangali 
Published: April 2011

AbstractMolten KOH etchings were implemented to delineate structural defects in the n- and ptype 4H-SiC samples with different doping concentrations. It was observed that the etch preference is significantly influenced by both the doping concentrations and the conductivity types. The p-type Si-face 4H-SiC substrate has the most preferential etching property, while it is least for n+ samples. It has been clearly demonstrated that the molten KOH etching process involves both chemical and electrochemical processes, during which isotropic etching and preferential etching are competitive. The n+ 4H-SiC substrate was overcompensated via thermal diffusion of boron to p-type and followed by molten KOH etching. Three kinds of etch pits corresponding to threading screw, threading edge, and basal plane dislocations are distinguishably revealed. The same approach was also successfully employed in delineating structural defects in (0001) C-face SiC wafers.
Room-temperature Photoluminescence at 1540 nm from Amorphous Silicon Carbide Films Implanted with Erbium
Authors: Gallis Spyros , Efstathiadis Harry , Huang Mengbing , Kaloyeros Alain E. , Nyein Ei Ei , Hommerich Uwe 
Published: April 2011

AbstractIn the present work, strong room-temperature photoluminescence (PL) at 1540 nm is reported from erbium-implanted and post-annealed amorphous silicon carbide (a-SiC:Er) films. The stoichiometric SiC films were grown by thermal chemical vapor deposition (TCVD) at 800°C, and then implanted to Er fluence of 3×1015 ions/cm2 using 380 keV implantation energy. Post-implantation annealing was carried out at the temperature range of 550°C to 1350°C in argon (Ar) ambient. The resulting SiC films were characterized by Auger electron spectroscopy (AES), Rutherford backscattering (RBS), Fourier transform infrared spectroscopy (FTIR), nuclear reaction analysis (NRA), x-ray diffraction (XRD), and high-resolution transmission electron microscope (HRTEM). Clear PL behavior was seen from the annealed a-SiC:Er samples, even at room temperature, with PL intensity reaching a maximum for samples annealed at 900°C.Additional studies of thermal quenching of Er luminescence from a-SiC:Er samples annealed at 900°C indicated that as the sample temperature increased from 14K to room temperature, the luminescence intensity at 1540 nm dropped by a factor of ∼ 3.6. Moreover, the PL spectra of the a-SiC:Er samples did not exhibit any defect-generated luminescence. It is suggested that the lower density of Si and C vacancies in the stoichiometric a-SiC:Er, as compared to its non-stoichiometric a-Si1-xCx counterpart, along with the incorporation of a higher Er dopant concentration, can effectively diminish defect-produced luminescence and lead to a significant improvement in PL performance.These properties suggest that stoichiometric a-SiC:Er may be a good candidate for producing optoelectronic devices operating in the 1540 nm region.
Morphology-Controlled Synthesis of Nanostructured Silicon Carbide
Authors: Guo Xiang-Yun , Jin Guo-Qiang , Hao Ya-Juan 
Published: April 2011

AbstractPhenolic resin and tetraethoxysilane were used to prepare a binary carbonaceous silicon xerogel, the precursor of silicon carbide (SiC). By employing different additives in the sol-gel process, a series of xerogel precursors with differently chemical composition were obtained. Heating these xerogels to 1250°C, nanostructured β-SiC with various morphologies including nanowires, nanofibers, nanoparticles and mesoporous SiC were produced via carbothermal reduction. The preparation method of the xerogels was presented and the influences of different additives on the sol-gel process and the SiC formation were discussed in this paper.
Fabrication and Initial Characterization of 600 V 4H-SiC RESURF-type JFETs
Authors: Hatsukawa Satoshi , Iiyama Michitomo , Fujikawa Kazuhiro , Ito Atsushi 
Published: April 2011

AbstractA RESURF-type JFET is a suitable structure as a lateral switching device with a breakdown voltage of above 600 V for an inverter module which drives motors of an electric or hybrid automobile. In this study, 600 V RESURF-type JFETs were fabricated to investigate the operation and characteristics. The drift region between the drain and the source areas has a double RESURF structure to reduce the on-resistance. At first, small devices were fabricated. The width and length of the channel are 200 μm and 10 μm, respectively. The distance between the drain and the gate areas, which is the drift length, is 15 μm. The saturation current normally-off device is about 0.6 mA at a gate voltage of 3 V. The specific on-resistance is about 160mωcm2. The maximum breakdown voltage is 720 V. Next, large ones were fabricated. The width of the channel is 80 mm. The saturation current normally-on device is about 0.5 A at a gate voltage of 2 V. The specific on-resistance is about 200mωcm2. The maximum breakdown voltage is 250 V.
The interaction of C60 with Si(111) and Co/Si(111)
Authors: Zilani M.A.K. , Xu H. , Wang X.S. , Wee A.T.S. 
Published: April 2011

AbstractWe have studied the interaction of C60 with clean Si(111) and sub-monolayer Co covered Si(111) using scanning tunneling microscopy (STM) and X-ray photoelectron spectroscopy (XPS). Our STM results indicate that C60 has little mobility at room temperature (RT) on Co/Si(111). After annealing to 450 °C, STM images show a regular arrangement of partially decomposed C60. XPS reveals a partial decomposition of C60 on Co/Si(111) at 520 °C, and total decomposition to form a SiC-3×3 phase at 720 °C. These results show that Co catalyses C60 decomposition resulting in the formation of the ordered SiC-3×3 phase ∼200 °C below that on clean Si(111).
Study by Weak Beam and HRTEM of double stacking faults created by external mechanical stress in 4H-SiC
Authors: Idrissi Hosni , Lancin Maryse , Douin Joel , Regula Gabrielle , Pichaud Bernard , Bouayadi Rachid El , Rousse Jean-Marc 
Published: April 2011

Abstract4H-SiC samples are bent in compression mode at 550°C and 620°C. The introduced-defects are identified by Weak Beam and HRTEM techniques. They consist of double stacking faults bounded by 30° Si(g) partial dislocations whose glide locally transforms the material in its cubic phase. The velocity of partial dislocations is measured after chemical etching of the sample surface. The formation and the expansion of the double stacking faults are discussed.
Investigation of the influence of different copper slurry systems on post CMP topography performance
Authors: Springer Goetz , Thieme Peter , Klose Pierre 
Published: April 2011

AbstractSince the early days of copper CMP much research and development effort was put into formulation of new copper and barrier CMP slurries. Two major motivations for this effort are the improvement of process performance for currently used integration schemes and the preparation for new integration schemes using low-k and ultra low-k dielectric materials. In this paper a systematic procedure for topography investigation after copper and barrier CMP is presented. The procedure is applied to four different copper slurries in order to compare after copper and after barrier CMP topography performance. As a result of the post copper CMP topography investigations, a discussion of advantages and disadvantages of non-selective and selective barrier polish processes will be presented. To complete the discussion of potential topography correction during barrier CMP, an investigation of an observed pronounced dielectric erosion close to large metal features or within high metal density arrays with medium or high selective barrier CMP processes will be presented.
Novel Pure Organic Particles for Copper CMP at Low Down Force
Authors: Cheemalapati K. , Chowdhury A. , Duvvuru V. , Lin Yong , Tang Kwok , Bian Guomin , Yao Lily , Li Yuzhuo 
Published: April 2011

AbstractIt is generally accepted that there is a minimum hardness requirement for abrasive particles to be used in CMP (Chemical Mechanical Polishing) slurries. For copper CMP, the common abrasives are various types of alumina and silica. It has also long been suspected that a softer organic based abrasive could significant reduce the defects during polishing. In this study, for the first time, we demonstrated the usefulness of an organic particle as abrasive in formulating copper CMP slurry. The unexpected consequence of using such soft hydrophilic particles is its low sensitivity of material removal rate for copper towards polishing down force and platen speed. In addition, due to its unique particle surface properties, the slurry gives high selectivity in removal rate for copper over barrier, cap, and dielectric materials. In this paper, some basic physical and chemical characteristics of the particles and slurry will be first presented. The performance of this new slurry in relation to conventional slurries on blanket and patterned wafers will be discussed.
Effect of Nano-Size Silica Abrasives in Chemical Mechanical Polishing of Copper
Authors: Jung Su-Ho , Singh Rajiv K. 
Published: April 2011

AbstractThe effect of nano-size silica abrasives in chemical mechanical polishing (CMP) of copper is studied in order to reduce mechanical stresses during polishing, which may minimize defects such as surface scratches, copper peeling, dishing and erosion. In order to achieve low stress polishing of copper while maintaining removal rate efficiency, the formation of chemically modified surface layer, which can be mechanically removed by small size and low hardness abrasives, is critical. Complexing agents play an important role in the formation of a removable surface layer in the presence of the oxidizer, which is responsible for oxide formation, and the inhibitor, which passivates the surface. A new removal mechanism is proposed by correlating results of surface roughness after polishing with removal and etch rates. The effects of large silica and alumina abrasives, ranging from 200-1000 nm in diameter, are also studied to compare the different removal mechanisms.
A Model of Cu-CMP
Authors: Paul Ed , Brusic Vlasta , Sun Fred , Zhang Jian , Vacassy Robert , Kaufman Frank 
Published: April 2011

AbstractCMP has been described qualitatively in terms of alternating cycles of chemical formation and mechanical removal of a thin layer on the wafer surface. A quantitative model of CMP has been developed2-7 which is based on mechanisms for surface kinetics, treating mechanical removal as one step in the mechanism. This model has been used successfully to explain removal rates for tungsten and thermal oxide CMP. In particular, for tungsten CMP the removal rate increases steeply with increasing oxidizer concentration at low concentrations, and then approaches an asymptotic maximum removal rate at high concentrations. The model explains this by starting with the assumption that mechanical abrasion removes only tungsten oxide but not tungsten metal. It then focuses on the fraction of wafer surface covered by a tungsten oxide layer. At low oxidizer concentrations, the oxide formation rate is small compared the removal rate, so only a small fraction of the surface is oxidized and the removal rate is small. At high oxidizer concentrations, the oxide formation rate is large compared to the removal rate, so most of the surface is oxidized and the removal rate is large. Increasing the oxidizer concentration in the high oxidizer concentration region does not significantly increase the surface fraction of tungsten oxide, and the removal rate approaches a constant value.
Polish profile control using magnetic control head
Authors: Tsujimura Manabu , Ishii Yu , Kimura Norio , Ota Masahiro 
Published: April 2011

AbstractMagnetic bearing technology is widely used in various technical fields, and is particularly appreciated in the semiconductor industry, where it is applied to the turbo molecular pump and wafer transfer system due to the excellent controllability it provides, even at speeds as high as 50,000 rpm. This report discusses the adoption of magnetic bearing technology to control the wafer carrier tilt angle during polishing. When the wafer is polished on a viscoelastic pad, the wafer carrier is inclined and pressed into the pad. Therefore, the reaction force on the wafer from the pad is concentrated at the wafer edge, increasing the polish rate at the edge relative to the rest of the wafer. Modification of the tilt angle is thought to offer a possible means of normalizing the distribution of the reaction force from the pad and correcting the nonuniformity of the polish rate. The wafer carrier was confirmed to press slightly into the pad and to be tilted 18 × 10-5 rad by the viscoelasticity of the pad (without tilt angle control). Constant current control led to better control of the polish rate profile relative to feedback control. The polish rate in the outer area of the wafer was increased by tilting the carrier to the positive side, and the polish rate of the wafer center area could be reduced by tilting it to the negative side. The best profile was obtained with control current of Im = -0.4 A. When the wafer carrier was tilted in the reverse direction, the polish rate became almost zero. It was concluded that hydro-planing occurred between the wafer and the pad. Accordingly, this report demonstrates the possibility of improving the polish rate profile by maintaining the wafer carrier in a horizontal position using magnetic control.
Modeling of Pattern Density Dependent Pressure Non-Uniformity at a Die Scale for ILD Chemical Mechanical Planarization
Authors: Choi Jihong , Dornfeld David A. 
Published: April 2011

AbstractLocal material removal rate is inversely proportional to the local pattern density in ILD CMP. With the assumption that the local velocity and Preston coefficient are constant across a chip, local MRR non-uniformity is mainly attributed to the local pressure non-uniformity. Pressure distributions on two different test patterns consisting of five different pattern density sections were obtained with a finite element model. These pressure distributions were compared with output from a semi-empirical pattern dependent oxide CMP model (MIT model) with three different weighting functions. Result showed that pressure distribution could be well approximated with the pattern density dependent oxide CMP model. This FEM model was further taken to evaluate the effects of thickness and material properties of each layer on the degree of pattern dependant pressure non-uniformity at a die scale for a typical polishing pad made up of a hard and a soft layer. The analysis shows that the degree of pressure nonuniformity at a die scale increases with the combination of a stiff hard layer and a thick soft layer, while it decreases with the combination of a stiff soft layer and a thick hard layer.
Advances in the CMP Process on Fixed Abrasive Pads for the Polishing of SOISubstrates with High Degree of Flatness
Authors: Kulawski Martin , Luoto Hannu , Henttinen Kimmo , Suni Ilkka , Weimar Frauke , Mäkinen Jari 
Published: April 2011

AbstractThe new approach using Fixed Abrasive (FA) pads for polishing thick film Silicon-on- Insulator (SOI) wafers after bonding and grinding process [1] has been further developed. The aim is a practicable industrial manufacturing process, where the major specifications especially in long term stability and removal rate should be achieved. In base line studies a stable removal rate on suitable level has been reached, while the degeneration of the total thickness variation (TTV) was limited to a clearly smaller value than that being typical for the standard stock removal polishing. The overall removal in these tests was adjusted to 2-3 μm, which removes all sub surface damage (SSD) from wafers ground by ultra fine grinding wheels with very small average abrasive particle size. The process has been able to remove all visible grindlines after removing less than 1.5 μm. In another test with a further developed high density FA pad, removal rates up to ∼0.6 μm/min were achieved. The polished samples were further processed and characterized by capacitive thickness measurements gauges, optical surface inspection tool (“Magic mirror”), atomic force microscopy (AFM) and optical reflection measurements.
Pad Asperity Parameters for CMP Process Simulation
Authors: Yoshida Takafumi 
Published: April 2011

AbstractThis paper reviews the contact mechanics between the surface of a wafer and the asperity of the polishing pad for CMP from basic asperity such as spherical, rectangular, and conical shapes to more general asperity with a height distribution. This paper also proposes a practical method to bridge a measured profile of pad asperity in microscopic scale to a set of simple parameters which describe the elastic behavior for CMP process simulation in larger scale. We show a scalable CMP simulation using the proposed pad asperity parameters.
Assessment of Planarization length variation by the Step-Polish-Response (SPR) Method
Authors: Bartha Johann. W. , Bormann Tilo , Estel Kathrin , Zeidler Dieter 
Published: April 2011

AbstractIn spite of the fact, that the main purpose of CMP is the planarization of surfaces, most processes are optimized with respect to the removal rate. This might be due to a lack in techniques for the determination of the planarization behavior. The commonly used expression “Planarization Length” implies a maximum lateral extension over which the planarization is obtained and which can not be improved. Several attempts have been made to determine the planarization length by studying the CMP on different test patterns. The general problem in the interpretation of the data is the interaction of neighboring pattern with different pattern densities. This problem does not apply to the most simple pattern possible, which is a single step with an extension of the up and down areas much larger than the planarization length. In this case the spatial derivative of the resulting contour after CMP is directly the demanding transfer function to be used for the convolution. This concept, initially proposed by Boning et. al., was applied to evaluate the polish of copper and silicon oxide. Wafers with concentrically steps in Cu or SiO2 films with an extension of 1 to 5 cm have been prepared. During polish, the initially infinite steep step widens up, yielding the planarization length as a function of the removal respective the polishing time. Significant differences in the evaluation of the planarization length could be quantified depending on the pad, slurry and tool parameters. Our first experiments revealed a decrease in planarization length by the addition of BTA in a copper slurry. We believe that the SPR method enables a unambiguous, pattern independent determination of the planarization capability in CMP.
Quantum confinement effect of silicon nanocrystals in situ grown in silicon nitride films
Authors: Kim Tae-Youb , Park Nae-Man , Kim Kyung-Hyun , Ok Young-Woo , Seong Tae-Yeon , Choi CheolJong , Sung Gun Yong 
Published: April 2011

AbstractSilicon nanocrystals were in situ grown in a silicon nitride film by plasma enhanced chemical vapor deposition. The size and structure of silicon nanocrystals were confirmed by high-resolution transmission electron microscopy. Depending on the size, the photoluminescence of silicon nanocrystals can be tuned from the near infrared (1.38 eV) to the ultraviolet (3.02 eV). The fitted photoluminescence peak energy as E(eV) = 1.16 + 11.8/d2 is an evidence for the quantum confinement effect in silicon nanocrystals. The results demonstrate that the band gap of silicon nanocrystals embedded in silicon nitride matrix was more effectively controlled for a wide range of luminescent wavelengths.
Electro-Optical Properties of Na0.5K0.5NbO3Films on Si by Free-Space Coupling Technique
Authors: Grishin Alexander M. , Khartsev Sergey I. 
Published: April 2011

AbstractWe report electro-optic performance of highly polar axis oriented Na0.5K0.5NbO3(NKN) films grown directly on Pt(100nm)/Ti(10nm)/SiO2/Si(001) substrates by rf-magnetron sputtering. Semitransparent gold electrodes (diameter Ø= 2 mm) were deposited ontop the NKN films by a thermal evaporation through the contact mask. Processing parameters have been specially optimized to obtain “electrosoft” NKN films with a non-linear fatigue-free P-E characteristics: low remnant Pr = 3.6 μC/cm2 and high induced polarization P = 26 μC/cm2 @ 522 kV/cm, and the coercive field Ec= 39 kV/cm. Electro-optical characterization of NKN/Pt/Si films has been performed using waveguide refractometry: a free-space coupling of a light beam into the thin-film waveguide modes. Intensity of TM- andTE-polarized light of 670 nm laser diode reflected from the free surface of NKN film and Au-cladding NKN/Pt/Si waveguide was recorded at zero and 30 V (100 kV/cm) bias electric field. Extraordinary and ordinary refractive indices as well as electro-optic coefficient have been determined by fitting these experimental data to the Fresnel formulas. Applying 160 V (530 kV/cm) across the parallel plate NKN capacitor (Ø= 2 mm, thickness 3 μm), modulation of the reflected light as high as 40% was achieved.