bluuebunny/crossref_metadata_2025_split huggingface dataset:
Low Temperature Growth of CIGS Thin Films for Flexible Solar Cells
Authors: Rudmann D. , Haug F.-J. , Kaelin M. , Zogg H. , Tiwari A.N. , Bilger G. 
Published: April 2011

ABSTRACTLow substrate temperatures have to be used for polymer substrates. Therefore, using soda- lime glass (SLG) substrates with and without an alkali barrier (Al2O3), a three-step CIGS coevaporation process for a substrate temperature of 450 °C has been developed and compared to film deposition with constant evaporation rates. The three-step process was found to enhance grain nucleation. An efficiency of 14.0 % has been achieved with this process for solar cells on SLG. Since polymers in general do not contain Na, a way of Na addition to the absorber is needed. It is shown that NaF coevaporation can be used to control the Na content in CIGS. Also incorporation of Na in CIGS by diffusion from a NaCl layer through a polyimide is demonstrated. With such SLG/NaCl/polyimide structures flexible solar cells can be obtained using a lift-off process. A cell efficiency of 11.6 % (0.99 cm2 area) has been achieved.
Structural and Electronic Properties of Polycrystalline Cu(In,Ga)(S,Se)2 Alloys
Authors: Kötschau I. M. , Turcu M. , Rau U. , Schock H. W. 
Published: April 2011

ABSTRACTWe present a systematic study on the polycrystalline Cu(In,Ga)(S,Se)2 alloys with a gallium to indium ratio of Ga/(Ga+In)<0.3 and a sulfur to selenium ratio varying in the range between 0<S/(S+Se)<1. All samples were grown by coevaporation of the elements at constant rates under high vacuum conditions. The formation of island-like (Cu,S,Se) segregations correlate with the sulfur to selenium ratio in the layer and are found in the growth region near the copper rich phase boundary. These segregations are related to a preferred incorporation of sulfur in the copper rich growth mode. We obtain solar cell grade material from an indium rich growth mode up to a sulfur to selenium ratio of S/(S+Se)=0.9. A detailed analysis of the electronic and optical properties of Mo/CIGSSe/CdS/ZnO:Al heterojunctions allows us to determine the energetic position of the bands within the Cu(In,Ga)(S,Se)2 alloy system. We find that contrary to the Cu(In,Ga)(Se)2 alloy system the valence band position is significantly lowered with increasing bandgap.
Impedance Spectroscopy and Hall Measurements on CdTe Thin Polycrystalline Films
Authors: Gilmore A.S. , Kaydanov V. , Ohno T.R. , Grecu D. , Rose D. 
Published: April 2011

ABSTRACTMeasurements of film impedance in a wide frequency range (impedance spectroscopy, IS) were used to evaluate the grain boundary (GB) and the bulk material (B) resistance. Undoped films demonstrated very low carrier concentration and negligible GB resistance, both due to depletion of the bulk material by the GB deep states. Doping the film with Cu led to a significant increase in the GB resistance, in addition to the expected increase in carrier concentration. Illumination of doped films reduced GB resistance by orders of magnitude. This effect was used for the analysis of Hall concentration and Hall mobility data, aimed at exclusion of GB influence on measured parameters, and was used to determine the carrier concentration and mobility in the grain bulk. Hall studies on undoped films under illumination were also used to estimate the lifetime of the photogenerated carriers.
Solar Cells Based on PVD Grown CuGaSe2 – Absorber and Device Properties
Authors: Schuler S. , Nishiwaki S. , Dziedzina M. , Klenk R. , Siebentritt S. , Lux-Steiner M.Ch. 
Published: April 2011

ABSTRACTFor solar cells based on CuGaSe2(CGS) absorber layers physical vapour deposition (PVD) was employed to deposit polycrystalline CGS thin films. Efficiencies up to 7.9% were achieved by applying a two-stage deposition process for absorber preparation. The high structural quality of the absorbers is shown. For highest cell efficiencies our standard recipe for the CdS buffer deposition had to be re-adapted. Voltage dependent spectral response measurements of the device in conjunction with absorption measurements of the absorber layers allow calculation of the minority carrier diffusion length, space charge region (SCR) width, absorber carrier concentration and the built-in voltage. The defect state density at the buffer/absorber interface is estimated. It can be shown that the benefical effect of the modified buffer deposition is mainly due to a reduced acceptor concentration at the absorber/buffer interface.
Challenges in Integrating the High-K Gate Dielectric Film to the Conventional Cmos Process Flow
Authors: Agarwal Avinash , Freiler Michael , Lysaght Pat , Perrymore Loyd , Bergmann Renate , Sparks Chris , Bowers Bill , Barnett Joel , Riley Deborah , Kim Yudong , Nguyen Billy , Bersuker Gennadi , Shero Eric , Lim Jae E. , Lin Steven , Chen Jerry , Murto Robert W. , Huff Howard R. 
Published: April 2011

ABSTRACTZrO2 and HfO2 and their alloys with SiO2 are currently among the leading high-k materials for replacing SiOxNy as the gate dielectric for the sub-100 nm technology nodes. International SEMATECH (ISMT) is currently investigating integration issues associated with this required change in materials. Our work has focused on the integration of ALCVD deposited ZrO2 and HfO2 with an industry standard conventional MOSFET process flow with poly-Si electrode. Since the impact of contamination by these new high-k materials introduced in a production fab has not yet been established, it becomes very critical to prevent cross- contamination through the process tools in the fab. A baseline study was completed within ISMT's fab and appropriate protocols for handling high-k materials have been established. The integrated high-k gate stack in a conventional transistor flow should not only meet all the performance requirements of scaled transistors, but the gate dielectric film should be able withstand high-temperature anneal steps. Reactions between ZrO2 and Si have been observed at temperatures as low as 560°C (during the amorphous Si deposition process). Various wet chemistries were also evaluated for removing the high-k film inadvertently deposited on wafer backside, and it was found that ZrO2 etches at extremely slow rates in the majority of the common wet etch chemistries available in a fab. A new hot HF based process was found to be successful in lowering Zr contamination on the wafer backside to as low as 1.8 E10 atoms/cm2. The patterning of a high-k gate stack with poly-Si electrode is another area that required considerable focus. Various dry (plasma) etch and wet etch chemistries were evaluated for etching ZrO2 using both blanket films as well as wafers with patterned poly-Si gate over the high-k films. On the full CMOS flow device wafers, most of these wet chemistries resulted in severe pitting in the ZrO2 film remaining over the source/drain (S/D) areas, as well as in the Si substrate and the field oxide. A poly-Si gate over ZrO2 gate dielectric film was successfully patterned using the standard poly-Si gate etch (Cl2/HBr) for the main etch, followed by a combination of HF and H2SO4 clean for removing all of the ZrO2 remaining over the S/D area. This allowed the fabrication of low-resistance contacts to transistor S/D areas, which ultimately resulted in demonstration of functional transistors with high-k gate dielectric films.
Atomic Scale Nitridation of Silicon Oxide Surfaces by Remote-Plasma-Excited Nitrogen
Authors: Saito Yoji , Tokuda Koichi 
Published: April 2011

ABSTRACTWe have incorporated several percent of nitrogen only near the top surfaces of thermally grown oxides by exposure to fluorine gas at room temperature followed by an atomic nitrogen treatment at 550°C. The depth profiles and the bonding of incorporated nitrogen atoms have been studied by angle-resolved x-ray photoelectron spectroscopy.MOS devices were fabricated using the nitrided oxide with boron doped polycrystalline silicon gate. From the capacitance-voltage measurements we confirmed that the nitrided oxide would prevent the boron penetration in comparison with the conventional oxide films. The proposed technique identifies a unique process for obtaining high quality ultrathin dielectrics.
Influence of Film/Substrate Interface Structure on Plasticity in Metal Thin Films
Authors: Dehm G. , Inkson B.J. , Balk T.J. , Wagner T. , Arzt E. 
Published: April 2011

ABSTRACTIn-situ transmission electron microscopy studies of metal thin films on substrates indicate that dislocation motion is influenced by the structure of the film/substrate interface. For Cu films grown on silicon substrates coated with anamorphousSiNxdiffusion barrier, the transmission electron microscopy studies reveal that dislocations are pulled towards the interface, where their contrast finally disappears. However, in epitaxial Al films deposited on single-crystalline α- Al2O3substrates, threading dislocations advance through the layer and deposit dislocation segments adjacent to the interface. In this latter case, the interface is between twocrystallinelattices. Stresses in epitaxial Al films and polycrystalline Cu films were determined by substrate- curvature measurements. It was found that, unlike the polycrystalline Cu films, the flow stresses in the epitaxial Al films are in agreement with a dislocation-based model.
Thickness-fringe Contrast Analysis of Defects in GaN
Authors: Farrer Jeffrey K. , Carter C. Barry , Mao Z. , McKernan Stuart 
Published: April 2011

ABSTRACTThe analysis of thickness-fringe contrast in weak-beam transmission electron microscope (TEM) images has been shown to be a reliable method for the complete determination of the character, as well as the magnitude, of a dislocation Burgers vector. By selecting multiple diffraction conditions and, for each condition, determining the number of terminating thickness fringes at the exit of a dislocation from a wedge-shaped sample, the Burgers vector can be unambiguously determined. Defect analysis of GaN pyramids grown on (111)Si by the lateral epitactic overgrowth (LEO) technique reveals a core region which contains a relatively high density of dislocations and a lateral-growth region where the defect density is decreased. The thickness-fringe contrast technique was used in the lateral growth regions of the pyramids to analyze the dislocation Burgers vectors.
Dislocations in thin metal films observed with X-ray diffraction
Authors: Seijbel Léon J. , Delhez Rob 
Published: April 2011

ABSTRACTX-ray diffraction has been used to measure the stress, the crystallite size and the dislocation distribution in thin metal layers. By measuring two orders of a reflection, the contribution of the size distribution to the diffraction line broadening can be eliminated. A model equation is fitted to the strain Fourier coefficients of the diffraction line from which the dislocation arrangement can be obtained. For untextured nickel on steel or on silicon the dislocation densities have been obtained. It is demonstrated that for highly textured layers more information can be obtained than for untextured layers. It was found that a heated molybdenum layer on oxidized silicon showed only inclined screw dislocations.
Integration of Materials and Device Research Enabled by Wafer Bonding and Layer Transfer
Authors: Tong Q.-Y. 
Published: April 2011

ABSTRACTWafer bonding and layer transfer technology has emerged as a versatile approach for integrated research and development of materials and devices. It does not only provide a flexible way to prepare integrated materials but also breaks the barrier between materials science and device engineering since it appears to be one of the fundamental technologies for 3-D device fabrication and for integration of partially or fully processed dissimilar functional layers. The device performance can be significantly enhanced when both sides of device layers can be processed such as in the double gate CMOS and in HBTs. The processed device layers can be considered as unique materials layers and can also be integrated. The integration of dissimilar integrated circuits provides a promising solution to realize micro-systems or system on a 3-D chip in which multi-functional layers are interconnected (3-D SOC). The main issues are to develop methods that form strong bond between required materials at low temperatures and to cut the device layer without compromising the device integrity by using VLSI compatible processes. The advances in low temperature bonding of hydrophilic and hydrophobic silicon, compound semiconductors and other materials in ambient are reviewed, and application examples are discussed.
TEM measurement of hydrogen pressure within a platelet
Authors: Grisolia J. , Assayag G. Ben , de Mauduit B. , Claverie A. , Kroon R.E. , Neethling J.H. 
Published: April 2011

ABSTRACTProton implantation and thermal annealing of silicon result in the formation of a specific type of extended defect involving hydrogen, named “platelets”. These defects have been related to the exfoliation mechanism on which a newly developed process to transfer thin films of silicon onto various substrates is based. In a previous paper, we have shown that these platelets undergo a quasi-conservative Ostwald ripening upon annealing. The measurement of the pressure within such pressurised gas-filled cavities is important to understand and simulate both the growth of these defects and the exfoliation mechanism. To extract this pressure from TEM studies, we have developed and tested an analogy between the platelets and a well-known 2D defect: a dislocation loop. The comparison between simulations of the image of the strain field surrounding a fictitious dislocation loop and experimental TEM images of the platelets shows that the platelets can be described by a Burgers vector of about 0.6nm. Moreover, this vector can be used to deduce the pressure of the molecular hydrogen within a platelet. A typical value of 10 GPa is found for a platelet of 20 nm in diameter at room temperature. Consequently, the atomic density of hydrogen within a platelet and the total number of hydrogen trapped by a population of platelet can be calculated and give reasonable values when compared to the implanted dose.
Thermomechanical stress in silicon on quartz wafer bonding and Smart Cut® process
Authors: Chao Yu-Lin , Tong Qin-Yi , Gösele Ulrich M. 
Published: April 2011

ABSTRACTThe thermal stress behavior of silicon/quartz bonded wafer pairs is examined. Sliding, debonding, and cracking are the observed mechanisms of relaxation. When the elastic energy due to the different thermal expansion coefficients of silicon and quartz exceeds the bonding energy, sliding will start and lead to a serrated curve on the curvature-versus-temperature graph. Finally, debonding will occur once the peeling stress exceeds the interface bonding strength. The debonded parts crack due to the overhang structure, and debonding-cracking processes continue during a further temperature increase. The stress behavior of the hydrogen-implantation induced layer splitting process (the so-called “Smart-Cut process”) of silicon/quartz pairs is also monitored in a stress measurement setup. It is observed that Smart-Cut process is a sudden process in agreement with the observations reported in the literature.
Characterization of Optical Lifetime in Silicon-on-Insulator Wafers by Photoluminescence Decay Method
Authors: Ibuka Shigeo , Tajima Michio , Ogura Atsushi 
Published: April 2011

ABSTRACTWe report observation of temporal decay of luminescence due to electron-hole condensation in silicon-on-insulator (SOI) wafers. The condensate luminescence was observable in SOI wafers under ultraviolet light excitation, because of shallow penetration depth of the light and confinement of photo-excited carriers in the top-Si layer. We found that the temporal decay of the luminescence depended on the surface/interface condition and fabrication method. These findings can be explained by the difference in the recombination process via surface, interface and defect states in the top-Si layer. We propose that the decay measurement of the condensate luminescence has great potential for characterization of SOI wafers.
Effect of Excimer Laser Annealing on Ultra-low Temperature Gate Dielectrics
Authors: Chung Wonsuk , Thompson Michael O. 
Published: April 2011

AbstractThe effect of excimer laser annealing on the properties of ultra-low temperature (150°C) plasma enhanced chemical vapor deposited (PECVD) oxides was investigated. Annealing was performed using a 308 nm excimer laser incident directly on the oxides, at fluences up to the melting of the silicon and for as many as 3000 pulses. Following multiple shot irradiations below the silicon melt threshold, the CV threshold voltage was observed to decrease by ≍15V volts, coupled with an increase in the slope near threshold. Leakage currents measured by IV were not significantly changed. Property modifications are shown to be comparable to a 450°C thermal soak anneal. These results suggest that excimer laser annealing has potential to improve ultra-low temperature gate dielectrics for poly-Si Thin Film Transistors (TFTs) on plastic substrates.
Double-Gated Singly-Addressable Polysilicon Tip Array Fabrication and Characterization
Authors: Chubun N.N. , Chakhovskoi A.G. , Hajra M. , Hunt C.E. 
Published: April 2011

AbstractPolysilicon-on-insulator singly-addressable arrays, consisting of double-gated field emission cells, were fabricated and tested. The field-emission tips were formed by a subtractive technique, using 2.5 µm thick polysilicon stripes on an insulating substrate. The tip structure was oxidized for dielectric isolation and coated with a 0.4 µm polysilicon layer as a first gate electrode. The polysilicon layer was then subsequently oxidized to provide a second isolation layer for separation from a 0.1 µm gold film, deposited as a second gate electrode. Finally, the 1.5 µm aperture was formed, combining wet etching of the silicon dioxide and dry etching of the polysilicon layers. The matrix allows addressing electrically any emission cell at the intersection of a cathode column and an extracting gate line. An independent voltage can be applied to the second gate during operation to focus the electron beam of an operating tip.
A Novel Poly-Si TFT in Line-Crossover with High Aperture Ratio and Small Signal Delay of AMLCD Panel
Authors: Park Jin-Woo , Song In-Hyuk , Park Kee-Chan , Jung Sang-Hoon , Han Min-Koo 
Published: April 2011

AbstractWe have proposed and fabricated a novel poly-Si TFT that is integrated into the gate-data line-crossover in order to increase aperture ratio and to decrease signal delay of AMLCD panel and electrical characteristics of TFT integrated into gate-data line-crossover almost are identical to conventional TFT. The aperture ratio of AMLCD panel was increased considerably because the TFT was located under the opaque metal line. We employed a low dielectric air-gap between the gate-data line crossover, which reduced a capacitance between the gate and data lines so that the RC signal delay of the data line is decreased significantly. Our experimental result shows that the fabricated TFT was successfully operated and the proposed structure found to reduce the RC signal delay has been reduced by factor of 9 compared with conventional AMLCD panel that employs SiO2 for insulator between gate and data lines.
The Effect of Sputtering Gas on the Materials and Electrical Characteristics of p-Si Films Formed by DC Magnetron Sputtering
Authors: Voutsas A.T. 
Published: April 2011

AbstractIn this work we will discuss the feasibility of sputtered-Si as a precursor for low-temperature p-Si films. We used DC sputtering to deposit thin Si films (30-100nm) that were subsequently crystallized by excimer-laser annealing using XeCl (308nm) irradiation. The as-deposited films were sputtered with different gases including Ar, He and Ar-He mixtures. As expected, He sputtering led to less dense films that Ar. However, the plasma voltage (during deposition) was also lower in these cases. It was found that mixing of Ar and He gases within an appropriate ratio range produced sputtered films with good optical properties, at much lower plasma voltages that Ar alone. The lower voltage application could be beneficial from the point of view of reducing microarcing and allowing application of higher DC power levels (to improve deposition rate). Polysilicon TFTs fabricated with the optimum Ar-He ratio (>5% Ar in He) demonstrate similar performance between pure-Ar and Ar-He sputtered p-Si TFTs.
Origin of Inhomogeneity in Pulsed Excimer-Laser Crystallized Silicon Films Studied by Computer Simulation
Authors: Kudo Toshio , Ichishima Daiji , Jin Cheng-Guo 
Published: April 2011

AbstractIn order to understand the occurrence and development of inhomogeneous poly-Si texture in the polycrystallization process of poly-SiTFT fabrication, we have simulated 1) the influence of pulse energy (PE) and optical axis (OA) fluctuations on the texture of poly-Si films and 2) the interference between both fluctuations, under the single-pulsed XeCl laser irradiation at the overlapping ratio 98%. The frequency of fatal irregular pulses in the PE fluctuation is much more than that in the OA fluctuation (pointing stability). Once the poly-Si texture suffers a fatal irregular pulse over the complete melting (CM) point, the inhomogeneous texture caused is never recovered by the following overlapping irradiation and no columnar structure is formed. However, when no irregular pulses exceed the CM point, the partial inhomogeneous texture caused in the poly-Si films is recovered by the thinning out of small Si grains in the texture and a columnar structure is formed. The key to the issue of fatal irregular pulses should be not only the reduction of PE and OA fluctuations but also the optimum selection of pulse energy not over the CM point.
Strained Ge Channel p-type MOSFETs Fabricated on Si1−xGex/Si Virtual Substrates
Authors: Lee Minjoo L. , Leitz Christopher W. , Cheng Zhiyuan , Pitera Arthur J. , Taraschi Gianni , Antoniadis Dimitri A. , Fitzgerald Eugene A. 
Published: April 2011

AbstractWe have fabricated strained Ge channel p-type metal oxide semiconductor field-effect transistors (p-MOSFETs) on Si1−xGex (x=0.7 to 0.9) virtual substrates. Capping the channel with a relaxed, epitaxial silicon layer eliminates the poor interface between silicon dioxide (SiO2) and pure Ge. The effects of the Si cap thickness, the strain in the Ge channel, and the thickness of the Ge channel on hole mobility enhancement were investigated. Optimized strained Ge p-MOSFETs show hole mobility enhancements of nearly 8 times that of co-processed bulk Si devices across a wide range of vertical field. These devices demonstrate that the high mobility holes in strained Ge can be utilized in a MOS device despite the need to cap the channel with a highly dislocated Si layer.
A Patterned Soi by Masked Anneal for System-on-Chip Applications
Authors: Cohen G. M. , Sadana D. K. 
Published: April 2011

AbstractWe present a method for fabricating pattern silicon-on-insulator (SOI) wafers that exploit internal thermal oxidation (ITOX) to control the BOX formation. We demonstrated the process by fabricating a pattern SOI having two different buried oxides (BOX) thickness. We also show that by using a very low oxygen dose the BOX can be quenched in the masked regions, while maintaining a continuous BOX in unmasked regions. Very low damage forms at the transition region from thick to thin BOX. Due to the oxygen diffusion the smallest patterned box feature we could obtain was limited to > 0.5 micron.