bluuebunny/crossref_metadata_2025_split huggingface dataset:
Thin-Film Polycrystalline-Silicon Solar Cells on Ceramic Substrates Made by Aluminum-Induced Crystallization and Thermal CVD
Authors: Gordon Ivan , Van Gestel Dries , Carnel Lode , Van Nieuwenhuysen Kris , Beaucarne Guy , Poortmans Jef 
Published: April 2011

AbstractA considerable cost reduction could be achieved in photovoltaics if efficient solar cells could be made from thin polycrystalline-silicon (pc-Si) layers. Aluminum-induced crystallization (AIC) of amorphous silicon followed by epitaxial thickening is an effective way to obtain large-grained pc-Si layers with excellent properties for solar cells. To obtain efficient solar cells, the electronic quality of the pc-Si material obtained by AIC has to be optimized and the cell design has to be adapted to the material. In this paper, we report on pc-Si solar cells made by AIC in combination with thermal CVD on ceramic alumina substrates. We made pc-Si solar cells on alumina substrates that showed Voc values up to 533 mV and efficiencies up to 5.9%. This is the highest efficiency ever achieved with pc-Si solar cells on ceramic substrates where no (re)melting of silicon was used. We demonstrate that the quality of the pc-Si material can be improved drastically by reducing the substrate roughness using spin-on oxides. We further show that a-Si/c-Si heterojunctions lead to much higher Voc values than diffused homojunctions. A cell concept that incorporates spin-on oxides and heterojunction emitters is therefore best suited to obtain efficient pc-Si solar cells on alumina substrates.
Light Filtering Properties in a-SiC:H Multilayer Structures: A SPICE model
Authors: Martins J. , Vieira M. , Fernandes M. , Louro P. , Fantoni A. 
Published: April 2011

AbstractA SPICE model of a-SiC:H/ a-Si:H pin/pin detector with voltage controlled spectral sensitivity is presented. The equivalent electric circuit able to describe the behavior of the multilayer structure under non-uniform illumination is composed of two series connected diodes, representing the pin structures, with two nonlinear current sources in parallel, representing the photogeneration for different steady state RGB illumination, with their value depending also on the thickness of the absorber layer and the built-in potential of the diodes. This device represents the 1D model of the LSP (Laser Scanned Photodiode) and may be interconnected in a 2D array trough resistors, modeling the high resistivity of the a-SiC:H layers. Electrical simulations were performed for different transducer configurations and illumination conditions and compared with the experimental data. The influence of the lateral and transverse resistors and built-in potential of the diodes on sensor parameters like spatial resolution, and signal amplitude are analyzed. A physical model supported by the electrical simulation gives insight into the methodology used for image representation and color discrimination.
Influence of Defect Post-deposition Treatments on poly-Si Thin-film Solar Cells on Glass grown by ECRCVD
Authors: Rau Björn , Schneider Jens , Conrad Erhard , Gall Stefan 
Published: April 2011

AbstractThe epitaxial thickening of a thin polycrystalline Si (poly-Si) film (seed layer) is a promising approach to realize an absorber layer of a poly-Si thin-film solar cell on glass. Such cell concept combines the benefits of crystalline Si and the high potential for cost reduction of a thin-film technology. Here, we discuss the influence of post-deposition treatments on the properties of absorber layers grown by electron-cyclotron resonance chemical vapor deposition (ECRCVD) and the solar cell performance, respectively. After the absorber growth and prior to the emitter deposition, defect annealing was used to improve the structural quality of the absorber layers and to increase the doping efficiency. For this, we used rapid thermal annealing (RTA) processes as well as thermal annealing in a conventional quartz furnace. In order to avoid damaging of the glass, only short annealing times (up to 400 s) were applied at temperatures of up to 950 °C. Defect passivation treatments were carried out at temperatures of about 350 °C to passivate the remaining defects in the films by hydrogen. The impact of both treatments on the solar cell parameter will be discussed. Excellent VOC's of up to 361 mV were achieved without hydrogenation showing the high potential of ECRCVD-grown absorbers. Applying both treatments resulted so far in an increase of VOC of about 400 mV. Because of the fact, that both post-treatments (particularly hydrogenation) are still not yet optimized, further improvements can be expected.
The Carbon Co-implant with Spike RTA Solution for Phosphorus Extension
Authors: Pawlak Bartek , Duffy Ray , Augendre Emmanuel , Severi Simone , Janssens Tom , Absil Philippe , Vandervorst Wilfried , Collart Erik , Felch Susan , Schreutelkamp Robert , Cowern Nick 
Published: April 2011

AbstractAs extensions have been up till now always used in N-MOS transistors with an activation anneal. Here, we show that also alternative doping by P can result in junction extensions that are extremely abrupt and shallow thus suitable for upcoming transistor technologies. P extensions are manufactured by amorphization, carbon co-implantation and conventional rapid thermal annealing (RTA). The impact of Si interstitials (Sii) flux suppression on the formation of P junction extensions during RTA is demonstrated. We have concluded that optimization of implants followed by RTA spike offers excellent extensions with depth Xj = 20 nm (taken at 5 × 1018 at./cm3), abruptness 3 nm/dec. and Rs = 326 Ω. Successful implementation of these junctions is straightforward for N-MOS devices with 30 nm gate length and results in an improved short channel effects with respect to the As reference.
Modeling and Simulation of the Influence of SOI Structure on Damage Evolution and Ultra-shallow Junction Formed by Ge Preamorphization Implants and Solid Phase Epitaxial Regrowth
Authors: Mok Caroline , Colombeau B. , Jaraiz M. , Castrillo P. , Rubio J. E. , Pinacho R. , Srinivasan M. P. , Benistant F. , Martin-Bragado I. , Hamilton J. J. 
Published: April 2011

AbstractPreamorphization implant (PAI) prior to dopant implantation, followed by solid phase epitaxial regrowth (SPER) is of great interest due to its ability to form highly-activated ultra-shallow junctions. Coupled with growing interest in the use of silicon-on-insulator (SOI) wafers, modeling and simulating the influence of SOI structure on damage evolution and ultra-shallow junction formation is required. In this work, we use a kinetic Monte Carlo (kMC) simulator to model the different mechanisms involved in the process of ultra-shallow junction formation, including amorphization, recrystallization, defect interaction and evolution, as well as dopant-defect interaction in both bulk silicon and SOI. Simulation results of dopant concentration profiles and dopant activation are in good agreement with experimental data and can provide important insight for optimizing the process in bulk silicon and SOI.
Impurity Solubility and Redistribution Due to Recrystallization of Preamorphized Silicon
Authors: Duffy Ray , Venezia Vincent , Hopstaken Marco , Maas Geert , Dao Thuy , Tamminga Yde , Roozeboom Fred , van der Tak Karel 
Published: April 2011

AbstractThe use of silicon substrate preamorphization in ultrashallow junction formation has increased in recent years. The reduction of channeling during impurity implantation, coupled with higher-than-equilibrium metastable solubility levels, produces scaled junctions with low resistances. However, a number of physical phenomena arise that must be considered for proper impurity profile and device optimization.With respect to impurity solubility advanced annealing techniques such as solid-phase-epitaxial-regrowth (SPER), flash, and laser annealing, can place impurity atoms on substitutional sites in the silicon lattice to extremely high concentrations when combined with preamorphization. In this context there is a relationship between the equilibrium distribution coefficient and metastable solubility. The long-established equilibrium distribution coefficient of an impurity, extracted in the liquid to solid phase transformation, can make a prediction of metastable solubility after transformation of amorphous silicon into crystalline silicon during SPER, flash, and laser annealing.With respect to impurity redistribution the significant effects can be split into 3 categories, namely before, during, and after recrystallization. Before recrystallization impurity diffusion in the amorphous region may occur. Boron is particularly susceptible to this effect, which is very significant for the formation of p-type junctions. During recrystallization many impurities move ahead of the amorphous-crystalline (a/c) interface and relocate closer to the surface. In general redistribution is more likely at high impurity concentrations. For low-temperature SPER there is a direct correlation between the magnitude of this redistribution effect and the impurity metastable solubility. After recrystallization, with SPER, flash, and laser annealing commonly leaving residual damage in the silicon substrate, interstitial-diffusers are especially vulnerable to preferential diffusion toward the surface, where impurity atoms may be trapped, ultimately leading to a more shallow profile.
Deactivation of Ultra Shallow B and BF2 Profiles After Non-melt Laser Annealing
Authors: Sharp Jim , Cowern Nicholas E.B , Webb Roger P. , Giubertoni Damiano , Gennaro Salvotore , Bersani Massimo , Foad Majeed A. , Kirkby Karen J. 
Published: April 2011

AbstractUltra-shallow B and BF2 implants in silicon pre-amorphised with Ge have been activated using a scanning non-melt laser. The implants were activated either by using 1 or 10 laser scans. Isochronal 60s post-laser annealing between 700-1000°C were then undertaken to study the deactivation and reactivation of the B. Both B and BF2 samples were implanted with a dose of 1x1015 B cm-2 at an effective energy of 500eV. The presence of F from the BF2 implants, which is superimposed over the boron profile increases the sheet resistance of the initial fabricated junction (from 600-700 Ω/sq from B implants only to 750-1100 Ω/sq for BF2 implants). Fluorine also changes the deactivation and reactivation behaviour of the boron during the post-anneals by increasing the amount of deactivation of the boron.
Accurate Sheet Resistance Measurement on Ultra-Shallow Profiles
Authors: Clarysse Trudo H. , Moussa Alain , Leys Frederik , Loo Roger , Vandervorst Wilfried , Benjamin Mark C. , Hillard Robert J. , Faifer Vladimir N. , Current Michael I. , Lin Rong , Petersen Dirch H. 
Published: April 2011

AbstractComparison of state-of-the-art zero-penetration sheet resistance tools on ultra-shallow Boron CVD layers on top of a medium doped As layer.
Schottky-barrier height tuning using dopant segregation in Schottky-barrier MOSFETs on fully-depleted SOI
Authors: Knoch Joachim , Zhang Min , Zhao Qing-Tai , Mantl Siegfried 
Published: April 2011

AbstractIn this paper we demonstrate the use of dopant segregation during silicidation for decreasing the effective potential barrier height in Schottky-barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs). N-type as well as p-type devices are fabricated with arsenic/boron implanted into the device's source and drain regions prior to silicidation. During full nickel silicidation a highly doped interface layer is created due to dopants segregating at the silicide-silicon interface. This doped layer leads to an increased tunneling probability through the Schottky barrier and hence leads to significantly improved device characteristics. In addition, we show with simulations that employing ultrathin body (UTB) silicon-on-insulator and ultrathin gate oxides allows to further improve the device characteristics.
A Novel High-Stress Pre-Metal Dielectric Film to Improve Device Performance for sub-65nm CMOS Manufacturing
Authors: Teh Young Way , Sudijono John , Jain Alok , Venkataraman Shankar , Thirupapuliyur Sunder , Whitesell Harry 
Published: April 2011

AbstractThis work focuses on the development and physical characteristics of a novel dielectric film for a pre-metal dielectric (PMD) application which induces a significant degree of tensile stress in the channel of a sub-65nm node CMOS structure. The film can be deposited at low temperatures to meet the requirements of NiSi integration while maintaining void-free gap fill and superior film quality such as moisture content and uniformity. A manufacturable and highly reliable oxide film has been demonstrated through both TCAD simulation and real device data, showing ~6% NMOS Ion-Ioff improvement; no Ion-Ioff improvement or degradation on PMOS. A new concept has been proposed to explain the PMD strain effect on device performance improvement. Improvement in Hot Carrier immunity is observed compared to similar existing technologies using high density plasma (HDP) deposition techniques.
Process-Induced Strained P-MOSFET Featuring Nickel-Platinum Silicided Source/Drain
Authors: Lee Rinus Tek Po , Liow Tsung-Yang , Tan Kian-Ming , Ang Kah-Wee , Chui King-Jien , Guo Qiang-Lo , Samudra Ganesh , Chi Dong-Zhi , Yeo Yee-Chia 
Published: April 2011

AbstractWe report the use of nickel-platinum silicide (NiPtSi) as a source/drain (S/D) material for strain engineering in P-MOSFETs to improve drive current performance. The material and electrical characteristics of NiPtSi with various Pt concentrations was investigated and compared with those of NiSi. Ni0.95Pt0.05Si was selected for device integration. A 0.18 μm gate length P-MOSFET achieved a 22% gain in IDsat when Ni0.95Pt0.05Si S/D is employed instead of NiSi S/D. The enhancement is attributed to strain modification effects related to the nickel-platinum silicidation process.
Stress and Strain Measurements in Semiconductor Device Channel Areas by Convergent Beam Electron Diffraction
Authors: Li Jinghong , Domenicucci Anthony , Chidambarrao Dureseti , Greene Brian , Rovdedo Nivo , Holt Judson , Dunn Drerren , Ng Hung 
Published: April 2011

AbstractConvergent electron beam diffraction (CBED) has been successfully applied to measure strain/stress in the channel area in PMOS semiconductor device with embedded SiGe (eSiGe) for 65nm technology. Reliable results of strain/stress measurements in the channel area have been achieved by good fitting of experimental CBED patterns with theoretical calculations. Stress measurements from CBED are in good agreement with simulations. A compressive stress as high as 823.9 MPa was measured in the <110> direction in the channel area of a PMOS device with eSiGe with 15% Ge and a thickness of 80nm. Stress measurements from CBED also confirm that the depth of the eSiGe and defects such as dislocation loops within the eSiGe relax strain/stress within the film and reduce strain/stress in the channel area.
A Physically Based Quantum Correction Model for DG MOSFETs
Authors: Karner Markus , Wagner Martin , Grasser Tibor , Kosina Hans 
Published: April 2011

AbstractIn this work we present a physically based quantum correction model for highly scaled double gate (DG) CMOS devices. In contrast to previous work, our quantum correction model is based on the bound states that form in the Si film. The Eigenenergies and expansion coefficients of the wave functions are tabulated for arbitrary parabolic approximations of the potential in the structure. This enables a highly efficient use for TCAD applications.
3D Modelling Of The Novel Nanoscale Screen-Grid FET
Authors: Ding Pei W. , Fobelets Kristel , Velazquez-Perez Jesus E 
Published: April 2011

AbstractA novel field effect transistor (FET) that uses 3-dimensional (3-D) embedded gate fingers – the Screen-Grid Field Effect Transistor (SGFET) – is proposed. The gating action of the SGFET is based on the design of multiple gating cylinders into the channel region, perpendicular to the current flow. Such configuration allows a full 3-D gate control of the current which improves the device characteristics by increasing the gate to channel coupling. Initial investigations of the SGFET using 3-D TCAD TaurusTM simulation software are presented in this paper. The results indicate that the proposed SGFET offers the possibility of downscaling without degrading the output characteristics. A comparison between the SGFET and both bulk and SOI MOSFETs shows the superior characteristics of the SGFET for low power operation.
Characterization of Chemical Bonding in Low-K Dielectric Materials for Interconnect Isolation: A XAS and EELS Study
Authors: Hoffmann Patrick , Schmeisser Dieter , Engelmann Hans-Juergen , Zschech Ehrenfried , Stegmann Heiko , Himpsel Franz , Denlinger Jonathan 
Published: April 2011

AbstractThe use of low dielectric constant materials in the on-chip interconnect process reduces interconnect delay, power dissipation and crosstalk noise. To achieve the requirements of the ITRS for 2007-2009 minimal sidewall damage from etch, ash or cleans is required. In chemical vapor deposited (CVD) organo-silicate glass (OSG) which are used as intermetal dielectric (IMD) materials the substitution of oxygen in SiO2 by methyl groups (-CH3) reduces the permit-tivity significantly (from 4.0 in SiO2 to 2.6-3.3 in the OSG), since the electronic polarizability is lower for Si-C bonds than for Si-O bonds.However, plasma processing for resist stripping, trench etching and post-etch cleaning removes C and H containing molecular groups from the near-surface layer of OSG. Therefore, compositional analysis and chemical bonding characterization of structured IMD films with nanometer resolution is necessary for process optimization.OSG thin films as-deposited and after plasma treatment are studied using X-ray absorp-tion spectroscopy (XAS) and electron energy loss spectroscopy (EELS). In both techniques, the fine structure near the C1s absorption or energy loss edge, respectively, allows to identify C-H, C-C, and C-O bonds. This gives the opportunity to differentiate between individual low-k mate-rials and their modifications. The O1s signal is less selective to individual bonds. XAS spectra have been recorded for non-patterned films and EELS spectra for patterned structures. The chemical bonding is compared for as-deposited and plasma-treated low-k materials. The Fluo-rescence Yield (FY) and the Total Electron Yield (TEY) recorded while XAS measurement are compared. Examination of the C 1s near-edge structures reveal a modified bonding of the re-maining C atoms in the plasma-treated sample regions.
Theoretical Analysis of Thermal Conductivity in Amorphous Inter-layer Dielectrics
Authors: Shamsa Manu , Morrow Patrick , Ramanathan Shriram 
Published: April 2011

AbstractUnderstanding thermal conduction in interlayer dielectrics (ILDs) is important for the optimal design of interconnect layers in backend semiconductor processing for future high-performance nano-scale devices. Reduced thermal conductivity of porous ILDs for example can adversely affect the temperature rise in the embedded metal lines leading to un-desirable reliability issues and design constraints. In this paper, we report results of our theoretical and experimental investigation of thermal transport in amorphous and porous dielectrics. A phonon-hopping model has been adapted to calculate the thermal conductivity in disordered materials. The value of hopping integral has been calculated by comparing the modeling results with experimental data for various amorphous and porous materials. The model shows reasonable agreement with experimental data for various amorphous materials including SiO2and other glasses over a wide temperature range from 50K – 300K. The model suggests that the hopping of localized high frequency phonons is a dominant thermal transport mechanism in such material systems.
Structures and Properties of an Ultra-Low-k Material: Classical-molecular-dynamics and First-principles Calculations
Authors: Ushio Jiro , Hamada Tomoyuki , Ohno Takahisa , Nakao Shin-Ichi , Yoneda Katsumi , Kato Manabu , Kobayashi Nobuyoshi 
Published: April 2011

AbstractWe determined the most probable atomistic structure of an ultra-low-k material (k≅ 2.5) by computer simulations. Among the candidate structures generated by a molecular-dynamics calculation, the most probable one that reproduces the observed properties was selected using a first-principles density-functional-theory calculation. The candidate structures consisted of Si-O-Si network with some silicon atoms, each of which had a CH3 group or a hydrogen atom bonded. The structure with CH3 groups but no hydrogen atom reproduced the experimental properties best. This structure was then used to investigate the behaviors of the material irradiated with ultraviolet light.
Thermal Oxidation of Ni and Co Alloys Formed by Electroless Plating
Authors: Gambino Jeff , Ivanov Igor , Mongeon Steve , Adams Ed , Hazel Scott , Meatyard Dave , Pokrinchak Phil , Chen Fen , DeHaven Pat , Kolics Artur , Polyanskaya Marina 
Published: April 2011

AbstractThe thermal oxidation of Co alloy and Ni alloy thin films on top of Cu, has been studied as a function of film composition. Four different alloys were studied; CoWP, CoWB, CoMoB, and NiMoB. For the Co alloys, significant oxidation is observed after an air anneal above 350C, accompanied by Cu diffusion through the film to the surface. In contrast, for the NiMoB films, there is minimal oxidation of the surface even after a 400C anneal in air, and Cu diffusion through the film is greatly reduced. These results indicate that Ni-based barriers may be desirable in applications where self-aligned metal layers are used on top of Cu interconnects as a replacement for dielectric caps such as SiN and SiCN.
Kinetics of Void Drift in Copper Interconnects
Authors: Choi Zung-Sun , Mönig Reiner , Thompson Carl V. , Burns Michael 
Published: April 2011

AbstractWe have observed the real-time behavior of electomigration-induced voids in both passivated and unpassivated copper interconnects in a Scanning Electron Microscope (SEM), and correlated void nucleation, growth, drift and stagnation with post-electromigration crystallographic microanalyses carried out using Electron Back-Scattered Diffraction (EBSD) analysis. Voids that nucleate at various locations along the interconnects often drift toward the cathode, where they grow, coalesce, and eventually cause electrical failure. In-situ SEM observations allowed for the tracking of void shapes and drift rates over long (multi-grain) distances. Changes in the size and the velocity of the voids were observed when the voids passed through different grains. These changes are attributed to the difference in diffusivity for different grain orientations. In passivated lines, voids were often trapped at individual grain boundaries, where they grew to cause failure, or de-trapped to continue to drift toward the cathode. In unpassivated lines, voids did not drift, but instead always nucleated and grew and grain boundaries. Locations at which voids grew in unpassivated lines, or at which voids were trapped and grew in passivated lines, were correlated with the crystallographic orientations of “upwind” and “downwind” grains. From these analyses, we find that the average electromigration interface diffusivities (z*D) as a function of grain orientation are ordered according to {100} > {111} > {110}. Quantitative analysis of void dynamics, correlated with crystallographic microanalyses, provides important data for modeling of electromigration-induced failure, and for process-optimization for improved reliability.