bluuebunny/crossref_metadata_2025_split huggingface dataset:
Effect of Mechanical and Chemical Wear on Consistency of Conditioning in Diamonds
Authors: Yamada Yohei , Kadomura Kazunori , Kawakubo Masanori , Sugaya Takahiro , Hirai Osamu , Tsugane Ken 
Published: August 2010

AbstractWe evaluated the effects of the edge degradation of diamonds in terms of their cutting ability from the viewpoint of mechanical, chemical and chemical-mechanical wear in chemical-mechanical polishing (CMP) systems for high-volume manufacturing. The results showed that both micro-chipping on the cutting edges of diamonds caused by a mechanical shock test and the rounding off of the sharp edges of diamonds in a marathon wear test degraded the pad cut rate, while no adverse effects on the cutting ability were observed during an acidic slurry immersion test. We also examined in situ coefficient of friction (COF) monitoring for use in identifying the tribology of the pad conditioning. Furthermore, we demonstrated the usefulness of measuring the height ratio of the asperity called “top surface area (TSA) ratio” as an appropriate topographical parameter to study the dependence of COF during conditioning on the decay of the tungsten removal rate. We presented a clear correlation between the pad cut rate degradation and the TSA ratio after CMP in order to elucidate an increase in the conditioning COF related to truncation of the asperity tip by wear and plastic deformation.
Influence of Ionic Strength and pH-value on the Silicon Dioxide Polishing Behaviour of Slurries Based on Pure Silica Suspensions
Authors: Kuenzelmann Ulrich , Estel Kathrin , Bartha Johann W , Meyer Erwin-Peter , Barthel Herbert 
Published: August 2010

AbstractIn this study, the effect of the addition of electrolytes in a given ionic strength to various high-purity silica suspensions was investigated by measurement of the removal rates (RR's) in CMP processes on oxide layers under the same experimental conditions. As so-called slurries the following suspensions were used: i) silica sols produced by the Stöber process, ii) conventional silica sols based on alkali silicate as well as iii) suspensions of fumed silica, with the same SiO2 concentration in each suspension. Ionic strength of the added electrolyte was adjusted to e.g. 0.065 mol/l, with the electrolytes being HCl, NH4Cl, KOH, or binary mixtures of these substances.These investigations revealed significant differences of the polishing behaviour between the different types of silica dispersions as slurries. While for the Stöber sols investigated, the RR's are highest in the acidic range and almost negligible in the alkaline pH range, fumed silica suspensions show an entirely different behaviour: RR is very low for acidic pH-values, and increases with the alkalinity of the slurry. In contrast to these observations, the RR's of slurries based on conventional silica sols are highest around the neutral point, and show a decrease for both more alkaline and acidic pH-values. In comparison to the other two types of material, these suspensions have a high amount of electrolyte background, originating from their manufacturing process.A model is developed to explain these results in a comprehensive manner. It involves effects of the electrolyte type and the ionic strengths as well as influences of the particle size.
The Mechanism of Low pH Colloidal Silica-based Oxide Slurries
Authors: White Michael L. , Jones Lamon , Romine Richard 
Published: August 2010

AbstractThe mechanism of oxide polishing at low pH in the presence of an organic cation is discussed. The role of the cation is thought to involve increasing the nucleophilicity of the silanolate active site on the particle surface by lowering the hydration state. Additionally, the activation energy of the reaction may be lowered by charge attraction between the particle and wafer surface and by increased hydrophobic interactions.
Characterization of Surface Processes During Oxide CMP by in situ FTIR Spectroscopy With Microstructured Reflection Elements at Silicon Wafers
Authors: Schumacher Henrik , Kuenzelmann Ulrich , Bartha Johann W 
Published: August 2010

AbstractIn situ investigations of the chemical and mechanical mechanisms during CMP processes require analytical access to the wafer surface while interacting with the slurry and the pad under polishing conditions. In this study me make use of novel, specifically prepared, and self-designed Si wafer called microstructured single reflection elements (mSRE) utilizing the IR transparency of silicon [1]. The mSRE's enable in and ex situ attenuated total reflection (ATR) Fourier transform infrared (FTIR) investigations at the interface between silicon and the ambient with an enhanced usable spectral range. So, a thin silicon oxide layer or the polishing slurry can be investigated in the entire mid and far infrared spectral region. These mSRE wafers were placed at a simple reflection accessory of a FTIR spectrometer and either wet etched by a buffered oxide etch or polished using a CMP equivalent polishing configuration. During CMP the change of typical vibration bands of SiO2 layers and slurry constituents are observed. It was shown that the sensitivity as well as the surface selectivity of the experimental setup enables slurry and thin-film characterisations within the thickness range of monolayers. Surprisingly, the spectral features of the pad have not been observed during the polishing investigations.
Effect of TaN Stoichiometry on Barrier Oxidation and Defect Density in 32nm Cu/Ultra-Low K Interconnects
Authors: Simon Andrew H. , Baumann Frieder H. , Bolom Tibor , Park Jong Guk , Child Craig , Kim Ben , DeHaven Patrick W. , Davis Robert E. , Ogunsola Oluwafemi O , Angyal Matthew S 
Published: August 2010

AbstractThe scaling of BEOL interconnect technology in ULSI circuitry requires the integration of Cu wiring with ultra-low K (ULK) dielectrics. We present the results of a study of the interaction between different-stoichiometry Ta(N)/Cu barrier processes and porous ULK dielectrics (k=2.4) at 32nm groundrules Auger and diffraction analysis of blanket wafers was used to benchmark two different stoichiometries of TaN barrier deposited using commercially-available ionized PVD sources. Comparison TEM and EDX/EELS images indicates that barrier oxidation is occurring in the low nitrogen-content Ta(N) barrier, which is absent at the higher stoichiometry. These differences are further manifested in defect-density analysis of patterned wafers comparing the two processes. These results illustrate the critical importance the TaN barrier properties play in enabling the integration of Cu/ULK interconnects at 32nm at beyond.
Interfacial Resistive Properties of Multi-layered Silicon-based Ohmic Contacts
Authors: Bhaskaran Madhu , Sriram Sharath , Holland Anthony Stephen 
Published: August 2010

AbstractThis article reports on the characterization of two- and three-layer ohmic contacts comprising of titanium disilicide and nickel silicide. Cross Kelvin resistor test structures were used to extract the specific contact resistivity (SCR) values for the different ohmic contacts fabricated. The SCR of aluminum to titanium silicide (Al-TiSi2) ohmic contacts was evaluated to be as low as 6.0 x 10-10 Ωcm2. Three-layer ohmic contacts were created using aluminum and nickel silicide thin films and doped silicon. SCR values as low as 5.0 x 10-9 Ωcm2 to antimony-doped silicon and 3.5 x 10-9 Ωcm2 to boron-doped silicon were evaluated.
Designing Ultra Low-k Dielectric Materials for Ease of Patterning
Authors: Antonelli George Andrew , Jiang Gengwei , Sriram Mandyam , Chattopadhyay Kaushik , Guo Wei , Sawin Herbert 
Published: August 2010

AbstractOrganosilicate materials with dielectric constants (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the film density, making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7% C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of the etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point.
Low Temperature Bonding via Copper Nanowires for 3D Integrated Circuits
Authors: Chun Shu Rong , Sasangka Wardhana Aji , Gan Chee Lip , Cai Hui , Ng Chee Mang 
Published: August 2010

AbstractLow temperature bonding is desired for compatibility with back-end-of-line processing (BEOL) conditions in order not to affect the three dimensional (3D) Integrated Circuits (IC) device performance. In this paper, the aim is to demonstrate that thermocompression bonding temperature can be lowered by changing the copper (Cu) film with Cu nanowires fabricated via electrodeposition through anodized aluminum oxide (AAO) template. A comparison was done between film-to-film (Film-Film) and nanowires-to-nanowires (NWs-NWs) bonding in terms of microstructure and shear strength. Cross-sectional images captured by Focused Ion Beam (FIB) revealed good interface between NWs-NWs bonding as the nanowires had fused together. Scanning Electron Microscope (SEM) images of samples after shear test also demonstrated that there is good adhesion between the bonding layers. Results from shear tests showed an increase in shear strength of NWs-NWs bonding as compared to that of Film-Film bonding at 200 °C. In addition, NWs-NWs bonding at 300 °C achieved higher shear strength than at 200 °C. In this study, it has been shown that copper nanowires fabricated via electrodeposition through porous AAO template can be a potential method to form a bonding intermediate layer for 3D ICs.
Silsesquioxane-based Photopatternable Porous Low-kDielectric Materials
Authors: Nelson Alshakim , Rathore Jitendra S , Davis Blake , Brock Phillip , Sooriyakumaran Ratnam , Miller Robert , Lin Qinghuang 
Published: August 2010

AbstractThe future resolution requirements for the semiconductor industry demand advanced lithographic techniques, such as immersion and extreme ultraviolet (EUV) technologies, which will increase the cost of microelectronics manufacturing. Currently, low-k dielectric materials, which are used as insulating layers between the copper wiring, are indirectly patterned using a set of sacrificial layers and etch processes. The sacrificial layers include a photoresist polymer that must first be imaged prior to transferring the pattern to the underlying layers, including the dielectric layer. In order to reduce the number of processing steps required for semiconductor manufacturing, we have developed a novel photo-patternable low-k dielectric material that (1) eliminates the need for sacrificial layers and (2) reduces the number of wafer processing steps. Silsesquioxane copolymers that undergo acid-catalyzed crosslinking when exposed to 193nm wavelength were synthesized. In addition to the direct photo-patternability, the patterned structures are suitable as a dielectric material with a dielectric constant as low as 2.4, and an appreciable elastic modulus (E > 4.0 GPa). These photo-patternable low-k materials represent a ‘greener' approach to semiconductor manufacturing which has the ability to reduce cost, waste materials, and energy consumption.
Annealing Effects on Si Nanocrystal Nonvolatile Memories
Authors: Dimitrakis Panagiotis , Bonafos Caroline , Schamm Sylvie , Normand Pascal , Assayag G. Ben 
Published: August 2010

AbstractThe effect of thermal treatments in oxidizing ambient on the structural and electrical properties of low-energy Si-implanted thin SiO2 layers which previously suffered or not high temperature annealing in inert ambient was investigated. Based on TEM examination, charge trapping evaluation and FN conduction analysis of the resulting Si-NC SiO2 matrices, a model taking into account the healing of excess silicon atoms introduced by implantation and the generation of Si interstitials by oxidation above and below the viscoelastic temperature of SiO2 is proposed.
Ultra-Low Energy Ion Implantation of Si into HfO2 and HfSiO-based Structures for Non Volatile Memory Applications
Authors: Gloux Florence , Coulon Pierre-Eugène , Groenen Jesse , Schamm Sylvie , Benassayag Gerard , Pecassou Beatrice , Slaoui Abdelilah , Sahu Bhabani , Carrada Marzia , Lhostis Sandrine , Bonafos Caroline 
Published: August 2010

AbstractThe fabrication of Si nanocrystals (NCs) in multilayer structures based on HfO2 and alloys for memory applications is carried out using an innovative method, the ultra-low energy (1 keV) ion implantation followed by a post-implantation annealing. Si+ ions are implanted into SiO2 thin layers deposited on top of thin HfO2-based layers. After annealing at high temperature (1050°C), the implantation leads to the formation of a two dimensional array of Si NCs at a distance from the surface larger than expected, due to an anomalous oxidation of the implanted Si. Nevertheless, the best memory windows are obtained at lower thermal budget, when no nanocrystals are present in the layer. This suggests that electrical measurements should always be correlated to structural characterization in order to understand where charge storage occurs.
Charge Trapping Sites in nc-RuO Embedded ZrHfO High-k Nonvolatile Memories
Authors: Lin Chen-Han , Kuo Yue 
Published: August 2010

AbstractMaterials and electrical properties of the MOS capacitor containing nc-RuO embedded in the high-k ZrHfO dielectric film have been studied. The electron- and hole-trapping capacities and trapping sites in this kind of device were investigated using the constant voltage stress method, the frequency-dependent C-V measurement, and the retention characteristics. The negligible charge trapping phenomenon in the non-embedded device rules out the possibility of any trapping site in the bulk ZrHfO film or at the Si/ZrHfO interface. The electrical characterization result suggests that electrons are trapped in the bulk nc-RuO. However, holes have two possible trapping sites, i.e., in the bulk nc-RuO or at the nc-RuO/ZrHfO interface.
Study on C60 Doped PMMA for Organic Memory Devices
Authors: Charbonneau Micael , Tiron Raluca , Buckley Julien , Py Mathieu , Barnes Jean-paul , Derrough Samir , Constancias Christophe , Licitra Christophe , Sourd Claire , Ghibaudo Gerard , De Salvo Barbara 
Published: August 2010

AbstractIn this paper, fabrication of nanocomposite thin films with introduction of fullerene (C60) molecules in PolyMethyl MethAcrylate resist (PMMA) was investigated from a material and electrical point of view. The effective inclusion of C60 molecules in the samples was characterized by using UV-vis and Tof-SIMS instruments. The modified resist PMMA:C60 was also studied with Thermal analysis (TGA, DSC) where modification of physical properties is reported. Films were included in MIS and MIM devices and results on non volatile trapping of C60 doped PMMA are presented. Moreover, e-beam exposure tests showed that PMMA:C60 active layers for memory devices, were scalable in size.
Correlation Between Oxygen Composition and Electrical Properties in NiO Thin Films for Resistive Random Access Memory
Authors: Nishi Yusuke , Iwata Tatsuya , Kimoto Tsunenobu 
Published: August 2010

AbstractAdmittance spectroscopy measurement has been performed on NiOx thin films with various oxygen compositions (x=1.0-1.2) in order to characterize localized defect levels. The activation energy and concentration of localized defect levels in NiOx films with low oxygen composition (x≤1.07) are 120-170 meV and lower than 2×1019 cm-3, respectively. From I-V measurement of the Pt/NiOx/Pt structures, samples with high oxygen composition (x≥1.10) did not show resistance switching operation, while samples with low oxygen composition (x≤1.07) did. The best oxygen composition of NiOx thin films turned out to be 1.07 in order to realize repeatable and stable resistance switching operation.
Formation of Ge Nanocrystals in High-k Dielectric Layers for Memory Applications
Authors: Dimitrakis Panagiotis , Ioannou-Sougleridis Vassilios , Normand Pascal , Bonafos Caroline , Schamm Sylvie , Mouti A , Schmidt Bernd , Becker Jill 
Published: August 2010

AbstractIn this paper, the fabrication of Ge-NCs embedded in Al2O3 and HfO2 layers by ion-beam-synthesis for memory applications is investigated. Structural properties of the high-k layers before and after implantation and annealing were studied by TEM observation and EELs analysis. Spherical Ge-NCs 5nm in diameter were observed in Al2O3 implanted layers after furnace annealing at 800°C in nitrogen. Annealing studies in the range 700-1050°C in nitrogen revealed the evolution of the charge storage properties of these structures utilizing MIS capacitors test structures. No NCs were observed in HfO2 implanted layers. However, significant negative-differential-resistance regions were observed in I-V characteristics of the related MIS structures. These may be attributed to the formation of conductive paths made of hafnium germanide (HfGe2) or hafnium germanate (HfGeO) regions.
Overview and Technical Trend of Chain FeRAM
Authors: Takashima Daisaburo 
Published: August 2010

AbstractA chain FeRAMTMis the best solution to realize high-speed and high-bandwidth nonvolatile RAM with low power dissipation. In this paper, the overview of chain FeRAM, the technical trend for FeRAM scaling and the marketing strategy are presented. First of all, the concept and performance of chain FeRAM are described. Secondly, the status and history of chain FeRAM development are presented. Thirdly, four kinds of scaling strategies for chain FeRAM are presented; (1) A shrink trend of chain cell including a capacitor plug shared with twin cells, and process techniques including Ir/TiAlN-barrier metal and MOCVD-PZT with SrRuO3electrode, which are installed in 16Kb, 8Mb, 32Mb, 64Mb and 128Mb chain FeRAMs, (2) Capacitor damage suppression processes to reinforce step coverage and protect H2damage even in 0.1μm2capacitor of 128Mb, (3) A scalable array architecture such as an octal / quad bitline architecture to reduce bitline capacitance and ensure enough cell signal in scaled ferroelectric capacitor, and (4) A ferroelectric capacitor overdrive technique by driving shield-bitlines to enlarge tail-to-tail cell signal in low voltage operation of 1.3V. Fourthly, future direction of chain FeRAM is discussed. The vertical capacitor is one of candidates for gigabit-scale chain FeRAMs, and solves signal problem and achieves small 4F2cell without contact formation. Finally, the marketing strategy to take full advantage of chain FeRAM is presented. A nonvolatile FeRAM cache is the promising candidate to achieve high bandwidth memory systems. Applications of chain FeRAM to solid-state drive (SSD) and hard-disk drive (HDD) and their system performance improvements are demonstrated.
Characteristics of ZnO Thin Film for the Resistive Random Access Memory
Authors: Seo Jung Won , Baik Seung Jae , Kang Sang Jung , Lim Koseng Su 
Published: August 2010

AbstractWe report resistive switching characteristics in Pt/ZnO/Pt devices where ZnO thin film is fabricated at various oxygen conditions. With the increase of oxygen contents in ZnO thin film, the forming voltage is gradually increased while reset and set voltages are almost unchanged. We also investigated the effect of top electrodes on resistive switching of top electrode/ZnO/Pt device. For a Pt/ZnO/Pt device, it exhibits the excellent resistive switching behavior due to high electrical field of the well-defined Schottky barrier. For Al/ZnO/Pt device, little resistive switching phenomena were occurred due to leakage current of the weak Schottky (or Ohmic) contact.
Effect of W Substitution in Strontium Bismuth Tantalate Ferroelectric Ceramics: Enhanced Ferroelectric Properties
Authors: Coondoo Indrani , Panwar Neearj , Biradar Ashok , Jha Arun 
Published: August 2010

AbstractTungsten (W)-substituted SBT ceramics [SrBi2(Ta1-xWx)2O9; 0.0 ≤ x ≤ 0.20] were synthesized by solid state reaction method using different sintering temperatures (1100 οC, 1150 οC, 1200 οC and 1250 οC). W substitution is found to significantly affect the electrical properties of SBT, including dielectric permittivity, Curie temperature, and ferroelectricity. Dielectric constant (εr) and the Curie temperature (Tc) increase with increasing W content. The dielectric loss reduces significantly with increase in W concentration. The maximum Tc of ~ 390 οC is observed in the sample with x = 0.20 as compared to ~ 320 οC for the pure sample when sintered at 1200 οC. The peak ε increases from ~ 270 in the sample with x = 0.0 to ~ 700 for the composition with x = 0.20, when sintered at 1200 οC. All the tungsten-substituted ceramics have higher 2Pr than that in the pristine sample. The maximum 2Pr (~25 μC/cm2) is obtained in composition with x = 0.05 sintered at 1200 οC. These effects have been interpreted based on the model of the recovery of oxygen vacancies upon W substitution. Such compositions with low loss and high Pr values should be excellent materials for highly stable ferroelectric memory devices.
Crystallization of ion amorphized Ge2Sb2Te5 in nano-structured thin films
Authors: Mio Antonio Massimiliano , Carria Egidio , De Bastiani Riccardo , Miritello Maria , Bongiorno Corrado , D'Arrigo Giuseppe , Spinella Corrado , Grimaldi MariaGrazia , Rimini Emanuele 
Published: August 2010

AbstractThe crystallization kinetics of nano-structured amorphous Ge2Sb2Te5 (GST) regions (20-100 nm in diameter) obtained by Electron Beam Lithography (EBL) and 40 KeV Ge+ 1014/cm2 ion irradiation of crystalline 20 nm thick films was investigated. The amorphous regions, surrounded by crystalline cubic (fcc) or hexagonal (hcp) phase, were recrystallized by isothermal annealing in the temperature range 80°C - 120°C and by focused electron beam irradiation. The process was followed in situ by transmission electron microscope (TEM). The recrystallization is governed by the growth of the surrounding f.c.c. crystalline interface with a velocity of 2×10-2 nm/s at 110°C. The interface velocity is higher in the h.c.p. substrate less than a factor ten. Local focused electron beam irradiation induces instead crystalline nucleation inside the nano amorphous regions. Similar experiments have been performed on planar ion amorphized thin films lying on both GST crystalline phases. In both cases the recrystallization is mainly associated to the movement of the amorphous-crystalline interface. These results indicate that the stability of the amorphous region, generated by ion irradiation, is severely affected by the adjacent crystalline structure and by the size of the amorphous area, critically involved in the scaling of the PCM-based devices.