bluuebunny/crossref_metadata_2025_split huggingface dataset:
High 2Deg Mobility and Fabrication of High Performance AiGaAs/GaAs Selectively Doped Heterostructure Transistors and Ring Oscillators on Si Substrates
Authors: Chand Naresh , Ren F. , Ziel J. P. Van Der , Chen Y. K. 
Published: March 2011

AbstractWe report growth by MBE and fabrication of state-of-the-art AlGaAs/GaAs selectively doped heterostructure transistors (SDHT's) and ring oscillators on Si substrates. In MBE growth, use of minimum As4/Ga flux ratio during initial nucleation combined with in-situ thermal cycles gave a marked improvement in material quality. Although undoped GaAs buffer layers were highly resistive and were fully depleted under a Schottky contact, a parallel n-type conduction path confined in a thin region (<0.1 pm) near the GaAs/Si interface was sometimes observed whose sheet density (1012 - 1013 cm−2) and mobility (600-900 cm2V−1 s−1) were independent of temperature between 77K and 300K. This parallel conduction did not affect the dc behavior and switching speed of SDHT's, and it was successfully prevented by doping the GaAs with Be near the interface. For a 2DEG sheet density of 1012 cm−2, a mobility as high as 53,500 cm2V−1s−1 at 77K was obtained, as against a mobility of ∼70,000 cm2 V−1 s−1 for a similar structure on GaAs substrates. For 1 μm-gate-length devices, maximum transconductances of 220 and 365 mS/mm were measured at 300K and 77K, respectively. A minimum propagation delay time, Td, of 28 ps/stage was measured at 300K for direct coupled FET logic (DCFL) ring oscillators for 1.1 mW/stage power dissipation. rd reduced to 17.6 ps/stage at 77K. From microwave S-parameter measurements at 300K, current gain and power gain cutoff frequencies of 15 GHz and 18 GHz, respectively, were measured. These results are comparable to the SDHT technology on GaAs substrates.
Reduction of Thermal Stress in Mbe Grown GaAs/Si by Patterning
Authors: Ziel J. P. Van Der , Chand Naresh , Weiner J. S. 
Published: March 2011

AbstractThe biaxial tensile stress of 2.65 kbar in as-grown GaAs/Si for T < 100K is reduced by post-growth patterning of the GaAs and the reduction in stress, as determined by photoluminescence and cathodoluminescence, is dependent on the pattern size and shape. For stripe patterns less than 15 gm wide the stress is largely uniaxial with stress relief normal to the stripe direction. Rectangular patterns exhibited stress relief in orthogonal directions, and a 9 x 12 µm2 rectangle exhibited an average stress of 0.5 kbar. For as-grown GaAs/Si layers 0.9 to 3.25 µm thick, the stress is weakly dependent on layer thickness. For T > looK the stress in as-grown GaAs/Si is reduced and at 295K a value of 1.51 ± 0.21 kbar is obtained. With patterned growth, using a native SiO2 mask, no reduction in stress was observed irrespective of the pattern size, indicating the importance of free GaAs edges in obtaining stress relief.
Photoelectronic Properties of Low Temperature GaAs Grown on Silicon and GaAs Substrates by Mbe
Authors: Mariella Raymond P. , Morse Jeffrey D. , Aines Roger , Hunt Charles E. 
Published: March 2011

AbstractThe characteristics of GaAs layers grown by MBE at growth temperatures from 200 °C to 400 °C have been evaluated by photoconductivity experiments in order to understand the photoelectronic properties of this material. Low temperature (LT) growth of GaAs on both silicon and GaAs substrates has been investigated in an attempt to better understand the nature of defects which are created in epitaxial layers grown under these conditions. Results from experiments on both annealed and unannealed LT samples indicate that the electronic transport properties of the epilayers can be controlled by selecting the appropriate growth conditions.
Comparison of the GaAs Layers Grown on Porous Si and on Si by Molecular Beam Epitaxy
Authors: Wu B.J. , Wang K.L. , Mii Y.J. , Yoon Y.S. , Wu A.T. , George T. , Weber E. 
Published: March 2011

AbstractGaAs layers have been successfully grown on tilted (100) Si as well as porous Si substrates by molecular beam epitaxy(MBE). Rapid thermal annealing and vacuum thermal annealing have been used to further improve the quality of the epitaxial layers. We observed that the dislocation density near the interface of the heterostructure is higher for GaAs on Si substrate. Both annealing processes are proven to be useful in improving layer quality, while the vacuum thermal annealing seemed to be more effective in minimizing the residual stress.
Initial Nucleation Studies of Heteroepitaxial GaAs films on Si Substrates by Modulated Molecular Beam Epitaxy
Authors: Lee Henry P. , Lius Xiaoming , Wang Shyh , George Thomas , Weber Eicke R. , Liliental-Weber Zuzanna 
Published: March 2011

AbstractNominal 100 Å and 150 Å thick GaAs layers were deposited on Si substrates by a modulated molecular beam technique and normal molecular beam epitaxy (MBE) at 300 °C and 375 °C respectively for plan view and cross-sectional transmission electron microscopy (TEM) examinations. From coverage of Moire fringes, it is found that the nucleated GaAs films grown by the modulated molecular beam technique were thinner, streaker and more two-dimensional than the MBE grown films. The same modulated molecular beam technique was also used for the deposition of the initial buffer layer of 3µm thick GaAs on Si films. Results from the 77k photoluminescence(PL) and double crystal X ray diffraction measurements showed that these films have superior optical and structural quality compared to similar films grown by normal two-step MBE. The improvement is attributed to a more two-dimensional nucleation of GaAs films associated with the modulated molecular beam growth technique.
Dependence of Threading Dislocation Density on Substrate Misorientation in In0.15Ga0.85As Grown on GaAs(100)
Authors: Uppal P.N. , Ahearn J.S. , Herring R. 
Published: March 2011

AbstractThe density and arrangement of dislocations in In0.15Ga0.85As grown on GaAs(100)) were determined by transmission electron microscopy as a function of misorientation toward (111)A, (111)B, and (110). Strained layer superlattices were used in all cases to reduce dislocation density. Layers grown on exact GaAs(100) exhibited a non-uniform threading dislocation dis- tribution whereby some areas had a high density (∼ 109cm-2or higher) of dislocation tangles and other areas that we in between had a more uniform density (∼ 2 x 107cm-2). The misorientated layers exhibited a uniform threading dislocation distribution with densities of ∼ 5 x 106 cm-2 for (100) misoriented towards (111)A, ∼ 1 x 107cm-2towards (111)B, and ∼ 3 x 107cm-2 towards (110). The misfit dislocation network (dislocations located at the GaAs-InO0.15Ga0.85 As interface) formed orthogonal dislocation arrays in the case of exact (100) substrates and slightly non-ortho- gonal arrays in the case of misoriented substrates. These results are explained with the help of a general glide model of strain relaxation in which the exact (100) orientation has eight equally stressed glide systems which presumably activate during strain relaxation. With misoriented substrates the stress symmetry is broken and fewer glide systems experience the maximum stress, thus reducing the number of active dislocation systems. A small asymmetry in interfacial dis- location density was observed in all the cases where the linear dislocation density along the two (011) and (011) orthogonal directions differed by about 20%. This is explained by the preferred activation of (x-dislocations (high dislocation mobility) over 13-dislocations (low dislocation mobility).
High Quality Epitaxial Growth on in-Situ Patterned Inp Substrates
Authors: Temkin H. , Harriott L. R. , Weiner J. , Hamm R. A. , Panish M. B. 
Published: March 2011

AbstractWe demonstrate a vacuum lithography process which uses a finely focused Ga ion beam to write the pattern which is then transferred to the InP pattern by low energy dry etching. Surface steps on the order of 1000-2000A in height, and lateral resolution limited only by size of the ion beam, can be efficiently prepared using moderate Ga ion fluences. The surfaces prepared by this process are damage free and suitable for epitaxial overgrowth. GaInAs/InP heterostructures grown on in-situ patterned substrates show excellent morphology and high luminescence efficiency.
Mbe-Growth of InAs and GaSb Epitaxial Layers on GaAs Substrates
Authors: Söderström J. R. , Chow D.H. , McGill T.C. , Watson T.J. 
Published: March 2011

AbstractWe have grown a number of InAs and GaSb bulk layers on GaAs substrates and studied the properties of the semiconductor films as a function of the various growth parameters. Preliminary results from GaSb growth are presented in addition to an extensive study of InAs growth. The films were characterized during growth by RHEED. RHEED-oscillations were observed during both InAs and GaSb growths. Hall effect measurements yielded peak electron mobilities for InAs of 18,900 cm2/Vs at 300 K and 35,000 cm2/Vs at 77 K. For GaSb the as grown layers were found to be p-type with a carrier concentration of 9x1015cm-3 and a hole mobility of 910 cm2 /Vs at 300 K.
Rheed Measurement and Chemical Kinetics of Chemical Beam Epitaxial growth of GaAs
Authors: Chiu T.H. 
Published: March 2011

AbstractRecent efforts employing reflection high energy electron diffiaction measurements to study the chemical beam epitaxial growth of GaAs is reviewed. A reaction model which assumes the dominance of Ga alkyls and their derivatives adsorbed on the growing surface can explain most of the growth results in a consistent way. Dynamic evolution of the reconstruction pattern of the adsorbed triethylgallium or trimethylgallium overlayer illustrates how the alkyl-Ga bonds are cleaved sequentially. The growth rate dependence on temperature and incident flux can be fitted quite well in this reaction model. In the absence of As flux, the existence of a metastable Ga alkyl overlayer makes possible the atomic layer epitaxy of GaAs.
Effect of Atomic Hydrogen on Impurity Reduction in Mombe-Grown GaAs
Authors: Kao Y.C. , Kim T.S. , Shih H.D. , Matteson S. , Duncan W.M. , Farrington D.L. 
Published: March 2011

AbstractIn this paper, the effect of atomic hydrogen on carbon impurity incorporation during the metalorganic-molecular-beam-epitaxy (MOMBE) growth of GaAs is studied. Atomic hydrogen was introduced into the MOMBE chamber during the growth by cracking molecular hydrogen with a high temperature cracker cell. Atomic hydrogen appears to be effective in reducing the background doping level of MOMBE-grown GaAs, presumably by reacting with hydrocarbon radicals. Background doping levels as low as 4 × 1014 cm−3 and room temperature hole mobilities as high as 430 cm2/V-sec were achieved. This result demonstrates that it is feasible to grow high quality GaAs films in MOMBE without using AsH3 or a high flux of As4by introducing atomic hydrogen into the chamber during the growth.
Low-Pressure Chemical Vapor Deposition of Polycrystalline Silicon and Silicon Dioxide By Rapid Thermal Processing
Authors: Öztürk Mehmet C. , Wortman Jimmie J. , Zhong Yu-Lin , Ren Xiao-Wei , Miller Roderick M. , Johnson F. Scott , Grider Douglas T. , Abercrombie David A. 
Published: March 2011

ABSTRACTLow-pressure chemical vapor deposition of polycrystalline silicon and silicon dioxide in a lampheated cold-wall rapid thermal processor have been investigated. Silicon dioxide films have been deposited by thermal decomposition of tetraethylorthosilicate known as TEOS. The technique can be used for rapid deposition of good quality thick passivation layers at moderate temperatures. Polycrystalline silicon depositions have been accomplished using silane (SiH4) diluted in argon as the reactive gas. Surface roughness and resistivity of the films deposited at temperatures above 700°C are comparable in quality to films deposited in a conventional LPCVD reactor at 610°C. In this temperature range, deposition rates as high as 4000Å/min can be obtained.
Polysilicon Emitter Transistors Manufactured using a Novel Limited Reaction Processing System
Authors: Ruddell Fred , Parkes Colin , Armstrong B Mervyn , Gamble Harold S 
Published: March 2011

ABSTRACTThis paper describes a LPCVD reactor which was developed for multiple sequential in-situ processing. The system is capable of rapid thermal processing in the presence of plasma stimulation and has been used for native oxide removal, plasma oxidation and silicon deposition. Polysilicon layers produced by the system are incorporated into N-P-N polysilicon emitter bipolar transistors. These devices fabricated using a sequential in-situ plasma clean-polysilicon deposition schedule exhibited uniform gains limited to that of long single crystal emitters. Devices with either plasma grown or native oxide layers below the polysilicon exhibited much higher gains. The suitability of the system for sequential and limited reaction processing has been established.
Thin Silicon Dioxide using the Rapid Thermal Oxidation Process for Trench Capacitors
Authors: Inoue Morio , Yoneda Kenji 
Published: March 2011

ABSTRACTElectrical characteristics of trench capacitor using RTO oxide, nitroxide and reoxidized nitroxide as the gate insulator are discussed. High temperature RTO is effective to prevent the oxide thinning at the trench corner and dielectric strength of trench capacitor is improved drastically. The lifetime of trench capacitors using RTO is more than 10 times longer than that of trench capacitors using conventional furnaces. Using reoxidized nitroxide as the gate insulator, higher charge to breakdown is obtained. The RTP is superior to the process using the conventional furnace for gate insulator of trench capacitor. Improvement in temperature uniformity and operation reproducibility are essential to RTP equipments for production use.
Formation of Device Quality Si/SiO2 Interfaces in a Multichamber Integrated Processing System
Authors: Kim S.S. , Tsu D.V. , Lucovsky G. , Fountain G.G. , Markunas R.J. 
Published: March 2011

ABSTRACTThis paper describes the key process steps in the low temperature, <300ºC, formation of device quality Si/SiO2 interfaces employing oxide deposition by Remote Plasma-Enhanced Chemical Vapor-Deposition (Remote PECVD). The quality of the Si/SiO2 interface correlates with the degree of surface reconstruction that is controlled by ex-situ wet cleaning and in-situ Rapid Flash Heating. Electronic properties of the MOS structure also vary with the deposited oxide thickness, independent of the initial surface quality.
(Rapid) Thermal Nitridation of SiO2 films
Authors: Oude Elferink J.B. , Habraken F.H.P.M. , van der Weg W.F. 
Published: March 2011

ABSTRACTIn this paper we report on the composition of thermally nitrided silicon dioxide films on silicon. Nitridation temperatures ranging from 950 to 1150ºC and nitridation times ranging from 10 to 240 s were used. The purpose of this study is to reveal the mechanisms involved in the nitridation process with emphasis on the role of hydrogen. From the temperature dependence of the amount of nitrogen in the films the effective activation energy for nitrogen incorporation in this initial stage was deduced.
Formation of Ultrathin Stacked Dielectrics Prepared by In-Situ Multi-Step RTP-CVD
Authors: Ting W. , Lin S. N. , Kwong D. L. 
Published: March 2011

ABSTRACTUltrathin stacked SiO2/Si3N4/SiO2 films have been fabricated successfully using in-situ multi-step rapid thermal processing chemical vapor deposition (RTP-CVD). Stacked Si3N4/SiO2 (NO) layers were deposited first by RTP-CVD. Some samples were further rapid-thermal oxidized after stacked layer deposition to form oxide/nitride/oxide (ONO) stacked layers. Ellipsometry, Fourier transform infrared spectroscopy (FTIR), x-ray photoelectron spectroscopy (XPS), and Auger electron spectroscopy (AES) were performed to characterize the films. Results show that well defined stacked Si3N4/SiO2 layers were fabricated and for wafers subjected to rapid-thermal oxidation an oxygen-rich SixNyOz layer was formed on the top of the dielectric stack. Nitrogen pile-up at the dielectric/substrate interface was observed for all wafers indicating that nitrogen diffuses into the bottom oxide during nitride deposition even though the deposition temperature is well below those used in thermal nitridation of thermal oxides.
Rapid Thermal Annealing of As in Si
Authors: Shih N.T. , Huang F.S. , Chu C.H. , Chen W.S. 
Published: March 2011

ABSTRACTThe results of a detailed investigation of diffusion of ion implanted As in Si during Rapid Thermal Annealing are reported. A series of experiments has been performed on samples prepared for various thermal treatments, such as peroxidation and preheat. The RTA conditions were chosen at 850°C for 15 seconds in order to study the metastable state. Sample analysis includes depth profiling by RBS and Spreading Resistance measurements, electrical characterization employing Hall measurements, and residual defects by cross-section TEM and planar image. The carrier concentration profile shows the different extent of the mixed Gaussian-Chebyshev polynomial distribution for various prepared samples. We believe the neutral interstitial state I°(Si) survives during RTA for asreceived samples. It gives a Gaussian curve in As profile. The denuded region produced after thermal treatments reduces the oxygen content and creates less 1°(Si) during SPE. So the Gaussian-Chebyshev polynomial distribution was obtained. From the above study, we believe the Gaussian profile can be obtained by controlling RTA conditions This Gaussian-like profile can also suppress hot electron effects by its smooth gradient (generating small electric field) near drain and large overlap under spacer (making large electric field away from gate). So we fabricated rapid thermal annealing singlediffusion drain n-MOSFET. The reduction of hot electron effects was studied, too.
Rapid Annealing of Rie-Induced Damage in GaAs and AlGaAs
Authors: Pearton S. J. , Hobson W. S. , Chakrabarti U. K. , Short K. T. , White A. E. , Jones K. S. 
Published: March 2011

ABSTRACTIon bombardment of the surface during CCI2 F2:O2 or C2 H6:H2 :Ar reactive ion etching of GaAs and AlGaAs can produce a heavily disordered near-surface (∼1000A for 380V self-bias on the cathode in a parallel plate reactor) region. The damage in this layer causes carrier depletion effects due to trapping of deep level defects. We have investigated the in-situ and post-RIE annealing of both the structural disorder and the electrical effects of the damage using TEM, ion channelling, C-V and I-V measurements. Etching at 400°C reduced the RIE-induced damage due to dynamic annealing processes. Carrier reductions of approximately an order of magnitude were observed immediately after etching GaAs and AIGaAs in C2H6:H2:Ar; much smaller changes (∼20%) were observed using CCI2F2:O2. For both gas chemistries annealing in the range 200–300°C produced the most ideal I-V characteristics in GaAs, whereas 300–400°C was required for AIGaAs.
Effects of Rapid Thermal Processing on Mbe GaAs on Si
Authors: Ito A. , Kitagawa A. , Tokuda Y. , Usami A. , Kano H. , Noge H. , Wada T. 
Published: March 2011

ABSTRACTVariations of electron traps in molecular-beam-epitaxial (MBE) GaAs layers grown on Si substrates by rapid thermal processing (RTP) have been investigated with deep level transient spectroscopy (DLTS). RTP was performed at 760 – 910 °C for 9s with Si02 encapsulant. In contrast with the layer on GaAs, the traps AI(Ec – 0.65eV) and A2(Ec – 0.81eV) are observed in the layer on Si. The trap EL2h, one of the EL2 family, is produced by RTP in the layer on Si. Some GaAs surfaces were etched to prove the deeper region. In the surface region, the concentrartion of EL2h is comparable to that of EL2 produced by RTP in the layer on GaAs. On the other hand, in ∿ 1 μm below the surface, the concentration of EL2h is about ten times as large as that of EL2. It is speculated that the stress from the GaAs/Si interface enhances the production of the EL2h concentration. In addition to the EL2, the traps R1(Ec – 0.23 eV), R2(Ec – 0.40 eV), R3(Ec – 0.43eV) and R4(Ec – 0.56 eV) are produced by RTP in the GaAs grown on Si.
Epitaxial Growth of Sil-xGex/Si Heterostructures by Limited Reaction Processing for Minority Carrier Device Applications
Authors: King C. A. , Hoyt J. L. , Noble D. B. , Gronet C. M. , Gibbons J. F. , Scott M. P. , Laderman S. S. , Kamins T. I. , Turner J. 
Published: March 2011

ABSTRACTIn an effort to extend the performance limits of semiconductors, devices based on heterojunctions rather than homojunctions are being investigated with great interest. Heterojunctions allow certain device design constraints to be relaxed because the charge distribution, electric field, and potential can be tailored extensively, permitting better device structures to be utilized. Silicon technology today enjoys a firm grip on a large portion of the electronics industry due in part to its superior material properties.
Focused Ion Beam Induced Deposition
Authors: Melngailis John , Blauner Patricia G. 
Published: March 2011

AbstractFocused ion beam induced deposition is already in use commercially for the repair of clear defects in photomasks, where missing absorber is added. Research is being carried out to extend this technique to the repair of x-ray lithography masks and to the restructuring and repair of integrated circuits, particularly in the prototype phase. In this technique a local gas ambient is created, for example, by aiming a small nozzle at the surface. The gas molecules are thought to adsorb on the surface and to be broken up by the scanned focused ion beam. A deposit is formed with linewidth equal to the beam diameter which can be below 0.1 Ό m. At small beam diameters and low currents (50–100 pA) the time to deposit 1Όm3 is in the vicinity of 10–20 sec. If the gas is a hydrocarbon, the deposit is largely carbon, which is useful for photomask repair. On the other hand, if the gas is a metal halide or a metal organic, the deposit is metallic. The deposits have substantial concentrations of impurities due to the atoms in the organometallic, to the ion species used, or to the ambient in the vacuum chamber. Thus the resistivities of the "metal" films deposited typically range from 150 to 1000 ΌΏcm which is usable for some repairs. (Pure metals have resistivities in the range 2.5 to 12 pQcm.) We have deposited gold from dimethyl gold hexafluoro acetylacetonate and have achieved linewidths down to 0.1 Όm, patches of 1 Όm thickness with steep side walls and in some cases, resistivities approaching the bulk value. Other workers have reported deposits of Al, W, Ta, and Cr. We will review previous work in the field and present some of our own current results.
Broad and Focused Ion Beam Ga+ Implantation Damage in the Fabrication of p+-n Si Shallow Junctions
Authors: Steckl A. J. , Lin C-M. , Patrizio D. , Rai A. K. , Pronko P. P. 
Published: March 2011

AbstractThe use of focused and broad beam Ga+ implantation for the fabrication of p+-n Si shallow junctions is explored. In particular, the issue of ion induced damage and its effect on diode electrical properties is explored. FIB-fabricated junctions exhibit a deeper junction with lower sheet resistance and higher leakage current than the BB-implanted diodes. TEM analysis exhibits similar amorphization and recrystallization behavior for both implantation techniques with the BB case generating a higher dislocation loop density after a 900°C anneal.