bluuebunny/crossref_metadata_2025_split huggingface dataset:
Amorphous Silicon Solar Cells With Silver Nanoparticles Embedded Inside the Absorber Layer
Authors: Santbergen Rudi , Liang Renrong , Zeman Miro 
Published: August 2010

AbstractA novel light trapping technique for solar cells is based on light scattering by metal nanoparticles through excitation of localized surface plasmons. We investigated the effect of metal nanoparticles embedded inside the absorber layer of amorphous silicon solar cells on the cell performance. The position of the particles inside the absorber layer was varied. Transmission electron microscopy images of the cell devices showed well defined silver nanoparticles, indicating that they survive the embedding procedure. The optical absorption of samples where the silver nanoparticles were embedded in thin amorphous silicon layer showed an enhancement peak around the plasmon resonance of 800 nm. The embedded particles significantly reduce the performance of the fabricated devices. We attribute this to the recombination of photogenerated charge carriers in the absorber layer induced by the presence of the silver nanoparticles. Finally we demonstrate that the fabricated solar cells exhibit tandem-like behavior where the silver nanoparticles separate the absorber layer into a top and bottom part.
Synthesis of Silicon Nano-particles for Thin Film Electrodes Preparation
Authors: Munao David , Erven Jan van , Valvo Mario , Vons Vincent , Evirgen Alper , Kelder Erik 
Published: August 2010

AbstractThe present work concerns novel approaches to fabricate silicon-based electrodes. In this study silicon nano-particles are synthesized via two aerosol routes: Laser assisted Chemical Vapour Pyrolysis (LaCVP) and Spark Discharge Generation (SDG). These two techniques allow the generation of uniformly sized particles, with a good control over the composition and the range of sizes. Herein, particles with size ranging from 2 to 70 nm were obtained. Starting from these nano-particles, nano-structured porous thin films are produced either by electrospraying a polymeric solution in which LaCVP-produced particles were previously dispersed, or by inertial impacting the SDG-produced particles directly from gas phase onto a substrate. The Electro- Spray (ES) is used to produce composite films for Li-ion battery applications, whereas the Inertial Impaction (II) is used to produce pure silicon films for other purposes (i.e.: sensors).
Float Foil Growth of Si-Foils for Solar Cell Applications
Authors: Cohen Uri , Roitberg Michael 
Published: August 2010

AbstractA new Float Foil Growth (FFG) technique has been demonstrated for growing thin Si foils from molten metal solvent, such as molten indium (In) or tin (Sn), at temperatures below 1,000°C. Si source is first dissolved to saturation (or close to saturation) in a molten metallic bath (or solvent) at a temperature T2 (T2 ≤ 1,000°C), and the molten bath is then cooled to T1, where T2 » T1. Due to lower solubility of Si at T1 than at T2, Si separates (or is driven) out of solution and, due to its much lower density than that of the molten metallic bath, it floats to the top of the melt to form a floating thin Si-foil. The thickness of the Si foil is determined primarily by T2, the dissolution temperature (i.e., Si solubility at T2), and the depth of the molten bath. This paper reports preliminary results demonstrating the utility of the FFG technique for growing Si-foils. Si foils with thickness range of 50-200μm were obtained from molten In baths. The Si foils were multicrystalline with crystalline (or grain) size of several millimeters, having a strong <111> preferred orientation. The Si-foils were very pure; with In (solvent) content as low as 14ppb. Other metallic impurities were below 0.1ppm, oxygen content was as low as 1.8ppm, and carbon content was below the detection level (50ppb). It is expected that large FFG thin Si-foils, when produced on large scale, will offer significant Si material cost and energy savings (> 80%), compared with conventional sliced Si wafers, with similar photovoltaic conversion efficiency.
Influence of Embedded a-Si:H Layer Location on Floating-gate a-Si:H TFT Memory Functions
Authors: Kuo Yue , Coan Mary 
Published: August 2010

AbstractThe influence of the location of the embedded a-Si:H layer in the gate dielectric film of the floating-gate a-Si:H TFT on the charge trapping and detrapping mechanisms has been investigated. The thin channel-contact SiNx gate dielectric layer favors both hole and electron trappings under the proper gate voltage condition. The sweep gate voltage affect the locations and shapes of forward and backward transfer characteristics curves, which determines the memory function. In order to achieve a large memory window, both the location of the embedded a-Si:H layer and the gate voltage sweep range need to be optimized.
Measure of carrier lifetime in nanocrystalline silicon thin films using transmission modulated photoconductive decay
Authors: Simonds Brian J. , Yan Baojie , Yue Guozhen , Dunlavy Donald , Ahrenkiel Richard K. , Taylor Craig 
Published: August 2010

AbstractWe present results of extremely short carrier lifetime measurements on a series of hydrogenated nanocrystalline silicon (nc-Si:H) thin films by a novel, non-destructive, non-contact method. Transmission modulated photoconductive decay (TMPCD) is a newly developed technique which appears to have high enough sensitivity and time resolution to measure the extremely short carrier lifetimes on the order of a nanosecond. As a proof of this, we measure various nc-Si:H samples of varying crystalline volume fraction as well as a fully amorphous sample. To ascribe an effective lifetime to the materials, we use a simple model which assumes a single exponential decay. By using this model, effective lifetimes can be deconvoluted from our pump beam giving nanosecond lifetimes. Lifetimes of between 1.9 and 0.9 nanoseconds are reported and trend to decreasing lifetimes as crystalline volume fraction is increased.
Molecular Dynamics Modeling of Stress and Orientation Dependence of Solid Phase Epitaxial Regrowth
Authors: Lai Haoyu , Sea Stephen M , Kennel Harold , Dunham Scott T 
Published: August 2010

AbstractSolid Phase Epitaxial Regrowth (SPER) is of great technological importance in semiconductor device fabrication. A better understanding and accurately modeling of its behavior are vital to the design of fabrication processes and the improvement of the device performance. In this paper, SPER was modeled by Molecular Dynamics (MD) with Tersoff potential. Extensive MD simulations were conducted to study the dependence of SPER rate on growth orientation and uniaxial stress. The results were compared with experimental data. It was concluded that MD with Tersoff potential can qualitively describe the SPER process. For a more quantitatively accurate model, a better interatomic potential are needed.
Threshold Voltage Shift Variation of a-Si:H TFTs With Anneal Time
Authors: Indluru Anil , Venugopal Sameer M , Allee David R , Alford Terry L 
Published: August 2010

AbstractHydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used in many areas and the most important application is in active matrix liquid crystal display. However, the instability of the a-Si:H TFTs constrains their usability. These TFTs have been annealed at higher temperatures in hope of improving their electrical performance. But, higher anneal temperatures become a constraint when the TFTs are grown on polymer-based flexible substrates. This study investigates the effect of anneal time on the performance of the a-Si:H TFTs on PEN. Thin-film transistors are annealed at different anneal times (4 h, 24 h, and 48 h) and were stressed under different bias conditions. Sub-threshold slope and the off-current improved with anneal time. Off-current was reduced by two orders of magnitude for 48 hours annealed TFT and sub-threshold slope became steeper with longer annealing. At positive gate-bias-stress (20 V), threshold voltage shift (∆Vt) values are positive and exhibit a power-law time dependence. High temperature measurements indicate that longer annealed TFTs show improved performance and stability compared to unannealed TFTs. This improvement is due to reduction of interface trap density and good a-Si:H/insulator interface quality with anneal time.
Al-mediated Solid-Phase Epitaxy of Silicon-On-Insulator
Authors: Sakic Agata , Civale Yann , Nanver Lis K. , Biasotto Cleber , Jovanovic Vladimir 
Published: August 2010

AbstractSilicon-on-insulator (SOI) regions have been grown on lithographically predetermined positions by Al-mediated Solid-Phase Epitaxy (SPE) of amorphous silicon (α-Si). A controllable Si lateral overgrowth is induced from windows formed in silicon dioxide (SiO2) to the crystalline Si substrate. The resulting hundred of-nanometer large areas of high-quality monocrystalline SOI are formed at the temperatures that can be as low as 400 °C. The as-obtained SOI regions were found to take on the same crystal orientation as the (100) Si substrate and have the ability to merge seamlessly over the oxide.
N-type Microcrystalline Silicon Oxide (μc-SiOx:H) Window Layers with Combined Anti-reflection Effects for n-i-p Thin Film Silicon Solar Cells
Authors: Smirnov Vladimir , Boettler Wanjiao , Lambertz Andreas , Astakhov Oleksandr , Carius Reinhard , Finger Friedhelm 
Published: August 2010

AbstractWe will describe the development and application of n-type microcrystalline silicon oxide (μc-SiOx:H) alloys as window layers in thin film silicon solar cells with microcrystalline silicon (μc-Si:H) absorber layers. Cells are prepared in n–i–p deposition sequence with illumination through the n-side. The layers were deposited by radio-frequency plasma enhanced chemical vapour deposition (RF-PECVD) at 185°C substrate temperature, using a mixture of phosphine (PH3), silane (SiH4), carbon dioxide (CO2) and hydrogen (H2) gases, at CO2flows varied between 0.5 and 2 sccm and different thickness. Films were characterised by dark conductivity measurements, Photothermal Deflection Spectroscopy (PDS) and Raman spectroscopy to evaluate optical band gap E04, refractive index n and crystallinity ICRS, respectively. The results were compared with the data of alternative optimised window layers, such as n-type μc-Si:H and silicon carbide (μc-SiC:H) films. Also solar cells with conventional illumination through the p-side window were investigated for comparison. Solar cells were prepared with μc-SiOx:H n-layers of varied compositions and characterised by current-voltage (J-V) measurements under AM 1.5 illumination (and also under modified AM 1.5 illumination with red (OG590) and blue (OG7) filters) and reflectance measurements. The effects of the μc-SiOxn-layer composition and thickness on the performance of n-i-p cells were investigated and correlated with the optical, electrical and structural properties of the μc-SiOx:H n-layers. The results indicate that n-type μc-SiOx:H provides a sufficient combination of conductivity (up to 0.1 S/cm) and crystallinity (ICRS up to 30%) to function well as a doped layer for the internal electric field and the carrier transport and as a nucleation layer for the growth of the μc-Si:H i-layer. As a window layer, it also results in an enhanced spectral response, particularly in the long wavelength part of the spectrum of the solar cells, in comparison with the cells containing alternative window layers. An improved short circuit current density (Jsc) can be attributed to the wide optical gap E04 (around 2.3 eV) in the μc-SiOx:H window layers and reduced reflection in the long wavelength region of the spectrum. A minimum total reflectance of only 6% at 570nm wavelength was achieved with such μc-SiOx:H window layers. Using optimised n-type μc-SiOx:H as a window layer, an efficiency of 8.0% for 1cm2cell area was achieved with 1 μm thick μc-Si:H absorber layer and Ag back reflector.
Defect Reduction in SiC Growth Using Physical Vapor Transport
Authors: Hansen Darren , Loboda Mark J , Drachev Roman Victorovich , Sanchez Edward , Zhang Jie , Carlson Eric P , Wan Jianwei , Chung Gil 
Published: August 2010

Abstract4H SiC is a promising material because of its mechanical, electrical, and physical properties. However, SiC material defects have had a rate limiting effect on the widespread adoption of SiC. Micropipes, basal plane dislocations (BPD), elementary screw dislocations (SDD) and threading edge dislocations (TED) have all been identified as limiting to device operation and/or performance. An ideal PVT strategy for manufacturing SiC crystals would be capable of driving defects out the crystal via a combination of thermal field control and defect dissociation pathways. In this work a PVT technology was realized which is capable of continuously improving the crystal quality. A low defect PVT process was conceived and optimized using iterative experiment and simulation methods. During the maturation of the process it was observed that the crystal defect density repeatedly decreased relative to the seed crystal, as evaluated by x-ray topography, x-ray diffraction, and molten salt etching. The process improvements were leveraged successfully to achieve 4H n+ SiC wafers at 76-100 mm diameter with MPD <1 cm-2, SDD <500 cm-2, and BPD <500 cm-2. This paper will illustrate the defect reduction pathways leading to state of the art defect density 4H SiC crystals and the impact of the improved crystal on epitaxy defects and simple device experiments.
a-SiC:H Based Devices as Optical Demultiplexers
Authors: Louro Paula , Vieira Manuela , Costa João , Vieira M. A. , Fernandes Miguel , Fantoni Alessandro , Barata Manuel 
Published: August 2010

AbstractIn this paper we present results on the use of a multilayered a-SiC:H heterostructure as a wavelength-division demultiplexing device (WDM) for the visible light spectrum. The WDM device is a glass/ITO/a-SiC:H (p-i-n)/ a-SiC:H(-p) /Si:H(-i)/SiC:H (-n)/ITO heterostructure in which the generated photocurrent at different values of the applied bias can be assigned to the different optical signals.The device was characterized through spectral response measurements, under different electrical bias. Demonstration of the device functionality for WDM applications was done with three different input channels covering wavelengths within the visible range. The recovery of the input channels is explained using the photocurrent spectral dependence on the applied voltage. The influence of the optical power density was also analysed.An electrical model, supported by a numerical simulation explains the device operation. Short range optical communications constitute the major application field, however other applications are also foreseen.
Diffusivity of Si in the 3C-SiC Buffer Layer on Si(100) by X-ray Photoelectron Spectroscopy
Authors: Chen Wei-Yu , Lin Jian-You , Hwang Jenn-Chang , Huang Chih-Fang 
Published: August 2010

AbstractA void free 3C-SiC film grown on Si(100) can be achieved by low pressure chemical vapor deposition using the modified four-step method. The diffusion step plays an important role to enhance the quality of the 3C-SiC buffer layer on Si(100). X-ray photoelectron spectroscopy was used to characterize the bonding characteristics of the 3C-SiC buffer layer of about 10 nm thick. The Si-C bonds are partially formed on the as-carburized Si(100) before the diffusion step. The ratio of C-C to Si-C bonds on the as-carburized Si(100) is about 7:3, which can be lowered to about 1:9 after the diffusion step at 1350 oC for 5 min or at 1300 oC for 7 min. According to XPS data and Fick's second law, the diffusivity of Si across the 3C-SiC interlayer are determined to be 2.2×10-16 cm2/s and 3.13×10-16 cm2/s at 1300°C and 1350°C, respectively. The derived activation energy is 1.6 eV for the diffusion of Si atoms in the 3C-SiC buffer layer.
Phosphorus Oxide Assisted n-type Dopant Diffusion in 4H-Silicon Carbide
Authors: Mendis Suwan P , Tin Chin-Che 
Published: August 2010

AbstractPhosphorus is an important n-type dopant for both silicon and silicon carbide. Although solid-state diffusion of phosphorus in silicon has been well documented and experimentally proven, not much is known about phosphorus solid-state diffusion in silicon carbide, especially at lower temperatures. A convenient source of phosphorus for solid-state diffusion in silicon carbide is phosphorus oxide. The possibility of using phosphorus oxide as a dopant source for silicon carbide is investigated by considering the probable reactions between silicon carbide and phosphorus oxide at temperatures below 1700 K using published thermodynamic data. By considering the standard free energies of reactions, it can be shown that phosphorus can be introduced in silicon carbide at temperatures below 1700 K using phosphorus oxide. A successful development of low temperature dopant incorporation in silicon carbide would reduce the need for high temperature processes and prevent process-induced thermal degradation of critical device structures such as the oxide-semiconductor interface. Experimental results showing phosphorus impurity incorporation and activation in 4H-SiC are presented.
Planarization Specification for 22nm and Beyond BEOL CMP
Authors: Choi Jihong , Wang Changan , Wei Yayi , Zielinski Eden , Tseng Wei-tsu , Moon Yongsik , Kelling Mark , Economikos Laertis 
Published: August 2010

AbstractThis study discusses topography specifications for 22 nm and beyond CMP process and presents recent experimental data. We evaluated local topography impact on CD development in the subsequent layer using specially designed 22-nm test patterns. A wide range of localized erosions were generated in CMP within a single exposure field to avoid any focus-correction effect by the scanner or any other scanner-induced focus change between different levels of local erosion. Local erosions were measured by atomic force microscopy (AFM) after each process step from CMP to lithography to identify the local planarization effect from other film coatings between CMP and lithography. Post-litho CD inspection was done in the subsequent layer over the local erosion areas. Using experimental results, the paper also discusses BEOL pattern design rule for maximizing the process window.
High Removal Rate CMP Process on TSV Thick Cu Overburden
Authors: Caramto Raymond , Qureshi Jamal , Mase Jerry 
Published: August 2010

AbstractIn 3D packaging, Through Silicon Vias (TSVs) with high aspect ratios and depths measuring tens of microns are filled by advanced Cu electroplating processes. Today's 300mm TSV plating platforms are intended to produce bottom-up via fill, no seam voids, and minimal, controlled overburden. To achieve this, the preceding Cu-seed coverage must be continuous at a constant resistance, and the plating chemistries optimized. However, other factors such as hardware configurations and simple depletion of the plating formulations during the extended TSV process can lead to high Cu overburden thickness requiring a high removal rate (HRR) chemical-mechanical polish (CMP) process to remove the thick Cu layer.Presented here are CMP results of a thick Cu overburden (~6um) resulting from the fill of 5 x 25um TSVs on 300mm wafers. The goal is to uniformly polish the overburden and utilize the tool's endpoint system at Cu clear before the next step of conventional barrier CMP. Slurries were screened for removal rate, uniformity, planarization ability, and defectivity. This study focuses on achieving a removal rate of >2.5um/min through evaluation of several commercial slurries in a multi-step polish application. Cross-sections post-plating show the Cu overburden, barrier and liner layer. Cross-sections post-CMP quantify Cu recess, dielectric loss, and presence/absence of seam defects. The process selected is demonstrated to achieve good planarization results with low occurrence of polish defects, at a rate and selectivity suitable for emerging 3D TSV Cu CMP applications.
An Alternative Non-contact Planarization Technique by Utilizing the Electrokinetic Phenomenon
Authors: Butler David , Leo Cheng Seng , Ng Sum Huan , Danyluk Steven 
Published: August 2010

AbstractIn this paper, the authors introduce and present some findings on an alternative non-contact material removal technique. Material removal is made possible by utilizing the electrokinetic and hydrodynamic effects of suspended particles to manipulate their trajectories to impact onto the surface of the workpiece. The research was previously demonstrated and reported where the removal rate can be precisely controlled by varying the electrical field and the flow rate of the slurry across the surface of the workpiece. New findings are reported on the application of the technique to different materials that will highlight the attractiveness of this alternative approach to producing surfaces with roughness in the order of nanometres.
Characterization and Modeling of Pad Asperity Response in CMP
Authors: Boning Duane , Fan Wei 
Published: August 2010

AbstractA model is proposed to understand the interactions between CMP pad asperities and the wafer. Pad asperity reduced modulus and height distribution are included in the model. Physical measurements of asperity properties are performed: asperity reduced modulus is measured by nanoindentation, and pad asperity height distribution is scanned by profilometry. The measured results are used in the model to predict the contact area percentage between the pad and wafer in the CMP process.
Copper Migration During Tungsten via Formation
Authors: Gambino Jeff , Cooney Ed , Murphy Will , Luce Cameron , Mongeon Steve , Lai Ning , Zwonik Bob , Anderson Felix , Schutz Laura , Lee Tom C , McDevitt Tom 
Published: August 2010

AbstractA yield problem is observed with tungsten vias formed on copper interconnects. Copper migration can occur during chemical vapor deposition (CVD) of tungsten, if there are defects in the liner inside the via. Copper can react quickly with SiH4during the early stages of tungsten deposition, when SiH4-reduction of WF6 is used. Under severe conditions, large amounts of copper diffuse out of the underlying metal layer, resulting in copper silicide formation in the via and leaving voids in the copper wire. Copper migration can be minimized by reducing the time that the wafers are exposed to SiH4.
Towards the Understanding of Resistive Contrast Imaging in in-situ Dielectric Breakdown Studies Using a Nanoprober Setup
Authors: Lambrinou Konstantina , Arstila Kai , Hantschel Thomas , Rummel Andreas , Tőkei Zsolt , Pantouvaki Marianna , Croes Kristof , Czarnecki Piotr , Carbonell Laure , Richard Olivier , Kleindiek Stephan , De Wolf Ingrid , Vandervorst Wilfried 
Published: August 2010

AbstractThis work aims at attaining a more complete understanding of the principles governing resistive contrast imaging (RCI) of copper/low-k interconnects used for dielectric breakdown studies in a nanoprober scanning electron microscope (SEM) system. RCI is employed in such in situ dielectric breakdown studies to facilitate the localization of interconnect defect sites related to various stages in the degradation process of the low-k dielectric material. This work shows that RCI is suitable for detecting high-resistance sites, like opens, in copper/low-k interconnects. Moreover, RCI demonstrates potential in locating defects that lie deep in the test structure and are, thus, not detectable by SEM. A model is also proposed to explain the formation of RCI images of specific interconnect test structures with complex layout.