bluuebunny/crossref_metadata_2025_split huggingface dataset:
Numerical Simulation of Microcrystalline Silicon Growth on Structured Substrate
Authors: Python Martin , Vallat-Sauvain Evelyne , Bailat Julien , Ballif Christophe , Shah Arvind 
Published: April 2011

AbstractThe growth of thin-film silicon close to the amorphous/microcrystalline transition is qualitatively described by a 3D - discrete dynamical growth model on a cubic lattice. The result of this simulation is a representation of the microstructure of the layer as a function of time, i.e. computer-generated animations of growing microcrystalline silicon layers. It permits to follow the evolution of the nucleation and of the growth of the crystalline phase, the surface roughness, the average crystalline volume fraction and the void volume fraction. In these computer simulations, the effects of the substrate surface morphology and of the distribution of particles incidence angle have been studied.Comparison between simulated normal and isotropic incidence on structured substrates indicates that, under microcrystalline growth conditions, shadowing effects lead to the occurrence of cracks in the simulated microstructure. These effects are also evidenced experimentally in the case of &#956;c-Si:H silicon layers deposited by very high frequency plasma-enhanced chemical vapour deposition (VHF-PECVD) on periodic and random nanostructured substrates.
Fast Deposition of Highly Crystallized Microcrystalline Si Films Utilizing a High-Density Microwave Plasma Source for Si Thin Film Solar Cells
Authors: Jia Haijun , Shirai Hajime , Kondo Michio 
Published: April 2011

AbstractIn this work, we investigate the influences of source gas supply method and dc substrate bias on the deposition rate as well as structural properties of &#956;c-Si films and demonstrate the high rate synthesis of highly crystallized &#956;c-Si films with improved film density by using a high-density and low-temperature microwave plasma source. A high flux of SiH3 and atomic hydrogen on film growing surface achieved through adjusting SiH4 gas supply configuration is effective for the fast deposition of highly crystallized &#956;c-Si films and for the improvement of film mass density. Appropriate ion bombardment under moderate negative dc substrate bias along with the suppression of contributions of detrimental species to film growth also account for the improvement in properties of resulting films. As a consequence, a very fast deposition rate of ~65 Å/s was achieved with a high Raman crystallinity Ic/Ia>3 and a low defect density of (1-2)×1016 cm-3 despite a high silane concentration of 67%.
Amorphous Silicon as an Active Material in Optical Resonators
Authors: Hohlfeld Dennis , Zappe Hans 
Published: April 2011

AbstractThe application of amorphous silicon as a thermo-optically active material in MEMS-based, tunable optical filters is presented. The thin film interference filter employs a solid-state silicon cavity and silicon-based distributed Bragg reflectors (DBR). Tuning is achieved by varying the the resonator's refractive index and thus its optical thickness through thermal modulation. The filter is configured as a membrane and operates up to a temperature of 450 °C. Such a filter is essential for monitoring and reconfiguration of optical data communication networks and is also applicable for chemical and gas sensing.
Role of the Oxide Layer on the Performances of a-Si:H Schottky Structures Applied to PDS Fabrication
Authors: Aguas Hugo , Pereira Luis , Costa Daniel , Raniero Leandro , Fortunato Elvira , Martins Rodrigo 
Published: April 2011

AbstractIn this work we present results of studies performed on Schottky and MIS (metal-insulator – semiconductor) PSD (position sensitive detectors) structures: substrate (glass)/ Cr (300 nm) / a-Si:H [n] (37 nm) / a-Si:H [i] (600 nm) / SiO2 (1.5 nm – for the MIS) / Au (7 nm). The effect of the interfacial oxide layer between Au and a-Si:H, for the MIS structures, was studied and compared with the Schottky, in order to determine how beneficial it could be for device performances and time degradation. For doing so, the Au thickness of 70Å was deposited by thermal evaporation on an oxide free (Schottky) and oxidized (20Å) (MIS) a-Si:H surfaces. These structures were characterized by SIMS, RBS, SEM and AFM in order to correlate the obtained diffusion profile of Au at the interface and the topography with the presence of the oxide at the interface. The results show that the Au inter-diffuses very easily in the oxide free a-Si:H surface, even at room temperature, degrading the devices performance. On the other hand, the MIS structures, with their interfacial oxide present no structural changes after annealing and the PSD produced are stable. We believe that this effect is associated with the barrier effect of the interfacial oxide that prevents the Au diffusion. The optimized 1D MIS sensors are stable and exhibit a linearity error as low as 0.8 % and sensitivities of 33 mV/cm for a 5 mW spot beam intensity at a wavelength of 532 nm, while the Schottky sensors showed a time degradation of their characteristics.
Un-cooled Micro-bolometer with Sandwiched Thermo-sensing Layer Based on Ge Films Deposited by Plasma
Authors: Kosarev Andrey , Moreno Mario , Torres Alfonso , Ambrosio Roberto 
Published: April 2011

AbstractWe have fabricated and studied an un-cooled micro-bolometer with thermo-sensing layer sandwiched between two electrodes. The micro-bolometer has “bridge” configuration to provide sufficient thermo isolation of the thermo-sensing layer and is made on the surface of silicon wafer by means of surface micro-machining technique. The support layer of SiN and thermo-sensing layer of a-Ge:H,F have been deposited by low frequency PE CVD. The active area of the thermo-sensing layer is Ab=70x66 &#956;m2. Temperature dependence of conductivity &#963;(T), current-voltage characteristics I(U), spectral noise density and thermal response time have been measured to characterize operation and to determine main performance characteristics. Activation energy of the thermo-sensing layer was Ea=0.34 eV providing thermal coefficient of resistance &#945;=0.043 K-1. Pixel resistance was in the range Rb=(1÷30)x105 Ohm. Current and voltage responsivities were in the range RI=0.3÷14 AW-1 and RU=(1÷2)x105 VW-1, respectively. The value of detectivity was in the range of D*=(1÷40)x108 cmHz1/2W-1 and response time was &#964;=100 &#956;s. The characteristics obtained in this micro-bolometer with sandwiched thermo-sensing layer make it promising for further development.
Dynamic Measurements of MEMS-Based Field Effect Transistors Using Scanning Capacitance Microscopy
Authors: Anderson Meredith L. , Young R.W. , Nakakura C.Y. 
Published: April 2011

AbstractIn this research, we have employed scanning capacitance microscopy (SCM) to image 2D carrier profiles of a MEMS device. Multiple device states are exercised and examined for changes in carrier response as a function of applied bias. First, experimental and simulated dopant profiles of the source and drain pn junctions were measured with device contacts grounded. Their comparison revealed good agreement. Scanning capacitance microscopy was then used to image changes in carrier distribution within the channel of the device while independent bias voltages were applied to the source, gate, drain, and well regions. Device operation was confirmed by simultaneously measuring the drain current. The SCM image contrast directly beneath the gate was observed to change as a function of applied gate bias voltage.
Ambipolar Thin-Film Transistors Fabricated by PECVD Nanocrystalline Silicon
Authors: Lee Czang-Ho , Sazonov Andrei , Rad Mohammad R. E. , Chaji G. Reza , Nathan Arokia 
Published: April 2011

AbstractWe report on directly deposited plasma-enhanced chemical vapor deposition (PECVD) nanocrystalline silicon (nc-Si:H) ambipolar thin-film transistors (TFTs) fabricated at 260 °C. The ambipolar operation is achieved adopting Cr metal contacts with high-quality nc-Si:H channel layer, which creates highly conductive Cr silicided drain/source contacts, reducing both electron and hole injection barriers. The n-channel nc-Si:H TFTs show a field-effect electron mobility (meFE) of 150 cm2/Vs, threshold voltage (VT) ~ 2 V, subthreshold slope (S) ~0.3 V/dec, and ON/OFF current ratio of more than 107, while the p-channel nc-Si:H TFTs show a field-effect hole mobility (mhFE) of 26 cm2/Vs, VT ~ -3.8 V, S ~0.25 V/dec, and ON/OFF current ratio of more than 106. Complementary metal-oxide-semiconductor (CMOS) logic integrated with two ambipolar nc-Si:H TFTs shows reasonable transfer characteristics. The results presented here demonstrate that low-temperature nc-Si:H TFT technology is feasible for total integration of active-matrix TFT backplanes.
An Asymmetric Dual Gate Poly-Si TFTs for Improving Hot Carrier Stress Stability and Kink Effect Suppression
Authors: Park Joong Hyun , Nam Woo Jin , Lee Jae Hoon , Han Min Koo 
Published: April 2011

AbstractAn asymmetric dual gate poly-Si thin film transistors (TFTs), which is consist a long-gate TFT and a short-gate TFT, were fabricated in order to suppress the kink current and increase the reliability. The long-gate TFT operates in a linear regime and limits the total current flow by its current operation region. The asymmetric dual-gate does not exhibit from the kink current in a high drain bias due to the distribution of lateral electric field. The asymmetric dual-gate structure improves kink-free characteristics compared with conventional single and dual-gate TFTs. The hot-carrier stress reliability is successfully improved due to kink current suppression.
A Novel Self-Aligned Field Induced Drain Polycrystalline Silicon Thin Film Transistor Fabricated by using a Selective Side Etch Process
Authors: Liao Ta-Chuan , Wu Chun-Yu , Chien Feng-Tso , Tsai Chun-Chien , Chen Hsiu-Hsin , Kung Chung-Yuan , Cheng Huang-Chung 
Published: April 2011

AbstractA novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with vacuum gaps has been proposed and fabricated only with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. Experimental results reveal that the proposed T-Gate poly-Si TFTs have excellent electrical performance, which has higher maximum on-off current ratio of 4.6 e107, and the lower off-state leakage current at VGS = -10 V and VDS = 5V of about 100 times less than that of the conventional one. It is attributed to the additional undoped offset region and the vacuum gap to reduce the maximum electric field at drain junction while ascribed to the sub-gate to maintain the on-current. Therefore, such a T-Gate poly-Si TFT is very suitable for the applications and manufacturing in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs).
Novel approaches of light management in thin-film silicon solar cells
Authors: Krc Janez , Zeman M. , Campa A. , Smole F. , Topic M. 
Published: April 2011

AbstractIn order to improve light trapping in thin-film silicon solar cells two novel approaches are investigated in this article: angle-selective management of light scattering inside the solar cell and wavelength-selective manipulation of high reflectance or transmittance of light. Diffraction gratings are analyzed as a representative of the first approach. Haze and angular distribution function of scattered (diffracted) light in reflection are measured for aluminum-based rectangular periodic gratings with different period and height of the rectangles. High haze values in specific wavelength region and scattering angles of the investigated gratings measured in air and water agree very well with the theoretical predictions. Considering the actual optical situation in microcrystalline silicon solar cells, optimal period and height of the rectangular gratings applied as a back reflector are calculated for obtaining the total reflection at the front interfaces. In the frame of the second approach, photonic-crystal-like structures are introduced. By means of optical simulations photonic-crystal-like structures are investigated for two possible applications: an intermediate reflector in a micromorph silicon solar cell with wavelength-selective reflectivity and a dielectric back reflector with a high reflectance in the long-wavelength region. The photonic crystal structure consisting of sequences of n-doped amorphous silicon and ZnO layers is designed for the efficient intermediate reflector. For the back reflector with a high reflectance the structures with intrinsic amorphous silicon, SiO2, MgF2 and TiO2 are proposed.
Thin-film polycrystalline-silicon solar cells on high-temperature glass based on aluminum-induced crystallization of amorphous silicon
Authors: Van Gestel Dries , Gordon Ivan , Carnel Lode , Pinckney Linda R. , Mayolet Alexandre , D'Haen Jan , Beaucarne Guy , Poortmans Jef 
Published: April 2011

AbstractEfficient thin-film polycrystalline-silicon (pc-Si) solar cells on foreign substrates could lower the price of photovoltaic electricity. Aluminum-induced crystallization (AIC) of amorphous silicon followed by epitaxial thickening at high temperatures seems a good way to obtain efficient pc-Si solar cells. Due to its transparency and low cost, glass is well suited as substrate for pc-Si cells. However, most glass substrates do not withstand temperatures around 1000°C that are needed for high-temperature epitaxial growth. In this paper we investigate the use of experimental transparent glass-ceramics with high strain-point temperatures as substrates for pc-Si solar cells. AIC seed layers made on these substrates showed in-plane grain sizes up to 16 μm. Columnar growth was observed on these seed layers during high-temperature epitaxy. First pc-Si solar cells made on glass-ceramic substrates in substrate configuration showed efficiencies up to 4.5%, fill factors up to 75% and open-circuit voltage (Voc) values up to 536 mV. This is the highest Voc reported for pc-Si solar cells on glass and the best cell efficiency reported for cells made by AIC on glass.
Ultra Shallow Junctions Optimization with Non Doping Species Co-implantation
Authors: Cagnat Nathalie , Laviron Cyrille , Mathiot Daniel , Duriez Blandine , Singer Julien , Gwoziecki Romain , Salvetti Frédéric , Dumont Benjamin , Pouydebasque Arnaud 
Published: April 2011

AbstractThe permanent decrease of the transistor size to improve the performances of integrated circuits must be accompanied by a permanent decrease of the depth of the source-drain junctions. At the same time, in order to keep acceptable sheet resistance values, the dopant concentration in the source-drain areas has to be continuously increased. A possible technological way to meet the junction depth and abruptness requirements is to use co-implantation of non doping species with classical implantations, especially for light ions as B or P.In order to clarify the complex interactions occurring during these co-implantation processes, we have performed an extensive experimental study of the effect of Ge, F, N, C and their combinations on boron. A special interest was given to the overall integration issues. We will show that it is required to optimize the respective locations of co-implanted species with respect to the B profiles (more precisely the ion implantation damage locations), as well as the co-implanted species doses, to get an acceptable compromise between the efficient diffusion decrease required for the junction abruptness and depth, and a reasonable current leakages.
Effect of Varying Dwell Time During Non-melt Laser Annealing of Boron Implanted Silicon
Authors: Zeenberg Daniel , Jones Kevin S , Felch Susan B , Parihar Vijay 
Published: April 2011

AbstractAs the fabrication for the CMOS technology trends to decreasing the size of transistors for the benefit of increased performance and device density, the implant and annealing process technologies are being forced to meet increasingly challenging demands for ultra-shallow junctions. As the current annealing preferences shift from rapid thermal annealing toward sub-second RTP technologies such as flash and laser annealing, the dynamics of micro-structural evolution on the order of milliseconds and microseconds become of increasing importance. To investigate the kinetics in this ultra-fast annealing regime, this study investigated the effect of varying the temperature and time of a scanning laser anneal in the millisecond and microsecond timeframe. Amorphous layers were created in silicon substrates using a 30 keV silicon implant at a dose of 1x1015 ions/cm3. These wafers were then processed using a scanning continuous wave near infra-red laser at varying temperatures and scan rates in order to vary the dwell time of each condition. A combination of sheet resistance, optical interferometry, and secondary ion mass spectrometry characterization techniques were used in order to investigate the activation and diffusion of these laser annealed samples. The regrowth temperature across all samples showed a positive correlation to the sheet resistance; trending toward lower values as temperatures increased. Dwell time, however, showed an inverse effect at lower temperatures. The microsecond anneal at 1200 °C showed a lower Rs than the millisecond anneal, while at higher temperatures the trend reversed. This trending shows an obvious competition between activation and diffusion mechanisms and their dependence on regrowth temperature.
Issues and Optimization of Millisecond Anneal Process for 45 nm node and beyond
Authors: Adachi Kanna , Ohuchi Kazuya , Aoki Nobutoshi , Tsujii Hideji , Ito Takayuki , Itokawa Hiroshi , Matsuo Koji , Yoshinori Honguh , Tamaoki Naoki , Ishimaru Kazunari , Ishiuchi Hidemi 
Published: April 2011

AbstractWe have investigated MSA, namely, Laser Spike Annealing (LSA) and Flash Lamp Annealing (FLA), dopant activation technology of source/drain extension for 45 nm node, which can be substituted for spike RTA. Since it is possible to achieve a similar relation between a sheet resistance and a junction depth by using either FLA or LSA, both annealing methods are capable of providing the junction characteristics required by the ITRS target. However, we have noticed that there are three crucial issues from the viewpoints of device integration and CMOSFET performance: junction leakage current, gate leakage current and pattern dependence. In this report, we discuss these issues and indicate how to cope with them.
Amorphization/templated Recrystallization (ATR) Method for Hybrid Orientation Substrates
Authors: Saenger K. L. , de Souza J.P. , Fogel K.E. , Ott J.A. , Reznicek A. , Sung C.Y. , Yin H. , Sadana D.K. 
Published: April 2011

AbstractHybrid orientation substrates make it possible to have a CMOS technology in which nFETs are on (100) Si (the Si orientation in which electron mobility is the highest) and pFETs are on (110)-oriented Si (the Si orientation in which hole mobility is the highest). This talk will describe a new amorphization/templated recrystallization (ATR) method for fabricating bulk hybrid orientation substrates. In a preferred version of this method, a silicon layer with a (110) orientation is directly bonded to a Si base substrate with a (100) orientation. Si regions selected for an orientation change are amorphized by ion implantation and then recrystallized to the (100) orientation of the base substrate. After an overview of the ATR technique and its various implementations, we will describe some of the scientifically interesting materials and integration challenges encountered while reducing it to practice.
Evidence of Reduced Self Heating with Partially Depleted SOI MOSFET Scaling
Authors: Guegan Georges , Gwoziecki Romain , Gonnard Olivier , Gouget Gilles , Raynaud Christine , Casse Mikael , Deleonibus Simon 
Published: April 2011

AbstractThe temperature rise in SOI has been measured on two successive generations. This work shows that self-heating effects become less and less severe with both MOSFET and power supply voltage scaling.
Impact of Pore Size and Morphology of Porous Organosilicate Glasses on Integrated Circuit Manufacturing
Authors: O'Neill Mark , Haas Mary K , Peterson Brian K , Vrtis Raymond N , Weigel Scott J , Wu Dingjun , Bitner Mark D , Karwacki Eugene J 
Published: April 2011

AbstractPorous organosilicate materials produced by plasma enhanced chemical vapor deposition are the leading candidates for back-end-of-line dielectric insulators for IC manufacturing at 45nm design features and beyond. The properties of porous organosilicate glass films of dielectric constant k=2.50 ± 0.05 formed using diethoxymethylsilane and five different porogen precursors with an ultraviolet post treatment are reported. By varying the porogen precursor type pore sizes of 1-2 nm (equivalent spherical diameter) and porosities in the range of 24-31% were measured. While there were no observable trends in pore size with the molecular volume or plasma reactivity of the porogen precursor, modulus values ranged from 6.6 to 10.8 GPa. Porous films with the highest mechanical properties were found to have the highest matrix dielectric constant, highest network connectivity (lowest methyl content), and highest density. Within this process space, maximizing the network connectivity of the film was found to be more important to mechanical properties than lowering the total porosity. In effect, the choice of porogen precursor dictates the film morphology through its impact on the organosilicate glass matrix and pore size.
Fracture Property Improvements of a Nanoporous Thin Film via Post Deposition UV Curing
Authors: Jacques Jeannette M. , Tsui Ting Y. , McKerrow Andrew J. , Kraft Robert 
Published: April 2011

AbstractAs silicon-based microelectronic devices continue to aggressively scale down in size, traditional BEOL dielectric materials have become obsolete due to their relatively high dielectric constant. Organosilicate glass (OSG) materials have emerged as the predominant choice for intermetal dielectrics in advancing technology nodes. A potential failure mechanism for this class of low-k dielectric films during the manufacturing process is catastrophic fracture due to channel cracking. To improve the mechanical strength and stability of these silicon-based materials, the use of post-deposition curing processes is under evaluation. In this work, the effects of UV curing on the properties of OSG films were characterized. After UV curing, film hardness and elastic modulus are improved, with no change in the residual film stress. The average film density increases linearly as a function of UV exposure time. Channel crack propagation velocities decrease with UV exposure. The improvements in the mechanical properties of OSG films are believed to correlate with the increasing Si-O-Si bond population. Comparisons between post-deposition UV and Electron Beam curing processes are provided.
Detection of Copper and Water in Low-k Dielectrics by Triangular Voltage Sweep Measurements
Authors: Ciofi Ivan , Tökei Zsolt , Saglimbeni Marco , Van Hove Marleen 
Published: April 2011

AbstractMetal-Insulator-Semiconductor (MIS) planar capacitors were fabricated in order to systematically investigate the effect of Cu and water in Cu/low-k structures by Triangular Voltage Sweep (TVS) measurements. We were able to resolve peculiar features in the TVS traces of Cu and water contaminated samples, which were related to Cu ions and protons, respectively. We demonstrate that these features can be used to distinguish the two ionic species. As these features do not depend on the specific dielectric, we provide a methodology to detect and distinguish Cu and water in porous low-k materials embedded in MIS structures.