bluuebunny/crossref_metadata_2025_split huggingface dataset:
Design for Solder Joint Fatigue Life of BGA Package Subject to Mechanical Environment
Authors: Lan Jia-Shen , Wu Mei-Ling 
Published: October 2015

There has been a dramatic proliferation of research concerned with thermal stress in electronic package for the last three decades. Moreover, reviewing the mechanical bending during printed circuit board (PCB) assembly has become important in the reliability assessment of modern electronic systems. The primary research demonstrates that the assessment approach can be applied successfully to the design model of a ball grid array (BGA) package with a more complete and accurate assessment model for solder joint fatigue life under mechanical bending. Previous research has focused mostly on the thermal analysis in electronic packages; however, most modern portable electronic products used in mobile devices, personal digital assistants, and aircraft have to endure extreme environments that involve not only thermal but also mechanical bending conditions. Initially, mechanical bending tests were conducted to demonstrate the reliability of the electronic packaging during the manufacturing and shipping process. Currently, the microelectronic packaging faces mechanical bending when everyone uses his or her Smartphones. The mechanical bending occurs when the user touches the screen on the Smartphone. Therefore, interest in the mechanical bending of BGA packaging has increased with the uptake in mobile device use.
In this research, the analytical solution and finite element analysis (FEA) are both presented to investigate the solder joint fatigue life. The analytical solution is presented for a PCB assembly subjected to mechanical bending by taking the axial stress, shear stress, and moment of the solder joints with discontinuity function into account. A FEM is proposed to analyze the solder joint fatigue life and to investigate the reliability of solder joints in BGA packaging subjected to mechanical bending.
An overview of molded underfill in flip chip packaging applications
Authors: Roa Fernando 
Published: October 2015

Flip chip packaging is a wide-spread process used in high frequency, high IO count IC devices. It consists of joining the IC chip with the substrate using solder alloys or Cu pillars to form a continuous interconnection for the electronic signals to travel through. However, because during operation these devices dissipate heat, the temperature at the bumps interface rise and drop in cycles which cause thermal stress to build up due to the different thermal expansion of the materials. If left unchecked, these stresses will weaken and eventually cause fatigue failures. Therefore, stress absorbers are dispensed or underfilled to fill the gap between the substrate and the die. Underfills, as these materials are commonly known, are typically dispense as liquids using a variety of techniques like spraying, jetting, injection dispense, etc.
In this paper we'll discuss the benefits and challenges of a new type of process that integrates the overall encapsulation of the package with the underfill process in one single process step, called molded underfilling. We'll discuss this application for simple devices consisting of one IC chip and then extend the discussion towards more complex package configurations consisting of IC chips and passive components to demonstrate the flexibility and robustness of this new process solution.
Multipurpose Wire Bonding – Bumps, Wires, Combination Interconnects, and Operation Efficiency
Authors: Evans Daniel D. 
Published: October 2015

Today's multipurpose wire bonding machines are required to deliver a combination of wires, bumps, and specialty interconnects for RF, automotive, and optical markets with odd-form factor parts. These market production requirements are generally lower volume with a higher mix of products compared to typical high-volume semiconductor packaging of memory and logic. These markets also require multipurpose wire bonders to accommodate large work area, deep access, and a complex mix of bond surfaces, wire shapes, and bumps. The number of components in a package can vary from one with a few wires up to hundreds of components with thousands of wires. Programming methods, process development, traceability, and rework are different for customers using this class of bonder.
A survey of customer application cases shows the range of capabilities available to packaging engineers.
The four primary cases presented highlight the range of applications that can be handled for odd-form factor packages and specific areas of focus to maximize productivity for these classes of products.Case 1: Ball Bump Size and Shape Examples: acheiving 119μm down to 44μm bonded ball diameters and range of shapes.Case 2: Ambient Wire Bonding to a 6″ Tall Package: demonstrating allowable bonding volume and tooling flexibility plus the ability to bond Au with substrates at ambient temperature.Case 3: Batch Load Tray (Mechanical and Vacuum Clamping): allowing quick change over for radically different sized packages.Case 4: Complex High Part Count Packages: supporting alternate parts and alternate bonding wires, stand-off stitch, and security bonds require special features for programming and navigation methods to allow easy creation and navigation of complex programs for maximum productivity. Breakdown of timing and efficiency is provided showing programming efficiencies of 2X or better.
These cases will help packaging engineers extrapolate to their own cases and show how a multipurpose automatic wire bonder can be an effective way of automating or semi automating these manually or automatically presented packages for higher throughput, higher quality and consistency, and less labor usage for lower cost.
Thermally and Electrically Enhanced Wirebond BGA
Authors: Carpenter Burton , Low Boon Yew , Higgins Leo M. , Neelakantan Sriram , Wenzel Robert , Boyne Daniel 
Published: October 2015

Next-generation processors continue to demand more thermal and electrical performance from the package. Frequently, devices are designed into Flip Chip (FC) packages where the previous generations were in Wire Bond (WB) because FC typically provides superior thermal dissipation and lower package electrical parasitics than WB packages. However, FC packages usually have higher costs for mid-range IO (500–800).
An Enhanced WB BGA package has been designed with improved thermal and electrical performance compared to the industry standard TEPBGA-2 (Thermally Enhanced PBGA type 2). The 500μm barrier of mold compound between the die and heatspreader in the TEPBGA-2 is a major impediment to heat flow out of the package. By contrast, the Enhanced WB package uses post-mold attachment of a heat spreader that is adhesively bonded to the mold cap and thermally coupled to the die using a 40μm TIM (thermal interface material). Improvements to substrate design rules and the die attach process that enabled the Enhanced WB design to shorten bond wires by 40% and improved electrical performance.
Package thermal resistance, Theta-Ja, was verified by simulation and measurement to be 3C°/W lower than TEPBGA-2, that dissipates up to 15W in some end-use applications, approximately 2× the performance of TEPBGA-2. DDR set-up and hold time showed 30ps improvement by both simulation and measurement.
This paper will present the package design, thermal and electrical simulation and measurement results.
Effects of Copper Pattern Density and Orientation on the Modulus of BGA Substrates
Authors: Carpenter Burton , Yeung Betty , Yuan Yuan 
Published: October 2015

Substrate material properties directly impact package mechanical performance. Estimation of substrate mechanical properties based on each component layer provides maximum flexibility and better accuracy. The component materials of a BGA substrate are the fiberglass-reinforced epoxy layers, copper and soldermask. Even when the material properties (modulus and CTE) of each component are known, the behavior of the final substrate is not easily determined because factors such as copper density and pattern have significant effects. For example, the copper pattern may be oriented such that conductor traces run in one direction for a considerable length. The modulus in the direction parallel to the traces will be different from the modulus in the direction perpendicular to the traces. Package mechanical simulations typically do not mesh the details of the copper patterns, but rather average within each layer, thus neglecting the orientation effects. Therefore FEM (Finite Element Model) simulations may yield inaccurate stress and warpage results.
This study utilized a test vehicle (TV) to study the copper pattern density and orientation effect on substrate modulus. Each TV sample was a two-metal-layer copper-clad laminate designed with one of eight simple geometric patterns. One set of patterns had Cu traces running parallel in one direction, with varied metal densities of 0%, 25%, 50%, 75% and 100% respectively. Measurements were made both parallel and perpendicular to the trace orientation. Also studied were a pattern of holes (continuous metal plane with unconnected holes) and a dot pattern (unconnected circular metal pads).
Substrate flexural modulus measurements were made using two types of instruments: DMA and Instron. Data was collected from −65 to 260°C. FEM simulations which meshed the details of copper patterns were used to calculate the overall substrate modulus. These correlated better with the empirical data than simulations utilizing traditional layer averaging.
The copper pattern had significant effects; the substrate modulus was always much lower in the direction perpendicular to the traces than the modulus in the direction parallel to the traces. The amount varied depending on temperature, but could be as high as 35%. When measured parallel to the copper traces, the substrate modulus was observed to increase with copper pattern density as predicted by theoretical mixture rules. However, the substrate modulus in the direction perpendicular to the traces was not easily predicted theoretically. Therefore, more sophisticated averaging techniques and simulations are needed.
DEVELOPMENT OF AN ULTRA THIN DIE-TO-WAFER FLIP CHIP STACKING PROCESS FOR 2.5D INTEGRATION
Authors: Parès G. , Attard A. , Dosseul F. , N'Hari A. , Boillon O. , Toffanin L. , Klug G. , Simon G. 
Published: October 2015

3D integration relying on novel vertical interconnection technologies opens the gate to powerful microelectronic systems in ultra-thin packages answering the demand of the mobile market.
Among these, die-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by, in one hand, the increase of the die surface and the number of I/Os and, on the other hand, the reduction of the vertical dimensions. In our integration scheme we have achieved flip chip stacking (or Face to Face) of 35 μm ultra-thin dies with low stand-off (&lt; 15 μm) copper micro-bumps and tin-silver-copper solders (SAC).
Ultra-thin dies are prepared using dicing before grinding (DBG) technique. After DBG, plasma stress release process is applied to the backside of the singulated chips.
Copper μbump technology is challenging with this very low profile stacking since the current flip chip process is no longer adapted to this geometry and that the die flatness tolerance become very critical to obtain a high soldering yield.
Process improvements have been achieved on the copper pillar fabrication itself with several metallurgy stack configurations as well as new processes using damascene techniques.
Furthermore, innovative technologies have been deployed on the pick and place and collective soldering processes.
Intermetallic formation during reflow process is achieved through transient liquid phase (TLP) reaction leading to thorough consumption of the tin layer and to the formation of Cu6Sn5 and Cu3Sn compounds.
Capillary underfill is finally successfully applied in the narrow die-to-wafer gap by jetting technique.
After optimization, electrical tests show a very high yield close to 100% over a representative number of fully populated wafers.
Reliability tests have also been carried out at wafer level exhibiting no significant resistance increase or yield loss over 1000 thermal cycles between −40 and +125°C.
Long-term Electromigration Study of Lead-Free Flip-Chips with Solder Bumps with 50 μm or 60 μm Diameter Employing ENIG Surface Finish on Both Chip and Substrate Side
Authors: Gorywoda Marek , Dohle Rainer , Härter Stefan , Wirth Andreas , Goßler Jörg , Franke Jörg 
Published: October 2015

Electromigration behaviour of Pb-free solder joints in flip-chip interconnects is usually studied in highly accelerated, short-term experiments using high current density and temperature. Failures typically occur in bumps which are in cathode contact at the chip side. There are only a few published studies in which Electroless Ni-P/Immersion Au (ENIG) surface finish was used as under-bump-metallization (UBM) structure, e.g. [5].
This paper deals with the long-term electromigration behaviour of Pb-free SAC305 flip-chip solder joints with a pitch of 100 μm and solder bump diameters of 50 μm or 60 μm, respectively. The ENIG surface finish was used on both the substrate and chip side. Test specimens were subjected to several levels of temperature and current density and tested up to 16,000 hours. The life time data is summarized using Weibull and lognormal distribution.
The microstructure changes of interconnects in failed samples were subsequently investigated by SEM and EDX. Interconnects had failed due to consumption of Nickel, voids caused by electromigration, and Kirkendall void formation in the Ni-P-layer. The damage was asymmetric in respect to the current flow direction through the solder bumps and was most pronounced at the cathode side. Unexpectedly, however, the most severe damage occurred at the substrate and not at the chip side. We could show that - allowing for a few guidelines - lead-free flip-chip solder joints with 50 μm or 60 μm diameter have a sufficient electromigration life time for most applications.
The Next Level of Accurate Server Power Monitoring and Capping
Authors: Steele Jerry 
Published: October 2015

Accurate server power monitoring is essential in extracting the maximum financial benefit of server performance in the capped environment. Capping power errors leave money on the table.
A fully integrated solution has been developed double the measurement accuracy of server power monitoring. Some little known error sources will be discussed along with the methods for increasing measurement accuracy.
Furthermore, advanced data processing such as true running averaging along with a variety of settings for energy metering provide important parts of the processing for advanced power capping strategies.
Obtaining continuous, rapid power data is only handicapped by the popular I2C or PMBus used for these devices. Described is an alternate data path connection that bypasses normal bus limitations.
A Highly Integrated GaAs-based Module for DC-DC Regulators
Authors: Miller Greg J. 
Published: October 2015

There is a need and desire to push low voltage point-of-load voltage regulators (POL VRs) to higher switching frequencies. The main reason for this is to increase power density. Silicon MOSFET-based solutions are rapidly approaching their technology limits and are not capable of providing multi-MHz switching frequency for high current (&gt;10A) applications. Gallium Arsenide (GaAs) field effect transistors (FETs) can switch much faster, enabling cost-effective, high-current, high switching frequency POL VRs. Recent advances in GaAs technologies have enabled the demonstration of 5MHz VRs and provide a path to even higher frequency (&gt;50MHz) Power Supply in Package (PSiP) solutions.
The high-speed GaAs power FETs are the “engine” to enable efficient high switching frequency POL VRs, but certain key elements must be designed appropriately to realize the desired performance. The gate driver and power path impedances must be minimized. To do this, a high level of integration is required, thus packaging is a critical element. New embedded die packaging solutions enable this high level of integration, dramatically reducing key parasitic impedances that can otherwise throttle performance, while also facilitating very compact multi-chip modules.
Challenges of Adhesion Promotion for the Metallization of Glass Interposers
Authors: Bamberg Simon , Merschy Michael , Bernhard Tobias , Bruening Frank , Taylor Robin , Brandt Lutz , Liu Zhiming , Fu Hailuo , Hunegnaw Sara 
Published: October 2015

Ultra-miniaturization and 3D integration of electronic systems require interposers with a very high density of off-chip interconnections. Silicon and glass interposers are being developed widely to meet these needs.
Through hole via formation or Through Package Via (TPV) in combination with the ability to handle of thin glass materials have already been demonstrated in combination with “polymer on glass” technologies at Georgia Tech Packaging Research Center and by industrial partners.
However there is an increasing industry demand to plate electroless copper directly onto smooth glass substrates which is extremely challenging.
This is being driven by the desire to be able to benefit from the ability to utilize existing infrastructure and therefore fully benefit from the cost advantages wet-chemical metallization can offer in the manufacturing of glass interposers.
It is therefore worthwhile to investigate replacing adhesion promoting techniques such as sputtered metal seed layers or laminated polymer films with a pure wet chemistry alternative.
In this study a modified sol gel processes were developed for the formation of metal oxide layers on the glass substrate. The impact of the sol composition on the resulting oxide's surface structure was examined.
Centrifugal adhesion measurement allowed quantification of the mechanical anchoring provided by metal oxide layers prepared from different sol gel compositions.
With regards to the interposer manufacturing process, the two possibilities of applying the sol gel coating prior to as well as after TPV formation are compared and their respective advantages are discussed.
Size Matters – Embedding as an Enabler of Next-Generation SiPs
Authors: Renaud-Bezot Nick 
Published: October 2015

Embedding is a relatively new packaging technology involving the use of (for example) laminates to encapsulate the active and/or passive component, as well as PCB and/or SMT processes for electrical connections. The embedded system can be used in that condition, or further processed to create a System-in-Package (or System-in-Board in case of larger assemblies). In that last case, the SiP (respectively SiB) is treated like any other substrate (respectively PCB).
In the search for higher integration, embedding is gaining traction as an alternative 3D-packaging solution, due to its multiple advantages: high integration, large production format, intrinsic matching to PCB in terms of pitch and CTE characteristics, mechanical stability and possibility to adapt substrate properties based on specific requirements (Dk, thermal conductivity…). The various players in the field are raking in new design-ins, and production volumes are rapidly increasing.
Those characteristics mean that embedded packages are directly competing with several other packaging architectures routinely used in smartphone applications:- Almost as small as WL-CSPs while being more robust and offering better thermal behavior,- Smaller than QFNs with similar thermal properties,- Thinner than PoPs while allowing easier 3D integration,- SiP architecture to decrease PCB-level cost-of-ownership.
Smartphone manufacturers are constantly demanding increased reliability and performance, while requesting from packages to enable higher functionalities in smaller form factors. This document compares multiple architectures meeting the tight height requirements from the smartphone industry, and proves that embedding is a valid enabler in the quest for higher integration. It also shows the latest developments in terms
Source-Sense Packages for HV MOSFETs
Authors: Lind Anders 
Published: October 2015

In traditional 3-pin High-Voltage (HV) power MOSFET (MOSFET) packages, the hard-switching transition speed is limited by the package source-inductance because the MOSFET drain current and gate current both share a path through the same package source inductance. The details of this mechanism are discussed and the resulting additional switching power loss caused by it is both measured and simulated.
Proposed innovative “Source-Sense” packages split the two currents into separate paths by adding separate source-pin for Kelvin-type driver connection to gate-source on the chip, thus completely eliminating all switching loss incurred by the source inductance for improved efficiency and lower die temperature.
Leadless SMD packages employing this method are explored for further addressing complications caused by package source inductance, such as common-mode noise and requirement for filtering.
Advanced package concepts are discussed for future optimization and thermal management, and versatility of these advanced concepts as well as existing leadless SMD packages with “Source-Sense” is examined.