bluuebunny/crossref_metadata_2025_split huggingface dataset:
A case for hierarchical routing in low-power wireless embedded networks
Authors: Iwanicki Konrad , Van Steen Maarten 
Published: September 2012

Hierarchical routing has often been mentioned as an appealing point-to-point routing technique for wireless sensor networks (sensornets). While there is a volume of analytical and high-level simulation results demonstrating its merits, there has been little work evaluating it in actual sensornet settings. This article bridges the gap between theory and practice.
Having analyzed a number of proposed hierarchical routing protocols, we have developed a framework that captures the common characteristics of the protocols and identifies design points at which the protocols differ. We use a sensornet implementation of the framework in TOSSIM and on a 60-node testbed to study various trade-offs that hierarchical routing introduces, as well as to compare the performance of hierarchical routing with the performance of other routing techniques, namely shortest-path routing, compact routing, and beacon vector routing. The results show that hierarchical routing is a compelling routing technique also in practice. In particular, despite only logarithmic routing state, it can offer small routing stretch: an average of ∼ 1.25 and a 99th percentile of 2. It can also be robust, minimizing the maintenance traffic or the latency of reacting to changes in the network. Moreover, the trade-offs offered by hierarchical routing are attractive for many sensornet applications when compared to the other routing techniques. For example, in terms of routing state, hierarchical routing can offer scalability at least an order of magnitude better than compact routing, and at the same time, in terms of routing stretch, its performance is within 10--15% of that of compact routing; in addition, this performance can further be tuned to a particular application. Finally, we also identify a number of practical issues and limitations of which we believe sensornet developers adopting hierarchical routing should be aware.
Avoidance of security breach through selective permissions in android operating system
Authors: Sekar Lakshmi Priya , Gankidi Vinitha Reddy , Subramanian Selvakumar 
Published: September 2012

The current Android application framework has an "all or none" permission policy, viz., an application can be installed if and only if all the permissions are granted. Also, no provision exists to deny granted permissions after installation. Therefore, any application can misuse the granted permission. CyanogenMod addresses this issue by denying the unwanted permissions which might cause the application to crash. WhisperCore, has worked on this problem but the working model is unavailable at the moment. APEX, also is currently doing some research on this issue but there is no publicly available document.
In this paper, the problem of misusing the granted permission n in Android is addressed and a novel idea of 'shadow manifest' is proposed. The proposed shadow manifest is implemented by creating a novel Content Provider, viz., SelPermProvider, which hosts the user permissions. In general, during the resource request phase, the system manifest is checked and the resources are allocated. But, in our implementation, the control is altered to flow through the shadow manifest after the system manifest is checked. If the query to shadow manifest is TRUE, then the resource is granted else a dummy or null value is returned. This facilitates the user to identify the malware and block the malware from achieving the intended task. Thus, the application is unaware of the indirect permission denial and continues to run normally. The user can decide which permission to restrict by checking a log of all recent permission requests, a facility provided in our app.
The proposed shadow manifest has been implemented and tested using an application called 'Contacts_Retrieve'. It was found to successfully complete the application if the shadow manifest returned TRUE, and unsuccessfully complete otherwise.
CompSC
Authors: Pan Zhenhao , Dong Yaozu , Chen Yu , Zhang Lei , Zhang Zhijiao 
Published: September 2012

Live migration is one of the most important features of virtualization technology. With regard to recent virtualization techniques, performance of network I/O is critical. Current network I/O virtualization (e.g. Para-virtualized I/O, VMDq) has a significant performance gap with native network I/O. Pass-through network devices have near native performance, however, they have thus far prevented live migration. No existing methods solve the problem of live migration with pass-through devices perfectly.
In this paper, we propose CompSC: a solution of hardware state migration that will enable the live migration support of pass-through devices. We go on to apply CompSC to SR-IOV network interface controllers. We discuss the attributes of different hardware states in pass-through devices and migrate them with corresponding techniques. Our experiments show that CompSC enables live migration on an Intel 82599 VF with a throughput 282.66% higher than para-virtualized devices. In addition, service downtime during live migration is 42.9% less than para-virtualized devices.
Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)
Authors: Van Craeynest Kenzo , Jaleel Aamer , Eeckhout Lieven , Narvaez Paolo , Emer Joel 
Published: September 2012

Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The effectiveness of heterogeneous multi-cores depends on how well a scheduler can map workloads onto the most appropriate core type. In general, small cores can achieve good performance if the workload inherently has high levels of ILP. On the other hand, big cores provide good performance if the workload exhibits high levels of MLP or requires the ILP to be extracted dynamically.
This paper proposes Performance Impact Estimation (PIE) as a mechanism to predict which workload-to-core mapping is likely to provide the best performance. PIE collects CPI stack, MLP and ILP profile information, and estimates performance if the workload were to run on a different core type. Dynamic PIE adjusts the scheduling at runtime and thereby exploits fine-grained time-varying execution behavior. We show that PIE requires limited hardware support and can improve system performance by an average of 5.5% over recent state-of-the-art scheduling proposals and by 8.7% over a sampling-based scheduling policy.
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
Authors: Krimer Evgeni , Chiang Patrick , Erez Mattan 
Published: September 2012

A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing speculation, where the pipeline operates at an unsafe voltage with any rare errors detected and resolved by the architecture, has been demonstrated to significantly improve the energy-efficiency of scalar processor designs. Unfortunately, applying the same timing-speculative approach to wide-SIMD architectures, such as those used in highly-efficient GPUs, may not provide similar gains.
In this work, we make two important contributions. The first is a set of models describing a parametrized general error probability function that is based on measurements of a fabricated chip and the expected efficiency benefits of timing speculation in a SIMD context. The second contribution is a decoupled SIMD pipeline that more effectively utilizes timing speculation and recovery, when compared with a standard SIMD design that uses only conventional timing speculation. The proposed lane decoupling enables each SIMD lane to tolerate timing errors independent of other adjacent lanes, resulting in higher throughput and improved scalability. We validate our models and evaluate our design using a cycle-based GPU simulator, describe the conditions where efficiency improvements can be obtained, and explore the benefits of decoupling across a wide range of parameters. Our results show that timing speculation can achieve up to 10.3% improvement in efficiency.
Reducing memory reference energy with opportunistic virtual caching
Authors: Basu Arkaprava , Hill Mark D. , Swift Michael M. 
Published: September 2012

Most modern cores perform a highly-associative transaction look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it with L1 cache access, but this overlap does not hide the power dissipated by TLB lookups. It can even exacerbate the power dissipation by requiring higher associativity L1 cache. With today's concern for power dissipation, designs could instead adopt a virtual L1 cache, wherein TLB access power is dissipated only after L1 cache misses. Unfortunately, virtual caches have compatibility issues, such as supporting writeable synonyms and x86's physical page table walker.
This work proposes an Opportunistic Virtual Cache (OVC) that exposes virtual caching as a dynamic optimization by allowing some memory blocks to be cached with virtual addresses and others with physical addresses. OVC relies on small OS changes to signal which pages can use virtual caching (e.g., no writeable synonyms), but defaults to physical caching for compatibility. We show OVC's promise with analysis that finds virtual cache problems exist, but are dynamically rare. We change 240 lines in Linux 2.6.28 to enable OVC. On experiments with Parsec and commercial workloads, the resulting system saves 94-99% of TLB lookup energy and nearly 23% of L1 cache dynamic lookup energy.
A defect-tolerant accelerator for emerging high-performance applications
Authors: Temam Olivier 
Published: September 2012

Due to the evolution of technology constraints, especially energy constraints which may lead to heterogeneous multi-cores, and the increasing number of defects, the design of defect-tolerant accelerators for heterogeneous multi-cores may become a major micro-architecture research issue.
Most custom circuits are highly defect sensitive, a single transistor can wreck such circuits. On the contrary, artificial neural networks (ANNs) are inherently error tolerant algorithms. And the emergence of high-performance applications implementing recognition and mining tasks, for which competitive ANN-based algorithms exist, drastically expands the potential application scope of a hardware ANN accelerator.
However, while the error tolerance of ANN algorithms is well documented, there are few in-depth attempts at demonstrating that an actual hardware ANN would be tolerant to faulty transistors. Most fault models are abstract and cannot demonstrate that the error tolerance of ANN algorithms can be translated into the defect tolerance of hardware ANN accelerators.
In this article, we introduce a hardware ANN geared towards defect tolerance and energy efficiency, by spatially expanding the ANN. In order to precisely assess the defect tolerance capability of this hardware ANN, we introduce defects at the level of transistors, and then assess the impact of such defects on the hardware ANN functional behavior. We empirically show that the conceptual error tolerance of neural networks does translate into the defect tolerance of hardware neural networks, paving the way for their introduction in heterogeneous multi-cores as intrinsically defect-tolerant and energy-efficient accelerators.
A case for exploiting subarray-level parallelism (SALP) in DRAM
Authors: Kim Yoongu , Seshadri Vivek , Lee Donghyuk , Liu Jamie , Mutlu Onur 
Published: September 2012

Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the high latency of off-chip memory. Adding more banks to the system to mitigate this problem incurs high system cost. Our goal in this work is to achieve the benefits of increasing the number of banks with a low cost approach. To this end, we propose three new mechanisms that overlap the latencies of different requests that go to the same bank. The key observation exploited by our mechanisms is that a modern DRAM bank is implemented as a collection of subarrays that operate largely independently while sharing few global peripheral structures.
Our proposed mechanisms (SALP-1, SALP-2, and MASA) mitigate the negative impact of bank serialization by overlapping different components of the bank access latencies of multiple requests that go to different subarrays within the same bank. SALP-1 requires no changes to the existing DRAM structure and only needs reinterpretation of some DRAM timing parameters. SALP-2 and MASA require only modest changes (< 0.15% area overhead) to the DRAM peripheral structures, which are much less design constrained than the DRAM core. Evaluations show that all our schemes significantly improve performance for both single-core systems and multi-core systems. Our schemes also interact positively with application-aware memory request scheduling in multi-core systems.
PreSET
Authors: Qureshi Moinuddin K. , Franceschini Michele M. , Jagmohan Ashish , Lastras Luis A. 
Published: September 2012

Phase Change Memory (PCM) is a promising technology for building future main memory systems. A prominent characteristic of PCM is that it has write latency much higher than read latency. Servicing such slow writes causes significant contention for read requests. For our baseline PCM system, the slow writes increase the effective read latency by almost 2X, causing significant performance degradation.This paper alleviates the problem of slow writes by exploiting the fundamental property of PCM devices that writes are slow only in one direction (SET operation) and are almost as fast as reads in the other direction (RESET operation). Therefore, a write operation to a line in which all memory cells have been SET prior to the write, will incur much lower latency. We propose PreSET, an architectural technique that leverages this property to pro-actively SET all the bits in a given memory line well in advance of the anticipated write to that memory line. Our proposed design initiates a PreSET request for a memory line as soon as that line becomes dirty in the cache, thereby allowing a large window of time for the PreSET operation to complete. Our evaluations show that PreSET is more effective and incurs lower storage overhead than previously proposed write cancellation techniques. We also describe static and dynamic throttling schemes to limit the rate of PreSET operations. Our proposal reduces effective read latency from 982 cycles to 594 cycles and increases system performance by 34%, while improving the energy-delay-product by 25%.
Staged memory scheduling
Authors: Ausavarungnirun Rachata , Chang Kevin Kai-Wei , Subramanian Lavanya , Loh Gabriel H. , Mutlu Onur 
Published: September 2012

When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from the CPU cores, leading to low system performance and starvation of CPU cores. Unfortunately, state-of-the-art application-aware memory scheduling algorithms are ineffective at solving this problem at low complexity due to the large amount of GPU traffic. A large and costly request buffer is needed to provide these algorithms with enough visibility across the global request stream, requiring relatively complex hardware implementations.
This paper proposes a fundamentally new approach that decouples the memory controller's three primary tasks into three significantly simpler structures that together improve system performance and fairness, especially in integrated CPU-GPU systems. Our three-stage memory controller first groups requests based on row-buffer locality. This grouping allows the second stage to focus only on inter-application request scheduling. These two stages enforce high-level policies regarding performance and fairness, and therefore the last stage consists of simple per-bank FIFO queues (no further command reordering within each bank) and straightforward logic that deals only with low-level DRAM commands and timing.
We evaluate the design trade-offs involved in our Staged Memory Scheduler (SMS) and compare it against three state-of-the-art memory controller designs. Our evaluations show that SMS improves CPU performance without degrading GPU frame rate beyond a generally acceptable level, while being significantly less complex to implement than previous application-aware schedulers. Furthermore, SMS can be configured by the system software to prioritize the CPU or the GPU at varying levels to address different performance needs.
Harmony
Authors: Kambadur Melanie , Tang Kui , Kim Martha A. 
Published: September 2012

Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effort by exposing relevant features of multithreaded applications. This paper describes parallel block vectors, which uncover previously unseen characteristics of parallel programs. Parallel block vectors provide block execution profiles per concurrency phase (e.g., the block execution profile of all serial regions of a program). This information provides a direct and fine-grained mapping between an application's runtime parallel phases and the static code that makes up those phases. This paper also demonstrates how to collect parallel block vectors with minimal application perturbation using Harmony. Harmony is an instrumentation pass for the LLVM compiler that introduces just 16-21% overhead on average across eight Parsec benchmarks.
We apply parallel block vectors to uncover several novel insights about parallel applications with direct consequences for architectural design. First, that the serial and parallel phases of execution used in Amdahl's Law are often composed of many of the same basic blocks. Second, that program features, such as instruction mix, vary based on the degree of parallelism, with serial phases in particular displaying different instruction mixes from the program as a whole. Third, that dynamic execution frequencies do not necessarily correlate with a block's parallelism.
End-to-end sequential consistency
Authors: Singh Abhayendra , Narayanasamy Satish , Marino Daniel , Millstein Todd , Musuvathi Madanlal 
Published: September 2012

Sequential consistency (SC) is arguably the most intuitive behavior for a shared-memory multithreaded program. It is widely accepted that language-level SC could significantly improve programmability of a multiprocessor system. However, efficiently supporting end-to-end SC remains a challenge as it requires that both compiler and hardware optimizations preserve SC semantics. While a recent study has shown that a compiler can preserve SC semantics for a small performance cost, an efficient and complexity-effective SC hardware remains elusive. Past hardware solutions relied on aggressive speculation techniques, which has not yet been realized in a practical implementation.This paper exploits the observation that hardware need not enforce any memory model constraints on accesses to thread-local and shared read-only locations. A processor can easily determine a large fraction of these safe accesses with assistance from static compiler analysis and the hardware memory management unit. We discuss a low-complexity hardware design that exploits this information to reduce the overhead in ensuring SC. Our design employs an additional unordered store buffer for fast-tracking thread-local stores and allowing later memory accesses to proceed without a memory ordering related stall.Our experimental study shows that the cost of guaranteeing end-to-end SC is only 6.2% on average when compared to a system with TSO hardware executing a stock compiler's output.
Unstable path routing in urban-scale WSN
Authors: Mirza Farrukh , Bouroche Mélanie , Cahill Vinny 
Published: September 2012

Wireless sensor networks (WSNs) may suffer from congestion at the nodes near the sink, and partition due to the failure of crucial nodes. In urban environments, mobile devices, such as vehicles and smart phones, present in the vicinity of the sensor field could be opportunistically used for data forwarding. Such devices, controlled by third parties, introduce paths that may appear for only very small intervals.
This paper discusses how exploiting such unstable paths to shift the routing-related processing and communication load to more capable mobile devices can alleviate traffic congestion, improve fault tolerance and reduce WSN energy consumption.
miRNA-34 Prevents Cancer Initiation and Progression in a Therapeutically Resistant K-ras and p53-Induced Mouse Model of Lung Adenocarcinoma
Authors: Kasinski Andrea L. , Slack Frank J. 
Published: September 2012

Abstract
Lung cancer is the leading cause of cancer deaths worldwide, and current therapies fail to treat this disease in the vast majority of cases. The RAS and p53 pathways are two of the most frequently altered pathways in lung cancers, with such alterations resulting in loss of responsiveness to current therapies and decreased patient survival. The microRNA-34 (mir-34) gene family members are downstream transcriptional targets of p53, and miR-34 expression is reduced in p53 mutant tumors; thus, we hypothesized that treating mutant Kras;p53 tumors with miR-34 would represent a powerful new therapeutic to suppress lung tumorigenesis. To this end we examined the therapeutically resistant KrasLSL-G12D/+;Trp53LSL-R172H/+ mouse lung cancer model. We characterized tumor progression in these mice following lung-specific transgene activation and found tumors as early as 10 weeks postactivation, and severe lung inflammation by 22 weeks. Tumors harvested from these lungs have elevated levels of oncogenic miRNAs, miR-21 and miR-155; are deficient for p53-regulated miRNAs; and have heightened expression of miR-34 target genes, such as Met and Bcl-2. In the presence of exogenous miR-34, epithelial cells derived from these tumors show reduced proliferation and invasion. In vivo treatment with miR-34a prevented tumor formation and progression in KrasLSL-G12D/+;Trp53LSL-R172H/+ mice. Animals infected with mir-34a-expressing lentivirus at the same time as transgene activation had little to no evidence of tumorigenesis, and lentivirus-induced miR-34a also prevented further progression of preformed tumors. These data support the use of miR-34 as a lung tumor-preventative and tumor-static agent. Cancer Res; 72(21); 5576–87. ©2012 AACR.