bluuebunny/crossref_metadata_2025_split huggingface dataset:
No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration
Authors: Li Zhaozhi , Evans John L. , Houston Paul N. , Lewis Brian J. , Baldwin Daniel F. , Lee Sangil , Tessier Theodore G. , Stout Eugene A. 
Published: October 2015

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity.
Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process.
Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield.
The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.
Stacking of Known Good Rebuilt Wafers without TSV - Applications to Memories and SiP
Authors: Val Christian , Couderc Pascal , Lartigues Pierre 
Published: October 2015

The 3-D interconnection started at 3D PLUS in 1996 and led to the stacking of nearly all types of analogical and logical components, sensors, MEMS, etc for the Hi-Rel field (Space, Defence, Medical, Industrial).
This technology is extremely robust (−130°C +175°C, 40000g), and is fully qualified by all worldwide most important Space Agencies and for Defence applications.
A technological break started in 2002 ; It consisted in another 20 to 30 reduction factor of the weight and volume of these 3-D modules.The Z pitch is 100μm and the X Y size is given by the size of the larger die plus 100μm of polymer around it.
This is a stacked of Known Good Rebuilt Wafer of full wafer level technique.
The dice are received in wafers and following operations are carried out :- Pick, flip and place of the good dice on a “sticking skin”- Moulding of the whole of this « pseudo wafer » in order to obtain what we call a « Known Good Rebuilt Wafer (KGRW) ».
These two first steps are already developed by Infineon and mainly Freescale (RCP technique up to 300mm)- Stacking and gluing of KGRW 1, 2, 3…, n, by means of an adhesive film- Dicing of these stacked rebuilt wafers by techniques identical to the dicing of standard wafers- Metallization of the dicing streets with nickel + gold by electroless chemical plating identical to the UBM plating technique- Direct laser patterning by laser with our edge connection technique up to 100μm pitch. Below this pitch, the Thru Polymer Via (TPV) are made through the stacked wafers. The equivalent pitch will be 20μm. it can be noticed that the shielding can be made on the dicing street.- Electrical test at the stacked wafer level- Singulation of the 3D modules
This approach allows using standard dice without any modification.
It is multi sources and the stacking of the good rebuilt wafers allows to get an excellent yield.
A development agreement has been signed with a semiconductors manufacturer.
A development is in progress with the most worldwide important manufacturer of smart cards in order to integrate 5 levels of dice (including a MEMS) within a cavity of 550 μm inside the 800μm SIM card.
Other applications with MEMS will be presented:- “Abandoned Sensors” for Heath Monitoring of the aircraft structure developed during the European Program: “e-Cubes” ,- Gyroscope with 6 MEMS,- Micro camera for endoscopy…- Medical applications with an important development made for 3 major pacemaker manufacturers.
This « full wafer level » approach will allow to build System in Package (SiP) or “Abandoned Sensors” at very low costs, since the process uses mainly the steps of wafers building; the “panelization” allows to be in parallel processing from A to Z steps. Moreover, the use of Known Good Rebuilt Wafer like the RCP allows stacking Good wafer at the reverse what is impossible with the wafer to wafer approach.
Integration of Electrografted Layers for the Metallization of Deep TSVs
Authors: Truzzi Claudio , Raynal F. , Mevellec V. , Frederich N. , Suhr D. , Bispo I. , Couturier B. 
Published: October 2015

Electrografting (eG) is a molecular engineering technology delivering high-quality films for Through Silicon Vias (TSVs). It generates surface-initiated conformal films which are thin, continuous, adherent and uniform. It is a wet-process technique, operated in standard plating tools, and is used on (semi)-conductive surfaces.
Chemical grafting (cG) is a similar technology, used to graft films on non-conductive surfaces. A wet deposition of insulator, barrier and copper seed layers inside deep TSVs using a combination of electrografting and chemical grafting techniques has already been demonstrated [1, 2].
Electrografting and chemical grafting formulations and processes have been developed and specifically tailored for TSV diameters ranging from 1 to 200 μm, covering a depth/diameter Aspect Ratio (AR) range from 2:1 to 20:1. Film thickness can be controlled to any value from 50nm to few microns, depending on the layer, with 5% 3ó in-wafer non-uniformity, providing a step coverage (bottom/top thickness ratio) value of up to 90%. Adhesion of all layers is measured using a 16-square scribe tape test method: all layers successfully pass the test.
The presentation will focus on film properties and show how TSV formed using these layers meet all key process requirements such as conformality, uniformity, adhesion, reliability and industrial compatibility for cost-effective high volume manufacturing of TSV wafers. A comprehensive set of film properties and reliability data characterized on blanket and pattern 200-mm Si wafers will be discussed. Integration schemes of electrografted layers within current 3D packaging process flows will be presented.
Processing of Lithographically Defined Apex Glass Structures with Smooth and Transparent Sidewalls
Authors: Tantawi Khalid H.M. , Oates Janeczka , Williams John D. 
Published: October 2015

We demonstrate a process to improve the surface roughness and optical transparency of the sidewalls of structures made in ApexTM photosensitive glass. Improved sidewall roughness is achieved through a post- etch anneal that reflows the surface of the glass microstructure and reduces the size of roughened glass nodules on the HF etched surface. The same anneal process is equally suited for bonding between substrates as the surface of the glass is melted allowing the glass to reflow across the seam of the bond.
The process involves four basic steps: the glass sample is exposed to mid UV light to photo-activate metallic particles, followed by a two-stage baking process to allow for formation of metallic nanoclusters in the glass matrix. The amorphous glass is then etched in a diluted 3–4% (by volume) HF solution. Finally the glass structure undergoes a post-etch annealing processes at 630°C for 15 min to smoothen the etched surface and enhance the transparency of the glass sidewalls.
The surface roughness obtained was approximately 200  36 nm. The surface roughness prior to post etch annealing was over 1 μm with a standard deviation of 0.4 μm. Thermal loading was observed between structures of varying size at these temperatures. The improvement of transparency in the sidewalls renders the glass structures useful for micro-optical sensors. Future work will investigate the use of this process for the development of visible and near IR microspectrometer curvets.
The Use of Metallographic and SEM Analysis for Characterization of Sidewall Surfaces in MEMS Devices with DRIE Processing
Authors: Levine Lee , Dean Robert , Stevens Colin , Lawrence Samuel 
Published: October 2015

The use of Bosch process Deep Reactive Ion Etch (DRIE) processing for manufacturing MEMS and MOEMS devices requiring high aspect ratio (depth/width) trenches has become commonplace. However, process conditions (etch rate, process parameters etc.) have a significant effect on the surface quality of the trench sidewalls. For many device types [1] (grates, waveguides) surface condition of the sidewall can have a large impact on the functionality of the device and therefore must be controlled to achieve performance requirements.
Optical microscopy techniques are not capable of the depth of focus and resolution necessary to adequately control processing within deep trenches where surface roughness of &lt; 10nm may be required. Scanning Electron Microscopy (SEM) is capable of this resolution, but even SEM is incapable of determining surface roughness within the deep trenches. Metallographic techniques, mounting and polishing a sample to reveal a section view through the trench, along with SEM, to image and measure the surface roughness is a requirement.
An experiment was designed, using etch parameters to vary the DRIE recipe, and then cross sectioning and SEM imaging of the devices were performed. The purpose of the experiment was to quantify the effect of the DRIE recipe on the sidewall surface roughness within the trench, and to demonstrate the use of metallographic techniques with SEM to accomplish this goal.
A Parametrically Amplified MEMS Gyroscope
Authors: Gallacher Barry J. , Hu Z. X. , Burdess J. S. , Harish K. M. 
Published: October 2015

The applicability of parametric amplification of either the primary and secondary vibration modes of a MEMS gyroscope, shown in Fig.1 is investigated experimentally in this paper. All control schemes have been implemented digitally onto a SHARC DSP development board. Parametric gains in excess of 80, which correspond to multiplication of the Q-factor by a factor of 80, are demonstrated experimentally for open-loop operation of the primary mode and are shown in Fig. 2. For open-loop operation it is shown that amplitude limiting nonlinearities become important as the vibration amplitude increases (see Figs.3) and that parametric amplification in excess of 80 can be only be achieved by further reducing the harmonic forcing amplitude.
In many applications it is desirable to have as high a Q-factor as possible. The rate gyroscope is one application were active control of the Q-factor is extremely pertinent. If applied to the primary mode then it permits reduced forcing levels and hence contamination from “feedthrough”. If applied to the sense mode then the Coriolis force is effectively amplified. Parametric amplification of the secondary mode of the gyroscope is a challenging problem but it has the potential to improve the performance of MEMS rate gyroscope but an order of magnitude.
In operation as a rate gyroscope it is important to maintain the amplitude of the primary mode of vibration at a constant level. For the case of a parametrically amplified primary mode the amplitude control circuit automatically adjusts the parametric excitation parameters to ensure the required parametric gain is achieved whilst at the same time reducing the amplitude of the harmonic forcing. In closed loop parametric amplification of the primary mode by a factor 20 have been demonstrated. Experimental results obtained from the amplified primary mode are shown in Fig.4.
Passive Device Integration from Silicon Technology
Authors: Liu Kai , Lee YongTaek , Kim HyunTai , Kim Gwang , Badakere Guruprasad , Lin Yaojian , Ahn Billy 
Published: October 2015

Passive components are indispensible parts used in electronics circuits for various functions, such decoupling, biasing, resonating, filtering, matching, transforming, etc. These passive components can be made on chips, or in PCBs, or in SMDs. SOC (system-on-chip) solutions where all passives are implemented may be long-term goals, but suffer high cost and long development cycle times at the time being. Making passive components embedded inside laminate substrates is limited on passive density. SMD solutions are by far the most popular approaches in the industry, and may still be dominant for some times. Passive components consume 70%–80% area of an electric package in a SiP solution, and therefore it is a great deal to reduce the area of passive components, in order to reduce the size of entire package.
We have developed an IPD (integrated passive device) process from silicon technology to make these passive components of high-Q performance, preferably to be used in RF packages. Low-loss substrate material is used in this process, and thick Cu layer is used for high-Q inductors. From this process, we can make capacitors in 330pF/mm sq density, and the Q-factor is around 30–35 peak for a 3nH–5 nH inductor. Most importantly, the thin-film IPD process has better tolerance control than other commonly available ones, such as PCB and LTCC technologies, which may results in very repeatable electrical performance, and provides packages in high integration. For a passive function block, using BPF (band-pass-filter) as an example, an IPD filter is typically two times smaller in X-Y size and half thinner in Z-height. This makes such IPD very suitable to be integrated in a SiP package. Using some case studies (individual IPD and chip-scale-module-package), we will present how high integration can be achieved, and where are the right spots to use IPD approaches other than SAW, or SMD, or LTCC solutions for RF SiP applications.
Evaluation of Low Stress Photo-Sensitive Spin On Dielectric Layers for Through Silicon Via (TSV) Copper Redistribution Layers
Authors: Jahnes Christopher , Huenger Eric , Kisting Scott 
Published: October 2015

To increase performance of semiconductor devices advances in packaging such as chip stacking (3D) and silicon carrier technologies (SoC) are being developed. Adaptation of these packaging fabrication methods offers the ability to incorporate functionality as well as provide memory and power distribution on one IC with increased signal bandwidth. An enabling element in both the stacking and silicon carrier technologies is through silicon vias (TSV) which electrically connect dies to a silicon carrier or via stacked chips (1). Creation of TSV involves via fabrication, wafer thinning and back side wafer finishing, to name a few, some of which are relatively new to semiconductor processing. Furthermore, because the wafer backside is accessible it can now be utilized to route wiring to further increase package density.
The focus of this research was to evaluate photo-sensitive spin on dielectric materials (SOD) that can be used as the backside wiring levels, commonly referred to as redistribution layers (RDL) in TSV technologies. The two materials evaluated are; the epoxy based Dow INTERVIA™ 8023 Dielectric and the Benzocyclobutene (BCB) polymer, Dow CYCLOTENE™ 4000 product series. These dielectric materials have low stress and provide good planarization (2). Test vehicles with a chip size of 3.7 cm x 2.26 cm were fabricated with a 6 um wide copper RDL layer using the SOD materials of interest as well as conventional PECVD SiO2/SiN dielectric layers. The large chip size accommodated parallel Cu lines running 1.8 cm long with a spacing of 3 ï&#x81;¬m and represented an aggressive shorting test for the SOD materials. It also enhances chip distortion after thinning and is evaluated for all three test vehicles. Chips were then electrically tested through simulated 260° C reflow cycles (for flip chip joining) and accelerated thermal reliability tests from −55° C to 125° C for 1000 cycles.
300mm Wafer-Level Image Sensor Packaging
Authors: Matthias Thorsten , Kim Bioh , Mittendorfer Gerald , Lindner Paul , Kriman Moshe , Grinman Andrey , Feldman Alex 
Published: October 2015

The image sensor market is still showing s tremendous market growth due to applications in consumer electronics, medical, automotive and communication. For a lot of new applications the image sensor packaging is in fact the enabling key technology. The introduction of wafer level packaging a couple of years ago allowed the cost reduction necessary for high volume consumer electronics. Innovative packaging concepts with TSVs and thin dies enable unmatched form factor.
Currently scaling image sensor manufacturing and packaging to 300mm is the next big step forward in cost reduction. Wafer level image sensor packaging requires capping of the sensor wafer with a glass wafer. This heterogeneous integration of silicon and glass results in a variety of challenges like thermal expansion mismatch and bow and warp of the wafer stack.
In this paper Tessera's OptiML Micro Via Pad technology for image sensors will be described with a special emphasis on equipment and process technology. Wafer encapsulation, via formation, electrical routing, passivation and solder bumping will be discussed.
Thermal Analysis for a Novel 3D Heterogenous Integrated Platform MorPack
Authors: Chen Shih-Lun , Huang Chun-Ming , Wu Chien-Ming , Yang Chih-Chyau , Chue Jin-Ju , Chen Shih-Lun , Chen Chi-Shi , Wang Jiann-Jenn , Chiueh Tzi-Dar 
Published: October 2015

This paper presents a thermal analysis result for a novel 3D heterogeneous integrated platform MorPack (morphing package). The MorPack platform is stacked by heterogeneous sub-modules composed of bare dies, a substrate, connection bridges, and solder balls. Since the MorPack platform owns the tiny, heterogeneous and integrable characteristics, the fabrication structure must be high-density and laminal. Thus, the cooling ability of forced convection is restricted due to limited space. It can be only cooled by increasing conduction and radiation capabilities.
In order to improve the cooling ability of MorPack platform, we created three indications to optimize the thermal solution. First, the vertical thermal conductivity can be improved by filling up whole MorPack with mold material. This skill efficiently cools down the 0.5-W consuming chip by 10°C more than non-filled-up structure. Second, the bare die chip with highest power consumption should be put on the lowest layer of this 3D structure because the bottom layer owns the best cooling ability. It achieves cooling a 0.5-W consuming chip by 12°C more than it is put on the top layer. Third, in order to lessen more volume of MorPack, the density of laminal structure was increased by reducing 50 % height of the platform. To realize it, we removed the connection bridges and cut out the substrate to make a room space for chip placement. With result shown, 50 % height and volume of MorPack can be minimized with only a few temperature rising.
Wafer Level Package for MEMS with TSVs and Hermetic Seal
Authors: Shiraishi Akinori , Higashi Mitsutoshi , Murayama Kei , Taguchi Yuichi , Mori Kenichi 
Published: October 2015

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated.
In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined.
Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages.
Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.
Low Cost, High Reliability WLCSP for Higher Pin Counts
Authors: Curtis Tony , Sivaswamy Senthil , Yazzie Ronnie , Lawhead David , Tessier Theodore G. 
Published: October 2015

The proliferation of Wafer Level Chip Scale Packages (WLCSPs) in portable handheld products has occurred due to the minimalist form factor, high reliability and low cost packaging that they afford. As the demand for WLCSPs has grown exponentially in recent years, the industry has also been coping concurrently with the technical challenges associated with increasing array sizes and more demanding end user reliability requirements. Since handsets are inherently prone to being dropped, they are particularly susceptible to this type of component failure though striking a proper balance of mechanical robustness and thermal cycling performance has remained an ongoing industry goal.
Similar to other packages, WLCSPs have transitioned over the past decade from lead-based solder alloys to Lead Free (LF) solders. LF solder connections are especially susceptible to brittle fracture and can result in variations in drop test performance from one bump structure to the next. This paper will provide an overview of process and material add-on strategies that have been shown to considerably improve mechanical robustness for bump structures or bumping applications that are inherently less robust than others. Such supplemental improvements can result in passing Board Level Reliability qualification requirements which may otherwise be elusive or have limited levels of reliability reproducibility.