bluuebunny/crossref_metadata_2025_split huggingface dataset:
Development of Electronic Substrates for Medical Device Applications
Authors: Egitto Frank D. , Das Rabindra N. , Marconi Francesco , Wilson Bill , Markovich Voya R. 
Published: October 2015

There is a strong desire to develop advanced electronic substrates that can meet the growing demand for miniaturization, high-speed performance, and flexibility for medical devices. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present study, we are developing flexible packages for a variety of medical applications. Here we discuss several classes of flexible materials that can be used to form high-performance flexible packaging. In addition, copper thinner than 5 μm is routinely used, with copper layers as thin as 0.2 μm used as a seed layer for semi-additive approaches. The use of semi-additive circuitization facilitates manufacture of fine-line circuit features, and traces narrower than 12μm have been produced routinely. A smooth copper-polymer interface is ideal for high speed applications and for fine line etching. Selection of an appropriate material provides good copper adhesion to the base film. Flexible materials with 1 or 2 metal layers provide the smallest possible roll diameter for systems such as catheters. Compatibility with well developed, high performance electronic materials represents a key advantage of flexible electronics systems that are enabled by high density fine line structures rather than unusual materials. Electrical interconnection between the chip and package can be made by a number of means. Solder-coated Cu-micro pillars for a variety of finer pitch applications are being developed. Cu micro pillars are grown through the dielectric or silicon and subsequently coated with solder to produce finer pitch 3D-interconnects. The paper also describes a novel approach for the fabrication of flexible electronics on PDMS substrates. The paper discusses the fabrication of PDMS substrates using different circuit patterns and geometries.
Rozalia/Ron ok move from 2.5/3D to FC/WLP 12-21-11.
Gold Stud Bump on Sn Based Solders
Authors: Collier Terence Q. 
Published: October 2015

When thick gold and tin come into contact the intermetallic formed is not one for long term reliability. AuSn intermetallics can lead to void formation, increased resistance and a very brittle joint that will fail in time.
Such intermetallic formations occur when gold stud bumps are brought into contact with Sn based allows. Fine pitched devices, such as optical, typically use gold studs due to the tight pitch and small pad sizes. By transforming the gold to a less benign state the gold stud bumps allow assembly using standard Sn based solders.
Such a process is beneficial when cheapers solders can be used as well as standard flip chip assembly equipment. This paper will provide cross sections of gold stud bumps with SAC305 solder after 3X reflow. The 3X reflow is required to demonstrate the capability and reliability of the modified solder joint.
Rozalia/Ron ok move from 2.5/3D to FC/WLP 12-21-11.
Stacked 3d package with improved bandwidth and power efficiency
Authors: Gupta Dev 
Published: October 2015

Stacked die packages such as PoP are used in space - constrained portable systems e,g. SmartPhones. The processor ( SoC ) and Mobile DRAM chips are stacked vertically to fit the combination within the restricted board space. The use of wire bonds in the memory chips as well as package level interconnects introduces delays into the data transmitted between the chips and limits the max. clock rate ( at present about 533 MHz for LP DDR 2 memory ) and hence the data transfer rate / bandwidth to less than 6.4 GB per sec. For Smart Phones to become capable of PC quality Games and high speed video would require a doubling of the bandwidth to over 12.8 GB per sec. To achieve that target PoP type packages were to be replaced by 3-d stacks using TSVs and wide I/Os. However recently JEDEC has postponed the introduction of Wide I/O Mobile memory stacks ( using TSVs ) to 2015. So the bandwidth of PoP packages must be improved.
A physical way to increase the Bandwidth between the SoC and memory chips in a PoP is by increasing the max. no. of vertical I/Os as this allows more channels / higher parallelism in data transfer. This can be accomplished by shrinking the pitch ( from current 0.4 mm to 0.3 mm ) and doubling the number of rows of vertical I/Os ( from current 2 to 4 ) in PoP. However this requires major effort for the Packaging supply chain and would still fall well short of the future Bandwidth and interconnect Power efficiency targets.
In this paper we will describe modifications and additions to the baseline PoP package so that it can be operated at clock rates up to 800 MHz and deliver bandwidth of 12.8 GB per sec or more and match the Interconnect Power efficiency of 3-d stacks with TSVs.
Compensation features are introduced for ea. interconnect line between the SoC and Memory in the PoP package. The features are integrated on chips that are inserted between the two layers of the package. The vertical interconnection between the two levels of the PoP are replaced and routed through this additional chip.
Only minor changes are required in the baseline PoP package thus will not require long delay to shrink current PoP interconnect pitch etc. The additional chip is built with available technologies and would increase cost by only a fraction of that needed for stacks with TSV-based wide I/O.
Simulation results will be presented and compared with test results.
High Reliability Fine Pitch WLCSP for High Pin Count Applications
Authors: Lawhead David , Yazzie Ronnie , Curtis Tony , Burgess Guy , Tessier Ted 
Published: October 2015

Wafer Level Chip Scale Packages (WLCSP) have seen wider adoption in hand held as well as automotive electronics in recent years due to their unmatched form factor reductions and improved electrical performance. WLCSP's have gained popularity in high pin count IC's with tighter pitches and increased reliability requirements. Enhanced board level reliability is achieved by using solder spheres with higher silver content. Traditionally, automotive applications require an improvement in thermal cycling over WLCPS found in hand held applications. This paper will study the differences in solder alloy and include a comparison to under filled parts to meet these reliability requirements.
This study shows characteristic life that exceeds the industry standard requirements for the drop and thermal testing reliability testing.
An Innovative 2.5D IC Interconnection Reliability System
Authors: Levy Andrew , Manhaeve Hans , McBain Ed 
Published: October 2015

In this paper we present a new methodology that addresses the quality and reliability problems of applications that deploy “2.5D” packaging technology for integrated circuits (ICs). This technology employs through-silicon vias (TSVs), enabling greatly increased circuit density, performance, and functionality for a given volume. The 2.5D ICs require the use of an interposer to route signals between the chips and the package substrate. While this packaging solution has some distinct advantages over other packaging/mounting technologies, there are disadvantages as well. Qualifying and testing such connections is very difficult and expensive, and techniques for anticipating failure do not currently exist. Therefore, confidence in the reliability of 2.5D IC interconnects is lacking. Systems that use them may require a high level of preventive maintenance whenever possible, or such packaging may simply be avoided when such maintenance is not possible or practical.
The paper outlines an approach that combines embedded digital and analog measurement instruments that are capable of detecting and identifying opens and shorts in 2.5D IC TSV stacks. The monitors reside on the silicon interposer. This system is the first to address the difficult issue of 2.5D IC package interconnect integrity after assembly is done and when the related devices are deployed in larger systems. The innovation will improve reliability of TSV-based packaging by detecting and identifying faulty connections at package test during the manufacturing process. It also provides prognostic monitoring so that interconnect-related operational faults can be detected before actual system failure occurs after the packaged component is deployed in the field.
Micro-tube insertion into aluminum pads: Simulation and experimental validations
Authors: Bedoin Alexis , de Brugière B. Goubault , Marion F. , Berger F. , Fendler M. , Volpert M. , Ribot H. 
Published: October 2015

Following the trend towards more densely integrated electronic devices; new flip-chip technologies are developed to address very fine pitch interconnection. Among them, it was demonstrated that the hybridization technique based on insertion of gold coated micro-tubes into aluminum pads (Al-0.5Cu) has the capability for a 10 μm bonding pitch and the advantage of a room temperature assembly process [1, 2] .
In this study, we propose to thoroughly study the electro-mechanical behavior of the micro-tube inserted into an aluminum pad.
A finite element model has been used to simulate the micro-tube insertion into an aluminum pad. This numerical model deals with critical issues such as contacts, large deformations and remeshing. It was used to predict the main process parameter: the minimum load required for the micro-tube insertion into the pad. On one hand, the load should be high enough to fracture the native alumina layer during insertion and to achieve an appropriate electrical contact. On the other hand it must be low enough to prevent over-stress and deterioration of the tube and the underneath technology.
The predicted load is then used in an experimental setting where the single micro-tube insertion into pads is conducted using a nano-indenter. The modified nano-indenter allows in-situ electrical measurements. The simulated load is confirmed and SEM inspections of the deformed pad are in accordance with the predicted shape. This load is shown to be influenced by the loading rate and the alignment between the micro-tubes and pads. A full understanding of the electromechanical insertion behavior is achieved thanks to these experimental setup and the simulation.
These results are generalized to assemble an array of over 100 000 micro-tubes into an array of pads using a pick and place equipment. The D2W bonding process has been optimized in order to reach a 100% yield of interconnection and a high mechanical strength. Electrical measurements show that these assemblies exhibit an electrical resistance lower than 300mΩ.
Direct Palladium-Gold on copper as a Surface Finish for next generation Packages.
Authors: Ozkok Mustafa , Lamprecht Sven , Ramos Gustavo , Kilian Arnd 
Published: October 2015

A new surface finish is entering the market. The need for this finish comes from needs for new assembly technologies like copper wire bonding or chip assembly by thermo compression bond. Furthermore Nickel an element, which is the base of many surface finishes like ENIG or ENEPIG, is more and more regarded as an unpleasant element as of several disadvantages, such as for high frequency applications, for environmental issues or for fine line applications were a 5 μm Ni Layer is just simply too thick.
All these concerns supporting the introduction of a new surface finish, a direct EP and direct EPAG finish. In particular, its suitability for copper wire bonding and its fine line capability makes it very attractive from a cost standpoint of view. In addition, the mentioned technological handicaps of nickel based finishes could be solved by applying a revolutionary surface finish – A Direct Palladium with an optional gold layer.
The direct deposition of palladium on copper with an optional gold layer does have further technological, environmental and economical advantages. The suggested paper will describe and discuss the advantages and chances using this new surface finish, as well as demonstrate soldering on various wire bond tests on the Direct EP and EPAG finishes as well as soldering test results.
Thermal Analysis of xFD DRAM Packages Through Simulation and Experimental Validation
Authors: Zhang Ron , Tseng John , Shaba Hala , Chau Ellis , Zohni Wael , Mirkarimi Laura 
Published: October 2015

The design optimization for thermal management of systems relies heavily on accurate thermal models of the individual components. Invensas is developing new packaging concepts that provide enhanced and reliable performance electrically, thermally and mechanically. These development efforts use predictive finite element analysis to drive the optimization of package design for improved thermo-mechanical strain and thermal management. Therefore, it is important to validate such models through rigorous experimental thermal measurements.
This work represents the 2nd half of our effort in the area of multi-die face-down stack thermal analysis. As was presented last year for the dual die face-down stack analysis, we will present details of our quad die face-down package design, assembly and the thermal test protocols. We will outline our methodologies for measuring thermal performance and achieving tight tolerances in the experimental apparatus as well as guidelines for making appropriate assumptions for associated simulations. We examined JEDEC standard test conditions for natural convection and forced air flow at various air velocities. Comparing values obtained from experimental measurements with simulation data showed results that were within 10% margin in many cases. We will discuss in detail the important calibration protocol and considerations required in the experimental test area for enhanced precision.
Development of Embedded High Power Electronics Modules for Automotive Applications
Authors: Boettcher Lars , Karaszkiewicz S. , Manessis D. , Ostmann A. 
Published: October 2015

The automotive industry has a strong demand for highly reliable and cost-efficient electronics. Especially the upcoming generations of hybrid cars and fully electrical vehicles need compact and efficient 400 V power modules. Within the engine compartment installation space is of major concern. Therefore small size and high integration level of the modules are needed. Conventionally IGBTs and diodes are soldered to DCB (Direct Copper Bond) ceramics substrates and their top contacts are connected by heavy Al wire bonds. These ceramic modules are vacuum soldered to water-cooled base plates. Embedding of power switches, and controller into compact modules using PCB (Printed Circuit Board) technologies offers the potential to further improve the thermal management by double-sided cooling and to reduce the thickness of the module.
In the recently started “HI-LEVEL” (Integration of Power Electronics in in High Current PCBs for Electric Vehicle Application) project, partners from automotive, automotive supplier, material supplier, PCB manufacturer and research teamed up to develop the technology, components and materials to realize high power modules.
The following topics of the development will be addressed in detail in this paper:Assemble of power dies (IGBT and diode) using new sinter die attach materials:The deployment of new no pressure, low temperature sinter paste for the assembly of the power dies is a mayor development goal. Here the development of a reliable process to realize a defect free bonding of large IGBT dies (up to 10x14mm2) is essentially. These pastes are applied by stencil printing or dispensing and the sintering will take place after die placement at temperatures of around 200 °C.Thick copper substrate technology:To handle the high switching current, suitable copper tracks in the PCB are required. The realization of such thick copper lines (up to 1mm thickness) requires advanced processing, compared to conventional multilayer PCB production.
In this paper the essential development steps towards a 10 kW inverter module with embedded components will be described. The process steps and reliability investigations of the different interconnect levels will be described in detail.
Next Generation High Power Electronic Modules Based on Embedded Power Semiconductors
Authors: Böttcher Lars , Karaszkiewicz S. , Manessis D. , Hoene Eckart , Ostmann A. 
Published: October 2015

The spectrum of conventional power electronics packaging reaches from SMD packages for power chips to large power modules. In most of these packages the power semiconductors are connected by bond wires, resulting in large resistances and parasitic inductances. Power chip packages have to carry semiconductors with increasing current densities. Conventional wire bonds are limiting their performance. Today's power modules are based on DCB (Direct Copper bonded) ceramic substrates. IGBT switches are mounted onto the ceramic and their top side contacts are connected by thick Al wires. This allows one wiring layer only and makes an integration of driver chips very difficult. Additionally bond wires result in a high stray inductance which limits the switching frequency. Especially for the use of ultra-fast switching semiconductors, like SiC and GaN, it is very difficult to realize low inductive packages.
The embedding of chips offers a solution for many of the problems in power chip packages and power modules. While chip embedding was an academic exercise a decade ago, it is now an industrial solution. A huge advantage of packaging using PCB technology is the cost-effective processing on large panel. Furthermore embedded packages and modules allow either double-side cooling or 3D assembly of components like capacitors, gate drivers or controllers.
The advanced results of research projects will be discussed in the paper. An ultra-low inductance power module with SiC switches at 20 A / 600 V has been realized and characterized. The DC link inductance of the module was 0,8 nH only. These results sparked a huge interest in currently starting follow up projects creating package for fast switches.
In a further project power modules for automotive power inverters for motor control are under development. As a project demonstrator, a 10 kW module with IGBTs and diodes at 400 V / 500 A, was manufactured. This demonstrator is based on high power PCB technology and was fully characterized; the results will be presented in detail.
Recently started research projects will face the challenges of MW solar inverters at 1000 A and 1000 V, using SiC semiconductors as switches. First concepts will be presented as an outlook.
Embedding Active and Passive Devices in Medical Electronics
Authors: Dzarnoski John , Johansson Susie 
Published: October 2015

Efforts to increase the packaging efficiency of microelectronic systems have been extensive and continuous over the past few decades. Evidence of this can be seen even before the expansion of the space program by the United States in 1961 and the race to the moon; one of the first settings where size was truly limited and miniaturization of electronics was a necessity. In the 1950's the world saw its first major size reduction of electronic component with the phase out of the vacuum tube in favor of the transistor. The transistor saw its first major commercial use in 1952 via hybrid vacuum tube transistor technology. While many industries benefitted from the shift, in 1954 the hearing aid industry specifically experienced major improvements owing to the implementation of transistors, becoming smaller, requiring less power and having better functionality. The first 4-transistor AM radio product followed shortly thereafter. Much of today's effort since 1978 has been driven by the telecommunications industry that has succeeded in reducing cell phone size while simultaneously increasing functionality.
Just as in the 1950's, hearing aid technology continues to be at the forefront when it comes to miniaturization. The hearing aid business has always had the need to use extremely small electronic packaging. The first completely in the canal (CIC) hearing aids were produced in 1993 and required all electronic components to be small enough that they fit entirely inside the ear canal. The introduction of wireless systems into hearing aids has sharply increased component count. Due to the size and shape of a multitude of types of hearing aids, flexible circuits need to be folded and bent to fit inside hearing aid cases, with essentially all available space being used. More powerful processors and more memory are enabling sophisticated algorithms that are able to greatly improve sound quality. There is also a strong market desire to add more features to hearing products while at the same time making them smaller and less visible. The latest hearing aids have succeeded in the later demand, constructed so small they are not visible and consequently are called invisible in the canal (IIC). In order to continue meeting the markets want for smaller and more features, a new packaging method needed to be developed. One such option is embedded die packaging.
This paper will examine the use of embedded die packaging (or chip-in-flex) to drive significant further size reduction in custom and standard hearing instruments over what can be achieved using chip-on-flex or traditional ceramic hybrid based technologies. The historical drivers, available circuit board technologies, use of integrated passive devices, performance improvement, size reduction, device reliability, changes in supply chain, impact on wafer test, impact on device test, and challenges of working with wafers instead of die will be discussed.