bluuebunny/crossref_metadata_2025_split huggingface dataset:
Transient Thermal Analysis as a Test Method for the Reliability Investigation of High Power LEDs during Temperature Cycle Tests
Authors: Elger Gordon , Kandaswamy Shri Vishnu , Derix Robert , Wilde Jürgen 
Published: October 2015

Light emitting diodes (LEDs) are today standard and mature light sources. They have several key advantages, like small size, low energy consumption and long lifetime. However, high reliability of the LED system is required to achieve long lifetime of the light source. Thermo-mechanical stress due to temperature cycle causes failure of electronic systems. The electronic component itself or the interconnect device, e.g. printed circuit board (PCB) might fail. In many cases, the weakest link is found to be the solder interconnect between package and the board. Cracking of the interconnect causes an open contact and the system fails.
In this paper we compare the existing methods to investigate LED interconnect failures during temperature cycle tests like the simple “light-on-test”, electric resistance measurement and the shear test. We describe and introduce the transient thermal analysis as a measurement method. We present the first reliability data analysis with transient thermal analysis of ceramic high power LED packages on Al-IMS during air to air thermal shock test (−40°C to +125°C) and correlate it with cross sections. We demonstrate the sensitivity of the thermal analysis to detect solder joint failures of the assembly. We compare the results with electric resistance measurements and light on tests and show that the resolution is significantly higher compared to the methods applied today. The sensitivity of the method enables us to detect the crack in a solder joint much earlier than the final failure of the joint, i.e. the open contact.
Non-Destructive Top Layer Bond Pad Cross Section
Authors: Collier Terence Q. , Gubeljic Indira 
Published: October 2015

Contaminated and corroded aluminum bond pads can lead to a number of reliability failures. Poor wirebondability, false failures at electrical probe due to high contact resistance, opens on RDL layers due to incomplete sputter, and various early life failures during JEDEC testing can all be attributed to excess oxidation and corrosion on aluminum bond pads.
Understanding what layers exist on the bond pad surface is critical. Oxides, hydrates, xyfluorides and various soups of materials can be confirmed from combinations of Auger, SIMMS and FTIR but there is a chance the die can be damaged and the spot sizes can be problematic picking up information outside the bond pad target. Layer analysis of the pad can also be difficult since sputtering rates vary based on the contaminants on the pad and any thermal processing.
How does one evaluate bond pads without a destructive test? Is there a process for accurate bond pad evaluation while minimizing die damage? Sure. The cycle time and costs of these tests can also be a concern particularly for a customer wanting a quick response from failure analysis.
A better method is to bond the die with a gold stud bump followed by selectively etching away the gold. Etching the gold highlights the intermetallics and shows how much of the gold alloyed with aluminum versus blocked oxides. Voiding can be demonstrated, that might be misconstrued as Kirkendall voiding, by cross sectional analysis.
Cost Comparison of 2.5D/3D Packaging to other Packaging Technologies
Authors: Palesko Chet , Palesko Amy , Vardaman E. Jan 
Published: October 2015

2.5D and 3D applications using through silicon vias (TSVs) are increasingly being considered as an alternative to conventional packaging. Miniaturization and high performance product requirements are driving this move, although in many cases the cost of both 2.5D and 3D is still high.
In this paper we will identify the major cost drivers for 2.5D and 3D packaging and assess cost reduction progress, including current costs versus expected future costs. We will also compare these costs to alternative packaging.
Conceptual Development Using 3D Printing Technologies for 8kV SiC Power Module Package
Authors: Ke Haotao , Xu Yang , Hopkins Douglas C 
Published: October 2015

Post-silicon power devices, SiC or GaN for example, have many advantages over traditional silicon devices, particularly for smaller size and higher thermal densities. Although these devices are in the early stage of development, many applications have been identified, such as hybrid vehicles and the smart grid. For power packaging, there is now a greater challenge of much higher voltage, faster switching speed and much smaller package size (higher density). All of these issues call for newer approaches in power packaging.
The microelectronics area has been developing stacked 3D technology along with printed 3D circuit technologies. Of been interested are the 3D printing technologies that can implement complicated structures, such as multilevel interconnects and selective dielectric field enhancements, besides introducing rapid prototyping in the early power stage design cycle. The 3D printing technology, introduced in the late 1980's, is now becoming prevalent. Commercial printers can create high-resolution structures in ceramic, metals (e.g. titanium, copper and aluminum) and polymers. The conceptual design proposed in this paper will incorporate a hybrid approach of traditional structures over-printed with polymers, or more advanced structures over-printed with metal and ceramic.
The design focuses on packaging 1 cm × 1 cm SiC Schottky diode, which has a blocking capability of 8kV with a final target at 15kV. Early use of the package, in keeping with rapid prototyping, is to provide a test vehicle for the device, and prove the application of 3D printed material to high voltage power modules. This paper will present the necessity for packaging new SiC devices, review device characteristics, introduce the use of extruded 3D printing materials for a hybrid structure, and use of jetted/extruded layer-by-layer buildup for total, direct structure creation. Characterization of some available dielectric and metal printable materials, and a test methodology for electrical, thermal and mechanical performance will be discussed. An early-stage example will be shown and extrapolated to higher-level conceptual designs.
Cost Analysis of TSV Process and Scaling Options
Authors: Vartanian Victor , Smith Larry , Hummler Klaus , Olson Steve , Sapp Brian , Barbera Tyler , Golovato Steve , Yu Kai-Hung , Hasegawa Toshio , Hu Shan , Leusink Gert , Maekawa Kaoru , Enloe Jack , Gracias Alison , Pattanaik Gyanaranjan , Wafula Fred 
Published: October 2015

SEMATECH evaluated the impact of various process options on the overall manufacturing cost of a TSV module, from TSV lithography and etch through post-plate CMP. The purpose of this work was to understand the cost differences of these options in order to identify opportunities to significantly reduce cost. Included in this study were multiple process and materials options for TSV etch, liner, and barrier/seed (B/S). For each of these options, recipes were adjusted for post-etch clean, ECD Cu fill and CMP overburden, and the resulting cost impacts were evaluated. The TSV dimensions used in this study are 5x50 μm and 2x40 μm.
These cost comparisons included a sensitivity analysis, highlighting the main factors responsible for the differences. Cost of materials, tool cost, and throughput were the primary factors affecting cost differences, especially in barrier/seed deposition. In some cases the contributions from both these sources were comparable.
We explain the assumptions used and some of the uncertainties inherent in this work. For example, where materials costs were significant, we extrapolated the cost of new materials from research quantities to those needed to support high volume manufacturing. We had to estimate throughputs and materials costs using our best engineering judgment, because the recipes have not yet been optimized. We also considered that the tools used on some non-critical steps might be fully depreciated, or a lower cost tool such as is used in wafer level packaging. Despite these uncertainties and assumptions, we were able to extract some fairly clear conclusions.
The process options include the following B/S variations: For 5x50 μm TSVs, the B/S film structure is TaN/Ta/Ru/Cu, and the options are with and without the Ru and/or Cu layers. For 2x40 μm TSVs, the B/S structure is TaN/Ru/Cu, with different thicknesses of Ru, and the Cu is an optional seed layer for the field. We also discuss the impact of scaling the TSV dimensions on manufacturing costs. This work is continuing to look at different process options and to apply this methodology to MEOL modules such as temporary bond and debond, wafer thinning, and TSV reveal.
Solder Joint Reliability Assessment for a High Performance RF Ceramic Package
Authors: Charbonneau Paul , Ohman Hans , Fortin Marc 
Published: October 2015

The prediction of long term solder joint reliability, (SJR), of microelectronic devices and packaging solutions continues to challenge the microelectronic packaging industry, particularly with the introduction of lead-free materials, the push for higher performance (frequency/speed/thermal) and lower unit cost. High performance packages are generally custom designed and therefore have minimal industry data on configuration specific reliability performance. In this application, the package substrate coefficient of thermal expansion, (CTE), was closely matched to the die resulting in a relatively large CTE mismatch between the package and organic PCB. In addition, the package RF and thermal performance requirements required this particular solution to be configured as a “cavity down” perimeter ball array with a large central ground pad to electrically couple the package to the PCB. Given the package's unique design requirements and CTE mismatch, even modest daily temperature swings of 20°C usually found in a controlled or “Central Office” environment could have an adverse impact on the interconnect reliability.
This study provides an overview of the solder joint reliability assessment methodologies performed for a custom design lead-free, high performance RF package as part of the requirements to demonstrate compliance to product specifications. SJR life predictions were made for varying package BGA configurations using a multi-tiered approach using constitutive material models, thermo-mechanical finite element simulations, and material specific fatigue models. Empirical accelerated life testing was performed and a life prediction obtained through modeling was validated. Finally, statistical failure distributions were fit to empirical data and discussed in the context of absolute solder life predictions of small fractions unit failures, (100ppm).
High Resolution Patterning Technology to enable Panel Based Advanced Packaging
Authors: Ruhmer Klaus , Cochet Philippe , McCleary Roger , Chen Nelson 
Published: October 2015

As the semiconductor industry is maturing, the reign of Moore's law has come to an end. New approaches beyond scaling down transistors have taken over the burden of continued and rapid performance growth. These new approaches are essentially related to integration of components. Decrease of form-factors and increase of functionality and performance is accomplished by sophisticated integration schemes. In other words, back-end Advanced Packaging technologies continue to grow ever more important to not only meet performance and size goals but also to drive down cost.
Although front-end manufacturing is naturally tied to round semiconductor wafers, some of the most recent back-end technologies are no longer required to be performed on round substrates. Embedded die, fan-out and interposer based packages can be manufactured on larger and more convenient substrates such as square and rectangular glass, molded or organic panels thus enabling economy of scale efficiency gains and cost savings.
This work focuses specifically on the challenges surrounding the lithographic patterning of these “non-round” substrates using a high-resolution 2x reduction stepper lithography system. The paper provides an overview of the various panel-based advanced packaging applications including Panel Fan-Out (P-FO), 2.5D glass interposers and high-density organic substrate interposers. The specific lithography requirements and challenges are highlighted and analyzed. These include patterning resolution down to 2μm and beyond, layer to layer overlay accuracy of better than 1μm, depth of focus of 15μm and more, resist sidewall angles of above 80 degrees, ability to deal with topographic variations, ability to handle and process panels with severe warpage, ability to prevent system contamination due to outgassing of photoresists or polyimides, ability to process devices without so-called field stitching only to name a few.
Last but not least, cost implications of the lithography process are analyzed and discussed.
Ultimately, the work attempts to assess the readiness of the industry for panel based Advanced Packaging specifically from a lithography perspective. The potential cost advantages but also the hurdles and challenges related to panel-based advanced packaging patterning technologies are highlighted.
Automated Metrology Improves Productivity and Yields for Wafer Level Packaging in High Volume Manufacturing
Authors: Zao Jin You , Yen Bong Yin , Kuan Lim Beng , Thornell John , Hart Darcy , Marx David 
Published: October 2015

Wafer Bumping In-line Process control of Wafer-Level Chip Scale Package (WLCSP) requires accurate measurement of bump features during processing. These bump features include critical dimension of Redistribution Layer (RDL), Under Bump Metal (UBM) and transparent polyimide thickness. For a 4-Mask Layer Cu plated WLCSP, accurate feature thickness measurement is required for both the Redistribution Layer (RDL) and Under Bump Metal (UBM) to ensure consistent delivery of good electrical performance and package reliability. This is especially important as WLCSP is moving towards finer feature size and pitch to meet increasing demand for smaller form factor.
This paper reports the development of an automated Critical Dimension (CD) measurement solution capable of measuring features at pre-defined locations on different topology both under sampling and full inspection mode on wafer. The solution is fully scalable to meet the requirement of high product-mix HVM environment, by highly adaptive to different features on different products for which measurement needs to be automated for effective process control.
Adhesive Enhancement Technology for Directly Metal Plating on EMC
Authors: Mukai Kenichiroh , Kim Kwonil , Eastep Brian , Gaherty Lee , Kashyap Anirudh 
Published: October 2015

Plating on molding compound is a relatively new field with many possible applications. One major application is magnetic or electrical EMI shielding of active components. This is currently done by metallic cans. However, this technique also increases the space requirements. A second major application, is the formation of build-up circuits on encased components, such as for Fan-out Wafer Level Packaging (FO WLP).
An established method to provide a metallic seed layer is sputtering. However, with respect to cost effectiveness and mass production capability, classical electroless metallization along with an adhesion promoters would a desirable alternative. In this paper we will present a new approach, where components encased by molding compound are directly coated with an electroless copper or nickel layer. By this method spatial requirements are minimized. Also, this process fits into the existing infrastructure within the PCB industry.
Due to the presence of fillers with an extremely high ratio (70–90%wt.) and irregular size (from few μm to tens of μm), classical Desmear followed by electroless seeding can get at best an adhesion of only 2–3N/cm . This is typically insuffient to prevent delamination during further processing. In contrast, with chemically bonding adhesion promoters, as presented in this paper, we are able to get up to 5N/cm of peel strength without any blistering. The plated layer stands up well to reflow shock (260C) and HAST without significant loss of adhesion.
These adhesion enhancement technology is applicable to various kinds of molding compound. Extending this technology to FO WLP (i.e. FO SiP, FO PoP) can be another far reaching application.
Pre-applied Inter Chip Fill for 3D-IC Joining
Authors: Kawase Y. , Ikemoto M. , Sugiyama M. , Kiritani H. , Mizutani F. , Matsumoto K. , Mori H. , Orii Y. 
Published: October 2015

For the conventional two dimensional (2D) packaging of integrated circuit (IC), reflow and capillary under fill have been used for more than a decade. But for the purpose of low power and high performance of IC, three dimensional IC (3D-IC) have been proposed in recent years. In case of 3D-IC, both bump pitches and gaps between stacked thin chips should be fine and narrow, so that pre-applied inter chip fill (ICF) which is applied in thermal compression bonding have been proposed. In this process, not only low viscosity but also thermal conductivity is simultaneously required.
In this study, some of selected epoxy based matrix and filler were simulated and evaluated for pre-applied ICF, we confirmed its process applicability to pre-applied chip bonding. Physical characteristics of cured ICF and void-less joining were also discussed.
Performance Assessment of a Low Temperature Polymer Conductor for Lead-Free Soldering Processes
Authors: Grabey Steven , Shahbazi Samson , Groman Sarah , Munoz Catherine 
Published: October 2015

An increased interest in low temperature polymer thick film products has become apparent due to the rise of the printed electronics market. The specifications for these products are becoming more demanding with expectations that the low temperature products should perform at a level that is typically reserved for their high temperature counterparts; including solderability with lead free solders, high reliability and strong adhesion.
Traditionally, it has only been possible to use leaded solders for soldering to polymer based thick film conductors. Over the last 15 years environmental concerns and legislation have pushed the industry towards a lead free approach. The shift to lead free solders, while beneficial, provides new challenges during processing. The high temperatures required for a lead-free soldering process yield a naturally harsher environment for polymer thick film pastes. In the past these conditions have proven too harsh for the pastes to survive.
The polymer thick film discussed in this document aims to address some of these concerns for a highly reliable and easy to process polymer thick film paste. Due to the poor leaching characteristics of polymer thick films, at elevated temperatures, the predecessors of this paste typically soldered at low temperatures with leaded solders. The goal of this paper is to present a low temperature paste that is compatible with a variety of substrates and readily accepts lead-free solder.
This paper will discuss a newly formulated low temperature curing (150°C – 200°C) RoHS and REACH compliant paste that shows excellent solderability with SAC305 solder. The paste was evaluated using a dip soldering method at 235°C–250°C on a variety of substrates. The data presented includes solder acceptance, adhesion data, thermal analysis and SEM analysis.
Reliability of LTCC using Electroless Nickel Immersion Gold (ENIG) Plating Technology
Authors: Graddy Patricia , Beikmohamadi Allan , Nair Deepukumar , Thrasher Brad , Parisi James 
Published: October 2015

In an effort to address the impact of rising gold costs on the fabrication expense for high frequency circuits, and maintain circuit quality and reliability, the DuPont™ GreenTape™ 9K7 low temperature co-fired ceramic materials (LTCC) with top silver conductors have been evaluated using electroless nickel immersion gold (ENIG) plating. Results comparable to the quality of efficiency and reliability of traditional gold conductor systems were achieved at reduced costs.
LTCC coupons produced using the ENIG process were tested and compared to standard specifications for coupons with gold printed conductors. The test methods used include wire bond and adhesion pull tests on eight layer coupons, and MIL-STD-883 [1] temperature cycle testing on a layered high frequency test pattern. The reliability of the high frequency characteristics including insertion loss and return loss measurements were evaluated periodically throughout 1090 temperature cycles. Adequate results for most applications were obtained using the ENIG plated system compared to gold printed coupons.
In an attempt to better understand the boundaries of the ENIG process on 9K7 LTCC and its use as an alternative for gold conductor systems; future testing will explore the effects of additional environmental testing. The added tests will include thermal shock, and temperature and humidity cycling on 9K7 LTCC test coupons. The testing will be conducted in accordance with MIL-STD-883 as a benchmark, and also evaluate wire bond and adhesion properties. This paper will report the reliability test results on plated GreenTape™ 9K7 LTCC systems after exposure to the stated environmental conditions.
A Novel Thin Wafer Handling Technology to Enable Cost-Effective Fabrication of Through-Glass Via Interposers
Authors: Lee Alvin , Su Jay , Arnold Kim , Bai Dongshun , Wang Bor Kai , Tsai Leon , Shorey Aric , Shen Wen-Wei , Chien Chun-Hsien , Chang Hsiang-Hung , Wang Jen-Chun 
Published: October 2015

Thin wafer handling technologies to fabricate silicon interposers have been widely discussed at conferences. Despite tremendous efforts to overcome several technical hurdles such as wafer chipping, cracking, and warpage, high manufacturing costs resulting from the complexity of the processes used to make silicon interposers remains a major concern.
Fabricating a through-glass via (TGV) interposer using novel thin wafer handling (TWH) technology will be presented here as an example of a simple and cost-effective solution for realizing 2.5-D IC integration. Utilizing a simplified TWH technology, a TGV interposer with 30-μm-diameter vias to eliminate the isolation layer is combined with polymer-based polybenzoxazole (PBO) as passivation to build one to two redistribution layers (RDLs) with 20-μm line width on both sides after thinning to 100 μm. The simplified TWH requires only a release layer on the glass carrier and another layer of bonding material on the TGV wafer to enable fabrication of a TGV interposer.
A process flow for fabricating a TGV interposer utilizing a simplified TWH technology will be presented in detail, including carrier treatment, bonding material, bonding, titanium/copper seed layer deposition, copper plating, RDL deposition, under-bump material (UBM) formation, debonding, and silicon chip stacking on a TGV interposer. The combination of TGV interposer and novel TWH technology will pave the way for cost-effective fabrication in 2.5-D IC.