bluuebunny/crossref_metadata_2025_split huggingface dataset:
Processing, Bumping and Assembly of Single Chip Plated Ni/Pd over ALCAP Bond Pads for Flip Chip Applications and Prototyping
Authors: Lewis Brian J. , Baldwin Daniel F. , Houston Paul N. , La Le hang , Spark Tim 
Published: October 2015

For Designer and Engineers, it is common during the process development cycle for new products to have limitations on the materials that are available for the prototype work. Most SMT devices are readily available in different formats/solder alloys to satisfy most of the needs for passive needs. However, many times IC devices are limited to what is available from the fab or an IC broker. These limitations can mean that die only come in aluminum, wirebond ready I/O metallization or that the silicon wafers already sawn and in single die formats. For applications where advancement in performance or miniaturization is needed, and the benefits of flip chip technology are attractive, then it is not trivial to be able to use these die. In these cases, the process of adding solderable plating technologies to the I/O bond pads is very favorable. The technologies are currently run for wafer lever plating baths, but very little has been done to evaluate single chip plating. Work in plating Ni/Pd onto the ALCAP structure has been performed to evaluate the process and feasibility of processing groups of singulated die with aluminum bond pads.
The work to be detailed in this paper will go through the chemistries used in the plating process onto an aluminum bond pad that makes it suitable for flip chip processes. Several bumping structures, such as solder bumping over this plating technology and plating over gold or copper stud bumps, are evaluated. A process for bumping the flip chips is also detailed. The data for shear testing of the 10 variations before and after 500 liquid thermal shock cycles is detailed. Finally, a comprehensive study for assembly of solder bumped flip chips, with the selective plating process, will be detailed as well as a detailed analysis of the TC reliability of this assembly approach. It will be shown that selective Ni/Pd plating onto single, ALCAP bare die can allow for these typical wirebond die can be used in a practical approach solder flip chip process and provide reasonable reliability results when compared to a mainstream, wafer processed, solder bumped flip chip die.
ChipsetT: Embedded Die Substrate Applications
Authors: Aday Jon G. , Tessier Ted , Itoi Kazuhisa , Okude Satoshi 
Published: October 2015

Embedded die substrate technologies are being developed in an assortment of configurations and for different market segments. The technology being discussed in this paper will be focused on both a fan out technology – ChipsetT Fan-Out and a system in package approach (ChipsetT SiP) in which a multiple component bill of materials (BOM) is used. The Chipset process is based on the WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multilayer polyimide flex wiring and conductive z-axis sintered metal interconnections.
This ChipsetT Fan Out technology allows for large scale production of fan out type solutions which can allow for very thin packages in addition to unique pin out solutions such as pin compatibility for a competitor part.
The ChipsetT SiP also allows embedding of single or multiple silicon die and/or components. Additional components can also be placed using conventional SMT on the top or bottom side of the package. There is a great deal of design flexibility with this technology which makes it a great solution for applications trying to reduce their x-y size or z-height. When utilizing RDL technology on the embedded die we are able to do the fine pitch routing in order to allow the substrate to route at larger pitches ensuring an overall cost effective solution.
This paper will focus on the different classes of applications that have benefited from this technology and will discuss the benefits and tradeoffs of the different solutions that have been engineered. Assembly and reliability data will be presented on several of the applications showing a robust solution set.
RF devices: from WLSCP to smart interposers
Authors: LAMY Yann , Bouayadi O. El , Ferrandon C. , Joblot S. , Jouve A. , Dussopt L. , Lacrevaz T. , Bermond C. , Fléchet B. , Simon G. 
Published: October 2015

RF wireless devices such as 3G/4G, Wifi, Bluethooth etc... represent today 32% of the whole WLCSP products which know a steady grow above 10% per year [1]. However, a clear trend of combining multi RF chips in one WLCSP module is emerging. This allows shorter RF connections, reduction of BOM and diminution of the overall cost. Complex and heterogeneous RF systems will become possible allowing soon tunability. A silicon package directly reported on board is a good candidate to meet these next challenges of RF WLCSP. Indeed, low cost and multi-chips interposers will soon be produced by TSV fabs or OSATs and tunables devices could be reported on them. But the direct report on board as well as the high frequency signal integrity must be first evaluated carefully.
In this work, we describe promising results of silicon package based on high resistive silicon interposer encompassing 2 levels of Cu Damascene, Tx/Rx antenna, one RF chip and TSV last for 60GHz applications. A new wafer-level molding [2] is performed on front side by lamination at wafer level. On the backside of the interposer, thick Cu RDL and soft layer passivation is deposited before the balling. Just like in WLSCP, different kinds of solder balls are mounted and analyzed with respect to their size (350 or 400 μm) or type (solder or polymer/solder). The passivated interposers are diced and then reported on a PCB, thus forming the silicon package. Low Rf loss (&lt;1dB) attenuation is demonstrated for the routing layers while the antennas exhibit a suitable gain of 5dBi over the 55–65 GHz band. The assembly characteristics between the silicon package and the board will be discussed with respect to the different chosen design rules.
These first results pave the way to a new kind of smart package based on Si interposers, moving forward to more complex WLCSP RF devices.
Lead Free Paste with under 3um Solder Particles for Fine Pitch C4 bumping and pre-coating solder applications
Authors: Uno Hironori , Ishikawa Masayuki , Masuda Akihiro , Muraoka Hiroki , Kuba Kanji 
Published: October 2015

The work to be detailed in this paper is our development of 96.5mass%Sn-3.0mass%Ag-0.5mass%Cu fine solder particles with an average particle size of under 3um (D50), using a chemical reduction method. An evaluation was conducted on the properties of the particles. The average size of particles appeared to be under 3um with a higher yield compared to particles using the conventional gas atomization method. The melting temperature of fine solder particles using this method was its eutectic temperature, which is same as using the gas–atomized particles.
120um pitch solder bumps from the solder paste using the above mentioned fine solder particles were created on the substrate. As a result of property evaluation, it was turned out that the solder paste created a superior printing shape and coplanarity compared to the conventional paste with gas-atomized particles.
In order to investigate the superior printing property generated by the paste with fine solder particles, the rheology of the paste was evaluated.It was verified that the anisotropic shape of particles has contributed to prevent the printed paste from slumping, which has resulted in the improvement of printed shape. It also shows that the filling characteristic of the paste was improved by the smaller particles and the better coplanarity was observed. The importance of finer solder particles for finer pitch assembly will be presented.
From Mechanical to Chemical Adhesion
Authors: Hsieh Meng , Libman Ellina , Brandt Lutz 
Published: October 2015

In the development of electronic systems, the miniaturization of electronic devices is strongly driven by the market and technology demands within the portable electronics sector. This size reduction affects all subsystems and components. Such reduction is observed in circuitry as the conductor lines and space dimensions are now aiming at dimensions significantly below ten microns. This continuing trend in miniaturization leads to challenges as printed circuits (typically copper) must adhere to a new generation of dielectric substrates, typically highly filled organic resins, for performance and reliability reasons.
Good adhesion of chemically deposited copper to the dielectric surface is currently achieved through mechanical means. The dielectric surface is typically chemically roughened or desmeared. Copper deposited onto the roughened surface will have good adhesion as surface features act as anchoring points. As the dimensions of the circuitry are reduced, a highly roughened surface becomes increasingly undesirable, as it will ultimately create poor line definition or even shorts in the circuit. On the other hand insufficient roughness will result in poor adhesion. It is evident that other means of adhesion (for example, chemical) will become necessary for smaller line widths.
This paper will review the current process for treating the dielectric surface for the subsequent deposition of electroless copper and will compare it to new treatments. The data presented will show that improved copper-to-dielectric adhesion with minimal roughening can be achieved with the new treatments. The origin of the improvement in adhesion is attributed to chemical bonding.
LEDs for SSL - Market Review and Forecast
Authors: Bhandarkar Vrinda 
Published: October 2015

This presentation presents an analysis of the worldwide market for LED packages and a market forecast for 2013 through 2016. It attempts to capture the adaptation of LEDs in various lighting applications and the transformation of the marketplace as it shifts to the new lighting technology.
We will also provide an overview of the structure of the lighting industry, the drivers for growth of the lighting market, the specific drivers for growth of LED lighting, and the challenges to further development of the LED lighting market.
The analyses of the top applications for LED in lighting — including 2012 market data and a forecast are presented.
Lithography for Wafer Level Packaging for LED Manufacturing
Authors: Hornung Michael 
Published: October 2015

Since LED became an attractive alternative for general lighting, the market demand for higher brightness, higher efficiency and lower costs was the motivation for improving the LED technology. Locking in on the LED manufacturing process, most steps are on die-level after chip singularizing and therefore the costs are dominated by the huge number of dies which could often reach several thousand dies on one wafer. It's obvious that WLP has a clear benefit for LED packaging and it is also the path to success for LED manufacturing. Moreover, it also allows the implementation and integration of additional functionalities to the LED chip module, e.g. electrical connects, Zener-Diode, mirrors, optics drivers etc.
Nonetheless, a clear important aspect to adopt WLP for LED manufacturing is to benefit from existing know-how of the IC manufacturing technology and of the experience of the equipment suppliers for this industry. However, the equipment needs to be optimized for the dedicated LED-WLP application. For example, microlithography with mask aligners is widely used for LED chip manufacturing, but the illumination system of these mask aligner are typically optimized for highest resolution which means contact lithography. For LED-WLP the optical systems must be capable for customized illumination for proximity lithography, where the photo mask and the wafer are separated by a proximity gap of typically 30 to 200 microns. Here, diffraction effects limit the resolution and fidelity of the pattern generated or printed in the photoresist. These diffraction effects are related to the mask pattern and the angular spectrum of the illumination light.
The requirements on the lithography process for LED-WLP will be explained and discussed. Experimental results of perfect 3D patterning on topographies up to several hundred microns will be shown.
A Process Dependent Warpage and Stress Model for 3D Packages Considering Incoming Die/Substrate Warpage and Assembly Process Impacts
Authors: Lin Wei , Syed Ahmer , Lee KiWook , Dhandapani Karthikeyan 
Published: October 2015

Warpage control and die stress are critical for 3D package assembly. Currently most of the warpage studies, either measurements or simulations, are mainly evaluated at the end-of-line (EOL) for the finished package. However, for 3D packaging such as multiple die stacking or through-silicon-via (TSV), the interaction between warpage and assembly process steps becomes far more important because: (1) Warpage at each single process step will impact the yield of the next process step. (2) Process induced warpage will accumulated and affect the final end-of-line package warpage, and (3) Die stress in the end-of-line package is highly dependent on the incoming die alone residual stress and the assembly process flow. It is required to develop capability to evaluate warpage at each process step following the process flow.
In this paper, we use a 2-die TSV package as a test vehicle to collect warpage data at each assembly step. A process dependent finite element model (FEM) method is developed which is capable of capturing the process induced warpage and stress at each process step based on the process condition.
Shadow moire is used to measure warpage data at following check points: (1) Incoming bare dies and bare substrate warpage; (2) Die 1 warpage after underfilled on substrate; (3) Die 2 warpage after TCNCP on Die 1; (4) Completed package after molding (end-of-line).
Element birth and kill approach is developed in the FEM model to simulate the assembly process flow. In each process step, only the presented components and materials in the model are active while the others are killed. When new parts or materials are added through the assembly flow, they are activated in the model and the related process condition is applied for each step. Using this process dependent modeling approach, excellent correlation of the model results with the actual measured warpage data is achieved at each process step.
One factor often been ignored is the incoming bare die warpage and bare substrate warpage effect. They are often assumed flat and stress free. However, as die and substrate become thinner and thinner, their incoming initial warpage or residual stress plays an important role. In this paper, the measured incoming substrate and die warpage data are presented, their impacts to the warpage and stress evolution through the process flow are evaluated. A novel method is also developed in the simulation model which is able to study the incoming die/substrate warpage and residual stress effect.
ADVANCED ORGANIC SUBSTRATE TECHNOLOGIES FOR HIGH PERFORMANCE, HIGH RELIABILITY ELECTRONICS MINIATURIZATION
Authors: Bagen Susan , Alcoe Dave , Blackwell Kim , Egitto Frank 
Published: October 2015

High reliability applications for high performance computing, military, medical and industrial applications are driving electronics packaging advancements toward increased functionality with decreasing degrees of size, weight and power (SWaP) The substrate technology selected for the electronics package is a key enabling technology towards achieving SWaP. Standard printed circuit boards (PWBs) utilize dielectric materials containing glass cloth, which can limit circuit density and performance, as well as inhibit the ability to achieve reliable assemblies with bare semiconductor die components. Ceramic substrates often used in lieu of PWBs for chip packaging have disadvantages of weight, marginal electrical performance and reliability as compared to organic technologies. Alternative materials including thin, particle-containing organic substrates, liquid crystal polymer (LCP) and microflex enable SWaP, while overcoming the limitations of PWBs and ceramic.
This paper will discuss the use of these alternative organic substrate materials to achieve extreme electronics miniaturization with outstanding electrical performance and high reliability. The effect of substrate type on chip-package interaction and resulting reliability will be discussed in detail, and compared to standard PWB and ceramic. Microflex assemblies to achieve extreme miniaturization and atypical form factors driven by implantable and in vivo medical applications are also shown.
Adhesive Enabling Technology for Directly Plating Copper onto Glass
Authors: Brandt Lutz , Liu Zhiming , Fu Hailuo , Hunegnaw Sara , Magaya Tafadzwa 
Published: October 2015

Reliable adhesion of copper to glass is a major hurdle for the entry of glass substrates into the electronic packaging market. Otherwise, glass is a strong competitor to organic substrates due to its superior flatness, thermal and dielectric properties. These are essential requirements for high density interconnects, high speed signal transfer and IC substrate packaging.
Typically, adhesion on glass is achieved by sputtering a thin metallic adhesive (Ti) and copper seed layer followed by galvanic plating.
This paper presents a promising wet-chemical alternative to sputtering. In this new approach a 50-200 nm thick adhesive metal oxide layer is deposited by a modified sol gel process followed by sintering, thus enabling electroless, and galvanic metal plating directly on glass.
Formerly the thickness of the galvanic copper layer constituted a major challenge leading to its facile delamination from the glass. With the new approach, Cu film thickness of over 50 μm can be applied without delamination. Adhesion at 15 μm Cu thickness as measured by 90o peel strength tests can achieve 5 N/cm or even higher values, while 2 N/cm appear to be sufficient to prevent delamination. In comparison, Ti/Cu sputtered glass substrates achieve at best 1.5 N/cm at the same copper thickness, while electroless Cu seeded glass substrates without the adhesive metal oxide layer show no adhesion.
The effect of glass roughness on adhesion was also studied. It does appear to have only a marginal impact on adhesion. On the other hand, the glass type has bearing on the achievable adhesion values. The plated layer stands up well to reflow shock (260C) and HAST without significant loss of adhesion. Good adhesion has been also demonstrated inside the via holes of patterned substrates without indication of blockages by the process.
The process is versatile in that it is also applicable to ceramic substrates such as aluminum oxide.
Pulsed 2 Micron Wavelength Fiber Lasers for Packaging
Authors: Jiang Shibin 
Published: October 2015

Fiber laser sources near 2um wavelength have attracted intense interest in recent years because of the combination of high laser efficiency, strong absorption of many visible transparent materials, outstanding reliability, as well as retina safety. In this presentation, we report our latest developments of various 2um fiber lasers at AdValue Photonics for packaging applications, especially Q-switched and mode-locked 2um fiber lasers using our proprietary infrared glass fiber technology.
We demonstrated and commercialized the first all-fiber Q-switched single-frequency laser at a wavelength near 2um using our proprietary rare-earth doped gain fibers. The laser pulsewidth can be 20ns and 180ns, and the peak power can be more than 10kW. Most transparent plastic materials have a relatively strong absorption near 2 micron wavelength, so 2 micron Q-switched fiber laser is one of the ideal laser for transparent plastic welding, marking, cutting, and drilling. Silicon has a good optical transmission near 2 micron wavelength, which allows 2 micron Q-switched to process the material after pass through the silicon wafer as well as remove residual materials containing any organic components. In this presentation we will describe detailed experimental results and present material processing samples for packaging applications.
Progress in Fabrication and Test of Glass Interposer Substrates
Authors: Shorey Aric , Pollard Scott 
Published: October 2015

There is growing interest in applying glass as an interposer substrate for 2.5D/3D applications. Advantages of glass based solutions include significant opportunities for cost benefits by leveraging economies of scale as well as forming substrates at design thickness.
A lot of work is being done to validate the value of glass as an interposer substrate. One important area is the electrical performance of glass relative to silicon. Because glass is an insulator, it is expected to have better electrical performance than silicon. Electrical characterization and electrical models demonstrate the advantages of the insulating properties of glass, and its positive impact on functional performance. Further advantages are anticipated in reliability performance, because of the ability to adjust thermal properties such as coefficient of thermal expansion (CTE) of glass.
Progress in the ability to fabricate wafers and panels fully populated with through and blind holes has been reported. We describe the ability to leverage existing downstream processes such as via filling of both through and blind vias, as well as novel handling techniques to enable processing of thin glass. We also report progress in evaluating reliability through thermal cycle tests.
Development of Passives on Sapphire Backside
Authors: Ahmad Syed Sajid , Bauer-Reich Cherish , Haring Fred , Strommen Greg , Mattson Kevin , Reinholz Aaron 
Published: October 2015

This work is an effort to demonstrate the convenient use of sapphire backside for placing support circuitry for device densification. Laser micromachining is used to form capacitors and inductors on the backside of sapphire. After their fabrication, they can be connected to the circuitry on the front side of sapphire using through-sapphire vias. Antenna, inductor and capacitor design variations have been formed on the backside of sapphire. Here we describe the development work carried out to form such elements on sapphire backside.
Elements were designed and their electrical attributes were simulated. The designed elements were then fabricated on sapphire by laser patterning sputtered and plated surfaces. Physical dimensions of the fabricated elements were compared with designed elements. Electrical measurements on the fabricated elements were compared with initial designs and simulations.