bluuebunny/crossref_metadata_2025_split huggingface dataset:
THERMAL MANAGEMENT SOLUTIONS FOR THE LED MARKET
Authors: Kintz K. Andrew , Paisner Sara N. , Thompson M. Shane 
Published: October 2015

High-brightness light emitting diodes (LEDs) are challenged with thermal management issues due to increased power and reduced surface area. This has led to the need for new materials with higher thermal conductivity that can quickly remove the heat from the active layer. LORD Corporation has developed two new thermal management materials, a “no pump-out” thermal grease and a low modulus die attach adhesive, as solutions to the heat dissipation problems facing LED manufacturers. These innovative technologies will help engineers solve complex fundamental thermal management problems.
A new 4 W/mK silicone thermal grease has been developed with significant resistance to in-package bleed-out or pump-out eliminating the reliability problem most commonly encountered with traditional thermal greases. A new 10–20 W/mK thermal epoxy adhesive has also been developed creating a new class of flexible adhesives with high adhesion. This combination allows the new LORD die attach adhesive to not only effectively transfer heat out of the package, but also to dissipate the stress caused by thermal expansion and contraction during thermal cycling thereby affording improved package reliability.
High Yield, Near Void-Free Assembly Process of a Flip Chip in Package Using No-Flow Underfill
Authors: Lee Sangil , Baldwin Daniel F. 
Published: October 2015

The advanced assembly process for a flip chip in package (FCIP) using no-flow underfill material presents challenges with high I/O density (over 3000 I/O) and fine-pitch (down to 150 μm) interconnect applications because it has narrowed the feasible assembly process window for achieving robust interconnect yield.
In spite of such challenges, a high yield, nearly void-free assembly process has been achieved in the past research using commercial no-flow underfill material with a high I/O, fine pitch FCIP. The initial void area (approximately 7% ) could cause early failures such solders fatigue cracking or solder bridging in thermal reliability. Therefore, this study reviewed a classical bubble nucleation theory to predict the conditions of underfill void nucleation in the no flow assembly process. Based on the models prediction, systematic experiments were designed to eliminate underfill voiding using parametric studies. First, a void formation study investigated the effect of reflow parameter on underfill voiding and found process conditions of void-free assembly with robust interconnections. Second, a void formation characterization validated the determined reflow conditions to achieve a high yield and void-free assembly process, and the stability of assembly process using a large scale of assemblies respectively.
This paper presents systematic studies into void formation study and void formation characterization through the use of structured experimentation which was designed to achieve a high yield, void-free assembly process leveraging a void formation model based on classical bubble nucleation theory. Indeed, the theoretical models were in good agreement with experimental results.
Thermosonic Gold to Gold Intermetallic Advantages for CSP Packaging
Authors: Couts Philip 
Published: October 2015

Flip chip thermosonic back end assembly method is a low cost clean gold to gold interconnection method. The advancement of flip chip thermosonic process for CSP packaging of HBLED and CMOS image sensors is occurring due to the precision intermetallic clean interconnection properties and ability to provide a small form factor packaging to consumer products. This paper will investigate thermosonic metal to metal interconnection process for these high growth assembly markets.
Thermosonic bonding uses a micro weld interconnection die attach method at lower bonding temperature (150°C). The thermosonic metal to metal interconnection method is lead free and the process does not use flux or solder alloys. Thermosonic flip chip die attach process uses a robust individual die “scrubbing” process which reduces assembly steps and eliminates the mass reflow oven used commonly in C4 solder process.
The metal to metal interconnection method provides excellent thermal performance for HBLEDs which require the Tj peak temperature to be controlled to maximize device MTBF and overall color temperature performance. The uses of metal to metal interconnection method provide superior thermal performance when compared to solder alloys.
The metal to metal interconnection method provides high precision with low particle generation for high performance bonding of CMOS image die using a low-k dielectric wafer. The line spacing for the substrate is 50 μm / 50 μm. Stud bumping machines have a ball placement accuracy of +/− 2.5 μm. Thermosonic GGI die bonders have a mounting accuracy of +/−7 μm.
Thermosonic bonding has fast process bonding times of &lt; 500 msec which is important productivity factor in cost sensitive cell phone camera and flash modules.
Molded Underfill (MUF) Technology Development for SiP Module with Fine Flip Chip
Authors: Yoo Do-Jae , Kim Ki-Chan , Kwak Young-Hoon , Jang Min-Seok , Ha Job , Doh Jae-Cheon , Lee Chang-Bae , Kweon Young-Do 
Published: October 2015

In this study, we developed the Molded Underfill (MUF) technology for system in package (SiP) module with fine pitch flip chip in RF application, in which two flip chips, LC filter, and additional passive components are integrated side-by-side. This study covered not only MUF reliability performance but also MUF design study focused on the void free methodology to minimize void between flip chip bumps in the SiP module. The investigation comprises several aspects: A design study that present a printed circuit board (PCB) and epoxy molding Compound (EMC) selection approach, air vent design of cavity vacuum molding, and void formation mechanism by mold flow simulation and DOE(Design of Experiment) of several SIP module layouts.
The test vehicle used for this study of MUF by vacuum transfer molding shown as SiP module (8.2×7.7×1.13mm) which was sawn from 52.70×68.70×0.75mm mold area of 118.5*75.5*0.38 substrate. One segment mold inside (52.70× 68.70×0.75mm) had 35ea SiP modules (7X5 unit array). In addition, one SiP module included one Flip chip RF/BB IC(6.51×5.81×0.41mm) which had 339ea bumps and 95um Bump height, one Flip chip RF switch (0.705×0.705× 0.33mm) which had 4 bumps and 85um bump height, 1.6×0.8×0.6mm size of LC filter, and total 25ea passives.
In the end, SAT result of void, moisture sensitivity test, thermal cycle test and pressure cooker test had also been carried out for reliability evaluation. The test result shows that the optimized SiP module with fine flip pitch has a good reliability performance.
The Future of Maximum CAD/CAM Automation for Ceramic Hybrids
Authors: Sovinsky John 
Published: October 2015

New concepts recently developed maximize CAD/CAM automation for all types of Ceramic Hybrids including Thick Film, Thin Film, LTCC and HTCC. Designs can now go quickly from concept to manufactured product, which will fuel more progress to bring a largely manual process to maximum automation, to include automatic masks, panels and generation of 3D analysis models. Maximum automation results in expanded use of technologies that are now shrinking. Technologies that have complex and difficult to understand design and manufacturing steps have a hard time gaining wide acceptance.
CDS is tackling this complex challenge and is designing and implementing the following processes to solve the most difficult CAD/CAM problems:Be a true CAM tool that reads in designs from any other EDA (layout) system. YRun all possible DRC checks necessary for high fabrication and assembly yield. YMake all manufacturing masks automatically from very basic designs by using settings in an automatically configurable table. YPanelize all types of Ceramic designs in preparation for manufacturing. YGenerate documentation automatically through from stored configuration files. DIn LTCC and HTCC, place cavity punches (nibbles and rubs) automatically and feed correct machine data to the punch machine. YExport resistor trimming data directly to the laser trimming machine. FFeed flying probe test data directly to the flying probe tester. DAutomatically make a 3D Image and export ACIS or STEP for thermal analysis. DExport data directly to all electrical analysis and thermal analysis tools. PSupport circuit fabrication on non-planar surfaces. FMake full 3D analysis models of circuits on non-planar surfaces.F
The purpose of this paper is to define what is required for the Ceramic Hybrid Microelectronics industry to realize full automation in design, checking and output to manufacturing. Your ideas are welcome.
A Systematic Approach for Creating a System-In-Package (SIP)
Authors: Sadri Sam , Le Tri , Althouse Stephanie A. 
Published: October 2015

Over the past several decades the quest to design electronics that boast ever increasing capabilities while continuously decreasing their size and weight has led to the development of a series of new packaging solutions. As the need for more functionality in less real estate increased, Multiple Chip Modules (MCM) were no longer satisfactory in many applications. Today, these applications call for a highly integrated packaging approach which often incorporates multiple functionalities into one package. In situations where time to the market for SOC (System on a Chip) is too slow or too costly the approach of System-in-a-package (SIP) can be the ideal solution.
One element in modern packaging is the use of new 3D structures and high-k dielectric materials. The second element is advanced packaging methods. New technologies such as chip-on-chip assemblies have been developed. The third element has been the progression in design tools that allow engineers to seamlessly design an overall, highly integrated system. The forth element, testing, is often an expensive part of product development. With SIP technology that cost can be significantly lowered, making new product development economically more feasible.
In this paper we present a systematic approach to designing highly integrated and miniaturized SIP packages. This approach enables rapid design, prototyping and time to production while achieving a new level of integration, miniaturization and reliability.
Finally, a case study is presented to demonstrate a typical maturity cycle of a SIP, in this case for a wireless application.
Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration
Authors: Li Zhaozhi , Lewis Brian J. , Houston Paul N. , Baldwin Daniel F. , Stout Eugene A. , Tessier Theodore G. , Evans John L. 
Published: October 2015

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced.
Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer.
100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.
Fine Pitch 3D Dispensable Electrical Interconnects for System In Package Solutions
Authors: Leal Jeff S. , Pangrle Suzette K. , Whyte Charles , Barrie Keith , Leff Jeff , McGrath Scott , Ayala Gerardo 
Published: October 2015

The use of dispensable conductive materials to create fine pitch 3D electrical interconnects has been proven by Vertical Circuits Inc. as a low cost, high reliability alternative to create System in Package (SIP) solutions.
This paper discusses the benefits of dispensing the 3D electrical interconnects instead of using traditional wire bond or high cost TSV processes to create a System in Package. Pad pitches achieved are typically less than 65um. A conformal coating of a dielectric material with the subsequent selective laser ablation of the dielectric over the die pads allows all interconnect lines to be dispensed in a single application adjacent to each other. Compared to traditional wire bond applications, the overall interconnect inductance is lower with comparable capacitive and resistance values enabling higher frequencies to be achieved.
Using this process, complex multi-step stacking and bonding applications that jeopardize known good die (KGD) and increase the XY footprint of the System in Package are eliminated. Furthermore, the entire die stacking process can be executed as a single step before the application of the electrical interconnect material. This method minimizes the overall material handling and repetitive die stack processes that increase the probability of defects leading to expensive yield losses.
Methods for matching the Coefficient of Thermal Expansion (CTE) for the stacked components within a System in Package will be demonstrated as well as surface treatments to enable fine pitch dispense that result in increased product reliability. JEDEC L3 reliability data will be presented to demonstrate SIP robustness using this technology.
Pinout Optimization for 10 Gbps+ Serial Link Routing
Authors: Siadat David , Priest Judy 
Published: October 2015

Definition and optimization a BGA (ball grid array) package pinout is a complicated process. Multiple factors must be considered, such as chip level floorplan, board placement of the component, the board stackup, escape routability, and signal and power integrity constraints. These tradeoffs and decisions impact package body size and board real estate, therefore overall system cost.
At high frequencies, such as &gt;10 Gbps, the BGA to board via transitions cause visible impedance and noise mismatches and becomes a critical factor in the end to end channel design. Determining BGA pin assignments and their PCB transitions must meet the package crosstalk constraints within the required commodity PCB technology manufacturing rules. This paper describes a methodology of extracting 4 differential signal pairs in the board file from BGA ball to its PCB via transitions through BGA pin field into 3D field solver. The extracted geometry is simulated to determine near-end and far-end crosstalk noise levels between a single victim pair and its associated aggressors. Different pin assignment designs will have different number of aggressors to consider. Different routing layers will also produce different signal via stub lengths (specific resonant frequency) and signal via coupling contributing to far-end crosstalk noise. This may require back drilling of differential signal via stubs to minimize this noise.
The aggregated crosstalk noise level must be equal to or better than what the package can deliver. Once these design rules are determined, they can be leveraged across all channels running at the same frequency.
High via density thin metal-core PCB using electro-coated dielectric
Authors: Scholz Bernd , Pekmic Ismir , Ahmad Syed Sajid , Reinholz Aaron 
Published: October 2015

Conventional printed circuit boards (PCBs) may be replaced by thinner metalcore boards for some applications, as well as for package substrates. Using thin, metalcore technology may provide advantages for radio frequency (RF) circuits and packages, and increase heat dissipation for high power applications.
The metalcore technology has several layers including the metal core, electrocoated dielectric, sputtered metal layers, and electroplated copper. Especially for RF application and automotive electronics printed circuit boards with a metal core is gaining interest. The advantage of metal core PCB is the low thermal coefficient as well as the possibility to achieve a high density of vias and electronic component assembly.
This paper describes the realization of metal core PCB with a dense array of vias and with a low thermal coefficient. The dielectric layer is applied after vias have been formed providing a high density electronics assembly on a double sided PCB which exhibits the heat dissipation of a metal core with minimal thermal expansion. After photochemically etching an array of vias, the metal core can be optionally plated with copper. The insulating dielectric is applied using a highly reliable electrodeposited coating. Metal core substrate provides the opportunity to form a via to the metal core to provide electrical grounding. The final traces are fabricated on top and bottom and can be interconnected through via openings.
Pure Palladium and Palladium Phosphorus Depositions Used in ENEPIG and ENEP Surface Finishes – Comparison of Physical Properties and Their Influence on Soldering and Au Wire Bonding
Authors: Oezkoek Mustafa , Roberts Hugh , McGurran Joe 
Published: October 2015

As a surface finish, electroless nickel / electroless palladium / immersion gold (ENEPIG) has received increased attention for both packaging/IC-substrate and PWB applications. With a lower gold thickness compared to conventional electroless nickel / immersion gold (ENIG) the ENEPIG finish offers the potential for higher reliability, better performance and reduced cost.[1,2]
This paper shows the benefits of using a pure palladium layer in ENEPIG and ENEP (Electroless Nickel / Electroless Palladium) surface finishes in terms of physical properties and in terms of gold wire bonding and solder joint integrity.
Sensor Packaging: New Challenges for New Applications
Authors: Beelen-Hendrikx Caroline , Tak Coen 
Published: October 2015

Advantages of silicon-based sensors are compatibility with CMOS, improved robustness and reliability, smaller size and reflow compatibility.
Biosensors that use an electrical measurement principle need electrical connections and fluidic access to the die. This only works when the electrical interconnects are kept clean of biofluid and when the package is compatible with the biofluids, receptor chemicals and other sensor elements. In addition, the package needs to be very cheap. A simple plastic overmolded package with a hole in the compound at the sensor location is an effective solution.
RFID sensors also need direct die access for gass and pH sensing. They require the integration of processor, memory, clock, battery and antenna. The package format depends on the application. For checking the quality of perishables during transport or in a store, a disposable flexible tag is needed whereas for smart building sensors, a plastic module is more appropriate. For the sensor tag, a flexible substrate and flip chip bare dies are used. Direct die access is realized by an opening in the flex. Battery and antenna are printed on the flex.
Automotive sensors that are used under the hood need to cope with very high operating temperatures with peak temperatures of up to 200 °C and they need to be delamination free. The critical points in the standard plastic packages used today are the molding compound and the wire-bonds. Standard packages can be used up to 150 °C. For higher temperatures, the molding compound and the wire-bond interconnect are being improved.
Hermetic Sealing of Stainless Steel Packages by Seam Seal Welding
Authors: Marinis Thomas , Nercessian Berj 
Published: October 2015

Welded stainless steel packages offer a number of advantages relative to those fabricated from kovar or aluminum metals and braze sealed. They are highly resistant to corrosion, especially in aqueous or elevated temperature environments, are mechanically stronger, dramatically so at temperatures above 100°C, exhibit lower outgassing rates, and have better vibration characteristics. Since welded stainless steel packages do not require over plating to facilitate braze sealing, combined material and fabrication costs are lower than kovar or aluminum packages. Also, unlike kovar, stainless steel is nonmagnetic, which is advantageous in many electronic applications.
For sealing stainless steel packages, we elected to use seam sealing rather than laser welding for two reasons. Seam sealing subjects the package contents to lower thermal excursions than laser welding because less material is melted to achieve a weld in seam sealing. Second, seam sealing confines the molten material between the cover and package, where as laser welding produces a surface filet. Consequently, there is more opportunity for molten metal to splatter or react with the atmosphere in laser welding than in seam sealing.
We successfully developed a process to weld a 2 millimeter thick cover onto a box with dimensions of 75 mm long by 50 mm wide by 15 mm deep using a seam sealer. The box walls were 1 mm thick and were penetrated by a dozen glass insulated feedthrus on one side. Both cover and box were fabricated from 316L stainless steel. A combination of analytical and finite element modeling were used in conjunction with a designed experiment to optimize the process variables of roller angle, speed and pressure, weld current, pulse shape, duration and spacing, number of weld passes, and sealing atmosphere. Weld quality and seal integrity were evaluated by leak testing before and after environmental stressing, mechanical testing and metallographic cross sectioning. The effects of component dimensions and tolerances on seal integrity were also investigated. Particular attention was paid to cover flatness, flange thickness, and tightness of fit between the cover and box. The process development was concluded by conducting a qualification experiment that used the optimized process parameters with controlled variation about their nominal values. A 100% yield of sealed boxes was obtained. These test articles were then subjected to various environmental screening tests, which were all passed with no failures.
Modeling of a heterojunction bipolar transistor based AlGaAs / GaAs
Authors: Bedia A. , Ghaffour D. , Guen-Bouazza A. , Bouazza B. , Ghaffour K. 
Published: October 2015

The simulation of the physical components semiconductor uses approximations varied depending on the type of devices to study and expected effects. Also, the systems obtained are rarely simple to solve. Numerically, the transportation problems are most difficult to discrete. It should also be noted that the problem is strongly nonlinear, coupling quantities very heterogeneous and are not at all in the same order of size. It should be noted moreover than the exploitation of the physical models can be conceived only if the computing times remain reasonable.
The physical model as simple implemented for HBT transistors is the model of drift diffusion. This model is given in the form of differential equations in partial derivatives, describing the physical behavior of charges and currents in each part of the device.
The objective of our work consists in studying the electronic properties of a heterojunction bipolar transistor based AlxGa1-xAs /GaAs, and the distribution of electric potential, of the field electric thus the concentration of the electrons and the holes.