bluuebunny/crossref_metadata_2025_split huggingface dataset:
Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter
Authors: Dohle Rainer , Härter Stefan , Wirth Andreas , Goßler Jörg , Gorywoda Marek , Reinhardt Andreas , Franke Jörg 
Published: October 2015

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed.
For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2].
For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side.
A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.
Assessment of XRF Technique as a Method to Measure Percent Ag in SnAg Solders for Flip Chip Applications
Authors: Schuler Jennifer D , Shih Chia-Hsin , Arvin Charles L , Kim KyungMoon , Perfecto Eric 
Published: October 2015

Pb-free SnAg solder has become the industry standard for fabricating flip chip interconnects utilizing C4 (controlled collapse chip connection) technology. One area of interest for manufacturability of Pb-free solders is the ability to control and measure the %Ag composition and its variation from wafer to wafer, chip to chip, and C4 to C4.
There are various ways to measure solder composition. These are divided into two categories which are invasive and non-invasive referring to whether solder must be removed from the wafer in order to conduct the measurement.
There are a variety of invasive methods including Atomic Absorption (AA), Differential Scanning Calorimetry (DSC), Inductively Coupled Plasma (ICP) and Electron Probe Micro-Analyzer (EPMA) used with cross sections. Non-invasive methods are limited, making the development of the non-invasive X-Ray Fluorescence (XRF) method an important technique to determine both the thickness and composition of C4s on wafers without modifying the wafer.
There are many factors which can affect the accuracy of the XRF measurements. These include bump geometry, composition, UBM (under bump metallurgy) stack, bump spatial density, underlying chip wiring, tool vibration and tool parameters, such as collimator size, power levels, scan time, etc.
This paper will address the implementation issues in utilizing XRF for Pb-free solder SnAg systems. The paper will describe:(1) Experimental bumping variables,(2) XRF configuration, calibration, optimized measuring methodology and the importance of having known standards with the same dimensions of the bumps being measured(3) Measuring accuracy and correlation with ICP and DSC,(4) Ag distribution study in the die and wafer level
Thinner and Miniaturization Embedded Device Package, MCeP, for PoP and Module Application
Authors: Tanaka Kouichi , Kurashima Nobuyuki , Iizuka Hajime , Ooi Kiyoshi , Machida Yoshihiro , Shiraki Satoshi , Koyama Tetsuya 
Published: October 2015

Along with miniaturization and high functionality of electronics, many embedded device substrates and packages have been developed by various companies. We have been also developing embedded device package named MCeP, Molded Core embedded Package. This package consists of base substrate, upper substrate and molding resin. These substrates material is conventional organic base. Bare IC devices without re-routing are mounted on inner surface of base substrate. Upper substrate and base substrate are connected electrically by copper core solder balls. The space between upper and base substrate is encapsulated by molding resin.
MCeP is possible to be adopted for bottom package alternative of PoP. For thinner PoP application less than 1.0mm height, thinner MCeP less than 300um has been investigated. Base substrate has 3 conductive layers and thickness is 130um. Upper substrate has 2 conductive layers and thickness is 95um. Embedded layer thickness is 52.5um.
For original MCeP, IC device is mounted by flip chip bonding using Au bump and tin-silver solder interconnection. The space between IC device and base substrate is encapsulated by under-filling resin. It is necessary to keep under-filling resin flow area around IC device. Because of this resin flow area, package size should be enlarged. To miniaturize package size, solder bumped IC device and encapsulation by molding resin instead of under-filling resin were used, then resin flow area was eliminated.
MCeP is possible to use bottom package alternative for PoP and module application with IC device and passive components embedded.
Solder Joint Reliability Study for Wafer Level Packages on Flexible and Rigid Boards
Authors: Gu Gary , Chadwick Jon , Jin Daniel 
Published: October 2015

Applications of Wafer Level Packages (WLPs) have shown tremendous growth in the rapid developing smartphones and other portable electronic devices. The technology trends lead to smaller chip size, low cost, and more integrated functions, but also face higher reliability requirements due to the reduced number of solder bumps as well as smaller bump size and height. New assembly technologies such as flexible phone board and conformal coating also brought up new thermo-mechanical reliability challenges.
Based on 3D finite element modeling, the current studies focus on solder joint reliability of WLPs and compared between flex based and traditional rigid based WLP assemblies. Conformal coated and underfilled WLPs as well as some bump parameters are also studied. The parametric studies were carried out in ANSYS and all models were created by using APDL (ANSYS Parametric Design Language) scripts. Each simulation starts from stress free status set at solder reflow temperature and were subjected to thermal cyclic load between −40 and +125°C with ramp and dwell time. Creep strain was considered for solder alloys and kinematic plastic hardening was considered for other elastic-plastic materials. The solder fatigue life is estimated by using modified Coffin-Manson equation and was compared with available thermal cycling test data. The results show that underfill is still the most effective option and conformal coating can play an important role if the right material is selected. Bump parameters such as height, which have certain effects on the solder reliability on WLP-on-Rigid, have limited impact on WLP-on-Flex assembly.
Moisture Reliability Improvement of a High Performance Depletion Mode 0.15 um Gate PHEMT Process
Authors: Abrokwah Jon , Stanback John , Wang Jerry , Johnson Molly , Jiaa Chi L. 
Published: October 2015

Moisture reliability of a 0.15-um gate PHEMT technology for mm-wave applications was investigated. The PHEMT technology is fabricated with a deep UV optical lithography, and typically exhibits transconductance of ~550 mS/mm and fT of ~90 GHz.
Moisture reliability, THBL or BHAST performed at 85% relative humidity, and 95 °C, or 130 °C and 85% RH, respectively, initially showed failures up to 70%, under various process splits. Extensive failure analysis pointed to a number of mechanisms contributing to failure, the key culprit being moisture ingress, enabled by poor quality of SiN, stresses, seams, and voids in the passivation dielectric around the gate topology. Moisture penetrated the SiN to GaAs surface through seams in the dielectric around the gate or regions of high local stress such as gate feeds and ends. A corrosion process ensued with the applied voltage bias on the device drain and gate during the THBL or BHAST environmental stress, leading to GaAs oxidation, metal migration and shorts.
By designing the gate topology appropriately, failures were reduced to the range of 0–3.4 %. Further, using a BCB overcoat, failures were completely eliminated.
Thermal Cycle Consideration in Applying Lead-Free TFBGA Simulation to a Design
Authors: Tsai Yi-Chuan , Wu Mei-Ling 
Published: October 2015

Three-dimensional (3D) stacked die packaging has become the trend to improve efficiency for transmitting signals, reduce the volume of the package, and help with functions integration. It is more and more applied popularly in telecommunications. Solder joints, interconnections in the packaging structure, are more easily damaged by critical stress from thermal cycle loading when the component is operating, because the coefficient of the thermal expansion of various materials mismatch. People have studied the common single die during the thermal cycle loading for a long time, but the researches for the stacked die BGA are not as complete. In addition, to protect the environment and comply with legislation, the semiconductor industry wants to find a lead-free material to replace the lead solder joints. Therefore, most extant or new types of packaging started using lead-free material to do thermal cycle testing. The critical solder ball location is not the same as in a single die package where at the die corner, due to it is influenced by stacked die with different geometry, the difference in dice length helps to redistribute the die stress.
In this paper, we used FEA software, ANSYS, to build up a 3D thin-profile, fine-pitch, ball grid array (TFBGA) model. The modeling investigated the effect on solder joints under thermal cycle and included deformation, von-Mises stress and strain energy density (SED). Then we utilized Darveaux's approach, which is a common methodology used to calculate the fatigue life based on energy and damage accumulation theories, to predict the fatigue life of the critical solder joint and modify our model with the theory. We changed various kinds of SAC solder joints with different ratios of the components and Anand's constants, analyze the divergence and compared them with the lead solder material. We develop a model to forecast the failure phenomenon and fatigue damage on an electronic package. This would help engineers and designers raise the reliability of the package. In addition, we hope to find a lead-free material that can be substituted for the lead solder material. If this is the case, based on simulating results, we hope to improve it and have much a better reliability performance than the original lead solder.
Smart Power Module Molding Advances: Evaluating high temperature suitability of Molding Compounds
Authors: Becker K.-F. , Thomas T. , Bauer J. , Kahle R. , Braun T. , Aschenbrenner R. , Schneider-Ramelow M. , Lang K.-D. 
Published: October 2015

During the last years within power electronics packaging a trend towards compact power electronics modules for automotive and industrial applications could be observed, where a smart integrated control unit for motor drives is replacing bulky substrates with discrete control logic and power electronics. Most recent modules combine control and power electronics yielding maximum miniaturization. Transfer molding is the method of choice for cost effective encapsulation of such modules due to robustness of the molded modules and moderate cost of packaging. But there are challenges with this type of package:
Typically those packages are asymmetric, a substrate with single sided assembly is overmolded on the component side and the substrate backside is exposed providing a heat path for optimized cooling. This asymmetric geometry is prone to yield warped substrates, preventing optimum thermal contact to the heatsink and also putting thermo-mechanical stress on the encapsulated components, possibly reducing reliability.
Such packages being truly heterogeneous, combining powerICs, wire bonds, SMDs, controlICs, substrate and leadframe surfaces, the encapsulant used needs to adhere sufficiently to all surfaces present. Additionally those packages need to operate at elevated temperatures for long time, e.g. operate at 200 °C for 1000 h and more, so high thermal stability is of ample importance.
Within this paper the main goal is to identify transfer molding compounds suitable for the encapsulation of smart power modules, ready to be used at 200 °C and determine the actual maximum temperature of use of such high performance molding compounds currently available in the market. Summarized a detailed description of the high temperature suitability of high performance molding compounds is provided – additionally an extended test methodology is described to facilitate future material evaluation for HT or harsh environment use of polymeric materials as encapsulants or base materials.
A friction based approach for modeling wire bonding
Authors: Althoff Simon , Neuhaus Jan , Hemsel Tobias , Sextro Walter 
Published: October 2015

A model approach for wedge/wedge bonding copper wire is presented. The connection between wire and substrate is based on a variety of physical effects, but the dominant one is the friction based welding while applying ultrasound. Consequently, a friction model was used to investigate the welding process. This model is built up universal and can be used to describe the formation of micro welds in the time variant contact area between wire and substrate.
Aim of the model is to identify the interactions between touchdown, bond normal force, ultrasonic power and bonding time. To do so, the contact area is discretized into partial areas where a Point Contact Model is applied. Based on this approach it is possible to simulate micro and macro slip inside the contact area between wire and substrate. The work done by friction force is a main criterion to define occurring micro joints which influence the subsequent welding.
RF MEMS DPDT Switch Using Novel Simulated Seesaw Design
Authors: Al-Amin Mohammed , Yousef Sufian , Morris Barry 
Published: October 2015

This paper investigates an RF MEMS (Radio Frequency Micro Electro-Mechanical System) switch from DC to 5.8 GHz switching, for use in mobile communications systems and devices. The RF MEMS switch uses a novel seesaw design to create a Double-Pole Double-Throw (DPDT) Switch which increases the capabilities of the seesaw design structure. A low Switching supply voltage with high RF isolation was achieved during its development. After looking at other available seesaw designs, it was discovered that an improvement could be attained by adding additional contacts.
An improved concept over existing Single-Pole Single-Throw (SPST) seesaw switches was achieved by using a DPDT switch with a set of upper and lower contacts at each side of the seesaw. To conform to the Microscale, from 1 μm – 100 μm, a length of 41μm was chosen to provide an adequate size for fabrication.
Copper Bulk General (Cu) was chosen for the pivot material due to its good electrical conductivity and sufficient flexibility for elastic recovery.
A working simulation was achieved without compromising the ‘Air-Gap’ between the contacts, which retains high isolation when the switch is open-circuited. The electrostatic supply voltage has been significantly reduced to a value which is closer to that used in mobile devices.
Development of low temperature sintered nano silver pastes using MO technology and resin reinforcing technology
Authors: Sasaki Koji , Mizumura Noritsuka 
Published: October 2015

Traditional thick film technology is widely used in various electronics products. There are two type of paste based on thick film technology. Typically, over 400°C is required for high temperature sintering type which contains glass for adhesion function. It shows high electrical and thermal performance. On the other hand, 150–300°C range process is used for low temperature process type as silver epoxy. In last decade, nano silver technology shows amazing progress to address low temperature operation by low temperature sintering.
This paper will discuss the results on fundamental study of newly developed nano silver pastes with unique approach which uses MO (Metallo-organic) technology and resin reinforcing technology.
Nano silver pastes contain several types of dispersant as surface coating to prevent agglomeration of the particles. Various coating technique has been reported to optimize sintering performance and stability. MO technology provides low temperature sintering capability by minimizing the coating material. The nano silver pastes show high electrical and thermal performance. However, degradation of die shear strength has been found by thermal cycling test due to the fragility of porous sintered structure. To improve the mechanical property, resin reinforcing technology has been developed. By adding special resin to the pastes, the porous area is filled with the resin and the sintered structure is reinforced. Degradation of die shear strength was not found by thermal cycling test to 1000 cycles.
Nano silver pastes using MO technology and resin reinforcing technology will meet lots of requirement on various thick film applications.
A Switched-Line Phase Shifter Fabricated with Additive Manufacturing
Authors: O'Brien Jonathan M. , Rojas Eduardo , Weller Thomas M. 
Published: October 2015

Additive manufacturing, also known as 3D printing, has proven to be advantageous compared to conventional planar methods when utilizing the volume of a structure to miniaturize the design. The use of additive manufacturing can allow for high frequency circuitry to be conformed to an arbitrary shape while maintaining or enhancing performance. Recent advancements in low loss materials applicable to additive manufacturing have pushed performance levels even further.
Utilizing additive manufacturing to build a three dimensional structure can improve factors such as reliability and repeatability by making the structure one solid piece as opposed to assembling multiple planar objects into the 3D shape. This allows the circuitry to be built around the structure. With this design approach other considerations, such as stability and strength, can be concentrated on during the structure design to realize new shapes.
The purpose of this work is to investigate a 3D printed material, ULTEM, for radio frequency use and design a switched line phase shifter using the derived material properties. The first step in any high frequency circuit design is to have accurate material properties. An efficient way to determine the permittivity and loss tangent of a material is to place a ring resonator on the substrate and measure the resonant frequency and Q factor. An equivalent circuit model can then be built to match the measured response and the material properties extracted through circuit theory. From here accurate transmission line models can be analyzed to optimize the performance of the RF circuit.
In this paper a ring resonator was designed on ULTEM to characterize the material properties. A 90° phase shifter was then fabricated on a 3D printed ULTEM substrate and a benchmark model was fabricated using traditional planar methods on Rogers RO4003C substrate. A comparison between the two models is given in this paper.
DIMM-in-a-PACKAGE (DIAP) signal integrity for high-performance on-board memory applications
Authors: Sun Zhuowen , Chen Kevin , Crisp Richard 
Published: October 2015

The recent explosion of thin notebooks and tablets has challenged the IC packaging industry to come up with new solutions of DRAM integration onto motherboard. Beyond traditional SO-DIMMs, innovative memory solutions should perform well at high speed (1600 MT/s) with much reduced footprint and z-height, while leveraging current manufacturing infrastructure for lower cost and also enabling simpler and cheaper motherboard design.
To accomplish all the goals stated above for high-performance on-board memory applications, we showed a new DIMM-in-a-Package (DIAP) technology. This 22.5×17.5×1.2mm quad-die face-down (QFD) part has four standard center bond DDR3L dies (each ×16) face-down, which are wire-bonded to the bottom layer of the 407-ball BGA package. This judiciously designed package places data nets at the peripheral and command/control/address nets in the middle of the BGA. As such, motherboard design and layout were substantially simplified to allow the use of low-cost non-HDI Type 3 board for signal integrity performance comparable to expensive HDI boards. The QFD™ ball assignment could accommodate future memory density expansion and different memory type (e.g. LPDDR3, DDR4). It also enables dual-rank operations in each channel when double-sided assembly is used.
We successfully demonstrated in production build that 1GB ×64 DDR3L QFD with data rate of 1600 MT/s can be achieved on a Type 3 motherboard for the Intel Haswell mobile platform in dual-channel dual-rank operation. A balanced-T Command/Address topology between the processor and the memory was implemented in a DELL XPS 12 Ultrabook. Channel simulations including chip, package and board were performed. We also conducted cross-talk analysis up to 9 aggressors to take into account the timing impact from the dense routing inside QFD. Layout optimization techniques for best signal integrity, such as trace length matching and stub length minimization, were discussed in detail and applied to both package and motherboard design. Lastly, we also presented and discussed DIAPs currently under study with different memory bus topologies for even higher data rate up to 2400 MT/s using the same QFD technology.
Our results and analysis demonstrated DIAP using wirebond-based QFD technology as a viable candidate for the compact, low-cost, high-performance on-board memory solution. We have identified several key aspects of DIAP architecture design and physical layout that are strongly impacting the SI of QFD parts at rate &gt;1600 MT/s and that could be optimized for DDR4 operations. QFD DIAP can become an attractive low-cost, high-performance option for many OEMs and ODMs in various mobile, personal and network computing platforms.