bluuebunny/crossref_metadata_2025_split huggingface dataset:
High Throuput Fluidic PCBs for Medical Devices
Authors: Gassmann Stefan , Pagel Lienhard 
Published: October 2015

Printed circuit boards (PCBs) perform normally wiring, holding and cooling tasks in electronic systems. But with the request for integration of more and more functionality in the devices the PCBs have to take over more and more tasks in a system and will become a functional device and not only the carrier for electronic devices.
One of these functions can be fluidics. The usage of PCBs for micro fluidic devices such as pumps and sensors was already reported. In this talk a new research area of the fluidic PCB group at the University of Rostock is presented: The usage of a fluidic PCB technology for the realization of medical fluidic devices with high throughput. The problems to overcome are the creation of high pressure proof channels with a low flow resistance and of course the biocompatibility.
In the talk a medical device developed in such a technology will be described. It is a support device for the minimal invasive surgery which has to regulate the pressure in the pneumoperitonaeum, a so called insufflator. For this device flow rates of up to 45l/min CO2 has to deliver and the channel must withstand a pressure of up to 3.5 Bar.
The focus in the talk will be the technological challenge of building pressure proof channels in the PCB. The requirements for the usage in medical devices will be explicitly described and the measurement results will be demonstrated. As a conclusion a comparison to a device build in a conventional technology device is given. The criterias are the functional parameters and the production and maintainance costs.
Coaxial Through-Strata-Via (TSV) Analysis and Modeling
Authors: Xu Zheng , Lu James Jian-Qiang 
Published: October 2015

Through-strata-via (TSV) is well accepted as a critical component in 3D integration that would extend Moore's Law. Since its electromagnetic fields that carry the signal exist only between the inner conductor and outer shell, the coaxial TSV offers small coupling, reduced loss and high density to meet rigorous specifications. The published results also show that the signal integrity of coaxial TSVs is better than that of other TSV configurations, while lack of detailed analysis and modeling for TSV physical design guidelines. In comparison to other TSV configurations, there are some advantages in fabrication of tungsten-based coaxial TSVs, although the fabrication could be challenging and complex for copper-based coaxial TSVs. This paper examines the performance of various coaxial TSV physical designs using a 3D electromagnetic field solver and SPICE simulator. Based on the analysis in both frequency domain and time domain, we report a number of design notes (as listed below) to avoid undesired energy consumption and potential logic malfunction:* Compared with a signal-ground TSV pair, the proposed coaxial TSV reduces the signal loss by more than half (~53%).* The electrical performance of copper-based coaxial TSV is very close to that of tungsten-based one.* 3D bathtub curves suggest good timing characteristics of coaxial TSV at high data rates.* The impact of the thickness of the coaxial TSV outer ground shell is insignificant.* Keeping the outer ground shell radius (that determines the I/O density), an optimal value of the inner signal TSV conductor radius exists (i.e., neither big nor small is good).* A thick tubular dielectric medium (i.e., large spacing) between the inner and outer conductors favors the performance remarkably.* This tubular dielectric medium with a small dielectric constant and tangent loss can suppress the signal attenuation.* If the tubular dielectric material is silicon or poly-silicon, low doping is preferred.* The desired thickness of the isolation liner, which isolates the metals, depends on the material properties of the tubular dielectric medium.* By converting fullwave scattering (S) matrix to the corresponding impedance (Z), admittance (Y) and transmission (ABCD) matrices, frequency-dependent RLGC of the coaxial TSV are analytically extracted based on ‘T’, ‘Pi’ and ‘lossy transmission-line’ models, showing a good agreement.* A SPICE broadband modeling approach is applied to accurately fit the amplitude and phase of insertion loss S11 and return loss S21 from 100 MHz to 100 GHz in the proposed coaxial TSV.
This work can help designers optimize the coaxial TSV physical design, hence improving electrical performance and maximizing the benefits of 3D integration/packaging.
SiP(System in Package) Solutions with Wafer Level Packaging Technology
Authors: Kang In Soo , Kim Jong Heon (Jay) 
Published: October 2015

In mobile application, the WLP technology has been developing to make whole package size almost same as chip size. However, the I/O per chip unit area has increased so that it gets difficult to realize ideal pad pitch for better reliability. Recently, to achieve the thin and small size, high performance and low cost semiconductor package, Embedding Die and Fanout Technologies have been suggested and developed based on wafer level processing. In this work, as a solution of system in package, wafer level embedded package and fanout technology will be reviewed.
Firstly, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level based new processes like wafer level molding for underfilling and encapsulation by molding compound without any special substrate have been applied and developed, including high aspect ratio Cu bumping, mold thinning and chip-to-wafer flipchip bonding. Secondly, Fan-out Package is considered as alternative package structure which means merged package structure of WLCSP (wafer level chip size package) and PCB process. We can make IC packaging widen area for SIP(System in Package) or 3D package.
In addition, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.
300mm Scaling of Critical Silicon Etches for Image Sensor Wafer-Level Packaging Based on Tessera's MVP (TSV) Technology
Authors: Thomas Dave , Muggeridge Matthew , Steel Mike , Sanz Dorleta Cortaberria , Griffiths Hefin , Ansell Oliver , Kriman Moshe , Grinman Andrey , Gershtenman-Avsian Hagit 
Published: October 2015

Miniature, high performance camera modules are found in a range of consumer devices including phones, PDAs, cameras and gaming consoles. According to Gartner the $1B image sensor market will grow to $2.3B by 2013. Image sensor packaging technologies are increasingly required to deliver greater reliability within smaller form factors.
Tessera's OptiML™ Micro Via Pad (MVP) wafer-level packaging technology is in production on 200mm wafers. This paper will report on the first joint activity that scales this technology to 300mm. We focus on three critical silicon etches that form the back-bone of the structure. These etches are carried out from the wafer back-side while bonded to a glass carrier.
First there is a blanket dry etch. This removes stress introduced by the back-grind. Uniformity control to &lt; ±5% is essential for this process. Second, after a lithography step, tapered silicon trenches are etched forming streets to a certain depth. The trench etch uniformity is critical because it defines the depth range for the subsequent Vias. Profile control is needed to ease the subsequent spray-coat lithography. Lastly, vias are then etched down to metal bond pads on the device side of the wafer. CD and taper control is required here both within wafer and between wafers. End-pointing represents a way of ensuring process reproducibility.
In 2010 Tessera carried out 300mm demos with key suppliers. As part of this activity SPTS scaled the above critical silicon etches. The wafers were further processed into functional die.
We will describe the etch equipment used, report on the critical processes developed emphasizing the relationships between 200mm and 300mm results and the essential control parameters. We will also demonstrate successful scaling by including data on the electrical performance of packaged devices.
Copper Migration in Flip-Chip Substrates Under Biased-HAST Conditions
Authors: Stahley Matthew E. , Osenbach John W. 
Published: October 2015

Biased-humidity testing is a critical reliability qualification requirement for integrated circuit packages. The benchmark of THB (Temperature Humidity Bias) at 85C/85%RH/bias for 1000 hours is a long duration test, so biased-HAST (biased Highly Accelerated Stress Test) conditions are adopted. Accelerated biased-HAST durations are based on aluminum corrosion failure mechanisms and may not be applicable to other materials such as in flip-chip packages. One such failure mechanism is discussed here.
Flip-chip packages with build-up substrates were exposed to biased-humidity at 85C, 110C, or 130C and 85%RH. After 96 hours of 130C/85%RH/bias, failures occurred with signatures ranging from bake-recoverable leakage to shorts. Physical failure analysis revealed copper migration in the substrate build-up dielectric rather than classical CAF (Conductive Anodic Filament) within the substrate core. No copper migration occurred with conditions of 110C/85%RH/bias, 85C/85%RH/bias, or 130C/85%RH/no-bias. Given that the JEDEC biased humidity durations are 96 hours at 130C/85%RH, 264 hours at 110C/85%RH, or 1000 hours at 85C/85%RH, it is concluded that the JEDEC acceleration function is not applicable for this failure mechanism.
A failure model is proposed based on humidity induced reduction of the glass transition temperature (Tg) of the build-up dielectric. Bond strength decreases and free volume increases above Tg, and the combination results in the formation of localized channels in the build-up dielectric where electrochemical migration of copper occurs under bias and humidity. Copper migration does not occur for conditions of humidity/bias below Tg, humidity/no-bias above Tg, and no humidity/bias near Tg. This indicates there is likely a threshold in humidity and/or temperature, below which copper migration does not occur. These results further demonstrate that caution must be used when employing accelerated reliability tests, as they may introduce failure mechanisms that would not occur in the field.
Cost Comparison of Fan-Out WLP vs. Embedded Die
Authors: Palesko Alan , Vardaman Jan 
Published: October 2015

Fabricating the package after the die is placed can result in smaller form factors, increased performance, and improved supply chain logistics for OEMs. There are many different approaches for this packaging technique, but two of the most prominent are Fan-Out WLP and Embedded Die. Fan-Out WLP leverages existing semiconductor technology for a cost effective approach to achieve relatively tight package design rules. The Embedded Die strategy leverages existing PCB lamination technology for cost-reduction through scale: fabricating many small packages on large production panels.
We will examine the cost differences and similarities between Fan-Out WLP and Embedded Die strategies by developing a comprehensive cost model for each technology. We will then analyze the manufacturing costs (labor, material, depreciation, yield loss, and tooling) and yield impacts across a variety of designs to demonstrate the cost differences and similarities in each packaging technology.
A New Robust One-Shot Switch for High-Power Pulse Applications
Authors: Baginski Thomas A. , Dean Robert N. , Surgnier Steven P. 
Published: October 2015

High Voltage (HV) switches capable of operating at high speeds and over a wide range of voltages and energies are used in a variety of pulse power applications in material science and plasma physics. Of particular interest is the use of small-scale capacitor discharges to measure the electrical properties of materials as they are heated from solid through liquid to a gas phase. In a capacitive discharge unit (CDU), energy stored in a capacitor is coupled through a switch into a low-impedance transmission line, which typically terminates with a thin sample of material. The energy coupled to the sample is sufficient to cause vaporization. Voltages in such systems range from a few volts to thousands of volts. These vaporized materials are used either as plasma sources for physics experiments, or to propel a thin layer of electrically insulating polymer for high-pressure-impact studies.
Several types of switches have been used to drive these systems, including triggered spark gap, dielectric breakdown, and mercury vapor switches. A wide variety of solid-state devices, such as the insulated gate bipolar transistors, are also being utilized for these applications. Inducing a high-pressure shock wave in a dielectric to produce a transition from dielectric to conductor has also been used as an efficient single-shot switch for capacitor discharges.
The high-voltage micro-machined switch presented in this document has been designed as a single-use alternative to the more expensive triggered spark gaps and solid-stage devices. The plasma-bridge switch is intended for large-volume, relatively inexpensive systems, and a cost-effective switch for use in destructive testing.
MEMS Tornado to Challenge Next Generation Packaging
Authors: Bryzek Janusz 
Published: October 2015

In the last decade multiple MEMS devices entered Tornado (avalanche sales growth), adopting along the way the IC packaging technologies with a “twist”. Consumer applications for MEMS devices exploded, with sensor shipments increasing from 10M units in 2007 to over 2B units in 2011. This explosion resulted from Steve Jobs vision converting a cell phone into a powerful computer. Computing power enabled creative user interfaces, such as touch sensitive screens and auto landscape-portrait rotation, opening a Tornado for MEMS. As more complex MEMS devices are finding its way to cell phones, they will be creating packaging challenges.
An emergence of even a bigger forthcoming Tornado is surfacing.History shows that all major technologies coming to market enabled advancement of world-changing productivity and balance of power. At a recent conference, a VP of Maxim Integrated Products stated that we have entered the 3rd technical revolution which will free humans for creative work through a fusion of computing, communication and sensing. This will enable MEMS component market to catch up with the semiconductor market ($300B).At the 2010 MEMS Technology Summit conference at Stanford University, Bosch presented a vision for 7 trillion devices driven by Sensory Swarms connected to the Internet to serve 7 billion people in 2017 (in 2010 there were already 5 billion mobile phone subscribers). This vision translates to 1,000 sensors per average person in 2017. We are already seeing high end applications supported by large number of MEMS sensors in advanced cars, smart homes, smart phones and medical diagnostics, to mention a few.In 2010 HP outlined a vision for CeNSE, a Central Nervous System for the Earth, which expected to deploy a trillion nano sensors and actuators. Processing the sensor information will require increasing the size of Internet 1,000 times; creating huge demand for computing and generating by 2013 a $70B global market for sensing systems, and $290B market for value added sensing services.
As device volumes start approaching a trillion units a year, packaging challenges will be created by:Complexity of emerging MEMS devices. The required “twists” to IC packaging will be in the areas such as low package stress, chemical and fluidic media compatibility, optical performance, etc.Cost pressure.
Due to a sheer size of expected market, packaging industry may expect very large changes.
Addressing these challenges will likely have a big impact on the packaging industry.
Assembly Challenges for Large Interposer 2.5D TSV Products
Authors: Mattei Marnie , Kelly Mike 
Published: October 2015

Interposers provide a crucial intermediate step for next generation products to allow side-by-side integration of technology optimized devices ahead of a full 3D assembly. The interposer size in most cases is greater than 22mm on a side and in some designs exceeds 30mm. This large size combined with a thickness of ≤ 100 microns may result in high warpage which can significantly impact the assembly process. Materials and process selection become a key consideration to create a high yielding, multi-die stacked product.
This presentation will outline the challenges of a large 2.5D TSV product and how assembly strategies can be used to accommodate these challenges. Different process options and die attach sequences for interposer to substrate and chips to interposer will be discussed. The assembly methods for attaching multiple die with tens of thousands of I/O at 40 micron fine pitch will be compared in relation to the die size and interposer warpage. Product design requirements may also dictate that the optimum assembly approach is achieved by combining methods such as mass reflow and TCNCP bonding for die attach and underfill. Test considerations at intermediate assembly steps will also be reviewed for feasibility in the overall process flow.
The Reactive Bridge: A Novel Solid-State Low Energy Initiator
Authors: Baginski Thomas A. , Dean Robert N. 
Published: October 2015

Within a broad variety of commercial (i.e. automotive airbags, mining) and government ordnance systems there exists an interface which utilizes electrical energy to initiate an exothermic reaction (i.e. combustion, deflagration, detonation). The structure that performs this function is commonly referred to as an Electro-explosive device (EED). The basic EED design is susceptible to initiation failures due to mechanical hazards such vibration and shock.
This paper discusses the fabrication and characterization of a micro-machined EED (the Reactive Bridge) which is mechanically robust, extremely reliable and inexpensive to manufacture. The structure is capable of directly initiating a wide variety of pyrotechnics and primary explosives. The Reactive Bridge offers the additional advantage of being able to be directly fabricated onto any custom integrated circuit. This feature may be of particular interest for adding anti-tamper features directly at the individual die level of electronic systems.
The structure consists of patterned sequential layers of titanium and boron which react exothermically when properly initiated. Design parameters will be discussed and compared to firing data for Reactive Bridge EEDs loaded with fine grain zirconium potassium perchlorate (ZPP). A number of different sized bridges were investigated. Scanning electron microscope photographs of cross-sectioned devices before and after firing will also be discussed.
3D Packaging Solution Providing DDR & LPDDR Co-Support for Ultrabooks and Next Generation Servers
Authors: McElrea Simon , Solberg Vern 
Published: October 2015

Effective 3D stacking of DRAM devices can offer many benefits; improved performance, increased component density and greater surface area utilization. To enable the new generations of processors to reach their performance potential many manufacturers have developed more efficient interface formats that enable greater memory bandwidth. This revolution in performance driven electronic systems continues to challenge the IC packaging industry. The challenge is clear. To ensure that the memory functions are able to support the increased signal speed, product developers will need to explore more innovative 3D package assembly techniques and process refinement methodologies. The methodology selected for package assembly, however, must consider process complexity, the costs associated with each process, overall package assembly yield and, from the users perspective, end product reliability.
For some applications companies have had limited success in stacking die elements directly onto an interposer substrate using wire-bond processes. High performance DRAM die, however, is especially difficult to stack. This is due to the center positioned wire-bond sites. This factor has complicated the DRAM die stacking process and because of the excessively long wire-bond interface, functional signal speed is significantly degraded. Stacking individually packaged DRAM (package-on-package) has had considerable success but the package outline dimension and package height can be excessive. In this paper the authors will introduce a very innovative and very thin 3D package developed specifically for center-bond pad DRAM die. The package assembly methodology promises to remain economical because it requires no special die level process steps and it can utilize the existing package assembly infrastructure. Additionally, data compiled during extensive performance and reliability modeling will be presented along with the results from actual physical qualification testing.
3D Glass and Silicon Interposers with TPV vs. 3D ICs with TSV
Authors: Tummala Rao 
Published: October 2015

3D Packaging has been emerging as the dominant theme for more than a decade. It started as package on package stacking in the 1970s for memory devices. More recently, it moved to stacked, wire bonded chips as well as miniaturized package-on-package (POP). Stacking with flip chip soon followed. In all these cases, ICs are fabricated in wafer fabs and packaging of these ICs was subsequently performed independently. The next natural evolution to be expected is to eliminate external interconnections outside the ICs by means of through vias, now called TSVs. But this became revolutionary, complex and costly. It impacted wafer fabrication by virtue of having to co-process transistors, BEOL wiring and TSV interconnections, all in the wafer fab. This is referred to as 3D ICs with TSV.
The benefits of 3D ICs are overwhelming. They include highest performance in smallest size by virtue of stacking many ultra-thin ICs and interconnecting them with through-silicon-vias. But such a technology is also complex and costly to manufacture. It presents many other problems that include thermal management, testability, and extendibility.
Georgia Tech PRC proposes to demonstrate lower cost and simpler 3D Interposers with TPVs to address most of the above challenges. In this scenario, through-package-vias (TPV) are fabricated in the ultra-thin and low-cost silicon or glass interposers at the same I/O density or pitch as in TSVs in the logic ICs but without the need for TSVs in the logic ICs. Such a concept is 3-dimensional; allowing stacking of ICs on both sides of the interposer with the same I/O pitch as TSVs and yet minimizes the thermal, testability and extendibility problems.
This paper presents the status, progress and remaining challenges of 3D Interposer concept at Georgia Tech involving more than 25 companies in a global consortium.