bluuebunny/crossref_metadata_2025_split huggingface dataset:
NanoBond® Assembly – A Rapid, Room Temperature Soldering Process
Authors: Matteau Jacques 
Published: October 2015

Indium Corporation of America has commercialized a new technology that will revolutionize how manufacturers join components using solder materials. (See Figure 1) The joining process is based on the use of reactive multilayer foils as local heat sources. The foils are a new class of nano-engineered materials, in which self-propagating exothermic reactions can be ignited at room temperature through an ignition process. By inserting a multilayer foil between two solder layers and two components, heat generated by the reaction in the foil melts the solder and consequently bonds are completed at room temperature in air, argon or vacuum in approximately one second. The resulting metallic joints exhibit thermal conductivities two orders of magnitude higher, and thermal resistivity’s an order of magnitude lower, than current commercial TIMs.
The use of reactive foils as a local heat source eliminates the need for torches, furnaces, or lasers, speeds the soldering processes, and dramatically reduces the total heat that is needed. Thus, temperature-sensitive or small components can be joined without thermal damage or excessive heating. In addition, mismatches in thermal contraction on cooling can be avoided because components see very small increases in temperature. This is particularly beneficial for joining metals to ceramics. The fabrication and characterization of the reactive foils is described, and the value proposition for NanoBonding is presented. This presentation also shows the applicability of this platform technology to many areas of packaging including Thermal Interface Materials, microelectronics, optoelectronics, and Light Emitting Diodes (LEDs)
The Mechanism of The Die Crack in exposed Pad Quad Flat Package(ePad QFP) with Large Die due to Die-attach Adhesive with high modulus
Authors: Kim Jin-Ho , Kim Dong-Nam , Jo Young-Chul , Kim Nam-Yong , Kang Seung-Geun , Lee Byung-Ju , Kim Dal-Soo , Yun Tea-Seob , Kim Sung-Jun 
Published: October 2015

Thermal-enhanced plastic packages, such as exposed Pad Quad Flat Package (ePAD QFP), are more sensitive to thermal stress and warpage. As a result, thermal stress and warpage in ePAD QFP can lead to severe die cracking. This stress and warpage are mainly due to the thermal mismatch of packaging materials with different coefficient of thermal expansion (CTE). In particular, the die attach adhesive plays an important role in controlling stress and warpage in the package.
In this paper, both experimental data and simulation were employed to gain a better understanding in a stress development and failure mechanism in ePAD QFP with a large die. Theoretical die-attach adhesives with different modulus were used for the evaluation of die crack and delamination by analysis of finite-numerical element method (FNEM). And the effect of the adhesion between Si die and Die-attach adhesive on the die crack was also discussed in this paper by FNEM. The simulation for thermal stress due to CTE mismatch was done by shadow moiré measurement technique and dynamic profiling method to verify the stress concentration area around the die in the package. And the delamination and die crack were simulated by thermal cycling test after changing appropriate adhesive materials that can directly affect on the die crack and the stress. The mechanism of die crack and the crack propagation through the die were mainly discussed in details at first and then the stress concentration and die crack initiation was verified by FNEM analysis and physical experimental validation. Finally, the major property of the die-attach adhesive to be considered for better reliability performance in ePAD QFP was suggested with die size.
Properties and Reliability of Silicon Nitride Substrates with AMB Copper Conductor
Authors: Gaby Böhm , Dieter Brunner , Ina Sichert , Andreas Pönicke , Jochen Schilm 
Published: October 2015

This paper focuses on the properties of Si3N4 substrate material with AMB (active metal brazing) copper conductor.
A recently developed type of tape casted, gas pressure sintered silicon nitride ceramic with a three times higher thermal conductivity than known from typical standard silicon nitride materials and with good flexural strength was applied. The increase of thermal conductivity is the result of using different species of sintering aids and the optimization of their ratio in the material. The high bending strength allows creating a thinner substrate compared to other standard ceramic materials for power electronics, e.g. aluminum nitride. This reduction in thickness leads to a decrease of the total thermal resistance of the substrate which improves heat dissipation. For the AMB process a silver based active brazing solder composition optimized for Silicon Nitride was used. This optimization could be obtained by an investigation of the physical and chemical interactions between the brazing and the base material. A void free joint without short circuits between adjacent structures could be formed. The copper surface can be coated on demand with Nickel or Nickel/Gold for improved solderability and wire bondability as well as for corrosion protection.
The silicon nitride substrate with AMB copper conductor lines and fully covered back side ground shows a higher reliability than comparable substrates made out of common, well known ceramic materials. The heat dissipation is comparable with conventional AMB substrates made of high thermal conductive ceramic such as Aluminum Nitride, but thermal cycling behavior exceeds the limits well known from AlN-AMB or AlN-DCB.
Finding “The Buffy” Talent Acquisition and Retention in Today’s Market
Authors: Troy Patrick J. G. 
Published: October 2015

Human Capital is a company’s most valuable asset and market success is directly linked to employee performance. Adopting best practices for recruiting, hiring, and retaining top performers is critical to successful talent acquisition and sustaining bench strength.
A recent survey found that a bad hire can cost an organization anywhere from one to five times the employee’s annual salary. Twenty-six percent of survey respondents reported that replacing an employee who doesn’t work out cost their organizations three times annual salary, and another 42 percent said bad hires cost two times annual salary. Hiring managers who do not utilize best practices will statistically experience fifty percent of their hires as underperforming employees.
An “Ideal Fit” is a comprehensive high order match of a candidate’s skills, talents, attributes, and abilities equally balanced with style, culture, values, and environment. Objectively grading each aspect of “Fit” is critical to evaluating potential. Utilizing process based on proven best practices gives employers a statistically higher probability of making good hires; building the company’s talent roster and brand; and producing a positive contribution to the company’s “bottom Line” by on-boarding successful contributors.
The focus of this paper is to present best practices, show how to implement these practices with real world examples, and expose practices that produce marginal or poor results
Predicting the Reliability of Zero-Level TSVs
Authors: Caswell Greg , Hillman Craig 
Published: October 2015

Through Silicon Vias (TSV) are the next generation technology for system in package devices and are similar to plated through holes in a PCB from a reliability behavior perspective. The promised advantages include thinner packages and a greater level of integration between active die. The process is still being optimized and costs must be reduced for widespread adoption.
TSV is rarely justified by just miniaturization alone as it is more cost-effective to thin, stack and wire bond. Cost can be 2X–4X price of flip chip ($200/wafer is the goal) and 5X–10X the price of wire bonding. TSV will be justified by performance; specifically an increase in inter-die I/O, increase in bandwidth, and a corresponding decrease in interconnect length as shown in Figure 1.
This paper will present two different approaches to the generation of TSVs as the vias can be created at various stages of the process: By the wafer provider, IC manufacturer, or packaging house.
The paper will also address the techniques for creating the TSVs e.g. etching and lasering with respect to their differences and results as well as provide insight into the various approaches for filling the vias. A comparison between solid fill, polymer fill and no fill concepts will be made.
Finally, the paper will address the three primary failure mechanisms for TSVs, that of, cracking of the copper plating, cracking of the silicon /change in resistance of silicon and interfacial delamination of the via wall from the silicon. The paper will conclude with a focus on the challenges for this technology as the exact process and architecture (materials, design) for TSV has yet to be finalized which in turn can lead to large changes in stress states.
Optimizing Product Cost with Supply Chain Cost Modeling
Authors: Palesko Chet , Palesko Alan 
Published: October 2015

Demands on the electronics industry for smaller, better, and cheaper packages have made the supply chain more complex. Outsourcing, new technologies, and increasing performance requirements make designing and building the right product for the right price more difficult than ever. We will present a framework for understanding and managing the supply chain through cost modeling. Cost models that accurately reflect the cost impact from technology and design decisions enable a more precise understanding of supply chain behavior. Cost models can show the extra cost of adding a layer, the expected savings from relaxing design rules, or the cost of package on package assembly compared to 3D packaging with through silicon vias (TSVs).
The models also provide context to understanding the ″should cost″ of a product and the path to achieving it. Since the guidance from cost models is based on the actual supplier cost drivers and pricing behavior, designer cost reduction efforts will result in higher savings compared to not using the cost models. Without cost models, designers risk missing their suppliers' real cost drivers and, therefore, the opportunity to decrease cost. This cost modeling framework allows the designers to realize the lowest cost product by matching the right design with the right supplier. It is a method for understanding a design decision's cost impact: a design change, a supplier change, or even the impact of new technology.
NiV Stress Control Utilizing PVD with an Ar / N2 Gas Mixture
Authors: Seryogin G. , Golovato S. , Smith S. , Williams K. , Limburn N. , Winn A. , Mundada G. , Adema G. 
Published: October 2015

Physical Vapor Deposition (PVD) is a commonly used technique for back side metallization (BSM) and under bump metallization (UBM). Cutting edge BSM and UBM stacks require good adhesion, low contact resistance and low intrinsic stress. Nickel Vanadium (NiV) is commonly used as a barrier layer in these BSM and UBM stacks. As a non-magnetic material, NiV is more suitable for magnetron sputtering than pure Ni, which is magnetic. NiV tends to be sputtered in a high stress state and high stress in thin films has often degraded adhesion, resulting in long term reliability issues, and bowing of thinned wafers.
NiV films deposited by PVD using argon (Ar) process gas are usually under high tensile stress. In these cases, film stress can be controlled by various means during the PVD process: deposition temperature, deposition pressure, and RF bias applied to the wafers during deposition. This paper explores how changing the process gas from pure Ar to a mixture of argon and nitrogen gasses can control film stress. Stress neutral NiV(N) films were achieved by adding up to 50% of nitrogen to the Ar/N2 mixture. Stress, deposition rate, and sheet resistance were studied as a function of nitrogen percentage in the process gas mixture. Electrical and barrier properties of the resulting NiV(N) films were found to be comparable to or better than NiV films deposited with a pure Ar gas.
Thin PoP: Warpage Control for Thinner PoP Package in Mobile Applications
Authors: Tamadate Yuka , Sato Seiji , Imai Hitomi , Takeda Kota , Meguro Takeshi , Ozawa Takashi 
Published: October 2015

In order to significantly improve warpage of a PoP bottom package, Shinko developed an enhanced PoP structure. The inclusion of a support material attached to the backside of the flip chip die and over molded resin is the structure's key attribute. By adjusting the balance of each material (mold resin, substrate and support material thickness), we can better control warpage at both room temperature and reflow temperature. This enhanced thin PoP structure can be easily incorporated into a standard assembly process with existing equipment sets.
This paper describes simulation results, along with measured warpage characteristics of the new package.
A Low Firing Temperature Copper Conductor for use on an Aluminum Metal Compatible Dielectric in LED Thermal Substrate Applications
Authors: Shahbazi Samson , Grabey Steve , Persons Ryan 
Published: October 2015

One of the most important contributing factors in the long life of LEDs (Light Emitting Diode) is keeping them cool, i.e., lowering the junction temperature, which can get as high as 150 °C. One way to accomplish this when building a circuit containing many LED packages is to use a thermal substrate. The majority of High Power/High Brightness (HP/HB) LED thermal circuits manufactured today are based on Metal Core Printed Circuit Board (MCPCB) technology. The MCPCB system consists of a copper foil, polymer dielectric layer and either an aluminum or copper base layer that are laminated together. The process of making MCPCB is a subtractive process, where most of the copper foil is removed. The copper foil is etched to create a circuit layer, the polymer dielectric provides the insulation between the copper foil and the metal base, and the aluminum or copper base provides thermal dissipation.
The thick film copper paste discussed in this document is processed using an additive process, like screening printing, where the copper conductor is deposited only in the chosen area. The copper thick film paste is screen printed to create a circuit design on top of a thick film dielectric (insulated area) layer which is also printed on a metal base layer. The selective deposition allows for less material usage, and potentially lower overall cost as well as improved thermal performance with inclusion of thermal vias.
This paper discusses the results of a newly developed lead (Pb) and cadmium (Cd) free low firing temperature (580–600°C) copper thick film conductor paste on top of a low temperature firing dielectric paste. This study includes evaluations based on SEM photos, solderability, leach resistance, and initial and long term adhesions using SAC 305 solder and RMA flux. There are many different applications for HP/HB LED circuits, from general lighting to street lighting to automotive lighting and more. All of them have varying degrees of performance testing requirement. To try to cover as much of the reliability testing as possible we have included tests such as thermal aging (150°C), thermal cycling from −50 to+150°C, as well as 85°C/85% RH reliability testing under bias.
Comparison between Single & Multi Beam Laser Grooving of Low-K layers
Authors: van Borkulo Jeroen , Hendriks Rene , Dijkstra Peter 
Published: October 2015

The traditional blade dicing technology has gone through an impressive evolution keeping up with quality, cost and miniaturization requirements that the semiconductor technology roadmaps introduced and specified. However, since wafer technologies have dropped below 90nm node and low k materials were introduced it became clear that blade dicing evolution came to an end and expensive hybrid solutions such as combined laser grooving processes and blade dicing technologies were required to achieve the desired product reliability.
Similar situations have been seen with the ongoing trend to thinner wafer that are needed for miniaturization, 3D packaging and IC performance improvements. To achieve sufficient mechanical strength, complex dicing technologies and sequences have been introduced which do not respond to the requirements for current and near future technologies.
This paper will discuss the low-k grooving process by laser pulses for IC wafers. The low-K laser grooving technology allows semiconductor manufacturers to execute the technology roadmap and continue to comply with Moore's law in an efficient manner. In specific this paper will elaborate on the comparison study made between the single beam and multi beam low-K grooving process. Together with a large IDM customer a comparison has been done to determine the results on quality, Heat Affected Zone (HAZ), productivity and yield.
Small Pitch Micro-Bumping and Experimental Investigation for Under Filling 3D Stacking
Authors: La Manna Antonio , Rebibis K. J. , De Vos J. , Bogaerts L. , Gerets C. , Beyne E. 
Published: October 2015

Although 3D-IC integration is largely acknowledged as most promising technology to push further the scaling concept of Moore's law, a few important uncertainties are delaying high volume production. Among these uncertainties, the reliability of 3D-IC stacked components is the most important. A key element in 3D stacking reliability is the choice of the correct UF to integrate in the assembly processing: die stacking and final packaging. In this paper we report the recent results coming from the UF screening and 3D stacking activities. These activities are performed at Imec in the frame of the 3D Imec Industrial Affiliation Program (3D-IIAP).
After describing the test vehicle used in this work, we introduce some of the requirements in term of process improvement and stacking accuracy to enable 3D stacking in case of small pitch micro-bumps. We then present recent results coming from the UF screening activity and report on the electrical characterization of the 3D stacks. This characterization is done by measuring the electrical resistance of the daisy chains connections between top/bottom dies bumps. The stacks are done with thermo-compression bonding and using die-to-die approach. The stacks are lately exposed to thermo-cycling processing followed by further characterization.
Use of 3D Packaging Technology for Satellite Active Antennas Front-ends
Authors: Bonnet B. , Chiniard R. , Legay H. , Nevo D. , Monfraix P. , Vendier O. , Couderc P. , Cazaux J.-L. 
Published: October 2015

Multi-Chip Module Vertical (MCM-V) technology, also called 3D packaging technology, enables the realization of a compact and low loss integrated feed for active antennas in Ka band. The active devices can be located in the vicinity of the radiating element, which reduces dramatically the volume and complexity of the antenna front-end for future architectures with more than a hundred beams in Ka band.
This paper deals with the optimization of 3D packaging technology to reach the requirements of 30GHz microwave modules for space applications. The technological developments that have been led on the design and the assembly processes are detailed. The measurement results of an integrated feed module in radiation are given and the circuit designed to optimize the signal-to-noise ratio of the front-end for receiving antennas is characterized. The performance is as good as for an optimized planar front-end with a waveguide access for a much more compact module, especially in terms of footprint in an antenna array. These results successfully position 3D packaging as a disruptive technology for future space and telecom subsystems.
A Ceramic Tubular Probe For Online Substance Concentration Measurement, Manufactured By Ceramic Injection Molding
Authors: Hartmann Matthias , Schmidt Bertram 
Published: October 2015

The current research presents recent respective to the work development of a ceramic tubular probe for online substance concentration measurements. The aim was to develop a robust and acid-resistant sensor device, which can be easily included in existing procedural pipeline systems. To archive those goals a lot of factors had to be checked. For the substance concentration measurements a capacitive sensor effect was chosen. With this method even low substance concentrations down to one-tenth of a per cent can be indentified.
For the package material zirconium oxide (tetragonal zirconia polycrystal – TZP) was used. Zirconium oxide is a technical ceramic which is wear-resistant, acid-resistant, has a low thermal conductivity, is electrically isolating and can be uses in a ceramic injection molding (CIM) process. In the phase of the sensor design process multiple geometries for the sensor effect and integration space for the evaluation electronics had to be considered. A standardized DN 10 DIN 32676 flanged joint was also added for an unproblematic connection to the pipelines. All these needed geometries had to be integrated into one ceramic element. As a result of these requirements a 3D CAD model of the sensor element was designed. The CAD-file has shown that there was only the CIM technology left to comprehend developed sensor geometry. CIM is a low cost process for large-scale production which is distinguished by high size accuracy. In the CIM process the material shrinkage, this is caused by the needed debindering and sintering steps, had to be considered.
The developed ceramic tubular probe was successfully tested in multiple fluidic systems. It has left the test phase and is now ready for maturity phase.
Copper Wire Bonding: R&D to High Volume Manufacturing
Authors: Chylak Bob , Clauberg Horst , Foley John , Qin Ivy 
Published: October 2015

During the past two years copper wire bonding has entered high volume manufacturing at a number of leading edge OSATs and IDMs. Usage of copper wire has achieved 20% market share and is expected to exceed 50% within three years. Products spanning the range from low pin count devices with relatively large wire diameter to FPGA's with nearly one thousand wires at 20 μm or even 18 μm wire are now using copper wire.
This paper will discuss the requirements for developing a robust copper wire bonding process and then moving it to high volume manufacturing. Process optimization begins with the selection of the appropriate wire diameter, ball diameter, bonding tool and bonding process type. These are functions not only of the bond pad opening, but also of the pad aluminum thickness and relative sensitivity of the pad to damage. Proper optimization depends on the availability of new and modified bond quality metrologies, such as extensive reliance on cross-sectioning and intermetallic coverage measurements. The bonding window of a copper wire bonding process is defined in substantially new terms compared to optimization in gold wire bonding.
Once an optimized process has been developed in the lab on a single bonder, it needs to be verified. Copper wire bond processes are much less forgiving with respect to the acceptable variability on the manufacturing floor. To ensure that the process is stable, a low volume pre-manufacturing test is highly recommended. This not only makes sure that the process is stable across multiple bonders, but also ensures the adequacies of manufacturing controls, incoming materials quality and sufficient equipment calibration and maintenance procedures.