Investigation of Cu Corrosion Defects Induced by Humidity Imbalance in the Cu Damascene Process of Semiconductors
Authors: Lee Koeun , Kim Taesung 
Published: August 2024

As integrated circuit design rules shrink in semiconductor, Copper (Cu) has been employed as the back end of line (BEOL) interconnect metal to enhance device performance through reduced resistivity and resistive-capacitive delay.[1] However, Cu metal lines are prone to degradation caused by Cu oxidation-induced defects, including extrusions and voids, owing to their inherent properties.[2] Consequently, it becomes essential to regulate the oxidation rate during the chip fabrication process, particularly when the Cu metal line is exposed during the Damascene process. This control is crucial for ensuring long-term reliability and achieving a higher yield.[3]
From the learning of earlier technological nodes, we are aware to and already precisely controlling both process queue time and wafer surface humidity. We must exercise control over the queue time, addressing both inter-process intervals and in-process queuing. [4] This underscores the importance of managing queue time and maintaining low environmental humidity to mitigate wafer surface defects when the FOUP (Front Opening Unified Pod) is opened at the EFEM (Equipment Front End Module).[5] Those humidity and queue times related Cu corrosion defects have been mitigated by N2 purge in FOUP and reducing the wafer quantity. However, dividing the lot, typically consisting of 25 wafers, by half or less to reduce queue times leads to an imbalance in low humidity due to N2 purging. This occurs when the FOUP is opened in EFEM.
This paper examines Cu corrosion under low humidity conditions in a FOUP with a small quantity of wafers, specifically examining the influence of queue time during N2 purging in the EFEM. Through simulation of the interaction between the inlet air entering the EFEM and the purged N2 gas, a vulnerable area is identified where copper oxidation takes place. In addition, we propose an arrangement to mitigate high humidity, supported by experiments conducted under real equipment conditions.
Fig. 1 shows Cu corrosion defects after ILD etching at around 20% RH in the FOUP. This defect is only observed in the lower slot of the FOUP on the N2 purged load port. Figure 2 illustrates a chart depicting the humidity inside the FOUP under various conditions. The humid region within the FOUP when opened on the N2 purged load port without wafers. (Fig.2a) While the extent of the humid area is contingent upon the flow rate of the N2 purge and the intake of air through the Fan Filter Unit (FFU), the vortex of the inlet air from the cleanroom (<42% RH) is notably observed at the bottom and front side of the FOUP. Therefore, wafers stored in the lower slot of the FOUP face an increased risk of Cu corrosions when subjected to elevated humidity levels during processes like ILD etching and subsequent cleaning. Specifically, an extended queue time amplifies the probability of Cu defects occurring in this high-humidity slot compared to slots with lower humidity. We observed an unintended increase to 28.2% RH in specific configurations when reducing the quantity of wafers to minimize queue time. (Fig. 2b)
Hence, we propose an arrangement for wafers that maintains low humidity with small quantity. When placing 12 wafers in the FOUP, an arrangement with equal spacing from the first slot to the 25th slot ensures uniform N2 flow, thereby reducing the highest humidity from 28.2% RH to 14.0% RH by half. (Fig.3a) Alternatively, positioning all wafers on the upper section is another method. (Fig.3b) Therefore, by halving the quantity of wafers and reducing the process wait time by half, and applying the optimal wafer arrangement that maintains low humidity balance even with a small number of wafers, we confirmed the absence of Cu corrosion.

References

[1] Y.-L. Cheng et al. Copper Metal for Semiconductor Interconnects. Noble and Precious Metals – Properties. Nanoscale Effects and Applicationshttp://dx.doi.org/10.5772/intechopen.723962018 (2018)
[2] N. R. Kamat et al. A Study of Sulphur Assisted Corrosion in Technologies with Copper Interconnects. 2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits 183–186 (2006)
[3] B. Li et al. Reliability challenges for copper interconnects. Microelectron. Reliab.
44, 365–380 (2004)
[4] J. Jeong et al. Control of Wafer Slot-Dependent Outgassing Defects during Semiconductor Manufacture Processes. 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)
21, 1–4 (2019)
[5] S. C. Hu et al. 450mm FOUP/LPU system in advanced semiconductor manufacturing processes: A study on the minimization of oxygen content inside FOUP when the door is opened. 2015 Joint e-Manufacturing and Design Collaboration Symposium (eMDC) & 2015 International Symposium on Semiconductor Manufacturing (ISSM
), 1-4 (2015)

Figure 1