bluuebunny/crossref_metadata_2025_split huggingface dataset:
Changes in high-risk sexual behaviour among Estonian adults between 1996 and 2006
Authors: Liivlaid Hedi , Uusküla Anneli 
Published: September 2012

ObjectiveTo describe and compare sexual behaviour patterns in 1996 (before the explosion of the HIV epidemic in 2000) and 2006, and the correlates of high-risk sexual behaviour in Estonia.MethodsData on selected sexual behaviour characteristics were obtained by interviewing a probability sample of the adult population in Estonia in 1996 and 2006.ResultsData were available from 2441 sexually experienced women and 1994 men, and 3005 women and 2812 men in the year 2006. There were no changes in the proportion of sexually experienced adults, frequency of intercourse, or same gender sexual relationships. There was an increase in sex under the age of 16 (women: 8.4% vs 14.1% adjusted OR (AOR) 2.05 (1.67 to 2.53); men: 21.9% vs 28.0% AOR 1.58 (1.35 to 1.84)). From 1996 to 2006, the proportion reporting intercourse with a casual partner in the previous 12 months decreased significantly for women (10.7% vs 6.0% AOR 0.54 (95% CI 0.41 to 0.72)) and men, (24.0% vs 16.5% AOR 0.71 (0.59 to 0.85)) in parallel with a decrease in those reporting never using condoms during intercourse with a casual partner (for women: 49.3% vs 19.2% AOR 0.27 (0.14 to 0.51); and men: 35.4% vs 20.2% AOR 0.37 (0.25 to 0.56)). In 2006, the odds for not always using condoms in intercourse with casual partners increased significantly with age (eg, ≤24 vs ≥45: AOR 3.46 (1.68 to 7.13)), and were higher among those widowed/divorced/separated (AOR 2.35 (CI 1.20 to 4.60)).ConclusionsFrom 1996 to 2006, a significant reduction in high-risk sexual behaviour has occurred in Estonia across all age groups and genders.
Fault linkage and damage zone architecture in tight carbonate rocks in the Suez Rift (Egypt): implications for permeability structure along segmented normal faults
Authors: Rotevatn A. , Bastesen E. 
Published: September 2012

Abstract
A field study focusing on fracture systems in a fault linkage zone from the Suez Rift, Egypt, is presented to elucidate the role of fault linkage zones in the permeability structure of segmented normal faults in tight carbonate rocks. Fracture systems in the linking damage zone show significantly increased structural complexity compared to that typical of isolated faults. The linkage zone is characterized by high fracture frequencies and multiple fracture sets of different orientations. Notably, pervasive fracture corridors strike at high angles to the fault trend and are interpreted to have formed during the latest evolutionary stages of what is interpreted as a breached relay. The structural observations indicate that along segmented normal faults in carbonate rocks, fault linkage zones represents locations of progressively increased cross- and along-fault permeability through the stages of relay growth and breaching. Our findings, in combination with previously published work, indicate that fault linkage zones represent localized conduits not only for increased fluid flow across faults, but also (vertically) within fault zones. Appreciating this has wide-ranging implications for understanding fluid transport in carbonate rocks and other naturally fractured lithologies.
The importance of natural fractures in a tight reservoir for potential CO
2
storage: a case study of the upper Triassic–middle Jurassic Kapp Toscana Group (Spitsbergen, Arctic Norway)
Authors: Ogata K. , Senger K. , Braathen A. , Tveranger J. , Olaussen S. 
Published: September 2012

Abstract

In the Longyearbyen CO
2
laboratory project, it is planned to inject carbon dioxide into a Triassic–Jurassic fractured sandstone–shale succession (Kapp Toscana Group) at a depth of 700–1000 m below the local settlement. The targeted storage sandstones offer moderate secondary porosity and low permeability (unconventional reservoir), whereas water injection tests evidence good lateral fluid flow facilitated by extensive fracturing. Therefore, a detailed investigation of fracture sets/discontinuities and their characteristics have been undertaken, concentrating on the upper reservoir interval (670–706 m). Datasets include drill cores and well logs, and observations of outcrops, that mainly show fracturing but also some disaggregation deformation bands in the sandstones. The fracture distribution has a lithostratigraphical relationship, and can be subdivided into: (A) massive to laminated shaly intervals, offering abundant lower-angle shear fractures; (B) massive to thin-bedded, heterogeneous, mixed silty–shaly intervals, with a predominance of non-systematic, pervasive bed-confined fractures; and (C) massive to laminated, medium- to thick-bedded, fine- to coarse-grained sandstones with a lower frequency of mostly steep fractures. These domains represent pseudo-geomechanical units characterized by specific fracture sets and fracture intensity, with indicated relationships between the bed thickness and fracture intensity, and with domains separated along bedding interfaces. We discuss the impact of these lithostructural domains on the fluid flow pathways in the heterolithic storage unit.
A theory of monte carlo visibility sampling
Authors: Ramamoorthi Ravi , Anderson John , Meyer Mark , Nowrouzezahrai Derek 
Published: September 2012

Soft shadows from area lights are one of the most crucial effects in high-quality and production rendering, but Monte-Carlo sampling of visibility is often the main source of noise in rendered images. Indeed, it is common to use deterministic uniform sampling for the smoother shading effects in direct lighting, so that all of the Monte Carlo noise arises from visibility sampling alone. In this article, we analyze theoretically and empirically, using both statistical and Fourier methods, the effectiveness of different nonadaptive Monte Carlo sampling patterns for rendering soft shadows.
We start with a single image scanline and a linear light source, and gradually consider more complex visibility functions at a pixel. We show analytically that the lowest expected variance is in fact achieved by uniform sampling (albeit at the cost of visual banding artifacts). Surprisingly, we show that for two or more discontinuities in the visibility function, a comparable error to uniform sampling is obtained by “uniform jitter” sampling, where a constant jitter is applied to all samples in a uniform pattern (as opposed to jittering each stratum as in standard stratified sampling). The variance can be reduced by up to a factor of two, compared to stratified or quasi-Monte Carlo techniques, without the banding in uniform sampling.
We augment our statistical analysis with a novel 2D Fourier analysis across the pixel-light space. This allows us to characterize the banding frequencies in uniform sampling, and gives insights into the behavior of uniform jitter and stratified sampling. We next extend these results to planar area light sources. We show that the best sampling method can vary, depending on the type of light source (circular, Gaussian, or square/rectangular). The correlation of adjacent “light scanlines” in square light sources can reduce the effectiveness of uniform jitter sampling, while the smoother shape of circular and Gaussian-modulated sources preserves its benefits—these findings are also exposed through our frequency analysis. In practical terms, the theory in this article provides guidelines for selecting visibility sampling strategies, which can reduce the number of shadow samples by 20--40%, with simple modifications to existing rendering code.
Sensor activation and radius adaptation (SARA) in heterogeneous sensor networks
Authors: Bartolini Novella , Calamoneri Tiziana , La Porta Tom , Petrioli Chiara , Silvestri Simone 
Published: September 2012

In order to prolong the lifetime of a wireless sensor network (WSN) devoted to monitoring an area of interest, a useful means is to exploit network redundancy, activating only the sensors that are strictly necessary for coverage and making them work with the minimum necessary sensing radius.
In this article, we introduce the first algorithm that reduces sensor coverage redundancy through joint Sensor Activation and sensing Radius Adaptation (SARA) in general application scenarios comprising two classes of devices: sensors with variable sensing radius and sensors with fixed sensing radius. This device heterogeneity is explicitly addressed by modeling the coverage problem through Voronoi-Laguerre diagrams that, differently from Voronoi diagrams, allow for correctly identifying each sensor coverage region depending on the sensor current radius and the radii of its neighboring nodes. SARA executes quickly with guaranteed termination and, given the currently available nodes, it always guarantees maximum coverage. By means of extensive simulations, we show that SARA obtains remarkable improvements with respect to previous solutions, ensuring, in networks with heterogeneous nodes, longer network lifetime and wider coverage.
A Model Checking Based Approach to Bounding Worst-Case Execution Time for Multicore Processors
Authors: Wu Lan , Zhang Wei 
Published: September 2012

As multicore processors are increasingly adopted in industry, it has become a great challenge to accurately bound the worst-case execution time (WCET) for real-time systems running on multicore chips. This is particularly true because of the inter-thread interferences in accessing shared resources on multicores, such as shared L2 caches, which can significantly affect the performance but are very difficult to be estimated statically.
This article proposes an approach to analyzing WCET for multicore processors with shared L2 instruction caches by using a model checking based method. We model each concurrent real-time thread, including the inter-thread cache interferences with a PROMELA process, and derive the WCET by using a binary search algorithm. To reduce the state explosion problem, we propose several techniques for reducing the memory consumption by exploiting domain-specific information. Our experiments indicate that compared to the static analysis technique based on extended ILP (integer linear programming), our approach improves the tightness of WCET estimation by more than 31.1% for the benchmarks we studied. However, due to the inherent complexity of multicore timing analysis and the state explosion problem, the model checking based approach currently can only work with small real-time kernels for dual-core processors.
RAIDR
Authors: Liu Jamie , Jaiyen Ben , Veras Richard , Mutlu Onur 
Published: September 2012

Dynamic random-access memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operations waste energy and degrade system performance by interfering with memory accesses. The negative effects of DRAM refresh increase as DRAM device capacity increases. Existing DRAM devices refresh all cells at a rate determined by the leakiest cell in the device. However, most DRAM cells can retain data for significantly longer. Therefore, many of these refreshes are unnecessary.
In this paper, we propose RAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times. Our key idea is to group DRAM rows into retention time bins and apply a different refresh rate to each bin. As a result, rows containing leaky cells are refreshed as frequently as normal, while most rows are refreshed less frequently. RAIDR uses Bloom filters to efficiently implement retention time bins. RAIDR requires no modification to DRAM and minimal modification to the memory controller. In an 8-core system with 32 GB DRAM, RAIDR achieves a 74.6% refresh reduction, an average DRAM power reduction of 16.1%, and an average system performance improvement of 8.6% over existing systems, at a modest storage overhead of 1.25 KB in the memory controller. RAIDR's benefits are robust to variation in DRAM system configuration, and increase as memory capacity increases.
PARDIS
Authors: Bojnordi Mahdi Nazm , Ipek Engin 
Published: September 2012

Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable---a proven technique that has seen wide use in other control tasks ranging from DMA scheduling to NAND Flash and directory control. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx controllers to fixed-function hardware.
This paper presents the instruction set architecture (ISA) and hardware implementation of PARDIS, a programmable memory controller that can meet the performance requirements of a high-speed DDRx interface. The proposed controller is evaluated by mapping previously proposed DRAM scheduling, address mapping, refresh scheduling, and power management algorithms onto PARDIS. Simulation results show that the average performance of PARDIS comes within 8% of fixed-function hardware for each of these techniques; moreover, by enabling application-specific optimizations, PARDIS improves system performance by 6--17% and reduces DRAM energy by 9--22% over four existing memory controllers.
Boosting mobile GPU performance with a decoupled access/execute fragment processor
Authors: Arnau José-María , Parcerisa Joan-Manuel , Xekalakis Polychronis 
Published: September 2012

Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the operating time per battery charge. The CPU/GPU component is only left with a shrinking fraction of the power budget, since most of the energy is consumed by the screen and the antenna.
In this paper, we focus on improving the energy efficiency of the GPU since graphical applications consist an important part of the existing market. Moreover, the trend towards better screens will inevitably lead to a higher demand for improved graphics rendering. We show that the main bottleneck for these applications is the texture cache and that traditional techniques for hiding memory latency (prefetching, multithreading) do not work well or come at a high energy cost.
We thus propose the migration of GPU designs towards the decoupled access-execute concept. Furthermore, we significantly reduce bandwidth usage in the decoupled architecture by exploiting inter-core data sharing. Using commercial Android applications, we show that the end design can achieve 93% of the performance of a heavily multithreaded GPU while providing energy savings of 34%.
TimeWarp
Authors: Martin Robert , Demme John , Sethumadhavan Simha 
Published: September 2012

Over the past two decades, several microarchitectural side channels have been exploited to create sophisticated security attacks. Solutions to this problem have mainly focused on fixing the source of leaks either by limiting the flow of information through the side channel by modifying hardware, or by refactoring vulnerable software to protect sensitive data from leaking. These solutions are reactive and not preventative: while the modifications may protect against a single attack, they do nothing to prevent future side channel attacks that exploit other microarchitectural side channels or exploit the same side channel in a novel way.
In this paper we present a general mitigation strategy that focuses on the infrastructure used to measure side channel leaks rather than the source of leaks, and thus applies to all known and unknown microarchitectural side channel leaks. Our approach is to limit the fidelity of fine grain timekeeping and performance counters, making it difficult for an attacker to distinguish between different microarchitectural events, thus thwarting attacks. We demonstrate the strength of our proposed security modifications, and validate that our changes do not break existing software. Our proposed changes require minor -- or in some cases, no -- hardware modifications and do not result in any substantial performance degradation, yet offer the most comprehensive protection against microarchitectural side channels to date.
A micro-architectural analysis of switched photonic multi-chip interconnects
Authors: Koka Pranay , McCracken Michael O. , Schwetman Herb , Chen Chia-Hsin Owen , Zheng Xuezhe , Ho Ron , Raj Kannan , Krishnamoorthy Ashok V. 
Published: September 2012

Silicon photonics is a promising technology to scale offchip bandwidth in a power-efficient manner. Given equivalent bandwidth, the flexibility of switched networks often leads to the assumption that they deliver greater performance than point-to-point networks on message passing applications with low-radix traffic patterns. However, when optical losses are considered and total optical power is constrained, this assumption no longer holds.
In this paper we present a power constrained method for designing photonic interconnects that uses the power characteristics and limits of optical switches, waveguide crossings, inter-layer couplers and waveguides. We apply this method to design three switched network topologies for a multi-chip system.
Using synthetic and HPC benchmark-derived message patterns, we simulated the three switched networks and a WDM point-to-point network. We show that switched networks outperform point-to-point networks only when the optical losses of switches and inter-layer couplers losses are each 0.75 dB or lower; achieving this would require a major breakthrough in device development. We then show that this result extends to any switched network with similarly complex topology, through simulations of an idealized "perfect" network that supports 90% of the peak bandwidth under all traffic patterns. We conclude that given a fixed amount of input optical power, under realistic device assumptions, a point-to-point network has the best performance and energy characteristics.
RADISH
Authors: Devietti Joseph , Wood Benjamin P. , Strauss Karin , Ceze Luis , Grossman Dan , Qadeer Shaz 
Published: September 2012

Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforcing both atomicity and determinism. Unfortunately, existing software-only dynamic race detectors are precise but slow; proposals with hardware support offer higher performance but are imprecise. Both precision and performance are necessary to achieve the many advantages always-on dynamic race detection could provide.
To resolve this trade-off, we propose Radish, a hybrid hardware-software dynamic race detector that is always-on and fully precise. In Radish, hardware caches a principled subset of the metadata necessary for race detection; this subset allows the vast majority of race checks to occur completely in hardware. A flexible software layer handles persistence of race detection metadata on cache evictions and occasional queries to this expanded set of metadata. We show that Radish is correct by proving equivalence to a conventional happens-before race detector.
Our design has modest hardware complexity: caches are completely unmodified and we piggy-back on existing coherence messages but do not otherwise modify the protocol. Furthermore, Radish can leverage type-safe languages to reduce overheads substantially. Our evaluation of a simulated 8-core Radish processor using PARSEC benchmarks shows runtime overheads from negligible to 2x, outperforming the leading software-only race detector by 2x-37x.
Scale-out processors
Authors: Lotfi-Kamran Pejman , Grot Boris , Ferdman Michael , Volos Stavros , Kocberber Onur , Picorel Javier , Adileh Almutaz , Jevdjic Djordje , Idgunji Sachin , Ozer Emre , Falsafi Babak 
Published: September 2012

Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by on-die caches of existing server chips. Large caches reduce the die area available for cores and lower performance through long access latency when instructions are fetched. Performance on scale-out workloads is maximized through a modestly-sized last-level cache that captures the instruction footprint at the lowest possible access latency.
In this work, we introduce a methodology for designing scalable and efficient scale-out server processors. Based on a metric of performance-density, we facilitate the design of optimal multi-core configurations, called pods. Each pod is a complete server that tightly couples a number of cores to a small last-level cache using a fast interconnect. Replicating the pod to fill the die area yields processors which have optimal performance density, leading to maximum per-chip throughput. Moreover, as each pod is a stand-alone server, scale-out processors avoid the expense of global (i.e., inter-pod) interconnect and coherence. These features synergistically maximize throughput, lower design complexity, and improve technology scalability. In 20nm technology, scale-out chips improve throughput by 5x-6.5x over conventional and by 1.6x-1.9x over emerging tiled organizations.
Effective Combination Therapy for Malignant Glioma with TRAIL-Secreting Mesenchymal Stem Cells and Lipoxygenase Inhibitor MK886
Authors: Kim Seong Muk , Woo Ji Sun , Jeong Chang Hyun , Ryu Chung Heon , Lim Jung Yeon , Jeun Sin-Soo 
Published: September 2012

Abstract
The apoptotic ligand TRAIL is believed to have promise as a cancer gene therapy, yet many types of cancer, including gliomas, have exhibited resistance to TRAIL-induced apoptosis. Here, we show that therapeutic combination of the lipoxygenase inhibitor MK886 and TRAIL-secreting human mesenchymal stem cells (MSC-TRAIL) provide targeted and prolonged delivery of TRAIL both in vitro and in orthotopic mouse models of glioma. Treatment of either TRAIL-sensitive or TRAIL-resistant human glioma cells with MK886 and MSC-TRAIL resulted in significantly enhanced apoptosis compared with each agent alone. MK886 effectively increased the sensitivity to TRAIL-induced apoptosis via upregulation of the death receptor 5 and downregulation of the antiapoptotic protein survivin in human glioma cell lines and in primary glioma cells. This regulation was accompanied by a substantial increase in caspase activation after combined treatment. Furthermore, in vivo survival experiments and imaging analysis in orthotopic xenografted mice showed that MSC-based TRAIL gene delivery combined with MK886 into the tumors had greater therapeutic efficacy than single-agent treatment. Together, our findings indicate that MK886 combined with MSC-based TRAIL gene delivery may represent a novel strategy for improving the treatment of malignant gliomas. Cancer Res; 72(18); 4807–17. ©2012 AACR.