bluuebunny/crossref_metadata_2025_split huggingface dataset:
Design of a MEMS Force Sensor for Quantitative Measurement in the Nano- to Pico-Newton Range
Authors: Liew Li-Anne , Moreland John M. , Pratt Jonathan R. 
Published: October 2015

We describe the design and fabrication of a MEMS nano- to pico-Newton force sensor with SI traceability.
There has been much recent interest in developing instrumentation for the quantitative measurement of forces in the nano- to pico-Newton range. Forces in this range are frequently encountered when investigating mechanical properties of nanomaterials, in nanobiotechnology, and in single-molecule biophysics.
Various methods of measuring forces at these levels include using AFM cantilevers, scanning probe microscopy, and nanoindentation. However, such measurements are relative, and in order to obtain precise quantitative measurements, it is necessary to be able to calibrate such sensors in a manner that is traceable to fundamental SI units. One such method of calibration is using an Electrostatic Force Balance (EFB) that has been established at NIST.
We thus describe the design and fabrication of a MEMS-based force sensor that may be directly calibrated with the EFB and thus has the potential to measure nano- to pico-Newtons of force with SI traceability. The sensor consists of a silicon rigid arm supported on silicon tethers and which are attached to capacitive electrodes. The bar, tethers and electrodes are made from the device layer of a double side SOI wafer. A glass wafer with patterned metal electrodes is anodically bonded on both the top and bottom of the wafer to form symmetrical capacitive electrodes. An external force moves the silicon arm and the resulting capacitive force gradient of the electrodes is measured with the EFB. The mechanical structure and electrodes are designed for force sensitivity in the nano- to pico-Newton ranges and for operation in UHV to reduce thermomechanical noise. We discuss the design, initial fabrication and testing of this force sensor as a step toward the ultimate goals of quantitative nanomechanical testing of materials, NEMS, and engineered surfaces at the nanoscale.
Advanced SiP Packaging Technologies of IPD for Mobile Applications
Authors: Kim Geun Sik , Liu Kai , Carson Flynn , Yoon Seung Wook , Padmanathan Meenakshi 
Published: October 2015

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices.
Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors.
The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand.
In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important.
This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.
Flip Chip and Wafer Level Packaging - Past, Present and Future
Authors: Elenius Peter 
Published: October 2015

Flip chip packaging was developed nearly 50 years ago by IBM for the purposes of improved reliability and automated semiconductor assembly. For the first 35 years the use of flip chip technology was limited to a few large IDMs and automotive companies. Beginning fifteen years ago, companies providing flip chip bumping services were established. The primary reason for adoption of flip chip in the 1990s was to enable higher I/O count chips and to improve the power and ground distribution through the use of area array interconnects. Beginning in the early 2000s high speed serial links and other I/O with fast edge rates required the use of flip chip interconnects to improve signal propagation. In the future a greater percentage of devices will utilize flip chip interconnects as these chip requirements continue to drive increased demand. Future challenges include the requirements for better power and ground distribution, finer pitch interconnects and higher I/O count devices while protecting the every more fragile inter layer dielectrics (ILDs) present on the device.
Wafer Level Package (WLP) technology was developed approximately fifteen years ago to address form factor requirements in mobile products. Today WLPs play an ever increasing role in both mobile and other applications. An understanding of the market drivers, technology limitations, and variety of WLP structures used will be reviewed from both a historical perspective and current implementation. The breadth of products that are currently packaged with WLPs will also be reviewed. The principal challenges for WLPs both today and historically has been to provide adequate thermal cycle reliability and drop test capability for ever increasing device sizes and ball counts. Future market requirements for WLP technology will likely require new structures that can be cost effectively produced.
SUEX Laminates for Fan-In, Fan-Out and eWLB Development
Authors: Johnson Donald W. , Tsai Bin-Hong 
Published: October 2015

The focus of this presentation is on the use of SUEX epoxy Thick Dry Film Sheets (TDFS) as a photoimagable dielectric layer in fan-in, fan-out and e-WLP applications. The sheets can be laminated over severe topography from under 2 μm to over 200 μm in height yielding void free coatings with 100% planarization over the entire substrate. The TDFS are available in a range of thicknesses and wafer or panel sizes.
This new material is prepared under a highly controlled solvent-less process, which provides uniform coatings between two throw-away layers of protective polyester film. SUEX sheets of 100 μm thickness have been vacuum laminated in an isothermal process at 60–80°C over 180 μm high, 2mm X 2mm device chips mounted onto a silicon carrier wafer. Process optimization studies were run to determine the desired chamber vacuum, chuck temperature, lamination pressure and lamination time for optimal performance. The entire lamination process has a cycle time of about 10min.
Using a vacuum laminator we have been able to obtain totally void-free coatings over 2 to 5 μm high bonding pads and buss lines at the silicon surface with a resist thickness of 205 μm over the trench and 25 μm thickness over the back of the chip with 100% planarization over the surface interface. Exposures on a contact aligner have yielded nominal 50 μm diameter via holes through the resist film to the contact pads at the bottom of the trench. Excellent adhesion to all surfaces on both the carrier wafer and the device chip has been obtained without any delamination or crack formation. Additional work to be presented will demonstrate the filling of the vias with electroplated copper to form interconnects the interconnects to for connection to bonding pads on the fan-out package surface.
Failure Analysis and Reliability of 3D Integrated Systems
Authors: Ramm Peter , Klumpp Armin , Franz German , Kwakman Laurens 
Published: October 2015

Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. According to the ITRS road map [1] there is a variety of reasons for application of 3D integration, such as miniaturization, improved circuit performance, lower power consumption and heterogeneous integration. World-wide, several full 3D process flows have been demonstrated. However, there is a strong demand for considering the behaviour and reliability of 3D-integrated systems [2]. Explicitly, the impact of 3D processes on the system, e.g. thermo-mechanical stresses, has to be evaluated before the implementation to production lines.
A test chip for reliability evaluation of 3D TSV technologies was designed and fabricated by Fraunhofer EMFT.
The 3D-integrated reliability test chip is a 3-level-stack with TSVs through a middle (2nd) device layer to connect structures on the bottom (1st) level with the top (3rd) level device. The layout is modular, so you can test basic assembly processing with the combination of level 1 with level 2 only and the influence of additional processing when adding level 3. For reliability testing, temperature cycling following the JEDEC standard was performed from −55 C ° to +150 °C (at a soak time of 5 minutes). Additionally, analysis was done by cross sectioning and reversed engineering.
The 3D-integrated test chips were fabricated by application of Fraunhofer EMFT's TSV SLID technology. The applied 3D TSV process is based on intermetallic compound (IMC) bonding and TSV formation before stacking [3]. Reliability issues related to thermo-mechanical stress caused by the 3D integration process have to be considered. Failures of 3D integrated systems caused by TSV formation and the permanent bonding process were analysed by a novel high rate milling Focussed Ion Beam equipment. Figure 1 schematically shows the application of the novel FIB analysis technique for the areas of interest (IMC bond, TSV cross sections). Compared to classical FIB systems, the new equipment allows to remove material significantly faster while maintaining good resolution at low beam currents, important for the subsequent analysis. Cross sections of the 3-layer stack are shown in Figure 2. The merits of the novel plasma FIB and the resulting failure analysis will be discussed in detail.
Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages
Authors: Katkar Rajesh , Huynh Michael , Mirkarimi Laura 
Published: October 2015

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance.
Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.
Electrolytic Solder Deposition for IC-Substrates: From Deposition Uniformity to Solder Ball Geometry
Authors: Roelfs Bernd , Matejat Kai 
Published: October 2015

The current screen printing process for solder deposition on IC substrates is coming to a technology boundary due to the continuous down sizing of the solder structures. This will require soon new methods of solder transfer to the substrate. This paper describes an alternative process based on electrolytic deposition of Tin and Tin alloys for sub 100 μm solder balls. A suitable process sequence is evaluated and described in detail.
Uniformity of the electroplated deposits both in terms of solder thickness and chemical composition is of vital importance for the process. Thickness determines the solder ball diameter after reflow and elemental composition influences the reflow performance and solder joint reliability. We will present in this paper results from an investigation program to identify main parameters for the distribution of the plated solder. Main emphasis is here on difference between direct plated (DC) and reverse pulse plated (RPP)deposits. We want to clarify if reverse pulse plated layers exhibit a better distribution than dc plated deposits as known from other applications. As a 2nd very important parameter electrolyte flow is identified. We will show how variations in these parameters itself are translated first in variations of the plated layer and then – after reflow- into different solder ball geometries.
Understanding these influences will help introducing this technology into future production scenarios.
Novel Die-to-Wafer Interconnect Process for 3D-IC Utilizing a Thermo-Decomposable Adhesive and Cu-Cu Thermo-Compression Bonding
Authors: Pascual Daniel N. 
Published: October 2015

Die-to-wafer interconnect offers key advantages for 3D-IC including heterogeneous die population using devices from different process lines, and higher yield by incorporating only known-good die. Attaching the dies to a wafer, however, typically involves serial processing whereby each die is aligned and bonded one at a time. This can be prohibitively time consuming particularly when using a slow, high-temperature process such as Cu-Cu thermo-compression for each die in succession. Also, the high temperatures applied locally can adversely affect neighboring sites by oxidizing the Cu bonding surface if not protected in an oxygen-free environment. We have developed a novel die-to-wafer interconnect process that circumvents these problems using a die-tacking and global-bonding approach.
Using a high-accuracy die placement tool, individual dies are aligned and tacked onto a wafer that is coated with a thermo-decomposable adhesive layer. The low-temperature tacking process avoids oxidation of the Cu bonding surfaces, minimizes thermal cycling, and increases throughput significantly. Once the wafer is fully populated, it is then processed in a closed-chamber wafer-bonding tool, which provides an oxygen-free environment. All of the dies are bonded in parallel using a high-temperature Cu-Cu bonding process to globally apply the required heat and force. Once the adhesive is heated past its critical decomposition temperature, it cleanly vaporizes away and allows the Cu-Cu bonding to proceed.
We have successfully demonstrated this process on a 300mm platform using custom-designed test dies and wafers containing through-silicon via (TSV) chains and Kelvin test structures providing 4-point resistance measurements. Experimental results including TSV chain yield, electrical resistance, alignment accuracy, and cross-sectional analysis will be presented. A discussion will also be given on the potential cost savings and future technical challenges of this approach.
Hetero-Structure Integration using an Atmospheric Plasma Treatment for Surface Preparation before its Interconnection
Authors: Charlet Barbara , Charlet B. , Di Cioccio L. , Rochat N. , Renault O. , Clavelier L. , Deguet C. 
Published: October 2015

One of the open challenges, related to the heterogeneous devices stacking, is its surface preparation, in order to assure the optimal electrical connections, and finally achieve the high performance structures having the stacked chips and passive components.
Several techniques, using dry or wet process, allow the surface activation and preparation before the successive vertical interconnection achievement. We report the implementation of an environment friendly method, developed for chips and passive circuits surface preparation before its interconnection. This method is based on the use of atmospheric-pressure plasma source generating the radicals flux in the nitrogen or noble gases, mixed with a small volume of reactive gases, in order to stimulate the surface reactions. The surface properties of various treated materials were characterised by water drop contact angle, FTIR and TXRF method. The results of these behaviours allow defining a dedicated flow chart, in order to apply this surface treatment for the self-positioning of small silicon chips on the connection pads of printed passive circuits. Optimised process was applied to the silicon ICs chips assembly on the flexible polymeric substrates with passive devices; furthermore the treatment potentiality was also proved for other type of substrates and materials used for hetero structure integration. The application example given in this study concerns a novel approach of FRID tag assembly.
300mm Large Scale eWLB(embedded Wafer Level BGA) : Cost Effective Solution with Performance
Authors: Yoon Seung Wook , Lin Yaojian , Marimuthu Pandi C. , Lee Yeong J. 
Published: October 2015

Demand for Wafer Level Package (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. The increasing demand for new and more advanced electronic products with smaller form factor, superior functionality and performance is driving the integration of functionality into the third dimension. There are some restrictions in possible applications for fan-in WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. 200mm eWLB is in HVM from industry last three years and there was need to move 300mm for scaling-up and low-cost solutions.
This paper will highlight some of the recent advancements in large scale 300mm eWLB development. Compared to 200mm case, 300mm has more warpage and process issues due to its area increase. Thermo-mechanical simulation shows 100~150% more warpage with 300mm compared to 200mm. So various design parameters were studied to optimized warpage, such as dielectric materials and thickness, molding compound thickness etc. This paper presents study of process optimization for 300mm eWLB and mechanical characterization, reliability data including component/board level, challenges encountered and overcome, and future steps of scalability for higher throughput and manufacturability.
Ultrathin WLP Die Embedded Polyimide Multi-Layer Wiring Board
Authors: Okude Satoshi , Okamoto M. , Sano Y. , Ueta N. , Nakao O. 
Published: October 2015

We have developed an ultrathin IC-embedded polyimide multi-layer wiring board utilizing a wafer level packaging (WLP) technology. The IC die is wafer level packaged with no solder bump (i.e. just copper land), thinned less than 100 micron and then sandwiched between multi-layer printed wiring boards composed of thin polyimide films with the thickness of several tens of microns used in standard flex boards. Therefore, the realized embedded board has a very thin structure, e.g. the thickness of a 4 layers board with 1 die embedded is 220 micron. For the electrical connection between circuit layers including redistribution layer of the embedded die, the means employed in our standard wiring board process is applied. The electrical connection is made by the conductive paste, which consists of several kinds of metal filler and resin adhesive and makes alloy between copper of circuit layer thorough pressing and heating processes. The alloying feature of the paste assures the robustness of the connection.
The reliability of the board under several environmental test conditions has been confirmed so far, however, the board performance under bending stress was unclear. The realized board is still flexible and bendable to some extent, although the board has higher stiffness than standard flex board owing to its multi-layer structure. To confirm whether this feature affect on the board's performance or not, we have investigated the performance of the embedded board under the condition that the bending stress is applied to the die embedded die. The experimental results show no significant change due to the bending stress and the high durability against bending is confirmed.
Impact of Process Improvements on Reliability of RCP Technology During Scale-up
Authors: Leal George R. , Hayes Scott , Koey Dominic , Gong Tony , Mitchell Doug , Wei Gao , Wright Jason , Vessa Tony 
Published: October 2015

The start-up of the 300mm RCP prototype production line using automated tools was challenged by significant differences in tool sets when compared to the manual and semi-automatic lab based equipment used to develop the baseline RCP fabrication process. Thus, process transfer to automated tools required key parameter adjustments in an attempt to match the process output and reliability performance previously achieved with the 200mm lab based flow. During reliability testing of early parts from the 300mm prototype line, failures in the build-up layers were observed after thermal cycling test. The failure mechanisms were previously observed and resolved during the technology development phase using the 200mm lab based tools.
An experiment was developed to identify the root cause of the build-up failures. A single die, 9x9mm, 258 I/O, 0.5mm pitch package with 2 metal routing layers was chosen as a test vehicle for the experiment. Moisture preconditioning and air to air thermal cycling at 2 different conditions followed by electrical test and visual inspection for dielectric cracks were used to gage reliability performance. Several factors were evaluated related to the dielectric and metallization processes as well as the backend interconnect process. The results from the experiment indicated the appropriate tool parameters that allowed the 300mm prototype line process output to closely match that of the 200mm lab based tools. The optimized process combined with the use of an alternate solder material allowed the 300mm RCP prototype line to successfully achieve line certification status and demonstrated RCP reliability performance beyond standards.