bluuebunny/crossref_metadata_2025_split huggingface dataset:
A Flexible Manufacturing Method for Wafer Level Packages
Authors: Strothmann Tom , Pricolo Damien , Yoon Seung Wook , Lin Yaojian 
Published: October 2015

The demand for Wafer Level Chip Scale Packages (WLCSP) has experienced tremendous growth due to the surge in demand for advanced mobile products. The increased demand is seen for both 200mm wafers and 300mm wafers, however a significant segment of the market continues to be driven by 200mm designs. The infrastructure capacity supporting 200mm WLCSP has been stressed as a result of the mature status of 200mm technology and the rate of conversion of alternative package formats to WLCSP. This creates a dilemma for WLP service providers because adding 200mm capacity continues to require a significant amount of capital. Since 200mm volumes will most likely decline within the next 5 years, it is difficult to justify the use of capital when the depreciation term is longer than the anticipated life cycle of the product.
Conventional methods of manufacturing wafer level packages require the use of equipment specifically sized to a given silicon wafer diameter although there is no technical requirement to maintain the round silicon format. The conventional method has been beneficial since it leveraged equipment and processes developed for the IC industry, however the equipment is very expensive for larger wafer diameters and the fine geometries required in advanced node IC products are not required for wafer level packaging. The problem is serious for 200mm and 300mm wafer bump lines, however the capital equipment cost for a future 450mm bumping line may well be prohibitive for wafer level packaging.
A new manufacturing method has been developed to produce a wafer level package that severs the link between wafer diameter and wafer level packaging methods. The new manufacturing method is wafer size agnostic, so one manufacturing module can produce fan-in, fan-out, and 3D fan-out products regardless of the incoming wafer size. The same bill of materials, manufacturing methods and manufacturing location can produce wafer level packages from any size silicon wafer. In this method the wafer is diced prior to processing and then the die are recombined into a uniform panel size. Once recombined into a panel format, the product is processed with conventional wafer level packing techniques, including dielectric deposition, metal plating and solder ball drop. Since the manufacturing module is wafer size agnostic, there is no risk of capital for investment in the manufacturing infrastructure. A change in loading between 200mm, 300mm, and 450mm wafers does not adversely affect the utilization of the manufacturing module. The process also enables new advanced wafer level packages otherwise unattainable with conventional manufacturing methods. This presentation will describe the new manufacturing module approach and the results of process characterization for products produced in the module.
Integrated Localized Cooling using Piezoelectrically-Driven Synthetic Jets
Authors: Kranz Michael , Hudson Tracy , Whitley Michael , English Brian 
Published: October 2015

RF communication and radar systems present an extreme thermal management challenge. These systems are comprised of tightly packaged and high wattage components requiring a controlled temperature to meet performance and reliability parameters. In these systems, there is little space available for air flow or other traditional cooling methods. In addition, the heat generating components are typically microscale semiconductor devices fabricated on integrated circuit substrates buried deep within the system. Localized cooling using integrated microsystems may provide a solution to these thermal management issues.
One approach being pursued to meet this thermal challenge is the integration of miniature synthetic air jets near the heat generating components. These synthetic jets are generated using oscillating piezoelectric actuators that force air through a small nozzle at high flow rates and in very close proximity to the heat generating component. The resulting jets provide vorticity within the fluid, leading to enhanced mixing with the surrounding lower temperature fluid, and a subsequent increase in the heat transfer coefficient. The US Army AMRDEC is developing and operating microactuator test beds to mature these concepts and implement practical integration solutions. This investigation has modeled potential actuators and jets in using computational fluid dynamics and heat transfer codes, verified the results of these models with the prototype test beds, and demonstrated high-levels of localized cooling. This paper will present actuator designs, thermal modeling results, and actual cooling results using a high-stroke piezoelectric actuator as the drive element.
Metrology and Inspection for New Interconnects in Advanced Packaging
Authors: Dudley Russ , Wilson Matt , Roy Rajiv 
Published: October 2015

Interconnects for Advanced Packaging are getting smaller and come in a variety of sizes, shapes, and materials. The height, diameter, shape, and the absence/presence of these interconnects are critical and must be monitored across the device and wafer to ensure reliable connections during the bonding process.
Solder bump technologies have been utilized in the past, but cannot support the high density interconnects that are required. New interconnect technologies being utilized for wafer level packaging (WLP) and through silicon via (TSV) packages include copper pillar posts and TSV posts. These new interconnect technologies provide higher density, improved reliability, and better electrical performance.
This paper will highlight the critical metrology and inspection requirements for these new interconnect technologies and demonstrate the capability of a single platform to support these new interconnects for high volume manufacturing (HVM).
The single platform includes 3D metrology performed using a proprietary interferometric sensor technology that can measure the height of the post and the thickness of the surrounding polymer at the same time to optimize the measurement performance and system throughput. The platform also provides the ability to inspect for surface defects, irregular posts, missing posts, and a variety of other inspections typically performed on bumped wafers or substrates.
Both the metrology and inspection results from the single platform are output to a proprietary analysis package using industry standard Rudolph Result Files (RRF). The analysis will demonstrate the value these results provide for process control and the defect analysis, ultimately leading to improved yields and equipment utilization.
Development of 2.5D and 3D IC Fabrication and Assembly Technologies
Authors: Gao Guilian , Sheng Hong , Lee Sangil , Lee Bong-Sub , McGrath Scott , Wang Liang , Woychik Charles , Uzoh Cyprian , Villavicencio Grant , Alatorre Roseann , Arkalgud Sitaram 
Published: October 2015

2.5D/3D IC assembly is where the traditional foundry and assembly house model breaks down. The greatly reduced feature sizes of microbumps in combination with very large, thin interposers and ICs present many challenges for assembly. With densely integrated packages and stacked thin dies, warpage at various steps of assembly process can lead to die crack, weak or open interconnection, and delamination. Microbump die with copper pillar and solder cap lacks the flexibility of conventional BGA solder balls in warpage compensation. Low temperature dielectric materials for interposer backside passivation lack chemical, thermal stability and mechanical strength compared to similar materials cured at higher temperatures. Ultra- low stand-off between dies creates new challenge for flux residue removal and underfill processing, adhesion and reliability.
In this paper, we present learning and results from building two Invensas 2.5D interposer test vehicles with rectangular (19mmx27mm) and square (24mmx24 mm) silicon interposers. Since the industry is still debating where the MEOL processes will take place, these two test vehicles use both assembly centric and fab centric flows. We conducted comprehensive material and process compatibility studies to meet our goal of process capability and product reliability. We explored three different interposer fabrication/ assembly flows that includes copper-to-copper bonding as well as solder capped copper pillar microbumps for microbump die to interposer connection. We optimized the interposer fabrication process to improve interposer quality and warpage. We instituted 100% bump inspection and tight control on microbump die quality and co-planarity to improve assembly yield. We developed robust soldering and cleaning processes to achieve high soldering process yield. We evaluated several methods of flux clean and developed a procedure to achieve optimal flux residue removal without causing mechanical damage to solder joints. We explored vacuum and pressure curing process for underfill and adopted advance underfill cure technology to eliminate voids in underfill. The impact of these factors on assembly yield and reliability will be presented.
Silicon Wafer Integrated Fan-out Technology
Authors: Zwenger Curtis , Huemoeller Ron , Kim JinHan , Kim DongJean , Do WonChul , Seo SeongMin 
Published: October 2015

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need. These include Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP) approaches. In particular, emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm.
Traditional WLFO technologies are limited in design rules and 3D integration capabilities due to the processes and equipment used for circuit patterning. For more aggressive designs, TSV processes must be incorporated, which often times exceed the cost budget and design requirements needed for the device. Consequently, a gap exists between the design capabilities of WLFO and TSV that needs to be addressed.
A new, innovative fan-out structure called Silicon Wafer Integrated Fan-out Technology (SWIFT™) incorporates conventional WLFO processes with leading-edge thin film patterning techniques to bridge the gap between TSV and traditional WLFO packages. The SWIFT package technology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single & multi-die applications. The improved design capability of the technology is due, in part, to the fine feature capabilities associated with this new, innovative wafer level packaging technique. This can allow much more aggressive design rules to be applied compared to competing WLFO and laminate-based technologies. In addition, the unique characteristics of the SWIFT process enables the creation of innovative 3D structures that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of the SWIFT technology and its extension into unique 3D structures. In addition, the advantages of SWIFT designs will be reviewed in comparison to current competing packaging technologies. Process information, material characterization, and design simulation data will be presented to show how the SWIFT process is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.
Low Cost Chip Last Fanout Package using Coreless Substrate
Authors: Chen Scott , Wang Simon , Lee Coltrane , Hunt John 
Published: October 2015

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, but at the same time they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), fan out WLCSP (FOWLP) and system in package (SIP) being widely used in these smart phones & mobile devices.
Two factors have driven a new package technology within the last 10 years. One is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solderball interconnects. The second factor also relates to the advancing technology nodes. Not all silicon functionality benefits from there advanced nodes, and merely adds to the cost of the die. This has driven the partitioning of device functionality into multiple die, which in turn requires effective interconnection of these partitioned die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP).
The typical FOWLP uses chip first processing, in which the bare die is molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers.
We will describe a relatively low cost alternative to FOWLP, which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm.
All previous FOWLP designs at ASE were able to be routed in a single layer using this new packaging technology . Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented.
3D MICROSENSOR IMAGING ARRAYS NETWORKS
Authors: Fries David , Barton Geran 
Published: October 2015

2D microsensor arrays can permit spatial distribution measurements of the sensed parameter and enable high resolution sensing visualizations. Measuring constituents in a flowing media, such as air or liquid could benefit from such flow through or flow across imaging systems. These flow imagers can have applications in mobile robotics and non-visible imagery, and alternate mechanical systems of perception, process control and environmental observations.
In order to create rigid-conformal, large area imaging systems we have in the past merged flexible PCB substrates with rigid constructions from 3D printing. This approach merges the 2D flexible electronics world of printed circuits with the 3D printed packaging world.
Extending this 2D flow imaging concept into the third dimension permits 3D flow imaging networks, architectures and designs and can create a new class of sensing systems.
Using 3D printing, 3D printed filaments, nets and microsensor cages, can be combined into integrated designs to generate distributed 3D imaging networks and camera systems for a variety of sensory applications.
Development of TSV Reveal Process Using Very Fine Si/Cu Grinding and Metal Contamination Removal
Authors: Watanabe Naoya , Aoyagi Masahiro , Katagawa Daisuke , Bandoh Tsubasa , Mitsui Takahiko , Yamamoto Eiichi 
Published: October 2015

Three-dimensional integrated circuits (3D-ICs) using through silicon via (TSV) have been developed as an emerging technology that can lead to significant progress (1–4). Among various TSV processes, the via-middle process has potential for wide spread use because formation of small-sized TSVs is relatively easy in the via-middle process. However, TSV reveal process must be performed for electrical contact in the via-middle process. This TSV reveal process is important because it can influence the metal contamination and stacking yield of 3D-ICs. Conventionally, TSV reveal is performed by Si grinding and Si dry etching (5). A disadvantage of that method is the resultant TSV depth deviation, which can cause bonding failure during wafer/chip stacking. In (6), TSV leveling was performed by introducing a chemical mechanical polishing (CMP) step after deposition of the backside insulator. However, the revealed TSVs break during CMP step if they exceed a certain height.
To overcome these problems, we developed a novel TSV reveal process comprising direct Si/Cu grinding and metal contamination removal (7,8). First, simultaneous grinding of Cu and Si was performed using a novel vitrified grinding wheel. In situ cleaning with a high-pressure micro jet and the inelastic porous structure of the grinding wheel suppressed the adhesion of Cu contaminants to the Si, and TSVs were leveled and exposed. Next, an electroless Ni-B film was deposited on the Cu surface of the TSVs. The Si was etched with an alkaline solution, whereas the Cu was protected by the Ni-B film. An insulator was deposited, and then the insulator on the top surface of the TSV was removed. We achieved the backside reveal of TSVs without TSV depth deviation and suppressed Cu contamination to less than 1e11 atoms/cm2. However, after direct Si/Cu grinding with an 8000 grit grinding wheel, the average surface roughness of Si was 5–10 nm, which is larger than that after chemical mechanical polishing (CMP).
In this paper, we developed vitrified grinding wheels with very high grit numbers (#30,000 and #45,000) and present an improved version of our TSV reveal process. The average surface roughness of Si after Si/Cu grinding was approximately 3 nm for the 30,000 grit grinding wheel and 1 nm for the 45,000 grit grinding wheel. This value is equivalent to that after CMP. The improved process produced a uniform reveal of 4-um-diameter TSVs without TSV depth deviation and Cu contamination. The Cu contaminant concentration on Si region between TSVs was small (&lt;3e10 atoms/cm2). This process will reduce the cost of the TSV reveal process and considerably improve the TSV yield.
Design and fabrication of MEMS-type compliant overhang flip-chip interconnect for RF applications
Authors: Xu Pingye , Hamilton Michael C. 
Published: October 2015

With the increase of I/O density and scaling of interconnects, conventional solder ball interconnects are required to be made smaller. As a result, the reliability of the conventional solder ball flip-chip interconnects worsens. One method to mitigate this issue is by using underfill. However, underfill undermines the reworkability of the solder joints and is challenging to apply when the gap between chip and substrate is small. Another approach to enhance the reliability is to use taller solder ball interconnects, which is however usually more costly.
Instead of using conventional solder ball interconnects, compliant interconnects have also been researched in the past few decades to mitigate the reliability issue. The use of compliant structures can compensate for the coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic substrate.
In this work, we present the design and fabrication of MEMS-type compliant overhang flip-chip interconnects. The structures are placed at the end of a coplanar waveguide (CPW) as interconnects between CPWs to research their performance at radio frequency (RF). A micro-fabrication process was adopted to build the interconnects. The CPWs are fabricated using conventional e-beam deposition followed by photolithography and then copper electroplating. The compliant overhangs were fabricated on top of a dome of reflowed photoresist on the CPWs to form a curved shape. The reflow and hard bake of the photoresist requires a process temperature of above 220 °C, which is similar to the reflow temperature of a Sn-Ag-Cu (SAC) solder. Therefore we believe our process is compatible with SAC solder processing infrastructures in terms of process temperature. The fabricated structures show high yield and uniformity. Due to the use of a micro-fabrication based process, the structures have the potential to be scaled and be compatible to wafer level packaging.
The CPWs were then flip-chip bonded with the compliant interconnect as transitions. The RF performance of the interconnects up to 50 GHz will be presented.
System in Package Design Case Study
Authors: Meyer James 
Published: October 2015

In today's world, electronics need to be as small as possible. This is especially true for a wide range of electronics from UAV controllers, cellphones, to implantable medical devices. One approach to achieving small system size is the System in Package (SIP). This approach incorporates a complete system (processor, memory, etc) into one small package. On the SIP, packaged parts are replaced by dies directly mounted to the substrate via flip-chip or wire-bond technology. SIP allows the designer flexibility to create a small system with only functionality that is required. A designer can pick and choose what parts are needed for a design and is not limited to the functionality of a single signal chip.
Since the first level part packaging is eliminated, the overall board size decreased leading to an overall reduction in area and weight. Not only is there a reduction in size of each packaged part, but routing area is also reduced. The line widths and spacings can be reduced along with via size.
The system used in the case study is a typical system with a FPGA, flash memory, DDR3 memory, ADC, DAC, voltage monitors, power supply monitor and control. The design is a complete system capable of processing analog sensor data, recording the data in external memory and controlling analog outputs. Such a system can be used for data collection, vehicle control, data processing, etc.
In terms of signal integrity, the SIP offers many advantages over a traditional PWB. Given the small nature of overall package generally means shorter routes. A shorter route has the advantage of a reduced propagation delay. Also, a shorter trace will have a lower insertion loss and improved return loss. Many parts require data busses signals to match in length. This is very important for DDR3 memory. A mismatch in trace length will cause skew between the data signals and the data strobe. On a smaller board, there is an overall improvement for matching signal traces.
Power distribution is another area of improvement for the SIP. A smaller board size means the board resonances will be shifted higher in frequency, alleviating possible power rail noise issues. Overall, the power planes are less lossy. Also, decoupling capacitors will be placed closer to the active components reducing the inductive path from the active device and the capacitor. This will allow decoupling for parts switching at fast rates. Given the shorter distances between transceivers within the system, the drive strength can be reduced. Decreased drive strength will reduce the amount of power dissipated by the transceiver.
This presentation details a case study for a system in package design. A comparison will be made between the system laid out on a traditional printed wiring board (PWB) and the same system laid out on a substrate (SIP). Comparisons of the area, weight, route-ability and signal integrity will be made.