bluuebunny/crossref_metadata_2025_split huggingface dataset:
Temporary Bonding Cost Of Ownership: The link between low total thickness variation and chip yield
Authors: Uhrmann Thomas , Burggraf Jürgen , Wiesbauer Harald , Bravin Julian , Matthias Thorsten , Wimplinger Markus , Lindner Paul , Meynen Herman , Civale Yann , John Ranjith , Wang Sheng , Fu Peng-Fei , Yeakle Craig , Aw Gary 
Published: October 2015

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D stacked ICs (3Ds-IC). The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld consumer devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. Temporary bonding and debonding comprises several processes for which yield is essential, as costly fully functional device wafers are being processed.
The presented temporary bonding process consists of a bi-layer system, a release layer, Dow Corning WL-3001 Bonding Release and an adhesive layer, Dow Corning WL-4030 or WL-4050 Bonding Adhesive, processed on EVG's 850XT universal temporary bonding and debonding platform. Furthermore, this bi-layer spin coated material allows a room temperature bonding-debonding process increase process throughput which translates to low cost of ownership for high volume manufacturing. As such, this bi-layer approach features high chemical stability exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. Besides chemical stability this adhesive system provides also a high thermal stability when exposed to temperatures up to 300 °C. The temporary bonding process yield has a major impact on the overall Cost of Ownership (CoO). On the other hand, throughput of the individual process steps like spin coating, bonding, cure, debonding and cleaning processes is the second determining factor for improved CoO.
In this presentation, we will present a study of the total thickness variation (TTV) and the evolution of TTV at different stages of the process. High resolution in-line metrology is an enabling tool to trace the bond integrity and yield throughout backside processing. As TTV is a major determining factor of the overall process yield, understanding its impact over the bonded wafer pair carries major importance. Especially, non-continuity of the edge region, showing an inherent edge bead after coating, and edge die yield will be focus of our contribution. Finally, our experimental results will be transferred into a cost of ownership model, discussing the pros and cons for high volume production.
Applying system modeling to define 2.5 - d and 3 - d packaging roadmaps
Authors: Gupta Dev 
Published: October 2015

Though work on 3-d and later 2.5-d packaging has been going on now for over 5 years, we do not yet see large applications in areas other than traditional heterogeneous integration e,g. in camera modules. Adoption of 2.5-d Si interposer technology in 2010-11 to build FPGA modules on a commercial scale had generated much enthusiasm and expectation that floodgates will open for wide use of this technology e,g. in every Smart Phone but that has not yet materialized, giving rise to a shift in attention in Blogs and Conferences from purely digital applications e,g. processor - memory modules to more performance driven and cost insensitive applications e,g. heterogeneous modules for electro - optic I/O in servers etc.
Roadmaps for emerging technologies like 3-d stacking or 2.5-d modules are developed taking process maturity into consideration but they must also anticipate major applications. Such applications using a new technology can succeed only if there are overwhelming advantages in performance and system cost that negate increases in module costs. When the author and his team developed electroplated solder bump flip chip technology and their high volume implementation at two of the leading IDMs over 2 decades ago, both performance ( electrical ) and cost modeling were used to short list applications most likely to succeed and limit process development only for those applications. Countless users & providers of flip chip technology since then have benefited from this original work on electroplated solder and pillar bumps as well as build up type organic substrate technologies.
A similar theoretical approach is sorely needed in the development of 2.5-d and 3-d technologies to define the most cost - effective configurations and focus development work on only those. In this work we will discuss the Bandwidth and Power consumption ( two of the key drivers for die stacking ) of various 2.5-d and 3-d package configurations and based on simulation results compare them.
Key takeaways : 3-d stacking of dice using TSVs may not necessarily produce improved performance compared to less complicated packaging. Expensive interposers with high interconnect density may not even be necessary for most volume applications. Most likely configurations for processor - memory 3-d modules to get good enough bandwidth at lowest cost.
Path Finding for Multiple Platforms
Authors: Park John 
Published: October 2015

With the increasing complexity of today's SOCs and the growth in multi-die packaging, companies are recognizing the value of cross-domain collaboration between the IC, package substrate and PCB design groups. High pin count devices coupled with cost sensitivity drive engineers to reconsider how they plan, optimize and automate the I/O placement on their chips, while targeting multiple packaging variables, which have direct impact on how the PCB will be designed. In some instances, informal design flows based on multiple EDA design tools have been pieced together. This is a step in the right direction; however, without a central repository for the data or accurate device modeling and rule-based optimization, design intent is often misinterpreted or lost and redundancy is often introduced into the flow.
This presentation outlines a co-design methodology that allows design teams the ability to easily plan and optimize I/O and connectivity from a chip(s), through multiple packaging variables while targeting multiple different system platforms (PCBs).
Using this planning, optimization and design methodology, engineering teams for the IC, the Package and the PCB would drive rule-based I/O level optimization and perform ball-out studies from their respective domains, all while visualizing the impact across the complete system.
Key features and advantages of this methodology are:Multi-mode connectivity management for cross-domain pin/signal mapping/shortingUser definable rules for I/O and ball-out assignmentsRobust support for feasibility analysis and rapid prototypingFully automated library developmentDirect integration to multi-mode physical layout toolSeamless interface to 2D and 3D EM analysis enginesTight interface with CFD based thermal analysis solutionEDA vendor neutral flow
The result of implementing this methodology will be a chip(s) that is fully optimized for its package(s) and PCB(s). This solution drives down the cost of the package and PCB through layer reduction and tighter control of the design process without impacting the cost of the chip.
UV-C LEDs for Sterilization Applications
Authors: Grzyb Joe 
Published: October 2015

HexaTech has developed a proprietary, patented process for manufacturing bulk aluminum nitride (AlN) crystals and semiconductor wafers. HexaTech is leveraging this unique capability to develop and commercialize high-performance, long-lifetime Ultra Violet Light Emitting Diodes (UV-C LEDs) for disinfection applications (particularly clean water) and high-voltage, high-efficiency power semiconductors for power conversion applications (particularly smart grid).
Deep-ultraviolet light with wavelength in the range of 250 to 280nm (UV-C) has been used to sterilize liquids, air and surfaces for over a century. UV-C light is absorbed by and damages the DNA of harmful bacteria, either outright killing the bacteria or preventing their ability to replicate. Traditionally, high voltage mercury tubes have been used to generate such UV light. While mercury tubes have enabled UV-C use bulk disinfection applications such as drinking water and waste water, they have proven impractical in point-of-use applications where small size, elimination of harmful mercury, and high reliability under intermittent use conditions are required. The solution is to generate UV-C light using LEDs.
In spite of numerous efforts, the power output and reliability of UV-C LEDs is still not sufficient for their adoption as practical and reliable UV-C light sources. Traditionally, AlGaN-based UV-C LEDs have been fabricated on sapphire substrates. Because of huge number of defects caused by the lattice mismatch between the AlGaN active layers and the sapphire substrate, these sapphire-based UV-C LEDs show performance and reliability of limited interest to sterilization system manufacturers.
HexaTech's AlN crystal growth and wafer processing technology results in single crystal wafers with extremely high quality. HexaTech and its development partners have fabricated UV-C LEDs that have shown performance dramatically superior to other devices in the market in terms of output power, power density and lifetime.
In this presentation, we will discuss the market requirements for UV-C LEDs, the challenges of UV-C device fabrication, package and test, and the solutions that are being pursued.
ARM Dual Core Product Demonstration with 2.5D Through-Silicon-Via (TSV)
Authors: Kelly Michael , Reed Rick 
Published: October 2015

Through-silicon-via (TSV) package construction offers several silicon integration advantages that are being validated by leading technology providers. This paper will describe a System in Package (SiP) design utilizing two functional system-on-chip (SoC) ARM dual-core Cortex-A9 processors connected across a 2.5D silicon interposer. The test vehicle was designed to demonstrate high speed and high bandwidth communication between multiple chips. The two logic chips were designed by Open Silicon, Inc. and fabricated by GLOBALFOUNDRIES on their 28nm-SLP (Super Low Power) process technology. GLOBALFOUNDRIES also fabricated the 2.5D interposer using their 65nm manufacturing flow. Amkor Technology provided the final assembly utilizing advanced TSV packaging technologies such as copper pillar bumping and mass reflow bonding.
This is a pivotal demonstration of the heterogeneous die integration approach. A silicon process node or package interconnect density can either preserve or limit inter-chip communication when comparing SoC versus SiP approaches. Connecting two dual-core Cortex-A9 processors within a single package illustrated the expansion of function through multiple die. The test vehicle also implies that a large IC can be re-architected into smaller constituents to increase yield or design flexibility. By utilizing the best technology node for price and performance, 2.5D packaging can lower overall system cost of ownership or conversely, can expand overall performance through multiple high performance ICs.
Chip designers are facing increased complexity and higher costs in order to move to smaller IC geometries and the adoption of 2.5D TSV technology will increase the options of construction (one vs. multiple die/SoCs). Having the flexibility to design with one or multiple die while maintaining high performance levels can offset the real estate costs of advanced nodes, permit silicon die reuse, improve yield and decrease overall product risk. The designer must choose the most appropriate silicon and assembly processes that satisfy the needs of each of the major functions in the overall system.
Amkor's assembly process for this key product construction has been demonstrated on a range of products for the communications, graphics and the mobile markets. Process flexibility has been a key factor in addressing different markets and package complexity.
How to bring 3D IC to Maturity: Example of a pacemaker
Authors: DAL MOLIN Renzo 
Published: October 2015

3D IC wafer level stacking raises the issue of yield and consequently cost.
If 4 levels of wafers are stacked and if the yield of each level is 95%, the global yield is expected to be 81%.
If 4 levels of wafers are stacked and if the yield of each level level is 90%, the global yield is expected to be 65%.
If 4 levels of wafers are stacked and if the yield of each level level is 85%, the global yield is expected to be 52%.
These numbers show that 3D IC stacking needs to increase the yield of each stacked level in order to get acceptable industrial yield.
One way to solve this issue is to use reconstructed wafers with known good dies.
We will give one example of a realized 4 level wafer stacking for an implantable pacemaker.
A second approach is to implement redundancies in each chip stacked in order to implement repair strategy. We will present this design strategy in some particular cases and mainly depending on the source of defects.
Another issue to solve when performing 3D IC stacking is the crosstalks specifically for analog circuits. We will present how we performed the capacitor extraction between interconnections in 3D for the pacemaker.
Finally we will compare the 2.5D with embedded PCB versus 3D IC on PCB stacking in terms of size and cost for a pacemaker.
Optimized TSV Module for High Performance 2.5D Device Packaging
Authors: Uzoh Cyprian , Wang Liang , Sun Zhuowen , Cao Andrew , Lee Bong-Sub , Gao Guilian , Shen Hong , Arkalgud Sitaram 
Published: October 2015

3D-IC has been increasingly adopted by the industry owing to its promise of higher device speed and package bandwidth, improved power consumption, reduced form factor, and lower cost for important applications over a wide range of industrial segments including image sensors, logic-memory and logic-logic integration, MEMS, integrated optical interposers and LEDs.
This presentation is a systematic study of multiple experimental factors affecting the electrical performance, reliability and scalability of TSVs. Electrical modeling and simulation was used to determine the key factors influencing singal transmission and return losses in TSVs at high (&gt;1 GHz) frequencies. A variety of process modules and steps for the fabrication of through silicon vias were then systematically optimized to ensure high performance. The modules evaluated include TSV etch, TSV fill, chemical mechanical polishing (CMP), pad finish, bonding schemes, wafer thinning, via reveal, passivation, wiring and bumping. One example is the improvement of TSV profile and sidewall roughness through the optimization of DRIE parameters and wet chemical methods to reduce silicon sidewall roughness from that of a typical Bosch etch to less than 10nm which is critical for adhesion of barrier/seed layer and the final reliability of 2.5D packaging. Scalability of void-free via fill process with respect to TSV diameter and depth was addressed by using highly conformal barrier layers. Adhesion of Cu to the barrier layer was also improved upon detailed analysis to prevent delamination and improve reliability. A bottom up plating chemistry with significantly low impurity content was utilized to mitigate voids, seams and excessive overburden in the TSV. Its impact on stress and delamination issues and subsequent reliability failures was studied in details. The annealing process following TSV formation is systematically studied with varying conditions and characterized with metrology and electrical tests to investigate its effect on microstructure and material properties. The process parameters were tuned for CMP of Cu, adhesion and barrier layer without causing corrosion or delamination between adjacent layers. Process requirements for these modules in TSV process are closely related. This presentation will review the process module development in the context of their effects on the integrated TSV parameters (performance, reliability and scalability). We will also provide an in-depth discussion on process module optimization, electrical and mechanical characterization and cost reduction methodologies.
Solderability Challenges in Emerging BGA Packages
Authors: Durham Maria , Liu Yan , Mackie Andy 
Published: October 2015

The final step of reflowing solder spheres to solderable pads on the bottom of substrates in FCBGA, CSP, and WLCSP packages is often considered to be a trivial step. However, with the increasing complexity and number of assembly processes taken prior to this final soldering step, the formation of a reliable final joint is far from certain. In order to eliminate this problem, many OSATs and ODMs are adopting the non-value-added process of prefluxing, reflowing, cleaning, and drying substrates immediately prior to the final ball-attach process.
This paper details the sequence of processes seen in typical BGA assembly, and examines the effects of each set of prior processes on the solderability of the final pad. It also details investigations of the solderable surface and metallurgy of the substrate pad.
The introduction of a “one-step” pin-transfer ball-attach flux is shown to be a means of reducing both process cost and time, and also reducing the risk of significant warpage in the finished package.
Direct EP/EPAG - Ultrathin Surface Finish for Soldering and Wire Bonding
Authors: Oezkoek Mustafa , RamosArnd Gustavo , Wegricht KilianJens 
Published: October 2015

New challenges in the industry, new technical requirements, as well as cost and environmental regulations, require a constant search for alternative manufacturing solutions for the electronic packaging industry. Finer lines and spaces, higher frequencies, improved solder joint reliability and new challenges in wire bonding – both with existing wire technology such as Al and Au or novel types such as Cu or Cu-Pd – are just a few examples of technological advancements for surface finishes in the packaging industry. Additionally, the reduction and elimination of toxic and hazardous materials, as well as the drive to further reduce the manufacturing costs, are important requirements which has to be addressed.
The new direct pure EP/EPAG surface finish is suggested as a solution to these challenges for the future. The direct EP/EPAG process allows the direct deposition of palladium on copper, without using any nickel. It is suitable for high frequency, for flexible applications, for gold, aluminum, gold, silver and copper wire bonding applications. The process proves superior solder joint strength for lead free and eutectic soldering and is compatible with many new base materials and soldermask types owing to its short deposit time and low temperature needs. Finally, the EP/EPAG process operates at a thickness of less than 300 nm, ideal for very fine lines and spaces. The EP/EPAG finish also features several environmental benefits, such as less water and energy consumption owing to reduced process steps and line lengths.
The suggested paper will provide new wire bond data with silver, gold and copper wire bonding results. A technical comparison to a thin ENEPIG finish will be provided to show the differences in terms of soldering and solder joint reliability.
Next Generation Electrochemical Deposition TSV Fill
Authors: Kim Bioh , Golovato Stephen , Barbera Tyler , Fujita Keiichi , Tanaka Takashi 
Published: October 2015

The first generation of through silicon via (TSV) designs for interposer and 3D die stacking has concentrated on TSV features with aspect ratio (AR) on the order of ten. Typical via sizes are 10 X 100 um for interposer and 5 X 50 um for 3D applications. Ionized physical vapor deposition (IPVD) has been successful in depositing barrier and seed layers in these AR=10 vias that allow efficient “bottom-up” filling by electrochemical deposition (ECD) using available chemistries. While these applications are currently moving to pilot lines and low scale production, research and development has already begun on the next generation of TSV structures for interposer and die stacking. These may be based on via middle or via last designs. They are expected to increase in aspect ratio for denser TSV arrays while maintaining similar wafer thickness. Structures with AR in the range of 15–20 are being designed and produced. For interposer, a typical structure might be 8 X 120 um and 2 X 40 um for 3D stacks. These structures will challenge all TSV formation processes, including etch, dielectric liner deposition, barrier-seed deposition and TSV fill.
This paper will focus on barrier-seed and TSV fill processes. IPVD barrier-seed deposition will be difficult for AR~15–20 and will require much longer deposition times for complete via coverage. Long IPVD times will produce thick overburden and pinch off the opening at the top of vias. Even if successful, IPVD may not be viable economically. More conformal deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD) and wet processes, like electro-less plating and conformal ECD, may be better alternatives to IPVD. A conformal process only needs to deposit the minimum required seed thickness in the via for successful ECD filling with the overburden being nearly the same thickness. The development of a successful conformal barrier-seed process may even challenge IPVD for AR=10. This paper presents ECD TSV fill results using several conformal barrier-seed processes, demonstrating the feasibility of this approach for structures with AR = 10–20.