bluuebunny/crossref_metadata_2025_split huggingface dataset:
Adhesive Enabling Technology for Direct Metal Deposition on Molding Resin
Authors: Mukai Kenichiroh , Kim Kwonil , Eastep Brian , Gaherty Lee , Kashyap Anirudh , Brandt Lutz 
Published: October 2015

Plating on molding resin is a relatively new field with many possible applications. One possible application is magnetic or electrical EMI shielding of active components. This is currently done mostly by metallic shells or “caps”. However, this technique also increases spatial requirements and reduces flexibility with respect to component layout on the PCB.
An alternative and more space saving approach is plated EMI shielding. While sputtering a metallic seed layer in preparation of plating is feasible – this process step is not very cost effective or suitable for mass production. In this respect, classical electroless metallization would be much more desirable but has been so far limited by insufficient adhesion.
In this paper we will present a new approach, where components encased by molding resin are directly coated with an electroless copper or nickel layer using an adhesion promoter. By this method spatial requirements are minimized. Also, this process fits into the existing infrastructure within the PCB industry.
Due to the extremely high filler content (70-90% wt.) and the wide size distribution (from tens of nm to tens of μm) of fillers, classical Desmear followed by electroless seeding can get a maximum adhesion of only 2-3N/cm. In contrast, with chemical bonding adhesion promoters as presented in this paper, we are able to get up to 5N/cm of peel strength. The plated layer stands up well to reflow shock (260C) and HAST without delamination or significant loss of adhesion – key requirements for this application.
These adhesion promoters are applicable to various kinds of molding resins. Extending this technology to embedded components can be another far reaching application.
Highly tunable Mn-doped PZT thin films for integrated RF devices
Authors: Benhadjala Warda , Sonnerat Florence , Guillaume Jennifer , Dieppedale Christel , Renaux Philippe , Le Rhun Gwenaël , Sibuet Henri , Billard Christophe 
Published: October 2015

Modern RF systems have triggered an important and urgent demand for inexpensive voltage controlled capacitors used for a wide range of applications such as tunable antennas or low-noise voltage-controlled oscillators (VCO). Ferroelectric materials have received considerable interest for electrically tunable dielectrics due to their high dielectric constant and large dielectric nonlinearity under dc bias field. Lead zirconate titanate (PZT) ceramics which have been under intense investigation for various industrial domains including micro-electro-mechanical systems (MEMS), non-volatile memories, and high-k capacitors, are especially well-known candidate materials due to their unequalled ferroelectric properties and stability in device operating ranges. However, reported voltage tunability of PZT films is relatively low (~35%@4GHz) and remains insufficient for microwave tunable devices. Therefore, much attention has been focused on the PZT modification by adding a small amount of dopants. Shao et al., studied strontium-doped PZT (PSZT) thin films and achieved a tunability of 48% @1MHz. More recently, Hu et al. reported a tunability of 65%@10kHz for lanthanum-modified PZT (PLZT) films. In the presented study, effect of manganese (Mn) doping on electrical properties of PZT (PMZT) thin films has been investigated.
Metal/insulator/metal (MIM) capacitors using PZT-based thin films and ruthenium (Ru) top electrodes were processed on platinized (Pt) silicon wafers by a sol gel method. Dielectric properties of PMZT thin films were studied by varying the dopant amount and compared to those of pure PZT layers. At this end, on-wafer electrical measurements were conducted with a particular attention on leakage current characterization and RF measurements under DC bias voltage. We have shown that leakage current density decreased from 6.5 μA/cm2 to 1 μA/cm2 at 850kV/cm by doping PZT with Mn. Observed conduction mechanisms will be discussed in detail in the full-length paper. Moreover, developed PZT-based thin films exhibit high dielectric strengths achieving 2.1MV/cm and outstanding tunability as high as 85% (~7:1) @1GHz at bias voltage of 20V. Thus, PMZT tunability is among the highest ones reported in the literature for PZT-derived thin films but also for other piezoelectric materials. Indeed, in comparison, the tunability of BST-based materials, typically studied for voltage tunable applications, does not exceed 5:1. These remarkable results indicate that Mn-doped PZT thin films are promising candidates for RF tunable capacitors.
A Module-on-module Manufacturing Process and the Study of its Warpage and Signal Integrity
Authors: Wang Thomas , Lin James , Cheng Tony , Hong Ping-Chi , Lin Albert , Chang Harrison 
Published: October 2015

This paper describes a package design and associated manufacturing assembly process that stack a module on top of another module using a frame board. The module on the top could be in molded or open frame form. In addition, this manufacturing process is compatible with the conformal shielding process important in RF applications. The complete module-on-module can be coated seamlessly and connected to the ground planes of the two substrates.
The module may be a part of product line that requires more functionality over the same foot print. There is the need to houses more components than its predecessor. Such example includes the standard memory package-on-package. However, if the module on top is not of commodity type, or when the volume is not big enough to develop a standard package, this module-on-module architecture and process could be a good solution. Alternatively, one could fix the design of bottom module , and design multiple choices of the top module. When stacked together, the two modules form various different configurations in order to serve different functionalities.
The structure of the module on module is shown in figure 1 below:
Figure 1 Structure of the Module on Module
On the frame board, there are vertical via where vertical electrical and power connection can be made. The frame board is mounted on the main board-II by surface mount process with underfill option. In the figure, a molded module on the top is shown, and an overall coating is applied to the whole module-on-module.
Figure 2 Manufacturing Process of the Module-on-module
The assembly process of the module-on-module is shown in Figure 2. First, the bottom module is manufactured by a one side SMT process and sawed, with the frame board soldered and underfilled. Then, the top module is SMT and molded in a panel form on the one side, and the bottom module is SMT and underfilled on the other side. Last, the complete module is sawed and conformal shielded by the sputtering process. The design of the ground plans of the substrates, together with that of the frame board, makes it such that the coating is connected to the ground planes of the boards.
It is important to study the warpage of such a module-on-module to make sure that it meets the JDEC standards. It is important to assure that the signal integrity of the electrical connections, including RF connections, inside of the frame board meets the requirement. Both simulation and measurement are made to test vehicles of the module-on-module. It is found that the simulation matches the measurement nicely. This module structure can be used for a variety of applications.
Ultralow Residue (ULR) Semiconductor Grade Fluxes for Flip-Chip and MEMs Applications
Authors: Durham Maria , Lim SzePei , Chou Jason , Mackie Andy 
Published: October 2015

Copper pillars topped with solder microbumps are emerging as a standard flip-chip solder bump replacement in the semiconductor assembly industry. The relentless drive towards finer pitch, combined with reduced copper pillar height, makes aqueous cleaning of flip-chip flux residues more difficult. An emergent failure mode is joint damage and subsequent yield loss during aqueous jet impingement.
The move towards semiconductor grade ultralow residue no-clean fluxes and away from cleaning processes is therefore inevitable for both flip-chip and MEMS applications to meet industry roadmap challenges. The low residue also optimizes underfill adhesion and decreases possible outgassing during underfill cure. This paper discusses the variety of new and emerging failure modes for new packing processes using thinned die with copper-pillar/microbumps. The testing of assembly materials for this purpose will also be discussed.
A Microcontroller Approach to Measuring Transmissibility of MEMS Devices
Authors: Li Chong , Wu Yixuan , Yang Haoyue , Jenkins Luke L. , Dean Robert N. , Flowers George T. 
Published: October 2015

The transmissibility reveals two very useful characteristics of a micro-electro-mechanical systems (MEMS) device, the resonant frequency and the mechanical quality factor. Real time knowledge on these two important factors can enhance application performance or avoid potential problems from environmental disturbances due to fabrication tolerances and the resulting operational differences in otherwise identical devices. Expensive laboratory equipment is typically used to measure the transmissibility. However, these test systems are not readily adaptable to field use. Therefore, it is important to be able to measure the transmissibility using a real time technique with a simplified test setup. This study proposes a technique that can compute the transmissibility in real time using a low cost microcontroller.
This technique utilizes two laser vibrometers to detect the input and output motions of the proof mass in a MEMS device, which are fed to high speed 500 KHz analog to digital converters (ADC) in the microcontroller. A filtering step is performed to decrease noise. After the sampling and pre-filtering, a Fast Fourier Transform (FFT) is performed to convert the time-domain signals to frequency domain signals. The amplitude of the output signal at each frequency is divided by the amplitude of the corresponding input signal at each frequency to obtain the transmissibility. To overcome the difficulties resulting from measurement and quantization noise, a recursive calculating algorithm and a de-quantization filter are introduced. The recursive calculating process guarantees that the system updates the results continually, which results in a transmissibility plot covering the entire bandwidth. The de-quantization filter considers the validity of the data and performs the transmissibility division step accordingly.
A cantilevered structure was chosen as the device-under-test to verify and evaluate this technique. The cantilevered device was attached to an electromechanical shaker system for vibratory stimulation. Two laser vibrometers were used to detect the input and output motion and this data was fed into a microcontroller. The microcontroller was STM32F407, which is 32-bit and 168 MHz controller. The tests demonstrated that this technique can measure the transmissibility and therefore the resonant frequency and mechanical quality factor accurately compared to a professional signal analyzer.
The Future of Maximum CAD/CAM Automation for Ceramic Hybrids
Authors: Sovinsky John , Sylvester Geoff 
Published: October 2015

New concepts developed maximize CAD/CAM automation for all types of Ceramic Hybrids including Thick Film, Thin Film, LTCC and HTCC. Designs can go quickly from concept to manufactured product, which will fuel more progress to bring a largely manual process to maximum automation, to include automatic masks, panels and generation of 3D analysis models. Maximum automation results in expanded use of technologies that are now shrinking. Technologies that have complex and difficult to understand design and manufacturing steps have a hard time gaining wide acceptance.
CDS is tackling this complex challenge and is designing and implementing the following processes to solve the most difficult CAD/CAM problems:1. Be a true CAM tool that reads in designs from any other EDA (layout) system. Y2. Run all possible DRC checks necessary for high fabrication and assembly yield. Y3. Make all manufacturing masks automatically from very basic designs by using settings in an automatically configurable table. Y4. Panelize all types of Ceramic designs in preparation for manufacturing. Y5. Generate documentation automatically through from stored configuration files. D6. In LTCC and HTCC, place cavity punches (nibbles and rubs) automatically and feed correct machine data to the punch machine. Y7. Export resistor trimming data directly to the laser trimming machine. F8. Feed flying probe test data directly to the flying probe tester. D9. Automatically make a 3D Image and export ACIS or STEP for thermal analysis. D10. Export data directly to all electrical analysis and thermal analysis tools. P11. Support circuit fabrication non-planar surfaces. F12. Make full 3D analysis models of circuits non-planar surfaces. FThe purpose of this paper is to define what is required for the Ceramic Hybrid industry to realize full automation in design, checking and output to manufacturing. Your ideas are welcome.
Electroless Nickel and Au Plated Silver LTCC Solution for Advanced Hermetic Packages
Authors: Ross David , Mitchell Greg , Draney Nathan , Gay Simon , Curley Michael 
Published: October 2015

Low Temperature Cofired Ceramics (LTCC) for military and medical applications requires high reliability interconnects that have been traditionally met using cermet Au metallization But due to the rising cost of Au, it has become cost prohibitive in some applications to tier 1 defense contractors. The utilization of Silver cermet metallization reduces the costs of LTCC up to 50%, however requires proper coverage using either a Mixed Metal, or a Nickel (Ni) and Au (Au) Plated surface. Efforts to date on mixed metal solutions with resistive PdAg or PtAg transitions without Kirkendahl voiding have been unreliable for systems requiring post fire metallizations due to voiding at the silver to Au transition. Anaren Ceramics has developed an all Silver LTCC solution that utilizes Electroless Ni and Au (ENiG) plating, lowering the cost of entry for LTCC users up to 50%.
Anaren Ceramics has developed a proprietary plating process for the DuPont 951 LTCC [1] tape material and silver metallization which meet the needs of high reliability, high cavity count LTCC packages that are fully solderable using PbSn, or AuSn materials for hermetic applications. The Anaren Ceramics solution meets Mil Std 883 test requirements and this paper will discuss the test results for plated LTCC substrates and AuSn brazed LTCC assemblies that include 350°C Bake Test, Tape Peel, X Ray Inspection, Open Header Leak Rate, Moisture under Bias, Salt Atmosphere, Die Shear, and Wire Bond.
Evaluation of Direct Bond Aluminum Substrates for Power Electronic Applications in Extreme Environments
Authors: Patterson Brian , Kulkarni Srikanth , Elshabini Aicha , Barlow Fred 
Published: October 2015

Power packages that require large current capacities typically employ some form of thick conductive traces attached to a thermally conductive ceramic material to create a suitable package substrate. The most common substrate currently used in high power applications is Direct Bonded Copper (DBC). Though this is a well established, reliable, and commonly used substrate, DBC suffers from poor long term mechanical reliability when exposed to extreme temperature excursions. In an attempt to improve on this technology, substrate materials such as Active Metal Bond / Braze (AMB) and Direct Bonded Aluminum (DBA) are being investigated.
Previous work has shown that the accelerated aging / thermal shock lifetimes of DBC and AMB are significantly shorter than that of DBA substrates. Though DBA substrates last longer, they still have some issues that require attention before it can be accepted as an improved alternative to DBC substrates in these types of applications. The main issues that have been observed are DBA's increase in surface roughness during aging and aluminum's poor solderability when compared to copper or nickel.
The emphasis of this paper is to investigate the dramatic increase in DBA's surface roughness and its' possible causes due to thermal cycling as well as present a thermal cycling lifetime comparison of the three different substrate. To evaluate this, a DBA sample with one side raw aluminum and one side electroless nickel plated (high phosphorous) was thermally shocked from −40°C to 200°C with surface roughness measurements preformed every 300 cycles. Another batch of samples was thermally shocked to 6000 cycles and lifetimes were compared. One nickel plated DBA sample shocked to 4000 cycles was cross-sectioned and analyzed with SEM and EDAX to evaluate any changes in the metal. The grain structure of a thermally cycled sample was also examined with a Scanning Electron Microscope (SEM).
Inkjet Printing as Technology for In-Situ Blending of Thick-Film Resistor Inks
Authors: Waßmer Marcel , Diel Waldemar , Krüger Klaus 
Published: October 2015

The integration of passive components directly into circuit boards is an efficient alternative to surface mounted devices. Digital printing methods are more and more emerging technologies for the fabrication of microelectronic circuits. Inkjet printing is a technology for the deposition of a variety of particles with the unique selling proposition of in-situ ink blending.
Resistors are one of the most frequently required passive components in electronic circuits. In LTCC technology the integration and additionally the embedding of resistors promises new applications. Integrated resistors are usually screen printed. Inkjet printing has several advantages to compete seriously with screen printing as production method. This study investigates the opportunities of in-situ blending in inkjet printing of thick-film resistors. In a first step, the different options of ink blending are analyzed theoretically. In order to have a basis for further calculations five compositions with a wide resistivity range are printed purely. Afterwards the printed resistors are passed through a post-fire process and the electrical properties are recorded. Reliability and long term stability in drop formation are fundamental for production process.
In a second step, the different options of ink blending are analyzed. The five compositions are blended to four combinations of neighbouring inks and are printed and blended with two inkjet printheads. The effect of blending is characterized towards the change in electrical behaviour and the different blending techniques are compared. Additionally, the opportunity of layer thickness variations is investigated and its influence is analyzed. Further, the influences of printing conditions on morphology and resistivity are discussed.
Recent progress in the shaping and sintering of barium titanate nanoparticles. Application to high permittivity capacitors
Authors: Guillemet-Fritsch Sophie , Voisin Christophe , Quintero Roman Nava , Dufour Pascal , Tenailleau Christophe , Garib Juan Antonio Aguilar , Melo Martin Edgar Reyes , Durand Bernard 
Published: October 2015

The miniaturisation of electronic components required for many devices involves an increase their volumic efficiency. This work focus on the size reduction of capacitors. They are two ways for increasing the capacity of such passive components. One is to find materials with high permittivity, the other is to reduce the thickness of the films used in multilayers ceramics.
Barium titanate, BaTiO3 (BT) nanoparticles were sintered using Spark Plasma Sintering (SPS) because the material presents interesting properties when obtained by SPS [1–3]. In this case, very unusual interesting dielectric properties, a so called “colossal” permittivity value up to several thousands. Moreover, no temperature dependence is observed. However, the values of dielectric losses are too high to consider industrial applications. In order to reduce these dielectric losses, different approaches have been proposed to control the chemistry of grain boundaries. We present here the structural, microstructural and electrical properties of ceramics sintered by SPS from BaTiO3 powders elaborated by co-precipitation method. Different routes tested to improve the dielectric properties of the ceramics are presented and discussed.
On the other side, thick films of BT have been prepared. The objective of this work was to develop a BaTiO3 material having an accurate particle size to reduce the thickness of sintered films down to 1 μm. The rheological properties of the slurry have been optimized and, thanks to a suitable tape casting process, homogeneous thin films of 1 μm thickness could be obtained. Some properties of the films are described.
Realisation of Large Cavities in Multilayer Ceramics by Cold Low Pressure Lamination and Their Characterisation by μCT
Authors: Deisinger Ulrike , Fey Tobias , Roosen Andreas 
Published: October 2015

In microelectronics the ceramic multilayer technology is frequently used as it allows a precise and yet flexible production of MEMS, microelectronic devices, micro reactors or devices for micro fluidics. During production of those multilayer structures the single layers are typically laminated by thermo-compression. However, large cavities cannot be realised using thermo-compression without adding sacrificial fillings. In contrast, the cold low pressure lamination (CLPL) technique allows lamination at room temperature without applying a high pressure. As in this lamination technique no mass flow occurs, internal cavities are not destroyed during the lamination step.
In this study, commercially available LTCC green tapes were structured using a milling plotter with a high frequency spindle. Different process parameters (milling speed, spindle frequency) were evaluated regarding the accuracy of shape and quality of the channel edge. Channels with various dimensions (2.5 - 15 mm width and 30 mm length) were milled into the green tapes. Subsequently, the green tapes were laminated using the CLPL technique. With CLPL adjacent ceramic green tapes are joined by a double sided adhesive tape, which is applied by a soft roller. By alternately applying green (structured or unstructured) and adhesive tapes multilayer structures with internal cavities are formed. For characterisation of the sintered LTCC structures μCT (computed tomography) was used to analyse the internal structure without destroying the sample. Influence of sintering regime on deformation was evaluated. It was shown that milling of green tapes in combination with CLPL is a suitable method to fabricate internal cavities in LTCC multilayer structures.