bluuebunny/crossref_metadata_2025_split huggingface dataset:
Diatom-based Sensors: Organic/Inorganic Interfaces and Health Science Application
Authors: Goryll Michael , Wang Xiaofeng , Ramakrishnan Shankar , Lin Kai-Chun , Rege Kaushal , Dey Sandwip , Ramakrishna B. L. 
Published: October 2015

Nanopore membranes exhibit tremendous potential for applications such as molecular filtration and DNA sequencng studies. However, the large-scale manufacturing of these nanopore membranes using MEMS technology is challenging, requiring slow serial electron or ion-beam patterning. Marine diatoms on the other hand feature biomineralized silica shells with the smallest pore diameters being 40 nm. Their hierarchical pore architecture makes these nanomembranes exceptionally mechanically stable. Moreover, the nanopores are homogeneous in size and have a low aspect ratio, enabling fast diffusion-driven transport.
The drawback of the biomineralized structures is that they are single entities, which have to be combined with a support structure to integrate them into a microsystem. Our solution consists of immobilizing the biomineralized structures on silicon substrates. With the diatom shells growing up to 200 μm in diameter, they are easy to manipulate on the oxidized silicon surface. Through-wafer via holes with diameters between 5 μm and 30 μm were etched using a dry etching technique to allow free access to the bottom of the immobilized diatom shell. Two pathways towards immobilization of the diatom shells were used, one being a chemical linkage approach using poly-L-lysine and the other involving UV-polymerizable epoxy. Controlled etching of the silica structure has been employed to manipulate both the dimensions of the nanopores as well as the pore hierarchy.
Studies of transport phenomena were carried out after mounting the silicon chip in a fluidic chamber with reservoirs for aqueous solution on either side of the chip. Electrical contact was made via Ag/AgCl electrodes and the transmembrane current was measured by a transimpedance amplifier. Results on our transport studies based on size and chemical considerations will be presented for ions, such as potassium and sodium, present in physiologically relevant isotonic buffers, polystyrene nanobeads and gold nanoparticles.
Realization of Power Modules by Chip Embedding Technology
Authors: Boettcher Lars , Manessis D. , Karaszkiewicz S. , Ostmann A. 
Published: October 2015

The continuous miniaturization of silicon dies and the need for a further package size reduction, with an equal or better performance and reduced manufacturing cost, are the main drivers for new packaging concepts. The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies.
This paper will briefly discuss the necessary process steps of the embedded chip technology, which is based on printed circuit board manufacturing processes, and will also demonstrate the transfer of the technology from a smaller size lab scale equipment environment to an industrial comparable process line, capable of processing large panel formats up to 18” x 24”. The paper will also briefly describe this development and categorize today's embedding technologies.
First modules with embedded chips are in production in Asia, mainly for telecom and computer applications. In Europe embedding has gained a strong interest for power modules, especially in automotive applications. Main drivers are the capability for compact and thin packaging, the high reliability and cost saving potential.
In a number of European cooperation projects with partners from industry and research, embedding of power chips, like IGBTS and power MOSFET, is of high interest. In this paper current achievements of these projects will be shown, especially examples of realized devices and their characteristics. The dominating technology for power chip embedding is a face-up technology. Chips are bonded with their backside (drain contact) to a Cu substrate using highly conductive adhesive or solder. Using the face up assembly, a direct contact to the backside of the die is possible, allowing a lot of benefits for driving high currents and applying an efficient thermal management for the power devices. Then Chips are embedded by vacuum lamination of prepreg or RCC (resin coated copper) layers. Via holes to the top contacts (gate and source) are formed by laser drilling. The vias are metallized using conventional Cu plating. Finally conductor structures are etched in the top Cu layer, finalizing the circuit. Details will be given about device manufacturing, related yield issues and strategies to overcome them.
Finally scenarios for the implementation of embedding technology and concepts for future applications will be discussed.
Solutions for Wafer-Level Packaging of High Brightness LEDs
Authors: Uhrmann Thomas , Kim B. , Matthias T. , Lindner P. 
Published: October 2015

High brightness LEDs (HB-LEDs) carry a high prospect for general lighting applications. Competing with the cost/performance ratio of current light sources demands an increase of the overall efficiency as well as the reduction of the device cost.
Since packaging accounts for 30%–50% of the cost of HB LED manufacturing, moving from die- level to wafer-level processes is one likely potential solution for reducing cost per lumen. Silicon-based WLP, using the established processing technology of the MEMS and IC industry, offers high fabrication reliability, high yield and the direct integration of the driver IC in the package. The already small form factor of WLP can be further reduced using Through-Silicon-Vias (TSV), increasing the maximum amount of chips per wafer. Silicon WLP also offers superior thermal management, with the relatively high thermal conductance of silicon. Redistributing LED dies on silicon wafer submounts, with metal bonding and copper TSVs, further improves the heat conductance away from the active region of the chip, resulting in increased device performance. Wafer-level optics can further improve performance and reduce packaging costs.
Wafer-level lens molding based on imprint lithography is in high volume manufacture for cell phone camera modules. It allows creation of spherical and a-spherical lenses as well as lens stacks with minimized form factor. In contrast to the currently applied drop dispensing technique for LED lens fabrication, the shape of the lens can be accurately tailored and the decrease of the lens size results in lower absorption and higher light output.
Most of these technologies are already in high volume production in other sectors. We will discuss the field proven solutions at each process step, from the formation of the silicon interposer, through the chip-to-wafer bonding, to the final imprinting of the wafer-level optics.
Packaging of High Brightness, Big-Chip LEDs
Authors: Lee Lidia , Panaccione Paul 
Published: October 2015

A common approach for designing HB-LEDs into a variety of lighting systems is to arrange an array of many emitters over a large area in order to provide the required photometric flux. In certain applications, this common approach of arraying a large number of small chip LEDs introduces a number of challenges that can be solved by using a single package of big-chip LEDs with enough light output to meet the system requirements. This presentation will discuss package design for big-chip LEDs, compared to an array of many small emitter packages.
In addition to big-chip package design, the impact on system design including optics, drivers, thermals, reliability, and form factor will be addressed. For illustration, a reference example will be presented in detail, consisting of an easy to use plug and play single package with 36mm2 of emitting area capable of up to 6000 lumens.
Formulation of Percolating Thermal Underfill by Sequential Convective Gap Filling
Authors: Brunschwiler T. , Goicochea J. , Wolf H. , Kuemin C. , Michel B. 
Published: October 2015

In 3D chip stacks, heat dissipation through wiring layers and the bonding interface contributes to the total temperature gradient. The effective thermal impedance of micro solder-ball arrays filled with a poorly-conducting silica underfill can be as high as 30 K*mm2/W, three times the value of a thermal grease interface. Efforts to improve the underfill conductivity to 5 W/(m*K) are underway, which would translate into in a significant interface-resistance reduction.
To achieve thermal conductivities &gt;1 W/(m*K), alumina particles were introduced in capillary underfills at particle loadings above the percolation threshold, but at these loading levels the high viscosity of the resulting underfill no longer permits capillary filling.
We propose a novel sequential gap-filling method. Particles are suspended in a carrier fluid at a low concentration (0.1 vol%). Using forced convection, the suspension is injected into the cavity formed between the IC dies by the C4 array. A filter element at the cavity outlet triggers particle accumulation in the cavity. The particles form a percolation network with an effective thermal conductivity of &gt;1 W/(m*K). Next an evaporation step removes the carrier fluid, and the exposed pores between the particles are refilled with a particle-free adhesive using capillary forces. Finally, the matrix is cured at 65 °C.
10x10 mm2 standard and micro-C4 cavities (&gt;30 μm) can be completely filled in 2 min at 0.2 bar, resulting in a homogeneous volumetric fill of 36%. Percolation was identified by SEM inspection. For the micro-C4 arrays filler particles of &lt; 10 μm were used. Uniform particle filling is precluded because of the longer filling time due to the small pore sizes. Particle trapping sites are introduced to form local stacks that provide an additional drainage network to guarantee acceptable filling times. Effective thermal-conductivity values of the percolating thermal underfill method proposed here are reported.
A Novel Frequency Addressable Micro Switch Array
Authors: Wang Minfeng , Zhang Yang , Li G. P. , Bachman Mark 
Published: October 2015

Addressable switch arrays are widely used in telecommunication, radar and satellite systems for many applications, such as switch network controlling, modularity and expansion. The existing method to achieve addressability of the switch is to design a grid structure switch array and to individually actuate switches with multiplexed control lines , . The MEMS switch array presented in this work addresses individual switches according to the unique intrinsic resonance frequencies of different mechanical structures driven by electro-magnetic force. This approach eliminates the need to have a dedicated control line for each switch, which readily enables the switch array with minimal complexity of control line design thus minimizes the overall footprint.
The frequency addressable switch array (FASA) is fabricated directly on printed circuit boards using patented laminate MEMS technology.
Instead of building everything bottom-up, three layers including top cantilever structure, middle spacer, bottom electrode and coils are fabricated separately through different processes and later laminated together. The switches are electro-magnetically actuated at operation voltage (~1V), which is much lower than the one of the conventional electrostatic actuation (&gt;30V) . Alternating electro-magnetic force is exerted on a mini neodymium magnet by a series of coils. Only when the maximum vibration stroke is obtained at the resonant frequency of individual switch, the mini magnet mounted on the top cantilever will make contact with the bottom electrode for signal transmission. The quality factors of the switches were measured to be nearly 100 with air damping. The related switch density (defined by the number of the switches per kHz in desired frequency range for individual addressing) in the array is around 10 per kHz. By improving the quality factor of the switch such as hermetic packaging avoiding the air damping, a high value (&gt;200 per kHz) of the switch density is expected.
Flip-Chip Technologies, Applications, Market Status and Forecasts
Authors: Zinck Christophe , Yannou Jean-Marc , Baron Jérôme , Garou Phil 
Published: October 2015

Renewed interest in flip-chip technologies in concurrently motivated in many application areas by such factors as the rising cost of gold used for wire bonding, the need for low thickness devices, continued CMOS downscaling, higher currents and temperatures, and lower voltages.
Today, many sophisticated devices can no longer be packaged with wire bonding technology and the mobile applications are more and more requiring footprint and weight reduction coupled with higher electrical performances (signal propagation and power distribution). The emergence of the 28nm CMOS technology node in particular, poses new quality and reliability constraints on interconnect technologies so as to cope with the increasing fragility of the back end of line, which may disqualify wire bonding for good. Not to mention the ever increasing IO density, making it necessary to develop new bumping and substrate technologies. It is not any longer only about higher performance and lower cost reliable interconnect, assembly and packaging technologies: if remained unresolved, the above constraints will prove to be bottlenecks if not obstacles to the continuation of Moore's law.
In this presentation, we will first focus on Flip-Chip technologies and their evolution. We will present the main players, their facilities and technologies. We will sketch a worldwide roadmap of flip-chip featuring such varied applications as wireless digital, PC processors, RF and power devices. We will then present our market forecasts and explain how we see these innovations will modify the market of packaging interconnections and assembly in the years to come.
Escalating Challenges in Developing Complex Solutions for Next Generation Package and Interconnect Technologies
Authors: Darveaux Robert 
Published: October 2015

There are several application and device trends driving IC package development today. Among the most prevalent are:- Form factor reduction for handheld devices- Increased functionality requiring higher bandwidth- Higher power dissipation- Higher operating frequencies resulting in reduced electrical noise margins- Increased use of sensors- Full conversion to green material sets- Silicon node progression.
These trends occur concurrently in many applications, which often results in conflicting requirements. In addition, the market continues to apply relentless pricing pressure on the supply chain. Hence, simple, cost-effective solutions are mandatory. This presentation will highlight packaging technology developments that address the device and application trends listed above. Several innovative packaging platforms will be discussed:- Copper pillar CSP and BGA- Through Mold Via Package on Package (TMV ® PoP)- Flip Chip Molded BGA (FCMBGA)- Wafer Level CSP- Through Silicon Via CSP and BGA.
In each case a clear value proposition will be presented, along with key supporting data. It is truly an exciting time to be part of the industry solving complex packaging and interconnect challenges.
Large Die Size Lead Free Flip Chip Ball Grid Array Packaging Considerations for 40nm Fab Technology
Authors: Bachman Mark A. , Liao Jerry , Osenbach John , Kutlu Zafer , Gim Jaeyun , Brady Danny 
Published: October 2015

To reduce the RC latency, leading edge silicon nodes employ porous SiO2 dielectrics in the interconnect stack. Introduction of porosity lowers the dielectric constant, k, but also significantly decreases both the elastic modulus and fracture toughness of the dielectric. As such, devices manufactured in silicon processes that use low K (90nm, 65nm, and 55nm) and even more so extremely low K ( 45nm, 40nm, and 28nm) interlayer dielectrics are substantially more prone to fracture as a result of package induced stresses than non porous higher K dielectrics. Since the package stresses scale with die size and package body size and inversely with bump pitch, manufacture of large die and package size flip chip devices made with extremely low K dielectrics has proven to be challenging. The stress challenge is further exacerbated by the RoHS requirements for lead free packaging which requires higher process temperatures and somewhat higher yield point solders. The combination of increased stress and reduced mechanical robustness of porous dielectrics has lead to significant reliability and assembly yield issues that have in some cases slowed the introduction of 45nm and 40nm large die lead free flip chip into the market.
The work summarized in this paper shows that devices designed to withstand stresses in combination with appropriate assembly processes and bill of materials, yield highly reliable, lead free flip chip packaged devices, with die sizes greater than 400mm2 and package sizes greater than 42.5mm on a side in commercial assembly production lines.
Cost-Effective Precision 3D Glass Microfabrication for Advanced Packaging Applications
Authors: Flemming Jeb , Cook Roger , Dunn Kevin , Gouker James 
Published: October 2015

Today's packaging has become the limiting element in system cost and performance for IC development. Assembly and packaging technologies have become primary differentiators for manufactures of consumer electronics and the main enabler of small IC product development. Traditional packaging approaches to address the needs in these “High Density Portable” devices, including FR4, liquid crystal polymers, and Low Temperature Co-Fire Ceramics, are running into fundamental limits in packaging layer thinness, high density interconnects (HDI) size and density, and do not present solutions to in-package thermal management, and optical waveguiding.
In this talk, 3D Glass Solutions will present on our efforts to create advanced microelectronic packing solutions using our APEX™ Glass ceramic which offers a single material capable of being simultaneously used for ultra-HDI through glass vias (TGVs), optical waveguiding, and in-package microfluidic cooling. In this talk we will discuss our latest results in wafer-level microfabrication of packaging solutions. We will present on our efforts for creating copper filled vias, surface metallization, and passivation. Furthermore, we will present our efforts in exploring this material to produce (1) ultra-HDI glass interposers, with TGVs as small as 12 microns, with 14 micron center –to-center, (2) advanced RF packages with unique surface architectures designed to minimize signal loss, and (3) creating wave guiding structures in HDI packages.
Temporary Wafer Bonding Materials and Processes
Authors: Lueck Matthew , Huffman Alan , Butler Marianne , Temple Dorota , Garrou Phil 
Published: October 2015

Temporary wafer bonding has been used for many years to provide mechanical support to device wafers during thinning processes. However, the advent of 2.5D and 3D integration is placing significantly higher demands on the performance of temporary bonding materials as more fabrication processes are required on progressively thinner wafers. In response, materials providers have recently developed several different types of temporary bonding solutions that seek to provide a robust carrier with a simple debond process.
Typical 2.5D or 3D integration process flows will require more types of processes than just backgrinding and CMP to be done on the backside of thinned wafers. RIE, PECVD oxide deposition, lithography, and electroplating are some of the process steps that will be needed to complete the TSV interconnects. Each of these steps, and the order in which they are done, will impose certain requirements on the temporary bond material. This presentation will examine the different categories of available temporary wafer bonding solutions with regard to their bonding and debonding methods as well as their resistance to and compatibility with various BEOL processing steps. In addition, ongoing work at RTI to evaluate temporary bond materials for silicon interposer and 3D-IC applications will be presented. This work has been focusing on the interaction between these materials and the processing requirements of several photoimageable dielectrics.
Next Generation eWLB (Embedded Wafer Level BGA): Advanced 3D SiP Packaging Solution
Authors: Yoon Seung Wook , Lin Yaojian , Jin Yonggang , Teysseyre Jerome , Baraton Xavier , Marimuthu Pandi C. 
Published: October 2015

Current and future demands of mobile/portable electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. To meet the above said challenges eWLB was developed which offers additional space for routing higher I/O chips on top of Silicon chip area which is not possible in conventional WLP or WLB. It also offers comparatively better electrical, thermal and reliability performance at reduced cost with possibility to address more Moore [decreasing technology nodes with low-k dielectrics in SoC] and more than Moore [heterogeneous integration of chips with different wafer technology as SiP solution in multi die or 3D eWLB approaches]. Currently 1st generation eWLB technology is available in the industry with 200mm and 300mm carrier size.
This paper will highlight some of the recent advancements in progress development and mechnical characterization in component level and board level reliaiblity of next generation eWLB technologies of double-side 3D eWLB. Standard JEDEC tests were carried out to investigate component level reliability and both destructive/non-destructive analysis was performed to investigate potential structural defects. Daisychain Test vehicles were prepared and also tested for drop and TcoB (Temperature on Board) reliaiblity in industry standard test conditions. There was significant improvement of characteristic lifetime with thined eWLB in TcoB performance because of its enhanced flexibility of package. And there was study of board level reliabiilty with underfill in SMT for large size eWLB packages. This paper will also present study of package warpage behavior with temperature profile as well as failure analysis with microsturctural observation for comprehensive understanding of mechanical behavior of next generation eWLBs.