bluuebunny/crossref_metadata_2025_split huggingface dataset:
Novel Low-Loss Photodefined Electrical TSVs for Silicon Interposers
Authors: Thadesar Paragkumar , Bakir Muhannad S. 
Published: October 2015

Silicon interposers with through-silicon vias (TSVs) have been widely explored to connect multiple chips using high-density fine-pitch lateral interconnects. However, there are challenges with the TSVs in silicon interposers: (1) TSV losses increase as TSV height increases and are much higher in low-resistivity silicon substrates, which are more economical, than in high-resistivity silicon substrates, and (2) coefficient of thermal expansion (CTE) mismatch between the copper and silicon leads to stress generation. To address this set of challenges, we fabricated and characterized two novel photodefined TSVs for silicon interposers: polymer-clad TSVs and polymer-embedded vias.
The fabricated polymer-clad TSVs consist of a ~20 μm thick photodefined dielectric liner instead of a 1 μm thin SiO2 liner, while the polymer-embedded vias consist of copper vias embedded in photodefined polymer wells within the silicon wafer. Compared to the conventional TSVs with thin (~1 μm) SiO2 liner, ~3.5X and ~20X reductions in TSV insertion loss can be obtained at 25 GHz using the fabricated polymer-clad TSVs and polymer-embedded vias, respectively. Full-wave EM simulations were performed in HFSS to compare the insertion loss of the novel TSVs with the conventional TSVs. With respect to the polymer-clad TSVs, in addition to the reduction in TSV insertion loss, a possible reduction in TSV stresses can be obtained using a low Young's modulus material for the thick liner. Finite-element modeling (FEM) simulations were performed in ANSYS to analyze the possible stress reduction that can be obtained using the fabricated polymer-clad TSVs compared to the conventional TSVs. Finally, four-point resistance measurements were performed for the novel TSVs to prove their high yield.
In summary, this presentation will report fabrication and resistance measurements of the novel polymer-clad TSVs and polymer-embedded vias as well as HFSS and ANSYS simulations for the novel TSVs.
Development of Plating Process for Micro Bump Formation
Authors: Katase Takuma , Tatsumi Koji , Hatta Tekeshi , Ishikawa Masayuki , Masuda Akihiro 
Published: October 2015

Flip chip connection has been applied to a lot of applications in order to shorten the connection length of high performance devices. Solder bumping is one of the key technologies for flip chip connections, and its quality makes a large impact on the reliability after packaging. Recently, bump size has been getting smaller to correspond to the finer connection pitch, and these types of bumps are called “micro bumps”.
Electroplating is one of the methods for solder bump formation. Sn-Ag is considered as the best candidate for lead free alloy to be used for the electroplating method. Electroplating is a suitable method to form micro bumps. For micro bump connections, Cu pillar is necessary to obtain a suitable bump height.
Traditionally, there have been some technical difficulties to achieve smooth morphology on “micro bump” surfaces due to its small diameter and/or high aspect ratio.
Lately, we succeeded in developing a new Sn-Ag plating process for micro bump formation by optimizing the plating process.
We also successfully developed our Cu plating process for Cu pillar application with a high plating rate more than 10 ASD condition. Our Cu plating process is available to obtain various surface shapes of Cu pillar such as flat, dome, and concave.
In this study, we established our plating process with Cu pillar + Sn-Ag solder cap. We will review our current status and features of our plating chemical for micro bump formation.
Production of Uniform Dimension Copper Pillars for Flip Chip CSP
Authors: Kenny Stephen , Matejat Kai , Schauer Carsten , Lamprecht Sven 
Published: October 2015

Copper pillars in FCCSP positioned on the substrate are being used instead of solder only joints to meet reliability targets and the demand for smaller feature size, thinner dies and to achieve a well defined stand off. The transfer of the copper pillars from the die to the substrate is required to ensure a reliable thinning process for the dies. The plated copper pillar geometry is dependent on the size of the solder resist opening and thickness. The uniformity and in particular the height of the pillar is very dependant on the electrolytic copper plating parameters used. The height uniformity of all pillars in an array is critical for reliable die attachment to the substrate.
This paper reviews conventional methods to produce electrodeposited copper pillars and introduces a new method for the production of uniform height copper pillars on a FCCSP substrate. Conventional photolithography is eliminated from the new process by use of laser ablation of the features which also prevents any misalignment issues. A sacrificial layer is used to ensure that the copper plated pillars have uniform height. Use of this sacrificial layer also ensures that no seed layer remains on the soldermask surface; conventional methods for pillar production have the disadvantage that seed layer residues may remain on the soldermask giving a pitch limitation. Use of the new process has no pitch limitation due to residual seed layer; initial results with pitch of 200 μm are shown with pillar height 50 μm above solder mask. Development is continuing to reach a pillar pitch of less than 100 μm.
The final solder finish on the plated copper pillar may be electroless tin or a further electrolytic nickel deposit may be used to give a barrier layer before solder deposit.
Microfluidic Technology using SU8 on top of PCBs
Authors: Gassmann Stefan , Pagel Lienhard 
Published: October 2015

The usage of standard PCBs (Printed Circuit Boards) for the creation of micro fluidic systems was already reported. The combination of a standard micro technology using photolithography and photo sensitive layers and the PCB technology leads to interesting low cost solutions for micro systems. The technology and some examples will be presented in this talk.
Using PCBs as the substrate the integration of electronics is simple and the substrate is available at low cost. Putting the sophisticated SU8 based micro technology using photolithography on top, new systems can be created. Both technologies deliver their best, in the PCB technology integrated electrodes and electronics can be created while the SU8 technology adds high resolution high aspect-ratio micro systems which are not possible in a PCB implementation. Although this combination seems to be straight forward, several issues have to overcome for a successful realization. These are the surface roughness, adhesion problems and the uniform coating of rectangular substrates. In the talk these issues will be addressed.
As successful examples an electro-osmotic pump and an electrochemical DNA sensor will be presented.
Glass Carrier Wafers for the Si Thinning Process for Stack IC Applications
Authors: Shorey Aric , Wang Bor-Kai , Canale Joe , Thomas Windsor 
Published: October 2015

Glass carriers have proven to provide a solution for carriers during wafer thinning operations for 3D-IC (Three-Dimensional Integrated Circuit). The attributes of the glass carrier, such as total thickness variation (TTV), flatness and properties such as coefficient of thermal expansion (CTE), are extremely important in their functional performance. Optimization of Corning's fusion forming process gives a platform that is very well suited to generate high precision glass carriers. This process provides glass at target thickness (no grind/polish required) with a pristine surface, extremely tight TTV, low warp/bow, and thickness tolerance over large volumes of material. Given that this material is formed in sheets as large as three meters in size, there is tremendous flexibility in the size of the wafers; as well as ability to scale to high volume manufacturing in a cost effective way. Furthermore, the ability to alter glass composition provides the opportunity to optimize material properties, such as CTE. This is important to accommodate the needs of various device structures which require thinning.
Non-uniformities (TTV, flatness) in the carrier directly impact the accuracy of the thinned wafer TTV. As important as the low TTV and warp/bow provided by Corning's optimized fusion process, is the method in which these attributes are characterized. Corning ® Tropel ® has developed a novel distance measuring interferometer based on a frequency stepping laser that is well-suited to characterize the flatness and TTV of glass wafers.
The work presented here will highlight the importance of high precision carriers and metrology techniques used to characterize and qualify these materials. The impact these have on the TTV of a bonded stack is just as critical. The ability to leverage all of these tools to provide bonded stacks with extremely low TTV and highly uniform silicon wafers after thinning operations will be demonstrated.
Temporary and Permanent Adhesives for Thin Wafer Handling and Assembly
Authors: Oliver Mark , Kim Jong-Uk , Gallagher Michael , Wang Zidong , Okada Janet , Iagodkine Elissei , Zoschke Kai , Wegner Matthias , Töpper Michael 
Published: October 2015

Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, excellent thermal stability, and clean room-temperature release directly from the device wafer. We will present successful temporary wafer bonding using a new BCB (benzocyclobutene)-based material that can meet these requirements.
For this temporary wafer bonding technology, wafer preparation involves spin coating the device wafer with the BCB-based adhesive to a thickness of up to 100 μm and spin coating the carrier wafer with an adhesion promoter. The wafers can then be bonded at temperatures as low as 80 °C for as short as 30 seconds. The low bonding temperature means the wafers can be loaded into a preheated wafer bonding tool, eliminating the time needed to heat and cool the bonding chucks during the bonding cycle. Also, no curing of the material is required during the bonding, enabling a short process time and high wafer throughput. Curing of the adhesive is done as a batch oven cure at 210 °C for one hour after which the material is stable enough for backside processes up to 300 °C. The material has been designed to adhere well to the carrier wafer and debond directly from the device wafer without any chemical or radiation pretreatment, leaving a clean device wafer surface in need of only mild cleaning before further processing.
Effect of Substrate Layer Variation on Package Warpage
Authors: Wells Brendan C. , Lin Wei , Park HyunJin 
Published: October 2015

As requirements for thinner packages continue to be driven by increased device functionality, warpage has become more and more of a concern in package design and processing. Designers are limited by available materials whose properties are not always capable of achieving low warpage targets. Outside of materials development, techniques in the fabrication processing of organic substrates have served as an important secondary approach to reducing package-level warpage. This is becoming more and more important as the substrate thickness is reduced. For a thin substrate, each layer has a marked impact on the substrate's mechanical character, so each must be specified carefully. In addition, a thin substrate is more sensitive to parameter variation within design tolerance and processing windows, resulting in higher warpage standard deviation, which is another challenge for warpage control.
In this paper, several substrate attributes are studied to determine the magnitude of their effect on overall package warpage and deviation. Packages are built using substrates with different variations of metal layer thickness, dielectric layer thickness, solder resist layer thickness, and metal layer density. Warpage data for these packages will be presented alongside statistical analysis. Warpage simulations are also performed and compared to assembly measurement data to rank the largest contributors. The goal of this paper is to inform package design teams of the best ways to limit warpage through processing, when bill of material changes are unavailable.
A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology
Authors: Caswell Greg , Hechfellner Rudi , Kruger Michiel , Heemstra Tewe , Lumileds Philips , Blattau Nathan , Kittlesen Gregg , More Vikrant 
Published: October 2015

LEDs are quickly evolving as the dominant lighting solution for a wide variety of applications. With the elimination of incandescent light bulbs and the toxic limitations of fluorescent bulbs, there has been a dramatic increase in the interest in high-brightness light emitting diodes (HB-LEDs). Getting the light out of the die, with reliable color, while maintaining appropriate thermal control over a long service life is a challenge. These issues must be understood and achieved to meet the needs of unique applications, such as solid-state-lighting, automotive, signage, and medical applications. These applications have requirements for 15–25 years of operation making their reliability of critical importance.
Philips Lumileds, in conjunction with DfR Solutions, developed reliability models for the LUXEON Rebel LED carrier series with respect to multiple circuit board construction types and material sets. Solder fatigue lifetime was predicted based on strain energy calculations. Finite element models were developed to calculate shear stress and strain range.
Temperature cycling of the different material sets was performed to validate the models. The experimental results were integrated in DfR's Automated Design Analysis™ software to ascertain the Physics of Failure (PoF) based reliability predictions for the LEDs. In this paper, the model development methodology and validation approach will be described. Additionally, the Philips Lumileds tool used to demonstrate the long term reliability characteristics of their LEDs to customers will be presented.
Low temperature MOCVD TiN barrier deposition for high aspect ratio TSVs : A solution for 3D integration
Authors: MOURIER Thierry , Minoret Stephane , Fadloun Sabrina , Djomeni Larissa , Maitrejean Sylvain , Burgess Steve , Price Andy , Jones Chris , Roule Anne , Vandroux Laurent 
Published: October 2015

In recent years, 3D integration has become an alternative solution to the “More Moore” concept for providing circuits with higher performance or increased functionality.
Via-Middle TSV is considered a reference integration scheme and requires void-free copper fill of very high aspect ratio TSVs.
Metallization of such structures, in particular barrier and seed layer deposition, becomes a critical process step as barrier material to copper diffusion must provide good efficiency to copper diffusion for further integration and especially on TSV sidewalls, requiring sufficient step coverage.
Ionized PVD is today widely extended from BEOL to TSV metallization. This technique has, however , several limitations for 3D integration coming from its poor step coverage in 10:1 aspect ratio features thus requiring thick material deposition to cover sidewalls which will lead to expensive process both for deposition and further CMP steps and high stress leading to adhesion issues.
Considering the maturity level of the alternative processes, MOCVD metallization appears to be a very promising Solution. MOCVD TiN layers have been widely reported to provide excellent step coverage and diffusion barrier efficiency in BEOL processes.
The presented study describes a process based on an MOCVD TiN deposition that can be performed from 175 to 400 °C. This polyvalent process can be performed for anytype of 3D integration from Mid process TSVs where performance is the key factor to Via last integration for which low temperature and low cost processes are required.
The paper will first discuss the process development and characterization of this material with particular focus on key parameters for 3D integration. In addition, film integration in Via-Middle TSVs will be described, comparing step coverage performance in high aspect ratio TSVs with the I-PVD reference process.
Then, electrical measurements of daisy chains and interconnect lines from a 300 mm 3D demonstrator will be presented.
Thermal & mechanical challenges for 3DIC integration
Authors: Cheramy Severine 
Published: October 2015

3DIC integration is considered as one of the biggest revolutions coming in the next few years in microelectronics and assembly: revolution for the integration & process - from front end to 3D final assembly; revolution for supply chain, design tools, test and characterization...Impact of 3D process and stacking on Cmos and associated design rules that this integration will generate is a key point to ensure the real interest of 3D stacking.
Many recent results tend to prove that some of those challenges are undertaken and on the good way to be solved: 2,5D integration, a step toward 3DIC, is already under production, and thus proposes some embryos of solutions. We can assume that when 2,5D will come with relevant yields and throughputs, the step toward 3DIC will be easier to climb.
Nevertheless, 3DIC will come with specific challenges: thermal impact, coupling effect, stress impact...This paper is an overview of past and current work at Cea-Léti on those thematic. Among others, thermal modeling and characterization is given. Technological solutions at device level are proposed to reduce areas & impacts of hot points.
Secondly, mechanical management of an interposer is detailed: especially with a large interposer, included high density of interconnections, warp management is a key point during 3D process steps, but also during 3D assembly. For this thematic also, some characterizations are given with some proposed solutions.
Finally, a review of major 3D technological steps with associated possible impacts on performances is given. It gives both the already done work, and some of the challenges still to address.
Trends in Automotive Packaging
Authors: Daves Glenn G. 
Published: October 2015

The long-term trend in automobiles has been increasing electronics content over time. This trend is expected to continue and drives diverse functional, form factor, and reliability requirements. These requirements, in turn, are leading to changes in the package types selected and the performance specifications of the packages used for automotive electronics. Several examples will be given.
This abstract covers the development of a distributed high temperature electronics demonstrator for integration with sensor elements to provide digital outputs that can be used by the FADEC (Full Authority Digital Electronic Control) system or the EHMS (Engine Health Monitoring System) on an aircraft engine. This distributed electronics demonstrator eliminates the need for the FADEC or EHMS to process the sensor signal, which will assist in making the overall system more accurate and efficient in processing only digital signals. This will offer weight savings in cables, harnesses and connector pin reduction.
The design concept was to take the output from several on-engine sensors, carry out the signal conditioning, multiplexing, analogue to digital conversion and data transmission through a serial data bus. The unit has to meet the environmental requirements of DO-160 with the need to operate at 200°C, with short term operation at temperatures up to 250°C.
The work undertaken has been to design an ASIC based on 1.0 μm Silicon on Insulator (SOI) device technology incorporating sensor signal conditioning electronics for sensors including resistance temperature probes, strain gauges, thermocouples, torque and frequency inputs. The ASIC contains analogue multiplexers, temperature stable voltage band-gap reference and bias circuits, ADC, BIST, core logic, DIN inputs and two parallel ARINC 429 serial databuses. The ASIC was tested and showed to be functional up to a maximum temperature of 275°C.
The ASIC has been integrated with other high temperature components including voltage regulators, a crystal oscillator, precision resistors, silicon capacitors within a hermetic hybrid package. The hybrid circuit has been assembled within a stainless steel enclosure with high temperature connectors. The high temperature electronics demonstrator has been demonstrated operating from −40°C to +250°C.
This work has been carried out under the EU Clean Sky HIGHTECS project with the Project being led by Turbomeca (Fr) and carried out by GE Aviation Systems (UK), GE Research – Munich (D) and Oxford University (UK).
Die Stacking is Happening in Mainstream Computin
Authors: Black Bryan 
Published: October 2015

Die stacking has proven effective in MEMs and FPGA solutions but has yet to impact mainstream computing CPUs and GPUs. This talk will walk through how die stacking will enter mainstream computing and how it will change the industry in the future
Operating 100kV downhole neutron tube power supplies at temperatures above 150 °C yield low operating efficiency due to excessive diode leakage in the series Cockroft - Walton multipliers typically used. Such circuits are usually limited to less than twelve stages due to N3 voltage regulation effects resulting in immoderate potentials across the switching rectifiers. This paper discusses the merits of using parallel multipliers with 30 stages or more to achieve higher conversion efficiencies at elevated temperatures in tools with 1.3 inch (32mm) diameters. By minimizing the per-stage voltage, definite improvements are realized due to reductions in reverse current leakage per device. Efficiencies of up to 50% may be achieved at 175 °C operating temperature by this technique. In addition, ripple voltages present on the output are not a function of the number of multiplying stages in parallel designs.