bluuebunny/crossref_metadata_2025_split huggingface dataset:
CHARACTERISTICS OF GLOBAL PUBLICATIONS ABOUT WRIST ARTHROSCOPY: A BIBLIOMETRIC ANALYSIS
Authors: Fernandes Carlos Henrique , Meirelles Lia Myiamoto , Neto Jorge Raduan , dos Santos João Baptista Gomes , Faloppa Flavio , Albertoni Walter Manna 
Published: October 2012

The objective of this study was to provide an assessment of published studies on the wrist arthroscopy. The search was performed from the "Web of Science (WoS) Science Citation Expanded Database" with studies published between January 1, 1990 and March 31, 2011. For research we used the following terms: "Wrist arthroscopy" and "Arthroscopy of the wrist". We located a total of 426 studies about wrist arthroscopic, published in 89 journals over the study period. Of all the publications retrieved (426), original articles were 387 (90.84%), but only two (0.47%) were randomised controlled trials, level 1 of evidence.This study showed there are a large number of studies on wrist arthroscopy, but the level of methodological evidence is low.
SURGICAL MANAGEMENT OF CHRONIC BOUTONNIERE DEFORMITY
Authors: El-Sallakh Sameh , Aly Tarek , Amin Osama , Hegazi Mostafa 
Published: October 2012

Purpose: Boutonniere deformity is caused by damage to the central slip of the extensor tendon hood with secondary palmer migration of the lateral bands. Accordingly, patients complain of disfigurement and impairment of function due to hyperextension of their DIP. The aim of this study is to evaluate the results of surgical treatment of chronic boutonniere deformity by using a modified technique.Patients and methods: Twelve patients with posttraumatic boutonniere deformity were available for follow up as a retrospective study. They were treated by release of the extensor expansion proximal to the distal insertion of the oblique retinacular ligaments with proximal recession of the extensor tendon and lifting the lateral bands dorsally onto the PIP joint after separation of the transverse retinacular ligaments from their insertion volarly. All patients had closed injury. The mean age was 32 years (range: 16–48 years). The average follow-up period was 33 months (range: 26–38 months). We included only cases with deformities that were totally correctable passively with or without joint osteoarthritic changes.Results: Preoperatively the average PIP joint extension deficit was 60° and postoperatively the average is reduced to 7°, preoperative the average DIP motion was 10° of hyperextension, post-surgery the average DIP active flexion was 75°. The final outcomes were 58.3% excellent, 33.3% good, and 8.3% poor.Discussion: This modified technique gave (91.6%) excellent and good results. The extensor tendon acted mainly on the PIP joint and allowing the DIP joint to flex freely. The procedure is simple and provides long-term good results.Level of evidence: Therapeutic case series, level 1V.
Selective replication
Authors: Vera Xavier , Abella Jaume , Carretero Javier , González Antonio 
Published: October 2012

Soft errors are an important challenge in contemporary microprocessors. Modern processors have caches and large memory arrays protected by parity or error detection and correction codes. However, today's failure rate is dominated by flip flops, latches, and the increasing sensitivity of combinational logic to particle strikes. Moreover, as Chip Multi-Processors (CMPs) become ubiquitous, meeting the FIT budget for new designs is becoming a major challenge.
Solutions based on replicating threads have been explored deeply; however, their high cost in performance and energy make them unsuitable for current designs. Moreover, our studies based on a typical configuration for a modern processor show that focusing on the top 5 most vulnerable structures can provide up to 70% reduction in FIT rate. Therefore, full replication may overprotect the chip by reducing the FIT much below budget.

We propose
Selective Replication
, a lightweight-reconfigurable mechanism that achieves a high FIT reduction by protecting the most vulnerable instructions with minimal performance and energy impact. Low performance degradation is achieved by not requiring additional issue slots and reissuing instructions only during the time window between when they are retirable and they actually retire. Coverage can be reconfigured online by replicating only a subset of the instructions (the most vulnerable ones). Instructions' vulnerability is estimated based on the area they occupy and the time they spend in the issue queue. By changing the vulnerability threshold, we can adjust the trade-off between coverage and performance loss.

Results for an out-of-order processor configured similarly to Intel® Core™ Micro-Architecture show that our scheme can achieve over 65% FIT reduction with less than 4% performance degradation with small area and complexity overhead.
Workshop on large-scale distributed systems for information retrieval
Authors: Michel Sebastian , Skobeltsyn Gleb , Yee Wai Gen 
Published: October 2012

Due to the dramatically increasing amount of available data, effective and scalable solutions for data organization and search are essential. Distributed solutions naturally provide promising alternatives to standard centralized approaches. With the computational power of thousands or millions of computers in clusters or peer-to-peer systems, the challenges that arise are manifold, ranging from efficient resource discovery to issues in load balancing and distributed query processing.
The 2008 edition of the Workshop on Large-Scale Distributed Systems for Information Retrieval (LSDS-IR'08) provided a forum for researchers to discuss these problems and to define new directions for the work on Distributed Information Retrieval. The Workshop program featured research contributions in the areas of similarity search, resource selection, network organization schemes, issues of data quality, result ranking techniques and query routing algorithms.
Hardware acceleration of transactional memory on commodity systems
Authors: Casper Jared , Oguntebi Tayo , Hong Sungpack , Bronson Nathan G. , Kozyrakis Christos , Olukotun Kunle 
Published: October 2012

The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware. We propose that hardware to accelerate software transactional memory (STM) can reside outside an unmodified commodity processor core, thereby substantially reducing implementation costs. This paper introduces Transactional Memory Acceleration using Commodity Cores (TMACC), a hardware-accelerated TM system that does not modify the processor, caches, or coherence protocol.
We present a complete hardware implementation of TMACC using a rapid prototyping platform. Using this hardware, we implement two unique conflict detection schemes which are accelerated using Bloom filters on an FPGA. These schemes employ novel techniques for tolerating the latency of fine-grained asynchronous communication with an out-of-core accelerator. We then conduct experiments to explore the feasibility of accelerating TM without modifying existing system hardware. We show that, for all but short transactions, it is not necessary to modify the processor to obtain substantial improvement in TM performance. In these cases, TMACC outperforms an STM by an average of 69% in applications using moderate-length transactions, showing maximum speedup within 8% of an upper bound on TM acceleration. Overall, we demonstrate that hardware can substantially accelerate the performance of an STM on unmodified commodity processors.
Hybrid NOrec
Authors: Dalessandro Luke , Carouge François , White Sean , Lev Yossi , Moir Mark , Scott Michael L. , Spear Michael F. 
Published: October 2012

Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such as Sun's prototype Rock processor and AMD's proposed Advanced Synchronization Facility (ASF), can efficiently execute many transactions, but abort in some cases due to various limitations. Hybrid TM systems can use a compatible software TM (STM) in such cases.
We introduce a family of hybrid TMs built using the recent NOrec STM algorithm that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware and software transactions. We evaluate implementations for Rock and ASF, exploring how the differing HTM designs affect optimization choices. Our investigation yields valuable input for designers of future best-effort HTMs.
A declarative language approach to device configuration
Authors: Schüpbach Adrian , Baumann Andrew , Roscoe Timothy , Peter Simon 
Published: October 2012

C remains the language of choice for hardware programming (device drivers, bus configuration, etc.): it is fast, allows low-level access, and is trusted by OS developers. However, the algorithms required to configure and reconfigure hardware devices and interconnects are becoming more complex and diverse, with the added burden of legacy support, quirks, and hardware bugs to work around. Even programming PCI bridges in a modern PC is a surprisingly complex problem, and is getting worse as new functionality such as hotplug appears. Existing approaches use relatively simple algorithms, hard-coded in C and closely coupled with low-level register access code, generally leading to suboptimal configurations.
We investigate the merits and drawbacks of a new approach: separating hardware configuration logic (algorithms to determine configuration parameter values) from mechanism (programming device registers). The latter we keep in C, and the former we encode in a declarative programming language with constraint-satisfaction extensions. As a test case, we have implemented full PCI configuration, resource allocation, and interrupt assignment in the Barrelfish research operating system, using a concise expression of efficient algorithms in constraint logic programming. We show that the approach is tractable, and can successfully configure a wide range of PCs with competitive runtime cost. Moreover, it requires about half the code of the C-based approach in Linux while offering considerably more functionality. Additionally it easily accommodates adaptations such as hotplug, fixed regions, and quirks.
Pocket cloudlets
Authors: Koukoumidis Emmanouil , Lymberopoulos Dimitrios , Strauss Karin , Liu Jie , Burger Doug 
Published: October 2012

Cloud services accessed through mobile devices suffer from high network access latencies and are constrained by energy budgets dictated by the devices' batteries. Radio and battery technologies will improve over time, but are still expected to be the bottlenecks in future systems. Non-volatile memories (NVM), however, may continue experiencing significant and steady improvements in density for at least ten more years. In this paper, we propose to leverage the abundance in memory capacity of mobile devices to mitigate latency and energy issues when accessing cloud services.
We first analyze NVM technology scaling trends, and then propose a cloud service cache architecture that resides on the mobile device's NVM (pocket cloudlet). This architecture utilizes both individual user and community access models to maximize its hit rate, and subsequently reduce overall service latency and energy consumption.

As a showcase we present the design, implementation and evaluation of PocketSearch, a search and advertisement pocket cloudlet. We perform mobile search characterization to guide the design of PocketSearch and evaluate it with 200 million mobile queries from the search logs of
m.bing.com
. We show that PocketSearch can serve, on average, 66% of the web search queries submitted by an individual user without having to use the slow 3G link, leading to 16x service access speedup. Finally, based on experience with PocketSearch we provide additional insight and guidelines on how future pocket cloudlets should be organized, from both an architectural and an operating system perspective.
Dynamic knobs for responsive power-aware computing
Authors: Hoffmann Henry , Sidiroglou Stelios , Carbin Michael , Misailovic Sasa , Agarwal Anant , Rinard Martin 
Published: October 2012

We present PowerDial, a system for dynamically adapting application behavior to execute successfully in the face of load and power fluctuations. PowerDial transforms static configuration parameters into dynamic knobs that the PowerDial control system can manipulate to dynamically trade off the accuracy of the computation in return for reductions in the computational resources that the application requires to produce its results. These reductions translate directly into performance improvements and power savings.
Our experimental results show that PowerDial can enable our benchmark applications to execute responsively in the face of power caps that would otherwise significantly impair responsiveness. They also show that PowerDial can significantly reduce the number of machines required to service intermittent load spikes, enabling reductions in power and capital costs.
Faults in linux
Authors: Palix Nicolas , Thomas Gaël , Saha Suman , Calvès Christophe , Lawall Julia , Muller Gilles 
Published: October 2012

In 2001, Chou et al. published a study of faults found by applying a static analyzer to Linux versions 1.0 through 2.4.1. A major result of their work was that the drivers directory contained up to 7 times more of certain kinds of faults than other directories. This result inspired a number of development and research efforts on improving the reliability of driver code. Today Linux is used in a much wider range of environments, provides a much wider range of services, and has adopted a new development and release model. What has been the impact of these changes on code quality? Are drivers still a major problem?
To answer these questions, we have transported the experiments of Chou et al. to Linux versions 2.6.0 to 2.6.33, released between late 2003 and early 2010. We find that Linux has more than doubled in size during this period, but that the number of faults per line of code has been decreasing. And, even though drivers still accounts for a large part of the kernel code and contains the most faults, its fault rate is now below that of other directories, such as arch (HAL) and fs (file systems). These results can guide further development and research efforts. To enable others to continually update these results as Linux evolves, we define our experimental protocol and make our checkers and results available in a public archive.
Inter-core prefetching for multicore processors using migrating helper threads
Authors: Kamruzzaman Md , Swanson Steven , Tullsen Dean M. 
Published: October 2012

Multicore processors have become ubiquitous in today's systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications with large serial components. The challenge, then, is to develop techniques that allow multiple cores to work in concert to accelerate a single thread. This paper describes inter-core prefetching, a technique to exploit multiple cores to accelerate a single thread. Inter-core prefetching extends existing work on helper threads for SMT machines to multicore machines.
Inter-core prefetching uses one compute thread and one or more prefetching threads. The prefetching threads execute on cores that would otherwise be idle, prefetching the data that the compute thread will need. The compute thread then migrates between cores, following the path of the prefetch threads, and finds the data already waiting for it. Inter-core prefetching works with existing hardware and existing instruction set architectures. Using a range of state-of-the-art multiprocessors, this paper characterizes the potential benefits of the technique with microbenchmarks and then measures its impact on a range of memory intensive applications. The results show that inter-core prefetching improves performance by an average of 31 to 63%, depending on the architecture, and speeds up some applications by as much as 2.8×. It also demonstrates that inter-core prefetching reduces energy consumption by between 11 and 26% on average.
Improving the performance of trace-based systems by false loop filtering
Authors: Hayashizaki Hiroshige , Wu Peng , Inoue Hiroshi , Serrano Mauricio J. , Nakatani Toshio 
Published: October 2012

Trace-based compilation is a promising technique for language compilers and binary translators. It offers the potential to expand the compilation scopes that have traditionally been limited by method boundaries.
Detecting repeating cyclic execution paths and capturing the detected repetitions into traces is a key requirement for trace selection algorithms to achieve good optimization and performance with small amounts of code. One important class of repetition detection is cyclic-path-based repetition detection, where a cyclic execution path (a path that starts and ends at the same instruction address) is detected as a repeating cyclic execution path.
However, we found many cyclic paths that are not repeating cyclic execution paths, which we call false loops. A common class of false loops occurs when a method is invoked from multiple call-sites. A cycle is formed between two invocations of the method from different call-sites, but which does not represent loops or recursion. False loops can result in shorter traces and smaller compilation scopes, and degrade the performance.
We propose false loop filtering, an approach to reject false loops in the repetition detection step of trace selection, and a technique called false loop filtering by call-stack-comparison, which rejects a cyclic path as a false loop if the call stacks at the beginning and the end of the cycle are different.
We applied false loop filtering to our trace-based Java™ JIT compiler that is based on IBM's J9 JVM. We found that false loop filtering achieved an average improvement of 16% and 10% for the DaCapo benchmark when applied to two baseline trace selection algorithms, respectively, with up to 37% improvement for individual benchmarks. In the end, with false loop filtering, our trace-based JIT achieves a performance comparable to that of the method-based J9 JVM/JIT using the corresponding optimization level.
Improved device driver reliability through hardware verification reuse
Authors: Ryzhyk Leonid , Keys John , Mirla Balachandra , Raghunath Arun , Vij Mona , Heiser Gernot 
Published: October 2012

Faulty device drivers are a major source of operating system failures. We argue that the underlying cause of many driver faults is the separation of two highly-related tasks: device verification and driver development. These two tasks have a lot in common, and result in software that is conceptually and functionally similar, yet kept totally separate. The result is a particularly bad case of duplication of effort: the verification code is correct, but is discarded after the device has been manufactured; the driver code is inferior, but used in actual device operation. We claim that the two tasks, and the software they produce, can and should be unified, and this will result in drastic improvement of device-driver quality and reduction in the development cost and time to market.
In this paper we propose a device driver design and verification workflow that achieves such unification. We apply this workflow to develop and test drivers for four different I/O devices and demonstrate that it improves the driver test coverage and allows detecting driver defects that are extremely hard to find using conventional testing techniques.
Synthesizing concurrent schedulers for irregular algorithms
Authors: Nguyen Donald , Pingali Keshav 
Published: October 2012

Scheduling is the assignment of tasks or activities to processors for execution, and it is an important concern in parallel programming. Most prior work on scheduling has focused either on static scheduling of applications in which the dependence graph is known at compile-time or on dynamic scheduling of independent loop iterations such as in OpenMP.
In irregular algorithms, dependences between activities are complex functions of runtime values so these algorithms are not amenable to compile-time analysis nor do they consist of independent activities. Moreover, the amount of work can vary dramatically with the scheduling policy. To handle these complexities, implementations of irregular algorithms employ carefully handcrafted, algorithm-specific schedulers but these schedulers are themselves parallel programs, complicating the parallel programming problem further.
In this paper, we present a flexible and efficient approach for specifying and synthesizing scheduling policies for irregular algorithms. We develop a simple compositional specification language and show how it can concisely encode scheduling policies in the literature. Then, we show how to synthesize efficient parallel schedulers from these specifications. We evaluate our approach for five irregular algorithms on three multicore architectures and show that (1) the performance of some algorithms can improve by orders of magnitude with the right scheduling policy, and (2) for the same policy, the overheads of our synthesized schedulers are comparable to those of fixed-function schedulers.
Stable matching with couples
Authors: Biró Péter , Irving Robert W. , Schlotter Ildikó 
Published: October 2012

In practical applications, algorithms for the classic version of the hospitals residents problem (the many-one version of the stable marriage problem) may have to be extended to accommodate the needs of couples who wish to be allocated to (geographically) compatible places. Such an extension has been in operation in the National Resident Matching Problem (NRMP) matching scheme in the United States for a number of years. In this setting, a stable matching need not exist, and it is an NP-complete problem to decide if one does. However, the only previous empirical study in this context (focused on the NRMP algorithm), together with information from NRMP, suggest that, in practice, stable matchings do exist and that an appropriate heuristic can be used to find such a matching.
The study presented here was motivated by the recent decision to accommodate couples in the Scottish Foundation Allocation Scheme (SFAS), the Scottish equivalent of the NRMP. Here, the problem is a special case, since hospital preferences are derived from a “master list” of resident scores, but we show that the existence problem remains NP-complete in this case. We describe the algorithm used in SFAS and contrast it with a version of the algorithm that forms the basis of the NRMP approach. We also propose a third simpler algorithm based on satisfying blocking pairs, and an FPT algorithm when the number of couples is viewed as a parameter. We present an empirical study of the performance of a number of variants of these algorithms using a range of datasets. The results indicate that, not surprisingly, increasing the ratio of couples to single applicants typically makes it harder to find a stable matching (and, by inference, less likely that a stable matching exists). However, the likelihood of finding a stable matching is very high for realistic values of this ratio, and especially so for particular variants of the algorithms.