bluuebunny/crossref_metadata_2025_split huggingface dataset:
Robust Reliability Performance of Large size eWLB (Fan-out WLP)
Authors: Yoon Seung Wook 
Published: October 2015

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield.
This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.
Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology
Authors: Zwenger Curtis , Khim JinYoung , Khim YoonJoo , Cha SeWoong , Lee SeungJae , Kim JinHan 
Published: October 2015

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm.
Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules to be applied compared to competing laminate-based technologies. In addition, the unique characteristics of WLFO enable innovative 3D structures to be created that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of WLFO and its extension into unique 3D structures. In addition, the advantages of these WLFO designs will be reviewed in comparison to current competing packaging technologies. Process & material characterization, design simulation, and reliability data will be presented to show how WLFO is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.
Techniques and Tools for Collaborative Thermal and Mechanical Modeling of 3D ICs
Authors: Karimanal Kamal 
Published: October 2015

The Industry has been using Computational Fluid Dynamics (CFD) and Finite Element Analysis (FEA) for thermal and mechanical modeling of IC packages for many years. What was already practiced as an engineering-art within packaging organizations for monolithic IC packages has now become more complex due to the need for collaboration across organizational walls in the case of 3D stacking. The holistic solution needed for collaborative engineering of 3D stacking process calls for newer methodologies and information exchange protocols.
One particular necessity while building low power System on Chip (SOC) is the methodology needed to ensure package specific thermal feasibility of IC stacking options at physical layout stage of the 3D IC design. A methodology built on the technique to be presented will avert the unintended consequences of stacked IC hot spot alignment during system operation. The presentation will include a validation of the technique by comparison with traditional thermal modeling technique.
The ability to fabricate such stacks using an evolving supply chain of foundry-OSAT combination is equally crucial to the viability and reliability of the packaged SOC. A process focused modeling tool for understanding the warpage, stress, and Chip Package Interaction (CPI) implications of assembly strategy choices is valuable for ensuring time to market at minimal technology development costs. The presentation will include a modeling case study with quantitative data of warpage and stress implications of process, material and stacking choices.
This presentation will introduce the tools and techniques for collaborative chip stack thermal and assembly process modeling with in-depth discussions on inputs needed, gaps in existing modeling methodologies and output metrics of engineering relevance.
Mobile Packaging and Interconnect Trends
Authors: Prior Brandon 
Published: October 2015

This paper will focus on emerging and fast growth package solutions to meet mobile products' density and cost requirements. A short review of where package miniaturization and modularization has taken us so far, and where it will lead in the next 5 years. Teardowns of high density systems and packages will be used to illustrate key points.
Low temperature Ag sintering technology provides a lead-free die attachment compatible with high temperature (300°C) applications. Previous work with Ag sintering has required some pressure during the sintering process or been limited to small area die. In this paper, a pressureless sintering of micro-scale silver paste procedure is presented for large (8mm x 8mm) area die.
Experimental combinations included: Ag metallized Si die, Au metallized Si die, Ag thick film substrate metallization, Au thick film substrate metallization, PdAg thick film metallization and sintering temperature.
For Au metallization (die and/or substrate), the initial shear strength results were good with 8mm x 8mm die sintered at lower temperatures (200°C). The shear strength was out range of our shear test machine (100 kg), corresponding to &gt;15.3 MPa. However, after aging for 24 hours at 300°C, the shear strength dropped significantly to 40.38 Kg (6.183 MPa). An SEM was used to characterize cross sections of as-built and aged sample. The decrease in die shear strength with high temperature sintering (250°C and 300°C) or high temperature aging is attributed to surface diffusion of Ag along the Au surface resulting in a dense Ag layer adjacent to the Au surface and a depletion layer within the die attach on the opposite side of the the dense Ag layer. Shear failures occurred through the depleted region.
For Ag metallization, no decrease in shear strength was observed with 300°C aging. Shear strength of 8x8cm2 dies was out range of our shear test machine (&gt;100 kg, &gt;15.3 MPa) as-built. The shear strength remained out of range (&gt;15.3MPa) after more than 2000 hours of 300C aging.
Electrical Performance Comparison between fcBGA and eWLB Packages
Authors: Liu Kai , Lee YongTaek , Kim HyunTai , Hlaing MaPhooPwint , Kim Gwang. , Park Susan , Ahn Billy 
Published: October 2015

Wafer-level packages, such as embedded-Wafer-Level-Ball-Grid-Array (eWLB) packages, can provide smaller form-factors and thinner profiles, as finer design rules on W/S, and thinner layers (both metal layers and passivation layers) can be applied in such packages.
However, a routine conversion from fcBGA to eWLB does not guarantee the electrical performance will be the same. Designer's electrical skills still play important roles to reduce design cycle-time for meeting critical electrical performance. We compare the performance from typical fcBGA and eWLB packages in the following areas: insertion-loss for signal nets, power-ground impedance for P/G nets, and cross-talk for both signal nets and P/G nets. Simulation data for both fcBGA and eWLB, along with some experimental data, is provides in the paper.
As metal-layer thickness (4um-12um) in eWLB is typically smaller, and finer design rules are used, the cross-section of a signal trace is smaller, which translates a higher metal-loss in unit- length. In addition, as the passivation layers in eWLB have slightly worse loss-tangent properties, it's substrate-loss is also little higher. The overall aspects above result in higher transmission-line (TML) loss in eWLB in unit-length. But as shorter trace-routing is possible in eWLB, given finer design rules, the overall transmission-line loss could be equivalent to that of a fcBGA transmission-line.
The finer design rules on vias in eWLB facilitate to implement Power/Ground (P/G) planes in a more continuous way, and contribute to less P/G impedance. In addition, as the layer-to-layer separation is smaller, decoupling capacitance inheritably made between the P/G planes is larger, which eventually helps to provide a better or smaller P/G loop-impedance.
Because of less separation distance between metal layers in eWLB, the signal traces see much closer GND planes (e.g., 5um in eWLB versus 50um in fcBGA) in their proximities. The closer GND planes make the electrical fields more locally contained. As a result, in a typical eWLB design (e.g., 12um/12um for L/S), the cross-talk between DDR data buses is typically smaller than that from a fcBGA design (e.g., 30um/30um for L/S).
Evaluation of Polymer Core Solderballs for Wafer Level Reliability Improvements
Authors: Hunt John , Hsieh Adren , Tsai Eddie , Chen Chienfan , Wang Tsaiying 
Published: October 2015

Nearly half a century ago the first die bumping was developed by IBM that would later enable what we call Wafer Level Packaging. It took nearly 40 years for Wafer Level Chip Scale Packaging (WLCSP), with all of the “packaging” done while still in wafer form to come into volume production. It began with very small packages having solderball counts of 2–6 I/Os. Over the years, the I/O count has grown, but much of the industry perception has remained that WLCSPs are limited to low I/O count, low power applications. But within the last few years, there have been growing demands for WLCSP packages to expand into applications with higher levels of complexity.
With the ever increasing density and performance requirements for components in mobile electronic systems, the need has developed for an expansion of applicability for Wafer Level Package (WLP) technology. Wafer Level packaging has demonstrated a higher level of component density and functionality than has been traditionally available using standard packaging. This has led to the development of WLCSPs with larger die and increasing solderball connectivity counts. Development activity has been ongoing for improved materials and structures to achieve the required reliability performance for these larger die.
For this study, we have evaluated several different metallic structures used for polymer core solderballs with two different WLCSP structures. The WLCSP structures which were evaluated included a standard 4-mask design with redistribution layer (RDL), using a Polymer 1, Metal RDL, Polymer2, and Under Bump Metallization (UBM); as well as a 3-mask design with RDL, using a Polymer 1, Metal RDL, and Polymer 2. In the first case, the solderballs are bonded to the UBM, while in the second case the balls are bonded to the RDL, using the Polymer 2 layer as the solder wettable defining layer. All of the combinations are tested using the standard JEDEC Temperature Cycling on Board (TCOB) and Drop Test (DT) methodologies. The two different metallurgies of the polymer core solderballs appear to react differently to the two different WLCSP structures. This suggests that the polymer core solderball compositions may perform best when optimized for the specific WLCSP structures that are manufactured.
We will review the results of the impact of the different polymer core metallurgies on the TCOB and DT reliability performance of the WLCSPs, showing the interactions of these materials with the two WLCSP structures.
Wet Chemical Processing with Megasonics Assist for the Removal of Bumping Process Photomasks
Authors: Seong Sohn Hong , Tracy John 
Published: October 2015

A new generation of negative tone resists by TOK, JSR, and Dow Chemical is gaining momentum in advanced packaging applications. Resist thickness requirements are actually increasing to the 50-100 um range as Cu pillars are adopted to accommodate the tighter pitches required in advanced packaging. In order to form pillars the resist must be thicker to contain the entire bump structure.
Thick, negative tone resists are more transparent to exposure light wavelengths than positive tone resists and can be exposed by the lithography process much faster (~1 x 104 cross-linking chemical events are driven by 1 photochemical event vs. 100 – 1000 for positive tone resist).1 Therefore exposure times can be shorter, post-exposure bake steps can be shorter, and delay before or after exposure is not necessary, saving photolithography time and CoO. And, due to more complete cross-linking throughout the resist, the resist mask profiles are truer (from Flack et.al, “A Comparison of New Thick Photoresists for Solder Bumping”, SPIE 2005).1
The major drawback to negative tone resists is that the solvent strip times of the highly cross-linked resist masks are much longer than for positive tone. Flack et.al. noted resist strip times of 5 minutes for two positive resists used in their experiments vs. 50 minutes for the AZ-100nXT negative tone resist, using AZ400T at 80°C (most likely in an immersion tool). Long strip times or special stripping requirements are noted on the data sheets of the other majority suppliers of negative resists as well.
Akrion engineers have developed a novel, single-wafer, negative PR strip processes using organic solvents plus Goldfinger megasonics, to provide 30 - 70% reductions in process times and the associated chemical consumption when compared to processes that do not utilize a megasonics assist. The multi-step process can be accomplished in a single process chamber, with each step optimized for time and temperature based on the resist thickness and solvent stripping chemistry used.
In the Akrion process, a period of solvent exposure at low wafer spin speed is used initially to begin swelling and dissolving the thick photoresist layer. This is followed by a second solvent exposure step using aggressive frontside megasonic energy to promote polymer chain scission throughout the bulk of the photoresist layer. Following this step A DI water rinse and spin dry step are sufficient to completely remove the solvent, dissolved photoresist and any polymer residues.
This paper reviews the development of the Akrion process and several examples of improvement in stripping time and results from work with customers.
Pathfinding and Design Optimization of 2.5D/3D devices in the context of multiple PCBs
Authors: Yazdani Farhang , Park John 
Published: October 2015

As the 2.5D/3D integration technologies shapes the future of semiconductor industry, pathfinding methodology and design optimization of such integration is still at its infancy. 2.5D/3D device integration generates ultra-high density interconnect between the devices. Planning and defining 2.5D/3D I/O cell placement in the context of the overall system is one challenge, optimizing such integration for performance and cost is another challenge. Defining 2.5D/3D partitions and integration feasibility at the early stages of product development is even more pronounced. Often, such early pathfinding feasibility and early assessment of the integration had direct impact on successful product.
In this paper, we disclose pathfinding and optimization methodology for integrating 2.5D/3D devices on silicon interposer in the context of multiple PCBs. Various integration schemes are investigated and trade offs are demonstrated. Additionally, we demonstrate constraint based signal assignment for early 2.5D/3D product evaluation and feasibility study. This paper teaches and contributes to rapid integration of 2.5D/3D devices in the context of multiple systems.
Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package
Authors: Zohni Wael , Katkar Rajesh , Co Rey , Cizek Rizza 
Published: October 2015

Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (&gt;100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years.
A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP.
This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware.
In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.
All-silicon multi-chip modules based on ultra-thin active pixel radiation sensors
Authors: Andricek Ladislav 
Published: October 2015

The Semiconductor Laboratory of the Max Planck Society is designing and producing cutting edge radiation and particle sensors for experiments in basic science conducted by institutes of the German Max Planck Society and other international partners. One of the most challenging projects is the construction of so-called vertex detectors for experiments at high energy particle colliders like KEKB in Japan and the future International Linear Collider (ILC) as the next big international high energy physics project after the LHC at CERN, Geneva, Switzerland.
Modern vertex detectors are pixelated position sensitive particle sensors based on highly specialized silicon technology similar to CMOS or CCD sensors for commercial optical applications. The goal is to measure the track of a secondary particle and extrapolate to the point of its origin. One of the main challenges for up-to-date vertex detectors is the requirement of low mass to minimize the effect of scattering of the traversing particle in the sensor material itself and the sensor support structures.
We are developing ultra-low-mass sensors based on the DEPFET (DEpleted P-channel FET) pixel technology. DEPFETs are MOS transistors made on fully depleted detector grade silicon and combine the sensing and first signal amplification element in the same device. The thickness of the sensor is minimized and optimized for the best vertexing performance of the detector arrangement as whole. The detector is a cylindrical arrangement of sensor modules around the primary beam interaction point.
The sensor module is a silicon based multi-chip module with the module substrate being the sensor wafer itself. There are three functional regions on the MCM: the 50 μm thin sensitive active pixel area with the DEPFETs in a two metal and two poly-silicon layer technology, the ‘end of stave’ with three metal layers (two Al and one Cu) where the read-out electronic is placed and the narrow frame in the same interconnect technology with the steering ASICs. Three types of ASICs are used: a mixed-signal ASICs as the analogue front-end and ADC, a digital data handling chip and a steering chip in HV-MOS technology for the row-wise addressing and clearing of the pixel matrix. There are 12 chips in total on the module, all bump-bonded to the substrate, about 3000 area array bumps in total.
The finished module has 250 kPixels and is read out at a frame rate of 50 kHz via a wire-bonded flex cable.
Our paper will describe the technology for the production of ultra-thin DEPFET sensors and the monolithically integrated support, testing challenges during production and their solutions as well as electrical, thermal, and mechanical properties of the assembled MCMs. An outlook will be given on how micro-channels for active cooling will be integrated in the current MCM concept.