bluuebunny/crossref_metadata_2025_split huggingface dataset:
Cost Effective Production of Glass Interposers for 3D ICs Using APEX(TM) Glass Ceramic
Authors: Flemming Jeb H. , Dunn Kevin , Gouker James , Schmidt Carrie 
Published: October 2015

The most singular focus of the electronics industry during the last 50 years has been to miniaturize ICs by miniaturization of transistors and on-chip interconnections. Two major problems are foreseen with this approach; electrical leakage and lack of improved electrical performance beyond 16nm. As a result, industry is transitioning from the current SOC-based approach to a through-silicon-via (TSV) based 3D IC-stacked approach. However, a major challenge remains; these 3D ICs need to be interconnected to other ICs with a much higher number of I/Os than are available with current ceramic or organic interposers. While silicon interposers currently in development can provide these high I/Os, they cannot do so at low enough cost.
In this talk, we will present on our efforts in glass interposers fabrication. Glass interposers possess many advantages over silicon interposers including: cost, production time, and scale. Life MicroFab's APEX™ Glass ceramic is a photo-sensitive material used to create high density arrays of through glass vias (TGVs) using three simple processing steps: exposure, baking, and etching. To date, we have been successful in producing large arrays of 12 micron diameter TGVs, with 14 micron center-to-center pitchs, in 125 micron thick APEX™ Glass ceramic. We will present (1) on our efforts producing high aspect ratio TGVs in thin (500-250 micron) and ultra thin (250-75 micron) APEX™ Glass ceramic wafers, (2) maximum TGV aspect ratios, and (3) TGV fidelity and limits of manufacturing.
Cu-Cu Thermocompression Bonding using Ultra Precision Cutting of Cu Bumps for 3D-SIC
Authors: Sakai Taiji , Toshiya Akamatsu , Imaizumi Nobuhiro , Toyoo Miyajima , Mizukoshi Masataka 
Published: October 2015

We have developed a new Cu-Cu thermocompression bonding technique by using cut Cu bumps in order to achieve high density 3D-stacked IC (3D-SIC). Currently, Sn layer is formed between Cu bumps, and then solid-liquid bonding is made by tin melting to connect Cu bumps. But using Sn layer can cause undesirable issues, such as electro-migration and Kirkendall voids formation between Cu/Sn interfaces, which could decrease bonding reliability. Therefore we believe that Cu-Cu thermocompression bonding is an essential technology especially in 3D interconnection.
In the present study, cut Cu bumps were obtained by ultra-precision cutting using a single crystal diamond bite that would give a highly smooth Cu surface (Ra:7nm). A major advantage of cut Cu bumps is that they have an amorphous-like layer on the surface. In TEM observation, it was found that about 120nm thick amorphous-like layer was formed after cutting of Cu bumps. This layer has a potential to connect bumps each other at a low temperature similar to solder bonding because amorphous-like layer accelerates a recrystallization reaction of Cu crystal.
Cut Cu bumps on both sides of LSI and substrate have been successfully bonded at 250 degrees C condition. From the analysis of crystal orientation by EBSD, it was found that the bonding interface had disappeared, which means solid diffusion was occurred and crystal grain grew across the interface.
Packaging HB LEDs with Integrated Beamshaping
Authors: Hoeftmann Thomas 
Published: October 2015

LED light will dominate in future a lot of application fields in everyday life and it already started not only in consumer market. Therefore more and more applications require new ideas and approaches for packaging to fulfill upgraded requirements for protection, reliability, beam shaping and cost reduction, especially for High Brightness (HB) LEDs in e.g. automotive and other markets.
This presentation will give an overview about the developed monolithic window with integrated anti-glare shield for HB LED packaging used in the automotive market for low and high beam headlights and other special lighting functions of modern cars.
Apart from the component protection, the monolithic window ensures that there is sufficient contrast and thus glare protection in the irradiation area of the LED array.
In addition future packaging technologies will be introduced to provide 3D interconnection and beam shaping by glass lenses. All discussed packaging ideas will meet the requirement of vacuum tight wafer level packaging by building monolithic packaging boards or capping wafers made of micro processed silicon and glass material.
Novel Wet Chemical Copper Metallization for Glass Interposers
Authors: Bamberg Simon , Bruening Ralf , Etzkorn Johannes , Bruening Frank 
Published: October 2015

The focus of the chip and IC substrate manufacturing industry for interposers is currently shifting from organic substrates to inorganic materials. Interposers overcome the dimensional mismatch between a die and an organic PWB substrate and need to buffer the differences in thermal expansion between these two materials.
While inorganics like silicon and glass, have a low CTE value compared to organic material, glass has some significant advantages over silicon. These are namely material cost, availability in panel size and a better electrical insulation. In order to further increase the cost advantage, metallization could be done by either electroless or electrolytic copper plating as an alternative route to sputter technology. Both wet chemical processes are well established in PWB manufacturing and need adaptation to glass substrates. Compared to sputtering, 3D-features can be covered with a wet chemical treatment in a comparatively economical process.
Filling of TGVs (Through Glass Vias) by electrolytic copper plating requires the presence of a conductive film which is created by applying electroless copper deposition of typically 300–500nm thickness. The general issue is poor adhesion to the smooth glass surfaces. To improve adhesion between glass and metal, various treatments were assessed in this study: Mechanical anchoring was achieved by etching the substrate (subtractive) as well as by depositing nano-sized silica particles (additive). Both treatments are in solution and 3D-features are accessible in contrast to a purely mechanical approach. Surface treatments without inducing additional roughness included the adsorption of functional metal-affine polyelectrolytes and silanization for conditioning which enhanced the adhesion of the copper layer to various degrees.
To study the impact of chemical formulation on strain/stress development and relaxation in the film as a key impact factor for blister (adhesion) performance, the electroless copper layer growth was monitored by in-situ XRD methods during and after deposition.
Evalulation of Electrodeposited Photoresists for use in the Fabrication of an Optochip Silicon Interposer
Authors: Tsang Cornelia , Okada Janet , Huenger Eric 
Published: October 2015

As 3D packaging technology and designs evolve, increasing complexity has been introduced in the fabrication of these devices. The integration of optical devices along with electronic wired elements such as the package platform identified in image sensors is one prime example where the design elements of the structures significantly increase the topography on the surface of the system. This multiplies the degree of difficulty in the lithography solution chosen to facilitate fabrication of these structures. The use of electrodeposited (ED) photoresists is a technology platform that has been used in MEMs, printed circuit boards, backside vias, etc, and can play a significant role in enabling new 3D packaging solutions.
In this research, the successful fabrication of an Optochip silicon interposer, which integrates electrical and optical components onto a single substrate with high density interconnection, was enabled through use of electrodeposited (ED) photoresist. The Optochip interposer was manufactured in a standard 200 mm semiconductor fab and this precipitated the process integration requirement of first etching “optical vias” into the silicon at wafer-level prior to the final lithography steps. As such, challenging topography was introduced into the system. A resist solution able to address the following conditions was required: 1) sufficient conformal coating into large optical vias measuring 150 um diameter by 200 um depth, 2) no resist pull-back over sharp 90 degree angle corners where the optical vias met the wafer surface, 3) ability to resolve 30 um diameter surface pads at 50 um pitch and 4) chemical resistance to Ni and cyanide-based Au plating baths.
This presentation will discuss how various photoresists were examined that resulted in ED photoresist being chosen for the aforementioned application. Both negative-tone and positive-tone ED photoresists were considered. Experiments to study process parameters and environmental factors on product yield were performed using test wafers with optical vias. These experiments resulted in positive-tone ED photoresist being selected. Test wafers plated with NiAu resulted in ~ 90% process yield. The presentation will conclude by demonstrating the ability to achieve good yield on integrated product wafers.
Flip Chip for Image Sensor Packaging
Authors: Kim Deok-Hoon , Cho Young-Sang , Elenius Peter 
Published: October 2015

The use of flip chip interconnects for image sensor packaging provides several unique challenges during packaging as well as benefits to the customer.
The principal challenges during assembly include the requirements of: no contamination of the image sensor during reflow, fabrication of a sealing structure to prevent future environmental contamination of the image sensor, and fabrication of a solder joint structure for the seal ring that can pass pre-conditioning. To achieve these requirements, the use of a fluxless solder reflow process and transient liquid phase (TLP) bonding will be explained.
Benefits to the customer for this type of flip chip image sensor packaging as compared to chip on board (COB) and thru silicon via (TSV) packages is a thinner camera module and versus TSV packages the ability to pass all required reliability tests without the use of an underfill. Reliability test results will be shown for thermal cycling, drop, and bending tests.
Low Profile Silicon Interposer using Passive Integration (PICS)
Authors: Bunel Catherine , Bellenger Stephane , Leruez Sebastien , Lenoir Lionel , Murray Franck 
Published: October 2015

Thanks to their 3D structure, the Silicon Capacitors offer drastic improvements in terms of performances compared to the commonly used ceramic and tantalum capacitors. They are also a smart way to reduce the application volume and increase the IP protection level.
With the increasing complexity in the die and package designs and ever increasing cost pressure in today's microelectronic industry, IPDIA is offering for a large range of products, customized or standard components, a low cost packaging solution: the Wafer Level Chip Scale Packaging. While wire-bond interface may remain the preference for many applications, face-down direct chip attachment has gained wide acceptance. More than interacting on electrical functionality, WLCSP is interacting on mechanical and thermo mechanical properties with a higher miniaturization and a transfer directly on printed circuit boards without additional packaging steps.
This paper presents the main characteristics of the 3D-IPD advanced technology emphasizing on its capability and advantages versus discrete components illustrated by different applications using ultra-thin IPD ( down to 60 μm ) and WLCSP.
Silicon Interposers Enable High Performance Capacitors
Authors: Savastiouk Sergey , Marcoux Phil , Hewlett Jim 
Published: October 2015

Thin film capacitors without TSVs have been used previously. However, with the interconnect inductance being high, benefits of thin film capacitors have not been fully realized. TSV interposers with embedded capacitors provide the shortest electrical path between devices and power supply decoupling capacitors. TSVs with their very low inductance interconnects thus will enable very high electrical performance when integrated with embedded thin film capacitors.
ALLVIA, on behalf of it's foundry customers, has been conducting studies of various capacitors on silicon interposers. The data presented in this paper shows after several thermal cycles that planar capacitors on silicon results in stable, reliable capacitors operating at very high frequencies. Unlike an issue of parallel resonance seen with chip capacitors, planar capacitors in interposers don't exhibit this property.
200mm & 300mm Processes & Characterization for Face to Back Flow Chart for Wide I/O
Authors: Cheramy Severine , Garnier G. , Jouve A. , Colonna J.-P. , Coudrain P. , Chausse P. , Segaud R. , Aumont C. , Hotellier N. , Brunet-Manquat C. , Laviron C. , Sillon N. 
Published: October 2015

3D integration so far has often been investigated through a face to face point of view: the top die FEOL is in front of bottom die FEOL. This allows a dense connectivity between both dies, but TSV are mandatory on the bottom die for each external exchange.
Another flow chart, which main application is identified as the Wide I/O, is “face to back”: the FEOL of the top die faces to the back side of the bottom dies. To communicate between top & bottom, interconnections then TSVs are needed. Advantage is that the bottom die, for Wide I/O the logic dies, faces directly to the board allowing a rapid communication with external. Also, the Wide I/O interface delivers high bandwidth at relatively low power consumption level.
The objective of this paper is to show latest integration at Leti, both on 200mm & 300mm wafers, using face to back integration. If we compare both flow charts, using via middle technology, the main challenge consists of the temporary bonding. The temporary adhesive needs to be at least 50 μm thick, even more depending on staking technology on board, and in presence of the macro connection. The choice of the adhesive is crucial for the final stability of the stack during back side process and also during debonding, even more on 300mm wafers.
Technical developments are introduced in the paper. A specific focus is done on temporary adhesive & the associated thermal stability of the stack. Impact of the temporary bonding on copper pillar is evaluated. Assembly of best processes for a full integration on daisy chain wafers, both 200 & 300 wafers is described.
Finally, a comparison of electrical datas (resistance, capacitance, isolation) for both wafer diameters is given. Morphological characterization finalizes this first integration and leads to further potential improvements.
Thermal Cycling Analysis of BGA Solder Joint Reliability
Authors: Yeung Betty H. , Hauck Torsten , Wilkerson Brett , Koschmieder Thomas 
Published: October 2015

The solder joint reliability of semiconductor package interconnects is critical to product durability. A dominant failure mode is solder fatigue due to the CTE mismatch between BGA component and PCB at thermal cycling. It is well known that besides thermal expansion mismatch of component and board, the solder joint geometry has a great impact on fatigue behavior and time to failure.
In this study, a combination of Surface Evolver and finite element analysis are use to predict the solder joint shapes for the assembly of medium pin count BGA's and to estimate the reliability at accelerated temperature cycling conditions. Results of Surface Evolver are compared with the assumption of a truncated sphere. The solder shape predictions are applied for a subsequent thermo-mechanical analysis of the BGA assembly. Inelastic creep deformation is evaluated for critical solder balls, and the Coffin-Manson relation is used to estimate the solder joint lifetime. The entire simulation procedure will be demonstrated for a product design study for high reliability automotive BGA's. A fractional factorial design is defined that considers solder sphere diameter and solder pad sizes on BGA substrate and on PCB side. Resulting creep values and lifetime estimates will be compared.
Comparative Test Data for TIM Materials for LED Applications
Authors: Papanu Victor 
Published: October 2015

Developments in thermal interface materials (TIMs) continue across the industry with a variety of different types of materials. Thermal and mechanical design engineers are often confronted with the need to select which type or category of TIM material is the most appropriate for a specific LED module application, which can be confusing, and how to determine which materials provide the best thermal performance. The next step is understanding which TIM material types meet requirements for ease of shipping, handling, placement, cost, and rework. These are important distinctions, in addition to thermal performance.
This presentation will illustrate comparative testing results for a set of thermal interface materials (TIMs) in different categories, using different TIM testing procedures. Test data prepared using three different test methods will be compared:1. ASTM D5470-06 with known temperatures and clamping forces;2. In-situ testing with industry-standard semiconductor modules, at known temperatures and estimated clamping forces;3. In-situ testing utilizing a thermal test vehicle (TTV) for TIM2 performance for a processor module.
In-situ testing has been performed at an independent power semiconductor manufacturer, using both industry-standard and commonly-available modules and a custom-designed module with a relatively small footprint, capable of high operating junction temperatures. This testing data can illustrate how different types of TIM materials perform in laboratory testing conditions, for precise comparisons on thermal performance alone; and how different types of materials perform in what are termed as “in-situ” test procedures. This term is used for application-specific conditions, where additional variables are encountered in the testing (such as non-flat surface conditions and unknown clamping force values), which is significantly different from the laboratory conditions used to generate ASTM D-5470 test values.
The comparative testing that has been undertaken will be described, showing that images of various power semiconductors with several different materials tend to correlate with the thermal resistance of materials measured with the ASTM D 5470-06 method. These thermal interface materials were also tested on a TTV supplied by a major processor module. The relevance of the thermal imaging, the TTV and the ASTM values will be discussed.
This presentation is intended to illustrate the differences in experimental data from one TIM material to another, as well as the differences in testing procedures.
The Evolution of LED Packaging: New Approaches for Solid State Lighting
Authors: Karlicek Robert F. 
Published: October 2015

The rapid evolution of solid state lighting is driving rapid and innovative approaches to LED packaging. While the bulk of LEDs are still packaged using decades old technology, the cost and performance needs of solid state lighting are forcing the development of new light emitter packaging technology, some of it being imported from more conventional electronic packaging. Concepts like wafer level packaging, chip on flex technology and SIP technology are infiltrating the LED packaging landscape, but with innovations developing from the need to simultaneously manage input power, thermal dissipation and light extraction for energy efficient lighting. Lighting cost constraints are also driving new requirements for higher packaging speeds and LED integration directly into lighting fixtures rather than through the conventional die-to-package-to-board-to-system sequence. Finally, lighting system performance specifications like intensity, color quality, glare, and beam pattern, all dependent on how light moves from inside the die to the user, are forcing new system level requirements into the LED packaging arena.
This talk will discuss how the development and evolution of solid state lighting systems are working to drive innovation and evolution in the development of LED packaging materials, structures and methods. With the need for energy efficient lighting driving a rapid transition from bulbs and tubes to solid state devices, LED packaging is poised for a revolution where the conventional roles of semiconductor packaging are redefined in new and exciting ways that are needed to make solid state lighting a practical reality.
Plating Opportunities in 3D
Authors: Uhlig Albrecht , Bera Holger , Jaeger Cornelia , Rohde Dirk 
Published: October 2015

Through Silicon Via's (TSV) are one of the key enabling technologies towards 3D packaging. Copper electroplating is frequently mentioned as candidate to fill TSV's besides polySi or ink-jetting conductive inks and attracts high attention. In addition to copper plating solder plating offers the next opportunity. Last but not least the ultimate target of an “all wet TSV” where also barrier and seed layers are electroplated, was demonstrated already. This paper targets to introduce the 3D related plating technologies and will encourage a discussion about targets to be meet in order to enable 3D. Even so copper plating is well introduced to the IC industry for Dual Damascene plating, TSV copper filling challenges the plating technology. One of the reasons why is that TSV dimensions are almost one magnitude larger than dual damascene structures. So in order to meet the industries target of fast and void free copper filling, type and function of organic additives applied in copper plating bathes need to be re investigated. Galvanic copper electrolytes contain three organic additives.
Carrier is a mild plating suppressor, Brightener is an accelerator, and Leveler is a strong suppressor and locally deactivates the Brightener. The Leveler component mainly affects the properties of the copper deposits. This paper will give an overview about type and role of organic additives used for TSV application. We will also discuss how namely the Leveler controls the filling mechanism and copper deposit properties. Two different acidic copper systems were used for TSV-filling. System A shows a super-conformal filling behavior and different copper grain structures at the surface compared to the TSV body. System B shows a bottom-up filling with similar copper grain structure at surface and TSV body. Both systems vary further regarding stress of the copper deposits, recrystallization temperature, incorporation of additives, and coefficient of thermal expansion. The paper discusses the influence of organic copper additives to the mechanical, thermal, and electrical properties of the copper deposits. Even so process technology to fill TSV's is still fast progressing we like to give a snapshot of fill times per TSV dimension reached using System B. Other potential plating applications in 3D stacking are eventually plating solder and/or diffusion barriers. This paper intends to introduce the basic principles of electrochemical and electroless plating and give application examples for Tin and Nickel/Palladium electroless plated layers applied for 3D packaging applications. Last but not least the concept of “all wet TSV” appears in the literature, targeting to substitute the barrier and seed layer so fare deposited by vacuum deposition technology by plating technologies. We will shortly review the literature and will introduce work currently under progress in Atotech towards an “all wet TSV”.