bluuebunny/crossref_metadata_2025_split huggingface dataset:
Getters and Design to Reliability: A Tool For Lifetime Assurance
Authors: Kullberg Richard C. , Phillip Bradley L. 
Published: October 2015

The key to reaching multi-decade package lifetimes and device reliability is to not just take a snap shot with a RGA and declaring a part passed per MIL-STD-883. It requires a deep understanding of the sources of unwanted gases in a package, characterizing their true flow rates within, without and through the package system, and carefully choosing processes and materials, including getters, to manage the unwanted gases. This is true whether the package is hermetic or non-hermetic.
A multi-step process is discussed to include identifying the gas sources, the species present and their quantities, modeling the true quantities of gas generated over the lifetime of the package, and removing it, either through process or materials. When package service lifetimes reach decades, traditional understandings start to fall apart and careful quantitative analysis is rewarded.
Getters play a key role in attaining multi-decade lifetimes. Getter selection and sizing is discussed. Included in the discussion will be a brief synopsis of the current state of the art of gettering technology.
Mixed Attachment Technology Studies in RF & Optoelectronic Packages Requiring High Accuracy Placement
Authors: Evans Daniel D. , Bok Zeger 
Published: October 2015

RF & Optoelectronic packages continue to shrink in size with less space for die. Power densities are increasing as well. Packaging engineers are exploring a switch from conductive adhesive to eutectic solder attachments on high power components. Lower power components still allow adhesive attachment but have their own challenges due to tight spacing. This paper explores a range of case studies that demonstrate both eutectic and adhesive assembly and the results for closely spaced components.
An overview of the technology and the placement accuracy and attachment method is presented for eutectic and adhesive based attachment for components ranging from 0.18mm [7.1mil] × 0.18mm [7.1mil] × 0.20mm [7.9mil] Si die to 1.7mm [67mil] × 1.4mm [55mil] × 0.16mm [6.3mil] GaAs die. Component spacing of 60μm or less create challenges in keeping epoxy or solder from squeezing between die.
A review of tools, guidelines, and actual results will be shared in this paper.
Reliability Study of Reference Semiconductor Encapsulation Materials for Biocompatible Packaging
Authors: Malachowski Karl , Qian Karen , de Beeck Maaike Op , Verbeeck Rita , Bryce George , Dekkers Harold , Tezcan Deniz S. 
Published: October 2015

Material selection is the key issue when developing a biocompatible packaging process for implantable electronic systems. To secure a reliable performance of the chip in such a package, its encapsulation has to be considered up-front in the wafer-level integration scheme. A differentiation of two main material types can be made:1) Insulating or passive materials functioning as a bi-directional diffusion barrier preventing body fluids leaking into the package causing systems malfunction due to possible materials corrosion and also avoiding a leakage of built-in materials to the in-vivo environment and2) Conductive or active materials as diffusion barriers, e.g. against copper diffusion or as direct external contacts responsible for electrical performance of the system.
This study investigates the properties of two widely used insulating materials in the semiconductor industry, the nitride and the oxide. Both material types are deposited in a PECVD system using different temperatures; 400 ° C for CMOS compatibility and 200 ° C for wafer back side process integration when a temporary carrier system is used. The biocompatibility investigations of these materials (evaluated using cell lines and primary cells) show promising results. However, for the long term application, the stability results for the oxide layers show hydration effects resulting in material degradation where the nitride layers clearly show corrosion and are even etched when elevated temperatures are applied. This fact is surprising since nitride layers are widely used as a humidity barrier for various chip types but obviously not suitable for a direct contact with liquids. Various analysis methods using e.g. Fourier Transformed IR Spectroscopy or mass measurements substantiate this thesis.
Epidermal electronics for health and fitness monitoring
Authors: Rafferty Conor , Dalal Mitul , Davis Dan , Elolampi Brian , Hsu Yung-Yu , Lee Stephen , Klinker Lauren , Morey Briana 
Published: October 2015

Medical deployment of electronics is frequently hampered by boxy, rigid packaging. Biological tissues are soft and curved, while electronic components are hard and angular. The mechanical mismatch can be alleviated by re-packaging electronics in radical new form factors. MC10 has developed a technology platform using ultra-thin components linked with stretchable interconnects and embedded in low modulus polymers which provide an excellent match to biological tissues.
The MC10 platform is based on packaging today's high-performance active components in new mechanical form factors. The platform has three key elements: thin silicon embedded in film for flexibility, silicon transfer from foundry CMOS wafers to polymer-coated carriers and flexible metallic interconnect on polymer.
On-body and in-body applications are both well suited to the technology platform. Skin-mounted systems resemble electronic tattoos, and can be worn for extended periods without discomfort while providing continuous monitoring. Inside the body, instrumented catheters provide a practitioner with unprecedented electrical information about the interior of the heart.
Biocompatible encapsulation and interconnection technology for implantable electronic devices
Authors: de Beeck Maaike Op , O'Callaghan John , Qian Karen , Morcos Bishoy M. , Radisic Aleksandar , Malachowski Karl , Amira M. F. , Van Hoof Chris 
Published: October 2015

A biocompatible packaging process for implantable electronic systems is under development at imec, combining biocompatibility, hermeticity, extreme miniaturization and cost aspects.
In a first phase of this packaging sequence, hermetic chip sealing is performed by encapsulating all chips to realize a bi-directional diffusion barrier preventing body fluids to leach into the package causing corrosion, and preventing IC materials such as Cu to diffuse into the body, causing various adverse effects. For cost effectiveness, this chip sealing is performed as post-processing at wafer level, using modifications of standard clean room (CR) fabrication techniques. Well known conductive and insulating CR materials are investigated with respect to their biocompatibility, biostability, diffusion barrier properties and sensitivity to corrosion. Material selection and integration aspects are modified until good properties are obtained.
In a second phase of the packaging process, all chips of the final device should be electrically connected, applying a biocompatible metallization scheme. We selected the use of Pt due to its excellent biocompatibility and corrosion resistance. Since Pt is very expensive, a cost effective Pt-selective plating process is developed.
During the third packaging step, all system components such as electronics, passives, a battery,… will be interconnected. To provide sufficient mechanical support, all components are finally embedded using a medical grade elastomer such as PDMS or Poly-urethane.
Modeling in the Cloud: Web Hosted CPI Modeling for Fabless Design Houses and OSATs Method for Mechanical Stress Simulation across the Chip & Package Domains in 3D IC's
Authors: Nakamoto Mark , Dhandapani Karthikeyan , Zhao Wei , Syed Ahmer , Lin Wei , Radojcic Riko 
Published: October 2015

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require ability to model and evaluate the interactions and risks. In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance.
Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates an interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. It allows flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online.
Examples are presented to demonstrate the influence and impacts of materials, process recipes and chip/package design; including an example of the flow from package level through silicon electrical level modeling to silicon hardware measurements.
Through Silicon Via (TSV) Technology Creates Electro-Optical Interfaces
Authors: Marcoux Phil 
Published: October 2015

Silicon is a most versatile material, it is readily etched into a multitude of shapes and it has very highly desirable electrical properties .Through Silicon Via (TSV) technology is emerging as an essential method for allowing circuits on one side of an IC to be accessible from the other. This ability is not only essential for devices requiring covers, such as image sensors and MEMs but for stacking ICs as well. Much has been reported about the interconnecting and stacking of devices, such as, memory-on-memory and memory-on-logic devices.
TSV fabrication is a micro-machining process for silicon. The micro-machining properties of silicon can also be utilized to etch and form features other than vias, such as the ability to etch precise channels which can be used to align and secure the fiber cables in an interposer. The interposer is one of the main elements in short length multimode (MMF) electro-optical transceivers capable of data rates exceeding 10 Gb/sec.
Enabling the 2.5D Integration
Authors: Xie John Y. , Shi Hong , Li Yuan , Li Zhe , Rahman Arif , Chandrasekar Karthik , Ratakonda Deepa , Deo Manish , Chanda Kaushik , Hool Vincent , Lee MJ , Vodrahalli Nagesh , Ibbotson Dale , Verma Tarun 
Published: October 2015

3D IC is the viable revolutionary technology that will enable system-level integration, miniaturization, optimal power management, increased data bandwidth, and eventually reduced system cost. Like any breakthrough technologies, it faces many challenges. Design methodology, integration technology, manufacturing process and new industrial ecosystem are the areas of focus. This paper will discuss these challenges and Altera's 3D integration development effort.
2.5D is an intermediate path to true 3D IC using silicon interposer and TSV (Through-Si-Via) stacking. The 2.5D stacking configuration offers different form factor, interconnect path, and thermal management options than monolithic packages, which could help to reduce system level power and thermal management pressure. It offers silicon level interconnect density, low inductive path and wide IO application. However, it's power delivery system (PDN) could be the bottleneck for the system to perform at the intended bandwidth and speed. Thus, the whole system, IC-Interposer-Package-PCB, must be considered holistically, and trade off study and compensation mechanism development are needed in such complex system level integration.
There are many different 2.5D integration manufacturing flows currently under development. They can be categorized into two major flow options: Attaching interposer to substrate first, which can be called CoCoS (Chip on Chip on Substrate); or attaching device silicon to interposer first, which is also called CoWoS (Chip on Wafer on Substrate). The major challenges are in the areas of manufacturing process window and yield, thin wafer handling, testability and overall cost of the integration process. ,).
This paper will discuss design consideration, manufacturability analysis, Logic/memory devices and silicon interposer interaction, and thermal management to enable the 2.5D integration. System level characterization and correlation with simulations are performed. The challenge of new supply-customer model and industrial ecosystem development associated with 2.5D integration will also be discussed.
Meander Delay Compensation in High-Speed Digital Multilayer Packages
Authors: Frye Robert , Liu Kai 
Published: October 2015

The routing of multi-trace digital signal buses in printed circuit boards often results in mismatches in the lengths of the lines. This results in mismatched propagation time, referred to as “timing skew” in a digital system. A common method that is used to compensate for this is to add meander sections of line to lengthen the signal path length. Many advanced circuit board design tools have the capability to perform this compensation automatically.
Advanced Ball Grid Array (BGA) packages are fabricated using fine-line multilayer laminate substrates or they are built up using multilayer wafer-scale processes. The design tools for these types of packages have evolved from printed circuit board tools and typically use the same methods and principles. It is very common in BGA packages for high-speed digital applications to use meander trace patterns to match the trace lengths of high speed bus interconnections either from the chip to the solder balls or between chips in a multi-chip package.
However, electromagnetic simulation of these packages shows that despite the use of these techniques to match the physical length of the traces, electrical lengths often vary by as much as a factor of two. Examples of such packages are presented and analyzed. The resulting timing skew is not a significant problem in most current applications, since the overall delay is small compared with the clock interval. But with emerging applications pushing well beyond 10Gb/s, timing skew in packages will be an important consideration.
The reasons for the ineffectiveness of meander delay compensation are discussed, and are demonstrated by some simple simulations.
Pd-coated Cu Wire Bonding Reliability Requirement for Device Design, Process Optimization and Testing
Authors: Singh Inderjit , Low Shin , Song Syu Fu , Jung Chen Shih , San Lin Ming , Qin Ivy , Huynh Cuong , Clauberg Horst , Nguyen Son Truong , Chylak Bob , Xu Hui , Acoff Viola L. 
Published: October 2015

One of the biggest technology drivers in the semiconductor industry today is the fast transition from Au wire bonding to Cu wire bonding. The fast adaptation of Cu and Pd-coated Cu (PCC) wire has focused the whole packaging industry to develop understanding, equipment and processes that can produce a more reliable and robust Cu wire bonding technology.
Although the fundamentals of wire bonding technology are very similar between Au and Cu wire bonding, there are a lot of new challenges in Cu wire bonding. Compared to Au wire bonding, Cu wire bonding needs different bond quality measures and metrology. Traditional ball diameter, ball height and shear measurements are not adequate to quantify a Cu wire bonding process. Some of the additional bond quality measures include pad material push out (pad splash), Al layer peel off (pad peel) and crack in the barrier and dielectric layer (pad crack).
Another area that is quite different between Au and Cu is the reliability test requirement. In Au wire bonding, because of the fast intermetallic compound (IMC) growth rate, the HTS test is normally the hardest to pass. Due to the corrosion of Cu wire, the HAST test is the most challenging in Cu wire bonding. Reliability requirements still need more knowledge. In this paper, we conduct reliability tests for devices with 3 sets of wire bonding parameters. The bonded samples have IMC coverage between 94% and 97%, well above the industry level of 80%. The reliability (HAST) test passed for all samples at 96 hours. However, there are some failures in the HAST test at 192 hr. There are many factors that can influence reliability outcome including wire bonding and non-wire bonding related factors. The failure analysis identified two potential causes in our case. In one failure case, an abnormally high Chlorine level and void in molding compound were detected next to the failed bond while no Chlorine and void were detected elsewhere. In the 2nd failure case, the bonded ball seems to be off centered and results in poor bonded ball to pad interface. These two factors will be more tightly controlled in future tests to verify the reliability outcome.
Intermetallic growth and phase transformation, aluminum oxide, and behavior of palladium in PdCu wire bonds are analyzed using transmission electron microscopy (TEM) of dual beam focused ion beam (FIB) thinned specimens. Results are compared to wire bonding measurement and reliability outcome.
Advanced Stepper Through-Silicon Alignment (TSA) Evaluation and Overlay of Distorted Bonded Wafer Stacks
Authors: Shelton Doug , (Charles) Wang C.Y. 
Published: October 2015

Canon Litho Products support Vertical Lithography challenges required by TSV and advanced packaging applications that support “More-than-Moore” advancements. Vertical Lithography challenges include accurately performing backside, infrared alignment to distorted bonded-wafer grids and imaging through thick resist films.
This paper will provide examples illustrating severe wafer distortion that can be experienced after wafer thinning and the impact of overlay and imaging control. This paper will also introduce Canon stepper features that are designed to address Vertical Lithography challenges including the Canon Through-Silicon Alignment (TSA) System and advanced Projection Lens. Grid distortion characterization data and stepper compensation results are presented to illustrate Canon stepper technology performance under severe process conditions.
Control of Package Warpage by Package Substrate Design for Low Profile Package-on-Package Structure
Authors: Furusawa Takeshi , Kawamura Naomi , Furutani Toshiki , Kariya Takashi 
Published: October 2015

In recent years, with increasing demand for high-density assembly in mobile electronics products, a package-on-package (PoP) structure has been standardized. The demand for lowering the PoP profile is getting stronger as consumers demand thinner mobile devices. To assemble a low profile PoP and mount it on a mother board, it is necessary to have a precise warpage control of PoP components, including its bottom package. It is expected that a flip-chip chip-scale-package (FCCSP) with thin mold cap will be used as the bottom package of the PoP in the next 2–3 years. In order to control the package warpage, it is necessary to optimize a large number of parameters related to the package substrate, silicon die and mold compound. Among them, equivalent coefficient of thermal expansion (CTE) of the package substrate is one of the most important factors.
In this paper, control of the package warpage was studied by focusing on the glass-cloth content ratio in the package substrate. Glass-cloth has the lowest CTE among the constituent materials of the substrate, so it contributes to reduce the equivalent CTE of the substrate. To maximize the glass-cloth content, a substrate with a thick core and thin build-up structure was prepared, and the package with thin mold cap was subsequently formed. Compared with a similar package with a conventional substrate structure, its warpage, measured experimentally, was about 20% smaller. Consequently, it was concluded that the glass-cloth content ratio is a key factor to control package warpage behavior in the PoP assembly process.
ULTRA THIN CHIPS STACKING ON TSV SILICON INTERPOSER USING BACK-TO-FACE TECHNOLOGY
Authors: Parès G. , Schnegg F. , Attard A. , Cruau D. , De Crecy F. , N'hari A. , Anciant R. , Klug G. , Luesebrink H. , Martinschitz K. , Karoui C. , Simon G. 
Published: October 2015

Chip-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by on one hand the increase of the die surface and the number of I/Os and on the other hand by the reduction of the vertical dimensions.
In our integration, the chips are reported on a silicon interposer containing copper via-middle TSVs. Two different approaches have been considered to realize chip-to-wafer stacking with respectively 35 and 20 μm ultra-thin dies. The first one is the conventional flip chip (or Face-to-Face, F2F) integration based on Cu/SAC μ-pillar connections while the second is a less classical Back-to-Face (B2F) way based on the realization of a high topology RDL after bonding the chips face up on the silicon interposer using a polymer. This last architecture becomes more and more attractive with the reduction of the chip thickness to ultra-thin dimension and can offer substantial advantages in terms of design flexibility and technology cost.
Chip bonding is one of the first tasks to address: several bonding materials have been tested either on die side using die attach film (DAF) or on bottom interposer side using wafer level spin coated polymers. Then a novel brick consisting of high topology encapsulation and metallization has been fully developed to connect the dies to the bottom wafer enabled by the development of a specific lithography process.
Thermo-mechanical FEM simulation and first reliability assessment have been carried out and support the good mechanical behavior of this integration.
Electrical tests have been also completed that allows comparing the performances of F2F and B2F interconnections in terms of resistances and yield at front side level but also at back side level after TSV exposure.
Back to Face integration can be very attractive in terms of process complexity and cost for ultra-thin chips with limited I/Os counts.