bluuebunny/crossref_metadata_2025_split huggingface dataset:
Modeling of Failure in Aluminum Alloy Braze for a High Temperature Thermoelectric Assembly
Authors: Arifeen S. , Potirniche G. , Elshabini A. , Barlow F. 
Published: October 2015

The objective of this work is to design a commercially viable thermoelectric generator (TEG) assembly that can be used in passenger vehicles to be able to withstand extreme environmental conditions. Since the operating temperatures of the TEGs can reach temperature levels higher than 500 °C, aluminum braze alloys offer a good high temperature solution for die attach. However, the evolution of fatigue damage in the aluminum braze must be understood in order to ensure an acceptable reliability of the TEG.
In this paper, the proposed design of TEG package assembly was evaluated under extreme temperature conditions. Three-dimensional models of full scale TEG were analyzed using finite element analysis (FEA). The failures of aluminum alloy based braze (high temperature form of solder) material in the TEG application was investigated. Low cycle fatigue using direct cyclic approach was considered for the reliability analysis. Continuum damage mechanics approach was used to study the fatigue failure due to power cycling. Different TEG assembly designs were investigated and compared to determine the best possible solution for the extreme environment application.
Package Technology Selection of 28nm High Power FPGA with Pb-Free Solder Bumps: Flip Chip Molded BGA (FCMBGA) versus Traditional Flip Chip Bare Die Package
Authors: Lyakas Michael , Reichman Corey , Jimarez Miguel , Ocampo Romina Mimi , Elberg Aaron , Hasan Altaf , Hale Dierdre , Hamilton Fred , Kim Joon Dong 
Published: October 2015

Selecting the optimal flip-chip package technology for the next generation 28nm FPGA is critical not only to meet reliability benchmarks for Pb-free bumps, but also in meeting the field-use environment requirements for high power devices.
Component level reliability testing was conducted on three separate package types: Bare die flip chip BGA (FCBGA), flip chip molded BGA with capillary underfill (FCMBGA w/CUF), and flip chip molded BGA with molded underfill. (FCMBGA). Testing was conducted independently at two separate sites. Testing included moisture resistance testing (MRT), temperature cycle (JESD22-A104 Condition Level B), and a hybrid test combining 100 hours of unbiased HAST (JESD22-A118A) with temperature cycling.
Reliability monitoring was conducted through multiple means including electrical testing for circuit continuity, CSAM imaging at frequent read points to monitor silicon integrity and underfill adhesion performance, cross-sections for the inspection of bump crack propagation, and FIB analysis of the UBM structure after test completion.
In addition to reliability testing of three flip chip BGA platforms, other usage factors were considered. These include package specific design rule flexibility for passive placement and future generation packaging requirements.
The results of the evaluation demonstrated that bump integrity remained strong for all three package types – showing no cracks after 1,500 temperature cycles, hybrid testing, or MRT. Ultimately, the FCMBGA with molded underfill was selected based on the quality of the bumps after testing, the design rule flexibility for capacitor placement, and improved component protection from mechanical damage.
Thermo-mechanical Stress of Underfilled 3D IC Packaging
Authors: Wang Ming-Han , Wu Mei-Ling 
Published: October 2015

In recent years, there has been a dramatic proliferation of research concerned with electronic products because of more various functions are integrate into the device and product's size has become smaller. As a result of these functional requirements, through silicon via (TSV) was investigated, this are getting considerable attentions not only from reducing the packaging size but also from shortening the interconnection's distance that can achieve the effect of enhancing signal transmission. TSVs are the vertical hole through the stacked IC, and they are also responsible for transferring signals between the ICs. Thus, they can improve the time delay of the signal transduction and allow better electrical performance than stacked ICs with wire bonding technology. However, a review of the literature indicates that electronic components will be affected easily by environmental factors such as humidity, pressure, and temperature. In general, the stacked ICs with TSV structure is easily affected by temperature changes than others factors since each material have different deformation. In very recently, the stacked IC packaging has been primarily concerned with thermo-mechanical loadings than traditional single IC packaging, which leads some problems such as via cracking, die cracking and interfacial delamination and so on. The above problems not only affect the performance of the device but also lead the device fail. Hence, most of the studies [1–9] are focus on discussing thermal mechanical loading with simulation method. Some of them discuss the relationship between the TSV shape and the stresses [4, 5]. In addition, most of people just build local TSV structure to do their research [4–9]. Although it can save more time but it also increase the error percentage with real situation. And this paper build the three dimensional four layers stacked IC packaging model from Hsieh [1]'s paper which can more close to real situation. And setting the structure to be simulated from the temperature 150°C to −50°C which is as retreat temperature.
This paper use ANSYS software which is based on finite element theory in order to reduce time used and save money, as finite element simulation can provide results more quickly and cheaply than experiments. Moreover, the research mainly analyzes the average value of maximum von Mises stress in TSVs and chips. Besides, this paper will sort out geometries and material properties which will serious affect von Mises stress value by design of experiments (DoE) analysis. Through the DoE analysis, the critical factors are selected as main design factors to reduce the von Mises stresses. This study can provide the significant information to effectively design the products and increase the reliability. This information can also eliminate the testing time.
Stencil Printing Process Guidelines for 0.3mm Pitch Chip Scale Packages
Authors: Whitmore Mark , Schake Jeff , Ashmore Clive 
Published: October 2015

With the form factor of electronic assemblies continuing to shrink, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged.
For the stencil printing process, todays accepted stencil area ratio rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components.
With aperture geometries shrinking, anything which can influence solder paste transfer efficiency has to be considered. New process technologies such as ultrasonic squeegees have emerged in recent years to assist the process with some degree of success. However, something which is often overlooked in terms of stencil design influence is that a square shaped aperture, size for size, has a volume which is 21.5% than its circular counterpart. In a process where quite literally every solder particle that can be printed is becoming significant then this fact can be utilized to the process engineer's advantage.
In this paper, the merits of stencil aperture shape, in conjunction with ultrasonic squeegees are investigated with the purpose of developing stencil printing guidelines for ultra-fine pitch components such as 0.3mm pitch CSP's.
Improvement of Back-Side Cosmetic Defects And Wafer Strength
Authors: Calero-DdelC Victoria L. , Popova Irene , Bicknell Aaron , Indyk Richard , Sullivan Joe , Fitzsimmons John 
Published: October 2015

The continued challenge to keep up with Moore's law with aggressive device scaling, and shrinking wiring dimensions established perpetual need for novel materials and dictates ever tighter semiconductor process fidelity. Despite large progress with reducing defect densities on the device side of Si wafers, considerably less attention is being paid to the wafer back-side. Back-side wafer defects have been shown to reduce yield by leading to die breakage during packaging processes. Scratches and voids formed on the back-side of the wafer during various manufacturing processes have been shown to create weak spots on the wafer, which can act as initiation points for die crack formation and propagation.
In this paper, we present the technical details of a back-side wet etch clean process which helps reducing back-side defect densities significantly. The process is set up on a single wafer wet etch tool at IBM's East Fishkill 300 mm wafer fabrication facility. The process removes the outer back-side layer of the silicon wafer which has become defective and damaged as a result of previous processing steps. This new defect removal process increases die strength, which is measured as wafer mechanical strength, and removes surface defects from the back-side of the wafer.
Our results show that removal of 15–30 microns from the wafer back-side reduces the amount of cosmetic defects on the back-side of the wafer by 90%, while increasing die strength by 60%. The effects of the back-side wet etch clean process on the wafer optical appearance and mechanical properties were characterized, and supporting data such as atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), defect inspection, thermal interface material adhesion test, and die strength is included. Results from package level modules indicate an increase in reliability compared to the uncleaned Si back-side. It can be concluded that wet Si removal process described in this paper is a viable method to reduce the back-side defect density with an associated increase in final module product yield.
Photopatternable Laminate BCB Dielectric
Authors: O'Connor Corey , Barr Robert , Calvert Jeff , Choubey Anupam , Gallagher Mike , Iagodkine Elissei , Oh Joon-Seok , Politis Andrew , Wang Kevin 
Published: October 2015

Divinylsiloxane-bis-benzocyclobutene (DVS-bis-BCB, or BCB) is a well-known dielectric material that has been used in high volume manufacturing for many years (Dow's CYCLOTENE™ 3000/4000-series Advanced Electronic Resins). Typically, the application of these products has been by spincoating or spray coating of the dielectric material from a solvent-based formulation. However, for certain applications - for example, those involving large area, square substrates such as glass panels - it is desirable to be able to apply the BCB-based dielectric material using a dry film coating process, such as vacuum or hot roll lamination. In this paper, we describe the concept of creating a laminate film utilizing DVS-bis-BCB as the primary dielectric material component. In creating the laminate dielectric material, it is important to maintain the unique combination of thermal and electrical properties of DVS-bis-BCB, including high thermal stability, excellent copper barrier properties, low moisture uptake, low dielectric constant, and low dielectric loss. However, DVS-bis-BCB alone is too rigid to produce a high quality laminate film, therefore, it is necessary to modify the formulation to improve flexibility and lamination quality. As the flexibility of the film is increased, higher fracture toughness (K1C) and higher elongation values should result. Novel formulation adjustments to the base DVS-bis-BCB polymer system have resulted in an experimental laminate dielectric product that will be the focus of this discussion.
Depending on the application, laminate films can vary in thickness from 2μm to 50μm or even thicker. A typical laminate film construct includes the BCB-based dielectric film with a base sheet of an optically-clear polyester (PET) film and a polyethylene (PE) cover sheet. The DVS-bis-BCB-based laminate can be tuned with appropriate additives to either pattern with UV exposure from a tool such as a Süss MicroTec Mask Aligner (50mJ/cm2 – 100mJ/cm2 exposure energy) or laser pattern with a tool such as a Süss MicroTec 248nm Excimer Laser. Aspect ratios of 1:1.5 have been achieved with a photopatternable DVS-bis-BCB film and aspect ratios of &gt;1:1 are possible with a laser-patterned film. Beside the photopackage added to the film to enable UV patterning, toughening additives have also been incorporated to enhance the fracture toughness (K1C) and elongation properties. K1C for the laminate has been improved to 0.55Mpa·m1/2 vs. 0.35Mpa·m1/2 for DVS-bis-BCB. Elongation has been improved to 13% for the laminate vs. 8% for DVS-bis-BCB. Electrical properties are similar to DVS-bis-BCB. An additional attribute of the laminate dielectric is the ability to tent over and protect vias. Vias &gt;100μm diameter have successfully been tented with a 10μm thick film. A DVS-bis-BCB-based laminate has been demonstrated with continued optimization and evaluation to follow.
Electrical Characterization of Fibre-Reinforced Plastics by Atmospheric Plasma Technology
Authors: Rene Schramm , Thomas Reitberger , Joerg Franke 
Published: October 2015

In previous investigations the additive metallization of conductor paths on thermoplastic substrate materials using printing technologies (Inkjet, Aerosol-Jet) was analyzed. Major disadvantages of printing technologies are the double-stage process chain divided in printing and sintering and the low current-carrying capacity of the printed structures. Accordingly, printed conductor paths are mainly used for sensor and control currents.
The plasmadust technology, based on a cold active atmospheric plasma beam, offers the possibility for additive metallization of copper circuit paths on a sandwich material. The process consists of a nano and micro scale metal powder (particle size 0.1 μm to 20 μm), which is melted in the plasma nozzle by a highly energetic nitrogen gas. Based on the kinetic and thermal energy of the nitrogen-metal-compound the circuit paths are generated in a thermo-mechanical interconnection on the substrate surface. The plasmadust technology is characterized by a one-stage process chain, a very high coating speed (up to 50 m/min) and a high current-carrying capacity of the generated conductor structures. Hence, it is possible to transfer high currents, e. g. for illumination applications. Additionally three-dimensional substrates (3D MID) can be processed by handling with an industrial robot.
In the investigations copper circuit paths on sandwich materials generated with the plasmadust technology were characterized. In this research work the adhesion of the layers and the current-carrying capacity of the copper structures were analyzed. Secondly the specimen were tested in selected reliability studies, a temperature-humidity (85 °C/85 % r.H.) and a temperature-cycling-test (−40 °C/+125 °C). With the first one the influence of moisture absorption of the sandwich material (up to 7 %) to the adhesion of the copper circuit paths is analyzed. With the second one the compound of the substrate and the additive metallization is qualified during thermo-mechanical stress. In conclusion the additive metallization of circuit paths on sandwich materials using plasmadust technology is qualified to mass production as well as different passivation possibilities of the generated structures will be presented.
Reliability of Multi-Layer Wiring Board Embedded with Two Dies in Stacked Configuration
Authors: Munakata Koji , Ueta Nobuki , Okamoto Masahiro , Onodera Kumi , Itoi Kazu , Okude Satoshi , Nakao Osamu , Tessier Theodore (Ted) G. 
Published: October 2015

As electronic devices decrease in size and increase in functionality, their surface-mount components grow in number. This trend created a need for securing appropriate space in and on a wiring board to accommodate necessary components. Conventionally, dies are mounted on a wiring board. Much effort is spent for space savings. We have come up with a structure to include dies inside a wiring board and succeeded in fabricating the board in which two dies are embedded in a 3D stacked configuration. This new structure shrinks the foot print size and thus contributes to higher density and functionality of a semiconductor package and SiP. In addition, since the base material is polyimide, this board is as thin as 0.45 mm with two WLP (Wafer Level Package) dies (3 mm x 3 mm x 0.085 mm) embedded between any of 9 wiring layers. The module level warpage on the both sides of this board is 0.035 mm, so it is possible to mount components on the both sides.
This board was fabricated based on our WABE technologyTM (Wafer and Board level Embedding technology) that includes a single step co-laminating process and embedded technology using conductive-paste-filled vias for establishing z-axis interlayer electrical connections. The conductive paste formed intermetallic compound with the copper foil and the via showed stable electrical connections by metallic bonding. Copper pads were fabricated on the dies by a wafer level process in advance. The polyimide-based films were laminated with adhesive and the dies were embedded. At the same time, electrical connections were established. This method enables the production of an embedded board by one-time curing after the alignment and fixing of necessary layers. We applied this method to the new structure that includes two dies in a 3D configuration to achieve a simple fabrication process using the single step co-lamination process.
We evaluated the reliability of this board as below. The electric resistance was measured after various reliability tests including Temperature Cycle Test, Temperature Humidity Bias Test and Highly Accelerated Stress Test following a moisture sensitive reflow test (based on IPC/JEDEC J-STD-020 Level 3). From the results, there were no major defects observed in the test boards, either visually or functionally.
This two-die embedding technology helps to realize the miniaturization and contribute to higher functionality of semiconductor packages and SiPs.
A Case Study of the Reliability of Copper Bond Wires In Plastic Encapsulated Integrated Circuits
Authors: Turner Ken 
Published: October 2015

Sixteen plastic encapsulated integrated circuits were initially received as part of a root-cause failure investigation, twelve of which contained copper bond wires and the other four containing gold bond wires. It was reported that eight of the integrated circuits had failed in the field with intermittent or complete malfunction of the components. Electrical testing confirmed the reported failure and found temperature sensitive, intermittent open circuits on various pins coinciding with the sample history.
C-Mode scanning acoustic microscopy (CSAM) was performed on the devices, with each sample exhibiting varying degrees of delamination between the lead-frame and the plastic encapsulant. The backside of the package was polished into the underside of the lead-frame to preclude the introduction of any contamination due to chemical decapsulation. This allowed the mechanical removal of the leads from the package and inspection of the stitch bonds. Scanning electron microscope (SEM) inspection revealed that the copper stitch bonds had corroded to some extent (ranging from mild corrosion to complete consumption of the stitch bond) in each of the examined bonds, whereas the gold stitch bonds were unaffected. Overall inspection of the leads identified chlorine contamination along the delaminated interface.
Fine Pitch Cu Wire Bonding Capability – Process Optimization and Reliability Study
Authors: Qin Ivy , Xu Hui , Huynh Cuong , Chylak Bob , Abe Hidenori , Kang Dongchul , Endo Yoshinori , Osaka Masahiko , Nakamura Shinya 
Published: October 2015

Wire bonding has been around for over 70 years and it is still growing. The most recent advances in wire bonding are the wide proliferation of fine pitch Cu wire bonded applications and the development of fine pitch Cu capability extending to the newest technology nodes. Around 2008, fine pitch Cu wire bonding started to take off driven by the skyrocketing Au price. Since then, Cu wire bonding capability has improved dramatically so that today's advanced technology devices such as 28nm and 20nm nodes are being bonded with Cu wire including Pd coated and AuPd coated Cu wire. It turns out that not only is Cu wire cheaper, but it is more suitable for high I/O counts, and fine pitch advanced node applications due to its better electrical and mechanical properties.
This paper examines the most advanced Cu wire bonding capability using a Cu optimized process called ProCuTM process. 40um pitch and 35um pitch capability are demonstrated using this new ProCu process. Process responses such as process bonding windows, intermetallic coverage (IMC), and free air ball size control are studied in detail. The ProCu process achieved fine pitch capability for 40um as a robust production process and it also shows that 35um pitch with 13um (0.5mil) wire is a possibility using the latest technology.
The JEDEC Reliability test has been a challenge for Cu wire bonding especially for fine pitch applications. As part of this paper, we also examined reliability aspects of fine pitch Cu wire bonding. TEM analysis was used to understand the major factors that affect Cu wire bonding reliability.
Low Cost Glass Interposer Development
Authors: Chen Yu-Hua , Hsu Shaun , Ray Urmi , Shenoy Ravi , Lai Kwan-Yu , Shorey Aric B. , Lu Rachel , Thomas Windsor P. , Hu Dyi-Chung 
Published: October 2015

For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, managing the substrate warpage becomes critical. Traditional organic substrates may face several challenges for high density I/Os with very fine line interconnections. Glass is one of the candidates that can be used in substrate industry. The infrastructure of glass for LCD industry has already been developed for many years. Glass also has several superior properties than other substrate candidates, such as large panel size availability, adjustable CTE, high modulus, low dielectric constant, low dielectric loss and high insulating ability.
In this paper, we successfully demonstrate early manufacturing feasibility of glass substrate with 4 build-up layers starting with a thin glass panel of thickness of 200μm in 508mm μ 508mm panel size format and under the IC substrate manufacturing environment. Fabrication and electrical results of a test vehicle are documented. The test vehicle includes daisy chains that are connected with 100μm diameter through glass via (TGV) in a 200μm thick glass. The laser via in via technology was adopted for double side electrical connection. The copper line width/space of 8/8μm was demonstrated. The total thickness of 4 layers test vehicle is about 390μm. The warpage of glass in comparison with an organic substrate (BT) with 200μm core thickness is 3X better. Further work is needed to develop, fine tune and assess the detailed manufacturability and reliability concerns.
Based on this work, it is clear that the potential of glass in IC packaging and integration is tremendous in diverse applications for substrate warpage enhancement.