bluuebunny/crossref_metadata_2025_split huggingface dataset:
Study of Factors Which Influenced to Bump Shape and Voids in Bumps during Bump Formation with Solder Paste
Authors: Ishikawa Masayuki , Uno Hironori , Yamaji Takashi , Uesugi Ryuji , Masuda Akihiro , Hirano Shingo , Mawatari Fuyumi , Tanaka Natsuko , Okada Kohki 
Published: October 2015

Regarding to inner bump formation using solder paste for FC-BGA and FC-CSP, the voids and abnormal bump shape generation are undesirable problems to achieve high quality assembly. The solder pastes which contain small solder particle and flux are applied to wafer bumping and substrate bumping method. However, as the bump pitch becomes tighter, the influence of those problems gets more serious especially for yield issue.
In this study, we tried to solve the following issues 1)voids generation using 99.3mass%Sn-0.7mass% Cu solder paste and other alloys, 2)the dint bumps generation on the top of bumps using 95mass%Pb-5mass%Sn paste and 3)the needle and plate like intermetallic compound generation on the top and side of bumps using 96.5mass%Sn-3mass%Ag-0.5mass%Cu paste and 95.5mass%Sn-4mass%Ag-0.5mass%Cu paste.
In terms of 1), it was available to understand when and where voids were generated by in-situ soft x-ray observation, and we could construct our original consideration why voids were generated during bumping process. In terms of 2) and 3), it was found that some kind of impurities affected on the dint, needle and plate like IMC generation. Furthermore, we tried to understand from the influence of reflow profile.
By understanding these defects, we believe we can bring benefits to operating solder paste for printing method.
Proven Cleaning Technology Solutions for Lead-Free Micro-Bumping Processes
Authors: Pollard Kimberly D. , Gilbert Nichelle , Pfettscher Don , Hochstetler Spencer 
Published: October 2015

Opportunities for developing new and enabling packaging schemes are being pursued as part of device improvement strategies for electronic products. Processes such as embedded technologies in wafer level packaging and 3-D chip architecture schemes open up opportunities for realization of a variety of package configurations. As a result, there are many opportunities to impact both device performance and the processes used to create them.
In the area of electroplated solder application, one area of growing interest is cleaning technology. There is a need for an integrated process to fabricate defect-free copper pillars with lead-free caps and lead-free solder plated bumps compatible with advanced packaging schemes and with improved yields and reliability. Photoresist removal and surface preparation have been identified as critical to the success.
In familiar and widespread technology using 150 micropitch solder bumping, the introduction of RoHS rules for lead-free solder bump compositions, (SnAg, SnAgCu), proceeded in the absence of an integrated and tailored process capable of defect-free surface preparation. It was relatively simple for solder bump compositions in many devices to be converted to lead-free alloys. However, new challenges continue to arise in higher volume fabrication of SnAg micro-pillars (micro-pillars) or copper micro-pillars with lead-free solder caps as the bump pitch approaches 25 microm with aspect ratios of 1:1 or 1.5:1. Individual processes that are involved in the total integration, including (1) dielectric cleaning steps, (2) PVD seed Ti and Cu deposition, (3) electroplating, (4) thick photoresist application and patterning, (5) photoresist removal, (6) associated descum processes, and (7) copper seed metal etch steps, have been challenged to meet the demands. New geometries, higher aspect ratios and very dense solder bump arrays have created further challenges for these processes, stretching the older 150 microm technology beyond its capability. The focus of this paper is to identify a reliable route to defect-free copper micro-pillars with lead-free caps and lead-free solder plated micro-bumps after photoresist removal in applications compatible with advanced packaging schemes and with improved yields and reliability.
TGV Microfabrication Technology for 3D Packaging
Authors: Takahashi Shintaro , Schmidt Christian , Dittmann Leander , Hoyer Svend , Chaize Adrien , Ono Motoshi , Kitaoka Kenji , Tatsukoshi Kentaro , Konishi Shoichi 
Published: October 2015

Glass is expected to be applied to a core material for panel size interposer for 3D package system nowadays. The most important challenge for glass as an interposer is the development of through hole formation with cost-effective and high-throughput. Several through hole drilling technologies such as wet etching, deep reactive-ion etching, sandblasting, laser ablation and the use of photosensitive glass have been studied and reported so far. However, the glass microfabrication technology combining both high-throughput and large area processability have not been reported yet.
This study explored the new glass fabrication method by means of electrical discharge to realize high throughput and fine pitch hole drilling. An alkali-free glass substrate was used. Focused and controlled electrical discharge induced dielectric breakdown of glass material and also created Joule heat induced ablation and ejection of glass. Approximately 50 – 60 micron in diameter through hole was made. The result shows, even serial process can have a potential for high high-throughput solution, because this phenomenon can complete as an ultrashort process time of 1msec or less. In terms of fine pitch processability, 100um pitch hole drilling was confirmed.
In this study, several glass fabrication technologies were compared by SEM and optical microscope observation for hole shape characteristic. Additionally a potential of industrialization and fine pitch hole drilling were considered. This study pointed out necessary development subjects towards an application, glass core material for 3D interposer substrate.
Development of Substrates for Through Glass Vias
Authors: Shorey Aric , Pollard Scott 
Published: October 2015

Through-substrate vias are critical for 3DS-IC integration. The choice of glass as an interposer substrate, TGV, present some interesting challenges and opportunities, making glass a compelling alternative to silicon.
There are two primary challenges to begin building a precision interposer in thin glass. The first is high quality thin glass wafers (300 mm OD, thickness 0.05 to 0.10 mm, warp and TTV of 30 μm and 1 μm respectively). The second challenge is developing a process capable of providing small (5–10 μm) precision vias in a cost-effective way.
“Glass” represents a large class of materials with a wide range of material properties. The first step in developing TGV is to identify the most appropriate glass composition for the application, which furthermore defines important properties such as coefficient of thermal expansion (CTE) and other mechanical properties, chemical durability and electrical properties.
The manufacturing process used to develop the glass has a significant impact on quality and manufacturability. Fusion formed glass provides a solution for high volume manufacturing supply in an as-formed, ultra-thin, pristine glass manufactured to tight tolerances, and avoids the issues associated with polishing or thinning. The supply of 50 μm to 100 μm as-formed ultra-thin glass wafers can compare very favorably in cost relative to polished or thinned glass as well as thinned silicon wafer.
While there are many technologies that have demonstrated vias in glass, challenges relating to via size and pitch, wafer strength and reliability remain to be resolved. However, substantial progress has been made to meet these challenges. Specific characterization data from some of these processes to demonstrate vias on the order of 10 μm diameter with a 100 μm glass thickness in alternative glass materials will be presented.
Enabling Packaging Houses to Achieve 3D Integration without Interposers
Authors: Leal Jeff , Robinson Marc , Pangrle Suzette 
Published: October 2015

The growth of small portable consumer electronics has increased the requirements of creating densely stacked packages with ever decreasing footprints while still increasing storage capacities as well as accessible memory. Traditional approaches to create these packages have included wire-bonding and Package on Package (PoP) as well as through Silicon Via (TSV). All of these methods present a solution to current system requirements, each with its own drawback.
This paper will discuss a novel method in which a vertical 3D die stack can be created of similar an in some cases dissimilar die. The final 3D structure of stacked die will present no XY offset between any level of the die stack achieving the smallest possible form factor. This method also eliminates the requirements of creating an interposer for the electrical connection between layers.
The final result is a completely vertical die stack with electrical connections drawn on the outside edges of the die stack which adds &lt;400um total in either the X or Y axis of the package. We will discuss required equipment, the best known methods and the optimal materials required to achieve the final product as well as JEDEC reliability data proving package robustness, such as Temperature Cycle, biased-HAST and High Temperature Storage.
Development of Lead Free Plating Chemical for Various Applications
Authors: Hatta Takeshi , Ishikawa Atsushi , Katase Takuma , Masuda Akihiro 
Published: October 2015

Flip chip connection has been applied to a lot of applications to shorten the connection length for high performance. Solder bumping is one of the key technologies for flip chip connection, and its quality strongly brings large impact on the reliability after packaging.
Electroplating is one of the methods to form solder bumps. And Sn-Ag is considered as the first candidate of lead free alloy for electroplating method. We have released Sn-Ag plating chemical and it has been used by many customers in the world.
In the future, flip chip technology will progress to further miniaturization and high integration with the new technologies such as Cu pillar and Through Silicon Via (TSV). At that time, further variations of alloys are necessary for electroplating method to meet various requirements. Even for Sn-Ag plating chemical, higher plating rate is required to improve productivity in mass production.
In this time, we have developed new Sn-Ag high speed plating chemical based on our conventional technology. Furthermore, we have succeeded to develop Pure Sn and Sn-Cu chemicals for bumping method to meet customer's requirement. Sn-Cu is considered as a good candidate for bumping alloy to achieve high reliability, but the chemical stability is not so good. Therefore, we successfully modified the Sn-Cu chemical and extended chemical stability.
We will update our current status about high speed Sn-Ag plating chemical and other chemicals like Sn-Cu and pure Sn in this time. By using these binary alloy chemicals, we are able to produce Sn-Ag-Cu solder bumps by stacking Sn-Ag and Sn-Cu. And it can bring further variation for bumping alloys.
Super Fine Lead-Free Solder Powder for Fine Pitch Bump Applications
Authors: Uesugi Ryuji , Uno Hironori , Ishikawa Masayuki , Masuda Akihiro , Muraoka Hiroki , Kawamura Yousuke , Nakagawa Sho , Kuba Kanji 
Published: October 2015

We have successfully developed super fine lead-free and low alpha solder powder, which contains more than two elements by the method of wet chemical reduction. The size (D50) of super fine powder is around 2–3 micrometer to meet finer pitch assembly in the near future. This new method made it available to synthesize various compositions of solder powder like Sn-Ag, Sn-Cu, Sn-Ag-Cu, etc. Also, this method achieves very high yield compared to a gas atomization method.
A solder paste for printing method composed of the fine solder powder has a superior printing ability because of the unique powder shape. The powder shows anisotropic shape, and it can make printed figure excellent after printing without bridge and coplanarity issues for finer pitch applications. With our super fine solder paste, we will be ready for &lt;100um pitch of solder bumps which will come in a few years.
Furthermore, the super fine powder is applied to the Cu pad pre-coat. The solder paste for pre-coat composed of the super fine powder shows an excellent coverage and solders flatness on the outer pad after reflow.
Passive Flexible-Substrate Blast Sensor Array
Authors: Phillips Stephen M. , Allee David R. , Lakamraju Narendra 
Published: October 2015

We have developed a design for a wearable passive blast sensor array to detect the peak shock experienced by personnel exposed to high energy events. The sensor is fabricated on a flexible substrate using a MEMS process. The design includes an array of sensors, each element of which is triggered at a different pressure level and which records the peak pressure by means of a permanently deformed diaphragm. The elements can be integrated with a flexible electrophoretic display or can be interrogated externally with an electronic reader.
A key application is in predicting the exent of traumatic brain injury for military peronnel exposed to explosions in a battlefield environment. Peak blast information can assist in prioritizing and determining the appropriate battlefield treatment. The flexible substrate allows integration into personal armor or clothing and the passive nature of the sensor ensures a very long shelf life and reduces cost and maintenance.
Details of the sensor designs and process flows for their fabrication are described. Prototype sensors have been fabricated and the fabrication characterized. Also included are simulation results for the preforamnce of the arrays. Finally, preliminary pressure blast test data for indivdual sensor elements are presented.
Ultra High 3D Capacitors Values with High Volume Efficiency and Outstanding Stability
Authors: Bunel Catherine , Murray Franck 
Published: October 2015

IPDIA's primary effort is to develop innovative 3D technologies to integrate Passive Devices .One of their key technology drivers is the trench high-density capacitor.
After introducing the 250nF/mm2 in mass production, it's now the turn to launch outstanding performances with a new worldwide record of 550nF/mm2.
With the advanced packaging solutions using very thin dies stacking ,combining a high level of capacitance integration and high volumetric efficiency, this achievement will enable to extend the range of high reliability Silicon Capacitor values up to 10 μF in a package size 3.4mm*2.4mm*1.4mm and even smaller .
This paper will provide the details to prove that the former ambitious target of 2 μF/mm3 is now close to reality.
Micromachined High Density Embedded Capacitor Technologies for Silicon Interposers
Authors: Beal Aubrey , Baginski T. , Dean R. , Hamilton M. 
Published: October 2015

We describe our work on micromachined, large surface area, thin and high-density capacitor technologies targeted at the growing interest and applications for embedded passive devices in thin silicon interposers. As integrated circuit I/O number, speed and density increase, chip current requirements grow and margins shrink leading to the requirement of large, distributed decoupling capacitance as close to the load as possible. The simple fabrication methods used to form our embedded capacitors can be used to alleviate the increasing demand for low impedance power distribution networks in high-density integrated electronic systems while maintaining required signal integrity through the interposer.
We have investigated silicon dioxide-based capacitors of varying oxide thickness, with and without integrated parallel metal Schottky barrier capacitors or pn junction capacitors. These device structures have been fabricated using standard MEMS processing techniques such as DRIE and thermal oxidation to enhance the available surface area and increase capacitance per chip foot-print.
We have characterized the performance of the various capacitor structures using both time and frequency response measurements. Time response measurements are performed using a capacitive charge and discharge ringdown test. High frequency (&gt; 1GHz) performance characterization and modeling of these devices has also been performed. In general, measurement results correlate with simulation. We will describe the challenges associated with fabricating, testing and integrating these passive devices.
On-going measurement and simulation work that will be reported includes modification of device structures to evaluate the range of achievable capacitance density, minimize leakage current, minimize effective series inductance / resistance, and achieve thinned capacitor structures integrated into our Si interposer technology that incorporates electroplated through-Si vias (TSVs) of varying sizes and densities. The results of these efforts will be presented.
Active and Passive Devices Embedded in Laminate-Based Multilayer Board
Authors: Okude Satoshi , Itoi Kazushisa , Okamoto Masahiro , Ueta Nobuki , Nakao Osamu 
Published: October 2015

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging.
Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.
A Methodology for Chip - Package Interaction (CPI) Modeling in 3D IC Structures
Authors: Dhandapani Karthikeyan , Syed Ahmer , Lin Wei , Nakamoto Mark , Zhao Wei , Radojcic Riko 
Published: October 2015

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require an ability to model and evaluate the interactions and risks.
In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance. Examples of these effects are ball cracking, ILD/ELK cracking or delamination and shifts in the behavior of sensitive devices such as transistors in analog circuits.
Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates a seamless interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. This package level simulator uses a nested sub-modeling approach for detailed extraction of stresses at different locations within BEOL layers of die, u-bumps, and C4 bumps from package level simulations. Additionally, it allows complete flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online.
The capabilities of this modeling approach are demonstrated by studying the impact of design and material parameters on stresses at various interconnect structures constituting a typical 3D IC stack package. An example of active silicon layer stress correlation from package level model and die-level model will be presented, thus validating this overall modeling flow.
Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking
Authors: Choubey Anupam , Anzures E. , Dhoble A. , Fleming D. , Gallagher M. , Lee I. , Oliver M. , Qin Y. , Truong C. , Wang Z. , Woertink J. 
Published: October 2015

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance.
Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.