bluuebunny/crossref_metadata_2025_split huggingface dataset:
Analysis of crack length and crack position in the Solder Joints of High Power LEDs by Transient Thermal Measurements and Finite Element Simulations
Authors: Kandaswamy Shri Vishnu , Tetzlaff Ulrich , Derix Robert , Elger Gordon 
Published: October 2015

In SMT devices, the CTE mismatch between the substrate and the component makes the solder joint region the most susceptible to crack. Due to temperature cycles experienced by the device during field life, the solder region often cracks leading to system failure. For high power devices that have to dissipate large thermal load through the solder joint, it was shown in earlier publication that transient thermal analysis is very sensitive to determine the solder joint reliability. For Transient Thermal Analysis the forward voltage (Vf) of the device is measured after switching the thermal load. By normalizing the transient Vf plots, an algorithm was introduced which eliminate the influence of k factor (a linear factor between Vf and T) and thermal load (Pth) for calculating the relative thermal resistance [1].
In this paper experimental studies are presented were the reliability of the solder joint of high power ceramic LED packages is investigated. The LEDs are soldered with two different lead free solders (SnAgCu 305 and Innolot FL-640) on Aluminum Insulated Metal Substrate (Al-IMS). Test batches were prepared and exposed to temperature cycles at −40°C / +125°C. Transient thermal measurements were performed directly after assembly and after specific cycle numbers. It is seen that as the temperature cycle number increases, the thermal signal corresponding to the solder region changes. After appropriate data processing the increase of the relative thermal resistance between the initial signal at ‘0’ cycles and ‘n’ cycles is calculated. Based on the increase of the relative thermal resistance a failure criterion is introduced and the cumulative failure probability is calculated. We observed a higher creep resistance for the test group soldered with Innolot FL-640 compared to the test group soldered with SAC 305.
Transient finite element analysis (FEA) is applied to simulate the experimental curves. The influence of crack length and crack position in the solder joint region of a high power ceramic LED used for automotive applications is analyzed and it is shown that the crack length and position has a significant impact on the relative increase in thermal resistance. Within the simulations the crack length and crack position is varied to match the peak-height difference and peak shift of the experimental curves by simulation. It is observed that the increase of relative thermal resistance strongly depends on the position of the crack. Therefore it is shown that the relative thermal resistance increase takes place not only within the solder joint but also within the dielectric layer of the Al-IMS. It is show that as the crack propagates from the exterior to the interior region of the solder joint, the effective area available for heat flow through the Al-IMS is significantly reduced and adds onto the increase of the thermal resistance within the solder joint.
Thermal and Reliability Demonstration of a Large Die on a Low CTE Chip Scale Package
Authors: Yamada Tomoyuki , Fukui Masahiro , Terada Kenji , Harazono Masaaki , Fujisaki Teruya , Iruvanti Sushumna , Carey Charles , Pan Yi , Reynolds Charlie , Sikka Kamal , Sundlof Brian , Toy Hilton , Wagner Rebecca 
Published: October 2015

In organic packages, large die and large laminate body sizes are susceptible to CTE (coefficient of thermal expansion) mismatch driven warpage, stresses and strains, which can result in C4 white bumps, micro Ball Grid Array (BGA) interconnection issues, and package thermal reliability concerns. Low CTE carriers minimize these concerns and allow increased chip join yields and improved package reliability. Modeling and characterization of warpage, chip and micro BGA integrity and electrical characterization of a low CTE, Chip Scale Package (CSP) were described in an earlier paper.
In this paper we report the progress on the next phase - thermal and chip package interaction (CPI) evaluation of a single chip CSP designed for use with Multi-Chip Modules (MCM). Assembly, characterization, thermal performance and reliability stress results of these low CTE CSP Single Chip Modules (SCMs) are described. Measured warpage values are compared with thermo-mechanical modeling results. Demonstration of a dual CSP design and assembly with large dies is also presented.
The successful demonstration of the material set, bond and assembly processes, and reliability of a large die, high I/O CSP, followed by the demonstration of a dual CSP on a multi component carrier, are fore-runners to the development of multi-CSP MCMs.
Fine pitch Copper Pillar interconnection with C4 (Mass Reflow) Processing
Authors: Roa Fernando 
Published: October 2015

Flip chip interconnection design and process capability has been extended with the use of copper pillar, specially for finer pitches, beyond what was possible with area array and standard C4 reflow and solder bumps. Many trends in device packaging are fueling this trend, specially the needs for thin packaging, increased function integration, challenging thermal, mechanical and physical specifications.
In terms of processing, devices using Cu Pillar are most commonly assembled using thermo-compression bonding due to sizable challenges in extending the conventional mass reflow solution, typical for solder bumps. TC is specially recommended for handling very thin die in sparse or peripheral bump layouts, which are a predominant share of all devices converting to Cu pillar, where a bonding head is used to both hold the die flat and in true alignment with the substrate while supplying the thermal energy necessary to complete the interconnection. This process most often also requires the use of a non-conductive paste/film for stress absorption in recognition to the fact that underfill materials have great limitations in filling the underdie cavity.
In this paper, we explore avenues to extend the current processing envelope for Cu pillar bumped devices using C4 reflow. Benefits of this approach are shown as decreased cost of ownership for materials, lower fixed costs due to using mostly depreciated equipment. Yet, challenges in defining new design rules, reformulating materials and extending process flows are among some of the barriers for further adoption of this solution in production
Wafer Dicing Using Dry Etching on Standard Tapes and Frames
Authors: Lishan David , Lazerand Thierry , Mackenzie Kenneth , Pays-Volard David , Martinez Linnell , Grivna Gordy , Doub Jason , Tessier Ted , Burgess Guy 
Published: October 2015

To meet the changing demands of consumer product form factors, there has been a steady shift to thinner and smaller semiconductor die, both of which increase the challenges for die singulation. The traditional approach of saw dicing is facing new limitations due to die damage and throughput. Compounding these issues is the finite width of saw blades, saw blade loading from clearing multiple materials, and orthogonal layout restrictions. Laser dicing has been introduced to address some of these issues, but faces other limitations such as damage from the heat affected zone, ablation residues, throughput, and material incompatibilities (changes in transparency and absorption in the street). In some cases, a combination of both saw and laser has been utilized to surmount some of the technical obstacles.
The recently introduced approach of front-side plasma singulation circumvents many of the limitations of saws and lasers. The technology presented in this work uses standard dicing tape and frames, is through-wafer complete die separation, and does not involve a subsequent wafer thinning or die cleaving step. Our approach utilizes lithographically defined singulation lines with typical widths of 10–15μm, and delivers chip/crack-free edges with low-stress rounded corners. The parallel nature of this singulation method enables non-orthogonal and non-linear singulation streets allowing die layout and design flexibility not achievable by saws and/or lasers. As a consequence, plasma singulation produces increased good die per wafer through better wafer area utilization, lower die failure (reduced corner stress with rounded geometry), and flexibility in die placement near wafer edge on larger die. One of the unique advantages is that this technology can be implemented without addition of any new masking layers but instead the use of the existing passivation, metals and/or upper dielectrics as masks.
Implementing this technology across a wide range of die applications such as power, memory, logic, imaging sensors, LEDs, and MEMS must address a diverse range of variables such as compatible materials, bond pads/bumps, and backmetal. For dies with backside metal, a non-etch based method to allow full die separation while the dies are still attached to tape has been demonstrated.
PMV (Plating Mold Via) interconnection development in molded SiP modules
Authors: Yoo Do-Jae , Ryu Jong-In , Oh Gyu-Hwan , Park Yong-Choon , Lee Ki-Ju , Kim Jin-Su , Choi Jong-Woo , Kim Ki-Chan , Lee Il-Hyeong , Kang Tae-Sung , Lim Peter 
Published: October 2015

Recently, there are increasing demands of a size reduction and a fine interconnection technology, especially for System-in-Package (SiP) module and Package on Package (POP) module in a smart phone and a wearable electronic device.
In this study, we presented the Plating Mold Via (PMV) interconnection technology as an innovative fine pitch interconnection solution between substrate I/O pads and package I/O pads in molded System-in-Package (SiP) modules. Similar to the Through Mold Via (TMV), the laser mold via process is first performed to produce a through-via in the Epoxy Mold Compound (EMC) mold, but plating and Soldering process are used simultaneously to produce the metallurgical interconnection to embody the I/O pins of the over-molded surface. After the PMV technology is described, a study of PMV in the molded packaging module is followed. The study is conducted using a test vehicle of SiP module that contains flip chips, Quad Flat Non-leaded (QFN) packages and passives. It is focused on several interface reliability issues, including the interfacial strength of PMV to substrate metal pad as well as to the laser projected area of EMC, and the study of IMC at the plating metal and solder interfaces.
The study clearly shows that the PMV technology is a promising fine pitch interconnect solution for various SiP modules.
BENEFITS OF TRANSMISSION LINE METAL-INSULATOR-METAL CAPACITORS IN MASS PRODUCTION OF RF CIRCUITS
Authors: ATALAN Cenk , TONGEL Eyup 
Published: October 2015

Coupling capacitors or DC blocks are essential tuning elements in RF/microwave applications. Their role becomes imperative in cascade amplifiers to isolate drain voltages of preceding MMIC from the gate voltage of the following chip where both RF and DC signals are carried through the same line. The purpose of this study is to explain the benefits of a newly designed thin film coupling capacitor called as transmission line metal-insulator-metal capacitor (TL MIM Cap), which serves as a DC block capacitor in microwave circuits. This novel structure provides a unique solution, which cannot be achieved with traditional single layer ceramic capacitor (SLC) structure. It combines two discrete circuit elements into one: “Microstrip transmission line of required length and width” with a “serially attached coupling capacitor”. Thin film capacitive layers ranged from 0.5pF to 50pF, which are typically needed for microwave frequencies within 1–40 GHz, constructed and embedded into 50 Ohm impedance transmission lines in series. Substrates like quartz, glass, or alumina can be used to minimize losses and to achieve higher RF/microwave performance. We used copper traces as conductive layers for optimal conductivity.
After manufacturing TL MIM Caps, we tested several capacitance values for 1pF, 5pF, 15pF and 30pF corresponding to a wide frequency range. The RF tests we performed showed that TL MIM Caps exhibited a minimum of 20dB return loss and a maximum of 0.3 dB insertion loss at 1–40GHz range. We also found our technique comes with some workmanship advantages in high frequency circuit assembly as follows: Traditional coupling capacitor attachment with silver epoxy on top of a microstrip transmission line is a manual operation, which requires well trained and experienced technicians. In contrast, using the TL MIM Caps in our high frequency hybrid modules, we found that the process caused errors were eliminated such as the micro short circuit effect caused by conductive epoxy. Therefore we improved yield in assembly stage of the circuits. In addition, improvements are observed in production processes such as less consumption of adhesives (epoxy), no technician failure caused wastes, elimination of extra curing process to attach capacitors, no short circuit inspection, rework, or re-cure operations to fix assembly errors. Last but not least, blocking capacitors are embedded into the microstrip transmission lines in TL MIM Caps. This ensures that having the lowest possible impedance since very short wire bond exists from the bond pad of the TL MIM Cap to the adjacent circuit element.
Analysis method of tool topography change and identification of wear indicators for heavy copper wire wedge bonding
Authors: Eichwald Paul , Sextro Walter , Althoff Simon , Eacock Florian , Unger Andreas , Meyer Tobias , Guth Karsten 
Published: October 2015

One of the main cost factors in the wire bonding process are consumables such as bonding tools. The technological transition to copper as wire material causes significant wear on the millimeter size effective contact area of the bonding tool. This wear leads to a reduction of the number of reliable interconnections which can be produced using a single tool by a factor of 30 replacing the wire material from aluminum to copper. To reduce setup time in the production and minimize costs, an increase in bonding tool lifetime is desired. Consequently a better understanding of the wear and recognition of wear pattern is required. This paper presents a method to analyze tool topography change of a heavy wire bonding tool by using a confocal laser scanning microscope. Furthermore, this paper discusses the identification of the main wear indicators by help of the change in topography.
Wear test has been carried out by choosing typical parameters of the production line. This topography change is compared to the topography change caused by increasing the ultrasonic voltage. To evaluate whether the quality requirement of the bond connections made by a single tool cannot be fulfilled, shear tests of the source bond were made in predefined intervals. All worn tools show dominant areas of wear especially for plastic deformation and accordingly abrasion. These wear mechanisms can be referred to the change of main parts of the groove geometry like the rounding of the front and back radius. The most loss in height was identified in the lower part of the tool flanks or rather at the transition from groove flank to the front or back radius. Furthermore the observation of the center of the groove flank shows just a little change. All in all, the identification of the wear indicators will be discussed with the objective of increasing the tool lifetime by optimizing the tool geometry without losses in bond quality and reliability.
Advanced Process Technology for 3D and 2.5D Applications
Authors: Shelton Doug , Kume Tomii , Wang Charles , Hubbard Alex , Murray Cody , DeLancey Rob 
Published: October 2015

Advanced process technology is required to develop and enable mass production of high-density 3D and 2.5D interconnect technologies.
In this paper, Canon and IBM @ Albany NanoTech will present process optimization results for lithography applications requiring precise thick-resist profile control and precise overlay accuracy of distorted patterns on bonded process wafers. Canon will also provide additional product updates from Canon Anelva.
Comparison of Measured and Modeled Lithographic Process Capabilities for 2.5D and 3D Applications Using a Step and Repeat Camera
Authors: Webb James , McCleary Roger , Lopez Gerald , Tan Qing 
Published: October 2015

Increasing volume using larger substrates with decreasing process margins create new challenges for advanced packaging applications. Key step and repeat camera technology continues being introduced for the mass production of high density interconnects used for 2.5D and 3D technologies that will provide solutions for the challenges encountered.
A 2X reduction stepper with unique features achieves the tighter specifications needed for many advanced packaging applications printed on large substrates. A large field-of-view optical projection system utilizes the 350–450nm light spectrum from a mercury arc to expose the circuit patterns from a reticle mask onto a substrate and image features with the optimal fidelity required for advanced packaging technologies. The imaging field prints a large 52mm x 66mm area or 59.4mm x 59.4mm in a single exposure. These features enable a system to process larger substrates in fewer shots which result in higher throughput using lower power.
Details of the camera and the adjustments that are provided to extend the range of use for both high power and high fidelity applications are discussed.
An extensive evaluation of measured and modeled lithographic capabilities of the step and repeat camera to achieve critical dimensions with precise image placement is provided. Limiting resolution and depth of focus results sampled over the imaging field will be provided and supported with simulation. Results of thin and thick resist patterning will be presented and compared to simulated 3D resist profiles using the MACK4 model.
Efficient Non-reagent Metrology for Modern TSV Baths
Authors: Pavlov Michael , Lin Danni , Shalyt Eugene 
Published: October 2015

Through-silicon via (TSV) technology is gaining popularity in 3D packaging and 3D integrated circuits. TSV baths are formulated with highly stable electrolytes that contain copper and sulfuric acid. Other components introduced into the bath in relatively small amounts are organic additives and chloride ions. This article will focus on a non-reagent metrology to efficiently monitor these components.
The chloride concentration is determined from the chloride oxidation current using specific voltammetric parameters. Similar to analysis of suppressor, the measurement is made directly in the undiluted plating bath. Results for non-reagent analysis for acid and copper were reported earlier. Electrochemistry and spectroscopy are employed in on-line monitoring of various TSV baths.
The concentrations of organic additives are determined from the rate of the copper deposition. The new techniques differ from conventional CVS procedures. The advantages of these newly developed electrochemical procedures are speed (results are obtained within one minute), accuracy and reproducibility. Our new non-reagent techniques do not use special reagents for analysis and require only standard solution used for automatic system calibration and validation.
Thermal and EMI Performance of Composite Plastic Molded Heat Sinks and Hybrid TIM Materials
Authors: Bhobe Alpesh , Chu Herman , Comiskey Lynn , Jiao Xiangyang , Li Xiao 
Published: October 2015

Heat sinks are widely used in thermal management of electronics. However, it is also well established that a heat sink can couple and radiate electro-magnetic (EM) energy from the same component that it is cooling. As the frequency of these devices continues to increase, it is more crucial to try to suppress the EM radiation at the source. The component suppliers for thermal management and EMI products have been developing materials that are thermally conductive and also have EM absorbing properties. The thermal and EMI material properties of the additives can change the properties of the final material and they may not always be complementary between thermal and EM absorbing behaviors. In this paper, two such hybrid solutions are investigated to understand the thermal and EM absorbing characteristics and interactions. These are: (1) heat sinks made of composite plastic materials; and (2) hybrid RF/thermal interface materials (HRTIMs).
For the heat sink study, three heat sinks of the same physical design (40mm square x 8.25mm tall) but with different materials are tested and analyzed. Two of the heat sinks are molded from two different composite plastics (Materials A and B), while the third one is constructed from aluminum and used as the baseline heat sink for comparison. The results presented in Figure 7 show EMI improvement for composite material heat sinks over the traditional aluminum heat sink. Material A provides a broadband reduction of 2–3 dB power whereas Material B heat sink provides significant reduction at lower frequency range of 1–8 GHz. The thermal performance results are plotted in Figure 11 – Figure 14, and the results show that the composite plastic materials are more suitable for applications that have lower power and power density.
For the HRTIMs, two different base materials at different thicknesses are investigated and the material details are given in Table 2 . Similar to the heat sink EMI study, Total Radiated Power (TRP) measurements are performed for the HRTIMs in an Electromagnetic Reverberation Chamber in the frequency range of 5–40 GHz show improvement for material TIM 1. The EMI results are plotted in Figure 9 and Figure 10. For thermal performance characterizations, an ASTM D-5470 compliance test stand (Figure 6) is used. The thermal impedance results of these materials are plotted in Figure 15.
Thick Film Technology For Today's Hearing Products
Authors: Dzarnoski John , Johansson Susie 
Published: October 2015

There has been continuous worldwide effort to increase the volumetric efficiency of electronic packaging. Much of this effort has been driven by the telecommunications industry that has succeeded in reducing cell phone size while simultaneously increasing functionality. The hearing aid business has always had the need to use extremely small electronic packaging because hearing aids pack electronics into the ear canal. The first commercial product using the transistor in 1952 was a hybrid vacuum tube-transistor hearing instrument. Today's hearing aids, such as Starkey's 3-Series product, have significant computing power and run complex hearing algorithms that have enormous impact on a patient's quality of life. The industry trend is to put more memory, more signal processing capability and more wireless capability into hearing aids to increase functionality and to improve performance. In order to achieve this increase in performance, the hearing business has had to develop and execute 3D packaging well ahead of other industries.
This paper will examine the history of ceramic hybrid packaging at Starkey. The challenges and drivers for major technology steps will be addressed. The following technical advancements, transitions, considerations and limitations will be examined: changing ASIC technologies, impact of chip metallization, solder interconnect temperature hierarchy, impact of RoHS legislation, overcoming routing design limits, miniaturization realized by flip chip attach, impact of chip stacking on size, migration to stacked thick film ceramic interconnect layers using vertical interconnect channels, advances in thick film materials to support higher interconnect density, and incorporation of integrated passive devices.