bluuebunny/crossref_metadata_2025_split huggingface dataset:
Advanced Applications of High Temperature Magnetics
Authors: Fraley John R. , Cilio Edgar , Western Bryon 
Published: October 2015

In recent years, high temperature magnetic structures have been developed and used for inductors and transformers in high temperature applications ranging from power electronics to wireless telemetry systems. Research in the high temperature magnetics field has led to the development of more advanced magnetic structures that can enable diverse applications ranging from regulators to amplifiers, with far reaching implications for the high temperature electronics community. Current high temperature electronics have shown potential in lab and rig tests, but high temperature electronics systems suffer from the relatively limited lifetime of the semiconductor devices themselves. The advanced magnetics discussed in this paper can be designed to have extreme lifetime capabilities even at elevated temperatures, and as such can have an immediate impact on the implementation of true field deployable high temperature electronic systems. Aerospace, power generation, and automotive industries may especially benefit from this technology, as significant advances in health monitoring and active engine control will be enabled by these advanced magnetic structures.
A theoretical understanding of these advanced magnetic structures is necessary for initial design and feasibility, while the true development and implementation of this technology depends on state of the art high temperature packaging approaches. By combining high temperature, grain-oriented magnetic materials along with high temperature packaging processes, APEI, Inc. has created advanced high temperature magnetic systems that indicate the technology described in this paper is a viable one, with applications across a wide range of high temperature electronics systems.
High Temperature Characterization and Reliability Data of Key Semiconductor Technologies for Power and Control Devices
Authors: Wilkinson Brian , Walters Kent , Ellerman Paul 
Published: October 2015

An increasing number of extreme temperature operating applications require temperatures that can range from −65°C to 300°C, driving semiconductor suppliers to innovate new analog, digital, and mixed-signal solutions based on technologies including SiC, GaN, Si, SOI and CMOS.
In addition, the paper will briefly highlight Microsemi's real-world results including characterization and reliability data on discrete power products including diodes and bridge rectifiers, and integrated circuits for demanding applications including down-hole drilling, commercial aviation, power sub-systems and power distribution in military vehicles.
High Temperature Performance of Oxide Film Capacitors
Authors: Jamison Keith D. , Balliette Bill 
Published: October 2015

Film capacitors that perform well at temperatures exceeding 150°C and have energy densities in excess of 1 J/cm3 are an enabling technology for many applications in automotive, geophysical exploration, aerospace, and the military. To address this need Faradox Energy Storage, Inc. has produced and is testing high temperature film capacitors fabricated using amorphous oxides (OxFilm™) as the dielectric material. The capacitors are made by depositing thin films of an oxide dielectric on both sides of a double metalized polyimide substrate to form dielectric-coated electrodes. Currently Faradox is producing 2″ long, 1/4″ diameter 2 uF, 100 VDC capacitors using silicon dioxide as the dielectric material.
In this paper we present test data demonstrating that OxFilm capacitors have relatively stable properties over a wide temperature range. Measurements include capacitor testing at different 3rd Party test facilities and internal testing using a variety of test conditions including:Life testing at 200 and 250°C for over 1000 hours with measurements of capacitance, leakage, dF and ESR.Capacitance versus voltage, temperature and frequencyImpedance, ESR, and dF versus frequency and temperature and voltageData will also be presented that show these capacitors can be cycled between 0°C and 200°C without degrading their performance. Work is ongoing to obtain additional test data with more statistically significant numbers of capacitors.
Die Attach of Power Devices Using Silver Sintering – Bonding Process Optimisation and Characterization
Authors: Buttay Cyril , Masson Amandine , Li Jianfeng , Johnson Mark , Lazar Mihai , Raynaud Christophe , Morel Hervé 
Published: October 2015

Silver sintering is becoming an attractive alternative to soldering, especially for high temperature applications. Indeed, the increase in operating temperature requires new soldering alloys with even higher melting points. Silver sintering, on the contrary, is a solution which only require moderate (&lt;300°C) process temperature.
In this paper, we present the implementation of a die attach technique based on sintering of some silver paste, with a special focus on the practical considerations. A good quality bond can be achieved by paying attention to the assembly process.
Semiconductor-to-metal attachment with silver-filled TPI bondlines
Authors: Fraivillig Jim , Koba Richard , Hutchings Kent 
Published: October 2015

In the attachment of semiconductor chips and submounts to metal heat sinks, bondlines utilizing silver-filled thermoplastic polyimide adhesive (TPI) are very durable across a wide range of environmental conditions (thermal, physical, chemical, radiation). TPI bondlines can withstand an extreme CTE-mismatch between the laminated materials, and have excellent bonding with adhesive-layer thicknesses down to only a few microns. To provide electrical conductivity and enhance thermal conductivity, the TPI bondline can be compounded with a high concentration of silver particles, and retain durability and adhesion.
There are two general constructions of silver-filled TPI bondlines:Bondfoil – thin layers of silver-filled B-staged TPI coatings on either side of a metal carrier/substrate. The thickness of the (cured) TPI coatings would be 2–10 μm/side. TPI-priming (B- or C-staged; partially or fully cured) of a semiconductor surface may be required.TPI coating only – thin layers of silver-filled TPI polymer (1–3 μm/surface; B- or C-staged) on the interface surfaces to be bonded. A minimal amount of A-staged TPI (liquid: polymer in solvent) may be added to the bondline construction to optimize surface wetting during lamination.The ultimate in robustness and thinness, silver-filled TPI bondlines can provide:Continuous operation at 350°C, as well as temporary exposure to 450°C. Thermogravimetric analysis (TGA) of the TPI polymer shows that degradation does not start until well above 500°C. [See opposite.]Thermal shock durability -- the CTE-mismatched TPI bondline between silicon and aluminum can survive repeated thermal shocks with a ΔT of 300–400°C.Thermal impedance as low as 0.06 °C-cm2/W (0.01°C-in2/W) when using a silver-filled TPI bondfoil, and about 0.01 °C-cm2/W (0.002°C-in2/W) when using just silver-filled TPI coatings on the interface surfaces (no metal foil). In both constructions, the thermal impedance includes all interface resistances.Shear strength of 10 MPa to an aluminum surface and 1–2 MPa to silicon.
These features make TPI bondlines ideal for demanding, CTE-mismatched semiconductor packages. As opposed to cross-linked thermoset bondlines -- which are brittle, especially when highly filled -- thermoplastic polyimide bondlines remain ductile and resist cracking, even when highly stressed.
Performance and Reliability of SiC dies, Die attach and Substrates for High Temperature Power Applications up to 300°C
Authors: Hamilton Dean , Mills Liam , Riches Steve , Mawby Philip 
Published: October 2015

The recent commercial availability of silicon carbide power semiconductor devices are theoretically capable of operating at temperatures well beyond the limits of silicon devices and have generated an interest in developing high temperature capable packaging solutions to match. In this work, the performance and reliability of a number of commercially available silicon carbide power MOSFET dies from multiple vendors was determined for die temperatures up to 350°C. Although these results have demonstrated a number of aging effects and very high on-state resistances at high temperatures, it appears that these devices can perform reliably even in air atmospheres for 100 hours or more at 350°C. In addition, commercially available DBC type ceramic-based substrates have been evaluated for their thermal cycling performance and candidate high temperature capable die attach materials including silver sinter paste and tin and gold-tin pre-form based transient liquid phase types have also been evaluated. These results have demonstrated that the active metal brazed substrates, both copper and aluminium variants, in conjunction with the silicon carbide dies and silver sinter die attach may serve as the basis for high temperature power modules, and may be operated reliably in thermal cycled applications and in air atmospheres up to 300°C. Due to large threshold voltage shift of the SiC MOSFETs at these temperatures, it may be necessary to implement a negative gate bias capability.
This work has been carried out under the Innovate UK supported project HITEC, led by Prodrive and also including The University of Warwick, GE Aviation Systems, Ricardo, TT Electronics Semelab, Diamond Hard Surfaces and GaN Systems.
Silver Thick Film Based Insulated Metal Substrates for High Temperature Power Applications
Authors: Riches S T , Whitmarsh J , Hamilton D 
Published: October 2015

Thick film technology is normally applied to ceramic substrates such as Al2O3 and AlN, where conductor thicknesses for Au and Ag-Pd based thick film materials are &lt;20μm for signal processing. For power devices applications, thicker deposits are required to increase the current carrying capacity and thick print Cu and Ag materials have been developed for ceramic substrates.
For power applications, this technology still requires attachment of the ceramic substrate to a heat sink, that may be made of aluminium or copper, which needs a thermal interface material. In printed circuit board technology, insulated metal substrates have been developed for power module assembly to eliminate the thermal interface material, where the copper conductor circuit is attached and isolated from the integral heatsink, through an organic based dielectric based on epoxy adhesive material. The organic based material limits the operating temperature of the substrate to around 175°C.
This paper covers the development of a thick film based approach to producing insulated metal substrates that can operate at higher temperatures than an organic based dielectric system. Thick film dielectric materials have been developed for direct deposition onto aluminium substrates with firing temperatures of around 500°C, combined with a silver based thick film material, which is used as the conductor to the power devices. SiC die attach to the silver based thick film material has been evaluated using a silver sinter die attach material which provides a mono-metallic die attach system. Samples have been temperature cycled from −40°C to +250°C for over 100 cycles without deterioration and the results are compared with Cu/Si3N4 substrates, which have shown issues with cracking and delamination for the equivalent thermal cycling regime.
This work has been carried out under the Innovate UK supported project HITEC, led by Prodrive and involving the University of Warwick, Ricardo, TT Electronics - Semelab, GE Aviation Systems – Newmarket, Diamond Hard Surfaces and GaN Systems.
Assessment of MEMS Vibration Energy Harvesting for High Temperature Sensing Applications
Authors: Riches S T , Doyle K , Tebbit N , Jia Y , Seshia A 
Published: October 2015

Distributed electronics for improving the accuracy of sensing in harsh high temperature environments, such as aero-engine and down-well is a growing field, where reduced power input requirements in cabling and batteries is viewed a key enabler for accelerating the adoption of high temperature electronics. Although batteries are available that can operate up to 200°C, they offer limited life at high temperatures and are bulky, increasing the costs of deployment and maintenance. Cabling also adds weight and takes up space in limited access applications. Energy harvesting in-situ offers the opportunity to make a step change in the design of high temperature electronics modules and in expanding their possible range of applications; for example, in sensor systems for combustor and turbine monitoring in aero-engines.
This paper covers an assessment of MEMS vibration energy harvesting technology for high temperature sensing applications. MEMS devices based on the principle of parametric resonance, using AlN on Silicon have been designed and fabricated, along with sourcing of high temperature components for rectification, impedance matching and energy storage. The MEMS devices have been packaged into ceramic chip carriers and measured for energy output from a random vibration profile representative of an aerospace application. The measured output from the MEMS vibration energy harvester is capable of providing sufficient power to be of interest for autonomous sensing applications.
This paper reports on the performance of the MEMS vibration energy harvesting devices and their associated circuitry at room temperature and at temperatures of up to 150°C. The challenges remaining to develop robust energy harvesting devices that could be applied in aero-engine, down-well and other high temperature applications are described.
This work has been carried out under the Innovate UK supported project HI-VIBE, in a collaboration between GE Aviation Systems – Newmarket and the University of Cambridge.
High Temperature 256Kbit (32Kbit × 8) HTEEPROM Reliability Testing
Authors: Guimont Joe G. , Ohme Bruce W. 
Published: October 2015

Results of reliability and qualification testing are presented for a commercial High Temperature EEPROM (HTEEPROM). This HTEEPROM is specified for operation at 225°C and is the highest temperature rated commercial non-volatile memory available to date.
Initial test results (at 250°C) and design details have been previously reported for a prototype 256Kbit (32Kbit × 8) HTEEPROM fabricated using a production high-temperature silicon-on-insulator (SOI) 0.8 micron CMOS process [1]. This paper presents reliability test results for a commercial version developed using knowledge gained from the previously reported HTEEPROM, and fabricated in the same technology. The reliability test results include data retention at 250°C, endurance (write cycling) &gt; 100,000 cycles, parametric and functional test results for 1000 hours of dynamic life test at 250°C, 100 temperature cycles from −65°C to 200°C, ESD, Group D and residual-gas-analysis (RGA) testing. The HTEEPROM is packaged in a 56-pin ceramic pin-grid-array (PGA) package. It is configurable by a control input pin for either serial or parallel memory access. The design incorporates an on-chip timer to support periodic memory refresh to extend data retention indefinitely.
Effectiveness of Barrier Layer Metallisations in Long Term High Temperature Endurance Tests on Wire Bond Interconnections
Authors: Riches S T , Johnston C , Lui A 
Published: October 2015

Silicon on Insulator (SOI) device technology has been shown to be capable of functioning satisfactorily at operating temperatures of &gt;200°C, with device lifetimes of 5 years at 225°C being declared. One of the key areas governing the lifetime of the packaged electronic devices is the reliability of the wire bond interconnection between the device and the package or substrate connection. Extended temperature storage testing at 250°C of packaged SOI devices has highlighted end of life failure modes associated with wire bond connections.
SOI devices are normally supplied with an aluminium based bond pad metallisation, which are not suitable for direct connection of Au wire at operating temperatures of &gt;125°C, due to the formation of Au-Al intermetallics. It is possible to post-process silicon wafers to deposit barrier and connection materials to create a mono-metallic Au-Au joint at the surface. For long term endurance at temperatures &gt;200°C, the effectiveness of the barrier layer in preventing diffusion of the aluminium bond pad metallisation to interact with the Au is a critical factor.
This paper presents results of studies carried out on two post-process metallisation systems Au/TiW and Au/Pd/Ni deposited onto aluminium bond pads, which have been Au wire bonded and exposed to 250°C temperature storage for up to 13,000 hours. The results have shown that the barrier layers are not effective in preventing diffusion of the aluminium bond pad metallisation to create Au-Al based intermetallics. The results are compared with Al-1%Si wire bonding to the aluminium bond pad, where the 2nd wedge bond is attached to a Au/Ni plated metallisation, where the degradation appears to be less severe. Recommendations for designing stable wire bond interconnection systems for extended high temperature operation will be presented.
A Ceramic Clevis Sensor For Online Substance Concentration Measurement, Manufactured By Ceramic Injection Molding
Authors: Hartmann Matthias , Doerner Steffen , Hirsch Soeren 
Published: October 2015

The current research presents recent respective to the work development of a ceramic clevis sensor for online substance concentration measurements. The aim was to develop a robust and acid-resistant sensor device, which can be easily included in existing procedural pipeline systems. To archive those goals a lot of factors had to be checked. For the substance concentration measurements a capacitive sensor effect was chosen. With this method even low substance concentrations down to one-tenth of a per cent can be indentified.
For the package material zirconium oxide (tetragonal zirconia polycrystal – TZP) was used. Zirconium oxide is a technical ceramic which is wear-resistant, acid-resistant, has a low thermal conductivity, is electrically isolating and can be uses in a ceramic injection molding (CIM) process. In the phase of the sensor design process multiple geometries for the sensor effect and integration space for the evaluation electronics had to be considered. A standardized DN 40 DIN 32676 flanged joint was also added for an unproblematic connection to the pipelines. All these needed geometries had to be integrated into one ceramic element. As a result of these requirements a 3D CAD model of the sensor element was designed. The CAD-file has shown that there was only the CIM technology left to comprehend developed sensor geometry. CIM is a low cost process for large-scale production which is distinguished by high size accuracy. In the CIM process the material shrinkage, this is caused by the needed debindering and sintering steps, had to be considered.
The developed ceramic clevis sensor was successfully tested in multiple fluidic systems. It has left the test phase and is now ready for maturity phase.
Investigation on the failure criterion of reliability testing for Pb-free BGA packages
Authors: Xie Weidong , Lee Tae-Kyu , Liu Kuo-Chuan , Xue Jie 
Published: October 2015

Daisy-chained test vehicles are commonly used in board level reliability testing. By continuously monitoring the in-situ daisy chain resistance change over time, a failure could be captured during cycling and eventually the failure data could be used to establish the solder joints failure distribution under different testing conditions. One of the most debatable matters is that when should one to determine a failure to occur. Per IPC 9701A [1] a failure is defined as 10 1000-ohm events in 1 micro-second duration for event detector or 20% increase over the baseline resistance for data logger. Other threshold values such as 100, 300, or 500 ohms are also commonly used by packaging reliability community. Such a wide range of failure threshold values may introduce significant delta in terms of cycle numbers for Pb-free solder joints if different criteria would be used as reported by Henshall, etc [2]. Therefore a systematic study of the impact of using such diversified resistance values on the final failure distribution is necessary and important such that no big difference among reliability results from different sources.
The purpose of this study is to investigate the impact of different failure thresholds on Pb-free solder joint failure distribution for most commonly used packages. The test vehicle, designed on an 8″×15″ double-sided printed circuit board (PCB) with multiple test sites, was populated on both sides with daisy-chained components. To reflect the real situation, the components were selected to include different package types (FCBGA, PBGA, CSP, QFN, etc), different pitches (0.4–1.0 mm), and different package size (6–50mm). The assembled test vehicles then went through 0C–100C thermal cycling, the cycle numbers corresponding to different resistance thresholds were recorded and compared. The test results showed that the failure threshold has significant impact on Pb-free solder joint failure distribution, thus it is important to unify the failure criterion such that the reliability results from different sources could be compared side by side. For some packages especially small wire-bond packages that have relatively low baseline resistance, the 20% failure criterion may be too sensitive to the resistivity changes caused not by solder joint failure but other events such as connection cable resistivity change over time or temperature.
Enabling MSL-1 Capability for QFN and Other Design Leadframe Packages
Authors: Hart Dan , Ganjei John , Kapadia Nilesh 
Published: October 2015

As the conversion of the electronics industry to lead free soldering materials continues some unexpected negative side effects of higher lead free reflow temperatures have occurred. Defects such as delamination or “popcorning” in surface mount components have increased significantly since lead free soldering has become mainstream. Popcorning is a defect that manifests itself as a fracture between the epoxy based encapsulant and the metal, usually copper alloy, leadframe components used to form a surface mount component. This fracture occurs when moisture in the package volatilizes during reflow processes and forces its way through the encapsulation material and leadframe interface.
Peak reflow temperatures for leaded solder typically run around 215° – 225° C but due to the higher melting point of lead free solders, they require peak reflow temperatures of 240° to 260° C range. This 30° increase in reflow temperatures can have a significant effect on the electronic devices and any resident moisture in the component
The keys to popcorning, or delamination, defect reduction is twofold. The first objective is to enhance the bond between the encapsulant and the copper leadframe materials to form a stronger bond that can resist the vapor pressures induced during reflow. The other objective is to provide a superior bond between the leadframe and encapsulant thus minimizing moisture ingress.
New chemical treatment processes have been developed that pre-treat the copper surfaces of the leadframe and significantly enhance the bond between the encapsulant material and the metal leadframe. The chemical treatment process results in micro-roughening of the copper surfaces and at the same time depositing a thermally robust film that enhances the chemical bond between the epoxy encapsulant material and the copper.
This paper examines the possible issues and the real life successes when comparing standard component manufacturing methods to those that incorporate the aforementioned chemical adhesion promotion process. Components are assembled using both processes and final performance is tested using MLS-1 conditioning protocols, acoustic microscopy analysis (SAM), and final yield improvement.