High-Quality Ge-Rich Nanosheets on Silicon on Insulator Substrates Based on Ultra-Low Temperature Epitaxy
Authors: Wilflingseder Christoph , Prado-Navarrete Enrique , Salomon Andreas , Fromherz Thomas , Aberl Johannes , Brehm Moritz 
Published: August 2024

Ge and Ge-rich SiGe channel materials are expected to enhance performance in next-generation electronic devices, such as e.g. reconfigurable field effect transistors [1]. However, an inherent lattice mismatch exists between Ge and Si of about 4%. Ge layers on Si grow under compressive in-plane strain, drastically limiting the thickness of high-quality Ge layers on Si to a few monolayers, i.e., far too thin for practical device applications.
In principle, vertically grown nanowires grown by vapor-liquid-solid growth (VLS) can be used to overcome these limitations as their small footprint can mitigate the strain. That is why, to date, basically all Ge-rich nanoelectronics device concepts are based on VLS nanowires.
However, for device fabrication, the nanowires grown on untypical (111) substrates need to be picked and placed onto Si(001) substrates, which is a serial process and, thus, barely scalable.
Thus, whenever two-dimensional nanosheets of a material are available, they provide distinct advantages with respect to device integration. In this context, pure Ge and SiGe alloyed nanowires formed from through top-down lithography from nanosheets would enable extended device functionalities.
The problem is that for high Ge contents, the achievable thickness of pseudomorphic, defect-free (Si)Ge epilayers is just a couple of monolayers if grown directly on Si(001) substrates [2] as the inherent strain between the layer and substrate leads to harmful plastic or elastic relaxation under common growth conditions. Thus, using conventional epitaxy, the attainable defect-free SiGe/Si layer thicknesses are typically far from usable in electronic transport devices.
Therefore, we depart from established (Si)Ge epitaxy temperatures of ≥500°C and employ molecular beam epitaxy (MBE) growth at ultra-low temperatures (ULT), ranging from 100°C to 350°C.[3] We show that the lowered surface kinetics leads to a pronounced layer supersaturation, allowing us to access layer thicknesses that are more than an order of magnitude larger than previously reported values. We highlight that pristine growth pressures deep in the ultra-high vacuum range ( ≤10-10 mbar) are crucial to keep the density of unwanted impurities in the (Si)Ge layers to a minimum and, thus, enable excellent electrical and optical properties of the grown heterostructures. These low growth pressures are particularly important in ULT growth since the low thermal budget impedes the efficient desorption of residual gas molecules from the substrate.
We show that such fully strained, defect-free (Si)Ge epilayers grown directly on SOI substrates form high-quality nanosheets [4] for which properties like thickness, SiGe(Sn) content, and barrier material, doping can be conveniently tuned during the epitaxy process beyond past limitations. These nanosheets are the highly scalable base for advanced transport devices, such as reconfigurable transistors with excellent performance characteristics [4,5,6].

References

[1] A. Heinzig et al., Nano Lett. 12, 119 (2012).
[2] M. Brehm et al., Nanotechnology 28 (39), 392001 (2017).
[3] A. Salomon et al., physica status solidi (a) 219, 2200154 (2022).
[4] L. Wind et al., Small 18 (44), 2204178 (2022).
[5] A. Fuchsberger, et al., Advanced Electronic Materials, 2201259 (2023).
[6] A. Fuchsberger et al., A Runtime Reconfigurable Ge Field-Effect Transistor with Symmetric On-States, IEEE Journal of the Electron Devices Society (in print)