bluuebunny/crossref_metadata_2025_split huggingface dataset:
Pharmacological basis for the medicinal use of <i>Viola odorata</i> in diarrhea, bronchial asthma and hypertension
Authors: Janbaz Khalid Hussain , Khan Waseem Ullah , Saqib Fatima , Khalid Mamoona 
Published: October 2015

<p class="Abstract"><em>Viola odorata</em> is traditionally used in the management of gastrointestinal, respiratory and vascular disorders. The present study was undertaken to validate its folkloric uses. The application of <em>V. odorata</em> to spontaneous contractions in isolated rabbit jejunum preparation exerted relaxant effect through decrease in magnitude and frequency of contractions. Moreover, it also caused relaxation of K<sup>+ </sup>(80 mM)-induced contractions and shifted the Ca<sup>2+ </sup>concentration response curves toward right in isolated jejunum similar to verapamil (standard Ca<sup>2+ </sup>channel blocker), confirming Ca<sup>2+ </sup>channel blocking activity. <em>V. odorata</em> also caused relaxation of carbachol (1 µM)- and K<sup>+ </sup>(80 mM)-induced contractions in isolated rabbit tracheal preparations comparable to verapamil, reflecting that observed relaxant effect may be the outcome of anti-muscarinic and/or Ca<sup>2+ </sup>channel blocking activities. It also exerted relaxant effect on phenylephrine (1 µM)- and K<sup>+ </sup>(80 mM)-induced contractions in isolated rabbit aortic preparations thus providing rationale for its folkloric uses to treat diarrhea, asthma and hypertension.</p>
La convention alpine, la montagne et la souris
Authors: Servoin François 
Published: October 2015

Le 6 décembre 1995, dans un climat ambigu, la France ratifiait in extremis la Convention alpine de manière à pouvoir figurer parmi les puissances fondatrices. La Convention ambitieuse continuait l'action menée de longue date par les écologistes allemands, reprise par le gouvernement allemand soucieux de leur appui.
Cette convention instaure des institutions et un cadre général permettant la rédaction de protocoles qui constituent autant de nouveaux accords internationaux. De fait, la Convention elle-même se réduit à un cadre peu innovant en droit français, son application est conditionnée par l'adoption ultérieure de protocoles dont le contenu croise largement les compétences communautaires dans le domaine de l'environnement.
La discussion en France provoqua des réactions vives de la part, principalement, des élus locaux, inquiets de n'avoir pas été associés à un projet, muet sur le développement économique des Alpes. Le débat sur la Convention qui ne vise qu'un seul massif de la montagne française a relancé le thème de l'avenir de la montagne et l'a réorienté sur la Charte européenne de la montagne en préparation au Conseil de l'Europe. En attendant que la discussion porte sur le projet Natura 2000.
System Level Thermal Performance Evaluation of Inverted Exposed Pad Packages
Authors: Chiriac Victor 
Published: October 2015

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the 54 lead SOIC (with inverted exposed Cu pad) packages for advanced automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated.
Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rj-hs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios.
Finally, compared different exposed pad packages. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package.
Contract Wafer Bumping of Compound Semiconductors
Authors: Strandjord Andrew , Teutsch Thorsten , Scheffler Axel , Otto Bernd , Li Jing 
Published: October 2015

There are a number of qualified technologies for backend processing of traditional silicon based semiconductors. GaAs wafers have several unique properties that make these established technologies inadequate, including: the presence of air bridges, gold bond pads, and the bulk material properties of the GaAs.
In this paper, we describe a process flow and a set of materials which enable the pad resurfacing, UBM deposition, and solder bumping of GaAs wafers. The gold bond pads are resurfaced using a resist liftoff technology and TiCu sputtering. The combination of these allows for pad resurfacing while protecting the air bridges and GaAs. The UBM is deposited on these new TiCu pads by using a thin film layer to again protect the air bridges and GaAs, followed by electrolessly plating nickel and gold. The solder bumping is accomplished using a laser based sphere drop process which is fluxless. To complete the backend processing, the bumped GaAs wafers are then diced and sorted into waffle packs. Details will be discussed relative to the processing conditions, materials used, and yields.
Nano-Porous Gold Interconnect
Authors: Oppermann Hermann , Dietrich Lothar , Klein Matthias , Wunderle Bernhard , Reichl Herbert 
Published: October 2015

Pure metal contacts offer some advantage as high thermal and electrical conductivity, ductile deformation behavior and reduction of mechanical peak stresses. They are used in flip chip assemblies as gold bumps, in die attach as sintered silver powder or as gold layer on very smooth surfaces for wafer bonding. Analyzing the demands in most suitable material properties we were looking for a compressible metal contact, which could compensate for all implanarities, with a highly reactive surface to reduce bonding temperature. It should be a noble metal, but with good adhesion to polymers.
We have developed a nanoporous metal layer processed by electroplating a silver-gold alloy with 20 to 30% gold. High plating rates could be achieved exceeding those of standard gold electrolytes. Subsequent de-alloying by etching off the silver provides a nano-porous gold layer as an open-porous sponge with 70 to 80% porosity. Pore and ligament size were measured from different samples between 20 to 100 nm. Aging experiments showed the coarsening of pore size.
We have successfully plated nano-sponge layer of 10 μm height on top of gold bumps on wafer level. But we don't see a limitation yet to further increase the thickness of gold nano-sponge. Chips were bonded by thermocompression resulting in a reduction of bump height without changing the bump diameter. At lower bond force and lower bond temperature the collapse of the porous structure occurred in the bond interface mainly, leaving the porosity in most of the bump volume unchanged.
This leads to a new interconnect structure of high porosity. For very high porosity stiffness should be reduced with the square of the volume ratio. We therefore expect improved reliability due to the reduction in stiffness.
Due to the compressible deformation behavior of the nano-sponge it could improve the yield during wafer-to-wafer bonding and stacking as the particle will be absorbed into the sponge. This allows bonding of wafers without the need of planarization the dielectric layer, e.g. due to steps over conductor lines. Therefore we will use the nano-sponge in stacking and 3D integration.
Beside compression bonding and sintering we use the nano-sponge also as a thermal interface for adhesives. Filler particles are pressed into the sponge structure leading to a larger contact area between particle and substrate surface, thereby the adhesive matrix can penetrate into the open porous film. The locking interface should also provide very high adhesion strength.
Electromigration Performance of WLPs with Standard and Polymer Core Balls
Authors: Nguyen L. , Nguyen H. , Prabhu A. 
Published: October 2015

This talk will compare the electromigration performance of wafer level packages having standard SnAgCu solder with those having solder balls with polymer cores. Information on package construction, process, and board level reliability of packages having balls with polymer cores was presented earlier (2009 International Wafer Level Packaging Conference, San Jose, CA). In the new ball variation, the structure is made of a large solid polymer core, which is plated with a thin layer of copper and covered with a layer of SnAg. The polymer core within the solder ball ensures that the standoff height remains constant during board assembly, and acts as a stress absorption layer between the Si and the PCB during any thermal excursion and drop testing. Such characteristics allow extension of the wafer level package from small pin count (~30 I/O) to higher pin count (100+ I/O) without the need for redistribution layers.
For electromigration, bump resistances were monitored continuously at different current densities and temperatures for the two package types. Equivalent performance was obtained. Similar failure modes were observed in both cases, with pancake-like void formation growing outward from the pad corners due to current crowding. Equivalent performance was obtained, with both packages exhibiting MTTF of 1200 hrs at 150C, and 550 hrs at 165C. Application to a modified Black's equation to predict MTTF and account for current crowding, heating, and stress will also be discussed.
Advanced TSV Copper Electrodeposition for 3D Interconnect Applications
Authors: Beica Rozalia , Siblerud Paul , Erickson Dave 
Published: October 2015

Robust and manufacturable processes are needed to enable a smoother and faster transfer of TSV technology from development to production.
There are several steps involved with TSV technology application. Either if it is done before or after thinning the wafer, as a via first, middle or via last approach, the main steps are: via etching, lining with insulator/barrier and copper seed, deep via fill and chemical mechanical planarization (CMP), chip dicing and stacking. Deep via fill is one of thee most critical steps in forming the TSV electrodes, and copper electrodeposition process has been identified to be the most appropriate and cost effective method of filling the vias.
Various critical factors with significant effect on the process performance were found: seed layer uniformity, via profile and size, stability and performance of the chemicals and equipment design. The amount and quality of the copper at the top of the vias and over the entire surface of the wafer is very important for the CMP processing. A more uniform deposition and lower overburden could significantly decrease the complexity and cost of the CMP step. The copper thickness profile between deposition and CMP can be cross-optimized to reduce dishing, increase throughput and reduce cost. This paper will focus on the deep via fill, the critical factors associated with this step and integration aspects of Cu TSV deposition step that need to be taken in consideration for successful application of this technology.
A significant amount of work has been performed to develop processes that can successfully fill features of various sizes in a cost effective way. Some of the chemistries available commercially today, although have very good super-fill characteristics, have the disadvantage of forming nodular and high-stress deposits which could have a negative impact on CMP processing. An innovative process with strong bottom-up capability that significantly reduces the overburden while increasing the speed of deposition has been developed at Semitool and the characteristics of this process and advantages over previous generation processes will be presented. The effect of copper stress and copper extrusion observed during annealing step as well as approaches taken to minimize this effect will be described.
A Robust Wafer-Level Capping Approach for MEMS Devices
Authors: Seetharaman Krishnan , van Velzen Bart , van Zadelhoff Hans , Yuan Cadmus , Rietveld Frank , Tak Coen , van Beek Joost , Koning Jan-Jaap , Magnée Peter H. C. , van Wingerden Johannes , Beijerinck Herman C. W. 
Published: October 2015

Micro-electromechanical systems (MEMS) devices are extremely sensitive to their environment, especially at wafer-level, until they are packaged in final form. The harsh back-end (BE) operations that the MEMS devices have to endure include dicing, pick-and-place, wire bonding and molding. During these processing steps, the MEMS device is exposed to particles and contaminants. Therefore, protection at an early stage is a fundamental requirement.
In this work, we describe a silicon nitride thin-film capping, which is processed using a sacrificial layer technique only with front-end technology. This approach is suitable for mass production of MEMS devices, owing to the fact that, it is more cost-effective when compared to other approaches such as wafer-to-wafer bonding and die-to-wafer bonding.
A Bulk Acoustic Wave (BAW) resonator, that finds application in the Radio Frequency (RF) front end, e.g., in cell phones, is taken as a MEMS vehicle for our work. It is an example of an extremely sensitive MEMS device, because the resonance frequency shifts significantly when additional mass is accidentally deposited on its surface. The thickness of the silicon nitride capping that is required to withstand all the BE steps, in particular transfer molding, is estimated using simple analytical calculations and finite element model (FEM) simulations. The pressure acting on the thin film capping and the thermal load during molding are included in the FEM model. Using this, the minimum thickness required for the capping is determined. We prove that, a BAW resonator capped with silicon nitride at wafer-level can be wafer-thinned, diced, wire bonded and molded without major degradation in its performance.
3D TSV Interposer Technology with Cu/SnAg Microbump Interconnections
Authors: Yoon Seung Wook , Shariff Dzafir , Ku Jae Hun , Marimuthu Pandi Chelvam , Carson Flynn 
Published: October 2015

Microelectronics packaging is driven by the continuous increase in demands for smaller, faster, and cheaper products with enhanced performances. Flip-chip technology and multichip packaging are developed to meet the market needs. In recent years, the concept of multichip packaging is evolved into system-in-a-package (SIP). Major advantages of SiP are that different types and generations of devices are assembled in a single package, providing high flexibility for systems designers. One way of integrating more devices into a smaller volume is 3-D packaging techniques by stacking the chips vertically. The 3-D packaging can be broadly classified as chip stacking and package stacking. In chip stacking technology, dice are stacked. This technology has advantages of increased die combination and flexibility.
These days there is more and more needs for 3D TSV interposers. Based on silicon or glass, 3D TSV interposers are next generation substrate technology which aims at replacing traditional PCB laminate or ceramic technologies for the sake of extreme miniaturization and performance. This intermediate TSV 3D technology is perceived as a bridging or linking platform between today¡¯s 2D and future genuine/ultimate 3D that will start beyond 2013.
This paper will highlight some of the recent advancements in 3D TSV interposer design, and fabrication and Cu/SnAg microbumping as well as what is being envisioned and developed to address future technology requirements in 3D TSV packaging. The advantage and applications of TSV silicon interposer technology will be presented with several examples. The process flow of TSV interposer fabrication, microbumping, assembly and packaging challenges, and performance characteristics will be also discussed.
Journey Toward Process Convergence in TSV Technology
Authors: Ramaswami Sesh , Dukovic John 
Published: October 2015

Continuous demand for more advanced electronic devices with higher functionality and superior performance in smaller packages is driving the semiconductor industry to develop new and more advanced 3D wafer-level interconnect technologies involving TSVs (through-silicon vias). The TSVs are created either on full-thickness wafer from the wafer front-side ¡V as part of wafer-fab processing during Middle-Of-Line (¡§via middle¡¨) or Back-End-Of-Line (¡§via last BEOL¡¨) ¡V or from the wafer backside after wafer thinning (¡§via last backside¡¨). Independent of the specific approach, the main steps include via etching, lining with insulator, copper barrier/seed deposition, via fill, and chemical mechanical planarization (CMP).
Over the past year, the industry has been converging toward some primary unit processes and integration schemes for creating the TSVs. A common cost-of-ownership framework has also begun to emerge. Active collaboration underway among equipment suppliers, materials providers and end users is bringing about rapid development and validation of cost-effective TSV technology in end products.
This presentation will address unit-process and integration challenges of TSV fabrication in the context of 20x100ƒÝm and 5x50ƒÝm baseline process flows at Applied Materials. Highlights of wafer-backside process integration involving wafers bonded to silicon or glass carriers will also be discussed.
Evaluation of Cu/Sn-Cu Bump Bonding Processes for 3D Integration Using a Fluxing Adhesive
Authors: Huffman Alan , Reed Jason , Lueck Matthew , Gregory Christopher , Temple Dorota , Stapleton Russ 
Published: October 2015

The study of copper-based bump structures for interconnects in 3D integration applications has been ongoing for several years. Typically, an array of Cu bumps is bonded to an array of Sn-capped Cu bumps or another Cu bump array using a thermocompression bonding process. These processes rely on high pressures and temperatures to facilitate bonding between the bump arrays. In order for this bonding to take place, some method of oxide removal is normally required for the Cu and/or Cu/Sn bump surfaces before bonding. A number of different methods have been investigated by a number of groups, including chemical cleaning, plasma cleaning, self-assembled monolayers, and no-flow underfill (NUF) materials. The use of NUFs is particularly intriguing, since these materials can be formulated with fluxing agents which could reduce surface oxides on Cu and Sn and can be deposited immediately prior to the thermocompression bonding process. In addition, the material provides a protective encapsulant to the interconnect array, protecting it from environmental damage and adding mechanical strength to the assembly.
We will present the results of a study to evaluate new fluxing NUF materials in thermocompression bonding processes on full area array test devices with 25 micron bump pitch. The test devices are fabricated with either Cu or Cu/Sn bumps to provide two different bonding options (Cu to Cu or Cu/Sn to Cu). We will compare the NUF bonding process and resulting bonded interfaces to assemblies fabricated using our standard bonding processes, which rely on both chemical and plasma pretreatment processes to prepare the bump arrays before bonding. Mechanical and electrical data will be used to compare the two bonding processes, as well as SEM cross-section analysis of the bonded interfaces.
Flexible On-Chip Inductors and Transformer
Authors: Wang James J. 
Published: October 2015

Inductors directly on-chip was designed, processed and tested. Combining thick, electroplated gold used to produce LCD driver ICs plus gold wire bonding, toroidal inductors are formed directly on top of ICs. Both processes are production ready. One layouts inductor line segments on top of ICs and then complete loops using gold wire bonds at packaging. Two, 4, 8 or 16 toroids will fit inside thin QFN package. Cost to integrate 2 or more inductors is less than buying 0402 chip inductors and then soldering SMT components around ICs. Integrating inductors shrinks PCB board and allows IC design of filters, LC oscillator, EM noise suppression or ESD protection circuits.
On-chip 4nH to 2000nH inductors is practical today. Choosing the magnetic core material and selecting the number of loops/turns, designers can integrate different inductors on top of an existing IC. Custom, ultra-tiny magnetic cores are produced from same magnetic materials that are inside discrete inductors or transformers. 50nH to 500nH inductors with Q comparable to chip inductors are possible for MHz frequency ranges by selecting ferrite core. Using high permeability permalloy, one produces 200nH to 2000nH inductors or transformers directly on-chip.
Flexibility is another advantage of on-chip Gold InductorsTM. By adjusting loop heights during wire bonding, one can adjust inductance value +- 100%. By laying out both primary and secondary coils around magnetic core, designers can choose to integrate transformer or inductors. Low cost, production processes, control with IC design, plus flexibility, one can begin to design and produce on-chip filters and transformers; achieving smaller electronics.
Thermal Design of the High Brightness Thin LCDs
Authors: Chestakov D. , Cennini G. , Albani L. , Bonfiglio S. 
Published: October 2015

Often, Medical Monitors have a special cabinet with closure to avoid liquids to hamper the monitor functionality and for cleaning requirements but limiting the airflow. The thermal management of the electronics and LCD panel should be designed with more accuracy and it is a limiting factor of the monitor specification. Introducing LED backlight in Medical Monitors not only allows a mercury free system (Green product) but provides the capability to match the white colour among similar Medical Monitors.
For thermal matters of the LCD backlights, one of the main differences between LEDs and CCFLs is that, the latter ones have an optimal operational temperature: CCFLs (and HCFLs as well) work better when they are hot. On the other hand, heating produces permanent damage to the electrodes, phosphor and gas mixture in the CCFL tube. This effectively reduces the lamp efficacy. For LEDs the situation is just the opposite: for higher efficacy, the light source temperature should be lower, which goes along with the increasing of the lifetime of the LEDs.
Moreover, red, red/orange and amber emitters are more sensitive to increases of junction temperature than other colors. Also, the wavelength of the emitter radiation shifts to higher wavelengths when the junction temperature rises. Red, Red/Orange and Amber emitters are the most sensitive to this effect.
Another difference is the construction of the light sources. The main heat transfer in CCFLs occurs via its glass tube, which is a light emitting surface as well. This makes difficult the realization of an efficient cooling without blocking the emitted light. Additionally, glass is famous for its low mechanical resistance against thermal stress. In case of LED, the heat transfer and light emitting surfaces are different. That makes easy the light and heat extracting designs.
In this paper, we report on the thermal design of a Medical Monitor based on LED backlight with brightness of 1000 cd/m2. The research has been carried out with the aim to define the optimum backlight architecture for an 18” size monochrome display. The design is based on an edge-lit configuration, with two or one row of high power LEDs, and a passive cooling by means of heat sinks or cooling plates