bluuebunny/crossref_metadata_2025_split huggingface dataset:
Analytic Optimization of Cost Effective Thermoelectric Generation on Top of Rankine Cycle
Authors: Yazawa Kazuaki , Koh Yee Rui , Shakouri Ali 
Published: January 2014

Thermoelectric (TE) generators have a potential advantage of the wide applicable temperature range by a proper selection of materials. In contrast, a steam turbine (ST) as a Rankine cycle thermodynamic generator is limited up to more or less 630 °C for the heat source. Unlike typical waste energy recovery systems, we propose a combined system placing a TE generator on top of a ST Rankine cycle generator. This system produces an additional power from the same energy source comparing to a stand-alone steam turbine system. Fuel efficiency is essential both for the economic efficiency and the ecological friendliness, especially for the global warming concern on the carbon dioxide (CO2) emission.
We report our study of the overall performance of the combined system with primarily focusing on the design parameters of thermoelectric generators. The steam temperature connecting two individual generators gives a trade-off in the system design. Too much lower the temperature reduces the ST performance and too much higher the temperature reduces the temperature difference across the TE generator hence reduces the TE performance. Based on the analytic modeling, the optimum steam temperature to be designed is found near at the maximum power design of TE generator. This optimum point changes depending on the hours-of-operation. It is because the energy conversion efficiency directly connects to the fuel consumption rate. As the result, physical upper-limit temperature of steam for ST appeared to provide the best fuel economy. We also investigated the impact of improving the figure-of-merit (ZT) of TE materials. As like generic TE engines, reduction of thermal conductivity is the most influential parameter for improvement. We also discuss the cost-performance. The combined system provides the payback per power output at the initial and also provides the significantly better energy economy [$/KWh].
Open and Contained Cold Aisle Experimentally Validated CFD Model Implementing CRAC and Server Fan Curves for a Data Center Test Laboratory
Authors: Alkharabsheh Sami A. , Muralidharan Bharathkrishnan , Ibrahim Mahmoud , Shrivastava Saurabh K. , Sammakia Bahgat G. 
Published: January 2014

This paper presents the results of an experimentally validated Computational Fluid Dynamics (CFD) model for a data center with fully implemented fan curves on both the servers and the Computer Room Air Conditioner (CRAC). Open and contained cold aisle systems are considered experimentally and numerically. This work is divided into open (uncontained) cold aisle system calibration and validation, and fully contained cold aisle system calibration and leakage characterization.
In the open system, the CRAC unit is calibrated using the manufacturer fan curve. Tiles flow measurements are used to calibrate the floor leakage. The fan curves of the load banks are generated experimentally. A full physics based model of the system is validated with two different CRAC fan speeds. The results showed a very good agreement with the tile flow measurements, with an approximate average error of 5%, indicating that the average model prediction of the tile flow is five percent lower that the measured values.
In the fully contained cold aisle system, a detailed containment CFD model based on experimental measurements is developed. The model is validated by comparing the flow rate through the perforated floor tiles with the experimental measurements. The CFD results are in a good agreement with the experimental data. The average error is about 6.7%. Temperature measurements are used to calibrate other sources of containment and racks leaks including mounting rails and clearance between racks. The temperature measurements and the CFD results agree well with average error less than 2%.
Detailed and equivalent modeling methods for the floor and containment system are investigated. It is found that the simple equivalent models are able to predict the flow rates however they did not succeed in providing detailed fluid flow information. While the detailed models succeeded in explaining the physical phenomena and predicting the flow rates with noticeable tradeoffs regarding the computational time.
Important conclusions can be drawn from this study. In order to accurately model the containment system, both the CRAC and the load banks fan curves should be simulated in the numerical model. Unavoidable racks and containment leaks could cause inlet temperature increase even if the cold aisle is overprovisioned with cold air. It is also noted that heat conduction through the floor tiles causes a slight increase the inlet temperature of the cold aisles. Finally, it is noteworthy that using detailed modeling is necessary to understand the details of the thermal systems, however simpler and faster to compute equivalent models can be used in extended optimization studies that show relative rankings of different designs.
Flip Chip Packaging of Wafer Level Encapsulated RF MEMS Tunable Capacitors
Authors: Cunningham Shawn J. , Heng Yvonne , Idrisi Nabeel , Nelson Brad , McKillop John 
Published: January 2014

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place.
In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability.
In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.
Effect of TSV Joule Heating on Device Performance
Authors: Mirza Fahad , Naware Gaurang , Raman Thiagarajan , Jain Ankur , Agonafer Dereje 
Published: January 2014

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs.
TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.
On the Thermal Management Challenges in Next Generation Handheld Devices
Authors: Wagner Guy R. , Maltz William 
Published: January 2014

Handheld devices are increasingly capable of running applications that used to require laptop and desktop computers. The requirement that these devices provide better performance with a smaller form factor or size presents significant challenges, especially with the limitations of passive cooling.
The current study presents a summary of the cooling solutions of several popular, commercially available tablets. The trends in power dissipation and thermal management techniques of handheld devices are presented.
The factors affecting the maximum possible power dissipation are discussed. The effects of the selection of the outer shell materials, the thermal interface materials, heat spreaders and air gaps are presented.
For all considered thermal management techniques of handheld devices, a figure of merit for the cooling solutions is defined as: Figure of Merit = Maximum Power Dissipation / Surface Temperature Rise, in (W/degC). This figure of merit allows for an objective comparison of the available cooling solutions.
Measurement of Microprocessor Die Stress due to Thermal Cycling, Power Cycling, and Second Level Assembly
Authors: Roberts Jordan C. , Motalab Mohammad , Hussain Safina , Suhling Jeffrey C. , Jaeger Richard C. , Lall Pradeep 
Published: January 2014

In the current work, we have extended our past studies on Flip Chip Ceramic Ball Grid Array (FC-BGA) microprocessor packaging configurations to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings.
Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time.
Thermal Management of Ultra Intense Hot Spots With Two-Phase Multi-Microchannels and Embedded Thermoelectric Cooling
Authors: Marcinichen Jackson B. , d’Entremont Brian P. , Thome John R. , Bulman Gary , Lewis Jay , Venkatasubramanian Rama 
Published: January 2014

This study concerns cooling of electronic components of intense background heat flux with one ultra intense hot spot (e.g. 1000 Wcm−2 on a footprint of 1 cm × 1 cm with 5000 Wcm−2 applied to a 0.02 cm × 0.02 cm region at the center). To manage these extreme heat fluxes and consequently surpass the thermal-hydrodynamic challenges and design paradigms, for example as specified in a recent DARPA request for proposals (Intrachip/Interchip Enhanced Cooling Fundamentals - ICECool Fundamentals [1]), on-chip two-phase multi-microchannel cooling integrated with a superlattice (SL) thin-film thermoeletric cooling (TEC) technology was investigated via computer simulations.
The simulations showed that increasing TEC electrical current results in greater enhancement of heat flow through the TEC, but at high currents this benefit is offset by a net addition of heat to the system, which must also be evacuated by the microchannels. When optimized, a minimum peak junction temperature of about 86 °C for a current of about 8 A was found, which represented a reduction of about 4 °C from a maximum allowed 90 °C at the ultra-intense hot-spot, thus potentially significantly capable of exceeding the DARPA [1] requirement, due to the embedded SL TEC within the microevaporator (ME) structure.
Solid State Lighting Life Prediction Using Extended Kalman Filter
Authors: Lall Pradeep , Wei Junchao , Davis Lynn 
Published: January 2014

Solid-state lighting (SSL) luminaires containing light emitting diodes (LEDs) have the potential of seeing excessive temperatures when being transported across country or being stored in non-climate controlled warehouses. They are also being used in outdoor applications in desert environments that see little or no humidity but will experience extremely high temperatures during the day. This makes it important to increase our understanding of what effects high temperature exposure for a prolonged period of time will have on the usability and survivability of these devices. The U.S. Department of Energy has made a long term commitment to advance the efficiency, understanding and development of solid-state lighting (SSL) and is making a strong push for the acceptance and use of SSL products to reduce overall energy consumption attributable to lighting.
Traditional light sources “burn out” at end-of-life. For an incandescent bulb, the lamp life is defined by B50 life. However, the LEDs have no filament to “burn”. The LEDs continually degrade and the light output decreases eventually below useful levels causing failure. Presently, the methods described in IES TM-21 are used to predict the L70 life of white LEDs from LM-80 test data. Several failure mechanisms may be active in a LED at a single time causing lumen depreciation. The underlying TM-21 Arrhenius Model may not capture the failure physics in presence of multiple failure mechanisms. Correlation of lumen maintenance with underlying physics of degradation at system-level is needed.
In this paper, a Kalman Filter and Extended Kalman Filters (EKF) have been used to develop a 70% Lumen Maintenance Life Prediction Model for LEDs used in SSL luminaires. This model can be used to calculate acceleration factors, evaluate failure-probability and identify ALT methodologies for reducing test time. Nine-thousand hour LM-80 test data for various LEDs have been used for model development. System state has been described in state space form using the measurement of the feature vector, velocity of the feature vector change and the acceleration of the feature vector change. System state at each future time has been computed based on the state space at preceding time step, system dynamics matrix, control vector, control matrix, measurement matrix, measured vector, process noise and measurement noise. The future state of the lumen depreciation has been estimated based on a second order Kalman Filter model and a Bayesian Framework. The measured state variable has been related to the underlying damage using physics-based models. Life prediction of L70 life for the LEDs used in SSL luminaires from KF and EKF based models have been compared with the TM-21 model predictions and experimental data.
CFD Modeling of Indirect/Direct Evaporative Cooling Unit for Modular Data Center Applications
Authors: Gebrehiwot Betsegaw , Dhiman Nikhil , Rajagopalan Kasturi , Agonafer Dereje , Kannan Naveen , Hoverson James , Kaler Mike 
Published: January 2014

An information technology (IT) container needs to be supplied with cold air to cool IT equipment housed in it. The type of cooling system to be used depends on many factors including geographical location of the modular data center. Data centers located in regions where the climate is cold benefit from use of air-side economization (ASE) and those located in hot and dry climate benefit from use of direct and/or indirect evaporative cooling (DIEC) systems. In terms of energy saving, ASE, direct evaporative cooling (DEC) system, and indirect evaporative (IEC) systems are better than compressor based cooling systems such as computer room air conditioning (CRAC) units and air handling units (AHU).
In this study, an existing DIEC unit which can also be operated in ASE mode is modeled in a computational fluid dynamics (CFD) tool. The cooling unit is intended to be used for supplying cold air to a containerized data center with specified volume flow rate, dry-bulb temperature and relative humidity. The CFD model is compared with published data of the cooling unit to see how well the CFD model represents the actual system and few design improvement ideas are tested by modifying the CFD model and running simulations. Results show that supplying air horizontally or as a downdraft to an IT container has negligible effect on the overall system. Results also show that orientation of dampers and placement of blanking panels inside the mixing chamber could affect the lifespan of air filters.
Neotectonics in Hydrocarbon Transportation Lines Corridors: The Need of a Detailed Study
Authors: Amórtegui José Vicente 
Published: January 2014

The Colombian pipeline network is exposed to the permanent activity of geological processes that happen in the country, due to the location of the country in the north-western corner of the South American plate — where it is interrelated to the Nazca and Caribbean plates —, the Andean zone is subject to compression strains that cause the uplifting of the mountain ranges and with it their slopes, which eases the instability processes. On the other hand, since the country is located in the inter-tropic zone of the planet, where the rock deterioration processes are harsher, landslides are more frequent, this together with the condition of strains, makes instability something fairly common.
Evidence on pipelines for hydrocarbon transport is obtained from the fault activity, like this:
The Santiago–El Porvenir oil pipeline, that rises from the plains to the mountain range, in December of 1991 a sudden linear landslide of the pipe was evidenced in the Santiago field (flat zone in the plains, south of Maní, Casanare), the position of the topographic control markers of the line was verified and a terrain shortening of 22.5cm was found in the markers located both sides of the Yopal fault, for this reason the pipe had moved from the area into the launching trap of Santiago, located 60km away from the trace of the fault.
In the Medellín–Cartago pipeline, in the crossing above the Cauca river, in the area of La Felisa, there is a 2.57m misalignment, in relation to the construction location, where the towers were aligned with the direction of the pipe, around 25 years ago. Nowadays the curve in the pipe suspended from the bridge cables can be observed, which, given the length of the bridge of around 200m doesn’t affect the mechanical conditions of the pipe. Along the Cauca river passes one of the geological faults of the Romeral system. (figure 5).
Due to the tracing of the initial pipes of the Cusiana Field, in the late 90s of the past century, a shortening of more than 2m of distance was detected between the geodesic spots of the National Geodesic Network, Taura and Mena, that are found beside the Guaicaramo faults system, these spots were built in the early 50s and located with first order geodesic precision procedures.