bluuebunny/crossref_metadata_2025_split huggingface dataset:
Optimal Thermal Management of Microelectronic Packages
Authors: Chiriac Victor 
Published: October 2015

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, at module and at system (module-board stack-up) levels. The microelectronics industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages.
A 3-D conjugate numerical study was conducted to evaluate the thermal performance of Gallium Arsenic (GaAs) die packaged in Quad Flat No Lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a Power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers.
Two powering scenarios are investigated: 1) one for standard operating parameters and 2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3x3 mm QFN under normal powering conditions is ~138.5°C (or 119°C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ~186°C (or 125°C/W junction-to-air thermal resistance). The top Au metal layer has limited impact on lateral heat spreading.
Under extreme powering conditions, the PQFN package reaches a peak temperature of ~126°C (66°C/W thermal resistance). A ~32% reduction in peak temperature is achieved with the 5x5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe and more board thermal vias.
A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package leads to only 3% reduction in peak temperature. By comparison, the die attach material (conductive epoxy vs. solder) has significant impact on overall reduction in peak temperature (~12%).
Experimental measurements using Infrared (IR) Microscope are performed to validate the numerical results.
Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV
Authors: Siblerud Paul , Beica Rozalia , Kim Bioh , Young Erik 
Published: October 2015

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow.
Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing
This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.
Integration Aspects of the Implementation of Through Silicon Vias (TSV) for CMOS Image Sensors
Authors: Thomas Dave , Michailos Jean , Hotellier Nicolas , Metellus Gilles , Guyader Francois , Inard Alain , Buchanan Keith , Sanz Dorleta Cortaberria , Song Yiping , Wilby Tony 
Published: October 2015

One of the first device types to benefit from TSV implementation is the CMOS image sensor, an image capture device designed to combine high image quality within a compact form-factor that can be mass produced at low cost. End markets include mobile phones, PDAs and gaming consoles.
STMicroelectronics is pioneering their production, based on ≤65nm CMOS technology, at its 300mm facility in Crolles. These sensors employ TSVs as part of a wafer level package allowing the camera module to be directly soldered to a phone PCB thereby saving cost, space and time to manufacture. SPTS's Versalis fxP system is being used to combine multiple TSV formation processes onto one platform including hard-mask deposition, hard-mask etching, TSV etching, partial PMD etching, dielectric liner deposition and spacer etching to define the area for the metal contact. All processes are carried out on a silicon wafer bonded to a glass carrier, through which the final device is illuminated.
We will present a TSV silicon etch process for 70 μm x 70 μm Vias in a thinned 300mm silicon wafer on glass carriers with an etch rate uniformity of ≤±1% and sidewall scalloping in the range 80–210 nm. We will show that this process can be conveniently mixed in production with the various oxide etches. A PECVD dielectric liner deposited at &lt;200 °C having excellent coverage, thermal stability and adhesion combined with a breakdown voltage &gt;8 MVcm−1 and leakage current &lt;1E-7 Acm−2 will also be described. Process integration aspects will be discussed using high resolution SEMS to show the key material interfaces in critical areas such as feature corners and along sidewalls.
Furthermore the successful implementation of TSV technology on ST's CMOS image sensors will be demonstrated through a combination of electrical characteristics, parametric device data and overall device performance/reliability.
Fluidic Devices in PCB Technology
Authors: Nowottnick Mathias , Pagel Lienhard , Gassmann Stefan 
Published: October 2015

Printed circuit boards (PCB) are widely used in electronics. They have the wiring and holding task for electronic devices. With the adding of more and more functionality to miniaturized devices the PCBs have to include more and more functionality. However, the usage of PCBs in fluidic applications is rare. Adding a fluidic functionality to a PCB will create intelligent fluidic systems at low cost. At the University of Rostock a special technology for creating fluidic systems in PCBs is developed. Low-Flow micro systems as well as High-Flow systems are feasible. The main advantage using PCBs is to create compact devices at low cost.
In this paper an overview is given over the devices made at the University of Rostock. This description include low flow devices like a thermopneumatical driven pump, a bimetal valve, a pressure sensor with force compensation, a bubble detector and static mixers. As well as a high flow device, the insufflator. The insufflator is a medical device where a flow rate of up to 45l/min has to be realized. This is a very good example for the high flow fluidic PCB technology where normal multi layer PCBs are used to hold the channels inside the PCB and connect pneumatic components electrically and pneumatically on the same substrate.
A short introduction to both technologies is given and the function of the devices is explained.
Integration of Electroactive Polymers in MEMS Ultrasonic Sensors
Authors: Kranz Michael , Whitley Michael , Sanchez Sharon , Allen Michael 
Published: October 2015

The U.S. Army AMRDEC, Stanley Associates, and the Georgia Institute of Technology are developing spectrally sensitive acoustic emission sensors for the detection of various phenomena of interest in Army missiles and assets. Multiple systems would benefit from monitoring the acoustic spectrum and identifying signatures of interest. These would include monitoring sounds external to Unattended Ground Sensors, looking for specific sounds associated with machine failure in a condition-based maintenance scenario, and identifying items that are impacting each other. Potential device designs employ electroactive polymers to convert acoustic waves into electrical impulses.
Many electroactive polymers are, however, not compatible with standard MEMS processing, particularly at elevated temperatures. Piezoelectric films, such as PVDF, require stretching and poling processes to orient the crystal structure. Electret films also require poling to create a permanent polarization, plus discharge occurs at relatively low-temperatures. These types of films are difficult to integrate directly into MEMS devices because of these incompatible processes. The films are therefore added using post-fabrication bonding and assembly processes, thus reducing design flexibility and increasing cost. This paper will present techniques being developed to integrate electroactive polymers directly in MEMS sensors as opposed to performing post-fabrication assembly of electroactive films into sensor structures.
Underfill Induced Tensile Strain Ratcheting and its Effect on Flip Chip Solder Bump Fatigue
Authors: Hillman Craig D. , Schueller Randy , Caswell Greg 
Published: October 2015

The effects of low Tg underfill material on the reliability of high-Pb first level interconnects were assessed through elastic-plastic finite element modeling and inspection of failure sites at the first-level interconnect. Temperature-dependent changes in specific underfill parameters (elastic modulus and coefficient of thermal expansion) induced a primary tensile stress within the solder bump. The presence and magnitude of this tensile stress were highly dependent upon the maximum and minimum temperature of exposure. Under certain specific thermal conditions, a form of tensile ratcheting was identified through finite element modeling.
The application of tensile stress was found to induce a change in degradation behavior and rates relative to the nominal shear stress state (see Figure). This effectively eliminated distance-to-neutral point as a predictor of first-level interconnects performance and required the development of new models to predict solder bump behavior. A discussion on this transformation in stress states and the potential influence on changes in part qualification procedures are provided.
ENEP – A Cost-Effective Alternative for High Reliability Soldering Applications
Authors: Ramos Gustavo , Oezkoek Mustafa , Lamprecht Sven , Roberts Hugh 
Published: October 2015

Electroless nickel / immersion gold (ENIG) has been recognized within the electronics packaging industry as a reliable surface finish for soldering applications. Unlike surface finishes, such as OSP, immersion silver or immersion tin, which produce a Cu-Sn intermetallic upon soldering, the nickel layer of ENIG acts as a barrier to minimize copper dissolution during the soldering application. This function is especially important for assemblies that require multiple reflow steps. However, if not properly controlled, excessive corrosion of the nickel by the immersion gold step can also cause the well documented “black pad” effect, often resulting in solder joint reliability issues, including brittle fracture.
As an alternative to ENIG, an electroless pure palladium layer over the electroless nickel (ENEP) provides a solderable surface without the noted risk of damage to the underling nickel layer. By eliminating the corrosive attack of the gold bath, the final layer stack would be suitable for high reliability soldering involving both IC substrate and PWB applications. In addition, because of the current high price of gold, replacing it with a pure palladium deposit can offer measureable cost savings for the ENEP process in comparison to ENIG.
The paper summarizes an in-depth study of the effect on solder joint reliability caused by replacing the immersion gold by an electroless pure palladium layer. The study includes evaluations for both Pb-free (Sn-3.0Ag-0.5Cu) and eutectic SnPb (63Sn-37Pb) soldering applications. Results of investigations include: (1) cold ball pull testing to evaluate solder joint integrity, (2) SEM examinations of the underlying nickel surface, (3) IMC examinations to quantify nickel thickness degradation after multiple solder reflow cycles and (4) surface wetting through solder spread examinations. The paper discusses the relatively simple surface finish that, if proven effective in large-scale fabrication, may offer measureable performance and cost benefits in comparison to the more traditional ENIG finish.
Wafer Level Packaging Cost Modeling
Authors: Palesko Chet A. 
Published: October 2015

Wafer level packaging is often the most cost effective approach to achieve miniaturization. However, if it is used for the wrong application, it can be very expensive. The significant difference in printed circuit board interconnect design rules and semiconductor interconnect design rules must be addressed in any type of packaging approach, and presents unique challenges for wafer level packaging. If miniaturization is not required, this translation of semiconductor design rules to PCB design rules is most easily accomplished in a traditional wire bond package. However, when the package size and the die size must be the same, the package IO count is limited. Fanout WLP is an option to overcome the WLP IO restriction, but still achieve cost effective miniaturization.
We will present the results of activity based cost and yield modeling of traditional wafer level packaging, fanout wafer level packaging, and flip chip packaging across a range of die sizes, package sizes, and defect densities. These results will show the most cost effective technology to match a variety of applications and package parameters.
ALX Polymer for Wafer Level Packaging: Mechanical Property Evaluation After Multiple Lead-Free Solder Reflows
Authors: Eriguchi Takeshi , Wang Orson , Tsuruoka Kaori , Ishibashi Yuichiro , Zhang Yong 
Published: October 2015

For bumping and wafer level packaging (WLP) applications, BCB and polyimide are the predominant spin-on dielectric materials used for re-passivation, redistribution, interlayer dielectric, and stress buffer layers. Each of these materials has their respective strengths and weaknesses. BCB has exceptionally low shrinkage on cure and moisture absorption, low curing temperature, and a low dielectric constant, but is a mechanically brittle material which limits its application in bump-on-polymer applications. Polyimides are superior mechanically to BCB and are utilized more in bump-on-polymer structures, but suffer from much higher shrinkage on cure and moisture absorption (which can lead to blistering if not carefully processed), have higher dielectric constants, and have much higher cure temperatures.
ALX spin-on polymer dielectric was developed to combine low shrinkage, low moisture absorption, low dielectric constant, and excellent mechanical and stress buffering properties with a cure temperature between 190C to 250C, depending on the application(1-3). Previous papers have reported the mechanical properties at 190C and the application of ALX in eutectic SnPb solder bump structures. The use of lead-free solder requires reflow temperatures up to 260C. Although ALX polymer is curable at less than 200C, the influence of lead-free solder reflow wasnft investigated. In this presentation we evaluate mechanical property changes of ALX Polymer films after different cure schedules and multiple reflows at lead-free solder temperatures. The impact of these parameters on WLP will be discussed.
Thin Film Packaging Reinforcement for Overmolded MEMS
Authors: Charlotte Gillot , Pornin Jean-Louis , Billard Christophe , Lagoute Emannuelle , Pellat Mihel , Parat Guy , Sillon Nicolas 
Published: October 2015

Thin Film packaging (TFP) is now well known at CEA/LETI and mainly used as a protection for MEMS against degradation which can occur during back end processes: TFP is strong enough to endure the mechanical constraints due to grinding, handling and protects the device from water during the sawing step. Our TFP process is also compatible with under bump metallisation, balling and flip chip processes. The main advantages of our TFP is a very low lost of silicon area, a low cost process with 3 mask levels, and is performed on equipments commonly used in IC fab. In this paper we will speek about process improvement for a TFP overmolded.
The thermo-mechanical constraints due to the standard overmolding step (100 bars and 200°C) are much more challenging for TFP: the cavity is about 5 μm high, the cap layer 2μm thick and the polymer plugging layer 6μm thick. So TFP needs to be reinforced to withstand these high constraints.
Two processes using conventional IC manufacturing technologies have been developed at wafer level with two materials. 200μm and 500μm wide cavities with TFP were reinforced with these processes and first tested under pneumatically pressure at room temperature: in case of contact between the cap and the substrate, a short circuit is measured between one electrode on the substrate and another electrode behind the cap. Then, the same devices were overmolded at 75 bars and 100 bars at 185°C. In the same run, BAW resonators with TFP and one type of reinforcement were overmolded at 100 bars. The electrical performances of these resonators after overmolding fit very well to the modelling of the test card and are very good. This Compatibility between TFP and overmolding constraints could be a cost effective solution in MEMS packaging.
TLP Bonding Technologies for Micro Joining and 3D Packaging
Authors: Murayama Kei , Aizawa Mitsuhiro , Higashi Mitsutoshi 
Published: October 2015

The bonding technique for High density Flip Chip(F.C.) packages requires a low temperature and a low stress process to have high reliability of the micro joining ,especially that for sensor MEMS packages requires hermetic sealing so as to ensure their performance.
The Transient Liquid Phase (TLP) bonding, that is a kind of diffusion bonding is a technique that connects the low melting point material such as Indium to the higher melting point metal such as Gold by the isothermal solidification and high-melting-point intermetallic compounds are formed. Therefore, it is a unique joining technique that can achieve not only the low temperature bonding and also the high temperature reliability.
The Gold-Indium TLP bonding technique can join parts at 180 degree C and after bonding the melting point of the junction is shifted to more than 495 degree C, therefore itfs possible to apply the low temperature bonding lower than the general use as a lead free material such as a SAC and raise the melting point more than AuSn solder which is used for the high temperature reliability usage. Therefore, the heat stress caused by bonding process can be expected to be lowered.
We examined wafer bonding and F.C bonding plus annealing technique by using electroplated Indium and Gold as a joint material. We confirmed that the shear strength obtained at the F.C. bonding plus anneal technique was equal with that of the wafer bonding process. Moreover, it was confirmed to ensure sufficient hermetic sealing in silicon cavity packages that had been bonded at 180 degree C. And the difference of the thermal stress that affect to the device by the bonding process was confirmed.
In this paper, we report on various possible application of the TLP bonding.
A High-Sensitivity Resonant Sensor Realised Through the Exploitation of Nonlinear Dynamic Behaviour
Authors: Waugh William , Gallacher B. J. , Burdess J. S. 
Published: October 2015

Existing MEMS viscometers and density meters typically measure vibrational characteristics such as resonant frequency, bandwidth and quality factor. In order to significantly improve sensitivity to changes in viscosity and/or density the proposed sensor will exploit nonlinear dynamic behaviour and measure the frequency separation between singular jump points in the frequency response function. By using a one-mode approximation when excited near resonance, the dynamics of a clamped-clamped slender beam in fluid is that of a standard Duffing oscillator. With harmonic forcing of sufficient magnitude, a bistable region, bounded by amplitude jump points, is seen to occur. The width of this bistable region is dependent on the damping ratio of the system, which is shown to be a function of the dynamic viscosity and density.
Experiments with clamped-clamped silicon beams in a range of gases demonstrate that the sensitivity of the proposed nonlinear sensor at low viscosity can be at least an order of magnitude better than that of conventional devices. Forcing magnitude and control is identified as being critical to the measured width of the bistable region. Beam dimensions can be chosen to optimise measurements for the desired application.
Thermally Conductive (TC) Plastics in LED Lamps
Authors: Janssen Rob , Douven Ir. L. , van Dijk H. K. 
Published: October 2015

In section 1, an assessment is made of the typical thermal conductivities attainable in a TC-plastic followed by an examination of the trade-off between increased thermal conductivity and decreased toughness caused by increasing filler load of such a TC-plastic.
Having established that currently there is a ceiling conductivity of around 25 W/mK for TC-plastics, i.e., well below the 100 W/mK TC level of metals, subsequently a basic analysis is provided on the suitability of materials with such moderate TC-levels in metal replacement. For this purpose, the ideal case of a unidirectional (1D) heat flow is considered in section 2, in section 3, a more complex case of a bidirectional heat flow is analyzed. Finally, section 4 considers the thermal performance of TC-plastics in a real 3D part, i.e., the heat sink housing of an LED lamp. More specifically, a comparison is made between the thermal performance of the housing molded in a heat conductive plastic and that of an all-aluminum housing. This comparison clearly demonstrates general validity and practical value of the conclusions drawn in sections 2 and 3 and highlights the outstanding suitability of TC-plastics for heat sinks in lighting applications. High performances STANYL TC in particular.
3D Modeling of Complex Combinations of Dies, Packages, Lead Frames, Sockets and Test Boards for Electrical, Thermal and Manufacturing Verification of Advanced Semiconductor Devices
Authors: Sovinsky John 
Published: October 2015

The software process described permits putting unlimited layers of dies and substrates in the same CAD database where many advanced optimizations and tunings can be accomplished on the entire electronic system simultaneously. Gates and swappable memory and FPGA pins may be optimally selected to reduce wire length and the number of routing layers. Die placement may also be optimized across multiple subtrates for the same purpose.
Interposers between substrates or side routing can be implemented and I/O locations optimized for maximum performance. Native scripts may be used to generate composite electrical models in the major electrical analysis tools that define 3D geometries precisely without 2-1/2 D abbreviations. Exact ACIS and Step models define the complex stackups for Thermal analysis in major Thermal Modeling softwares. All these models are created with high speed which enables the multiple design cycle iterations necessary for the refinement of a quality product. All relevant material properties and ports are exported with the 3D graphical data. Where appropriate changes are initialised back into parametric models.
Customizations of the process by the users are routine.