bluuebunny/crossref_metadata_2025_split huggingface dataset:
Characteristic Life Based Acceleration Transforms for Lead-Free Solder Joint Reliability under Thermal Cycling Conditions
Authors: Ahmad Mudasir , Liu Kuo-Chuan 
Published: October 2015

The conversion to Pb-free solders has already been implemented in the consumer market. However, the transition to Pb-free solders in the high performance, mission critical networking/server industry has not yet been fully implemented.
A significant factor in the slow transition to Pb-free solders is the absence of industry accepted Pb-free acceleration transforms that can translate lab test results into field reliability life data. Without such industry accepted acceleration transforms, it is difficult to translate lab test data into reliable predictions of field life performance.
In this two-phase study, a comprehensive set of test data have been generated over a wide spectrum of package types, solder joint metallurgies, joint size, pitch, die sizes, PCB thicknesses and thermal cycling conditions. The effect of aging on acceleration transforms was also included. The data has been analyzed and compared with existing Pb-free and SnPb acceleration transform models.
The data helps explain contradictions in the existing literature, and offers more comprehensive acceleration transforms for Pb-free solders. Some publications indicate that the acceleration transforms for Pb-free solders are the same as SnPb acceleration transforms [1]. Comprehensive results of this study also show that in specific conditions, Pb-free acceleration transforms could even be lower than SnPb acceleration transforms.
Challenges of Wire Bonding In High Value and High Performance Medical Devices
Authors: Ohneck James A. 
Published: October 2015

Wire bonding is a fairly mature technology that has been used in medical implantable products for over twenty years. Today however, its relevance continues to grow as the size of die continues to get smaller. Size, weight and volume are paramount when developing and manufacturing an implantable medical device, which often needs to perform a specific function such as, monitoring or adjusting parameters of the device itself, monitoring patient data or communicating data from the device to the healthcare professional.
Wire bonding can be the answer to addressing many of the requirements mentioned above. This paper will review the current status of the use of gold ball wire bonding and its relevance to the medical device industry as well as discuss how advancements in wire bonding processes benefit today's implantable products.
Wire bond interconnections can be made using gold, aluminum and copper wires. They each have different bonding characteristics and therefore require different application methods and equipment. The advantages and characteristics of gold ball wire bonding will be reviewed as this process relates to High Value Medical Devices.
Achieving high yields can also be a challenge with any wire bonding processes. Today's smaller die and pads require smaller gage wires. Typical production requirements are .8 – 1.2 mil wire and 4X4 pads. The demand to still go smaller requires continual adaptations and ingenuity as wire thicknesses are being pushed to .5 mils and below. Bond pull testing at the beginning, mid and end of production runs becomes important to verify integrity of the wire bonds with such small wire gages.
The complexities involved in wire bonding can lead to increased cost as well. To address this, a single process procedure is being adopted by many, which eliminates pattern plating and saves time and money. This new process will also be explained and reviewed.
Use of Wafer Applied Underfill for 3D Stacking
Authors: La Manna Antonio , Rebibis K. J. , Gerets C. , Beyne E. 
Published: October 2015

A key element for improving 3D stacking reliability is the choice of the right Underfill materials.
The Underfill is a specialized adhesive that has the main purposes of locking top and bottom dies; it must fill the gap between bumps and between dies, while reducing the differential movement that would occur during thermal cycling. Traditional underfill processes are based on local dispensing after solder bump reflow (Capillary dispensing), or before flip chip operation with no need of reflow (No Flow Underfill, NUF). In case of 3D stacking, such processes present some limitations: need of a dispensing area (die size increase); material flowing (spacing between dies) and cost (low throughput). After an introduction on typical underfill applications like die-to-package and die-die assembly, we report the work done to assess the properties of several Wafer Applied Underfill (WAUF) materials and their integration in 3D stacking. These materials have been initially applied on silicon wafers in order to assess the minimum achievable thickness and the material uniformity. The wafers have been coated by using different methods: spin coating and film lamination. After this initial assessment, the most promising materials have been used for 3D stacking. The test vehicle used has Cu/Sn μbumps with a pitch of 40μm. The quality of the materials is judged by electrical test, SAM (Surface Acoustic Microscope) and X-SEM (Scanning Electron Microscope).
Design and Fabrication of WLP Compatible Miniaturized Pressure Sensor System with Through Silicon Via (TSV) Interconnects
Authors: WANG Tao , CAI Jian , WANG Qian , ZHANG Hao , WANG Zheyao 
Published: October 2015

In this paper, a Wafer Level Packaging (WLP) compatible pressure sensor system enabled with Through Silicon Via (TSV) and Au-Sn inter-chip micro-bump bonding is designed and fabricated in lab, in which TSV transmits electrical signal from piezoresistive circuit to processing circuit vertically.
The pressure sensor system includes TSV integrated piezoresistive pressure sensor chip and Read-Out Integrated Chip (ROIC) in which TSV also incorporated. Two CMOS compatible fabrication process flows for pressure sensor system are demonstrated. And, flip chip bonding structure of TSV integrated pressure sensor with a ROIC are realized using one of these two process flows. Inter-chip interconnects enabled with TSV and micro-bump bonding is obtained.
Screen printed RFID antennas on low cost flexible substrates
Authors: Janeczek Kamil , Jakubowska Małgorzata , Kozioł Grażyna , Młożniak Anna , Sitek Janusz 
Published: October 2015

Recently, more and more studies are carried out in the field of printed RFID tags. It is connected with rapid development of new electronic technology, i.e. printed electronics which utilizes printing techniques, like screen printing, inkjet, flexography or gravure, for production of electronic components. This method is on one hand environmentally friendly because it allows eliminating wastes emerging during etching process used commonly in electronics. On the other hand, components can be printed on low cost flexible substrates, like foil or paper. These two factors cause that such products are cheap and can be competitive with their equivalents used currently.
In this study, investigations of RFID tag antennas working in UHF frequency range made with screen printing technique are described. Conductive polymer pastes containing silver nanopowder, silver flakes or carbon nanotubes were used for antenna fabrication. Each of them was deposited on foil and paper. Properties of printed antennas were investigated by return loss measurements performed in the frequency range 0.5 ÷ 1.5 GHz. Achieved results were compared with simulation carried out in CST Microwave Studio. Antenna surface profile was checked using optical profilometer or metallographic microscope. Its mechanical tests were also conducted. The obtained results showed that the best candidate for antenna printing on flexible substrate was the paste with silver nanopowder because it combined high conductivity and high mechanical durability.
Accelerated Life Tests of Flip-Chips With Solder Bumps Down to 30 μm Diameter
Authors: Dohle Rainer , Härter Stefan , Goßler Jörg , Franke Jörg 
Published: October 2015

In this study, accelerated life tests with ultra fine-pitch flip-chips with solder bumps down to 30 microns diameter have been performed. Tests commonly used like temperature cycling, high temperature storage, and humidity bias tests are not sufficient for such small packaging feature sizes any more. As solder bump sizes continue to decrease, along with the shrinkage of the solder pads and the scaling of line/space geometries, thermal diffusion has even more impact on reliability and lifetime of the solder connections, and current densities within single solder bumps increase. Therefore, electromigration of flip-chip interconnects is a significant reliability concern, especially when it comes to further miniaturization for high reliability applications. Since electromigration is a function of interconnect sizes and metallurgies, new interconnect developments need to be characterized for electromigration reliability.
Flip-chips 10 mm × 10 mm × 0.8 mm in size with a die layout providing a pitch of 100 μm for solder bump sizes of 60 μm, 50 μm, 40 μm, or 30 μm diameter, respectively, have been used [1]. The SnAgCu alloy solder spheres were placed on a NiAu UBM realized in an electroless nickel process [2]. A daisy chain connection is integrated for each of the solder sphere sizes and each chip can separately be connected for online measurements during electromigration or reliability testing.
A variety of current density and temperature combinations which is individually adapted to the respective solder sphere diameter has been used. Lifetime data were collected using online measurement through the daisy chains. Cross sectioning has been employed to analyze the influence of thermal diffusion as well as electromigration on the failure mechanism of the highly miniaturized solder joints. A prediction model for flip-chip interconnects with solder spheres down to 30 μm diameter will be outlined using Black’s equation.
Cost effective Precision 3D Glass Microfabrication for Electronic Packaging
Authors: Flemming Jeb H. , Dunn Kevin , Gouker James , Schmidt Carrie , Buckley Colin 
Published: October 2015

The most singular focus of the electronics industry during the last 50 years has been to miniaturize ICs by miniaturization of transistors and on-chip interconnections. Two major problems are foreseen with this approach; (1) electrical leakage and (2) the lack of improved electrical performance beyond 16nm. As a result, the industry is transitioning from the current SOC-based approach to a through-silicon-via (TSV) based 3D IC-stacked approach. However, a major challenge remains; these 3D ICs need to be interconnected to other ICs with a much higher number of I/Os than are available with current ceramic or organic interposers. While silicon interposers currently in development can provide these high I/Os, they cannot do so at low enough cost.
In this extended abstract, 3D Glass Solutions, a division of Life BioScience, Inc., presents our efforts in glass interposer microfabrication. Glass interposers possess many advantages over silicon interposers including: cost, production time, and scale. 3D Glass Solution’s APEX™ Glass ceramic is a photo-sensitive material used to create high density arrays of through glass vias (TGVs) using three simple processing steps: exposure, baking, and etching. To date, we have been successful in producing large arrays of 12 micron diameter TGVs, with 14 micron center-to-center pitch, in 125 micron thick APEX™ Glass ceramic. This extended abstract covers (1) on our efforts producing high aspect ratio TGVs in ultra thin (75–250 micron) APEX™ Glass ceramic wafers, (2) maximum TGV aspect ratios, and (3) TGV fidelity and limits of manufacturing.
APPLICATIONS OF SOLDER PREFORMS TO IMPROVE RELIABILITY
Authors: Gowans Carol , Homer Seth , Lasky Ronald 
Published: October 2015

As early as the 1990s people were predicting the end of through-hole components, but they are alive and well with the numbers of dual in-line packages (DIPs) and connectors still measured in the 10s of billions per year. Many of these components are assembled by wave soldering, however in mixed technology (SMT and through-hole on the same board) where the through-hole count is low, it is often advantageous to consider selective soldering or the pin-in-paste process (PIP). PIP is a process in which solder paste is printed over or near the PWB through-holes. The through-hole components are then placed and the solder joint is formed during the reflow process. PIP has the advantage of eliminating the wave soldering process step. In many cases it is difficult to print enough solder paste to make an acceptable through-hole solder joint. Solder preforms were developed to meet this need.
These solder preforms are typically shaped in the form of 0402, 0603, or 0805 passive components. The preforms are placed on the appropriate printed solder paste deposit by a component placement machine. Preforms come in tape & reel packaging.
Today solder preforms are also used in other “solder starved” applications such as radio frequency (RF) shields, connectors, and under QFN thermal pads. In all cases, the extra solder delivered by the preform is vital to the reliability of the assembled product.
In this paper, process, design, and assembly methods for solder fortification using preforms will be discussed. Four successful solder fortification examples will be presented along with the associated defect reductions.
Embedded Actives and Its Industry Effects
Authors: Fillion Ray 
Published: October 2015

Over the 60 plus year history of microelectronics packaging, electronic devices have been mounted onto an interconnect structure to form a microelectronics circuit. The devices could be bare chips, CSPs or packaged components such as SMT or thru-hole carriers. The interconnect structures could be circuit boards, ceramic substrates or flex circuits. This methodology has enabled a clear divide between the fabrication, assembly and test of the semiconductor device, the fabrication and test of the interconnect structure and the assembly and test of the component/substrate assembly.
Over the past decade a new packaging methodology, embedded actives (chips), has been developed that changes all of these industry norms. In an embedded actives packaging approach, one or more bare or chip scale semiconductor devices are embedded within the interconnect structure. Although these approaches have significant electrical performance, size and cost benefits, the normal barriers between chip packaging, substrate fabrication and component assembly are removed. The interconnect structure is not completed prior to component embedding and the embedded component cannot be tested at packaged part level without the interconnect structure. This complicates electrical testing and makes it virtually impossible to differentiate between a defective component, a defective interconnect or a defective component to substrate contact.
This paper will look at the history of embedded active developments and go into the various processes and structures being used. It will cover their electrical, reliability and size advantages and will address the revolutionary changes that the microelectronics industry must make to effectively utilize these technologies.
Technologies and Trends to Improve Power Electronic Packaging
Authors: Schneider-Ramelow M. , Hutter M. , Oppermann H. , Göhre J.-M. , Schmitz S. , Hoene E. , Lang K.-D. 
Published: October 2015

In the realm of power modules a strong trend toward high temperature and high reliability applications can be observed, which entails new technological challenges, especially for the assembly and packaging of power semiconductors. Because of the well known failure mechanisms of established lead-free standard soldering and heavy aluminum wire bonding technologies, such as fatigue and creep of die attach material and wire bonds at thermal cycling, academic and industrial research focuses on more reliable interconnection technologies.
A priority is the research of alternative top and bottom side chip interconnection materials or technologies to improve the temperature cycling capability of power chips that are typically assembled on ceramic substrates. The scientific focus is on Ag sintering as die attach and/or heavy ribbon bonding, for example with Al or bi-metal (Al-Cu). Another focus is the material behavior of ribbon bonds in combination with bonding machine improvements (higher bonding parameters, cutting tool). But there are other very promising technologies like transient liquid phase bonding, for example with Cu-Sn or Ag-Sn systems or Cu heavy wire bonding (up to 400 μm wire diameter) or Cu/Al-Bi metal ribbon bonding.
Challenges posed by these technologies have to be discussed focusing on materials and process selection and reliability issues. Process temperatures and temperature profiles must be optimized, wire bonding machines and the chip surface structures as well as finish metallizations need to be adapted.
This paper will give an overview of alternative power chip interconnection technologies and discuss the challenges related to processing and reliability.
Advanced Thermal Study of Very High Power TSV Interposer and Interconnects for 28nm Technology FPGA
Authors: Banijamali Bahareh , Ramalingam Suresh , Chaware Raghunandan 
Published: October 2015

TSV interposer has emerged as a good solution to provide high wiring density interconnections and improved electrical performance due to shorter interconnection from the die to substrate. Furthermore, silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps.
This paper presents the thermal study of TSV interposer technology for a high-performance 28nm logic die that is mounted on a large silicon interposer with Cu through silicon via. A representative silicon interposer test chip with thousands of micro-bumps at 45um pitch has been fabricated. The silicon interposer is 100um thick, and is mounted on a 42.5mmx42.5mm substrate through 180um pitch C4 bumps. 3D thermal modeling and simulation for the packaged device with TSV interposer have been performed. Several DOEs have been constructed to optimize thermal interface material selection and to study the effect of high power and hot spots on underfill and solder bump material properties as well as the effect of bump pitch and underfill properties on the die junction temperatures. Furthermore, thermal behavior of 28nm technology monolithic FPGA was compared to the 3D TSV interposer FPGA package. Optimized passive thermal solution was recommended for this high power FPGA in order to cool down up to 100 Watt power.
Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Molded Underfill Technology
Authors: Tamil Jonathan , Ore Siew Hoon , Gan Kian Yeow , Bo Yang Yong , Ng Geraldine , Wah Park Teck , Suthiwongsunthorn Nathapong , Chungpaiboonpatana Surasit 
Published: October 2015

Increasing challenges are faced to ensure moldability with rapid advances in flip chip technology such as decreasing bump pitch and stand-off height, especially when commercial Moldable Underfill (MUF) is used and in particular, during panel level molding. One key challenge faced is severe void entrapment under the die. Experiments involving a large DOE matrix, which require significant time and process resources, are typically used to solve this issue. 3D flow simulation can be used to optimize the process to reduce defects without doing actual runs. Mold flow simulation can effectively reduce the design-to-implementation cycle time, identifying key problems before actual fabrication. In this paper, 3D mold flow simulation using Moldex3DTM V10 is applied to transfer molding to optimize design and process parameters.
This paper proposes and verifies a systematic method that can save computational resources by using 2 steps analysis: simplified panel simulation and single package simulation. The initial step, simplified panel level simulation, is to optimize the process parameters to obtain balanced melt front. The second step is to study on the package level the effect of various package-scale parameters. This analysis provides a prediction of the void location and an insight on the appropriate parameters to minimize void problem. The actual voids location and size from the experiment was captured by SAT machine and short shots were obtained. For final validation, a complete panel-level flow model is built, where the process and design parameters adopted in the actual molding were implemented. The mold filling simulation showed good correlation with the experimental short shots and actual void location. With optimized parameters from the simulation used as guidelines, experimental tests were conducted and the study showed that the simulation is a useful tool to optimize the molding process.
Thin-film High Voltage Capacitors for Hybrid Electric Vehicle Inverter Applications
Authors: Fairchild M. Ray , Berlin Carl W. , Sarma D.H.R. , Taylor Ralph S. , Lee Han S. , Staller Steven E. 
Published: October 2015

The propulsion system in hybrid electric vehicles (HEVs) requires an alternating current (AC) electric motor in combination with an internal combustion engine. When the HEV is being propelled by the AC motor, the power for the motor is provided by batteries whose direct current (DC) voltage is chopped into an AC waveform via an electronic device called a power inverter. Capacitors known as DC bulk capacitors are placed between the battery and the inverter to “decouple” the AC switching inverter from the power source. Power electronics inverters use several large high voltage discrete DC bulk capacitors, which negatively influence the inverter's size, weight and are a high cost item in the assembly.
The use of a high dielectric constant (Dk) ferroelectric material enables smaller, higher temperature capable, lower-cost power capacitors. Ceramic ferroelectrics, such as (Pb,La)(Zr,Ti)O3 [PLZT], offer the highest dielectric constants. Argonne National Laboratory is developing a novel film-on-foil technology for high-power capacitors utilizing PLZT. These capacitors, with an increasing dielectric constant with temperature, low equivalent series resistance and a benign failure mode, are well suited for power applications. The PLZT is deposited onto a metal foil via a chemical deposition process and the top electrode metal (Pt or Al) is then deposited by electron beam evaporation onto the top surface of the dielectric thus creating the capacitor.
This project involved the fabrication and electrical evaluation of film-on-foil capacitors for HEV inverter applications. Capacitors utilizing both nickel and platinum-on-silicon as the base substrate, and PLZT as the dielectric material were fabricated. These capacitors were tested for dielectric integrity, capacitance, voltage breakdown, and benign failure mode. Results from these mechanical and electrical evaluation tests will be presented. Key processing challenges and implementation methods will also be described.