bluuebunny/crossref_metadata_2025_split huggingface dataset:
Design and Assembly of High Temperature Distributed Aero-engine Control System Demonstrator
Authors: Riches S T , Warn C , Cannon K , Rickard G , Stoica L , Johnston C 
Published: October 2015

This paper covers the development of a distributed high temperature electronics demonstrator for integration with sensor elements to provide digital outputs that can be used by the FADEC (Full Authority Digital Electronic Control) system or the EHMS (Engine Health Monitoring System) on an aircraft engine. This distributed electronics demonstrator eliminates the need for the FADEC or EHMS to process the sensor signal, which will assist in making the overall system more accurate and efficient in processing only digital signals. This will offer weight savings in cables, harnesses and connector pin reduction.
The design concept was to take the output from several on-engine sensors, carry out the signal conditioning, multiplexing, analogue to digital conversion and data transmission through a serial data bus. The unit has to meet the environmental requirements of DO-160 with the need to operate at 200°C, with short term operation at temperatures up to 250°C.
The work undertaken has been to design an ASIC based on 1.0μm Silicon on Insulator (SOI) device technology incorporating sensor signal conditioning electronics for sensors including resistance temperature probes, strain gauges, thermocouples, torque and frequency inputs. The ASIC contains analogue multiplexers, temperature stable voltage band-gap reference and bias circuits, ADC, BIST, core logic, DIN inputs and two parallel ARINC 429 serial databuses. The ASIC was tested and showed to be functional up to a maximum temperature of 275°C.
The ASIC has been integrated with other high temperature components including voltage regulators, a crystal oscillator, precision resistors, silicon capacitors within a hermetic hybrid package. The hybrid circuit has been assembled within a stainless steel enclosure with high temperature connectors. The high temperature electronics demonstrator has been shown to operate from −40°C to +250°C.
This work has been carried out under the EU Clean Sky HIGHTECS project with the Project being led by Turbomeca (Fr) and carried out by GE Aviation Systems (UK), GE Research – Munich (D) and Oxford University (UK).
230°C Accelerometer with Digitized Output for Directional Drilling
Authors: MacGugan Douglas C. , Abbott Eric C. , Milne J. Chris 
Published: October 2015

Measurement-While-Drilling (MWD) technology for oil and gas, and geothermal directional drilling exploration is pushing into ever higher temperature environments - beyond 200°C. Orientation sensors supporting these high temperature environments need to provide highly accurate elevation and tool face measurements on the order of 0.1°. Honeywell has developed a new digital high temperature down-hole accelerometer, DHTA230, capable of providing the required accuracy at the elevated temperatures of 230°C, in the rugged MWD shock and vibration environment, with expected excellent reliability and life.
The DHTA230 is designed for use in the downhole environment, but is based upon a mature Honeywell accelerometer using dual vibrating beam sensing elements. These sensing elements are configured as double-ended-tuning-forks in a push-pull orientation attached onto a pendulous proof mass. This push-pull configuration provides an acceleration signal proportional to the frequency difference of the vibrating beams, an easily captured digital signal through measurement of the two vibrating beam phases. The digitized accelerometer eliminates the need for A/D electronics in the high temperature drilling environment. The DHTA230 is 0.79” in diameter with a depth of .393” at the mount flange. The ruggedized configuration of the DHTA230 is expected to provide reliable orientation measurement in high temperature direction drilling applications up to 1000h.
The DHTA230 electronics incorporate ceramic hybrids with chip and wire construction. Active die are based upon proven 300°C chips developed previously for the Enhanced Geothermal Systems OM300, fabricated using Honeywell HTSOI4 process. The electronics include power conditioning providing reliable operation using a single power supply between 7V and 15V. Dual oscillator electronic circuits provide the necessary function to drive and sense the dual vibrating beams, while providing a CMOS logic level signal of the frequency pulse train. The accelerometer provides precision output up to 15g acceleration inputs, and allows sensing of higher-g vibration levels.
This paper contains information on the target application, electrical and mechanical component requirements, design, fabrication approach, and initial prototype testing. The DHTA230 is expected to enter production transition in 2015.
Design Considerations for Reliable High Temperature Operation of Wet Electrolytic Tantalum Capacitors
Authors: Ladd Jeremy 
Published: October 2015

Wet electrolytic tantalum (Ta) capacitors have historically been utilized in a variety of applications which endure harsh ambient conditions. Thermal, electrical and mechanical stresses, though, pose significant challenges to reliable performance of these capacitors in such environments. Thermal stress can increase the internal pressure of the capacitors, as well as mechanically compromise some of the components of which the capacitors are comprised. Electrical stress, in the form of current flow due to applied voltage, can elicit hydrogen gas evolution, which further exacerbates the internal pressure issue, potentially embrittles Ta components, and degrades AC performance of the capacitors. Mechanical stress, resulting from shock and vibration for example, can jeopardize the internal mechanical integrity of the capacitors.
This paper elaborates on these obstacles, and offers design approaches to reliably overcome them. Also presented are results of high temperature performance, predominantly up to 230°C, but also a mention of limited 245°C results, of wet Ta capacitors manufactured with proper attention paid to these concerns.
Pressureless, Low Temperature Sintering of Micro-scale Silver Paste for Die Attach for 300°C Applications
Authors: Yu Fang , Johnson R. Wayne , Hamilton Michael 
Published: October 2015

Low temperature Ag sintering technology provides a lead-free die attachment compatible with high temperature (300°C) applications. Previous work with Ag sintering has required pressure during the sintering process or been limited to small area die. In this paper, the pressureless sintering of micro-scale silver paste is examined for larger (8mm × 8mm) area die. Experimental combinations included: Si die metallization (Ag and Au); thick film substrate metallization (Au, Ag and PdAg); and sintering temperature.
For Au metallization (die and/or substrate), the initial shear strength results were good with 8mm × 8mm die sintered at lower temperatures (200°C). The shear strength was beyond the limit of the shear test machine (100 kg), corresponding to &gt;15.3 MPa. However, after aging for 24 hours at 300°C, the shear strength dropped significantly. An SEM was used to characterize cross sections of as-built and aged sample. The decrease in die shear strength with high temperature sintering (250°C and 300°C) or high temperature aging is attributed to surface diffusion of Ag along the Au surface resulting in a dense Ag layer adjacent to the Au surface and a depletion layer within the die attach adjacent to the dense Ag layer. Shear failures occurred through the depleted region.
For Ag metallization (die and substrate), no decrease in shear strength was observed with 300°C aging. Shear strength of 8 mm × 8 mm dies was &gt;100 kg ( &gt;15.3 MPa) as-built. The shear strength remained &gt;15.3MPa after 3000 hours of 300°C aging.
KEMET SMD Film Capacitors for High Temperature Applications
Authors: Caliari Luca , Bettacchi Paola , Boni Evangelista , Montanari Davide , Gamberini Arrigo , Barbieri Luigi , Bergamaschi Francesco 
Published: October 2015

Trends of several applications like down-hole drilling, commercial aviation (e.g. jet engines), heavy industrial and automotive are challenging the capabilities of capacitors and other electronic components.
The growing harsh-environment conditions for these applications are: high temperature, high voltage and high current. At the capacitor component level, required features are: very high reliability under mechanical shock, rapid changes in temperature, low leakage current (high insulation resistance), small dimensions, good stability with time and humidity, and high peak withstanding voltage. Capacitors for power-conversion circuitry must maintain a low AC loss and DC leakage at high temperatures.
KEMET has recently designed film capacitor series using PEN to address the needs of the above mentioned circuits, in particular regarding the working temperature, voltage and current.
This paper will cover technological advances in film capacitor technology to address harsh environment conditions needs, providing test results on temperature, voltage and thermal shock acceleration factor.
285°C Resistor Drift and Failure Analysis
Authors: Watts Milton , Smith Ron 
Published: October 2015

In order to improve the reliability of down-hole electronics, Quartzdyne Electronics has invested millions of device test hours in life testing circuits in both powered and un-powered modes. In addition to time at temperature, these tests include thermal cycling and high impact drop testing. Resistors drift has become a significant wear-out mechanism in these tests. Prior testing has shown that resistor material, substrate material, resistance range and trim method each play a significant role in resistor stability at elevated temperatures. Some resistance ranges tested had no acceptable performers.
The purpose of this study is to expand the range of values, materials and package sizes in hopes of identifying reliable resistors for high temperature applications. This study will focus on a broad range of NiCr-on-silicon resistors, including larger package sizes than were previously tested. Additionally, we will be testing several precision foil-type resistors. Resistors will be mounted in hermetic packages and aged at 285°C for 1000 hours. The packages will be removed from the oven periodically and the resistance of the devices will be measured at ambient temperature. This study is being done in cooperation with resistor vendors who have supplied some of the devices for this test.
Au-Sn SLID bonding for high temperature applications
Authors: Tollefsen Torleif André , Larsson Andreas , Aasmundtveit Knut 
Published: October 2015

Au-Sn solid-liquid-interdiffusion (SLID) bonding is a novel and promising interconnect technology for high temperature (HT) applications. In combination with Silicon Carbide (SiC) devices, Au-Sn SLID has the potential of being a key technology for the next generation of innovative, cost effective and environmentally friendly drilling and well intervention systems for the oil industry. However, limited knowledge about Au-Sn SLID bonding for combined HT and high power applications is a major restriction to fully realize the high temperature potential of SiC devices. This paper presents a comprehensive study of fluxless Au-Sn SLID bonding.
Two different processing techniques – electroplating of Au / Sn layers and sandwiching of eutectic Au-Sn preform between electroplated Au layers – have been studied in a simplified metallization system. The latter process was further investigated in two different Cu / Si3N4 / Cu / NiP / Au-Sn / Ni / Ni2Si / SiC systems (different Au-layer thickness). Die shear tests and cross-sections have been performed on “as bonded”, thermally cycled and thermally aged samples to characterize the bonding properties associated with the different processing techniques, metallization schemes and environmental stress tests.
A uniform Au-rich bond interface is produced (the ζ phase with a melting point of 522 °C). The importance of excess Au on both substrate and chip side in the final bond is demonstrated. It is shown that Au-Sn SLID can absorb thermo-mechanical stresses induced by large CTE mismatches (up to 12 ppm/K) in a packaging system during HT thermal cycling. The bonding strength of Au-Sn SLID is shown to be superb, exceeding 78 MPa. Importantly, Au-Sn SLID is shown to be an excellent interconnect technology for HT packaging.
High Temperature Silicon Carbide Power Modules for High Performance Systems
Authors: Hornberger J. , McPherson B. , Bourne J. , Shaw R. , Cilio E. , Cilio W. , Reese B. , Heinrichs E. , McNutt T. , Schupbach M. , Lostetter A.B. 
Published: October 2015

The demands of modern high-performance power electronics systems are rapidly surpassing the power density, efficiency, and reliability limitations defined by the intrinsic properties of silicon-based semiconductors. The advantages of silicon carbide (SiC) are well known, including high temperature operation, high voltage blocking capability, high speed switching, and high energy efficiency. In this discussion, APEI, Inc. presents two newly developed high performance SiC power modules for extreme environment systems and applications. These power modules are rated to 1200V, are operational at currents greater than 100A, can perform at temperatures in excess of 250 °C, and are designed to house various SiC devices, including MOSFETs, JFETs, or BJTs.
One newly developed module is designed for high performance, ultra-high reliability systems such as aircraft and spacecraft, and features a hermetically sealed package with a ring seal technology capable of sustaining temperatures in excess of 400°C. The second module is designed for high performance commercial and industrial systems such as hybrid electric vehicles or renewable energy applications, implements a novel ultra-low parasitic packaging approach that enables high switching frequencies in excess of 100 kHz, and weighs in at just over 130 grams (offering ~5× mass reduction and ~3× size reduction in comparison with industry standard power brick packaging technology). It is configurable as either a half or full bridge converter. In this discussion, APEI, Inc. introduces these products and presents practical testing of each.
Ultra low power CMOS circuits working in subthreshold regime for high temperature and radiation environments
Authors: Boufouss E. , Francis L. A. , Gérard P. , Assaad M. , Flandre D. 
Published: October 2015

We present three ultra-low-power CMOS circuits: a temperature sensor, a voltage reference and a comparator developed for an ultra-low-power microsystem (ULP-MST) aiming at temperature sensing in harsh environments. The microsystem has 3 main functions: detecting a user-defined temperature threshold T0, generating a wake-up signal that turns on a data-acquisition microprocessor (located in a safe area) above T0, and measuring temperatures above T0.
To achieve ultra-low-power operation, the three CMOS circuits are implemented in Silicon-on-Insulator (SOI) CMOS technology and are optimized to work in the subthreshold regime of the transistors. Since our application is mainly for harsh environment (i.e. high temperature and radiation), the chip has been designed using a suitable 1-μm SOI-CMOS technology. Simulations have been performed over the different process corners to verify functionality after fabrication. The typical power dissipation at high temperature (up to 240°C) is less than 100 μW at 5 V supply voltage. Measurements have validated correct operation in the temperature range from −40°C to 300°C before radiation and to 125°C after radiation up to now which will be extended further with a new set-up.
Irradiation has been performed from 10 to 30 kGy. Such very high doses cause a shift down of output voltage values, which leads to a change of the temperature detection level and also increases the power dissipation by up to six times. Annealing effects help the partial recovery of the device operation at high temperature and the remote microprocessor enables calibration after radiation to readjust the temperature detection level.
The European SEEL (Solutions for energy efficient lighting) project: High temperature electronics for LED-lighting architectures
Authors: Habenicht S. , Funke H.J. , Gruber D. , Oelgeschläger D. , Schumacher O. , Gehn R. , Walczyk S. , Mavinkurve A. , Reiners Th. , Fiederling R. , Vogl M. , Schug J. , Willwohl H. , Blandin J. , Hutter M. , Ehrhardt C. , Oppermann H. 
Published: October 2015

Due to superior properties in energy-efficiency and design freedom, the “liberation of light” by LED-technology will draw more attention in future applications. Within the European SEEL project, the partners are performing research in enabling technologies for high-temperature electronics (up to 185°C) to be designed into the next generation of high-efficient LED-driver circuits. This requires high-temperature evaluation of the product architecture of electronic components, i.e. the 1st-level interconnection, i.e. the chip metallization and the chip bonding technology. Different methods such as Au- and Cu-wirebonding as well as soft-soldering technologies are evaluated and discussed. The material properties, i.e. the encapsulating mound compound and the die adhesives play an important role as these materials tend to degrade at elevated temperatures. On top of that, also the board mounting architecture of the products, i.e. the board materials and the interconnection techniques such as high-temperature soldering play an important role and have to be discussed during the architecture evaluation, as solder joints and board materials are prominent candidates for mechanical degradation during high-temperature treatment. Thermal aspects in the circuit design in order to prevent part of the system architecture from overheating during operation, play an important role in the system design.
The current status of the project as well as the future exploitation outlook will be presented.
Reliability Modeling to Enable Damage Assessments for Plated Through Holes
Authors: Sharon Gilad , Barker Donald 
Published: October 2015

A modeling approach to assess the reliability characteristics of the copper used in printed circuit boards (PCBs) is presented. Plated Through Holes (PTHs) for electrical connections across PCBs are formed by drilling the PCB and electroplating the hole, often using a copper (Cu) finish. Although the mechanical strain on the Cu in the center of the PTH may be insignificant to disrupt circuit functioning in a single reflow soldering cycle, more substantial damage accrues over multiple reflow cycles. Loads applied after the reflow cycles are shown to contribute to subsequent mechanical disconnects.
Efforts to quantify the damage to the Cu are hindered by the difficulties of measuring direct strain or displacement inside a PTH and extrapolating the damage to the Cu in the first three reflow cycles.
The assessment of damage to the Cu is enabled by finite element analysis. The authors' finite element model is defined as a single load system based on PTHs with flanges on every side of the laminate board connected by a hollow cylinder, a configuration treated as symmetric from the center of the board. The critical area of focus is the inner ring of the PTH. Stress and strain measurements in the region of interest are obtained using numerical simulations. The two-dimensional axi-symmetric model is validated against a three-dimensional full model and several test cases.
Reliability assessments relying on undamaged circuits are shown to be less accurate than estimates incorporating Cu damage following three reflow cycles. An increased probability of intermittent connection for the PTH's remaining use is suggested. Accordingly, the authors propose that damage assessments of copper finishes be incorporated into models of PCB reliability.
Tape-Peel Testing as a Simple Method to Evaluate the Adhesion of Coated Layers on Metal Core PCB
Authors: Scholz Bernd , Pekmic Ismir , Ahmad Syed Sajid , Reinholz Aaron 
Published: October 2015

Conventional printed circuit boards (PCBs) may be replaced by thinner metal-core boards for some applications, as well as for package substrates. Using thin, metal-core technology may provide advantages for radio frequency (RF) circuits and packages, and increase heat dissipation for high power applications.
The metal-core technology discussed in this paper has several layers including the metal core, electro-coated dielectric, sputtered metal layers, and electroplated copper. For PCB and substrate reliability, it is important to have sufficient adhesion between the dielectric layer and plated copper. Sputtered metal layers with cleaning pre-treatments are one of the methods to improve the interfacial adhesion.
This paper describes an efficient testing method for the adhesion of a thin sputtered metal layer to a dielectric substrate. In this method, adhesive tape was attached to the surface and peeled off at 90 degrees in a tensile tester. Due to the sub-micron thickness of the sputtered layers, conventional peel test methods could not be applied. Typical adhesion testing of upper layers like paint coatings use a lattice pattern. The new method provided a convenient, repeatable way to evaluate the adhesion of three different sputtered metals with fifteen different pretreatment combinations. The test results were used to choose the sputtered metal and were later confirmed by testing the copper plated assembly using the metal adhesion specification in the industry standard IPC-TM-650.
A review of other methods and the need to identify an easy to use method which can provide repeatable quantitative measurements.
A study of high Cu behavior on electrolytic Ni and electroless Ni pad finish
Authors: Lee Hyun-Kyu , Chu Yong-Chul , Chun Myung-Ho , Jeon Sang-Ho 
Published: October 2015

It has been used various pad finish materials to enhance the reliability of solder joint and Electroless Ni Immersion Gold (the following : ENIG) pad has been used more than others.
This study is about reliability according to being used in commercial Electrolytic Ni pad and ENIG pad, and was observed behavior of various Cu contents.
After reflow, the inter-metallic compound (IMC) between solder and pad is composed of Cu6Sn5 (Ni substituted) by using EDS, and in case of ENIG, between IMC and Ni layer was observed the dark layer (Ni3P layer).
Additional, it could be controlled the thickness of dark layer according to Cu contents.
Investigated the different fracture mode between electrolytic Ni and ENIG pad after drop shock test, in case of soft Ni, accelerated stress propagated along the interface between 1st IMC and 2nd IMC, and in case of ENIG pad, accelerated stress propagated along the weaken surface such as dark layer.
The unstable interface exists through IMC, pad material and solder bulk by the lattice mismatch, so that the thermal and physical stress due to the continuous exterior impact is transferred to the IMC interface. Therefore, it is strongly requested to control solder morphology, IMC shape and thickness to improve the solder reliability.