bluuebunny/crossref_metadata_2025_split huggingface dataset:
GHz High Frequency TSV for 2.5D IC Packaging
Authors: Chen Chi-Han , Lu Kuan-Chung , Hung Chang-Ying , Lee Pao-Nan , Wang Meng-Jen , Hung Chih-Pin , Tong Ho-Ming , Horng Tzyy-Sheng 
Published: October 2015

TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC stacking solution in FCBGA (Flip Chip Ball Grid Array). As the 2.5D interposer design pushing toward smaller & shorter via due to high I/O density and high frequency requirement, the electrical performance of thinner interposer is therefore much more challenging in low signal loss performance for high frequency application and process.
From the structure point of view, the silicon interposer is an additive layer between top side chip(s) and bottom side substrate, it is therefore an additional electrical interconnection which affects the signal propagation between chip(s) and substrate. Therefore, the performance of the TSV insertion loss in silicon interposer becomes critical, especially for above GHz application.
Real measurement is conducted to validate the electrical performance of TSV interconnection up to 67GHz, and the wideband scalable model of TSV is also proposed and compared with the measured data. The measurement of this TSV structure has demonstrated the advantages with low parasitic capacitance and low insertion loss at high frequency. Full validated reliability test is also presented to verify interposer fabrication, assembly process optimization, and interconnection stability of the 2.5D IC package.
Precision Jetting of Glob Top Materials – a methodology for process optimization
Authors: Becker K.-F. , Koch M. , Bauer J. , Braun T. , Aschenbrenner R. , Schneider-Ramelow M. , Lang K.-D. 
Published: October 2015

During the last years, jetting processes for higher viscosity materials have gained widespread interest in microelectronics manufacturing. Main reasons for this interest are high throughput/productivity of jetting, contactless material deposition, high volume precision and freely designable deposition patterns.
In previous studies we have demonstrated the jetability of different resin-based materials, being exemplary for unfilled adhesive, for low viscous Underfill resin and for higher viscosity Glob Top materials. The focus of our previous work was on the dosing of Underfill material, where this study is dealing with more complex materials – Glob Top resins. These materials are non-Newtonian fluids - the flow curves of the filled materials can be described by models of Cross or Herschel/Bulkey. Furthermore, highly filled and paste-like mixtures show a significant time dependency of formation of structural equilibrium after deformation, so process development needs to take this into account, so detailed material analysis is described within this study.
To illustrate the potential of jetting as a flexible and powerful tool for Chip on Board encapsulation, both, simple test-structures (dots, lines, dams) but also more complex demonstrators have been assembled using wire bonded ICs on ceramic substrates and encapsulants showing viscosities ranging from 10 Pas to &gt; 100 Pas. Not only basic process data on droplet diameter, resulting material depot size and positioning accuracy have been evaluated, but also statistical means have been employed to determine process homogeneity and stability depending on the respective parameter set. Additionally, the whole process was followed by a high-speed camera system, providing detailed information on actual jetting behaviour during droplet release, flight and impact.
Summarized this paper gives a detailed insight into jet process development for high viscosity Glob Top materials and describes process design rules and limitations and thus allows the optimized use of advanced jetting technology for Chip on Board assemblies.
Glass-Insulated Bonding Wire Scales to Support advances in Miniaturization
Authors: Stephan Dominik 
Published: October 2015

The semiconductor industry is facing a major challenge today – it must adapt to the constant need to miniaturize, and in order to accommodate this major trend the entire ecosystem must adapt and evolve. While the current standard materials and tools make it possible to scale down to a certain level, it is simply not enough.
Although there are efforts to make smaller wires, wire makers, wire drawing equipment and tool makers are working toward a boundary of existing methods. When wire diameter is successfully reduced, more issues correlated with wire uniformity and production control of the low required tension during the drawing process appear, these may result in low yield and higher cost. Another limiting point is the drawing die which experiences yield issue and high erosion at the very small diameter.
It is clear that there is a need for smaller wire diameter to support advances in miniaturization. There are, however, intrinsic challenges of physics that may limit the ability to manufacture and use such wire, most of which are related to the mechanical strength, and concerns about wire stability and shorting.
This presentation will explore the question of bonding wire scalability, and will discuss a possible solution. Data will be provided to show how glass coated wire may effectively address issues related to the mechanical strength and stability of wire and enable relaxed chip design rules while providing a smaller effective wire diameter on smaller bonds.
Planar Power Inductor with Magnetic Film for Embedded LSI Package
Authors: Fujii Tomoharu , Kobayashi Kazutaka , Shimizu Hiroshi , Nakazawa Shinji , Sato Toshiro , Sato Fumihiro , Kobayashi Hiroki 
Published: October 2015

A power inductor component is relatively very thick and large shape. Therefore, these components are not appropriate feature to be embedded into a LSI package and mounted nearby a LSI chip, it is challengeable to make the embedded application. However, LSI power delivery system is going for low voltage and large current, and losses between power supply and loads impacts on the power supply efficiency characteristic. In order to solve this problem, miniaturization for a power inductor is needed to realize the embedded applications.
As one of approaches to realize the power delivery systems, the planar power inductor with Zn-Ferrite film has been studied for the next generations. A structure of planar power inductor was designed to be configured 2-turn inner copper spiral coil covered with top and bottom magnetic core. The Zn-Ferrite film used as a magnetic core has a high resonance frequency around 300MHz and high saturation magnetization of 0.6T or more, and this film can be formed in low temperature, which can be handled in parallel way to fabricate an organic package.
We have developed the organic package with employing the power inductors covered with Zn-Ferrite as prototype of the embedded application, and evaluated the electrical and magnetic characterizations.
The thickness of embedded planar power inductor covered with Zn-ferrite film is 50um, and the size is 850um squares. Q factor is 10 to 13 in 30MHz to 100MHz. The degradation of inductance caused by the superimposed current does not happen without changing until 3A.
Investigation of electrical performance and mechanical reliability of device embedded power module
Authors: Tanaka Masaya , Sawada Keisuke , Serizawa Toru , Sagara Shuji 
Published: October 2015

We investigate electrical properties and reliabilities of DC-DC converter module with the use of embedding technology. We designed and manufactured two kinds of DC-DC converter module as a means of verification for these characteristics. One is the surface mounted module with side-by-side structure for reference and another is the device embedded module.
To evaluate time-domain simulation analysis accurately, we conducted accurate built circuit model of the DC-DC converter IC and extracted multi-port S-parameters models including multi-coupled wiring models primarily. As a result of time domain voltage waveform simulation using these accurate built circuit model and multi-port S-parameters, we verified that the device embedded power module is excellent in electrical characteristics of switching operation. We demonstrated in this study that miniaturization of approximately 25% for the module size and voltage noise improvement of approximately 50% compared with the surface mounted power module when applying device embedding technology. Furthermore we validated these electrical performances of the device embedded power module by using experimental measurement method. We evaluated mechanical and electrical reliabilities of the device embedded power module collaterally, in consequence mechanical and electrical reliabilities of the device embedded module holds the sufficient performances
Obsolescence Management & the Impact on Reliability
Authors: Tulkoff Cheryl , Caswell Greg 
Published: October 2015

Component obsolescence management is a strategic practice that also mitigates the risk of counterfeit parts. Left unchecked, obsolescence issues increase support, development and production costs. So, planning ahead is critical. For companies that do proactively manage component availability and obsolescence, the effect of long-term storage on manufacturability and reliability is the area of major concern. Many issues can arise depending on the component technology and storage environment. Reliability concerns to consider include solderability, stress driven diffusive voiding, moisture, Kirkendall voiding, intermetallics/oxidation and tin whiskering.
When component obsolescence isn't planned for, the secondary market is often the supply chain of last recourse. While it is possible to get high quality, genuine parts, it is also possible to get nonconforming, reworked, or counterfeit components. And, it is increasingly difficult to differentiate genuine parts from their counterfeit equivalents. Historically, the secondary market provided a mechanism for finding parts in short supply or at reduced cost. Today, high-reliability system manufacturers are less willing to risk contamination of their supply chain with potentially substandard parts in order to save a few dollars on the cost of a part.
This paper will cover obsolescence management strategies, relevant industry standards, use of managed supply programs (MSP) and contract pooled options, plus long term storage recommendations and practices.
Electrolytic Deposition of Fine Pitch Sn/Cu Solder Bumps for Flip Chip Packaging
Authors: Kenny Stephen , Matejat Kai , Lamprecht Sven , Mann Olivier 
Published: October 2015

Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate alloy solder paste. The continuing trend towards increased miniaturization and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 150μm for these applications.
This paper describes latest developments in the electrolytic deposition of solder to replace the stencil printing process; results from production of 90μm bump pitch solder arrays with tin/copper alloy are given. The solder bump is produced with a specially developed electrolytic tin process which fills a photo resist defined structure on the SRO. The photoresist dimensions determine the volume of solder produced and the subsequent bump height after reflow.
Investigations on the bump reliability after reflow are shown including copper alloy concentration at 0.7% and x-ray investigation to confirm uniform metal deposition. The self centering mechanism found in the bump production process during reflow is presented and the capability to correct photoresist registration issues.
The solder bumps are shown as deposited onto an electroless nickel/gold or electroless nickel/palladium/gold final finish which serves also as a barrier layer to copper diffusion into the solder bump.
Discussion of further development work in the production of alloys of tin/copper together with silver are given with first test results.
Cost effective 3D Glass Microfabrication for Advanced Packaging Applications
Authors: Flemming Jeb H. , Dunn Kevin , Gouker James , Schmidt Carrie , Cook Roger 
Published: October 2015

Interposer technologies are gathering more importance in IC packaging as the industry continues miniaturization trends in microfabrication nodes and IC packaging to meet design and utility needs in consumer electronics. Furthermore, IC packaging is widely seen as a method to prolong Moore's law. Historically, silicon has been the material of interest for interposer materials given its prevalence in IC production, but it presents many technical and costs hurdles. In contrast, glass interposer technology presents a low cost alternative, yet attempts at producing advanced through glass vias (TGVs) arrays using traditional methods, such as laser ablation, have inherent process flaws, such as reduced interposer mechanical strength and debris sputtering among others.
In this extended abstract we present 3D Glass Solutions' efforts in using our proprietary APEX™ Glass ceramic to create various interposer technologies. This extended abstract will present on the production of large arrays of 10 micron diameter TGVs, with 20 micron center-to-center pitch, in 100 micron thick APEX™ Glass ceramic and the comparisons of wet etching of APEX™ Glass vs. laser ablation.
Mechanical Stress Analysis and Evaluation of Hybrid Land Grid Array Attached Large Form Factor Organic Modules
Authors: Torok John , Canfield Shawn , Yu Yuet-Ying , Zheng Jiantao 
Published: October 2015

Recent industry trends to continue enabling increased server system performance and packaging density has driven the need to implement larger form factor hybrid land grid array (LGA) attached organic modules. In addition, given the need to package multiple modules on a single printed circuit board (PCB) assembly, PCB cross-sections and their corresponding physical properties (e.g., flatness, etc.) as well as module bottom surface metallurgy (BSM) co-planarity require a more detailed understanding of impacts to the compliant as well as the soldered connector interfaces. Lastly, the migration to lead (Pb)-free solders has further complicated the issue given both the change in material properties as well as processing temperatures.
In this paper we will discuss the mechanical stress analysis and evaluation tests assessment of a recently developed 50 mm square organic processor module, hybrid LGA attached to a multiple site PCB. The analysis presented will highlight the methodology to identify both connector soldered stress and predicted contact load variation across the module's mated interface. Key parameters discuss will include the PCB flatness, Organic substrate BSM co-planarity (both predicted and measured) and the Hybrid LGA as-soldered contact co-planarity. Corroborating predicted analytical results, we will discuss various evaluation tests performed to validate the design's integrity. Key tests include, pressure sensitive film (PSF) studies and environment stress exposures, including thermal shock, mechanical shock and vibration and seismic exposure. Post test electrical integrity and test sample construction analysis, including 3D x-ray and mechanical cross-section, will also be described.
The analysis process and testing described will provide a method to evaluate more challenging hybrid LGA applications as both module sizes and/or number applied per PCB assembly increase and Pb-free assembly is introduced in future applications.
Study of Warpage and Mechanical Stress of 2.5D Package Interposers during Chip and Interposer Mount Process
Authors: Hisada Takashi , Yamada Yasuharu , Asai Junko , Aoki Toyohiro 
Published: October 2015

As data transmission rate increases, flip chip plastic ball grid array (FCPBGA) utilizing a interposer for multiple chips is gaining popularity because of high electrical performance, ease of chip design, ease of thermal management with thermal lid, etc.
The authors assessed package design configuration and key design elements for two chips application assuming 1600 signal I/Os for logic and 800 signal I/Os for memory. Then, we studied warpage behavior of the interposer, and mechanical stress of solder interconnections and low-k dielectric layer under controlled collapse chip connection (C4) pad. We set three different mount process assumptions for chip to interposer and interposer to base organic substrate. The mount process assumptions are (1) two pass reflow of chip to interposer first, then interposer to base organic substrate, (2) reversed sequence of two pass reflow which is interposer to base organic substrate first, then chip to interposer, (3) one pass reflow of chip, interposer and base organic substrate all together. We also set three different interposer material assumptions of Si, glass and organic in this study.
We analyzed warpage behavior and mechanical stress using finite element method (FEM) modeling technique with a set of combinations of coefficient of thermal expansion (CTE) and elastic modulus of the interposers. The study also includes an analysis for conventional multi-chip-module (MCM) FCPBGA as a reference. We show the analysis results of interposer warpage, first principal stress at low-k dielectric layer under C4 pad and von Mises stress at solder interconnections of chip joining and interposer joining.
Alternative technology concepts for low-cost and high-speed 2D and 3D interconnect manufacturing
Authors: Roozeboom F. , Smets M. , Kniknie B. , Hoppenbrouwers M. , Dingemans G. , Keuning W. , Kessels W.M.M. , Pohl R. , Huis in't Veld A.J. 
Published: October 2015

The current industrial process of choice for Deep Reactive Ion Etching (DRIE) of 3D features, e.g. Through-Silicon Vias (TSVs), Microelectromechanical Systems (MEMS), etc., is the Bosch process, which uses alternative SF6 etch cycles and C4F8-based sidewall passivation cycles in a time-sequenced mode. An alternative, potentially faster and more accurate process is to have wafers pass under spatially-divided reaction zones, which are individually separated by so-called N2-gas bearings ‘curtains’ of heights down to 10–20 μm. In addition, the feature sidewalls can be protected by replacing the C4F8-based sidewall passivation cycles by cycles forming chemisorbed and highly uniform passivation layers of Al2O3 or SiO2 deposited by Atomic Layer Deposition (ALD), also in a spatially-divided mode. ALD is performed either in thermal mode, or plasma-assisted mode in order to achieve near room-temperature processing.
For metal filling of 3D-etched TSVs, or for deposition of 2D metal conductor lines one can use Laser-Induced Forward Transfer (LIFT) of metals. LIFT is a maskless, ‘solvent’-free deposition method, utilizing different types of pulsed lasers to deposit thin material (e.g. Cu, Au, Al, Cr) layers with μm-range resolution from a transparent carrier (ribbon) onto a close-by acceptor substrate. It is a dry, single-step, room temperature process in air, suitable for different types of interconnect fabrication, e.g. TSV filling and redistribution layers (RDL), without the use of wet chemistry.
Monitoring of Wet Etch for Wafer Thinning and Via Reveal Process
Authors: Bai Chuannan , Shalyt Eugene , Liang Guang , Bratin Peter 
Published: October 2015

TSV (Through Silicon Vias) are usually formed and deposited as blind vias. As a last stage, vias are opened by thinning of the back side of the wafer. While the bulk of the silicon can be removed by both wet and dry methods, the final step of the “Via Reveal” process is predominantly performed by wet etch.
Two commonly used types of etching solutions are anisotropic alkaline etch (KOH, TMAH, etc.) and isotropic etch (HF/HNO3, etc.). Etch rate, uniformity, and product characteristics strongly depend on the composition of solution: both original compounds and reaction products.
This presentation describes different approaches for process control of both alkaline and acidic etch solutions using advanced spectroscopic models and potentiometry. Pros and cons of different approaches are discussed. Specific emphasis is placed on the monitoring of reaction products.
Better, Faster and Cheaper Precision Cleaning: Advanced CO2 Cleaning Technology
Authors: Jackson David 
Published: October 2015

Precision cleaning of microelectronic substrates is a requirement prior to critical fabrication steps such as wire bonding and adhesive bonding, and following processes such as laser machining and soldering. With respect to adhesive bonding, difficult-to-bond materials such as thermoplastics, metals, glasses, ceramics and composites of same present special challenges. Important surface preparation steps include surface cleaning, microscopic etching, and functionalization. This is especially true for materials which exhibit low surface energy or heterogeneous surface contamination and chemistry. Surface treatment challenges are amplified when bonding adherent surfaces with dissimilar cohesive energy densities, for example metal-to-polymer and metal-to-ceramic. Post-laser processing of organic substrates leaves carbon char and particles on or near the laser kerf and surrounding area. These residues must be removed prior to the follow-on fabrication steps such as plating, adhesive bonding, wire bonding, and precision assembly operations.
In this regard, conventional precision cleaning processes typically require multiple steps, chemistries, and equipment to accomplish the decontamination and surface modification if required. Moreover, conventional cleaning methods are sometimes non-selective for both contaminant and contaminated surface. For example, conventional vacuum plasma using Ar/O2 is typically used to remove post-laser char on organic films such as Kapton flexible circuits. Vacuum plasma is usually performed off-line, taking up to 30 minutes to complete, and is generally non-selective for the organic contamination. The entire organic substrate is etched away during the cleaning process to remove laser char. In another example, surfaces are prepared for adhesive bonding using multiple steps involving vacuum plasma, organic solvents, chemical etchants or primers.
Advanced carbon dioxide (CO2) cleaning technology uniquely and consistently achieves precision clean (and functional surfaces if needed), including 2D and 3D surface geometries, for a variety of critical cleaning applications using one process chemistry – CO2. Numerous possible hybrid combinations of CO2 are possible including centrifugal CO2 immersion, supercritical CO2 extraction, CO2 composite spray, and atmospheric CO2 plasma cleaning and treatment. Besides addressing a broad spectrum of surface treatment requirements, CO2 cleaning technology can adapt to existing or new manufacturing tools or processes to improve production flow, increase equipment utilization, and decrease floor space. Measurable benefits derived from utilizing this technology include more productive processes with reduced labor and material inputs, improved worker safety and environmental quality, and cleaner parts – faster and with a lower cost-per-clean.