bluuebunny/crossref_metadata_2025_split huggingface dataset:
A PCB Technology Moisture Content and Electrical Conductivity Sensor Probe for Agricultural and Horticultural Applications
Authors: Dean Robert N. , Guertal Elizabeth , Newby Adam , Fain Glenn 
Published: October 2015

Commercial printed circuit board (PCB) technology affords the realization of low-cost sensor probes for agricultural and horticultural applications. Plant growth can be optimized when the soil (in field crop applications) or the substrate (in greenhouse crop applications) properties can be measured and properly adjusted. Two important parameters are moisture content and electrical conductivity. Measuring moisture content allows the grower to better time irrigation for most efficient crop growth. Accurate moisture content measurement also allows the grower to apply sufficient irrigation volume for optimum plant growth while avoiding excessive irrigation volume. Likewise, measuring the electrical conductivity reveals useful information regarding ions in the soil or substrate, which can be used to optimize the application of plant nutrients or manage soil salinity.
Commercial soil probes are expensive, which limits their widespread use in commercial applications. PCB probes, on the other hand, can be very inexpensive and can quickly be redesigned to modify the form factor for different applications. These sensors make use of the materials and processes inherent in commercial PCB manufacturing, including the FR4 substrate, patterned Cu cladding and soldermask. The non-conductive E-glass FR4 substrate is used as the rigid backbone of the sensor probe. The patterned Cu cladding is used for electrodes and signal traces. The polymeric soldermask is used as a thin insulating and moisture barrier layer. With these materials, insulated fringing field sensors can be realized on the surface of the PCB to measure moisture content, while exposed metal pads on the surface can be used to measure electrical conductivity. Additionally, the PCB probe is directly compatible with the integration of any desired integrated electronic components. Furthermore, the turnaround time for a new PCB sensor design can be as little as 24 hours at modest cost, making this technology economically superior to traditional sensor technologies, such as silicon based MEMS, where it can take months to realize a new design and be very expensive.
A prototype sensor probe has been designed, fabricated and evaluated. Test data is analyzed, compared with test data from traditional sensor probes and presented.
2D PCB WITH 3D PRINT FABRICATIONS FOR RIGID-CONFORMAL PACKAGING OF MICROSENSOR IMAGING ARRAYS BASED ON BIOINSPIRED ARCHITECTURES
Authors: Fries David , Barton Chase StarrGeran 
Published: October 2015

Macro sensor systems typically measure a localized space above a single sensor element. Expanding these single sensor elements into arrays permits spatial distribution measurements of a particular parameter and allow flux visualizations. Furthermore, applying microsystems technology to macro sensor systems yields imaging arrays and high resolution spatial/temporal sensing functions. Extending the high spatial resolution imaging over large areas is a desirable feature for new “vision” modes on autonomous robotic systems and for deployable environmental sensors.
Rigid-flexible PCB's are desirable for miniaturization and integration of systems for mobile technology. The hybrid substrates provide substantial flexibility in systems design and integration of multiple functions into limited spaces. Using this design and construction approach allows lightweight, complex, and space efficient systems. Flex microsystems based on structured, fiber or non-fiber filled PCB laminates permits packaging to occur at two levels, at the local (micro) substrate scale and at the macro scale with the ability to flex the system across millimeter to centimeter lengths on real everyday systems.
We continue to explore the use of PCB and PCBMEMS technology for new sensing concepts. In order to create rigid-conformal, large area imaging “camera” systems we have merged flexible PCB substrates with rigid constructions from 3D printing. This approach merges the 2D flexible electronics world of printed circuits with the 3D printed packaging world.
Furthermore employing architectures used by biology as a basis for our imaging systems we explored naturally and biologically inspired designs, and their relationships to non-visible imagery, and alternate mechanical systems of perception. Radiolaria are extremely tiny ocean organisms that utilize a similar additive construction process to 3D printing. Their cell bodies secrete a substance mainly composed of silica to form intricate exoskeletons used as a system of protection. A correlation can be made between the radiolaria's construction process and the plastic extrusion system of the 3D fused deposition model printer.
The benefits of additive construction are efficient use of materials, reduced cost and energy, and ability to customize forms. Through the use of bio-inspiration, a framework is laid out to base further research on (DFP)-design for packaging. Radiolarian exoskeletons take on a grid-like pattern while creating a cage around each microsensor interior and producing strong scaffolding. Using the 3D printed exoskeleton's form and function with flexible printed circuits one can create systems that are both rigid and form fitting with three-dimensional shape and enable new camera systems for various sensory applications.
New Lithography Requirements driven by 2.5D Interposer Manufacturing
Authors: Ruhmer Klaus , Battaglia Joe , Cochet Philippe 
Published: October 2015

In recent years, 2.5D packaging has quickly turned from a buzz-word into an Advanced Packaging reality. Not dissimilar to the Multi-Chip-Modules (MCM's) of the past, 2.5D packages utilizing high density interposers with favorable electrical characteristics can be a cost efficient and high performance alternative to significantly more complex 3D or SOC integration schemes.
Dictated by the trend towards ever thinner, smaller and higher integrated and more capable devices, high density interposer technology is required to enable 2.5D packages. Patterning of these kind of substrates, regardless if manufactured on Silicon, Glass or other suitable materials requires relatively advanced lithography systems. Simple contact or proximity exposure is no longer up to the task.
This paper specifically lists the various patterning / lithography challenges which are being encountered when manufacturing high density 2.5D interposers. Typical back-end litho requirements regarding minimum resolution, overlay, maximum sidewall angle capability in relatively thick resist and depth of focus are being established and discussed. In addition, the application specific litho challenges such as a large exposure field size and IR backside alignment capability for TSV (Through-Silicon-Via) or TSG (Through-Glass-Via) definition are being reviewed and characterized.
As with all back-end processes, interposer manufacturing must be extremely cost efficient and high yielding. A middle ground between costly front-end processes and more robust, faster and lower cost back-end processes has to be found. This paper also discusses potential cost reduction via economy of scale. A detailed cost model for glass interposer manufacturing on large panels is being offered.
Optimization of Lead Free Plating for Flip Chip Applications
Authors: Arvin Charles L. , Stahl Jurg , Sauter Wolfgang , cox Harry , Perfecto Eric , Oberson Valerie , Normand Nathalie 
Published: October 2015

Traditional flip chip processes have consolidated to a SnAgCu (SAC) solder system. Each company based upon their own needs and application space has come to their own method to achieve the desired final composition of the interconnect. These have included different solder compositions for both the pre-solder and the C4. The various interconnect solutions can range from no solder on one side such as pure Cu or Ni to an interconnect that has identical solder composition for both the substrate and the C4.
Decisions for the optimized solution include the need for reliability, cost and yield. Picking the right solution also enables the elimination of defects such as solder voids, interfacial voids, white bumps, micro-solder bumps and non-wets. The optimized solutions are dependent upon many factors that include the fragility of the silicon dielectric, the size of the die, type of flux used at assembly, the assembly process used, method by which SnAg is plated such as various layering techniques, final processes steps in C4, test probe concepts, DSP methods and many more. In order to pick the appropriate scheme for each product and for each industry, it is imperative to know the interaction of all of these factors.
This paper provides concepts and data about how to optimize assembly and lead free plating for a particular process. In the plating process, this includes the importance of various layering steps and analysis of incoming chemicals, especially the acids, and in the assembly process, the knowledge and matching of solder hierarchy, warpage, flux characteristics and preparation / cleaning steps prior to underfill. In particular, we will provide the data and the scheme by which it is possible to produce void free solder processes without bleed and feed on SnAg baths that are over 100 amp-hr per liter and over 1 year old.
A Decade of High Accuracy Die Attach Equipment and Process Developments (Addressing Photonics Device Packaging Challenges)
Authors: Weinhaendler Johann , Kaiser Rudolf , Kellermann Hardy 
Published: October 2015

Fueled by the Internet and nowadays unlimited connectivity expectations, the assembly of optoelectronic packages became a key element to enable the explosive growth in the communication field around the entire globe.
The primary challenge in the field of advanced optoelectronics and photonic device packaging (e.g. laser diodes, VCSEL's, optical benches, lenses etc.) is to accurately align the different optical components in reference to each other for optimal optical device performance. This growing need for high precision die attach (&lt;= 0.5um @ 3 sigma) systems and solutions at the shortest possible cycle times has been studied and implemented by AMICRA Microtechnologies. AMICRA's state of the art high accuracy automated assembly system solutions have been successfully used for over a decade in both a laboratory setup and a high volume manufacturing environment.
From handling a large variety of substrate materials, thin and fragile chips with odd aspect ratios, lenses and other components, the flexible and dynamic vision alignment concept and the bonding process controls required to achieve high overall component placement accuracies has been AMCIRA's industry focus since the company's inception. While significant progress has been made to provide solutions for all communications and photonics applications there are currently still some challenges out there to be overcome, challenges that can also change on an application by application basis. Besides the technical challenges the cost effectiveness or cost per bond for those applications is a very critical overall success factor as well.
This paper will elaborate on manufacturability concerns and equipment automation challenges associated with the key parameters of a Photonics applications high accuracy die attach process which, amongst others, not only require highly sophisticated vision alignment algorithms but also thermal transfer processes either using an eutectic process or a laser soldering technique.
Given the ever shrinking packaging form factors, all of AMICRA's research and developments in the Photonics field have also been successfully introduced and applied in more traditional semiconductor applications which have an increasing need for high accuracy die attach.
A New Method for Testing Electrolytic Capacitors to Compare Life Expectancy
Authors: Gulbrandsen Stephani , Arnold Joelle , Kirsch Nick , Caswell Greg 
Published: October 2015

Power system applications, such as street lighting, typically have a 10 year warranty. When these systems include electrolytic capacitors, it is important to choose a supplier that meets these requirements. Traditional lifetime testing of electrolytic capacitors to ascertain their life expectancy requires specialized equipment, is time consuming, labor intensive, and for most OEMs, is ultimately cost prohibitive.
Electrolytic capacitors with the same capacitance and voltage ratings from different suppliers may be rated to the same lifetime, but historical data confirms that they can have significantly different operational expected lives. An accelerated testing methodology is needed to compare the reliability of electrolytic capacitors from different suppliers.
DfR has developed an approach that reduces test times from thousands of hours to several weeks by taking advantage of two key behaviors of electrolytics. The first involves the rate at which capacitors lose electrolyte, which is fairly predictable at a given temperature and electrical stress. The second key behavior is the dependence of the equivalent series resistance (ESR) of electrolytic capacitors on the volume of liquid electrolyte.
The approach that will be described in this paper will demonstrate a means of comparing the time to failure for comparable capacitors from different suppliers under the same conditions. Case studies will demonstrate how this method avoids the extended testing that is typically required.
SiPs in the medical domain and in the defense and industrial domain produced with WDoDTM technology
Authors: COUDERC Pascal , NOIRAY Jérôme 
Published: October 2015

Based on Wire free Die on Die disruptive technology (WDoDTM), complex SiPs can be manufactured in a small factor package size. Stacking known good rebuilt wafers allows high yields while integrating high performance devices (1).
Wafer processing is done with e-WLB technology and a specific redistribution layer (RDL) is designed to match with 3D PLUS bus metal edge interconnect technology. 300 mm rebuilt wafers are processed and thinned down to 200 μm before stacking and polymer bonding. Bonding alignment is within ±5 μm allowing small lateral pitches demonstrating WDoDTM versatility with denser IO products such as FPGA. Besides, this new process integration scheme allows the stacking of both conventional boards with SMDs not available at wafer level together with rebuilt wafers made of known good dies.
WDoDTM technology has been successfully used with different kind of products in the defense and medical markets.
A calculator node including a 484 I/O FPGA with 2 mDDR and an EEPROM in addition to more than 150 decoupling capacitors was manufactured and is exhibiting better electrical performance when compared to the 2 dimensions version.
Moreover, a medical implant has been successfully developed embedding 2 ASICS and several PICS capacitors allowing an 8 times shrink of the electronics compared to advance lead based pacemakers..
With this new technology, 3D PLUS is highlighting the way to highly integrated System in Package (SiP) and demonstrates its know-how in the three dimensional integration.
An In Situ Atmospheric Probe for Real Time Weather Monitoring
Authors: Adams Mark L. , Shapland Audrey Rose , Gutierrez Matthew , Owen Evan 
Published: October 2015

Weather affects many aspects of our daily lives from our individual commutes to the global economy. Although much progress has been made in understanding atmospheric physics and weather forecasting, there is still a need for better in situ atmospheric data. Forecasts are based on high performance computer models which solve the differential equations that represent the dynamics of the atmosphere. In all of these models, initial conditions based on the current state of the atmosphere are ingested into the models. The initial conditions are based on data from many sources including remote sensing satellites, ground based weather stations, weather balloons and even aircraft. However, the amount of in situ atmospheric data is very limited and so often times the initial conditions for the models are not truly representative of the current atmosphere. This is especially true for severe storms such as super cell thunderstorms, tornadoes, and hurricanes. Severe weather impacts millions of people every year costing both human life and substantial resources. A better understanding of severe weather will have a significant impact on human safety and infrastructure protection.
Electronics miniaturization and advances in manufacturing such as 3D printing have allowed for the development of low-cost, light-weight probes capable of providing real-time in situ information about the atmosphere which can improve forecasts models and provide a better understanding to atmospheric scientists. The probes provide temperature, relative humidity, pressure, position and velocity data. MEMS sensors are used to monitor the ambient weather conditions and an on-board GPS provides position information. The sensors are combined with a microcontroller and radio to transmit data back to a receiver on the ground. Power is provided by zinc-air batteries and antennas for both the GPS and data radio are integrated into the package. In order to ensure correct operation of the electronics, 3D printing is used to generate a custom electronics/mechanical package that is both functional and robust while maintaining low weight and high drag coefficient. The desire is for the probes to stay airborne as long as possible without any active means of propulsion or buoyancy.
The probes are designed to be small, light-weight and low-cost. They can be deployed from aircraft, weather balloons or launched directly into a storm. Although most probes can be recovered, our design is focused on minimizing the environmental impacts of any probes that are not recovered.
A Cost and Yield Analysis of Wafer-to-wafer Bonding
Authors: Palesko Amy , Palesko Chet 
Published: October 2015

When a product requires the bonding of two die or wafers, there are a number of methods that may be used. Not only does the type of bonding process itself have to be selected, but it must also be determined whether the items being bonded will be in wafer or die form. This paper will focus on wafer-to-wafer bonding, which has the highest throughput compared to die-to-wafer and die-to-die bonding; it also has the potential to be the lowest cost option if proper yields are achieved.
This paper will introduce the background and general pros and cons of wafer-to-wafer, die-to-wafer, and die-to-die bonding. Activity based cost modeling will be used to construct a generic flow of a wafer-to-wafer bonding process. The process flow will be divided into a series of activities, and the total cost of each activity will be identified. The cost of each activity will be determined by analyzing the following attributes: time required, amount of labor required, cost of material required (consumable and permanent), tooling cost, depreciation cost of the equipment, and yield loss associated with the activity.
The model will be used to explore multiple variables that affect the total cost of the wafer-to-wafer bonding process, including: incoming wafer cost, incoming wafer defect density, time required for the dicing process, time required for the bonding process, cost of the equipment for the bonding process, and the yield of the bonding process. First, a sensitivity analysis will be conducted to determine the impact each variable has on the total cost. Then scenarios will be created to conduct trade-offs between multiple variables.
Only one, generic wafer-to-wafer bonding model will be created, but there will be enough variables to accurately reflect different bonding methods in use by the industry today. Methods for bonding two wafers together will also be discussed in the paper, as well as the cost and yield issues associated with each. An example of these methods are thermo compression bonding and direct bonding.
The goal of this analysis will be to understand the cost and yield drivers associated with wafer-to-wafer bonding, and to determine scenarios in which wafer-to-wafer bonding is a suitable, cost effective technology selection.
Thin Wafer Handling Using Mechanical- or Laser-Debondable Temporary Adhesives
Authors: Fleming David , Kim Jong-Uk , Okada Janet , Wang Kevin , Gallagher Michael , Barr Bob , Calvert Jeff , Zoschke Kai , Wegner Matthias , Töpper Michael , Rapps Thomas , Griesbach Tim , Lutter Stefan 
Published: October 2015

The development of adhesives that enable handling, processing, and assembly of thin wafers and die is a key technical challenge for the realization of 3D devices. We will present on temporary adhesive technology for processing of thinned wafers that is amenable to either mechanical or laser-assisted debonding that can occur at room temperature.
Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, thermal stability to 300 °C or higher, and clean room-temperature release directly from the device wafer using either mechanical or laser-assisted debonding
We will present successful temporary wafer bonding using a BCB (benzocyclobutene)-based material that can meet these requirements. The mode of adhesive release from a device wafer will be discussed in detail as it relates to wafer thinning and handling, and material physical properties and resistances will be expressed. Formulation requirements needed for successful debonding will be presented, with an emphasis on a laser-debonding scheme that utilizes either a 248nm or 308nm laser source capable of ablating a laser sensitive layer residing between a glass carrier and the temporary wafer bonding material. Successful room temperature tape-peeling of the adhesive film after ablation and carrier removal will be discussed.
Flexible Hand-Free Microelectronics assembly Line for the Chip and Wire industry
Authors: Bhartia Prakash , Angeloni Jim , Bolinger Will 
Published: October 2015

This paper presents Natel's effort in pioneering the design and development of the first Touch-Free Microelectronics assembly Line for the Chip and Wire industry. When the Surface Mount Technology (SMT) industry first started, it began as a series of discrete pieces of equipment that performed the functions required to populate Circuit Cards. Over the years, the technology has evolved as has the industry such that fully integrated, automated lines are available where the circuit cards are installed at one end of the line, reels or tubes of components, such as packaged resistors, inductors, capacitors and semiconductors etc., loaded, the machine programmed and assembled circuit cards are available at the other end. However, no such line has been developed for the Chip and Wire industry, with most assembly houses still using individual stand alone die attach, bonders, plasma clean machines to populate substrates.
Natel has developed the first of its kind integrated Auto line for the Chip and Wire industry, which conceptually replicates a SMT line. This Auto Line is touch–free and incorporates die attach ( including eutectic), ball and ribbon bonding , plasma clean and in line testing. The line is ideal for high volume production of Hybrid and Microwave Integrated Circuits. The obvious advantages of this approach are the “ hands-free” continuous flow aspect with significant reduction in product defects, increase in efficiency and cost reduction thereby increasing competitiveness against low labor rate overseas operations.
This paper will provide details of the line, and discuss what additional capabilities can be added and hopefully promote the future development of the Chip and Wire industry built on this pioneering development.