bluuebunny/crossref_metadata_2025_split huggingface dataset:
A Novel Approach to 3D Chip Stacking
Authors: Vandermeulen Mark , Smith Andrew , Csermak Ron 
Published: October 2015

Designers seeking electronic package miniaturization but lacking the resources to utilize custom ASIC or complex 3D integration approaches can now take advantage of chip stacking technology for integrating a range of devices into small, system-in-package (SiP) structures.
A robust, innovative approach, suitable for supporting low- to medium-volume applications, has been developed which avoids the cost and/or size penalties typically encountered using traditional multi-chip packaging techniques. Using bare die and vertical interconnect/interposer structures, this stacking technology permits the design of multi-chip assemblies with either identical or dissimilar die, co-packaged with discrete and/or integrated passive devices. The approach is independent of ASIC foundry process and does not require through-silicon via (TSV) technology, and is therefore well-suited for designs incorporating multiple IC's from different semiconductor processes or manufacturing sources. Relative to system-on-chip (SoC) ASIC implementations, which carry large upfront NRE costs and long development cycles, 3D co-packaging of heterogeneous devices in customized SiP packages offers a proven, cost-effective alternative with greater design flexibility and reduced time to market.
This presentation will describe this novel 3D packaging approach, and how it can be used in conjunction with discrete and integrated passive components to address package designs where size, weight, and/or performance are at a premium.
Packaging Related Failure Modes of Microelectronic Components
Authors: Hertl Michael 
Published: October 2015

Today's electronics development is governed by two trends: miniaturization of size and increase of power, which both contribute to significantly higher operation temperatures of the components and assemblies. Additionally, with the establishment of the RoHS standards, also the assembly process takes place at temperatures which are significantly higher than some few years ago. Therefore the package needs to protect the component against higher and higher temperatures during the entire component live time, from assembly through the entire operation cycle.
The packaging design engineer disposes of a large number of parameters to optimize each packaging for its individual application. Even in the “simple” case of just a small silicon die in a small package, the specific composition of the mould compound may make the difference between an “easy-to-solder” package and one with repetitive failure issues during soldering and/or product operation. It is immediately clear that the situation is even much more complicated in case of highly evolved MEMS components. Modern type cavity based sensor packages need to be designed for minimum component warpage during the entire product live time, a task which is particularly challenging for the 260 °C top temperature the component may face during assembly.
In the present paper we will apply our TDM (Topography and Deformation Measurement) system to monitor the warpage behavior of various components during temperature cycles which are either typical for the solder process, or for the components operation conditions. Simultaneously with heating or cooling the components, high resolution ( μm range) topographies will be obtained on the components packaging. These topography and deformation maps will be used to analyze potential packaging related failure modes. An example will be presented how to optimize a MEMS packaging process only by carefully adjusting the assembly conditions, without any variation of the packaging materials or design.
Towards a Parametrically Pumped Xylophone Bar Magnetometer
Authors: Grigg Harry T.D. 
Published: October 2015

Xylophone Bar Magnetometers (“XBMs”) have considerable potential as a class of MEMS sensor, having desirable scale-invariance properties and being suited to fabrication via surface micromachining, as well as achieving high Q factors when carefully designed. Parametric amplification is a control technique which has attracted some attention in the sensor literature, being capable of augmenting resonator Q factors by two or more orders of magnitude. This work presents ongoing research aimed at developing a parametrically amplified XBM in a microscale integrated package.
The operating principles of an XBM and parametric amplification are briefly reviewed, and an analytical model is developed for a prototype device under parametric amplification and electrostatic actuation, based on the method of multiple scales and local nonlinear theory. The predicted behaviour and regions of instability are compared to numerical results obtained via FEA and numerical solution of the nonlinear differential equation. Control of the device is then considered, and the analytical results are used to propose a sense/control scheme.
The Q factor emerges from the analysis as the dominant design factor limiting the sensitivity of the device: on this basis, the prototype design is optimised for maximum Q, treating such sources of dissipation as gas damping, TMD, EMD, and support losses. It is shown that under certain reasonable assumptions, support loss dominates the Q factor. A novel expression for the support loss in an XBM is developed, which is shown to impose a tuning condition on the geometric design of the resonator. A lower-bound estimate for the device Q is thus obtained and compared with simulation and experimental results, leading to an estimated sensitivity on the order of nanoTesla – sufficient for inertial grade application.
Miniature MEMS Interface Circuits Using Nanoparticle Conductors and Embedded Components
Authors: Christensen C. Paul 
Published: October 2015

MEMS devices are typically used in subsystems comprising the MEMS component and the infrastructure required to support it. This infrastructure – signal processing, communication interface, power supply, and system packaging – often determines the size and cost of the subsystem. This paper describes a new approach to fabrication of highly miniaturized electronic circuitry and packaging that is well-suited to interfacing and support of MEMS components.
The fabrication process utilizes nanoparticle silver conductors to connect miniature embedded surface-mount components. Interconnect conductors are produced by filling laser-ablated channels with nanoparticle silver pastes that cure at low temperatures. This laser-based approach allows production of very fine line interconnect structures (&lt; 10 micron trace widths), which simplifies conductor routing and reduces layer count. Avoiding subtractive copper processes significantly reduces capital equipment and facilities costs and minimizes waste streams.
After interconnection, the component assembly is encapsulated in a thermally conductive epoxy to produce a robust, stackable electronic module. Techniques also have been developed for stacking and interconnection of these circuit modules to form 3D electronic systems of nearly arbitrary form factor. All fabrication processes are CAD/CAM controlled, providing fast adaptability to design change and a smooth transition to production in both small and large volumes.
The new fabrication technology has been applied to the challenge of miniaturization of wireless sensor nodes with the goal of constructing complete nodes of sugar-cube size (including an advanced battery). Node form factor can be easily adapted to specific applications.
Effects of Under-Fill Curing on Substrate Warpage
Authors: Hubbard Robert L. 
Published: October 2015

The formulation of flip-chip under-fill adhesives has become more critical to avoid stress-induced cracking at the solder ball interfaces farthest from the center of the die (neutral point) and of the low-k dielectric layers on the die surface. Single die packages, multiple die packages, and thin core-less substrates have now become so warped as to make the ball attach and board attach processes difficult. Recommended under-fill supplier cure profiles are generally accepted without much modification.
This work compares the stress-induced substrate warpage developed in flip-chip assemblies using seven different under-fills from three different suppliers. Both low and high Tg materials from each supplier are included. Standard isothermal convection oven cures and variable frequency microwave (VFM) cures were compared with programmed multi-step cure profiles to determine the optimum conditions for lowest die stress and substrate warpage.
Due to the complex nature of modern under-fill mixtures and the significant differences in the heating mechanisms, the thermo-mechanical properties of the cured resins are not easily interpreted with respect to cause and effect, however some of the results are surprising. The differences in warpage between “full cure” and “cure to Tg” profiles for both heating methods are demonstrated and discussed with respect to potential adhesive network structures from model studies and actual thermal data. Recommendations are made for dispense temperatures, ramp rates, soak temperatures, and extended curing. These effects are important when assemblies face additional heat processing such as subsequent solder reflow.
RF System in Packages (SiP) using Integrated Passive Devices
Authors: Liu Kai , Lee YongTaek , Kim HyunTai , Kim Gwang , Ahn Billy 
Published: October 2015

Passive components are indispensible parts used in System in Packages (SiP) for various functions, such as decoupling, biasing, resonating, filtering, matching, transforming, etc. Making passive components embedded inside laminate substrates is limited on passive density. SMD solutions are by far the most popular approaches in the industry, and may still be dominant for some times. As high integration and high performance have become a trend in the packaging solutions, integrated passive device (IPD) technology shows some unique features, which helps to achieve these goals, especially for RF packages. In the IPD process, low-loss substrate material is used, and therefore high-Q inductors can be built. In addition, thin-film IPD process has finer pitch feature and better tolerance control than other commonly available ones, such as PCB and LTCC technologies, which may yield very repeatable electrical performance, and provide packages of high integration.
Several cases of study will be presented and here are some highlights of them. In case one, a most straightforward SiP approach is presented using QFN package, where several dies (including IPD dies) are implemented side-by-side. This approach may give fast developing cycle times. But importantly, wire-bonding models have big impact on performance from RF packaging, and should be obtained accurately for designs. Another case of study is a stack-die package, where inter-die coupling/cross talk could be a big issue as far as electrical performance is concerned. Placement of some critical parts, such as coils in IPD and in VCO, should be investigated very carefully in design phases. This leads to a concept of ‘IC/IPD/package’ co-design. Finally, a hybrid SiP package solution, where an IPD die is embedded in a mold compound along side with a RF power amplifier die, is presented. This approach (so called ‘eWLB’ packaging), results in the shortest interconnection between dies to dies and dies to balls. With the benefit from both the IPD process and the eWLB process (where low-loss mold materials are used), this approach may lead to high electrical performance and small form-factor at the same time.
2.5D and 3D Packaging Enables Effective Multi-Chip Packaging
Authors: Marcoux Phil 
Published: October 2015

3D and 2.5D packaging has been heralded as a set of the best package architectures to satisfy shrinking time to market windows while offering an effective way to combine the ever increasing set of circuits needed for today's popular products. There is significant confusion as to the design guidelines and the economics involved to create a 3D (stacked) or a 2.5D (stacked on interposer) package. The numbers vary widely depending on the sources and the designs utilized.
This paper will examine the relative cost, design, and performance trade-offs from actual production practice. Comparisons of designs using different via types, various substrate options and BEOL vs. FEOL RDL trace layers. It will show the economics of using 3D and 2.5D for a number of the more common applications in cell phones, tablets and other products.
3D & System-in-Package Development with the Redistributed Chip Package (RCP)
Authors: Gong Zhiwei (Tony) , Hayes Scott , Chhabra Navjot , Duong Trung , Mitchell Doug , Wright Jason , Vincent Michael 
Published: October 2015

Fan-out wafer level packaging (FO-WLP) has become prevalent in past two years as a package option with large number of pin count. As the result of early development, the single die packages with single-sided redistribution has reached the maturity to take off. While the early applications start to pay back the investment on the technology, the developments have shifted to more advanced packaging solutions with System-in-Package (SiP) and 3D applications. The nature of the FO-WLP interconnect along with the material compatibility and process capability of the Redistributed Chip Package (RCP) have enabled Freescale to create novel System-in-Package (SiP) solutions not possible in more traditional packaging technologies or Systems-on-Chip. Simple SiPs using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or a substrate based multi-chip module (MCM). More complex three dimensional (3D) SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMDs, CMOS, GaAs, MEMS, imaging sensors or IPDs gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. The following paper further discusses SiP advantages, applications and examples created with the RCP technology.
Rozalia/Ron ok move from 2.5/3D to Passive 1-4-12.
Thin Film Packaging for Vacuum MEMS Encapsulation: A Study on Outgassing Phenomenon
Authors: Saint-Patrice D. , Pornin J. L. , Savornin B. , Rodriguez G. , Danthon S. , Charvet P. L. , Nicolas P. , Nicolas S. , Fanget S. 
Published: October 2015

Most of the time, MEMS devices require hermetic encapsulation for protection against atmosphere, moisture, particles and standard back-end manufacturing technologies. In the last few years, Wafer Level Packaging (WLP) is moving toward developments on Thin Film Packaging (TFP) in order to save footprint, to reduce chip thickness and packaging costs. In the specific case of high-vacuum MEMS encapsulation (gyro, compass), long term pressure stability is required. As the final performances of these kinds of devices are strongly dependent on the working pressure, using TFP for MEMS encapsulation with controlled vacuum becomes more challenging due to very small cavity volumes. It is then necessary to understand the outgassing phenomenon that take place during TFP encapsulation in order to reduce it.
In this paper, our latest developments on thin film packaging technology are presented. Outgassing from materials used in TFP and MEMS devices become key parameters to decrease the pressure inside the package and to improve the reliability.
In a first part, pressure and Residual Gas Analysis (RGA) of typical TFP and typical MEMS materials are measured under different time / temperature baking processes. Measurements show that material outgassing mainly comes from H2 and maximum pick appears in the beginning of the thermal process. Thanks to these characterizations, an optimized outgassing baking process in term of time and thermal budget is presented. By minimizing the internal outgassing, materials deposited by PVD sputtering can now be implemented as sealing materials for low pressure MEMS devices.
In a second part, specific low temperature Al based materials which has been developed on equipment fully compatible with front-end fab is presented. Multi-layer materials like Ti / Al based materials are compared to our single Al based material to decrease the microstructure size and to improve the sealing performances. Scanning Electronic Microscopy (SEM) and Focused Ion Beam (FIB) cross section characterizations confirm that the grain sizes are highly impacted by sputtering process parameters and a compromise has to be done with MEMS outgassing.
Finally, the most suitable outgassing baking process for the inside cavity materials and various Al-based sealing materials and stacks are performed for a MEMS compass device on 200 mm wafers. Pressure inside the cavity less than 10 mbar is obtained and the TFP yield is presented on each process conditions.
These results are very promising and showed the capabilities of TFP for vacuum MEMS encapsulation applications despite very small volume cavity. Development of such technology is still under way in order to reach high vacuum level in the range of 10-1 to 10-3 mbar.
In-Coated Carbon Nanotubes for Flexible Interconnects
Authors: Xu Pingye , Hamilton Michael C. 
Published: October 2015

This work explores a method to construct metal-coated carbon nanotube (CNT) structures, which are potential candidates for interconnects, transmission lines and contact structures. This simple method is suitable to many applications including flexible substrates.
In this work, electroplating is used to coat a carbon nanotube surface with Indium. CNT films are prepared using drop casting method on different substrates: Ni coated silicon wafer, copy paper and photo paper. The CNT dispersion used for this work is prepared using sonication and centrifugation with a surfactant. The resulting dispersion has 0.8 wt. % of multi-walled CNTs and 0.5 wt. % of sodium dodecyl sulfate (SDS) in DI water. This dispersion is modified to reduce resistivity by adding either silver nanoparticle powder or silver ink. Electroplating is done at room temperature with a current density of 0.02 A/cm2.
This work addresses two issues about electroplating on CNT: low electrical conductivity of CNT film and low CNT adhesion to substrate. A CNT film on a Ni surface displays poor adhesion; the film peels off easily during ultrasonication and electroplating. After thermal annealing or microwave treatment, adhesion between the CNT film and Ni is greatly enhanced such that no CNT film peel-off is observed during electroplating. A CNT film on paper has a high sheet resistance. As a result, Indium is only plated on the CNT film near the attached electrode. To reduce the film sheet resistance, the CNT solution is modified by adding silver nanoparticle powder or silver ink. Ethanol rinsing is also performed on the CNT film surface to wash away surfactant and further reduce sheet resistance.
On-going work involves ink-jet printing of CNT solutions onto flexible substrates. Indium, as an example metallization, will be plated on these ink-jet printing defined transmission lines and interconnects patterns. Performance of these structures will be presented.
Temperature Cycling Induced Warpage of Packages with Embedded Copper Heatspreaders
Authors: Stahley Matthew , Osenbach John , Gogue Brenda , Heo Byong Il , Lee Byung Cheol , Meng Dongmei 
Published: October 2015

Temperature cycling is an important reliability qualification test given the differences in thermal expansion coefficients for the materials in integrated circuit packages. In this work, leadfree Plastic-Ball-Grid-Array (PBGA) packages with embedded C1100 copper heatspreaders were exposed to standard qualification testing including MSL3 Moisture Preconditioning with leadfree reflows at 245C followed by Temperature Cycling (TC) with ranges of −55/+125C (TC-B) and 0/+125C (TC-K) per JEDEC JESD47. Electrical performance and package warpage were characterized on as-received, post-preconditioning, and post-TC devices.
After 200 cycles TC-B, gross electrical open failures were found on a large percentage of devices in some package lots. Physical failure analysis of the open failures revealed severe package warpage, as high as 20mils on a 31mm package. The severe warpage was accompanied by delamination and sheared wires. In contrast other package lots did not show failures nor severe warpage (&lt;6mils) even after 1000 cycles of TC-B. The same package and BOM was qualified with 225C reflows for eutectic lead/tin solder with no warpage or failures after TC.
Detailed commonality studies revealed that the copper heatspreader lot used was the only definitive difference between “good” and “warped” package lots. It was found that for “warped” lots exposure to the leadfree reflow at 245C caused a significant reduction in the micro-hardness of the copper heatspreader, while there was minimal change in micro-hardness after exposure to leadfree reflow in the “good” lots.
The mechanism for this change is explained by the softening temperature of the C1100 copper heatspreader which is well within the range of leadfree reflows. Above this softening temperature, re-crystallization and grain growth occur, which result in susceptibility to permanent warpage induced by temperature cycling. Control of this warpage is critical to qualifying temperature cycling performance for heatspreader PBGA packages, and this can be achieved through micro-hardness screening of the heatspreaders.
Low Temperature Direct Aluminum Soldering Paste
Authors: Avery William F. 
Published: October 2015

For economic and weight considerations using aluminum to make connections to copper has been important in electronic components and making these connections via soldering provides an excellent thermal and electrical pathway. Soldering aluminum to copper in many applications involves the use of low temperature solder bonding to prevent damage to heat sensitive parts such as sealed copper heat pipes and sensitive electronic components. Typically, aluminum soldering is accomplished by plating over the aluminum to make that surface solderable, which is an expensive extra step in this processing. The development of a low temperature direct aluminum soldering paste eliminates the costly plating operation needed to make certain aluminum alloys solderable.
The low temperature direct aluminum soldering paste, performing below 200 °C, provides for a soldering option that will work via induction, oven reflow, hot plate, or soldering iron techniques. The paste consists of a special flux medium and a proprietary low temperature lead-free solder alloy. Evaluation of the solderpaste was by several methods. Solderability testing compared the paste on a variety of aluminum alloys. Soldering joint cross-sectioning followed by scanning electron analysis proves the viability of the solder joints. Tensile strength testing of the solder joints measured the strength of the copper to aluminum and aluminum to aluminum solder joints.