bluuebunny/crossref_metadata_2025_split huggingface dataset:
Method to measure wafer stiffness in Fan-Out Wafer Level Package
Authors: Teixeira Jorge , Ribeiro Mário 
Published: October 2015

Wafer level packaging is an important development trend for IC package design. One of the emerging variants is the fan-out wafer level package (FO-WLP), namely Embedded Wafer Level Ball Array (eWLB) [1].
In the eWLB process, singulated known good dies are placed into a “reconstituted wafer” with enough space around each chip to accommodate second-level connections. Space between dies is filled with molding compound, this construction results in a plurality of microelectronic elements triggering a particular mechanical behavior.[1].
Two of the main characteristics associated to the handling and process capabilities of wafers are warpage (or bow) and stiffness. These two properties are directly related to the success of the wafer handling and processing. However, all equipment and processes running FO-WLP were designed to process silicon wafers, which have high and homogenous rigidity and whose behavior approaches that of a true elastic material, in opposition to the “reconstituted wafer”. This fact poses several manufacturing and process challenges when dealing with “reconstituted wafers”.
Currently, different warpage methods and measurement systems are available, but wafer stiffness assessment is not yet explored and to our knowledge there is no commercially available instrument to perform this task.
In our research, it's presented an original experimental method to measure wafer stiffness. The method is based on an apparatus specifically designed to quickly record the force-displacement curve of wafer stiffness. Results are demonstrated by varying different characteristics of reconstituted wafers: Si/mold compound ratio, wafer thickness, mold compound, humidity absorption and process steps. The correlation between wafer stiffness and warpage was also investigated.
This method has been successfully used in the field and showed to be a valuable process instrument for both product development and process monitoring.
Formulation of percolating thermal underfills using hierarchical self-assembly of micro- and nanoparticles by centrifugal forces and capillary bridging
Authors: Brunschwiler Thomas , Schlottig Gerd , Ni Songbo , Liu Yu , Goicochea Javier V. , Zürcher Jonas , Wolf Heiko 
Published: October 2015

Thermal underfills are crucial to support integration density scaling of future integrated circuit packages. Therefore, a sequential process using hierarchical self-assembly of micro- and nanoparticles is proposed to achieve percolating thermal underfills with enhanced particle contacts. The three main process steps hereby are assembly of filler particles by centrifugation, formation of nanoparticle necks by capillary bridging, and the backfilling of the porous structure with an unfilled capillary adhesive.
Numerical simulations predicting trajectories and distributions of micron-sized particles dispensed into a rotating disk are presented. The trajectories exhibit a strong dependence on the particle size; thus in the case of polydisperse filler particles nonuniform particle beds may result. An efficient centrifugal disk design with spiral-like guiding structures is experimentally validated. Defect-free, percolating particle beds in confined space with fill fractions of 46 vol-% to 66 vol-%, i.e., close to the theoretical limit, are also presented.
The self-assembly of nanoparticles, forming enhanced thermal contacts between the percolating filler particles, is discussed. Two consecutive evaporation patterns during the capillary bridging process were identified: 1) dendritic network growth and 2) collapse of capillary bridges. The concave neck topology could only be achieved at temperatures below the boiling point. An optimal evaporation temperature of 60°C with respect to in-plane uniformity and neck shape was identified. Existing thermal gradients normal to the cavity surface resulted in strongly asymmetric neck formation in the cavity. Hence, uniform heating in an oven is the preferred method to initiate evaporation. Two types of bimodal dielectric necks are demonstrated. Polystyrene acts as the adhesive between thermally conductive alumina particles to form mechanically stable dielectric necks after an annealing step at 140°C. Interstitial and core-shell necks are presented.
Finally, a benchmark study was performed to compare the effective thermal conductivity of the percolating thermal underfill with and without necks with state-of-the-art capillary underfills. A close to fivefold improvement could be obtained for diamond filler particles with silver necks (3.8 W/m-K).
Characterization of Interconnects and RF Components on Glass Interposers
Authors: Ndip Ivan , Töpper Michael , Löbbicke Kai , Öz Abdurrahman , Guttowski Stephan , Reichl Herbert , Lang Klaus-Dieter 
Published: October 2015

As a result of their myriad of advantages over silicon and other conventional substrate technologies, glass substrates have received significant attention from the electronic packaging and system integration community worldwide. So far, most of the research effort on glass has concentrated on developing methods for fabricating cylindrical through glass vias (TGVs). However, to fully evaluate the potential of glass as an interposer material for microelectronic systems with computing and communication functions, an extensive characterization of interconnects and RF components on these substrates must be carried out.
In this contribution, we go beyond state-of-the-art research and present an in-depth characterization of TGVs, coplanar lines and 60 GHz coplanar excited patch antennas on two glass substrates. One of these substrates has a low alkaline content (Borofloat33®) and the other is alkaline-free (AF32®). The effects of these glass materials on the RF performance of TGVs, coplanar lines and 60 GHz antennas are extensively studied, and recommendations for performance optimization are proposed. For experimental verification, test samples are fabricated and measured. Very good correlation is obtained between the measurement and simulation results from 100 MHz to 100 GHz.
Full Integration and Electrical Characterization of 3D Silicon Interposer Demonstrator Incorporating High Density TSVs and Interconnects
Authors: Miyairi Ken , Sunohara Masahiro , Charbonnier Jean , Assous Myriam , Bally Jean-Philippe , Cuchet Robert , Feldis Helene , Murayama Kei , Aizawa Mitsuhiro , Simon Gilles , Higashi Mitsutoshi 
Published: October 2015

Silicon interposers with TSVs appear to open new possibilities thanks to high wiring density interconnections and improved electrical performances given by shorter interconnections from die to die and also from die to substrate. Silicon interposers are also promising in terms of high reliability interconnections for large chips due to minimized CTE mismatch compared to standard organic substrates.
A silicon interposer including high density TSVs has been successfully processed and fully tested. Process integration has been characterized, electrical results have been analyzed and they will be discussed in this paper. The first half of this paper will focus on integration including several technical challenges such as: 10:1 Aspect Ratio dense TSV of 10μm diameter, damascene metal layers 100,000 25μm diameter micro-bumps per die, and a specific backside redistribution layer, and the electrical data from DC tests achieved after full realization of the silicon interposer. These results show very high yield and a good uniformity among wafers.
The later half of this paper will focus on assembly process and reliability test. Conventional mass reflow was performed for each level assembly. As assembly was successfully processed, reliability test which were TC 1000 cycles to check electrical connection on daisy chain and C4 bump, HTS for 1000 hours to observe resistance change on C4 bump and HAST 1000hours to check underfill delamination was performed. All samples passed each reliability test. The results in detail will be discussed in this paper.
LORD SolderBrace™ Wafer Applied Coating for Improved Reliability and Throughput in WLCSP
Authors: Sears George , Tian Guoyun , Le Duy , Bradley Heather 
Published: October 2015

As more manufacturers look to increase the size of Wafer Level Chip Scale Package (WLCSP) dies and also look to decrease the ball pitch, the susceptibility of the die to fail during thermal cycling and drop shock testing increases. The stress conditions introduced during thermal cycling from the mismatches in Coefficients of Thermal Expansion (CTE) lead to solder fatigue. The failure of WLCSPs during drop shock is found at the solder/pad interface. The general solution to address solder fatigue during thermal cycling and solder joint stress at the copper pad interface has been capillary underfilling the chips after chip attachment.
To address these issues, a new material from LORD Corporation – SolderBrace™ wafer applied coating, can be used to partially underfill the WLCSP die at the wafer level. This type of technology can be applied using existing equipment and processing techniques making these materials a more cost effective solution. This new material technology has enabled thermal cycling reliability improvements by replacing the final passivation layer with a new low CTE material as the partial underfill.
This wafer applied partial underfill material technology has been successfully used to provide increased thermal cycling and drop shock reliability in WLCSPs using a number of different methods that have been previously described. The method to be discussed in this paper is a production process using a screen printed, photo defined polymer system that does not require any in-process post cure.
Packaging of 1.3 Tb/s Full Duplex Optical Interconnect
Authors: Benjamin Shuki , Hasharoni Kobi , Stepanov Stanislav , Katz Gideon , Geron Amir , Mesh Michael 
Published: October 2015

The electro-optical packaging process of an optical interconnect device is described. The device has an aggregate full duplex bandwidth of 1.3 Tb/s.
The optical interconnect is assembled from a standard printed-circuit-board (PCB), an optical module chip (icPhotonics™ module) and a large format fiber-bundle.
The icPhotonics™ module is assembled from an organic substrate, an Application-Specific-Integrated-Circuit (ASIC) die, vertical-cavity surface-emitting laser (VCSEL) matrix, Photo-diode (PD) matrix and 2 micro-lens-arrays (MLA's). The data is transmitted to and from a specially designed fiber-bundle through a second set of MLA's. Each optical device consists of a 12 × 14 matrix array, where each link transmits and receives in 8 Gb/s – totaling to a 1.344 Tb/s full duplex in each optical interconnect module and a bandwidth density of 64Gb/s/mm2
The icPhotonics™ module packaging is performed using five different flip-chip and reflow or glue steps – thus maximizing module density. The optical fiber-bundle assembly is performed after the PCB is populated, and completes a full optical-interconnect.
Reliability studies had been performed successfully for the entire assembly.
The optical-interconnect PCB's are routinely fabricated in a small series production scale and used as a crucial building block in Compass-EOS core-router system, creating a full mesh optical link between different line-cards and racks
A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology
Authors: Hechfellner Rudi , Kruger Michiel , Heemstra Tewe , Caswell Greg , Blattau Nathan , More Vikrant 
Published: October 2015

Light Emitting Diodes (LEDs) are quickly evolving as the dominant lighting solution for a wide variety of applications. With the elimination of incandescent light bulbs and the toxic limitations of fluorescent bulbs, there has been a dramatic increase in the interest in high-brightness light emitting diodes (HB-LEDs). Getting the light out of the die, with reliable color, while maintaining appropriate thermal control over a long service life is a challenge. These issues must be understood and achieved to meet the needs of unique applications, such as solidstate-lighting, automotive, signage, and medical applications. These applications have requirements for 15–25 years of operation making their reliability of critical importance.
The LUXEON Rebel has been accepted as an industry leading LED product, widely used in Mean-Time-Between-Failure (MTBF) sensitive applications. Customers use various mounting platforms, such as FR4 Printed Circuit Board (PCB), FR4 PCB with thermal via's, Aluminum & Copper Metal Core printed Circuit Boards (MCPCB), Super MCPCB, etc. As in other LEDs, when mounting to a platform where a large Coefficient of Thermal Expansion (CTE) exists between the LED & the PCB, Solder fatigue could become an issue that may affect system level lifetime.
In this paper we have examined extreme cases and how a solder joint can impact system level reliability. We have modeled the conditions and formed a means to predict system level reliability. We have compared the prediction modeling with empirical tests for validation of the models.
It is vital to understand system level reliability factors to build lighting solutions that match the application and customer expectations. It is impractical to test LEDs and other components for 50k hours ~5 years since the device evolution is much faster than that – on average one LED generation every 12–18 month. Hence we need models and prediction methods …..
High Thermal Conductive Inter Chip Fill for 3D-IC through Pre-applied Joining Process
Authors: Kawase Y. , Ikemoto M. , Yamazaki M. , Sugiyama M. , Kiritani H. , Mizutani F. , Matsumoto K. , Horibe A. , Mori H. , Orii Y. 
Published: October 2015

Three dimensional (3D) IC has been proposed for high performance and low power in recent years. Due to the narrow gap between stacked chips and fine pitch of bumps, new inter chip fill (ICF) which can be used for pre-applied ICF process is required. The heat generation of 3D-IC is higher than 2D, so that a high thermal conductive inter chip fill (HT-ICF) is simultaneously required to dissipate the heat from 3D-IC and for the purpose of pre-applied ICF and HT-ICF, highly active flux agent and thermal conductive materials such as filler and matrix have been called for at the same time.
In this study, some kind of materials were prepared, synthesized and optimized for the HT-ICF, and we evaluated its characteristic and confirmed applicability to pre-applied joining for 3D-IC.
A Photo-Desmear Method for Via Residue Removal Using a VUV Light Source
Authors: Habu Tomoyuki , Yabu Shintaro , Hirose Kenichi , Horibe Hiroki , Fujinami Toru , Kitano Naoki , Ozawa Eiji , Bhattacharjee Sanchali , Andideh Ebrahim , Sobieski Daniel 
Published: October 2015

The desmear process of removing via residue after laser drill in substrate manufacturing is a critical step for reliability and electrical performance. Cost effective and environmentally clean desmear processes are industry-wide objectives, as the current wet desmear process results in significant chemical waste and regular bath replacement.
Here, we evaluated an effective photo desmear method targeting a low total cost of ownership and negligible environmental impact. This method achieves residue and silica free via bottoms with the use of 172nm vacuum ultraviolet light (VUV) photo-chemical ashing followed by water clean. Studies of organic molecular photochemical decomposition by short wavelength UV light are widely reported and have been applied for purposes such as surface cleaning and improving wettability and are naturally extendable to via residue removal. Scanning electron microscope (SEM) and energy dispersed X-ray spectroscopy (EDX) reveal that the application of VUV desmear results in residue free microvia without negatively affecting via shape or the dielectric surface. In addition, the surface remains highly wettable, which aids downstream copper plating. The high reaction rate, absence of wet chemistry, and creation of surfaces amenable for subsequent copper plating make this dry desmear process a strong candidate for future applications in substrate manufacturing.
Package design and development of a low cost high temperature (250°C), high current (50+A), low inductance discrete power package for advanced Silicon Carbide (SiC) and Gallium Nitride (GaN) devices
Authors: McPherson B. , Passmore B. , Killeen P. , Martin D. , Barkley A. , McNutt T. 
Published: October 2015

The demands for high-performance power electronics systems are rapidly surpassing the power density, efficiency, and reliability limitations defined by the intrinsic properties of silicon-based semiconductors. The advantages of post silicon materials, including Silicon Carbide (SiC) and Gallium Nitride (GaN), are numerous, including: high temperature operation, high voltage blocking capability, extremely fast switching, and superior energy efficiency. These advantages, however, are severely limited by conventional power packages, particularly at temperatures higher than 175°C and &gt;100 kHz switching speeds.
In this discussion, APEI, Inc. presents the design of a newly developed discrete package specifically intended for high performance, high current (&gt;50A), rapid switching, and extended temperature (&gt;250°C) wide band gap devices which are now readily available on the commercial market at voltages exceeding 1200V. Finite element analysis (FEA) results will be presented to illustrate the modeling process, design tradeoffs, and critical decisions fundamental to a high performance package design. A low profile design focuses on reducing parasitic impedances which hinder high speed switching. A notable increase in the switching speed and frequency reduces the size and volume of associated filtering components in a power converter. Operating at elevated temperatures reduces the requirements of the heat removal system, ultimately allowing for a substantial increase in the power density.
Highlights of these packages include the flexibility to house a variety of device sizes and types, co-packaged antiparallel diodes, a terminal layout designed to allow rapid system configuration (for paralleling or creating half- and full-bridge topologies), and a novel wire bondless backside cooled construction for lateral GaN HEMT devices. Specific focus was placed on minimizing the cost of the materials and fabrication processes of the package components. The design of the package is discussed in detail. High temperature testing of a SiC assembly and electrical test results of a high frequency GaN based boost converter will be presented to demonstrate system level performance advantages.
Advanced warpage characterization for FOWLP
Authors: Teixeira Jorge , Ribeiro Mário , Pinho Nélson 
Published: October 2015

Current standards for silicon wafers shape characterization use simple metrics. Warpage and bow are computed as the mean surface wafer height range or the mean surface wafer center height, respectively [1]. These metrics are valid for silicon wafers because of their homogenous and linear thermomechanical properties [2].
In fan-out wafer level package (FO-WLP), embedded Wafer Level Ball Grid Array in specific (eWLB), the use of epoxy mold compound that works both as the physical carrier of the dies and as the base of second level connections has a major impact on the overall macroscopic behavior of the wafer, inducing shapes that do not follow a simple bended or bowed wafer, impacting wafer processability [3].
Warped wafers can affect device performance, reliability, and linewidth control in various processing steps [3]. Early detection will minimize cost and processing time. In our research, we present a solution for wafer characterization in FO-WLP by increasing the information vector that one obtains from standard automated non-contact scanning equipment. For this, we defined wafer shape and wafer ratio as the two new metrics besides warpage, creating a three dimensional vector that can be used to compare and evaluate wafers in high volume production or even single wafer analysis. This is a major improvement over previously used approaches, in which only the average warpage is considered. These metrics were determined by the developed numeric algorithm and their validity was demonstrated through the use of different production conditions, wafer constructions and production monitoring. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods. Experimental results demonstrate its feasibility and repeatability. This methodology was successfully used in the field and proved to be of high value when evaluating wafer geometrical requirements for both product development and process monitoring.
Immersion Tin for QFN Packages to create a 3-D solder joint for reliability enhancement
Authors: Özkök Mustafa , Mertens Hubertus , Bender Jerome 
Published: October 2015

The QFN (Quad-Flat No-leads) package is one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. The side edges of the standard QFN Package are not covered by solder, which results in the fact that the package is soldered only planar in 2 dimensions from the QFN bottom side onto the PCB as shown on fig. 1 a).
The QFN where the side edge is covered by immersion tin will keep the side edged of a QFN solderable as shown in fig. 1 b). This allows the package to be soldered in 3 dimensions onto the PCB providing a stronger solder joint and a better reliability. The suggested paper describes a new process to cover the side edges of the package with immersion tin after the QFN package singulation step. The exposed lead frame edges are covered by immersion tin. No exposed copper is visible and delivers a 3 dimensional solder joint with better reliability and protection for the soldered package.
Thick film pastes for nitride ceramics for high power applications
Authors: Wenzel Marco , Schmidt Richard , Partsch Uwe , Eberstein Markus 
Published: October 2015

Aluminum and silicon nitride ceramics show high potent as substrate materials for thick film- / hybrid applications in the field of power electronics and microwave technology. A main advantage of AlN is its very high thermal conductivity. Si3N4 has also a thermal conductivity comparable to AlN but higher thermal shock resistance and fracture toughness. Nevertheless, the use of Si3N4 in power electronic packages or heater applications is not achieved due to the lack of suitable connection technology such as thick film pastes. The main challenge for the respective pastes is the adhesion on the substrate. The low thermal expansion (CTE) of about 2.8 ppm/K of Si3N4 and material interactions with the thick film components must be considered in the paste development. Therefore, new glasses and glass-ceramic composites are required.
Reason development was performed towards AgPd based thick film heater pastes for Si3N4. The pastes consists of AgPd in a 1:1 ratio, an inorganic filler and a glass phase adapted to the CTE of Si3N4. By variation of the content of inorganic filler and glass content three pastes with a sheet resistivity of 0.1 ohm/sq, 0.8 ohm/sq, and 7.9 ohm/sq and temperature coefficient of the resistance (TCR) between −100 and 100 ppm/K were developed. The performance of heater films prepared from these pastes under electric pulse load was studied. An electrical power of up to 85 W can be applied without a significant change of the resistivity (ΔR/R) of 0.1%. As reference comparable investigations on AlN were performed with adapted pastes. The film structures were analyzed in FESEM studies.