bluuebunny/crossref_metadata_2025_split huggingface dataset:
High Temperature Endurance of Packaged SOI Devices for Signal Conditioning and Processing Applications
Authors: Riches S T , Johnston C , Sousa M , Grant P 
Published: October 2015

Silicon on Insulator (SOI) device technology is fulfilling a niche requirement for electronics that functions satisfactorily at operating temperatures of &gt;200°C. Most of the reliability data on the high temperature endurance of the devices is generated on the device itself with little attention being paid to the packaging technology around the device. Similarly, most of the reliability data generated on high temperature packaging technologies uses testpieces rather than real devices, which restricts any conclusions on long term electrical performance.
This paper presents results of high temperature endurance studies on SOI devices combined with high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. The endurance studies have been carried out for up to 7,056 hours at 250°C, with functioning devices being tested periodically at room temperature, 125°C and 250°C. Different die attach and wire bond options have been included in the study and the performance of multiplexers, transistors, bandgap voltage, oscillators and voltage regulators functional blocks have been characterised.
This work formed part of the UPTEMP project which was set-up with support from UK Technology Strategy Board and the EPSRC. The project brought together a consortium of end-users (Sondex Wireline and Vibro-Meter UK), electronic module manufacturers (GE Aviation Systems Newmarket) and material suppliers (Gwent Electronic Materials and Thermastrate Ltd) with Oxford University-Materials Department, the leading UK high temperature electronics research centre.
High-Temperature Trench Capacitors, Using Thin-Film ALD Dielectrics
Authors: Dietz Dorothee , Celik Yusuf , Goehlich Andreas , Vogt Holger , Kappert Holger 
Published: October 2015

High-temperature passive electronic becomes more and more important, e.g. in the field of deep drilling, aerospace or in automobile industry. For these applications, capacitors are needed, which are able to withstand temperatures up to 300 °C, which exhibit a low leakage current at elevated temperatures, a breakdown voltage above the intended operating voltage and a high capacitive density value.
In this paper, investigations of 3D-integration and atomic layer deposition (ALD) techniques to achieve these features are presented. A highly n-doped Si-substrate acts as a bottom electrode. Medium- and high-k dielectrics represent the insulator and the upper electrode consists of Ru, TiN or TiAlCN. The materials can be used at elevated temperatures. At room temperature, the leakage current is less than 10 pA/mm2 without showing a soft-breakdown up to ± 15 V, indicating the absence of Fowler-Nordheim tunneling. At 300 °C and at 3 V the leakage current amounts about 1 nA/mm2 and at 5 V a soft-breakdown is detected.
Inorganic Insulated Metal Substrates
Authors: Shashkov Pavel , Curtis Steven , Humpston Giles 
Published: October 2015

Insulated metal substrates (IMS) are gaining ground in electronics applications thanks to their high thermal conductivity and low cost. However, the organic dielectrics (such as epoxy or polyimide based material) traditionally used on IMS are limited by their maximum operating temperature, generally to below 150–200 °C. Thus in high temperature applications manufacturers are restricted to using expensive inorganic substrates such as alumina (Al2O3), aluminium nitride (AlN) or silicon nitride (Si3N4). A cost-effective IMS with an inorganic dielectric would be an attractive alternative for high temperature electronics.
Cambridge Nanotherm has developed an electrochemical process for building inorganic dielectric ceramic onto a metal base. Nanotherm ceramic material is nanocrystalline alumina with a grain size of 20 to 60 nanometres. This grain size plays a critical role in providing the dielectric layer with its unique combination of properties such as high thermal conductivity (6–7 W/mK), high dielectric strength (&gt;50 V/um) and formability when applied on thin, foil-type substrates. The Nanoceramic layer can be built from 3 to 50 microns thick, depending on the breakdown voltage required. This avoids excessive dielectric thickness that unnecessarily increases the thermal resistance of the system. The electric circuit is built onto the ceramic surface using either PVD metal sputtering followed by galvanic metal build up or conventional thick film processing. The result is a cost-effective, easy to process and use inorganic substrate with a thermal conductivity around 150 W/mK and a maximum working temperature above 350 °C.
This paper will present an overview of the key electrical and thermal properties of Nanoceramic aluminium substrates and their manufacturing process. Potential use in the thermal management of high temperature electronic devices will be discussed with reference to some applications.
Validated High Speed Pull and Shear Test Methodologies to Evaluate Pb-Free BGA Mechanical Strength
Authors: Ahmad Mudasir , Assudani Ravi , Nelson Drew , Youssef Amir 
Published: October 2015

The conversion to lead free Ball Grid Array (BGA) packages has raised several new assembly and reliability issues. Lead-free solder joints are generally stiffer than tin-lead solder joints, and mechanically induced failures have become more prevalent in lead-free solder assemblies. Traditionally, assembly bend and shock testing is performed to evaluate mechanical assembly reliability. However, bend and shock tests are expensive, cumbersome and not feasible for evaluating lot-to-lot variations in mechanical strength.
Consequently, there is a need for a validated, component level test method that can be used as an accurate indicator of assembly level mechanical strength. Several publications have been written to evaluate the efficacy of high speed pull and shear testing as a viable reliability indicator [1 – 10].
In this study, a comprehensive Gauge R&R study was performed to evaluate the accuracy of the test equipment, including high speed video calibration. Then, test studies were performed to compare the accuracy of the results, spread across different package constructions, solder metallurgies, ball pitch and surface finish. In addition, the effect of parameters like multiple reflows and aging on specific metallurgies and surface finishes was studied. The results were generated over more than 2000 test runs.
Finally, the study rank orders all critical test parameters and articulates what precise steps can be taken to generate relevant data for standard and custom devices during early evaluation stages and during high volume manufacturing.
Interconnect Failure Rate Estimation Based on the Extreme Value Distribution
Authors: Plucinski Mark , Hoffmeyer Mark 
Published: October 2015

Evaluating and predicting the failure rate of interconnect is a time consuming and expensive process. Non parametric techniques to analyze the qualification data, such as employing the Chi-square distribution require large sample sizes to achieve an accurate estimate.
Recently there has been a resurgence in the use of extreme value theory (EVT). Increases in temperature records, the numbers of strong storms, and flooding events have fueled this interest. A novel method that is based on EVT and an accelerated degradation model for estimating the failure rate from a set of stress data is proposed and described.
There are many advantages of this technique, and recommendations on sample size are discussed. Advice is given as to how the total sample should be sectioned before the maximum is taken of each subset. Interconnect examples are given, generated from Monte Carlo simulations of known distributions, and used for a comparison of the extreme value technique versus Chi-square and Johnson distribution methods.
Improvements in Solid State Lighting Applications with the use of Traditional Thick Film Technology.
Authors: Groman Sarah , Jones Neil 
Published: October 2015

As the LED market continues to grow and overtake many other lighting technologies such as incandescent and compact fluorescent bulbs (CFL), there are many challenges that LED manufacturers face. As demand for higher power and longer life continue to drive LED adoption in lighting applications, manufacturers must be able to find ways to increase thermal efficiency while reducing cost for LED package designs.
In this paper, the benefits of a new Pb Free smooth-print thick film Ag conductor are examined in comparison to more traditional die attach methods, which include plated thin films, and polymer based die attach adhesives. A smooth print thick film conductor can offer the best of both worlds as cost and process simplicity are comparable to a polymer system, while thermal efficiency and solderability are comparable to plated thin film systems. As surface smoothness increases, there is also the benefit of reduced solder voiding and material usage; solder voiding is a major contributor to thermal inefficiency. In the case of high cost solders such as Au/Sn, the reduction in material usage can translate to significant cost savings. Thermal efficiency, solderability, and manufacturing complexity must all be considered as new LED package designs are sought that reduce overall cost while increasing thermal efficiency and effective operational life.
This paper evaluates these benefits as they apply to wire bonding, thermal dissipation, surface smoothness, and voiding at the die-package interface. Each of these properties can affect thermal efficiency of the package, which in turn affects the light output and effective operational life of the LED. A new option for LED package design is presented, and this packaging can allow for cost-effective manufacturing while keeping up with industry demands of higher power, maximum efficiency, and greater effective operational life.
Study of Grounding Schemes Utilized in Conformal Shielding Applications
Authors: Morris Scott , Carey Dan 
Published: October 2015

There are many different shielding technologies available for electromagnetic interference (EMI) shielding in radio frequency (RF) applications. We will investigate various EMI shielding technologies, one of which is RFMD's MicroShield™ Integrated RF Shielding technology's conformal plating process that encapsulates the device with a solid sheet of metal. This novel technology provides improvements in form factor, ease of use, and lower cost as compared to traditional shielding approaches.
We will compare ground designs within the substrate to determine maximum EMI shield performance. An examination of ground structures, layer grounding, and external ground connections will be analyzed. The test device structure will be comprised of a radiating element on the top surface of the laminate. A thorough look at the advantages and limitations between these different EMI grounding configurations will be discussed. This data will be used to quantify grounding effectiveness which will, in turn, be used to generate design guidelines.
Mask and mask-less injection molded solder (IMS) technology for fine pitch substrate bumping
Authors: Nah Jae-Woong , Gruber Peter A. , Lauro Paul A. , Feger Claudius 
Published: October 2015

We report the results of a new pre-solder bumping technology of injection molded solder (IMS) for fine pitch organic substrates. Pure molten solder is injected through a reusable film mask (mask IMS) or directly injected without a mask (mask-less IMS) on the pads of an organic substrate to overcome the limitation of current pre-solder bumping technologies such as solder paste stencil printing and micro-ball mounting.
In the case of mask IMS, targeted solder height over the solder resist (SR) is designed into the mask which has desirable thickness and hole sizes. Three different solder bump heights such as 30, 50, and 70 microns over SR were demonstrated for commercial organic substrates which have a pitch of 150 μm for 5,000 area array pads. To show the extendibility of the mask IMS bumping method to very fine pitch applications, 100 μm pitch bumping of 10,000 pads and 80 μm pitch bumping of 15,000 pads were demonstrated.
In mask-less IMS, the pure molten solder is directly filled into the opening volume of the SR. After the injection of molten solder, solidification of the solder under low oxygen leads to solder protrusions above the SR surface because 100 % pure solder is filled into the whole SR opening volume. For a 150 μm pitch commercial substrate, we demonstrated minimum bump heights of 15 μm over the 20 μm thick SR. Since there is no need to align mask and substrate, the maskless IMS method lowers process costs and makes the process more reliable. By manipulating the opening in the SR, it is possible to enable variations in the height of the solder bumps.
Flux or formic acid is not needed during solder injection of both described processes, but a low oxygen environment must be maintained.
In this paper, we will discuss laboratory scale processes and bump inspection data, along with the discussion of manufacturing strategies for IMS solder bumping technology for fine pitch organic substrates.
Using In situ Capacitance Measurements to Monitor the Stability of Thermal Interface Materials in Complex PCB Assemblies
Authors: Gaynes Michael , Chainer Timothy , Yarmchuk Edward , Torok John , Edwards David , Olson David , Pizzolato Katie 
Published: October 2015

A thermal solution for an array of voltage transformer modules which are cooled by a large area, common aluminum heat spreader for a high end server was evaluated using an in situ, capacitive bond line thermal measurement technique. The method measures the capacitance of a non-electrically conducting thermal interface material (TIM) between the electronic module and heat spreader to quantify the TIM bond line effective thickness during assembly and operation. The thermal resistance of the TIM has the same geometric dependence as the inverse of capacitance, therefore, the capacitive technique also provided a monitor of the thermal performance of the interface.
This technique was applied to measure the bond line in real time during the assembly of the heat spreader to an array of 37 modules mounted on a printed circuit board. The results showed that the target bond lines were not achieved by application of a constant force alone on the heat spreader, and guided an improved assembly process.
The mechanical motion of the TIM was monitored in situ during thermal cycling and found to fluctuate systematically from the hot to cold portions of the thermal cycle, either compressing or stretching the TIM respectively. The capacitive bond line trend showed thermal interface degradation vs. cycle count for several modules which was confirmed by disassembly and visual inspection. Areas of depleted TIM ranged as high as 25% of the module area.
Several design and material changes were shown to improve the TIM stability. Power cycling tests were run in parallel to the thermal cycle tests to help relate the results to field performance. The capacitance technique enabled the development and verification of a thermal solution for a complex mechanical system early in the development cycle.
A Novel Metal Core Substrate with Simplified Manufacturing Process and High Adhesion Conformal Dielectric and Circuitry Metal for High Density Chip-Scale Packaging Applications
Authors: Ahmad Syed Sajid , Jacobson John , Johnson Zane , Mattson Kevin , Reinholz Aaron , Schneck Nathan , Scholz Bernd , Strommen Greg 
Published: October 2015

Substrates play a critical role in the quality and reliability of electronic packages and systems. Metal core substrates provide opportunities with respect to strength, heat dissipation, and speed over common organic substrates. The metal core provides an opportunity for grounding enhancements in RF circuits.
This paper presents the results of the development of a metal core substrate design which has advantages over conventional competitive designs. The manufacturing flow developed in this work has fewer process steps, uses fewer materials and shows interfacial adhesion strength above industry requirements.
The work outlines material evaluations to enhance the interfacial adhesion and corrosion resistance. The results of the evaluation of mechanical, chemical, and other methods to enhance interfacial adhesion are presented and compared. The enhanced interface shows significant adhesion increase for the circuitry metal over and beyond industry requirement.
A Method to Quickly Measure the Thickness of Aluminum Bond Pad on Silicon Substrate
Authors: Nguyen Son , Delalic Z. Joan , Clauberg Horst 
Published: October 2015

In wire bonding, the thickness of the aluminum pad under the bonds needs to be measured for bonding process optimization purposes. In Cu wire bonding, the deformation of the Al bond pad is larger than in Au wire bonding. Because of this, the uniformity and thickness of Al that remains under the ball is often used as a metric in the process optimization. The thickness of the Al pads can be inspected with manual cross sectioning or FIB (Focused Ion Beam). However, these two methods are time consuming and expensive. This paper presents a method that helps to quickly measure the aluminum pad, which involves creating a graph of penetration of electron beam at different EDS (Energy Dispersive Spectroscopy) voltages versus Al thickness.
The method basically consists of: a) crafting Al layers of different thicknesses, b) obtaining EDS for each layer at different EDS voltages, c) performing cross sectioning of those layers and measuring the thickness of the layers, d) generating the metric based on the acquired data, and e) testing the acquired metric.
Automated Precision Assembly for High-Volume HB LEDs
Authors: Beck Donald J. , Sylvester Jessica 
Published: October 2015

Since the introduction of automated die and wire bonders in the 1980s, equipment manufacturers and process engineers have been challenged to balance speed with repeatability. Today, die bonders can perform epoxy die attach at a rate of 1.5 to 4 thousand die per hour [6]; and wire bonders can interconnect complex packages at speeds of more than 10 wires per second [7]. The advantage of automation is speed and consistency—however, there is one major concern with operating at these speeds: if something in the assembly process is wrong, everything will be wrong. Having tightly regulated assembly processes helps avoid the risk of building a large batch of rejected product.
This paper presents a methodology and process flow supporting High Bright Light Emitting Diode (HB LED) automated assembly, supported by equipment certification, product inspection and SPC data collection methods. The methods presented in this paper have been formulated through extensive work in the high-reliability microelectronics industry and commercial production lines over the last three decades. To ensure time-to-market success in high-volume production, specific methods to achieve throughput and quality are required. This paper will cover the strategies and methods necessary to achieve the ultimate goal of an automated precision HB LED assembly—to blend the requirements of high-reliability and high-throughput to support high-volume commercial production.
GaN based RF Modules - Demands & Needs for Packaging
Authors: Oppermann M. , Widmer K. , Reber R. , Sledzik H. , Schuh P. , Schmid U. , Bunz B. , Chartier S. , Drüeke K. , Bedenbecker M. 
Published: October 2015

GaN/SiC based powerbars and MMICs are the youngest semiconductor devices which have arrived in the field of Radio Frequency modules and applications, e.g. radar, communication links and high power transmitters and amplifiers. Nearly 5 years ago, the first GaN devices were used in the fields of telecommunication equipment, mainly in base-station amplifiers and today GaN devices are more and more part of modern radar applications, like T/R (Transmit/Receive) modules in AESA (Active Electronically Scanned Array) antennas.
The main advantages of GaN/SiC semiconductor devices in comparison to GaAs-devices are the higher bandwidth, higher robustness level and the higher operation voltage. Another big issue of GaN is the higher power density, with in minimum 4 times higher values compared to GaAs. Therefore the assembly of GaN MMICs and powerbars on heatsinks and module-baseplates is a big challenge for soldering technology. An absolute minimum of voids between backside of the GaN/SiC devices and the heatsink is necessary to guarantee an optimised heat transfer during operation.
Different package materials and technologies are on the market and big international package suppliers deal with new material combinations, like sandwich structures of Cu and Mo. Materials like Al-diamond are used for heatsink materials and with special tests and measurements the results of heat transfer studies will be shown.
In this paper examples of power amplifiers, operating in the frequency range of 2–6 GHz and 6–18GHz, and a typical X-Band Frontend will be shown and the RF results will be discussed.
Evaluation of electromigration in flip-chip solder joints
Authors: Lee Hyun-Kyu , Chu Yong-Chul , Chun Myung-Ho , Jeon Sang-Ho , Kwak Jung-Ug , Lee Seung-Jin , Bae Sung-Mun 
Published: October 2015

The flip-chip solder joint has become one of the most important technologies of high-density packaging in the microelectronics industry. But, electromigration has become a critical reliability issue in flip-chip technology. Because the dimensions of solder joints are expected to decrease and current density is expected to increase.
This study is about electromigration of flip-chip solder joints, we evaluated many kinds of solder balls such as SnAgCu, SnCu and so on in flip chip package. The lifetime against electromigration was defined the fail from the value of resistance with electric current reaches 1.5 times of that of initial resistance with electric current for.
In solder bumps with electric current, since the atoms composed of the solder bump and UBM move in the direction of electron flows, the IMC was accumulated on the anode side. Meanwhile, the IMC disappeared in the cathode side, and the voids were formed. In the solder bumps without electric current, the IMC gradually grew on both sides.
SnAgCu had better lifetime than SnCu, and different time-to-failure caused by different crystallographic orientation of Sn. And various dopants in SnCu had a different EM lifetime each other.