bluuebunny/crossref_metadata_2025_split huggingface dataset:
Next Generation System in a Package Manufacturing by Embedded Chip Technologies
Authors: Boettcher Lars , Ostmann A. , Manessis D. , Karaszkiewicz S. , Reichl H. 
Published: October 2015

The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies.
This paper will briefly discuss the necessary process steps of the embedded chip technology and more importantly it will focus on new efforts to actually use chip embedding concepts for the realization of standard-type industrial Quad Flat Packages with embedded chips (embedded chip QFN). Chips of 50 μm thickness, a pad pitch of 100 μm and pad size of 85 μm are die bonded to a copper substrate and subsequently embedded in RCC (Resin-Coated-Copper) layers by using vacuum lamination.
The resulting QFN packages are only 160 μm thick and provide standard pads at 400 μm pitch and a total number of 84 I/Os with dimensions of 10x10 mm2. All embedded chip QFN packages at prototype level are manufactured in 250x300 mm2 panels.
The present work will include QFN package reliability results after extensive testing of thermal cycling, temperature humidity, high temperature storage and pressure cooker test.
The investigation of new embedding material combinations is one task to provide a reliable package. The main focus here is on new materials that offer improved package stability and also the ability to embed dies of different thickness. Together with material suppliers improved resin formulations as well as the introduction of filler and glass fibers into the resin layers is currently realized and tested.
In order to realize a further miniaturization ultra fine pitch (UFP) and fine line (UFL) approaches will be presented. For a UFP approach the goal is to develop the laser via technology further towards their limits as well as the investigation of new concepts.
UFP requires the use of a semi additive patterning process. Here LDI processing is being used for all new generation chip embedded packages due to its potential for very fine copper patterning. Results on very fine L/S of 15–20μm will be shown based on the semi-additive processes on an ultra thin initial 1–2μm copper foil.
Finally different applications will be presented. In an industrial cooperation different power package developments are ongoing. Here single and multi chips modules are realized as well as multiple routing layers. The combination of power and logic is one of the main challenges here, due to the need of thick copper layers for the power part and the more fine pitch demands for the controller chips. Process developments and results will be discussed in detail.
Effect on Reliability of Bending Flexible Circuits
Authors: Dzarnoski John , Sun Kexia 
Published: October 2015

There has been enormous worldwide effort to increase the volumetric efficiency of electronic packaging. Much of this effort has been driven by the telecommunications industry that has succeeded in reducing cell phone size while simultaneously increasing functionality. The hearing aid business has always had the need to use extremely small electronic packaging because hearing aids pack electronics into the ear canal. In recent years hearing aid microelectronic packaging has moved from ceramic hybrid based packaging to a flexible circuit based technology. Due to the size and shape of all types of hearing aids, flexible circuits need to be folding and bent to fit inside hearing aid cases. In order to reduce space, bends and folds are pushing conventional wisdom on the limits of mechanical integrity.
There is little published information regarding bendability of multilayer flexible circuits for class I medical device applications. This paper will examine bending and folding effects on a Polyimide/Adhesive/Copper/Polyimide/Copper/Adhesive/Polyimide structural stack-up on a test coupon and a HDI flexible circuit. A forming tool that controls every aspect of bend testing will be discussed. A variety of factors were investigated including bend angle, thickness of the circuit, bend radius, foil weight, copper materials, construction, and frequency of flexing. The circuit electrical resistance, microstructure and crack initiation were monitored during the process and will be examined. Failure mechanisms will be discussed as well as their impact on design.
A Review of Wafer Coating Methods for 3D Packaging
Authors: Adamson Steven J. , Klocke James , De Sanctis Gareth 
Published: October 2015

For many years, Front End of Line (FEOL) wafer fabrication, has used spin coating as the method of choice for photoresist application. Today, 3D packaging requires coatings applied to the non-active side of the wafer. Popular applications for back side coatings are, temporary adhesives to hold wafers to carriers during Through Silicon Via (TSV) fabrication, applying die / wafer bonding materials, and dielectric layers.
Spin coating of wafers can be used to apply a number of materials for backside coatings. Although this application method is quite fast, it has a number of drawbacks which include high material waste and its limitation to low viscosity materials. Wafer Backside Coating (WBC) adhesives applied prior to dicing poses some unique challenges due to their filler loadings, and therefore the formulations can be limited by the spinning process. Today, most companies using spin coating to apply WBC materials have to lower the viscosity of the fluid with solvents, which creates other problems.
Screen or stencil printing to apply WBC adhesives is a proven method and is currently in production at manufacturing sites. Screen printing gives good print uniformity, but requires a formulation that self-levels after printing. Stencil printing can be used with almost any formulation or filler loading, but is highly dependent on the tooling accuracy to maintain the coating thickness uniformity. Both methods are limited to coating thicknesses in the 25–100 micron range.
There exists a need for a wafer coating methodology that can overcome the aforementioned restrictions. The ability to apply materials of varying rheologies, with low material waste and yet provide high quality, uniform coatings is required.
This paper will review the current methods of applying WBC coatings. The authors will also present results from a newly developed spray coating process developed to process high viscosity fluids such as WBC coatings.
Characterization of Wafer Level Metal Thermo-Compression Bonding
Authors: Cakmak Erkan , Kim Bioh , Dragoi Viorel 
Published: October 2015

The process of wafer-level bonding is being successfully used to form MEMS devices. Wafer level bonding may be realized by different methods such as thermo compression, transient liquid phase, anodic, glass frit, or polymer bonding. These methods have different requirements and the choice of wafer level bonding method is defined by the application type. Metal TCB has a wide variety of applications with materials of choice including Au, Cu and Al. 3D electrical connections are created by the use of Cu-Cu TCB; while CMOS MEMS devices may be realized by Al-Al TCB.
In this study the wafer level bonding process of Cu-Cu and Al-Al TCB are characterized. The effects and significance of various bonding process parameters and surface treatment methods are reported on the final bond interfaces integrity and strength. Analysis methods include SAM, SEM, AFM, and four point bending test.
Al-Al TCB samples were investigated on the interfacial adhesion energy and bond quality. IAE and bond quality were found to be positively correlated with bonding temperature. A bonding temperature of 500 °C or greater is necessary to obtain bond strengths of 8–10 J/m2. A positive relation between IAE and bonding temperature was observed for Cu-Cu TCB. IAE's of greater then 10 J/m2 were obtained on bonded samples that do not show a post bond residual seam on the bonding interface. An acid based pre treatment was shown to impact the surface properties of the initial metal surface hence affecting the IAE. Post bond annealing processes showed the most significant impact on the IAE of the Cu-Cu TCB system.
To obtain comparable IAE values the Al-Al TCB method requires a higher bonding temperature. However the Cu-Cu TCB is sensitive to the initial metal surface condition and requires surface treatment processes prior to bonding to obtain high quality bonding results.
Direct Cu Wet Seed on Barrier of TSV Wafer
Authors: Han Jianwen , Lin Xuan , Zhang Yun , Aby Joseph , Mourier Thierry 
Published: October 2015

Through Silicon Vias (TSVs) promise to provide shorter interconnect length and higher electrical connection density with reduced signal delay and power consumption for both multichip interconnection and packaging. To achieve void free electrolytic TSV gapfill, continuous seed is critical. While the TSV dimension scales down and the aspect ratio increases, continuous Cu seed coverage is harder to achieve by conventional PVD process. Giving the conformal nature of electrochemical process, direct electrolytic Cu deposition on barrier is an alternative to enable continuous seed coverage.
The challenges for direct wet seed are: (1) the barrier layer, typically TiN and TaNx, is too resistive to achieve uniform thickness distribution by conventional copper plating processes. (2) the nucleation of copper on barrier oxides is difficult and the copper growth is dendritic.
Designed for direct seeding on barriers, a novel chemistry has been developed. This alkaline (pH 9~10) bath has been demonstrated with TSV wafers with different barriers including Ta, TaNx, Ti, TiN. The process has shown to provide high nucleation density (10Exp11~10Exp12 nuclei/cm2) and continuous seed coverage can be achieved between 10 and 25nm thickness on most barriers. The deposition takes place at very negative plating potential while the current efficiency is maintained at &gt;90%. The strong polarization enables in-situ barrier oxide reduction for some barriers, and pretreatment becomes not necessary. Elimination of oxides along with high nucleation density significantly enhanced the bonding strength between copper and barriers. The wet seed on all barriers including Ta, TaNx, Ti, TiN has passed ASTM D3359 cross-cut tape test. Electrolytic TSV gapfill on the wet seed is demonstrated for patterned TiN barrier TSV wafer. Void-free fills are achieved for the features with dimensions between 20 and 200 microns.
In summary, the novel chemistry for direct copper wet seed deposition on barriers has been demonstrated to yield high nucleation density and uniform seed distribution with adequate adhesion, and the wet seed enables subsequent void free TSV gapfill.
Enabling Thin Wafer Metal to Metal Bonding through Integration of High Temperature Polyimide Adhesives and Effective Copper Surface Cleaners
Authors: Rardin Anthony B. , Kirk Simon J. , Zussmann Mel P 
Published: October 2015

This paper will examine the use of high temperature Polyimide temporary adhesives and advanced copper cleaning solutions for thin wafer handling during metal to metal (Cu-Cu) bonding. In the case of Cu to Cu solid state diffusion bonding, temperature requirements can be up to 400C for as long as 40 minutes. These extreme conditions pose a significant challenge with existing materials used for temporary bonding.
Polyimides are ideally suited for high temperature application and polyimide adhesives have been developed which can withstand 400°C processing without significant failure in adhesion. As well, Cu to Cu bonding processes will require the need for contamination free surfaces, which becomes increasingly important if lower temperature processes (&lt;400C) are desired. Close-coupled copper cleaning immediately prior to the bonding step offers an excellent approach for providing process reproducibility while achieving increased electrical yields. Utilizing advanced wet cleaning solutions to obtain optimal Cu surface preparation through the removal of undesirable copper oxide layers as well as organic contaminants such as Benzotriazole (BTA) is also discussed in detail.
Micro IMU Utilizing Folded MEMS Approach
Authors: Rivers Montgomery C. , Trusov Alexander A. , Zotov Sergei A. , Shkel Andrei M. 
Published: October 2015

In this paper, we propose a novel wafer-level approach for fabrication and 3-D integration of MEMS devices in miniature multi-axis assemblies of inertial, acoustic, and optical sensors. The approach is based on simultaneous fabrication of all sensors on the same substrate connected by flexible electrical interconnects, mechanical hinges and latches. A multi-axis sensor system is then obtained by folding the fabricated structures into 3-D cubes, pyramids, or other rigid shapes, and subsequently micro-welded. In the current work, we demonstrate feasibility of the folded cube approach for creation of miniature MEMS IMU with &lt;1 cm3 volume.
Design of the IMU consists of a folded cube or pyramid backbone structure with micromachined accelerometers and gyroscopes on its sidewalls. Silicon-on-insulator (SOI) wafers are used as a substrate for fabrication of both the inertial sensors and the folded backbone structure. Fabrication of the sensors consists of lithography, deep reactive ion etching (DRIE), and HF acid release of the inertial proof masses. Flexible polymer hinges connecting faces of the folded structures are defined on the same substrate and incorporate electrical interconnects. To provide rigidity to the assembled 3-D structure, interlocking silicon latches are fabricated along the edges of each sidewall, which are silicon-to-silicon welded after assembly.
The approach allows for creating miniature multi-axis sensor systems without compromising performance of individual sensors. Gyroscopes integrated in the current folded cube IMU have experimentally demonstrated 3-dB bandwidth of 250 Hz and angle random walk (ARW) below 0.1 (deg/s)/rt-Hz in atmospheric pressure. Measured uncompensated temperature coefficients of gyroscope bias and scale factor were 313 (deg/h)/degC and 351ppm/degC, respectively. Accelerometers on the cube have been characterized, yielding a noise floor of 570μG/√Hz. Sensitivity of the accelerometers is measured at 40mV/G with a bandwidth of 100 Hz.
Boron Nitride in Thermoplastics (for LED Housings)
Authors: Rappelt Thomas , Raman Chandrashekar 
Published: October 2015

Boron nitride (BN) is increasingly being used as a filler in thermoplastics, primarily to increase the thermal conductivity of the resins. Filler-reinforced plastics are being considered to replace traditionally metal parts in a number of markets, with applications such as under-hood automotive parts, sensors and housings for motors, LEDs, and other electronic devices.
When BN powders are used as fillers in resins, the BN-resin composite materials also demonstrate anisotropic properties, largely determined by the orientation of the platy BN crystals in the final part. To overcome this problem of anisotropy, boron nitride powders have been developed which are agglomerates of single crystal. In such agglomerate grades, platy BN crystals are held together to form a larger particle to randomize their orientation. Such BN powder grades, broadly called agglomerate grades, demonstrate more isotropic properties than do single crystal BN grades.
One of the biggest challenges of using agglomerate BN grades is to preserve the structure through all the processing steps. In the case of thermoplastics, the BN agglomerates can break down during the extrusion step and/or the molding step. Both the screw configuration during extrusion and the flow configuration during molding determine the extent of shear of the BN agglomerates.
The thermal conductivity of single crystal platelet and agglomerate boron nitrides in a thermoplastic resin is examined in this paper to consider and explain the effect of particle morphology. The anisotropic properties will be characterized on BN-plastic composite parts. The effect of screw configuration during extrusion and molding conditions on the thermal conductivity and other physical strength properties will also be examined and the trade-offs will be discussed.
3D Passive Integrated Capacitors Towards Even Higher Integration
Authors: Gaborieau Sophie , Bunel Catherine , Murray Franck 
Published: October 2015

IPDIA is involved in Silicon based 3D-IPD advanced technology. This very flexible technology is using standard processing techniques to integrate passive components such as inductors, resistors or capacitors into a silicon substrate.
3D high-density capacitor is at the forefront of IPDIA development program. First process generation with 25nF/mm2 and second generation reaching 80nF/mm2 have been in production for several years. The third generation with multiple metal-insulator-metal (MIM) layer stacks in the pores is reaching 250nF/mm2 and is being qualified now.
Intrinsic low parasitic elements of these capacitors (low ESR and ESL) make it very attractive for DC decoupling and very competitive with the ceramic technology. Assembly can be performed using standard reflow soldering and its low profile also allows PICS capacitor integration in embedded module board technology. Sensors, healthcare and medical applications can benefit from this new development.
To enable even higher integration, development activities are now focused on the third and fourth generation of high-density capacitors targeting ambitious 1μF/mm2.
In this presentation, main characteristics of the PICS high-density capacitors will be described emphasizing on its capability, main applications and advantages versus discrete components. Then, in a second part, challenges raised by the increase of the capacitor density while keeping an acceptable breakdown voltage will be discussed. This includes the integration of high-k materials with adequate electrode and the research for maximizing the 3D silicon surface.
Through Package Defect Localization by Lock-In Thermography
Authors: Schlangen Rudolf , Deslandes Herve , Toda Toru , Nagatomo Toshinobu , Sako Shigeki , Sawaya Hiromichi 
Published: October 2015

Root cause analysis for package defects is currently performed by de-processing the package until such defects can be physically seen. However, many such defects within the package are removed, or are confused with defects created during de-processing itself. 3D X-ray has been used to analyze such physical defects within a packaged device in a non-destructive manner. However, the increasing density and associated shrinkage of components such as multi-layered substrates require significantly higher resolutions, which translates to longer times. High resolution X-ray is impractical when searching for a defect over a wide area due to the time to acquire detailed 3D images (~24 hrs).
Thermal emission analysis has been widely used for localizing defects on ICs. Recent advancement in thermal emission camera technology coupled with lock-in thermography has allowed orders of magnitude better sensitivity ( &lt; 1μW) and improvement in localization resolution (x,y to &lt; 3 um). However, the application of lock-in thermography has been primarily limited to defect localization at the die level [1]. A a highly sensitive MWIR camera combined with a real time lock-in technique demonstrates the capability to localize defects within packaged devices, even through its mold compound. The technique accurately predicts the depth (z) of a thermal defect within the device (&lt; + 5%)
This paper will demonstrate multiple examples of the successful combination of advanced lock-in thermography analysis and high resolution 3D X-ray for totally non-destructive defect location within a packaged device. This initial accurate thermal localization in x, y and z enables the high resolution 3D X-ray system to focus analysis to a few microns so that the defect can be seen quickly (&lt; 1 hr), enabling detection and analysis of previously undetected defects with highest throughput.
3D-TSV Test Options and Process Compatibility
Authors: Smith Ken , Hanaway Peter , Jolley Mike , Gleason Reed , Strid Eric 
Published: October 2015

3D-TSV stacking with non-reworkable bonding processes implies known-good die screening with high test coverage to be economical.Depending upon the stack architecture, the need to contact TSVs directly or TSV bonding pads during wafer test ranges from minimal to mandatory. An example of minimal need to contact is a low-power logic or memory chip powered and tested through a small number of test pads for scan chains or built-in self-test (BIST) signals. Examples of mandatory TSV pad contact during wafer test include power delivery pins (up to thousands), analog or RF I/Os, stacked logic functions, or more complex requirements.With appropriate design, test throughput (and therefore test cost) can dramatically benefit from contacting the many more I/Os available at the TSVs or TSV pads, just as the speed of the stack benefits from the many more I/Os when in mission mode.Probes and probing processes that touch TSVs and thin pads with minimal forces and pad marking are described herein. Feasibility of tip forces ~1 gram or less and very low pad damage are demonstrated at 40 micron array pitch. The lithographically printed probe structures are scalable to even smaller pitches, and fabrication costs scale by probe area, not by pincount.The degree of pad marking from probe tips depends on pad material choices. A non-oxidizing metal surface, such as ENIG, requires &lt;0.1 gm for good contact, thus disturbing the surface so little that marks are difficult to detect. By contrast, a Sn surface requires ~1 gm for low and consistent contact resistance.
Probe contacting at TSV pitches is practical with evolutions of existing probe technology, and enables test strategies which probe some or all of the TSV pads, whether on the face or back of the wafer.
Processing and Reliability Assessment of Silicon Based, Integrated Ultra High Density Substrates
Authors: Lewis Brian J. , Baldwin D. F. , Houston P. N. , Smith B. , Kwok P. , Mueller J. Thompson. A. , Racz L. 
Published: October 2015

High density interconnect (HDI) advances in substrate technology have allowed considerable improvements in processing more complex, compact devices. Chip Scale Packaging (CSP) and multi-chip modules (MCM) have continued to decrease in size and increase in functionality, moving closer to be more like flip chip technology. Improvements in wafer structuring allow for tremendous possibilities for device functionality; however a limit does exists on what traditional substrate fabrication methods will allow. A push in developing through silicon vias (TSVs) and use of alternative materials, other than organic or flex, are needed to enable new packaging technology developments. As needed, an alternative substrate has been developed that uses Silicon-based technology, photo-defined vias and the capability of semiconductor level routing density. It also includes the possibility to open cavities in the substrate to embed integrated die. This technology has opened up many possibilities for fabricating Ultra high density substrates from a US-based supplier that enables the use of integrated die, surface mount processing and fine pitch, multi-die placements.
The following paper details the processing and reliability capabilities of this substrate technology. A comprehensive characterization study was conducted to evaluate the processing of units containing ultra-small SMT devices, intermixed with fine pitch, flip chip die. The units were also processed with traditional BGA balling, making them compatible with level 2, PCB level processes. Data will be shown with the results of the assembly analysis and subsequent reliability assessment of these units, showing a robust performance with thermal shock, uHAST and MSL level testing. A full analysis of the substrates structure will also be shown. The paper will show this technology's possibilities as a next generation substrate alternative.