bluuebunny/crossref_metadata_2025_split huggingface dataset:
Inkjet Printing of Thick-Film Resistors
Authors: Wassmer Marcel , Diel Waldemar , Krueger Klaus 
Published: October 2015

The integration of passive components directly into circuit board is an efficient alternative to surface mounted devices. Inkjet printing is the emerging technology for the deposition of a variety of particles and therefore for digital fabrication of microelectronic circuits. Resistors are one of the most frequently required passive components in electronic circuits. In LTCC-technology the integration and additionally the embedding of resistors promises new applications. Integrated resistors are usually screen printed. Inkjet printing has several advantages to compete seriously with screen printing as production method. This study investigates the possibilities and reliability of inkjet printing of thick-film resistors.
In a first step, different resistive compositions are characterised towards compatibility with a commercial inkjet print head. The reliability and long term stability in drop formation are fundamental for production process. Further on, the interaction between ink and substrate has to be taken into account to reach the desired morphology. In a second step, the advantages of using inkjet for printing resistors are shown. A measure of ink amount is introduced for exact dosing of the ink. Afterwards, compositions with a wide resistivity range are printed with different print heads. The printed resistors are further passed alternatively through a post-fire or through a co-fire process. The effect of variations in particle composition and ink amount are characterized towards the change in electrical behaviour. Further, the influences of printing conditions on morphology and resistivity are discussed.
A Path Toward Non-Destructive 3D Metrology for Through-Silicon Vias
Authors: Gelb Jeff , Kong LayWai , Hunter Luke , Gu Allen , Fong Tiffany , Diebold Alain C. , Lau S. H. , Yun Wenbing 
Published: October 2015

As integrated circuit designs are pushed to tighter dimensions, chip real-estate is becoming of increasing value. Much like the growth of a developing city, a common modern approach is to grow the circuits upwards, building one layer on top of another. In this 3D stacking approach, the common issue lies in how to connect the multiple layers, for which direct connections through the silicon substrates have been found to produce the smallest footprint. These through-silicon vias (TSVs) are currently the subject of heavy research and development (R&D) investigation and their efficiencies are, in part, directly related to the occurrence or absence of voids within the metal structures.
3D x-ray microscopy (XRM) has recently been pushed to unprecedented resolution levels and may fit the inspection needs of the TSV R&D community. Using a unique projection-based micro-CT imaging geometry, entire packages may be inspected with as high as 1 μm resolution. This technique delivers non-destructive metrology of the metal fills as well as the post-etch regions in 3D, without the need for physical cutting or sectioning. By employing x-ray optics, resolution as high as 50 nm is now routinely achievable, allowing the detection of far sub-micron voids within the post-metallization TSV structures. These results may be further analyzed for void sizes and void volume fractions per via. Post-etch samples are also well-visualized using this technique, which allows high-resolution inspection of the side walls as well as measurement of the critical dimensions using the same system as for the post-metallization structures.
Heterogeneous integration – packaging on and in organic substrates
Authors: Becker Karl-F. , Braun T. , Bauer J. , Böttcher L. , Ostmann A. , Pahl B. , Haberland J. , Kallmayer C. , Aschenbrenner R. , Schneider-Ramelow M. , Lang K.-D. 
Published: October 2015

Decreasing the bill of materials for an electronic device saves development time, money and space. The integration of more and more functions not only on the chip (SoC; system on chip) but also in the package (SiP; system in package) is therefore a natural and very important step in the devolvement of micro electronics. Realizing the goal of Ambient Intelligence requires low cost system solutions where all necessary components are integrated. The future will be a combination of “System on Chip”- and “System in Package” solution called as “Heterogeneous Integration”.
As far as technical and economical feasible “System on Chip” solutions will be chosen, the adoption to various applications and the integration of highly complex systems containing non-electronic functions will be carried out more cost efficiently, with a high degree of miniaturization and flexibility in “Heterogeneous Integration”. “Heterogeneous Integration” integrates several chips or components in one package (system in package or SiP) and carries out the interface to the application environment.
This paper will summarize a variety of heterogeneous integration technologies researched at Fraunhofer IZM with a strong focus on embedding in printed circuit boards and embedding in molded reconfigured wafers – looking also on the requirements of sensor packaging. Not only the technological principles but also specific material demands and necessary processes as 3D routing and also 3D interconnection will be discussed in detail. Application examples and technology demonstrators from will be shown to demonstrate technological potential and challenges of miniaturized heterogeneous integration by embedding from a European perspective.
Design and characterization of a biocompatible packaging concept for implantable electronic devices
Authors: Op de Beeck Maaike , Qian Karen , Fiorini Paolo , Malachowski Karl , Van Hoof Chris 
Published: October 2015

A biocompatible packaging process for implantable electronic systems is described, combining biocompatibility and hermeticity with extreme miniaturization. In a first phase of the total packaging sequence, all chips are encapsulated in order to realize a bi-directional diffusion barrier preventing body fluids to leach into the package causing corrosion, and preventing IC materials such as Cu to diffuse into the body, causing various adverse effects. For cost effectiveness, this hermetic chip sealing is performed as post-processing at wafer level, using modifications of standard clean room (CR) fabrication techniques. Well known conductive and insulating CR materials are investigated with respect to their biocompatibility, diffusion barrier properties and sensitivity to corrosion.
In a second phase of the packaging process, all chips of the final device should be electrically connected, applying a biocompatible metallization scheme using eg. gold or platinum. For electrodes being in direct contact with the tissue after implantation, IrOx metallization is proposed.
Device assembly is the final packaging step, during which all system components such as electronics, passives, a battery,… will be interconnected. To provide sufficient mechanical support, all these components are embedded using a biocompatible elastomer such as PDMS.
Mechanical Robustness of Solder Connections to Thick Film Gold
Authors: Marinis Thomas F. , Soucy Joseph W. 
Published: October 2015

Thick film gold metallization is required for many high reliability circuits, especially those subjected to operation in high temperature or high humidity environments. Traditionally, wire bonded bare die are used on these circuits, but there is a trend to replace them with BGA packaged devices. State-of-the-art, chip scale packages increase circuit volume by less than 20 percent, while their use greatly simplifies testing and repair, as compared to wire bonded die.
The use of small, high density I/O pad arrays for attachment of BGA packages, necessitates very careful control of the solder reflow process to avoid excessive leaching of the gold into the solder. Also, unlike passive chip components and leaded devices, the solder filet associated with a solder ball attachment does not distribute mechanical loads over an extended area. Consequently, the stresses imposed on fine pitch, BGA pads are much higher than those imposed by other components. During aging, the gold metallization is converted to gold-tin intermetallic as inter-diffusion proceeds. This further reduces the mechanical integrity of the solder connection. This manifests itself in the observation that when BGA solder balls are subjected to accelerated aging followed by shear testing, the entire solder pad lifts off of the substrate, rather than failing in the solder joint.
What we have done is construct a diffusion based model to estimate the conversion of a thick film gold metallization pad to intermetallic and coupled this result with a finite element analysis to examine the effect of pad size and solder composition on the propensity of a pad to lift off the substrate, when subjected to mechanical or thermal induced loading. We are designing experiments to compare the predictions of our model to experimental results obtained from shearing solder balls, of different compositions and sizes, attached to substrates metalized with several different solderable, thick film gold materials.
Thermal and Mechanical Characterization of High Power GaN Packages
Authors: Willis Don , Gu Gary , Jin Daniel , Dry Rob 
Published: October 2015

The typical package available for high power GaN application has the devices directly attached onto a metal flange, which could contribute significantly to the overall thermal resistance. This paper discusses an alternative approach to packaging both single and multiple devices through a heat spreader, which could potentially improve thermal performance and bring significant benefits to assembly in yields and cost. However, the heat spreader could also introduce significant CTE mis-match and potential concerns in reliability.
Nonlinear 3D finite element analysis (FEA) was conducted to characterize the thermal performance and evaluate mechanical/reliability concerns. Thermal modeling considered single and multiple die applications, and the results show13–15% thermal improvement with the copper heat spreader. Mechanical analysis focused on the thermal loads of the die attach and solder reflow processes. It reveals that the die attach process is more critical as shown in the higher stress due to higher thermal load, but stress/strain levels appear to be acceptable. Thus, this alternative approach could be a viable solution.
ASSESSMENT AND CHARACTERIZATION OF STRESS INDUCED BY VIA-FIRST TSV TECHNOLOGY
Authors: Parès G. , De Crecy F. , Moreau S. , Maurice C. , Borbely A , Mazuir J. , Chapelon L.L. , Sillon N. 
Published: October 2015

Through Silicon Via (TSV) is a key enabling technology for 3D stacking. One of the main concerns regarding the TSV introduction inside the IC fabrication is the resulting stress build up in the silicon substrate that may induce warpage or expansion at the wafer level, strain and crystalline defects in the neighboring silicon of the TSV and finally can impact performances and reliability of the CMOS devices as well. Polysilicon, tungsten and copper are the three main conductors that are nowadays considered for the TSV fabrication. In a first part of this paper the different factors that contribute to the stress in these tree TSV types including the geometry, the materials and the process will be reviewed.
After bonding on a temporary carrier and thinning of the substrate to expose the via the stress built up during the fabrication of the TSV can be also revealed by the expansion of the silicon membrane.
Thermo-mechanical FEM simulations will be equally introduced and confronted to the experimental findings.
We also present some characterizations of silicon defects by chemical revelation around the TSV structures.
For characterization of the stress in TSV structures scale different techniques as EBSD, μRaman, XRD will be then presented.
Finally we conclude that with the optimization of some key processing steps, the stress induced in via-first technology may be acceptable for IC integration.
Topography and Deformation Measurement as a new Tool for Thermal Stress Assessment on Electronics Components
Authors: Hertl Michael 
Published: October 2015

Requirements on electronics components are more and more demanding and extremely variable: the Automotive industry typically requires “zero defect” quality, which in practice means failure rates in the ppb range. Speed and energy critical applications are the drivers for the development of 3D die stacks and PoP designs, with the particularity that these components are facing at least 2 reflow solder cycles up to 260°C instead of only one. MEMS solutions typically include a cavity, with the specific demand for minimum component warpage during production in order not to damage the cavity.
Recently, Topography and Deformation Measurement (TDM) has been developed as a novel tool for the reliability analysis on package designs in the early development phase. It can be used to optimize the warpage behaviour of any new component under any kind of realistic thermal stress condition like for example reflow solder conditions, expected product life cycle thermal conditions, or accelerated aging test conditions.
The present paper will deal with four case studies: In the first, TDM is used to minimize the maximum warpage of a MEMS component’s package during reflow. In the second case study we will highlight the stress interaction between a component and a PCB, by analyzing the topography vs. temperature characteristics of the component before and after soldering it onto the PCB. In the third, the solderability of a small package which is strongly warped at room temperature will be studied. Finally, the In-Plane deformation behaviour of a PCB and a component will be compared in order to identify potential reliability issues due to CTE (coefficient of thermal expansion) mismatch between component and PCB.
A First Room Temperature Stable and Jetable Solder Joint Encapsulant Adhesive
Authors: Liu Mary , Yin Wusheng 
Published: October 2015

With the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, YINCAE has published a white paper on a first individual solder joint encapsulant which can eliminate underfilling process with at least five times solder joint increase and provide more flexibility for fine pitch and high density application. In order to meet the demand of manufacturing of high speed and low cost, YINCAE has invented a room temperature stable and jettable solder joint encapsulant adhesive – SMT 266. The invention of SMT 266 has allowed our customers to have more flexibility in their high-speed production line such as worry free on the work life of adhesive and workable jetting process.
After being used in the customer field for a few years, the implementation of SMT266 has been approved improving the process yield, eliminating voids and cracks in solder joint, eliminating head-in-pillow issue for large component during lead free reflow process. The results from thermal cycling test indicated that the first failure cycles using SMT266 is high up to 6000 cycles, at least 4000 – 5000 cycles higher than other processes. The pull strength is 1.5 times higher than using solder paste plus underfilling process. All reliability data implied encapsulating each individual solder joint is the right direction to move toward. The enforcement mechanism will be discussed in our paper.
Why Wedge Bond?
Authors: Bubel Joe , Levine Lee 
Published: October 2015

Wedge bonding has the potential to emerge as a driving technology for bonding fine-pitch devices. The deformation (width) of a full strength wedge bond is typically 33% smaller than the smallest diameter ball bond of the same wire diameter. As we move to finer pad pitches which necessitates smaller bond pads (as predicted by the ITRS Roadmap) the diameter of smaller diameter bonding wire presents a roadblock. Smaller diameter wire has significantly lower conductivity (current carrying capacity). Wedge bonding allows use of a larger wire diameter than ball bonding for the same pad size providing higher current for the package.
New looping capabilities, higher bonding speed (productivity) and quality assurance tools (Process Integrated Quality Control™) provide high-reliability interconnection solutions for advanced military, aerospace, medical and optoelectronic packages.
High Thermal-Transient Packaging for a SiC-Based Solid State Circuit Breaker
Authors: Baltis Theodore , Hopkins Douglas C , Pitaressi James M , Hazelmyer Donald R 
Published: October 2015

Solid-State Circuit Breakers (SSCBs), or Contactors, are critical components in next generation electric aircraft, and must be small in size, fast in response, and have high reliability. Silicon Carbide (SiC) semiconductor switches provide a series of improvements over traditional silicon-based breakers in both electrical and thermal performances. The reported SSCB uses SiC MOSFETs mounted on cast-aluminum traces, cast onto an aluminum nitride (AlN) ceramic co-captured in an aluminum composite baseplate. The system is similar to an AlSiC and Direct-Bonded-Aluminum (DBA) approach.
This presentation details the transient thermal characterizations of an SSCB having the highest density in development. Previous work focused on a 30A SSCB that was constructed and tested to show a 300A, 500ns circuit breaking capability. The high density comes from allowing the SiC junctions to pulse to ∼350°C (in 5ms) from a 105°C ambient baseplate. The 30A/300A module was reported in IMAPS HiTEC’10 “Development of a SiC SSPC Module with Advanced High Temperature Packaging,” This paper builds on that paper adding the mechanical results and all new data on the larger, high energy density module with larger die. The objective of the presentation is to introduce (or update) the use of cast composite metal-ceramic structures for high thermal transient applications and document the mechanical stress/strain performance through simulations. The module is in development for military applications and has not been field-tested. This is also developed for Smart-Grid applications in local distribution systems.
Mix of analog and digital circuitry analysis in a noisy environment
Authors: Tournier Hugues , Hu Kaisheng , Deng Shuhui 
Published: October 2015

High transient current from a digital circuitry, fast di/dt, within an analog circuitry co-existence is very demanding. Analysis of the diverse potential noise coupling path, and suggested solutions, is required to guarantee proper functionality and performances of both circuitries. Our noise analysis includes the die, package and PCB power supply and decoupling strategy. This analysis takes into consideration the efficiency of the power delivery Network, PDN, at a Macro and Micro environment.
The analysis is using 3D Simulations techniques based on causal model. With this novel technique, we investigate the potential noise induction through the ground path and isolation. For the conclusion, we suggest a method that improve the PI analysis over a mix signal IC..
BGA Solder Life Prediction under Combined Power and Temperature Cycling Condition
Authors: Chai Fei , Osterman Michael , Pecht Michael 
Published: October 2015

Solder interconnect failure is a known life limiting failure mechanism that is induced by cyclic temperature excursions. Thermal fatigue reliability of solder interconnects is conventionally assessed by simple temperature cycling test, which applies a constant temperature range, fixed dwell times and ramp rates during the test. However, due to the user controlled power cycles, non-constant workloads, and changes in the surrounding environment, electronics in the field often experience a complex combination of temperature and power cycling.
In this study, the effect of power cycling superposed on a simple temperature cycling is experimentally examined. Furthermore, a scheme for modeling the solder interconnect fatigue life of Plastic Ball Grid Array (PBGA) parts under the concurrent power and temperature cycling. Damage, defined as the number of applied cycles over the number of survivable cycles, from the simple temperature cycle and the power cycle are linearly added using Miner's rule, and compared with the concurrent temperature and power cycling test. Cycles to failure of each condition is derived by life testing conducted on Plastic Ball Grid Array (PBGA) assembled with eutectic and SAC305 solder.
Understanding and Controlling Cu Protrusions in 3D TSV Processing
Authors: Kruger Seth , Hummler Klaus , Geer Robert , Dunn Kathleen , McDonough Colin , Cordes Aaron , Enloe Jack , Sapp Brian , Ali Iqbal , Pieper Stefan , Arkalgud Sitaram , Murray Thomas 
Published: October 2015

Cu-filled through-silicon vias (TSVs) are an essential building block of 3D and 2.5D integrated chips. In the TSV-mid processing flow, which has emerged as an industry mainstream, one or more on-chip wiring levels are formed after the TSV Cu fill is completed, which exposes the fill to peak temperatures of up to 400 °C. Due to the higher coefficient of thermal expansion (CTE) of Cu than the surrounding silicon and dielectrics, the TSV fill protrudes above the level previously defined by the TSV chemical mechanical polishing (CMP) step. Even after returning to room temperature, the top of the TSV will not occupy the same space due to plastic deformation during the thermal treatment. This phenomenon is known as Cu protrusions, pumping, or popping. Excessive amounts of Cu protrusion present a risk to yields and reliability because the expansion can damage dielectrics and wiring above or adjacent to the TSVs.
In this study, we report the underlying mechanisms as well as process remedies for Cu protrusions. The SEMATECH 5 um × 50 um TSV process and learning vehicle is used to conduct process split experiments comparing various plating chemistries, plating recipes, and post-plating anneal conditions. Stresses in the surrounding silicon are studied by micro-Raman, and a distinct signature distinguishing good from bad Cu protrusion behavior is identified. Cu material properties such as contamination, grain size, grain orientation, and strain may also influence the protrusion behavior; these factors are studied by micro-secondary ion mass spectroscopy (SIMS) and electron backscatter spectroscopy (EBSD). Our results shows that the choice of plating chemistry and subsequent optimized post-plating anneal are the main factors in suppressing Cu protrusions. Our best known method is able to reduce Cu protrusions to about 15 nm after typical thermal loads.
An Overview - Temporary Wafer Bonding / Debonding for 2.5D and 3D Technologies
Authors: Chanchani Rajen 
Published: October 2015

In recent years, material suppliers in collaboration with equipment suppliers have developed many new materials/process options for temporary bonding and debonding to be used in 2.5D and 3D technologies. . These options are still being evaluated and at best they are in prototype stage. As a result, the cost is still perceived to be high, there are no reliability data available and many new users in the market are confused about which option and corresponding equipment set should they invest in. I will present the requirements for ideal temporary bonding debonding solution, describe the available technology options for temporary bonding and debonding and their status.
The primary technologies for temporary bonding are adhesive-based. These adhesives are tailored so the adhesive bonds can be broken either by laser ablation, thermal-slide, ZoneBond process, solvent release or mechanical peel-off. It appears that a single solution will not be applicable to all different 2.5D/3D technologies that are being developed and thus, multiple options will be the forerunners.