bluuebunny/crossref_metadata_2025_split huggingface dataset:
ChipletT, A Cost-Effective, High Reliability, Embedded Die Fan-Out Package Based on Multilayer Flex Laminate with Enhanced Thermal Performance
Authors: Sivaswamy Senthil , Tessier Theodore (Ted) G. , Curtis Tony , Clark David , Itoi Kazuhisa , Okamoto Masahiro , Sano Yoshinori , Ueta Nobuyuki , Okude Satoshi , Nakao Osamu 
Published: October 2015

Fan-Out Wafer Level Packaging (FO-WLP) technology has been developed in recent years to overcome the limitations of Fan-in WLP (FI-WLP) packages and to add more functionality to WLP. Fan-Out packages expand the WLP market to higher pin count devices and add multiple die System in Package (SiP) capability. In this paper, a novel approach to low cost fan-out packaging based on polyimide flex circuits and wafer level Embedded Die Customization (EDC) is discussed.
ChipletT refers to Fan-Out packaging. ChipsetT refers to System in Package developed with WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multi layer polyimide flex wiring and conductive z-axis sintered metal interconnections. Using WABE technology, ultra thin fan-out packages (0.4mm) can be fabricated with lower processing costs, higher throughput and with 3D extendibility. Embedded Die Customization is performed at the wafer level and involves optimization of the die-to-embedding process by using optimized wafer level processing capabilities including polymer processing, copper plating and wafer thinning.
Reliability of the ChipletT packages, both component level and board level is evaluated. ChipletT packages show high reliability in component level testing and board level testing (Thermal Cycling and Drop Testing). The thermal performance of ChipletT packages were also evaluated in this study. Thermal resistance parameters θja and θjc were simulated with and without thermal vias for both face up and face down configurations. ChipletT provides a new low cost fan out packaging option with proven component level and board level reliability performance.
High Density Attachment of HB-LED Die to Heat Sink Surfaces Using Aerosol Jet Printing
Authors: Christenson Kurt K. , Renn Michael J. , Paulsen Jason A. , Bourassa Justin J. , McDonald Kelley M. 
Published: October 2015

High LED junction temperature leads to reduced LED output and color shift, and are a factor in most LED failure mechanisms. Every interface and layer of packaging between the junction and the heat sink increases the device operating temperature necessitating more aggressive heat sink design. Packaging also increases the footprint of the device, limiting packing density. The ideal design would have the bare LED die attached directly to the heat sink with a micron-scale bond of thermally conductive adhesive. This paper discusses the use of an Aerosol Jet ® system to create micron-scale bonds of adhesives for both top and bottom-side (flip-chip style) connections. The system is also used to write topside connections, replacing wire bonding.
In order to limit the temperatures of LED junctions with power densities of 250 W/cm2 to below 100 °C, it is necessary to limit the thermal resistance of a direct die-heat sink bond for a 0.4 W, 0.16 mm2 die to approximately 100 C/W. Assuming 50% coverage, this implies a thickness of approximately 1.5 um for an unfilled adhesive (K=0.2) or 40 um for a filled adhesive (K=5). For a 0.16 mm2 die this requires an adhesive volume of 65 pl and 1600 pl respectively, far below the 17,000 pl in the 8 mil hemisphere from a syringe dispense. Aerosol Jet systems are able to produce patterned deposits with total volumes in the 100 pl range. This paper will describe the results of work with top and bottom-side attachment of 450 nm InGaN LED die to thermally conductive substrates.
Hybrid Bonding Methods Using Ultra Precision Cutting for 3D-SIC
Authors: Sakai Taiji , Imaizumi Nobuhiro , Mizukoshi Masataka , Kawase Masayuki , Tanimoto Ryoji , Mori Takashi , Takeda Kohei , Enami Toshio 
Published: October 2015

We have developed Cu-Cu/adhesives hybrid bonding technique by using collective cutting of Cu bumps and adhesives in order to achieve high density 3D-SIC. It is considered that progression of fine pitch interconnection leads to lower height of bonding electrodes, resulting in narrow gap between 3D-SICs. Therefore, it is difficult to fill in adhesive to such a narrow gap 3D-SICs after bonding, so we consider that hybrid bonding of pre-applied adhesives and Cu-Cu thermocompression bonding must be advantageous, in terms of void less bonding and minimizing bonding stress by adhesives and also low electricity by Cu-Cu solid diffusion bonding.
In the present study, we adapted the following process; at first adhesives were spin coated on the wafer with Cu post and then pre-baked. After that, pre-applied adhesives and Cu bumps were successfully cut by single crystal diamond bite. Typical adhesives may cause bite damage with continuous cutting, but in this research, we selected low damage adhesive against continuous cutting, which is important properties to commercial uses. Then, chips with adhesives were attached to substrates and Cu oxidation layer was removed by exposing formic acid atmosphere. Finally permanent bonding was done at 225 degree C for 30 minutes. We concluded that solid diffusion between bonded Cu bumps could be achieved and no adhesive residue could be seen between bonded interfaces by TEM/EDX analysis.
Room Temperature Debonding - An Enabling Technology for TSV and 3D Integration
Authors: Matthias Thorsten , Pabo Eric , Burggraf Juergen , Burgstaller Daniel , Wimplinger Markus , Lindner Paul 
Published: October 2015

Thin wafer processing is a critical technology for TSV manufacturing and 3D integration. Thin wafer processing allows to reduce the aspect ratio of the vias, thereby reducing the total processing cost and enables ultra-thin packages for handheld applications. Temporary bonding to a rigid support carrier and debonding after backside processing have been used for thin wafer handling/processing for many years. However, so far all the debonding methods imposed severe limitations on the manufacturability. For light induced debonding the carrier had to be transparent and for solvent based debonding the carrier had to be perforated. For thermally induced debonding, “slide-off debonding” the debonding temperature had to be below the reflow temperature of the solder bumps, which limited the maximal process temperature of the adhesive.
In this paper we describe a new debonding method at room temperature. This new technology decouples the debonding process from the adhesive properties, which creates a de facto material independent debonding standard. As the debonding process does not rely on the adhesive properties a major boundary for adhesive engineering has been removed. The debonding method is compatible with bumps or pillars in the bond interface as well as on the backside of the wafer stack. No force is applied on the bumps during debonding which results in very high yields.
Laddered-UBM Structure: Bump Reliability Improvement through Distribution of Load Concentration Points
Authors: Topacio Roden 
Published: October 2015

Flip-chip mounting schemes have been used for decades to mount semiconductor chips to substrates. In flip-chip process, a solder bump is metallurgically bonded to the under-bump-metallurgy, also known as UBM, on a given pad of the semiconductor chip and a pre-solder is metallurgically bonded to a corresponding pad of the substrate. Thereafter the solder bump and the pre-solder are brought into proximity and metallurgically bonded using reflow.
Flip-chip solder joints are subjected to mechanical stresses from a variety of sources, such as coefficient of thermal expansion mismatches, ductility differences and circuit board warping. Such stresses can subject the conventional UBM structure to bending moments specially during the flip-chip reflow solder solidification stage where the bump is still unprotected by the underfill. The effect is somewhat directional in that the stresses tend to be greatest nearer the die edges and corners and fall off with increasing proximity to the die center. The bending moments associated with this so-called edge effect can impose stresses on the dielectric film beneath the UBM structure that, if large enough, can produce fracture.
This paper will discuss the load distribution on a conventional UBM structure due to the bending moments and how the Laddered-UBM structure attempts to overcome or reduce the effects of these bending moments. Contrary to conventional methods where stress concentration points are eliminated, the Laddered-UBM is designed to strategically increase the number of load concentration points along the UBM structure. With the increased number of load concentration points, the stress along the UBM is distributed more evenly which effectively reduces the stress at any given point thus preventing a single large enough stress to cause dielectric fracture. Theoretical analysis and experimental data including reliability results on both the conventional UBM structure and the Laddered-UBM structure will be presented and discussed in this paper.
Post-Packaged Measurement of MEMS Gap, Displacement, Force, Stiffness, Mass, Damping, and Quality Factor
Authors: Clark Jason Vaughn 
Published: October 2015

What is presented: We present a practical MEMS metrology technology that can be used to extract system stiffness, mass, damping, and excitation force after a MEMS is packaged. Presently the technology applies to planar MEMS with comb drives. Our method is quick, accurate, and precise.
Why important: Our technology will likely be important for manufacture, accuracy, and controllability. During manufacture, MEMS metrology can be 30% to 40% of the cost. This high cost is due to factory testing tools that are impractical and not optimized for batch fabrication. The tools often apply an external disturbance that the MEMS are electronically tuned to. Accuracy is a critical problem area in MEMS. Often MEMS are more sensitive and precise than the tools used to calibrate them. And there are no ASTM standards in MEMS for measuring stiffness, mass, damping, and force. Since there is a lack of standards, high cost in metrology, and low return on measurement due to large uncertainties, it has been difficult for manufacturers and their customers to agree on calibration technologies. Moreover, calibration in controlled laboratory conditions may not be consistent with conduction due to harsh environmental changes or long-term dormancy. Conventional calibration methods often treat MEMS as a black box, where numerous parameters remain uncharacterized. Without complete characterization, a complete understanding of what is being sensed is unlikely. However, by measuring the stiffness, mass, damping, and excitation forces on-chip, MEMS can become self-calibrating and offer more complete analysis of what is being sensed.
What is different: Our method consists of using on-chip or off-the-shelf electronics to measure changes in capacitance to measure geometry, displacement, stiffness, and comb drive force. Upon measuring stiffness, mass is determined by velocity resonant frequency. The benefit of using changes in capacitance is that our technology is independent of meter accuracy; that is, it is the precision of the meter that matters. E.g. Zeptofarad precision has been realized by a few groups. Such an independence from absolute measurements allows our technology to be repeatable between different laboratories, where parasitics will likely differ.
Results: We validate our electro-metrology technology for geometry, displacement, stiffness, and force. Our results of geometry compares favorably against geometry measured by a scanning electron microscope by 2 orders of magnitude. We validate displacement by measuring the distance traveled between a pair fabricated displacement stops. Stiffness and force are simi-validated by applying an identical (but unknown) AFM-cantilever force to two different MEMS which are each calibrated using our method. Although such a method does not directly provide a traceable measurement of force, it does imply the possibility of developing a standard of measure because the same value of force is obtained across different devices.
Cost Drivers for 2.5D and 3D Applications
Authors: Palesko Chet , Vardaman E. Jan , Palesko Alan 
Published: October 2015

2.5D and 3D applications using through silicon vias (TSVs) are increasingly being considered as a packaging alternative. Miniaturization and high performance product requirements are driving this move – even though in many cases the cost of both 2.5D and 3D is still high.
The primary applications for 2.5D interposers with TSVs are GPUs/CPUs, high-end ASICs, and FPGAs. Adoption for FPGAs has already started. The key to the performance gains in recently introduced FPGAs is the partitioning of an FPGA die into four “slices” that are mounted on a silicon interposer or what Xilinx calls its Stacked Silicon Interconnect technology. Applications for interposers include tablets, gaming, and high-end computing and network systems. The drivers are mainly partitioning large die, integrating single chips into a module, reducing die size where substrate density is the constraint, and using the interposer to minimize the stress on large die that are fabricated with extra-low-k (ELK) dielectrics.
The primary applications for 3D solutions are stacked memory cubes and memory plus logic. The true 3D nature of stacking all active silicon allows better miniaturization, but yield issues can quickly drive the cost unacceptably high.
This analysis examines the cost drivers for 2.5D and 3D applications. Activity based cost models will be used to analyze the complete cost of fabricating and assembling active die on a silicon interposer and active die stacking on other active die. Total product cost impact - not just the cost of a specific activity - is the focus of this analysis. Since yields play a major role in cost, a sensitivity analysis of the different yields including die yield before wafer probe, die yield after wafer probe, TSV yield, interposer yield, assembly yield, substrate yield, etc. will be presented. The critical yield points in the manufacturing flow and dominant activity cost drivers (equipment, material, and /or labor) will be presented as well as suggested minimum thresholds for 2.5D and 3D technology to be a cost effective technology.
Reliability of die to wafer bonding using copper-tin interconnections
Authors: Garnier Arnaud , Franiatte Rémi , Bouchu David , Anciant Romain , Chéramy Séverine 
Published: October 2015

One major step for 3D integration is the die stacking which has to meet mechanical and electrical requirements. Transient Liquid Phase bonding is studied because it is suitable with high interconnection density and also multiple stacking.
For this study, top and bottom wafers including redistribution layers were electroplated with CuSn and Cu respectively. Die to wafer bonding was carried out at 250 °C in neutral atmosphere. Capillary underfill was added in some cases to check its influence.
Interconnections quality was then assessed. Electrical tests were carried out using daisy chains. Shear tests enabled to check mechanical strength and failure location. Finally, cross sectional scanning electron microscopy and energy dispersive X-ray spectrometry allowed identifying metallurgical phases and potential defects. These characterizations were achieved before and after aging. This aging consisted either in thermal cycle test (TCT: 500 cycles between −40 °C and 125 °C with 10min soak time) or high temperature storage (HTS) applying the same thermal budget as during the TCT.
After assembling, interconnections have very good electrical and mechanical properties. Their degradations are measured after TCT but they are larger than after HTS. This reveals failure mechanisms is not only based on chemical aging but also involve thermomechanical stress. This last feature has been limited thanks to underfill addition. Its effect was investigated through TCT where electrical yield drop was lower than when the gap between the die and the wafer is not filled.
Moreover, SEM images reveal different kinds and densities of voids. Kirkendall voids are located at the Cu/Cu3Sn interface. Smaller voids are visible at the initial bonding interface in the case of CuSn to Cu bonding. After aging, some cracks develop mainly through Kirkendall voids which therefore seem to be the most detrimental defects to overcome.
Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages
Authors: Bhopte Siddharth , Galloway Jesse , Park Kyung-Rok , Park Hyun-Jin , Choi Jeong-Han , Yu Ho-Beob , Yang Sung-Hwan 
Published: October 2015

Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being primary drivers for devices like smart-phones and tablets. Today solder interconnect pitches, for both low-end and high-end flip chip applications, approximately range from 200μm to 90μm in area array. Advanced silicon nodes create challenges to fine pitch flip chip interconnects and corresponding substrate technology.
Fine pitch (&lt;60μm pitch) flip chip (FPFC) packaging is an emerging technology that meets the demand for both smaller form factors and lower cost products. Copper pillar bumps are best suited for fine pitch applications because they allow low standoff height and robust package reliability. Previous feasibility studies show that thermo-compression bonding process with non-conductive paste (NCP) is well suited for manufacturing copper pillar based FPFC packages because the NCP paste encapsulates the bumps and protects the vulnerable die interconnects.
TCNCP process can be described as (1) NCP paste is pre-dispensed on a substrate (2) bumped die is picked up by the heater tool (3) proper heating profile and compression load is applied and (4) heater tool detaches and die is allowed to cool. This process requires precise control of temperature and force to get robust flip chip interconnect shape and void-free NCP coverage.
TCNCP process has very small heating times usually ranging between 2 to 4 seconds per die. Within such short time, the heater temperature is quickly ramped up to 3 times its initial temperature to melt the solder at the tip of the copper bumps and cure the NCP. Small package layers make it very difficult for the heat to spread quickly. Therefore any temperature gradients within the heater are propagated into the die. Large temperature gradients within the die can potentially introduce manufacturing related challenges like solder “non-wet” and “de-wet”. In this paper these issues are briefly discussed. An experimentally validated thermal model is presented to develop an understanding of rapid heat flow patterns during a typical TCNCP process. Detailed parametric computational study is performed on different die sizes, heating temperature and time to propose a broad guideline on achieving optimal temperature distribution during the TCNCP process.
Sealing dispensing requirements to meet MEMS packaging and throughput impact
Authors: Park Heakyoung 
Published: October 2015

The MEMS industry has gained big momentum recently with significant unit growth, especially in the consumer market. While traditional MEMS devices like automotive accelerators have established high-volume manufacturing processes and packages with high reliability, most MEMS devices have been fragmented in packaging because of their unique requirements and small volumes, resulting in high packaging costs. In the cost-sensitive consumer market, devices such as MEMS microphones, accelerometers, and gyroscopes in mobile devices have rapidly increased their production volume and chased lower packaging cost while accepting relatively less reliability than traditional devices.
Sealing dispensing can be applied to device or cap wafer for wafer capping process. Wafer capping protects active MEMS from dicing process after release because the additional cavity wafer with sealing covers the MEMS structure. There are manufacturing challenges because wafer capping requires precise alignment and a variety of bonding methods have technical drawbacks. Printing is one way to deposit sealing lines to cap wafers, but consumes a relatively wide area and may not work if the sealing line must go onto the MEMS die wafer. Sealing line can also be applied to organic substrate that contains MEMS device and ASIC and then lid is attached for bonding in cavity packages.
Previous paper covered technical requirements for dispensing sealant, volumetric accuracy, and motion systems to meet packaging trends and addressed manufacturing cost reductions. This paper will include investigating the impact on the throughput model due to size reduction efforts in packaging. More dies can be produced per given wafer size, which means there is more dispensing area per wafer. In addition, sealing line requirements will be more challenging, and so this paper will address these demands.
Assembly Challenges for 2.5D Packages
Authors: Kelly Michael G , Mattei Marnie , Reed Rick 
Published: October 2015

Interposers provide a crucial intermediate step for next generation products to allow side-by-side integration of technology optimized. The interposer size in most cases is greater than 22mm on a side and in some designs exceeds 30mm. This large size combined with a thickness of ≤ 100 microns may result in high warpage which can significantly impact the assembly process. Materials and process selection become a key consideration to create a high yielding, multi-die stacked product.
This presentation will outline the challenges of a large 2.5D TSV product and how assembly strategies have been used to accommodate these challenges. Different process options and die attach sequences for interposer to substrate and chips to interposer will be discussed and critically differentiated. The assembly methods for attaching multiple die with tens of thousands of I/O at 40 micron fine pitch will be compared in relation to the die size and interposer warpage. Product design requirements may also dictate that the optimum assembly approach is achieved by combining methods such as mass reflow and TCNCP bonding for die attach and underfill. Test considerations at intermediate assembly steps will also be reviewed for feasibility in the overall process flow.