bluuebunny/crossref_metadata_2025_split huggingface dataset:
Versatile Lead-Free Solder Electroplating Products for Advanced Bumping Technologies
Authors: Lee Inho , Cho Regina , Grippo Lou , Taylor Yen-Lin , Baldelli Wayne , Farrell Ryan , Woertink Julia , Qin Yi , Prange Jonathan , Lee Yil-Hak , Imanari Masaaki , Dong Jianwei , Calvert Jeff 
Published: October 2015

Lead-free SnAg solder bumps deposited by electroplating are used extensively in high volume production lines for a number of new bumping technologies including C4 bumps, Cu pillars capped with SnAg solder and 3D microbumps. New bumping technologies present their challenging requirements such as tightly controlled thickness uniformity, alloy composition uniformity and avoidance of reflow voids to create high yields and low defects. To meet these requirements, SnAg plating chemistry must deliver strong performance over a wide range of applications.
Traditional device manufacturers, wafer foundry companies and Outsourced Assembly and Test (OSAT) companies are manufacturing a number of different types of bumped wafers in their production lines; a diverse range of die design and pattern densities, thin and thick resist film wafers, mushroom and in-via plating, and wide range of plating rate. The variety and complexity of bumping wafers have challenged SnAg plating chemistries to meet tight requirements in terms of running cost saving and high production yield. Hence, development of versatile and robust chemistries for electroplating is critical to overcome these challenges
In view of all these challenges and unmet needs in the market, Dow focused its efforts on developing a brand-new additive system for SnAg plating. On the one hand, we tapped into our know-how on solder plating to establish correlations between various types of end-user requirements and experiences to fundamental electrochemistry response. On the other hand, 300mm in-house plating and process tools are leveraged to speed up the feedback process and provide pilot run data. At the end, this highly iterative approach enabled us to optimize the performance of the chemistry without sacrifice on design space.
In this paper, we will discuss next generation of SnAg electroplating products capable of achieving versatile performance requirements over a wide range of applications. The bump height WID co-planarity% ((hmax-hmin)/2havg ×100) was achieved less than ±5% over the wide range of current density from 4 ASD to 12 ASD. Smooth surface morphology, narrow Ag alloy composition distribution less than ±0.2% across the 300mm wafers, and reflow void free were observed. An optimized formulation of the next generation SnAg products was successfully demonstrated plating capability on various bumping technologies such as C4 bumping, Cu pillars capped SnAg solders and micro bumps meeting plating requirements.
Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging
Authors: Tatsumi Koji , Mineo Kyouhei , Hatta Takeshi , Katase Takuma , Ishikawa Masayuki , Masuda Akihiro 
Published: October 2015

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation.
We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary.
This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed.
With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming.
In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes.
We'd like to present our updates on controlling bump morphology for various applications.
Use of Darkfield Laser Technology in Monitoring Particles Generated by Process Tools in Cu Pillar Bumping & Wafer Edge Inspection
Authors: Asgari Reza 
Published: October 2015

In recent years, the semiconductor industry has witnessed an increasingly fast adoption rate of Cu pillar bumps for a variety of devices including memory, logic, processors, and FPGA. Cu pillar bumps provide several advantages over their counterparts, among which are tighter pitch, large number of I/Os as well as better heat dissipation. Due to the constant drive for miniaturization, the size and pitch of these bumps are getting smaller and smaller. As the sizes shrink, the need to minimize size and number of particles generated by the process tools increases. Unwanted particles generated by tools such as sputtering or etch can create killer defects driving down yields.
The purpose of this paper is to examine how a darkfield laser technique can be used to monitor process tools for the amount of particles they generate. Determination of excessive particle density could trigger a chamber clean. After the chamber is cleaned, particle density needs to be re-characterized before releasing tool into production. Figure 1 shows the working principal of this sensor and figure two shows an example of maps generated by the inspection tool. Particle and haze data generated on a monitor wafer allows engineers to maintain process tools at optimal cleaning levels.
SiP Technology for Wireless Module Miniaturization
Authors: Kuo Benny 
Published: October 2015

SiP (System in package) module provide a integrate functions, smaller and thinner package solution on electronic portable devices. For the wireless application, the advanced AoP (Antenna on package) and compartment shielding has been proposed and developed by Advanced Semiconductor Engineering (ASE), Inc. to be the next request for complex application and miniaturization solution. For AoP package, more focus on near field/wireless connection to have specific metal antenna design and attached on package surface to achieve SiP module miniaturization and perform required antenna efficiency on low frequency application. Advanced compartment shielding provide the simple method on function isolation area to prevent the electromagnetic noise interference (EMI) and high level of total radiated EMI from system product due to more complex package performance.
The major benefit of novel AoP package is transfer the antenna designed on PCB to directly attached on package to reduce the PCB X/Y dimension but still keep antenna efficiency performance. The fabrication of AoP consists of following factors: 1) special substrate design to have antenna connection pads; 2) specific 3D metal frame design for antenna; 3) antenna frame attachment and over mold for package. Following these processes, AoP provide a simple process on package assembly and smaller dimension of package.
For compartment shielding development in ASE, previously we design a metal can on module package to reduce EMI but induce a thickness increase. The novel compartment shielding more focus on shielding frame design inside the package to achieve simple process flow and good shielding performance, their fabrication consists the following factors: 1) specific tooth-type frame design to have shielding function for different zone in package and provide suitable slot width/pitch ratio for mold flow; 2) adhesion material for metal frame attached on substrate ; 3) over mold and laser trenching; 4) conductive material sputtering on package surface. This novel compartment shielding solution provides a simplified shielding and more reliable process on SiP module package.
Wireless module was designed RF/power/Switch/Bluetooth function inside the package, the high density of electrical function is usually designed in the portable devices with small/thinner size. Advanced AoP or compartment shielding technology provides more competitive solution on SiP module miniaturization. In the paper, we will present the design for AoP and compartment shielding, process characterization and measurement of antenna and shielding performance of module to present the advantage of SiP modules with this technology application.
Electroplating with Dielectric Bridges
Authors: Stout Gene , Scott Doug , Curtis Anthony , Burgess Guy , Tessier Theodore G. 
Published: October 2015

The electroplating of underlying metal redistribution layers, under-bump metallization (UBM) layers, WLCSP, Cu pillar and other flip chip applications is well established in the semiconductor industry. The use of semi-additive plating can sometimes be adversely affected by the absence of plating occurring in all targeted locations or with plating non-uniformity as a result of front-end fab related structural anomalies.
Subsequent analysis has routinely determined that the previously deposited metal seed layer had been discontinuous due to the topography of wafer features. The most predominant types of topographical issues causing discontinuity in the seed layer are related to adverse sidewall profiles of an underlying dielectric layer or an edge of die feature. Typically die streets are kept clear of certain dielectric layers to avoid complications from saw tool wear and residual defects. As such, these particular dielectric layers are usually terminated at or near each die edge on a semiconductor wafer during processing. Introducing dielectric bridges over the dicing streets provides additional assurances an alternative means to significantly improve the ability to uniformly plate on all targeted die by creating an electrically continuous seed layer pathway while still allowing for subsequent wafer dicing with minimal blade wear, die chipping or residual dielectric issues. FCI has developed and successfully uses this patent pending method to insure the uniform electroplating of metallization layers for a wide variety of applications.
This paper will highlight the advantages of this wafer level processing strategy in a high volume, high mix wafer bump fabrication facility including improvements in processing quality and consistency. The transparency on deploying this front-end process change on back-end assembly operations and device reliability will also be addressed.
Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding
Authors: Zoschke Kai , Lang Klaus-Dieter 
Published: October 2015

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves.
Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general.
The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages.
However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways.
The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap.
The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail.
All processes were performed at 200mm wafer level.
A Kinetic Monte Carlo Approach to Study Transport in Amorphous Silicon
Authors: Muralidharan Pradyumna , Vasileska Dragica , Goodnick Stephen M. 
Published: October 2015

The constant innovation of devices in the semiconductor industry to improve performance to meet very specific demands has led to the study and exploration of a host of new materials. The use of ternary and quaternary materials, organic materials, amorphous silicon are a few examples of promising alternatives to traditional crystalline silicon. However, the use of novel materials presents a unique challenge for a theoretical analysis using device simulation. Traditional device simulation methods are sometimes not enough to capture the nuances of transport. In this paper we study transport through amorphous silicon to evaluate it's role in a-Si/c-Si HIT Cell and it's potential for other device operations by the use of Kinetic Monte Carlo (KMC) method.
As an amorphous materials lack long range order, it is near impossible to create a bandstructure for it and conduct Ensemble Monte Carlo (EMC) simulations to study transport through the material. Also, the presence of many defects creates localized states below the conduction band which facilitates hopping transport. As hopping transport happens through a series of capture and emission processes, the time scales of these mechanisms render the use of a traditional EMC unfeasible. It is crucial to understand the nature of the defects/traps that are present in the amorphous material. Understanding defect assisted transport is the key to understanding how the amorphous silicon layer will affect overall device performance. Defect assisted transport (DAT) can be conducted in the amorphous material through various different mechanisms such as capture of carriers by a defect, tunneling emission, Pool-Frenkel emission, defect to defect transition etc.
Using the Kinetic Monte Carlo approach we will be able to simulate individual charge carriers that interact with point like defects over a period of time. However, the transient nature of the KMC is not limited to short time scales. Also, the suggested method can be used to study the effect of many transition mechanisms. This method facilitates the simulation of the many individual steps in a Markovian chain that mimics carriers moving through various defects. We study hopping transport through a triangular barrier with use of phonon assisted mechanisms to analyze current and carrier transit times. The distribution function is also analyzed before and after defect assisted transport. One of our primary objectives is to study the role played by the amorphous silicon layer in determining overall device performance of a-Si/c-Si HIT Cell.
Advanced Silicon Interposer for High density and High Integration Electronic Packages
Authors: KUMOCHI SATORU , Koiwa Sumio , Suzuki Kosuke , Fukuoka Yoshitaka 
Published: October 2015

As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger.
Interposers for system in package will became more and more important for advanced electronic systems.
Interposers will be needed more complicated structure for 2.5D , 3D package and MEMS, OEMEMS new heterogeneous package structure
Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. [1]
This paper presents the demonstration of Silicon Interposers with fine pitch through Silicon vias(TSV),with embedded passive device.
We have developed the TSV interposer with redistribution layers on both sides using MEMS technology, high aspect ratio deep etching technology and filled Cu plating with deep through holes for cost reduction and low electrical loss. The TSV interposer with 400μm thick high resistivity Si, obtained without backside processing use of carriers.
Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TSV at 200μm pitch passed 1000 thermal cycles from −55°C to 125°C.
We have evaluated high frequency transmission characteristic of Si through hole by the measurement S21 parameter. Highly insulating TSV resulted in insertion loss of less than 1dB at 20GHz.
Thin film SiN capacitor as embedded passive device was built in surface of TSV interposer by via first and via last method. The capacitance and leakage current of capacitor was measured and compared with two types of fabrication method.
Design and Fabrication of a PCB MEMS Module With Integrated Switches and Sensor Suite
Authors: Liew Li-Anne , Boteler D. , Lin C.Y. , Marsiglia N. , Lee Y.C. 
Published: October 2015

We demonstrate the feasibility of integrating Kapton-based MEMS capacitive switches and a sensor suite onto a printed circuit board (PCB) with minimal impact to existing manufacturing processes. Copper-cladded kapton laminates were bonded onto rigid PCB substrates with a BCB film spacer. The kapton was patterned using reactive ion etching to produce MEMS structures such as suspended membranes and flexures. Atomic layer deposited alumina coatings were applied as dielectric layers for the capacitive switches and tilt sensors/accelerometers. The copper cladding was also patterned by etching to function as electrical leads, resistors, and capacitive electrodes.
In this way, MEMS switches, tilt/acceleration sensors, temperature sensors, humidity sensors, and vacuum pressure sensors, were all fabricated monolithically onto a PCB in a single module. We describe the fabrication process, challenges and improvements to the process in particular in the bonding and etching of the kapton films. We also describe the design of the various sensors and switches and demonstrate their functionality.
Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology
Authors: Mobley Tim , Keusseyan Roupen , LeClair Tim , Yamnitskiy Konstantin , Nocon Regi 
Published: October 2015

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging.
This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.
Waveguide Inductive Strip Filter Embedded in LTCC
Authors: Abousaif Ehab , Elshabini Aicha , Barlow Fred 
Published: October 2015

Microwave filters are generally designed with microwave transmission lines. However these filters are typically lossy. The waveguide filters using conventional inductive elements such as metal rods and transverse diaphragm have some disadvantages such as complicated structure, high cost and they can be hard to mass produce. But they also have many advantages such as the capability of high power transmission, a non-radiating structure, and their thermal efficiency. A novel waveguide inductive strip filter embedded in LTCC is introduced in this paper where the disadvantages of the conventional waveguide filters are eliminated. By using LTCC technology, the cost will typically be lower, it can easily be mass produce, and these designs can also be tested easily.
The equivalent T-network parameters of the inductive strip mounted in a waveguide and embedded in LTCC substrate were derived. A new iterative technique was used based on the Variation principle. The design formulas and curves of the filter were presented. The design method of the filter was derived by applying the equivalent network of the inductive strip to the usual method of the filter design. A complete set of new curves relating the various filter parameters were introduced. Similar curves can be derived to design similar filters for any frequency band using any dielectric material.
Three-dimensional electromagnetic field modeling and simulation was carried out using HFSS (High Frequency Structure Simulator). An optimization process was done for the designed filter. The modeling and the optimization S-parameters curves are shown.
This paper introduces a new methodology of designing waveguide inductive strip filters embedded in LTCC. The design methodology was derived and presented with formulas and curves. The design steps are explained and verified by examples and results.