Unveiling Sub-60 mV/decade Subthreshold Swing in The Oxide Local Thinning (OLT) Gated MIS Tunnel Diodes by TCAD Simulations
Authors: Huang Sung-Wei , Lin Jun-Yu , Hwu Jenn-Gwo 
Published: August 2024

Metal-insulator-semiconductor (MIS) tunnel diodes (TD) are widely used in the modern integrated circuit, for its ease of fabrication and low cost. Recently, we have reported that the gated MIS TDs can exhibit sub-60 mV/decade subthreshold swing (SS) [1], which can be further reduced by introducing oxide local thinning (OLT) regions. SSs could be as low as 9.7 and 8.4 mV/decade in gated MIS TDs with the OLT regions formed by soft breakdown and photolithography, respectively [2,3]. The reason is unclear and the feasibility of scaling is of interest. In this work, we unveiled the mechanism and designed the scaled devices with ultra-low SS by TCAD simulation.
We performed Silvaco TCAD with the 2-D cylindrical structure identical to [2] (Fig. 1). Models of direct tunneling and quantum confinement were included. The OLT region at the center TD is 100 nm. The OLT region at the gate is 400 μm from the inner gate edge, and the width (W
GOLT) varies from 100 to 1000 nm.
Fig. 2(a) shows the simulated I
TD-V
G curves of the OLT gated MIS TDs, denoted as TDOLT+GOLT, with different W
GOLT, compared to the one without an OLT region at the gate, denoted as TDOLT, and Fig. 2(b) shows the corresponding SS. TDOLT+GOLT turns-on steeply, with SS approaching 10 mV/decade, close to the value observed in [2,3]. The electron densities n
e at 2 nm depth in the silicon under different V
G are examined for TDOLT and TDOLT+GOLT with W
GOLT = 100 nm in Fig. 3(a) and (b) respectively. n
e near the inner gate of the latter case increases abruptly from -0.8 to -0.7 V, due to the injection of the extra electrons from the gate OLT region. Fig. 3(c) shows the electron densities at 2 μm inside the gate edge for different devices, following the similar trend with the I
TD-V
G curves, indicating that the magnitude of the TD current is determined by n
e near the gate edge. Fig. 4 shows the mechanism of TD current under different situations. For V
G = -1 V, I
TD is off and comes from the generation of electrons under the TD. For V
G = -0.5 V, I
TD is in the stage 1 and comes from the injection of electrons through the gate OLT region. The injection of electrons results in the steep increase of I
TD and subsequently the ultra-low SS. For V
G = 0.2 V, I
TD is in stage 2 and collects the electrons generated in the whole substrate. The rapid increase of n
e at the gate edge can be understood in another point of view. Fig. 5 shows the band diagram laterally near the silicon surface. Since n
e depends on the difference between the conduction band energy (E
C) and the electron quasi-Fermi level (E
Fn), when V
G increases from -0.8 to -0.7 V, E
C is pushed down while E
Fn at the gate edge is pulled up due to the injection of electrons through the gate OLT region. Therefore, the device can have SS lower than 60 mV/dec.
To test whether the ultra-low SS characteristics can maintain when scaling down, we performed the simulation of the sub-micro device shown in Fig. 6. We find the TD cannot be turned off if we still use substrate thickness t
sub = 5 μm (Fig. 7(a)), since the injection of electrons are too strong. However, by reducing t
sub, I
TD can be turned off and shows superior performance with on-off ratio over 8 orders and SS lower than 60 mV/decade (Fig. 7(b)). Since the electron diffusion current flowing to the substrate of an MIS TD with the substrate much shorter than the diffusion length can be expressed as

J
n = (qD
n
n
i
2/t
sub
N
A) e
qΔΦ

n/kT

where q, D
n, n
i, N
A, ΔΦ
n, k, T are the elementary charge, electron diffusion coefficient, intrinsic carrier concentration, p-type doping concentration, electron quasi-Fermi level splitting, Boltzmann constant, and temperature, respectively, reducing t
sub can lead to a stronger diffusion of electrons to the substrate, and there will be fewer electrons flowing to the gate edge (Fig. 8). Therefore, the electron densities can be lower near the gate edge when V
G is negative enough, as shown in Fig. 9, leading to the effective turn-off of the TD.
REFERENCES
[1] Liao, et al., IEEE Trans. on Electron Devices, 62(6), 2061, (2015).
[2] Yang, et al., IEEE
Trans. Electron Devices, 66(1), 279, (2018).
[3] Chiang, et al., IEEE Trans. Electron Devices, 67(4), 1887, (2020).
ACKNOWLEDGEMENT
This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 111-2221-E-002-192-MY3 and NSTC 111-2622-8-002-001.

Figure 1