bluuebunny/crossref_metadata_2025_split huggingface dataset:
Manufacturability & Reliability Challenges with Leadless Near Chip Scale (LNCSP) Packages in Pb-Free Processes
Authors: Tulkoff Cheryl , Caswell Greg 
Published: October 2015

Leadless, near chip scale packages (LNCSP) like the quad flat pack no lead (QFN) are the fastest growing package types in the electronics industry today. Early LNCSPs were fairly straightforward components with small overall dimensions, a single outer row of leads and small lead counts. However, there is currently a proliferation of advanced LNCSP package styles that have started to approach BGA packages in terms of both size and number of connections. Some of the newer packages have 3 or more rows, pitches as fine as .35mm, lead counts exceeding 200, and dimensions exceeding 12 mm × 12 mm.
While the advantages of these packages are well documented, concerns arise with both reliability and manufacturability in Pb-free environments. So, acceptance of these packages in long-life, severe-environment, high-reliability applications is somewhat limited. One of the most common drivers for reliability failures is the inappropriate adoption of new technologies like LNCSP. Since robust manufacturing and qualifications standards always lag behind implementation, users must carefully select and validate these components for suitability in their use environments and customer applications.
Soldering, flexure, and cleanliness issues have driven many failures seen in production and in the field. All of these areas must be addressed early in the selection and validation processes. In this paper, we will review and discuss LNCSP related reliability concerns and challenges, and propose Physics-of- Failure (PoF) based approaches to allow the successful introduction and failure analysis of LNCSP components in electronics products.
Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly
Authors: Whitmore Mark , Ashmore Clive 
Published: October 2015

As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged.
A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s.
Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures having area ratios as low as 0.4. Such a breakthrough will allow the printing of ultra fine pitch components and additionally will assist with heterogeneous assembly concerns, to satisfy up and coming mixed technology demands.
Robustness and Versatility of Thin Films on Low Temperature Cofired Ceramic (LTCC)
Authors: Wolf J. A. , Peterson K. A. , Vianco P. T. , Johnson M. H. , Goldammer S. 
Published: October 2015

Thin film multilayers have previously been introduced on multilayer low temperature cofired ceramic (LTCC). The ruggedness of a multipurpose Ti-Cu-Pt-Au stack has continued to benefit fabrication and reliability in state-of-the-art modules. Space optimization is described, preserving miniaturization of critical spaces and component pads. Additional soldering details are also presented, including trends with solder-stop materials. Feature compensation becomes a simple step in the normal manufacturing flow which enables exact targeting of desired feature sizes. In addition, fine details of the manufacturing process, including ion milling, will be discussed. We will discuss full long-term aging results and structural details that reinforce the reliability and function. Different thin film materials for specific applications can be exploited for additional capabilities such as filters and other integral components. Cross sections verify the results shown. This successful integration of thin films on LTCC points to higher frequencies which require finer lines and spaces. Advancements of these applications become possible due to the associated progression of smaller skin depth and thinner metallic material.
This work prepared by The Kansas City Plant for the United States Department of Energy under Contract No. DENA0000622. The Kansas City Plant is operated by Honeywell Federal Manufacturing & Technologies, LLC.
Ageing characteristics of Cu Wire Bonds on Palladium Surface Finishes
Authors: Oezkoek Mustafa , Clauberg Horst , Roberts Hugh 
Published: October 2015

During the past two years, fine pitch copper wire bonding has finally entered high volume production. It is estimated that nearly 15% of all wire bonders used in production are now equipped for copper wire bonding. Most of these are used exclusively for copper wire bonding. In terms of pitch, copper wire is only barely lagging behind the most advanced gold applications. The most commonly used copper wire is 20um in diameter and 18um copper wire is already being used in mass production. Evaluations with even finer wire are underway.
Although some technical challenges remain, many years of research have now resolved most of the problems associated with copper wire bonding and attention is beginning to shift from merely ensuring reliable manufacturing processes to optimizing processes for efficiency and throughput. The most advanced wire bonders now have pre-configured processes specifically designed for copper. In addition to throughput optimization, further cost reductions are being sought. Among these is the desire to eliminate the high-cost gold not just from the wire, but also from the substrate.
On the substrate side the electronics packaging industry still works with electrolytic nickel / electrolytic (soft) gold (Ni/Au) for copper wire bond applications. This surface finish works with copper wire bonding but includes some disadvantages, such as:- Thick expensive Au layers of 0.1 to 0.4μm- Electrically connected pads (bussing for the plating) which requires added space on the substrate.- Pd-coated copper wire often delivers better results on gold covered finishes, but is two to three times more expensive as pure copper wire
Furthermore electrolytic Ni/Au was not chosen for Cu wire bonding as a result of in-depth investigations for the most effective surface finish. The selection was made because it was the surface finish with the highest distribution in the market for wire bond packages.
This paper is offering the results of a two company joint work regarding alternative copper wire bondable surface finishes.
The result of the project is separated in 2 papers/publications. The first publication [1] presents the investigations with Cu wire bond pull forces and process windows of 23 different surface finish variations. The main aim was to identify alternative surface finishes for copper wire bonding. Within this study the surface finishes ENEP (Electroless Nickel/Electroless Palladium) and “Direct Electroless pure Pd on copper” (pure EP finish) was identified as copper wire bondable finishes with the pure Cu wire.
The second part of the evaluation summarizes an in-depth study of copper wire bonding tests after thermal aging with ENEP and the pure EP surface finish using the pure copper wire. The results of this investigation does include results with pull forces after thermal aging and an IMC Investigation with FIB Pictures of the copper wire/surface finish connection in order to evaluate the reliability of such an interconnection.
Which Frequency is Best for Wirebonding?
Authors: Sedlmair Josef , Farassat Farhad , Schlicht Franz 
Published: October 2015

In industrial practice, frequencies from 40 kHz up to 160 kHz are currently employed for wire-bonding while for experimental purposes, lower and higher frequencies from around 25 kHz up to 300 kHz are discussed. Typically, heavy aluminium wire or ribbon is preferably bonded at lower frequencies between 40 and 80 kHz, while thin aluminium or gold wires are wedge- or ball-bonded at frequencies between 100 and 140 kHz.
We present a discussion of the pros and cons of different ultrasonic frequencies by looking at the mechanics during the bonding process. Higher frequencies allow shorter bonding times and permit bonding on more sensitive surfaces, but suffer from a narrower parameter window. This is mainly due to the smaller vibration amplitudes at the tool tip which can be employed for higher frequencies. The major benefit for many applications is that higher bond quality is possible even at lower wire deformation which additionally creates a healthier bond heel. Lower frequencies, on the other hand, seem to have advantages for rougher surfaces where some planarizing and smoothing is required before bonding can begin to take place, while running a higher risk of damaging the bond after forming it.
Resonance effects can seriously damage bond formation, and ways are discussed on how to deal with this problem.
The Reliability Impact of Reballing COTS Pb-Free BGAs to Sn/Pb for Military Applications
Authors: Caswell Greg , Arnold Joelle 
Published: October 2015

The electronics assembly market has experienced a material shift from lead (Pb) based solders to Pb-free solders. This is a result of the widespread adoption of Reduction of Hazardous Substances (RoHS) legislation and practices in commercial industry. As a result, it is becoming increasingly difficult to procure commercial off-the-shelf (COTS) components with tin-lead (SnPb) solder balls or finish.
There are essentially three responses to the scarcity of acceptable SnPb parts: custom order, post process or adapt. Custom ordering parts with SnPb finishes negates the benefits of COTS based acquisition; however, has a reduced reliability risk because the material and processes are known. Reprocessing parts once in house saves money because the parts are COTS, but expends money and resources by performing post processing on them.
Also, the additional touch labor and handling increases the risk of damaging the part. Finally, adapting to Pb-free finishes is the preferred long term approach because it preserves the cost benefits of using COTS parts and does not require post processing. It is the riskiest approach due to the lack of historical data in the DoD environment.
This paper presents results regarding reballing 208 I/O Ball Grid Array (BGA) parts from tin-silver-copper (SAC305) solder to SnPb eutectic solder. It is important to understand the reliability risks associated with the reballing procedure, particularly as it relates to thermal cycling, shock and vibration environments. Three major efforts will be presented to answer these concerns.
First, a survey of reballing vendors was performed to better understand the processes and variables associated with that industry. The results of that survey were used to down-select to five vendors that were used for the physical testing portion of the effort. Finally, physical testing consisting of thermal cycling, shock, and vibration was performed. The physical testing was performed on parts from the five different reballing vendors as well as native SnPb parts and native SAC305 parts. The results of these activities will be presented.
Optoelectronic Substrate With High-Aspect-Ratio Optical Through-Hole for Chip-to-Chip Interconnects
Authors: Suzuki Atsushi , Takagi Yutaka , Horio Toshikazu , Kojima Toshifumi , Takada Toshikatsu , Iio Satoshi , Okuyama Masahiko 
Published: October 2015

We report high-aspect-ratio optical through-holes fabricated in optoelectronic substrates for chip-to-chip optical interconnections. They are used for transmitting optical signals vertically through the optoelectronic substrate. They consist of cladding layer and cores that are 50 μm in diameter. Their lengths are 1.2 mm equal to the thickness of the substrate. This small diameter enables the optical through-holes to achieve low-loss optical coupling with a polymer optical waveguide. This thickness of the optoelectronic substrate accommodates embedded capacitor integration under CPUs. The capacitor will improve power supply to the CPU and co-planarity for both package level and board level assembly.
We have evaluated the optical characteristics of the high-aspect-ratio optical through holes. We have measured optical loss and crosstalk. Optical coupling dependencies of alignment offset for the optical through-holes are also evaluated to clear the effects of misalignment. The optical loss of core-cladding optical through-hole was 1.3 dB that was 2.9 dB better than that of only one kind of transparent resin and 3.8 dB better than that of a vacant drilled hole. The narrowest 1-dB coupling tolerance was +/− 12 μm from the transmitter optical through-hole to the optical waveguide. Total optical loss was estimated to be 6.8 dB from a vertical-cavity surface-emitting laser through 100-mm polymer waveguide with two 45°-ended mirrors to a photodiode.
An Innovative High Thermal Conductive Solderable Adhesive
Authors: Liu Mary , Yin Wusheng 
Published: October 2015

With increasing LED development and production, thermal issues are becoming more and more important for LED devices, particularly true for high power LED and also for other high power devices. In order to dissipate the heat from the device efficiently, Au80Sn20 alloy is being used in the industry now. However there are a few drawbacks for Au80Sn20 process: (1) higher soldering temperature, usually higher than 320 °C; (2) low process yield; (3) too expensive.
In order to overcome the shortcomings of Au80Sn20 process, YINCAE Advanced Materials, LLC has invented a new solderable adhesive – TM 230. Solderable adhesives are epoxy based silver adhesives. During the die attach reflow process, the solder material on silver can solder silver together, and die with pad together. After soldering, epoxy can encapsulate the soldered interface, so that the thermal conductivity can be as high as 58 W/mk. In comparison to Au80Sn20 reflow process, the solderable adhesive has the following advantages: (1) low process temperature – reflow peak temperature of 230 °C; (2) high process yield – mass reflow process instead of thermal compression bonding process; (3) low cost ownership. In this paper we are going to present the die attach process of solderable adhesive and the reliability test. After 1000 h lighting of LED, it has been found that there is almost no decay in the light intensity by using solderable adhesive – TM 230.
3D Integration of Wide IO Memory Cube Stacking to 28 nm Logic Chip with High Density TSV through a Fabless Supplier Chain
Authors: Gu S.Q. , King D.W. , Ramachandran V. , Henderson B. , Ray U. , Nowak M. 
Published: October 2015

Wide IO memory has higher IO–count (up to 16×) than typical low power DDR memory, which could enable higher system bandwidth at low power. Wide IO DRAM can be stacked as Micro Pillar Grid Array (MPGA) cubes [1], which will provide high memory density for the system. With the high number (∼1200) of connections to the MPGA, a direct face to back stack (3D) to logic chip with high density TSV is the most efficient approach. To utilize the extra large bandwidth, the logic chip containing high speed processors requires logic chip fabrication in advanced node devices.
In this paper, we report the–demonstration of a 2-memory chip JEDEC standard wide IO MPGA stacking on logic chip through a fabless supplier chain. A successful integration of via middle through Si via (TSV) to 28 nm logic process has been demonstrated with minimum impact to logic devices. The final package showed good TSV and ubump integrity. The wide IO memory is functional post stacking. In addition, the early reliability data for TSV and ubump showed no detrimental impact through temperature cycle and high temperature storage.
High-Reliability Component Attachment Process for &lt;5μm Placement Accuracy
Authors: Beck Donald J. , Bok Zeger , Martinez Daniel 
Published: October 2015

As complex microelectronic packaging designs and components mature, improved placement accuracy becomes increasingly more important. High-accuracy placement has been an ongoing theme in the commercial assembly arena for several years. For example, some phononic designs require better than 2μm precision placement for optimum performance.
Military and aerospace companies routinely evaluate higher precision technologies, although this has been traditionally accomplished using semi-automatic bonder equipment. A manual or semi-automatic process is adequate and often perceived as essential for prototyping; however, semi-automatic processes are not practical for higher volume production. Aside from the slower speed of semi-automatic equipment, application performance relies on how well the technician can target the die since these systems mainly require manual alignment.
This paper presents a process solution for automating &lt;5μm component attach specific to organizations requiring high-reliability device packaging. The methods presented in this paper have been proven through real-world experiences related to the high-reliability microelectronics industry.
Pb-free PBGA Design Points to Improve Handling Robustness
Authors: de Sousa Isabel , Roggeman Brian , Chacon Oswaldo , Spencer Niki , Ueno Mamoru 
Published: October 2015

Pb-Free BGA solder joints are more brittle and more susceptible to interfacial fails than the leaded versions. These brittle failures typically occur if the modules are subjected to high strain rates through module handling impacts or PCB flexural stress. The high speed ball shear technique is a useful method to submit solder joints to high strain rates in a controlled manner to emulate the levels of strain the BGAs may see in handling. This measurement technique was used to evaluate different laminate design and process variables on organic laminate substrates to create a more robust Pb-Free solder joint.
Experiments were conducted to evaluate the effects and interactions of laminate, module assembly process, SAC alloy composition, and thermal treatments. Modulations of shear speed and shear angle made it possible to observe transitions from ductile to brittle solder fractures. The high speed ball shear method was successful to differentiate subtle effects resulting from different design points and process variables. The copper composition in the PbFree solder alloy, thermal history, and geometric factors such as solder volume, solder resist opening and solder resist thickness all had measurable impacts on the shear strength and transition point of ductile to brittle failure.
Some BGA configurations have also been tested in reliability, namely in thermal cycling, and were shown to meet application requirements. Optimal design points can therefore be applied to enhance handling robustness without compromising on reliability.
Realisation of High Temperature Electronics Packaging Technology for Sensor Conditioning and Processing Applications
Authors: Riches S T , Johnston C , Lui A 
Published: October 2015

The requirement to install electronic power and control systems in high temperature environments in aero-engines and in down-well exploration has posed a challenge to the traditional limit of 125°C of electronics systems. The leap in operating temperature to above 200°C in combination with high pressures, vibrations and potentially corrosive environments means that different semiconductors, passives, circuit boards and assembly processes will be needed to fulfil target performance specifications.
Silicon on Insulator (SOI) device technology has been shown to be capable of functioning satisfactorily at operating temperatures of &gt;200°C. Most of the applications to date have required performance for short times (&lt;2,000 hours) at the highest operating temperatures of up to 225°C in down-well drilling applications. There is interest in extending the endurance of high temperature electronics into aero-engine and other applications where a minimum 20 year operating life is stipulated. Most of the reliability data on the high temperature endurance of the integrated circuit is generated with little consideration of the packaging technologies, whilst most of the reliability data pertinent to high temperature packaging technologies uses test pieces, which limits any conclusions relating to long term electrical performance.
This paper will present results of studies on high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. Different die attach and wire bond options have been included in the study and the performance of several functional blocks on a high temperature SOI device has been tracked over the endurance tests which have lasted for &gt;11,000 hours at 250°C. Degradation phenomena such as thermal migration and material deterioration due to high temperature exposure in air and inert atmospheres will be described. An assessment of the availability of high temperature materials and components to meet long term requirements for operation at 250°C will be presented.
New Flip-Chip Interconnect Technology for High Performance and High Reliability Applications
Authors: Yamaguchi Eiji , Tsuji Mutsuo , Shimoishizaka Nozomi , Nakano Takahiro , Hirata Katsunori 
Published: October 2015

As the current and next generation devices are embracing geometries below 28nm and requiring softer low-K dielectric isolation on very thin large silicon dies ∼ to perform a reliable die-to-package interconnect is becoming a challenge. Further, the high pressure from Cu wire bonding and high reflow temperature of conventional flip-chip bonding often results in damage of device structure.
A new flip-chip bonding technology has been developed for such critical applications, and is claimed to be “damage free”. It uses soft bump made by non-full cured conductive paste on the package substrate. These soft bumps require ultra-low bonding pressure on the pad of the die. Thus the bonding process don't make any damage on ULK isolation layer. Details of the process, material sets used for such fragile device structures have been discussed. Reliability results are shared, which further ensures the robustness of this process. Finally, the cost advantage through adaptation of this process has also been elaborated.
Making New With Old
Authors: Renaud-Bezot Nick , Beesley Mark 
Published: October 2015

In the past few years, embedding has emerged as a valid contender to traditional packaging technologies for specific applications. It uses PCB (Printed-Circuit Board) processes for 3D integration of active and passive elements to create SiPs (System in Package).
Just like MEMS (Micro Electro-Mechanical System) and IPD (Integrated Passive Device) emerged from standard semiconductor processes, and then were adapted to match the specific requirements, so does embedding build on decades-old techniques to create this new class of packages. Inherent advantages include:- Compatibility with traditional SMT processes, in particular with regards to pitch,- Production batch size,- Historical reliability and process data,- Thermal management,- Possibility to integrate EMI shielding,- CTE matching.
This paper will present the challenges and opportunities of this packaging technology in terms of processes, performance and reliability. It will focus on the solution developed by AT&S called ECP® (Embedded- Component Packaging). Whereas competition is integrating PCB processes to their semiconductor-packaging operations, AT&S is the only vendor building on its PCB tradition to enter the packaging industry, thereby presenting an alternative view of the subject.