bluuebunny/crossref_metadata_2025_split huggingface dataset:
New Mixed Metal Transition Via-Fill Conductors for Cost Effective DuPont GreenTape™ 951 & 9K7 LTCC Circuits
Authors: Nair K. M. , McCombs M.F. , Souders K.E. , Gordon S. E. 
Published: October 2015

LTCC (Low Temperature Co-fired Ceramic) technology provides an option for circuit designers that combines the benefits of HTCC and thick film technologies and is the technology of choice for many complex automotive, consumer, and military applications. For demanding and high reliability applications, LTCC circuits containing gold conductors for all ground planes, signal traces, and via fills are common. With the rise in gold cost from $400/TO in 2005 to a recent peak of over $1,200/TO in 2009, OEMs and circuit designers are forced to seek lower cost alternatives to all gold LTCC structures. The use of all silver conductors raises questions of reliability, especially for the external silver layers, and wire-bonding to silver is not possible.
The traditional method employed to address cost and reliability has been the use of mixed metallurgies, rather than using gold throughout the LTCC module. Silver based conductors for signal and ground are used internally, with gold conductors for wire bonding, brazing, or soldering on the external surfaces. Today there are two primary options to achieve this type of structure: 1) Ni/Au plating the top silver surface; or 2) Use of precious metal based transition via fill compositions that interconnect the silver to the gold conductors.
Traditional LTCC transition via fills compositions have consisted of Pd/Ag or Pd/Pt/Ag mixtures. However, such systems may be disposed to certain phenomena at the surface interface(s) between dissimilar metals. For example, the Kirkendall Effect has been found in various alloy systems and can impact the bonding between different materials. In particular, it has been studied and is used to describe voids that are produced in the boundary region at a bonding interface especially during high temperature processes such as metallic powder sintering.
This paper introduces two new mixed metal via-fill conductors that are compatible with the DuPont GreenTape™ 951 and 9K7 LTCC systems. Reliability and refire stability are described in detail.
Development on Silicon module with Cu-filled TSV and Integrated Passive Devices
Authors: Park Yun-Mook , Lee Jun-Kyu , Park Byung-Jin , Kim Byeung-Gee , Lee Jung-Won , Kang In-Soo 
Published: October 2015

In recent years, market demands on more functionality, smaller form factor and higher speed is becoming strong increasingly. In order to come up with those, many new technologies are emerging in the market. Among them, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.
In this work, we have developed the silicon module with Cu filled TSV and LPF [Low Pass Filter] in combination with Inductor and MIM Capacitor integrated at the surface of silicon interposer. And also have made very small form factor package with less than 0.8mm in thickness including 2 chips mounted side by side at the silicon interposer.
In order to make silicon module with Cu filled TSV, we have evaluated and optimized via etch, thin-film deposition and via filling process which characterized a high uniformity via etch, good step-coverage and void-free at 200um in depth and 65um in TSV diameter at wafer-level. Furthermore, the IL [Insertion loss] of 0.14dB and 0.11dB for 3rd order filter and 5th order filter at 2.4 GHz respectively was achieved through both front-end process capable of high uniformity insulator deposition and back-end process capable of forming thick Cu RDL [Redistribution]. A good matching between measured value and simulated one using 3D simulator was achieved.
We are currently running component reliability tests for Preconditioning, TC, HTS and 85%/85. So test results will be discussed and submitted at the full manuscript.
Chip-last Embedded Actives and Passives in Ultra-Miniaturized Organic Packages with Chip-First Benefits
Authors: Kumbhat Nitesh , Liu Fuhan , Sundaram Venky , Sridharan Vivek , Choudhury Abhishek , Chan Hunter , Tummala Rao 
Published: October 2015

Embedded actives and passives are being pursued by chip-first and wafer-level fan-out approaches to address high functionality and miniaturization. A next generation embedding alternative- “chip-last embedding”, which retains all the benefits of chip-first, has been demonstrated at Georgia Tech for complex multi-component heterogeneous systems. This paper presents detailed results from the first demonstration of this novel technology called Embedded MEMS, Actives and Passives (EMAP) with Chip-Last (CL) interconnections. This technology is targeted at highly integrated modules and systems with multiple 2D and 3D ICs for RF, Digital, Analog, MEMS and passive devices.
Ultra-thin (55μm) silicon test dies were embedded in a 60μm deep cavity within 6-metal layer substrates yielding a total module thickness of 0.22mm. The robustness of substrate materials and processes was demonstrated using thermal cycling of the blind-vias and through-holes. The embedded IC was bonded to the substrate at 160°C by ultra-fine pitch (30–50μm) and low-profile (10–15μm) Cu-to-Cu interconnections with polymer adhesives. Two different die-sizes 3mm × 3mm and 7mm × 7mm were investigated for reliability performance of these interconnections, which passed 1000 thermal cycles, in addition to Highly Accelerated Stress Test (HAST) and High Temperature Storage Test (HTS).
Comprehensive analysis of new materials and processes used in the chip-last embedding technology has been carried out demonstrating the advantages and robustness of this promising technology. Due to manufacturing process simplicity and unparalleled set of benefits, the chip-last technology provides the benefits of chip-first while enabling highly miniaturized, multi-band, high performance modules with embedded actives and passives.
Compression Molding for Thin PoP Top Packages
Authors: Adimula Ravikumar , Brand Jason , Yim Myung Jin , Zhang James , Strode Richard , Yoo Chan 
Published: October 2015

The package on package (PoP) has become the preferred method for vertical stacking of logic processors and memory in mobile applications. The industry is constantly working toward reducing the total stack height, and current road maps point toward a total stack Z-height of 1mm. One approach to reduce the package height is to reduce the mold cap thickness as well as reduce the mold cap clearance (the distance between the top silicon die to the mold top). In this study, we used the compression molding for manufacturing top PoP packages with 200μm, 250μm, 300μm, and 350μm mold cap and with sub-100μm mold cap clearance. As part of the mold material selection, two different form factors, granular and powder form, of the mold compound were used for the compression mold process. The key objective for this study is to investigate compression mold process and to study its effect on the package integrity.
The major challenge for PoP stack up is the package warpage at reflow temperatures. All the PoP packages must meet certain critical warpage criterion to meet board mount yield requirements. Warpage of the packages was measured by the shadow moiré method, and the warpage results for the packages molded by the transfer mold were compared against that of the compression molded packages. Results indicate that there is considerable difference in warpage behavior betwee n the pellet and powder form of the same mold compound. However, the granular form of the same mold compound resulted in similar warpage behavior of the pellet form mold compound. Further analysis was done to compare the filler distribution in the mold for transfer versus the compression mold process. Results indicate much uniform filler distribution in compression mold furthering evidence that the warpage for the unit level package will be uniform across the strip. Warpage results were analyzed using finite element methods, and the results are extrapolated to different package XY dimensions. The data obtained from these experiments show that the compression mold method can be potentially implemented for thin PoP top packages in the future.
Development of a Low Voiding Solder Attach Process for Photovoltaic Cell Assemblies
Authors: Hardy Ian 
Published: October 2015

The level of competition for a share of the burgeoning solar cell market naturally drives companies towards low-cost, high-volume subcontractors. But the stringent operating requirements in a concentrated photovoltaic (CPV) application are more consistent with the process capabilities of lower volume manufacturers. Specifications for attach of PV cells as large as 1 cm2 require the high thermal conductivity of a solder connection with minimal voiding in order to prevent current-crowding effects and thermal hotspots. These design aspects are most easily achieved through the use of lower volume, more labor-intensive batch processes such as vacuum reflow, often using expensive alloys such as 80Au20Sn.
Crane Electronics in Redmond, WA, has developed an in-line solder reflow process for PV cell attach that uses standard, inexpensive solder alloys to address large die, low-voiding applications. This paper discusses the initial design and subsequent incremental improvement of that process, with supporting x-ray and yield data.
“Cleaning”- The Dirty Word in Packaging Assembly
Authors: Brooks Rich 
Published: October 2015

A majority of the package assembly facilities are using only DI water to remove flux residue from under flip-chip devices, prior to an underfill process. As the new technologies are being implemented, not only has DI water reached its limitations, but some cleaning chemistries are not able to perform adequately to remove ALL of the flux residues. Complete cleaning and removal of the flux residues under low profile components are critical to maintain the reliability of the integrated circuit. Therefore, the cleaning process must be carefully examined and optimized to obtain maximum performance for removing the flux residues. The total cleaning process can be broken down into two subsets:Static Cleaning rate & Dynamic Cleaning rate
The Static Cleaning rate is ability of the cleaning chemistry to remove or dissolve the residue in the absence of temperature and pressure. The Dynamic Cleaning rate involves the kinetic forces and energy to remove the residue. This includes the Thermal energy and Impingement energy required to remove the flux residue. The sum of these two cleaning rates (Static and Dynamic cleaning rates) equal the Total Process Cleaning rate (see formula below). This paper will review cleaning problems brought about with the implementation of the latest technologies and explain how the cleaning process can be optimized to guarantee the reliability of the assemblies.
How Silver Powder Metallurgy Affects the Physical Properties of Low Temperature Firing Silver Conductor
Authors: Shahbazi Samson , Challingsworth Mark 
Published: October 2015

With the implementation of RoHS (the Restriction of Hazardous Substance) Directive banning the use of Lead, Cadmium, Mercury and Hexavalent Chromium, hybrid microelectronic manufacturers are globally embracing the lead free movement. These manufacturers must not only understand the implications of their material choice but must be aware of the interaction between lead free solder alloys and their RoHS compliant thick film materials.
It is commonly known that lead free solder alloys process at much higher reflow temperatures than lead containing solder which can directly impact the fired film leach resistance and the loss of adhesion. There are also other concerns; lead free solders alloys generally require a different organic flux system to promote wetting and reflow, but this change may cause a fired film conductor to leach more easily than the flux used in the lead containing solders. The use of lead free solders such as SAC305, SAC405 or 95/5 on a low firing (550–570 °C) pure silver conductor has the tendency of leaching the fired film more readily than conductors containing small amounts of palladium or platinum. Many of these situations provide new challenges for the hybrid circuit manufacturer. There is little information available regarding the effects of the lead free solders on low firing silver thick film conductors.
This paper discusses the results of a newly developed Pb and Cd free silver thick film conductor paste with a modified silver powder metallurgy to improve the leach resistance, solder acceptance and adhesion using lead free solder. In addition, the pure silver conductor was fired on top of a low temperature dielectric paste. This conductor was evaluated by comparing lead free solder alloys to traditional tin-lead-silver solder alloys. This study included evaluations based on SEM photos, solderability, leach resistance, and initial and long term adhesions. Results are published describing the difference in behavior between the different solder alloys in conjunction with the different silver powder metallurgy.
Evaluation of Test Protocol for Eutectic Die Attach Using High Power LEDs
Authors: Hartnett Amanda , Homer Seth , Beck Donald , Evans Daniel 
Published: October 2015

High-power semiconductor devices, such as high-brightness Light Emitting Diodes (LEDs), must be mounted using a robust adhesive material to handle the temperature fluctuations generated by the chip and the mechanical stresses due to the coefficient of thermal expansion (CTE) mismatches between the die material and substrate it is mounted to. The selected material must also comply with current legislation restricting manufactured products containing numerous materials including some that were historically popular in HB LED applications due to environmental concerns. Eutectic gold-tin (AuSn) materials meet these requirements, and process recommendations for their implementation will be presented in this paper.
Utilizing a Palomar Technologies die bonder, AuSn solder preforms and paste will be placed/dispensed and reflowed using a Pulsed Heat System (PHS). Evaluation methods comparing these means of eutectic die attach to a pre-plated AuSn die will be discussed. Technical generalizations will be detailed to explain the derivation of test methods as well as hypotheses of results.
“IC Packaging Trends Causing Concerns in Complete Flux Removal”
Authors: Brooks Rich 
Published: October 2015

The complete cleaning and removal of flux / soil residues under low profile components (especially flip-chip devices) are becoming more critical, especially as the conductor spacing’s decreases and the power increases. The reliability of the circuit can be greatly affected when residues are not completely removed.
Flip chip bump pitch and die size push packaging trends resulting in tighter and smaller spaces underneath the devices. A majority of flip-chip assemblers are using water soluble fluxes and they typically use only DI water to remove the flux residues. Because of the tighter spaces and increased I/Os, the complete removal of these water soluble flux residues are becoming more difficult. Due to the ionic nature of water soluble flux residues all residue must be removed to prevent a pathway for electrochemical migration and acceptable bonding of the underfill material.
To insure that all of the flux residues are being removed from under the package, cleaning chemistries must be used. Cleaning chemistries provide the polarity and hydrogen bonding forces needed to remove oxidized flux while lowering surface tension to improve penetration under the die. The cleaning agent design must also be matched with the cleaning equipment.
To completely remove flux residue under the IC packages, the cleaning equipment’s dynamic energy must also be studied, along with the cleaning chemistry. Additionally, both the cleaning chemistry and equipment must be matched up with the flux residue that is being removed. This paper will evaluate various cleaning chemistries and cleaning equipment that provide the best cleaning performance for very low package stand-offs and tighter pitch devices, as well as the different flux residues and process parameters.
Electro-migration Behavior in Micro-joints of Sn-57Bi solder and Cu Post Bumps
Authors: Murayama Kei , Sakai Taiji , Imaizumi Nobuaki , Higashi Mitsutoshi 
Published: October 2015

The bonding technique for high density Flip Chip(F.C.) packages requires a low temperature and a low stress process to achieve high reliability of the micro joining. Sn-Bi solder has been noted as a low temperature bonding material.
Electromigration behavior of Sn-57wt%Bi flip chip interconnection with Cu post bumps was investigated. The flip chip bumps used for this experiments consisted of Cu post formed with plating and Sn-57wt%Bi solder. Two types of under bump metal(UBM) of organic substrate were studied, that is, electroless Ni(6μm)/Au(0.5μm) on Cu pad and Cu pad. Electron flow to induce the electro-migration was from organic substrate side (Cu pad) to chip side (Cu post) with current density of 40000A/cm2 at 125 degree C. At both types of the UBM, Bi migrated and accumulated to the anode side (Cu post) and Sn migrated to the cathode side (substrate pad). Each interconnect resistance has increased to about 25% and 46% within 100 hours, respectively. However, after more than 3000 hours, they were stabilized.
With Ni/Au UBM pad, Cu3Sn/Cu6Sn5 intermetallic compounds (IMCs) were formed at the Cu bump side. And under the Bi layer Cu6Sn5/Ni-Sn compounds were formed. But we didn’t observe the failure like cracks or voids at the Ni layer.
With Cu pad, only Cu3Sn IMC at the Cu bump side and under the Bi layer Cu6Sn5/Cu3Sn compounds were formed after 4000 hours. Although the voids were observed at Cu3Sn/Cu interface, good electrical connection was obtained.
Quality and Reliability of 3D TSV Interposer and Fine Pitch Solder Micro-bumps for 28nm Technology
Authors: Banijamali Bahareh , Chaware Raghunandan , Ramalingam Suresh , Kim Myongseob 
Published: October 2015

Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting significant industry attention.
High density three dimensional (3D) interconnects formed by high aspect ratio through silicon via (TSV) and fine pitch solder micro bumps are presented in this paper. Different design/material related factors are evaluated during this study in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents some of the quality and reliability results as well as micro-bump and TSV resistance data. Furthermore, bake and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA.
Design and Process Implementation for Embedding Components
Authors: Solberg Vern 
Published: October 2015

Although the printed circuit has traditionally served as the platform for mounting and interconnecting active and passive components on the outer surfaces, companies attempting to improve product functionality and minimize space are now considering embedding a broad range of these components within the circuit structure. Both uncased active and passive component elements are candidates for embedding but the decision to embed components within the multilayer circuit structure must be made early in the design process. Some components are easy candidates for integrating into the substrate while other may involve more complex processes and will be difficult to rationalize. Although many of the discrete passive and active devices may remain mounted on the outer surfaces of the multilayer board, embedding passive components and one or more silicon based semiconductor elements within the inner layers of the subsrate will enable greater utilization of the circuit board structure. Benefits can include improved performance. For example, by embedding the uncased semiconductor element on an inner layer of the circuit vertically in-line with a related semiconductor package mounted on the outer surface, the conductor interface can be minimized. The close coupling of semiconductor elements will significantly reduces resistance, inductance and contributes to increasing signal speed.
This paper includes design guidelines, material selection and the use of micro-via build-up termination methodology for embedding and interconnecting miniature passive components; resistor, capacitor, inductor, discrete transistor elements and thinned semiconductor elements. Detailed process information and examples will be included to enable the product designer and manufacturing specialist to have a clear understanding of the principles for embedding and interconnecting components in an organic multilayer circuit board structure
Overview on Thermal and Mechanical Challenges of High Power RF Electronic Packaging
Authors: Yuan Cadmus , Kregting René , van Driel Willem , Gielen Sander , Xiao An , (Kouchi) Zhang G. Q. 
Published: October 2015

High Power RF electronics is one of the essential parts for wireless communication, including the personal communication, broadcasting, microwave radar, etc. Moreover, high efficient high power electronics has entered the ISM market, such as the power generator of microwave oven.
Power electronics requires a close co-development of digital-analog mixed circuit design, high power IC manufacturing technologies, and high power packaging design/process, in order to guarantee their performance and lifetime. In this paper, we overviewed our works on the packaging/assembly development of high power packages, including three parts: (1) Thermal simulation and die bond defect control (2) Mechanical integrity model for soft package heatsink implementation (3) Al wire multiphysics modeling and reliability of plastic power package.
Fully Additive Chip Packaging: Science or Fiction?
Authors: Oosterhuis Gerrit , van der Zon Ben , Maalderink Hessel , Dunias Par 
Published: October 2015

The current trend in IC packaging towards an ever increasing degree of integration, combined with a high level of production flexibility calls for novel approaches in manufacturing. To address these challenges in a flexible manufacturing setting, TNO investigated to what extend mask-less additive manufacturing (3D printing) can be applied to packaging of semiconductor components and systems.
The micro-stereolithography (μSLA) process has been applied to two different cases to assess its feasibility in creating integrated chip packages and interconnects. First, 2D interconnects based on conductive inks have been integrated into thin layers, manufactured using μSLA. In principle, this process allows building a 3D interconnect circuit on a layer-by-layer basis. A second approach is to build a fully functional, densely integrated system based on a 3D interconnect structure in μSLA resin (insulator) followed by global metallization and a trimming step. This approach allows creating almost free form interconnects integrated with functional properties in the package.
These process examples allow manufacturing of small series with complex, integrated packages. Therefore, to asses the industrial relevance, the cost-of-ownership of manufacturing with the μSLA process on 200 mm wafers is estimated as a comparison to wafer-level molding. It will be shown that, especially in cases where complex geometries, integrated functionality or small series are required, mask-less additive manufacturing enables novel manufacturing solutions at reasonable cost.