bluuebunny/crossref_metadata_2025_split huggingface dataset:
Embedded Chip Technology: Technologies, Applications and Future Developments
Authors: Boettcher Lars , Karaszkiewicz S. , Manessis D. , Ostmann A. 
Published: October 2015

Technology approaches for the embedding of active and passive components using printed circuit board materials and processing gained an increasingly high interest over the last years. The use of such technologies for industrial fabrication has attracted increasingly interest by manufacturers and commercial products have been released.
The realization of embedded modules is quite a robust process for different applications. Several approaches for a laminate based embedding of components were developed and implement into the manufacturing. An overview and status of the different methods and their advantages for specific applications will be given.
The process flow, yield and challenges of such technologies for miniaturized packages and modules will be presented briefly.
By nature of the process, extremely flat packages can be realized. The routing of electrical contacts from the embedded components to the top and bottom side of the package allows the fabrication of highly versatile package layouts. The flatness and freedom in design makes these packages ideal candidates for package on package stacking. The main focus of the presentation will be the discussion of different applications. Single and multi-component packages will be presented. Extensive reliability testing of single die packages was done in order to compare different material sets for embedding, but also to compare the reliability of such embedded die packages with conventional packages. In addition, new process developments targeting the embedding of ultra-fine pitch dies, with pad pitches below 100 μm, will be shown.
Manifold applications targeting e.g. medical and power electronic modules will be presented and their way of manufacturing will be described.
Recent developments focus on the use of such embedding technologies for the integration of high-power modules e.g. for automotive applications (Hybrid and eCars). Beside the integration of semiconductors, to achieve miniaturization and high robustness of such modules, also the use of organic substrates as an alternative to currently used direct copper bonded (DCB) boards is of high interest. The need to handle high current and to realize an excellent thermal management are the main challenges for these modules. The concepts and first results of these latest developments will be presented in detail.
Rozalia/Ron ok move from 2.5/3D to Passive 1-3-12.
Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers
Authors: Gallagher Michael , Kim Jong-Uk , Huenger Eric , Zoschke Kai , Lopper Christina , Toepper Michael 
Published: October 2015

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade.
Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature.
Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (&lt;0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state.
Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied.
Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.
Micromachined Snap-In Resonators
Authors: Stevens Colin , Dean Robert , Wilson Chris 
Published: October 2015

MEMS resonators have many applications, including micromachined gyroscopes, resonating pressure sensors and RF devices. Typically, MEMS resonators consist of a proof mass and suspension system that allows the proof mass motion in one or two directions. Micromachined actuators provide kinetic energy to the proof mass, usually at its resonant frequency. In the simplest resonators, the actuators are driven with an AC signal at or near the resonant frequency. In more complex resonators, the actuator-proof mass system is placed in an amplifier feedback circuit so that the electromechanical system self-resonates.
MEMS parallel plate actuators (PPAs) are simple to realize, yet complex nonlinear variable capacitors. If a DC voltage is applied in attempt to move the proof mass greater than 1/3 of the electrode rest gap distance, the device becomes unstable and the electrodes snap into contact. A current limiting resistor is often placed in series with the PPA to limit short circuit current due to a snap-in event.
Consider the effect of placing a large resistor, on the order on 10 meg-Ohms, in series with the PPA. Then apply a DC voltage across the resistor-PPA pair of sufficient voltage to cause snap-in. Once the electrostatic force (ES) exceeds the spring force (SF), the electrodes will accelerate toward each other. The capacitance between the electrodes swells as the separation distance shrinks. Since the large resistor limits the charging rate of the capacitor, the voltage across it drops. Once the SF exceeds the EF, the momentum of the movable electrode brings it into contact with the fixed electrode, discharging the capacitor. The movable electrode then accelerates away from the fixed electrode while the resistor slowly allows recharging. After recharging, the cycle repeats resulting in stable oscillation. This resonator requires only a DC power supply, a resistor and a MEMS PPA.
Ultra-fine pitch Package on Package solution for high bandwidth mobile applications
Authors: Katkar Rajesh , Zhao Zhijun , Zhang Ron , Co Rey , Mirkarimi Laura 
Published: October 2015

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint.
BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.
Multi-scale materials data for 3D TSV stack performance simulation and model validation
Authors: Zschech Ehrenfried , Yeap Kong Boon , Sander Christoph , Mühle Uwe , Sukharev Valeriy 
Published: October 2015

Within a DFM type of methodology, the application of physics-based models for a multi-scale simulation of mechanical stress in 3D TSV-stacked products was proposed in [1]. Highly accurate multi-scale materials data are needed as input for this approach of simulation and for model validation.
This paper focuses on the set of materials data for wafer-level and package-level structures, needed to feed a materials database that comprises the input parameters for simulation. Particularly the generation of materials data such as (local and effective) Young's modulus, Poisson ratio and (effective) coefficients of thermal expansion (CTE) on several scales will be described. The nanoindentation method was developed further to measure local and effective elastic modulus values and Poisson ratio for micro-bump, TSV and BEoL stacks. TCAD simulations show significant influence of the copper microstructure on the charge carrier mobility in transistors [2]. To consider the orientation dependence of elastic properties of copper, nanoindentation with extremely low penetration depths was applied. A high-resolution in-situ technique was developed to determine “composite CTE” values for BEoL stacks. A free-standing cantilever containing the region of interest was extracted using the FIB technique, and imaged in a SEM at several temperatures.
For model validation and calibration, local stress measurements are needed to determine the effect of the TSV/package-induced stress on the transistor performance. Due to the high resolution needed, the only direct technique to measure strain in transistor channels is TEM. For the first time, the strain in transistor channels will be reported as a function of the distance from the TSV, based on Convergent Beam Electron Diffraction (CBED) data.
A Versatile Optical Head for 3D IC TSV Integration Process Control
Authors: Fresquet G. 
Published: October 2015

3D Integration of miniaturized systems at wafer level generates new needs of metrology and defects inspection for the control of TSV geometries, temporary wafer bonding, wafer thinning, via interconnects technology and of wafer/die stacks. In this paper we demonstrate the capabilities of a versatile optical measurement system combining several microscopy and interferometry techniques in the visible and near infrared wavelength range.
I. INTRODUCTION AND BACKGROUND
ALL roadmaps predict a large spread of 3D heterogeneous integration technologies for the fabrication of miniaturized systems in the coming years1. Beside a large development of new fabrication processes, 3D integration generates new challenges in terms of metrology and defects inspection for wafer/die bonding, thinning and interconnection processes as well as for 3D architectures. Adaptation and/or combination of existing techniques and the development of new techniques become necessary in order to perform non destructive, fast and inspections or quantitative measurements on large area wafers with high lateral and vertical resolutions. In this work we describe results obtained with an optical system combining several microscopy and interferometry techniques.
Ultra High Density Capacitors merged with Through Silicon Vias to enhance performances.
Authors: Bunel Catherine 
Published: October 2015

IPDIA presents itself as the 3D Silicon leader providing innovative platforms for customers who want to demonstrate technological concepts based on Through Silicon Vias.
The market segments Medical, Lighting, and Industrial addressed by the Ipdia Technology are adopting 2.5-D and 3-D technologies to increase the performance and density of their devices through the use of silicon interposers and through-silicon vias (TSVs).
The via last approach developed by IPDIA allows large possibility of integration combining TSV with active or passive devices such as High-density trench capacitors, MIM capacitors, Resistors, High-Q inductors or Zener diodes .
The purpose of this paper is to focus on through-silicon via (TSV) combined with IPD , providing an interposer which could have two surfaces with devices. Emphasis is placed on 3D trench capacitor technology with an update of the roadmap .Examples of applications using chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) are briefly presented. Some important results and recommendations are summarized: the process steps for passive devices interposer /TSV/redistribution layer (RDL)/microbumps /, the design rules .A comparison between TSV on active chips and passive interposer with TSV will be detailed.
3D Packaging- Synthetic Quartz Substrate and Interposer for High Frequency Applications
Authors: Stygar Vern , Mobley Tim , Takahashi Shintarou 
Published: October 2015

Glass for use as an Interposers with through vias (TGV) are emerging as the next generation substrates for die level and wafer level packaging substrates. This need is being driven increasing number of interconnects, desire to have a KGD (known good die) at the wafer level package (WLP), high electrical/thermal conductivity vias, and hermeticity between the PWB and the die, while being cost competitive with a TSV passive interposer. These TGV characteristics translate to longer battery life, higher yield at the end user applications, and an optimized WLP solution that not require silicon processing foundries to fabricate a passive interposer.
The next generation of communication devices will operate at much higher frequencies to allow video on demand and video vis a vis communication. Coupled with multiple frequencies, to facilitate a phone to work with GSM, CDMA and other communication schemes require multiple filter and low noise amplifiers.
This paper will describe work done with Alkali free, copper filled (not plated) hermetic vias that are both low cost and provide engineering design flexibility for the more advance low cost personal handheld devices.
CoC (Chip on Chip) or FtoF (Face to Face) - PossumTM Technology for 3D MEMS and ASIC eliminating the need of TSV or Wire Bonding
Authors: Sutanto Jemmy , Kang D. H. , Yoon J. H. , Oh K. S. , Oh Michael , Lanzone R. , Huemoeller R. 
Published: October 2015

This paper describes the ongoing 3 years research and development at Amkor Technology on CoC (Chip on Chip)/FtF (Face to Face) – PossumTM technology. This technology has showed a lot of interests from the microelectronics customers/industries because of its various advantages, which include a) providing smaller form factor (SFF) to the final package, b) more functionalities (dies) can be incorporated/assembled in one package, c) improving the electrical performance - including lower parasitic resistance, lower power, and higher frequency bandwidth, and d) Opportunity for lower cost 3D system integration. Unlike other 3D Packaging technology (e.g. using TSV (Through Silicon Vias)) that requires some works in the front stream (wafer foundry) level, needs new capitals for machines/equipments, and needs modified assembly lines; CoC/FtF technology uses the existing flip Chip Attach (C/A) or TC (Thermal Compression) equipment/machine to perform the assembly joint between the two dies, which are named as the mother (larger) die and the daughter (smaller) die. Furthermore, the cost to assemble CoC/FtF is relatively inexpensive while the applications are very wide and endless, which include the 3D integration of MEMS and ASIC.
The current MEMS packaging and test cost contributes about 35 to 45% to the overall MEMS unit cost. WLC (Wafer Level Capping) with wire bonding have been widely used for mass production for accelerometer (e.g. ADI and Motorola), gyroscope (e.g. Bosch and Invensense), and oscillator /timer (e.g. Discera). The WLC produce drawbacks of a large form factor and the increase in the capacitive and electrical resistances. Currently, the industries have been developing a new approach of 3D WLP (Wafer Level Packaging) by using a) TSV MEMS cap with wire bonding (e.g. Discera), b) TSV MAME cap with solder bump (e.g. Samsung, IMEC, and VTI), and c) TSV MEMS wafer/die with cap (e.g. Silex Microsystems). The needs of TSVs in the 3D WLP will add the packaging cost and reduce the design flexibility is pre-TSV wafer is used.
“Amkor CoC/FtoF – PossumTM” is an alternative technology for 3D integration of MEMS and ASIC. CoC/FtoF – PossumTM does not require TSV or wire bonding; Miniaturizing form factor of 1.5 mm x 1.5 mm x 0.95 mm (including the package) of MEMS and ASIC can be achieved by using CoC/FtoF – PossumTM while Discera's design of 3D WLP requires substrate size &gt; 2 mm x 2 mm. CoC/FtoF – PossumTM will likely produce packaging cost which is lower than WLC or 3D WLP – TSV at the same time the customer is benefited from smaller FF and reduced electrical/parasitic resistance. CoC/FtoF – PossumTM can be applied to any substrates including FCBGA and laminate. This technology also can be applied to package multiple MEMS microsensors, together with ASIC, microcontroller, and wireless RF to realize the 3D system integration.
Fabrication of 3D-IC Interposers
Authors: Keech John T. , Piech Garret , Pollard Scott 
Published: October 2015

Interposer fabrication has gained a lot of attention in the area of three-dimensional integrated circuit (3D-IC) integration. Glass has many properties that make it well suited for interposer substrates, such as adjustable coefficient of thermal expansion, advantaged electrical properties and unique forming processes. Furthermore, glass based solutions can also provide significant cost advantages in substrate material, via formation, and subsequent processing.
In this paper, we will cover how fusion formed glass provides cost-effective solutions for the manufacturing of interposer substrates. Leveraging the ability to create through-glass-via (TGV) substrates in as-formed 100 μm thick precision glass, with a pristine surface, can avoid the need for back grinding and polishing operations. This has the potential to eliminate several manufacturing steps for polishing and thinning, while providing associated cost savings.
Significant progress has been made in demonstration of TGV technology. Fully populated wafers with 100,000s of through or blind holes (≥ 25 μm diameter) are fabricated today, and 10–20 μm diameters are in development. We will report on important quality parameters measured on TGV wafers and positive implications with respect to product quality and strength. The ability to leverage industry metallization techniques and performance characteristics will also be reported. Finally, we will discuss opportunities to leverage cost-effective glass interposer solutions.
Through Si Vias Using Liquid Metal Conductors for Re-workable 3D Electronics
Authors: Hernandez George A. , Martinez Daniel , Patenaude Stephen , Ellis Charles , Palmer Michael , Hamilton Michael 
Published: October 2015

This paper describes the design and fabrication of liquid metal interconnects (vias) for 2.5D and 3D integration. The liquid metal is gallium indium eutectic with a melting temperature of approximately 15.7°C that is introduced into via openings of a silicon interposer. This liquid interconnect technology can be integrated with existing interposer technologies, such as capacitors and traditional (solid metal) through-silicon vias (TSVs). In addition, liquid metal interconnects can better accommodate thermal stresses and provide re-workability in case of chip failure.
Our research efforts are focused on the integration of multi-chip modules using liquid metal interconnects. Our study encompasses Direct Current (D.C.) measurements and failure analysis using snake and comb structures at low temperature (10 degrees Kelvin) to slightly above room temperature (300 degrees Kelvin). The snake and comb structure allows us to measure electrical shorts and opens, as well as provide estimates of via yield and allows additional information for determination of possible failure mechanisms.
In order to make electrical contact to the liquid metal interconnect interposer from both the top and bottom, test coupons have been fabricated with arrays of large numbers of vias. The interposer structure consists of a thin (200 um thick) silicon wafer with via holes filled with liquid metal. The test coupon consists of bottom and top silicon die with a thickness of 500 um. The bottom wafer incorporates a 2 um-thick daisy-chain metallization and 100 um copper tall vias, which are electrically isolated from each other and the underlying Si by patterned AL-X dielectric. The top wafer incorporates an array of 80 um tall, electroplated copper pillars and top daisy-chain metallization. Liquid metal containment mechanisms and structures have also been investigated.
In our presentation we will describe the design, fabrication and characterization of this re-workable interposer with liquid metal interconnects. We will present D.C. resistance and X-ray imagery of the liquid metal filled via. In addition, we will provide failure analysis of via yield per chip.
The Role of Extreme Agitation in Accelerating the Removal Rate of Advanced Packaging Photoresists
Authors: Sobhian Mani 
Published: October 2015

Negative Dry Film and Negative Spin-On photoresists are widely adopted as the prime choice in wafer-scale packaging processes such as bumping, TSV, and copper pillars.
High transparency of negative resist produces vertical profiles with no footing at low exposure energy, resulting in a robust, high throughput lithography process (Doki, 2005).
In plating applications, the 3-D cross-linking of negative resist provides good adhesion to wide range of substrates, enabling high-current ECD processes with high throughput.
The main challenge of negative photoresist has always been its removal difficulty. Aggressive remover chemistries consisting of DMSO, NMP, and TMAH have been used to cleave, swell, and dissolve the material (Moore, 2002).
This paper demonstrates the capabilities of a novel immersion-based strip technology that maintains a constant boundary layer at the wafer surface by providing high-speed agitation to each individual wafer. Results show an acceleration of the removal process, while reduced exposure to remover chemistries reduces risks of bump corrosion.
Removal rates of negative dry film and negative spin-on resist materials have been studied across variety of commercially available strip chemistries.