bluuebunny/crossref_metadata_2025_split huggingface dataset:
Long-Term Protective Effect of N-Acetylcysteine against Amikacin-Induced Ototoxicity in End-Stage Renal Disease: A Randomized Trial
Authors: Vural Alperen , Koçyiğit İsmail , Şan Furkan , Eroğlu Eray , Ketenci İbrahim , Ünal Aydin , Tokgöz Bülent , Ünlü Yaşar 
Published: November 2017

Background The aim of the study is to evaluate the long-term protective effect of N-acetylcysteine (NAC), an antioxidant agent, against aminoglycoside (AG)-induced ototoxicity. Methods A total of 40 patients receiving continuous ambulatory peritoneal dialysis (CAPD) and having their first peritonitis attacks and planned to be treated with AGs were enrolled in the study. They were randomized into 2 groups: 1 group received additional NAC and the other did not. All patients underwent hearing tests with pure tone audiometry (PTA) after the diagnosis, at 1 month and 12 months and at the same time the tumor necrosis factor (TNF)-α and interleukin (IL)-6 levels were measured. Results Patients taking NAC had better hearing test results in both ears at 1 month except 2,000 Hz for the left ear, which wasn't significantly different between the 2 groups. Although patients taking NAC had generally better PTA results at 12 months, differences between the 2 groups were not statistically significant. Baseline IL-6 level was significantly higher in the NAC group than the control group. Both TNF-α and IL-6 levels at 1 month were significantly lower in the NAC group than in the control group. On the other hand, there was no significant difference between the 2 groups in terms of TNF-α and IL-6 levels at 12 months. Conclusions The results of the current study showed that NAC, a potent anti-inflamatory drug, may be otoprotective, but that the effect is not long-lasting.
H2 Ortho-to-para Conversion on Grains: A Route to Fast Deuterium Fractionation in Dense Cloud Cores?
Authors: Bovino S. , Grassi T. , Schleicher D. R. G. , Caselli P. 
Published: November 2017

Abstract
Deuterium fractionation, i.e., the enhancement of deuterated species with respect to non-deuterated ones, is considered to be a reliable chemical clock of star-forming regions. This process is strongly affected by the ortho-to-para H2 ratio. In this Letter we explore the effect of the ortho–para (o–p) H2 conversion on grains on the deuteration timescale in fully-depleted dense cores, including the most relevant uncertainties that affect this complex process. We show that (i) the o–p H2 conversion on grains is not strongly influenced by the uncertainties on the conversion time and the sticking coefficient, and (ii) that the process is controlled by the temperature and the residence time of ortho-H2 on the surface, i.e., by the binding energy. We find that for binding energies between 330 and 550 K, depending on the temperature, the o–p H2 conversion on grains can shorten the deuterium fractionation timescale by orders of magnitude, opening a new route for explaining the large observed deuteration fraction D
frac in dense molecular cloud cores. Our results suggest that the star formation timescale, when estimated through the timescale to reach the observed deuteration fractions, might be shorter than previously proposed. However, more accurate measurements of the binding energy are needed in order to better assess the overall role of this process.
Stencil Print solutions for Advance Packaging Applications
Authors: Vallabhajosyula Phani 
Published: November 2017

Abstract
This paper address two significant applications of stencils in advance packaging field: 1. Ultra-Thin stencils for miniature component (0201m) assembly; 2. Deep Cavity stencils for embedded (open cavity) packaging.
As the world of electronics continues to evolve with focus on smaller, lighter, faster, and feature-enhanced high-performing electronic products, so are the requirement for complex stencils to assemble such components. These stencil thicknesses start from less than 25um with apertures as small as 60um (or less). Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, step stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and the pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 15um–40um with steps of 15um are used to obtain desired print volumes. Stencils with thickness to this order can be potential tools even to print for RDLs in the package.
Cavity technology can be an effective solution in reducing the total assembled PCB thickness (Z-height), most importantly, on designs utilizing taller - stacked devices. Traditionally, dipping process or dispensing process was used to deposit solder paste, flux, or glue on uneven surfaces. However, this takes a longer time when compared to printing using a stencil printer. Reservoir printing using a stencil printer has greater potential in such application. Extensive work has been done in the past to print glue, solder paste and/or flux into cavities using reservoir printing. This paper focuses on printing solder paste into multiple cavities (stencil pockets) with depths ranging from 355 microns to 450 microns, and with varying cavity size, wall angles and various stencil thicknesses ranging from 100 microns to 150 microns. Apertures varying in area ratio were placed in these cavities and experiments were conducted to analyze the print performance of the stencils. As the size of the components and boards/substrates gets smaller - closer placement of components to the cavity (stencil pocket) walls needed to be assessed as well.
These applications, the associated stencil design and print results were discussed in detail in this paper.
Rapid Prototyping Tape Stencils for the Application of Solder Paste
Authors: Yang Mimi X. , Dowling Karen , Senesky Debbie , Wong H.-S. Philip 
Published: November 2017

Abstract
This works describes a promising method for rapid prototyping tape stencils for the application of solder paste. This process is appropriate for research settings requiring developmental flexibility and the ability to deal with small device dies. This work compares the volume of solder paste deposited versus aperture volume for several common tape materials and several common printed circuit board (PCB) stencil materials. The solder deposits are then reflowed to identify which aperture and solder paste parameters can generate successful solder bumps. Electrically conductive solder bonds for small bond pads (100 μm and larger) are demonstrated between silicon device dies and glass dies using this process.
High Current Testing and Simulation for Land Grid Array Sockets
Authors: Beaman Brian , Audet Jean 
Published: November 2017

Abstract
Land grid array (LGA) sockets are commonly used for industry standard and custom microprocessors to meet the increased performance challenges for a variety of server applications. Along with the need for increased high speed signaling capabilities comes the challenge to support lower voltages and higher currents. Typical testing that is conducted by the LGA socket suppliers does not provide an accurate assessment of the maximum current capabilities in a real product application due to the test card design and construction limitations. Typical test card designs use daisy chain connections to wire multiple LGA socket contacts in series. The daisy chain wiring in the test card adds to the resistive heating and results in an inaccurate maximum current rating. Also, the test cards typically do not have a cross section construction that is representative of a real product application with multiple ground planes that provide improved thermal dissipation of the heat generated by the LGA socket interface.
Hardware testing was conducted to better understand the performance limitations for a new product application. The test card was designed to use multiple voltage and ground planes in the circuit card cross section to provide a low impedance path for current flow and a low voltage drop through the LGA socket interface. In addition to the test card construction, the test hardware included a special test module with a shorted chip to provide a more accurate power distribution path through the socket and processor package. The test variables included different plating metallurgy options for the LGA socket and the processor module along with different configurations for the voltage supply and ground return contacts. Electrical and thermal modeling techniques were used to simulate the test hardware configuration with good correlation between the hardware and modeling results. Based on the positive correlation results, additional modeling was conducted to simulate the worst case power mapping conditions for the processor chip along with a more accurate power distribution. The additional modeling results provided further insights into the maximum current capabilities for the LGA socket based on the temperature increase from the resistive heating in the socket contacts.
Relation between relative humidity and electrical performance of electrochromic displays
Authors: Garcia Alexandre , Jin Huiting , Olafsen Kjell , Kolberg Sigbjørn , Wright Daniel Nilsen , Visser Taklo Maaike M. , Eveborn Annelie , Hagel Olle , Eriksson Torbjörn 
Published: November 2017

Abstract
Electrochromic displays are among the key components of smart tags and their performance, defined by the color switch time, is directly linked to the level of humidity inside the displays. A time-efficient procedure, based on the use of a gravimetric moisture analyzer, was implemented, where the water content in a display could be related to the temperature and relative humidity of the manufacturing environment. The electrical performance of the displays was evaluated by measuring current as a function of time during voltage pulses of 4 s as these measurements quantified the time needed for color switch (should be &lt; 1 s). The electrical performance was also measured as a function of the temperature and relative humidity of the manufacturing environment. By varying the temperature and the relative humidity systematically and measuring water content and display performance, a correlation between water content, switch time and manufacturing environment could be established and a safe range for manufacturing conditions could be found.
3D Printed Integrated Microfluidic Cooling for High Power RF Applications
Authors: Craton Michael , Ghazali Mohd Ifwat Mohd , Wright Brian , Park Kyoung Youl , Chahal Premjeet , Papapolymerou John 
Published: November 2017

Abstract
This paper presents the design and fabrication of microfluidic channel integration in a plastic substrate using 3D printing. The microfluidic channels are integrated along with a copper plate which the coolant is in direct contact with. To demonstrate the design, a diode intended for switched power supplies is integrated onto the copper plate and its performance characterized. 3D printing or additive manufacturing (AM) allows for fast prototyping of such package designs and can be readily adopted in the fabrication of RF circuits. This paper, to the best of our knowledge, for the first time will demonstrate a 3D printed integrated microfluidic channel for the cooling of electronic circuits. Details of design, fabrication and characterization are presented.
Journey to Success for New Analog Technologies for Texas Instruments
Authors: Magaña Mario , Chatterjee Basab , Javier Rey 
Published: November 2017

Abstract
TI's commitment to meeting customer requirements has resulted in the development of package technologies and process to improve performance and higher power at lower cost for wire-bonded packages and automotive products are requiring more stringent reliability requirements.
Some of the strategies we have adopted include using thinner metal and low-K ILD for lower parasitics and higher performance, thick copper routings for higher power and larger wafer diameters and smaller scribe streets for lower cost and using Copper (Cu) wire. Cu wire is a key enabler due to higher electrical conductivity and lower cost than gold), but also poses integration challenges due to hardness, CTE mismatch and corrosion susceptibility. The hardness of the copper wire imposes significant challenges for wire-bonding on pads w thin metal and low-k ILD. This required co-design of die bond pad structure for enhanced reliability as well as Cu wire process development requires comprehensive approach encompassing multiple areas including ball and stitch parameters, capillary design, bonding processes like segmented bonding and validation of process margins using ‘hammer’ test. Copper wire also requires metrology and test/detection tools like Nomarski, stitch pull test in addition to the traditional wire pull at mid span and neck, rapid-bake test, measuring intermetallics & Al remaining under ball, and Al-splash. The susceptibility of Cu wire to corrosion required us to introduce new materials like PCC and Au-flash PCC, tight environmental controls in the form of forming gas, monitoring of Ph and ion-trappers in BOM, wire oxidation check at outgoing/incoming inspection as SERA (Sequential Electrochemical Reduction Analysis), and paying close attention to handling and non-process gases. More stringent qualification requirements like AEC-006 is driving additional changes to lead frame design and finish, selection of EMC and Die attach, to reduce delamination and epoxy bleed-out.
The demands for lower cost is driving us to use larger sized wafers (like 300mm) and narrower scribe width, while packing more functionality into smaller dies thereby driving higher metal densities. Additional requirements for thinner and 3D packages requiring post backgrind thickness as low as 50–75um imposing challenges in terms of warpage and saw. The demand for higher power applications is requiring us to use thick copper routings. We have developed test structures and redesigned layout of the scribe street and scribe seal and pursuing new saw methods. We have also learned many lessons in terms of handling and corrosion risks and implemented safeguards in terms of process and material selection.
Reduction of Thermal Stress - Part II: Passivation Thickness Optimization of FLATPV Surface Bump Design
Authors: Sethu Raj Sekar , Kulkarni Salil Hari , Ha How Ung , Soon Kok Heng 
Published: November 2017

Abstract
Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material. The flat passivation design can reduce the chip package interaction for underfill material but it needed to be evaluated numerically for wafer level stress before being touted as a solution towards reducing passivation cracks. In Part II of this series of papers, the flat passivation layer thicknesses were numerically simulated and modified using response surface methodology design of experiments (RSM DOE) techniques. The optimized passivation layer thickness showed decreased stress which was validated using a simulation confirmation run.
Operation of Silicon Carbide Integrated Circuits under High Temperature and Pressure
Authors: Barlow M. , Francis A. M. , Holmes J. 
Published: November 2017

Abstract
Silicon carbide integrated circuits have demonstrated the ability to function at temperatures as high as 600 °C for extended periods of time. Many environments where high temperature in-situ electronics are desired also have large pressures as well. While some validation has been done for high pressure environments, limited information on the parametric impact of pressure on SiC integrated circuits is available. This paper takes two leading-edge SiC integrated circuit processes using two different classes of devices (JFET and CMOS), and measures the performance through temperature and pressure variation. Circuit functionality was verified at high temperature (475 °C) as well as high pressure (1700 psig).
Solderability and Reliability Evolution of No-Clean Solder Fluxes For Selective Soldering
Authors: Guéné Emmanuelle , Anisko Richard , Puechagut Céline 
Published: November 2017

Abstract
Flux consumption for wave soldering tends to decrease, mainly due to its gradual replacement by reflow soldering methods (i.e. pin-in-paste) in many electronics applications. However, in several cases, wave soldering still remains a must, with an increasing share of “selective” soldering processes, either using wave frames with dedicated apertures or solder fountains. Such processes are more challenging for the fluxes in terms of reliability under operation, since some chemistries remaining on the printed circuit boards after soldering may promote corrosion. Thus, flux manufacturers had to adapt their formulations to minimize such issues while keeping an efficient activation level, with several types of alloys (tin-lead, tin-silver-copper and low/no-silver) and associated with the numerous types of finishes encountered.
The paper will cover the types of flux used in the electronic industry according to their chemistry and activation level (rosin-based, halides, alcohol-based or water-based flux…), and their characteristics with reference to standards. The limits of current standards will be discussed in regards to the last generation solder fluxes.
Then, the development of two low-residue new generation fluxes, an alcohol-based flux and a true VOC-free flux, will be described, according to requirements: the lab tests results (surface tension, spread tests, wettability tests…) will be presented and discussed. Reliability will be especially investigated through surface insulation resistance, electro-chemical migration test, ionic contamination as well as Bono tests to determine the candidates able to provide high processability combined with chemical inertness of residues. Finally, the performance of flux will be assessed through customer tests, involving several types of boards, finishes and different solder alloys and wave equipment.
Characterizations of Fan-out Wafer-Level Packaging
Authors: Li Ming , Li Qingqian , Lau John , Fan Nelson , Kuah Eric , Kai Wu , Cheung Ken , Li Zhang , Tan Kim Hwee , Xu Iris , Chen Dong , Beica Rozalia , Ko CT , Yang Henry , Lim Sze Pei , Ran Jiang , Xi Cao 
Published: November 2017

Abstract
The calling for smaller form factor, higher I/O density, higher performance and lower cost has made fan-out wafer level packaging (FOWLP) technology the trend. Good control of die position accuracy and molded wafer warpage are some of the keys to achieve high-yield production for FOWLP. In this study, 10mm×10mm test chips were fabricated and attached (chip-first and die face-up) onto 12 inch glass wafer carriers using die-attach-film (DAF). These reconfigured wafers were compression-molded with selected epoxy molding compounds (EMC). Cu bumps (contact-pads) were revealed by grinding, and redistribution layers (RDLs) were fabricated by lithography and electroplating process. The fan-out wafers were evaluated and characterized after each process step with main focus on the die-misplacement/die shift, re-configured wafer warpage, compression molding defects and RDL fabrication defects. The root causes of these defects were investigated and analyzed, while the possible solutions to overcome the defects were proposed and discussed.
Effective Inspection Methods for Advanced Packaging Technologies
Authors: Brueckner Julia , Schwander Michael , Jurgschat Moritz , Tuason Ramon 
Published: November 2017

Abstract
Advanced packaging technologies have ramped up to provide solutions for new high density devices that are based on the integration of several components with different functions. The need for thin packages with memory, APU, modem and analog all packed in one requires each individual layer thickness to have exacting specifications. In this work we concentrate on the challenging task of measuring epoxy mold compound (EMC) thickness distribution across the wafer. We will present how an optical sensor based on spectral coherence interferometry (SCI) can be utilized to collect critical measurements related to mold thickness, uniformity and height information between bumps and the mold surface. SCI provides an optical, non-destructive, high-throughput solution to measure mold thickness and surface warpage simultaneously. This is done by utilizing a sensor with high numerical aperture (NA) which enables one to measure layers and surfaces of mold materials despite the usual measurement constraints introduced from high roughness values, high internal scattering, and severe wafer warpage. By adding a bottom sensor in a so called twin-configuration, further simultaneous data collection is possible.
Photoresist Residue Detection in Advanced Packaging
Authors: Cohen Jonathan , Han Woo Young , Singh Gurvinder , Best Keith , Shay Amy , Marshall Mike 
Published: November 2017

Abstract
Semiconductor manufacturers are continuously driving efforts to put more computing power and speed into less volume. At the same time, consumers are demanding devices with more functionality that integrate a variety of interconnected circuit types. The result has been an increasing reliance on advanced packaging technologies that use fab-like processes to integrate multiple chips and to provide the increased I/O capability required. With continued focus on device miniaturization, the rapid detection of trace chemical residue during intermediate processing steps becomes increasingly difficult. In the lithography area, detection of polymer residue on wafer surfaces presents special opportunities. One area of opportunity for the detection of lithographic polymer residue takes advantage of the fact that these materials possess unique optical properties not found in metals or other inorganic materials used in semiconductor manufacturing. Rudolph Technologies has submitted patent applications for a novel defect illumination technique that offers key advantages over traditional white light inspection. This paper will present the results of using this inspection technique for the detection of photoresist residue on test wafers as well as on actual customer devices. Sample data included herein are representative of advanced packaging technology used today by a wide range of semiconductor manufacturers and OSAT facilities. While this novel inspection technique will not be a panacea for all trace residue detection problems, it offers a method complementary with bright field or dark field inspection when these two traditional inspection methods lack the sensitivity required.