bluuebunny/crossref_metadata_2025_split huggingface dataset:
EXCITATION OF COUPLED STELLAR MOTIONS IN THE GALACTIC DISK BY ORBITING SATELLITES
Authors: D’Onghia E. , Madau P. , Vera-Ciro C. , Quillen A. , Hernquist L. 
Published: May 2016

ABSTRACT
We use a set of high-resolution N-body simulations of the Galactic disk to study its interactions with the population of cosmologically predicted satellites. One simulation illustrates that multiple passages of massive satellites with different velocities through the disk generate a wobble, which has the appearance of rings in face-on projections of the stellar disk. They also produce flares in the outer disk parts and gradually heat the disk through bending waves. A different numerical experiment shows that an individual satellite as massive as the Sagittarius dwarf galaxy passing through the disk will drive coupled horizontal and vertical oscillations of stars in underdense regions with small associated heating. This experiment shows that vertical excursions of stars in these low-density regions can exceed 1 kpc in the Solar neighborhood, resembling the recently locally detected coherent vertical oscillations. They can also induce non-zero vertical streaming motions as large as 10–20 km s−1, which is consistent with recent observations in the Galactic disk. This phenomenon appears as a local ring with modest associated disk heating.
Quartiers et effets de quartier. Analyse de la variabilité de la taille des quartiers perçus dans l’agglomération parisienne
Authors: Vallée Julie , Le Roux Guillaume , Chauvin Pierre 
Published: May 2016

Cet article propose de discuter des approches rigides et standardisées du quartier qui prévalent dans les études sur les « effets de quartier ». En étudiant les zones que plus de 650 habitants de l’agglomération parisienne (enquête SIRS « Santé, Inégalités et Ruptures sociales ») définissent comme étant leur quartier de résidence, il s’agit d’abord d’analyser comment la taille des quartiers perçus varie selon la morphologie urbaine et sociale des espaces résidentiels mais aussi selon le profil sociodémographique des habitants et leurs rapports au quartier. Après avoir constaté que les habitants de Paris intra-muros et des espaces socialement favorisés perçoivent leur quartier comme une zone sensiblement plus étendue que les autres habitants, l’idée est de souligner les erreurs de quantification et d’interprétation des effets de quartier auxquels s’exposent les études lorsqu’elles considèrent les quartiers comme des unités spatiales de taille constante (mailles administratives ou zones circulaires) et négligent ainsi les capacités différenciées des populations à s’approprier leur quartier de résidence.
Flip-chip Bonded SiC Power Devices on a Low Temperature Co-fired Ceramic (LTCC) Substrate for Next Generation Power Modules
Authors: Seal Sayan , Glover Michael D. , Mantooth H. Alan 
Published: May 2016

Abstract
This paper explores the design and performance benefits of an LTCC-based power module using SiC power devices. The goal of the design is to achieve high power density with an improved level of reliability as compared to the state-of-the-art, especially at elevated operating temperatures. This will enable a more complete leveraging of the benefits of SiC semiconductor technology. The reliability of existing power modules under high thermo-mechanical stress is adversely affected by the presence of wire bonds and by delamination at the die attachment interface between the die and substrate. As power devices are driven at higher frequencies, wire bonds will inhibit performance by introducing ringing and large overshoots due to the parasitic inductances they introduce in the critical switching loops in the circuit. A flip-chip bonding process for bonding the power devices has been investigated in this paper as an alternative to wire-bonding. It was found that flip-chip interconnects not only improved the switching characteristics of the device, but also reduced thermo-mechanical stresses on the bonding interface.
Degradation Analysis of TO-247 Package SiC-MOSFETs Subjected to High Temperature Storage and Heavy Thermal Cycle Test
Authors: Araki Sawa , Suzuki Tatsuhiro , Yamashita Mari , Tanimoto Satoshi , Ono Toshiaki , Yakumaru Hisashi , Sawada Hiroki 
Published: May 2016

Abstract
Three types of TO-247 package SiC-MOSFETs, denoted as A, B and C and fabricated by different manufacturers, were subjected to thermal cycle tests (TCT) ranging from −40°C to 200°C and a high temperature storage test (HTST) at 200°C in air. Their reliability was continuously investigated based on electrical characterizations, X-ray inspection and scanning acoustic tomography (SAT). Intermittent SAT observation revealed that, regardless of the device type, the epoxy resin (encapsulant) first peeled on the Cu die pad around the outer edge of the SiC power die and then peeling rapidly spread outward as the number of thermal cycles or storage time increased. The number of cycles or storage time differed depending on the device type (manufacturer). Subsequently, further peeling occurred on the SiC die and the devices failed or showed instability. The deterioration pattern tended to differ somewhat between the TCT and HTST. Uplift of the die attachment was observed for device A after thermal storage for 1000 hours.
Internal Structure Refinement of Porous Sintered Silver via Electromigration
Authors: Mansourian Ali , Paknejad Seyed Amir , Wen Qiannan , Khtatba Khalid , Zayats Anatoly V. , Mannan Samjid H. 
Published: May 2016

AbstractAtoms can move under high stress conditions such as temperature, mechanical pressure or electric current. Electromigration provides a driving force to move the atoms in metals conducting current usually resulting in the accumulation of atoms and void formation in anode and cathode respectively. The electromigration effect is normally considered a serious problem for electronic circuits but the recent works1–7 show that it can be used constructively for controlled fabrication of nanostructures2–4.We demonstrate that electromigration can be utilized to refine the porous structure of a sintered silver stripe leading to transformation of the internal pore and grain structure. The results show that pore shape, size and distribution are significantly changed after electromigration. Similarly, we have used the electromigration effect to mass produce nanorods under current densities of the order of 2.4 ×10+8 A/m2. Nanorods were formed across the whole stripe contrasting with studies on non-porous substrates which show nanorod production at the anode only. The results show the internal pore structure can be transformed and refined by electromigration. The results also suggest that by controlling current densities in a porous substrate, complex patterns of porous structures and high-quality single crystal nanorods can be formed in-situ with significant advantages over competing methods of nanorod formation for sensor applications.
HOT-300 – A Multidisciplinary Technology Approach Targeting Microelectronic Systems at 300 °C Operating Temperature
Authors: Vogt Holger , Altmann Frank , Braun Sebastian , Celik Yusuf , Dietrich Lothar , Dietz Dorothee , van Dijk Marius , Dreiner Stefan , Doering Ralf , Gabler Felix , Goehlich Andreas , Hutter Matthias , Ihle Martin , Kappert Holger , Kordas Norbert , Kokozinski Rainer , Naumann Falk , Nowak Torsten , Oppermann Hermann , Partsch Uwe , Petzold Matthias , Roscher Frank , Rzepka Sven , Schubert Ralph , Weber Constanze , Wiemer Maik , Wittler Olaf , Ziesche Steffen 
Published: May 2016

Abstract
Several applications in the fields of industrial sensors and power electronics are creating a demand for high operating temperature of 300 °C or even higher. Due to the increased temperature range new potential defect risks and material interactions have to be considered. As a consequence, innovation in semiconductor, devices and packaging technologies has to be accompanied by dedicated research of the reliability properties. Therefore various investigations on realizing high temperature capable electronic systems have shown that a multidisciplinary approach is necessary to achieve highly reliable solutions. In the course of the multi-institute Fraunhofer internal research program HOT-300 several aspects of microelectronic systems running up to 300 °C have been investigated like SOI-CMOS technology and circuits, silicon capacitor devices, a capacitive micromachined ultrasonic transducer (CMUT), ceramic substrates and different packaging and assembly techniques. A ceramic molded package has been developed. Die attach on different leadframe alloys were investigated using silver sintering and transient liquid phase bonding (TLPB). Copper and gold wire bonding was studied and used to connect the chips with the package terminals. Investigations in flip chip technology were performed using Au/Sn and Cu/Sn solder bumps for transient liquid phase bonding. High operating temperatures result in new temperature driven mechanisms of degradation and material interactions. It is quite possible that the thermomechanical reliability is a limiting factor for the technology to be developed. Therefore investigations on material diagnostics, reliability testing and modeling have been included in the project, complementing the technology developments.
The Design, Simulation, and Performance Characteristics of High Temperature Brushed and Brushless DC Motors, and Their Electronic Controllers
Authors: Snyder Harold L. 
Published: May 2016

Abstract
High temperature brushed and brushless direct current (DC) motors convert electrical energy to mechanical in order to actuate physical systems. This paper is an exploration of these systems from simple designs, which can actuate systems without the use of an electronic controller, to speed or power feedback controlled motors, and finally, to more complex microprocessor controlled systems. The design will review the advantages, disadvantages, specifications, and choice of these motors and their controllers. The simulation will use both Matlab and Spice models to predict the performance characteristics and system stability. And the performance characterization will evaluate measurements of the motors and their electronic control circuits in operation over wide temperature ranges.
Component Attachment with Pressureless Sintering for 300°C Applications
Authors: Yu Fang , Cui Jinzi , Zhou Zhangming , Johnson R. Wayne , Hamilton Michael C. 
Published: May 2016

Abstract
With an increased demand for high power and high temperature electronics, Ag sintering paste has been considered a promising Pb-free die attach material candidate for these applications. A large amount of research has been performed investigating pressure and pressureless Ag sintering for die attach.
In this work, passive component (chip resistor) attachment with Ag sintering was explored. Due to termination geometry differences between resistors and die, different processing procedures and parameters were developed.
For PtAu terminated resistors, the mean shear force of as-built samples on thick film Ag metallized substrates was 90 N, but dropped to 18.6 N after 1500 hours at 300°C. Formation of a dense Ag layer near the PtAu resistor termination and a void region near the thick film metallization was observed in cross-sections after 1000 hours at 300°C.
For PdAg terminated resistors with a plated Ni/Au finish, the initial shear force results were low due to Ag diffusion along Au metallization surface. For PdAg terminated resistors with Ag thick film substrates, the initial shear force was approximately 60 N and remained in the range of 50–70 N during aging at 300°C for 1500 hours. A new thick film metallization (Au+Ag) was developed to enable the use of thick film Au interconnect metallization.
A 200C capable embedded EEPROM
Authors: Allum Dean , Drajsajtl Tomas , Plachejda Radomir , Seleznev Stanislav , Wheelus Richard 
Published: May 2016

Abstract
An embedded logic EEPROM is presented that demonstrates full functionality at 200C. Several stress tests were performed to verify required reliability and endurance in the given temperature lifetime profile. Endurance has been demonstrated to greater than 110 thousand erase/write cycles (2000 cycles at 200C). This EEPROM is designed using a 0.18um logic process with a single 70 Angstrom gate oxide. This 0.18um process was designed to combine digital logic with high voltage (45V and 70V) BCD. A special test chip was designed containing 4 arrays of 512×39 bits. Test chips from a wafer lot that purposely skewed threshold voltage implants, poly CD, and gate oxide to achieve 6 sigma corners were probed at 200C and assembled in ceramic packages. The parts were soldered onto burn-in boards to avoid issues with sockets at high temperature. Six burn-in boards of 60 parts each were placed in a 200C oven for 1008 hours HTOL test and monitored while in a constant read mode. The paper describes the challenges in both design and stress that were overcome to achieve this 200C performance.
High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application
Authors: Francis A. Matthew , Holmes Jim , Chiolino Nick , Barlow Matthew , Abbasi Affan , Mantooth H. Alan 
Published: May 2016

Abstract
In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated.
More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time.
Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.
Low Power Silicon Carbide RS-485 Transceiver
Authors: Benavides M. R. , Castillo A. N. , Rahman A. , Barlow M. , Abreu D. , Rowlett C. , Mantooth H. A. , Francis A. M. , Holmes J. A. 
Published: May 2016

Abstract
This paper describes the first RS-485 transceiver for high temperature applications designed in SiC-CMOS. The transceiver was designed and developed in a 1.2μm CMOS HiTSiC® process from Raytheon UK. It has been tested at a voltage supply of 15 V from temperatures of 25°C to 400°C. At 320°C, the rise and fall times are 40 ns (for both), and the propagation delay from driver to output high and to output low is 150 ns and 50 ns respectively. The transceiver has been demonstrated to operate over 700 m of Cat5 cable. A high temperature data acquisition and transmission system has potential applications such as deep earth drilling, remote connection to high temperature locations, and high temperature data acquisition.
A High Temperature Passive GaN-HEMT Mixer for Downhole Communications
Authors: Salem Jebreel M. , Ha Dong Sam 
Published: May 2016

Abstract
Declining reserves of easily accessible natural resources have motivated the oil and gas industry to drill deeper. Temperatures in these hostile wells can exceed 210 °C. Cooling and conventional heat extraction techniques are impractical in such a harsh environment. Reliable electronic designs that can sustain high temperature become necessary. This paper presents a high temperature passive RF mixer that is suited for downhole communications. The proposed mixer is designed to upconvert or downconvert the incoming signal with a low conversion loss (CL) and high linearity and reliable operation at temperature up to 250 °C. Gallium Nitride (GaN) is a wide band gap technology that can provide a reliable operation at the elevated ambient temperature, and the proposed mixer adopts a commercial GaN high electron mobility transistor (HEMT) technology. Measurement results indicate that the proposed mixer achieves CL of 6.5 dB at LO power of 2.5 dBm for the downconversion from 230–253 MHz to 97.5 MHz at 250 °C and input P1dB compression point lies at 5 dBm. The power dissipation of the mixer is virtually zero.
A 225C Geothermal Logging Tool
Authors: Soares Marshall , Normann Randy , Ohme Bruce 
Published: May 2016

Abstract
Geothermal logging tools are difficult to develop due to sustained high temperature operation. Recent commercial component offerings are significantly altering the high temperature geothermal tool problem. This paper implements a new baseline geothermal tool circuit working with five 225C, SOI components. An example tool including up to four spinners (fluid flow measurement), four analog inputs (for pressure, temperature or other sensors), EEPROM storage (program and data), FSK logic (wireline data transmission), and a high-speed UART (tool communication). Field updates of code and calibration constants are supported. Further, this paper demonstrates how the tool electronics can be expanded for more complex applications such as a geothermal well logging camera.
Aerospace Performances of IPDiA −250°C up to 250°C Grade Silicon Capacitors
Authors: Lengignon Laurent , Leruez Sebastien 
Published: May 2016

Abstract
This paper covers technological results achieved with silicon capacitors for Aerospace applications, including stability, reliability and frequency data at high temperatures, as well as thermal stress, vibration & shock tests and radiations stress, according to ESA TRP reference (n° T723-325QT).
Tantalum Capacitor Technology Options for High Temperature and Harsh Environment Applications
Authors: Reynolds Chris 
Published: May 2016

Abstract
As new temperature critical applications continue to emerge, the need for components capable of enduring temperatures up to and exceeding 200°C is increasing. Advanced down-hole electronics, underhood automotive and aerospace systems rely on components delivering optimal performance while subject to extreme environmental conditions.
This paper will discuss the design advances in tantalum technology that have given rise to innovative devices that provide the enabling technology for a new generation of applications.
Traditionally, hermetically sealed “wet” axial tantalum capacitors (utilizing a non-solid electrolyte that promotes self-healing and long lifetime), have been used for both high bulk capacitance (to 5,600uF) and high voltage applications (to 125VDC). In recent years, this technology has been developed to meet the 200°C operational requirements of harsher environment industrial applications.
For lower operating voltages (6v – 25v), SMD packages are preferred, and for several years, 200°C rated high temperature solid tantalum chip devices have been the preferred technology over “wet” tantalum for capacitances to 220uF, being smaller size, lower cost and having the combination of lower ESR and higher frequency response.
More recently, hermetic SMD packaging has been developed for SMD solid tantalum capacitors. The hermetic seal enables the internal element to be operated in an inert gas environment, while offering superior resistance to moisture ingress. These two factors enable operation to 230°C, with higher capacitance (up to 330uF) and voltage (up to 63vDC) ranges.
Both molded and hermetic high temperature SMD solid tantalum capacitors have been developed to be compatible with high temperature pcb or hybrid circuit assembly processes, with a range of termination finishes compatible with HMP solder, epoxy or wire bonding. Their design also harsh mechanical environment shock & vibration.
This paper will discuss the evolution in materials, design and testing for each of these technologies, along with the considerations taken into account to give maximum compatibility with emerging requirements in high temperature and harsh environment applications, with emphasis on down-hole oil exploration, aerospace and military systems and underhood automotive electronics.
AVX High Temperature Products for Surface Mount and SMPS Applications
Authors: Dupre Dave , German Patrick 
Published: May 2016

Abstract
AVX produces a myriad of surface mount ceramic products, as well as stacked SMPS capacitors. AVX no offers many high temperature solutions for applications involving temperature requirements above what basic X7R and C0G can offer. This paper will discuss the advantages of base metal electrode devices, as well as AVX's methods of producing high temperature Nickel NP0 and VHT dielectric ceramics. This paper will also discuss high temperature SMPS capacitors, including custom solutions for MWD and LWD applications as well as AVX's SMX style products.
System On Chip (SOC) ASIC chipset for Smart Actuators in Distributed Propulsion Systems
Authors: Tulpule Bhal , Behbahani Alireza R. 
Published: May 2016

Abstract
This paper describes the results of the risk reduction testing task recently completed by Embedded Systems LLC under the Air Force SBIR contract {5} titled “Improved Full Authority Digital Engine Control (FADEC) System”. The objective of this program has been to develop a hierarchical, distributed architecture for future propulsion FADEC and aerospace control systems with flexible, scalable and reconfigurable Smart Nodes (SN) built with high temperature capable devices. A key part of this program is the design, development and validation of the System On Chip (SOC) chipset in high temperature (225 Deg. C) SOI (Silicon On Insulator) technology ASIC (Application Specific Integrated Circuit) devices. The SOC chipset designed by Embedded Systems LLC provides the scalability and reconfigurability that enables the Smart Node to interfaces with most sensors and actuators found in FADEC and other aircraft control systems. The analog portion of this 2-chip SOC chipset fabricated by Honeywell using their SOI process is working properly. The digital portion of the SOC chipset, currently implemented in a commercial temperature FPGA (Field Programmable Gate Array), contains important computational functions needed for reconfiguring the SOC and performing complex control functions, such as real time control of an actuator, The risk reduction task was therefore focused on verification and validation of these key functions in a real environment before converting the design into an ASIC. The recent successful demonstration of the real time actuator control capability has minimized the risks and cleared the way for the digital ASIC implementation. The complete high temperature SOC chipset is expected to be available in late 2016.