bluuebunny/crossref_metadata_2025_split huggingface dataset:
High versus low energy administration in the early phase of acute pancreatitis (GOULASH trial): protocol of a multicentre randomised double-blind clinical trial
Authors: Márta Katalin , Szabó Anikó N , Pécsi Dániel , Varjú Péter , Bajor Judit , Gódi Szilárd , Sarlós Patrícia , Mikó Alexandra , Szemes Kata , Papp Mária , Tornai Tamás , Vincze Áron , Márton Zsolt , Vincze Patrícia A , Lankó Erzsébet , Szentesi Andrea , Molnár Tímea , Hágendorn Roland , Faluhelyi Nándor , Battyáni István , Kelemen Dezső , Papp Róbert , Miseta Attila , Verzár Zsófia , Lerch Markus M , Neoptolemos John P , Sahin-Tóth Miklós , Petersen Ole H , Hegyi Péter 
Published: September 2017

IntroductionAcute pancreatitis (AP) is an inflammatory disease with no specific treatment. Mitochondrial injury followed by ATP depletion in both acinar and ductal cells is a recently discovered early event in its pathogenesis. Importantly, preclinical research has shown that intracellular ATP delivery restores the physiological function of the cells and protects from cell injury, suggesting that restoration of energy levels in the pancreas is therapeutically beneficial. Despite several high quality experimental observations in this area, no randomised trials have been conducted to date to address the requirements for energy intake in the early phase of AP.Methods/designThis is a randomised controlled two-arm double-blind multicentre trial. Patients with AP will be randomly assigned to groups A (30 kcal/kg/day energy administration starting within 24 hours of hospital admission) or B (low energy administration during the first 72 hours of hospital admission). Energy will be delivered by nasoenteric tube feeding with additional intravenous glucose supplementation or total parenteral nutrition if necessary. A combination of multiorgan failure for more than 48 hours and mortality is defined as the primary endpoint, whereas several secondary endpoints such as length of hospitalisation or pain will be determined to elucidate more detailed differences between the groups. The general feasibility, safety and quality checks required for high quality evidence will be adhered to.Ethics and disseminationThe study has been approved by the relevant organisation, the Scientific and Research Ethics Committee of the Hungarian Medical Research Council (55961-2/2016/EKU). This study will provide evidence as to whether early high energy nutritional support is beneficial in the clinical management of AP. The results of this trial will be published in an open access way and disseminated among medical doctors.Trial registrationThe trial has been registered at the ISRCTN (ISRTCN 63827758).
Associations between participation in organised physical activity in the school or community outside school hours and neighbourhood play with child physical activity and sedentary time: a cross-sectional analysis of primary school-aged children from the UK
Authors: Jago Russell , Macdonald-Wallis Corrie , Solomon-Moore Emma , Thompson Janice, L. , Lawlor Debbie, A. , Sebire Simon, J. 
Published: September 2017

ObjectivesTo assess the extent to which participation in organised physical activity in the school or community outside school hours and neighbourhood play was associated with children’s physical activity and sedentary time.DesignCross-sectional study.SettingChildren were recruited from 47 state-funded primary schools in South West England.Participants1223 children aged 8–9 years old.Outcome measuresAccelerometer-assessed moderate-to-vigorous-intensity physical activity (MVPA) and sedentary time.MethodsChildren wore an accelerometer, and the mean minutes of MVPA and sedentary time per day were derived. Children reported their attendance at organised physical activity in the school or community outside school hours and neighbourhood play using a piloted questionnaire. Cross-sectional linear and logistic regression were used to examine if attendance frequency at each setting (and all settings combined) was associated with MVPA and sedentary time. Multiple imputation methods were used to account for missing data and increase sample size.ResultsChildren who attended clubs at school 3–4 days per week obtained an average of 7.58 (95% CI 2.7 to 12.4) more minutes of MVPA per day than children who never attended. Participation in the three other non-school-based activities was similarly associated with MVPA. Evidence for associations with sedentary time was generally weaker. Associations were similar in girls and boys. When the four different contexts were combined, each additional one to two activities participated in per week increased participants’ odds (OR: 1.18, 95% CI 1.12 to 1.25) of meeting the government recommendations for 60 min of MVPA per day.ConclusionParticipating in organised physical activity at school and in the community is associated with greater physical activity and reduced sedentary time among both boys and girls. All four types of activity contribute to overall physical activity, which provides parents with a range of settings in which to help their child be active.
BARRACUDA: binary-level analysis of runtime RAces in CUDA programs
Authors: Eizenberg Ariel , Peng Yuanfeng , Pigli Toma , Mansky William , Devietti Joseph 
Published: September 2017

GPU programming models enable and encourage massively parallel programming with over a million threads, requiring extreme parallelism to achieve good performance. Massive parallelism brings significant correctness challenges by increasing the possibility for bugs as the number of thread interleavings balloons. Conventional dynamic safety analyses struggle to run at this scale.
We present BARRACUDA, a concurrency bug detector for GPU programs written in Nvidia’s CUDA language. BARRACUDA handles a wider range of parallelism constructs than previous work, including branch operations, low-level atomics and memory fences, which allows BARRACUDA to detect new classes of concurrency bugs. BARRACUDA operates at the binary level for increased compatibility with existing code, leveraging a new binary instrumentation framework that is extensible to other dynamic analyses. BARRACUDA incorporates a number of novel optimizations that are crucial for scaling concurrency bug detection to over a million threads.
Instruction punning: lightweight instrumentation for x86-64
Authors: Chamith Buddhika , Svensson Bo Joel , Dalessandro Luke , Newton Ryan R. 
Published: September 2017

Existing techniques for injecting probes into running applications are limited;
they either fail to support probing arbitrary locations, or to support scalable,
rapid toggling of probes. We introduce a new technique on x86-64, called
instruction punning, which allows scalable probes at any instruction. The key
idea is that when we inject a jump instruction, the relative address of the jump
serves simultaneously as data and as an instruction sequence. We show that this
approach achieves probe invocation overheads of only a few dozen cycles, and
probe activation/deactivation costs that are cheaper than a system call, even
when all threads in the system are both invoking probes and toggling them.
A formally verified compiler for Lustre
Authors: Bourke Timothy , Brun Lélio , Dagand Pierre-Évariste , Leroy Xavier , Pouzet Marc , Rieg Lionel 
Published: September 2017

The correct compilation of block diagram languages like Lustre, Scade, and a discrete subset of Simulink is important since they are used to program critical embedded control software. We describe the specification and verification in an Interactive Theorem Prover of a compilation chain that treats the key aspects of Lustre: sampling, nodes, and delays. Building on CompCert, we show that repeated execution of the generated assembly code faithfully implements the dataflow semantics of source programs.
We resolve two key technical challenges. The first is the change from a synchronous dataflow semantics, where programs manipulate streams of values, to an imperative one, where computations manipulate memory sequentially. The second is the verified compilation of an imperative language with encapsulated state to C code where the state is realized by nested records. We also treat a standard control optimization that eliminates unnecessary conditional statements.
Responsive parallel computation: bridging competitive and cooperative threading
Authors: Muller Stefan K. , Acar Umut A. , Harper Robert 
Published: September 2017

Competitive and cooperative threading are widely used abstractions in computing. In competitive threading, threads are scheduled preemptively with the goal of minimizing response time, usually of interactive applications. In cooperative threading, threads are scheduled non-preemptively with the goal of maximizing throughput or minimizing the completion time, usually in compute-intensive applications, e.g. scientific computing, machine learning and AI.
Although both of these forms of threading rely on the same abstraction of a thread, they have, to date, remained largely separate forms of computing. Motivated by the recent increase in the mainstream use of multicore computers, we propose a threading model that aims to unify competitive and cooperative threading. To this end, we extend the classic graph-based cost model for cooperative threading to allow for competitive threading, and describe how such a cost model may be used in a programming language by presenting a language and a corresponding cost semantics. Finally, we show that the cost model and the semantics are realizable by presenting an operational semantics for the language that specifies the behavior of an implementation, as well as an implementation and a small empirical evaluation.
Low overhead dynamic binary translation on ARM
Authors: D'Antras Amanieu , Gorgovan Cosmin , Garside Jim , Luján Mikel 
Published: September 2017

The ARMv8 architecture introduced AArch64, a 64-bit execution mode with a new instruction set, while retaining binary compatibility with previous versions of the ARM architecture through AArch32, a 32-bit execution mode. Most hardware implementations of ARMv8 processors support both AArch32 and AArch64, which comes at a cost in hardware complexity.
We present MAMBO-X64, a dynamic binary translator for Linux which executes 32-bit ARM binaries using only the AArch64 instruction set. We have evaluated the performance of MAMBO-X64 on three existing ARMv8 processors which support both AArch32 and AArch64 instruction sets. The performance was measured by comparing the running time of 32-bit benchmarks running under MAMBO-X64 with the same benchmark running natively. On SPEC CPU2006, we achieve a geometric mean overhead of less than 7.5% on in-order Cortex-A53 processors and a performance improvement of 1% on out-of-order X-Gene 1 processors.
MAMBO-X64 achieves such low overhead by novel optimizations to map AArch32 floating-point registers to AArch64 registers dynamically, handle overflowing address calculations efficiently, generate traces that harness hardware return address prediction, and handle operating system signals accurately.
Simple, fast, and safe manual memory management
Authors: Kedia Piyus , Costa Manuel , Parkinson Matthew , Vaswani Kapil , Vytiniotis Dimitrios , Blankstein Aaron 
Published: September 2017

Safe programming languages are readily available, but many applications continue to be written in unsafe languages because of efficiency. As a consequence, many applications continue to have exploitable memory safety bugs. Since garbage collection is a major source of inefficiency in the implementation of safe languages, replacing it with safe manual memory management would be an important step towards solving this problem.
Previous approaches to safe manual memory management use programming models based on regions, unique pointers, borrowing of references, and ownership types. We propose a much simpler programming model that does not require any of these concepts. Starting from the design of an imperative type safe language (like Java or C#), we just add a delete operator to free memory explicitly and an exception which is thrown if the program dereferences a pointer to freed memory. We propose an efficient implementation of this programming model that guarantees type safety. Experimental results from our implementation based on the C# native compiler show that this design achieves up to 3x reduction in peak working set and run time.
HyperMAMBO-X64
Authors: d'Antras Amanieu , Gorgovan Cosmin , Garside Jim , Goodacre John , Luján Mikel 
Published: September 2017

Current computer architectures --- ARM, MIPS, PowerPC, SPARC, x86 --- have evolved from a 32-bit architecture to a 64-bit one. Computer architects often consider whether it could be possible to eliminate hardware support for a subset of the instruction set as to reduce hardware complexity, which could improve performance, reduce power usage and accelerate processor development. This paper considers the scenario where we want to eliminate 32-bit hardware support from the ARMv8 architecture.
Dynamic binary translation can be used for this purpose and generally comes in one of two forms: application-level translators that translate a single user mode process on top of a native operating system, and system-level translators that translate an entire operating system and all its processes.
Application-level translators can have good performance but is not totally transparent; system-level translators may be 100% compatible but performance suffers. HyperMAMBO-X64 uses a new approach that gets the best of both worlds, being able to run the translator as an application under the hypervisor but still react to the behavior of guest operating systems. It works with complete transparency with regards to the virtualized system whilst delivering performance close to that provided by hardware execution.
A key factor in the low overhead of HyperMAMBO-X64 is its deep integration with the virtualization and memory management features of ARMv8. These are exploited to support caching of translations across multiple address spaces while ensuring that translated code remains consistent with the source instructions it is based on. We show how these attributes are achieved without sacrificing either performance or accuracy.
Swift Birth and Quick Death
Authors: Nitu Vlad , Olivier Pierre , Tchana Alain , Chiba Daniel , Barbalace Antonio , Hagimont Daniel , Ravindran Binoy 
Published: September 2017

The ability to quickly set up and tear down a virtual machine is critical for today's cloud elasticity, as well as in numerous other scenarios: guest migration/consolidation, event-driven invocation of micro-services, dynamically adaptive unikernel-based applications, micro-reboots for security or stability, etc.
In this paper, we focus on the process of setting up/freeing the hypervisor and host control layer data structures at boot/destruction time, showing that it does not scale in current virtualization solutions. In addition to the direct overhead of long VM set-up/destruction times, we demonstrate by experimentation the indirect costs on real world auto scaling systems. Focusing on the popular Xen hypervisor, we identify three critical issues hindering the scalability of the boot and destruction processes: serialized boot, unscalable interactions with the Xenstore at guest creation time, and remote NUMA memory scrubbing at destruction time. For each of these issues we present the design and implementation of a solution in the Xen infrastructure: parallel boot with fine-grained locking, caching of Xenstore data, and local NUMA scrubbing. We evaluate these solutions using micro-benchmarks, macro-benchmarks, and real world datacenter traces. Results show that our work improves the current Xen implementation by a significant factor, for example macro-benchmarks indicate a speedup of more than 4X in high-load scenarios.
HA-VMSI
Authors: Zhu Min , Tu Bibo , Wei Wei , Meng Dan 
Published: September 2017

Once compromising the hypervisor, remote or local adversaries can easily access other customers' sensitive data in the memory and context of guest virtual machines (VMs). VM isolation is an efficient mechanism for protecting the memory of guest VMs from unauthorized access. However, previous VM isolation systems either modify hardware architecture or introduce a software module without being protected, and most of them focus on the x86 architecture.
This paper proposes HA-VMSI, a lightweight hardware-assisted VM isolation approach for ARM, to provide runtime protection of guest VMs, even with a compromised hypervisor. In the ARM TrustZone secure world, a thin security monitor is introduced as HA-VMSI's entire TCB. Hence, the security monitor is much less vulnerable and safe from attacks that can compromise the hypervisor. The key of HA-VMSI is decoupling the functions of memory isolation among VMs from the hypervisor into the security monitor. As a result, the hypervisor can only update the Stage-2 page tables of VMs via the security monitor, which inspects and approves each new mapping. It is worth noting that HA-VMSI is more secure and effective than current software approaches, and more flexible and compatible than hardware approaches. We have implemented a prototype for KVM hypervisor with multiple Linux as guest OSes on Juno board. The security assessment and performance evaluation show that HA-VMSI is effective, efficient and practical.
Rethinking TLB Designs in Virtualized Environments
Authors: Ryoo Jee Ho , Gulur Nagendra , Song Shuang , John Lizy K. 
Published: September 2017

With increasing deployment of virtual machines for cloud services and server applications, memory address translation overheads in virtualized environments have received great attention. In the radix-4 type of page tables used in x86 architectures, a TLB-miss necessitates up to 24 memory references for one guest to host translation. While dedicated page walk caches and such recent enhancements eliminate many of these memory references, our measurements on the Intel Skylake processors indicate that many programs in virtualized mode of execution still spend hundreds of cycles for translations that do not hit in the TLBs.
This paper presents an innovative scheme to reduce the cost of address translations by using a very large Translation Lookaside Buffer that is part of memory, the POM-TLB. In the POM-TLB, only one access is required instead of up to 24 accesses required in commonly used 2D walks with radix-4 type of page tables. Even if many of the 24 accesses may hit in the page walk caches, the aggregated cost of the many hits plus the overhead of occasional misses from page walk caches still exceeds the cost of one access to the POM-TLB. Since the POM-TLB is part of the memory space, TLB entries (as opposed to multiple page table entries) can be cached in large L2 and L3 data caches, yielding significant benefits. Through detailed evaluation running SPEC, PARSEC and graph workloads, we demonstrate that the proposed POM-TLB improves performance by approximately 10% on average. The improvement is more than 16% for 5 of the benchmarks. It is further seen that a POM-TLB of 16MB size can eliminate nearly all TLB misses in 8-core systems.
Jenga
Authors: Tsai Po-An , Beckmann Nathan , Sanchez Daniel 
Published: September 2017

Caches are traditionally organized as a rigid hierarchy, with multiple levels of progressively larger and slower memories. Hierarchy allows a simple, fixed design to benefit a wide range of applications, since working sets settle at the smallest (i.e., fastest and most energy-efficient) level they fit in. However, rigid hierarchies also add overheads, because each level adds latency and energy even when it does not fit the working set. These overheads are expensive on emerging systems with heterogeneous memories, where the differences in latency and energy across levels are small. Significant gains are possible by specializing the hierarchy to applications.
We propose Jenga, a reconfigurable cache hierarchy that dynamically and transparently specializes itself to applications. Jenga builds virtual cache hierarchies out of heterogeneous, distributed cache banks using simple hardware mechanisms and an OS runtime. In contrast to prior techniques that trade energy and bandwidth for performance (e.g., dynamic bypassing or prefetching), Jenga eliminates accesses to unwanted cache levels. Jenga thus improves both performance and energy efficiency. On a 36-core chip with a 1 GB DRAM cache, Jenga improves energy-delay product over a combination of state-of-the-art techniques by 23% on average and by up to 85%.
LogCA
Authors: Altaf Muhammad Shoaib Bin , Wood David A. 
Published: September 2017

With the end of Dennard scaling, architects have increasingly turned to special-purpose hardware accelerators to improve the performance and energy efficiency for some applications. Unfortunately, accelerators don't always live up to their expectations and may under-perform in some situations. Understanding the factors which effect the performance of an accelerator is crucial for both architects and programmers early in the design stage. Detailed models can be highly accurate, but often require low-level details which are not available until late in the design cycle. In contrast, simple analytical models can provide useful insights by abstracting away low-level system details.
In this paper, we propose LogCA---a high-level performance model for hardware accelerators. LogCA helps both programmers and architects identify performance bounds and design bottlenecks early in the design cycle, and provide insight into which optimizations may alleviate these bottlenecks. We validate our model across a variety of kernels, ranging from sub-linear to super-linear complexities on both on-chip and off-chip accelerators. We also describe the utility of LogCA using two retrospective case studies. First, we discuss the evolution of interface design in SUN/Oracle's encryption accelerators. Second, we discuss the evolution of memory interface design in three different GPU architectures. In both cases, we show that the adopted design optimizations for these machines are similar to LogCA's suggested optimizations. We argue that architects and programmers can use insights from these retrospective studies for improving future designs.
Fractal
Authors: Subramanian Suvinay , Jeffrey Mark C. , Abeydeera Maleen , Lee Hyun Ryong , Ying Victor A. , Emer Joel , Sanchez Daniel 
Published: September 2017

Most systems that support speculative parallelization, like hardware transactional memory (HTM), do not support nested parallelism. This sacrifices substantial parallelism and precludes composing parallel algorithms. And the few HTMs that do support nested parallelism focus on parallelizing at the coarsest (shallowest) levels, incurring large overheads that squander most of their potential.
We present FRACTAL, a new execution model that supports unordered and timestamp-ordered nested parallelism. FRACTAL lets programmers seamlessly compose speculative parallel algorithms, and lets the architecture exploit parallelism at all levels. FRACTAL can parallelize a broader range of applications than prior speculative execution models. We design a FRACTAL implementation that extends the Swarm architecture and focuses on parallelizing at the finest (deepest) levels. Our approach sidesteps the issues of nested parallel HTMs and uncovers abundant fine-grain parallelism. As a result, FRACTAL outperforms prior speculative architectures by up to 88x at 256 cores.