bluuebunny/crossref_metadata_2025_split huggingface dataset:
X-ray Absorption Spectroscopy on Copper Trace Impurities on Silicon Wafers
Authors: Singh Andy , Baur Katharina , Brennan Sean , Homma Takayuki , Kubo Nobuhiro , Pianetta Piero 
Published: February 2017

AbstractTrace metal contamination during wet cleaning processes on silicon wafer surfaces is a detrimental effect that impairs device performance and yield. Determining the chemical state of deposited impurities helps in understanding how silicon surfaces interact with chemical species in cleaning solutions. However, since impurity concentrations of interest to the semiconductor industry are so low, conventional techniques such as x-ray photoelectron spectroscopy cannot be applied. Nonetheless, chemical information on trace levels of contaminants can be determined with x-ray absorption near edge spectroscopy (XANES) in a grazing incidence geometry. In this study, silicon samples were dipped in ultra pure water (UPW) and 2% hydrofluoric (HF) solutions with copper concentrations of 5 and 1000 ppb, respectively. These samples were then analyzed using XANES in fluorescence yield mode to determine the oxidation state of deposited copper contaminants. It was found that copper impurities on the silicon surface from HF solution were metal in character while copper impurities deposited from the spiked UPW solution were deposited as an oxide. These results show that XANES can provide information on the chemical state of trace impurities even at surface concentrations below a few thousandths of a monolayer.
Linewidth Dependence of the Reverse Bias Junction Leakage for Co-Silicided Source/Drain Junctions
Authors: Lauwers Anne , Potter Muriel de , Lindsay Richard , Chamirian Oxana , Demeurisse Caroline , Vrancken Christa , Maex Karen 
Published: February 2017

AbstractIn this work the reverse bias junction leakage was studied for Co-silicided 100 nm deep As source/drain junctions. The effect of pre-clean and silicidation temperature was investigated. The area component of the leakage current was found to be dominant for silicided source/drain areas wider than 1 mm. Increasing the thermal budget for silicidation was found to improve the area leakage. For diodes consisting of active area stripes narrower than 0.5 μm, the leakage current is no longer improved by increasing the silicidation temperature. As a result the leakage current is found to depend strongly on the active area linewidth. It was found that the linewidth dependence of the junction leakage cannot be attributed to silicide induced stress. It is argued that the higher leakage current observed for narrow lines can be attributed to the stress induced by the STI isolation and to increased silicide thickness in the narrow active lines
Thickness Effect on Nickel Silicide Formation and Thermal Stability for Ultra Shallow Junction CMOS
Authors: Zhao F. F. , Shen Z. X. , Zheng J. Z. , Gao W. Z. , Osipowicz T. , Pang C. H. , Lee P. S. , See A. K. 
Published: February 2017

AbstractHigh purity Ni films from 200Å down to 40Å on p-type Si (100) substrates are treated by rapid thermal annealing to form the metastable and stable phases of nickel silicides. The stoichiometric composition of NiSi determined by Rutherford backscattering is independent of the initial Ni thickness under 500°C annealing. Channeling RBS results reveal that the NiSi growth on Si (100) has no preferred orientation. The sheet resistance as well as surface roughness of thinner films starts to increase at a lower temperature, indicating that thinner films are thermally less stable. Agglomeration of NiSi film agrees with the grain boundary grooving model and occurs more easily within thinner films. The transformation from the NiSi phase to the NiSi2 phase is studied by micro-Raman spectroscopy. This phase transition of thinner films begins at a lower temperature than that of thicker ones.
Suppression of NiSi-to-NiSi2 Transition Using Very Short-time RTA Silicidation
Authors: Ma D. , Chi D. Z. , Wang W. D. , Wong A. S. W. , Chua S. J. 
Published: February 2017

AbstractThermal stability of NiSi is a major concern for its application in sub-0.1 μm CMOS devices, due to the transition of NiSi to the high-resistivity disilicide (NiSi2) at elevated temperatures. In this study, we have investigated the effect of RTA silicidation duration on NiSito-NiSi2 transition during Ni-silicidation reaction of Ni film (20-25 nm thick) on (100)Si. It was found that the NiSi-NiSi2 transition temperature was increased remarkably from 700 to > 800 °C by reducing the RTA time from 60 to 1 s. Agglomeration of silicides films was also found to besuppressed by short-time annealing. A temperature-time transformation (TTT) diagram has been constructed, which demonstrates the time-dependency of NiSi-NiSi2 transition. Based on the classical theory on phase transformation kinetics, a concept of induction time was employed to elucidate the key roles of transformation time and film thickness in determining the NiSi-NiSi2 transition temperature.
Nickel, Platinum and Zirconium Germanosilicide Contacts to Ultra-shallow, P+N Junctions Formed by Selective SiGe Technology for CMOS Technology Nodes Beyond 70nm
Authors: Liu Jing , Mo Hongxiang , Öztürk Mehmet C. 
Published: February 2017

AbstractSelective SiGe source/drain technology based on selective deposition of in-situ doped SiGe alloys in recessed source/drain regions can provide junctions with low sheet and contact resistance as well as abrupt doping profiles. This paper examines properties of Ni, Pt and Zr germanosilicides on heavily boron doped SiGe junctions. Our results show that all three metals can form low resistivity germanosilicides on heavily boron doped SiGe alloys. The stability of Ni germanosilicide was found to be limited to about 400°C on undoped SiGe. On heavily boron doped SiGe thermal stability was found to be significantly better possibly due to boron strain compensation. Our findings indicate that on undoped SiGe, thermal stability of Ni germanosilicide could be much enhanced by using a thin Pt interlayer. According to X-ray diffraction analysis, with increasing formation temperature, both Ni and Pt germanosilicides moved toward Ni and Pt monosilicides with signs of excess Ge appearing outside the contact. Analysis of the Pt germanosilicide layers is suggestive of a Ge rich SiGe layer under the germanosilicide. Boron diffusion into Pt and Ni germanosilicides was not observed. On the other hand, a distinct boron peak was observed in Zr germanosilicide suggestive of a stable Zr-B compound. Ultra-shallow junctions with excellent reverse bias behavior were formed using both Ni and Zr germanosilicides.
Study Of Ta2O5 Based MOS Capacitors, With Tantalum Oxidized In O2:NH3 Ambient.
Authors: Krishnamoorthi Pallavi , Chandorkar A N 
Published: February 2017

AbstractTantalum Pentaoxide, an alternative to SiO2, as a high-k dielectric for DRAM and MOS applications, faces the problem of interface mismatch at silicon. SiO2 or Si3N4 interfacial layer could help in overcoming this problem. The higher band offsets of these materials also help in the reduction of leakage currents at low electric fields. Here we study the physical and electrical characteristics of Ta, oxidized in O2:NH3 ambient, and without any other interface layer. This is done to check if N/H moves to the interface, and thus improves the electrical properties. XRD studies of the film, showed the presence of Ta2O5. Peaks corresponding to TaSi2, un-oxidized tantalum and TaN were also found in the film. But the intensity of these peaks decreased with the reduction of NH3 content. Thus a higher oxygen content could reduce the content of TaN and unoxidized tantalum. FTIR analysis however showed strong Ta=O and Si-O peaks. For the MOS capacitors, due to the presence of resistive components, the maximum capacitance was reduced, compared to that of pure Ta2O5 films. Oxide charges in the films were observed to be around 1.9E10 cm-2. But the traps in these films were found to be almost negligible as observed from the negligible hysteresis in the C-V characteristics. Films with N/H showed lesser oxide charges by an order of magnitude, as compared to pure Ta2O5 films.
Effects of Borophosphosilicate Glass Dopant Concentrations on Isotropic Etch Profile
Authors: Gibson Chris , Williams Bradley , Evans Stacey 
Published: February 2017

AbstractIn the process of chemically etching contact openings, film characteristics of the Borophosphosilicate glass (BPSG) film strongly effect the formation of an ideal contact profile. Ideal contact profiles represent a wine glass shape to provide better metal step coverage into the contact opening in comparison to a vertical sidewall profile. The rounded shape of the wine glass is etched chemically (isotropic) allowing for etch in the vertical and horizontal direction. As the addition of dopants to the oxide film effect the etch rate, the profile of the isotropic etch will change which in turn effects the electrical device properties, down stream processes and device reliability.BPSG film characteristics are the area of investigation. Characteristics of concern are weight percent concentrations of boron and phosphorus, film density and dopant concentration profiles in relation to depth. To evaluate the entire contact formation module, chemical etch characteristics including etch rate in relation to film depth for thermal oxide films were also investigated. Experimentation in the form of a response surface design was used to model effects of previously discussed BPSG film characteristics.To achieve the desired and predictable wet etch rate of BPSG in a buffered oxide etch (BOE), calculated control limits were placed on the boron and phosphorus dopant concentrations. Results showed that dopant effects on the isotropic etch process exceeded the control capability of dopant concentrations in the deposition process. In relating process control capabilities to 6σ techniques, a Cpk above 1.5 is considered capable. To eliminate previously discussed defects created in the isotropic etch process, reject limits for dopant concentrations in a BPSG film deposition process would need to be set well within the typical 6σ giving a Cpk below 1.5
Optimization of Ultrathin ALD Tantalum Nitride Films for Zero-Thickness Liner Applications
Authors: Straten Oscar van der , Zhu Yu , Eisenbraun Eric , Kaloyeros Alain 
Published: February 2017

AbstractA metal-organic atomic layer deposition (ALD) tantalum nitride process has been demonstrated for zero-thickness liner applications in advanced copper metallization schemes. Utilizing a commercially available ALD reactor, this process employs a liquid tantalum source (tertbutylimido tris(diethylamido) tantalum—TBTDET) and ammonia as the reactants. Key functionality data addressing the self-limiting nature of ALD film growth with respect to key process parameters including processing temperature and the substrate surface exposures to TBTDET and ammonia have been obtained, leading to the establishment of an optimized ALD processing window. Highly conformal, continuous, and smooth growth over high aspect ratio structures is exhibited, and incubation periods appear to be relatively substrate independent. Preliminary thermal and electrical copper barrier performance testing of the deposited films indicates that they hold promise for use in emerging nanoscale interconnect applications.
Nanoindentation of Silicate Low-K Dielectric Thin Films
Authors: Vella Joseph B. , Volinsky Alex A. , Adhihetty Indira S. , Edwards N.V. , Gerberich William W. 
Published: February 2017

AbstractThe capabilities of nanoindentation to characterize low-k organo silicate glass (OSG) thin films is explored as a relatively rapid and inexpensive metric of mechanical properties, adhesion strength, and fracture toughness. One method of decreasing the static dielectric constant of OSG interlayer dielectrics requires the introduction of porosity in the material which has a dramatic impact on its mechanical and toughness properties. Percolation theory is used to formulate a correlation between porosity and elastic modulus. Using cube corner diamond indentation and scratch testing fracture toughness calculations are also discussed.
Characteristics of low-k and ultralow-k PECVD deposited SiCOH films.
Authors: Grill A. , Patel V. , Rodbell K.P. , Huang E. , Christiansen S. , Baklanov M. R. 
Published: February 2017

AbstractWe have shown previously that the dielectric constants of PECVD prepared SiCOH dielectrics can be extended to ultralow-k values of k=2.0. The reduction in the dielectric constants has been achieved by adding an organic precursor to the tetramethylcyclotetrasiloxane (TMCTS) used for the preparation of the SiCOH dielectric and annealing the films to remove the thermally less-stable organic CHx fractions from the films, thereby adding porosity and reducing the density of the films. To assess the effects of the reduction of the dielectric constant on other physical properties of the material, the density and composition of the films have been determined by RBS and FRES and the porosity has been measured by PAS/PALS, SAXS and ellipsometric porosimetry. In addition the films have been characterized structurally and topologically by TEM and AFM.It has been found that addition of the organic precursor reduces the Si fraction in the films, however, there is no direct correlation between dielectric constant and film composition. The dielectric constant and density decrease with increasing porosity in the films, which reaches values of 30-39% for k values of 2.05. The pore size increases with decreasing k, however the diameter remains below 5 nm for k=2.05. This is significantly smaller than the pore size typically found in porous spin-on films and may provide an integration advantage compared to spin-on films having similar k values.
Novel Periodic Nanoporous Silicate Glass With High Structural Stability as Low-k Thin Film
Authors: Oku Yoshiaki , Nishiyama Norikazu , Tanaka Shunsuke , Ueyama Korekazu , Hata Nobuhiro , Kikkawa Takamaro 
Published: February 2017

AbstractWe have recently developed novel periodic nanoporous silicate glass with high structural stability as low-k thin film by spin-coating method. Periodic porous silicate glass films developed so far cause structural shrinkage (10>∼20% or more) by annealing the spin-coated films. In this investigation we adopt vapor-phase TEOS (tetraethoxysilane)-treatment before anneal. Our novel nanoporous film shows little shift of XRD peak position after annealed at 673K, indicating both the ultimate mechanical strength and the minimization of stress in the interface between the prepared film and the underlying substrate. Such a shrinkage-free periodic nanoporous silica film can possess higher VBD (break down voltage) and lower ILeak (leakage current). In this article we estimate structural properties (including information on pores introduced intentionally) by XRD and TEM observation, and electrical properties (dielectric constant, VBD and ILeak) by IV and CV measurement of this special-treated periodic nanoporous silica film. The dielectric constant of the thus prepared periodic porous silica film with silylation after calcination was evaluated to be around 1.8 at 100kHz.
Thermal Stability Studies on 1, 3, 5, 7 - Tetramethylcyclotetra-Siloxane(TMCTS), a Low к CVD Precursor
Authors: Xu C. , Borovik A. S. , Wang Z. , Arno J. , Baum T. H. 
Published: February 2017

AbstractChemical studies on 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS) were conducted to elucidate its thermal behaviors with water and under various reaction conditions. TMCTS was heated in the presence of 316L stainless steel and in the presence of water. The heated TMCTS then was evaluated using 1H NMR (proton nuclear magnetic resonance) spectroscopy, GC-MS (gas chromatography-mass spectrometry) as a function of time, temperature and residual water concentration. The thermal degradation kinetics of gas-phase TMCTS were investigated using FTIR (Fourier transform infrared) spectroscopy at elevated temperatures. These initial results indicated that TMCTS degradation rates increased with both temperature and water concentration. This work spawned the development of a “dry” TMCTS that is expected to exhibit enhanced thermal stability relative towards uncontrolled decomposition.
Electromigration in Submicron Dual-damascene Cu/low-k Interconnects
Authors: Lee Ki-Don , Lu Xia , Ogawa Ennis T. , Matsuhashi Hideki , Blaschke Volker A. , Augur Rod , Ho Paul S. 
Published: February 2017

AbstractElectromigration (EM) lifetime characteristics and failure mechanism were investigated for Cu/porous-low-k interconnects and compared to Cu/oxide. The porous low-k dielectric was JSR LKD-5109TM, an MSQ-based spin-on organosilicate material with k = 2.2. The activation energies for EM failure were found to be 0.9 - 1.0 eV for the porous MSQ and 0.8 eV for oxide while the current density exponents for both materials were found to be similar, 1.2 - 1.3. This range of activation energies are commonly associated with mass transport at the Cu/cap-layer interface and suggest a similar mass transport mechanism; interfacial diffusion. Porous MSQ structures showed the same distinct failure morphology as observed in other Cu/low-k interconnects: voiding at the cathode and lateral Cu extrusion at the anode under the cap layer, which seems to be related to the thermo-mechanical properties of Cu/low-k interconnects. The shorter lifetime characteristics of Cu/low-k interconnects comparing to Cu/oxide can be attributed to a smaller back stress, due to less thermomechanical confinement. Results of this study indicate that thermo-mechanical properties of low-k interconnects are important parameters in controlling EM reliability of Cu/low-k interconnects.
EBIC and XTEM Analysis of High Voltage SMOS Reliability Failures
Authors: Rice Larry 
Published: February 2017

AbstractMicroscopists are faced with many challenges in locating and examining failure sites in the ever-shrinking semiconductor device. The site must be located using electrical characterization techniques like electron beam induced current (EBIC), photo emission microscopy (PEM) or liquid crystal (LC) and then cross-sectioned with a focused ion beam (FIB). Both PEM and LC require the semiconductor circuit to be running near operating conditions which has been observed to locally melt the area of interest, frequently destroying evidence of the failure mechanism. In contrast, EBIC typically can be accomplished at low or no applied voltage eliminating further damage to the circuit. EBIC has been applied to locate leakage sites in high voltage metal oxide semiconductor (MOS) electro static discharge (ESD) reliability failures. In addition to a brief revisit of the basic principles of EBIC and describing a technique to successfully cross section ‘hot spots’ for transmission electron microscopy (TEM) observation, focus will be placed on a case study of the reliability testing failure analysis of ESD power transistors using EBIC, SEM, focused ion beam (FIB), and XTEM.
Mechanical-Stress-Controlled Silicide Interconnections for Highly Reliable Semiconductor Devices
Authors: Shimazu Hiromi , Miura Hideo 
Published: February 2017

AbstractMechanical stress develops in silicide interconnection structures due to the volumetric shrinkage of newly grown silicide film during silicidation. Silicidation-induced stress of about 1 GPa was measured by inducing a reaction between a silicon wafer and a titanium film deposited on the wafer. The stress developed near the interface between the grown silicide film. The remaining silicon was analyzed using a finite-element method. The critical stress for delamination at the interface was determined by comparing the results of the estimated stress at the interface with the cross-sectional observation results of different interconnection-structures test samples. We also determined the critical thickness of TiSi2 and the diameter of silicide contacts for eliminating delamination at the interface.
Chemical Vapor Deposition of Ru and RuO2 for Gate Electrode Applications
Authors: Papadatos Filippos , Skordas Spyridon , Patel Zubin , Consiglio Steven , Eisenbraun Eric 
Published: February 2017

AbstractIn this work, Ru and RuO2 films have been investigated for potential applications in emerging CMOS gate electrode and memory capacitor bottom electrode applications. Films were deposited on SiO2 using chemical vapor deposition (CVD) and low power plasma assisted CVD (PACVD) in a 200-mm wafer deposition cluster tool using a metal beta-diketonate precursor [Bis (2,2,6,6-tetramethyl-3,5-heptanedionato) (1,5-cyclooctadiene) ruthenium (II)]. Hydrogen and oxygen were employed as the reactive gases to deposit, respectively, Ru and RuO2, over a wafer temperature range from 320°C to 480°C. The resulting film properties were analyzed using cross-sectional scanning electron microscopy (CS-SEM), four point resistance probe, x-ray photoelectron spectroscopy (XPS), Rutherford backscattering spectrometry (RBS) and x-ray diffraction (XRD). Both Ru and RuO2 films could be deposited with minimal carbon concentration (∼5 at. %). The purity of the films was also reflected in the as-deposited resistivity of the films, which was as low as 47 μΩ-cm, and was strongly dependent on processing conditions. In order to assess thermal stability, the films were subsequently annealed in forming gas and oxygen ambients for 60 min at 650°C. It was observed that, generally speaking, CVD RuO2 films were stable, with respect to resistivity, in oxidizing ambients, while annealing in a reducing ambient resulted in significant film densification and reduction of the film resistivities to as low as 43 μΩ-cm. Ru films demonstrated good adhesion after anneals in oxidizing, but not in reducing ambients.
Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics
Authors: Mohapatra Nihar R. , Desai Madhav P. , Narendra Siva G. , Rao V. Ramgopal 
Published: February 2017

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.
Atomic-Layer Deposition of ZrO2 Thin Films Using New Alkoxide Precursors
Authors: Jones Anthony C. , Williams Paul A. , Roberts John L. , Leedham Timothy J. , Davies Hywel O. , Matero Raija , Ritala Mikko , Leskelä Markku 
Published: February 2017

AbstractAtomic layer deposition is a promising technique for the deposition of ZrO2 thin films for high-k gate dielectric applications. However, there are a number of problems associated with existing Zr precursors such as ZrCl4 and [Zr(OBut)4]. In this paper, we examine the ALD of ZrO2 using the new alkoxide complexes, [Zr(OBut)2(dmae)2], [Zr(OPr1)2(dmae)2] and [Zr(dmae)4] (dmae = [OCH2CH2NMe2]), and compare the results with data obtained using [Zr(OBut)4].