bluuebunny/crossref_metadata_2025_split huggingface dataset:
Draft Genome Sequence of Toxigenic
Corynebacterium ulcerans
Strain 03-8664 Isolated from a Human Throat
Authors: Guimarães Luis C. , Viana Marcus V. C. , Benevides Leandro J. , Mariano Diego C. B. , Veras Adonney A. O. , Sá Pablo H. C. , Rocha Flávia S. , Vilas Boas Priscilla C. B. , Soares Siomar C. , Barbosa Maria S. , Guiso Nicole , Badell Edgar , Azevedo Vasco , Ramos Rommel T. J. , Silva Artur 
Published: July 2016

ABSTRACT

Corynebacterium ulcerans
is an emergent pathogen infecting wild and domesticated animals worldwide that may serve as reservoirs for zoonotic infections. In this study, we present the draft genome of
C. ulcerans
strain 03-8664. The draft genome has 2,428,683 bp, 2,262 coding sequences, and 12 rRNA genes.
Complete Genome Sequence of a Virulent Newcastle Disease Virus Strain Isolated from a Clinically Healthy Duck (
Anas platyrhynchos domesticus
) in Pakistan
Authors: Wajid Abdul , Rehmani Shafqat F. , Wasim Muhammad , Basharat Asma , Bibi Tasra , Arif Saima , Dimitrov Kiril M. , Afonso Claudio L. 
Published: July 2016

ABSTRACT

Here, we report the complete genome sequence of a virulent Newcastle disease virus (vNDV) strain, duck/Pakistan/Lahore/AW-123/2015, isolated from apparently healthy laying ducks (
Anas platyrhynchos domesticus
) from the province of Punjab, Pakistan. The virus has a genome length of 15,192 nucleotides and is classified as member of subgenotype VIIi, class II.
Draft Genome Sequence of
Fonsecaea monophora
Strain CBS 269.37, an Agent of Human Chromoblastomycosis
Authors: Bombassaro Amanda , de Hoog Sybren , Weiss Vinicius A. , Souza Emanuel M. , Leão Aniele C. R. , Costa Flávia F. , Baura Valter , Tadra-Sfeir Michele Z. , Balsanelli Eduardo , Moreno Leandro F. , Raittz Roberto T. , Steffens Maria Berenice R. , Pedrosa Fabio O. , Sun Jiufeng , Xi Liyan , Bocca Anamélia L. , Felipe Maria S. , Teixeira Marcus , Santos Germana D. , Telles Filho Flávio Q. , Azevedo Conceição M. P. S. , Gomes Renata R. , Vicente Vânia A. 
Published: July 2016

ABSTRACT

The black yeast
Fonsecaea monophora
is one of the main etiologic agents of chromoblastomycosis in humans. Its pathogenicity profile is more invasive than that of related
Fonsecaea
species, causing brain infection in addition to (sub)cutaneous infections.
Complete Genome Sequence of
Cyanobium
sp. NIES-981, a Marine Strain Potentially Useful for Ecotoxicological Bioassays
Authors: Yamaguchi Haruyo , Shimura Yohei , Suzuki Shigekatsu , Yamagishi Takahiro , Tatarazako Norihisa , Kawachi Masanobu 
Published: July 2016

ABSTRACT

Cyanobium
sp. NIES-981 is a marine cyanobacterium isolated from tidal flat sands in Okinawa, Japan. Here, we report the complete 3.0-Mbp genome sequence of NIES-981, which is composed of a single chromosome, and its annotation. This sequence information may provide a basis for developing an ecotoxicological bioassay using this strain.
Full-Genome Sequence of a Neuroinvasive West Nile Virus Lineage 2 Strain from a Fatal Horse Infection in South Africa
Authors: Mentoor Juliet L. D. , Lubisi Alison B. , Gerdes Truuska , Human Stacey , Williams June H. , Venter Marietjie 
Published: July 2016

ABSTRACT
We report here the complete genome sequence of a lineage 2 West Nile virus (WNV) strain that resulted in fatal neurological disease in a horse in South Africa. Several recent reports exist of neurological disease associated with lineage 2 WNV in humans and horses in South Africa and Europe; however, there are a lack of sequencing data from recent fatal cases in Southern Africa, where these strains likely originate. A better understanding of the genetic composition of highly neuroinvasive lineage 2 strains may facilitate the identification of putative genetic factors associated with increased virulence.
Draft Genome Sequence of
Photorhabdus luminescens
Strain DSPV002N Isolated from Santa Fe, Argentina
Authors: Palma Leopoldo , Del Valle Eleodoro E. , Frizzo Laureano , Berry Colin , Caballero Primitivo 
Published: July 2016

ABSTRACT

Here, we report the draft genome sequence of
Photorhabdus luminescens
strain DSPV002N, which consists of 177 contig sequences accounting for 5,518,143 bp, with a G+C content of 42.3% and 4,701 predicted protein-coding genes (CDSs). From these, 27 CDSs exhibited significant similarity with insecticidal toxin proteins from
Photorhabdus luminescens
subsp.
laumondii
TT01.
Genome Sequence of
Bacillus anthracis
Strain Tangail-1 from Bangladesh
Authors: Rume Farzana Islam , Antwerpen Markus , Braun Peter , Biswas Paritosh Kumar , Yasmin Mahmuda , Grass Gregor , Ahsan Chowdhury Rafiqul , Hanczaruk Matthias 
Published: July 2016

ABSTRACT

Soil was collected in July 2013 at a site where a cow infected with anthrax had been the month before. Selective culturing yielded
Bacillus anthracis
strain Tangail-1. Here, we report the draft genome sequence of this
Bacillus anthracis
isolate that belongs to the canonical A.Br.001/002 clade.
Draft Genome Sequence of
Lewinella
sp. Strain 4G2 Isolated from the Coastal Sea Surface Microlayer
Authors: Wong Shu-Kuan , Yoshizawa Susumu , Nakajima Yu , Ogura Yoshitoshi , Hayashi Tetsuya , Hamasaki Koji 
Published: July 2016

ABSTRACT

We report here the draft genome of
Lewinella
sp. strain 4G2, isolated from the sea surface microlayer (SML) of a coastal marine inlet. The genome sequence of strain 4G2 should contribute to understanding the lifestyles of bacteria living in the SML.
Complete Genome Sequence of
Bacillus subtilis
subsp.
subtilis
Strain ∆6
Authors: Reuß Daniel R. , Thürmer Andrea , Daniel Rolf , Quax Wim J. , Stülke Jörg 
Published: July 2016

ABSTRACT

Bacillus subtilis
∆6 is a genome-reduced strain that was cured from six prophages and AT-rich islands. This strain is of great interest for biotechnological applications. Here, we announce the full-genome sequence of this strain. Interestingly, the conjugative element ICE
Bs
1 has most likely undergone self-excision in
B. subtilis
∆6.
Socioeconomic status influences the toll paediatric hospitalisations take on families: a qualitative study
Authors: Beck Andrew Finkel , Solan Lauren G , Brunswick Stephanie A , Sauers-Ford Hadley , Simmons Jeffrey M , Shah Samir , Gold Jennifer , Sherman Susan N ,   H2O Study Group
Published: July 2016

BackgroundStress caused by hospitalisations and transition periods can place patients at a heightened risk for adverse health outcomes. Additionally, hospitalisations and transitions to home may be experienced in different ways by families with different resources and support systems. Such differences may perpetuate postdischarge disparities.ObjectiveWe sought to determine, qualitatively, how the hospitalisation and transition experiences differed among families of varying socioeconomic status (SES).MethodsFocus groups and individual interviews were held with caregivers of children recently discharged from a children's hospital. Sessions were stratified based on SES, determined by the percentage of individuals living below the federal poverty level in the census tract or neighbourhood in which the family lived. An open-ended, semistructured question guide was developed to assess the family's experience. Responses were systematically compared across two SES strata (tract poverty rate of <15% or ≥15%).ResultsA total of 61 caregivers who were 87% female and 46% non-white participated; 56% resided in census tracts with ≥15% of residents living in poverty (ie, low SES). Interrelated logistical (eg, disruption in-home life, ability to adhere to discharge instructions), emotional (eg, overwhelming and exhausting nature of the experience) and financial (eg, cost of transportation and meals, missed work) themes were identified. These themes, which were seen as key to the hospitalisation and transition experiences, were emphasised and described in qualitatively different ways across SES strata.ConclusionsFamilies of lower SES may experience challenges and stress from hospitalisations and transitions in different ways than those of higher SES. Care delivery models and discharge planning that account for such challenges could facilitate smoother transitions that prevent adverse events and reduce disparities in the postdischarge period.Trial registration numberNCT02081846; Pre-results.
Armband activity monitor data do not correlate with reported pain scores in patients receiving vertebroplasty
Authors: Peacock Justin G , Vine Roanna L , McDonald Jennifer S , Novotny Paul J , Kallmes David F 
Published: July 2016

BackgroundPrior research on the efficacy of vertebroplasty has focused primarily on subjective, patient-reported outcomes.ObjectiveTo apply an armband activity monitor (SenseWear by BodyMedia Inc, USA) to patients presenting for consideration for vertebroplasty and to determine the correlation between patient-reported outcomes and quantitative activity metrics at baseline and 30 days after presentation.Materials and methodsNineteen patients were enrolled (15 receiving vertebroplasty, 4 not receiving vertebroplasty). Patients reported their average pain over the past 24 hours and completed the Roland–Morris disability questionnaire at baseline and 30 days. Patients wore the SenseWear Armband activity monitor for a median of 4 days at baseline and at the 30-day time period to assess steps, metabolic equivalents expended, sedentary activity time, moderate activity time, sleep efficiency, and total sleep time. Pain and disability scores were correlated with activity monitor metrics using linear regression analysis.ResultsChanges in reported average pain in the past 24 hours and disability scores were not significantly different between vertebroplasty and non-vertebroplasty groups (p>0.05). Changes in activity monitor data were not significantly different between the vertebroplasty and non-vertebroplasty groups (p>0.05). None of the correlations between the reported pain or disability scores and the activity monitor data were significant.ConclusionsActivity monitors can be used to objectively record changes in activity following vertebroplasty procedures. Patient-reported pain or disability scores do not correlate with activity monitor-measured activity or sleep metrics.
Green Route for Silver Nanoparticles Synthesis by Raphanus Sativus Extract in a Continuous Flow Tubular Microreactor
Authors: Jolhe P. D. , Bhanvase B. A. , Patil V. S. , Sonawane S. H. 
Published: July 2016

The present work deals with the investigation of the greener route for the production of silver nanoparticles using Raphanus sativus (R. sativus) bioextract in a continuous flow tubular microreactor. The parameters affecting the particle size and distribution were investigated. From the results obtained it can be inferred that the ascorbic acid (reducing agent) present in the R. sativus bioextract is responsible for the reduction of silver ions. At optimum condition, the particle size distribution of nanoparticles is found between 18[Formula: see text]nm and 39[Formula: see text]nm. The absorbance value was found to be decreased with an increase in the diameter of the microreactor. It indicates that a number of nuclei are formed in the micrometer sized (diameter) reactor because of the better solute transfer rate leading to the formation of large number of silver nanoparticles. The study of antibacterial activity of green synthesized silver nanoparticles shows effective inhibitory activity against waterborne pathogens, Shegella and Listeria bacteria.
How to Build Static Checking Systems Using Orders of Magnitude Less Code
Authors: Brown Fraser , Nötzli Andres , Engler Dawson 
Published: July 2016

Modern static bug finding tools are complex. They typically consist of hundreds of thousands of lines of code, and most of them are wedded to one language (or even one compiler). This complexity makes the systems hard to understand, hard to debug, and hard to retarget to new languages, thereby dramatically limiting their scope. This paper reduces checking system complexity by addressing a fundamental assumption, the assumption that checkers must depend on a full-blown language specification and compiler front end. Instead, our program checkers are based on drastically incomplete language grammars ("micro-grammars") that describe only portions of a language relevant to a checker. As a result, our implementation is tiny-roughly 2500 lines of code, about two orders of magnitude smaller than a typical system. We hope that this dramatic increase in simplicity will allow people to use more checkers on more systems in more languages.
We implement our approach in μchex, a language-agnostic framework for writing static bug checkers. We use it to build micro-grammar based checkers for six languages (C, the C preprocessor, C++, Java, JavaScript, and Dart) and find over 700 errors in real-world projects.
CSR
Authors: Shalev Noam , Harpaz Eran , Porat Hagar , Keidar Idit , Weinsberg Yaron 
Published: July 2016

One of the adverse effects of shrinking transistor sizes is that processors have become increasingly prone to hardware faults. At the same time, the number of cores per die rises. Consequently, core failures can no longer be ruled out, and future operating systems for many-core machines will have to incorporate fault tolerance mechanisms.
We present CSR, a strategy for recovery from unexpected permanent processor faults in commodity operating systems. Our approach overcomes surprise removal of faulty cores, and also tolerates cascading core failures. When a core fails in user mode, CSR terminates the process executing on that core and migrates the remaining processes in its run-queue to other cores. We further show how hardware transactional memory may be used to overcome failures in critical kernel code. Our solution is scalable, incurs low overhead, and is designed to integrate into modern operating systems. We have implemented it in the Linux kernel, using Haswell's Transactional Synchronization Extension, and tested it on a real system.
TPC
Authors: Jeon Myeongjae , He Yuxiong , Kim Hwanju , Elnikety Sameh , Rixner Scott , Cox Alan L. 
Published: July 2016

In interactive services such as web search, recommendations, games and finance, reducing the tail latency is crucial to provide fast response to every user. Using web search as a driving example, we systematically characterize interactive workload to identify the opportunities and challenges for reducing tail latency. We find that the workload consists of mainly short requests that do not benefit from parallelism, and a few long requests which significantly impact the tail but exhibit high parallelism speedup. This motivates estimating request execution time, using a predictor, to identify long requests and to parallelize them. Prediction, however, is not perfect; a long request mispredicted as short is likely to contribute to the server tail latency, setting a ceiling on the achievable tail latency. We propose TPC, an approach that combines prediction information judiciously with dynamic correction for inaccurate prediction. Dynamic correction increases parallelism to accelerate a long request that is mispredicted as short. TPC carefully selects the appropriate target latencies based on system load and parallelism efficiency to reduce tail latency.
We implement TPC and several prior approaches to compare them experimentally on a single search server and on a cluster of 40 search servers. The experimental results show that TPC reduces the 99th- and 99.9th-percentile latency by up to 40% compared with the best prior work. Moreover, we evaluate TPC on a finance server, demonstrating its effectiveness on reducing tail latency of interactive services beyond web search.
M3
Authors: Asmussen Nils , Völp Marcus , Nöthen Benedikt , Härtig Hermann , Fettweis Gerhard 
Published: July 2016

In the last decade, the number of available cores increased and heterogeneity grew. In this work, we ask the question whether the design of the current operating systems (OSes) is still appropriate if these trends continue and lead to abundantly available but heterogeneous cores, or whether it forces a fundamental rethinking of how systems are designed. We argue that: 1. hiding heterogeneity behind a common hardware interface unifies, to a large extent, the control and coordination of cores and accelerators in the OS, 2. isolating at the network-on-chip rather than with processor features (like privileged mode, memory management unit, ...), allows running untrusted code on arbitrary cores, and 3. providing OS services via protocols over the network-on-chip, instead of via system calls, makes them accessible to arbitrary types of cores as well.
In summary, this turns accelerators into first-class citizens and enables a single and convenient programming environment for all cores without the need to trust any application.
In this paper, we introduce network-on-chip-level isolation, present the design of our microkernel-based OS, M3, and the common hardware interface, and evaluate the performance of our prototype in comparison to Linux. A bit surprising, without using accelerators, M3 outperforms Linux in some application-level benchmarks by more than a factor of five.
ProteusTM
Authors: Didona Diego , Diegues Nuno , Kermarrec Anne-Marie , Guerraoui Rachid , Neves Ricardo , Romano Paolo 
Published: July 2016

The Transactional Memory (TM) paradigm promises to greatly simplify the development of concurrent applications. This led, over the years, to the creation of a plethora of TM implementations delivering wide ranges of performance across workloads. Yet, no universal implementation fits each and every workload. In fact, the best TM in a given workload can reveal to be disastrous for another one. This forces developers to face the complex task of tuning TM implementations, which significantly hampers their wide adoption. In this paper, we address the challenge of automatically identifying the best TM implementation for a given workload. Our proposed system, ProteusTM, hides behind the TM interface a large library of implementations. Underneath, it leverages a novel multi-dimensional online optimization scheme, combining two popular learning techniques: Collaborative Filtering and Bayesian Optimization.
We integrated ProteusTM in GCC and demonstrate its ability to switch between TMs and adapt several configuration parameters (e.g., number of threads). We extensively evaluated ProteusTM, obtaining average performance <3% from optimal, and gains up to 100x over static alternatives.
Scaling up Superoptimization
Authors: Phothilimthana Phitchaya Mangpo , Thakur Aditya , Bodik Rastislav , Dhurjati Dinakar 
Published: July 2016

Developing a code optimizer is challenging, especially for new, idiosyncratic ISAs. Superoptimization can, in principle, discover machine-specific optimizations automatically by searching the space of all instruction sequences. If we can increase the size of code fragments a superoptimizer can optimize, we will be able to discover more optimizations. We develop LENS, a search algorithm that increases the size of code a superoptimizer can synthesize by rapidly pruning away invalid candidate programs. Pruning is achieved by selectively refining the abstraction under which candidates are considered equivalent, only in the promising part of the candidate space. LENS also uses a bidirectional search strategy to prune the candidate space from both forward and backward directions. These pruning strategies allow LENS to solve twice as many benchmarks as existing enumerative search algorithms, while LENS is about 11-times faster.
Additionally, we increase the effective size of the superoptimized fragments by relaxing the correctness condition using contexts (surrounding code). Finally, we combine LENS with complementary search techniques into a cooperative superoptimizer, which exploits the stochastic search to make random jumps in a large candidate space, and a symbolic (SAT-solver-based) search to synthesize arbitrary constants. While existing superoptimizers consistently solve 9--16 out of 32 benchmarks, the cooperative superoptimizer solves 29 benchmarks. It can synthesize code fragments that are up to 82% faster than code generated by gcc -O3 from WiBench and MiBench.
Scalable Kernel TCP Design and Implementation for Short-Lived Connections
Authors: Lin Xiaofeng , Chen Yu , Li Xiaodong , Mao Junjie , He Jiaquan , Xu Wei , Shi Yuanchun 
Published: July 2016

With the rapid growth of network bandwidth, increases in CPU cores on a single machine, and application API models demanding more short-lived connections, a scalable TCP stack is performance-critical. Although many clean-state designs have been proposed, production environments still call for a bottom-up parallel TCP stack design that is backward-compatible with existing applications.
We present Fastsocket, a BSD Socket-compatible and scalable kernel socket design, which achieves table-level connection partition in TCP stack and guarantees connection locality for both passive and active connections. Fastsocket architecture is a ground up partition design, from NIC interrupts all the way up to applications, which naturally eliminates various lock contentions in the entire stack. Moreover, Fastsocket maintains the full functionality of the kernel TCP stack and BSD-socket-compatible API, and thus applications need no modifications.
Our evaluations show that Fastsocket achieves a speedup of 20.4x on a 24-core machine under a workload of short-lived connections, outperforming the state-of-the-art Linux kernel TCP implementations. When scaling up to 24 CPU cores, Fastsocket increases the throughput of Nginx and HAProxy by 267% and 621% respectively compared with the base Linux kernel. We also demonstrate that Fastsocket can achieve scalability and preserve BSD socket API at the same time. Fastsocket is already deployed in the production environment of Sina WeiBo, serving 50 million daily active users and billions of requests per day.
NVWAL
Authors: Kim Wook-Hee , Kim Jinwoong , Baek Woongki , Nam Beomseok , Won Youjip 
Published: July 2016

Emerging byte-addressable non-volatile memory is considered an alternative storage device for database logs that require persistency and high performance. In this work, we develop NVWAL (NVRAM Write-Ahead Logging) for SQLite. The contribution of NVWAL consists of three elements: (i) byte-granularity differential logging that effectively eliminates the excessive I/O overhead of filesystem-based logging or journaling, (ii) transaction-aware lazy synchronization that reduces cache synchronization overhead by two-thirds, and (iii) user-level heap management of the NVRAM persistent WAL structure, which reduces the overhead of managing persistent objects.
We implemented NVWAL in SQLite and measured the performance on a Nexus 5 smartphone and an NVRAM emulation board - Tuna. Our performance study shows the following: (i) the overhead of enforcing strict ordering of NVRAM writes can be reduced via NVRAM-aware transaction management. (ii) From the application performance point of view, the overhead of guaranteeing failure atomicity is negligible; the cache line flush overhead accounts for only 0.8~4.6% of transaction execution time. Therefore, application performance is much less sensitive to the NVRAM performance than we expected. Decreasing the NVRAM latency by one-fifth (from 1942 nsec to 437 nsec), SQLite achieves a mere 4% performance gain (from 2517 ins/sec to 2621 ins/sec). (iii) Overall, when the write latency of NVRAM is 2 usec, NVWAL increases SQLite performance by at least 10x compared to that of WAL on flash memory (from 541 ins/sec to 5812 ins/sec).