bluuebunny/crossref_metadata_2025_split huggingface dataset:
Lugné-Poe e l’Œuvre simbolista
Authors: Altamura Giuliana 
Published: November 2016

Il volume, nato dall’esigenza di rivalutare l’esperienza teatrale simbolista affrancandola dall’annoso pregiudizio sulla sua anti-teatralità, propone una ricostruzione storico-biografica della figura di Lugné-Poe – attore, regista, direttore, nonché principale animatore del teatro simbolista francese – e del suo teatro, l’Œuvre, per riconoscerne i tentativi di sperimentazione scenica. Ripercorrendo la prima parte della vita del protagonista di questa affascinante stagione, lo studio traccia – con un criterio rigorosamente cronologico – un capitolo fondamentale della storia del teatro, affrontato finora quasi unicamente dal punto di vista della teoria, della poetica e dell’analisi testuale. Partendo da un attento studio del contesto della nascita del teatro simbolista, la ricostruzione delle fortune alterne dell’Œuvre si sofferma, stagione per stagione, sui singoli spettacoli e sulla loro fortuna critica, oltre che sulle vicende interne delle relazioni umane e professionali intrattenute con artisti, scrittori, poeti, attori che per una ragione o per l’altra sfiorarono le vicende del teatro. Il volume, frutto di un ampio lavoro di documentazione, ricontestualizza l’esperienza dell’Œuvre alla luce della consapevolezza contemporanea, rilevandone l’importanza per gli sviluppi delle avanguardie e dando inoltre maggiore spessore alla personalità di Lugné-Poe, da cui la scelta di un taglio biografico che, attraverso la ricostruzione di una vicenda professionale tanto ricca, arrivi a descrivere l’uomo, testimone e attore di un momento epocale di trasformazione.
CD8αβ+ γδ T Cells: A Novel T Cell Subset with a Potential Role in Inflammatory Bowel Disease
Authors: Kadivar Mohammad , Petersson Julia , Svensson Lena , Marsal Jan 
Published: November 2016

Abstract
γδ T cells have been attributed a wide variety of functions, which in some cases may appear as contradictory. To better understand the enigmatic biology of γδ T cells it is crucial to define the constituting subpopulations. γδ T cells have previously been categorized into two subpopulations: CD8αα+ and CD8− cells. In this study we have defined and characterized a novel subset of human γδ T-cells expressing CD8αβ. These CD8αβ+ γδ T cells differed from the previously described γδ T cell subsets in several aspects, including the degree of enrichment within the gut mucosa, the activation status in blood, the type of TCRδ variant used in blood, and small but significant differences in their response to IL-2 stimulation. Furthermore, the novel subset expressed cytotoxic mediators and CD69, and produced IFN-γ and TNF-α. In patients with active inflammatory bowel disease the mucosal frequencies of CD8αβ+ γδ T cells were significantly lower as compared with healthy controls, correlated negatively with the degree of disease activity, and increased to normal levels as a result of anti–TNF-α therapy. In conclusion, our results demonstrate that CD8αβ+ γδ T cells constitute a novel lymphocyte subset, which is strongly enriched within the gut and may play an important role in gut homeostasis and mucosal healing in inflammatory bowel disease.
Thermal and Electrical Characterizations of Ultra-Thin Flexible 3YSZ Ceramic for Electronic Packaging Applications
Authors: Zhao Xin , Jagannadham K. , Reainthippayasakul Wuttichai , Lanagan Michael. T. , Hopkins Douglas C. 
Published: November 2016

Abstract
This paper presents thermal and electrical characterizations of an ultra-thin flexible 3YSZ (3 mol% Yttria Stabilized Zirconia) ceramic substrate to explore its potential for electronic packaging applications. The thicknesses of the ultra-thin 3YSZ substrates were 20 μm and 40 μm. The flexible thin ceramic substrate can provide not only better modulus for higher robustness in manufacturing, especially in Z-axis direction of modules, but also low thermal resistance for high density 2D (two dimensional) / 3D (three dimensional) power module packaging applications. To better understand the thermal and electrical properties of the ultra-thin flexible ceramic, different measurements were employed. Thermal conductivity was measured at different temperatures by 3-omega method, the results were verified by thermo-reflectance measurement at room temperature. Relative permittivity was measured from 100 Hz to 10 MHz, with dielectric losses determined by dielectric spectroscopy. The dielectric breakdown of the ultra-thin flexible 3YSZ was measured, from room temperature to 150 °C. Weibull analysis was performed on 20 measurements for each temperature. The test results showed that the thermal conductivity of 3YSZ decreased from 3.3 W/mK at 235 K to 2.2 W/Mk at 600 K. The relative permittivity decreased from 30.9 to 27.3 for higher frequencies for both substrates with different thickness. The temperature-dependence of relative permittivity and dielectric loss was studied. The results showed that these two parameters increased slowly from −65 °C to 150 °C, but more repidly from 175 °C to 250 °C. The dielectric breakdown decreased at higher temperature, from 5.76 kV to 2.64 kV for thickness of 20 μm, 7.84 kV to 3.36 kV for thickness of 40 μm. SEM (Scanning Electron Microscopy), EDS (Energy-dispersive X-ray Spectroscopy) and XRD (X-ray Powder Diffraction) analysis was performed to compare the microstructure of 3YSZ ultra-thin substrate and that of AlN (Aluminum Nitride) substrate. The microstructure of 3YSZ consisted of smaller round particles and that of AlN contained larger columnar particles. FEA (Finite Element Analysis) simulations were also applied to demonstrate the thermal properties of 3YSZ in simplified model of power modules. Though the measurement results showed that it did not meet expectations for high temperature power modules, the present work showed potential applications of the ultra-thin 3YSZ substrates in low voltage power modules, LED modules.
Higher Efficiency Power Module Solutions by Chip Embedding
Authors: Essig Kay S , Chiu CT , Kuo Jarris , Chen Phidia , Yannou Jean-Marc 
Published: November 2016

Abstract
The development in communication handheld devices has pushed the demand for packages with high level of functionality and complexity at the same time smaller package outline and decreased package thickness. Embedding active dies and/or passive components into the substrate is fulfilling these integration requirements, but embedding can have further beneficial effects (electrical performance, thermal dissipation, shielding) that deliver more benefit for embedding (1).
Whereas embedding dies in substrates seems a simple concept, it can come with strong advantages as found in the described case for Power Modules in terms of electrical performance and thermal dissipation.
In this paper we shall report the development of embedded technologies for Power Modules and compare electrical performance, thermal dissipation and reliability results with other Power Module package types. We shall report on an intelligent power module for server applications up to 1.5kW consisting of a driver IC and 2 MOSFETs using embedded die in substrate technology in high volume manufacturing.
We will describe the development of next generation embedding technologies for Power Modules, their expected benefits and respective application targets together with simulation results. We conclude with a brief overview of the challenges that come with embedded packaging supply chain.
Direct write lithography approach for Panel Level Package
Authors: Matsui Hiroshi , Nagao Tatsuya , Norimitsu Yoshinao 
Published: November 2016

Abstract
Fan-out processing a is booming technology at wafer level packaging. However, chip last process in fan-out gives great difficulty to lithography. At the same time, the industry is looking for increasing substrate size in order to reduce production cost. Direct write technology shall be the key lithography process having both flexibility and compatibility for large size substrate.
A deeper understanding on the motion behaviors of wire during ultrasonic wedge-wedge bonding process
Authors: Long Yangyang , Dencker Folke , Wurz Marc , Feldhoff Armin , Twiefel Jens 
Published: November 2016

AbstractUltrasonic wire bonding is a dominating interconnection technique that has been applied in packaging industry for decades. The phenomena at the wire/substrate interface and the wire/tool interface, however, are not clear yet. Specifically, the motion behaviors of the wire during the bonding process have to be deeply understood. In this project, the relative motion amplitudes at the wire/tool interface and the self-cleaning efficiency at the wire/substrate interface are investigated via the analysis of an artificially coated layer. For each experiment, a thin layer made of a specific material was coated onto the surface of a 400 μm wire by physical vapor deposition. The change of thicknesses of the layer was observed by a scanning electron microscope after the bonding process. The results indicated a complex relative motion behavior at the wire/tool interface. The relative motion amplitude at the fillets contact regions is higher than that at the other contact perimeter regions while the amplitude at the central area is the lowest. The insignificant influence of a 200 nm aluminum oxide layer on the bonding quality demonstrated the high self-cleaning efficiency of the wedge-wedge bonding process.
Advances in Wire Bonding Technology for Overhang Applications
Authors: Shah Aashish , Schulze Gary , Mendoza Nestor , Yang J.H. , Ellenberg Rob , Qin Ivy , Chylak Bob 
Published: November 2016

Abstract
Wire bonding is the most popular interconnect technology and the workhorse of the semiconductor packaging industry. Wire bonding is widely used for 3D packaging in which multiple dies are often stacked vertically in a ‘stacked die’ configuration. In such packages, one or more dies may be unsupported in an ‘overhang’ (e.g. cantilever beam) configuration. Wire bonding on an overhang die causes die deflection. If not optimized, it may lead to improper ball shape, inconsistent looping, pad crack and die crack issues. Therefore, careful process optimization is needed to have the best outcome in wire bonding performance. This optimization is often tedious and time-consuming. Moreover, recent trends towards minimizing package size (e.g. ultra-thin dies) and increasing number of die stacks add to the challenges of optimizing a wire bonding process for overhang devices.
This paper examines the challenges of wire bonding on overhang devices. Finite element analysis (FEA) of overhang devices is presented. Die deflection data obtained from the FEA correlates well with the experimental results obtained on the ball bonder. The FEA results show that die deflection increases significantly with decreasing die thickness and increasing overhang distance. Other factors such as substrate thickness, and bonding temperature also effect die deflection, although less significantly than die thickness and overhang distance. Various considerations for optimizing a ball bonding process on overhang devices are discussed. Experimental results of ball bonding optimization on 50 μm and 75 μm thick overhang devices with different overhang configurations are presented.
In-situ measuring module for transfer molding process monitoring
Authors: Kahle R. , Braun T. , Bauer J. , Becker K.-F. , Schneider-Ramelow M. , Lang K.-D. 
Published: November 2016

Abstract
While Moore's Law is slowing down heterogeneous integration and System-in-Package (SiP) are taking up the challenge towards further miniaturization. To ensure reliability of these packages often encapsulation by transfer molding is used – providing a highly productive and cost effective device housing. Though transfer molding is the dominant process for microelectronics encapsulation, the process details are typically not accessible directly but only via machine settings. To understand more of the mold process further research needs to be conducted to get inside information from the process. A sensor based system was developed to in-situ measure transient material data and process parameters. The temperature of the tool and melt front, the cavity pressure and cure related dielectric material data was measured with a first prototype.
Summarized this paper presents the development of a sensor based system to in-situ measure characteristic material properties and process parameters in a transfer mold machine. The in-situ measurement tool allows a live documentation, optimization and knowledge extension of transfer mold processes parallel to FEM simulation and external measuring like DSC analysis. The sensor approach can lead to material driven self-adjusting transfer mold machines with an economized process.
Alternative Metallurgies for MEMS Lid Seal
Authors: Shearer Catherine 
Published: November 2016

Abstract
MEMS devices are a segment of the electronics industry enjoying explosive growth. With the advent of the internet of things (IoT), the trajectory for growth will continue to be steep and price pressures on both the devices and packaging will be intense.
Current MEMS packaging schemes rely heavily on an architecture that employs a metal-can or laminate “lid” attached to the device package with a solder ring. This ring serves to connect the package elements together mechanically and to protect the device from noise (electronic or acoustic) and environmental damage.
Like most modern electronic devices, MEMS devices are subject to the challenges imposed by the requirement for lead-free packaging. As with many devices, solder connections formed within the package have a similar composition, and therefore a similar reflow profile, to the solder used to attach the packaged components to a substrate. Devices that yield well at the manufacturer are thus susceptible to field failure at the assembly site induced by remelting of the solder within the package during assembly reflow. Unlike in SIP packages where the solder joints in the module are often encased in mold compound, the ring seal in MEMS devices is exposed and unreinforced resulting in failures such as lid shift, solder flow or flux contamination in the device cavity, and package deconstruction - particularly during rework. These type of post-fabrication yield losses can be very costly.
Transient liquid phase (TLPS) sintering paste compositions are a new class of solder replacement materials that can be processed at typical reflow temperatures, but which do not remelt when subjected to subsequent thermal excursions. TLPS pastes combine solder alloy particles and reactive metal particles in proportions such that the solder ‘thermosets’ during a typical solder reflow cycle. This ‘thermosetting’ behavior results in a joint that does not remelt at the original reflow temperature, and thus enables the highly reliable electrical interconnect essential for assemblies that will undergo subsequent reflow excursions.
TLPS pastes are similar to solders in many respects. The electrical, thermal and mechanical performance is similar to conventionally used tin-based solders. The TLPS pastes are stored and applied like solder pastes. The reflow cycles used to form the TLPS paste joints are also similar to those for forming solder joints. However, unlike solder, TLPS materials do not change shape during reflow or wet substrates beyond the deposition footprint. Also unlike solder, the metals within the bulk of the TLPS interconnect react with one another resulting in a stable interconnect with a thermally robust bonding structure to joining surfaces, even after subsequent thermal cycles. These attributes present both unique opportunities and unique challenges for addressing MEMS lid seal applications. This paper will explore the key material and engineering challenges for implementation of TLPS paste in MEMS lid seal applications.
The Die Embedded and RDL structure on the high density substrate (i-THOP®) for mobile application
Authors: Kyozuka Masahiro , Yoshida Tatsuro , Shimizu Noriyoshi , Tanaka Koichi , Koyama Tetsuya 
Published: November 2016

Abstract
The current trend in the electronics industry is one of increased computing performance, combined with a seemingly unending demand for portability and increased miniaturization; this is especially evident in the significant changes to the semiconductor device. To sustain the performance-improvement trend without increasing total cost, the partitioning of single die into a multi-chip architecture is widely studied in industry. These partitioned chips are then integrated into a single system-in-package (SiP).
However, partitioning a single die into multiple split die causes two major challenges. The first is that it creates the need for very high density die to die interconnection. This interconnection is needed to provide enough routing density between the multiple die. Based on design studies, it believes that 2μm line and 2μm space is required in the package substrate.
The second challenge is created by the increase in the overall die size. After partitioning the single die, each resulting smaller die must have its own I/O circuits, and effectively increases the total die area. This increase is a penalty, as mobile devices have a limited package size. When comparing a conventional package on package (PoP), the SiP requires a higher pin count with a finer pitch connection between the die and the memory. This finer pitch is needed to have enough I/Os, but within a limited package size to support mobile devices.
To overcome these challenges, the structure of i-THOP® with POP pad, named “i-THOP® with Die embedded +ReDestribution Layer(RDL) structure”, has been developed. Herein, i-THOP® (integrated Thin film High density Organic Package) is a type of high-density substrate A key aspect to development of Die embedded +RDL is forming the multiple redistribution layers (RDL) over die and the fine pitch via connection. To achieve this, the proper material set was selected based on stress simulations and basic experiments. Regarding the manufacturing process, a conventional printed-circuit board (PCB) production line was used to minimize production cost. This article reports the manufacturing process and characteristics of the structure.
Voltammetric Detection of Low Copper Concentrations in Nickel Plating Baths
Authors: Pavlov Michael , Coffin Mitchell , Lin Danni , Shalyt Eugene 
Published: November 2016

Abstract
Nickel electroplating is widely used in semiconductor manufacturing, primarily during the packaging stage. It is not used as a final coating, but instead as a barrier layer to prevent formation of copper–tin intermetallic compounds that affect the reliability of solder joints. The nickel is deposited from baths containing nickel salt (in relatively high concentrations), boric acid, and other ions.
The quality of the deposited nickel is highly dependent on the composition of the plating bath. Metallic contaminants are acceptable when their concentrations are below approximately 30 ppm. Copper, lead, zinc, and cadmium, even in relatively small quantities (higher than 30 ppm) produce a dull, black, or skip plate condition in the low-current-density areas. These metals may be removed from the plating solution by low-current-density dummy plating, but a sensitive and accurate analytical method must be used to determine when to treat the bath. Copper is considered a main contaminant due to its higher concentrations in the bath and its most detrimental effect on the nickel deposit. To prevent plating defects, the bath contaminants must be monitored.
Addressing Flux Dip Challenges for 3D Integrated Large Die, Ultra-fine Pitch Interconnect
Authors: Marsan-Loyer C. , Danovitch D. , Boyer N. 
Published: November 2016

Abstract
The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5D/3D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent upon the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces in order to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, while excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This paper presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die with ultra-fine pitch (60 μm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behaviour and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e. cleaning and underfill) as well as product reliability.
Electrodeposited copper-graphite composites for low-CTE integrated thermal structures
Authors: Dwarakanath Shreya , Raj P. Markondeya , Demir Kaya , Smet Vanessa , Sundaram Venky , Tummala Rao 
Published: November 2016

Abstract
Emerging high-power and high-temperature electronic modules require thick copper structures for power-supply, thermal vias, heat-spreaders, and also as carriers or lead-frames for high-power packages. Such structures should coexist with glass and other low-CTE substrates to meet high-temperature performance, dimensional stability and superior device interconnection reliability with low stresses and warpage. The primary challenge with these packages arises from the coefficient of thermal expansion (CTE) mismatch between the conductors and the substrates. Cu-graphite composites with glass-matched CTE are explored to address this challenge through analytical modeling of properties such as CTE, Young's modulus and thermal conductivity, FEM predictions of glass warpage and stresses, process development to deposit copper-graphite composite films with high graphite loading of 64 vol. %, and warpage measurements using shadow-moiré. Results indicate that Cu-graphite composites can mitigate the warpage and stress issues in high-temperature and high-power packages.