bluuebunny/crossref_metadata_2025_split huggingface dataset:
Planar Antenna for Terahertz Application in Fan Out Wafer Level Package
Authors: Ishibashi Daijiro , Nakata Yoshihiro 
Published: November 2017

Abstract
This paper shows the terahertz planar antenna integration module structure using a fan out wafer level package (FOWLP), and the important parameters when that structure is designed. A FOWLP enabled a low-loss connection. Embedding an insulator and reflector into the mold resin improved flexibility of the module design. In this paper, the patch antenna was employed as a planar antenna in a proposed structure, and that antenna was operated at 300 GHz. For the design of this structure, two parameters were noted as the most important factors. One was the thickness of the insulator of the patch antenna. The optimal thickness of between 40 μm and 80 μm allowed the radiation efficiency to remain high. The other factor was the gaps of the vias between the ground of the microstrip line and the reflector. The gaps of a quarter-wavelength or less made the antenna characteristics excellent.
Fully Printed Static Gain Reconfigurable Conformal Patch Antenna Arrays
Authors: Grant Nolan , Haghzadeh Mahdi , Akyurtlu Alkim 
Published: November 2017

Abstract
This work presents design and fabrication processes for creating statically gain-reconfigurable conformal patch array antennas. In our previous work, a fully printable and conformal antenna array on a flexible substrate with a new Left-Handed Transmission Line (LHTL) phase shifter based on a Barium Strontium Titanate (BST)/polymer composite was computationally studied for radiation pattern correction and beam steering applications. In this work, additive manufacturing techniques were used to experimentally demonstrate the phase compensation needed to improve the degraded performance of the conformal arrays. An Aerosol Jet direct-write printer was used to print several patch antenna arrays and was tested in an anechoic chamber to establish baseline gain metrics. Once a baseline is established, a high dielectric constant material (BST nano-ink) was dispensed onto the IDCs in several configurations, to provide the necessary phase compensation. The antennas were retested and the changes in their gain profiles were investigated. The findings of this work and the proposed method allow for gain compensation of curved conformal antennas and post-production modification of the radiation pattern of antenna arrays. This work has potential applications in the automotive industry due to the low cost of production and the ability to be integrated onto curved conformal surfaces without interfering with super structure or other mechanical design related criteria.
RELIABILITY; WHAT'S RIGHT FOR YOUR BUSINESS?
Authors: Mohanty Rita 
Published: November 2017

Abstract
In today's high-tech world, we heavily depend on electronics for our health, safety, mobility and economic welfare. When they fail, the results can be as minor as consumer annoyance to as severe as loss of life. Not to mention a significant financial penalty to the producer in the form of warranty cost. In the electronics industry, especially in the consumer electronics segment, warranty expense cost can be 1% - 2% of the total revenue1. As an example, for a $1B company, this can impact the bottom line by $10M–$20M. For this reason, reducing warranty cost through increased product reliability is not only necessary for survival but also smart.
However, achieving product reliability in today's environment with limited development resources and demand for reducing product development cycle time creates a special challenge. In addition, many small to medium size organizations struggle to understand the basic concepts behind reliability engineering, often confusing it with quality. This paper presents a lean approach to developing and implementing a reliability program that is simple, flexible and woven into a product development program.
Modeling Vibration Induced Fatigue Failure of Free Standing Wire Bonds
Authors: Shen Zhenzhen , Storey James , Fanini Otto , Osterman Michael 
Published: November 2017

Abstract
Wire bonds are used to connect device terminals to package terminals or substrate terminal that forms circuits that are needed to create desired higher level functions. If a wire bond breaks or becomes detached during operation, the desired function will be lost. Depending on the design, a loss in function could be catastrophic. Aluminum, gold, and copper wires are used to create wire bonds in electronic products. These materials have been selected for their ability to be formed as fine wires and their ability to provide low electrical resistance.
In many electronics packages, wire bonds are encapsulated in a polymer molding compound that is used to protect the electronic device. However, in some electronic devices such as hermetically sealed cavity packages, wire bonds may be free-standing. Under vibration loading, free-standing wire bonds may be subject to failure due to mechanical fatigue.
In this work, an analytic model is presented for predicting natural frequency of a free-standing wire bond and for assessing a wire bond time to failure under a harmonic loading condition. The model for natural frequency is calibrated by finite element analysis and validated through experimental testing. The life prediction model, a test plan, and preliminary test results are presented.
Reinforced Solder Technology for Increased Reliability
Authors: Jensen Tim , Neoh Sunny , Murling Adam 
Published: November 2017

Abstract
The reliability of solder joints have been studied for many years. The selection of a solder for a particular application is often limited based on melting point requirements. This limits the number of options that are available for use. When alloy selection options are limited, people look to process changes to try and improve the reliability. Two such areas that have been identified that can impact reliability are bondline control and void reduction. This paper analyzes a new reinforced solder technology to maintain a consistent solder joint bondline. Experiments were also conducted to determine how best to design these preforms to minimize voiding.
Reduction of Thermal Stress - Part III: UBM and Passivation Thickness Optimization
Authors: Sethu Raj Sekar , Kulkarni Salil Hari , Ha How Ung , Soon Kok Heng 
Published: November 2017

Abstract
Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps. Finite Element Analysis (FEA) of such designs can help identify possible root causes early in the design process and i.e. before actual fabrication. This would help save valuable prototyping & testing costs. In Part III of this series of FEA studies, two factors i.e. silicon nitride thickness (from the BEOL process), and the Under Bump Metalization (UBM) thickness (from the WLP process) were identified as significant factors in changing the maximum first principal stress levels in the passivation layer.
Supply Chain Hardware Integrity for Electronics Defense (SHIELD) Using Small “Dielets”
Authors: Chorosinski Len , Sundaram Venky , Wolter Klaus , Calatayud Richard , Ralston Parrish , Suko Scott , Fry David , Ellerhoff Nathanael 
Published: November 2017

Abstract
Under the DARPA/MTO SHIELD program, a Northrop Grumman led team is developing a supply chain traceability and authentication method to protect against the growing threat of counterfeit electronic parts. The foundation of our SHIELD solution is an advanced 100μm × 100μm × 20μm near-field RFID “dielet” fabricated on 14nm CMOS. This dielet will be embedded in a host component's packaging and provides a hardware root-of-trust through the integration of advanced key protection and cryptographic techniques. Throughout the life-cycle of the host component, the authenticity can be verified using an RF probe to energize and communicate with the dielet, performing a cryptographic challenge and providing a response to a centralized secure server and SHIELD authenticity database. This paper provides a general overview of the dielet design, packaging, and host component insertion.
This research was developed with funding from the DARPA. The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.
Nondestructive Imaging of Packaged Microelectronics using Pulsed Terahertz Technology
Authors: Bowman Tyler , El-Shenawee Magda 
Published: November 2017

Abstract
This work presents the use of terahertz reflection imaging for nondestructive evaluation of packaged microelectronics. Power MOSFETs and SRAM devices are placed in a pulsed terahertz imaging system in the reflection mode with an incident angle of 30°. From the received signal at each point on the sample under test, the internal structure of the device can be clearly seen. For transistors, terahertz nondestructive imaging has been successful in determining die size and location as well as the bond wire size, number, and connections. High-pass frequency filters are utilized to enhance the image quality for viewing the bond wires. In addition, the terahertz B-scans are used to determine additional information including the vertical position of the bond wires and the die inside the packaged device. For the SRAM, the terahertz nondestructive imaging shows similar effectiveness in defining the layout of the metal connections inside the package and the wire positions. Thus terahertz imaging is shown to have a strong potential for nondestructive evaluation of these devices.
Development of Thinner POP Base Package by Die Embedded and RDL Structure
Authors: Kyozuka Masahiro , Kiso Takahiko , Toyazaki Hiroki , Tanaka Koichi , Koyama Tetsuya 
Published: November 2017

Abstract
As mobility products, such as smart phones, tablets and wearable devices, continue on the paths of both miniaturization and high performance, components and packaging are likewise driven to become smaller and thinner. In mobile devices, a thinner package is required, especially for the Application Processor and memory combination.
The Package-on-Package structure can achieve module thinness by embedding a die (or dies) into a package and is thus attractive for reducing the height of an AP. The Die-Embedded and RDL structure has been in development as a package corresponding to POP structure. This structure has two characteristics of manufacturing method, based on the substrate manufacturing process. One is the RDL-first process, whereby the RDL is manufactured before die attachment. This process decreases the die loss from defects in the RDL formation. The other method is to manufacture the packages in panel form instead of wafer form.
The key features of this structure are panel-form manufacturing and via connection between the substrate and the top-RDL. In IMAPS 2016, the Die Embedded and RDL structure on i-THOP®, which was used as the substrate was reported. The die-to-die inter connection was fabricated on i-THOP® for a 2.1D application. Both the die attachment and the RDL formation were successfully performed. The reliability tests proceeded. The results indicated that the i-THOP® with the Die Embedded and RDL structure can be applied to packaging of AP in mobile devices.
The next challenge is to make a smaller package using the Die Embedded and RDL structure. To decrease the package area, a finer-pitch via connection that was less than the design rule of 200μm was evaluated. For reduction of package thickness, a thinner substrate, approximately 160μm thickness, was applied. The new test sample with these improvements was designed and proceeded to evaluation. The dimensions of the sample are 15 × 15 mm2 size and 340μm thickness (without solder ball), a 100μm-thick die was embedded and a one-layer of RDL was formed on the die.
In this development, the warpage of the thin substrate after die attachment might be large, so there is an issue of package warpage and the handling of a thin substrate. In this report, results of low warpage structure design and development status of fine via connection formation are described.
Cost Comparison of Fan-out Wafer-Level Packaging to Embedded Die Packaging
Authors: Palesko Chet , Lujan Amy 
Published: November 2017

Abstract
Fan-out wafer-level packaging (FOWLP) and embedded die packaging offer similar advantages over traditional packaging technologies. For example, both packages can be quite thin since the die is placed early in the manufacturing process and the package is fabricated around the die. This is in contrast to traditional packaging technologies, in which the package is fabricated first, and then the die is placed on top of the package. This results in a thicker package compared to fabricating the package around the die. Due to the ongoing miniaturization market requirements, thinner packages are becoming increasingly important. Both FOWLP and embedded die packaging also provide the capability of placing multiple die and passives in a single package. This capability can have both size and performance benefits since the interconnect distance between the embedded components is shorter.
In this paper, the cost and cost drivers of FOWLP and embedded die packaging technologies will be compared. Activity based modeling will be used to characterize the cost of each activity in the two manufacturing flows.
Multichip Module Planarity Requirements Derived From Solder Surface Tension Models
Authors: Marinis Thomas F. , Soucy Joseph W. 
Published: November 2017

Abstract
The number of die and routing layers in multichip modules has been steadily increasing, which has exasperated the problem of maintaining module planarity for interconnect to a system board. The usual remedies are to try to balance the composition of the layers on either side of the module's neutral axis or to build the layers on a stiff, planar interposer. Both of these approaches can impact module performance, size and cost. We have examined an alternative approach to accommodating module bow, by allowing the solder ball interconnects to compress or elongate as necessary to maintain electrical connections. This approach is further enhanced by making the module very thin, which does not reduce its bow, but rather allows the high surface tension force exerted by molten solder to flatten the module. We have derived a model for the surface tension force exerted by a solder ball as a function of the degree to which it is compressed or elongated. This model also predicts the maximum elongation that the solder connection can sustain before it ruptures. We have applied this model in a design tool, which allows us to predict the maximum module bow that can be accommodated as a function of the number, size and location of the solder connections and the physical composition of the multichip module.
High Reliability and High Throughput Ball Bumping Process Solution – Solder Joint Encapsulant Adhesives
Authors: Liu Mary , Yin Wusheng 
Published: November 2017

Abstract
The miniaturization of microchips is always driving force for revolution and innovation in the electronic industry. When the pitch of bumps is getting smaller and smaller the ball size has to be gradually reduced. However the reliability of smaller ball size is getting weaker and weaker, so some traditional methods such as capillary underfilling, corner bonding and edge bonding process have been being implemented in board level assembly process to enhance drop and thermal cycling performance.
These traditional processes have been increasingly considered to be bottleneck for further miniaturization because the completion of these processes demands more space. So the interest of eliminating these processes has been increased. To meet this demand, YINCAE has developed solder joint encapsulant adhesives for ball bumping applications to enhance solder joint strength resulting in improving drop and thermal cycling performance to eliminate underfilling, edge bonding or corner bonding process in the board level assembly process. In this paper we will discuss the ball bumping process, the reliability such as strength of solder joints, drop test performance and thermal cycling performance.
Power cycle reliability of SiC devices with metal-sinter die-attach and thermostable molding
Authors: Nagao Shijo , Fujita Hirofumi , Shimoyama Akio , Seki Shinya , Zhang Hao , Suganuma Katsuaki 
Published: November 2017

Abstract
Metal paste sintering die-attach is recently attracting much attention as an alternative to Pb containing high temperature solders, particularly required for power device packaging with post-Si wide band-gap semiconductors. For high voltage and high power devices, which are used in electric vehicles, railway trains, or power grid systems, SiC MSOFET/SBD devices are emerging replacing Si IGBT devices. These SiC devices have two prominent advantages to traditional Si based devices: fast switching and high maximum junction temperature TJ. The excellent characteristics serve for miniaturization of the device module; the former allows to use smaller capacitor and reactors because of the high frequency, and the latter excludes cooling system without affecting the device life time. However, the thermal reliability should be critically tested before used in industrial applications. We have hence conducted comprehensive reliability tests using several types of metal sintering die-attach including Ag and Cu. High temperature storage tests at 250°C certify that the device structure is truly thermostable, and thermal cycling between −50°C and 250°C indicates that the thermomechanical stress caused by device package design is the key for high reliability of power devices. Power cycling demonstrates the usefulness for effective acceleration tests to estimate the device life time. Our results conclude that present metal paste die-attach is ready for use in the product instead of high temperature solders.
Temperature and Process Dependent Material Characterization and Multiscale Stress Evolution Analysis for Performance and Reliability Management under Chip Package Interaction
Authors: Karmarkar Aditya P. , Xu Xiaopeng , El-Sayed Karim 
Published: November 2017

Abstract
Distinct temperature and process dependent deformation behaviors under packaging temperature cycles are characterized for various packaging materials. Substrate and underfill deformations are described using Maxwell viscoelasticity model. Solder bump deformation is represented by incremental plasticity model. Anisotropic deformation in silicon and orthotropic deformation in substrate are also considered. The material deformation effects on stress evolutions during fabrication and under chip package interaction (CPI) are analyzed for a large package structure. Complex geometries spread over a large range of length scales are simulated using multi-level and multiscale sequential submodeling technique. Global package simulations show that substrate orthotropy has a significant impact on the package warpage during the assembly process. Sequential package assembly simulations are performed to examine the residual stresses at package, bump and interconnect scales. The results show that the package material behaviors during the assembly process affect not only the residual stresses in the large package structure but also in the local bump regions and the interconnect structures. The temperature dependent material non-linear behaviors under operating conditions also affect residual stresses and carrier mobility. This work demonstrates that developing performance and reliability management strategies under CPI should consider temperature and process dependent material deformations during fabrication and packaging.
Fine Resolution Photosensitive Polyimide Dry Film with High Resistance to Electromigration under HAST condition
Authors: Tomikawa Masao , Matsumura Kazuyuki , Shoji Yu , Tatsuta Yoshiko , Okuda Ryoji 
Published: November 2017

Abstract
We investigated the effects of photosensitive system (positive and negative) and polymer structures on Cu migration under bias HAST test. The HAST condition is 130C for 85% RH. Bias condition is 2MV/m. We found that there is polyimide structure shows big effect is big effect of no big difference between negative photosensitivity and positive photosensitivity in photo sensensitive polyimides. Polyimide structure effects significant difference on Cu migration under bias HAST condition. Cu migration of soft polyimide seems better than that of rigid polyimide. From these results, we developed good reliable photosensitive polyimide B-sheet having fine pattern capability successfully.
Packaging and Miniaturization of a 2–18 GHz UWB Radar for Measurements of Snow and Ice: Initial Results
Authors: Morales F. R. , Leuschen C. , Feathers A. , McDaniel J. , Wolf A. , Garrison S. 
Published: November 2017

Abstract
We report recent progress towards miniaturizing and packaging an ultra wideband (UWB) radar developed for measurements of ice and snow over the 2–18 GHz range. The initial objective of this work is the close integration of the radar's RF section (composed of a receiver and a low-power transmitter) while maintaining or enhancing its electrical performance. First, we describe a connectorized reference system developed to serve as a performance benchmark for transmit and receive signal chains. Next, we discuss the use of drop-in modules to achieve a significant size reduction of the RF front-end. These modules are based on packaged chips and arranged in a planar configuration. We present system-level performance metrics of the reference system justifying the need for further integration. We briefly discuss other potential applications of the miniaturized radar and the direction of future packaging efforts as we work toward our future goal of integrating the complete radar “from antenna to bits” by using a system-in-package approach.
3D Printed Metalized Plastic Waveguides for Microwave Components
Authors: Ghazali Mohd Ifwat Mohd , Park Kyoung Youl , Gjokaj Vincens , Kaur Amanpreet , Chahal Premjeet 
Published: November 2017

Abstract
This paper investigates the design and fabrication of 3D printed waveguide and their application for the design of microwave passive components. This includes a simple waveguide structure, a band pass filter, and a leaky wave. A Lego-like approach is used to assemble together different 3D printed sub-sections after metal coating. These allow the structure to be fabricated in multiple layers. Simulation and measured results match closely. Details of modeling, fabrication and measurement are presented for these three passive components.