bluuebunny/crossref_metadata_2025_split huggingface dataset:
Pulmonary toxoplasmosis in immunocompromised patients with interstitial pneumonia: a single-centre prospective study assessing PCR-based diagnosis
Authors: Desoubeaux Guillaume , Cabanne Églantine , Franck-Martel Claire , Gombert Martin , Gyan Emmanuel , Lissandre Séverine , Renaud Marc , Monjanel Hélène , Dartigeas Caroline , Bailly Éric , Van Langendonck Nathalie , Chandenier Jacques 
Published: January 2016

AimsPulmonary toxoplasmosis has become a very rare parasitic infection since the advent of highly active antiretroviral therapies. It is generally diagnosed by the direct microscopic observation ofToxoplasma gondiitachyzoites in bronchoalveolar lavage fluid (BALF). The aim of this study was to assess possible improvements in diagnostic performance associated with the use of real-time PCR.MethodsThis prospective study was carried out on BALFs obtained from immunocompromised patients over a 2-year period. We systematically compared the results of conventional staining with those of molecular detection.ResultsTwo cases of pulmonary toxoplasmosis were diagnosed for a total of 336 samples. PCR did not detect any additional cases and was more time-consuming than conventional staining.ConclusionsConventional staining is a reliable technique and is probably the most appropriate method for experienced microbiology laboratories, whereasT. gondii-specific PCR may be useful for laboratories with less experience in parasitology.Trial registration number2015_030, May 27th 2015.
Oxyntic gastric atrophy inHelicobacter pylorigastritis is distinct from autoimmune gastritis
Authors: Venerito Marino , Varbanova Mariya , Röhl Friedrich-Wilhelm , Reinhold Dirk , Frauenschläger Katrin , Jechorek Doerthe , Weigt Jochen , Link Alexander , Malfertheiner Peter 
Published: January 2016

AimTo assess characteristics of oxyntic gastric atrophy (OGA) in autoimmune gastritis (AIG) compared with OGA as a consequence ofHelicobacter pyloriinfection.MethodsPatients undergoing oesophagogastroduodenoscopy from July 2011 to October 2014 were prospectively included (N=452). Gastric biopsies were obtained for histology andH. pyloritesting. Serum gastrin-17 (G17), pepsinogen (PG) I, PGII and antibodies againstH. pyloriand cytotoxin-associated gene A protein were determined in all patients. Antibodies against parietal cells and intrinsic factor were determined in patients with advanced (moderate to severe) OGA. Areas under the receiver operating characteristic curves (AUCs) were calculated for serum biomarkers and compared with histology.ResultsOverall, 34 patients (8.9%) had advanced OGA by histology (22 women, age 61±15 years). Current or pastH. pyloriinfection and AIG were present in 14/34 and 22/34 patients, respectively.H. pylori-negative AIG patients (N=18) were more likely to have another autoimmune disease (OR 6.3; 95% CI 1.3 to 29.8), severe corpus atrophy (OR 10.1; 95% CI 1.9 to 54.1) and corpus intestinal metaplasia (OR 26.9; 95% CI 5.3 to 136.5) compared withH. pylori-positive patients with advanced OGA. Antrum atrophy was present in 39% ofH. pylori-negative AIG patients. The diagnostic performance of G17, PG I and PGI/II was excellent for AIG patients (AUC=0.83, 0.95 and 0.97, respectively), but limited forH. pylori-positive patients with advanced OGA (AUC=0.62, 0.75 and 0.67, respectively).ConclusionsH. pylori-negative AIG has a distinct clinical, morphological and serological phenotype compared with advanced OGA inH. pylorigastritis.
Semantic locality and context-based prefetching using reinforcement learning
Authors: Peled Leeor , Mannor Shie , Weiser Uri , Etsion Yoav 
Published: January 2016

Most modern memory prefetchers rely on spatio-temporal locality to predict the memory addresses likely to be accessed by a program in the near future. Emerging workloads, however, make increasing use of irregular data structures, and thus exhibit a lower degree of spatial locality. This makes them less amenable to spatio-temporal prefetchers.
In this paper, we introduce the concept of Semantic Locality, which uses inherent program semantics to characterize access relations. We show how, in principle, semantic locality can capture the relationship between data elements in a manner agnostic to the actual data layout, and we argue that semantic locality transcends spatio-temporal concerns.
We further introduce the context-based memory prefetcher, which approximates semantic locality using reinforcement learning. The prefetcher identifies access patterns by applying reinforcement learning methods over machine and code attributes, that provide hints on memory access semantics.
We test our prefetcher on a variety of benchmarks that employ both regular and irregular patterns. For the SPEC 2006 suite, it delivers speedups as high as 2.8X (20% on average) over a baseline with no prefetching, and outperforms leading spatio-temporal prefetchers. Finally, we show that the context-based prefetcher makes it possible for naive, pointer-based implementations of irregular algorithms to achieve performance comparable to that of spatially optimized code.
Heracles
Authors: Lo David , Cheng Liqun , Govindaraju Rama , Ranganathan Parthasarathy , Kozyrakis Christos 
Published: January 2016

User-facing, latency-sensitive services, such as websearch, underutilize their computing resources during daily periods of low traffic. Reusing those resources for other tasks is rarely done in production services since the contention for shared resources can cause latency spikes that violate the service-level objectives of latency-sensitive tasks. The resulting under-utilization hurts both the affordability and energy-efficiency of large-scale datacenters. With technology scaling slowing down, it becomes important to address this opportunity.
We present Heracles, a feedback-based controller that enables the safe colocation of best-effort tasks alongside a latency-critical service. Heracles dynamically manages multiple hardware and software isolation mechanisms, such as CPU, memory, and network isolation, to ensure that the latency-sensitive job meets latency targets while maximizing the resources given to best-effort tasks. We evaluate Heracles using production latency-critical and batch workloads from Google and demonstrate average server utilizations of 90% without latency violations across all the load and colocation scenarios that we evaluated.
ArMOR
Authors: Lustig Daniel , Trippel Caroline , Pellauer Michael , Martonosi Margaret 
Published: January 2016

Architectural heterogeneity is increasing: numerous products and studies have proven the benefits of combining cores and accelerators with varying ISAs into a single system. However, an underappreciated barrier to unlocking the full potential of heterogeneity is the need to specify and to reconcile differences in memory consistency models across layers of the hardware-software stack and among on-chip components.
This paper presents ArMOR, a framework for specifying, comparing, and translating between memory consistency models. ArMOR defines MOSTs, an architecture-independent and precise format for specifying the semantics of memory ordering requirements such as preserved program order or explicit fences. MOSTs allow any two consistency models to be directly and algorithmically compared, and they help avoid many of the pitfalls of traditional consistency model analysis. As a case study, we use ArMOR to automatically generate translation modules called shims that dynamically translate code compiled for one memory model to execute on hardware implementing a different model.
PIM-enabled instructions
Authors: Ahn Junwhan , Yoo Sungjoo , Mutlu Onur , Choi Kiyoung 
Published: January 2016

Processing-in-memory (PIM) is rapidly rising as a viable solution for the memory wall crisis, rebounding from its unsuccessful attempts in 1990s due to practicality concerns, which are alleviated with recent advances in 3D stacking technologies. However, it is still challenging to integrate the PIM architectures with existing systems in a seamless manner due to two common characteristics: unconventional programming models for in-memory computation units and lack of ability to utilize large on-chip caches.
In this paper, we propose a new PIM architecture that (1) does not change the existing sequential programming models and (2) automatically decides whether to execute PIM operations in memory or processors depending on the locality of data. The key idea is to implement simple in-memory computation using compute-capable memory commands and use specialized instructions, which we call PIM-enabled instructions, to invoke in-memory computation. This allows PIM operations to be interoperable with existing programming models, cache coherence protocols, and virtual memory mechanisms with no modification. In addition, we introduce a simple hardware structure that monitors the locality of data accessed by a PIM-enabled instruction at runtime to adaptively execute the instruction at the host processor (instead of in memory) when the instruction can benefit from large on-chip caches. Consequently, our architecture provides the illusion that PIM operations are executed as if they were host processor instructions.
We provide a case study of how ten emerging data-intensive workloads can benefit from our new PIM abstraction and its hardware implementation. Evaluations show that our architecture significantly improves system performance and, more importantly, combines the best parts of conventional and PIM architectures by adapting to data locality of applications.
A scalable processing-in-memory accelerator for parallel graph processing
Authors: Ahn Junwhan , Hong Sungpack , Yoo Sungjoo , Mutlu Onur , Choi Kiyoung 
Published: January 2016

The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations.
In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.
FASE
Authors: Callan Robert , Zajić Alenka , Prvulovic Milos 
Published: January 2016

While all computation generates electromagnetic (EM) side-channel signals, some of the strongest and farthest-propagating signals are created when an existing strong periodic signal (e.g. a clock signal) becomes stronger or weaker (amplitude-modulated) depending on processor or memory activity. However, modern systems create emanations at thousands of different frequencies, so it is a difficult, error-prone, and time-consuming task to find those few emanations that are AM-modulated by processor/memory activity.
This paper presents a methodology for rapidly finding such activity-modulated signals. This method creates recognizable spectral patterns generated by specially designed microbenchmarks and then processes the recorded spectra to identify signals that exhibit amplitude-modulation behavior. We apply this method to several computer systems and find several such modulated signals. To illustrate how our methodology can benefit side-channel security research and practice, we also identify the physical mechanisms behind those signals, and find that the strongest signals are created by voltage regulators, memory refreshes, and DRAM clocks. Our results indicate that each signal may carry unique information about system activity, potentially enhancing an attacker's capability to extract sensitive information. We also confirm that our methodology correctly separates emanated signals that are affected by specific processor or memory activities from those that are not.
A case for core-assisted bottleneck acceleration in GPUs
Authors: Vijaykumar Nandita , Pekhimenko Gennady , Jog Adwait , Bhowmick Abhishek , Ausavarungnirun Rachata , Das Chita , Kandemir Mahmut , Mowry Todd C. , Mutlu Onur 
Published: January 2016

Modern Graphics Processing Units (GPUs) are well provisioned to support the concurrent execution of thousands of threads. Unfortunately, different bottlenecks during execution and heterogeneous application requirements create imbalances in utilization of resources in the cores. For example, when a GPU is bottlenecked by the available off-chip memory bandwidth, its computational resources are often overwhelmingly idle, waiting for data from memory to arrive.
This paper introduces the Core-Assisted Bottleneck Acceleration (CABA) framework that employs idle on-chip resources to alleviate different bottlenecks in GPU execution. CABA provides flexible mechanisms to automatically generate "assist warps" that execute on GPU cores to perform specific tasks that can improve GPU performance and efficiency.
CABA enables the use of idle computational units and pipelines to alleviate the memory bandwidth bottleneck, e.g., by using assist warps to perform data compression to transfer less data from memory. Conversely, the same framework can be employed to handle cases where the GPU is bottlenecked by the available computational units, in which case the memory pipelines are idle and can be used by CABA to speed up computation, e.g., by performing memoization using assist warps.
We provide a comprehensive design and evaluation of CABA to perform effective and flexible data compression in the GPU memory hierarchy to alleviate the memory bandwidth bottleneck. Our extensive evaluations show that CABA, when used to implement data compression, provides an average performance improvement of 41.7% (as high as 2.6X) across a variety of memory-bandwidth-sensitive GPGPU applications.
Reducing world switches in virtualized environment with flexible cross-world calls
Authors: Li Wenhao , Xia Yubin , Chen Haibo , Zang Binyu , Guan Haibing 
Published: January 2016

Modern computers are built with increasingly complex software stack crossing multiple layers (i.e., worlds), where cross-world call has been a necessity for various important purposes like security, reliability, and reduced complexity. Unfortunately, there is currently limited cross-world call support (e.g., syscall, vmcall), and thus other calls need to be emulated by detouring multiple times to the privileged software layer (i.e., OS kernel and hypervisor). This causes not only significant performance degradation, but also unnecessary implementation complexity.
This paper argues that it is time to rethink the design of traditional cross-world call mechanisms by reviewing existing systems built upon hypervisors. Following the design philosophy of separating authentication from authorization, this paper advocates decoupling of the authorization on whether a world call is permitted (by software) from unforgeable identification of calling peers (by hardware). This results in a flexible cross-world call scheme (namely CrossOver) that allows secure, efficient and flexible cross-world calls across multiple layers not only within the same address space, but also across multiple address spaces. We demonstrate that CrossOver can be approximated by using existing hardware mechanism (namely VMFUNC) and a trivial modification of the VMFUNC mechanism can provide a full support of CrossOver. To show its usefulness, we have conducted case studies by using several recent systems such as Proxos, Hyper-Shell, Tahoma and ShadowContext. Performance measurements using full-system emulation and a real processor with VMFUNC shows that CrossOver significantly boosts the performance of the mentioned systems.
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
Authors: Alvarez Lluc , Vilanova Lluís , Moreto Miquel , Casas Marc , Gonzàlez Marc , Martorell Xavier , Navarro Nacho , Ayguadé Eduard , Valero Mateo 
Published: January 2016

The increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a hybrid memory system. Scratchpad memories are more power-efficient than caches and they do not generate coherence traffic, but they suffer from poor programmability. A good way to hide the programmability difficulties to the programmer is to give the compiler the responsibility of generating code to manage the scratchpad memories. Unfortunately, compilers do not succeed in generating this code in the presence of random memory accesses with unknown aliasing hazards.
This paper proposes a coherence protocol for the hybrid memory system that allows the compiler to always generate code to manage the scratchpad memories. In coordination with the compiler, memory accesses that may access stale copies of data are identified and diverted to the valid copy of the data. The proposal allows the architecture to be exposed to the programmer as a shared memory manycore, maintaining the programming simplicity of shared memory models and preserving backwards compatibility. In a 64-core manycore, the coherence protocol adds overheads of 4% in performance, 8% in network traffic and 9% in energy consumption to enable the usage of the hybrid memory system that, compared to a cache-based system, achieves a speedup of 1.14x and reduces on-chip network traffic and energy consumption by 29% and 17%, respectively.
Fusion
Authors: Kumar Snehasish , Shriraman Arrvindh , Vedula Naveen 
Published: January 2016

Chip designers have shown increasing interest in integrating specialized fixed-function coprocessors into multicore designs to improve energy efficiency. Recent work in academia [11, 37] and industry [16] has sought to enable more fine-grain offloading at the granularity of functions and loops. The sequential program now needs to migrate across the chip utilizing the appropriate accelerator for each program region. As the execution migrates, it has become increasingly challenging to retain the temporal and spatial locality of the original program as well as manage the data sharing.
We show that with the increasing energy cost of wires and caches relative to compute operations, it is imperative to optimize data movement to retain the energy benefits of accelerators. We develop FUSION, a lightweight coherent cache hierarchy for accelerators and study the tradeoffs compared to a scratchpad based architecture. We find that coherency, both between the accelerators and with the CPU, can help minimize data movement and save energy. FUSION leverages temporal coherence [32] to optimize data movement within the accelerator tile. The accelerator tile includes small per-accelerator L0 caches to minimize hit energy and a per-tile shared cache to improve localized-sharing between accelerators and minimize data exchanges with the host LLC. We find that overall FUSION improves performance by 4.3× compared to an oracle DMA that pushes data into the scratchpad. In workloads with inter-accelerator sharing we save up to 10x the dynamic energy of the cache hierarchy by minimizing the host-accelerator data ping-ponging.
Age‐Related Changes of Normal Cerebral and Cardiac Blood Flow in Children and Adults Aged 7 Months to 61 Years
Authors: Wu Can , Honarmand Amir R. , Schnell Susanne , Kuhn Ryan , Schoeneman Samantha E. , Ansari Sameer A. , Carr James , Markl Michael , Shaibani Ali 
Published: January 2016

Background
Cerebral and cardiac blood flow are important to the pathophysiology and development of cerebro‐ and cardiovascular diseases. The purpose of this study was to investigate the age dependence of normal cerebral and cardiac hemodynamics in children and adults over a broad range of ages.

Methods and Results

Overall, 52 children (aged 0.6–17.2 years) and 30 adults (aged 19.2–60.7 years) without cerebro‐ and cardiovascular diseases were included in this study. Intracranial 4‐dimensional flow and cardiac 2‐dimensional phase‐contrast magnetic resonance imaging were performed for all participants to measure flow parameters in the major intracranial vessels and aorta. Total cerebral blood flow (
TCBF
), cardiac and cerebral indexes, brain volume, and global cerebral perfusion (
TCBF
/brain volume) were evaluated. Flow analysis revealed that
TCBF
increased significantly from age 7 months to 6 years (
P
<0.001) and declined thereafter (
P
<0.001). Both cardiac and cerebral indices declined with age (
P
<0.001). The ratio of
TCBF
to ascending aortic flow declined rapidly until age 18 years (
P
<0.001) and remained relatively stable thereafter. Age‐related changes of cerebral vascular peak velocities exhibited a trend similar to
TCBF
. By comparison, aortic peak velocities maintained relatively high levels in children and declined with age in adults (
P
<0.001).
TCBF
significantly correlated with brain volume in adults (
P
=0.005) and in 2 pediatric subgroups, aged <7 years (
P
<0.001) and 7 to 18 years (
P
=0.039).

Conclusions
Cerebral and cardiac flow parameters are highly associated with age. The findings collectively highlight the importance of age‐matched control data for the characterization of intracranial and cardiac hemodynamics.
Kronos: A Declarative Metaprogramming Language for Digital Signal Processing
Authors: Norilo Vesa 
Published: January 2016

Abstract
Kronos is a signal-processing programming language based on the principles of semifunctional reactive systems. It is aimed at efficient signal processing at the elementary level, and built to scale towards higher-level tasks by utilizing the powerful programming paradigms of “metaprogramming” and reactive multirate systems. The Kronos language features expressive source code as well as a streamlined, efficient runtime. The programming model presented is adaptable for both sample-stream and event processing, offering a cleanly functional programming paradigm for a wide range of musical signal-processing problems, exemplified herein by a selection and discussion of code examples.