bluuebunny/crossref_metadata_2025_split huggingface dataset:
Draft Genome Sequence of the Vaginal Isolate Corynebacterium amycolatum ICIS 9
Authors: Gladysheva Irina V. , Khlopko Yuriy A. , Cherkasov Sergey V. 
Published: September 2017

ABSTRACT

Corynebacterium amycolatum
ICIS 9 was isolated from a vaginal smear of a healthy woman. Here, we report the draft genome sequence of
C. amycolatum
ICIS 9, which will be useful for further studies of specific genetic features of this strain and for understanding its probiotic properties.
Complete Genome Sequence of Salmonella enterica subsp.
enterica
Serovar Paratyphi B Sequence Type 28 Harboring
mcr-1
Authors: Borowiak Maria , Hammerl Jens A. , Fischer Jennie , Szabo Istvan , Malorny Burkhard 
Published: September 2017

ABSTRACT

In 2015, plasmid-mediated colistin resistance was reported to be caused by a mobilized phosphoethanolamine transferase gene (
mcr-1
) in
Enterobacteriaceae
. Here, we announce the complete genome sequence of the earliest
d
-tartrate-fermenting
Salmonella enterica
subsp.
enterica
serovar Paratyphi B isolate harboring
mcr-1
from the collection of the German National Reference Laboratory for Salmonella.
Draft Genome Sequence of the Type Strain Sphingopyxis bauzanensis DSM 22271
Authors: Kaminski Michal A. , Furmanczyk Ewa M. , Dziembowski Andrzej , Sobczak Adam , Lipinski Leszek 
Published: September 2017

ABSTRACT

We present here the draft genome sequence of
Sphingopyxis bauzanensis
DSM 22271. The assembly contains 4,258,005 bp in 28 scaffolds and has a GC content of 63.3%. A series of specific genes involved in the catabolism or transport of aromatic compounds was identified.
Mechanical cervicAl ripeninG for women with PrOlongedPregnancies (MAGPOP): protocol for a randomised controlled trial of a silicone double balloon catheter versus the Propess system for the slow release of dinoprostone for cervical ripening of prolonged pregnancies
Authors: Diguisto Caroline , Gouge Amélie Le , Giraudeau Bruno , Perrotin Franck 
Published: September 2017

IntroductionInduction of labour for prolonged pregnancies (PP) when the cervix is unfavourable is a challenging situation. Cervical ripening by pharmacological or mechanical techniques before oxytocin administration is used to increase the likelihood of vaginal delivery. Both techniques are equally effective in achieving vaginal delivery but excessive uterine activity, which induces fetal heart rate (FHR) anomalies, is more frequent after the pharmacological intervention. We hypothesised that mechanical cervical ripening could reduce the caesarean rate for non-reassuring FHR especially in PP where fetuses are already susceptible to this.Methods and analysisA multicentre, superiority, open-label, parallel-group, randomised controlled trial that aims to compare cervical ripening with a mechanical device (Cervical Ripening Balloon, Cook-Medical Europe, Ireland) inserted in standardised manner for 24 hours to pharmacological cervical ripening (Propess system for slow release system of 10 mg of dinoprostone, Ferring SAS, France) before oxytocin administration. Women (n=1220) will be randomised in a 1:1 ratio in 15 French units. Participants will be women with a singleton pregnancy, a vertex presentation, a term ≥41+0 and≤42+0 week’s gestation, and for whom induction of labour is planned. Women with a Bishop score ≥6, a prior caesarean delivery, premature rupture of membranes or with any contraindication for vaginal delivery will be excluded. The primary endpoint is the caesarean rate for non-reassuring FHR. Secondary outcomes are related to delivery and perinatal morbidity. As study investigators and patients cannot be masked to treatment assignment, to compensate for the absence of blinding, an independent endpoint adjudication committee, blinded to group allocation, will determine whether the caesarean for non-reassuring FHR was justified.Ethics and disseminationWritten informed consent will be obtained from all participants. The Tours Research ethics committee has approved this study (2016-R23, 29 November 2016). Study findings will be submitted for publication and presented at relevant conferences.Trial registration numberNCT02907060; pre-results.
Achieving high-quality care: a view from NICE
Authors: Leng Gillian , Partridge Gemma 
Published: September 2017

The National Institute for Health and Care Excellence (NICE) was established in 1999 to provide evidence-based guidance. The task of producing guidance by reviewing primary research data and using an advisory committee to develop evidence-based recommendations, is not straightforward. Guidance production is, however, less challenging than the task of putting evidence-based recommendations into practice.NICE is very sensitive to this challenge as, since 1999, over 1500 pieces of NICE guidance have been published. A number of pieces of guidance relate to heart disease, including pharmaceutical agents, new medical technologies and clinical guidelines. Examples include guidelines on acute heart failure and atrial fibrillation, and advice on technologies including edoxaban and implantable cardioverter defibrillators.The research evidence is clear that a change in practice rarely comes about as a result of simply disseminating guidance on best practice. Simple dissemination is particularly ineffective if the guidance has not been produced by a well-respected, credible organisation. It is also clear from the literature that implementation is more successful when more than one approach is taken, and when there is alignment between efforts at organisational, local and national levels.At an organisational level, there should be support from the Board for quality improvement, with ongoing measurement of progress. Resources should be provided for targeted change programmes, particularly where new guidance suggests improvements are required. A systematic process for putting change in place should include identifying barriers to change, agreeing interventions to overcome the barriers and drive forward improvement and planning for implementation and evaluation.
Non-aqueous electrochemical deposition of lead zirconate titanate films for flexible sensor applications
Authors: Joseph Sherin , Kumar A. V. Ramesh , John Reji 
Published: September 2017

Lead zirconate titanate (PZT) is one of the most important piezoelectric materials widely used for underwater sensors. However, PZTs are hard and non-compliant and hence there is an overwhelming attention devoted toward making it flexible by preparing films on flexible substrates by different routes. In this work, the electrochemical deposition of composition controlled PZT films over flexible stainless steel (SS) foil substrates using non-aqueous electrolyte dimethyl sulphoxide (DMSO) was carried out. Effects of various key parameters involved in electrochemical deposition process such as current density and time of deposition were studied. It was found that a current density of 25 mA/cm2 for 5 min gave a good film. The morphology and topography evaluation of the films was carried out by scanning electron microscopy (SEM) and atomic force microscopy (AFM), respectively, which showed a uniform morphology with a surface roughness of 2 nm. The PZT phase formation was studied using X-ray diffraction (XRD) and corroborated with Raman spectroscopic studies. The dielectric constant, dielectric loss, hysteresis and I–V characteristics of the film was evaluated.
AOT vs. JIT: impact of profile data on code quality
Authors: Wade April W. , Kulkarni Prasad A. , Jantz Michael R. 
Published: September 2017

Just-in-time (JIT) compilation during program execution and ahead-of-time (AOT) compilation during software installation are alternate techniques used by managed language virtual machines (VM) to generate optimized native code while simultaneously achieving binary code portability and high execution performance. Profile data collected by JIT compilers at run-time can enable profile-guided optimizations (PGO) to customize the generated native code to different program inputs. AOT compilation removes the speed and energy overhead of online profile collection and dynamic compilation, but may not be able to achieve the quality and performance of customized native code. The goal of this work is to investigate and quantify the implications of the AOT compilation model on the quality of the generated native code for current VMs.
First, we quantify the quality of native code generated by the two compilation models for a state-of-the-art (HotSpot) Java VM. Second, we determine how the amount of profile data collected affects the quality of generated code. Third, we develop a mechanism to determine the accuracy or similarity for different profile data for a given program run, and investigate how the accuracy of profile data affects its ability to effectively guide PGOs. Finally, we categorize the profile data types in our VM and explore the contribution of each such category to performance.
Auto-vectorization for image processing DSLs
Authors: Reiche Oliver , Kobylko Christof , Hannig Frank , Teich Jürgen 
Published: September 2017

The parallelization of programs and distributing their workloads to multiple threads can be a challenging task. In addition to multi-threading, harnessing vector units in CPUs proves highly desirable. However, employing vector units to speed up programs can be quite tedious. Either a program developer solely relies on the auto-vectorization capabilities of the compiler or he manually applies vector intrinsics, which is extremely error-prone, difficult to maintain, and not portable at all.
Based on whole-function vectorization, a method to replace control flow with data flow, we propose auto-vectorization techniques for image processing DSLs in the context of source-to-source compilation. The approach does not require the input to be available in SSA form. Moreover, we formulate constraints under which the vectorization analysis and code transformations may be greatly simplified in the context of image processing DSLs. As part of our methodology, we present control flow to data flow transformation as a source-to-source translation. Moreover, we propose a method to efficiently analyze algorithms with mixed bit-width data types to determine the optimal SIMD width, independently of the target instruction set. The techniques are integrated into an open source DSL framework. Subsequently, the vectorization capabilities are compared to a variety of existing state-of-the-art C/C++ compilers. A geometric mean speedup of up to 3.14 is observed for benchmarks taken from ISPC and image processing, compared to non-vectorized executions.
Static deadlock detection for asynchronous C# programs
Authors: Santhiar Anirudh , Kanade Aditya 
Published: September 2017

Asynchronous programming is a standard approach for designing responsive applications. Modern languages such as C# provide async/await primitives for the disciplined use of asynchrony. In spite of this, programs can deadlock because of incorrect use of blocking operations along with non-blocking (asynchronous) operations. While developers are aware of this problem, there is no automated technique to detect deadlocks in asynchronous programs.
We present a novel representation of control flow and scheduling of asynchronous programs, called continuation scheduling graph and formulate necessary conditions for a deadlock to occur in a program. We design static analyses to construct continuation scheduling graphs of asynchronous C# programs and to identify deadlocks in them.
We have implemented the static analyses in a tool called DeadWait. Using DeadWait, we found 43 previously unknown deadlocks in 11 asynchronous C# libraries. We reported the deadlocks to the library developers. They have confirmed and fixed 40 of them.
Synthesizing highly expressive SQL queries from input-output examples
Authors: Wang Chenglong , Cheung Alvin , Bodik Rastislav 
Published: September 2017

SQL is the de facto language for manipulating relational data. Though powerful, many users find it difficult to write SQL queries due to highly expressive constructs.
While using the programming-by-example paradigm to help users write SQL queries is an attractive proposition, as evidenced by online help forums such as Stack Overflow, developing techniques for synthesizing SQL queries from given input-output (I/O) examples has been difficult, due to the large space of SQL queries as a result of its rich set of operators.

In this paper, we present a new scalable and efficient algorithm for synthesizing SQL queries based on I/O examples. The key innovation of our algorithm is development of a language for abstract queries, i.e., queries with uninstantiated operators, that can be used to express a large space of SQL queries efficiently. Using abstract queries to represent the search space nicely decomposes the synthesis problem into two tasks: 1) searching for abstract queries that can potentially satisfy the given I/O examples, and 2) instantiating the found abstract queries and ranking the results.

We have implemented this algorithm in a new tool called Scythe and evaluated it using 193 benchmarks collected from Stack Overflow. Our evaluation shows that Scythe can efficiently solve 74% of the benchmarks, most in just a few seconds, and the queries range from simple ones involving a single selection to complex queries with 6 nested subqueires.
StreamQRE: modular specification and efficient evaluation of quantitative queries over streaming data
Authors: Mamouras Konstantinos , Raghothaman Mukund , Alur Rajeev , Ives Zachary G. , Khanna Sanjeev 
Published: September 2017

Real-time decision making in emerging IoT applications typically relies on computing quantitative summaries of large data streams in an efficient and incremental manner. To simplify the task of programming the desired logic, we propose StreamQRE, which provides natural and high-level constructs for processing streaming data. Our language has a novel integration of linguistic constructs from two distinct programming paradigms: streaming extensions of relational query languages and quantitative extensions of regular expressions. The former allows the programmer to employ relational constructs to partition the input data by keys and to integrate data streams from different sources, while the latter can be used to exploit the logical hierarchy in the input stream for modular specifications.
We first present the core language with a small set of combinators, formal semantics, and a decidable type system. We then show how to express a number of common patterns with illustrative examples. Our compilation algorithm translates the high-level query into a streaming algorithm with precise complexity bounds on per-item processing time and total memory footprint. We also show how to integrate approximation algorithms into our framework. We report on an implementation in Java, and evaluate it with respect to existing high-performance engines for processing streaming data. Our experimental evaluation shows that (1) StreamQRE allows more natural and succinct specification of queries compared to existing frameworks, (2) the throughput of our implementation is higher than comparable systems (for example, two-to-four times greater than RxJava), and (3) the approximation algorithms supported by our implementation can lead to substantial memory savings.
Achieving high coverage for floating-point code via unconstrained programming
Authors: Fu Zhoulai , Su Zhendong 
Published: September 2017

Achieving high code coverage is essential in testing, which gives us confidence in code quality. Testing floating-point code usually requires painstaking efforts in handling floating-point constraints, e.g., in symbolic execution. This paper turns the challenge of testing floating-point code into the opportunity of applying unconstrained programming --- the mathematical solution for calculating function minimum points over the entire search space. Our core insight is to derive a representing function from the floating-point program, any of whose minimum points is a test input guaranteed to exercise a new branch of the tested program. This guarantee allows us to achieve high coverage of the floating-point program by repeatedly minimizing the representing function.
We have realized this approach in a tool called CoverMe and conducted an extensive evaluation of it on Sun's C math library. Our evaluation results show that CoverMe achieves, on average, 90.8% branch coverage in 6.9 seconds, drastically outperforming our compared tools: (1) Random testing, (2) AFL, a highly optimized, robust fuzzer released by Google, and (3) Austin, a state-of-the-art coverage-based testing tool designed to support floating-point code.
Rigorous analysis of software countermeasures against cache attacks
Authors: Doychev Goran , Köpf Boris 
Published: September 2017

CPU caches introduce variations into the execution time of programs that can be exploited by adversaries to recover private information about users or cryptographic keys.
Establishing the security of countermeasures against this threat often requires intricate reasoning about the interactions of program code, memory layout, and hardware architecture and has so far only been done for restricted cases.
In this paper we devise novel techniques that provide support for bit-level and arithmetic reasoning about memory accesses in the presence of dynamic memory allocation. These techniques enable us to perform the first rigorous analysis of widely deployed software countermeasures against cache attacks on modular exponentiation, based on executable code.
Heterogeneous Managed Runtime Systems
Authors: Kotselidis Christos , Clarkson James , Rodchenko Andrey , Nisbet Andy , Mawer John , Luján Mikel 
Published: September 2017

Real-time 3D space understanding is becoming prevalent across a wide range of applications and hardware platforms. To meet the desired Quality of Service (QoS), computer vision applications tend to be heavily parallelized and exploit any available hardware accelerators. Current approaches to achieving real-time computer vision, evolve around programming languages typically associated with High Performance Computing along with binding extensions for OpenCL or CUDA execution.
Such implementations, although high performing, lack portability across the wide range of diverse hardware resources and accelerators. In this paper, we showcase how a complex computer vision application can be implemented within a managed runtime system. We discuss the complexities of achieving high-performing and portable execution across embedded and desktop configurations. Furthermore, we demonstrate that it is possible to achieve the QoS target of over 30 frames per second (FPS) by exploiting FPGA and GPGPU acceleration transparently through the managed runtime system.
CHARSTAR
Authors: Ravi Gokul Subramanian , Lipasti Mikko H. 
Published: September 2017

High-performance architectures are over-provisioned with resources to extract the maximum achievable performance out of applications. Two sources of avoidable power dissipation are the leakage power from underutilized resources, along with clock power from the clock hierarchy that feeds these resources. Most reconfiguration mechanisms either focus solely on power gating execution resources alone or in addition, simply turn off the immediate clock tree segment which supplied the clock to those resources. These proposals neither attempt to gate further up the clock hierarchy nor do they involve the clock hierarchy in influencing the reconfiguration decisions. The primary contribution of CHARSTAR is optimizing reconfiguration mechanisms to become clock hierarchy aware. Resource gating decisions are cognizant of the power consumed by each node in the clock hierarchy and additionally, entire branches of the clock tree are greedily shut down whenever possible.
The CHARSTAR design is further optimized for balanced spatio-temporal reconfiguration and also enables efficient joint control of resource and frequency scaling. The proposal is implemented by leveraging the inherent advantages of spatial architectures, utilizing a control mechanism driven by a lightweight offline trained neural predictor. CHARSTAR, when deployed on the CRIB tiled microarchitecture, improves processor energy efficiency by 20-25%, with efficiency improvements of roughly 2x in comparison to a naive power gating mechanism. Alternatively, it improves performance by 10-20% under varying power and energy constraints.
Language-level persistency
Authors: Kolli Aasheesh , Gogte Vaibhav , Saidi Ali , Diestelhorst Stephan , Chen Peter M. , Narayanasamy Satish , Wenisch Thomas F. 
Published: September 2017

The commercial release of byte-addressable persistent memories, such as Intel/Micron 3D XPoint memory, is imminent. Ongoing research has sought mechanisms to allow programmers to implement recoverable data structures in these new main memories. Ensuring recoverability requires programmer control of the order of persistent stores; recent work proposes persistency models as an extension to memory consistency to specify such ordering. Prior work has considered persistency models at the abstraction of the instruction set architecture. Instead, we argue for extending the language-level memory model to provide guarantees on the order of persistent writes.
We explore a taxonomy of guarantees a language-level persistency model might provide, considering both atomicity and ordering constraints on groups of persistent stores. Then, we propose and evaluate Acquire-Release Persistency (ARP), a language-level persistency model for C++11. We describe how to compile code written for ARP to a state-of-the-art ISA-level persistency model. We then consider enhancements to the ISA-level persistency model that can distinguish memory consistency constraints required for proper synchronization but unnecessary for correct recovery. With these optimizations, we show that ARP increases performance by up to 33.2% (19.8% avg.) over coding directly to the baseline ISA-level persistency model for a suite of persistent-write-intensive workloads.
The Mondrian Data Engine
Authors: Drumond Mario , Daglis Alexandros , Mirzadeh Nooshin , Ustiugov Dmitrii , Picorel Javier , Falsafi Babak , Grot Boris , Pnevmatikatos Dionisios 
Published: September 2017

The increasing demand for extracting value out of ever-growing data poses an ongoing challenge to system designers, a task only made trickier by the end of Dennard scaling. As the performance density of traditional CPU-centric architectures stagnates, advancing compute capabilities necessitates novel architectural approaches. Near-memory processing (NMP) architectures are reemerging as promising candidates to improve computing efficiency through tight coupling of logic and memory. NMP architectures are especially fitting for data analytics, as they provide immense bandwidth to memory-resident data and dramatically reduce data movement, the main source of energy consumption.
Modern data analytics operators are optimized for CPU execution and hence rely on large caches and employ random memory accesses. In the context of NMP, such random accesses result in wasteful DRAM row buffer activations that account for a significant fraction of the total memory access energy. In addition, utilizing NMP's ample bandwidth with fine-grained random accesses requires complex hardware that cannot be accommodated under NMP's tight area and power constraints. Our thesis is that efficient NMP calls for an algorithm-hardware co-design that favors algorithms with sequential accesses to enable simple hardware that accesses memory in streams. We introduce an instance of such a co-designed NMP architecture for data analytics, the Mondrian Data Engine. Compared to a CPU-centric and a baseline NMP system, the Mondrian Data Engine improves the performance of basic data analytics operators by up to 49x and 5x, and efficiency by up to 28x and 5x, respectively.