bluuebunny/crossref_metadata_2025_split huggingface dataset:
Physicochemical environment of Malala Lagoon in Southern Sri Lanka
Authors: Titus L. P. , Deepananda K. H. M. Ashoka , Cumaranatunga P. R. T. 
Published: September 2017

Malala Lagoon is the largest of the five enclosed shallow lagoons in Bundala National park, and is one of the most productive of the fifteen lagoons in the Hambantota district, Sri Lanka. It has been vulnerable to human induced pollution for nearly three decades. This paper ascertains the status of physicochemical environment of the lagoon and its temporal variation from 1995 to 1997. During the study period physicochemical and biological parameters measured in Malala lagoon were water temperature, pH, conductivity, Secchi depth, dissolved oxygen, salinity, total alkalinity, dissolved phosphate, and chlorophyll-a, and their mean values were; 27.69 ± 1.62°C, 7.93±0.46, 5.14±3.88 mS/cm, 00.39 ± 00.19 m, 7.83±0.89 mg/L, 2.18±1.61‰, 2.14 ±0.59 mmol/L, 12.25±4.67 mg/L and 8.86 ± 4.62 mg/L respectively. Maximum depth of the lagoon rarely exceeded 2 m during the study period. Due to the shallowness of the lagoon, there were no significant differences (p>0.05) in physicochemical parameters of surface, middle and bottom layers of the water column. Water level of the lagoon showed a significant (p<0.01) negative correlation with electrical conductivity (r = 0.727) as well as with the salinity (r = 0.729). Water influx to the lagoon showed a significant (p < 0.05) negative correlation with conductivity (r = 0.454) and salinity of the lagoon (r = 0.406). Findings of the study are compared with those carried out over a decade to explore and elucidate the long term changes in the lagoon environment. When compared with the published data from preceding and subsequent studies, it confirmed that the brackish water characteristics of the lagoon are gradually degrading due to pollution caused by natural phenomena and anthropogenic activities adversely affecting the ecological balance and the productivity of the lagoon. These findings could be of great importance when studying long term changes in the coastal waters, which are essential for sustainable coastal planning, with respect to socioeconomic development programmes as well as to identify the impacts of Hambantota port and maritime activities in the area and to understand the trends related to global climate change.
Addressing Next Generation Packaging and IoT with Glass Solutions
Authors: Shorey Aric , Lu Rachel , Smith Gene 
Published: September 2017

New requirements are emerging in electronics packaging. The ever-growing need for solutions for mobile communications and sensors that address the Internet of Things (IoT) provide interesting new challenges. RF applications strive to move to higher frequency bands, fan-out technology is being leveraged as an effective way to address interconnect demands, and there is a continuous search for more cost-effective solutions for difficult packaging challenges. Glass provides numerous opportunities to address these needs.
As an insulator, glass has low electrical loss, particularly at high frequencies. The relatively high stiffness and ability to adjust coefficient of thermal expansion helps optimize warp in glass core substrates, bonded stacks leveraging TGV and in carrier applications. Glass forming processes allow the potential to both form in panel format as well as at thicknesses as low as 100 um, giving opportunities to optimize or eliminate current manufacturing methods and address packaging challenges in a cost effective way.
We will provide the latest demonstrations of electrical, thermal and mechanical performance and reliability, describe areas where glass is being leveraged to achieve goals of next generation products and how properties of different glass types are leveraged by application.
Application of 3D PLUS WDoD technology for the manufacturing of electronic modules in implantable medical products
Authors: Couderc Pascal 
Published: September 2017

3D PLUS has patented an innovative 3D technology based on the stacking of Know Good Rebuilt Wafers with only Know Good Dies, named WDoDTM.
The first 2D steps are those used by the manufacturers of Rebuilt Wafers with well-known eWLBTM technology:- Pick-Flip and Place of KGD from the die wafer on an thermal-release tape on a silicon carrier ( 300 or 200 mm diameter)- Compression molding with epoxy resin with silica fillers- Know Good Rebuilt Wafer grinding in order to decrease total thickness to 250 Âμm or less- Fan-out built-up with Redistribution layer process- This last step can be replaced by interconnection of the die to external sides by “flat” gold wires, in specific conditions
The next steps concern the WDoDTM process with edge connection.- gluing of first Know Good Rebuilt Wafer- sequential staking and gluing of Know Good Rebuilt Wafers- dicing of rebuilt and stacked wafers- plating of dicing streets with electroless process
All these steps can be collective at the wafer level.
Final laser patterning on the plated edges of each module is the final step before electrical test.
3D PLUS has designed with LINANOVA and manufactured two different electronic modules in the frame of a feasibility study of implantable products.
These developments were funded by one European project named MANPOWER for a first application dedicated for leadless pacemaker and by a French PIA project (INTENSE) dedicated to neurostimulation for severe conditions, particularly refractory heart failure.
Description of these modules is detailed: these modules have several layers including PCB layers including components which cannot be processed with fan out technology.
Layers only with bare dies are processed with fan out WLP technology eWLB based or with “falt” gold wires. Top and bottom sides of these modules can be also populated by additional components and allow the interconnexion with other sub-modules. They can also be solderballed in order to be reflow as a BGA components.
Manufacturability trade-offs of bare-die FCBGA package using thin or core-less substrate
Authors: Verma Ankita , Tabrez Baqar , Duong Lam , Wuest Martin 
Published: September 2017

With the increasing demand for thinner packages and higher electrical & thermal performance requirement bare-die packaging is an inevitable trend that is growing. The assembly process for manufacturing of bare die in thin or core-less substrate FCBGA packages can be challenging especially considering the effects of substrate warpage during flip chip bonding and the excessive warpage of the flip chip package. We are evaluating the manufacturing risks during bare-die FCBGA package assembly to eliminate package warpage failures using experimental techniques and improve the functional performance of the flip chip package. Various substrate & under fill materials were tested for package warpage values for warpage-free control in the full range of temperature variation.
Die designs at 28nm and 40nm process nodes are extremely complex in order to achieve the highest electrical & thermal performance requirement. Die design constraints on advanced process nodes necessitate increased thermal dissipation requirements thereby requiring investigation of thermal solutions utilizing thermal interface materials (TIM) with heat-sink. The interaction of such thermal solutions with the bare die packages is evaluated using various trial and error for material selection, experimental and simulation techniques to improve the assembly process. This study also focuses on selection of thermal interface materials [TIMs] and heat sinks which have considerable impact on die integrity during package assembly and/or during process of removal for failure analysis.
Micromachined Interfaces for Metrology and Packaging Applications in the Submillimeter-Wave Band
Authors: Weikle Robert M. , Li H. , Arsenovic A. , Nadri S. , Xie L. , Bauwens M.F. , Alijabbari N. , Barker N. Scott , Lichtenberger A.W. 
Published: September 2017

The continued emergence of new terahertz devices has created a need for improved approaches to packaging, integration, and measurement tools for diagnostics and characterization in this portion of the spectrum. Rectangular waveguide has for many years been the primary transmission medium for terahertz and submillimeter-wave systems operating from 300 GHz to 1 THz, with the UG-387 flange the most common interface for mating waveguide components over this frequency range. Alignment of UG-387 flanges is accomplished with pins and alignment holes that are placed around the flange perimeter and, under the standard MIL SPECS tolerances, misalignments of up to 6 mils (150 microns) are possible as a result of practical milling tolerances. With the emergence of vector network analyzers operating beyond 1 THz, such misalignment of waveguide mating flanges is not negligible and is recognized as a fundamental issue limiting calibration and measurement precision at frequencies greater than 300 GHz. In response to this issue, a number of new waveguide flange concepts have been investigated to reduce flange misalignment and the P1785 IEEE Standard was recently issued to recommend designs for waveguide interfaces at frequencies above 110 GHz. Among the new flange concepts being proposed is a modified UG-387 that utilizes tighter machining tolerances and the ring-centered flange where alignment is accomplished using a precision coupling ring that fits over raised bosses that are centered on each waveguide.
This paper discusses the new interface concepts that are being developed to address waveguide flange misalignment as well as emerging micromachined interconnects, calibration standards and heterogeneous integration methods that are being applied to implement low-loss and high-performance circuit architectures for the terahertz frequency range. Among the technologies that will be described are (1) design and characterization methods for the new ring-centered waveguide standard, (2) micromachined waveguide components and calibration standards for the terahertz band, (3) silicon-based micromachined probe structures for direct-contact interfacing and metrology, and (4) epitaxial transfer of III-V semiconductor material onto high-resistivity silicon to realize a low-loss platform for integration of terahertz components. Details of the processing methods used to realize these components as well as measurement techniques for assessing their performance will be described.
Technology Review of System in Package
Authors: Wase Yashashree S. , Li Feng 
Published: September 2017

The Moore's law is approaching to an end at today's 14 nm technology and System in Package (SiP) is a promising solution for achieving denser electronics like mobile phones with small form factors. System in package is bringing together multiple ICs of various functionality stacked in 3D fashion. A fully functional system consisting of passive elements like resistor, capacitor, inductors, electromechanical elements, antenna, and ICs like sensors, can be integrated into a single package. To meet the requirements of the end product, system design characterization becomes very important for overall success in the development of system in package. Failure analysis and testing of the end product helps improve the product yield which is a point of concern for industries while designing system in package. But system in package has proven to be a viable solution for reduction in total cost and minimize time-to-market. Hence, system in package will continue to thrive and grow into mainstream technology despite of challenges faced during the development and production phase. In this paper, summary of system in package is presented with the perspective of reviewing the research carried out to overcome the challenges, cost issues, compatibility of different functional dice, quality and reliability issues.
This paper discusses the recent technological development of system in package modules and the limitations faced at various system levels while bringing multiple chips together to achieve fully functional package. This paper focuses on bridging the gap between the system integration by reviewing the research progress in the 3D IC and packaging using system in package. Some of the applications like portable electronics, automotive and wearable electronics, where the significance of system in package is more relevant are reviewed in this paper. The core challenges like thermal management, flip chip or wire bond interconnect that arise due to integration of different components and packages like package on package, package in package in the system in package are also discussed.
Development of Fan Out Package Platform for High Performance and RF Applications
Authors: Sharma Gaurav , Sharma Gaurav , Beece Adam , Shan Gao , Wieland Marcel 
Published: September 2017

ABSTRACT
Over the last few years quite significant and well publicized advancements have been made in the IC industry in the potential adoption of fan out wafer level package platforms for both analog and digital applications. HD-FO platforms are likely to find significant adoption in the mobility, consumer application space as these have the capability to achieve sub-micron package routing density, high processor/memory and interconnect band width, very thin package height and small foot print area. Development of HD-FO package development reported in this work includes:Multiple advanced silicon technology nodesBroad range of package sizesSingle die, multi-die packagesDifferent package configurations that include with substrate, without substrate, organic and inorganic package redistribution layer optionsSystem in Package (SiP) for RF applications
An electrical simulation based lateral and vertical interconnect insertion loss comparison is being reported for high density fan out packages and silicon interposer with through silicon via (TSV). Multiple metal layers, interconnect widths, organic and inorganic redistribution layers are modelled. High density fan out package provides orders of magnitude less vertical interconnect loss in comparison to TSV. Least lateral interconnect insertion loss is demonstrated by organic interconnect based HDFO package. For RF applications HDFO package based inductors of 1.1nH and 3.3nH demonstrate ~ 3 X improvements in Qmax when compared to similar CMOS based inductors.
In addition to providing differentiating technology value propositions through the advanced HD-FO packaging platform collaborative ecosystem, customer centric business model and flexible supply chains are also being built to meet the business requirements for the integrated circuit customers. Finally, silicon/package co-design environment and RF enablement will ensure that customers realize the benefits of seamless product design, fast yield feedback and reduced time to market.
Modeling Nonlinear MEMS Beams and the Chaotic Duffing Oscillator in SPICE
Authors: Beal Aubrey Nathan 
Published: September 2017

Nonlinear MEMS beams have been modeled using SPICE. This allows for the complex dynamics of MEMS resonators to be observed parallel to their supporting electronics via circuit simulation. Silicon generally provides suitably linear parameters for use in MEMS. However, nonlinearities may arise due to issues such as amplitude-frequency (A-F) effect, large displacement of the proof mass, pull-in voltage, fatigue, material or electrical parameters, process variation, simplified beam modeling and nonlinear spring constants. By modeling these effects in SPICE, the design of electronics that automatically test, calibrate, report or even mitigate these effects is aided.
Single-crystal silicon is a highly linear material up until its failure, especially type &lt;100&gt;. High quality factor MEMS devices may, however, be affected by even small nonlinear terms in the material's Young's modulus. Geometric deformations may also occur due to decreases in cross-sectional area of beams in reaction to stretching and loading. Specifically, by including nonlinear geometric effects of MEMS beams and nonlinear terms in the Young's modulus of &lt;100&gt; and &lt;110&gt; silicon - nonlinear and chaotic oscillations are shown to arise via SPICE simulation.
Using this SPICE modeling method, electronic systems were designed to monitor the nonlinear parameters of MEMS beams that cause A-F effect and chaotic Duffing oscillations. Extracting parameters such as those from the oscillation's Poincare section may yield advantage in built-in self-test (BIST) applications. The features in these nonlinear oscillations extend parameters to monitor and potentially calibrate MEMS devices for reliability, stability and processing variation.
The Effect of Processing Parameters on the Physical and Microwave Electrical Properties of Low Temperature Co-fired Ceramics
Authors: Walker Jim , Aguirre Jerry , Graddy Ed , Henry Jim 
Published: September 2017

Low Temperature Co-fired Ceramics (LTCC) represent a multilayer electronic packaging technology with the ability to incorporate many electrical components such as conductive, resistive, and dielectric materials, into a single monolithic package. Example devices would include capacitors, inductors, resistors, antennae, transformers, hybrid circuits, etc. In general, the LTCC package consists of a glass/ceramic dielectric and compatible conductive inks (Au, Ag, etc.). The dielectrics and conductors are patterned/laminated to form the desired 3D structure and then co-fired to complete densification. The resulting monolithic block is mechanically robust with a high density of (often buried) electrical components. Typically, LTCC systems have found implementation in circuitry utilizing the RF and microwave frequency ranges. In general, the material design and processing parameters, and knowledge of how these affect the final mechanical and electrical properties of the LTCC package are needed for successful circuit design.
The electronic performance of an LTCC dielectric/conductor system (Ferro L8) was investigated as a function of processing parameters (peak fire temperature, temperature ramp rate, furnace air flow, etc.). Comparisons were also made between multiple manufacturing sites as the mentioned processing parameters vary slightly from site to site even with nominally identical set points due to differences in furnace design, fab layout, etc. Material properties of fired parts such as effective permittivity and electrical losses were measured both on bare dielectric using resonant cavity methods and on the dielectric/conductor system as a whole using microstrip transmission line methods to frequencies as high as 50 GHz. Correlations were made between electrical performance and models based on material properties. The effects of varied processing parameters and processing sites were also studied and used to help establish process understanding and improvement with respect to high frequency electrical performance. As an example, optimization of electrical performance could be achieved by adjusting the nominal furnace temperature set point at a specific site where losses were slightly high even with identical processing parameters to those at another manufacturing site.
Ura Yilan: The art and science of rain making among the Tiv of central Nigeria
Authors: Andrew Philips Adega 
Published: September 2017

Rain is a natural phenomenon in which showers by means of natural causation down- pours water from the sky for the purpose of moisturing the earth, man, plants and animals for their sustenance. Without water, survival for man, plants and animals on earth will be a mirage. The fact that the Tiv are farmers who produce variety of crops implies that the Tivs necessarily need rain for their survival and for the crops and animals they rear. Thus, when the Tivs experience a dearth in rain, they employ the services of the yilan ura (rain maker) of the community for the purposes of ura yilan (rain making). The art and science of rain making among the Tiv is meant to avert catastrophe in the community for man, plants and animals. In making rain, the Tiv do not usurp or short change Aondo - the Supreme Being; but they do so conscious of the fact that Aondo has given them the arcane knowledge to tap into and control the natural resources of their environment for their benefit. Thus, the study is motivated by the factors responsible for ura yilan and the techniques employed by the Tiv to bring about rain and the derivable benefits there from. The study employed both the primary and secondary methods to collect data. Oral interviews were held with rain makers in selected parts of Tivland. In the secondary method, information was collected from books, journals, encyclopaedias, newspapers and magazines, etc. The study established that the Tiv, like other ethnic nationalities across the globe, make rain when circumstances demand. The Tiv therefore, make rain for different purposes including for productive, destructive/obstructive purposes as well as the detection of evil in the community. Ura yilan (rain making) among the Tiv was important in the sense that it procured bountiful harvest, regulated evil and cleansed Tiv society of defilement as well as bringing peace and happiness in the society. Expectedly, several taboos followed the making of rain among the Tiv; for instance, the genuine or yilan ura was prohibited from touching a corpse, never interacted with women observing their menstrual cycle and neither was he in the habit of collecting ingyato (consent fee) to cause the death of members of his community. In conclusion the study notes that although the art of rain making has drastically receded with the advent of western education and Christianity; where it becomes necessary for the Tiv to make rain, it should be for productive but not destructive ventures.
Fabricating Monstrosity: Secrets and Violence in the Lay of Graelent and Several Old French Fabliaux
Authors: Goyette Stefanie 
Published: September 2017

ABSTRACT
Hidden knowledge in the Old French lays and fabliaux predominantly concerns the bodies, behaviors, and desires of women, who are portrayed as jealously guarding their secrets while men seek to discover them. In the twelfth-century Lai de Graelent and various Old French fabliaux from the twelfth through fourteenth centuries, women are marked with the trait of monstrosity, indicating the bodily site of hidden knowledge. The body itself thus becomes the secret, representing the material difference that supposedly produces epistemological difference, and these two registers are conflated as knowledge is sought by violating the body. This article connects the lays and fabliaux, which are rarely studied together, and argues that women in these tales can exploit perceptions of monstrosity to short-circuit the violence inherent to conventions that pose them as the ultimate object of knowledge.