bluuebunny/crossref_metadata_2025_split huggingface dataset:
Building an EcoSystem for User-friendly Design of Advanced System in Package (SiP) Solutions
Authors: Reiter Herb 
Published: November 2017

Abstract
The Semiconductor Industry has followed “Moore's Law” for more than five decades and has made remarkable progress by continuously shrinking features sizes. However, meeting today's and future market requirements, such as shorter development times, lower up-front cost, lower unit cost, many more gates and pins in even smaller form-factors, integration of heterogeneous functions (logic, memory, analog, RF, MEMS, sensors, optical and others) and higher performance per Watt is becoming much more challenging. These requirements call for advanced IC packaging technologies to enable continued semiconductor revenue and profit growth.
In addition to IC packaging-specific expertise and development resources, very close cooperation with knowledgeable partners across all planning, design and manufacturing steps is needed, to create cost-effective and reliable electronic components, sub-systems, even entire systems in a package.
This paper analyzes why and where advanced IC packaging technologies are needed and suggests steps for developing Assembly Design Kits (ADKs) and Reference Design Flows, and other essential elements for building a strong “More than Moore”-focused semiconductor EcoSystem.
Printed Wiring for High-Power Electric Devices by Using Ag-sinter paste
Authors: Noh Seungjun , Choe Chanyang , Chen Chuantong , Nagao Shijo , Suganuma Katsuaki 
Published: November 2017

Abstract
This work introduces the possibility of using Ag sinter-paste as a novel high-temperature and high-current wire bonding solution. We investigated the electromigration (EM) behavior and lifetime of the sintered Ag wiring under high current density and high temperature required for the design of power electronic devices. The sinter Ag wiring fabricated on the two Cu substrates were tested under current densities of 2.7 × 104 A/cm2 at temperature of 250 °C. The microstructure evolution of sintered wiring was characterized after EM test. The resistance of sintered wiring did not change even after EM test for 300 hours, which confirms that the Ag-paste sinter wire bonding is rather stable than aluminum wire bonding under high temperature and high current density. No degradation was observed in microstructure of sintered wiring after EM test. Thus, it is expected that Ag paste sinter wire bonding is one of potential alternative interconnection technology for power electronic devices.
3D IPD on Thru Glass Via Substrate using panel Manufacturing Technology
Authors: Takano Takamasa , Kuramochi Satoru , Yun Hobie 
Published: November 2017

Abstract
As electronic products become smaller and thinner with increasing number of functions, the demand for high density and high integration becomes stronger. Glass has many properties that make it an ideal substrate for high integration substrate such as; ultra high resistivity, adjustable thermal expansion (CTE) high modulus, low dielectric constant, low dielectric loss and manufacturability with large panel sizes.
Multi-bands with carrier aggregation, Wi-Fi/GPS coexistence, and LTE-U make RF front end more and more complicated. 3D IPD (integrated passive devices) on Glass substrate technology could be advantage solution include reducing power consumption and small form factor.
This paper presents a demonstration of 3D RF front end filters using 3D solenoid inductors with through glass vias (TGV) and Cu-SiN-Cu MIM structure on Gen1 glass substrate (300mm × 400mm) panel format using color filter manufacturing line for flat panel display. For inductors, drastic performance (size and low resistance therefore high-quality factor) improvement have been demonstrated by technology evolutions from 3D solenoid using TGV with conformal Cu plating method, achieving low resistance of 3.1mohm per 70um diameter TGV on a 400um thick glass panel. This low-resistance TGV with 2.7mOhm/sq TGV connections on both sides of the glass substrate, record high inductor quality factor of 39 was obtained at 2.5GHz using five and half turn inductor of 7.9nH inductance, For capacitors, we have successfully integrated a Cu MIM (metal-insulator-metal) structure by using 15um thick Cu plates and dielectric, resulting in high capacitance density of 0.26nF/mm2 for RF application. By integrating TGV inductor-first and MIM capacitor-next, high-performance and high-density LC components are synthesized to perform as RF front end filters such as low-pass filters, diplexers, triplexers, and multiplexers.
The 3D inductors, Cu MIM, LC resonators and filters were successfully integrated using glass panel manufacturing infrastructure for the first time. Process characterization and process control monitors were evaluated at the panel level to address high-volume and high-yield manufacturability of RF filters with the unprecedented filter performance in terms of insertion loss and out of band rejections in smaller form factor than any other technologies have achieved so far. Furthermore, the TGV filters were mounted on electrical evaluation boards as well as JEDEC standard testing boards to check any device-level, chip-level, and board-level reliabilities associated with glass or TGV materials as well as their interaction with Cu, SiN, polymer inter layer dielectric materials, and solder joints, showing no performance degradations during thermal cycling, drop shock, bending, or high-power testing situations.
Ultra-fine Line Multi-Redistribution Layers with 10 μm Pitch Micro-Vias for Wafer Level and Panel Level Packaging realized by an innovative Excimer Laser Dual Damascene Process
Authors: Gernhardt Robert , Müller Friedrich , Woehrmann Markus , Hichri Habib , Hauck Karin , Toepper Michael , Arendt Markus , Lang Klaus-Dieter 
Published: November 2017

Abstract
Multi-chip integrated Fan-Out packages and high I/O CSPs demands for higher routing density on wafer level. Due to that, the classical mask aligner lithography and photosensitive thin-film polymers used for BEOL reach its limits and new technologies and materials are necessary to generate lines and space down to two μm. These multi-metal layers set also higher demands on the mechanical properties of the materials.
This paper presents a new excimer laser dual damascene process for ultra-fine routing for BEOL. Various materials like low cure temperature polyimide, BCB and 15-μm thick dry-film ABF material are structured by using an excimer laser stepper with a reticle mask to realize feature size below four μm with a high throughput.
Micro-vias with a diameter below five μm are realized with high aspect ratio, which overcome the photolithographic limitations of the common used photosensitive thin-film polymers. The laser structuring allows to use innovative dielectric materials for WLP with optimized mechanical and electrical parameters for example inorganic filled polymers like dry-film ABF materials, which do not have to be photosensitive. The ablations depth per laser pulse and the cross-section of the ablated structures in dependence of the ablation parameters was investigated. The depth of embedded lines was set by number of pulses aside of integrated micro-vias. The lines and micro-vias were metallized with copper by galvanic process and the following CMP step removes the copper outside the ablated structures. The CMP removes only the copper and the metal of the seed-layer, which has the functions of an adhesion and barrier layer, stays intact. The under-etching of the conventional wet etch seed layer removal is a major problem for the fine line structures realized by the Laser Dual Damascene process. Due to that, the removal of the seed layer (usually titan) was investigated and it could be shown, that this layer can be removed by the excimer laser system. The stepper like system allows a sub-micron alignment accuracy with no need of a capture pad of the embedded lines. Test structures have been designed and fabricated with lines and spaces below 10 μm to demonstrate the dense multi-layer routing capability where the excellent reliability can be proven by air to air thermal cycling (from −55°C up to 125°C), current leakage and electro migration test.
Separating Temporary Carrier from Large Thin Panel with Air Jetting
Authors: Tang Hao , Nguyen My , Yin Ming 
Published: November 2017

Abstract
As electronic components becomes thinner and more powerful than ever, substrates are being pushed to be so thin that they are flexible. Furthermore, both passive and active components are being embedded into substrates to further reduce packaging thickness. To fabricate a substrate that is too thin to be rigid and flat, a temporary carrier is applied onto the substrate to support the fabrication. However, but it must be removed upon completion, and the substrate and carrier must be bonded with very high adhesion strength during solder reflow cycles, due to a mismatch in the coefficient of thermal expansion (CTE). Such high adhesion strength typically creates more problems in the debonding process.
Unlike mechanical debonding, which generates significant peeling stress on a device's surface, air jet debonding introduces air streams between the carrier and the substrate, thus lifting the carrier from underneath and compressing the substrate surface downward. This results in the most uniform stress distribution, which is best suited for larger-area debonding processes.
In this paper, the air-jet debonding of a glass carrier from a 300 x 300 mm thick panel is demonstrated. The bonding adhesive Z-Coat 421G is developed to temporarily bond with panel substrate for lead-free assembly.
Enhanced In-Plane Heat Transport in Embedded Mini Heat Pipes PCB
Authors: de Sousa Jonathan Silvano , Fulmek Paul , Unger Michael , Haumer Peter , Nicolics Johann , Ras Mohamad Abo , May Daniel 
Published: November 2017

AbstractWe demonstrate the embedding of heat pipes as a solution for heat management in high density applications where heat spreading and heat guiding can be extremely important. Measurements results describe the advantages of the presented technology in comparison with thick copper inlays in the PCB. Further, this paper will also discuss the transient aspects of the heat transport in PCBs with embedded heat pipes.
Direct Measurement of Silicon Strain in a Fine Pitch Flip Chip BGA Package
Authors: Whitchurch Nathan , Rinne Glenn , Lin Wei , Balaraman Devarajan 
Published: November 2017

Abstract
A method for directly measuring the silicon strain in a flip chip ball grid array (FCBGA) package is disclosed. The method uses anisotropically etched holes in the die backside to reveal fiducial crosses on the front side of the die. A geometric model is proposed that allows extraction of the strain component of the measured displacement. A finite element model is described which correctly predicts the sign and magnitude of the strain.
Non-Destructive Testing for System-in-Package Integrity Analysis
Authors: Becker Karl-Friedrich , Minkus Mathias , Pauls Jeremias , Bader Volker , Voges Steve , Braun Tanja , Jungmann Gerd , Wieser Hubert , Schneider-Ramelow M. , Lang K.-D. 
Published: November 2017

Abstract
The constant drive of microelectronics towards ever higher degrees of integration leads to a wide variety of concepts to yield smallest packages with maximized functionality – while side by side packaging leads to thinnest packages a small footprint can typically only be achieved by using component stacking approaches. This leads to truly heterogeneous packages where a variety of materials are forming a complex potpourri of building blocks with different thermo-mechanical properties. While building such an integrated package needs high precision material dosing, component placement and fine pitch wire bonding and is already challenging – the non-destructive analysis of such packages for process and reliability characterization is even trickier. Additionally this NDT approach can not only be applied to determine the initial device quality but also during accelerated ageing tests as a tool for intermediate testing to determine the effects of chip-package interaction.
At Fraunhofer IZM a methodology has been applied to analyze a molded package using state of the art NDT equipment. A high resolution x-ray CT system by GE and a Gen6 CSAM system have been used as complimentary means to gain insight into a reference package that contains a four die stack assembled on PCB and is overmolded by a standard transfer molding process. To facilitate setting up the analysis procedure a variety of artefacts have been introduced to the package allowing the exact localization of layers and can be used to optimize the parameters for ultrasonic analysis for the variety of transducers used for package analysis. Additionally a simulation software is used to calculate the resulting ultrasound echoes for the different intra-package layers and the applicability of this tool for setting up an analysis procedure is provided.
As a result the paper describes an analysis methodology for highly integrated packages that uses CSAM analysis and x-ray CT for device analysis, while cross sectioning is used to confirm these results. Ultrasound simulation is applied to explain the findings of analysis process setup and will be evaluated on its potential to transfer the analysis method to SiP packages with varying geometry.
Silicon microfluidics: An enabling technology for life sciences application
Authors: Majeed Bivragh. , Zhang Lei , Fiorentino Giuseppe , Verbinnen Greet , Ashraf Huma , Walsby Edward , Roberts Kerry , Al Kuzee Jafar , Dawe Rhys , Thomas Dave , Sabuncuoglu Deniz. 
Published: November 2017

Abstract
In this paper we review the silicon microfabrication process that has been developed for various life science applications over the last several years. Silicon microfabrication is a key enabling technology in the developing personalized point of care or point of need systems. Silicon microfabrication allows for accurate control of fine features and it can combine active and passive components within a single chip. It is also very reliable, repeatable and it benefits from cost reduction due to mass production capabilities
Depending on the application, we have fabricated devices with either a single silicon etch or a two-step approach. Single step etches are typically 250–280μm deep. Two-step etching, the shallow features are 50μm while deeper are 250μm. We have developed an optimized deep silicon etch process that gives very straight profiles with minimum loss of critical dimension (CD) for different features. The minimum CD is 3μm while the largest features are 500μm wide The etching was done an SPTS Rapier DRIE system.
We describe the working principles of the various components in the system including PCR and micropillar filters. The filter has been used for high performance liquid chromatography (HPLC). It exhibits very low broadening of the components travelling through it and separation of a mixture of coumarin dyes is efficiently performed in a very short time. A micro PCR chamber with thermal isolation to the surrounding silicon is characterized and DNA amplification is achieved.
Plasma Dicing Process-Flows for Advanced Packaging Fabrications
Authors: Wei Frank , Tabuchi Tomotaka , Sando Hideyuki 
Published: November 2017

Abstract
Comprehensive investigations were conducted on identifying integration efforts needed to adapt plasma dicing technology in BEOL pre-production environments. First, the authors identified a few suitable process flows. Within the plasma dicing process flows, laser grooving before plasma etching was shown to be a key unit process to control the resulting die sidewall quality. Significant improvement on laser grooving quality has been demonstrated. Through these efforts, extremely narrow kerfs and near ideal dies strengths were achieved on Si dies. The Bosch-etching based plasma dicing process generates fluorinated polymer residues both on the Si die sidewalls as well as under the topography overhangs on wafer surfaces, such as under the solder balls or micro-bumps. The fluorinated polymers in certain areas cannot be cleaned by an in-chamber post-treatments. Multiple wet chemistry-based cleaning methods demonstrated excellent process capability, and are compatible with plasma singulated dies-on-tape handling. Lastly, many methods exist for backside metal and under Si die-attach-film (DAF) separations. The authors highlighted recent processing results suitable for post-plasma dicing die separations of such film materials.
Technology Transfer for MEMS and Advanced Packaging: Precision Surface Preparation Innovatively Applied to Emerging Technologies
Authors: Roberts Bob 
Published: November 2017

Abstract
The purpose of this presentation is to examine how certain mainline silicon substrate and semiconductor wafer manufacturing processes, can be and are being applied to applications in the manufacture of some of the most advanced digital devices including advanced packaging applications.
Periodically, the manufacturing steps and procedures of advanced semiconductor devices have changed dramatically enough that they are termed “paradigm shifts.” Two of the more dramatic manufacturing paradigm shifts in our professional lifetimes have been Precision Ultra-Thinning, and Chemical Mechanical Polishing to achieve planarization of substrates and specifically thin films that have been deposited on those substrates. In addition to the many activities in all or nearly all semiconductor IC manufacturing operations (Integrated Circuits), these two advanced technologies are now being applied to the manufacture of MEMS, MOEMS, LEDs, OLEDs, Nanotechnology and their associated Advanced Packaging methods and procedures.
In our technology driven world, it is safe to say that hardly anything in the world of microelectronics, semiconductors, and nanotechnology has been invented only for its awe-inspiring beauty alone, with no intrinsic value toward the improvements in form factor (miniaturization), and functional operation (speed, capacity, reliability, etc.). The same can be said about these two interesting technologies.
Thermally Stable Ag-Ag Joints Bonded by Ultrasound-assisted Stress Migration Bonding
Authors: Zhang Hao , Asatani Norio , Kimoto Yukiharu , Suetake Aiji , Nagao Shijo , Sugahara Tohru , Suganuma Katsuaki 
Published: November 2017

Abstract
We introduce a Ag-Ag direct bonding process with the aid of ultrasonic bonding, which uses silver “Nano-volcanic eruption of Ag” caused by stress migration at 250 °C. Various preheating temperatures before the ultrasonic pulse and various sputtering methods such as direct current (DC) and radio frequency (RF) have also been evaluated. A novel bonding process which combines ultrasonic bonding and stress migration bonding (SMB) method is established. The bonding achieved a die-shear strength of more than 50 MPa and a nearly-perfect voidless bonding interface. High temperature storage (HTS) test at 250 °C was used to evaluate the thermal-resist ability of bonded SMB joints. The results indicate that the bonded joints show no obvious changes in the interfacial morphology and the die-shear stress after HTS test for 1000 h is still higher than 30 MPa. The thermally-stable SMB joints can be applied to advanced devices such as thin-wafer multi-chip integrations and next-generation power devices.
Comparative Evaluation and Analysis of Gate Driver Impacts on a SiC MOSFET-Gate Driver Integrated Power Module
Authors: Zhang Liqi , Guo Suxuan , Liu Pengkun , Huang Alex Q. 
Published: November 2017

Abstract
SiC MOSFET-gate driver integrated power module is proposed to provide ultra-low stray inductance compared to traditional TO-247 or TO-220 packages. Kelvin connection eliminates the common source stray inductance and zero external gate resistor enables faster switching. This module can be operated at MHz switching frequency for high power applications with lower switching losses than discrete packages. Two different gate drivers and two different SiC MOSFETs are grouped and integrated into three integrated power modules. Comparative evaluation and analysis of gate driver impacts on switching speed of SiC MOSFET is shown in detail. The paper provides an insight of the gate driver impacts on the device switching performance in an integrated power module.
Inkjet and 3D Printing Technology for Fundamental Millimeter-Wave Wireless Packaging
Authors: Tehrani Bijan K. , Bahr Ryan A. , Tentzeris Manos M. 
Published: November 2017

Abstract
This paper outlines the design, processing, and implementation of inkjet and 3D printing technologies for the development of fully-printed, highly-integrated millimeter-wave (mm-wave) wireless packages. The materials, tools, and processes of each technology are outlined and justified for their respective purposes. Inkjet-printed 3D interconnects directly interfacing a packaging substrate with an IC die are presented using printed dielectric ramps and coplanar waveguide (CPW) transmission lines exhibiting low loss (0.6–0.8 dB/mm at 40 GHz). Stereolithography (SLA) 3D printing is presented for the encapsulation of IC dies, enabling the application-specific integration of on-package structures, including dielectric lenses and frequency selective surface (FSS)-based wireless filters. Finally, inkjet and 3D printing technology are combined to present sloped mm-wave interconnects through an encapsulation, or through-mold vias (TMVs), achieving a slope up to 65° and low loss (0.5–0.6 dB/mm at 60 GHz). The combination of these additive techniques is highlighted for the development of scalable, application-specific wireless packages.
Lighting System Packaging for Smart Underwater Reefs for Sensing, Communications, and Robotics
Authors: Fries David , Tate Connor , Hutcheson Tim , Josef Noam , Millie David 
Published: November 2017

Abstract
Strings and ropes are a proven, common fisheries and aquaculture construction elements outside the US. Using them as scaffolding also enables a diversity of ocean sensing, communications and architectures, including our goal of sentinel reefs. Packaging of electronics is key to enabling such structures and systems. Our research is towards a demonstrable science-engineering-informed framework for 3D habitat designs critical to stock fish development & coastal protection. These ‘nature-inspired’ reef infrastructures, can enable novel instrumented ‘reef observatories’ capable of collecting real-time ecosystem data. Embedding lighting and electronic elements into reef systems are the first systems in development. This new approach of bringing light to the underwater world for optical sensing, communication and even a new breed of underwater robotic vehicle is an interdisciplinary research activity which integrates principles of electronic packaging, and STEM with art/design.