Multi-Scale Modeling of Self Heating Effects on Power Consumption in Silicon CMOS Devices
Authors: Daugherty Robin , Vasileska Dragica 
Published: September 2017

This work pursues a multi-scale modeling approach to combine interconnect and device level simulation in order to study the effects of carrier self-heating and thermal transport on device performance. More specifically, this work will focus on power consumption and heat dissipation in silicon CMOS technology.
As device dimensions decrease to the nanometer scale, current density in the device active regions and the circuit interconnects increases [4]. This increase in current density leads to substantial increases in operating temperatures in critical regions of nano-scale electronic devices. We have already shown these effects in n-channel MOSFETs [2], and will continue to explore how this phenomenon affects p-channel MOSFETs and CMOS circuits. This paper presents the methodology used for the study, multi-scale results from the n-channel MOSFET simulations, and preliminary results from the device level p-channel MOSFET simulation.
The modeling approach combines an electro-thermal device simulation with a thermal transport solver at the circuit level. The electrical simulation solves Poisson's equations self-consistently coupled with an ensemble Monte Carlo to determine internal electric fields and model electron and hole transport in the device [3]. The thermal simulation solves the energy balance equations for acoustic and optical phonons and uses the phonon energy to determine the lattice temperature [5]. The electro-thermal solver couples these two processes by introducing temperature dependent scattering to the carrier transport solver.
Thermal transport can be modeled in a variety of ways: phonon Monte Carlo simulations are necessary for modeling extreme nano-scale and hot-carrier devices, energy balance modeling is used in this study to model thermal transport at the device level, and the Joule heating method commonly used in commercial device simulators is used in this study to model thermal transport at the interconnect level. The thermal modeling in the device and the interconnects is coupled using the device structure itself as an interface: the electro-thermal simulator provides Joule heating terms throughout the device to be used in the Joule heating simulator which in turn gives the temperature profile in the interconnects to be used as a boundary condition in the electro-thermal solver. These simulations are repeated in a self-consistent loop until convergence is achieved [2].
This modeling approach has been successfully applied to n-channel MOSFET devices and the results have been confirmed using a novel experimental approach. Two identical MOSEFTs in either common source or common drain configuration can be biased such that one device is in saturation and one device is in cut-off or sub-threshold region. The device in saturation heats up and the device in sub-threshold is used as a sensor; the temperature in the sensor can be determined using the subthreshold slope [2]. Confirming the simulation results with experimental results for the temperature in the subthreshold device substantiates the accuracy of the methodology for determining the temperature throughout the device [2].
This methodology, now verified by comparison with experimental results for n-channel MOSFETS, will be applied to the study of CMOS circuits.