bluuebunny/crossref_metadata_2025_split huggingface dataset:
Identification and Characterization of Conductive Dislocations in p-GaN/AlGaN/GaN Heterojunctions on GaN-on-Si Substrates
Authors: Stabentheiner M. , Tilly D. , Schinnerl T. , Taylor A.A. , Javernik P. , Novak M. , Ostermaier C. , Pogany D. 
Published: October 2024

Abstract
We present a study of dislocation conductivity under forward bias in p-GaN/AlGaN/GaN heterojunctions on a GaN-on-Si substrate, which are part of every p-GaN HEMT structure. Conductive atomic force microscopy (C-AFM) is combined with structural analysis by scanning transmission electron microscopy (STEM) and defect selective etching (DSE). The density of conductive TDs was found to be 5 × 106 cm-2, using semi-automatic measurements to gather larger statistics on a delayered HEMT sample. IV measurements show a shift in turn-on voltage at the leakage positions. To characterize the type of the conductive TDs, DSE with a KOH/NaOH melt was used. Three distinct etch pit sizes were observed after 5 s etch time, with large, medium and edge pits according to STEM characterization seemingly corresponding to screw, mixed and edge TDs, respectively. However, characterization by DSE etch pit size alone was found to be unreliable, as STEM TD typing of seven conductive TDs using two-beam diffraction conditions revealed mostly pure screw and mixed-type dislocations with medium-sized etch pits as origin of the observed leakage current. Our work highlights the limitations of DSE as a characterization method and recommends additional validation by STEM for each new material system, investigated layer, and etching setup. The implications of finding conductive TDs with screw-component under low forward bias conditions on device behavior and the limitations of the C-AFM method are discussed. Based on the results, it is not anticipated that the identified conductive TDs will have a substantial effect on a GaN HEMT device. Overall, this study provides important insights into the electrical properties of TDs and offers useful recommendations for future research in this area.
Increasing TEM Prep Throughput with an Extendable Manipulator Tip
Authors: Brogden Valerie , Garman Jeff , Langworthy Kurt , Wiemholt Steve 
Published: October 2024

Abstract
We introduce a novel piece of hardware that allows researchers to extend a nanomanipulator needle further into the vacuum chamber of a dual beam FIB SEM without venting the system. This hardware innovation will elevate throughput and diminish the instrument's downtime, which is pivotal for transmission electron microscope (TEM) sample preparation—a process integral to semiconductor manufacturers where the demand for TEM samples is high due to their necessity for process characterization and failure analysis of integrated circuits. Traditionally, the manipulator needle shortens with each sample preparation, ultimately reaching a mechanical limit that necessitates system venting to install a new needle. This hardware innovation allows users to feed out more needle length into the vacuum chamber by twisting a knob on the outside of the FIB SEM.
An Improved Backside Deprocessing Technique for Advanced IC Devices
Authors: Li Susan , Hulog Jose , Wang Zhaofeng , Sui Shixian , Zhang Ming , Andreasyan Armen , Goh Yeow Shen 
Published: October 2024

Abstract
A successful failure analysis not only depends on extensive electrical and physical fault isolation by using all the advanced FA tools to narrow down the possible failure site, but also relies on actual physical defect findings. For advanced IC devices with technologies approaching sub-10nm and more than 10 layers of metallization built in ultra-low k materials, finding convincing physical defects becomes increasingly challenging. Backside deprocessing to reveal the physical defects at the active circuit layers and interconnect layers have been mostly done with KOH or TMAH as bulk Si etching chemicals, and some successful results have been published in the literatures. However, some challenges are also reported using these chemicals to achieve satisfactory results. In this paper, an improved backside deprocessing technique will be discussed using a special bulk Si etching chemical, choline hydroxide, to successfully reveal the physical defects on advanced IC devices. The new technique showed advantages over the existing techniques with more predictable and reliable results for backside deprocessing work. Two case studies will also be shared to demonstrate how this improved technique has been utilized to successfully reveal the physical damage at transistor gate level on the advanced MCU devices.
Flexible Application of Multispecies Plasma-FIB in Failure Analysis Workflows
Authors: Mullen Melissa , Stokes Adam , Johnson Jared , Lam Andrew , Benson Samuel 
Published: October 2024

Abstract
Advanced semiconductor devices are disrupting traditional failure analysis workflows and creating demand for instrumentation that enables flexible capabilities to address these technology inflections. Such trends can be observed across multiple development areas, including faster processing, increased memory bandwidth, and power delivery. In every case, shrinking structures, complex packaging architecture, and advanced materials drive the need for efficient, precise targeting for regions of interest (ROI) over a wide range of length scales. An important example is the implementation of wide-bandgap (WBG) semiconductors, such as SiC and GaN, in advanced power devices. Various complexities are introduced, not only in device architecture, but also in defectivity analysis by conventional methods. As a result, high quality and high throughput failure analysis is achieved with specialized use of several plasma focused ion beam (PFIB) species best suited to these materials. Here we demonstrate such sample preparation for workflows involving electrical failure analysis (EFA) and localization, cross-sectional and volume analysis using scanning electron microscopy (SEM), as well as lamella preparation for transmission electron microscopy for physical failure analysis (PFA).
Etching Monitoring of Advanced Forksheet Devices Using AKONIS SIMS Tool
Authors: Robbes A-S. , Dulac O. , Soulard K. , Adier M. , Choi S. , Jacobson D. , Merkulov A. , Tilmann R. , van der Heide P.A.W. , Franquet A. 
Published: October 2024

Abstract
Imec has developed a fully-functional integrated forksheet field-effect transistors (FETs), which is the most promising architecture for advancing beyond the GAA (Gate-All-Around) nanosheet generation for scaling and performance improvements past the 2nm technology node. From a manufacturing perspective, forksheet devices are extremely complex to process and requires accurate and sensitive analytical instruments like the AKONIS SIMS tool.
Failure Investigation of Copper-to-Copper Bonding in Advanced 3D Packaging—From Sample Preparation to Structural Characterization
Authors: Nowakowski Pawel , Li Richard Wei-Chih , Ray Mary , Fischione Paul 
Published: October 2024

Abstract
This paper describes the detailed sample preparation of direct Cu-to-Cu bonding in 3D packaging between processor and memory. Different sample preparation techniques are described and compared. The sample preparation methods will then be confirmed by advanced structural characterization and strain measurement. The presence of voids and strain at the bonding interface is associated with the development of device failure.
Localization of Subtle Front-End FinFET Defects Using EBIC
Authors: Pronin Nick , Ly Khiem , Chrastecky Tony , Levenson Jacob , Yi Eric , Dickson Kris , Subramanian Sam , Serrels Keith 
Published: October 2024

Abstract
We demonstrate the effectiveness of combining top-down and cross-sectional electron beam induced current (EBIC) imaging with SEM nanoprobe analysis to identify subtle front-end defects in advanced FinFET technology. Our approach successfully localized a novel fin nanocrack defect that had previously eluded detection through conventional TEM imaging. This systematic resistive pMOS failure, observable only in memory arrays at 150°C, exemplifies the power of EBIC as an alternative to scanning capacitance microscopy for detecting dopant anomalies and subtle defects. The sample preparation and EBIC methodologies presented here are broadly applicable across CMOS technologies, offering a versatile approach to defect analysis.
Application of Thermal Emission Phase Lock-In Image Statistics to Locate Defects in Z-depth for Advance 2.5D Packaging
Authors: Nuez Daniel , Tan Phoumra , Lai Brian 
Published: October 2024

Abstract
This paper presents a novel method for determining the Z-depth location of short circuit defects in flip chip packages using lock-in thermography (LIT). The approach analyzes phase shift values from localized hot spots using the LIT system's "Image Statistics" feature, specifically focusing on phase "mean" values at specific lock-in frequencies. Through extensive testing on 2.5D stacked silicon interconnect technology (SSIT) packages exhibiting short failures, we established a strong correlation between phase mean values and the vertical location of defects. This technique's reliability was validated through both physical analysis and non-destructive verification methods, demonstrating its effectiveness as a precise diagnostic tool for complex semiconductor packages.
The Impact of TEM Analysis Temperature on Photoresist Profiles Using Cryo-FIB and Cryo-TEM
Authors: Hye Hyun Ji , Dai Yanchao , Chang Choi In , Kang Christopher H. 
Published: October 2024

Abstract
Photoresist (PR) profiles tend to have deformation and shrinkage with typical transmission electron microscopy (TEM) analysis method using a focused ion beam scanning electron microscope (FIB-SEM) and TEM. The elevated temperatures during sample preparation and TEM analysis are believed to contribute to these issues. This study evaluates the effectiveness of cryogenic workflow in mitigating PR profile shrinkage by employing cryo-focused ion beam (Cryo-FIB) and cryo-transmission electron microscopy (Cryo-TEM). Comparative experiments were conducted at room temperature and cryogenic conditions, demonstrating that full cryogenic workflow reduces the shrinkage of PR, bottom anti-reflective coating (BARC), and line critical dimension (CD). Our findings indicate that both the sample preparation and analysis temperatures influence PR profiles. This study highlights how the full cryogenic workflow significantly minimizes shrinkage, providing more accurate PR profile measurements.
Frequency-Tunable Current Imaging using a Quantum-Mixer Microscope Based on Nitrogen-Vacancy Centers in Diamond
Authors: Karlson Samuel , Kehayias Pauli , Schloss Jennifer M. , Maccabe Andrew C. , Phillips David F. , Wang Guoqing , Cappellaro Paola , Braje Danielle A. 
Published: October 2024

Abstract
Wide-field magnetic imagers using nitrogen-vacancy (NV) centers in diamond yield high-resolution images for various applications, including magnetic field imaging (MFI) of electronics. Despite the ongoing successes of this emerging technique for passively interrogating electronics components (including failure analysis troubleshooting), most of the focus has been on sensing DC and low-frequency currents, due to the technical challenges associated with measuring higher-frequency magnetic fields. Here, we overcome these existing challenges and adapt a recently developed technique for sensing MHz-frequency AC fields, a “quantum frequency mixing” approach. We demonstrate the instrument’s capabilities by imaging the current through a fabricated spiral test structure at various frequencies with a ~1 mm2 field of view. Finally, we discuss anticipated future applications in electronics interrogation and failure analysis for this imaging technique.
Wafer Level Monitoring of Optical Insertion Loss during Silicon Photonics Manufacturing
Authors: Beaudoin Felix , Hirokawa Takako , Bian Yusheng , Houghton Thomas , Lin Yarong , Shea Kenneth , Popielarski Brian , Robson Norman , Sinnott Aaron , Sapra Neil V. , Bappi Golam , Fini John 
Published: October 2024

Abstract
Silicon photonics has emerged as a key solution for on-chip communication to improve computational systems especially for AI workloads. Testing of such photonic integrated circuits (PICs) is key to deliver known good dies to be co-packaged with the compute IC. The recent availability of commercial photonic testers has allowed for monitoring most optical components at wafer level using vertical grating couplers. However, the measurement of optical insertion loss prior to fiber attach of edge-coupled spot size converters remains one of the significant challenges. In this article we demonstrate the use of a novel system for wafer–level optical edge-coupling insertion loss measurement. This method proved to be effective in capturing manufacturing process issues impacting insertion loss with a relatively fast turnaround time compared to fiber attach.
Failure Analysis of Liquid Cooling Setup for Hyperscale Datacenter Infrastructure
Authors: Pichumani Pradip Sairam , Yan Ting , Dillon Eoghan 
Published: October 2024

Abstract
Air-assisted liquid cooling (AALC) has emerged as a preferred cooling solution for data centers housing traditional air-cooled server racks, owing to its straightforward integration with existing infrastructure. However, the rising power demands of AI hardware (30-100kW per rack) and its variable computational loads generate unprecedented heat levels that challenge system reliability and uptime. Through long-term reliability testing of AALC systems, we identify and analyze unique failure mechanisms associated with liquid cooling implementations. This paper presents our findings on system vulnerabilities, details the failure analysis methodology, establishes root causes, and outlines the corrective measures implemented to enhance AALC system reliability in high-performance computing environments.
A Correlative Microscopic Workflow Powered by Artificial Intelligence to Accelerate Failure Analysis of Next-Generation Semiconductor Packages
Authors: Chang Yu-Jen , Liu Cheng-Hsin , Lin Yi-Sheng , Wang Chen-Chao , Liu Nicky , Chiu Bessy , Gu Allen 
Published: October 2024

Abstract
Over the past decade, the semiconductor industry has increasingly focused on packaging innovations to improve device performance, power efficiency, and reduce manufacturing cost. The recent heterogeneous integration offers an attractive solution in advanced IC packaging because it enables the integration of diverse functional components, such as logic, memory, power modulator, sensor on a single package platform. However, the adoption of the emerging structures, materials and components in advanced packages has challenged the existing fault isolation and analysis techniques. One of the major challenges is the limited accessibility to defects because fault regions are often located deep within devices. Without high-accuracy positional information of a defect, physical cross-sectioning and FIB polishing may alter or destroy the evidence of root causes. A non-destructive microscopic approach is preferred to map defective sites and surrounding structures. However, this method is limited by spatial resolution, especially for analyzing novel submicron interconnects such as fine pitch microbumps, redistribution layers (RDLs), and hybrid bonds. In this paper, we report an AI powered correlative microscopic workflow, where non-destructive X-ray imaging, FIB polishing and high-resolution SEM analyzing techniques are combined to solve the accessibility problem. Because 3D X-ray imaging may take a larger fraction of the time span over the entire workflow, a deep-learning based reconstruction method was applied to accelerate data acquisition. Several next-generation packages, fan-out wafer-level package (FOWLP) and hybrid bonds with sub 10 µm pitch, were used as the test vehicles to demonstrate the workflow performance and efficiency.
Imaging Nanoscale Electronic Changes in a Biased GaN HEMT
Authors: Hubbard William A , Regan B.C. 
Published: October 2024

Abstract
The transmission electron microscope (TEM) is the standard high-resolution technique for imaging microelectronics. But TEM primarily generates contrast related to the physical structure and composition of samples, giving little insight into their electronic properties. Samples must also be electron transparent, typically requiring cross-sectioning of components to nanometers-thin foils prior to imaging, which can compromise their electronic integrity. These cross section samples are also notoriously difficult to electrically connect to without surface leakage dominating transport. As a result, successful in situ electronic testing or bias-manipulation of electronic devices in the TEM is notably rare. Here we image nanoscale, bias-induced electronic changes in an electrically contacted cross section extracted from a GaN high electronmobility transistor (HEMT). The sample is prepared using a Xe+-based plasma focused ion beam (PFIB) to eliminate conducting implantation of the standard FIB ion, Ga+. Scanning TEM electron beam-induced current (STEM EBIC) imaging visualizes bias-induced changes to the device’s electronic structure during normal biasing, stressing, and after failure, all performed in situ.
A Comprehensive Approach for Post Silicon Unique Hold Time Violation Debug on Ethernet Interface Issue
Authors: Shen Lee Shen , Khei Kuan Lai , Jun Wu Jia , Lay Goh Lay , Shah Tirthak , Gupta Gaurav , Gayatri Vinay Padmanabha , Li Yuet 
Published: October 2024

Abstract
Unique frequency dependent hold time violation debug seen on Ethernet IP that caused at least 50% yield loss is showcased in this paper. This debug exposed the process variation issue seen, limitation in current FPGA timing sign-off methodology and design limitation that led to this rare hold time behavior. Customized ATPG patterns has become de facto for effective HVM screening including exploration of new path hold time fault pattern generation. The debug was backed by tester level and system validation debug with help from optical probing and FIB to confirm the root cause and silicon fixes required.
Concept-Proof of Lock-in OBIRCH Application for Three-Dimensional Analysis of Four-Dimensional NAND Flash Memory
Authors: Chinone Norimichi , Uchikado Akihito 
Published: October 2024

Abstract
The importance of three-dimensional (3D) localization capability is growing as advanced semiconductor devices go to 3D structures. An algorithm for processing lock-in OBIRCH data was developed especially for 3D/4D memory devices. The concept was tested with a simple test sample, which was confirmed to be capable of generating depth separated images.
Machine Learning for Predicting DataCube Atomic Force Microscope (AFM)—MultiDAT-AFM
Authors: Coq Germanicus Rosine , Othman El-Hassani 
Published: October 2024

Abstract
In nanoscience, techniques based on Atomic Force Microscope (AFM) stand as a cornerstone for exploring local electrical, electrochemical and magnetic properties of microelectronic devices at the nanoscale. As AFM's capabilities evolve, so do the challenges of data analysis. With the aim of developing a prediction model for AFM mappings, based on Machine Learning, this work presents a step towards the analysis and benefit of Big Data recorded in the hyperspectral modes: AFM DataCube. The MultiDAT-AFM solution is an advanced 2000-line Python-based tool designed to tackle the complexities of multi-dimensional measurements and analysis. MultiDAT-AFM offers visualization options, from acquired curves to scanned mappings, animated mappings as movies, and a real 3D-cube representation for the hyperspectral DataCube modes. In addition, MultiDAT-AFM incorporates a Machine Learning algorithm to predict mappings of local properties. After evaluating two supervised Machine Learning algorithms (out of the eight tested) for regression, the Random Forest Regressor model emerged as the best performer. With the refinement step, a root mean square error (RMSE) of 0.18, an R2 value of 0.90 and an execution time of a few minutes were determined. Developed for all AFM DataCube modes, the strategy and demonstration of MultiDAT-AFM are outlined in this article for a silicon integrated microelectronic device dedicated to RF applications and analyzed by DataCube Scanning Spreading Resistance (DCUBE-SSRM).
A Quantitative and Automated Quality Metric for Delayering Integrated Circuits
Authors: Padro Noah , Balint Tim , Harner Nick , Scholl Jon , Patel Yash , Sale Matt , Kimura Adam 
Published: October 2024

Abstract
Integrated circuit (IC) delayering is highly subjective, as operators must make process decisions based on minute details observed in optical images of the ICs. Process decisions have a strong influence on the quality of the final sample, with the result being highly dependent on an operator’s technique, skill, and experience. However, end point detection, process development, and in-process feedback all benefit from a quantitative method to evaluate results. To this end, a quality metric for IC delayering based solely on optical images has been developed. The optical images are processed into CIE-Lab color space, candidate zones are established, and color homogeneity both within and among these zones is calculated, which contribute to a final die quality score. The work done in this study takes a significant step forward in quantifying IC delayering results, which is critical for improving repeatability, reproducibility, and developing automation frameworks in these workflows.
Scanning Capacitance Microscopy Application for Top-down Sample Failure Analysis on SOI and Bulk Silicon Wafers
Authors: Tun Zin Nwe , Sweeney Ryan , Davidson Kevin , Chen Esther 
Published: October 2024

Abstract
Scanning Capacitance Microscopy (SCM) is an essential technique in semiconductor failure analysis. It is widely known in studies of dopant profiles and carrier concentration. Not only that, SCM can be utilized as an electrical fault isolation tool to localize a failing transistor. Compared to Conductive Atomic Force Microscopy CAFM, the main advantage of SCM is that it can be used on both Silicon on Insulator (SOI) and Bulk Silicon wafers. In addition, SCM can scan over a relatively large area in a shorter time than conventional nanoprobing methods. This paper presents case studies illustrating the effectiveness of SCM for die level top-down failure analysis on 45nm node SOI and 14nm FinFET bulk Si technologies.
Lock-in Amplifier Applications for Fault Isolation
Authors: Lee Sukho , Dickson Kristofor 
Published: October 2024

Abstract
This paper describes how lock-in amplifiers and boxcar averaging can overcome limitations in conventional fault isolation techniques for microelectronic testing. Our approach achieves superior results compared to traditional spectrum analyzer methods through three key applications. First, we measure the signal-to-noise ratio of individual pulses during laser voltage tracing (LVT) across varying pulse widths. Second, we leverage enhanced LVT imaging to improve computer-aided design to stage alignment and laser voltage probe placement—a crucial advancement for analyzing compressed scan and streaming scan network test failures. Finally, we present a case where our Lock-In amplifier system successfully generates pass/fail signals for dynamic laser stimulation in scenarios where conventional test hardware proved inadequate.