bluuebunny/crossref_metadata_2025_split huggingface dataset:
Embedded RDL formation in Non-Photo Polymers using Excimer Laser Ablation
Authors: Hichri Habib , Lee Seongkuk , Arendt Markus , Malik Sanjay , Dimov Ognian , Sakamuri Raj , Sundaran Venky 
Published: November 2016

Abstract
The continuous trend towards miniaturization, increasing performance and mobility of electronic devices drives interconnect density and integration, not only at the chip level, but also at interposer and package level. Silicon interposers coming from wafer foundries using back end of line (BEOL) redistribution layer (RDL) processes have been introduced successfully. However, there is a continuing need for low cost interposers based on large organic or glass panels. While traditional organic flip-chip substrates using semi-additive processes (SAP) have not been able to scale to ultra-fine RDL pitches, photo-sensitive spin-on dielectrics and RDL processes used for wafer level packaging do not sufficiently address the cost reduction need, This paper presents the latest results from cost effective and innovative package RDL processes using excimer laser ablation, to meet the market's most stringent requirements.
To enable panel and wafer based interposers to reduce RDL cost and scale interconnect pitch to 40um and below, excimer laser ablation is introduced as a direct patterning process that uses proven industrialized excimer laser sources to emit high-energy pulses at short wavelengths to remove polymer materials with high precision and high throughput. The combination of a high-power excimer laser source, large-field laser mask and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without the need for any wet-processing. In addition, with excimer laser patterning technology the industry gains a much wider choice of dielectric materials (photo and non-photo) to help achieve further reductions in manufacturing costs as well as enhancements in interposer and package performance.
In this paper, we propose new process that uses excimer laser ablation to integrate via and RDL traces in one patterning process step, followed by seed layer deposition, plating and planarization steps. A new integration process flow is proposed, and its technical robustness and commercial advantages have been demonstrated. The capability of this excimer laser process to extend the current material portfolio to non-photo materials will be discussed, and its commercial benefits as compared to the current process of record (POR) will be highlighted.
Smart in-line defectivity/metrology process control solution for advanced 3D integration
Authors: Sidhoum Amina , Devanciard Nicolas , Bana Franck , Garnier Arnaud , Bresson Nicolas , Bos Sandra , Rey Stéphane , Beitia Carlos , Alliata Dario , Hart Darcy , Thornell John , Miller Justin , Vera Gilles , Balak Scott 
Published: November 2016

Abstract
When combined with in-line local metrology, Automatic Visual Inspection/Classification is a powerful tool to characterize 3D interconnect processes, either at the R&D level or in volume manufacturing environments. A new methodology that uses visual inspection results to drive local smart metrology was used for the first time to control the fabrication process of micro-pillar/micro-bump vertical contacts. Quantification of the inspection time when the smart logic concept was used revealed a throughput increase of 23% on average, while consistency of the automatic morphological accuracy was preserved as confirmed by in-line mechanical profilometry. The morphology characterization is discussed with respect to the electrical performances at die level.
Characterizing and solving imaging challenges in thick resists for wafer and panel based lithography applications
Authors: Webb James E. , McCleary Roger 
Published: November 2016

Abstract
Increasing volume using larger substrates with decreasing process margins continues to create new challenges for advanced packaging applications. Key step and repeat camera technology continues evolving for the mass production of microstructures used for 2.5D and 3D technologies. Printing dense arrays of smaller features with high aspect ratios requires higher sidewall angles in thick photoresists and polyimides. To help solve these imaging challenges we have leveraged resist modeling software and guided the adjustment of optical parameters needed for better performance. Higher contrast films have also been evaluated to help achieve the improvements in performance needed. Resist models that can include the effects of flare have been critical to understand the requirement for printing in thick negative resists and has aided in printing features on varying topography and film thicknesses. Special chucks help improve the flatness of warped wafers and real-time auto-focusing provides good image fidelity. Printing microstructures over larger formats with higher throughput has been accomplished using large magnification adjustment for improving overlay and validated by characterizing image placement errors over large substrates. Examples of resist models that are created using resist parameters and optimized using SEM images of printed features are compared. Extrapolations of the resist models have shown that guide improvements can be achieved by varying optical parameters. SEM images confirm that the modeled result of the optimal solution was achieved. Reduction in large substrate overlay error was achieved after the stage corrections were applied. Examples show that topographical errors of warped wafers can be reduced and how real-time auto-focusing for each exposure minimizes focus errors.
Ultra thin, low ESL and high frequency performance of high density silicon capacitors
Authors: Bunel Catherine , Murray Franck 
Published: November 2016

Abstract
The very high capacitance platform (now up to 900 nF/mm2) of the 3D Silicon capacitor technology presents many advantages for signal integrity, performance improvement, and miniaturization. In this paper, we will illustrate these advantages for communication infrastructure and high speed processors. The intrinsic IPDiA Silicon capacitors construction and the simplified equivalent electrical models will be compared with the multilayer ceramic capacitor (MLCC) model. We will also demonstrate how the Silicon capacitors are better candidates for performance, miniaturization and integration thanks to their low profile. The thickness has been a limiting factor for ceramic capacitors and we believe that Silicon capacitors will help to address this profile challenge. On top of the competitive overview of performances specific to the Ultra Wide Broadband Capacitors - like signal integrity, frequency response, linearity, and dielectric absorption - the additional Silicon capacitor technology benefits will be detailed. Design recommendations will be given to those who want to optimize performance. Perspectives and roadmap for the future will be disclosed.
Washable Coatings for Packaging Processes
Authors: Brewer Alex , Laymon Alex , Moore John 
Published: November 2016

Abstract
Many packaging processes require the protection of components while another application is conducted. This may include a planarizing coat over large topography while a deposition, bonding, or curing step is completed. Washable coatings are materials that protect the substrate during thermal or mechanical activities and are simply washed away using readily available and green products, such as water or detergent. Washable products are not new, an example includes laser washable coatings that remove debris from the heat activation zone (HAZ) during scribe and break processes. In such cases, thermal resistance is desired as high as possible. The chemistry of washable products includes polyvinyl alcohol (PVA) and polyvinylpyrrolidone (PVP) [1]. While these are excellent choices for consumer packaging (e.g. laundry packets, vitamins), they are best used in electronics for room temperature processing due to their cross-linking upon exposure to heat and metals. Alternatively, thermal resistant and washable products (e.g. DaeCoat™ 515) are available that provide protection to ≥300°C without the aid of mechanical tooling [2]. Planarizing coatings over metals can be thick (&gt;300μm) as in cases where solder bump encapsulation is needed during dielectric coating and cure or when another die is thermal compression bonded. This approach has been demonstrated with washable temporary bonding adhesives in protecting C4 bumps while bonding micro-bumped die onto FPGA interposers [3]. Washable adhesives have been created for thermal and vacuum driven processing as EMI/RFI shielding in a PVD tool. Such coatings are applied to porous substrates, affixing die, processing, and removal by water washing [4]. Success in these and related temporary applications depend upon matching the chemistry of the washable coating with the process. Our experience in creating solutions for these and other industry needs will be discussed as well as the criteria for using temporary washable coatings.
Reliability of SAC 105 and SAC1205N under Drop Tests
Authors: Lan Jia-Shen , Fan Stuwart , Huang Louie , Wu Mei-Ling 
Published: November 2016

Abstract
In this paper, the solder joint failure and the solder joint fatigue life in the Thin-profile Fine-pitch Ball Grid Array (TFBGA) Package was investigated by performing the drop test, and implementing a simulation model. Owing to the need to meet the increasing demands for functionality, microelectronic package reliability can be compromised and has become the key issue when executing drop tests. During impact in drop test, the deformation of PCB due to bending and mechanical shocks can cause solder joint crack. While this is a well-known issue, observing the solder joint responses during the test execution can be a challenge. Therefore, in this work, a simulation model approach has been developed to investigate the stress and strain of the solder joint during the drop test. In this research, the JEDEC Condition B drop test was simulated, characterized by 1500G peak acceleration and 0.5 ms duration. The drop test simulation model was successful in predicting the solder joint fatigue life with different solder joint materials, such as SAC105 and SAC1205N, while also facilitating result comparison to identify the most optimal structure.
Package Architecture and Component Design for an Implantable Peripheral Nerve Stimulation and Recording System for Advanced Prosthetics
Authors: Bjune Caroline K. , Lachapelle John R. , Czarnecki Andrew , Kindle Alexander L. , Burns John R. , Segura Carlos A. , Grainger Julianne E. , Nugent Brian D. , Sriram Tirunelveli S. , Parks Philip D. , Keefer Edward , Cheng Jonathan 
Published: November 2016

Abstract
One of the limitation of current prosthetics is the ability to provide sensory feedback to the human user. Due to this constraint, approximately 60–80 percent of amputees experience a phenomenon known as phantom limb pain, an ongoing painful sensations that to the individual, seems to be coming from the part of the limb that is no longer there. The lack of sensory feedback also limits the intuitive control of the user's hand movement, i.e. sense of grip or position. To address these limitations, we created am implantable system that could provide peripheral nerve stimulation, recording and motor control. The architecture of our Sensory-Stimulation Lead (SSL) system consist of multiple satellites connected to Draper's custom designed nerve electrodes. In this phase of the design, the implanted system is connected to a controller via percutaneous connections. The active electronics of the satellite is enclosed in a hermetic package approximately 14mm in diameter and less than 5mm thick. A custom ceramic feedthrough substrate provides the electrical connections of the internal electronics board to both the nerve electrodes and percutaneous leads. In this paper, we will describe the various packaging components of the system and the design, fabrication, and assembly considerations that drove our technology choices.
Unique Silicon Passive Component Technology for Medical implants combining highly flexible integration with outstanding performances.
Authors: Bunel Catherine , Murray Franck 
Published: November 2016

Abstract
Many implantable medical devices such as pacemakers, cochlear implants and neurostimulation devices have been developed and tremendously improved in electrical power consumption, battery lifetime, functionality, system delivery, and wireless communication but there is still a lot of room for improvement and these devices are still facing challenges with size shrinkage and reliability. Many efforts have been engaged to miniaturize and to facilitate the implantation of the device in order to reduce the impact of the surgery. IPDiA's technology is strongly contributing to this progress by providing passive components such as capacitor arrays or RC networks, with a high contribution to miniaturization, a very low profile, extremely low leakage and outstanding reliability. In this paper, the enablers such as design flexibility, co-integration, low leakage, extended life time will be presented and illustrated by several examples of solutions. Firstly, the recent progress in the capacitor technology development will be presented, secondly the impact of the component technology on the overall system size and performances through advanced packaging solutions will be highlighted together with other key differentiators and finally some of the applications where this technology is essential will be presented.
Correlation of Through-silicon Via (TSV) Dimension Scaling to TSV Stress and Reliability for 3D Interconnects
Authors: Spinella Laura , Im Jang-Hi , Ho Paul S. , Jiang Tengfei 
Published: November 2016

Abstract
Through-silicon vias (TSVs) are a crucial technology for enabling full three dimensional integration, yet they pose unique reliability risks, including thermal stress buildup due to the mismatch in the coefficient of thermal expansion between the silicon and the copper and the via extrusion phenomena. These effects can degrade device performance and it has been proposed that smaller TSV dimensions will reduce these reliability risks. In this paper, the correlation of shrinking dimensions to TSV stress and reliability is investigated, focusing on the effect of the microstructure on the plasticity and extrusion for 10, 5, and 2 μm diameter copper vias. Synchrotron x-ray microdiffraction revealed local plasticity concentrated in the tops of the vias of all diameters, and showed that the TSV stress behavior seemed to depend on the variations in the grain structure. Electron backscatter diffraction quantified the microstructure to show a tight distribution of grain sizes after the post-plating anneal, but further annealing to 400°C causes considerable data scatter for vias of all diameters. This result is consistent with the observed via extrusion statistics, in which the absolute values and variations in the extrusion heights increased significantly with further annealing. The wafer curvature technique is also used to observe the TSV stress relaxation behavior. Overall, these results suggest that scaling down TSV dimensions may not improve the stress and reliability behavior, particularly after further annealing at 400°C. Since such annealing processes are required for via-middle fabrication, it seems that via reliability will continue to be a challenge as TSV scaling continues.
High Aspect Ratio Bumping Process with Solder Bumps Included Sintered Pillars
Authors: Nakagawa S. , Yasoshima T. , Uno H. , Ishikawa M. 
Published: November 2016

Abstract
This study provides new method for fine pitch bumping described as sintered pillar (SP) bumping method, which enables the formation of high aspect ratio bumps for stable assembly process. The SP bumps include sintered pillars formed by the transient liquid phase sintering process, and both SP bumps and sintered pillars are used with conventional paste printing process and equipment. By optimizing the sintered pillar paste, we achieved approximately 25% increase in bump height compared to those formed by the conventional paste printing process. We propose that the SP bumping method is one of the solutions for fine pitch bumping.
Advanced Wafer Level Packaging of RF-MEMS with RDL Inductor
Authors: Castillou Paul , Gaddi Roberto , van Kampen Rob , Lin Yaojian , Jamshidi Babak , Yoon Seung Wook 
Published: November 2016

Abstract
The market for portable and mobile data access devices that are wirelessly connected to the cloud anytime and anywhere is exploding. The trend to access any network from anywhere is driving increased functional convergence in the radio, which translates into increased packaging complexity and sophistication. This is creating unprecedented demand for RF components providing more integration- in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as wafer level chip scale packaging (WLCSP) or fan-out wafer level packaging (FO-WLP) solutions such as embedded Wafer Level Ball Grid Array (eWLB) to meet these needs.
One of the most promising solutions to enable the required RF performance levels in mobile and wearable devices is the use of RF MEMS Tuners. Mobile original equipment manufacturers (OEMs) are rapidly adopting antenna tuning solutions to be able to provide the required signal strength across the large number of LTE spectrum bands used globally.
With RF MEMS technology now maturing, the biggest challenge to address the fast growing opportunity was to find a suitable packaging technology that can deliver RF MEMS tuners in the smallest possible form factor, while maintaining the excellent performance characteristics of the RF MEMS technology. After careful analysis, an eWLB/FO-WLP package was adopted and released to volume production in 2015. The commercial eWLB/FO-WLP RF MEMS tuners outperform traditional RF silicon-on-insulator (SOI) switch-based antenna tuning solutions, resulting in much higher data rates (up to 2×) and improved battery life (up to 40%). Redistribution layers (RDL) in eWLB are utilized for higher electrical performance and complex routing to meet electrical requirements. The ability to utilize embedded passives in a multi-layer eWLB structure provides a number of advantages including cost reduction, footprint reduction and increased reliability. Inductors in eWLB offer significantly better performance compared to inductors in standard on-chip technologies.
In this paper, we examine the WLCSP and eWLB packaging assembly flow, solutions to RF design challenges as well as characterization of RF performance. Further improvement of the quality factor of the integrated inductor and capacitors by using low-loss thin-film dielectrics and molding compound in eWLB will be reported as well. Package level reliability test results will also be presented in this paper.
Optimization of laser release layer, glass carrier, and organic build-up layer to enable RDL-first fan-out wafer-level packaging
Authors: Lee Alvin , Su Jay , Huang Baron , Trichur Ram , Bai Dongshun , Liu Xiao , Shen Wen-Wei , Lin Yu-Min , Chang Tao-Chih , Chang Hsiang-Hung , Chiang Chia-Wei , Fu Huan-Chun , Chen K. C. , Lu Yu-Lan , Chen Kuan-Neng 
Published: November 2016

Abstract
With increasing demand for mobile devices to be lighter and thinner and consume less power while operating at high speed and high bandwidth, many equipment suppliers and assembly participants have invested great efforts to achieve fine-line fan-out wafer-level packaging (FOWLP). However, the inherent warp of reconstituted wafers, which can contribute to poor die placement accuracy and/or delamination at the interface of the build-up layer and carrier, remains a major challenge. In this study, the interactions among laser release layer, glass carrier, and build-up layer were evaluated for optimization of redistribution layer (RDL)–first FOWLP as a foundation to move toward fine-line FOWLP.
In this study, a series of experiments incorporating glass carrier, laser release layer, and build-up layers were carried out to determine the optimal setup for RDL-first FOWLP. First, glass carriers (300 mm × 300 mm × 0.7 mm) with coefficients of thermal expansion of 3 and 8 ppm/°C were treated with 150-nm laser release layers. After deposition of 0.1 μm of sacrificial material on the glass carrier, 8-μm build-up layers were coated and patterned by lithography to electroplate Cu interconnections with a density of approximately 10% of the surface area. Subsequent to die attachment, molding compound was applied on top to form a 200-μm protective overcoat. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 308-nm laser to complete the design of experiments (DOE).
An experiment to study the correlation of glass carrier, laser release layer, build-up layers, and molding compound in RDL-first FOWLP processes is discussed to address full process integration on 300-mm glass substrates. The combination of glass carrier, laser release layer, build-up layer, and molding compound will pave the way for realizing cost-effective RDL-first FOWLP on panel-size substrates.
Increasing the Reliability of 3D Printing a Wi-Fi Sensor Device
Authors: Deffenbaugh Paul I. , Stramel Danielle M. , Church Kenneth H. 
Published: November 2016

Abstract
Printed electronics and 3D printing have proved their viability for manufacturing functional devices. The state of the art is now at a crossroads where yield, reliability, survivability, and longevity improvements will govern its continued success in manufacturing. Currently, 3D printed electronics demonstration parts are either grossly oversized or are meticulously fabricated and involve significant human interaction and repair and ultimately have low manufacturing yield.
Presented here are techniques for improving manufacturing yield. Coefficient of thermal expansion (CTE) mismatch problems frequently occur in devices with heterogeneous materials such as bulk metals, thermoplastics, thermosets, conductive pastes and inks, and pourable dielectrics. Controlling the interfaces between these materials in new and creative ways is key to solving these problems during manufacturing and lifecycle. Selecting materials with good properties such as adhesion, surface energy, flexibility, conductivity, and dielectric properties is the path forward to excellence in this field.
Certain improvements in the design of 3D printed electronic devices (demonstrated here) show improved ruggedness. A long-lasting 3D printed electronic device that has been operating 24/7 for 21,000 hours is shown, and the techniques of its design and fabrication are described in detail. Several testing procedures evaluate the performance of the devices. Microscope photos show key problem areas, solutions are implemented, and material selections are presented. Overall device function is monitored wirelessly before, during, and after temperature changes.