bluuebunny/crossref_metadata_2025_split huggingface dataset:
Joint Healing Thermal Interface Material
Authors: Yang Jingting , Strader Jason , Orzolek Sean , Pruss Eugene , Fosnot Phillip , Galloway Jesse 
Published: November 2016

Abstract
Today, thermal interface materials (TIM) are widely used between a processor die and an integrated heat-spreader (IHS) to provide a good thermal conduction path for heat transfer from the electronic package. As the current trend towards larger “die size designs” progresses, the performance and reliability of the TIM will be a greater challenge for thermal engineers. In these larger die size designs, the TIM will experience increased movement as a result of the coefficient of thermal expansion (CTE) mismatch between the die and the printed circuit board. Traditionally, indium and dispensable thermoset materials are utilized in this application. However, delamination of the TIM from one of the mating surfaces is becoming more common as these materials are unable to compensate for the increased movement. In addition, the increasing cost of indium metal is causing indium-based TIMs to become cost prohibitive while dispensable materials require frozen shipment and storage, creating logistics complications and increased costs.
A recently concluded application study demonstrated that a joint-healing thermoplastic pad had better performance after thermal shock cycling, when compared to typically used TIMs. The joint-healing, thermoplastic pad maintained lower thermal resistance at the center and edges of the die. The soft thermoplastic nature of this material helps prevent delamination, or pump out, during cycling and is capable of joint-healing most delaminations that occur at operating temperatures. Data at various intervals ending at 1000 cycles will be presented.
The ability to ship and store this material at room temperature as well as pre-apply it to the IHS adds additional value by simplifying logistics and reducing cost.
Minimizing Voiding in Bottom Terminated Components by Optimizing the Solder Paste Flux
Authors: Briggs Ed 
Published: November 2016

Abstract
Perhaps the single biggest challenge in PCB assembly today is voiding under bottom terminated components (BTCs) such as QFNs (quad-flat-pack, no-leads), D-Paks, and LGAs (land grid arrays). Many bottom terminated components, such as QFNs, have a large thermal pad on the bottom side which provides excellent thermal and electrical grounding properties. However, effectively soldering these components to minimize thermal pad voiding can be a challenge. Many automotive electronics assemblers are increasing this challenge by requiring less than 10% voids to improve reliability.
The large deposit of printed solder paste required to solder the thermal pad typically induces flux entrapment and subsequent voiding during the reflow process. Large voids and/or a high number of voids cause decreased thermal conductivity and lower the mechanical strength of the resulting solder joints. The large solder paste deposit required may also cause the component to float and open up the electrical connections around the perimeter of the component. Another factor affecting voiding has been the transition to lead-free solder, which has been marked by the use of various SAC alloys. Most applications for surface mount assembly use SAC305 (96.5Sn/3.0Ag/0.5Cu) with a melting temperature range of 217–220°C. The higher temperatures required for lead-free soldering and the increased surface tension of the SAC alloy exacerbate the voiding issue.
This paper will focus on the techniques for optimizing the assembly process for QFN components, with a focus on minimizing voiding. Best practices for lead-free reflow profiling, stencil aperture design, solder paste volume control, and the importance of flux chemistry to minimize void formation will be discussed.
An Integrated Sensor for Detecting Moisture Ingress in Printed Circuit Board Assemblies
Authors: Dean Robert N. , Loden Nathan B. , Hartley Curtis J. , Craven Jeffery D. 
Published: November 2016

Abstract
Numerous applications exist where electronics must operate reliably in moist environments, and often for long periods of time. In these environments, the circuit board assemblies may experience moisture ingress, which can deleteriously affect the operation and life span of these systems. Detecting moisture ingress is therefore useful for improving system design, assembly techniques, packaging technologies and maintenance scheduling. Capacitive fringing field sensors are useful for measuring the moisture content of materials. Therefore, a capacitive fringing field sensor, implemented in printed circuit board technology with a CMOS relaxation oscillator interface circuit, is proposed for detecting moisture ingress into the printed circuit board assembly. A set of instrumented sensors was designed, fabricated and tested. The results demonstrated that when the test articles experienced prolonged exposure to moisture, the instrumented sensors experienced an 18.42% change in output value, indicating a satisfactory sensitivity to moisture ingress.
Evaluation of a Lead-Free Ultra Low Temperature Co-Fire Ceramic (ULTCC) Tape Designed for Lamination on Aluminum Substrates and a Compatible Co-Fireable Silver Conductor
Authors: Grabey Steven , Shahbazi Samson , Persons Ryan , Shahbazi Caitlin 
Published: November 2016

Abstract
Light-emitting diodes (LEDs) are the product of choice for many commercial and industrial lighting applications. Due to increasing power densities, alternative mounting solutions are being evaluated in order to achieve the lowest junction temperatures and lowest thermal resistances. Previous papers have explored the benefits of using a thick film system as opposed to a traditional Metal Core Printed Circuit Board (MCPCB). The advantage of being able to directly insulate a heat sink eliminates additional MCPCB layers and mechanical attachment that can decrease the thermal conductivity of the module and increase cost. Lower thermal resistance results in higher performing LED modules at a lower cost and a longer lifetime.
A process has been developed and evaluated where an ultra-low temperature co-fired ceramic (ULTCC) tape will be laminsated directly on to an aluminum heat sink in order to electrically isolate the substrate. The green tape will then have a silver conductor applied to it and fired in one step. Using a tape system as opposed to an ink system creates many advantages. The tape system allows for processing in cavities, which is beneficial for recessed lighting and three-dimensional substrates. The co-firing silver conductor reduces the number of firing steps, leading to less dimensional variation of the heat sink and lower processing costs. This paper will discuss the material solutions, processing requirements, and reliability data for a completely co-fired ULTCC system on aluminum.
Challenges in Assembly implementation of ultra-thin profile flipchip package-on-package
Authors: Eghan Abu , Choi Kyoo B 
Published: November 2016

Abstract
The assembly and structural challenges associated with a low profile bare die flipchip package-on-package (PoP) are reviewed. The PoP was designed to accommodate a JEDEC 256 ball FBGA memory. This dual channel 32-bit LPDDR3 memory package has a unique signal crossing ball arrangement between the Data bus of one channel and the Control/Address (CAS) bus of the other. The ball arrangement presents some crossing challenges for PoP implementation of controller ICs. For timing reasons, the memory controller blocks are traditionally placed together in a central area of the base chip, and signals are routed to line up with the fixed LPDDR3 landing sites. For the dual channel case the routing requires crossing one CAS signal group over the other's data lines. To address this crossing in this product, a copper redistribution layer (RDL) was deployed at the bump stage to bring the appropriate LPDDR3 signals from the controller block to line up with the memory balls. The thick copper RDL/Cu-Pillar arrangement left a 10–13um of dielectric layer over the base die. Because the 0.4mm pitch and clearance requirements of the selected memory package, a very low profile flipchip die standoff was required. The dielectric layers and copper density in RDL had significant impact on the handling of these thinned wafers and die through the assembly processes. Though newer package offerings - like Amkor's Thru Mold Via (TMV) technology or Invensas' Bond Via Array (BVA could have been deployed, a Cu-pillar based bare die flipchip (FCBGA) using a very thin die was selected for its simplicity and lower cost. All package related reliability tests have been completed with success. The process optimization and trade-off needed to achieve success through assembly are discussed in this paper
Novel glass substrates for minimizing thermal stress development during electronic device packaging process
Authors: Nomura Shuhei , Sawamura Shigeki , Hanawa Yu , Sakai Yusuke , Hayashi Kazutaka ,   Asahi Glass Co., Ltd.
Published: November 2016

Abstract
Glass can be utilized for support or career substrate in large size packaging process since it has excellent mechanical and optical properties. However, the thermal stress caused by a mismatch of coefficient of thermal expansion (CTE) causes an unneglectable warpage during a thermal process.
In order to overcome this thermal stress issue, we have developed novel glasses that have finely tuned CTE characteristics to fit each packaging process. In this paper, we will report on a glass substrate whose CTE is perfectly matched with that of Si, and a series of glass substrates whose CTEs are controlled in sub-ppm order and within the range of 3.3 ~ 12.0 ppm/°C.
To evaluate the effect of glass CTE on the thermal stress management, the warpage behavior of Si wafer after glass wafer bonding were investigated by both numerical simulation and experiment. Both results indicate that a small CTE mismatch can cause an unneglectable wafer warpage during the thermal process. Thus sub-ppm order control of glass CTE is essential for minimizing thermal stress development in large size packaging process.
The glass substrate with Si matched CTE is suitable for the process where glass and Si are contact directly, e.g. Si back grinding process or through glass via (TGV) technology. The series of glass substrates whose CTEs are finely controlled in a high range are useful when the packaging process utilizes high amount of resins, such as Fan-Out wafer level packaging process.
Measuring Die Tilt Using Shadow Moiré Optical Measurements; New Techniques for Discontinuous and Semi-Reflective Surfaces
Authors: Hubble Neil 
Published: November 2016

Abstract
When dealing with production of Flip Chip Packages in semiconductor packaging, the angle between the die and package substrate is critical for maintaining product yield and reliability. Current outgoing quality checks for die tilt can be time consuming to measure heights via point to point measurement techniques. Existing die tilt measurement approaches can also have reproducibility issues from user to user.
Shadow moiré technology is a full field optical inspection technique commonly used for flatness characterization in the semiconductor industry, particularly at elevated temperatures. Two limitations to shadow moiré apply when discussing outgoing QC of die tilt: 1) shadow moiré requires a diffuse reflective surface for measurement; 2) shadow moiré is unable to measure sudden step heights.
This paper discusses applications techniques and real world examples to overcome or mitigate the limitations of shadow moiré technology and use this full field and high speed measurement technology to measure die tilt. Using shadow moiré for this measurement technology can reduce measurement and user time as well as improve consistency of measurements from user to user. As shadow moiré tools are often used for at temperature flatness measurements, this added application can reduce the number of different measurement tools needed in QA labs.
Achieving Low Voiding with Lead Free Solder Paste for Power Devices
Authors: Zappella Pierino I , Sedehi Saeed , Hizon Robert , Williams Adrienne D. 
Published: November 2016

Abstract
The objective of this research was: (1) to demonstrate a low void concentration of &lt;5% using solder paste on different materials such as nickel to nickel, copper to copper, nickel to copper, silicon die to nickel and silicon die to copper; (2) to achieve a short cycle time for the solder paste reflow operation and (3) to highlight the advantages of solder paste vs. AuSn and other alloy preforms that require gold metallization.
For power device applications where low void concentration and reduced costs are important, we have demonstrated a solder paste solution that can offer a lower cost solution. The flux incorporated in solder paste is a major contributor in creating voids. Our approach was to utilize different pressures to reduce voids resulting in higher production yields.
Test coupons of pure nickel and copper were sized to simulate die and substrates. Silicon device die were also included. A lead free 95Sn5Ag alloy water soluble solder paste was selected for this evaluation. The paste application consisted of a manual screen print with templates of different thicknesses. Void detection concentrations were identified via our in-house X-ray system. The advantages of solder paste can be significant, but typically, we would expect an increase in voids resulted from the flux incorporated in the paste. Accordingly, in this paper, we evaluated a low voiding flux solder paste compatible with power device metal materials and suitable for use in a production environment.
Transient liquid phase sintering materials (TLPS) vs. conventional solders for high temperature MLCC interconnects.
Authors: McConnell John , Bultitude J. , Jones L. , Qazi J. 
Published: November 2016

Abstract
There is a growing need within the electronics industry for interconnect materials that can meet higher processing and operating temperatures. The solidus to liquidus range of current tin (Sn) based solders and other lead (Pb) solders are narrower than traditional SnPb solders as the industry is moving to higher temperatures. Transient Liquid Phase Sintering (TLPS) is a technology that offers low processing temperatures while having high temperature capabilities but has had limited exposure outside of the Semiconductor industry. Results of mechanical testing as well as product environmental data is presented herein as TLPS is used as a mechanical and electrical interconnect for Multi-Layer Ceramic Capacitors (MLCC).
Study of Void Formation Mechanism in Electroplated SnAg Solder Bump
Authors: Tatsumi Koji , Sakai Akio , Kawai Syunsuke , Katase Takuma , Miyazawa Takashi , Ishikawa Masayuki 
Published: November 2016

AbstractSnAg electroplating method is widely used in the formation of LF solder bump for flip chip connection. While electroplating is able to form void free solder bump in a suitable operating condition, void may occur suddenly when used in mass production. This study aims at understanding the gas source in the void of electroplated SnAg solder bumps and determining the manufacturing process factors which affect the void formation.There are various types of void formation mode. One mode is H2 gas generation on cathode surface during electroplating. Both the cross-sections of solder bumps, as well as an analysis data of the gas in the void taken by the TDS (Thermal Desorption Spectrometry) were evaluated. The cross-section of the solder bump which contains void due to the reflow process revealed the existence of several tens of nm to several μm size pits in the solder bump before reflow. TDS analysis indicates that the pits consisted of mainly H2O, H2 and the decomposition of organics. A possible void formation mechanism is the evaporation of H2 gas and the incorporated electrolyte solution in the bump by reflow. These pits in the solder were caused by various process parameters. One of the causes is due to the setting of the current density in the SnAg electroplating process being inappropriate. The current density should be adjusted corresponding to the electrolyte performance and bump design such as PR thickness, opening diameter and bump density. The computer simulation demonstrated that a thick PR limits the diffusion of the Sn2+ ions into via holes and having the current density too high causes a lack of Sn2+ ions on the cathode surface and causes H2 gas generation.The other mode of void formation is Ag displacement of the under bump metallization (UBM) surface in dwell time in the SnAg electrolyte solution before the start of plating. The adjustment of each process parameter can eliminate the source of the void and achieve a high reliability of SnAg bump formation.
Effects of x-ray exposure on NOR and NAND flash memories during high-resolution 2D and 3D x-ray inspection
Authors: Sharma Anju , Sivakumar Preeth , Feigel Andrew , Bae In Tae , Lehman Lawrence P. , Gregor Joseph , Cash James , Kolly Joseph 
Published: November 2016

Abstract
In this paper, we present a detailed study on the effects of x-ray exposure on data corruption in commercially available NOR and NAND flash memory devices during x-ray inspection with a high-resolution Phoenix Nanomex system from GE. We investigated role of the x-ray tube voltage, tube current, device orientation, x-ray filters and photon energy. We explored the low exposure regime in detail when the first byte errors start occurring and also determined the absorbed dose for 100% byte errors. No data corruption was observed after the normal 2D x-ray inspection and CT scans of the NOR and NAND flash memory devices under study. However, increase in the tube voltage, tube current and/or the x-ray beam size resulted in byte errors which increased exponentially with the exposure time. The byte error rate was found to be much more sensitive to the tube voltage than the tube current. It was also affected by the device orientation with respect to the x-ray beam. The NAND flash memories were found to be more susceptible to data corruption from x-ray exposure than the NOR devices examined in this work. Some NOR devices were irradiated with the monochromatic x-rays from the CHESS synchrotron facility at Cornell University. Of all the photon energies used in this study, 12 keV x-ray irradiation resulted in the highest byte error rate. In this paper, we thus present a direct proof that it is the low-energy photon absorption that plays a major role in introducing bit errors in flash memories. Commonly available low-energy x-ray filters such as Cu and Al foils were found to be effective in preventing data corruption in such devices for long exposure time. Use of lower tube voltage, lower tube current, smaller x-ray spot size, short exposure time and low-energy x-ray filters, is recommended to prevent data corruption during 2D and 3D x-ray inspection of flash memory devices and other semiconductor devices in general.
The Impact of Stencil Printing Upon Assembly & Reliability Of 0.3mm Pitch CSP Components
Authors: Whitmore Mark , Schake Jeff 
Published: November 2016

Abstract
With the continual shrinking of electronic assembly form factors, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged.
For the stencil printing process, this means that historically accepted stencil aperture area ratio design rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. As a result, a major study has been undertaken looking at several different aspects of the stencil printing process, and their impact upon the assembly and reliability of 0.3mm pitch CSP components.
In a preliminary test, stencil printing factors such as stencil aperture size and printing technology (standard squeegees vs ultrasonically aided active squeegees) were investigated. Data showed that the active squeegees provided a significantly larger process window. Subsequently, components were assembled using a range of solder paste volumes printed with both standard and active squeegee technology. The components assembled using an active squeegee process exhibited higher assembly yield, and also extended reliability when subjected to thermal cycling.
Glass 3D Solenoid Inductors IPD Substrate Manufacturing Assembly and Characterization
Authors: Chien Chun-Hsien , Chen Yu-Hua , Hsieh Yu-Chung , Lin Wei-Ti , Chen Chien-Chou , Hu Dyi-Chung , Tseng Tzvy-Jang , Shenoy Ravi 
Published: November 2016

Abstract
This paper aims to discuss the integration of 3D solenoid inductors fabricated by using a glass core substrate with through glass via (TGV) technology. Glass materials were chosen for the substrate core based on the natural properties of low insertion loss, adjustable CTE, low surface roughness and high insulation for RF application. The TGV formation and semi-additive conformal copper electroplating were the key processes of the glass core substrate manufacturing. The key benefits of these evaluations are a competitive cost structure for a 508mm × 508mm glass panel IC (integrated circuit) substrate HVM (high volume manufacture) line. The characterization results of TGV formation, the process flow of 3D solenoid inductor glass core substrate and real silicon device chips assembled on the top of glass core substrate were also investigated and discussed.
Silicon based cell sorting device: Fabrication, characterization and applications
Authors: Majeed Bivragh , Liu Chengxun , Sohn Erik , Van Acker Lut , De Wijs Koen , Sabuncuoglu Deniz , Lagae Liesbet 
Published: November 2016

Abstract
Cell sorting is an important diagnostic tool used in various aspect of medical prognosis. Numerous cell sorting techniques are currently available on market but they are quite bulky, expensive and at the same time requires very trained operators. In this paper we report on wafer level fabrication technique that will allows for a small form factor device targeting cell sorting. We give detailed overview for the fabrication of our miniaturized cell sorter that is formed with a CMOS compatible process. It used standard fabrication technique in combination with photo-patternable polymer, that has excellent properties for microfluidics applications. The ability to process on wafer level distinguish this from other processes, whose yields are limited to few test samples. The device fabrication includes: processing of micro-heaters, definition of polymer microfluidic channels and collective die-to-wafer bonding of glass substrate onto the polymer channels. We report on the initial characterization of the cell sorting targeting sorting rate and sorting yield. We have achieved sorting rate of 5,000 cells/s and yield of 70% is obtained in initial investigations.