bluuebunny/crossref_metadata_2025_split huggingface dataset:
Epidemiology and mapping of serious and fatal road traffic injuries in Guyana: results from a cross-sectional study
Authors: McWade Conor M , McWade Melanie A , Quistberg D Alex , McNaughton Candace D , Wang Li , Bux Zulfikar , Forget Nicolas P 
Published: November 2016

ObjectiveTo describe the epidemiology of Guyana's road traffic injuries and perform the first geocoding of road traffic injuries in this setting.MethodsThis was a registry-based retrospective cross-sectional study investigating collisions resulting in serious and fatal injuries. Police reports from two police divisions were used to identify victim, second party (ie, non-victim) and collision characteristics of all serious and fatal collisions between January 2012 and June 2015. Collisions with available location data were geocoded using Geographic Information Systems. Distributions of characteristics were compared for urban and rural areas. Multivariable logistic regression was used to assess variables associated with fatal collisions.ResultsThe study included 751 collisions, resulting in 1002 seriously or fatally injured victims. Fatally injured victims tended to be older, male and either pedestrians or cyclists. Fatal collisions tended to take place in rural areas, occur on weekends and involve speeding. Fifty-three per cent of fatalities occurred due to non-motorised road users being struck by motorised road users, and the most common fatal collision type was between pedestrians and motor vehicles (35%). The distribution of collisions was similar for urban (43.8%) and rural (56.2%) areas. Fatal collisions were more likely to occur in rural settings.ConclusionsRoad traffic injuries pose a considerable public health burden in Guyana. These results suggest a pattern of high mortality in rural collisions and a disproportionate burden of injuries on vulnerable road users. The spatial distribution of collisions should be considered in order to target interventions and improve road traffic safety.
Dural sinus stenting for idiopathic intracranial hypertension: factors associated with hemodynamic failure and management with extended stenting
Authors: Kumpe David A , Seinfeld Joshua , Huang Xianchen , Mei Quelin , Case David E , Roark Christopher D , Subramanian Prem S , Lind Kimberly E , Pelak Victoria S , Bennett Jeffrey L 
Published: November 2016

BackgroundSome patients undergoing dural sinus stenting for idiopathic intracranial hypertension (IIH) develop clinical and hemodynamic failure (recurrence of the pressure gradient) owing to stent-adjacent stenosis.ObjectiveTo characterize factors associated with hemodynamic failure, and to describe outcomes of patients after repeat stenting.Materials and methodsWe reviewed the initial and follow-up clinical, venographic, and hemodynamic data in 39 patients with IIH treated over 17 years with stenting. Thirty-two had follow-up angiographic and hemodynamic data at 1–99 months (mean 27.6, median 19.5 months). Eight patients were treated with 12 repeat stenting procedures, including extended stenting into the superior sagittal sinus (SSS).ResultsAll patients had an initial successful hemodynamic result with the pressure gradient reduced from 10–43 to 0–7 mm Hg. 10/32 patients (31.3%), all women, developed new stenoses in the transverse sinus or posterior SSS above the stent with a recurrent pressure gradient. 7/9 patients with pure extrinsic stenosis of the transverse-sigmoid junction pre-stenting developed new stenoses and hemodynamic failure. All patients with hemodynamic failure who were restented had early and mid-term documented hemodynamic success at 1.7–50 months. They were free from papilledema at 3.8–50 months after the last restenting, and 11.5–99.5 months after initial stent placement (mean 45.3, median 38.5 months).ConclusionsPure extrinsic compression of the transverse-sigmoid junction and female gender were strongly associated with hemodynamic failure. Eight patients with hemodynamic failure who were restented had successful control of papilledema, including 4/4 who had extended stenting into the SSS.
Testing unmanned aircraft systems for salmon spawning surveys
Authors: Groves Phillip A. , Alcorn Brad , Wiest Michelle M. , Maselko Jacek M. , Connor William P. 
Published: November 2016

Unmanned aircraft systems (UASs) were tested for counting Chinook salmon ( Oncorhynchus tshawytscha) redds as a more accurate, safer alternative to manned helicopter flights. Counting redds from the helicopter was less expensive and time consuming, but of the total redds counted at selected sites with a UAS, an average (± SD) of only 77% ± 14% was counted from the helicopter. A river-wide census of redds was not possible with a UAS because the study area was too large for the single field crew to survey. Simulation analyses were used to compare stratified random sampling (STRS) and sampling proportional to size (PPS) for estimating annual total redd counts from data collected with a UAS. The STRS estimates were more accurate and precise, whereas the PPS estimates, though biased, had 95% CIs that included the observed redd count more frequently. We strongly recommend that researchers conduct simulation analyses to evaluate alternative survey sampling methods if they are considering replacing census counts made from manned aircraft with counts estimated from data collected with a UAS. We conclude that UAS application reduces the risk inherent to manned aircraft flights, but the reduction in risk can come at the cost of estimates of population parameters that can sometimes be inaccurate and lack 95% CI coverage.
Synthesising graphics card programs from DSLs
Authors: Cartey Luke , Lyngsø Rune , de Moor Oege 
Published: November 2016

Over the last five years, graphics cards have become a tempting target for scientific computing, thanks to unrivaled peak performance, often producing a runtime speed-up of x10 to x25 over comparable CPU solutions.
However, this increase can be difficult to achieve, and doing so often requires a fundamental rethink. This is especially problematic in scientific computing, where experts do not want to learn yet another architecture.
In this paper we develop a method for automatically parallelising recursive functions of the sort found in scientific papers. Using a static analysis of the function dependencies we identify sets - partitions - of independent elements, which we use to synthesise an efficient GPU implementation using polyhedral code generation techniques. We then augment our language with DSL extensions to support a wider variety of applications, and demonstrate the effectiveness of this with three case studies, showing significant performance improvement over equivalent CPU methods, and similar efficiency to hand-tuned GPU implementations.
Type-directed automatic incrementalization
Authors: Chen Yan , Dunfield Jana , Acar Umut A. 
Published: November 2016

Application data often changes slowly or incrementally over time. Since incremental changes to input often result in only small changes in output, it is often feasible to respond to such changes asymptotically more efficiently than by re-running the whole computation. Traditionally, realizing such asymptotic efficiency improvements requires designing problem-specific algorithms known as dynamic or incremental algorithms, which are often significantly more complicated than conventional algorithms to design, analyze, implement, and use. A long-standing open problem is to develop techniques that automatically transform conventional programs so that they correctly and efficiently respond to incremental changes.
In this paper, we describe a significant step towards solving the problem of automatic incrementalization: a programming language and a compiler that can, given a few type annotations describing what can change over time, compile a conventional program that assumes its data to be static (unchanging over time) to an incremental program. Based on recent advances in self-adjusting computation, including a theoretical proposal for translating purely functional programs to self-adjusting programs, we develop techniques for translating conventional Standard ML programs to self-adjusting programs. By extending the Standard ML language, we design a fully featured programming language with higher-order features, a module system, and a powerful type system, and implement a compiler for this language. The resulting programming language, LML, enables translating conventional programs decorated with simple type annotations into incremental programs that can respond to changes in their data correctly and efficiently.
We evaluate the effectiveness of our approach by considering a range of benchmarks involving lists, vectors, and matrices, as well as a ray tracer. For these benchmarks, our compiler incrementalizes existing code with only trivial amounts of annotation. The resulting programs are often asymptotically more efficient, leading to orders of magnitude speedups in practice.
Synchronising C/C++ and POWER
Authors: Sarkar Susmit , Memarian Kayvan , Owens Scott , Batty Mark , Sewell Peter , Maranget Luc , Alglave Jade , Williams Derek 
Published: November 2016

Shared memory concurrency relies on synchronisation primitives: compare-and-swap, load-reserve/store-conditional (aka LL/SC), language-level mutexes, and so on. In a sequentially consistent setting, or even in the TSO setting of x86 and Sparc, these have well-understood semantics. But in the very relaxed settings of IBM®, POWER®, ARM, or C/C++, it remains surprisingly unclear exactly what the programmer can depend on.
This paper studies relaxed-memory synchronisation. On the hardware side, we give a clear semantic characterisation of the load-reserve/store-conditional primitives as provided by POWER multiprocessors, for the first time since they were introduced 20 years ago; we cover their interaction with relaxed loads, stores, barriers, and dependencies. Our model, while not officially sanctioned by the vendor, is validated by extensive testing, comparing actual implementation behaviour against an oracle generated from the model, and by detailed discussion with IBM staff. We believe the ARM semantics to be similar.
On the software side, we prove sound a proposed compilation scheme of the C/C++ synchronisation constructs to POWER, including C/C++ spinlock mutexes, fences, and read-modify-write operations, together with the simpler atomic operations for which soundness is already known from our previous work; this is a first step in verifying concurrent algorithms that use load-reserve/store-conditional with respect to a realistic semantics. We also build confidence in the C/C++ model in its own terms, fixing some omissions and contributing to the C standards committee adoption of the C++11 concurrency model.
Dynamic trace-based analysis of vectorization potential of applications
Authors: Holewinski Justin , Ramamurthi Ragavendar , Ravishankar Mahesh , Fauzia Naznin , Pouchet Louis-Noël , Rountev Atanas , Sadayappan P. 
Published: November 2016

Recent hardware trends with GPUs and the increasing vector lengths of SSE-like ISA extensions for multicore CPUs imply that effective exploitation of SIMD parallelism is critical for achieving high performance on emerging and future architectures. A vast majority of existing applications were developed without any attention by their developers towards effective vectorizability of the codes. While developers of production compilers such as GNU gcc, Intel icc, PGI pgcc, and IBM xlc have invested considerable effort and made significant advances in enhancing automatic vectorization capabilities, these compilers still cannot effectively vectorize many existing scientific and engineering codes. It is therefore of considerable interest to analyze existing applications to assess the inherent latent potential for SIMD parallelism, exploitable through further compiler advances and/or via manual code changes.
In this paper we develop an approach to infer a program's SIMD parallelization potential by analyzing the dynamic data-dependence graph derived from a sequential execution trace. By considering only the observed run-time data dependences for the trace, and by relaxing the execution order of operations to allow any dependence-preserving reordering, we can detect potential SIMD parallelism that may otherwise be missed by more conservative compile-time analyses. We show that for several benchmarks our tool discovers regions of code within computationally-intensive loops that exhibit high potential for SIMD parallelism but are not vectorized by state-of-the-art compilers. We present several case studies of the use of the tool, both in identifying opportunities to enhance the transformation capabilities of vectorizing compilers, as well as in pointing to code regions to manually modify in order to enable auto-vectorization and performance improvement by existing compilers.
Chimera
Authors: Lee Dongyoon , Chen Peter M. , Flinn Jason , Narayanasamy Satish 
Published: November 2016

Chimera uses a new hybrid program analysis to provide deterministic replay for commodity multiprocessor systems. Chimera leverages the insight that it is easy to provide deterministic multiprocessor replay for data-race-free programs (one can just record non-deterministic inputs and the order of synchronization operations), so if we can somehow transform an arbitrary program to be data-race-free, then we can provide deterministic replay cheaply for that program. To perform this transformation, Chimera uses a sound static data-race detector to find all potential data-races. It then instruments pairs of potentially racing instructions with a weak-lock, which provides sufficient guarantees to allow deterministic replay but does not guarantee mutual exclusion.
Unsurprisingly, a large fraction of data-races found by the static tool are false data-races, and instrumenting them each of them with a weak-lock results in prohibitively high overhead. Chimera drastically reduces this cost from 53x to 1.39x by increasing the granularity of weak-locks without significantly compromising on parallelism. This is achieved by employing a combination of profiling and symbolic analysis techniques that target the sources of imprecision in the static data-race detector. We find that performance overhead for deterministic recording is 2.4% on average for Apache and desktop applications and about 86% for scientific applications.
Abstraction and invariance for algebraically indexed types
Authors: Atkey Robert , Johann Patricia , Kennedy Andrew 
Published: November 2016

Reynolds' relational parametricity provides a powerful way to reason about programs in terms of invariance under changes of data representation. A dazzling array of applications of Reynolds' theory exists, exploiting invariance to yield "free theorems", non-inhabitation results, and encodings of algebraic datatypes. Outside computer science, invariance is a common theme running through many areas of mathematics and physics. For example, the area of a triangle is unaltered by rotation or flipping. If we scale a triangle, then we scale its area, maintaining an invariant relationship between the two. The transformations under which properties are invariant are often organised into groups, with the algebraic structure reflecting the composability and invertibility of transformations.
In this paper, we investigate programming languages whose types are indexed by algebraic structures such as groups of geometric transformations. Other examples include types indexed by principals--for information flow security--and types indexed by distances--for analysis of analytic uniform continuity properties. Following Reynolds, we prove a general Abstraction Theorem that covers all these instances. Consequences of our Abstraction Theorem include free theorems expressing invariance properties of programs, type isomorphisms based on invariance properties, and non-definability results indicating when certain algebraically indexed types are uninhabited or only inhabited by trivial programs. We have fully formalised our framework and most examples in Coq.
High-level separation logic for low-level code
Authors: Jensen Jonas B. , Benton Nick , Kennedy Andrew 
Published: November 2016

Separation logic is a powerful tool for reasoning about structured, imperative programs that manipulate pointers. However, its application to unstructured, lower-level languages such as assembly language or machine code remains challenging. In this paper we describe a separation logic tailored for this purpose that we have applied to x86 machine-code programs.
The logic is built from an assertion logic on machine states over which we construct a specification logic that encapsulates uses of frames and step indexing. The traditional notion of Hoare triple is not applicable directly to unstructured machine code, where code and data are mixed together and programs do not in general run to completion, so instead we adopt a continuation-passing style of specification with preconditions alone. Nevertheless, the range of primitives provided by the specification logic, which include a higher-order frame connective, a novel read-only frame connective, and a 'later' modality, support the definition of derived forms to support structured-programming-style reasoning for common cases, in which standard rules for Hoare triples are derived as lemmas. Furthermore, our encoding of scoped assembly-language labels lets us give definitions and proof rules for powerful assembly-language 'macros' such as while loops, conditionals and procedures.
We have applied the framework to a model of sequential x86 machine code built entirely within the Coq proof assistant, including tactic support based on computational reflection.
Towards fully automatic placement of security sanitizers and declassifiers
Authors: Livshits Benjamin , Chong Stephen 
Published: November 2016

A great deal of research on sanitizer placement, sanitizer correctness, checking path validity, and policy inference, has been done in the last five to ten years, involving type systems, static analysis and runtime monitoring and enforcement. However, in pretty much all work thus far, the burden of sanitizer placement has fallen on the developer. However, sanitizer placement in large-scale applications is difficult, and developers are likely to make errors, and thus create security vulnerabilities.
This paper advocates a radically different approach: we aim to fully automate the placement of sanitizers by analyzing the ow of tainted data in the program. We argue that developers are better off leaving out sanitizers entirely instead of trying to place them.
This paper proposes a fully automatic technique for sanitizer placement. Placement is static whenever possible, switching to run time when necessary. Run-time taint tracking techniques can be used to track the source of a value, and thus apply appropriate sanitization. However, due to the runtime overhead of run-time taint tracking, our technique avoids it wherever possible.
The ramifications of sharing in data structures
Authors: Hobor Aquinas , Villard Jules 
Published: November 2016

Programs manipulating mutable data structures with intrinsic sharing present a challenge for modular verification. Deep aliasing inside data structures dramatically complicates reasoning in isolation over parts of these objects because changes to one part of the structure (say, the left child of a dag node) can affect other parts (the right child or some of its descendants) that may point into it. The result is that finding intuitive and compositional proofs of correctness is usually a struggle. We propose a compositional proof system that enables local reasoning in the presence of sharing.
While the AI "frame problem" elegantly captures the reasoning required to verify programs without sharing, we contend that natural reasoning about programs with sharing instead requires an answer to a different and more challenging AI problem, the "ramification problem": reasoning about the indirect consequences of actions. Accordingly, we present a RAMIFY proof rule that attacks the ramification problem head-on and show how to reason with it. Our framework is valid in any separation logic and permits sound compositional and local reasoning in the context of both specified and unspecified sharing. We verify the correctness of a number of examples, including programs that manipulate dags, graphs, and overlaid data structures in nontrivial ways.
Compiling functional languages for von Neumann machines
Authors: Honschopp U. , Lippe W. M. , Simon F. 
Published: November 2016

Functional programming languages based on the lambda calculus provide a powerful programming tool. Much of this power derives from the ability to use higher order functions, that means functions having either functional arguments or a functional result. However, attempts to implement such higher order functions without any restrictions have always been expensive, both in storage and time (e.g. [Bo/We]).
ALGOL-like languages only have functions with functional arguments (e.g. ALGOL 60 or, with some mode restrictions, PASCAL) and a run time stack can be used for managing function and procedure calls. Using Dijkstra's “display-technique” we can obtain a simple and efficient implementation.
A functional shell
Authors: Shultis Jon 
Published: November 2016

One of the best features of the standard UNIX shell is the use of pipes to compose programs. A C language derivative is used for more complex program combinations involving looping or branching. This paper presents an alternative shell language based on natural extensions of the pipe concept.
“Structured data streams” are introduced as a means of expressing potentially concurrent processing, and “labelled data streams” serve to route data to one of a pool of programs. These complex data streams are hooked together with functional operators much as simple data streams are hooked together with pipes. A generalized notion of “powers” provides for repetition of programs and also for systems that take an arbitrary number of input streams. This provides a uniform way of building complex tools from simple ones, as advocated by Kernighan and Plauger [8]. A major advantage of this new shell language is its program algebra, which facilitates system verification and analysis.