bluuebunny/crossref_metadata_2025_split huggingface dataset:
Synthesizing memory models from framework sketches and Litmus tests
Authors: Bornholt James , Torlak Emina 
Published: September 2017

A memory consistency model specifies which writes to shared memory a given read may see. Ambiguities or errors in these specifications can lead to bugs in both compilers and applications. Yet architectures usually define their memory models with prose and litmus tests—small concurrent programs that demonstrate allowed and forbidden outcomes. Recent work has formalized the memory models of common architectures through substantial manual effort, but as new architectures emerge, there is a growing need for tools to aid these efforts.
This paper presents MemSynth, a synthesis-aided system for reasoning about axiomatic specifications of memory models. MemSynth takes as input a set of litmus tests and a framework sketch that defines a class of memory models. The sketch comprises a set of axioms with missing expressions (or holes). Given these inputs, MemSynth synthesizes a completion of the axioms—i.e., a memory model—that gives the desired outcome on all tests. The MemSynth engine employs a novel embedding of bounded relational logic in a solver-aided programming language, which enables it to tackle complex synthesis queries intractable to existing relational solvers. This design also enables it to solve new kinds of queries, such as checking if a set of litmus tests unambiguously defines a memory model within a framework sketch.
We show that MemSynth can synthesize specifications for x86 in under two seconds, and for PowerPC in 12 seconds from 768 litmus tests. Our ambiguity check identifies missing tests from both the Intel x86 documentation and the validation suite of a previous PowerPC formalization. We also used MemSynth to reproduce, debug, and automatically repair a paper on comparing memory models in just two days.
One Process to Reap Them All
Authors: Hussein Ahmed , Payer Mathias , Hosking Antony L. , Vick Chris 
Published: September 2017

Ubiquitous mobile platforms such as Android rely on managed language run-time environments, also known as language virtual machines (VMs), to run a diverse range of user applications (apps). Each app runs in its own private VM instance, and each VM makes its own private local decisions in managing its use of processor and memory resources. Moreover, the operating system and the hardware do not communicate their low-level decisions regarding power management with the high-level app environment. This lack of coordination across layers and across apps restricts more effective global use of resources on the device.
We address this problem by devising and implementing a global memory manager service for Android that optimizes memory usage, run-time performance, and power consumption globally across all apps running on the device. The service focuses on the impact of garbage collection (GC) along these dimensions, since GC poses a significant overhead within managed run-time environments. Our prototype collects system-wide statistics from all running VMs, makes centralized decisions about memory management across apps and across software layers, and also collects garbage centrally. Furthermore, the global memory manager coordinates with the power manager to tune collector scheduling. In our evaluation, we illustrate the impact of such a central memory management service in reducing total energy consumption (up to 18%) and increasing throughput (up to 12%), and improving memory utilization and adaptability to user activities.
Security Analysis of Encrypted Virtual Machines
Authors: Hetzelt Felicitas , Buhren Robert 
Published: September 2017

Cloud computing has become indispensable in today's computer landscape. The flexibility it offers for customers as well as for providers has become a crucial factor for large parts of the computer industry. Virtualization is the key technology that allows for sharing of hardware resources among different customers. The controlling software component, called hypervisor, provides a virtualized view of the computer resources and ensures separation of different guest virtual machines. However, this important cornerstone of cloud computing is not necessarily trustworthy or bug-free. To mitigate this threat AMD introduced Secure Encrypted Virtualization, short SEV, which transparently encrypts a virtual machines memory.
In this paper we analyse to what extend the proposed features can resist a malicious hypervisor and discuss the tradeoffs imposed by additional protection mechanisms. To do so, we developed a model of SEV's security capabilities based on the available documentation as actual silicon implementations are not yet on the market.
We found that the first proposed version of SEV is not up to the task owing to three design shortcomings. First the virtual machine control block is not encrypted and handled directly by the hypervisor, allowing it to bypass VM memory encryption by executing conveniently chosen gadgets. Secondly, the general purpose registers are not encrypted upon vmexit, leaking potentially sensitive data. Finally, the control over the nested pagetables allows a malicious hypervisor to closely monitor the execution state of a VM and attack it with memory replay attacks.
Parallel Automata Processor
Authors: Subramaniyan Arun , Das Reetuparna 
Published: September 2017

Finite State Machines (FSM) are widely used computation models for many application domains. These embarrassingly sequential applications with irregular memory access patterns perform poorly on conventional von-Neumann architectures. The Micron Automata Processor (AP) is an in-situ memory-based computational architecture that accelerates non-deterministic finite automata (NFA) processing in hardware. However, each FSM on the AP is processed sequentially, limiting potential speedups.
In this paper, we explore the FSM parallelization problem in the context of the AP. Extending classical parallelization techniques to NFAs executing on AP is non-trivial because of high state-transition tracking overheads and exponential computation complexity. We present the associated challenges and propose solutions that leverage both the unique properties of the NFAs (connected components, input symbol ranges, convergence, common parent states) and unique features in the AP (support for simultaneous transitions, low-overhead flow switching, state vector cache) to realize parallel NFA execution on the AP.
We evaluate our techniques against several important benchmarks including NFAs used for network intrusion detection, malware detection, text processing, protein motif searching, DNA sequencing, and data analytics. Our proposed parallelization scheme demonstrates significant speedup (25.5x on average) compared to sequential execution on AP. Prior work has already shown that sequential execution on AP is at least an order of magnitude better than GPUs, multi-core processors and Xeon Phi accelerator.
Redundant Memory Array Architecture for Efficient Selective Protection
Authors: Zheng Ruohuang , Huang Michael C. 
Published: September 2017

Memory hardware errors may result from transient particle-induced faults as well as device defects due to aging. These errors are an important threat to computer system reliability as VLSI technologies continue to scale. Managing memory hardware errors is a critical component in developing an overall system dependability strategy. Memory error detection and correction are supported in a range of available hardware mechanisms. However, memory protections (particularly the more advanced ones) come at substantial costs in performance and energy usage. Moreover, the protection mechanisms are often a fixed, system-wide choice and can not easily adapt to different protection demand of different applications or memory regions.
In this paper, we present a new RAIM (redundant array of independent memory) design that compared to the state-of-the-art implementation can easily provide high protection capability and the ability to selectively protect a subset of the memory. A straightforward implementation of the design can incur a substantial memory traffic overhead. We propose a few practical optimizations to mitigate this overhead. With these optimizations the proposed RAIM design offers significant advantages over existing RAIM design at lower or comparable costs.
PowerChief
Authors: Yang Hailong , Chen Quan , Riaz Moeiz , Luan Zhongzhi , Tang Lingjia , Mars Jason 
Published: September 2017

Modern user facing applications consist of multiple processing stages with a number of service instances in each stage. The latency profile of these multi-stage applications is intrinsically variable, making it challenging to provide satisfactory responsiveness. Given a limited power budget, improving the end-to-end latency requires intelligently boosting the bottleneck service across stages using multiple boosting techniques. However, prior work fail to acknowledge the multi-stage nature of user-facing applications and perform poorly in improving responsiveness on power constrained CMP, as they are unable to accurately identify bottleneck service and apply the boosting techniques adaptively.
In this paper, we present PowerChief, a runtime framework that 1) provides joint design of service and query to monitor the latency statistics across service stages and accurately identifies the bottleneck service during runtime; 2) adaptively chooses the boosting technique to accelerate the bottleneck service with improved responsiveness; 3) dynamically reallocates the constrained power budget across service stages to accommodate the chosen boosting technique. Evaluated with real world multi-stage applications, PowerChief improves the average latency by 20.3x and 32.4x (99% tail latency by 13.3x and 19.4x) for Sirius and Natural Language Processing applications respectively compared to stage-agnostic power allocation. In addition, for the given QoS target, PowerChief reduces the power consumption of Sirius and Web Search applications by 23% and 33% respectively over prior work.
Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware
Authors: Li Zhaoshi , Liu Leibo , Deng Yangdong , Yin Shouyi , Wang Yao , Wei Shaojun 
Published: September 2017

CPU-FPGA heterogeneous platforms offer a promising solution for high-performance and energy-efficient computing systems by providing specialized accelerators with post-silicon reconfigurability. To unleash the power of FPGA, however, the programmability gap has to be filled so that applications specified in high-level programming languages can be efficiently mapped and scheduled on FPGA. The above problem is even more challenging for irregular applications, in which the execution dependency can only be determined at run time. Thus over-serialized accelerators are generated from existing works that rely on compile time analysis to schedule the computation.
In this work, we propose a comprehensive software-hardware co-design framework, which captures parallelism in irregular applications and aggressively schedules pipelined execution on reconfigurable platform. Based on an inherently parallel abstraction packaging parallelism for runtime schedule, our framework significantly differs from existing works that tend to schedule executions at compile time. An irregular application is formulated as a set of tasks with their dependencies specified as rules describing the conditions under which a subset of tasks can be executed concurrently. Then datapaths on FPGA will be generated by transforming applications in the formulation into task pipelines orchestrated by evaluating rules at runtime, which could exploit fine-grained pipeline parallelism as handcrafted accelerators do.
An evaluation shows that this framework is able to produce datapath with its quality close to handcrafted designs. Experiments show that generated accelerators are dramatically more efficient than those created by current high-level synthesis tools. Meanwhile, accelerators generated for a set of irregular applications attain 0.5x~1.9x performance compared to equivalent software implementations we selected on a server-grade 10-core processor, with the memory subsystem remaining as the bottleneck.
ShortCut
Authors: Choi Jiho , Shull Thomas , Garzaran Maria J. , Torrellas Josep 
Published: September 2017

The same flexibility that makes dynamic scripting languages appealing to programmers is also the primary cause of their low performance. To access objects of potentially different types, the compiler creates a dispatcher with a series of if statements, each performing a comparison to a type and a jump to a handler. This induces major overhead in instructions executed and branches mispredicted.
This paper proposes architectural support to significantly improve the efficiency of accesses to objects. The idea is to modify the instruction that calls the dispatcher so that, under most conditions, it skips most of the branches and instructions needed to reach the correct handler, and sometimes even the execution of the handler itself. Our novel architecture, called ShortCut, performs two levels of optimization. Its Plain design transforms the call to the dispatcher into a call to the correct handler --- bypassing the whole dispatcher execution. Its Aggressive design transforms the call to the dispatcher into a simple load or store --- bypassing the execution of both dispatcher and handler. We implement the ShortCut software in the state-of-the-art Google V8 JIT compiler, and the ShortCut hardware in a simulator. We evaluate ShortCut with the Octane and SunSpider JavaScript application suites. Plain ShortCut reduces the average execution time of the applications by 30% running under the baseline compiler, and by 11% running under the maximum level of compiler optimization. Aggressive ShortCut performs only slightly better.
Clank
Authors: Hicks Matthew 
Published: September 2017

The processors that drive embedded systems are getting smaller; meanwhile, the batteries used to provide power to those systems have stagnated. If we are to realize the dream of ubiquitous computing promised by the Internet of Things, processors must shed large, heavy, expensive, and high maintenance batteries and, instead, harvest energy from their environment. One challenge with this transition is that harvested energy is insufficient for continuous operation. Unfortunately, existing programs fail miserably when executed intermittently.
This paper presents Clank: lightweight architectural support for correct and efficient execution of long-running applications on harvested energy---without programmer intervention or extreme hardware modifications. Clank is a set of hardware buffers and memory-access monitors that dynamically maintain idempotency. Essentially, Clank dynamically decomposes program execution into a stream of restartable sub-executions connected via lightweight checkpoints.
To validate Clank's ability to correctly stretch program execution across frequent, random power cycles, and to explore the associated hardware and software overheads, we implement Clank in Verilog, formally verify it, and then add it to an ARM Cortex M0+ processor which we use to run a set of 23 embedded systems benchmarks. Experiments show run-time overheads as low as 2.5%, with run-time overheads of 6% for a version of Clank that adds 1.7% hardware. Clank minimizes checkpoints so much that re-execution time becomes the dominate contributor to run-time overhead.
DICE
Authors: Young Vinson , Nair Prashant J. , Qureshi Moinuddin K. 
Published: September 2017

This paper investigates compression for DRAM caches. As the capacity of DRAM cache is typically large, prior techniques on cache compression, which solely focus on improving cache capacity, provide only a marginal benefit. We show that more performance benefit can be obtained if the compression of the DRAM cache is tailored to provide higher bandwidth. If a DRAM cache can provide two compressed lines in a single access, and both lines are useful, the effective bandwidth of the DRAM cache would double. Unfortunately, it is not straight-forward to compress DRAM caches for bandwidth. The typically used Traditional Set Indexing (TSI) maps consecutive lines to consecutive sets, so the multiple compressed lines obtained from the set are from spatially distant locations and unlikely to be used within a short period of each other. We can change the indexing of the cache to place consecutive lines in the same set to improve bandwidth; however, when the data is incompressible, such spatial indexing reduces effective capacity and causes significant slowdown.
Ideally, we would like to have spatial indexing when the data is compressible and TSI otherwise. To this end, we propose Dynamic-Indexing Cache comprEssion (DICE), a dynamic design that can adapt between spatial indexing and TSI, depending on the compressibility of the data. We also propose low-cost Cache Index Predictors (CIP) that can accurately predict the cache indexing scheme on access in order to avoid probing both indices for retrieving a given cache line. Our studies with a 1GB DRAM cache, on a wide range of workloads (including SPEC and Graph), show that DICE improves performance by 19.0% and reduces energy-delay-product by 36% on average. DICE is within 3% of a design that has double the capacity and double the bandwidth. DICE incurs a storage overhead of less than 1KB and does not rely on any OS support.
Effect of increases in cardiac contractility on cerebral blood flow in humans
Authors: Ogoh Shigehiko , Moralez Gilbert , Washio Takuro , Sarma Satyam , Hieda Michinari , Romero Steven A. , Cramer Matthew N. , Shibasaki Manabu , Crandall Craig G. 
Published: September 2017

The effect of acute increases in cardiac contractility on cerebral blood flow (CBF) remains unknown. We hypothesized that the external carotid artery (ECA) downstream vasculature modifies the direct influence of acute increases in heart rate and cardiac function on CBF regulation. Twelve healthy subjects received two infusions of dobutamine [first a low dose (5 μg·kg−1·min−1) and then a high dose (15 μg·kg−1·min−1)] for 12 min each. Cardiac output, blood flow through the internal carotid artery (ICA) and ECA, and echocardiographic measurements were performed during dobutamine infusions. Despite increases in cardiac contractility, cardiac output, and arterial pressure with dobutamine, ICA blood flow and conductance slightly decreased from resting baseline during both low- and high-dose infusions. In contrast, ECA blood flow and conductance increased appreciably during both low- and high-dose infusions. Greater ECA vascular conductance and corresponding increases in blood flow may protect overperfusion of intracranial cerebral arteries during enhanced cardiac contractility and associated increases in cardiac output and perfusion pressure. Importantly, these findings suggest that the acute increase of blood perfusion attributable to dobutamine administration does not cause cerebral overperfusion or an associated risk of cerebral vascular damage. NEW & NOTEWORTHY A dobutamine-induced increase in cardiac contractility did not increase internal carotid artery blood flow despite an increase in cardiac output and arterial blood pressure. In contrast, external carotid artery blood flow and conductance increased. This external cerebral blood flow response may assist with protecting from overperfusion of intracranial blood flow.
Small RNA-seq during acute maximal exercise reveal RNAs involved in vascular inflammation and cardiometabolic health: brief report
Authors: Shah Ravi , Yeri Ashish , Das Avash , Courtright-Lim Amanda , Ziegler Olivia , Gervino Ernest , Ocel Jeffrey , Quintero- Pinzon Pablo , Wooster Luke , Bailey Cole Shields , Tanriverdi Kahraman , Beaulieu Lea M. , Freedman Jane E. , Ghiran Ionita , Lewis Gregory D. , Van Keuren-Jensen Kendall , Das Saumya 
Published: September 2017

Exercise improves cardiometabolic and vascular function, although the mechanisms remain unclear. Our objective was to demonstrate the diversity of circulating extracellular RNA (ex-RNA) release during acute exercise in humans and its relevance to exercise-mediated benefits on vascular inflammation. We performed plasma small RNA sequencing in 26 individuals undergoing symptom-limited maximal treadmill exercise, with replication of our top candidate miRNA in a separate cohort of 59 individuals undergoing bicycle ergometry. We found changes in miRNAs and other ex-RNAs with exercise (e.g., Y RNAs and tRNAs) implicated in cardiovascular disease. In two independent cohorts of acute maximal exercise, we identified miR-181b-5p as a key ex-RNA increased in plasma after exercise, with validation in a separate cohort. In a mouse model of acute exercise, we found significant increases in miR-181b-5p expression in skeletal muscle after acute exercise in young (but not older) mice. Previous work revealed a strong role for miR-181b-5p in vascular inflammation in obesity, insulin resistance, sepsis, and cardiovascular disease. We conclude that circulating ex-RNAs were altered in plasma after acute exercise target pathways involved in inflammation, including miR-181b-5p. Further investigation into the role of known (e.g., miRNA) and novel (e.g., Y RNAs) RNAs is warranted to uncover new mechanisms of vascular inflammation on exercise-mediated benefits on health. NEW & NOTEWORTHY How exercise provides benefits to cardiometabolic health remains unclear. We performed RNA sequencing in plasma during exercise to identify the landscape of small noncoding circulating transcriptional changes. Our results suggest a link between inflammation and exercise, providing rich data on circulating noncoding RNAs for future studies by the scientific community.
Downregulation of SAFB Sustains the NF-κB Pathway by Targeting TAK1 during the Progression of Colorectal Cancer
Authors: Jiao Hong-Li , Ye Ya-Ping , Yang Run-Wei , Sun Hui-Ying , Wang Shu-Yang , Wang Yong-Xia , Xiao Zhi-Yuan , He Liu-Qing , Cai Juan-Juan , Wei Wen-Ting , Chen Yan-Ru , Gu Chun-Cai , Cai Yue-Long , Hu Yun-Teng , Lai Qiu-Hua , Qiu Jun-Feng , Liang Li , Cao Guang-Wen , Liao Wen-Ting , Ding Yan-Qing 
Published: September 2017

Abstract
Purpose: To investigate the role and the underlying mechanism of scaffold attachment factor B (SAFB) in the progression of colorectal cancer (CRC).
Experimental Design: SAFB expression was analyzed in the Cancer Outlier Profile Analysis of Oncomine and in 175 paraffin-embedded archived CRC tissues. Gene Ontology analyses were performed to explore the mechanism of SAFB in CRC progression. Western blot, RT-PCR, luciferase assay, and chromatin immunoprecipitation (ChIP) were used to detect the regulation of transforming growth factor-β–activated kinase 1 (TAK1) and NF-κB signaling by SAFB. The role of SAFB in invasion, metastasis, and angiogenesis was investigated using in vitro and in vivo assays. The relationship between SAFB and TAK1 was analyzed in CRC tissues.
Results: SAFB was downregulated in CRC tissues, and low expression of SAFB was significantly associated with an aggressive phenotype and poorer survival of CRC patients. The downregulation of SAFB activated NF-κB signaling by targeting the TAK1 promoter. Ectopic expression of SAFB inhibited the development of aggressive features and metastasis of CRC cells both in vitro and in vivo. The overexpression of TAK1 could rescue the aggressive features in SAFB-overexpressed cells. Furthermore, the expression of SAFB in CRC tissues was negatively correlated with the expression of TAK1- and NF-κB–related genes.
Conclusions: Our results show that SAFB regulated the activity of NF-κB signaling in CRC by targeting TAK1. This novel mechanism provides a comprehensive understanding of both SAFB and the NF-κB signaling pathway in the progression of CRC and indicates that the SAFB–TAK1–NF-κB axis is a potential target for early therapeutic intervention in CRC progression. Clin Cancer Res; 23(22); 7108–18. ©2017 AACR.