bluuebunny/crossref_metadata_2025_split huggingface dataset:
Development of BiAgX® HT Solder Paste for 200°C Application
Authors: Zhang Hongwen , Minter Jonathan , Lee Ning-Cheng 
Published: May 2016

Abstract
BiAgX® paste with the remelting temperature around 262°C has been tested and adopted successfully for die attach applications [1–5]. BiAgX® HT pastes with the enhanced remelting temperature above 265°C have been designed for the application of 200°C or even higher. The joint strength has been well maintained for most of the tested pastes after thermal aging @ 200°C for 1000hrs. The thermal cycling test (from −55°C to 200°C) degrades the bond shear strength but some of the tested pastes can still keep the joint strength well above IEC standard (IEC 60749-19) required. The melting temperature and the reliability have been observed to closely associate with the alloying elements Z%wt. The BiAgX® pastes have also been modified for board level assembly application. BiAgX® solder wire is under development too.
Silver Sintering Paste Rendering Low Porosity Joint for High Power Die Attach Application
Authors: Chen Sihai , LaBarbera Christine , Lee Ning-Cheng 
Published: May 2016

Abstract
Silver joints with ~10% porosity for die-attach have been achieved with specially engineered Ag sintering pastes, through combined pressureless sintering process plus thermal aging. The pastes developed in this work have the following advantages: 1) they can be used under pressure-less processing condition; 2) they are compatible with conventional reflow oven, resulting in a higher through-put as compared to that of stepwise heating oven; 3) they can be used under air reflow condition; 4) a highly reliable joint has been obtained as judged from the shear strength results from thermal aging and temperature cycling tests.
The silver sintering pastes are versatile in bonding different metallization surface including Au, Ag and Cu. It can also be used in bonding large area (10mm × 10mm) dies. Shear test results under varied temperatures implied that the maximum service temperature of Ag sintered joints can be as high as 470 – 530 °C, depending on the shear strength pass criteria, and this is more than 250°C higher than that of high-Pb joints.
Thermal aging test at 250°C for the joints generated on Ag-die/Au-DBC combination revealed that Ag continuously consolidates in the bulk phase resulting in the formation of larger pores with reduced numbers as compared to that of untreated samples. At the same time, it diffuses to sintered Ag/Au-DBC interface to form a dense Ag layer induced by alloying with Ni(Au) and Cu, which strengthened the bonding. A large bondline thickness is critical for obtaining highly reliable joints. The total porosity of the joint is found slightly decreased during the course of 3200h aging test. Temperature cycling at −55 °C to 200°C shows that the silver joints are stable for at least 1000 cycles.
Increased High-Temperature IC Packaging Reliability Using Die Extraction and Additive Manufacturing Assembly
Authors: Spory Erick M. 
Published: May 2016

Abstract
Semiconductor parts are most often specified for use in the “commercial” 0 to 70°C and, to a lesser extent, in the “industrial” −40 to 85°C operating temperature range. These operating temperature ratings generally satisfy the demands of the dominant semiconductor customers in the computer, telecommunications, and consumer electronic industries. There is also a demand for parts rated beyond the “industrial” temperature range, primarily from the aerospace, military, oil and gas exploration, and automotive industries (−55 to +125C, and even higher). However, the demand has not been large enough to attract or retain the interest of major semiconductor part manufacturers to make these parts. In fact, wide temperature range parts are becoming obsolete and functionally equivalent parts are not replacing them.
Today, for some applications, it is difficult to procure parts that meet engineering, economic, logistical, and technical integration requirements of product manufacturers, and that are rated for an extended temperature range (typically beyond 0 to 70°C). In some applications, the product is available only in the “commercial” temperature range, with commercial packaging. If the product application environment is outside the commercial range, steps must be taken to address this apparent incompatibility. For example, oil exploration and drilling applications require small, advanced communication electronics to work underground at high temperatures where cooling is not possible. This is where uprating comes into play.
Despite the fact that a part can be uprated relative to functional performance at higher than specified temperatures, the original packaging and connectivity may not be reliable with long term exposure to greater than 150C due to Kirkendall voiding and general plastic degradation. However, if the original die with gold wire and aluminum pad bond is extracted from the original plastic commercial package and reassembled into a new ceramic package body, excellent reliability at temperatures exceeding 200C can be achieved. The original gold/aluminum bond interface can be removed and replaced with an electroless nickel, electroless palladium, immersion gold (ENEPIG) process, or a much more economical, automated process can be used. This process is discussed in the accompanying paper and utilizes additive manufacturing to place an aerosol jet silver deposition over the existing gold ball, interfacing with the remaining exposed aluminum. In this manner, a high-reliability connection system can be achieved which is immune to Kirkendall voiding for the temperature range of interest.
Development of a High Temperature Interconnect Solution as an Alternative to High Lead or Gold Content Solders
Authors: Wickham Martin , Clayton Kate , Robador Ana , Hunt Chris , Pittson Robin , Statton Laura , Brown Tina , Lambert Fiona , Wotherspoon Tracy 
Published: May 2016

AbstractA collaborative research programme between project partners Microsemi, the National Physical Laboratory (NPL) and Gwent Electronic Materials (GEM), has successfully developed innovative materials specifically designed to offer an alternative for high Pb or Au content materials to increase the operating temperature of electronic assemblies. Currently, for electronic assemblies to operate at high temperature, they must use a high lead solder or a very expensive gold based solder to withstand these temperatures. The ELCOSINT project has developed an inexpensive lead-free alternative for joining high temperature electronics suitable for operating at temperatures above 250°C utilising standard surface mount assembly processes. This paper summarises the work undertaken by the authors to develop and better understand this new family of electrical interconnection materials. The project brought together a materials supplier (GEM – Gwent Electronic Materials), an end-user (MSL - Microsemi) and an technology research organisation (NPL – National Physical Laboratory) to jointly develop, test and implement in production, the solution based on silver-loaded silicone materials. This paper focuses on the testing and materials evaluation undertaken at NPL to determine the long term performance of these alternative materials including high temperature ageing up to 300°C, thermal cycling and damp heat testing. Details of the shear strength and electrical performance of interconnects between the substrates and components during the test regimes are given. The manufacturing process is outlined including details of the test vehicles utilised. The processing temperature for the conductive adhesive is 250°C which offers additional advantages in potential improvements in component and substrate reliability compared to soldered solutions which would typically be processed at temperatures above 300°C.
Method to Determine Maximum Allowable Sinterable Silver Interconnect Size
Authors: Wereszczak A. A. , Modugno M. C. , Waters S. B. , DeVoto D. J. , Paret P. P. 
Published: May 2016

Abstract
The use of sintered-silver for large-area interconnection is attractive for some large-area bonding applications in power electronics such as the bonding of metal-clad, electrically-insulating substrates to heat sinks. Arrays of different pad sizes and pad shapes have been considered for such large area bonding; however, rather than arbitrarily choosing their size, it is desirable to use the largest size possible where the onset of interconnect delamination does not occur. If that is achieved, then sintered-silver's high thermal and electrical conductivities can be fully taken advantage of. Toward achieving this, a simple and inexpensive proof test is described to identify the largest achievable interconnect size with sinterable silver. The method's objective is to purposely initiate failure or delamination. Copper and invar (a ferrous-nickel alloy whose coefficient of thermal expansion (CTE) is similar to that of silicon or silicon carbide) disks were used in this study and sinterable silver was used to bond them. As a consequence of the method's execution, delamination occurred in some samples during cooling from the 250°C sintering temperature to room temperature and bonding temperature and from thermal cycling in others. These occurrences and their interpretations highlight the method's utility, and the herein described results are used to speculate how sintered-silver bonding will work with other material combinations.
Towards High Temperature Electronic Modules in which all Components would be attached using Silver Sintering
Authors: GEOFFROY Thomas , RIOU Jean-Christophe , BIENVENU Yves , PONS Corinne , MEILLE Sylvain , BAILLY Eric 
Published: May 2016

Abstract
This article points out the fact that conventional low temperature silver sintering processes do not seem to satisfy the needs for reliability when they are used to assemble passive components (such as multilayers ceramic capacitors) in electronic modules undergoing wide amplitude thermal cycles (−65°C / +200°C). These processes indeed lead to very porous microstructures of silver which favors rapid fatigue cracks propagation [1], [2], [3]. Even if these types of porous microstructures may be suitable for die attach, tests presented in this paper show they cannot resist to the levels of thermomechanical stress reached in attachment joints of multilayers ceramic capacitors (MLCCs). To find process parameters minimizing porosity in attachment joints of capacitors, measurements of the shrinkage of silver during sintering have been carried out by dilatometry. Then the impact of densification of attachment joints on the ageing behavior and on the mechanical behavior of assemblies has been assessed in this study.
Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits
Authors: Spry David J. , Neudeck Philip G. , Chen Liang-Yu , Lukco Dorothy , Chang Carl W. , Beheim Glenn M. , Krasowski Michael J. , Prokop Norman F. 
Published: May 2016

Abstract
This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over ~ 1-μm scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 °C operational testing. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.
First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits
Authors: Neudeck Philip G. , Spry David J. , Chen Liang-Yu 
Published: May 2016

Abstract
A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 °C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 °C to 500 °C SPICE simulation models of first-order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.
C0G and X7R Ceramic Capacitors for High Temperature Applications
Authors: Gurav Abhijit , Magee Jim , Phillips Reggie , Carson Scott 
Published: May 2016

Abstract
For applications such as electronics for down-hole drilling and exploration, geothermal energy generation and power electronics, there is a growing need for capacitors that have robust reliability at temperatures of 150°C or above. Conventional X7R and X8R type ceramic capacitors are designed for applications up to 125°C and 150°C, respectively. At temperatures above 150°C, these types of capacitors typically suffer from degradation of reliability performance and severe reduction in capacitance, especially under DC bias conditions. A Class-I C0G dielectric has been developed using Nickel electrodes for high temperature application up to 200°C and beyond. Due to its linear dielectric nature, this material exhibits highly stable capacitance as a function of temperature and voltage. Multi-layer ceramic capacitors (MLCC) made from this material can be qualified as X9G with robust reliability. These C0G capacitors are showing robust reliability at extreme temperature of 260°C (500 degrees Fahrenheit). We have also developed a modified-X7R dielectric composition with nickel internal electrodes showing high reliability in this Class-II dielectric at 175°C. This paper will report electrical properties and reliability test data on these Class-I C0G and Class-II ceramic capacitors at high temperatures of 150–200°C and above.
High temperature / radiation hardened capable ARM® Cortex®-M0 microcontrollers
Authors: Bannatyne R. , Gifford D. , Klein K. , Merritt C. 
Published: May 2016

Abstract
VORAGO Technologies has developed a pair of ARM Cortex M0 MCUs designed from the ground up to be high temperature capable. One of these devices is specifically developed for high temperature applications, the other adds capabilities that make it suitable for use in high radiation environments as well. These devices are fabricated using a modified version of commercial bulk 130nm CMOS technology utilizing our HARDSIL® technology, which provides immunity to the increased effects of latchup and EOS encountered at higher application temperatures. In addition to the processor these devices include features more typical of low temperature SoCs including on-chip memory, timers, and communications peripherals. In addition to the ceramic package and die format typically utilized at high temperature, a new lower-cost plastic package is available that has been characterized at higher temperatures. These devices have been characterized at temperatures up to 200C and results showing the latchup behavior and device performance are provided. Some of the tradeoffs involved in creating such devices are discussed, as well as some of the similarities and tradeoffs in creating a radiation hardened devices vs. a high temperature device.
High Temperature Potting Materials for Wire Bond Encapsulation
Authors: Shaddock David , Yin Liang 
Published: May 2016

Abstract
Test results for a range of potting materials for encapsulation of wire bonds for a high temperature multi-chip module is presented. The potting materials include gels and more rigid epoxies, silicone, and silicone-ceramic materials. The materials were initially screened based on ease of processing, cracking, and weight loss at 200, 225, and 250°C. Materials that performed well after this initial screening were tested for insulation resistance at 200, 225, and 250°C and wire bonds were encapsulated for thermal cycled at −55 to 200°C and −55 to 250°C.
Encapsulation Method for Small Wireless Measurement Systems in High Temperature Environments
Authors: Johansson J. , Borg J. 
Published: May 2016

Abstract
This paper presents an encapsulation concept that enables the construction of small wireless measurement systems that can operate in industrial environments with ambient temperatures of up to 1200°C. To maximize operational time and minimize size, a layer of thermal insulation is combined with water absorbed in a porous material in the core of the device. The simulated operating time before all of the frozen water at 0°C has transformed into steam at 100°C when the ambient temperature of the device was 1200°C is 21 minutes for a sphere with an outer radius of 4 cm. If the outer radius is increased to 10 cm the simulated operating time increases to 125 minutes. Measurements were performed to validate the design. When a sphere with a radius of 4 cm was subjected to an oven temperature of 1200°C the device held the core temperature at or below 101°C for a total of 25 minutes. The time to reach the boiling point of the water was 9 minutes. Thereafter, the temperature was held constant at 100 +/− 1°C for an additional 16 minutes whereafter a rapid rise in temperature took place once all water had evaporated.
Anaesthetic management of vein of Galen malformation in a very low birth weight preterm baby for endovascular embolisation
Authors: Ramakrishnan Rajani , Goraksha Shwetal , Thakore Bhoomika , Monteiro Joseph , Butani Manju 
Published: May 2016

AbstractExtra-cardiac arteriovenous malformations are rare causes of severe cardiac failure in the neonatal period. Aneurysmal malformation of the vein of Galen may lead to a diagnostic confusion because the presenting signs point to a cardiac cause of failure. Endovascular therapy is found to be an effective and safe therapeutic modality available to treat these lesions. Intervention in the newborn is difficult and is preferably postponed until about 5 months. We present the anaesthetic management of a very low birth weight preterm neonate with a vein of Galen malformation who needed intervention within the first week of life.
An unusual case of osmotic demyelination syndrome without electrolyte changes in a patient with diabetes
Authors: Kote Shrikant , Khandelwal Ankur , Pathak Deba , Nath Rupankar 
Published: May 2016

AbstractCentral pontine myelinolysis (CPM) is a demyelinating disease of the pons which is also associated with the demyelination of extrapontine areas of the central nervous system. Although the aetiology and pathogenesis are unclear, CPM is usually associated with hyponatremia or its rapid correction. Malnutrition and chronic alcoholism are also the common underlying conditions. Herein, we report a rare presentation of ODS, secondary to hyperosmolar hyperglycaemic state. We observed a 37-year-old female with diabetes type 1 and hypertension who presented with ataxia, dysarthria and pseudobulbar effect which evolved over a duration of few weeks at home with no evidence of hyponatremia or its rapid correction and no history of alcohol abuse or malnutrition.
Anaesthetic management and perioperative complications during deep brain stimulation surgery: Our institutional experience
Authors: Bala Renu , Chaturvedi Arvind , Pandia Mihir , Bithal Parmod 
Published: May 2016

Abstract
Background: Deep brain stimulation (DBS) surgery is an established therapeutic option for alleviating movement disorders. It represents unique challenges for anaesthesiologists. We retrospectively reviewed the patients, who underwent this surgery at our institution, to study anaesthetic management and perioperative complications. Materials and Methods: After taking approval from the Institutional Ethics Committee, medical, surgical and anaesthesia records of 67 patients who were admitted to undergo DBS surgery during 11 years period (January 2001 to December 2011) were retrieved and reviewed. Sixty-five patients underwent the procedure. Various anaesthetic events and perioperative complications were noted and appropriate statistical analysis was carried out to analyse the data. Results: Electrode placement under monitored anaesthesia care (MAC) was the most commonly used technique (86% of patients). Intra-operative complications occurred in 16 patients (24%) whereas post-operative complication occurred in 10 patients (15.4%). There was one mortality. Though age >60 years and American Society of Anesthesiologists status >II were found to be the risk factors for post-operative complications in the bivariate analysis; they were not significant in multivariate analysis. Conclusions: We report our experience of DBS surgery, which was performed using MAC in majority of patients, though general anaesthesia is also feasible. Further prospective randomised studies comprising large number of patients are warranted to corroborate our finding and to find out the most suitable sedative agent.
Intensive care management of status epilepticus
Authors: Gupta Nidhi 
Published: May 2016

AbstractStatus epilepticus (SE) is a life-threatening neurological emergency that requires prompt diagnosis and treatment. SE may be classified into convulsive and non-convulsive types, based on the presence of rhythmic jerking of the extremities. Clinically, tonic-clonic convulsive SE (CSE) is divided into four subsequent stages: Early, established, refractory and super-refractory. Initial elements of resuscitation include airway protection, haemodynamic resuscitation and seizure control. Further treatment should then be guided by the diagnostic workup. Rapid treatment of early SE is achieved with intravenous (IV) lorazepam or intramuscular midazolam. In established SE, IV antiepileptic drugs (AEDs) (phenytoin/fosphenytoin, valproate, levetiracetam, phenobarbital) are most commonly used, but there is no Class I evidence for choosing one over the other. Considered overall, cumulative data from the literature are consistent with valproate and levetiracetam, being a safe and effective therapeutic alternative to phenobarbital and phenytoin for treatment of established SE. Refractory SE (RSE) and super-RSE are treated with anaesthetic medications (propofol, midazolam, thiopental/pentobarbital, ketamine), non-anaesthetic drugs (lidocaine, magnesium, pyridoxine), AEDs (levetiracetam, lacosamide, topiramate, lacosamide, pregabalin, gabapentin) and other cause-directed treatments with low success rates. Potential non-pharmacologic interventions to be considered in super-RSE include hypothermia, electroconvulsive therapy, ketogenic diet, immunomodulatory treatments, emergency resective epilepsy surgery, cerebrospinal fluid drainage and vagal nerve or deep brain stimulation or transcranial magnetic stimulation. Diagnosis of non-CSE requires continuous electroencephalography and involves a high index of suspicion in all patients with an altered mental status of unclear cause or with a prolonged postictal state. Treatment options include addressing underlying causes and aggressive pharmacologic interventions with a benzodiazepine, phenytoin and valproate.