System level IC packaging - Integration of Key Technologies: TSVs, Interposers, and Advanced IC Packaging
Authors: Kelly Mike , Hiner Dave , Mattei Marnie , Reed Rick , Silvestri Paul , Huemoeller Ron 
Published: April 2016

New system level IC package integration requires a flexible assembly portfolio. A review of current wafer scale processing and assembly solutions and new development directions is warranted.
2.5D TSV
System level IC packaging is not new, but the performance levels that are being attained today with memory stacking, interposers, advanced silicon nodes and advanced packaging are new and are unparalleled. Several key technologies have come together to create this bold shift to higher performance. The Thru-Silicon Via (TSV) technology has been foremost, whether in the interposer, memory or logic devices, the importance of the this electrical pass through connection in silicon cannot be overstated. To commercialize the TSV package constructions, IC packaging technology had to be developed to permit its use. This included TSV reveal on TSV-bearing interposers, new ways of controlling warpage due to the presence of large x-y interposers, new functional IC bumping technologies and attachment methods. This portfolio of advanced technologies are then combined to provide package constructions that are increasingly compelling as a result of the higher electrical performance attained, while at the same time minimizing unwanted die to die interface power requirements.
2.5D TSV bearing products have enabled an array of multi-die products and have a significant role to play in the semiconductor industry going forward. Examples include new economics for SOC-splitting, and especially for combinations of logic and high speed memory (HBM), with performance levels heretofore unachievable. With fine line damascene Cu Back End of Line (BEOL) typical of a 65nm Cu backend, the signal routing resources available for multi-die implementation is unparalleled. Functionally, the TSV is required to provide a suitable power deliver network (PDN), and to enable off-package IO signaling.
3D TSV
The COS Chip last is a proven approach for 2.5D TSV packages and is already in early production. This process flow is also being developed for 3D packages applications as well.
New technologies being developed for 3D applications include new UF processing technologies that will be used to extend this technology to a 2-die stack with the same die size top and bottom, as well as 50 um large die silicon handling. These will include logic on logic combinations and memory on logic configurations, as well as stacked memory offerings.
SLIMTM
Amkor's most advanced integrated modular based package development program is for SLIMTM (Silicon-Less Integrated Module). The roots of SLIM innovation were forged during the 2.5D TSV-bearing interposer package development. SLIMTM attempts to retain all the best features of a 2.5D TSV interposer approach, but without bulk silicon for TSVs.
The objective of SLIM is to retain the very strong signal routing capability afforded by the damascene BEOL, and provide that benefit without the requirement for a TSV. This can enable a lower total cost than the 2.5D interposers, and some specific electrical performance improvements as well. The primary mechanical feature of the SLIMTM construction is the lack of TSVs. For SLIM, the TSV is not in the electrical path from the top die to the C4, providing electrical benefits. In the case of SLIM the bulk silicon has been removed from the interposer, so that only the thin-film metal and dielectric layers present in the BEOL construction are retained. Connection to the BEOL metal stack is made directly using thin film techniques developed for 2.5D TSV.
The end result is a very thin package, with signal routing resources on par with the 2.5D interposer, and without bulk silicon or a TSV. This can have electrical signaling advantage, especially for very high speed IO off package signals which avoid bulk silicon dielectric losses that can be significant above 20 Gigabit/sec. The process flow developed for SLIM is essentially a truncated version of the 2.5D production line. Key steps not required are CVD deposition of inorganic dielectrics and CMP processing.
In summary, the final system package construction can be derived with different process approaches as previously discussed, each with their own particular benefits. Amkor continues in its commitment to the development of these critical process modules to enable customers to achieve their ultimate system-in-module product designs.