bluuebunny/crossref_metadata_2025_split huggingface dataset:
Effect of Aspect Ratio and Flow Rate on the Flow Regimes and Thermal Performance of Two-Phase Micro-Channel Cold Plates for Direct to Chip Cooling
Authors: Shah Yousaf , Ortega Alfonso , Mehrabi-kermani Mehdi , Martinez Victor A. , Manaserh Yaman , Heydari Ali , Rodriguez Jeremy 
Published: November 2024

Abstract
Liquid cooling technology is experiencing rapid acceptance in high-speed computing and data centers, driven by the remarkable advancements in these sectors that have resulted in unprecedented increase in thermal loads that are anticipated to surpass the capabilities of single-phase liquid cooling. Two-phase direct to chip cooling is a promising alternative for managing these high loads. The majority of the literature has investigated thermal performance enhancement in two-phase cooling utilizing small scale microchannel structures suitable for fundamental studies. For actual deployment of the two-phase liquid cooling technology, it is of practical importance to understand flow and cooling in full-scale devices. This paper will present an experimental study on the thermal performance of full-scale microchannel cold plates, employing thermal test vehicles (TTV) as the heat source to simulate the heat generation rates in practical applications. The study focuses on characterizing a single cold plate, but the work is part of a larger study simulating data center thermal loads in rack level experiments employing multiple rack level thermal test vehicles in a rack with distribution manifolds feeding each server TTV. Simulated cold plates, suitable for fundamental laboratory studies, were used in this study. The cold plates had skived fins on a copper base, with suitable inlet and outlet manifolds. The lid was made of transparent acrylic to allow for flow visualization from the top of the fins. The cold plate had a base area of 50 by 50 mm with rectangular channels having a fixed height of 4 mm, identical channel width and fin-pitch of 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, and channel length of 50 mm. Tests were conducted in steady state conditions using R-134a as the working fluid. Flow rate varied between 1.2 to 3.5 LPM and the fluid inlet temperature was maintained at 17° C. The effect of fin-pitch and the liquid flow rate on the thermal performance was evaluated by measuring base temperature for applied power up to 3200 W. Flow regimes and flow instability were investigated utilizing high-speed high-resolution video flow visualization showing the effects of mass flux and heat flux on the flow and heat transfer at different aspect ratios. The effect of fin aspect ratio, heat flux, and mass flux on the flow regimes, instabilities, and the average heat transfer coefficients were investigated. At all mass fluxes, the boiling curves showed no sign of criticality. For all aspect ratios, an optimum exit flow quality was found that maximized the average heat transfer. Furthermore, it was found that there is an optimum fin aspect ratio that maximizes the overall heat transfer; this aspect ratio is distinct from what is normally found for single phase flow.
A Thermal Reduced Order Model for Power Throttling Simulations of a 3D IC
Authors: Geb David , Deodhar Subodh , Netake Nitin , Jeurkar Tejas 
Published: November 2024

Abstract
Power throttling with dynamic voltage and frequency scaling (DVFS) is important to the dynamic thermal management (DTM) of processors. With increasing numbers of on-chip thermal sensors monitoring temperature conditions, optimizing the DVFS control logic with design tools becomes increasingly important due to the problem’s complicated nature. Furthermore, three-dimensional integrated circuits (3D ICs) with vertically stacked chips present additional challenges as cross-die thermal coupling, increased power densities, and localized hot spots, among other concerns, become more important. Effective thermal simulation methods of 3D ICs with DVFS power throttling and external cooling control can serve as an important tool in both chip and system co-design. However, overcoming the long simulation times inherent in transient thermal simulations is a key hurdle to overcome. In this paper, a dynamic thermal analysis method that includes handling of DVFS for a 3D IC example, with cooling control, is presented. A test case is prepared in which dynamically varying heat loads are imposed on the 3D IC over a 60 second operating time frame. The DVFS and cooling control react to the operating conditions measured at the on-chip temperature sensors in the 3D IC. A 3D field model is prepared from which a Linear Parameter Varying (LPV) Reduced Order Model (ROM), with variable cooling effects represented by a scheduling parameter, is obtained. The 3D field model provides the training data upon which the ROM is built. The power throttling algorithm is defined, specifically in a Python script, which is then applied within both the 3D field model and the ROM. The external cooling control is implemented via a PID controller in the model. The simulation results demonstrate both the on-chip and cross-chip hot spot thermal coupling (both strong and weak coupling is observed) along with variable cooling impacts on the 3D IC test case. Furthermore, temperature prediction verification of the ROM with the DVFS power throttling algorithm applied is obtained to within 1% over the 60 second time frame. Finally, the value of the ROM as a 3D IC thermal design tool is presented in terms of solution speed up, compared to the 3D field model representation, with a speedup factor of 61 being observed in this example. ROM speedup can be significantly higher as the corresponding 3D field model’s mesh size increases. The methodology presented in this paper can serve as the basis for improved 3D IC chip and system DTM, with simulation-based DVFS and cooling controller design. Furthermore, the method can be extended to other thermal ROM technologies.
Fabrication and Passive Assembly of Compact, Broadband Substrate-To-Die Evanescent Couplers for Sustainable Pbps Co-Packaged Optics
Authors: Weninger Drew M. , Serna Samuel , Ranno Luigi , Kimerling Lionel , Agarwal Anuradha 
Published: November 2024

Abstract
The co-packaging of optics and electronics provides a potential path forward to achieving Pbps per package data capacities. In a co-packaged design, the scaling of bandwidth, cost, and energy is governed by the number of optical tranceivers per package as opposed to transistor shrink. The scaling of optical transceivers is hindered by the need to actively assemble bulky single mode fiber arrays directly to optical transceivers. The development of efficient, dense optical couplers with wide alignment tolerances allowing for automated, passive assembly will be an enabler for continued scaling in co-packaged designs. To this end, a passively assembled substrate-to-die evanescent coupler between silicon nitride and silicon was experimentally demonstrated with a 0.39 ± 1.06 dB coupling loss at 1550 nm, a 160 nm 1-dB wavelength tolerance (1480–1640 nm), and a 1-dB lateral alignment tolerance of ± 1.56 μm. The thermal stability was evaluated from 23–60°C with average coupling loss and alignment tolerance varying by less than ± 0.35 dB and ± 30 nm, respectively. Finally, repeatability was evaluated across four packaged systems, demonstrating a coupling loss range of 1.5 dB. Together, these results show this coupler can help achieve Pbps co-packaged optics input/output (I/O) within a sustainable envelope.
Modelling Effect of Isothermal Aging of Anisotropic SaAgCu(SAC) Solder Joint Using Crystal Viscoplasticity
Authors: Bharamgonda Aniket , Dasgupta Abhijit , Chen Yaxiong , Hauck Torsten 
Published: November 2024

Abstract
SnAgCu (SAC) solder joints have oligocrystalline (few large grains) structure, with each grain showing strongly anisotropic behavior due to body-centered tetragonal (BCT) structure of Sn crystals. SAC solder joints go through microstructural evolution which directly affect their life during the life time o solder joint, Crystal viscoplasticity (CV) model has been used in the literature for demonstrating anisotropy of solder grains and is used in this paper, to demonstrate the effect of isothermal aging on anisotropic creep properties of solder grains. Changes in secondary creep strain rate of solder grains along principal crystal directions is demonstrated in this article.
Predictive Machine Learning Models for LiDAR Sensor Reliability in Autonomous Vehicles
Authors: Farahani Saba A. , Lee Jae Yun , Kim Hunjae , Won Yoonjin 
Published: November 2024

Abstract
The emergence of autonomous vehicles marks a transformative moment in the transportation sector, significantly propelled by the integration of Light Detection and Ranging (LiDAR) technology. LiDAR revolutionizes how vehicles perceive their environment, emitting laser beams to measure distances to objects and creating highly accurate three-dimensional maps. This innovation is pivotal for enhancing the operational efficiency and safety of autonomous vehicles by providing instantaneous and detailed environmental mappings. However, the efficacy of LiDAR sensors is compromised by environmental factors such as dust, dirt, snow, and rain, which can severely affect their accuracy and, consequently, the safety of the vehicles they guide. Despite the importance of this issue, the research field has shown a notable lack of investigation into predicting LiDAR sensor contamination and its reliability. This gap underscores a critical need for dedicated research efforts to ensure the reliability and safety of autonomous driving technologies, making it a pressing challenge for researchers and developers alike. Therefore, it is imperative to develop a novel way to detect LiDAR sensors’ reliability like contamination level.
In response to the urgent need to address LiDAR sensor contamination, our team have initiated a comprehensive data collection journey, spanning from California’s diverse climates to Michigan’s variable weather conditions. This dataset contains multi-level features such as contamination levels on multiple sensors, environmental factors, and sensor images across varying weather conditions and geographical locales. The dataset is a groundbreaking contribution to the field, playing a vital role in developing our machine learning models and offering novel insights that could dramatically advance research and practical applications.
In this work, our framework employs machine learning methods across two distinct but complementary strategies: sensor data analysis and image data analysis. The first strategy indirectly predicts the contamination levels by leveraging environmental variables, such as temperature, humidity, precipitation, and vehicle speed. This indirect method represents a novel approach to assessing sensor contamination, offering a significant advantage by allowing for the prediction of contamination risks before they impact sensor performance. The second strategy directly predicts the contamination levels by visually assessing LiDAR sensors under various weather conditions. The integrated strategy better performs in terms of the contamination level predictions, which is meaningful to ensure safer navigation in complex environments. Together, by introducing a novel dataset and predictive machine learning models, our framework shows a potential to address a critical gap in existing research.
Numerical Analysis of Immersed Confined Coaxial Liquid Jet Impingement Heat Transfer for Electronics Thermal Management
Authors: Kahbandeh Faramarz , Harris Daniel , Arik Mehmet 
Published: November 2024

Abstract
A large amount of data has been loaded into data centers as well as faster computational time due to the current emergence of artificial intelligence (AI), augmented reality (AR), 5G mobile networks, and digital currencies. These data require a significant amount of processing power, and as a result, this enormous processing performance generates heat in electronic chips and data center racks specifically. Conventional cooling methods are not capable of answering thermal management requirements in electronic systems. Therefore, novel techniques are needed to meet aggressive demands. One of those candidate cooling approaches is dielectric liquid impingement heat transfer. A computational study has been performed to understand the impact on chip cooling. The current study uses a constant heat flux thermal boundary condition to computationally analyze a confined coaxial impingement water jet on a heated flat plate. Four velocity ratios, three jet to target distances, and three different Re numbers have been studied through numerical simulations. The finite volume method (FVM) was used to solve the governing equations on discretized elements with RANS SST k-ω turbulence model. It has been noted that the local heat transfer coefficients increase with increasing Re numbers. On the heated flat plate, increasing the jet to target distance and decreasing the velocity ratio cause turbulence effects and increase in Nu number over the radial distance especially in the stagnation region. Additionally, it was revealed that the coaxial jet’s attained higher heat transfer characteristics than the single circular jet’s.
Effect of Passivation Layer and Line Thickness on Damage Mechanism of Flexible Ag Nanowire Interconnects Under High Density Current
Authors: Hisasue Kazuki , Sasagawa Kazuhiko , Fujisaki Kazuhiro , Miura Kotaro , Souma Yusuke 
Published: November 2024

Abstract
In recent years, the demand of flexible electronic circuits has been increasing with the development of wearable devices. Ag nanowire network structures are attracting attention as a material for flexible transparent conductive films because of their low cost, flexibility and light transmittance. In general, the density of electric current flowing through the interconnect line increases as devices become smaller. The increase in density of electric current leads to problems of line failure due to electromigration (EM), and it is known that resistance EM damage can be improved by passivation layer coating. In previous studies, it has been found that Ag nanowires were damaged by EM. However, the EM damage mechanism of network-structured Ag nanowire line under high-density current and the effect of passivation layer have not been clarified. Then, in this study, Ag nanowire network line coated with a passivation layer was fabricated. Furthermore, Ag nanowire networked line intentionally expanded in thickness direction was fabricated to measure the line thickness change with damage. We conducted accelerated electric current loading tests on these test lines and observed the damage morphology after the tests to investigate the damage mechanism under high-density current.
Maturation of Pumped Two-Phase Liquid Cooling to Commercial Scale-Up Deployment
Authors: Tipton Russell , Wise Ashley , Mutabdzija Srdan , Shores Craig , Kulkarni Devdatta 
Published: November 2024

Abstract
Applying cold plates to primary heat sources of high-performance compute (HPC) or Artificial Intelligence (AI) servers and pumping refrigerant through them is known as pumped two-phase (P2P) liquid cooling. Refrigerant to air (RA) and refrigerant to liquid (RL) versions of P2P direct to chip liquid cooling of artificial intelligence / machine learning (AI/ML) IT equipment have been developed and their performance was evaluated at commercial scale. P2P captures heat from the silicon and transports it to outdoor air. Matching silicon power map to the cold plate is critical and its design is in the IT manufacturer’s domain. Therefore, collaboration with transport system designer is necessary for optimized P2P performance. The transport system includes working fluid conveyance from coolant distribution unit (CDU) pump to an array of two-phase cold plates, return to CDU condenser, and back to CDU pump. The condenser transfers heat from the secondary fluid, refrigerant, to primary fluid which is either the whitespace air of an air-cooled data center or facility cooling system of an economized chiller.
Important performance parameters demonstrated in this paper include distribution and flow regulation of necessary refrigerant flow to each set of cold plate array; stability of CDU operation over the full range of zero to 100% IT load and during transient and asymmetric IT loading; CDU stable operation at startup as server population varies from zero to full population and while hot-swapping servers from racks. Demonstration of safe operation during abnormal conditions including pump switch over and loss of heat rejection is discussed. Lessons learned are included from commissioning P2P CDU and flow conveyance including charging, flushing, and start-up. Advantages of P2P in achieving sustainability goals and insights into a TCO analysis of RA and RW comparing 1P to 2P LC are discussed.
Investigation of Server Level Direct-To-Chip Two Phase Cooling Solution for High Power GPUs
Authors: Narayanan Akshith , Wang Qingyang , Ozguc Serdar , Bonner Richard W. 
Published: November 2024

Abstract
As artificial intelligence and technology advance, top end server CPU and GPUs are getting more and more powerful. Conventional air-cooling struggles to keep up with the surging processor power densities, leaving room for an efficient and scalable solution. This investigation focuses on the Nvidia H100 GPU architecture in a mimic 1U server with four-way GPUs. While direct to chip two phase cooling offers high heat transfer coefficients and heat capacity, there are technical challenges associated with pressure drop and flow maldistribution to understand the requirements and cost of its use. A single sled test bench is built to conduct systematic experiments with in-house designed Thermal Test Vehicles (TTVs) that replicate the form factor of Nvidia H100 GPUs. The facility is used to characterize pressure drops, die temperature, pumping power and thermal resistance at varying heat loads and flow rates, using R1233zd(E) as the working fluid. Flow restrictors were carefully chosen to balance the flow between the chips, making sure each of them receives sufficient liquid in all usage cases. The results show that the thermal resistance of the cold plate assembly varies between 0.02–0.03W/K. Higher power tests, up to 1.35kW, were conducted to understand how future-proofed the cold plate design is, in terms of rapidly scaling heat loads in the market. Results show that with sufficient flow, the system operates extremely well. The flow restrictors chosen scale quadratically with pressure drop and mass flow rate, and they efficiently suppress the maldistribution between chips on the server level and can be expanded to balancing flow on the rack level. The investigation concludes that pumped direct-to-chip two-phase cooling offers an elegant and scalable solution to the rapidly increasing power densities of CPUs and GPUs, while maintaining efficiency and minimizing the leak risks compared with using a water-based solution.
Minimizing Die Cracking Risk by Copper Pillar Design Optimization for Advanced 5nm Silicon Node
Authors: Ramdas Shrinath Shrinivas , Chauhan Tushar , Patterson Mark , Shirley Dwayne R. , Zhang Lijuan , Coccioli Roberto 
Published: November 2024

Abstract
To enable higher computing power in a single chip, there is demand for increasing die and substrate size for high performance applications in advanced nodes. Chip package interaction (CPI) performance is very critical for package reliability, specifically for advanced low-k 5nm, 3nm technology node chips including extreme low-k (ELK) and low-k (LK) dielectric materials. The material property coefficient of thermal expansion (CTE) mismatch between dielectric materials, copper, silicon can induce significant stresses, causing ELK-LK cracking or delamination and chip failure in electronic packages. For advanced semiconductor nodes like 5nm and 3nm, the Back End of Line (BEOL) structure mechanical strength is reduced due to the presence of porous material with low-dielectric constant which makes it more prone to thermal mechanical failures. On the other hand, use of stiff first level interconnect (copper pillars) together with large die, and package size causes an increased level of stress transfer from package to chip. For these reasons, die BEOL cracking or delamination due to Chip Package Interaction (CPI) is becoming more and more critical in advanced nodes and therefore necessary design optimizations should be done during initial package design phase to avoid any CPI related cracking or delamination failures in package. This study investigates in detail the impact of copper pillar design parameters such as copper pillar height, under bump metallization (UBM) diameter, copper pillar plating chemistry on die cracking or delamination within die BEOL structure. Novel fracture mechanics and stress-based with detail BEOL structure multi-level finite element analysis (FEA) simulation methodology based on the energy release rate (ERR) driving delamination using J-integral approach is developed to assess impact of various package parameters on cracking or delamination in die BEOL layer and used to assess die ELK cracking risk for advanced 5nm packages. Energy release rate (ERR) is the change in the elastic strain energy with respect to change in crack area. Critical ERR (ERRc) is material property also known as fracture toughness and it is used to estimate if the crack will propagate or not (crack will propagate if, ERR ≥ ERRc). This work is expected to provide design guidelines for package designers and help to optimize copper pillar structure for advanced 5nm packages.