bluuebunny/crossref_metadata_2025_split huggingface dataset:
Fluxes Effective in Suppressing Non-Wet-Open at BGA Assembly
Authors: Zhou Fengying , Chen Fen , Lee Ning-Cheng 
Published: December 2018

Abstract
With the advancement in miniaturization, the die is getting thinner and the solder bump is getting smaller for BGAs. Consequently, the thermal warpage is getting more severe due to coefficient of thermal expansion mismatch between die and molding compound, and often resulted in non-wet-open (NWO) at BGA assembly. NWO has been ailing the industry for a long time, and costly rework is required to remove the problem. In this study, a “cold-welding barrier” method has been developed in suppressing NWO. At BGA assembly, after printing solder paste onto PCB, the BGA bumps are dipped into creamy flux prior to placing onto paste printed. This flux pickup will effectively suppress NWO by serving as cold-welding barrier. A low activity flux is considered having as wider reflow profile window than a medium activity flux. Alternatively, the solder bump of BGA can be pre-coated with solid flux at packaging house. The effect of solid-flux coating is equally effective in suppressing NWO. As cold welding barrier, both no-clean flux and water soluble flux are considered physically effective. However, a water soluble flux should not be used together with a no-clean solder paste based on compatibility and reliability consideration. Furthermore, only no-clean solid flux is recommended for solder bump coating purpose, mainly based on moisture pickup issue associated with water soluble flux.
System ElectroThermal Co-Design of a Zero-Drift Current-Shunt Monitor with Precision Integrated Shunt Resistor
Authors: Chen Jie , Murugan Rajen , Kummerl Steven , Chaudhry Usman , Lim Edwin , Shimizu Tatsuhiro , Klumpp Thatcher , Grantham Jack 
Published: December 2018

Abstract
In this paper, we detailed the system (die + package + pcb) electrothermal co-design modeling and silicon validation effort that led to the industry's first, highly accurate, voltage-output current-sense amplifier. By integrating and co-designing the low-Ohmic shunt resistor in the package, along with the current amplifier, key performance design challenges (viz. electrical and thermal) become manageable. The validity of the co-design electrothermal modeling methodology was assessed by comparing directly to silicon measurements made on an evaluation module (EVM). Good correlation between simulation and laboratory measurements on the integrated solution is demonstrated.
Reliability of Fan-Out Wafer-Level Heterogeneous Integration
Authors: Lau John , Li Ming , Lei Yang , Li Margie , Xu Iris , Chen Tony , Yong Qing Xiang , Cheng Zhong , Kai Wu , Lo Penny , Li Zhang , Tan Kim Hwee , Cheung Y. M. , Fan Nelson , Kuah Eric , Xi Cao , Ran Jiang , Beica Rozalia , Lim Sze Pei , Lee N. C. , Ko C. T. , Yang Henry , Chen Y. H. , Tao Mian , Lo Jeffery , Lee Ricky 
Published: December 2018

Abstract
In this study, the reliability (thermal-cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5mm×5mm), three small chips (3mm×3mm), and 4 capacitors (0402) embedded in an epoxy molding compound (EMC) package (10mm×10mm) with two RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging (FOWLP) is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.
Increase Power Density and Simplify Designs Using 3-D SiP Modules
Authors: Kummerl Steven , Devries Charles , Chaudhry Usman , Lim Chong Han 
Published: December 2018

Abstract
Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more circuit board real estate toward end-user applications – all with less space allocated to power management where not just the X–Y shrink but the 3D volumetric shrink is required. For example, in today's Telecommunications Cloud Infrastructure systems, board space and power density are challenging particularly in power supply designs where several high-current point-of-load rails are present. End equipment such as enterprise servers and switches, workstations, base stations, network attached storage, FPGA testers, network testers, and other test and measurement equipment employ several high-current CPUs, ASICs, FPGAs, and DDR memory – all of which need high power, while the available board area is steadily decreasing. This paper will discuss volumetric co-design methodology and packaging construction trade-offs for 3D SiP power modules and also introduce the straddle mounted inductor assembly technique. Also provided are details around the SiP eco-system, co-design, construction, materials, and circuit topology.
A numerical study on mitigation of flying dies in compression molding of microelectronic packages
Authors: Dreissigacker Marc , Hoelck Ole , Bauer Joerg , Braun Tanja , Becker Karl-Friedrich , Schneider-Ramelow Martin , Lang Klaus-Dieter 
Published: December 2018

Abstract
Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds (EMC) depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity.
The focus is set on forces exerted on individual dies during encapsulation in Fan-Out Wafer Level Packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemo-rheology, as well as to extract forces exerted on individual dies. It offers separate evaluation of pressure and shear-contributions for two cases, 0 ° and 45 ° between the dies' frontal area and the melt front.
Process parameters, such as compression speed and process temperature, are determined to minimize flying dies and thereby maximize yield.
The approach is easily scalable and is therefore well suited to face the challenges that come with the current efforts towards the transition from FOWLP to FOPLP (Fan-Out Panel Level Packaging).
High reliable and high bonding strength of silver sintered joints on copper surfaces by pressure sintering under air atmosphere
Authors: Chew Ly May , Schmitt Wolfgang 
Published: December 2018

AbstractSilver sintering is a promising die attach technology for high temperature power electronics packaging. Our previous studies have revealed that highly reliable sintered joints was obtained on silver and gold surfaces by either non-pressure or pressure sintering. In this paper, we extended our study to die attachment on copper surfaces by pressure sintering under air atmosphere. We attached Ag metallized die on silicon nitride active metal braze copper substrates with Ag metallization and without metallization by silver sintering at 230°C with a pressure of 10 MPa for 3 min. We observed that the average initial die shear strength for bare Cu substrate is lower than for Ag metallized substrate. This observation is attributed to the self-diffusion of Ag is faster than the interdiffusion between Ag and Cu. However, the average die shear strength for all samples increased considerably after temperature cycling test (−40°C/+150°C) and high temperature storage at 250°C. It is highly likely that sintering process is not yet completed under the sintering conditions used in this study and consequently Ag and Cu continued to diffuse during thermal cycling and high temperature storage and as a result strengthen the sintered joints. It is believed that after a certain time of storage at 250°C the sintering process is completed as we observed the average die shear strength remained relatively constant after 250 h storage. Voids, drying channels and delamination in the sintered joints were not detected by scanning acoustic microscopy for the samples before and after 2000 thermal cycles.
Study on high temperature resistant die bonding formed by Al/Ni nano-particles composite paste
Authors: Tanaka Yasunori , Wakata Tatsumasa , Murakawa Norihiro , Iizuka Tomonori , Tatsumi Kohei 
Published: December 2018

Abstract
In power modules using SiC devices, high temperature operation is expected. Therefore, a bonding technology having high temperature resistance of 250°C or more is required. In recent years, research on low temperature sintering bonding by Ag nanoparticles, Cu nanoparticles and sub-micron particles has been conducted as a new bonding technology corresponding to SiC power devices. Nanoparticles are sintered at a temperature much lower than the sintering temperature in ordinary powder metallurgy. We focus on Ni having high melting point and excellent corrosion resistance as a new bonding material and are conducting research on high temperature resistant interconnection technology using Ni nanoparticles. We have found that bonding is possible at a bonding temperature of 400°C or less and enable to interconnect SiC devices for high temperature operation. However, there are still following problems to be improved, as follows, especially for a large chip size : Voids formed in the bonding layer and cracks generaled stress caused by a difference in thermal expansion coefficient(CTE). In this paper, we propose a bonding material of composite paste in which Ni nanoparticles and Al particles are mixed. From the results of the research, it was found that the occurrence of cracks and gas void was suppressed by mixing Al particles. Also the thermal stress analysis by FEM, the addition of Al particles shows to reduce the thermal stress during thermal cycle test (TCT).
Fatigue Cycling of Electrical Interconnects Dispensed on Flexible Substrate
Authors: Alhendi Mohammed , Lombardi Jack P. , Khinda Guvinder S. , Kokash Maan Z. , Weerawarne Darshana L. , Borgesen Peter , Poliks Mark D. , Stoffel Nancy C. , Iannotti Joe 
Published: December 2018

Abstract
In the presented work, electrical traces were directly printed on 2 mil thick polyimide flexible substrate by a dispenser system using two different silver pastes, SW 1400 paste from Asahi Co. and 125-13 HV paste from Creative Materials Co. The dispenser printing parameters were optimized to achieve the finest possible line width and the printing quality of both materials was investigated. The electrical behavior of the dispensed traces was investigated by monitoring the change in the electrical resistance of the test samples during fatigue cycling at different strains, strain percentage of 1.50%, 2.0%, and 2.5% for different number of cycles up to 1000 cycles. The life time of the dispensed traces versus the applied strain was modeled using Coffin-Manson relation setting 20% change in the initial resistance as the failure criteria. Based on the change in the trace resistance during testing, we concluded that the dispensed SW 1400 silver paste traces were less robust than the dispensed 125-13 HV traces. The finer microstructure, smaller particle size, and shorter inter particles distances of the 125-13 HV silver paste enhanced its durability when subject to fatigue cycling. Moreover, 125-13 HV paste presented better and more uniform printed traces.
Characterization of Fine-Pitch Interconnections (≤ 10 μm) on Silicon Interconnect Fabric for Heterogeneous Integration
Authors: Jangam SivaChandra , Bajwa Adeel , Thankappan Kannan K. , Iyer Subramanian S. 
Published: December 2018

Abstract
We propose a fine-pitch, highly scalable, heterogeneous integration platform called the Silicon-Interconnect Fabric (Si-IF) where dielets are assembled with fine-pitch interconnects (≤ 10 μm) at short inter-dielet spacings (≤ 100 μm) using direct metal-metal Thermal Compression Bonding process (TCB). As a result, short links on Si-IF (≤ 500 μm) are used for inter-dielet communication, reducing the latency to ≤ 35 ps. We experimentally demonstrated the measured insertion loss in these short Si-IF links (≤ 500 μm) is ≤ 2 dB for frequencies up to 30 GHz. Consequently, we show that assemblies on Si-IF have 10–40X lower parasitic inductance, and 7–35X lower parasitic capacitance compared to assemblies on interposers and PCBs. We propose the Simple Universal Parallel intERface for chips (SuperCHIPS) protocol for data transfer that efficiently utilizes the Si-IF to achieve data-rates of ≥ 10 Gbps/link at an energy/bit of ≤ 0.04 pJ/b. Further, the aggregate bandwidth/mm is ≥ 8 Tbps/mm. This corresponds to an improvement of 120–300X in bandwidth/mm and a reduction of 100–500X in energy/bit compared to conventional systems.
Investigation towards the optimum of power capability, ageing stability and costs effectiveness on thick film resistor pastes for AlN ceramics
Authors: Schmidt Richard , Marcinkowski Manja , Feller Claudia , Partsch Uwe 
Published: December 2018

Abstract
The focus of this work was the optimization of a 10 Ω/□ thick film resistor (TFR) paste composition to obtain increased power capability, aging stability and minimum use of ruthenium oxide for cost savings without changing the defined narrow sheet resistance (R□) and temperature coefficient of resistance (TCR) specifications. In times of highly fluctuating precious metal costs, the use of a minimum of the precious metal ruthenium respectively ruthenium dioxide is one essential part for cost-effectiveness. The thick film paste formulation consists of the electrically conducting phase ruthenium dioxide, a lead-free glass phase and two inorganic additives for tuning thermo-mechanical and electrical properties of the formed films. A phthalate free organic vehicle with ethyl cellulose polymer was used to formulate a screen printable ceramic thick film paste.
For this paper, RuO2 powders with various specific surface area values (BET) were prepared by thermal annealing of a precipitated fine ruthenium dioxide powder. All other solid and liquid components of the paste were the same as used for IKTS 10 Ω/□ TFR paste FK9611 for AlN substrates. Furthermore, the content of ruthenium dioxide in the paste compositions was changed systematically around an assumed target content to achieve the desired sheet resistivity. Concurrent to the variation of the ruthenium dioxide content the inorganic additives had to be adapted too. The influence of the variations of raw material and paste composition on the film properties were investigated by screen printing 24 resistors of 2 mm × 1 mm dimension on an 1” × 1” AlN substrate, firing at 850 °C for 10 minutes in air atmosphere and subsequently measuring R□, TCR, the stability of resistance ΔR/R0 effected by artificial aging of the resistors (stored 100 up to 1000 hours @ 200°C) and the maximum rated power dissipation (MRPD) as well as short term overload voltage (STOL). The results are discussed in regard to find an optimum between all demands of the most important electrical film properties.
High Performance Etchable RoHS Compliant Thick Film Gold Conductor
Authors: Shahbazi Samson , Berube Gregg , Edwards Stephanie , Persons Ryan , Shahbazi Caitlin 
Published: December 2018

Abstract
The thick film paste manufacturers are expected to produce conductors which are lead and cadmium free, yet have excellent fired film properties and the same performance and properties as the cadmium and lead containing formulations. The fired film surface of these conductors must be defect free (i.e. imperfections, pills, agglomerates) after multiple firing steps and must perform on dielectric as well as substrates from different suppliers. Typically, the thick film gold conductors are used in high reliability applications such as medical devices, military applications, and high frequency circuits, which require robust performance at high and low temperatures, in chemically aggressive environments, or extremely humid conditions. As circuits decrease in size and become more complex, the thick film gold properties become increasingly critical. The challenge is to develop an alternative gold conductor formulation, which can print and resolve fine features (down to 4 mil lines and spaces) as well as have the ability to be etched for higher density circuit designs (down to 1–2 mil lines and spaces). Gold conductors are typically used in conjunction with other high temperature thick films so good performance after multiple firings was also a targeted requirement. Heraeus has been proactive for the past decade in the development of thick film products that are both RoHS (lead and cadmium free) as well as REACH compliant.
This paper discusses the experiments that were performed in order to understand the contribution of gold powder, organic and inorganic system to improve the fired film performance. These formulations were compared against existing gold conductors including the high performance gold conductor options as well as other available standard gold conductor options. Thin wire bonding trials including both gold and aluminum wire are used to compare influences of raw materials which includes high volume wire bonding reliability including failure modes and aged wire bond adhesion at elevated temperature exposures (300°C) for extended periods of time. In order to analyze fired film morphology and link this up to wire bond performance, SEM images of the conductor surface and cross sections were conducted.
These studies resulted in a newly developed thick film gold conductor paste for use in a wide variety of applications. We present wire-bonding data with gold and aluminum wire and reliability results on both 96% Al2O3 ceramic substrates as well as on top of standard dielectrics.
RF Test Article Experiment on the Impact of Non-Hexavalent Chromium-Based Conversion Coatings on Electrical Assemblies
Authors: Petko Joshua S. , Lovell Philip A. , Clifton Jeremy D. , Bersani Alexander J. , Schoch Karl F. 
Published: December 2018

Abstract
Conversion coatings are treatments applied to aluminum structures to inhibit corrosion while maintaining electrical conductivity. In aerospace applications, the most common type of conversion coatings (MIL-DTL-5541 Type I) contain hexavalent chromium compounds as the corrosion-inhibiting agent. These Type I conversion coatings have a long pedigree and are highly effective in preventing corrosion; however, the hexavalent chromium compounds in these coatings are carcinogenic and water-soluble. Therefore, the use of these compounds is highly regulated in order to protect both workers and the public, leading to high cost in both use and disposal. Regulations are also beginning to restrict outright use, where new designs for the DOD are prohibited from using Type I coatings by DFARS 48 CFR Parts 223 and 252 and all use has been prohibited by Europe by REACH regulations since September 2017. In response, more environmentally friendly non-hexavalent chromium-based processes, referred to as MIL-DTL-5541 Type II conversion coatings, have become available. However, the long term reliability and performance impacts resulting from the use of these coatings are not fully understood and there is an ongoing effort in the aerospace industry organized by NASA to fully define these impacts while hardware is still in the design stage.
While significant work has been performed to define the corrosion performance of various type-II conversion coatings, there has been minimal work performed to quantify the impact a type-II conversion coating would have on RF electrical assemblies. The standard methodologies defined by MIL-DTL-81706B have significant limitations and cannot fully capture the impact at microwave frequencies. For this reason, an investigation is underway at Northrop Grumman to quantify the impact these coatings may have on the quality, reliability, and performance of our electronic systems. At IMAPS 2017, Northrop Grumman introduced a RF test article designed to assess the longitudinal impact a Type II conversion coating would have on RF electrical assemblies where plated printed wiring boards (PWBs) and aluminum structures come in intimate contact. The test article features a specialized suspended stripline/microstrip stepped impedance filter designed to de-tune in the presence of galvanic corrosion. This talk follows the work presented in IMAPS 2017 by discussing an experiment where three different populations of test articles, each coated with a different type of conversion coating, are subjected to environmental testing. This talk also discusses how an initial measurement of these test articles before environmental exposure showed little difference between these populations. Finally, this talk reviews the initial results of this experiment, discussing environmental testing and the RF measurements captured during these tests.