bluuebunny/crossref_metadata_2025_split huggingface dataset:
Unlocking the full Potential of Lithography for Advanced Packaging
Authors: van der Voort Jelle , van der Stam Michiel 
Published: December 2018

Abstract
Advanced Packaging technologies and applications are developing rapidly in order to support the ever increasing demand for integrating functionality in small and thin devices with low power consumption, high bandwidth, low latency- all at low cost of ownership. Lithography is the key enabling technology for developing and manufacturing such devices. Advanced Packaging processes, in particular Fan-Out, drive towards redistribution patterns with smallest feature sizes of a few micron today and towards 1 micron in the future. These feature sizes must be realized in production processes with multiple layers stacked on top of each other which need to be accurately aligned. In order to meet economic boundary conditions, routine operation on 300 mm wafers (possibly strongly warped) is required with high throughput. Kulicke & Soffa Liteq B.V. developed together with key partners, a novel Lithography system which is focused specifically to meet the challenging requirements of Advanced Packaging, both for current and future applications. The high quality optics used is capable to project the optimally sized reticle field with lowest possible aberrations on the wafer. The system includes Reticle Masking blades (REMA), which delivers high flexibility and high speed for multi-pattern jobs. The magnification of the optics is adjustable for optimal intra-field overlay performance. The reticle is illuminated by a high power UV laser. This novel setup creates many advantages for imaging, Cost of Ownership and throughput. The illumination and projection optics is combined with modern mechatronics to handle warped wafers with minimal overhead times. The design has a strong focus on contamination control. Wafer Edge Processing functions are integrated in the system to support the use of state-of-the-art plating processes. The modularity of the system architecture makes it possible to extend functionality and performance into the future. In this paper we will introduce the novel LITEQ 500 projection stepper, present imaging results and demonstrate the flexibility and high throughput potential of reticle masking for complex multi-pattern jobs.
Advances in Temporary Bonding and Debonding Technologies for use with Wafer-Level System-in-Package (WLSiP) and Fan-Out Wafer-Level Packaging (FOWLP) Processes
Authors: Fowler Michelle , Massey John P. , Koch Matthew , Edwards Kevin , Braun Tanja , Voges Steve , Gernhardt Robert , Wohrmann Markus 
Published: December 2018

AbstractToday's complex fan-out wafer-level packaging (FOWLP) processes include the use of redistribution layers (RDL) and reconstituted wafers with epoxy mold compound (EMC) for use in heterogeneous integration [1]. Wafer-level system-in-package (WLSiP) uses fan-out wafer-level packaging (FOWLP) to build the system-in-package (SiP) by attaching know-good die (KGD) in a chip-first process to a tape laminated temporary carrier. If the dies are attached in a die-up configuration (active area facing up) and then over-molded with EMC, contact pads on the embedded die are exposed during the backside grind process. During the RDL build, the temporary carrier supplies mechanical support for the thinned substrate. In a die-down configuration with the active area facing down (eWLB), the temporary carrier is removed after the molding process thus exposing the contact pads for RDL build and solder ball mount.The ideal chip attachment scheme should minimize lateral movement of the die during over-mold (die shift) and also minimize vertical deformation of the bonding material. Thermal release tape provides a convenient way to attach die to a carrier prior to over-molding with EMC. However, not all bonding materials are suitable for presentation in tape form, so the material used in the tape may not be the optimal choice. An alternative method is to directly apply temporary bonding material to the carrier substrate. This enables the use of bonding materials with higher melt viscosity and improved thermal stability, resulting in less vertical deformation during die placement, and reduced die shift during over-molding. The bonding material will ideally have high adhesion to the EMC wafer to prevent delamination in the bond line during downstream processing. Stack stress and warpage is a major concern which causes handling and alignment problems during processing. The bonding material and carrier will need to be specifically suited to minimize the effects of stress in the compound wafer.Such material must balance rigidity with warp to prevent lateral die shift and deformation induced by coefficient of thermal expansion (CTE) mismatch between the carrier and EMC material [2]. Bonding materials must also have enough adhesion to the EMC material to overcome such stress without bond failure for an associated debond path (such as laser or mechanical release). In this experiment, we will examine a thermoplastic bonding material in combination with different release materials, addressing die shift, and deformation after EMC processing. Successful pairs will then undergo carrier release using either mechanical release or laser ablation release technology.
Solder-Joint Reliability of a Radar Processor for Semi-Autonomous Driving Applications
Authors: Benson Mollie , Carpenter Burton , Mawer Andrew 
Published: December 2018

Abstract
Radar is currently employed in automotive applications to provide the range, angle, and velocity of objects using RF waves (77GHz). This paper outlines solder joint reliability of a specific micro-processor that processes data received from a SRR (short range radar operating from 0.2 to 30 meters). It is a powerful digital signal processing accelerator, which targets safety applications that require a high Automotive Safety Integrity Level (ASIL-B). The paper explores the package design and construction, SMT (surface mount technology) assembly, and board level reliability testing of various BGA pad surface finish and solder ball alloy materials on a 0.65 mm pitch, 10 × 10 mm body 141 MAPBGA (mold array process-ball grid array) package. The package configurations include two BGA pad surface finishes (Ni/Au and OSP [organic solderability protectant]) and three solder alloys (SnAg, SAC405, and SAC-Bi [a Bi containing SAC derivative]). Solder joint reliability analysis was performed through AATS (air-to-air thermal shock) between 40°C and +125°C and JEDEC Drop Testing at 1500G's. Thermal shock was extended until at least 75% of the populations failed, which was well past the points needed to qualify the packages for the intended end-use applications. The evaluations of the micro-processor indicate that the MAPBGA package can meet the ASIL-B specification requirements with optimized combinations of BGA pad surface finish and solder alloy. The focus of this paper was to determine the baseline solder-joint thermal shock and JEDEC drop performance with varied BGA pad surface finish and solder ball alloy materials.
Thin Core Substrate Large Size FCBGA Stress and Thermal Challenges and Characterization
Authors: Sung PoHsien , Hu Ian , Yang Penny , Feng Avis , Chin Shouyi , Shih MengKai , Tarng David , Wang Marwan , Hung CP 
Published: December 2018

Abstract
Recently, high speed communication packages require much larger chip sizes and the increased ball/lead counts (&gt;3000), in order to meet high input/output (I/O) functionality, requires large size substrate (&gt;50×50 mm2) to content it. Comparing with conventional substrate, thin core substrate brings about not only lower thickness of package, lightweight, but also short interconnection distance and good power integrity. For large size FCBGA with thin core, the challenge is how to effectively mitigate the assembly and reliability risks. Generally, it is not easy to control warpage using a stiffener ring or a lid for larger package size. Meanwhile, design for warpage control and TIM/chip interface stress reduction are conflicting in general. In addition, there has higher bump crack risk due to increased die center to bump distance resulted by larger die size. The solder resist opening of substrate and micro ball volume are considered to be the factors for solder bump stress reduction. The research work presented in this paper describes key factors for mitigating several assembly related issues, and the identification of the optimum structure design for successfully manufacturing larger size flip chip packages with thin core substrate.
A comparison of the Cu electrochemical migration behavior between Cu lines with 5 um L/S realized by conventional Semi Additive Process (SAP) and an innovative Excimer Laser Damascene Process
Authors: Gernhardt Robert , Müller Friedrich , Woehrmann Markus , Hichri Habib , Hauck Karin , Arendt Markus , Lang Klaus-Dieter 
Published: December 2018

Abstract
The technological evolution regarding multi-chip integrated Fan-Out packages and chip scale packages (CSPs) with high amounts of I/O demands for even higher routing densities. Conventional used technologies and materials like mask aligner and photosensitive polymers used for semi additive process (SAP) in the BEOL have reached its limits to push the resolution down to two um. New materials and technologies are necessary to overcome these limits. As the routing density increases, so does the reliability requirements. The electrochemical migration between Cu lines cannot be neglected and need to be analyzed as the distance between the Cu lines is decreasing.
A new approach for fine-line multi redistribution layers (RDL) realized by an excimer laser dual damascene process was presented in the past, using laser ablation and Cu chemical mechanical planarization (CMP) to realize embedded Cu lines.
This approach has several advantages regarding the processing but one of the most important characteristics of the damascene approach is the improved electrochemical migration behavior. The Cu lines are partially cladded by the Ti part of the seed layer due to the way of processing. The Ti acts as a barrier layer and inhibits the Cu migration into the surrounding polymer. RDL structures realized by conventional SAP have Ti only under and not between the Cu lines.
In this study different test samples with interdigital structures (resp. interdigital capacitor IDC) with five um line and space width (L/S) were realized to analyze the electrochemical migration behavior between the fingers of the IDC. The samples were realized by SAP and by the excimer laser damascene process and were subsequently tested by the temperature humidity bias (THB) test resp. biased High Accelerated Stress Test (bHAST). With the help of this work, we were able to compare the reliability of both process variants and to demonstrate and prove the reliability of embedded copper lines realized by the excimer laser damascene process.
Copper Oxidation Effect in the EMC/Cu Interfacial Adhesion Improvement for a Novel Copper Interconnection Substrate Application
Authors: Shu Min-Fong , Tseng Yi-Hsiu 
Published: December 2018

Abstract
Copper oxidation structure, cupric oxide (CuO) and cuprous oxide (Cu2O), under Ar/H2 plasma reaction mechanism for the EMC/Cu interface adhesion improvement was studied in this work. This work is utilized TGA to figure out Cu oxidized state and sample preparation, and using plasma treatment Cu oxidation layer to evaluate the EMC/Cu interface adhesion strength by shear testing method. Results show a plasma reduction on Cu oxidation layer provide a better interface adhesion, and the layer structure has a significant composition change, Cu/Cu2O/CuO/EMC → Cu/Cu2O/CuO/Cu2O/EMC. These layer structures were identified by high-resolution TEM mapping with EELS spectrum fitting, it was also verified for CuO reduction to form Cu2O, following the Cu2O hydration would provide much hydrogen-bonding in the EMC/Cu interface. This kind of chain reaction mechanism including CuO reduction and Cu2O hydration was described by 2CuO + H2 → Cu2O +H2O → 2CuOH (hydration molecular). The reaction mechanism of the EMC/Cu bonding has been investigated and verified in this experimental study and our conclusion is that hydrogen bonding on the Cu oxidation layer surface can strengthen the EMC/Cu interface adhesion.
Shear Strength and Thermomechanical Reliability of Sintered Ag Joints Containing low CTE Non-metal Additives for Die Attach
Authors: Fan Guangyu , Labarbera Christine , Lee Ning-Cheng , Clark Colin 
Published: December 2018

Abstract
Ag sintering has been paid attention as an alternative to soldering in die attach for decades, especially for high temperature power electronics packages because of its high melting temperature, highly thermal and electrical conductivity of the sintered silver joints, and low process temperature less than 275°C. The coefficient of thermal expansion (CTE) of silver (19.1ppm/°C), however, is much higher than the silicon die (2.6ppm/°C) and the commonly used alumina substrate (7.2ppm/°C). CTE mismatch of the different materials in the various components in a power electronics package lead to the delamination at the interface between interconnection layer and chips or substrate, and/or cracking of the interconnection layer is one of the mostly common causes of failure of power electronics device during thermal cycling or high temperature operation. In recent years we have been developing a series of silver sinter pastes containing low CTE non-metal particles to reduce or adjust CTE of the sintered joints so as to extend the lifetime and reliability of power electronics device in high temperature applications.
In the present paper, we will report a new set of silver sinter pastes containing micro scale non-metal particles, a sintering process, microstructural morphologies, thermo-mechanical reliability of the sintered joint and effect of the contents of non-metal particles on shear strength of the sintered silver joints bonding an Ag silicon die on Ni/Au DBC substrates. Shear tests on the sintered joints with and/or without the low CTE non-metal additives have been conducted at room temperature, 200, 250, and 300°C. Thermo-mechanical reliability of the sintered joints was evaluated by thermal cycling, thermal shock, high temperature storage tests (HTS), respectively. X-ray inspection and scanning electronic microscopy (SEM) were used to characterize void, crack and microstructure morphologies of the sintered joints with and/or without the additives.
Chip Package Interaction: Understanding of Contributing Factors in Back End of Line (BEoL) Silicon, Cu Pillar Design and Applied Process Improvements
Authors: Kuechenmeister Frank , Breuer Dirk , Geisler Holm , Boehme Bjoern , Machani Kashi Vishwanath , Hecker Michael , Kosgalwies Sven , Cho Jae Kyu , He Dongming , Zhang Xuefeng , Zhao Lily 
Published: December 2018

Abstract
This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied jointly by GLOBALFOUNDRIES as the silicon supplier and Qualcomm Technologies, Inc., as the customer responsible for packaging. This strategy involves thermo-mechanical modelling, data collection on wafer level using shear test to assess the BEoL-stability, Cu Pillar process development and optimization. The qualification of these process changes had been completed and implemented in volume production.
The paper also discusses mechanical wafer level and thermo-mechanical package modeling approaches. A model has been applied to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to set up experiments to further mitigate CPI related failure modes in BEoL on the package level.
GLOBALFOUNDRIES and Qualcomm Technologies, Inc., assessed Cu Pillar design related rules such as Cu Pillar diameter and height as well as the Cu Pillar stack up. Process improvements were carried out to reduce the undercut of the barrier underneath the Cu Pillar. The paper reveals how effectively an optimized Cu Pillar design and improved Cu Pillar processing can contribute to the risk mitigation of CPI failure modes in the BEoL for critical package designs and assembly processes with low margin against BEoL fracture during solder reflow.
Furthermore, process improvements applied to enhance the BEoL stack strength were investigated and have been implemented in high-volume production. A strong correlation was established between data collected on wafer level to assess the BEoL strength and data collected on package level.
Packaging and Integration Strategy for mm-Wave Products
Authors: Ray Urmi , Cho NJ , Kim YC , Yoon SW , Choi WK , Marimuthu Pandi 
Published: December 2018

Abstract
This paper is a follow on to the paper presented at the IMAPS 14th International Conference DEVICE PACKAGING and will provide more comprehensive case studies of few different system integration strategies for high frequency packaging. The packaging options vary widely based on the end market requirements, from performance, thermal, types and numbers of antenna arrays as well as the RF transceiver ICs. Tied closely to these performance related requirements is competing trade-offs of reliability, form factor and cost.
We present assessment of packaging structures for (a) high performance mm-Wave network product and (b) consumer/mobile product and (c) automotive radar product. The former (a) is generally not challenged by form factor and can be enhanced by the addition of more antenna arrays and RFICs. However, care has to be taken to address the thermal solutions for effective heat dissipation as well as manufacturability issues as the package size may target ~400mm2 for Gen 1 and double or triple the area for subsequent generations. For (b), the primary drivers are cost and form factor. To manage antenna propagation and losses in a constrained form factor, mobile products generally require antenna in package (AiP) integration. The integration of the antenna within the same package as the RF IC greatly reduces the difficulty at the system level. This approach coupled to aggressive miniaturization of the antenna itself, using the same substrate technologies as the SiP leads to a new class of sub-systems termed Antenna in Package (AiP). This is extremely challenging from design, manufacturability and test perspectives. For example, Fan out wafer level packaging, such as eWLB packaging provides extremely smooth copper surfaces with tight etch tolerance compared to standard laminate based packaging. However, having multiport antenna structures fabricated in fan out technology with inductance matching and efficient ground ports, continue to be problematic. Hence adoption of 3D structures, in conjunction with SIP integration (with inductors and IPDs) can potentially provide relief. Inductors can also be built into the eWLB structure using the RDL as well as in the laminate packages using substrate embedded thin film cores.
Bumping Process Impact on the Chip Package Interaction (CPI) Reliability
Authors: Fu Lei , Bhagavat Milind , Barber Ivor 
Published: December 2018

Abstract
Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) became critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Controlled collapse chip connection (C4) bump technology provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important role for chip package interaction reliability.
In this paper, we focused on bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, Ti seed layer deposition, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability.
Lithographic evaluation of thin photoimageable dielectric dry film for advanced panel level packaging applications
Authors: Best Keith , Dimov Ognian , Habib Sudmun , Malik Sanjay 
Published: December 2018

Abstract
This paper presents a new dielectric material capable of resolving 2 to 3μm features that are required for high density advanced packaging applications. The material is applied in dry film format to be conducive to panel-level processing. The material can be processed at temperatures below 170°C and total thermal shrinkage is below 5%, resulting in exceptionally low stress of 11 MPa. The film is thermally stable at temperatures up to 350°C. Mechanical and electrical properties of the material are state of the art.
As the demand for high density packages increases, so will the pressure to lower the cost of manufacturing. Migrating from wafers to large non-circular panels offers several key cost advantages. There are multiple technical challenges that need to be addressed before commercial viability of panel scale manufacturing can be established. A new class of novel dielectric materials will be needed that can be processed at low temperatures and demonstrate low shrinkage to minimize warpage.
In this study, 2 to 3μm patterns were successfully formed using i-line stepper exposure conditions. The process started by laminating a 510mm × 515mm panel with highly photosensitive dielectric film. The laminated panels were exposed at a nominal dose of 125 mJ/cm2. Fine negative tone patterns were created after development. For the metallization of the layer, the seed layer was deposited with titanium-copper sputtering. After the seed formation, trenches were filled with copper by an electrolytic plating process.
Integration of a K-Band Receiver Front-End Using a Copper Core Printed Circuit Board
Authors: Curran Brian , Reyes Jacob , Tschoban Christian , Ndip Ivan , Lang Klaus-Dieter , Leiß Jens , Martinez-Vazquez Marta , Baggen Rens 
Published: December 2018

Abstract
Increasing demand for high bandwidth wireless satellite connections and telecommunications has resulted in interest in steerable antenna arrays in the GHz frequency range. These applications require cost-effective integration technologies for high frequency and high power integrated circuits (ICs) using GaAs, for example. In this paper, an integration platform is proposed, that enables GaAs ICs to be directly placed on a copper core inside cavities of a high frequency laminate for optimal cooling purposes. The platform is used to integrate a K-Band receiver front-end, composed of four GaAs ICs, with linear IF output power for input powers above −40dBm and a temperature of 42°C during operation.