bluuebunny/crossref_metadata_2025_split huggingface dataset:
Sn3.2Ag0.7Cu5.5Sb Solder Alloy with High Reliability Performance up to 175C
Authors: Geng Jie , Zhang Hongwen , Mutuku Francis , Lee Ning-Cheng 
Published: December 2018

Abstract
A novel lead-free solder alloy 90.6Sn3.2Ag0.7Cu5.5Sb, designated as Indalloy276, was developed targeting for high reliability with a wide service temperature capability. The alloy exhibited a melting temperature range of 223 to 232°C, reflowable at profile with peak temperature 245°C and 255°C, with ambient temperature Yield Stress 60MPa, UTS 77 MPa, and ductility 28%, and a higher stress than both SAC305 and SACBSbN, the latter two alloys were used as controls. When tested at 140°C and 165°C, the die shear stress of 276 was comparable with SACBSbN but higher than SAC305, and the ductility was higher than both SACBSbN and SAC305, with SACBSbN exhibited distinct brittle behavior. When aged at 125°C and 175°C, the die shear strength of 276 was comparable or higher than both controls. When pretreated with a harsh condition, TST (−55°C/155°C) for 3000 cycles, the die shear strength of 276 was 8 times of that of SACBSbN and SAC305. When pre-conditioned at TCT (−40°C/175°C) for 3000 cycles, the die shear strength of 276 was 11 to 20 times of SACBSbN and SAC305, depending on the flux type used. Both 276 and SACBSbN are alloys based on SnAgCu, but reinforced with precipitate hardening and solution hardening, with the use of additives including Sb, Ni, and Bi. 276 exhibited a finer microstructure with less particles dispersed, while SACBSbN exhibited more particles with some blocky Ag3Sn plates or rods. 276 is rigid and ductile, while SACBSbN is rigid but brittle. Under the harsh test condition where ΔT was high, the dimension mismatch between parts and substrate became very significant due to CTE mismatch. This significant dimension mismatch would cause a brittle joint to crack quickly, as seen on SACBSbN. The challenge was more tolerable for a ductile joint, as shown by 276. Accordingly 276 showed a much better reliability than SACBSbN under harsh condition, including high testing temperature and large ΔT. Overall, to achieve high reliability under a wide service temperature environment, a balanced ductility and rigidity for solder alloy is critical for success.
Enhancements to Picosecond Acoustic Metrology for application in FO-WLP Process
Authors: Mehendale M. , Mair R. , Chen J. , Tan J. , Dai J. , Mukundhan P. , Kim C. , Kryman T. 
Published: December 2018

Abstract
Fan out wafer level packaging (FO-WLP) is one of the fastest growing advanced packaging segments due to its versatility for a wide variety of applications. It's compatibility with large scale, low cost, ultra-thin and high-density packages has made it very attractive. Cu redistribution layer and multiple metal under bump metallization stack play critical role in the FO-WLP process especially with shrinking line/space size and increasing density. We previously discussed the adaptation of PULSE™ technology, with the integration of a visible reflectometer and high resolution camera as a comprehensive in-line metrology tool for the advanced packaging applications. In this paper, we present results from some recent work on enhancements to the configuration for measurements of very thick, rough RDL films. The modifications provided significant improvement (9×) to throughput while maintaining gage capable repeatability. Cross-section SEM measurements on 1μm RDL structures were used to validate the extendibility of the technique.
Optical Run-Out Correction for Improved Lithography Overlay Accuracy for FOWLP Applications
Authors: Hichri Habib , Vis William , Arendt Markus 
Published: December 2018

Abstract
Finer features sizes in advanced Wafer-level-packaging (WLP) processes create increasing demands to improve lithography equipment overlay control. The improvement goes beyond the inherent overlay capability of the equipment (“tool-to-itself”), but requires ways to compensate for mismatches in actual feature size and position on the wafer with respect to the photomask pattern. In Fan-Out wafer level packaging (FOWLP), error contributions from the die placement robot, and especially errors from expanding and shrinking mold compound in which the dies are embedded (magnification error), lead to undesirable errors in layer to layer overlay. Mask-less laser direct imaging (LDI) technologies or die-by-die alignment strategies on steppers can deal with these error contributions, but they cannot provide adequate throughput and have a high cost-of-ownership, and therefore offer a limited solution for the industry.
An Active Optical Magnification Correction and Beam-Steering technology option has been developed, available on a full-field UV projection scanner tool. This option allows compensating any type of run-out or run-in up to +/− 200 ppm, or die shifts of +/− 30 μm on a 300 mm wafer, which corresponds to the amount of magnification error caused by the embedding of dies in mold compound nowadays. In addition, an additional optical asymmetrical correction function has been developed to compensate shifts of up to 50ppm in either X or Y. This paper will detail the principle and realization of this optical magnification correction technology. Performance data results for magnification error mitigation will be presented, and its effects on overlay, patterning performance, resolution, and throughput will be studied.
5G Systems and Packaging Opportunities
Authors: Sturdivant Rick 
Published: December 2018

Abstract
5G systems are being developed to meet the ever increasing desire for additional data bandwidth in mobile devices. Two enabling technologies for these systems are millimeter-wave electronics and phased arrays. Phased arrays have traditionally been used on military radar and satellite systems. However, they provide the capability to direct communication antenna beams directly to users or groups of users. In fact, standards committees agree that all network elements (including base stations, Access Points, and User Equipment) will be equipped with directional steerable antennas and can direct their beams in specific directions. In other words, phased arrays will be deployed at a variety of points in the 5G system even down to user equipment such as mobile phones, tablets, and lap tops. However, the components and modules used in 5G systems come with their unique packaging challenges. Those challenges will be described and some solutions will be given. 5G systems alternatives will also be described based on several architectures that are available for phased arrays. The two main reasons they are a challenge to package will be described. Several alternative solutions including heterogeneous packaging and 3D integration are described.
Cu diffusion into the glass under bias temperature stress condition for through glass vias (TGV) applications
Authors: Kim Hoon , Cai Ling , Fahey Albert , Vaddi Rajesh , Zhu Bin , Mazumder Prantik 
Published: December 2018

Abstract
For Through Glass Via (TGV) applications, significant copper migration in-between vias would result in failure of the device. The Cu migration occurs due to a combination of thermal and applied electrical field. Thus, it is critical to generate data of Cu diffusivity through glass as function of temperature and electrical field to determine whether a Cu diffusion barrier is required for this application. In this study, the Cu diffusion profiles in the Corning SG 3.4 glass, under varying electrical fields and temperature are evaluated. Using a planar capacitance test structure and a bias temperature stress test at elevated temperature, an Arrhenius plot of Cu diffusivity was obtained. Cu diffusion in the SG 3.4 glass has an activation energy of 1.1 eV which is in the range of thermal SiO2 and low-k of the references. Based on this Arrhenius plot, Cu diffusion depth at various combinations of operating temperatures and electrical fields can be determined. Based on the calculated diffusion lengths we infer that Cu diffusion barrier may not be required in most TGV applications.
Processing Through Glass Via (TGV) Interposers for Advanced Packaging
Authors: Woychik Charles , Lauffer John , Bajkowski David , Gaige Michael , Edwards Robert , Benninger Gordon , Wilson William 
Published: December 2018

Abstract
In recent years new applications for RF and MEMS devices require the insulating properties of glass. In order to realize these applications using a glass substrate, it becomes necessary to be able to deposit a metalized layer on both surfaces as well as create vias through the glass substrate. In this paper we will present results of glass interposers that have fine line circuitry on both sides of the substrate and that have through glass vias (TGVs). One major challenge is creating TGVs, using either electrically conductive adhesives (ECAs) or Cu plating methods, to achieve high conductivity and reliable via connections. In addition, it is important to have the capability to produce fine line metallization on the surface of the glass substrate. We employ a semi-additive plating (SAP) method to produce the fine line metallization. The combination of a robust process to create a TGV and the ability to use SAP to do fine line circuitry are the fundamental building blocks to generate advanced carriers for these new future electronic packaging applications.
Smart Passivation Materials with a Microencapsulated Liquid Metal for Self-Healing Conductors in Sustainable Electronic Devices
Authors: Chu Kunmo , Song Byong Gwon , Kim Yongsung , Lee Chang Seung 
Published: December 2018

Abstract
Passivation and self-healing of electric circuits are of importance in the area of electronic packaging for improving durability of devices. In particular, flexible or stretchable devices are vulnerable to mechanical stimuli, such as cutting, piercing, scratching, and pressing. The damage to a circuit results in the breakdown of devices. Therefore, a passivation layer has been essential to preserve the soft circuits and provide self-healing of the electrical pathways after they are damaged.
Evaluation of Low Cost, High Temperature Die and Substrate Attach Materials for Silicon Carbide (SiC) Power Modules
Authors: Seal Sayan , Passmore Brandon , McPherson Brice 
Published: December 2018

Abstract
The performance of SiC power devices has demonstrated superior characteristics as compared to conventional Silicon (Si) devices. Some of the advantages of SiC power devices over Si include higher voltage blocking capability, low specific on-resistance, high switching frequency, high temperature operation, and high power density. Thus, SiC modules are capable of processing significant levels of power within much smaller volumes compared with its Si counterparts. These high thermal loads present a formidable challenge in integrating SiC devices in power modules. For example, known-good materials and processes for silicon power modules are not rated at the aggressive operating conditions associated with SiC devices. Two of the most critical interfaces in a power electronics module are the die-attach and substrate- attach. A degradation in these interfaces often results in potentially catastrophic electrical and thermal failure. Therefore, it is very important to thoroughly evaluate die-attach materials before implementing them in SiC power modules. This paper presents the methodology for the evaluation of die attach materials for SiC power modules. Preforms of a lead-free high-temperature attach material were used to perform a die and substrate attach process on a conventional power module platform. The initial attach quality was inspected using non- destructive methods consisting of acoustic microscopy and x-ray scanning. Die attach and substrate attach voiding of &lt; 5% was obtained indicating a very good attach quality. Cross-sectioning techniques were used to validate the inspection methods. The initial attach strength was measured using pull tests and shear tests. The measurements were repeated at the rated temperature of the module to ensure that the properties did not degrade excessively at the service temperature. At the rated module temperature of 175 °C, the die bonding strength was found to be ~ 75 kg. This was only 25% lower than the strength at room temperature. In addition, the contact pull strength was measured to be &gt; 90 kg at 175 °C, which was 25% lower than the value measured at room temperature. The effect of power cycling and thermal cycling on the quality and strength of the die and substrate attach layers was also investigated.
Design and demonstration of Glass Panel Embedding for 3D System Packages for heterogeneous integration applications
Authors: Ravichandran Siddharth , Yamada Shuhei , Ogawa Tomonori , Shi Tailong , Liu Fuhan , Smet Vanessa , Sundaram Venky , Tummala Rao 
Published: December 2018

Abstract
This paper demonstrates a next generation high-performance 3D packaging architecture with smaller form factor, excellent electrical performance and reliability for heterogeneous integration. High density Logic-HBM integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are again limited by package size and ability to integrate many components. WLFO promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This paper presents the first demonstration of 3D Glass Panel Embedding (GPE) technology for high-performance large package applications involving heterogeneous integration. The tailorable CTE of glass allows a reliable direct board SMT of large GPE packages that not only benefits form factor and signal speed, but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump limited and can support BEOL-like I/O densities with Silicon-like RDL at much lower costs. The fundamental limitations like die-shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die-shift to &lt;2 um while also improving the RDL surface planarity for high-yielding fine-line structures. This paper describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40um I/O pitch while also enabling double-side assembly of chips to achieve 3 levels of device integration.
A Reusable 3D Printed Cavity Resonator for Liquid Sample Characterization
Authors: Karuppuswami Saranraj , Mondal Saikat , Ghazali Mohd Ifwat Mohd , Chahal Premjeet 
Published: December 2018

Abstract
In this paper, additive manufacturing (3D printing) is used to fabricate and demonstrate a reusable microfluidic coupled rectangular cavity resonator for characterizing liquids in small volumes. The designed cavity operates in the fundamental TE101 mode and resonates at 4.12 GHz. The resonance of the cavity is perturbed by the sample placed in a small volume sample holder through a slot in the top cover. Two different perturbation configurations are investigated: i) strongly coupled (liquids with low to medium dielectric constants), and ii) weakly coupled (liquids with medium to high dielectric constant). The sample holder is loaded with different solvents and the shift in the resonance frequency is monitored. Based on these changes, the dielectric constant of the solvent is theoretically estimated and compared to standard values. The reusable liquid sensor holds significant potential in identifying and quantifying unknown liquid samples in the supply chain.
Reversed Pulse Plating of Silver-Cobalt for Connector Applications
Authors: Dadvand Nazila , Dadvand Mina , Kipouros Georges 
Published: December 2018

Abstract
The manuscript describes the use of anti-galling silver-cobalt alloy as a novel metallic contact finish for connector applications. The purpose of this work was to develop a cost-effective and cyanide-free and self-lubricated silver-cobalt alloy deposited using reversed pulse electrodeposition process for silver-based contact finishes in electrical contacts applications. The manuscript describes a novel silver-cobalt alloy deposited through reversed pulse-electroplating process that provides exceptionally low friction coefficient (similar to hard gold) and outstanding wear resistance compared to standard silver and any commercially available electroplated silver alloys such as silver-tin, silver palladium, silver antimony, silver-bismuth, silver-tellurium, and silver-tungsten.
X-ray Advances in Support of Advanced Packaging – Today and Tomorrow
Authors: Bernard David 
Published: December 2018

Abstract
As advanced packaging continues to develop to support novel and emerging technologies, the need for, ideally non-destructive, test and inspection continues to be vital to ensure the quality and assurance of functionality, wherever the package may go. This is made ever more difficult as the package complexity increases, whilst the feature sizes within continue to decrease. X-ray technology has long been an important part of the non-destructive inspection protocol over the history of advanced packaging and will continue to need to play a more important part in the future. This paper will review the advances made in both 2D and 3D X-ray inspection over recent years and the new opportunities that are now starting to be available, especially in 3D, or CT, inspection, that will enable this 120-year-old technology to remain relevant to and supportive of the needs of advanced packaging.
To highlight the above, a case study will be presented on the faults that 2D and CT X-ray analysis can find in LEDs during their manufacture. LEDs are a good example of the remarkable developments in packaging and technology over the last 20 years, where the use of higher powers, smaller sized features and increased reliability requirements intensify the need for higher quality, more consistent production output. Flaws cannot be accepted, especially as higher usage powers mean higher operating temperatures which, in turn, then requires very good thermal conductivity in the package to move heat away from key areas. Without good heat dissipation then heat stresses at the interfaces can cause delamination or die fractures, so reducing LED lifetimes. The presence of voids, particularly at the die to package interface, creates air gaps that reduces heat transfer efficiency. As many LEDs are potted, or encapsulated, the only non-destructive test option to check for voiding and other faults is by using 2D and CT X-ray analysis.
Low Dk and Df Photosensitive Insulation Material for Low Transmission Loss Packages
Authors: Abe Shinichiro , Mitsukura Kazuyuki , Imazu Yuki , Toba Masaya , Masuko Takashi , Kurafuchi Kazuhiko 
Published: December 2018

Abstract
The interposer or fan-out packaging technology with ultra-fine line/space and high frequency signal has been required in order to achieve high speed interconnection between chips with low cost. In this paper, we have newly developed low Dk and Df photosensitive insulation material. The additional features of the developed materials are very low moisture absorptivity less than 0.3 wt%, low anion impurities and high resistance to hydrolysis. The micro-strip line was fabricated to evaluate the influence of developed material. The insertion loss from transmission lines on Material C shows much lower loss than the conventional reference material at higher frequencies. The peel strength to the sputtered Ti and Cu is over 0.7 kN/m. The material also demonstrated SAP fabrication compatibility with fine circuitry and passed insulation reliability by biased-HAST showing no copper migration measured by EDX.
Reliability of Novel Ceramic Encapsulation Materials for Electronic Packaging
Authors: Kaessner S. , Scheibel M.G. , Behrendt S. , Boettge B. , Nickel K.G. 
Published: December 2018

Abstract
Enhancements on power electronic systems with reduced chip area and miniaturized passive components are subject of several research activities in academics and industry. To realize such future electronic devices, it is necessary to incorporate wide bandgap semiconductor technology such as silicon carbide and gallium nitride operating at higher temperatures. Therefore, the development of novel materials with high thermal conductivities and stability, withstanding harsh environments up to 300°C is of major interest. Especially, polymeric encapsulation materials have to be improved because of common degradation effects above 175°C. Ceramic (nonpolymeric) materials with thermal conductivities above 5 W/(m·K) already illustrated promising results for the encapsulation of power electronics. The present work illustrates recent developments and improvements on novel ceramic encapsulation materials, which finally avoid critical interactions with the chip surface. Furthermore, advances in reliability will be discussed in terms of passed high-temperature reverse bias and humidity tests correlated with relevant material properties.
Advanced Packaging for Automotive Dashboard Application
Authors: Islam Nokibul , Choi HC 
Published: December 2018

Abstract
The current automotive market for the integrated circuit (IC) packaging industry has grown significantly due to the increasing need for automation and higher performance in vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting its focus to prioritize the development of advanced packages for next generation automotive market requirements.
Automotive IC's are traditionally wirebond packages. Due to the increasing complexity and higher performance requirements of automotive applications, the packaging industry is moving towards high performance flip chip packages for automotive infotainment, GPS, and radar applications. In this study, a comprehensive view of the evolving packaging landscape from traditional wirebond to flip chip interconnect to advanced fan-out wafer level packages will be discussed. The pros and cons of each packaging technology will be examined. Packaging roadmap details will be discussed along with assembly process information, determining the right bill of materials (BOM), and extensive package and board level reliability (BLR) including grade 1 and grade 0 reliability data will be discussed.
Novel Low Temperature Curable Photosensitive Negative-tone Polyimide with Higher Resolution and Reliability
Authors: Matsukawa Daisaku , Yotsuyanagi Hiroko , Sakakibara Shiori , Yamazaki Noriyuki , Enomoto Tetsuya , Motobe Takeharu 
Published: December 2018

Abstract
Hitachi Chemical DuPont MicroSystems (HDMS) has been developing photo sensitive negative-tone polyimides (PIs) as dielectrics for re-distribution layers (RDLs) in wafer level packages (WLPs) and as protection layers in semiconductor ICs. Photo sensitive negative-tone PIs can simplify the manufacturing process and ensure high reliability owing to their good mechanical properties, high thermal stability, and high electrical properties. On the other hand, since advanced packaging application such as Fan-Out WLP (FO-WLP) requires finer L/S design as well as higher reliability, lithographic performance of PIs has to be further improved and good cured film property should be achieved when cured at lower temperature (&lt;230 °C). In order to meet these requirements, HDMS started the development of new PI which shows enhanced lithographic performance with good film property.
In this paper, we will demonstrate our novel low temperature curable photo sensitive solvent developable negative-tone PI. By adopting a new photo-package to improve lithographic performance, this PI can achieve 3 μm via opening at 5 μm cured thickness and 5 μm via opening at 10 μm cured thickness with smooth pattern profile after cure. In addition, this PI shows good film property when cured at 200 °C and no electrical failure is observed during 300h bias-HAST using 2/2 μm L/S pattern.