bluuebunny/crossref_metadata_2025_split huggingface dataset:
PSMB11 Orchestrates the Development of CD4 and CD8 Thymocytes via Regulation of Gene Expression in Cortical Thymic Epithelial Cells
Authors: Apavaloaei Anca , Brochu Sylvie , Dong Mengqi , Rouette Alexandre , Hardy Marie-Pierre , Villafano Geno , Murata Shigeo , Melichar Heather J. , Perreault Claude 
Published: December 2018

Abstract
T cell development depends on sequential interactions of thymocytes with cortical thymic epithelial cells (cTECs) and medullary thymic epithelial cells. PSMB11 is a catalytic proteasomal subunit present exclusively in cTECs. Because proteasomes regulate transcriptional activity, we asked whether PSMB11 might affect gene expression in cTECs. We report that PSMB11 regulates the expression of 850 cTEC genes that modulate lymphostromal interactions primarily via the WNT signaling pathway. cTECs from Psmb11−/− mice 1) acquire features of medullary thymic epithelial cells and 2) retain CD8 thymocytes in the thymic cortex, thereby impairing phase 2 of positive selection, 3) perturbing CD8 T cell development, and 4) causing dramatic oxidative stress leading to apoptosis of CD8 thymocytes. Deletion of Psmb11 also causes major oxidative stress in CD4 thymocytes. However, CD4 thymocytes do not undergo apoptosis because, unlike CD8 thymocytes, they upregulate expression of chaperones and inhibitors of apoptosis. We conclude that PSMB11 has pervasive effects on both CD4 and CD8 thymocytes via regulation of gene expression in cTECs.
Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost
Authors: Hübner Henning , Ohde Christian , Ruess Dirk 
Published: December 2018

Abstract
Electrolytic metal deposition is a key process step in the manufacturing of vertical and horizontal interconnections used in today's PCBs and IC substrates on one hand and advanced packaging applications on the other hand. Historically both application areas were clearly defined and separated by different requirements in feature sizes and substrate formats. PCBs and IC substrates were based on organic large scale substrates with rather large features while advanced packaging technology is wafer based with the capability to incorporate fine features down to a few microns.
The ever increasing demand of higher performance, lower cost and thinner end user devices like smartphones require intense developments and innovation in all areas of the electronic component design including the substrate and chip packaging. Latest manufacturing technologies in both areas like fan-out wafer level packaging and advanced substrates are constantly emerging and promise to be a critical piece to meet these requirements. As a consequence both areas are currently merging while creating a new application segment. This segment combines the request of small feature sizes with the manufacturability on large scale substrates. Obviously many of the traditional process technologies like plating and available equipment cannot be easily adopted and need certain developments, adaptions and improvements.
In this respect, a key challenge in the area of electrolytic metal deposition is the combination of various challenging requirements: creation of feature sizes down to 2μm L/S with heterogeneous feature density on large substrates up to 600mm at excellent metal thickness uniformity and high plating speed. The paper presents latest studies and conclusions in critical performance areas of the plating process such as electrolyte fluid dynamics, impact of anode design, pulse reverse rectification and newly designed electrolytes. Finally latest test results of optimized process conditions will be discussed in detail with different feature sizes providing data of within die and within substrate uniformity. All tests are done on panel level, both organic and glass substrates.
The latest findings and achievements of the discussed panel based plating process technology will support the industry to develop panel based packaging processes that meet both technical and commercial requirements.
Converter-Level Integration for Wide Band-Gap Automotive Power Electronics
Authors: Johnson C Mark , Espina Jordi , Ahmadi Behzad , Dai Jingru , Mouawad Bassem , Empringham Lee , De Lillo Liliana , Dimarino Christina 
Published: December 2018

Abstract
Wide band-gap (WBG) semiconductors offer many potential benefits to designers of power electronic systems. Lower switching losses allow operation at higher switching frequencies, which in principle allows a reduction in passive component values in many converter applications. However, efficient operation at higher switching frequencies requires increased voltage and current transition rates. With conventional packaging and circuit construction, parasitic inductance and capacitance can deteriorate converter performance, reducing efficiency and adding to the electromagnetic interference (EMI) emitted from the system. Outside the commutation cell, fast voltage transitions may lead to unacceptably high levels of conducted and radiated EMI, so approaches involving the local filtering of converter outputs are attractive. To mitigate these effects in conventional modules, switching speeds are often deliberately limited and the potential benefits of using WBG technologies cannot be fully realized. Here we examine the design and realization of Converter-in-Package (CiP) modular blocks for system power levels from 100s W to 100s kW, incorporating individual commutation cells with close-coupled gate drives, input/output filtering and reduced EMI. The concept is illustrated through the realization of a modular, segmented power converter for an integrated drive.
Enabling a Robust Copper Seed Etch Process for Fine Line RDL by Electroplating on a Thin PVD Seed Layer
Authors: Bernt Marvin , Van Valkenburg Paul , Surdock David , Lianto Prayudi 
Published: December 2018

Abstract
Integration of heterogeneous chips into fanout packages requires interconnection by redistribution lines (RDL). As I/O counts increase, higher density routing is required, and can be achieved by finer RDL line/space dimension, stacking multiple RDL layers, or both. Conventional WLP plating processes for pillar or RDL use a PVD deposited copper seed layer between 1000 and 4000Å thick. Removal of this copper seed layer by isotropic wet etching leads to sidewall loss that can be ignored on larger features, but can lead to significant copper cross sectional area loss on features with 2/2μm line/space and below. By enabling plating onto much thinner seed layers, next generation WLP plating chambers enable a conventional copper seed layer etch process with less sidewall loss and more uniform cross-sectional area across plated features.
Fabrication of an advanced epoxy based molding compound with high thermal conductivity and outstanding mechanical properties
Authors: Dadvand Nazila , Dadvand Mina , Kipouros Georges 
Published: December 2018

Abstract
A novel molding compound was fabricated through surface modification of aluminum particles followed by chemical grafting to an epoxy based resin. The fabricated material demonstrated high thermal conductivity and outstanding mechanical properties. A thin layer of alumina was formed on the surface of aluminum particles (spherical with average 30 μm in diameter) by ultrasonic treatment with hydrogen peroxide followed by functionalization with a hydroxylated long-chain organic acid. The fabricated composite was chemically bonded to epoxy skeleton. The chemical bond formation between the filler and organic matrix was responsible for high thermal conductivity as well as outstanding mechanical properties. As well, the loading capacity of epoxy matrix to surface modified fillers was remarkably higher than non-modified fillers.
Reliability of an Electronic Product Fabricated of Mass-Produced Components
Authors: Suhir E. 
Published: December 2018

Abstract
Bathtub curve (BTC), the reliability “passport” of an electronic product, is affected by two major irreversible processes: the decreasing with time statistics-related failure rate (SFR) process and increasing with time physics-of-failure-related failure rate (PFR) process. The first process dominates at the infant-mortality portion (IMP) of the curve and the second one – at its wear-out portion (WOP). For many electronic products these two processes compensate for each other at the BTC's steady-state portion. The SFR process can be predicted theoretically for products comprised of mass-produced components, i.e., for typical electronic products. This could be done assuming that the failure rates of the components received by an electronic product manufacturer from various and numerous vendors can be viewed as random variables distributed between zero and infinity and that the SFR and PFR processes are statistically independent. The predicted non-random SFR depends, of course, on the particular probability distribution function (PDF) of the random SFRs of its components. Two PDFs for the components' random SFR have been considered in this analysis: normal (Gaussian) and Rayleigh. The normal law turned out to be more conservative: it led to a slower decrease in the SFR of the product than the Rayleigh law. Future work should include the investigation into the most realistic distributions of the random SFR for the most critical and the most vulnerable components obtained from major vendors of the particular manufacturer, particular products and applications. The computed data indicate that the decrease in the resulting failure rate at the WOP of the BTC because of the favorable effect of the decrease of the non-random SFR with time can be appreciable for highly reliable products expected to function for a long time.
Warpage Behaviors of System-in-Packages on a Substrate Strip
Authors: Ouyang Eric , Ahn Billy , Gu SeonMo , Hsu Jim , Jeong Yonghyuk , Kim JaeMyong , Lin Susan , Liu Goran , Yang Anthony 
Published: December 2018

Abstract
In this paper, the impact of two different types of warpage, strip warpage and system-in-packages (SiP) module warpage, are considered and studied, both experimentally and numerically. An advanced material characterization method is also conducted to study the curing reaction and Pressure-Volume-Temperature-Cure (PVTC) kinetics of the packages. The curing reaction of epoxy resins, as a function of temperature and activation energies, is experimentally determined. During the curing process, the viscosity of epoxy resins change with temperature and conversion rate. The Castro-Macosko model is adopted to describe the rheological properties of epoxy resins. Experimentally, we have prepared substrate strip samples with different component density and molding compound materials. Each substrate strip contains eighteen system-in-packages. The warpages of all substrate strips and all the system-in-package modules were measured, compared, and correlated.
Mixed-Port Hybrid Parameters for High-Speed Differential Lines
Authors: Engin A. Ege , Ndip Ivan , Lang Klaus-Dieter , Aguirre Jerry 
Published: December 2018

Abstract
High-speed transmission lines are commonly routed as differential lines to control sensitivity to noise on the reference planes at higher speeds. The preferred method of characterization of differential lines is in terms of mixed-mode scattering parameters, as they provide insight into the behavior of differential and common signals, as well as the mode conversion among them. These mixed-mode scattering parameters can be mathematically obtained from single-ended parameters, which can for example be measured with a 4-port vector network analyzer. There has been recent concerns about the so-obtained mixed-mode scattering parameters, especially for tightly-coupled lines, resulting in extended or modified definitions of mixed-mode scattering parameters. This can be a point of confusion in interpreting the behavior of differential lines. In this paper we introduce the mixed-port hybrid parameters, which do not suffer from any such ambiguous definitions, as they are based on intuitive differential and common-port excitations of the network. As such, mixed-port hybrid parameters can be used to analyze the mixed-mode performance of any arbitrary 4-port network, certainly including coupled or asymmetrical lines, without any ambiguity.
BATCH MICROWAVE PLASMA CLEANING FOR ROBUSTNESS ENHANCEMENT OF AUTOMOTIVE DEVICES: AN ALTERNATIVE TO STRIP-TYPE RADIOFREQUENCY PLASMA
Authors: Abarro Ghizelle Jane E. , Delos Santos Rod J. , Denoyo Alvin B. , De Lazo Darwin , Ramos Manny S. 
Published: December 2018

Abstract
This study attempts to explore Batch-type Microwave (B-MW) plasma cleaning as a potential alternative to the conventional Strip-type Radiofrequency (S-RF) plasma; for application prior molding to improve adhesion along the mold-lead frame interface. Performance of B-MW was evaluated in terms of improvement in surface wettability, quantified via Contact Angle (CA) measurements. Mix of typical industrial plasma gases (Ar, H2 and O2) were assessed. Constant flow pattern was observed to significantly improve surface wettability and uniformity compared to its pulsed counterpart; and also affect the effect of other factors on the over-all cleaning performance of B-MW. Proceeding with constant flow pattern, surface wetting was found to improve with increasing power and cleaning time. The combination of O2 and H2 plasma was found to be more effective compared to utilizing them separately. Both cleaning time and flow rate increased the amount of reactive species that come in contact with the contaminants. With optimized parameters, B-MW was confirmed to be a more effective plasma method than S-RF i.e. 12% more effective in removing contamination and improving surface wettability, up to 20% better uniformity and can boost throughput to at least 34%.
New Photosensitive Dielectric Material for High-Density RDL with Ultra-Small Photo-Vias and High Reliability
Authors: Okamoto Daichi , Shibasaki Yoko , Shibata Daisuke , Hanada Tadahiko 
Published: December 2018

Abstract
This paper presents an advanced ultra-thin photosensitive dielectric Film (PDM) newly developed with high resolution, low CTE and low residual stress for next-generation high-density redistribution layer (RDL), 2.5D interposer, and high-density fan-out package applications. For high-density RDL, photosensitive dielectric materials need to have low CTE to achieve high package reliability. The CTE of the material is 30–35ppm/K. While maintaining the low CTE, we successfully demonstrated the minimum micro-via diameter of 3um in the 5um thickness. Curing temperature of the PDM is 180°C × 60 min. which is lower than most of the advanced dielectric materials which currently used in industry. Low-temperature curing process results in low stress. We have calculated residual stress in the cured PDM from a test result of warpage measurement on 4 inch wafer. As another benefit of the PDM material in curing process, the PDM can be cured in air oven. Most of advanced photo dielectric materials need to cure in N2 oven due to prevent an oxidation of the material. We have demonstrated copper traces of 2um lines and spaced on the PDM by using semi-additive process (SAP) with sputtered Ti/Cu seed layer. Thanks to the low CTE and low residual stress due to the low-temperature curing, it passed temperature cycle test (1,000 cycles) with daisy chain structure which has 400 vias in the structure. It can be concluded that the newly developed PDM is a promising dielectric material for highly reliable high-density redistribution layer (RDL) for 2.5D interposers and fan-out wafer level package applications.
Photosensitive Polyimide having low loss tangent for RF application
Authors: Tomikawa Masao , Araki Hitoshi , Kiuchi Yohei , Shimada Akira 
Published: December 2018

Abstract
Progress of 5G telecommunication and mm radar for autopilot, high frequency operation is required. Insulator materials having low loss at high frequency is desired for the applications. We designed the low dielectric constant, and low dielectric loss materials examined molecular structure of the polyimide and found that permittivity 2.6 at 20GHz, dielectric loss 0.002. Furthermore, in consideration of mechanical properties such as the toughness and adhesion to copper from a point of practical use. Dielectric properties largely turned worse when giving photosensitivity. To overcome the poor dielectric properties, we designed the photosensitive system. After all, we successfully obtained 3.5 of dielectric constant and 0.004 of dielectric loss, and 100% of elongation at break. In addition, we offered a B stage sheet as well as varnish. These materials are applicable to re-distribution layer of FO-WLP, Interposer and other RF applications for microelectronics.
Novel Low Temperature Curable Photo-Patternable Polyamide with High Planarity for Wafer Level Fan-Out Packaging (WLFO)
Authors: Nawrocki Daniel , Cooper Andrew , Koizumi Takanori , Inagaki Shinya , Kawamoto Naoki , Honda Nao , Markt Kristina , Bernal Milton 
Published: December 2018

Abstract
As Wafer Level Fan-Out Packaging (WLFO) designs continue to evolve, higher pattern densities for Cu lines and interconnects continue to increase while thickness continues to decrease. As Cu densities increase, the patterning resolution of the RDL dielectric needs to shrink to allow increased bump density. The higher Cu density in turn requires enhanced dielectric performance to minimize Cu migration, whilst utilizing lower temperature and shorter cure times which result in lower levels of wafer warpage.
Minimizing mechanical stress, continues to be a critical function of the RDL dielectric. Warpage leads to poor yields, distorting the planarity of the package and ultimately leading to stress induced failure from cracking and delamination. Reduction of the thermal budget is the primary means of reducing mechanical stress in WLFO designs. The amount of Cu in the package continues to increase. Differences in thermal expansions of such and the dielectric increase with temperature. Further, conventional solder reflow processes and set points will continue to be used, therefore the RDL dielectric must continue to be thermally and mechanically stable but capable of being cured at lower temperatures, 180–200 °C to minimize overall mechanical stresses from thermal expansion.
We present a novel polyamide based RDL dielectric, KMRD, designed to achieve current and future WLFO design requirements. KMRD is a low temperature curable, aqueous (2.38%TMAH) developable dielectric capable of meeting industry standards for mechanical and electrical requirements, with a high level of reliability while utilizing a single stage cure at 185 °C. KMRD provides clear advantages over incumbent materials, with low temperature cure, improved pattern resolution, wide process latitudes, superior adhesion, chemical compatibility, and cost benefits using standard processing equipment and chemistry.
A study of Sub-micron Fan-out Wafer Level Packaging solutions
Authors: GOTO Yoshio , URUSHIHARA Kosuke , TAKESHITA Bunsuke , MORI Ken-Ichiro 
Published: December 2018

Abstract
In Fan-out Wafer Level Packaging (FOWLP) processes, redistribution layer (RDL) line width reduction is a key challenge to expand the FOWLP market to multi-chip interconnections, including interconnections between SoC and DRAM, split-die connection of FPGA, and interconnections between image sensors and SoC. Next generation FOWLP requires 1.0 μm RDL and future FOWLP is targeting 0.8 μm RDL. To meet these requirements, Canon has developed new projection optics with a high NA and wide-field that is best suited for sub-micron FOWLP. These projection optics are a new option for FPA-5520iV steppers, offering NA 0.24 imaging and a 52 × 34 mm exposure field. FPA-5520iV steppers with NA 0.24 provide excellent 0.8 μm resolution performance throughout all imaging fields thanks to Canon's wave-front aberration based projection optics manufacturing methods and on-axis optical tilt focus sensor.
Flexible PET Substrate for High Definition Printing of Polymer Thick Film Conductive Pastes
Authors: Dobie Art 
Published: December 2018

Abstract
A major obstacle in screen printing conductive low temperature curing polymer thick film (PTF) pastes onto common flexible PET substrate materials is the substantial spread of the pastes beyond the designed line width after printing. Industry observation and controlled testing have shown this spread can be as much as 80% over the circuit design's intended line width. This phenomenon prevents designers from increasing circuit density and/or reducing circuit real estate without incorporating other, more involved and higher cost patterning methods. In many cases, flexible circuit fabricators, desiring more accurate high definition circuit elements, may have to subcontract parts out of house in order to incorporate alternate patterning methods. In-turn this subcontracting leads to a loss of control of both cost and lead time.
This paper will provide results of numerous in-house and field testing, comparing printed line width control, edge definition, and improved conductivity of printed polymer Ag conductors on different flexible PET substrates.
Wire Bonding Advances for Multi-Chip and System in Package Devices
Authors: Xu Hui , Shah Aashish , Milton Basil , Qin Ivy 
Published: December 2018

Abstract
Wire bonding continues to be the most commonly used interconnection technology due to its low cost, high yield rate, increased flexibility and improved reliability. Among wire bonded packages, the high growth areas include Multi-Chip modules and System in Package (SiP) applications. A type of wire bonding, Stand-Off-Stitch Bond (SSB), is widely used in Multi-chip, die-to-die, SiP and light-emitting diodes (LEDs).
The SSB process starts with a flat-topped bump bonding on the substrate or die, followed by the formation of a new ball bond (1st bond). The stitch bond (2nd bond) of that wire is bonded on top of the initial bump. This paper focuses on key SSB process steps, by examining the main challenges and solutions of SSB applications. We demonstrate ultra-fine pitch SSB process capability with 0.6 mil Au wire using newly developed response-based processes for sub-20 nm node wafer technology.
Investigation of a proactive glass filler removal in IC substrate build up films and its effect on topography and copper adhesion reliability
Authors: Kempa Stefan , Friz Wolfgang , Gaul Florian , Habig Ellen , Gregoriades Laurence J. 
Published: December 2018

Abstract
In order to achieve interconnections at extremely small scale, the latest build up laminates contain increasing amounts of spherical glass fillers, which are needed to compensate the CTE mismatch between the epoxy based resin matrix and the electroplated copper circuits. Desmear of the resin surface during industrial processing exposes these glass fillers and weakens their anchoring in the surrounding resin matrix, which decreases adhesion strength of the plated copper.
We describe a newly developed cleaner process for the removal of glass fillers in industrially important build-up materials. Its effects on cleanliness and copper to resin adhesion is described in detail and illustrated by SEM imaging. Finally we propose a mechanism, explaining the adhesion increase as compared to standard processing and fluoride etch treatment.