bluuebunny/crossref_metadata_2025_split huggingface dataset:
Versatility of Fan Out – Simple 2D to Complex 3D
Authors: Hunt John 
Published: June 2019

Many mobile applications strive for the thinnest package possible, and therefore benefit from the high density of basic Fan Out technology. At the same time, Fan Out has evolved from a simple, single die packaging solution into a high-density solution enabling more complex 2D and 3D connectivity.
Fan Out first went into volume manufacturing in 2009 with a simple, single die package using eWLB. For the next few years, it was only thought of in this context. Then in 2016, two packages came into production that broke this stereotype. The first was a hybrid, very high-density Fan Out combined with a BGA package called FOCoS for server applications. The second was a 3D PoP structure for mobile cellular phone applications called InFO. With these structures, Fan Out became a more versatile tool, capable of wider applicability. And since then, multiple manufacturers have continued the evolution of Fan Out's capabilities into more and more packaging opportunities.
This presentation will illustrate how the integration of a wide variety of packaging technologies, wafer level processing, substrate evolution and Flip Chip packaging have all come together into both simple and complex packages structures. We will further explore the higher levels of integration and sophistication available using Fan Out as a basic manufacturing technology, describing the evolving functionality and complexity achieved by combining low cost materials and innovative process flows. By using such combinations of tools and processes, the resulting packages are only limited by our imagination and creativity.
Temporary and permanent bonding enables 3D integration of ultrathin wafers
Authors: Brandl Elisabeth , Uhrmann Thomas , Pires Mariana , Jung Stefan , Burggraf Jürgen , Koch Matthew 
Published: June 2019

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes.
The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened.
For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.
Development of High Density RDL Technologies for Panel Level Processing
Authors: Böttcher Lars , Karaszkiewicz S. , Schein F. , Kahle R. , Ostmann A. 
Published: June 2019

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix.
At first dies with Cu pillar structures are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15 μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305×256mm2 panel format, aiming for a final size of 610×615 mm2. On the top side of embedded chips, a 20μm dielectric film is applied. The goal is to avoid additional via formation and to realize a direct connection between the Cu pillar of the die and the RDL
The RDL formation is based on semi-additive processing. Therefore a Ti or TiW barrier and Cu seed layer is sputtered. Subsequently a 7μm photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were achieved with high yield. In the following, Cu is simultaneously electroplated for the via contacts and interconnects traces.
Finally, the photo resist is stripped and the TiW barrier and Cu seed layers are etched.
The goal of the development is to provide a technology for a high-density RDL formation on large panel sizes.
The paper will discuss the new developments in detail, e.g. the influence of most significant process parameters, like lithographical resolution, minimum via diameter and the placement and alignment accuracy on overall process yield.
Ultra-low Warpage and Anhydride-free Liquid Compression Molding Materials for Advanced Semiconductor Packaging
Authors: Champagne Tim , Chao Jay , Tanaka Kazuyasu , Trichur Ramachandran , Zhang Rong 
Published: June 2019

Advanced semiconductor packaging landscape is rapidly evolving to accommodate requirements of front end node shrink and performance expectations from emerging applications in big data, artificial intelligence, mobile and autonomous driving. Multiple innovations in packaging process technology as well as processing materials enable the progress in advanced packaging. Several wafer level packaging (WLP) platforms have emerged recently using fan-in, fan-out, 2.5D and 3D packaging processes to satisfy the requirements of increased functionality, reduced form factor, lower power consumption, and high reliability. These often-conflicting requirements drive the design and development of many new electronic materials including liquid compression molding (LCM) for Fan-In and Fan-Out WLPs. Historically, anhydride-based LCM materials have been used to balance the material properties to achieve consistent dispensability, high quality molding, and high mechanical stability during grinding, RDL, and singulation processing. However, stricter environmental regulations driven by EU REACH stipulates complete replacement of anhydride resins with more environmentally friendly raw materials while still providing the same or better performance.
Most recently, Henkel has developed new platforms of anhydride-free LCM materials with reduced cure shrinkage, ultra-low warpage, good chemical resistance, and high reliability. LCM material choice is integral to the package design and end use as this material needs to withstand several thermal, mechanical, chemical and vacuum processes during the construction of the package and stringent reliability conditions. By judicious construction of the polymer network, appropriate filler selection, and controlled cure kinetics design, the cure shrinkage and warpage were significantly reduced over other designs.
Furthermore, the low warpage stability of the molded wafer is maintained through post-mold curing, PI simulation, and RDL simulation process steps ultimately leading to improved reliability performance. Compared to traditional anhydride-based LCM, our reliability data (after 96 hours of uHAST & 1000 cycles of AATC) clearly indicates performance advantages of no filler-fall-off, no delamination, and better chemical resistance. In terms of workability, the new system shows improved work-life, fast-cure at 110–130°C, and complete gap filling. Lower die shift, good mold release, and improved tape debonding has also been observed through formulation and process optimization. Taking advantage of the proprietary resin and formulation design, Henkel's new LCM materials are delivering positive results in new FO-WLP designs and WLCSP applications needing 5-side or 6-side protection.
The bifurcation of advanced packaging
Authors: Park John 
Published: June 2019

Following a similar trend from the 1990's, IC package design is experiencing a sea change. As a refresher, the 1990's is when the ball grid array (BGA) came along, introducing a whole new set of design tool requirements. The mechanical design tools used for the previous generation of lead frame styled packages were no longer capable of supporting the new design requirements of the BGA. In short, the BGA introduced multi-layer routable organic and ceramic substrates and new possibilities for stacking (and embedding) multi-die, requiring designers to abandon their mechanical design tools and look at new solutions for doing package design. On top of that, IO's were switching faster than ever, requiring engineers to look at new ways of electrically characterizing these designs.
As a result, a couple of EDA companies stepped up and adapted their printed circuit board (PCB) layout and analysis tools for that generation of BGA-based advanced packaging. Problem (more or less) solved!
Fast forward to today and we see a very similar trend. Now being introduced at a rapid pace, are new advanced IC packaging solutions that have a lot more silicon content, wafer stacking and, in some cases, chips being packaged directly at the wafer-level at traditional IC foundries, skipping the traditional OSAT model of the past. Make no mistake, this is a significant change to the status quo of BGA package design tools of the past. The PCB-like flows that were established for BGA design are likely not the path forward for technologies like, 2.5D/3D IC and fan-out wafer-level packaging (FOWLP). Instead, in all likelihood IC design tools and flows will need to be slightly adapted to support the next generation of package designs.
Let's start with foundry-based FOWLP. In this case, induvial dice are placed on a chip-carrier with additional spacing between them. Molding is poured in the empty space and then an array of bumps (UBM) and the connectivity (RDL) are added. In foundry-based flows, these UBM and RDL layers require IC-styled routing/metal fill and mask generation from the layout tool. In addition, these masks must be verified with traditional IC DRC/LVS tools. It's clear that some kind of hybrid advanced packaging flow using some traditional IC tools in the flow is required to support this type of design. And in fact, if you look at the largest semiconductor foundries reference flow tools, you will find this to be true.
This presentation further examines the design tool/flow requirement for FOWLP, 2.5D/3D IC and future multi-die packaging technologies.
Design, Processes & Technology Co-design Methodology
Authors: Peng Diane , Tabrez Baqar 
Published: June 2019

Costs, design complexity and manufacturing risks are creating opportunities with a rapid convergence of the traditional IC design and IC package design processes. For the goal of achieving the electrical (SI/PI) performance requirements of a complex SoC design, choices of package technology, impact of material selection, process flow optimization are critical factors with increasing challenges to overcome.
We have undertaken a co-design methodology to optimize the IC chip layout and substrate design to streamline assembly processes while assimilating the physical and logical interactions within each design domain. We have optimized the die top-level/RDL layout & pattern, defined bump placement & structures for the current density, established electrical constraints for critical nets, applied PG supply strategy, and facilitated routings in the package thereby mitigating assembly risks.
To streamline the design and development process, we have employed simulation tools for a thorough evaluation of electrical, mechanical and thermal performance to identify the areas of enhancing the packaging assembly processes:Cadence XtractIM and Ansys SIwave to assess current density and electrical performance on the combo of die + package.Ansys mechanical to understand the underlying assembly issues such as stress induced to die and bumps.Mentor Graphics Flotherm to evaluate the thermal performance per the different die thickness and bump stackup.
Using simulation results as the guideline, we have defined and conducted DOEs focusing on bump structures and stackup, die thickness, substrate stackup, assembly mold processes (CUF vs MUF), die placement and configuration, and low CTE material selection to mitigate underlying assembly issues and refine the assembly recipes. We have gained a thorough understanding of dependency factors on the assembly manufacturing processes and parameters in each DOE to finetune and finalize the assembly PORs for the advanced package technology. The refined assembly recipes have delivered the robust package performance and reliability for high volume production.
Microbump Processing for 3D IC Integration
Authors: Li Feng , Owens Andrew W. , Li Qianyi 
Published: June 2019

In recent years, the development of microbumps has allowed even smaller sizes of ICs to utilize the flip chip technique. In addition, microbumps have enabled the implementation of three-dimensional (3D) ICs, which drastically improve the spatial efficiency of packaging. However, as the bumps size decreases and the number increases, several process challenges must be considered, for example, the height consistency of bump, the ratio of miss and deformity bump and the yield and strength of interconnection, etc. Therefore, it is increasingly important to study the interconnection technology and materials of high-density microbump interconnection.
After briefly introducing the common electronic packaging techniques, including wire bonding, tape-automated bonding and flip chip, this paper reviews microbumps as an advanced bonding technology. Techniques such as Controlled Collapse Chip Connection - New Process(C4NP), printing, insert bump bonding, and self-replication process are discussed and compared. C4NP can achieve low-cost, fine pitch bumping by utilizing varied lead-free solder alloys, which overcomes the limitation of existing bumping technologies. Depending on the microbump size, engraved mask stump, and photosensitive organic mask and squeegee are the two ways for micro-bump printing. The micro-insert bump bonding process is new to stack chips vertically, which has robust bonding structure and a simpler bonding process compared to Cu pillar bonding process. The self-replication process is using the surface tension property of molten solder between the micro bridged bump to get two bumps with same volume and geometries on each faced pairs of lands. The use of two common material for the microbump, Cu, Sn, and its alloys are presented along with the differences in the process for each.
As with any technology, a new breakthrough addressing an issue brings with it its own set of shortfalls. Microbumps are no different. The various techniques and materials used to realize the reduced scale bonding method are subject to a number of challenges. Most prominent among them are electromigration, thermomigration, and thermallyinduced mechanical fatigue, which are discussed in this paper.
Additive Manufacturing of Dielectric Microstructures
Authors: Christenson Kurt 
Published: June 2019

Additive, printed, 3D electrical traces are needed to achieve the desired advances in packaging. Recent advances in silver inks in some cases provide resistivities of 2× bulk silver (3.2E-6 Ohm-cm) when sintered at 120 C, and laser sintering can provide similar performance on substantially room-temperature substrates. Compared to wire bonds, printed traces have smaller heights (no loops) and the trace cross sections can be tailored to carry larger currents. In RF applications, printed traces can be shorter, have lower inductance and crosstalk, and be shaped to form substantially impedance-matched connections.
Additive dielectric microstructures are often required to support the additive printing of conductors on 2.5D and 3D electronic structures. For example:A fillet, or at minimum a wall coating, is needed on the conductive sidewall of an unpackaged IC die that is to be connected to an underlying PCB by a printed trace. Large fillets (ca 350 um) are needed on typical single die, &lt;50 um fillets on stacks of thinned die, and &lt;20 um fillets are needed on flexible die.Filling the inter-die gap is necessary when interconnecting closely spaced die.Filling the gap between the substrate dielectric and die is needed when the die is mounted in a cavity in the substrate. Cavity mounting is sometimes used when the floor of the cavity is a thick metal layer that acts as both a ground plane and a heat sink.
Dual-cure (UA and/or heat) resins are desirable for creating microstructures as the resins can be “pinned” in-situ to create structures that would normally be impossible due to the flow of the resin. A secondary heating step is normally used to cure any areas shadowed from the UV. These resins can shrink on curing by as much as a few percent causing delamination from underlying structures or stress in the final parts. Much like applying multiple thin coats of paint to avoid the cracking that results from applying one thick coat, applying multiple thin coats of dielectric with simultaneous UV or UV exposure between the coats allows the polymer to be deposited with low stress and without delamination. For example, a method for creating fillets around thick die by multiple layering has been described by Hines et al. It is also possible to create structures with low-shrinkage/CTE materials, but these materials are often compromised in other metrics.
Creating micro dielectric structures by conventional syringe dispense methods is difficult due to the size of currently used dispense needles. Even the 190 um OD of a 34 ga needle, which is too small to be used with filled resins, is poorly suited to forming 45-degree fillets on a stack of 35 um-tall die. This work discusses some of the practical aspects and results of creating these micro dielectric microstructures and printed traces using Aerosol Jet® technology.
Intertrial Rest for Maximum Grip and Key Pinch Strength in Japanese Young Adults
Authors: Kurosaki Masaki , Momose Kimito 
Published: June 2019

Abstract
OBJECTIVE. This study investigated the most appropriate intertrial rest period for maximum grip and key pinch strength measurements involving three trials.
METHOD. The study included 40 male and 40 female participants. Using a repeated-measures design, six intertrial rest periods—15 s, 30 s, 60 s, 90 s, 120 s, and 150 s—were investigated, one per day on 6 different days.
RESULTS. A repeated-measures analysis of variance or Friedman test found significant decreases in grip and key pinch strength over the three trials in all test conditions. However, for both hands, only small differences were observed in test conditions (≥90 s, male grip; ≥60 s, female grip; male and female key pinch; effect sizes of &lt;0.5).
CONCLUSION. If a rest of ≥150 s is not possible, 90 s of rest between trials for grip strength and 60 s of rest between trials for key pinch strength can be considered.
The TRIple-frequency and Polarimetric radar Experiment for improving process observations of winter precipitation
Authors: Dias Neto José , Kneifel Stefan , Ori Davide , Trömel Silke , Handwerker Jan , Bohn Birger , Hermes Normen , Mühlbauer Kai , Lenefer Martin , Simmer Clemens 
Published: June 2019

Abstract. This paper describes a 2-month dataset of ground-based triple-frequency (X,
Ka, and W band) Doppler radar observations during the winter season obtained
at the Jülich ObservatorY for Cloud Evolution Core Facility (JOYCE-CF),
Germany. All relevant post-processing steps, such as re-gridding and offset and
attenuation correction, as well as quality flagging, are described. The
dataset contains all necessary information required to recover data at
intermediate processing steps for user-specific applications and corrections
(https://doi.org/10.5281/zenodo.1341389; Dias Neto et al., 2019). The large number of ice clouds included in the dataset
allows for a first statistical analysis of their multifrequency radar
signatures. The reflectivity differences quantified by dual-wavelength ratios
(DWRs) reveal temperature regimes where aggregation seems to be triggered.
Overall, the aggregation signatures found in the triple-frequency space agree
with and corroborate conclusions from previous studies. The combination of
DWRs with mean Doppler velocity and linear depolarization ratio enables us to
distinguish signatures of rimed particles and melting snowflakes. The riming
signatures in the DWRs agree well with results found in previous
triple-frequency studies. Close to the melting layer, however, we find very
large DWRs (up to 20 dB), which have not been reported before. A combined
analysis of these extreme DWR with mean Doppler velocity and a linear
depolarization ratio allows this signature to be separated, which is most likely
related to strong aggregation, from the triple-frequency characteristics of
melting particles.
Weaving a Map of “Global” Empire: The Second-Century BCE Origins of Mediterraneanism
Authors: Davies Sarah H. 
Published: June 2019

ABSTRACTThe debated term “Mediterranean” has been variously understood as a modern construct, a “politics of knowledge,” and/or a zone of community or conflict. This article argues that such polyvalence can be traced back to the second century BCE. During this period, and in Polybius' Histories, a teleological understanding of world power was evolving, one that labeled Rome as an inevitably superior focal point of a Mediterranean-centered “oikoumenē.” Geographic determinism combined with a language of cultural capital to weave a new map of the “inhabited world,” according to which “global” time and space unified along the spine of an “Our Sea.”