bluuebunny/crossref_metadata_2025_split huggingface dataset:
Experiential Learning at Scale with Computer-Based Roleplay Simulations
Authors: Kok Bethany E , Dagger Declan , Gaffney Conor , Kenny Austin 
Published: December 2018

<p class="0BodyText">Experiential learning is an effective method for changing behavior and teaching new material at work. Unfortunately, experiential learning is difficult to deliver at scale as it requires hands-on participation and interactivity.</p><p class="0BodyText">EmpowerTheUser (ETU)’s computer-based roleplay simulations enable experiential learning at scale. In a simulation, learners take on a role and have to react to various situations and make choices that have downsteam consequences. ETU Simulations engage the learner in cycles of assessment and practice, with summative scoring in the assessment mode and real time coaching and feedback in the practice mode. </p><p class="0BodyText">ETU partnered with one of the oldest custodian banks headquartered in New York to deliver a series of three simulations on risk management to nearly 6,000 managers on five continents. User feedback shows that learners are highly satisfied with the program. Performance improved from simulation I to simulation II, indicating transfer of learning. Underperforming learners were remediated using the assess/practice/assess learning loop, resulting in a 227% improvement in performance.</p><p class="0BodyText">EmpowerTheUser Simulations provided fast, consistent training in risk management. Feedback was overwhelmingly favorable and decision tracking within the simulations demonstrated effective learning.</p>
Deviser les merveilles du monde
Authors: Collet Hadrien 
Published: December 2018

Ibn Baṭṭūṭa, « le voyageur de l’Islam », a narré ses aventures dans sa relation de voyage, baptisée la Riḥla. La question semble entendue. Pourtant, une étude attentive du contexte de production de l’œuvre conduit à réévaluer la lecture habituelle qui l’a accompagnée depuis au moins l’époque moderne. La Tuḥfat al-nuẓẓār fī ġarāʾib al-amṣār wa-ʿaǧāʾib al-asfār, titre authentique du livre, écrite à quatre mains, propose un récit polymorphe construisant un monde structuré autour de la manifestation d’une typologie de merveilles et de la civilisation universelle apportée sur terre par l’islam. Dans cette perspective, nous procédons à une relecture de la riḥla sūdāniyya, le voyage au sultanat du Mali, à la lumière du projet littéraire et de l’économie de l’œuvre.
L’esprit des lieux
Authors: Caiozzo Anna 
Published: December 2018

La cosmographie est un genre littéraire qui fleurit dans le monde musulman médiéval entre le xiie et le xve siècle, mais les copies illustrées valorisent surtout les versions de ʿAǧāʾib al‑maḫlūqāt d’al-Qazwīnī en arabe et en persan, tandis que la cosmographie d’al-Ṭūsī Salmānī, plus diversifiée pour l’aspect monumental, est malheureusement plus rare, voire unique par son exemplaire jalayride de la BnF. La représentation des curiosités des pays peut aussi s’observer dans d’autres corpus tels que les manuscrits de Firdawsī ou de Niẓāmī. Les merveilles des lieux offrent une vision du monde marquée par le mystère, l’enchantement, le poids de la magie mais aussi des signes divins. Les illustrations insistent sur trois aspects principaux, la nature enchantée, les curiosités des pays construites par les hommes ou de mystérieux acteurs, et enfin les lieux de culte, de l’Inde à la Méditerranée offrant une panoplie des différentes religions du monde connu.
La suppression de l’impôt de solidarité sur la fortune : réforme économique ou idéologique ?
Authors: Merle Pierre 
Published: December 2018

L’année 2018 se caractérise par la suppression de l’impôt de solidarité sur la fortune. Cette réforme fiscale majeure est censée favoriser l’investissement, la croissance économique et l’emploi. L’analyse socio-économique ne valide ni les effets négatifs attribués à cet impôt, ni les effets positifs associés à sa suppression. La taxation de la richesse n’est pas seulement une question économique et fiscale. Elle exerce aussi des effets sur la répartition des pouvoirs et l’organisation politique.
“A Cross-Domain, System Planning Methodology”
Authors: ACITO Bill 
Published: December 2018

Abstract
Through several decades of electronic product design, three high-level design domains have emerged; IC (SoC) design, package (SiP) design and board (PCB/PWB) design. These three domains are separated and somewhat isolated, based on the EDA tools they use and by domain expertise. In many cases, the design tools come from 2 or 3 different EDA companies, leading to limited or no methods of sharing design data across the three domains.
This typically leads to an “over-the-wall” design approach, resulting in downstream layout complexities for the package and board design teams, requiring domain expertise (human in the loop) in these design domains. Typically, this high-level of complexity occurs because the package substrate and board form-factor are not planned and optimized in context of the IC(s). Thus, the automation of these layouts becomes nearly impossible and tremendous human interaction (domain expertise) is the only way to complete the designs cost-effectively. Moreover, this methodology directly impacts time-to-market and results in products that do not live up to cost or performance expectations.
Recess in the motherboard architectures for small form factor systems
Authors: Swettlen Tim , Landeros Juan , Mokler Scott , Caputo Antonio 
Published: December 2018

Abstract
This paper details an architecture that includes a recess in motherboard (RiMB) to enable increased packaging density of functional components for next generation mobile personal computing products. The recess depth, manufacturing methods, and SMT assembly data are included to provide the reader with a full overview of the manufacturing and assembly challenges.
Universal Connection Matrix: A Breadboard in a Package
Authors: Welsh Erik , Frantz Gene , Murtuza Masood 
Published: December 2018

Abstract
Process improvements driven by Moore's Law have created disparate processes for different best-in-class components, such as analog sensors, digital processors, RF electronics, and power electronics. Therefore, it becomes impossible to integrate all components of a system into a single System-on-Chip (SoC) giving rise to System-in-Package (SiP) devices which integrate multiple components together at the package level. However, traditional SiP devices are monolithic systems that have a fixed design and require a large investment to update or modify. To avoid the fixed nature of SiP devices and improve the ability to prototype with SiP technology, this paper presents the Universal Connection Matrix (UCM), a breadboard in a package.
Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration
Authors: Ko Cheng-Ta , Yang Henry , Lau John , Li Ming , Li Margie , Lin Curry , Lin JW , Chang Chieh-Lin , Pan Jhih-Yuan , Wu Hsing-Hui , Chen YH , Chen Tony , Xu Iris , Lo Penny , Fan Nelson , Kuah Eric , Li Zhang , Tan Kim Hwee , Lin Chia-Hung , Beica Rozalia , Lin Marc , Xi Cao , Lim Sze Pei , Lee NC , Tao Mian , Lo Jeffery , Lee Ricky 
Published: December 2018

Abstract
The design, materials, process, and fabrication of a heterogeneous integration of 4 chips by a FOPLP (fanout panel-level packaging) method are investigated in this study. Emphasis is placed on (a) the application of a dry-film EMC (epoxy molding compound) for molding the chips, and (b) the application of a special assembly process called Uni-SIP (uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508mm × 508mm. The package dimensions of the FOPLP are 10mm × 10mm. The large chip size and the small chip sizes are, respectively 5mm × 5mm and 3mm × 3mm.
Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging
Authors: Hanna Amir , Alam Arsalan , Ezhilarasu G. , Iyer Subramanian S. 
Published: December 2018

Abstract
A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrateTM) was used to assemble 625 dies with co-planarity and tilt &lt;1μm, average die-shift of 3.28 μm with σ &lt; 2.23 μm. Fine pitch interconnects (40μm pitch) were defined using a novel corrugated topography to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then used to interconnect 200 dies, and then tested for cyclic mechanical bending reliability and have shown less than 7% change in resistance after bending down to 1 mm radius for 1,000 cycles.
Power cycle tests of high temperature Ag sinter die-attach on metalized ceramic substrate by using micro-heater SiC chip
Authors: Kim Dongjin , Nagao Shijo , Wakasugi Naoki , Yamamoto Yasuyuki , Suetake Aiji , Takemasa Tetsu , Suganuma Katsuaki 
Published: December 2018

Abstract
Next generation power semiconductors, e.g. SiC and GaN, are emerging for the further minimization and high current/voltage of power devices with high reliability covering wider operating environments than those based on Si. To implement high reliability operation, the key technology is the control of the temperature distribution in the module, and thermal stress caused by the heat generated by power loss. In the present study, we have developed SiC micro-heater chip with temperature probe to evaluate thermal characteristics of an assembled system of Ag sinter die-attach on metalized ceramic substrate (Cu/Si3N4/Cu) during the repetitive power cycling. The test specimens were fixed on a water cooling system, and steady-state heat resistance of the system was measured during the power cycling. For comparison, Pb-Sn, Sn-Cu-Ni-P, Sn-Ag-Sb-Cu solders were used as die-attach material bonded on the same metalized ceramic substrates. The maximum applied power exceeds 200 W with cycles of 2 seconds of heating and 5 seconds of cooling, and the test cycles was over 5000 cycles. The power cycle number dependence on the temperature swing and thermal resistance characteristics would be discussed, in connected with the power cycle testing for real power devices.
Molding Recipe Study for MUF Solder Crack Improvement
Authors: Chen Scott , Liang Leander , Hsu Pallas , Tsai Tim , Liang Mason , Shy Michael 
Published: December 2018

Abstract
In recent years, flip chip technology becomes more and more important with benefits of thin package profile, reduction of package outline, and excellent electrical and thermal performance by connection of copper pillar bumps (CuP) or C4 solder bumps. In order to fill the die gap to prevent voids problem, two encapsulated solutions could be applied: capillary underfill (CUF) and molded underfill (MUF). In general comparison, CUF means to dispense underfill first to fill in die gap then proceed over-molding afterward; and MUF is directly fill under and above die by mold compound. The advantages of MUF solution are low cost and high throughput, however, it will suffer other assembly issues such as solder extrusion and solder crack, and might result in potential function failure. To form these kinds of defects, we suspected that solder will plastically deform under thermal stress treatment, which comes from unbalance mold transfer pressure and material expansion stress during thermal process. In this article, we have tried to investigate the mechanism of solder crack through molding recipe DOE (Design of Experiment) and mold flow simulation. The test vehicle is 12 × 12 mm2 FCCSP, with 6 × 5 mm2 die size. The bump type is copper pillar bump and pitch/size are 126 um and 35 × 60 um2, respectively. The molding recipe has been evaluated by cross section, and it revealed that molding transfer time and molding temperature are directions toward improvement of solder crack issue.
Understanding Mold Compound Behavior on Flip Chip QFN Packages
Authors: Camenforte Ruby Ann M. , Colte Jason , Sumalinog Richard , Sanchez Sylvester , Williamson Jaimal 
Published: December 2018

Abstract
Overmolded Flip Chip Quad Flat No-lead (FCQFN) is a low cost flip chip on leadframe package where there is no need for underfill, and is compatible with Pb free or high Pb metallurgy. A robust leadframe design, quality solder joint formation and an excellent molding process are three factors needed to assemble a high performance FCQFN. It combines the best of both wirebonded QFN and wafer chip scale devices. For example, wafer chip scale has low resistance, but inadequate thermal performance (due to absence of thermal pad), whereas wirebonded QFN has good thermal performance (i.e., heat dissipated through conductive die attach material, through the pad and to the board) but higher resistance. Flip chip QFN combines both positive aspects – that is: low resistance and good thermals.
One of the common defects for molded packages across the semiconductor industry is the occurrence of mold voiding as this can potentially affect the performance of a device. This paper will discuss how mold voiding is mitigated by understanding the mold compound behavior on flip chip QFN packages. Taking for example the turbulent mold flow observed on flip chip QFN causing mold voids. Mold compound material itself has a great contribution to mold voids, hence defining the correct attributes of the mold compound is critical. Altering the mold compound property to decrease the mold compound rheology is a key factor. This dynamic interaction between mold compound and flip chip QFN package configuration is the basis for a series of design of experiments using a full factorial matrix. Key investigation points are establishing balance in mold compound chemistry allowing flow between bump pitch, as well as the mold compound rheology, where gelation time has to be properly computed to allow flow across the leadframe.
Understanding the flow-ability of mold compound for FCQFN, the speed of flow was optimized to check on its impact on mold voids. Mold airflow optimization is also needed to help fill in tighter bump spacing but vacuum-on time needs to be optimized as well.
FCCSP IMC Growth under Reliability Stress follow Automotive Criteria
Authors: Liu (Xenia) Wei-Wei , Weng Berdy , Li Jerry , Yeh CK 
Published: December 2018

Abstract
The kirkendall void had been a well-known issue for long term reliability of semiconductor interconnects, while even the KVs existing at the interfaces of Cu & Sn, it may still be able to pass the condition of un-bias long term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000hrs of high temperature storage. A large numbers of KVs was observed after 200cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 & Cu layers. These kinds of voids will growth proportional with the aging time at initial stage, but slowing down attribute to the barrier layer of Cu3Sn & Cu interfaces. This paper compare various IMC thickness as a function of stress test, the Cu3Sn & Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture.
The Effect of Nickel Oxidation Formed in the Interface of ENEPIG Structure for Flip Chip Technology
Authors: Chuang Chuan Lung , Shu Min-Fong , Tseng Yi-Hsiu 
Published: December 2018

Abstract
In flip chip assembly, the smaller solder ball is used in chip and substrate joint. This may have an adverse influence on the reliability of electronic products. Thus, the mechanical strength of solder joint is an important topic for the major reliability in electronic assembly technology. We found the intermetallic compound (IMC) crack issue for Electroless Ni(P) / Electroless Pd(P) / Immersion Au (ENEPIG) Interposer product. In this study, we analyzed the failure samples, for ENEPIG processes verified to find out the IMC crack root cause. The interposer pad structure for these samples was manufactured by ENEPIG process, in which the formation of the oxidation layer is affected by the duration that the sample is exposed on top of Ni bath. These samples print solder paste were performed multi-times reflow for ENEPIG and solder interfacial reaction observation to clarify the nickel oxidation influence on crack issue. These samples were observed and analyzed by Scanning Electron Microscope (SEM), Focused Ion Beam (FIB), Transmission Electron Microscope (TEM), and Energy-Dispersive X-ray Spectroscopy (EDX). The interface strength between ENEPIG and solder were tested by hot bump pull test (HBP), and also has the adhesion analysis. The results show that with the shorter exposure on top of nickel bath is no nickel oxidation formed and the interface has a higher pull strength, with a longer exposure on top of nickel bath had more nickel oxidation formed in the ENEPIG interface and also reveal lower pull strength. Therefore, the IMC crack was induced by the void at ENEPIG interface, which was the reaction of nickel oxidation and Au chemical, and the control of the exposure time on top of nickel bath can inhibit the oxidation formation to reduce the IMC crack risk.
Result of high accelerated stress test of organic substrates made by integrated dry process
Authors: Habu Tomoyuki , Endo Shinichi , Yabu Shintaro 
Published: December 2018

Abstract
The uses of the semiconductor increase by the development of Internet of Things. Miniaturization of the semiconductor wiring to bring speedup, electric power saving advances, and various technologies are developed. The new technology that applied a semiconductor production technology is waited eagerly for the production of the printed circuit board and semiconductor packaging. We presented new dry process “Integrated dry process” using Photodesmear technology and sputter seed process in IMAPS2016 Pasadena. After the micro via formation with the laser, the smear is effective to remove a smear remaining behind in the via bottom by Photodesmear. Furthermore, we improved adhesion between copper metal and epoxy resin in a sputtering seed together. We made the large experimental tool that Photodesmear could process an actually size of the print circuit board by static irradiation. And we proved that handling of panel size was technically possible. The connection reliability of the contact via is evaluated after electric copper plating by quick via peel examination. A cross section of the vias was made and, the residual smear removal properties of wet desmear processing and the Photodesmear processing were compared with the residual smear and the thin oxidation layer by observation of the connection interface. The interfacial surface state after the desmear processing was analyzed in X-ray probe analyzer. We produced the test vehicle using Photodesmear technology and a sputtering seed technology. I compared it with the same pattern sample produced by a process conventionally. In this paper, we report the result of the high accelerated temperature and humidity stress test.
System Co-Design Modeling Methodology of a High Speed (25Gbps) Multi-Rate 4-Channel Retimer: Simulation to Measurement Correlation
Authors: Tang Tony , Wray Bridger , Murugan Rajen 
Published: December 2018

Abstract
In this paper we detail the system (viz. silicon-package-pcb) electrical co-design of a 130nm BiCMOS high-speed (25Gbps) 4-channel multi-rate retimer, packaged in a small 6-mm × 6-mm FC BGA package, with integrated advanced signal conditioning circuitries. Electrical optimization of the silicon-package-pcb over the high speed channels, to achieve desired performance, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation methodology. Key figure of merits for system electrical performance (viz. insertion loss, return loss, crosstalk/isolation, jitter, and power supply inductance and resistance parasitics, among others) are modeled and analyzed. Laboratory measurements on a retimer are presented that validate the integrity of the modeling methodology. Good correlation between modeling methodology and laboratory measurements is achieved.
A Systematic Approach to the Reliability Characterization of System in Package (SiP)
Authors: Dhandapani Karthikeyan , Roggeman Brian , Rae David 
Published: December 2018

Abstract
System-in-Package (SiP) solutions are gaining popularity across multiple market segments, dually reducing product design complexity for Original Equipment Manufacturers (OEMs) while increasing system performance and functionality. For SiP customers, product design complexity is reduced with the integration of electrical sub-system functionality into a module that can be designed into a product with relative ease. Further, logistical complexity is reduced, with the supplier carrying responsibility for the sub-system's quality and reliability. In addition, OEMs benefit from the performance, functionality and form factor improvements enabled by advanced SiP packaging and substrate technologies. With the increased responsibility of SiP solutions in mind, the authors addressed a systematic approach and methodology to understand the complexity of thermo-mechanical risk and challenges in SiP solutions. A modeling and characterization methodology was used to systematically identify and mitigate reliability risks for system-in-package SiP modules. Specifically, a combination of Shadow-Moire technique, digital image correlation (DIC), reliability testing and finite element (FE) models were used to demonstrate this upstream thermo-mechanical evaluation for SiP Solutions. Empirical warpage trends for the SiP module and solder joint fatigue failure trends were in close agreement with the model output based upon design and material factor inputs to the FE models.