bluuebunny/crossref_metadata_2025_split huggingface dataset:
High Aspect Ratio Vertical Bipolar Junction Transistor NPN Device Fault Isolation and Analysis Techniques
Authors: Distelhurst Kevin , Bader Dan 
Published: October 2021

Abstract
Analog components are still an important aspect of our society's electronic portfolio. They play a role in the emerging and expanding 5G electronic industry, for instance. NPN bipolar junction transistors (BJTs) are the foundation of many analog circuits and have continually evolved to meet more demanding specifications. Certain embodiments of these NPNs, however, pose difficulties in failure analysis. Vertical NPN BJTs, with nanometer thick junctions extending several microns in length, are one such example. Although the high aspect ratio dimensions of these devices provide desired performance improvements, a subtle nanometer-scale defect anywhere along their length can cause electrical shifts detrimental to analog circuits. This paper examines the nature of these defects and explains how to isolate them using common failure analysis tools and special techniques.
EC-Seg: Electronic Component Segmentation for PCB Assurance and Counterfeit Avoidance
Authors: Sathiaseelan Mukhil Azhagan Mallaiyan , Agrawal Sudarshan , Vutukuru Manoj Yasaswi , Asadizanjani Navid 
Published: October 2021

Abstract
PCB assurance currently relies on manual physical inspection, which is time consuming, expensive and prone to error. In this study, we propose a novel automated segmentation algorithm to detect and isolate PCB components called EC-Seg. Component segmentation and localization is a vital preprocessing step in the automation of component identification and authentication as well as the detection of logos and text markings. As test results indicate, EC-Seg is an efficient solution to automate quality assurance toolchains and also aid bill-of-material (BoM) extraction in PCBs. It also has the potential to be used as a region proposal algorithm for object detection networks and to facilitate sensor fusion involving artifact removal in PCB X-ray tomography.
Failure Localization Techniques for 7nm and 16nm Process Nodes in Monolithic and 2.5D SSIT Packages using OBIRCH, LVP, and Advanced Die Thinning
Authors: Nuez Daniel , Tan Phoumra , Lu Daisy , Zhang Benhai , Miller Joshua , Lynaugh Mark , Harper Tom , DiBattista Michael , Silverman Scott 
Published: October 2021

Abstract
Sub-nanometer fabrication processes and advanced packaging solutions such as 2.5D stacked silicon interconnect technology (SSIT) facilitate the production of high-performance ICs, but make physical failure analysis and debugging more difficult. For example, at 16nm, most diagnostic tools reach their limitations in terms of spatial resolution and signal sensitivity and require complex modifications and adjustments. In addition, a higher level of precision and uniformity is required for sample preparation. This paper describes a fault isolation technique that combines solid immersion lens (SIL) technology with precision die thinning. Two failure analysis case studies are presented to demonstrate the method, one a low level negative current leakage failure caused by ESD testing, the other a scan chain failure traced to the input of a delay buffer circuit. In both cases, success is attributed to the resolution and sensitivity of the SIL lens and the ability to precisely control die thickness.
Heterogeneous Industry Collaboration and System CAD Navigation for Advanced Package Failure Analysis
Authors: Bhattacherjee Arpan , Shankar Anand , Singh Arshdeep , Singla Mehak 
Published: October 2021

Abstract
The emergence of heterogenous integration driven by system-in-package (SiP) technology not only increases the complexity of semiconductor failure analysis, but also makes it more difficult to protect intellectual property because of the growing need to share design information to facilitate fault isolation in assembly and test. One way to address these challenges is through a computer-aided design (CAD) database that can be navigated across multiple components without exposing sensitive information. This paper describes the development and use of such a resource and how it enables safe and secure data sharing among supply chain partners.
Thickness Control and Targeting in Large Scale Automated XTEM Lamella Preparation
Authors: Dixit Vikas , Gauntt Bryan , Lee Taehun 
Published: October 2021

Abstract
The automation of TEM imaging and lamella preparation using focused ion beam (FIB) technology has gained significant momentum, particularly in the development of microprocessors. A key requirement of automating TEM sample preparation is ensuring consistent thickness control and accurate targeting of features of interest in the ultra-thin lamella. This work examines the factors that impact both metrics. It explains how FIB pattern calibration requires milling to be divided into steps to minimize the effects of drift, how the height of the protective cap on the ion-beam tip influences sample thickness, and how FIB aperture erosion has little impact on lamella thickness until it reaches a certain point where the lamella profile cannot be reliably maintained. It was also found that the tail of the ion beam remains invariant during aperture degradation in the operable range and that it plays a prominent role in determining the cross-sectional thickness of the TEM lamella.
Accurate Sub-micron Device Delayering of Plan View TEM Specimens By Ar Ion Milling
Authors: Bonifacio C.S. , Nowakowski P. , Li R. , Ray M.L. , Fischione P.E. 
Published: October 2021

Abstract
This paper describes an accurate and controllable delayering process to target defects in new materials and device structures. The workflow is a three-step process consisting of bulk device delayering by broad Ar ion beam milling, followed by plan view specimen preparation using a focused ion beam, then site-specific delayering via concentrated Ar ion beam milling. The end result is a precisely delayered device without sample preparation-induced artifacts suitable for identifying defects during physical failure analysis.
Quantitative Study of Photoelectric Laser Stimulation for Logic State Imaging in Embedded SRAM
Authors: Chef S. , Chua C.T. , Tay J.Y. , Gan C.L 
Published: October 2021

Abstract
The use of optical techniques for attacking integrated circuits (ICs) is increasingly being reported, particularly the nefarious extraction data from embedded SRAM. Such attacks can provide access to highly sensitive information such as encryption keys and bypass various security measures. Attackers usually exploit one of several interactions between light and semiconductors to generate logic-state images that reflect data in memory. Thermal laser stimulation (TLS) and laser probing via electro-optical frequency mapping (EOFM) have been reported in the literature, but photoelectric laser stimulation (PLS) gets little attention. Considering the potential advantages of PLS over other techniques (e.g., less power is required to generate current-voltage changes and the effect can be triggered at shorter wavelengths, which can lead to improved spatial resolution), the authors set out to determine if logic state images can be generated from various types of devices with PLS and assess the strengths and limitations for each case. The results of the investigation are presented in this paper.
Low Angle Annular Dark Field Scanning Transmission Electron Microscopy Analysis of Phase Change Material
Authors: Li J. , Brew K. , Cheng K. , Chan V. , Arnold N. , Gasasira A. , Pujari R. , Demarest J. , Iwatake M. , Tierney L. , Ogundipe O. , Toole K. , Li N. 
Published: October 2021

Abstract
In this work, we investigate mushroom type phase-change material (PCM) memory cells based on Ge2Sb2Te5. We use low-angle annular dark field (LAADF) STEM imaging and energy dispersive X-ray spectroscopy (EDX) to study changes in microstructure and elemental distributions in the PCM cells before and after SET and RESET conditions. We describe the microscope settings required to reveal the amorphous dome in the RESET state and present an application example involving the failure analysis of a PCM test array made with devices fabricated at IBM’s Albany AI Hardware Research Center.
Application and Optimization of Automated ECCI Mapping to the Analysis of Lowly Defective Epitaxial Films on Blanket or Patterned Wafers
Authors: Han Han , Hantschel Thomas , Lagrain Pieter , Porret Clement , Loo Roger , Baryshnikova Marina , Kunert Bernardette , Strakos Libor , Vystavel Tomas 
Published: October 2021

Abstract
Although the physical limits of CMOS scaling should have been reached years ago, the process is still ongoing due to continuous improvements in material quality and analytical techniques. This paper describes one such technique, electron channeling contrast imaging (ECCI), explaining how it is used to analyze nanoscale features and defects. ECCI allows for fast, nondestructive characterization and has the potential for extremely low detection limits. The detection of low-level defects requires measurements over large areas (usually with the help of automation) to obtain statistically relevant data. For example, automated ECCI mapping routines have been shown to quantify crystal defect densities as low as 1 x 105 cm-2 in epitaxially grown Si0.75Ge0.25. The paper presents various methods to reduce measurement time without compromising sensitivity. It also explains how the mapping routine can be optimized to detect extended crystalline defects in III/V layers, selectively grown on shallow trench isolation patterned Si wafers.
Accelerate Your 3D X-ray Failure Analysis by Deep Learning High Resolution Reconstruction
Authors: Gu Allen , Andreyev Andriy , Terada Masako , Zee Bernice , Mohammad-Zulkifli Syahirah , Yang Yanjing 
Published: October 2021

Abstract
3D X-ray tomography plays a critical role in electronic device failure analysis, but it can take several hours to overnight to get sufficient resolution in fault regions to detect and identify defects. In this paper, we propose a machine learning based reconstruction technique that can speed up data acquisition by a factor of four or more, while maintaining image quality. The method, which uses neural networks, extracts signals from low-dose data more efficiently than the conventional Feldkamp-Davis-Kress (FDK) approach, which is sensitive to noise and prone to aliasing errors. Several semiconductor packages and a commercial smartwatch battery module are analyzed using the new technique and the results compared with those obtained using conventional methods. The neural network can be trained on as little as one tomography image and the only requirement for the training data is that the sample or region of interest is well represented with all characteristic features in the field-of-view.
SCM Application and Failure Analysis Procedure for Ion-Implantation Issues in Power Devices
Authors: Ho Kuang-Tse , Li Cheng-Che 
Published: October 2021

Abstract
This paper discusses the steps involved in the failure analysis of power semiconductor devices in which leakage currents are observed and can be traced to doping-profile variations in ion-implanted layers. The discovery and assessment of such defects takes knowledge and skill in sample preparation, fault isolation, and the use of advanced inspection techniques, particularly scanning capacitance microscopy, as explained in the paper. Several diodes, MOSFETs, and IGBTs were examined using the proposed approach and the results are presented along with SCM images showing incomplete and poorly shaped ion-implanted structures determined to be the root cause of failure in each case.
SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data
Authors: Kim Hyungtae , Kim Geonho , Li Yunrong , Jeong Jinyong , Kim Youngdae 
Published: October 2021

Abstract
This paper presents a fast and accurate method for identifying defects responsible for SRAM bitcell failures. The steps involved in the process include functional testing, current-voltage measurements, and defect classification based on electrical failure analysis data. The entire procedure takes less than two hours and works for both hard and soft defects as well as reliability failures. A case study is included in the paper to demonstrate the efficiency of the nondestructive technique.
FA Approach on MIM (Metal-Insulator-Metal) Capacitor Failures
Authors: Lee Kuang Shien , Kuan Lai Khei 
Published: October 2021

Abstract
Defects associated with metal-insulator-metal (MIM) capacitor failures can be difficult to locate using conventional fault isolation techniques because the capacitors are usually buried within a stack of back-end metal layers. In this paper, the authors explain, step by step, how they determined the cause of MIM capacitor failures, in one case, in an overvoltage protection device, and in another, a high-speed digital isolator circuit. The process begins with a preliminary fault isolation study based on OBIRCH or PEM imaging followed by more detailed analyses involving focused ion beam (FIB) cross-sectioning and delayering, micro- or nano-probing, resistive or voltage contrast imaging, and other such techniques.
Universal Application of Load Board (L/B) and Socket with Direct Current Tester (DCT) for Various Packages
Authors: Lin Yi-Sheng , Hsiao Yu-Hsiang , Tseng Pei-Yu , Chang Yu-Jen , Liu Cheng-Hsin , Lin Yu-Ting 
Published: October 2021

Abstract
This paper discusses the development of an electrical failure analysis workflow that uses a multifunction direct current tester (DCT) to map the location of defects associated with open and short circuits as well as leakage current. It explains how software and tooling were designed to accommodate a wide range of package types and sizes and how they were verified by testing. It also presents two case studies showing the accuracy of the defect mapping function for sockets with 0.8 and 1.0 mm ball pitch.
Commonality Analysis for Multiple Chain Integrity Failures
Authors: Merassi Angelo Antonio , Medda Matteo 
Published: October 2021

Abstract
This paper presents an alternative approach for analyzing complex scan chain failures in which there are multiple candidates that could be the root cause. It demonstrates the approach on an automotive IC with several failing flip-flops. An analysis of the interconnections shared by the failing devices reveals a common clock branch where the root cause is likely to reside. Photo-emission microscopy (PEM) is then used to verify the existence of a defect which, based on passive voltage contrast, is determined to be an open path.
Non-Visual Defect Identification by Dopant Analysis Method in FinFET Devices
Authors: Son Seungjun , Penley Christopher , Hurst Jeffrey , Michon Chris , Guo Yong , Lainez Rafael , Reifsnider Jason 
Published: October 2021

Abstract
This paper explains how tunneling atomic force microscopy (AFM) was used to determine the cause of leakage in FinFETs along the boundary of SRAM cells. The leaking devices were electrically isolated using photoemission microscopy, but conventional FA techniques, including SEM and TEM imaging, found no structural abnormalities. Suspecting that the failures may be due to dopant-related issues, the authors obtained cross sections of both good and bad devices and scanned them in a tunneling AFM. The paper describes the sample preparation process and includes cross-sectional images showing the difference between good and bad transistors. In SRAM areas where no leakage occurred, the fins are well defined and evenly spaced. However, in the area where an emission spot was observed, two of the fins appear to be overlapping, the result of n-well implants that merged.
Wafer Pattern Recognition for Detecting Process Abnormalities in NAND Flash Memory Manufacturing
Authors: Choe Jeongin , Kim Taehyeon , Yoon Saetbyeol , Yoon Sangyong , Song Ki-Whan , Song Jai Hyuk , Kim Myungsuk , Choi Woo Young 
Published: October 2021

Abstract
We have adopted various defect detection systems in the front stage of manufacturing in order to effectively manage the quality of flash memory products. In this paper, we propose an intelligent pattern recognition methodology which enables us to discriminate abnormal wafer automatically in the course of NAND flash memory manufacturing. Our proposed technique consists of the two steps: pre-processing and hybrid clustering. The pre-processing step based on process primitives efficiently eliminates noisy data. Then, the hybrid clustering step dramatically reduces the total amount of computing, which makes our technique practical for the mass production of NAND flash memory.
Dielectric Film Thickness Measurement Via a Convolutional Neural Network for Integrated Circuit Delayering End Point Detection
Authors: Scholl Jonathan , Darby Nick , Baur Josh , Patel Yash , Boona Isabel , Wickey Kurtis , Schley Jeremiah 
Published: October 2021

Abstract
Integrated circuit (IC) delayering workflows are highly reliant on operator experience to determine processing end points. The current method of end point detection during IC delayering uses qualitative correlations between the thickness and color of dielectric films observed via optical microscopy. The goal of this work is to quantify this relationship using computer vision. As explained in the paper, the authors trained a convolutional neural network to estimate the thickness of dielectric films based on images and measurements recorded during processing. The trained vision model explained 39% of the variance in dielectric film thickness with a mean absolute error of approximately 47 nm. The paper describes the entire workflow, including verification testing, and addresses the primary sources of error.
Focused Ion Beam (FIB) for Chip Circuit Edit and Fault Isolation
Authors: Herschbein Steven , Tan Shida , Livengood Richard , Wong Michael 
Published: October 2021

Abstract
This presentation introduces the practice of focused ion beam (FIB) chip editing and its power and versatility as a problem-solving tool. It begins with a review of the features and functions of FIB systems, the role of gas chemistry in milling, etching, and deposition, and the use of IR imaging for navigation and targeting. It goes on to identify challenges due to packaging materials, chip-package interactions, and other factors, and in each case, provide alternate approaches and procedures to circumvent potential problems. It also covers advanced practices and methods and assesses potential future advancements.
Failure Analysis Techniques for 3D Technology
Authors: De Wolf Ingrid , Jacobs Kristof J.P. 
Published: October 2021

Abstract
This presentation provides an overview of the tools and techniques that can be used to analyze failures in semiconductor devices made with 3D technology. It assesses the current state of 3D technology and identifies common problems, reliability issues, and likely modes of failure. It compares and contrasts all relevant measurement techniques, including X-ray computed tomography, scanning acoustic microscopy (SAM), laser ultrasonics, ultrasonic beam induced resistance change (SOBIRCH), magnetic current imaging, magnetic field imaging, and magneto-optical frequency mapping (MOFM) as well as time domain reflectometry (TDR), electro-optical terahertz pulsed reflectometry (EOTPR), lock-in thermography (LIT), confocal scanning IR laser microscopy, infrared polariscopy, and photon emission microscopy (PEM). It also covers light-induced voltage alteration (LIVA), light-induced capacitance alteration (LICA), lock-in thermal laser stimulation (LI-TLS), and beam-based techniques, including voltage contrast (VC), electron-beam absorbed current (EBAC), FIB/SEM 3D imaging, and scanning TEM imaging (STEM). It covers the basic principles as well as advantages and limitations of each method.
STEM-in-SEM: From Basic Imaging to Rigorous Quantitative Analysis
Authors: Holm Jason 
Published: October 2021

Abstract
This presentation covers the principles of STEM-in-SEM technology and its application in materials research and failure analysis. Part 1 describes the arrangement and function of major components in TEM-in-STEM systems, compares and contrasts imaging modes, and explains how different types of images are obtained by adjusting imaging parameters. Part 2 covers the implementation and use of 4D STEM-in-SEM. It provides examples showing how the method is used to examine diffraction patterns, capture images of materials susceptible to low-energy beam damage, and produce nanoscale strain, grain orientation, and temperature maps. It also includes a wide range of images obtained using a programmable STEM detector.
Цифровізація розвитку міст: Urban Atlas на основі відкритих даних для міст України
Authors: Шелестов Андрій Юрійович , Лавренюк Алла Миколаївна , Яйлимов Богдан Ялкапович , Яйлимова Ганна Олексіївна 
Published: October 2021

Ukraine is an associate member of the European Union and in the coming years it is expected that all data and services already used by EU countries will be available to Ukraine. The lack of quality national products for assessing the development and planning of urban growth makes it impossible to assess the impact of cities on the environment and human health. The first steps to create such products for the cities of Ukraine were initiated within the European project "SMart URBan Solutions for air quality, disasters and city growth" (SMURBS), in which specialists from the Space Research Institute of NAS of Ukraine and SSA of Ukraine received the first city atlas for the Kyiv city, which was similar to the European one. However, the resulting product had significantly fewer types of land use than the European one and therefore the question of improving the developed technology arose. The main purpose of the work is to analyze the existing technology of European service Urban Atlas creation and its improvement by developing a unified algorithm for building an urban atlas using all available open geospatial and satellite data for the cities of Ukraine. The development of such technology is based on our own technology for classifying satellite time series with a spatial resolution of 10 meters to build a land cover map, as well as an algorithm for unifying open geospatial data to urban atlases Copernicus. The technology of construction of the city atlas developed in work, based on the intellectual model of classification of a land cover, can be extended to other cities of Ukraine. In the future, the creation of such a product on the basis of data for different years will allow to assess changes in land use and make a forecast for further urban expansion. The proposed information technology for constructing the city atlas will be useful for assessing the dynamics of urban growth and closely related social and economic indicators of their development. Based on it, it is also possible to assess indicators of achieving the goals of sustainable development, such as 11.3.1 "The ratio of land consumption and population growth." The study shows that the city atlas obtained for the Kyiv city has a high level of quality and has comparable land use classes with European products. It indicates that such a product can be used in government decision-making services.