bluuebunny/crossref_metadata_2025_split huggingface dataset:
L’héritage conservateur du néolibéralisme
Authors: Beddeleem Martin , Colin-Jaeger Nathanaël 
Published: January 2021

Les années 1930 et 1940 marquent une période de crise pour le libéralisme. Des auteurs aussi divers que Friedrich Hayek, Wilhelm Röpke, Walter Lippmann ou encore Michael Polanyi et Louis Rougier se réunissent lors de deux événements fondateurs, le colloque Walter Lippmann en 1938 et la création de la Société du Mont-Pèlerin en 1947, pour repenser le libéralisme. Cette refonte du projet libéral les pousse à établir un diagnostic relatif à la crise du libéralisme, remontant, pour les auteurs mentionnés, à la Révolution française. Cet article se propose de montrer la cohérence du projet néolibéral à partir de leur diagnostic historique dans cette période de crise. En effet, en critiquant la Révolution française et ses effets comme participant d’un rationalisme néfaste, ayant donné naissance aussi bien au laissez-faire qu’aux divers collectivismes, les néolibéraux reprennent explicitement des concepts des critiques de la révolution, au premier rang desquels Edmund Burke. Le concept de tradition, compris comme recouvrant des règles sociales et juridiques ayant lentement évolué de façon à constituer des dispositifs de coordination permettant nos actions, est ainsi très largement repris et valorisé par les néolibéraux. Nous interprétons ainsi la théorie néolibérale à partir de cette recatégorisation du concept de tradition, et pointons les affinités des positions néolibérales avec le conservatisme philosophique. Ce rapprochement fait apparaître plusieurs tensions conceptuelles entre d’une part un évolutionnisme culturel et d’autre part la défense de valeurs occidentales substantielles.
Solder Joint Reliability Modeling of WLP and FOWLP with Crack Path Evaluation Method under Thermal Cycling
Authors: Kim Dae-Suk , Dhandapani Karthikeyan 
Published: January 2021

Abstract
An updated solder joint reliability (SJR) modeling methodology under thermal cycling (TC) is proposed and implemented for the diagonal solder crack path case as well as the SJR correlation of wafer-level package (WLP) and fan-out wafer-level package (FOWLP) data, which have the conventional solder failure mode around the under-bump metallization (UBM). First, two critical element layers near by the UBM layer and the printed circuit board (PCB) Cu pad are defined as the percentage of the total solder height in order to differentiate the critical element size around the UBM and the PCB Cu pad. Secondly, a crack path evaluation (CPE) method is developed for the gradual selection of the elements from the highest creep strain energy density (SED) value up to the predefined volume. The conventional solder crack path at the package interface or the diagonal solder crack path can be analyzed depending on the package technology because the critical solder elements are selected depending on the SED level and the failure path. The proposed SJR modeling method successfully demonstrates the diagonal solder crack path selection and further improves the SJR correlation of WLP and FOWLP.
Advanced No-Clean Solder Paste for SIP applications
Authors: Rath Santosh Kumar , Huei Yam Lip , Sutino Sylvia , Yuan Chieng Yu , Balasubramanian Senthil Kumar , Lo Yee Ting , Agala Joel , Zhang HanWen , Chan Li-San , Kang Sungsig , Mausner Stefan , Fritzsche Sebastian 
Published: January 2021

Abstract
This paper reports the comparison of two solder pastes made using a no clean flux platform and ultrafine SAC305 powders of Type 7 and Type8+, made using Heraeus’ Welco® technology. The application tests were carried out using 008004 components, the smallest passives used in SiPs. For the paste with Type 7 powder, the application tests complete with 12hrs of stencil evaluation have been reported, whereas for the paste with Type8+ powder, a preliminary work-life evaluation has been reported. Both pastes have been compared for the release performance using area ratios down to 0.35, with both circular and square stencil opening apertures. Cleaning evaluation was carried out with some of the commercially available cleaning agents to assess the compatibility of the flux residue. It has been demonstrated that the no clean solder paste with Type 7 powder has excellent stencil work-life performance until 12hrs of printing, with voids after reflow being less than 10%. The paste with Type8+ shows better release performance vis-à-vis Type 7, down to area ratio of 0.35, for square stencil opening aperture. Results from cleaning evaluation show the leftover contamination can be fully removed.
Heterogeneous System-In-Package (HSIP) Technology
Authors: Woychik Charles , Mundella Robert , Kunard Keith , Vilar Victor , Borski Justin , Nead Robert 
Published: January 2021

Abstract
A stitched test vehicle has been designed using molded wafer technology to characterize the assembly yield and reliability of a 4-layered topside Buildup (BU) and 4 layered bottom side BU package. In this design, the individual module uses 20 1mm square Si die elements, and one 10mmm square Si die and 8 through substrate vias (TSVs) arrayed on a 14mm square module size to produce a Reliability Test Vehicle (RTV) using Fan-out Wafer-Level (FOWL) technology. 17 individual RTV modules are molded on a 100mm wafer to create a reconstituted wafer. On the 1mm square Si die are two dog bone structures that allows for the design of a stitched net for each build layer with the embedded Si die. Therefore one can generate a stitched net between the first BU layer with the embedded Si die, the second BU layer with the embedded die layer, and so on. The layered stitched design feature, allows one to characterize the integrity of the individual BU layers during the sequential BU processing of the layers on both sides of the molded core. The TSVs allow for signal communication between the top 4 BU layers with the 4 backside BU layers. On top of each 4th layer is a ball grid array (BGA) pad on a 0.8mm pitch that can be used to stack this module using conventional soldering methods. This approach to embed die in a molded wafer and then BU layers on each side is referred to as Heterogeneous System-in-Package (HSIP) technology.
Another feature to be included in this work is the use of Current Induced Thermal Cycle (CITC) testing. This is a fast and accurate test method developed by i3 Electronics in Endicott, NY to assess the reliability of vias in a BU package. It is widely used in the industry for circuit boards and build up organic substrates, and is now be applied to the finer via dimension (25um diameter) used for HSIP technology. As was discussed above for the RTV design, the same BU and TSV features will be tested in this CITC module design. The BU layers are exactly the same as that used in the above RTV design.
For this wafer build, the die will be molded to create a reconstituted wafer. The first goal is to develop a molding process that has less than 20um die shift and produces a molded substrate with the acceptable amount of bow to accommodate the topside build up layers. For each BU layer, the assembly yield can be characterized by probing the stitched nets for the first, second, and so on BU layers for both sides. This data will provide assembly yield. The individual RTV and CITC modules can then be diced from the wafer, solder balls are attached to the topside BGA pads, and then tested using a conventional clam shell socket test fixture. The first set of reliability tests will be thermal cycling and temperature humidity. In this paper we will discuss the challenges with building HSIP modules, their yield and the first phase of reliability testing.
Six-Side Molded Panel-Level Chip Scale Package with Multiple Diced Wafers
Authors: Lau John H , Ko Cheng-Ta , Tseng Tzvy-Jang , Peng Chia-Yu , Yang Kai-Ming , Xia Tim , Lin Puru Bruce , Lin Eagle , Chang Leo , Liu Hsing Ning , Lin Curry , Cheng David , Lu Winnie 
Published: January 2021

Abstract
In this study, the design, materials, process, assembly, and reliability of a 6-side molded panel-level chip scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the RDLs (redistribution layers) of the PLCSP on a large temporary panel with multiple device wafers. Since all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Since all the processes/equipment are PCB process/equipment (not semiconductor process/equipment), it is a very low cost process. After the fabrication of RDLs, the wafers from the PCB panel are debonded. It is followed by solder ball mounting and fabricating the 6-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the 6-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.
Detecting a security breach and pinpointing its source
Authors: Huntley Dave 
Published: January 2021

Abstract
There are many rapidly emerging technologies to embed a “Root of Trust” (RoT) in silicon or in assembled packages and PCBs further down the supply chain. These all aim to provide an un-hackable proof of device identity and uncompromised firmware. Despite these efforts we can, and should, assume that bad actors will succeed to counterfeit devices, install malware, etc. So how do we detect and respond to these attacks in time before they cause too much harm? This is, of course, of particular concern for defense and aerospace applications.
We will discuss an initiative at SEMI to provide asset traceability through the supply chain. The intention is to detect counterfeits and security attacks quickly, track them back through the supply chain and identify the culprit. The threat of capture and penalties is expected to reduce the incentive for the bad actors in future.
The proposed SEMI standard will define the transactions and data required to record chain of custody for electronic assets as they flow through the supply chain. These transactions will be recorded on Hyperledger Fabric, a blockchain platform which offers an immutable transaction ledger, maintained within a distributed network of peer nodes. The ledger will not be public (like bitcoin), nor will it be private to one organization. Instead it will follow a consortium model and be permissioned to support flexible trust assumptions.
The SEMI standard will facilitate supply chain members to form one or more consortiums and host the Hyperledger nodes. This will enable the early detection and response to counterfeit and security threats to electronic assets that the supply chain members manufacture or distribute. The standard takes care not to expose any confidential technical or commercial information. However, Hyperledger offers the concepts of private data collections and channels to allow for the sharing of private data between specific members. This could become an enabler to realize the data sharing required to meet Smart Manufacturing 4.0 objectives.
There are a number of similar chain of custody ledger initiatives underway both in the commercial and standards arena. The hope is that the SEMI standard will encourage these systems to merge into an industry wide consortium with increased interoperability, performance, reliability and security.
Reliability Simulation of Cu/Polymer interface in Fan-out Wafer Level Packaging
Authors: Okada Yuji , Fujii Atsushi , Ono Kenta , Kariya Yoshiharu 
Published: January 2021

Abstract
In order to improve the performance and reliability of the package, the interlayer dielectric (Polymer) must not be delaminated and materials should not fracture due to thermal stresses during the operation or the manufacturing process. If the reliability of the package can be known in advance by simulation, it can be expected to greatly help in material selection and package design. Firstly, we created material-specific master curves (time–temperature superposition) by considering the measurement results of the Peel Test at the Cu/Polymer interface and the mechanical properties of polymer. The critical Energy Release Rate (𝒢𝒸) could be calculated by its master curve. Secondary, we calculated the Energy Release Rate (𝒢) from Finite Element Analysis (FEA) in the package model structure. Finally, delamination is judged by normalizing 𝒢/𝒢𝒸. This study has made it possible to simulate the delamination possibility of Cu/Polymer interface at arbitrary temperatures and displacement rates from basic material data and FEA analysis of the package model structure.
Characterization of sintered Cu nanopaste for micro-bumping with Injection Molded Solder technology
Authors: Nakamura Eiji , Aoki Toyohiro , Yamaguchi Ryota , Sekine Nobuhiro , Sueoka Kuniaki , Marushima Chinami , Yatsugi Kenichi , Yada Makoto , Hisada Takashi 
Published: January 2021

Abstract
We have previously developed a novel plating-free bumping process using Cu nanopaste and Injection Molded Solder (IMS) technology. In the present study, we investigated the further detail about the microstructural and mechanical properties of sintered Cu nanoparticles formed into a pillar shape. By analyzing cross-sections of Cu nanoparticle pillars sintered in various conditions, we clarified how the sintering conditions affect the microstructural features, including the size and numbers of Cu grains and voids inside sintered Cu nanoparticles. In addition, we conducted the shear testing for the obtained Cu pillars to evaluate relationships between the mechanical strength and the microstructural features. We found that the results of the shear testing were consistent with the microstructural features of the sintered Cu nanoparticles. Finally, we injected molten solder onto the Cu nanoparticle pillars to evaluate the overall feasibility of the developed process. It was confirmed that the molten solder injected by IMS process has good wettability against the sintered Cu nanoparticles, which resulted in the successful bump formation without solder missing. In addition, The IMC layer between the sintered Cu nanoparticles and injected solder was formed well. These results proved the quality of microbumps fabricated by the novel bumping process using Cu nanopaste and IMS.
Ultra-thin Flip-Chip Assembly for Heterogenous and Hybrid Integration
Authors: Hackler Douglas , Prack Edward 
Published: January 2021

Abstract
Flip-chip packaging of thin-die, in fact any packaging of thin-die, is one of today’s most significant challenges for die handling. Despite the difficulties presented as the thickness of chips continues to decrease, the wide range of applications they have enabled across multiple industries has led to increasing interest, as evidenced by the growth in the cumulative total number of publications on thin silicon based electronics, including Ultra-Thin Chips (UTCs), thinning of Silicon-on-Insulator, and wafer thinning. Smart devices including labels, loggers, wearables, implantable medical, and IoT are in demand. A key area of difficulty in the packaging of thin chips comes from removing the individual chips from dicing tape due to the adhesive nature of the tape and die cracking and edge chipping characteristic of thin die.
As the industry continues to embrace the benefits afforded by thin devices, two trends are being witnessed. Devices continue to grow larger in area and thinner in thickness. American Semiconductor’s automated production process for packaging and assembly of chips ≤35um in thickness will be presented. This includes details regarding needleless die eject, pick tip design for ultra-thin devices, ultra-thin flip-chip interconnects, thin-chip overcoat, process controls, and assembly on flexible circuit boards (FCB).
Parameter Optimization for Unstable Pin Bonding
Authors: Seppänen Henri 
Published: January 2021

Abstract
Plastic frame power modules with press-fitted or molded pins create challenging bonding conditions. Pin stability variations, from relatively stable to unstable within a single power module, makes it difficult to find process parameters that fit to all pins equally well. Also, tight space, full utilization of the pin surface for bonding and a large number of pins per module makes clamping solutions difficult or impractical. Therefore, we used process optimization to find optimal process parameters for the unstable pin bonds and active process control feature to reduce deformation variance in bonding. The study revealed the importance of the cleaning phase optimization for both sides of the pin stability variations. We found that ensuring a good cleaning phase, typically within first 10ms of the process on the unstable pins, significantly improved the quality of the bonds. Unstable pins tended to lift after bonding with traditional parameters, but demonstrated good shear strength with optimized parameters. Active process control ensured that all bonds reached optimal deformation, regardless of the pin stability. Generally, the best approach to reach good bond quality is to ensure an optimal bonding environment, including clean and stable bond pads. However, when it is not possible or practical to stabilize the bond pad, this study shows that carefully executed process optimization combined with the active process control can lead to robust bonding on unstable pins.
Plasma Surface Engineering: An Enabling Technology Designed to Clean and Protect Printed Circuit Boards
Authors: Pappas Daphne , Guist Sebastian , Ben Salem Dhia 
Published: January 2021

Abstract
Long term reliability and performance of printed circuit boards (PCBs) are strongly affected by the presence of surface contaminants from the manufacturing and assembly processes. Flux and solder residue, dust particles, oils and greases are often found on the assembled boards and can inhibit the successful application of conformal coatings that are used to protect the electronic components. Surface contaminants can cause coating delamination, dendritic growth, electromigration, corrosion and result in compromised coatings.
In the first part of this paper, the fundamental mechanism of plasma-induced removal of organic contaminants from PCBs will be presented. While vacuum based plasmas are considered the traditional solvent-free technology for surface cleaning, a new approach involving air plasma operating under atmospheric pressure conditions is gaining interest due to its adaptability for industrial inline processing. The low concentration of oxygen that is available in the plasma gas is effective in vaporizing organic contaminants leaving behind a clean surface.
Additionally, atmospheric plasma processes focusing on the development of functional nanocoatings on PCBs have been investigated. These plasma-enhanced chemical vapor deposition (PECVD) processes involve the delivery and vaporization of small volumes of solvent-free precursors that react with the plasma to form thin coatings on polymer substrates. Depending on the chemical structure of the precursor used, adhesion promoting, water repellant or electrical barrier coatings of 30–100nm thickness can be deposited. These protective functional coatings do not require any curing or special handling and no chemical waste is generated. The latest developments in atmospheric pressure PECVD for electronics protection will be presented in the second part of the paper. Besides the improvement of device performance and reliability, the application of PECVD has the potential to replace chemical substances such as primers known to have harmful impact on human health and the environment.
Advanced Low Df Dry film Build-up Material on Glass panel for 5G application
Authors: Kakutani Takenori , Guan Zhong , Suzuki Yuya , Ali Muhammad , Erdogan Serhat , Watanabe Atom , Kathaperumal Mohanalingam , Swaminathan Madhavan 
Published: January 2021

Abstract
This paper describes the demonstration of a low loss substrate (laminated glass) for high-frequency transmission using a dry film build-up material with low loss tangent (Df). This paper also evaluates filter characteristics and dielectric characteristics of the substrate in the mm-Wave band. The advanced low loss dry film build-up material was newly developed, and applicable to high frequency transmission. This material has a Df of 0.0025 at 10 GHz and also exhibits excellent adhesion and electrical reliability required for advanced dielectric materials. In addition, glass was used as a core material in this paper because of its excellent signal transmission characteristics compared to silicon wafers or organic substrates. To demonstrate the benefit of low loss materials for high frequency transmission, passive components for high frequency filter substrates were fabricated using - 6-inch square thin (0.2mm) glass panel with various build-up materials (Material A with a Df of 0.0025, and Material B with a Df 0.0042 at 10 GHz) laminated. Copper wiring patterns on the dielectric layers were fabricated by a semi-additive process (SAP). Circuit patterns with low pass filters and band pass filters were also fabricated. First, transmission characteristics and characteristic impedances were measured to check the electrical performance. The measured lowest transmission loss of &lt; 1.43 dB at 39 GHz were achieved when Material A was applied as the build-up material. Second, biased-highly accelerated stress test (bHAST) was conducted to evaluate the reliability performance of the substrates with two build-up materials, Material A and a conventional material. The test condition was based on the JEDEC level 2 standard. The substrate with Material A retained good insulation properties over 300 hours of bHAST treatment, demonstrating its excellent insulating performance. In summary, Material A has been shown in this paper to exhibit reduced transmission loss in high-frequency filter substrates at millimeter wave frequencies.
Development of Dielectric Material Enabling Low Insertion Loss of Organic Substrates at Various Operational Temperatures
Authors: Hayashi Tatsushi , Lin Po Yu , Watanabe Ryoichi , Ichikawa Seiko 
Published: January 2021

Abstract
With IP traffic increasing by 10-fold over the last decade, together with limitation and cost increase due to shrinking semiconductor nodes have led to requiring technological breakthrough in the packaging of semiconductor devices especially those used in high performance computing (HPC).This increase in IP traffic has led to requirement for higher data speed transmission in these devices, and consequently packaging technologies that enable those solutions such as 2.5D packaging utilizing silicon interposers. Furthermore, in recent years, increasing number of dies are placed in a single package for these devices thereby making the size of silicon interposers larger. Thus, the design of organic substrates used in these devices, are also becoming ever complex often with multiple layers with long trace lengths for routing increased number of IOs and allowing for power and signal control management. In order to facilitate the high speed data transmission requirement with longer trace lengths, stable low insertion loss design of organic substrates are becoming significantly important even when devices are exposed at elevated humidity or higher temperatures due to surrounding environment or from dies heating. Additionally, as silicon interposers are increasing in size, preventing stress build-up, which can cause cracking between the interposer and the organic substrate, is also becoming paramount. These requirements have led to innovative materials to be developed to enable organic substrates to have these properties. In this paper, we present a new dielectric build-up material for use in advanced organic substrates, by combining newly developed original resin with existing formulation technology that meet these criteria of enabling lower insertion loss with design that reduces deterioration even at elevated humidity and temperature, and furthermore having high crack resistance during temperature cycle testing.