Epitaxial Growth of Highly Sb-Doped Ge on p-Ge (100) for Vertical Transistor Applications
Authors: Saputro Rahmat Hadi , Matsumura Ryo , Fukata Naoki 
Published: July 2021

In recent years, Ge-based semiconductor materials has attracted a lot of attention for its possibility of higher mobility channel formation, toward next-generation complementary metal-oxide-semiconductor (CMOS) transistors. For this material to reach its potential, formation and optimization of p-n junction, which is the fundamental structure for a practical device, need to be investigated. In most cases, dopant ions are injected to form dopant-enriched films at the semiconductor interface, followed by annealing with various possible techniques1. However, crystal damages caused by high implantation energy makes it difficult to recrystallize and activate the dopant atoms. In this research, in-situ doping of Sb in epitaxial Ge layers grown on crystalline p-Ge substrates were studied, aiming a vertical p-n diode with higher Sb doping while maintaining good crystal quality. Formation of highly doped n-Ge is one of the most crucial challenges, as it was reported that uniform doping distribution across the layers are difficult to be achieved, which potentially deteriorate the crystallinity of the n-Ge layer2,3. Therefore, a study to overcome the doping problems in n-Ge, can lead to wider application of Ge-based devices.
The p-Ge substrates were treated by ultrasonic cleaning in Acetone followed by a diluted-HF dip and de-ionized water rinse. The cleaned substrate then loaded into molecular beam epitaxy (MBE) chamber (base pressure of 10-8 Pa) and subjected to thermal cleaning at 450 ºC for 10min. Subsequently, Ge film were homo-epitaxially grown on the p-Ge substrate using the Knudsen cell (K-cell) that heated around 1100 ºC to maintain a fixed 0.2 Å/s deposition rate. At the same time Sb source was evaporated by heating the Sb K-cell (Tdop.: 325-400 ºC) for the in-situ doping deposition. Here, the depositions of Sb-doped Ge layer were performed on the p-Ge substrate at fixed temperature of 450 ºC. The Sb contents in the epitaxial layer were quantitatively evaluated by the secondary ion mass spectrometry (SIMS), and a reflection high-energy electron diffraction (RHEED) system equipped on the MBE chamber was used to monitor the epitaxial growth during depositions. Moreover, the crystal quality also characterized by the Raman spectroscopy method. After the deposition of 100 nm Sb-doped Ge layer, the samples then used to form vertical p-n diode structures using a conventional lithography method as shown in Fig. 1.
The depth profiles obtained by SIMS measurements shows that high amount of Sb atoms (>1019 cm-3) was incorporated into the epitaxial Ge layer (Fig 2(a)). It also shows that Sb atomic concentrations vary with the Sb K-cell temperatures (Tdop.), in which higher temperature (Tdop.: 400 ºC) resulted in higher Sb concentration. The epitaxial growth of Sb-doped Ge layer was observed using the RHEED system, which resulted in a streaky pattern of the diffracted electron beam as seen in the inset of Fig. 2(b). The crystallinity of the epitaxial layer also matched with the results obtained by of Raman measurement shown in Fig.2(b). A strong Ge-Ge phonon peak at similar position to the reference crystalline Ge (at 300.2 cm-1) was obtained for both Tdop.: 325 ºC and 400 ºC samples. This result indicates the growth of Ge crystals with high crystallinity despite the high Sb content. Fig. 2(c) shows rectifying properties for vertical p-n junctions using these samples, where the current obtained at forward bias is much higher than that obtained at reverse bias (ION >>
IOFF
). Interestingly, this p-n diode rectifying behavior was also improved (higher ION
/IOFF
ratio) with the increase of dopant concentrations. The relation between Sb concentration and electrical properties can be explained by the dopant activation rate in the Sb-doped Ge layer, because higher amount of Sb atoms increases the electron doping density. This result clearly shows that highly doped n-Ge layer was formed on the top of p-Ge. This can be expected a useful method for the formation of next-generation vertical transistors where n+-Ge is utilized in source/drain formation. Further investigation about the growth conditions and its relations with electrical properties of the vertical p-n diodes will be discussed in the main presentation.

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Figure 1