An Extended-Gate Ion-Sensitive Field-Effect Transistor with CMOS Technology-Intrinsic TiN Sensing Layer
Authors: Teng Nan-Yuan , Wu Yi-Ting , Lin Chih-Ting 
Published: July 2021

The extended-gate ion-sensitive field-effect transistor (EGISFET) has promising potentials in chemical and biological sensing due to flexibility for array arrangement, less light-sensitivity, and compatibility with CMOS standard fabrication process [1-2]. An EGISFET is consisted of a MOSFET and a floating-gate structure separated from analyte solutions by a sensing layer. Because charges adjacent to the sensing layer change the floating-gate potential, the channel current of the EGISFET can be modulated through the electrical field effect. In a general CMOS process, the EGISFET can be achieved by using metal/VIA/polysilicon layers as the extended gate material and the passivation nitride layer on top of the metal as the sensing layer. For the EGISFET operation, a solution gate voltage is provided in the analyte solution and a capacitive voltage divider can be obtained based on a series connection of the electrical double layer capacitance (CEDL), the sensing layer capacitance (CS) and the gate oxide capacitance (COX). Due to the capacitive coupling nature, a higher CS/(CS+COX) ratio can have a larger part of solution gate voltage transferred to COX, and thus can have a higher EGISFET transconductance [3], which promises a better sensing response, e.g. channel-current change for a given charge change. However, CS is decreasing because of scaling down for realizing high spatial resolution sensing array. Then EGISFETs become less sensitive due to a weaker capacitive coupling.
In order to ameliorate this scaling effect, we developed a TiN-EGISFET based on a CMOS 0.35 mm standard fabrication process. Instead of using the 1-2 mm thick passivation/intermediate dielectric layer as the sensing layer, we took advantage of an intrinsic extra-thin TiN layer within the VIA structure as the sensing layer. To expose the TiN layer, the metal/VIA layout was placed in a special manner to form a hanging micro-structure after a one-step wet etching. Followed by sonication, the micro-structure was broken at a mechanical weak point, e.g. the metal/VIA interface, and the ultra-thin TiN was successfully exposed. To have a control group, a traditional EGISFET was also implemented on the same chip. In the EGISFET measurement, a Ag/AgCl electrode was used to provide solution gate voltage, and the electric characteristic curve for each device was measured in pH solutions with different values.
Compared to the traditional EGISFET occupying the same chip area, transconductance for the TiN-exposed EGISFET was improved up to 240%. This enhancement is possibly attributed to the conductivity and chemical stability of TiN, which make CS in the TiN-exposed region disappeared, only left CEDL and COX in series. As a result, a larger portion of solution gate voltage is dropped across COX because CEDL>>COX. Furthermore, the pH sensitivity of TiN-exposed EGISFET reaches 51 mV/pH without obvious hysteresis and drift (Figure 1). This is also supported by the previous literatures [4-5]. At 0.5V overdrive voltage, the current variation of TiN-exposed EGISFET is -9.12 mA/pH, which is 275% as high as that of the traditional EGISFET (Figure 2). These results suggest that a TiN-exposed EGISFET with a smaller footprint can possess the same sensitivity of a traditional EGISFET with a larger footprint.
In conclusion, we developed a method to fabricate EGISFETs with TiN sensing layers in a commercialized CMOS process. This is the first time to have the in-situ TiN EGISFET in the CMOS process without extrinsic TiN deposition. This method can be employed to realize EGISFETs with higher density in a given area without sacrificing sensitivity, thus potentially beneficial to the development of high performance and high spatial resolution ISFET sensing array.

References

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Figure 1