(Invited) Modeling the Influence of Interface Traps on the Transfer Characteristics of InAs Tunnel-FETs and MOSFETs
Authors: Pala Marco , Esseni David 
Published: February 2020

ITRS [1] has identified Tunnel-FETs as the most promising transistors to reduce the inverse subthreshold swing with respect to MOSFETs and thus allow for an aggressive VDD scaling, and encouraging experimental data have been reported [2]. Interface states, however, are a serious concern for III-V FETs [3], because, by acting as stepping stones for the tunneling through the gap, they may have a large impact on IDS versus VGS(I-V) characteristics of Tunnel-FETs.
In this work we present a comprehensive computational study employing a full quantum transport model to investigate the effects of interface traps in nanowire InAs Tunnel-FETs and MOSFETs by varying the trap energy level, its volume and position, as well as the working temperature [4, 5]. To this purpose, we introduced a description of interface traps in a simulator based on the Non-equilibrium Green’s functions formalism, using an 8 bands k.p Hamiltonian and accounting for phonon-scattering [6]. In our model, traps are treated as 0-D electrically active states that can affect the I-V curves of the transistors both by modifying the device electrostatics and by actively participating to the carrier transport.
Our 3-D self-consistent simulations show that: even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; shallow traps have the largest impact on subthreshold slopes; and the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the otherwise temperature-independent Tunnel-FET characteristics.
Further, we considered Tunnel FETs or MOSFETs with a spatially random distribution of traps. The physical mechanisms behind the effects of traps in either tunnel FETs or MOSFETs are compared and, furthermore, traps are also investigated as a possible source of device variability [7]. We show that, in MOSFETs, an aggressive oxide thickness scaling can effectively counteract the degradation of the inverse subthreshold slope possibly produced by interface traps. Tunnel FETs are instead more vulnerable to traps, which are probably the main hindrance to the experimental realization of tunnel FETs with an inverse subthreshold slope better than 60 mV/decade.
[1] International Technology Roadmap for Semiconductors: 2011 Update. http://www.itrs.net, 2011.
[2] G. Dewey, et al., “Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing,” in IEEE IEDM Technical Digest, pp. 33.6.1–33.6.4, 2011.
[3] L. Lin and J. Robertson, “Defect states at III-V semiconductor oxide interfaces,” Applied Physics Letters, vol. 98, no. 8, p. 082903, 2011.
[4] MG. Pala and D. Esseni, “Interface Traps in InAs Nanowire Tunnel-FETs and MOSFETs—Part I: Model Description and Single Trap Analysis in Tunnel-FETs,” Electron Devices, IEEE Transactions on, vol. 60, pp. 2795 - 2801, 2013.
[5] D. Esseni and M.G. Pala, “Interface Traps in InAs Nanowire Tunnel FETs and MOSFETs—Part II: Comparative Analysis and Trap-Induced Variability,” Electron Devices, IEEE Transactions on, vol. 60, pp. 2802 - 2807, 2013.
[6] F. Conzatti, et al., “Strain-induced performance improvements in InAs nanowire tunnel FETs,” Electron Devices, IEEE Transactions on, vol. 59, pp. 2085–2092, 2012.
[7] F. Conzatti, M.G. Pala, and D. Esseni, “Surface-roughness-induced variability in nanowire InAs tunnel FETs,” IEEE Electron Device Letters, vol. 33, pp. 806–808, 2012.