Enhancing Normally-Off P-GaN Gate HEMTs Performance with Composite GaN/AlN/AlGaN Blocking Layers
Authors: Chen Hsin Chu , Liu An-Chen , Huang Yu-Wen , Kuo Hao-Chung 
Published: December 2024

Purpose of Work

Due to the excellent figure of merit and reliable normally-off functionality, p-GaN gate HEMTs have been superior to traditional silicon-based components, especially with higher breakdown voltage and lower RON [1]. Despite the excellent performance of p-GaN gate HEMTs, there are still some significant challenges that require improvement. Firstly, reducing gate leakage current via the incorporation of an additional dielectric layer beneath the gate provides an effective method for reducing leakage current and enhancing gate drive voltage [2]. Secondly, during the epitaxial growth of the p-GaN capping layer, an undoped GaN (u-GaN) blocking layer needs to be considered in the p-GaN structure to achieve optimal Mg activation by MOCVD. This layer acts as a blocking function to mitigate Mg out-diffusion into the AlGaN barrier and/or GaN channel, thus preventing 2DEG degradation [3]. In this work, we demonstrated a novel composite blocking layer comprising u-GaN/AlN/AlGaN for normally-off p-GaN gate HEMTs. Compared with traditional p-GaN gate HEMT without a composite blocking layer, the IDMAX current is significantly increased by 37% and RON is reduced by 23%. This reason can be attributed to the introduction of the u-GaN as a blocking layer under p-GaN which effectively mitigates Mg diffusion in the capping layer, thus solving its deleterious effects.

Approach

The fabrication of p-GaN gate HEMTs followed a standardized base structure which included an identical AlN seed layer, an AlGaN buffer layer, and an Al0.18Ga0.82N barrier/GaN channel layer. To study the effects of the AlN spacer and u-GaN blocking layer on device characteristics, the epitaxial structure of the active layer was designed for comparative analysis. These designed structures were denoted to "Device A" without an AlN spacer and u-GaN layer, "Device B" with an AlN spacer but without a u-GaN layer, and "Device C" with including an AlN spacer and a u-GaN layer in Fig. 1 (a). For normally-off p-GaN HEMTs, mesa isolation was fabricated by ICP-RIE. Next, a Schottky contact was formed using a Ti/Al/Ni layer by an E-Gun. A 15 nm Al2O3 layer was deposited as dielectric by ALD, followed by 50 nm Si3N4 passivation by PECVD. Ohmic contact was fabricated through Ti/Al/Ti metal stack and RTA in the N2 atmosphere at 825°C for the 30s. The final steps include a gate field plate, a 150 nm Si3N4 passivation layer, and contact hole openings for the Ti/Al metal stack as electrode pads in Fig. 1 (b).

Results and Significance

In Fig 2 (a), the VTH for devices A, B, and C were determined to be 1.5 V, 1.4 V, and 1.0 V, respectively. IDMAX current at the VG of 6 V was observed to be 198 mA/mm for Device A, 241 mA/mm for Device B, and 272 mA/mm for Device C, and maximum transconductance (Gm,MAX)values of 51.2 mS/mm, 72.7 mS/mm, and 77.3 mS/mm, respectively. Device A exhibited the subthreshold slope (SS) value of 121 mV/dec, while Device B had 117 mV/dec, and Device C demonstrated the lowest SS value of 102 mV/dec. Notably, Device C exhibits excellent gate control efficiency which is attributed to the introduction of the u-GaN barrier layer that effectively mitigates Mg diffusion into the AlGaN barrier and/or GaN channel, thereby reducing band-to-band leakage. Fig. 2 (b) shows the RON of the devices, with values of 14.5 Ω-mm, 12.1 Ω-mm, and 11.1 Ω-mm for devices A, B, and C. Devices B and C contain AlN spacer layers and exhibit lower RON compared to device A. It is worth noting that device C has the u-GaN barrier layer and effective AlN spacer, which not only mitigates Mg diffusion into the AlGaN/GaN channel but also enhances the interface polarization field, thereby injecting more electrons into the 2DEG channel and improving turn-on resistance.
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[2] M. Jia, B. Hou, L. Yang, F. Jia, X. Niu, J. Du, Q. Chang, M. Zhang, M. Wu, and X. Zhang,"High VTH and Improved Gate Reliability in P-GaN Gate HEMTs with Oxidation Interlayer," IEEE Electron Device Lett., vol. 44, pp. 1404-1407, 2023.
[3] T. Pu, Q. Huang, T. Zhang, J. Huang, X. Li, L. Li, X. Li, L. Wang, and J. P. Ao,"Normally-off AlGaN/GaN heterostructure junction field-effect transistors with blocking layers," Superlattices Microstruct., vol. 120, pp. 448-453, 2018.

Figure 1