Performance Enhancement of Metal Floating Gate Memory by Using a Bandgap Engineered High-k Tunneling Barrier
Authors: Jiang Dandan , Jin Lei , Xia Zhiliang , Chen Guoxing , Zou Xingqi , Zhang Yu , Tang Zhaoyun , Huo Zongliang 
Published: February 2020

With conventional nonvolatile flash memories approaching their scaling limit from cell-to-cell coupling and stress induced leakage current, many studies have been performed to explore the next generation memory technologies. Metal ﬂoating gate (FG) memory is one of the most promising candidates because of its less ballistic transport even with ultrathin floating gate (<10 nm). Enhancd memory performance including fast program speed, excellent data retention and program/erase (P/E) cycling endurance have been repored by P. Blomme et. al from IMEC. Moreover, S. Jayanti et. al explored that full Metal-FG could scaled down to even 1 nm thickness with excellent memory performance.
Nevertheless, less attention had been paid on the study of tunneling layer which matches with full Metal-FG. Sufﬁcient gate coupling ratio could obtained by using tunneling barrier without compromising the device performance. In our previous work , both the P/E speed and retention characteristic has been improved in the TaN floating gate flash memory based on the SiO2/HfO2 dual tunneling layer structure.The HfO2 layer adjacent to TaN was expected to suppress the inter-diffusion between tunneling dielectric and TaN FG.
In this letter, bandgap engineered of the triple tunneling layer (SiO2/HfO2/Al2O3) has been demonstrated to be an effective method to optimize the performance of TaN Metal-FG. Compared to a device with a single SiO2
tunneling layer, faster program/erase speed and better data retention characteristics have been simultaneously achieved in this proposed structure.
The schematic structure of a metal ﬂoating gate device is illustrated in Figure 1. P-type Si (100) wafers were cleaned by the standard Radio Corporation of America process. Devices with SiO2 (SiO2-4.5nm), SiO2/HfO2 (SiO2-2.7nm/HfO2-8nm) and SiO2/HfO2/Al2O3 (SiO2-2.7nm/HfO2-4nm/Al2O3-2nm) as tunneling layers are denoted as O-TaN , OH-TaN and OHA-TaN respectively. The thicknesses of tunneling layers were chosen for achieving the same effective oxide thickness (EOT). The memory characteristics such as operation speed and data retention were measured by using Agilent B1500A.
The C-V hysteresis memory window of both O-TaN and OH-TaN device have been test. The improvement in the memory window for the OH-TaN device indicates the better carrier trapping capability of the stacked SiO2/HfO2 structure.It also can be attributed to the difference of the effective tunneling distance, which is resulted from the different potential drop when low-k and high-k dielectrics are employed as tunneling layer. Devices with SiO2/HfO2/Al2O3 (OHA) as tunneling layer was further characterized and compared with O-TaN and OH-TaN device. Compared to the O-TaN device, fast P/E speed along with large memory window is achieved with the OH-TaN and OHA-TaN device. Moreover, the device with OHA is slightly more advanced than the device with OH. The improvement of P/E speed in the OH-TaN and OHA-TaN structure can be explained by the energy band diagram under the program bias condition. Owing to the difference of voltage drop and bandgap between SiO2 and high-k (HfO2 and Al2O3), the effective tunneling distance is reduced in a high-k engineered tunneling layer structure. In addition, The reason that devices with OHA as tunneling layer shows slightly faster P/E speed than devices with OH as tunneling layer may attribute to a high defect state density at the interface of HfO2 and Al2O3. We also programmed the devices with an identical initial flat-band voltage to compare their room temperature retention characteristics. The OH-TaN and OHA-TaN structure exhibits negligible decrease in flatband voltage, whereas the control sample shows a significant loss of 2.7 V in flatband voltage in 104s. This can be attributed to the larger physical tunneling layer thicknesses of the engineered ones. The tunneling can be suppressed by large physical thickness under flat band or low electric field conditions.
In this paper, a stacked high-k tunneling layer is proposed and investigated for TaN metal ﬂoating gate memory application. Compared to a single SiO2 tunneling layer, a stacked SiO2/HfO2 (SiO2-2.7nm/HfO2-8nm) and SiO2/HfO2/Al2O3 (SiO2-2.7nm/HfO2-4nm/Al2O3-2nm) tunneling layer structure have several memory performance improvements: a larger memory window, faster program/erase speed and better data retention characteristics. The improvement of P/E speed in the high-k tunneling barrier structure can be explained by the energy band diagram under the P/E bias condition. the effective tunneling distance is reduced Owing to the difference of voltage drop and bandgap between SiO2 and high-k (HfO2 and Al2O3). The performance enhancement of retention is attributed to the larger physical tunneling layer thicknesses of the high-k engineered ones.
This work was supported by the National Natural Science Foundation of China (Grant No. 61306107, No. 61474137, No. 61404168, No. 61404160), China Postdoctoral Science Foundation funded project (No.2014M550866), and the Scientific Research Foundation of CUIT (KYTZ201318, J201404).

Figure 1