(Invited) A Brief History of Selective Epitaxy (at IBM SRDC)
Authors: Holt Judson Robert , Stoker Matthew Wahlquist , Mcardle Timothy J , Levesque Annie 
Published: February 2020

Over more than a decade—and half a dozen technology nodes—selective expitaxy has consistently been a major performance element, propelling logic devices to their ultimate targets. Throughout this period (the “Epi Renaissance”), a huge variety of epitaxial processes have been evaluated across the semiconductor industry. Because each technology generation has unique constraints and process assumptions, these epitaxy processes have varied significantly in shape, size, and composition. And of course not all survived to be implemented in full production. This presentation gives a retrospective survey of each of these epitaxial processes, ranging from a simple, single undoped Si raised source/drain to multi-pass growth with complex multi-layer film stack.
Selective epitaxy at IBM SRDC began with an undoped selective Si raised source drain (RSD) at the 90nm technology node, used to improve the silicide formation and placement. This was a key enabling feature of the Si on SiGe on insulator (SGOI) technology [1]. Since the silicide had difficulties with the SiGe underlayer, a selective epitaxial Si solution allowed significantly improved contact resistance. SGOI showed great promise on long channel devices, and due to the uniaxial nature of the strain it showed a clear performance benefit on both NFET and PFET. Unfortunately, the short channel devices were consistently degraded, so for the ultimate performance targets IBM instead turned to stressed nitride liners to deliver channel strain [2], while Intel introduced embedded SiGe source/drain (eSiGe) [3].
IBM incorporated eSiGe as a PFET performance element starting at the 65 nm node. However, instead of an in-situ boron doped eSiGe grown just prior to silicide (late eSiGe) similar to what Intel had published, IBM used a lower %Ge, undoped SiGe film grown just after gate module (early eSiGe). Early eSiGe was effectively a “drop-in” solution that allowed for minimal disruption to the existing integration and device design while still providing significant performance gains via channel strain [4].
For the 45nm node IBM published a novel method called Hybrid Orientation Substrate (HOT) that enabled PFET performance gain by changing the PFET Si crystal orientation from <100> to <110>. This method utilized a SOI wafer with <100> top Si layer bonded to a <110> handle wafer. At the beginning of the process, the PFET regions were etched down through the buried oxide, and a thick, undoped selective Si epi was then re-grown on the <110> substrate. In contrast to SGOI the benefit of HOT was demonstrated even on short channel devices. Even better, this mobility increase was shown to be additive with eSiGe strain [5]. Unfortunately a combination of factors including significantly higher substrate cost, area density penalty from expanded groundrules, and concerns about defectivity of the selective epitaxial re-growth prevented it from being implemented in full manufacturing. Instead of HOT, a second generation early eSiGe process was developed with closer proximity to the gate, and increased recess depth [6].
At the 32nm node IBM was focused on the switch to high-K with metal gate, and again IBM and Intel’s solutions diverged. IBM and partner companies used a “gate first” integration flow, contrasted with Intel’s “gate last” replacement metal gate process. Since differential metal workfunction tuning was unavailable in the gate-first integration, IBM introduced a second epitaxy step, growing a thin layer of channel SiGe on the PFET in order to separately tune the PFET threshold voltage [7], and increase performance [8].
Despite remaining planar and gate first, 22nm saw multiple disruptive changes in the source/drain epi module. IBM gained an industry first with the introduction of strained Si:CP in the NFET S/D, a process that required cyclic dep/etch in order to achieve high substitutional carbon incorporation [9]. On the PFET side, the reduced dimensions and the effect of ion implant lateral straggle finally forced a switch from early to late eSiGe. This change drove increased complexity in the epi by adding a buffer layer to control dopant out-diffusion, a ramped high-boron main layer, and a cap layer for improved silicide. Additionally, both NFET and PFET benefited from the introduction of an integrated preclean module, where the wafer does not break vacuum in between oxide etch and epitaxial growth.
Today, the 14nm node marks the arrival of FinFETs at the SRDC – with significant integration differences compared to Intel’s FinFET solution. IBM chose to stay with SOI substrate, leading to challenges with the source/drain recess for embedded SiGe. Eventually, IBM sidestepped the recess issue by implementing cladded epitaxy for both the PFET and NFET source/drain, focusing on improving performance by lowering contact resistance instead of straining the channel [10].

Figure 1