Experimental Study for Mosfet with Ellipsoidal Layout
Authors: Cruz William Souza , Gimenez Salvador Pinillos 
Published: February 2020

Many efforts in research are conducted and high investments are currently made to create increasingly smaller MOSFETs and with better analog and digital electrical characteristics. There are several ways to try to achieve these goals, among them are the use of new materials for the manufacture of semiconductor devices, new planar and threedimensional structures of MOSFETs and new manufacturing processes. Another innovative and fully-Brazilian alternative is the use of new and different layouts for the implementation of these devices.
Among the different layouts proposed, we have the ellipsoidal that is the evolution of other layouts, such as the hexagonal and the octagonal. Recently, experimental studies on the advantages and disadvantages between the ellipsoidal layout MOSFET and its corresponding rectangular were conducted showing promising results for this new layout.
The main idea of diamond and ellipsoidal layouts was to take advantage of the cornering effects to potentiate the drain current of the device. This effect is called the LCE (Longitudinal Corner Effect) and it is responsible for increasing the longitudinal electric field along the channel of the MOSFET, thus increasing the velocity of drift from the movable carriers in the channel, which ultimately results in a higher drain current (IDS), transconductance, on-state resistance, etc.
In addition to the effect cited above, others are still incorporated into the structure of MOSFET ellipsoidal, which can enhance their electric performance. Examples of these new effects are the PAMDLE (Parallel connection of MOSFETs with Different channel Length Effect) and the LECRE (Leakage Current Reduction Effect), which further enhances the drain current around the margins of the device and reduces the leakage current when the device operates in the cut-off region, respectively.
The main objective of this study then is to investigate the benefits of this geometry in relation to conventional geometry, to apply this innovative layout in analog and digital integrated circuits. For conducting the study, devices of the same technology were characterized in the ellipsoidal and conventional geometries, in the same bias conditions and through the normalization of curves by the aspect ratio (W/L).
For the characterization of the devices was used a chip with the manufacturing technology of TSMC (Taiwan Semiconductor), with a minimum size of 180 nm. These devices were manufactured via MOSIS, through the MEP program. Through the system of electrical characterization of the Keithley were obtained the curves ID x VD and ID x VG for the same conditions of polarizations on both devices. After the normalization of the curves by the aspect ratio, several parameters of the devices were compared to establish how much the gate geometry influenced the electric behavior of the ellipsoidal MOSFET. Figure 1 shows the values of the drain current in function of the gate tension for both devices, with a drain tension of 50 mV.
Table I presents the values obtained for the currents of the on-state and off-state (ION and IOFF), as well as the figure of merit ION/IOFF.
A comparative study between Ellipsoidal MOSFET and conventional counterpart was performed. The ellipsoidal layout style proved to be a better alternative for the improvement of the performance of devices.

Figure 1