Co-Planar Nano-Resistor Devices
Authors: Kuo Yue , Zhang Shumao 
Published: February 2020

Nano-resistors made from the breakdown of a MOS capacitor with a metal oxide high-k gate dielectric layer have been reported previously [1-3]. The high-k dielectric surrounded nano-resistor structure has many interesting properties suitable for electronic and optoelectronic devices. The material and fabrication process of the nano-resistor device are completely IC compatible. Therefore, the cost of the device can be very low. The nano-resistor structure can be used as diodes or antifues in low- or medium-power logic and memory ICs [4]. Separately, when a voltage is applied through the nano-resistor, light can be emitted from the thermal excitation process [1-3]. This kind of device is named the solid state incandescent light emitting device (SSI-LED) because the light spectrum covers the whole visible and part of the near IR wavelength range with the peak located in the red light region. The light is located in the warm white light region of the CIE chart with a large CCT of above 2,500K and a high CRI of > 95. Similar to the light of the conventional incandescent light bulb, the SSI-LED is suitable for the lighting purpose. In addition, the broadband light can be narrowed down to near the 850 nm wavelength by adding a thin film filter [5,6]. When used in combination with the proper waveguide and modulation units, the SSI-LED can be a light source for the on-chip optical interconnect.
Nano-resistors reported in the literature are made from the vertical MOS capacitor structure, as shown in Figure 1(a). Conductive paths are formed from the breakdown of the gate dielectric film due to the large electric field between the top and bottom electrodes. Since all nano-resistor devices are formed on the same wafer sharing the common bottom electrode, electrical interferences or crosstalks among adjacent devices are unavoidable. In this paper, a new type of co-planar nano-resistor structure formed from the MOS capacitor with both electrodes located on the same side of the wafer, as shown in Fig. 1(b), is introduced. The gate dielectric layer is broken from the application of an electric field between the two electrodes. Different nano-resistor devices can be formed individually on the same substrate. When properly isolated, the nano-resistor device can be operated without being interfered by surrounding devices. Then, a large array of devices can be fabricated and operated for various applications. Figure 2 shows breakdown curves of the conventional vertical (control) and the new co-planar structured samples. Nano-resistors are formed in the similar way. Figure 3 shows an array of co-planar nano-resistor devices fabricated on the Si wafer. In this paper, we will describe the fabrication process of the co-planar nano-resistor device. Electrical and optical characteristics of the device will be shown and discussed. Possible applications of this kind of device will also be discussed.
[1] Y. Kuo and C.-C. Lin, APL,
102, 031117 (2013).
[2] Y. Kuo and C.-C. Lin, SSE, 89, 120 (2013).
[3] Y. Kuo, IEEE TED, 62, 3536 (2015).
[4] Y. Kuo, ECS Trans.
69(12) 23 (2015).
[5] S. Radovanovic, et al, High-Speed Photodiodes Standard CMOS Technol., p. 24 (2006).
[6] S. Zhang and Y. Kuo, ECS JSS, 6 Q39 (2017).

Figure 1