(Keynote) Development of Magnetic Tunnel Junctions for Stt-Mram Application
Authors: Yakushiji Kay , Kubota Hitoshi , Fukushima Akio , Yuasa Shinji 
Published: February 2020

A spintronic-based STT-MRAM (Spin-Transfer-Torque Switching type Magnetic Random Access Memory) is one of the promising candidates in the next generation memory thanks to the features such as high density (above giga-bit), non-volatile, low power consumption, high endurance (almost unlimited), high operation speed (~nano sec) and the compatibility with Si technology. Since 2006, we (AIST, Toshiba, Tohoku Univ., Osaka Univ. and Univ.Elec-comm.) have worked on joint projects of STT-MRAM and achieved some key breakthroughs and discoveries that realized high-scalability and the commercialization. This paper presents our R&D activities and prospects for Normally-Off computing [1] using the non-volatility as well as the overall review of STT-MRAM.
The first feature of the STT-MRAM is non-volatility which is the most recognized advantage over semiconductor-based DRAMs. It brings low energy operation because the memory cell stores the information without wasting power. Such a feature exhibits in an MTJ (Magnetic Tunnel Junction) which consists of a thin MgO tunnel barrier and a storage and a reference ferromagnetic thin film layers [2]. Then the STT writing technology is also the important phenomenon which was discovered in the last decades. Another breakthrough was the development of the perpendicular-type MTJ (p-MTJ) [3]. Our joint project have firstly realized p-MTJ in 2007, and until now, attained non-volatility, low power STT-switching, high thermal stability and also high magnetoresistance at the same time despite some conflicting conditions. The success of p-MTJ opened up the high scalability above giga-bit. Finally, a recent p-MTJ has met the requirements 30 nm generation or beyond [4].
In the past few years, our challenge for highly scalable STT-MRAM has moved toward further low power and faster p-MTJ, and a new concept of spintronics device. For a cache application, we indeed demonstrated 1/8 power operation of a mobile processor by replacing part of a last level cache by new p-MTJs [5]. For further low power consumption, even if p-MTJ is well optimized, it is difficult to further reduce the switching power in the framework of current-induced driven. To overcome it we have been testing a new concept of the switching, voltage-driven writing technology, in p-MTJs. Although p-MTJ was not fully optimized, we achieved voltage-induced precessional switching with two orders lower power than the current-induced one. So far, STT-MRAM technology has brought some novel functional devices such as a physical random number generator called “Spin-Dice” [7] and a spin-torque oscillator (STO) [8]. Because fabrication process is basically the same as STT-MRAM, on-chip integrated those devices would provide new functions to STT-MRAM: for example, Spin-Dice for the secure data encryption and STO for the inter-chip communication.
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[2] S. Yuasa et al., NMAT 3 (2004) 868.
[3] K. Yakushiji et al., APEX 8 (2015) 083003.
[4] T. Kishi et al., IEDM (2008) 309.; K. Tsuchida et al., ISSCC (2010) 258.; H. Yoda et al., Curr. Appl. Phys. 10 (2010) E87.
[5] K. Ikegami et al., IEDM (2015) 25.1.1.
[6] Y. Shiota et al., APEX (2016) 013001.; T. Nozaki et al., APL (2013) 073005.
[7] A. Fukushima et al., APEX 7 (2014) 083001.
[8] S. Tamaru et al., Sci. Rep. 5 (2015) 18134.; S. Tsunegi et al., APEX 7 (2014) 063009.