(Invited) Low-Energy Plasma Enhanced Chemical Vapor Deposition and In-Situ Doping for Junction Formation in Group-IV Semiconductor Devices
Authors: Sakuraba Masao , Sato Shigeo 
Published: February 2020

In novel semiconductor devices, such as a tunnel field-effect transistor (TFET) [1,2], a resonant-tunneling device [3-5] and a semiconductor spin qubit [6], energy-band modulation in group -IV semiconductors using nanometer-scale heterostructure and local doping [7] with suppressed intermixing is a key technology. Additionally, 2-dimensional (2D) nanosheet semiconductor materials (e.g. graphene, silicene, tungsten disulfide and so on) are aggressively investigated [8]. In such a trend, as well as conventional low-temperature thermal processes, utilizing a low-energy plasma process has been explored. We have clarified that low-energy Ar plasma irradiation effectively induces surface reaction and epitaxy of Si-based group-IV semiconductor on Si(100) [9-19]. Our efforts in development of such material processing utilizing low-energy Ar plasma process will be presented.
Without substrate heating, low-energy electron-cyclotron-resonance (ECR) Ar plasma chemical-vapor deposition (CVD) process has enabled epitaxy of strained/unstrained films of group-IV materials (Si, Ge, Si-Ge alloy and Si-C alloy) with in-situ doping and an atomic-layer (AL) doped structure (Fig. 1) [9-19]. Especially in the TFET, sub-nanometer-order (atomic-order) abrupt profile control of impurities (B or P) concentration will be examined in epitaxy and in-situ doping. As a typical issue in our plasma CVD, it is considered that surface segregation of impurity during Si deposition occurs and degrades the profile abruptness near the interface. However, it has been demonstrated that the abruptness can be improved by atomic-layer doping technique [14,18]. Additionally, it is found that electrical activity of B doped in Si tends to be lowered especially at higher concentration than 1019 cm-3, while higher-energy plasma irradiation effectively improves the activity. These imply that semiconductor device process can be performed at lower temperatures where unexpected thermal diffusion and reactions are effectively suppressed.
Our recent challenge is penta-silicene formation from epitaxial Si nanosheet. We believe that 2D materials as a novel semiconductor will be obtained not only by atomically-controlled epitaxy of heterostructures but also by reconstruction of atomic arrangement at surface. Here, our target is penta-silicene transformed from a 3-atomic-layer-thick Si nanosheet, which is different from the diamond structure. Our concept is crystal structure transformation in the Si nanosheet, and this is based on long-range coordinated and double-sided surface reconstruction on Si(100) to form the penta-silicene (Fig. 2) [15]. Because penta-silicene has a 3-dimensional structure composed of 3 atomic layers (similar to tungsten disulfide), it is expected to be more stiff and stable physically than monolayer of hexa-silicene. Realization methods of the penta-silicene on Si wafer for large-scale integration of the penta-silicene devices are now in progress. After formation of penta-silicene, control of interface structure between the penta-silicene and gate insulator will be one of the important issues to control interface structure.
From the view-point of material science and control of the interfaces in semiconductor, development of process technology must be proceeded further. Such efforts will encourage smart electronic devices for enabling artificial intelligence and higher security in the next-generation information society.

Acknowledgements

This work was partly supported by Grant-in-Aid for Challenging Exploratory Research (No. 18K18987) from the JSPS in Japan and the Cooperative Research Project Program of the Research Institute of Electrical Communication, Tohoku University.

References

[1] A.M. Ionescu et al.: Nature
479, 329 (2011).
[2] Y. Morita et al., IEEE Electron Dev. Lett.
35, 792 (2014).
[3] R. Ito et al., Semicond. Sci. Technol.
22, S38 (2007).
[4] T. Seo et al., Solid-State Electron.
53, 912 (2009).
[5] K. Takahashi et al., Solid-State Electron.
60, 112 (2011).
[6] K. Ono et al., Sci. Rep.
9, 469 (2019).
[7] R. People, IEEE J. Quantum Electron.
QE-22, 1696 (1986).
[8] C. Huyghebaert et al., IEEE Int. Electron Dev. Meeting (IEDM, Dec. 1-5, 2018) No. 22.1.
[9] M. Sakuraba et al., Thin Solid Films
517, 10 (2008).
[10] M. Sakuraba et al., Key Eng. Mat.
470, 98 (2011).
[11] N. Ueno et al., Thin Solid Films
557, 31 (2014).
[12] N. Ueno et al., ECS Trans.
64 (6), 99 (2014).
[13] M. Sakuraba, Research Proposal “Research and Development of Group IV Quantum Heterointegration Processing”, June 18, 2016, DOI: 10.13140/RG.2.1.1667.0322.
[14] T. Nosaka et al., Thin Solid Films
518, S140 (2010).
[15] M. Sakuraba et al., Chapter 4 in Book “Chemical Vapor Deposition (CVD): Types, Uses and Selected Research” (Nova Sci. Pub., Ed. M. Powell, 2017), pp.61-115.
[16] S. Sasaki et al., Mat. Sci. Semicond. Proc.
70, 188 (2017).
[17] M. Sakuraba et al., Sci. Technol. Adv. Mat.
18, 294 (2017).
[18] K. Motegi et al., Mat. Sci. Semicond. Proc.
70, 50 (2017).
[19] N. Ueno et al., Mat. Sci. Semicond. Proc.
70, 55 (2017).

Figure 1