bluuebunny/crossref_metadata_2025_split huggingface dataset:
A New Chemical Method of Wright Etch in the Delineation of Stacking Faults and Crystalline Defects in Fabrication Silicon Wafer Substrate
Authors: Hua Y. , Fong S.Y. 
Published: December 2020

Abstract
In wafer fabrication (fab), stacking faults (SF) & crystalline defects in the silicon substrate will affect the yield. Wright Etch is the most common chemical etching method used to delineate SF on both (100) & (111) silicon surface. However, when Wright Etch is used directly, no SF could be revealed, even if the fab wafers are etched up to 40 mins. The reason is that the fab wafers have thin films deposited on it. After delayering by using dry & wet etches and subsequently Wright Etch, the SF were revealed. But this method is tedious & time consuming as it requires a long time to delayer. Thus in this paper the possibility of using HF (aq) to deprocess fab wafer prior to Wright Etch is investigated. A new chemical etching method - 155 Wright Etch has been proposed. This method has been applied to failure analysis for two years in our FA labs. The analytical results show that it is a rapid & reliable method and is effective in the delineation of SF or crystalline defects on fab silicon wafers due to high temperature oxidation, junction spiking, silicon precipitation, contamination, charging damage, BVGO failure and contact chain failure during fab processes.
Gain Reduction in Silicon Phototransistors Induced by Metallization Mask Misalignment
Authors: Malberti P. , Ciappa M. 
Published: December 2020

Abstract
Silicon planar phototransistors in hermetic pig-tail metallic package for airborne system application failed the acceptance test because of low responsivity. No significant difference between the electrical characteristics of good and defective devices could be detected by systematic investigation of focusing lens, anti-reflecting coating, optical alignment, and by internal electrical microprobing. EBIC inspection instead revealed that all defective phototransistors were affected by an anomalous region with a very high photo-carrier generation rate. This effect was produced by the misalignment of the emitter metallization which partially exposed the emitter-base junction. Partial exposition of the emitter diffusion to impinging radiation generates an induced photocurrent in the emitter-base junction which has opposite direction with respect to the photocurrent induced in the base-collector junction. The extra photocurrent in the base-emitter junction reduces the emitter-base forward polarization and, as direct consequence, the phototransistor responsivity is lower.
Comparison Precision XTEM Specimen Preparation Techniques for Semiconductor Failure Analysis
Authors: Hunt C. A. 
Published: December 2020

Abstract
Transmission electron microscopy (TEM) is now commonly employed in semiconductor device quality control and failure analysis. Precision cross-section specimens (PXTEM) are often required - these are samples that isolate an extremely small volume such as a single failed transistor. PXTEM samples are among the most difficult TEM samples to prepare. It is important for laboratories that perform PXTEM to master a variety of techniques so that the issues of cost, quality, and risk can be properly balanced. This paper addresses these issues while explaining the most common methods of PXTEM preparation along with an illustrative case study.
The Application of FIB Voltage-Contrast Technique Combining with TEM on Subtle Defect Analysis: Via Delamination After TC
Authors: Yang X. , Song X. 
Published: December 2020

Abstract
Novel Focused Ion Beam (FIB) voltage-contrast technique combined with TEM has been used in this study to identify a certain subtle defect mechanism that caused reliability stress failures of a new product. The suspected defect was first isolated to a unique via along the row through electrical testing and layout analysis. Static voltage contrast of FIB cross-section was used to confirm the suspected open defect at the via. Precision Transmission Electron Microscope (TEM) was then used to reveal the detail of the defect. Based on the result, proper process changes were implemented. The failure mode was successfully eliminated and the reliability of the product was greatly improved.
Failure Analysis Challenges of Surface Micromachined Accelerometers
Authors: Saltmarsh M. P. 
Published: December 2020

Abstract
As more micro-electro-mechanical systems (MEMS) are going into volume production, unique challenges are being presented to the failure analyst. Although traditional electrical components have always had some degree of non-electrical concerns (e.g., chemical contamination, mechanical bond failure), MEMS components, which generally sense non-electrical signals, by their nature require more emphasis on their physical properties. This paper will discuss new applications of existing techniques, notably high resolution infrared and visible laser scanning microscopy to examine and obtain topological (3 axis) information of a silicon encapsulated micromachined accelerometer, both prior to and following decapsulation. The utilization of low intrusion electrical measurement instruments are discussed. A technique for removing a single polysilicon plate with minimal disturbance to an underlying polysilicon plate spaced less than a few microns apart is presented.
Novel Failure Analysis Technique “Light Induced State Transition (LIST)” Method Using an OBIC System
Authors: Nishikawa A. , Odani C. , Miura N. , Kohno Y. , Shimizu M. 
Published: December 2020

Abstract
This paper describes a new technique, called the Light-Induced State Transition (LIST) method, that uses an optical beam induced current (OBIC) system for failure analysis of CMOS LSIs. This technique allows the user to locate a low signal line shortcircuited to a GND bus (or a high signal line shortcircuited to a VDD bus) in stand-by condition, which is not possible with conventional failure analysis techniques such as photo-emission analysis, liquid crystal technique, or the conventional OBIC method. The effectiveness of the LIST method was verified by a experiment on inverter chains that included quasi-failures intentionally patched by FIB deposition. The LIST method has also been used for actual CMOS failure analysis, and has proved useful for finding a failure location rapidly.
Voltage Contrast Application on 1M SRAM Single Bit Failure Analysis
Authors: Luo D. , Song X. 
Published: December 2020

Abstract
A single bit failure is the most common and the most difficult failure mode to analyze in a Static Random Access Memory (SRAM). As chip feature sizes decrease, the difficulties compound. Traditional failure analysis techniques are often ineffective, particularly for high temperature operating life (HTOL) failures, because HTOL failures are most often caused by subtle physical defects. A new analysis approach, using Focused Ion Beam (FIB) cross-sectioning combined with FIB passive voltage contrast (PVC), greatly enhances the analysis success rate. In this paper, we outline the use of these new techniques and apply them to a technologically important problem.
The RAC Data Sharing Consortium: Sharing Test, Field and Failure Analysis Data
Authors: David Dylis D. 
Published: December 2020

Abstract
Many organizations perform component and equipment testing to ensure that parts in various applications and environments are robust and will operate reliably in the field. In addition, failure analyses are often performed to identify the cause of failures resulting from device testing and/or field usage. The Reliability Analysis Center (RAC) Data Sharing Consortium (DSC) accumulates data from these sources and assembles this data into a repository accessible to its members. This article discusses the purpose of the DSC, the benefits of DSC, and the data sharing agreement. It presents a list of organizations who are members of the DSC consortium and of organizations which are in the process of reviewing membership requirements. RAC's mission, the awards it has received, and its efforts towards developing and maintaining effective DoD systems are also covered.
Thermally Assisted Photoemission for CMOS Device Analysis
Authors: Symonds K. , Wilson J. 
Published: December 2020

Abstract
Enhancement of Existing Fault Isolation Techniques for CMOS VLSI Failure Analysis is important in keeping pace with device design and process technologies. Recently, we enhanced our photoemission microscopy capability by applying heat to the device during analysis1. This provided greater defect related light emission from nSRAM test structures and allowed identification of subtle failure modes not observable during room temperature inspection. In the present work, we investigate the theoretical dependencies of emission mechanisms and analyze experimental data to identify the dominant physical mechanisms involved with thermally assisted photoemission. We introduce a thermal factor to help quantify the effect from various light emitting structures. Experimentally, we find that emission mechanisms involving leaky and forward junctions are enhanced by temperature, and propose that the dominant factor for increased signal may be an increasing contribution from phonon absorption rather than phonon emission-based recombination. For emission mechanisms based on impact ionization; however, we find that the emission response is inversely proportional to temperature, and show that mobility degradation is the dominant limiting factor at higher temperatures.
Aluminum Interconnect Response to Electrical Overstress
Authors: Vinson J.E. 
Published: December 2020

Abstract
The response of aluminum interconnect to electrical overstress (EOS) is an important component of semiconductor reliability. Proper modeling of the fusing characteristics are necessary to build more robust circuits without wasting die area and allow estimation of the events that cause failures. This paper reviews previous work on aluminum EOS and presents experimental evidence of the mechanisms involved in aluminum EOS. From this evidence a simplified model is proposed based on the physical characteristics of the structure.
Passive Voltage Contrast Technique for Rapid In-Line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology
Authors: Liang Victor , Sur Harlan , Bothra Subhas 
Published: December 2020

Abstract
Three case studies in which the passive voltage contrast technique (PVC) was used in-fab during the development of a 0.25μm ASIC CMOS technology for rapid characterization and failure isolation are presented. The first case involved using the PVC technique to evaluate the gate oxide quality at different points of the process, allowing for quick identification of the process steps that were damaging the gate oxide and the relative magnitude of the damage that each process step contributed. PVC was then used to perform in-line evaluation of the split lots that were ran to address the problem without having to pull wafers off the line for electrical testing. In the second case study, PVC was used in-line to identify the source of siliciderelated gate-to-source/drain leakage. At this point of the process, electrical probing was not possible, and PVC circumvented this problem. The third case involved using PVC to help identify a new failure mechanism for tungsten plug vias that manifested itself due to plasma charging and layout peculiarities related to deep submicron design rules.
Auto-Fault-Locating-System for Mounting Boards
Authors: Nikaido M. , Yojima M. , Iida M. 
Published: December 2020

Abstract
In the process of fabricating high density mounting boards, locating faults in boards rejected in a functional test requires special circuit knowledge and skills, so it has been becoming more and more difficult to find the faults in a limited time. To address this problem, we have developed an Auto-Fault-Locating-System for mounting boards using a simple comparison technique and faulty net tracing algorithm. In the system, net-propagated faults are detected by comparing pulse-counts and voltages in good boards and faulty ones under full power supply. Faulty nets, which include the fault origin, are detected by tracing backward via a faulty propagation path using the input-output attribute of terminals. Measurements require 2.5 seconds per net (i.e., about 40 minutes for 1,000 nets), and searching faulty nets requires 10-20 seconds. The system successfully located the fault origin in 22 out of 25 boards rejected in a functional test. The located fault origins were found to be IC problems, pattern errors, open terminals and shorts between nets.
A Study on Discolored Bondpads and Galvanic Corrosion
Authors: Younan Hua 
Published: December 2020

Abstract
Discolored bondpads failure was investigated. SEM & EDX techniques were used to identify the root causes. The results show that discolored bondpads are caused by many holes on bondpads due to galvanic corrosion. It is most severe at power-line pads and less severe on rest of pads in the die. These bondpad holes have led to poor contact between the wire & integrated circuits and faulty computer chips. The holes are most likely to be caused by galvanic corrosion as there is a nucleus centered inside almost all holes. EDX results on the nucleus show high Cu concentration comparing to that on normal area. It is concluded that galvanic corrosion was due to DI water problem during wafer sawing at assembly. In this paper, the mechanism of galvanic corrosion will be further discussed.
The Logic Mapper
Authors: Smith Shawn 
Published: December 2020

Abstract
The Logic Mapper software created by Knights Technology bridges the gap between traditional yield enhancement techniques in the wafer fab and analytical failure techniques in the failure analysis (FA) laboratory. With Logic Mapper, fabs can test logic devices as easily as memory devices. Traditional logic chip yield enhancement techniques within product engineering and wafer fab yield enhancement organizations rely heavily on binsort functional test correlation to anticipate and correct semiconductor process issues. Some of the key shortcomings of these techniques are: · The inability to relate a particular bin’s fallout to a suspect process level. · The inability to distinguish a defect-driven yield issue from a device-integration issue. · The inability to establish a clear link between large populations of failed die. Logic Mapper resolves these key shortcomings by taking the output from functional testers and translating it from a list of failed scan chains into a list of suspected netlist nodes. Using Merlin’s FrameworkTM software, the netlist can be used to identify the X, Y coordinates of a suspected failing node; the failure analysis and yield enhancement engineers have created a starting point for investigating failures. These nodes can then be crossmapped from the circuit design onto the chip’s layout over multiple photomask layers within the design. The ability to translate a logic device’s binsort functional test fail data to defect traces is an advancement in the quality of test information provided for failure analysis and yield enhancement.
High-Yield and High-Throughput TEM Sample Preparation Using Focused Ion Beam Automation
Authors: Young R.J. , Carleson P.D. , Da X. , Hunt T. , Walker J.F. 
Published: December 2020

Abstract
Recent advances in the methods of preparing transmission electron microscope (TEM) samples using the focused ion beam (FIB) are presented. In particular, automation of TEM sample preparation is described. These automation methods, coupled with advances in ion column design, make it possible to prepare samples more efficiently and with less user involvement, thereby increasing FIB system utilization. Issues relating to sample handling and process-induced artifacts are also discussed.
Reduced Device Life Caused by Flux Entrapment During the Construction Process
Authors: Pierce James V. , Shuniak Lawrence F. 
Published: December 2020

Abstract
Devices that are sealed with a process using flux (all solder seals, some brazed seals some weld seals, etc.) will have residual flux entrapped. Devices with an internal construction such that areas exist where solvents can not completely clean surfaces exposed to flux vapor will also have residual flux entrapped. This entrapped flux will cause these devices to be susceptible to electromigration induced failure prior to the normal end-of-life of the device. If solder flux is trapped within a device, elevated temperature operation will shorten the life of the device. At elevated temperature, the activators in the flux will become a vapor and act as a catalyst for electromigration. Metal will be distributed across the surface between the "anode" and the "cathode" of the applied potential. The metal will be pulled from the "anode" to the "cathode". The electromigration can be stopped (or slowed) by reducing the maximum temperature the device will be exposed to when a potential is applied. If the amount of entrapped flux is not sufficient to bridge the gap between the "anode" and the "cathode" of the potential when in a non-vapor state (liquid or solid), the electromigration will be stopped when the temperature is below that needed for the flux activators to be in a vapor state. This paper contains details of this failure mode in hermetically sealed EMI filters and includes life test data (insulation resistance at elevated temperature), life reduction calculations, and photographs of the electromigration.
Application of Standard Metallurgical Analytical Techniques to Improve High Temperature Operational Life Performance of Bump Interconnect Technology of Flip Chip Packaging
Authors: Wills Kendall Scott , Abbott John , Carty Chris , Raghunathan Rohini , Simon Philip , Todd Charles , Vance Andy , Zhu Jianbai 
Published: December 2020

Abstract
Flip Chip packaging requires an understanding of the solder bump metallurgy and its aging characteristics. In this paper we demonstrate how standard failure analysis techniques can help determine aging characteristics and, how an understanding of bump age can be successfully employed to enhance bump reliability.
A Study of Effects of Backside Thinning on Integrated Circuits Using a Precision Diamond Wheel Apparatus
Authors: Roberts S.P. , Patterson J.M. 
Published: December 2020

Abstract
Recent advances in integrated circuit technologies and in interconnect methodologies to external electronics have made it extremely difficult to conduct failure analysis from the top side of the die (1,2). Therefore analysis techniques are being developed that allow analysis from the backside of the die. The first step in this process involves gaining access to the back of the die through the packaging material. Most backside analysis techniques require that the die then be thinned and polished. This paper describes specialized equipment and procedures to meet those requirements. The equipment is relatively inexpensive compared to other approaches.
OBIC Endpointing Method for Laser Thinning of Flip-Chip Circuits
Authors: Silverman Scott , Aucoin Richard , Ehrlich Daniel , Nill Kenneth 
Published: December 2020

Abstract
Laser microchemical etching systems provide enhanced through-wafer IR viewing and provide access for focused ion beam (FIB) tools and e-beam testers on flip-chip packaged die [1]. In demanding applications, laser etching is directed at rates of 100,000 cubic micrometers per second and must be stopped within 10 to 15 micrometers (thickness remaining) of the active flip-chip circuit. In cases where the initial die thickness is known, the laser process is sufficiently reproducible and system depth of focus is sufficiently narrow to place the laseretched floor within an accuracy of about plus or minus 5 micrometers relative to the initial surface of the die. However, greater accuracy is often desired to minimize FIB etch time. In addition, the laser step is often proceeded by a mechanical thinning operation on the die. This mechanical process introduces an uncertainty in initial part thickness, as well as part wedge and bowing. In this paper we describe an optical beam induced current (OBIC) method for accurate closed-loop endpointing with direct reference to the active device surface on the flipped die. The method relies on an exponentially increasing current that is induced by the laser as the device is thinned. Because of the strong absorption of the silicon bulk at visible wavelengths, the signal is sensitive to submicrometer thickness changes and, hence, may be used to stop the laser etching process with high accuracy at the desired 10 to 15 micrometer distance from the active circuit. The new technique has been studied on commercially available devices and shown to be insensitive to localized device junction density. Hence, endpointing is not highly dependent on the circuit design or exact placement of circuit elements. We outline the substrate and circuit properties that are most relevant to accurate implementation of the technique. The laser-etch process dependency of the OBIC signal has also been characterized. Simple high-speed closed loop electronics have been developed in order to apply the method for in situ endpointing New failure analysis/circuit debug techniques, including spectroscopic photoemission and picosecond time-resolved methods rely on observation of weak optical signals through the wafer. These would optimally be viewed though a remaining silicon thickness of a few micrometers or less. The limits of the OBIC endpointing method have been explored for the high-speed preparation of ultra thin local viewing windows in support of these new techniques.
Non-Invasive Backside Failure Analysis of Integrated Circuits by Time-Dependent Light Emission: Picosecond Imaging Circuit Analysis
Authors: Kash J.A. , Tsang J.C. , Knebel D.R. , Vallett D.P. 
Published: December 2020

Abstract
A noninvasive backside probe of integrated circuits has been developed. This new probe can diagnose at-speed failures, stuck faults, and other defects. Because it is a highly parallel imaging technique, faults may be isolated which are difficult to locate by other methods. This optical technique has been named “PICA”, for picosecond imaging circuit analysis. PICA relies on the fact that an FET in a CMOS circuit emits a picosecond pulse of light each time the logic gate changes state. The source of this emission is explained. The PICA technique, which combines optical imaging of the emission with picosecond time-resolution, is described. Because of the imaging, time-resolved emission data is acquired for many transistors in parallel. The use of the emission for failure analysis and AC characterization of integrated circuits is demonstrated. Because the emission can be detected from either the front or back side of the chip, it can be used for both front and back side analysis.