bluuebunny/crossref_metadata_2025_split huggingface dataset:
Change in Thermal Conductivity By Hydrogen Intercalation in Amorphous WO3 Film
Authors: Nakamura Ayano , Harada Shunta , Kobayashi Ryota , Tagawa Miho , Ujihara Toru 
Published: February 2020

We are developing “thermal switching materials”, whose thermal conductivity varies over a wide range. It has a wide range of applications such as temperature controls, thermal energy storages and so on. WO3 is expected as a thermal switching material because the electrical conductivity of WO3 can widely change owing to the metal-insulator transition (MIT) caused by hydrogen interactions. Moreover, hydrogens can be intercalated into and deintercalated from WO3 film reversibly and quickly by an electrochemical reaction. Therefore, the thermal conductivity is expected to change reversibly. Here, we report the thermal conductivity changes in WO3 film associated with hydrogen intercalations.
WO3 film was prepared on ITO coated glass at room temperature by RF magnetron sputtering method in an Ar-O2 atmosphere. The total pressure and the oxygen content of the atmosphere were 4.0 Pa and 13%, respectively. The thickness of WO3 film was 0.7-1.4 μm. Hydrogen intercalations into WO3 film on ITO coated glass were performed in an 0.5 M H2SO4 electrolyte with a Pt counter electrode and a calomel reference electrode. The structure of the films was determined by x-ray diffraction analysis. The thermal diffusivity of the films was measured by an ac calorimetric method and the thermal conductivity was calculated by the differential method using measured thermal diffusivity. The electrical conductivity was measured by a four-point probe method.
X-ray diffraction measurements showed that the WO3 films were amorphous. The value of thermal conductivity decreased with increasing hydrogen content x in H
x
WO3, from x = 0 to x = 0.33, and the value of thermal conductivity increased markedly with increasing x above x = 0.33. The hydrogen content of x = 0.33 is close to that of MIT. On the other hand, the electrical conductivity after MIT was 1×105 times higher than that before MIT. However, a variation of the electron thermal conductivity given from the electrical conductivity by the Wiedemann-Franz law is much smaller than a variation of the thermal conductivity. Therefore, the lattice thermal conductivity is expected to contribute to a change in the thermal conductivity. Present results indicate that the thermal conductivity of WO3 film can be controlled by hydrogen intercalations and potentialize the hydrogen-induced active control of thermal switches.
Low Temperature Microwave Anneal in FinFET Fabrication
Authors: Kassim Joseph , Lee Rinus T.P. , Krishnan Rishikesh , Ferrer Domingo , Yang Jie , Shusterman Yuriy , Ramirez Isreal , Liu Huang , Lui Jinping , Krishnan Bharat 
Published: February 2020

Low temperature anneal solutions are attractive for 7 nm CMOS transistor fabrication and beyond. This desire is necessitated by the introduction of new materials, novel integration flows and alternate device architectures that are incompatible with high temperature anneal solutions. Recently, microwave anneal has emerged as a potential approach for low temperature processing.
We have demonstrated an alternate low temperature anneal run path using microwave anneal for Titanium silicidation. The best in class microwave annealed split had matched contact resistivity and slightly improved device performance relative to the mSec annealed control wafer. HRTEM of both anneal processes revealed comparable silicidation.
Moreover, we demonstrated densification of FCVD grown oxide using low temperature microwave anneal. The wet etch rate ratio (WERR) achieved was comparable to that obtained from high temperature steam oxidation process. This low temperature process could be highly useful for fabrication of devices that use materials that suffer from unwanted diffusion, oxidization, and defects resulting from high temperature anneals.
Keywords—microwave, anneal, activation, trench, contacts, silicide, TiSi, FinFET, processes, materials.

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(Invited) a Novel Metallization Process Using Slotogo As a Conducting Layer for HDI-Msap and Cu Pillar Applications
Authors: Yeh Ding-Chiang 
Published: February 2020

With the demand of miniaturization, multifunction, and faster manufacturing for package substrates and the 3D packaging technology, fabricating high-density interconnection printed circuit boards (HDI PCBs) with a smaller line-space ratio becomes a challenging problem. There are several critical issues of conventional HDI-mSAP process: (1) Low thickness uniformity between the high-dense trace and the ground area. (2) Not only the planarity of the lines is greater than 20% but also voids and missing vias appear during copper via-filling plating. (3) It is not vialbe when line/space design is smaller than 30/30 um. On the other hand, copper (Cu) pillar bump seems promising in design for the next generation interconnections, there are still some issues such as low productivity, non-uniformity, and high energy consumption in manufacturing. Therefore, we developed SLOTOGO by using reduced Graphene Oxide (rGO) as a conducting layer to solve HDI-mSAP and Cu pillar problems.
In this study, the filling performance of micro via can get the extra-thin plated surface Cu by rGO special property in 3D narrow space. By modifying the mSAP process, two steps are needed for Cu plating: (1) via filling (2) pattern plating for line trace. By doing so, we can not only increase the via filling power to avoid the impurity of the residual dry film in the hole but also achieve the excellent planarity of the line by reverse pulse plating. Moreover, using rGO on pattern plating of Cu pillar also can improve the yield by using only 1/10 of the energy as opposed to the conventional process. Hence, with the SLOTOGO, the defects in conventional mSAP and Cu pillar process can be avoided and the manufacturing quality of HDI can be greatly improved.
Polymer and Bump Planarization for Fine Pitch Micro-Bump Stacking
Authors: Inoue Fumihiro , Derakhshandeh Jaber , Moeller Berthold , Gokita Yohei , Duval Fabrice , Bex Pieter , Capuz Giovanni , June Rebibis Kenneth , Miller Andy , Sleeckx Erik , Beyer Gerald , Beyne Eric 
Published: February 2020

Advanced packaging, including fan-outs, 2.5D and 3D integration is gaining more interests as alternative driving force for performance improvement instead of scaling. A key element for the advanced packaging is interconnection technology between different chips. Flip chip micro-bumping enables electrical connection of different chips with shorter length than that of wire bonding. Although it is promising method for advanced packaging, there are several challenges need to be tackled to obtain robustness stacking below 10 μm pitch. For instance, the mechanical stability of micro-bumps become low due to the shape of the bumps. The bump height uniformity also becomes an issue when the pitches shrunk. In addition, the thermo-compression bonding (TCB) alignment and stacking will require incredibly high accuracy tool. In order to overcome these issues, alternative concept of flip chip bumping structures, which is embedded bump was introduced [1]. In this embedded bump concept, neither top nor bottom surfaces have topography, which improves the mechanical stability. In addition, it can be feasible in high-accuracy TCB process.
One of the challenge for this concept is to planarize Sn bumps and polymer. The well-known method for material planarization in CMOS technology is chemical mechanical polishing (CMP). However, optimization of polishing on soft adhesive polymer and metal Sn bump requires comprehensive CMP development. On the other hand, pure machining process such as flat milling has wider range of process window. Therefore, we are investigating to apply a single diamond flat milling process, so called surface planer, for this embedded bump concept. The surface planer process is able to mechanically remove polymer top surface and bumps by a diamond bit.
In the presentation, we will report characterization results of surface planer process for embedded bump concept. In addition, the stacking performance on 10 μm pitch bumps are shown. The middle images in the figure show that the planarized adhesive polymer and 10 μm pitch bump (top: schematic image, bottom: actual cross-sectional FIB image). The step height between bump and polymer is about 200 nm. By the planarization process, 10 μm pitch of Sn bumps can be connected by thermal compression bonding with minimum misalignment. By this feasibility study of polymer/bump planarization process, compatibility and challenges of embedded bump concept were laid out.
[1] Jaber derakhshandeh et al,” 3D Stacking Using Bump-Less Process for Sub 10um Pitch Interconnects” ECTC2016

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Transition Layer Thickness Control in Additive-Assist Electroplated Nanotwin Copper
Authors: Chung Stream , Chen Yao-Tsung , Chen Zong-Cyuan 
Published: February 2020

Unidirectional (111) nanotwin copper has shown exceptional performance such as thermal stability, mechanical strength, fatigueless behavior, electromigration resistance, electric conductivity, low bonding temperature, and ultra-large grain growth. These unique properties make it a promising solution to several IC applications including fine line RDL in fan-out WLP, copper direct bond in 3D IC vertical interconnect, high conductivity Cu interconnect for VLSI etc. Both electrochemical deposition and physical vapor deposition are able to form such microstructure, and electrochemical deposition is considered the suitable production method in terms of process flexibility, throughput, and overall cost. Direct current was successfully applied to nanotwin copper formation in many reports, but the common feature of these tests is using low or no acid electrolyte with pH around 1. This approach greatly hinders the industrial implementation because of poor deposit uniformity from low electrolyte conductivity. Pulse plating with low duty cycle was also tried, and able to produce nanotwin in high acid electrolyte. However, throughput and hardware cost are the downside of this method. Another approach is DC plating with additives of crystal plane adsorption selectivity, and then electrolyte acid concentration over 100g/L could be used to form nanotwin copper. During the preferred orientation grain development, a micrometer transition layer between non-nanotwin substrate and columnar nanotwin grain is formed. The transition layer thickness is found sensitive to substrate copper grain orientation as well as electrolyte acid concentration, and may dominate the material property when overall deposition thickness reduces in fine line RDL application. In order to reduce the transition layer thickness, two additive modification approaches are demonstrated in this paper. The first one is to increase columnar grain nucleation density by reducing nucleation overpotential, and the second one is to increase lateral grain growth rate by increasing nucleation overpotential. The prior approach results in smaller columnar grain diameter, and the later one results in larger columnar grain diameter. Both approaches are effective in reducing transition layer thickness.
Figure Caption: Transition layer boundary represented by green dash line on TiW/Cu substrate. (a) thick, irregular transition layer with nt-Cu additive. (b) thin transition layer with modified nt-Cu additive increasing substrate nucleation sites.

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(Invited) Deep-Level Analysis of Passivation of Transition Metal Impurities in Silicon
Authors: Mullins J. , Markevich Vladimir , Leonard S. , Halsall M.P. , Peaker A.R. 
Published: February 2020

Experimental results on the interactions of transition metal (TM) impurities with hydrogen and on passivation by the displacement of the metals from interstitial to substitutional sites in crystalline silicon will be presented in this talk. Iron, titanium and vanadium from the 3d series, and Zr and Mo from the 4d series have been studied. The results have been obtained by means of deep level transient spectroscopy (DLTS), high resolution Laplace DLTS, minority carrier transient spectroscopy and secondary ion mass spectroscopy.
The 3d metals are the most important TM series in relation to recombination in silicon. The most recombination active site is with the 3d metal in an interstitial position. It is found that in the presence of excess vacancies 3d TMs tend to move to substitutional sites and are quite stable in this position with no or much reduced recombination activity and much reduced diffusion.
The experimental results on passivation of TMs with hydrogen show that in general the reactions of H atoms with TM impurities are much more effective in n-type material than in p-type Si. These findings can be easily explained considering charge states of the interacting species. Essentially the initial H-TM reaction is driven coulombically at equilibrium conditions. We have managed to promote reactions of hydrogen atoms with Fe, Mo and V impurities in p-type silicon by changing charge states of the interacting defects either by shifting the Fermi level upon the application of reverse bias to Schottky barrier diodes or by illumination of the contaminated and hydrogenated Si samples with the use of light emitting diodes with photon energies above the Si band gap energy.
It has been found that the binding of hydrogen to the metal atoms, in all cases we have examined, is rather weak … of the order of 2 eV. This implies that the passivated fraction of the TMs resulting from the reaction of hydrogen with metals in bulk silicon is diminishingly small at device processing temperatures.
Based on the results obtained we try to understand some of the previously published data on lifetime improvement in Si crystals by hydrogenation. In some of the commercially important cases, particularly those reporting on multi-crystalline slices, this is far from simple as other important effects such as enhanced diffusion, precipitation and gettering can take place during hydrogenation simultaneously with hydrogen-metal reactions. It appears that in some cases hydrogen-metal reactions does not seem to be the most important processes in enhancing the minority carrier lifetime of the silicon.
(Invited) Dual-Gate and Gate-All-Around Polycrystalline Silicon Nanowires Field Effect Transistors: Simulation and Characterization
Authors: Salaun Anne-Claire , Le Borgne Brice , Pichon Laurent 
Published: February 2020

The need of miniaturization following Moore’s law has intensified research efforts on silicon nanostructures such as nanowires or nanoribbons that can be used as active part of electronic nano-devices. In this way, nanowires offer great potential as field effect transistors channel region for ultra large scale integration electronics, and also as sensitive units for the detection of charged biochemical species for sensors on CMOS platforms. Top-down approach favors patterning architectures in a planar layout, most of the SiNWs are patterned on high cost silicon-on-insulator substrates (SOI). Polycrystalline silicon SiNWs (poly-SiNWs) synthesis using sidewall spacer top down method seems to be a lower cost alternative, fully compatible with planar complementary metal oxide semiconductor (CMOS) silicon technology. In such new gate architecture passing from 2D to 3D, surrounding-gate transistors, called Gate-All-Around (GAA) where the gate circles the nanowire channel, allow a better electrostatic gate control.
In our study, nanowires are elaborated using a classical fabrication method commonly used in microelectronic industry: the sidewall spacer formation technique. Assets of this technological process rest on the use of low cost lithographic tools, and the possibility to get by direct patterning numerous parallel nanowires with precise location on the substrate. We develop a low temperature (≤ 600°C) fabrication process of top-gate, bottom-gate and GAA FETs. Independent biasing of each gate allows a possible threshold voltage control of these bottom gate (BGT), top gate transistors (TGT) and GAA architecture. Electrical performances are analyzed as a function of the density of state highlighting oxide/semiconducting nanowire interfaces difference in top and bottom gate configurations. Applications for chemical and biochemical species sensing have also been investigated.
Channel-Length Dependent Performance Degradation of Thermally Stressed IGZO TFTs
Authors: Kabir Muhammad Salahuddin , Ganesh Prashant , Chowdhury Rahnuma Rifat , Sethupathi Harithshanmaa , Okvath Julia , Konowitch Jason , Manley Robert G. , Hirschman Karl D 
Published: February 2020

The focus of this work is on the performance degradation of thermally stressed IGZO TFTs with SiO2 for both the gate dielectric and back-channel passivation material. The TFT fabrication process included a post-passivation 400 °C O2 anneal to adjust the IGZO semiconductor properties. I-V characteristics of TFTs with bottom-gate (BG) and double-gate (DG) electrode configurations were observed to left-shift and degrade with 200 °C hotplate treatments as shown in Fig. 1. The mechanism causing the instability is not completely understood, however experimental results indicate the instability occurs either directly or indirectly due to the influence of H2O within the passivation oxide above the IGZO channel region. The instability of DG devices was consistently more pronounced, suggesting a reaction between H2O and the aluminum top-gate electrode resulting in the liberation of monatomic hydrogen. This interpretation is supported by complementary experiments on MOS capacitors fabricated on bulk silicon substrates. The application of an alumina capping layer deposited by atomic layer deposition (ALD) was successful in improving thermal stability, with representative results shown in Fig. 2.
While most BG capped devices remained stable over several successive thermal treatments, DG devices demonstrated the onset of degradation with noted variation in both the time required and occurrence frequency. The analysis revealed an unanticipated dependence on channel length, with long-channel devices (L = 48 µm) being much more prone to an early onset of degradation compared to shorter devices (L = 12 µm) as shown in Fig. 2. With H2O remaining as the expected origin of thermal instability, a hypothesis has been developed to explain the observed channel length dependence. The results are consistent with the molybdenum source/drain contact regions acting as gettering sites for H2O molecules during the 400 °C annealing process. The removal of H2O from the back-channel region is a two dimensional process limited by the diffusivity of water, with the process more complete in short channel devices. Remaining H2O molecules at or near the back-channel interface in long-channel devices are able to migrate during thermal stress treatments, establishing complete coverage on devices that experience degradation. Experiments which explore the addition of getter features on or adjacent to the back-channel region, as illustrated in Fig. 3, in addition to localized materials analysis techniques such as secondary ion mass spectroscopy (SIMS) will provide additional evidence either in support or denial of the proposed hypothesis.

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(Invited) Multi-Terminal Oxide-based Electric-Double-Layer Thin-Film Transistors for Neuromorphic Systems
Authors: He Yongli , Wan Qing 
Published: February 2020

Our brain is a highly parallel, energy efficient and event-driven information processing system, which is fundamentally different from traditional von Neumann computers. Neuron is the most important building block, and information processing in individual neuron involves the transformation of input synaptic spike train into an appropriate output spike train. Inspired by biological neural computing, neuromorphic systems may open up new paradigms to deal with complicated problems such as pattern recognition, classification and decision making. The idea of building brain-inspired adaptive artificial devices has been around for decades, and hardware implementation of neuron by individual ionic/electronic hybrid device is of great significance for enhancing our understanding of the brain and solving sensory processing and complex recognition tasks. Although two-terminal memristors can performe some basic synaptic and neural functions, our human brain contains many more synapses than neurons. This fact suggests that multi-terminal devices are more favorable for complex neural nwtwork emulation. In recent years, multi-terminal electric-double-layer (EDL) Thin-film transistors (TFTs) based on interfacial ion-modulation have attracted significant attention in mimicking synaptic dynamic plasticity and neural functions. Here, we provide the proof-of-principle artificial synapses/neurons based on solid electrolytes coupled oxide-based EDL TFTs with multiple driving and modulatory inputs terminals. Paired-pulse facilitation, dendritic integration and orientation tuning were successfully emulated. Additionally, neuronal gain control (arithmetic) in the scheme of rate coding is also experimentally demonstrated. Our results provide a new-concept approach for building brain-like cognitive systems.
References
[1] Feng Shao, Changjin Wan, Ping Feng, Xiang Wan, Yi Yang, Liqiang Zhu, Yi Shi, and Qing Wan*, “Multifunctional Logic Demonstrated in a Flexible Multi-Gate Oxide-based Electric-Double-Layer Transistor on Paper Substrate”, Advanced Electronic Materials. 3, 1600509, (2017).
[2] Changjin Wan, Liqiang Zhu, Yanghui Liu, Ping Feng, Zhaoping Liu, Hailiang Cao, Peng Xiao, Yi Shi, and Qing Wan*, “Proton Conducting Graphene Oxide Coupled Neuron Transistors for Brain-Inspired Cognitive Systems”. Advanced Materials. 28, 3557 (2016).
[3] Xiang Wan, Yi Yang, Yongli He, Ping Feng, Wenjun Li, and Qing Wan*, “Neuromorphic Simulation of Proton Conductors Laterally Coupled Oxide-based Transistors with Multiple In-Plane Gates”, IEEE Electron Device Letters. 38, 525-528 (2017).
[4] Liqiang Zhu, Changjin Wan, Liqiang Guo, Yi Shi, and Qing Wan*. “Artificial Synapse Network on Inorganic Proton Conductor for Neuromorphic Systems” Nature Communications, 5. 3158 (2014).
[5] Jie Jiang, Qing Wan*, Jia Sun, and Aixia Lu, “Ultralow-voltage transparent electric-double-layer thin-film transistors processed at room-temperature”, Applied Physics Letters.95, 152114 (2009)

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