bluuebunny/crossref_metadata_2025_split huggingface dataset:
Failure Analysis Methodology on Unique 68mm Single Ring Pattern Due to Load Lock Burr
Authors: Quah A.C.T , Ang G. B. , Chen C. Q. , Zhu David , Gunawardana M. , Indahwan J. , Lee M.T. , Neo S.P. , Chen Y. 
Published: December 2020

Abstract
This paper describes a low yield case which results in a unique 68 mm single ring wafer sort failure pattern. A systematic problem solving approach with the application various FA techniques and detailed Fab investigation resolved the issue. The root cause for the unique ring failure pattern was due to a burr at the implanter load lock. The burr scratched and toppled the photoresist resulting in subsequent blocked well implantation and memory failure.
Acoustic Micro Imaging of Large Objects
Authors: Sullivan Daniel J. D. , Guzman Jesse A. 
Published: December 2020

Abstract
Scanning acoustic microscopy (SAM) has been in use for the analysis of small devices, mostly ICs, for quite some time. [1] This paper address the use of the technique on larger objects, such as solar panels, PCBs, and brazed cooling plates, the issues that arise, and solutions to mitigate those issues.
New Failure Analysis Method for Laser Voltage Probing (LVP) Utilizing System Evaluation Board and Software
Authors: Lee Suk Ho , Lee Yun Woo , Hong Moo Jong , Yun Sung Jun , Lee Eun Cheol , Hong Kyu Shik 
Published: December 2020

Abstract
Due to the development of semiconductor’s fabrication and design technologies, SOC (System-On-Chip) products have been improved to enable development of a one-chip solution, which integrates a high performance main processor and various IP blocks. With this successful technical development, it is necessary to have a high speed interface that is complicated between the main processor and each IP block, but this can be problematic when the interface must support system level functions even though each IP alone does not have any problem. Most semiconductor companies and those doing Failure Analysis (FA) have adopted Automatic Test Equipment (ATE) because of its efficiency, but in cases where faulty products are detected at the customer site with their specific set of operating functions, the FA engineers have difficulties because of the challenge to convert customer’s functions to ATE test functions. To get through such a difficult situation, this paper presents a novel FA solution, utilizing Laser Voltage Probing (LVP) and set evaluation software and hardware, instead of ATE. This new FA technique can reduce the time to solve a system level application problem, improve FA quality with accurate timing analysis (detecting a 400ps signal glitch) and meet customer satisfaction by improving product quality. Fundamentally, the results of this paper compensated for the weakness in design procedures of IP blocks or products by adopting an additional simulation tool, which should prevent the recurrence of same-type errors.
Evaluation of Electrical Properties of Cell Area on the Semiconductor Devices by FIB Technique
Authors: Oh Jangwon , Kim Jonghyeb , Lee Jonghak , Kim Jongmin , Back Taesun , Kim Won , Kim Hojoung , Kim Changreol 
Published: December 2020

Abstract
We have demonstrated the sample fabrication by focused ion beam (FIB) milling and delineation etch gas which makes it possible to directly measure resistance in a cross section of semiconductor devices with a nano probe after cell fabrication. With direct evaluation of electrical properties, this technique can help improve semiconductor devices.
The “Perfect Storm” Now Appearing in FA Labs Everywhere
Authors: Shade Gary F. , Sood Bhanu 
Published: December 2020

Abstract
The International Symposium for Testing and Failure Analysis (ISTFA) 2010 event added a focus topic on Counterfeiting in Electronics. This topic was chosen because of the emergence of this concern and the critical role that Failure Analysis plays in this challenge. Failure Analysts will be involved deeply as companies worldwide are attempting to reduce the impact of increasing numbers of counterfeit products in the supply line and in fielded products. This paper will attempt to provide an overview of the topic and support the contributors to ISTFA 2010 while providing additional resources for information.
Fault Isolation of Open Defects Using Space Domain Reflectometry
Authors: Xie Mayue , Qian Zhiguo , Pacheco Mario , Wang Zhiyong , Dias Rajen , Talanov Vladimir 
Published: December 2020

Abstract
Recently, a new approach for isolation of open faults in integrated circuits (ICs) was developed. It is based on mapping the radio-frequency (RF) magnetic field produced by the defective part fed with RF probing current, giving the name to Space Domain Reflectometry (SDR). SDR is a non-contact and nondestructive technique to localize open defects in package substrates, interconnections and semiconductor devices. It provides 2D failure isolation capability with defect localization resolution down to 50 microns. It is also capable of scanning long traces in Si. This paper describes the principles of the SDR and its application for the localization of open and high resistance defects. It then discusses some analysis methods for application optimization, and gives examples of test samples as well as case studies from actual failures.
FemtoFarad/TeraOhm Endpoint Detection for Microsurgery of Integrated Circuit Devices
Authors: Colvin Jim 
Published: December 2020

Abstract
Interactive electrical endpoint detection when thinning conductive and capacitive materials opens the door to approaching a suspect site in an IC without relying on the traditional iterative approach. Controlled approach of embedded conductors in insulators (packages) as well as controlled die thinning with submicron control will be shown, allowing safe approach to the desired feature without overshoot.
Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology
Authors: Tsang Yuk L. , Wang Xiang D. , Ricklefs Reyhan , Goertz Jason 
Published: December 2020

Abstract
In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.
Words for the “Whys”
Authors: Ross Richard J. 
Published: December 2020

Abstract
In an era where the complexity and cost of Failure Analysis tools and techniques is rapidly expanding, it is easy sometimes to lose sight of the basic tool and technique required for successful root-cause analysis. That technique is intellectual curiosity and the tool is the human brain. This paper will describe a simple methodology to insure that this tool and technique are properly engaged either concomitant with or in the absence of state-of-the-art instrumentation and computation. Two simple case studies will be used to illustrate where the Failure Analysis process can easily go awry without proper attention to detail, and, conversely, from too much attention to detail.
Lock-in Thermography-Based Local Efficiency Analysis of Solar Cells
Authors: Breitenstein Otwin 
Published: December 2020

Abstract
The electronic properties of solar cells, particularly multicrystalline silicon-based ones, are distributed spatially inhomogeneous, where regions of poor quality may degrade the performance of the whole cell. These inhomogeneities mostly affect the dark current-voltage (I-V) characteristic, which decisively affects the efficiency. Since the grid distributes the local voltage homogeneously across the cell and leads to lateral balancing currents, local light beam-induced current methods alone cannot be used to image local cell efficiency parameters. Lock-in thermography (LIT) is the method of choice for imaging inhomogeneities of the dark I-V characteristic. This contribution introduces a novel method for evaluating a number of LIT images taken at different applied biases. By pixel-wise fitting the data to a two diode model and taking into account local series resistance and short circuit current density data, realistically simulated images of the other cell efficiency parameters (open circuit voltage, fill factor, and efficiency) are obtained. Moreover, simulated local and global dark and illuminated I-V characteristics are obtained, also for various illumination intensities. These local efficiency data are expectation values, which would hold if a homogeneous solar cell had the properties of the selected region of the inhomogeneous cell. Alternatively, also local efficiency data holding for the cell working at its own maximum power point may be generated. The amount of degradation of different cell efficiency parameters in some local defect positions is an indication how dangerous these defects are for degrading this parameter of the whole cell. The method allows to virtually 'cut out' certain defects for checking their influence on the global characteristics. Thus, by applying this method, a detailed local efficiency analysis of locally inhomogeneous solar cells is possible. It can be reliably predicted how a cell would improve if certain defects could be avoided. This method is implemented in a software code, which is available.
Analysis of Fractures of Printed Circuit Board Traces
Authors: Nail Carl , Rice Larry 
Published: December 2020

Abstract
A PCB trace was repeatedly cracking in the same location. Visual inspection showed cracking there and at structurally similar locations, with solder mask missing from one side of the trace of interest. Fracture analysis suggested that these issues and etch pitting caused crack initiation, followed by fatigue failure that ultimately led to full fracture. A FIB section of a second failure reinforced the finding that the fundamental cracking mechanism was fatigue.
Characterization of Ion Beam Current Distribution Influences on Nanomachining
Authors: Tan Shida , Livengood Richard H. , Greenzweig Yuval , Drezner Yariv , Hallstein Roy , Scheffler Chris 
Published: December 2020

Abstract
The requirements for focused ion beam (FIB) systems to provide higher image resolution and machining precision continue to increase with the continuation of Moore’s Law. Due to the shrinking geometry and increasing complex structures and materials, it is ever more critical to scale the entire ion probe. The necessity for comprehensive analysis of the ion beam profile and understanding how the ion beam current distribution profile influences different aspects of nanomachining are becoming increasingly important and more challenging.
Photon Emission Microscope as a Tool for 3-Dimensional Semiconductor Device Failure Analysis
Authors: Chun Steven J. 
Published: December 2020

Abstract
A three dimensional (3-D) photon emission failure analysis method has been developed to pinpoint failure sites or emission sites on the x, y, and z planes of a degraded diode. The 3-D analysis consists of a cross-sectioning step process on two adjacent sides of a diode utilizing two photon emission sites from respective sides of the die as a map. This process negates the uncertainty and long processing times during cross-sectional analysis to find minute defects in diodes.
Scan Chain Bridge Defect on a 28 nm Technology Node Circuit, Localization Using Dynamic Power Supplies
Authors: Parrassin Thierry , Petit Emmanuel , Celi Guillaume , Mousseau Yann , Dudit Sylvain 
Published: December 2020

Abstract
The bridge defect is one of the most difficult defects to locate. When classical static and dynamic optical techniques reach their limits, applying a dynamic signal on the power supplies for stimulating the defect allows obtaining useful additional information helping the localization. In this paper, we explore these techniques on a real case analysis of bridge defect in a scan chain on a 28nm technology node circuit. We will show that OBIRCH, LVI, static & dynamic EMMI do not give significant signatures for the defect localization. Finally we show that EMMI and LVI signatures applying a clock on the power supply bring relevant information to locate efficiently the defect.
Marginal RF Gain Investigation and Root Cause Determination
Authors: Harber Keith , Brockett Steve 
Published: December 2020

Abstract
This paper outlines the failure analysis of a Radio Frequency only (RF-only) failure on a complex Multimode Multiband Power Amplifier (MMPA) module, where slightly lower gain was observed in one mode of operation. 2 port S-parameter information was collected and utilized to help localize the circuitry causing the issue. A slight DC electrical difference was observed, and simulation was utilized to confirm that difference was causing the observed S-parameters. Physical analysis uncovered a very visible cause for the RF-only failure.
Anamnesis in Failure Analysis—How a System-Related Approach Can Save Failure Analysis (FA) Time, Shorten Learning Loops and Reduce Cost
Authors: Jacob Peter 
Published: December 2020

Abstract
Anamnesis is known as an important method for pre-diagnosis in medical sciences. In device failure analysis (FA) it is not so far used, yet – especially with regard to system- and application-aspects. As a consequence, a lot of useless rootcause-related FA efforts are done on device level, while the root cause is on system level. Introduced by an illustrative case study, the benefit of a suitable anamnesis is shown as well as the way to do it – by posing the right questions before FA starts. Many FA efforts can be saved or optimized and frequently, a sound anamnesis already may lead towards the root-cause conclusion.
Advantage of AFP Nanoprobing on the 28 nm Technology Failure Analysis
Authors: Chen C.Q. , Ang G.B. , Zhao S.P. , Alfred Q. , Dayanand N. , Dnyan K. , Liu B.H. 
Published: December 2020

Abstract
As the rapid developments of semiconductor manufacturing technologies, the CD of the device keep shrinking. The IC devices have a smaller feature sizes and higher densities, and thus there are many challenges come up in terms of the failure analysis and localized device characterization. Besides the challenge of smaller feature size, there is another challenge as well. Some of the traditional FA method can no longer be employed on advanced technologies, such as 28nm and beyond. Quickly and successfully isolating the failed location and obtaining electrical signature of the defect has become more of a challenge, especially for the device level analysis and characterization. AFP nanoprobing system provides some solutions to advanced nodes fault isolation through its AFM imaging mode of CAFM.
Applications of Nanoprobing for Localization of Design for Manufacturing Issues on Analogue-to-Digital Converter on Advanced Technology Node
Authors: Quah A.C.T. , Chen C.Q. , Ang G.B. , Nagalingam D. , Li Y. , Zhu J. , Neo S.P. , Zhao S.P. 
Published: December 2020

Abstract
This paper describes 2 case studies where device characterizations using Atomic Force Probe (AFP) nanoprobing, allow for the localization and verification of design weakness and process variations on the Analog-to-Digital (ADC) block that resulted in degraded device performance and severe yield loss. In these cases, the sensitive resistor structures in the ADC block was impacted due to design pattern density interaction with process fabrication steps. In addition, close collaboration with customer was also essential for quick root cause identification, design and process fix.
Nondestructive Analysis Solution Using Combination of Lock-In Thermography (LIT) and 3D Oblique X-Ray CT Technology
Authors: Seimiya Naoki , Watanabe Takuhei , Ichinomiya Takashi 
Published: December 2020

Abstract
We developed the non-destructive failure analysis method that is combination of Lock-in thermography (LIT) and high resolution 3D oblique CT. It made possible to complete the total analysis efficiently, because we can distinguish the type of failure by this non-destructive method.
Advanced Fault Localization through the Use of Tester Based Diagnostics with LVI, LVP, CPA, and PEM
Authors: Safran Laura , Sylvestri John , Albert Dave , Song Zhigang , McGinnis Patrick 
Published: December 2020

Abstract
Fault localization on functional macros during advanced technology development requires a complex combination of tester based diagnostics and image based techniques including laser voltage imaging (LVI), laser voltage probing (LVP), critical parameter analysis (CPA) with laser stimulation and photon emission microscopy (PEM). These techniques are exemplified in the following three case studies. The first case involves a voltage sensitive SRAM block fail which was localized to a resistive via through the use of CPA, LVI and LVP. The second case demonstrates how a hard fail (a net-to-net metal short) in a scan chain was localized through use of tester based diagnostics, LVI, LVP and PEM. Finally, the last case shows how a condition sensitive failing latch chain was localized through CPA, LVI, LVP and PEM. Subsequent atomic force probing (AFP) identified source-drain leakage in one of the localized devices, and TEM analysis revealed a dislocation in the failing FET. Each of these cases demonstrates the value in utilizing tester based diagnostics along with laser based imaging and photon emission microscopy to localize failures.
Optimization of Soft Defect Localization Technique Scan Time Using Dummy Subroutine Test Vector Insertion
Authors: Yeoh B.L. , Goh S.H. , Chan Y.H. , You G.F. , Koh Y.E. , Lam Jeffrey 
Published: December 2020

Abstract
Soft Defect Localization (SDL) is a laser scanning methodology that is commonly used to isolate integrated circuits soft defects. The device is exercised by a functional vector set in a loop manner while localized laser heating stimulates a change in the pass/ fail (P/F) response at the location of the defect or critical path. Although SDL is effective for this purpose, long scan time arising from test overheads, can be a concern to turnaround time for root cause understanding. In this paper, an optimized scheme on synchronous SDL that has a potential to eliminate more than 90% of tester overheads and improve overall SDL test time by at least 17% is proposed. This is achieved by optimizing SDL test loop algorithm.
A Simple Polishing Technique for Removing the Entire Metallization Stack for Sub 100 nm Device Technologies
Authors: Mulder Randal , Anderson Robert 
Published: December 2020

Abstract
The physical analysis of sub-100nm device technologies in many cases requires the total or partial removal of the multiple layers of metallization that route electrical signals and power through the device. This paper presents a simple and quick polishing technique that will remove the entire metallization stack above metal 1 for a 55nm technology device, which results in significantly reducing the time needed to reach the transistor level of the device and also greatly improving uniform planarity across the device. This method is intended for those cases in which gaining access to the transistor layer is required for electrical characterization and physical analysis. The improved speed of this polishing technique to reach the transistor layer has greatly reduced cycle time. The results for the polishing method have been relatively reliable with over a 95% success rate.
Data Center Equipment Reliability Concerns—Contamination Issues, Standards Actions, and Case Studies
Authors: Muller Chris , Arent Chuck , Yu Henry 
Published: December 2020

Abstract
Lead-free manufacturing regulations, reduction in circuit board feature sizes and the miniaturization of components to improve hardware performance have combined to make data center IT equipment more prone to attack by corrosive contaminants. Manufacturers are under pressure to control contamination in the data center environment and maintaining acceptable limits is now critical to the continued reliable operation of datacom and IT equipment. This paper will discuss ongoing reliability issues with electronic equipment in data centers and will present updates on ongoing contamination concerns, standards activities, and case studies from several different locations illustrating the successful application of contamination assessment, control, and monitoring programs to eliminate electronic equipment failures.
Silicon Junction Profile Delineation by Anodic Etching in HF/HNO3/CH3COOH Solution
Authors: Lee Jeng-Han , Chen Y.M. , Huang C.M. , Tseng F.Y. , Chen C.J. , Yin K.M. , Lin Y.T. , Huan Y.S. , Su David 
Published: December 2020

Abstract
An anodic etching is used for silicon junction profile delineation. Experimental results show that the etching rate is determined by dopant type, of which P type silicon etching rate will be enhanced while the N type silicon become inactive when an external positive voltage is applied. The experiment verifies the role of holes on the silicon etching. The proposed method is applicable for exploring the profile of P+/N-well, N+/P-well, and N-well/P-well junctions, using the same recipe.
Validity-Study of Commercial Semiconductor with TO-18 Package for Space Application by PIND Test
Authors: Nakatake Yusuke , Okabe Makoto , Sato Shota 
Published: December 2020

Abstract
In this paper, we carried out PIND (Particle Impact Noise Detection) test and X-ray inspection of a transistor in a TO-18 package for commercial and industrial applications. From our evaluation results, we explain the validity of the PIND test by comparing PIND test and X-ray inspection results. We make clear that PIND test is able to detect internal foreign material that may be transparent to X-ray inspection. In addition, we report analysis results of internal foreign materials from defective devices. This matter suggests that a problem is contamination control in the manufacturing process, most likely the sealing process.
Case Studies on Application of 3D Real Time X-ray for Flip Chip C4 Package
Authors: Cao Lihong , Donna Wallace , Tran Loc , Tuttle Lynda 
Published: December 2020

Abstract
This article describes how 3D Real Time X-Ray (RTX) technique enhances the capability of package-level failure analysis of a flip-chip package. 3D RTX was successful in detecting different failure signatures. This paper outlines detailed applications of 3D RTX with case studies.
Observation of Channel Strain Release in pMOS Device with Low Idsat Using Energy-Filtered Nano-Beam Diffraction Technique
Authors: Zhu Jie , Du An Yan , Liu Bing Hai , Er Eddie , Zhao Si Ping , Lam Jeffrey 
Published: December 2020

Abstract
In this work, energy-filtered TEM nano-beam diffraction (NBD) technique was used to evaluate channel strain profile in pMOS transistors suffering low Idsat issue. TEM and EDX analysis showed nickel deep diffusion into embedded SiGe source/drain. Such defect not only led to leakage current from S/D to substrate but might also reduce compressive strain induced to channel by eSiGe. Comparison of channel-direction strain between bad and good samples using NBD confirmed strain relaxation in bad sample which explained low Idsat as a result of reduced holes mobility.