(Invited) Advanced Virtual Sigesn Substrates for the Monolithic Integration of Novel Opto- and Nanoelectronics
Authors: Schwarz Daniel , Schäfer Sören Christopher , Spieth Christian , Oehme Michael 
Published: December 2024

In the past three decades, the ternary alloy semiconductor SiGeSn has evolved from a predicted direct semiconductor to a serious candidate for the realization of a myriad of interesting applications. The fields of application vary from novel transistor concepts 1–4 for up-coming processor generations to the already reported electrically pumped heterostructure laser diode 5–7, the last missing key component for the monolithically integrated optical on-chip communication on Si.
This rise of SiGeSn originates mainly due to its ability of decoupling its bandgap from its lattice-constant by what it is predestined for the epitaxy of strain-reduced heterostructures and thus their monolithic integration on Si using the well-established Ge virtual substrate technology 8.
However, utilizing the lattice-matching on Ge limits the epitaxy of strain-reduced heterostructures to an extremely narrow composition range of SiGeSn, for which a constant concentration ratio of Si to Sn of 3.67 needs to be fulfilled. In addition, the composition ranges of the more desirable direct bandgap SiGeSn require lattice-constants which are much larger than that of Ge, and thus a GeSn virtual substrate. Therefore, unlocking an even larger composition range necessitates a reliable technology for complete strain-relaxation of GeSn.
However, up to this day, the complete strain-relaxation of GeSn proves itself quite challenging due to its limited thermal budget. In the case of chemical vapour deposition (CVD) based epitaxy, only partial relaxation occurs during growth, while the complete strain-relaxation is limited to post-growth methods like clearance etching for the strain relief of the resulting free-standing structures. Besides that, during the low-temperature molecular beam epitaxy (MBE) of GeSn, there is insufficient thermal energy for the formation of misfit dislocations. Therefore, MBE grown GeSn structures are typically pseudomorphic or show a very small degree of strain-relaxation. Nevertheless, various approaches, like post-growth annealing (PGA) have been investigated and reported to achieve partial relaxation up to 89 % 9. On top of that, partially relaxed GeSn buffers typically exhibit a surface roughness in the range of a few nanometres which is disadvantageous for high-performance heterostructures with individual layer thicknesses of a few tens of nanometres. A possible approach to counteract this problem is the introduction of surface smoothening steps such as using chemical mechanical polishing (CMP).
In this work, we report the development of a combined fabrication scheme of MBE, PGA and CMP to achieve a GeSn double layer buffer stack with a final Sn concentration of 10 %, almost complete strain-relaxation and a surface roughness of ≈ 1.7 nm. A schematic overview of the process and the involved corresponding layer stacks is shown in Fig. 1a.
All shown epitaxy experiments were performed in a 6” MBE system, where Si, Ge and Sn are used as matrix materials and B and Sb as dopants, respectively. In order to stabilize the Sn segregation in the low-temperature growth regime of SiGeSn at TS ≤ 200 °C, the substrate temperature is precisely measured and controlled in-situ using mid-infrared pyrometry 10.
The development of the GeSn virtual substrates is based on the well-reported Ge virtual substrate on Si(001) 8, followed by an additional 100 nm thick Ge buffer layer. For the actual GeSn virtual substrate, a 400 nm thick GeSn layer with 6% Sn underwent PGA in a rapid thermal annealing system, subsequent to its growth. To achieve a best possible growth interface, a CMP step was used afterwards to smoothen the surface. Atomic force microscopy images of a final strain-relaxed GeSn virtual substrate with and without CMP are compared in Fig. 1b, where a nice cross-hatch pattern can be seen for the sample with CMP. The crucial step is then the growth continuation, which necessitates the effective removal of the native GeSn oxide. For this, a combination of wet etching via hydrogen chloride and a following in-situ soft thermal desorption at TS = 300 °C has proven itself as best solution 11. A final 400 nm thick GeSn layer with 10 % Sn completes the GeSn virtual substrate. This virtual substrate forms then the basis for the subsequent device growth, with the layer stack shown in Fig. 1c, and their fabrication using standard cleanroom processes, as described in an earlier report 11. The current voltage characteristics of an exemplary device with a diameter of 4 µm in Fig. 1d proves a good device functionality.
Alongside to the latest results on the current development of GeSn virtual substrates using MBE, we provide an overview of past and future approaches for the realization of virtual SiGeSn substrates and their suitability for monolithically integrated SiGeSn heterostructures on Si.

Figure 1