bluuebunny/crossref_metadata_2025_split huggingface dataset:
A New Method to Authenticate Components and PCB Assemblies Using Fingerprint from X-Ray Images
Authors: Cardoso Bill 
Published: December 2020

Abstract
In this work, we introduce the use of the x-ray image as the unique fingerprint for an electronic component or printed circuit board assembly (PCBA). Unique features of the x-ray image include solder voids, cracks, part alignment, die attach porosity and voiding, die placement and alignment, and wire bonding diagram. These are just a few of the many features in the x-ray image that can be used in tandem to create a unique fingerprint for a single component or an entire PCBA. This technique can also be expanded to mechanical objects by utilizing other idiosyncratic features of the part - such as voids and porosity - to generate the x-ray image fingerprint.
A Latent Issue of Via Resistance: Mechanism and Solution
Authors: Qin Wentao , Donaldson Scott , Rogers Dan , Boukhanfra Lahcen , Thiefain Julien , Barrientos Denise , Grivna Gordy , Steinwall Jim , Chang George , Gambino Jeff 
Published: December 2020

Abstract
Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.
Failure Analysis for Inter-Level Short in Nanometer Semiconductor Technologies
Authors: Song Zhigang 
Published: December 2020

Abstract
As semiconductor technology keeps scaling down, plus new structures of transistor and new materials introduction, not only are new failure mechanisms introduced, but also old classic failure mechanisms get evolved. The obvious example of failure mechanism evolution is short defect. In the previous technologies, although short defects can happen in different layers and appear in different forms, they always happens at intra-level. As semiconductor technology advanced into nanometer regime, short defect no longer only happened in intra-level, but also more and more often happened in interlevel. Failure analysis on the inter-level short defects is much more challenging because they are usually due to interaction of two processes, such as process variation in two process steps at the same location, and often hide in the bottom of tapered and dense patterns. The conventional PFA (Physical Failure Analysis) methodology often misses discovering the defect and then the defect will be removed by subsequent polishing. This paper has demonstrated some methods to tackle the challenges with three case studies of such inter-level short defects in nanometer semiconductor technologies.
Soft Single-Bit Failure on Power Fluctuation by Concurrent Operation
Authors: Ryu Keunchul , Nam Incheol , Kim Jinseon , Kim Daesun , Hwang Hongsun , Oh Taeyoung , Kim Jonghoon , Jang Seongjin 
Published: December 2020

Abstract
Reduced noise immunity due to dimensional shrinkage, lower operational voltages and increasing densities results in increased soft or random failures. In practice, noises are generated by complex operation of device. In Dynamic Random Access Memory (DRAM), failures by noise are regarded as either decrease in charge at cell capacitor or increase in systematic interferences. Simple equivalent circuit of One Transistor One Capacitor (1T1C) DRAM and theoretical approach in time-domain are provided for quantitative noise analysis related to sense amplifier circuitries. Results show that local voltage fluctuation reduces sensing margin to judge data-0 or data-1. This phenomenon is easily observed at 1T1C with high resistance because response of voltage generator is comparatively slow.
Ambient Temperature Thermally Induced Voltage Alteration for Identification of Defects in Superconducting Electronics
Authors: Jenkins Mark W. , Tangyunyong Paiboon , Missert Nancy A. , Pimentel Alejandro A. , Vernik Igor , Kirichhenko Alex , Mukhanov Oleg , Wynn Alex , Day Alexandra L. , Bolkhovsky Vladimir , Johnson Leonard 
Published: December 2020

Abstract
As research in superconducting electronics matures, it is necessary to have failure analysis techniques to identify parameters that impact yield and failure modes in the fabricated product. However, there has been significant skepticism regarding the ability of laser-based failure analysis techniques to detect defects at room temperature in superconducting electronics designed to operate at cryogenic temperatures. In this paper, we describe preliminary data showing the use of Thermally Induced Voltage Alteration (TIVA) [1] at ambient temperature to locate defects in known defective circuits fabricated using state-of-the-art techniques for superconducting electronics.
Effective Backside Circuit Edit Methods for CSP IC
Authors: Kim Y. J. , Yeo J. H. , Choi J. I. , Kim C. S. , Jeong M. M. 
Published: December 2020

Abstract
In the semiconductor chip manufacturing industry, a method of evaluating characteristics by applying a direct circuit edit at an already manufactured chip level is widely used in order to shorten the product development time and release the product to the market in a short time. [1] This is because, when the fab process is performed by modifying the mask to improve the characteristics as in the conventional method, it takes a lot of time and cost for feedback. Feedback of semiconductor characteristics through circuit edit can save 10-20 times in terms of cost and time. As the process becomes more complex and the pattern size becomes smaller, its benefits become even greater. However, when the chip level circuit edit is applied to the Chip Scale Package (CSP) IC, it is very difficult to apply a general method of the frontside circuit edit, so that the success rate of the circuit edit is lowered. In order to solve this problem, a circuit edit method in the backside direction of the chip has been attempted for many years. [2, 3] However, the backside circuit edit (BCE) has more difficulties than the frontside circuit edit. A typical issue is how to uniformly and precisely control and remove the backside Si of the circuit edit area. The following three points should be considered for this. First, the uniformity of the remaining silicon thickness should be high. Second, it is necessary to control the thickness of remaining silicon to an appropriate thickness in the process of removing backside silicon. Third, it is important not to damage the peripheral circuit during etching and deposition. In this paper, we propose a method to increase the backside circuit edit success rate of CSP IC using Al or Cu metal by controlling these three factors effectively.
Identification of Defective Fin by E-beam Induced Current in Advanced FinFET Device Failure Analysis
Authors: Wei Yuting , Zhang Chuan , Chen Liangshan , Khiam Oh Chong 
Published: December 2020

Abstract
E-beam induced current technique is a fault isolation technique based on SEM-based nanoprobers. Electron beam induced current (EBIC) can help failure analysts quickly identify the defective device with abnormal junction behavior from a relatively large area of interest. Using EBIC, defects can be pin-pointed down to individual Fin, which significantly enhanced the success rate. In this paper, two cases are used as examples to illustrate how this failure analysis (FA) methodology provides a powerful and efficient solution in localizing defective fins. In the first case, a local full bit-line fail was submitted for failure analysis. In the second case, a MOS capacitor parametric test structure designed to monitor gate oxide break down voltage that showed early break down behavior during in-line test. Failure analysis was requested to investigate the root-cause.
Successfully Look Up Table Distribution RAM Control Circuitry Fault Isolation with Different Test Methodologies and Conflict Results Analysis by Using Virtual IO and Integrated Logic Analyzer Debug Tools
Authors: Jingyao Huang , Jing Yang , Salinas Peter Floyd 
Published: December 2020

Abstract
This electrical fault isolation based on Xilinx 28nm all programmable device in a Distribution RAM (LUTRAM) functional block. The Look-Up-Table (LUT) was the major component to achieve the programmable chip versus the ASIC chip. In the device architecture, one 6-inputs-LUT (LUT6) memory can be configured as a 64bits distribution RAM (LUTRAM64) or two 32bits distribution RAMs (LUTRAM32). The Vivado design and debug tool brought up two powerful Intellectual Property (IP) Cores: Virtual Input/Output (VIO) and Integrated Logic Analyzer (ILA). This debug tool used Block RAM (BRAM) and fabric routing resources to store the full test results and achieved package level probe-less. [1] It can probe LUTRAM block input, output and Build-In Self-Test (BIST) interconnects. However the limitation was that the inner primitive functional block LUTRAM like memory cells, decoders, mode switchers, write/read controllers and so on were not able to probe. In this case study, the defect was not conventional failure inside the LUTRAM memory cell or stuck on Address/Data_in inputs. Moreover the test behavior with LUTRAM64 mode had conflicting results, which made the fault isolation even more challenge to narrow down from complex LUTRAM control circuitry to transistor level. Therefore different pattern test methodologies, pattern commonality analysis and hypothesis verification were wisely compiled together. In the end, the defect was successfully localized at the fault Isolation circuitry. It was fully matching with the failing mode and proving the fault isolation was correct. The physical defect analysis shown multiple layers metal fusing. The defect shorted the internal control output with the GND signal, which forced LUTRAM to setup as an invalid mode.
Characterizing Interlayer Sub-μm Features in Microelectronics Devices Using High-Resolution Scanning Probe-IR Spectroscopy and Imaging
Authors: Roy Anirban , Hu Qichi , Yang Honghua , De wolf Peter , King Sean W. 
Published: December 2020

Abstract
High resolution scanning probe microscopy techniques combined with infrared (IR) light sources offer unique solutions to combined chemical/mechanical/electrical characterization of defects in nanoscale dimensions. Previously, atomic force microscopy combined with infrared (AFM-IR) technology has demonstrated its capability to characterize nano-patterned metal/low-k dielectrics, nanoscale organic contaminants, and directed self-assembly of block co-polymers used for advanced micro/nanofabrications. In this paper, two complementary nanoscale chemical analysis techniques, photothermal AFM-IR and scattering type scanning near-field optical microscopy, are implemented to isolate and characterize microelectronic device cross-sections. It is observed that both techniques are able to detect patterned features with a half-pitch less than 15 nm.
Localization of Dielectric Breakdown Sites in 3D Through-Silicon Via (TSV) Interconnects by Laser Stimulation and Chip Deprocessing
Authors: Jacobs K. J. P. , Li Y. , De Wolf I. , Van Huylenbroeck S. , Beyne E. 
Published: December 2020

Abstract
We report and demonstrate a new methodology for the localization of dielectric breakdown sites in through-silicon via (TSV) structures. We apply a combination of optical beam induced resistance change (OBIRCH) and mechanical/chemical chip deprocessing techniques to localize nm-sized pinhole breakdown sites in a high aspect ratio 3x50 ìm TSV array. Thanks to the wavelength-selective absorption process in silicon, we can extract valuable defect depth localization info from our laser stimulation measurement. After chip deprocessing we inspect and localize the defect site in the dielectric liner using a scanning electron microscope (SEM). We confirm our results and analysis by cross-sectioning a TSV with a focused-ion beam (FIB).
ToF-SIMS, Time-of-Flight Secondary Ion Mass Spectroscopy for Counterfeit Detection of Electrical, Electronic, and Electromechanical (EEE) Parts
Authors: Simard-Normandin M. , Banks C. , Havercroft N. , Clark P. , Tallarek E. 
Published: December 2020

Abstract
This presentation demonstrates how Time-of-Flight Secondary Ion Mass Spectroscopy provides unique information to identify suspect counterfeit semiconductor devices. An example is shown where the epitaxial layers of a light emitting device (LED) do not match those of the exemplar.
Keywords: Secondary Ion Mass Spectroscopy, SIMS, counterfeit detection, LED, Light emitting diode.
Automated Multi-Level Circuit Net Trace for Hotspot Analysis
Authors: Goh S. H. , Susanto E. , Li Song , Yeoh B. L. , THor M. H. , Zhou D. 
Published: December 2020

Abstract
Post-fault isolation layout net trace and circuit analysis based on abnormal hotspots is a critical step because it directly impacts the outcome of failure analysis. In this work, we review current commercial net tracing solutions in terms of their strengths and drawbacks. As an enhancement, a new net methodology that enables automation and the capability to execute tracing beyond first-level transistors is introduced. This approach could potentially eliminate manual net tracing and significantly improves the overall failure analysis turnaround time.
Low Energy Xe+ PFIB Specimen Preparation for Cs-Corrected HRSTEM Imaging
Authors: Giannuzzi Lucille A. , Anzalone Paul A. , Rao Jiancun , Hoffman Tom , McKie Mike , Girgis Joseph , Kuwahara Takayuki , Ford Jamie , Yates Douglas M. , Stach Eric A. 
Published: December 2020

Abstract
Low energy (i.e., 5 keV, 3 keV) Xe+ plasma FIB methods were applied to Si ex situ lift out specimens. Cs-corrected STEM imaging reveals the Si dumbbell structure indicating excellent surface quality achieved during the low energy polishing steps.
Residual EG Oxide in FinFET Analyses and Its Impact to Yield, Product Performance, and Transistor Reliability
Authors: McGinnis Pat , Albert Dave , Song Zhigang , Oarethu Johns , Tran Phong , Sylvestri John , Hornicek Greg , Tenney Mike 
Published: December 2020

Abstract
This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.
Transmission Electron Microscopy Sample Preparation By Design Based Recipe Writing in a DBFIB Part 2
Authors: Demarest J. , Austin B. , Arjavac J. , Breton M. , Bergendahl M. , Biedrzycki M. , Boye C. , Cilingiroglu B. , Gaudiello J. , Hager J. , Matham S. , Nguyen K. , Persala M. , Rizzolo M. , Shaar S. , Teehan S. 
Published: December 2020

Abstract
Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a factor of two improvement in comparison to optical or scanning electron microscope based processes. This paper provides an additional update on this project. The study is about a GDS based process developed to simplify the complicated workflow for examining discrete electrical failures. The results of this study indicated that the recipe prototype developed on a test structure had a unique feature that consisted of an approximately 45nm by 200nm Cu line segment. Executing the prototype recipe on a wafer at the same process point fabricated 6 months after the original wafer yielded four identical successful samples of about 30nm sample thickness. This technique can thus be extended to large 2D arrays of small structures.
Early Maladaptive Schemas as Predictors Symptomatology among Victims and Non-Victims of Dating Violence
Authors: Borges Jeane Lessinger , Dell'Aglio Débora Dalbosco 
Published: December 2020

Este estudo investigou como os esquemas iniciais desadaptativos (EIDs) podem predizer o desenvolvimento de sintomas de depressão, ansiedade e estresse em uma aamostra alargada de adolescentes vítimas de violência no namoro. Um total de 525 adolescentes, de 14 a 19 anos de idade, oriundos da região metropolitana de Porto Alegre/RS, participaram no estudo. Os participantes foram divididos em dois grupos: Grupo de adolescentes vítimas (n = 396 adolescentes, 60,4% do sexo feminino, M = 16,67 anos de idade, DP = 1,18 anos) e não-vítimas (n = 129 adolescentes, 52,7% do sexo feminino, M = 16,50 anos de idade, DP = 1,23 anos). O Questionário de Esquemas para Adolescentes-Forma Breve, o Inventário de Conflitos nas Relações de Namoro na Adolescência e a Escala de Depressão, Ansiedade e Estresse para Adolescentes foram aplicados. Os resultados indicaram maior sintomatologia de depressão, ansiedade e sintomas de estresse entre as vítimas, em comparação com as não vítimas, e entre as meninas vítimas, em comparação com os meninos vítimas. Vítimas de violência no namoro apresentaram significativamente escores mais altos nos EIDs de Abandono, Desconfiança/abuso, Arrogo/grandiosidade, Autossacrifício, Busca por Aprovação, Negativismo/pessimismo e em Padrões Inflexíveis, quando comparadas ao grupo de não-vítimas. Para o grupo de vítimas do sexo feminino, regressões múltiplas indicaram que os EIDs explicam a variância dos sintomas de depressão (36%), ansiedade (28%) e estresse (26%). Para os adolescentes do sexo masculino, os EIDs também explicam a variância dos sintomas de depressão (43%), ansiedade (38%) e estresse (39%). Os resultados são discutidos a partir dos pressupostos da Terapia dos Esquemas. Implicações para políticas públicas e práticas de intervenção são consideradas.
Chagas Disease Screening Using Point-of-Care Testing in an At-Risk Obstetric Population
Authors: Zamora Lindsey E. , Palacio Federico , Kozlowski Debra S. , Doraivelu Kamini , Dude Carolynn M. , Jamieson Denise J. , Haddad Lisa B. 
Published: December 2020

ABSTRACTCongenital transmission is the most important mode of transmission of Chagas disease (CD) in non-endemic countries. Identifying CD in reproductive-aged women is essential to reduce the risk of transmitting the disease to their children and offer treatment to women and their children, which could cure the disease. We evaluated the use of point-of-care (POC) testing for CD in postpartum patients. In our patient population, 16.7% (23/138) tested positive by POC testing, but confirmatory testing was negative for all patients. Among those considered high risk, 30% declined participation. Our results suggest limited utility of the point-of-care test used in our study and identify an opportunity for improvement to broaden diagnostic testing options. Our study also highlights the need to develop strategies to increase subject participation in future research.
A crônica no Brasil: um gênero em mutação
Authors: Magri Dirceu 
Published: December 2020

RESUMO: Trata-se de reflexões sobre uma das principais características da crônica: sua capacidade de adaptação (mutação) ao longo do desenvolvimento dos periódicos. Reflete-se ainda, neste estudo, sobre a transferência cultural França-Brasil, destacando-se os jornais como arcabouço de tal transposição. Por fim, ressalta-se a presença de grandes autores no gênero, em que ora atuam como romancistas, ora como cronistas e, dentre eles, Machado de Assis como um dos esteios da crônica no Brasil.
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RÉSUMÉ: Il s'agit de réflexions sur l'une des principales caractéristiques de la chronique : sa capacité d'adaptation (mutation) tout au long de l'élaboration des périodiques. On réfléchit dans cette étude encore sur les transferts culturels France-Brésil, en particulier les journaux comme pivot de cette mise en œuvre. Enfin, on relève la présence de grands auteurs dans le genre, où ils jouent le rôle tantôt de romanciers, tantôt de chroniqueurs et, parmi eux, Machado de Assis comme l'un des piliers de la chronique au Brésil.
Terror no Cone Sul: O fundamentalismo islâmico e o Caso Amia - 1994
Authors: Teles Paulo Roberto Alves 
Published: December 2020

O presente artigo é fruto de investigações iniciais e tem como objetivo analisar o processo de formação do fundamentalismo islâmico contemporâneo e o atentado contra a Associação Mútua Israelita Argentina (AMIA) em Buenos Aires. Para isso, utilizamos como metodologia a análise historiográfica sobre o nascimento do fundamentalismo islâmico e os seus principais elementos ideológicos como também obras e reportagens que se debruçaram sobre o atentado contra a AMIA. O trabalho se dedica a retomar o debate acadêmico sobre o nascimento do fundamentalismo islâmico como uma ferramenta de ativismo político e nesse sentido, entende que o atentado promovido em Buenos Aires teria sido um desdobramento desse posicionamento ideológico. Soma-se a isso, os elementos antissemitas históricos presentes na Argentina, que reúne simultaneamente as maiores comunidades judaicas e árabes da América Latina. Corrupção, negligência e envolvimento de agentes do governo argentino também foram considerados nesse trabalho como aspectos potencializadores para esse traumático evento que ainda continua imerso a suspeitas e questionamentos. Palavras-chave: Extremismo; Fundamentalismo Islâmico; América Latina
Microdecisions and autonomy in self-driving cars: virtual probabilities
Authors: Sprenger Florian 
Published: December 2020

AbstractTo operate in an unpredictable environment, a vehicle with advanced driving assistance systems, such as a robot or a drone, not only needs to register its surroundings but also to combine data from different sensors into a world model, for which it employs filter algorithms. Such world models, as this article argues with reference to the SLAM problem (simultaneous location and mapping) in robotics, consist of nothing other than probabilities about states and events arising in the environment. The model, thus, contains a virtuality of possible worlds that are the basis for adaptive behavior. The article shows that the current development of these technologies requires new concepts because their complex adaptive behaviors cannot be explained by referring them to mere algorithmic processes. Instead, it proposes the heuristic instrument of microdecisions to designate the temporality of decisions between alternatives that are created by probabilistic procedures of world modeling. Microdecisions are more than the implementation of deterministic processes—they decide between possibilities and, thus, always open up the potential of their otherness. By describing autonomous adaptive technologies with this heuristic, the question of sovereignty inevitably arises. It forces us to re-think what autonomy means when decisions can be automated.