Self-Aligned IGZO TFTs with Boron Implanted Source/Drain Regions
Authors: Chowdhury Rahnuma Rifat , Kabir Muhammad Salahuddin , Manley Robert G. , Hirschman Karl D 
Published: February 2020

Self-aligned channel regions in thin-film transistors (TFTs) have advantages in reduced parasitic capacitance and stage delay, and a reduction in overhead real estate. A common method used to fabricate self-aligned a-Si:H TFTs is to utilize a through-glass exposure of photoresist which is blocked by the opaque metal bottom-gate electrode [1,2]. This process does not require an additional photomask or lithographic alignment, and thus supports low production cost. Sputtered IGZO has been introduced into flat panel display product manufacturing, exhibiting a channel mobility of approximately an order of magnitude higher than a-Si:H. The working source/drain electrodes in IGZO TFTs can be direct metal contact regions to the IGZO, without the need for additional processes such as doping to render the IGZO conductive. Proper metallurgy and annealing processes can provide ohmic behavior with minimal series resistance [3], however this usually requires several microns of gate-to-source/drain overlap in order to ensure such behavior. Various self-aligned channel strategies have been demonstrated that either utilize through-glass exposure or a top-gate structure [4,5]; however such methods must address associated process integration challenges.
The focus of this study is a novel technique to realize bottom-gate (BG) Indium-Gallium-Zinc Oxide (IGZO) TFTs that is not design-rule dependent or dependent on lithographic alignment. This work presents an alternative method to attain a self-aligned IGZO channel on the traditional staggered BG TFT structure which utilizes top-side exposure and optical thin-film interference. Reflection from the underlying bottom-gate electrode can result in a lower effective exposure of positive-working photoresist, creating a mirror image of the gate electrode in photoresist above the IGZO channel region (see Figure 1). One-dimensional verification of this technique was demonstrated using an underlying molybdenum gate electrode, 100 nm SiO2 gate dielectric, 50 nm IGZO, and AZ MIR 701 positive photoresist imaging layer. Top-side illumination at g-line (λ = 436 nm) with slight underexposure resulted in “reflection gates” that were aligned to the underlying bottom metal electrodes (see Figure 2). This pattern definition can then be used to protect the channel region during subsequent source/drain “activation” processes under investigation which include ion implantation, UV irradiation and plasma exposure [5-7]. Details of the lithographic process, selective source/drain activation, and resulting TFT operation will be presented.
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Figure 1