bluuebunny/crossref_metadata_2025_split huggingface dataset:
Acid Decapsulation for Silver Wire Bonded Package
Authors: Suzuki Satoshi , Yamaguchi Mamiko 
Published: December 2020

Abstract
Decap methods which have been used for copper wire packages are not effective for silver wire packages, and the authors recognized the need for the development of a novel method. This paper discusses the development of various processes to decap silver wire packages with acid. The first decap method developed for a silver wire package was to add hydrochloric acid to fuming nitric acid. This method proved insufficient to prevent silver wire from dissolving when solution temperature is 60 degree. The authors then developed the Saturation Etch method for decapsulating silver wire packages using a chemical solution. When dissolution amount of silver wire put in normal fuming HNO3 is defined as 100%, the authors were able to achieve its reduction to less than 3% by using saturated acid. This method is also effective for copper wire packages, and damages to wires can be minimized by dissolving copper into acid.
What Happens to Electrostatic Sensitive Devices in Case of Direct ESD from Plastics?
Authors: Jacob Peter 
Published: December 2020

Abstract
The judgment of ESDS risks by direct electrostatic discharge from plastics is a challenge due to the variety of possible discharge scenarios. This paper discusses physical backgrounds of the different discharge scenarios from plastics and tries to rank ESDS related risks. It includes specific hints for ESD prevention in plastics lamination processes as RFID cards, smart cards or contactless money cards, where ESD-sensitive devices (ESDS) are at specific high risk for ESD discharge from plastics. Also further process-related risks and package issues are discussed.
Capturing Defects in Flip-Chip CMOS Devices Using Backside EBAC Technique and SEM Microscopy
Authors: (Jane) Li Yuanjing , Aguada John , Lu Jiafang , Yang Jessica , Ng Roy , Marks Howard Lee 
Published: December 2020

Abstract
This paper presents backside physical failure analysis methods for capturing anomalies and defects in advanced flip-chip packaged, bulk silicon CMOS devices. Sample preparation involves chemically removing all the silicon, including the diffusions, to expose the source/drain contact silicide and the gate of the transistors from the backside. Scanning Electron Microscopy (SEM) is used to form high resolution secondary and/or backscattered electron images of the transistor structures on and beneath the exposed surface. If no visual defects/anomalies are found at the transistor level, the Electron Beam Absorbed Current (EBAC) technique is used to isolate short/open defects in the interconnect metallization layers by landing nano-probe(s) on a transistor’s source/drain silicide or on the gate. Using the combination of secondary and backscattered electron imaging and backside EBAC thus allows defects residing in either the transistors or the metal nets to be found. Case studies from 20 nm technology node graphics processing units (GPU) are presented to demonstrate the effectiveness of this approach.
In-Situ Mechanical Sample Preparation of Selected Sites and Components on Large Modules and Boards
Authors: Colvin Jim , Hazeldine Timothy , Patel Heenal 
Published: December 2020

Abstract
The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.
FIB on Test Board
Authors: Suzuki Eiji , Adams Josh , Ball Calvin , McCready Tim , Robinson Sonya 
Published: December 2020

Abstract
This paper offers an alternative solution in dealing with Focused Ion Beam (FIB) circuit edit debug of RF products that often required soldering the device onto a test board to enable sensitive RF characterization. Performing FIB circuit edit while the device is soldered on a test board not only eliminates signal degradation and inconsistency caused by a socket; but also, it allows for adding additional FIB edits on the same device. The conventional way of RF product debug of devices in a wire bond package was to characterize the device in a socket, perform the FIB circuit edit, encapsulate the cavity to protect the device from physical & thermal damage, solder the device onto the test board, and then perform post-FIB characterization. This is a very long, one-way process and needs multiple devices for design debug. For RF products in flip chip package, this approach was extremely difficult to almost impossible, because thermal stress of soldering device would significantly deform thinned die. All characterization had to be done with a socket, which often introduced changes of the same magnitude of the parameters of interest as well as repeatability issues. The purpose of this paper is to outline steps to allow for the RF FIB and characterization cycle to be done in a way to decrease throughput time and increase measurement accuracy. True characterization of highly sensitive RF circuit modifications is achieved through: soldering the device to the test board, performing sample preparation, preforming pre-FIB characterization, preforming FIB, and finally preforming post FIB characterization. Elimination of the need to solder a thinned device to a test board allows for the edit location to remain open enabling additional FIB edits to be performed on the same device. This eliminates redundant steps in the device sample preparation and enables quicker throughput times.
Conductive-AFM for Scan Logic Failure Analysis at Advanced Technology Nodes
Authors: Zhang Chuan , Khiam Oh Chong , Chen Esther P.Y. 
Published: December 2020

Abstract
The increase in complexity of process, structure, and design not only increases the amount of failure analysis (FA) work significantly, but also leads to more complicated failure modes. To meet the need of high success rate and fast throughput FA operation at the leading-edge nodes, novel FA techniques have to be explored and incorporated into the routine FA flow. One of the novel techniques incorporated into the presented scan logic FA flow is the conductive-atomic force microscopy (CAFM) technique. This paper demonstrates CAFM technique as a powerful and efficient solution for scan logic failure analysis at advanced technology nodes. Several failure modes in scan logic FA are used as examples to illustrate how CAFM provides excellent solutions to some of the very challenging FA problems. The gate to active short in nFET devices, resistive contact, and open defect on gate contact are some modes used.
Innovative Nondestructive Compositional Mapping of Trace-Elements and Contaminants at Micron-Scale in Wafers and Packaging
Authors: Lau S.H. , Yun Wenbing , Lewis Sylvia JY , Stripe Benjamin , Kirz Janos , Lyon Alan , Reynolds David , Chen Sharon , Semenov Vladimir , Spink Ian 
Published: December 2020

Abstract
We describe a technique for mapping the distribution and concentrations of trace elements, most notably with capabilities of achieving 1-10 parts per million sensitivities within 1 second and at &lt;8 μm resolution. The technique features an innovative, high flux microstructured x-ray source and a new approach to x-ray optics comprising a high efficiency twin paraboloidal x-ray mirror lens. The resulting ability to acquire dramatically higher sensitivities and resolution than conventional x-ray fluorescence approaches, and at substantially higher throughput enables powerful compositional mapping for failure analysis, process development, and process monitoring.
Charging Reduction Method for Auger Analysis on Imide Surface
Authors: Zakaria Nurhanani 
Published: December 2020

Abstract
This paper outlines a method that has been found to effectively reduce the charging effect on imide surfaces during Auger analysis. This methodology enables in-house Auger analysis on insulators in the semiconductor industry. The compositional analysis at the imide surface is as critical as analysis at the bond pad surface due to its impact on the reliability of the product. Current practice is the use of a thin Au/Pd coating to reduce the charging effect, but there are some drawbacks such as the creation of artifacts due to the presence of Au/Pd peaks in the spectrum. Apart from that, the signal to noise ratio (S/N) is reduced, masking the desired signal. When this scenario occurs, we implement a new combination method of a low angle incident beam along with special sample preparation. This method provides a spectrum with good S/N and no charging effects and eliminates the Au/Pd peak artifacts.
Use of Second Harmonic and Thermal Effects of Laser Voltage Probing for Better Fault Isolation
Authors: Yeluri Ramya , Thirugnanasambandam Ravishankar , Wagner Cameron , Urtecho Jonathan , Neirynck Jan M. 
Published: December 2020

Abstract
Laser voltage probing (LVP) has been extensively used for fault isolation over the last decade; however fault isolation in practice primarily relies on good-to-bad comparisons. In the case of complex logic failures at advanced technology nodes, understanding the components of the measured data can improve accuracy and speed of fault isolation. This work demonstrates the use of second harmonic and thermal effects of LVP to improve fault isolation with specific examples. In the first case, second harmonic frequency is used to identify duty cycle degradation. Monitoring the relative amplitude of the second harmonic helps identify minute deviations in the duty cycle with a scan over a region, as opposed to collecting multiple high resolution waveforms at each node. This can be used to identify timing degradation such as signal slope variation as well. In the second example, identifying abnormal data at the failing device as temperature dependent effect helps refine the fault isolation further.
Improved Method of ROI Encapsulation during Axis Conversion of Cross-Sectional S/TEM Lamellae
Authors: Senowitz Corey , Endrinal Lesly , Nguyen Hieu , Ranganathan Lavakumar , Vollrath Ruby , Yuan Caiwen 
Published: December 2020

Abstract
Defect localization has become more complicated in the FinFET era. As with planar devices, it is still generally possible to electrically isolate a failure down to a single transistor. However, the complexity of certain FinFET devices can lead to ambiguity as to the exact physical location of the defect. The default technique for isolating the defect location for this type of device is to start with a plan view S/TEM lamellae. Once the defect is located in plan view, the lamellae can be converted to cross-section (if necessary) for further characterization. However, if the defect is not detectable in plan view S/TEM analysis, an alternative approach is to examine the device in cross-section along either the x- or y- axis. Once the defect is located in the initial cross-sectional lamellae, it can be converted to the orthogonal axis if the initial cross-sectional lamellae did not provide adequate information for characterization. However, in converting a cross-sectional lamellae to the orthogonal axis, the initial lamellae must be exceedingly thin due to the dimensions of devices on 1x nm FinFET technologies, else other structures on the sample can obscure the view in the S/TEM. This can lead to structural integrity (warping) issues for the converted lamellae. In this paper, a novel solution to the warping issue is presented.
Nondestructive Bond Pull and Ball Shear Failure Analysis Based on Real Structural Properties
Authors: Asadizanjani Navid , Forte Domenic , Tehranipoor Mark 
Published: December 2020

Abstract
Bond pull testing, a well-known method in the failure analysis community, is used to evaluate the integrity of an electronic microchip as well as to detect counterfeit ICs. Existing bond pull tests require that the microchip be de-capsulated in order to obtain physical access to the bond wires in the IC package. Bond pull analysis based on simulation and finite element methods also exists but relies on the original model for a bond wire from a CAD design. In this work, we introduce X-ray tomography imaging with 700nm imaging resolution to acquire the 3D geometry details of bond wires non-destructively. Such information can be used to develop more accurate models for finite element analysis based on real size and structure. Therefore, one can test the bond wire strength as a proof of concept for virtual mechanical testing and counterfeit detection in microchips.
Nondestructive Visualizations of Short Circuits in Ball Grid Arrays by Magnetic Field Imaging and Three-Dimensional X-Ray Microscopy
Authors: Suzuki Kazuhiro , Tsutsumi Masayoshi , Saito Masako , Toda Makoto , Yamamoto Kouzou , Terui Yuji 
Published: December 2020

Abstract
It is important to locate a short circuit failure in semiconductor devices, and powerful tools such as lock-in thermography and optical beam induced resistance change are used. However, those tools are inappropriate for investigating the device covered with the impenetrable substance to light, because the covering substance blocks the light from the defect point in the device and also prevents the optical beam from outside of the device. We demonstrate that a subsurface short circuit in a ball grid array device can be located by magnetic field imaging (MFI) and the electromagnetic field reconstruction method (EM-FRM), which makes it possible to calculate a magnetic field in the immediate vicinity of the current that is the source of the field from a measured magnetic field at a distance. Moreover, we visualize the short circuit by three-dimensional X-ray microscopy. MFI is also applied to visualization of a magnetic field created by a current flowing inside a printed circuit board and a light emitting diode package.
Study on Development Behavior and Mechanism of Delamination by NCF Material under uHAST Test Condition
Authors: Kim Ju Young , Kim Hyoung-Ryeun , Hahn Dong Woo , Hwang Sung Min 
Published: December 2020

Abstract
NCF (Non Conductivity Film) is a material used for under-fill purpose in the TSV (Through Silicon Via) process, and is a key material for ensuring TSV 3D Package (PKG) reliability. Among the types of defects generated by the NCF, the most typical type is delamination. Particularly in NCF delamination frequently occurs during reliability test, we analyzed chemical state change of NCF according to reliability test step/condition by utilizing FTIR and TMA. Through these studies, we clarify the cause of Delamination.
Failure Analysis of Variable Resistor
Authors: Iwai Yasunobu , Imai Yasuo 
Published: December 2020

Abstract
Three failed modules were found during routine inspection of industrial equipment after several years of service. We investigated failure causes of them. As a result of the investigation, we show that there are different failure modes for each type of variable resistors (cermet type, carbon composition type, wire wound type). (1)Cermet type: The wiper was unstable because the wiperfixing was weak already during manufacturing. (2)Carbon composition type: The R12 (resistance between #1 and #2 terminals) was unstable because of extraneous materials in manufacturing or zinc whiskers. (3)Wire wound type: The R13 (resistance between #1 and #3 terminals) was broken by the scratch in manufacturing.
A Case Study of Trapped Charge Induced Surface Leakage
Authors: Wang Xiang-Dong , Cheng Xu , Stefanov Evgueniy , Godek William 
Published: December 2020

Abstract
In many cases, the leakage is relatively small and tends to spread out over a relatively large area. While diagnostic techniques using laser stimulation, such as OBIRCH, or photoemission are powerful in identifying localized defects in silicon crystal and backend metal layers, they are found to be not as sensitive in isolating charge induced leakage. This paper presents a case study of dielectric charge induced leakage in a high voltage ESD device. In this case, conventional photoemission and laser probing diagnostic techniques were not able to localize leakage sites. By using atomic force probing for detailed electrical characterization of individual devices, experimenting with UV radiation, and SCM 2D dopant profiling analysis, it showed that trapped charges in dielectric layers cause leakage near silicon surface. Based on the finding, the FAB fixed the issue by implementing UV bake in the process.
EBAC for Isolating Partially-Localized FEOL Electrical Shorts on Test Structures during Sub-14 nm Technology Development
Authors: Masnik John , Saujauddin Noor Jehan , Davidson Kevin , Chen Esther P.Y. , Beaudoin Felix 
Published: December 2020

Abstract
EBAC is a high-resolution, static technique that can be used for isolating electrical shorts, but it begins to fail for large, interconnected, test structures. In such cases, localization can be achieved when combined with optical localization techniques such as OBIRCH. This paper presents two case studies of subtle, FEOL shorts on a sub-14nm technology that required the resolution of EBAC.
Nanoprobing Beyond 14 nm with Latest Generation SEM-Based Nanoprobers
Authors: Saujauddin Noor Jehan , Chen Esther P.Y. , Beaudoin Felix 
Published: December 2020

Abstract
As the technology scales down, SEM (Scanning Electron Microscope) based nanoprobing faces challenges. Transistors are more susceptible to electron beam damage. As SEM energy decreases to prevent damage, imaging resolution degrades, making it increasingly more difficult to position the probe tips on the contacts. Once landed, the probe stability is important to maintain a good electrical connection throughout the measurement time. We review how well one of the latest generation nano probers addresses these challenges on sub 14nm transistors. Results are compared with a previous generation tool to illustrate the improved imaging and stability capabilities.
Fault Isolation of MOL and FEOL Buried Defects Using Conductive Atomic Force Microscopy as a Complement to Passive Voltage Contrast Imaging
Authors: Sheridan Lucile C. Teague , Conohan Linda , Oh Chong Khiam 
Published: December 2020

Abstract
Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.
Overcoming the Challenges of Parallel, SRAM Shorts Test Structures with EBIRCH
Authors: Saujauddin Noor Jehan , Smith Lloyd , Newkirk Randy , Davidson Kevin , Johnson Gregory M. , Khan Zaheer , Berman Harvey , Chen Esther P.Y. 
Published: December 2020

Abstract
Massively parallel test structures, based on looking for shorts between certain design elements in the SRAM cells, are becoming increasingly relied upon in yield characterization. The localization of electrical shorts in these structures has posed significant challenges in advanced technology nodes, due to the size, and design complexity. Several of the traditional methods (nanoprobing, OBIRCH, etc.) are shown to be inadequate to find defects in SRAM cells, either due to resolution, or time required. In recent years, the Electron Beam Induced Resistance Change (EBIRCH) technique has increasingly been utilized for failure analysis. Combining EBIRCH with other techniques, such as SEM based nanoprobing system and PVC, allows not only direct electrical characterization of suspicious bridging sites but also allows engineers to pinpoint the exact location of defects with SEM resolution. This paper will demonstrate the several cases where SRAM-like test structures provided extreme challenges, and EBIRCH was the key technique towards finding the fail. A node to node, node to wordline, and ground-ground contact fails are presented. A combination of EBIRCH with the more traditional techniques in advanced technology node is key to timely and accurate determination of shorting mechanisms in our test structures.
Failure Modes, Mechanisms and Analysis Methods for a Microcontroller-Based System on Chip
Authors: Saludares Junald , de Guzman Airene , Bernil John Stephen 
Published: December 2020

Abstract
Different failure modes on a microcontroller-based SoC are presented. Several steps in the analysis needed to find the failure mechanism as well as prove "non-fails" amidst the maze of false positives and false trails, second-order effects, confusion and other challenges due to product complexity and the device's interaction with the embedded firmware (FW) are also discussed. The cases presented in this paper tackle issues that are related to FW, non-volatile memory (NVM), digital logic and analog modules.
Beam-Based Defect Localization using Electrons: EBIRCH Overview
Authors: Johnson Gregory M. , Khan Zaheer , D’Aleo Christopher , Yates Brian , Iwatake Michael , Katnani Ahmad 
Published: December 2020

Abstract
Electron-Beam Induced Resistance CHange (EBIRCH) is a technique that makes use of the electron beam of a scanning electron microscope for defect localization. The beam has an effect on the sample, and the resistance changes resulting from that effect are mapped in the system. This paper explores the beam-based nature of the technique and uses understanding from another beam-based technique, Optical Beam Induced Resistance CHange (OBIRCH), to propose a dominant mechanism. This mechanism may explain the widely different success rates between different types of samples observed after six month’s use of the technique for isolations on large health of line structures in a failure analysis lab.