Selective Epitaxial Growth of SiGe(:B) for Advanced p-Type Fd-SOI
Authors: Lespiaux Justine , Kanyandekwe Joël , Marion Tanguy , Saidi Lazhar , Lapras Valérie , Bond Alice , Bringuier Fabien , Richy Jérôme , Thouvard Alan , Biet Tim , Nolot Emmanuel , Couture Ludovic , Brunet Laurent , Rodriguez Philippe , Dos Reis Eva , Gauthier Nicolas , Blot-Saby Adrien , Hartmann Jean-Michel 
Published: December 2024

Epitaxy is of major importance during the manufacturing of p-type metal oxide semiconductor field effect transistors (p-MOSFETs) for next generation fully depleted-silicon on insulator (FD-SOI) integrated circuits. A compressive-strained SiGe channel has indeed to be present in p-type regions for threshold voltage tuning and hole mobility boosting. In-situ boron-doped SiGe raised sources/drains (RSD) have otherwise to be used to reduce access resistance and, ideally, inject uniaxial compressive strain in the channel. Selective epitaxial growth (SEG) is needed for both types of layers,with deposition occurring solely in Si or SiGe areas surrounded by dielectrics. Reduced pressure-chemical vapor deposition (RP-CVD) processes in the 600–800 °C range have been under study for years. We are however still facing technical constraints during their use into complex process flows. Hence, optimizations are required to achieve suitable films in terms of Ge and B compositions (with sometimes dopant incorporation above their solubility limit), morphology (significantly thicker layers in small patterns) and structure (faceting and anisotropic effects). We focus here on various SEG processes used during the manufacturing of advanced p-MOSFET devices, as depicted in Fig. 1: (i) 20 nm thick in-situ boron doped Si0.7Ge0.3 layers grown at 650 °C, 20 Torr then capped with 5 nm of Si:B (at 730 °C, 20 Torr) for RSDs and (ii) 8 nm intrinsic SiGe layer grown at 650–700 °C, 20 Torr for channels. For each process, growth rate, layer composition and selectivity (e.g. poly-nuclei density) were first assessed through depositions on 300 mm bare Si (001) substrates or wafers fully covered by dielectrics (SiO2 or Si3N4). Subsequently, optimal blanket conditions were evaluated on test-patterned substrates then tailored for a use during electrical device fabrication.
First of all, the Si0.7Ge0.3:B growth kinetics and doping was evaluated at 650 °C, 20 Torr with a SiH2Cl2 + GeH4 + HCl + B2H6 + H2 chemistry. As expected, we had a linear increase of the SiGe:B growth rate with the B2H6 partial pressure (Fig. 2(a)). This was due to a catalysis of H desorption on B surface sites. Selectivity was initially assessed on oxide surfaces to determine the appropriate amounts of B2H6 and HCl for given SiH2Cl2 and GeH4 mass-flows. As shown in Fig. 2(b), two different B2H6 partial pressures, 0.03 and 0.11 mTorr, resulted in a lack and the presence of poly-nuclei on SiO2 surfaces, respectively. “Apparent” and atomic Ge contents, from high resolution X-ray diffraction (HRXRD) and X-ray fluorescence (XRF) measurements, are plotted as functions of the B2H6 partial pressure in Fig. 2(c). The difference between the two gave us access to the substitutional B concentrations, which will soon be compared with atomic and possibly electrically active B concentrations (from SIMS and Hall effect measurements).
Given the challenges associated with the formation of germano-salicides with the right properties, we have also evaluated the growth of a Si:B cap on SiGe:B. Various process parameters at 730 °C and 20 Torr were examined in order to have selectivity, thanks to the proper F(SiH2Cl2)/F(HCl) mass-flow ratio, and a meaningful growth rate (addition of B2H6). Active temperature ramps were adopted to prevent elastic relaxation and thus the formation of undulated SiGe:B surfaces. The growth rates (Fig. 3(a)) and structural quality (Fig. 3(b)) of {SiGe:B/Si:B} stacks were assessed with XRD for different Si:B cap thicknesses.
SEG of {SiGe:B/Si:B cap} was then used to thicken the SD regions on each side of FD-SOI pMOSFETs. The right thicknesses, a high crystalline quality and a smooth SiGe:B/Si:B interface were obtained, as shown by Fig. 4 TEM cross-section. Challenges faced during the integration of such a SEG process will be discussed, including the selection of the right surface preparation strategy on SiGe channels, faceting and loading effects.
Finally, SiGe 20%–30% SEG followed by high temperature oxidation is used to fabricate the SiGe channels of SOI devices. To that end, SEG must be strictly controlled. A blanket study was therefore performed at 20 Torr with SiH2Cl2, GeH4 and HCl. Three temperatures (650, 675 and 700 °C) were evaluated in terms of intrinsic SiGe growth rate, Ge content (Fig.5 (a)) and selectivity versus SiN surfaces. We had at 700 °C a severe layer corrugation and islanding for 8 nm of SiGe grown on patterned SOI wafers, as shown by Fig. 5(b) SEM images. Reducing the growth temperature minimized the surface roughness, with definitely longer growth durations as growth rates were smaller, then. When switching to real patterned devices, a combination of in-line monitoring techniques will be mandatory to properly determine the thickness and Ge content of such thin SiGe channels.

Figure 1