Electrochemical Deposition of 3D Interconnects
Authors: Dubin Val M 
Published: December 2020

3D integration is an emerging semiconductor technology that is used to form highly integrated small-factor electronic systems by vertically stacking two or more thin electronic chips in a single package. In metallization of 3D through-substrate vias (TSuV) such as through-silicon (TSV), through-glass (TGV), through-ceramic (TCV) interconnects et al, TSuV having a very small diameter (down to several microns) and long length (hundreds of microns) are filled with plated metal in order to create massive networks of uniform interconnects with high aspect ratio (length/diameter) > 20. Existing conventional industry processes are based on expensive physical-vapor-deposition (PVD) technology, which has serious limitations on via fill uniformity and metal quality (poor step coverage, voids and other defects) as well as is limited to aspect ratios < 10.
Electrochemical deposition processes have been extensively studied for 3D interconnects. These processes are appealing due to superior performance as compared to conventional PVD processes at a substantially lower cost. NANO3D’s processes are based on novel electrochemical nanomaterials (plating solutions with self-assembled suppression-based organic additives to achieve bottom up fill and conformal electroless nickel alloys/copper barrier/seed) that provide defect-free TSuV fill with Cu or other metals for aspect ratios up to >20 [1-5]. Electrochemical deposition techniques have no limitations on chips design rules (down below 20 nm) and can be applied to all types of 3D applications from logic and memory to MEMS, wireless and power electronics. Electrochemical TSuV metallization is fully compatible with all process steps in various 3D TSuV manufacturing schemes currently under evaluation and can be easily incorporated into any finally standardized “process flow of reference”. The low cost electrochemical TSuV technology addresses the major threats for adoption of 3D TSuV that is the scalability to high aspect ratio and the cost. Another threat for adoption of 3D TSuV technology, that is related to power density limitation and thermal dissipation from thinned dies are expected to be solved by controlled expansion metal alloys (INVAR et al.) where electrochemical deposition offers high flexibility for designers with various aspect ratios and via sizes.
In this work, copper and INVAR electroplating as well as nickel alloys and copper electroless deposition processes have been developed and characterized to achieve bottom up fill in trenches & vias of high aspect ratio and wide range of features sizes with superior interconnect properties including low electrical resistivity, CTE and internal stress. Plated films with low-thermal expansion (of about 0.4±0.1 (x10-6, (K-1)) and ultralow internal stress (of about 30 MPa) have been deposited on patterned substrates such as TSuV on various substrates, redistribution layers (RDL), pillars and bumps for 3D Interconnects. The plated patterned substrates are flat, smooth, uniform, defect free and possess with complete fill of TSuV and well controlled thickness non-uniformity of about 5 % @ 3 σ for Cu & INVAR & Ni alloys films (Figure). Thermal shock testing of plated TSuV substrates showed promising reliability & adhesion results after 500 cycles of thermal shock with no cracking and delamination.

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Figure 1