bluuebunny/crossref_metadata_2025_split huggingface dataset:
Using Nano-Probing Technique to Clarify Nickel Silicide beyond Process Window Causing Device Failure
Authors: Lin Jian-Chang , Wu Wen-Sheng 
Published: December 2020

Abstract
A scanning electron microscopy (SEM) based nano-probing system is used in this study to clarify nickel silicide phase beyond process window. According to the nano-probing measurement result and the cross-sectional transmission electron microscopy (TEM) images, phenomena of junction leakage along with high resistance and a larger nickel silicide area are observed at failure site at the same time. The type of failure mechanism and in-line process issue caused multiple failure phenomena at failure site will be the major focuses in this paper. Nickel silicide phase transformation from NiSi to NiSi2 is highly suspected by the comparison of sheet resistance and silicon consumption. Consequently, nickel silicide beyond process window could be verified immediately.
Design Rule of Microchip Al Bond Pad and Optimization of Bonding Process in Wafer Fabrication
Authors: Younan Hua , Rao Nistala Ramesh , Boon Ang Ghim , Shuting Chen 
Published: December 2020

Abstract
Wire bonding continues to remain as the dominant chip interconnect technology in the far backend process, regardless of the shrinkage of microchip Al bond pad size and the increase in the number of I/O connections in the modern ICs. The reliability of IC devices is directly affected by the quality of adhesion between wire bond and microchip Al pad. Many factors, such as the wafer fab process residue and corrosion, creep-induced wire breakage and electrostatic damage, may result in poor adhesion. In this paper, we show a p-channel Field-Effect Transistor (pFET) failure caused by a mismatch in the bond pad size and the wire bond diameter as well as electrostatic damage during wire bonding. The failure analysis results, failure mechanism and the design rule of microchip Al bond pad in wafer fabrication are discussed. FA investigations were performed on the high gate leakage (nA to mA level) issue in the packaged pFET. It was found that two major factors contributed to the failure, namely mechanical and electrostatic damage. The mechanical damage was mainly due to incompatible Al pad size and bond wire diameter. More specifically, in the failed device, the bond wire diameter was larger than half size of the bond pad opening, contrary to the general design rules of wire bonding. The failure to adhere to the design rule resulted in the device failure. In addition, the electrostatic damage during wire bonding resulted in defects of poly Si/gate oxide and thus the high gate leakage. In this paper, the FA results, failure mechanism of the high gate leakage and the bond pad design rule will be discussed. Also, it will be demonstrated that to achieve good bonding quality and eliminate mechanical and ESD damage the diameter of the bond wire should be equal to or smaller than half of the bond pad opening.
Application to Non Destructive Physical Analysis Method Using X-ray CT Imaging
Authors: Mizoguchi Akira , Sugawara Minoru , Nakamura Masahide , Takeuchi Koichiro 
Published: December 2020

Abstract
We have been paying attention to the development of the nondestructive physical analysis (NDPA) technology. We think that NDPA is a technology which doesn't depend on the worker's capability or experience. There are many NDPA techniques, and analysis using X-ray imaging is one of the principal techniques. Due to the progress of the image analysis using computers in recent years, X-ray imaging have been evolving from two dimensional images to three dimensional imaging. We have been applying X-ray CT imaging to actual failure analysis and reliability evaluation since 2008. At ISTFA 2009, we reported on the effectiveness of X-ray Computed Tomography (CT) images in the failure analysis. [1] We confirmed that the X-ray CT image had various applications, for example, screening for counterfeit parts, the detection of the defect of the multi-layers printed wiring boards (multi-layers PWB), the structure confirmation of caulking contacts, and the detection of cracks or voids of the solder joint. This paper discusses the effectiveness of X-ray CT imaging in failure analysis and discusses the effectiveness of applying X-ray CT imaging to the propagation of cracks occurring at solder joints during temperature cycling test.
Case Studies of Counterfeit Part Detection in Assembled Products
Authors: Hartgerink Daniel P. 
Published: December 2020

Abstract
Counterfeit parts are marketed with the intent to deceive the customer. This intent to deceive defines a counterfeit part and separates it from faulty parts, which have defects that are unknown to the manufacturer or distributor. This paper presents three cases in which counterfeit electronic parts were assembled into hardware items and later found to be faulty in some manner. Laboratory techniques used to identify these parts as counterfeits are presented. Non-laboratory techniques that could have prevented the parts from entering service in these cases are also described. Techniques to combat counterfeit parts range from very simple observation of the parts and the paperwork to failure analysis carried out in a laboratory environment. In all of these cases, the potential existed to detect the counterfeit parts prior to assembly into hardware and prior to field deployment of the defective devices.
Differential and Lock-in Imaging of Dynamic Photon Emission and Applications in Failure Analysis
Authors: Qian Zhongling , Brillert Christof , Burmer Christian , Yokoyama Yoshiyuki 
Published: December 2020

Abstract
In this paper, the differential and lockin imaging techniques of Dynamic Photon Emission (DPE) were developed by using highly sensitive near-infrared InGaAs camera in time integrated mode. At first, the setup and method for differential imaging of DPE (DI-DPE) are introduced. The unique debug and pinpointing capability of fails of DI-PEM is discussed in combination with two case studies. Based on DI-DPE, the setup and method for Lockin imaging of DPE (LI-DPE) are then developed for such cases where the correlated DPE is enhanced in strong photon emission background. The correlation in LI-DPE can separate the emission spots from different power domains.
Methodology for Analysis of Schottky Diode Failures
Authors: Sood Bhanu P. , Pecht Michael , Miker John , Wanek Tom 
Published: December 2020

Abstract
Schottky diodes are semiconductor switching devices with low forward voltage drops and very fast switching speeds. This paper provides an overview of the common failure modes in Schottky diodes and corresponding failure mechanisms associated with each failure mode. Results of material level evaluation on diodes and packages as well as manufacturing and assembly processes are analyzed to identify a set of possible failure sites with associated failure modes, mechanisms, and causes. A case study is then presented to illustrate the application of a systematic FMMEA methodology to the analysis of a specific failure in a Schottky diode package.
Failure Analysis of Flip Chip C4 Package Using Focused Ion Beam Milling Technique
Authors: Cao Lihong , Tran Loc , Donna Wallace 
Published: December 2020

Abstract
This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. Dual- Beam Focused Ion Beam (DB FIB) cross sections were successful in detecting failure mechanisms related either to the die/C4 bump or package defect inside the organic substrate. This paper outlines detailed sample preparation techniques prior to performing the DB FIB cross-sections, along with case studies of DB FIB cross-sections.
Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree
Authors: Huang Yu , Cheng Wu-Tung , Tai Ting-Pu , Lai Liyang , Guo Ruifeng , Kuo Feng-Ming , Chen Yuan-Shih 
Published: December 2020

Abstract
If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.
Al Bondpads, Halogens, and an ESCA-Based Search for the Invisible Cause of Poor Throughput at Wafer Probe
Authors: Niles David W. , Kee Ronald W. 
Published: December 2020

Abstract
The authors use electron spectroscopy for chemical analysis and Auger electron analysis to study the interaction of Cl and F with Al thin-films deposited as thin-films on Si wafers and as Al bondpads. The motivation behind the study is F contamination being the putative source of poor throughput at wafer probe. F species stemming from NH4F and XeF2 exposure behave quite differently from HF on the Al surface. Whereas HF tends to attack the Al metal and leave an extended oxygenated-fluorinated surface, NH4F and XeF2 promote the formation of a stable, non-deliquescent fluoride salt of aluminum. HCl is far less corrosive to Al than HF, leaving a thin chlorinated-oxygenated surface. Immersion of Al thin-films in tetra-methyl-ammonium hydroxide (TMAH) and NH4OH provided non-halogenated surfaces for comparison. With exposure to air, the surface coated with the fluorinated Al salt (NH4F) adsorbs oxygen from the air to form a segregated AlF3/Al2O3 bilayer that remains stable with a total thickness on the order of 5 nm to 10 nm. Furthermore, wafers treated with NH4F display stellar throughput performance at wafer test despite having surface F contamination. A mechanical rather than chemical model is proposed to explain the improved performance at wafer probe with the immersion of wafers in a bath containing fluoride salts before wafer probe.
Comprehensive Nano-Structural Approach of SSRM Nanocontact on Silicon through TEM-STEM Study
Authors: Domengès B. , Delaroque T. , Danilo K. , Colder A. 
Published: December 2020

Abstract
Scanning Spreading Resistance Microscopy electro-mechanical nanocontacts are nowadays well understood and numerous influent parameters have been identified (Bias, load, surface state of the sample, radius of curvature of the tip). Despite several simulation and modelization possibilities, calibration curves are required to ensure reliable electrical characterizations. In this paper, we bring, through nano-structural studies (Scanning Electron Microscopy, Transmission Electron Microscopy) of surface state of both SSRM tips and doped silicon surface a new understanding of tip-sample interaction during SSRM measurements. As a result of load, a nanometric residual amorphous silicon layer was observed which thickness depends on applied force and might be due to as well the plastic transformation (Si to β-tin phase) as plough-effect residues resulting from the tip indentation into the sample. It appears thus in a failure analysis process to find the best compromise between stable electrical SSRM response and sample/tip surface degradation.
Setup for Locating PV-Cell Defects through ISC Measurements
Authors: Shankar Santhosh , Bernhardt Andreas , Srinivasan Balaji , Enimidisetty Sravanthi , Versen Martin 
Published: December 2020

Abstract
Optical or light beam induced current (OBIC or LBIC) are well known techniques for the analysis of integrated circuits and the study of electrically active materials in material science. They are also natural methods for analysis of photovoltaic cells, as the photocurrent of a photovoltaic cell itself is measured. We present a new measurement setup including graphical user interface software which has been created in a student project by refurbishing a used CNC (Computer Numerical Control) milling machine. The technique is applied to the measurement of the short circuit current of a photovoltaic (PV) cell with dimensions of 154 × 154 mm2.
All-Contactless Measurement of Series Resistance Distributions on Solar Cells with Photoluminescence Imaging
Authors: Kasemann M. , Reindl L.M. , Michl B. , Warta W. , Schütt A. , Carstensen J. 
Published: December 2020

Abstract
Conventional series resistance imaging methods require electrical contacts for current injection or extraction in order to generate lateral current flow in the solar cell. This paper presents a new method to generate lateral current flow in the solar cell without any electrical contacts. This reduces the sample handling complexity for inline application and allows for measurements on unfinished solar cell precursors.
Failure Analysis Method of Using Laser Nano Electrostatic Field Probe Sensor (L-NEPS)
Authors: Ito Seigo , Sodeyama Hiroko , Takiguchi Kiyoaki , Matsumoto Toru 
Published: December 2020

Abstract
We propose in this paper to introduce the L-NEPS (Laser Nano Electro-static field Probe Sensor), which can detect the slight quasi-electrostatic field generated by optical excitation and thermal excitation occurred when laser beam irradiates on the surface and back of the Die of LSI under non-bias and non-contact conditions, as well as the method to locate the failure point with this device. This report explains the principle of quasi-electrostatic field sensing by L-NEPS and the detection mechanism, and also illustrates the effectiveness of this detection method on the basis of analysis data of two examples of LSI failures (ESD breakdown).
Hardness of Rinse Water and Swelling Behavior of Dry Film Photo-Resist
Authors: Kim Song-I , Heo JinWoo , Kim YunHee , Yu Yeonseop , Choi ChungSik , Yu JaeSu 
Published: December 2020

Abstract
We investigated the swelling behavior of dry film photoresist in rinse process after development by varying the hardness of water. We inspected the appearance of sidewalls and the foot of the resist. We also measured the depth of once swollen resist using a FIB (focused ion beam) and analyzed the chemistry of the resist after rinse using an XPS (X-ray photoelectron spectroscopy). We experimentally proved that divalent cations such as Ca2+ and Mg2+ in hard water could be exchanged with Na+ on the resist surface and quench swelling of the exposed resist in rinse. This study indicates that the use of hard water in rinse process may result in better line definition and resolution in PCB (printed circuit board).
Precise Localization of 28 nm via Chain Resistive Defect Using EBAC and Nanoprobing
Authors: Larré P. , Tupin H. , Charles C. , Newton R.H. , Reverdy A. 
Published: December 2020

Abstract
As technology nodes continue to shrink, resistive opens have become increasingly difficult to detect using conventional methods such as AVC and PVC. The failure isolation method, Electron Beam Absorbed Current (EBAC) Imaging has recently become the preferred method in failure analysis labs for fast and highly accurate detection of resistive opens and shorts on a number of structures. This paper presents a case study using a two nanoprobe EBAC technique on a 28nm node test structure. This technique pinpointed the fail and allowed direct TEM lamella.
In FAB 300mm Wafer Level Atomic Force Probe Characterization
Authors: Kane Terence 
Published: December 2020

Abstract
A 300mm wafer atomic force prober (AFP) has been installed into IBM’s manufacturing line to enable rapid, nondestructive electrical identification of defects. Prior to this tool many of these defects could not detected until weeks or months later. Moving failure analysis to the FAB provides a means of complementing existing FAB inspection and defect review tools as well as providing independent, non-destructive electrical measurements at an early point in the manufacturing cycle [1] Once the wafer sites are non destructively AFP characterized, the wafer is returned to its front opening unified pod (FOUP) carrier and may be reintroduced into the manufacturing line without disruption for further inspection or processing. Whole wafer atomic force probe electrical characterization has been applied to 32nm, 28nm, 20nm and 14nm node technologies. In this paper we explore the cost benefits of performing non-destructive AFP measurements on whole wafers. We have found the methodology of employing a whole wafer AFP tool complements existing in-line manufacturing monitoring tools such as brightfield/dark field optical inspection, SEM in-line inspection and in-line E-beam voltage contrast inspection (EBI).
An Overview of Cu Wire Intermetallic Compound Formation and a Corrosion Failure Mechanism
Authors: Meng Dongmei , Buck Laura , Cargo James 
Published: December 2020

Abstract
Cu needs a higher level of ultrasound combined with bonding force to be bonded to the Al pad properly, not just because Cu is harder than Au, but it is also harder to initiate intermetallic compounds (IMC) formation during bonding. This increases the chances of damaging the metal/low k stack under the bondpad. This paper presents a fundamental study of IMC as well as one example of a failure mode of Cu/Al bonded devices, all based on detailed analysis using scanning electron microscopy, scanning transmission electron microscopy, energy dispersive spectrometers, and transmission electron microscopy. It presents a case study showing a corrosion mechanism of Cu/Al ballbond after 168hr UHAST stress. It is observed that all Cu9Al4 was consumed, while very little copper aluminide remained after 168 hours of UHAST stressing.
Study on ATPG Failure with Butterfly Pattern
Authors: Chen C.Q. , Ang G.B. , Zhao S.P. , Neo S.P. , Quah A. , Teo Angela , Liu B.H. 
Published: December 2020

Abstract
In this study, a 65nm product level low yield case has been investigated and its failure mechanism was identified. Root cause analysis was discussed and concluded. The product has been hit with ATPG failure with a unique wafer map signature - a butterfly pattern. Tools commonality and timeframe analysis show that the highly suspected process is the Metal1 Cu seed PVD step. To understand the failure mechanism and its root cause, product level FA was needed. However due to its functional failure property, the conventional EFA is not applicable in this case. Instead GDS study was performed to isolate the failure sites. Subsequently physical FA analysis was carried out at the identified sites to reveal its failure mechanism. Metal1 void was observed on the sidewall of the metal1. Meanwhile, a very interesting phenomenon was observed. If die was selected on the left part of the butterfly pattern, the void would be on the right side sidewall of the metal. If the die was selected on the right part, the void would be on the left side sidewall of the metal1. All of the voids were towards wafer center. After in-depth study of the PVD process, we suspect the pass die could also have void. These voids must be also towards wafer center. Subsequent PFA on good unit confirmed our suspect. The more detailed mechanism of the void formation was discussed and evidences supporting our analysis are to be presented in the paper. Nevertheless, the butterfly pattern is still a question in our mind. After in-depth analysis, we found the voids formation was associated with Metal1 orientation. Because of the horizontal orientation of Metal1, if the void happens it should locate in the end of the metal line in the butterfly area. While the majority of Via1/contact are stand on the line end, so the open Via1/contact failure will happen. For the die out of the butterfly area, the majority of the void locates in the sidewall of the metal line center. The majority Via1/contact are not stand in the center of the metal line center, of no Via1/contact open happen. But it is still has reliability concern. Much more detailed and in-depth mechanism is investigated in the paper. Moreover, improvement is also touched on. Systematic problem solving method is employed in this case. It is good reference for same kinds of failure analysis.
Fault Isolation Techniques and Studies on Low Resistance Gross Short Failures
Authors: Tan P.K. , Mai Z.H. , Lee W.Y. , Ma Y.Z. , He R. , Ng T.H. , Dawood M.K. , Low G.R. , Tan H. , Oh C.K. , Lam J. 
Published: December 2020

Abstract
With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economical and simple way of identifying low resistance gross short failures.
Post Decapsulation Internal Visual Inspection
Authors: Jordan Erik 
Published: December 2020

Abstract
One of the biggest problems in the integrated circuit industry as of late has been counterfeiting. Because the counterfeiting process is still quite crude in its nature, visual inspection has become a cornerstone process. This paper discusses the significance of the documentation post decapsulation during internal visual inspection. In order to properly inspect for counterfeit components, it is critical to understand that one inspection method alone will not provide enough information to detect all counterfeits. Proper counterfeit detection involves detailed inspection of multiple aspects of a component in order to gather as much information as possible, so that each component can be successfully labeled counterfeit or authentic. A collaboration of multiple inspection processes, comparison of data amongst sample testing batch, comparison to "known good/golden sample" when possible, and documentation of findings results in the highest confidence level of authenticity of counterfeit labeling of components.
Alternative Lapping Method to Reduce Edge Rounding Effect
Authors: Ong Hock Guan , Gan Chee Lip 
Published: December 2020

Abstract
Polishing is a simple and direct method to prepare samples for failure analysis and characterization. However, polishing commonly gives rise to the issue of rounding at the sample's corners and edges. This is believed to have arisen from the uneven distribution of polishing slurry between the edges and sample surface during polishing. Thus, we propose a new lapping method to reduce the rounding effect. From our experiments, negligible rounding effect was observed on a 9 mm by 7 mm die after a depth of ~ 2 μm of material was removed using our proposed alternative lapping method.
Stress Reduction during Silicon Thinning Using Thermal Relaxation and 3D Curvature Correction Techniques
Authors: Colvin Jim , Patel Heenal , Hazeldine Timothy 
Published: December 2020

Abstract
Backside sample preparation is required by many post silicon validation techniques like FIB (Focused Ion Beam) circuit editing and optical probing using Photon Emission or Laser Stimulus methods [1]. In spite of many conventional methods of silicon thinning and polishing, some challenges remain as new packages are introduced. With large die packages the issue of cracking during backside thinning is arising due to package curvature stress. 3D profile methods will be shown in conjunction with thermal relaxation to alleviate silicon center to edge variance allowing sample prep of large areas with thicknesses below 10μm. Thinning and polishing methods will be shown to be interactive with the device heated; demonstrating both thermal stress reduction coupled with curvature reduction.