bluuebunny/crossref_metadata_2025_split huggingface dataset:
Analysis of Poly-Si Thin Film Solar Cells by IR-LBIC
Authors: Boostandoost M. , Lin H.-P. , Kerst U. , Boit C. , Gall S. 
Published: December 2020

Abstract
The carrier collection properties of polycrystalline Si (poly-Si) thin film solar cells on glass with interdigitated mesa structure have been locally analysed with Infrared Light Beam Induced Current (IR-LBIC) and compared to LBIC measurements using visible light. The low absorption of IR light leads to a low current level when the light is coupled vertically into the active volume. An enhanced carrier collection has been detected at the corners of the mesa because the etch allows to couple the light horizontally into the solar cell, This investigation shows that IR-LBIC is sensitive to light trapping structures in silicon based thin film solar cells.
Inter Layer Dielectric Defect Induced High Contact Resistance
Authors: Chiu Re-Long , Higgins Jason , Kinder Toby , Tyni Juha , Ying Sharon , Chung Jones 
Published: December 2020

Abstract
High contact resistance can be caused by moisture absorption in low phosphorus content BPTEOS. Moisture diffused through the TiN glue layer is absorbed by the BPTEOS during subsequent thermal processes resulting in increased contact resistance. This failure mode was studied by combining different failure analysis methods and was confirmed by duplication on experimental wafers.
Semi-Automated Full Wafer In-Line SRAM Failure Analysis by Dual Beam Focused Ion Beam (FIB)
Authors: Herschbein Steven B. , Kang Hyoung H. , Berman Harvey E. , Scrudato Carmelo F. , Shore Aaron D. , Dai Bing 
Published: December 2020

Abstract
The presence of a full wafer dual-beam FIB on the process floor gave rise to an environment in which formerly segregated off-line lab and FAB tasks could be linked. One such idea involved a methodology for semi-automated defect targeting based on the spatial predictions of static random access memory (SRAM) electrical testing. The embedded memory blocks on some processors are fully configured and probe pad testable as early as the forth metal level. Using a unique navigation technique that combines electrically sorted SRAM bit map data with CAD coordinate information and stage driven X-Y stepping, the FIB tool was used to locate, section and image prior level defects. We believe that with the inclusion of suitable fiducial markers in the chip design and advanced pattern recognition to aid navigation and guide depth milling, a fully automated process for electrical yield detractor diagnosis could be introduced.
Fault Localization of Power-Ground Short via Signal Injection and Oscilloscope Technique
Authors: Nguyen Binh 
Published: December 2020

Abstract
For those attempting fault isolation on computer motherboard power-ground short issues, the optimal technique should utilize existing test equipment available in the debug facility, requiring no specialty equipment as well as needing a minimum of training to use effectively. The test apparatus should be both easy to set up and easy to use. This article describes the signal injection and oscilloscope technique which meets the above requirements. The signal injection and oscilloscope technique is based on the application of Ohm's law in a short-circuit condition. Two experiments were conducted to prove the effectiveness of these techniques. Both experiments simulate a short-circuit condition on the VCC3 power rail of a good working PC motherboard and then apply the signal injection and oscilloscope technique to localize the short. The technique described is a simple, low cost and non-destructive method that helps to find the location of the power-ground short quickly and effectively.
High Volume Scan FA for Yield Enhancement at the 90nm Node
Authors: Ross Ryan , Garteiz Gil 
Published: December 2020

Abstract
Driving yield improvement activities to decrease baseline logic / scan yield fallout is often perceived as a challenging or complex activity. Much of this perception is based on yield or device teams historical interactions with the FA teams on these types of requests. This paper will present our methodology for generating a relatively high volume of scan FA results in a short time frame. This type of high volume scan FA enables real time FA paretos of what is causing scan / logic yield loss.
DRAM Static Refresh Weak Cell Characterization and Structure Analysis
Authors: Lee Sung Ho , Yoo Yong Ho , Park Tae Jung , Choi Jin , Ahn Ju Hyeon , Kim Seok Sik , Kang Chang-Jin , Nam Seok Woo , Lee Joo Young , Jin Gyo Young 
Published: December 2020

Abstract
Data retention characteristic is one of the most critical issues in low power DRAMs because it determines idle currents of self-refresh operation. Compared to normal healthy cells, a few ppm orders of cells in a tail distribution have much higher leakage currents. The origin of the leaky cells (so called weak cells or tail cells) has been quite arguable for the past decades [1, 2], but it should be scrutinized in order to achieve long data retention time. In this paper, we have thoroughly investigated the behavior of the retention weak cells using a newly generated combination program and TEM analysis so as to discover and explain their origins
Flash Single Bit Cycling Fail Due to Charge Accumulation from Incorrect Lateral Drain Junction Formation
Authors: Harber Keith , Subramanian Sam , Chrastecky Tony , Ly Khiem , Mu Fuchen 
Published: December 2020

Abstract
This paper outlines the analysis of a flash single bit failure caused by bitcell degradation over write/erase cycling. With no physical anomaly present at the failing single bit, Atomic Force Probing (AFP) characterization was utilized in conjunction with thermal response characterization to direct analysis towards a particular non-visible defect as the root cause. Existence of the hypothesized non-visible defect causing the single bit cycling failure was proven through Transmission Electron Microscopy (TEM) stained sample analysis, which highlighted an anomalous lateral drain junction formation at the single bit that caused the cycling failure.
Challenges and Benefits of Product-Like SRAM in Technology Development
Authors: Beaudoin Felix , Lucarini Stephen , Towler Fred , Wu Stephen , Song Zhigang , Albert David , Safran Laura , Sylvestri John , Karve Gauri , Yu Xiaojun , Kachir Eli , Jungmann Noam 
Published: December 2020

Abstract
For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.
A Novel ONO Inspection Methodology for DRAM Deep Trench Structure
Authors: Chen Kuo Hsiung , Chang Chih-Chung , Lin Jian Chan 
Published: December 2020

Abstract
The oxide-nitride-oxide (ONO) is one of the critical layers in the deep trench (DT) capacitor of the modern DRAM structure. This paper highlights a ONO inspection methodology, which used the silicon wet etching to enhance the ONO leakage point. First, a hole was milled nearby the leakage ONO, which was localized by using focused ion beam (FIB). Then, silicon was removed by an etching solution from the opening. When the poly of DT is etched through the ONO weak point, the leakage site will be enhanced. With the silicon wet etching enhancement, the ONO leakage point is easy to be observed by X-S FIB inspection. The real ONO leakage point is useful information for the root cause finding and the process improvement.
A Study of SRAM Device Soft Failures Caused by Contact Volcano Defects Using Nanoprobing Analysis
Authors: Shu Yu Hsiang , Huang Vincent , Chao Chia Hsing 
Published: December 2020

Abstract
Using nanoprobing techniques to accomplish transistor parametric data has been reported as a method of failure analysis in nanometer scale defect. In this paper, we focus on how to identify the influence of Contact high resistance on device soft failures using nanoprobing analysis, and showing that the equivalent mathematical models could be used to describe the corresponding electrical data in a device with Contact high resistance issue. A case study was presented to verify that Contact volcano defect caused Contact high resistance issue, and this issue can be identified via physical failure analysis (PFA) method (e.g. Transmission Electron Microscope and Focus Ion Beam techniques) and nanoprobing analysis method. Finally, we would explain the physical root cause of Contact volcano issue.
Nanoelectronic Analog Circuit PFA – The Return of Circuit Level Probing
Authors: Albert D. E. , Fischer L. , Beck S. 
Published: December 2020

Abstract
Circuit level probing is testing, measuring, or characterizing the operation of an electronic circuit. It reveals the true operation of a circuit, and takes the next step beyond electrical engineering design and circuit simulation. This paper presents the return of circuit level probing in nanoelectronics by means of SEM based nanoprobing. It provides information on the process of characterizing resistance matching, diode matching, Op Amp offset matching, and mirrored current. Circuit level probing, using a SEM based nanoprober, identified the problem to be poor matching between the current mirror devices in the circuit. A family of curves device characterization was obtained from the circuit level probing. Discrete devices testing showed good correlation back to the circuit level data. The device mismatch was determined to be associated with the "as processed" built-in potential of the devices, with no abnormal influence from either the gate or drain electrical fields.
Characterization and TCAD Simulation of 90nm Technology PMOS Transistor under Continuous Photoelectric Laser Stimulation for Failure Analysis Improvement
Authors: Llido R. , Sarafianos A. , Gagliano O. , Serradeil V. , Goubier V. , Lisart M. , Haller G. , Pouget V. , Lewis D. , Dutertre J.M. , Tria A. 
Published: December 2020

Abstract
This study responds to our need to optimize failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus it is mandatory to understand the behavior of elementary devices under laser stimulation, in order to model and anticipate the behavior of more complex circuits. This paper characterizes and analyses effects induced by a static photoelectric laser on a 90 nm technology PMOS transistor. Comparisons between currents induced in short or long channel transistors for both ON and OFF states are made. Experimental measurements are correlated to Finite Elements Modeling Technology Computer Aided Design (TCAD) analyses. These physical simulations give a physical insight of carriers generation and charge transport phenomena in the devices.
Differential Polarization Imaging and Probing [DPIP]: Seeing and Probing the “Invisible”
Authors: Niu Baohua , von Haartman Martin , Pardy Patrick , Sacks Mitch 
Published: December 2020

Abstract
A novel method for obtaining diffraction limited high resolution images, and increased signal to noise ratio (SnR), for imaging and probing silicon based complementary metal oxide semiconductor field effect transistor (CMOS, and MOSFET) integrated circuits (IC), is presented. The improved imaging is based on the sub wavelength features’ asymmetric layout, which is dictated by the lithography design rules constrain in CMOS IC and their interactions with polarized light. This asymmetry in layout and the inherent stress engineering on the CMOS IC, produce both dichroism and birefringence in silicon (Si). An elegant design enabled us to obtain two images with orthogonal polarization detection to take advantages of the dichroism and birefringence in Si based CMOS IC. Differential Polarization Image (DPI) is obtained by subtracting the two orthogonal polarization resolved images. On infrared emission microscopes (IREM), DPI in optical imaging mode and DPI plus probing [DPIP] in emission mode, showed 2X or more in terms of optical resolution (imaging mode) and 2X or more SnR (emission-probing mode) improvements. Striking images in probing mode, revealing previously “invisible” emission, were demonstrated.
Routine Backside FIB Milling With EXpressLO™
Authors: Giannuzzi Lucille A. 
Published: December 2020

Abstract
A new method and grid design is described for implementation of ex-situ lift-out of FIB prepared specimens. This technique negates all prior disadvantages to ex-situ liftout and provides a method for higher throughput and rethinning of ex-situ specimens. In particular, this method allows for easy, fast, and routine manipulation for subsequent backside FIB milling and analysis.
Metallographic Investigation on Solder Creep Phenomenon
Authors: Gustilo Paul Angelo D. , Fernandez Joyce Lyn G. 
Published: December 2020

Abstract
Solder bulging is detected on the exposed paddle of Device A after burn-in causing the affected units to fail the coplanarity criteria. The affected units show up at random burn-in board socket locations and occur with varying frequency. Potential causes are plotted through an Ishikawa diagram which reveal fusion and creep as the potential mechanisms behind the solder bulging phenomenon. This paper seeks to determine the mechanism behind the solder bulging phenomenon via a 2-step metallographic investigation through (i) material deformation characterization and (ii) deformation mechanism simulation. In material deformation characterization, visual inspection on affected units show that the solder bulge is generally circular and is located on the center of the exposed paddle. Moreover, SEM/EDX analysis reveal that the solder bulge is not caused by a foreign contaminant or a compositional anomaly in the solder plating. On the other hand, deformation mechanism simulation involves the metallographic comparison between controlled simulations of fusion and creep versus the actual unit with solder bulge. Metallographic inspection reveal that the grain size and grain shape of the solder bulge possess the characteristics of creep phenomenon. Additionally, investigation on the burn-in (BI) process conditions also supports creep over fusion as the mechanism behind the solder bulging phenomenon. The static stress induced by the socket on the package at elevated temperature caused the solder plating to creep towards the free area which is the hole on the bottom of the socket.
Challenges for Physical Failure Analysis of 3D-Integrated Devices—Sample Preparation and Analysis to Support Process Development of TSVs
Authors: Meyer Andreas , Grimm Gabriele , Hecker Michael , Weisheit Martin , Langer Eckhard 
Published: December 2020

Abstract
The trend to higher integration of electronic devices to include more functions into ever-smaller devices, such as mobile phones or tablet computers, drives the development of novel packaging technologies for semiconductor chips. One of the approaches to reduce packaging size and power consumption is to stack multiple silicon chips on top of each other. An alternative approach is the utilization of through-silicon vias (TSV) to connect multiple chips to each other. This paper provides a set of sample preparation and analysis techniques for the comprehensive analysis of TSVs in support of technology development and qualification. The toolset ranges from simple cross-section imaging of cleaved samples to the evaluation of wafer planarity at the end of the TSV process flow and to the more specific analysis of the stress field around TSVs. The results provide valuable insights for designers, integration engineers, and process engineers.
The Unique and Completed Characteristics of Device Behaviors in the Nanoprobing Analysis and Application for Missing LDD
Authors: Lai LiLung 
Published: December 2020

Abstract
The Nanoprobing technique has become a popular tool for the Failure Analysis. This paper tries to establish the fundamental postulates for the following improvement of the technique. After description of the postulates, the application to missing or blocked LDD is claimed. Meanwhile, the following strategy of post-Nanoprobing is discussed by the case of missing LDD and for general conditions.
Sub-mohms Resistance Characterization of Conductive Interfaces on Automotive Power MOSFET to Determine the Origin of On-Resistance Drift
Authors: Weber Yann , Rousseille Philippe 
Published: December 2020

Abstract
This paper presents an original approach allowing determining the failure mechanism at the origin of onresistance (RDSon) drift on vertical Power N-MOSFETs, dedicated to automotive application. The studied devices failed after Temperature Cycling (TC) qualification stress. The originality of that paper concerns the necessity to use strategic Failure Analysis (FA) approaches to determine the origin of the defect, without any localization possibilities. In that perspective, an original microprobing sub-mohms resistance electrical characterization of the different conductive interfaces was performed in order to determine the failing layer. Then, physical destructive FA techniques (backside SAM, leadframe peel-off and mechanical cross-section) were combined in order to finely characterize the defect. As a result, problems in die attach layer were highlighted, confirming the electrical probing characterization. At last, root cause of this abnormal die attach will be discuss through review of assembly process parameters. These results allowed implementing corrections and improving product stress resistance.
UV-Raman Microscopy on the Analysis of Ultra-Low-k Dielectric Materials on Patterned Wafers
Authors: Huang Maggie Y.M. , Ng Tsu Hau , Tan Hao , Dawood Mohammed Khalid Bin , Tan Pik Kee , Lam Jeffrey C.K. , Mai Zhihong 
Published: December 2020

Abstract
With the shrinkage of the IC device dimensions, Cu and ultra-low-k dielectric were introduced into IC devices to reduce RC delay. Ultra-low-k dielectrics generally suffer more damage than silicon oxide dielectric during process integration and subsequently cause reliability degradation. Therefore, ultra-low-k damage characterization on Cu damascene structures is of great importance to understand the damage mechanisms. This paper describes the application of UV-Raman microscopy with enhanced spatial resolution and signal sensitivity for characterizing ultra-low-k dielectric in the three-dimension structure of Cu metallization with nanometer feature size. It shows UV-Raman technique has an advantage in analyzing ultra-low-k layer on patterned wafer and extracting ultra-low-k signals from Cu/ultra-low-k mixed structure. UV-Raman is also effective to characterize the ultra-low-k degradation for ultra-low-k related reliability analysis by time dependent dielectric breakdown (TDDB) test.
Applying Innovative Techniques for Solving FA Challenges of 3D IC Failures Utilizing Conventional Equipment
Authors: Tan Phoumra , Ng Kenny , Thorne Eric , Pai S.Y. , Hamilton Doug , Nuez Dan 
Published: December 2020

Abstract
With the advent of three-dimensional stacked integrated-circuit (3D IC), the functionality, performance and power of semiconductor devices has been elevated to a new level. At the same time, the analytical techniques used in the evaluation of 3D IC must also advance in capability. Some new methodologies, based on FPGA products, have been developed to analyze 3D IC failures, all using conventional FA equipment and innovative techniques to achieve a short turn-around time and high success rate. A few case studies will be presented to show the effectiveness of the methodologies.
Applications and Techniques for 2D Picosecond Imaging for Circuit Analysis
Authors: Stellari Franco , Song Peilin , Weger Alan J. 
Published: December 2020

Abstract
In this paper, we present the latest results obtained with a 2D Picosecond Imaging Circuit Analysis (PICA) camera with enhanced Near InfraRed (NIR) sensitivity [1] for taking 2D Time Resolved Emission (TRE). We will discuss key applications where the time-resolved imaging capability is very effective in reducing the debug time and improving the interpretation of the failure signatures of several VLSI chips. Besides conventional chip diagnostics, specific focus will be dedicated to new areas of applications, such as security and reverse engineering [2]. We will also discuss spectral analysis and other techniques that can be used to extract valuable information from the PICA dataset.
Localization of Weak Points in Thin Dielectric Layers by Electron Beam Absorbed Current (EBAC) Imaging
Authors: Jatzkowski Jörg , Simon-Najasek Michél , Altmann Frank 
Published: December 2020

Abstract
A novel approach for the localization of weak points in thin transistor and capacitor oxides before electrical breakdown will be presented in this paper. The proposed approach utilizes Electron Beam Absorbed Current (EBAC) imaging based on Scanning Electron Microscopy (SEM). This technique uses the generation of additional charge carriers within the semiconductor substrate level by scanning with a focused electron beam. Over a thin transistor or capacitor oxide layer inside the interaction volume of the electron beam an increased tunnel current is visualized by EBAC and shows areas with different current intensities indicating weak points. These soft defect areas are investigated in comparison to references which were analyzed by using cross sectioning in a dual beam FIB/SEM system followed by a high resolution Transmission Electron Microscopy (TEM) investigation. The feasibility of this new technique is demonstrated on a defective transistor gate oxide test structure.
Fault Isolation Using Electrically-Enhanced LADA (EeLADA)
Authors: Goh S.H. , Yeoh B.L. , You G.F. , Hao H. , Sio W.L. , Lam J. , Chua C.M. 
Published: December 2020

Abstract
Pulsed-LADA is found to play an important role in the advancement of next-generation LADA and it is reported that tens of μs pulses with 10 kHz frequency is sufficient to observe enhancements in carrier injection. Electrically-enhanced LADA (EeLADA), based on pulsed-LADA, is introduced as a new fault localization method capable to overcome current limitation of Laser Assisted Device Alteration (LADA) application on soft failure and extends it to hard failure debug. We present the EeLADA methodology and experimental data to demonstrate its feasibility.
Quantitative SiGe TEM Elemental Analysis in FinFET Test Structures
Authors: Demarest James , Bruley John 
Published: December 2020

Abstract
As semiconductor device scaling continues to reduce the structure size, device geometries are also changing to three dimensional structures such as finFETs, and the materials which compose the devices are also evolving to obtain additional device performance gains. The material change studied in this paper is the introduction of silicon germanium into the electrically active region of a finFET test structure. The paper demonstrates a quantitative energy dispersive X-ray spectroscopy transmission electron microscopy (TEM) technique through the use of blanket film calibration samples of known concentration characterized by X-ray diffraction. The technique is used to identify a test structure issue which could only be diagnosed with a technique having nanometer spatial resolution and atomic percent sensitivity. The results of the test structure analysis are independently verified by the complementary TEM electron energy loss spectroscopy technique.