bluuebunny/crossref_metadata_2025_split huggingface dataset:
Scan-Shift Debug Using LVI Phase Mapping
Authors: Ng Yin (Roy) S. , Marks Howard , Nemirov Christopher , Tsao Chun-Cheng , Vickers Jim 
Published: December 2020

Abstract
Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LVP) [3], the Physical Failure Analysis (PFA) success rate exceeds 90% for all types of failing conditions, from hard stuck-at fails to soft transition fails. This combination of Electrical Failure Analysis (EFA) techniques is effective because of its ability to pre-isolate the defect to a small enough area for successful PFA. While high PFA success rates are proven, there remains the issue of throughput: CW-LVP can be time consuming, and techniques that minimize the need for it are important. This paper introduces a novel LVI methodology that incorporates phase information [4] and reduces the need for CW-LVP for certain types of failures. Case studies will be presented.
Routine Device-Level Atom Probe Analysis
Authors: Lawrence D.F. , Ulfig R.M. , Larson D.J. , Olson D.P. , Reinhard D.A. , Martin I.Y. , Strennen S. , Clifton P.H. 
Published: December 2020

Abstract
Continuing advances in Atom Probe Tomography and Focused Ion Beam Scanning Electron Microscope technologies along with the development of new specimen preparation approaches have resulted in reliable methods for acquiring 3D subnanometer compositional data from device structures. The routine procedure is demonstrated here by the analysis of the silicon-germanium source-drain region of a field effect transistor from a de-packaged off-the-shelf 28 nm design rule graphics chip. The center of the silicon-germanium sourcedrain region was found to have approximately 180 ppm of boron and the silicide contact was found to contain both titanium and platinum.
Advances in FIB-SEM Analysis of TSV and Solder Bumps—Approaching Higher Precision, Throughput, and Comprehensiveness
Authors: Hrnčíř Tomáš , Dluhoš Jiří , Hladík Lukáš , Moyal Efrat , Teshima Janet , Kopeček Jaromír 
Published: December 2020

Abstract
Cross sections of large Through Silicon Vias (TSV) and solder bumps are often prepared using the Focused Ion Beam (FIB). The high current Xe plasma ion source allows fast and precise target preparation of TSV with small diameter. Solder bumps can be accessed due to the high milling rate too. However, the high current milling by plasma FIB causes the worsening of the milled surface quality. An optimized FIB scanning strategy accompanied with the novel rocking stage for the sample tilting during the milling has been developed for the plasma FIB. Whole milling process is observed by the Scanning Electron Microscopy (SEM). Time to prepare a cross section is accelerated and the excellent quality is suitable for subsequent failure analysis. Also important is proper sample cleaving before FIB milling. Using an accurate method to cleave the sample prior to FIB preparation further reduces the overall sample preparation time. The high quality cross sections prepared using this new method are ready not only for SEM but also for EDX and EBSD analysis, either 2D or 3D, when combined with FIB slicing. Broadening the analysis to these techniques increases the obtainable information, allowing the arrangement of materials and their crystalline structure to be studied in a detail.
Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs
Authors: Kearney Ian , Sung Hank 
Published: December 2020

Abstract
Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.
Application of Automated FIB for TEM Sample Preparation in Semiconductor Failure Analysis
Authors: Zhu Jie , Seah Soo Sien , Tee Irene , Liu Bing Hai , Er Eddie , Zhao Si Ping , Lam Jeffrey , Najarian Mark , Brogden Valerie 
Published: December 2020

Abstract
In this paper, we describe automated FIB for TEM sample preparation using iFast software on a Helios 450HP dual-beam system. A robust iFast automation recipe needs to consider as many variables as possible in order to ensure consistent sample quality and high success rate. Variations mainly come from samples of different materials, structures, surface patterns, surface topography and surface charging. The recipe also needs to be user-friendly and provide high flexibility by allowing users to choose preferable working parameters for specific types of samples, such as: grounding, protective layer coating, milling steps, and final TEM lamella thickness/width. In addition to the iFast recipe, other practical factors affecting automation success rate are also discussed and highlighted.
Quantitative Analysis of Interference Noise by Capacitive Coupling Effects in DRAM
Authors: Seo Seoungbin , Lee Hyongyong , Hong Heeil , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung 
Published: December 2020

Abstract
As microelectronic feature sizes are scaled down, the soft failure rate has increased. Additionally the characteristics and distribution of Dynamic Random Access Memory (DRAM) data retention time and write recovery time (tWR) are getting worse. As a result of this failure analysis, we revealed that the major contributors are caused by the interference noise, resultant from decreasing separation distance between nodes and the signal line noise increasing. This paper gives a detailed analysis of the problem caused by the coupling effects. We investigated the cause of soft noise by simulation and proposed calculation of sensing margin change by interference noise. Finally, we expect that a design improvement to reduce the magnitude of interference noise will result in overall improvement when implemented in the test vehicle.
Novel FIB Use for Failure Analysis of MEMS Gyroscopes
Authors: Wang Nathan , Shah Saunil , Garcia Camille , Pasating Vicente , Perreault George 
Published: December 2020

Abstract
MEMS samples, with their relatively large size and weight, present a unique challenge to the failure analyst as they also included thin films and microstructures used in conventional integrated circuits. This paper describes how to accommodate the large MEMS structures without skimping on the microanalyses needed to get to the root cause. Investigations of tuning folk gyroscopes were used to demonstrate these new techniques.
Fault Isolation of DQ Failures in 14 nm SRAM Using Laser Voltage Imaging and Probing
Authors: Serrels K.A. , Kalarikkal A. , Jakati A.M. , Dabney G. 
Published: December 2020

Abstract
Through custom test pattern generation and SRAM design analysis, we present the first demonstration of Laser Voltage Imaging (LVI) and Probing (LVP) for the successful fault isolation and physical analysis of DQ failures within a 14nm SRAM macro. These findings revealed the fail site to reside within the I/O circuitry of the associated failing pin, a previously overlooked location as common block failures are typically associated with physical anomalies within the SRAM periphery.
Thermal Exposure Effects of Backside Thinned Flip-Chip Device on Visible Light Probing
Authors: Li Jane , Halteh Elia , Elliott Jonathon , Marks Howard Lee , Richardson Chris 
Published: December 2020

Abstract
We report the results of our studies on thermally induced surface topography changes in ultra-thinned silicon flip-chip packaged devices. Previous results showed that over polishing can result in bump topography on the ultra-thinned Si backside. The topographic bumps were found to form over the solder bump locations on the die. Our latest results show that heating exacerbates the topological variation, possibly due to underfill shrinkage caused by additional curing during heating, or plastic deformation caused by underfill and bump CTE mismatch. Our findings are relevant for Visible Light Probing because the induced topography can prevent Solid Immersion Lenses from making the intimate contact necessary for optimum performance.
Nanoscale 3D X-ray Microscopy for High Density Multi-Chip Packaging FA
Authors: Schmidt Christian , Hartfield Cheryl , Kelly Stephen T. , England Luke , Kannan Sukeshwar 
Published: December 2020

Abstract
An effective method is presented to locate certain failure sites on exposed junction of insulated-gate bipolar transistor (IGBT) devices. High emitter to collector leakage current, hereafter called ICESR, is an IGBT failure mode. The leakage current is typically related to the exposed P+/N+ junction on the die sidewall. Solder die attach residue bridging or silicon damage at this exposed P+/N+ junction are common causes of ICESR leakage. The die attach residue can be dislodged during decapsulation resulting in loss of failure information. A failure analysis flow will be described to precisely locate the ICESR leakage site without disturbing any possible die attach residue.
Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes
Authors: Sheridan Lucile C. Teague , Schaeffer Tanya , Wei Yuting , Kodali Satish , Oh Chong Khiam 
Published: December 2020

Abstract
It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.
Contamination Troubleshooting Approach from Problem to Solution
Authors: Chia Victor K. F. , Gotts Hugh E. , Li Fuhe , Camenzind Mark 
Published: December 2020

Abstract
Semiconductor devices are sensitive to contamination that can cause product defects and product rejects. There are many possible types and sources of contamination. Root cause resolution of the contamination source can improve yield. The purpose of contamination troubleshooting is to identify and eliminate major yield limiters. This requires the use of a variety of analytical techniques[1]. Most important, it requires an understanding of the principle of contamination troubleshooting and general knowledge of analytical tests. This paper describes a contamination troubleshooting approach with case studies as examples of its application.
Loop Transformation Algorithm for Test Vector Accessing at High Speed
Authors: Dahlberg Bjorn , Versen Martin 
Published: December 2020

Abstract
Looping on test vectors is a widespread requirement in failure analysis of semiconductor devices. The start of the loop and the number of vectors in the loop can be of critical importance. Present-day vector memory architecture tends to impose restrictions on both due to test speed requirements. A new Vector Loop Transformation algorithm is introduced to remedy the tester constraints.
Submicron Thinning of finFET Devices with High Power Density Observed in 10/7nm Process Nodes Using High Aspect Ratio Trenches
Authors: Bakken Nathan , Vlasyuk Vladimir , Beal Michael , Artishuk Ilya , Chivas Robert , DiBattista Mike , Silverman Scott 
Published: December 2020

Abstract
Infrared optical probing techniques that have significant applications to and continued development for silicon physical debug have existed for decades. More recently, resolution enhancement achieved by improving numerical aperture, etc. have reached fundamental limits and the ability for resolution to match node scaling with radiation transparent to silicon (photon energy &lt; silicon bandgap) becomes diffraction limited for some 10nm and many future process nodes. Decreasing the wavelength used for imaging and signal acquisition can improve resolution; however, it is well documented that absorption increases sharply for photons with energy greater than the bandgap of the bulk substrate material. Significant reduction in the thickness of the backside substrate material can be performed to achieve acceptable transmission through the absorbing substrate, but the requirement for very thin sample preparation significantly modifies the thermal system surrounding active circuitry. Here, high aspect ratio trenches are shown to offer a unique method to take advantage of thick silicon (&gt; 100µm) for lateral heat dissipation as well as thin silicon (&lt; 2µm) for minimally absorbing optical path in close proximity to enable case-by-case preparation methods for postsilicon labs faced with visible light resolution requirements on high power density circuits.
Expression of the neurotrophic tyrosine kinase receptors,ntrk1andntrk2a, precedes expression of otherntrkgenes in embryonic zebrafish
Authors: Hahn Katie , Manuel Paul , Bouldin Cortney 
Published: December 2020

BackgroundThe neurotrophic tyrosine kinase receptor (Ntrk) gene family plays a critical role in the survival of somatosensory neurons. Most vertebrates have threeNtrkgenes each of which encode a Trk receptor: TrkA, TrkB, or TrkC. The function of the Trk receptors is modulated by the p75 neurotrophin receptors (NTRs). Fiventrkgenes and one p75 NTR gene (ngfrb) have been discovered in zebrafish. To date, the expression of these genes in the initial stages of neuron specification have not been investigated.PurposeThe present work used whole mount in situ hybridization to analyze expression of the fiventrkgenes andngfrbin zebrafish at a timepoint when the first sensory neurons of the zebrafish body are being established (16.5 hpf). Because expression of multiple genes were not found at this time point, we also checked expression at 24 hpf to ensure the functionality of our six probes.ResultsAt 16.5 hpf, we found tissue specific expression ofntrk1in cranial ganglia, and tissue specific expression ofntrk2ain cranial ganglia and in the spinal cord. Other genes analyzed at 16.5 hpf were either diffuse or not detected. At 24 hpf, we found expression of bothntrk1andntrk2ain the spinal cord as well as in multiple cranial ganglia, and we identifiedngfrbexpression in cranial ganglia at 24 hpf.ntrk2b,ntrk3aandntrk3bwere detected in the developing brain at 24 hpf.ConclusionThese data are the first to demonstrate thatntrk1andntrk2aare the initial neurotrophic tyrosine kinase receptors expressed in sensory neurons during the development of the zebrafish body, and the first to establish expression patterns ofngfrbduring early zebrafish development. Our data indicate co-expression ofntrk1,ntrk2aandngfrb, and we speculate that these overlapping patterns indicate relatedness of function.
Temperature effect on the physical and mechanical properties of parallel strand bamboo
Authors: Liu Yanyan , Huang Dongsheng , Zhu Yan 
Published: December 2020

SummaryThis study sets out to assess the temperature effect on the physical and mechanical properties of parallel strand bamboo (PSB). Seventeen temperature levels, in the range of 20°C to 290°C, were considered. Results indicated that a high temperature led to a reduction in compressive strength and modulus. The reduction is associated with the glass transition and thermal decomposition of the chemical compositions in bamboo. Due to the higher crystallinity of cellulose at high temperatures between 150°C and 190°C, a rising in the compressive modulus parallel‐to‐grain was observed. The temperature effect on the mechanical properties of PSB was further supported by scanning electron microscopy (SEM) images. Statistical regression‐based models were developed for predicting the reduction of compressive strength and modulus of PSB with exposure temperature. The models provided a good fit to the experimental data. Comparison with that of bamboo scrimber and timber structures in literature was also presented in this study.
The effect of mushroom management style and perceived supervisor support on employee performance: ‘An application with university hospital employees’
Authors: Yorgancioglu Tarcan Gamze , Erigüç Gülsün , Kartal Nazan , Şeyma Koca Gülsüm , Karahan Ayça 
Published: December 2020

AbstractObjectivesMushroom management, which has entered the management literature using the metaphor of growing mushrooms, is a management style in which managers generally keep their power and knowledge in one centre and do not like to be questioned and criticized. This study conducted to determine the effect of the mushroom management style of administrative staff working in the healthcare sector and perceived supervisor support on job performance.MethodsA total of 234 healthcare professionals included in the study. To achieve the purpose of the study, the ‘Mushroom Management Scale’, the ‘Perceived Supervisor Support Scale’ and the ‘Job Performance Scale’ were used. Multivariate linear regression analyses were performed to analyse.ResultsWhen the effect of mushroom management style on job performance was examined, it was found that inadequate information sharing, the anxiety of power loss, inadequate communication and lack of participatory management did not have a significant effect on job performance alone. According to the regression analysis, perceived supervisor supports have a significant effect on a job performance. This effect explains 0.045 of the total variance. The fact that employees received tangible support from their managers increased their performance levels positively (t = 2.945; p < 0.05). Finally, employee performance had a significant effect on perceived supervisor support. This effect explains 0.513 of the total variance.ConclusionsAs a result of this study, it was found that mushroom management style had no effect on job performance, but had a significant effect on perceived supervisor support.
Nonlinear radiation and cross‐diffusion effects on the micropolar nanoliquid flow past a stretching sheet with an exponential heat source
Authors: Mishra Satyaranjan , Mahanthesh Basavarajappa , Mackolil Joby , Pattnaik Pradyumna K. 
Published: December 2020

AbstractMetallurgy, polymer and processing engineering, and petrochemical enterprises frequently encounter polar nanoliquid flows due to stretchable surfaces with radiative heat energy. Therefore, the radiative flow of a polar nanoliquid over a stretchable sheet is analyzed considering cross‐diffusion and magnetic heat flux effects. The heat transport phenomenon is explored, including the characteristics of nonlinear radiation and exponential space‐based heat generation. The highly nonlinear governing equations are converted to ordinary differential equations using apt transformations. These are, in turn, solved employing the finite difference method. The behavior of contributing parameters is presented using graphical visualizations. The interactive impacts of the pertinent constraints on the rate of heat transfer and skin friction are analyzed using three‐dimensional surface plots. The enhancement of the temperature profile is observed by incrementing the radiation and exponential heat generation parameters. The magnetic field can be used to regulate the fluid flow as it decreases the flow field. Also, the heat generation factor has a predominant decreasing effect on the Nusselt number.
Audiometric Profile of Cochlear Implant Recipients Demonstrates Need for Revising Insurance Coverage
Authors: Barnes Jason H. , Yin Linda X. , Marinelli John P. , Carlson Matthew L. 
Published: December 2020

Objectives/HypothesisTo describe the pre‐implant audiometric profile of adult cochlear implant (CI) recipients to investigate whether current binaural candidacy requirements prevent access to patients who could benefit from CI.Study DesignRetrospective case series.MethodsRetrospective review from 2016 to 2018 evaluating preoperative pure‐tone thresholds and speech perception scores in the ipsilateral and contralateral ear.ResultsA total of 252 adult CI recipients undergoing 270 implants were identified. Median age at time of implantation was 70.5 years (IQR 61.3–78.3) for those undergoing unilateral implantation and 59.0 (IQR 48.0–72.3) for those undergoing bilateral implantation (P < .01). For unilateral implantation, median pre‐implantation speech perception performance in the ear to be implanted was 8.0% (IQR 0%–26.0%) for CNC word scores, and 9.0% (IQR 0%–34.0%) for AzBio sentence scores in quiet. Median speech perception performance in the contralateral ear was 36.0% (IQR 14.0%–60.0%) on CNC word scores, and 48.5% (IQR 17.5%–76.0%) on AzBio sentence tests. Speech perception scores were significantly different between ears for word and sentence tests (P < .01). Patients older than age 65 were significantly less likely to undergo bilateral implantation (P = .03).ConclusionsAdult CI recipients exhibit substantially poorer pre‐implant speech perception scores than the commonly utilized ipsilateral qualifying threshold of 50% on sentence testing. Yet, existing insurance paradigms limit patients by excessively stringent binaural best‐aided requirements. This limitation likely leads to worse device performance as patients often wait years for their binaural hearing to qualify while their ear to be implanted potentially experiences an unnecessarily extended duration of deafness. Older patients also experience a unique delay in referral for cochlear implantation.Level of Evidence3‐ Retrospective review Laryngoscope, 131:E2007–E2012, 2021