Silicene Nanoribbon Tunnel Field Effect Transistor
Authors: Fahad Md S , Srivastava Ashok , Sharma Ashwani K , Mayberry Clay , Mohsin K M 
Published: February 2020

Scaling of metal oxide semiconductor field effect transistor (MOSFET) following the Moore’s law is approaching to its near end as the power dissipation at the chip level is becoming increasingly difficult to reduce [1]. The International Technology Roadmap for Semiconductors (ITRS) considers several non-classical devices as a future replacement of silicon-based MOSFETs among which tunnel field effect transistor (TFET) is found to be promising [2, 3]. Compared to bulk three dimensional material based TFETs, study of TFETs based on two dimensional atomically thick materials have shown potential to operate at low supply voltage with a low subthreshold slope (SS) compared to 60mV/decade in conventional MOSFETs [4]. Different forms of two dimensional materials are studied such as Dirac cone materials (graphene, silicene, gemanene, stanene), transition metal dichalcogenides (TMD), transition oxides (TO) and topological insulators (TI). Compared to the study of TFET based on other two dimensional materials, silicene TFET remained large unexplored.
Silicene is the two dimensional atomically thick planer form of bulk silicon. Stable room temperature operation of FET based on silicene has recently been reported [5]. Like graphene, silicene is a Dirac cone material with devices which provide high off-state leakage current due to the lack of a significant bandgap. However, quantum confined silicene nanoribbon (SiNR) shows observable bandgap making it suitable for digital applications [6]. Moreover, being an allotrope of silicon, silicene is also expected to be suitable for fabrication technology. Here, we present our work on SiNR TFET using atomistic simulation based on self-consistent solution of the 3D Poisson and Schrödinger equations within the non-equilibrium Green’s function (NEGF) formalism.
SiNR has two types of edges, armchair and zigzag. We have considered armchair configuration in our study for a channel length of 10nm of a double gate SiNR TFET. Source and drain are 10nm each. Our default SiNR width is ~4nm providing a band gap of 1.42eV. Top and bottom gate oxides of our studied TFET are 2nm of SiO2. The effective tight binding Hamiltonian is adopted from the work of Voon et al. [7] and is simulated using the simulation code proposed in [8] for Si-Si bond length of 2.25Å and hoping integral of -6.43eV with -1.12eV correction at the SiNR edges [7]. The n+-type source and p+-type drain are doped with a molecular fraction of 0.001. A drain source voltage (VDS) of 0.3V is considered in this work.
The studied SiNR TFET provides an on/off current ratio of ~107 with an average steep subthreshold slope (SS) of 6mV/decade for VDS=0.3V. A record low ~0.75x10-11pW/μm off-state leakage power is estimated. We have found that the leakage level increases as the supply voltage increases. The off-state leakage current increases to 0.6pA/μm as VDS increases from 0.3V to 0.95V. As the width of SiNR increases and the corresponding band gap decreases, leakage current also increases at small band gap with a reduction in on/off current ratio. The steep subthreshold slope of our studied SiNR TFET suits low power operation. With a suitable high-k dielectric and low gate oxide thickness, on-state drive current can be improved. Performance of SiNR TFET is also compared with ITRS projected high performance (HP) requirements of 2026 nMOSFET where SiNR TFET exceeds the performance of 2026 nMOSFET by 1014 times less power dissipation at 103 times higher on/off current ratio.

Acknowledgement: Part of the work is supported by the United States Air Force Research Laboratory under agreement number FA9453-10-1-0002. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon.

References: [1] M. Lundstrom, Science, 299, 5604 (2003) [2] ITRS online: http://www.itrs.net/links/2013itrs/ summary2013.htm [3] D. E. Nikonov and I. A. Young, Proc. IEEE, 101, 12 (2013) [4] D. Jena, Proc. IEEE, 101, 12, (2013) [5] L. Tao et al., Nat. Nano,
10, (2015) [6] Kim et al., Phys Rev. B, 86, (2012) [7] L. Voon et al., New J. Phys., 17, (2015) [8] G. Fiori and G. Iannaccone, available:www.vides.nanotcad.com/vides, (2013)