Tight Control of SiGe Condensation Technique for Large Scale Fabrication of High Quality Thick S0.5G0.5oi Layer
Authors: Gourhant Olivier , Mallet Anne-Flore , Arette-Hourquet Adam , Favre Luc , Berbezier Isabelle , Duluard Christophe , Takala Adonis Steve , Madaci Ismail 
Published: December 2024

The development of thick pseudo-substrate of SiGe usually involves a complex epitaxy of several microns thick gradual buffer layer. However, a drawback of this approach relies on high roughness of the top layer which implies the addition of subsequent planarization step. Furthermore, if the top part of the layer is relaxed and defect free, abundant dislocations are embedded several microns deep. They can expand during following thermal processes, possibly reaching the surface. Obviously, these defects are detrimental for electronic and photonic purposes. State of the art studies report dislocations density around 106 cm-2 for on a Si0.7Ge0.3 substrate[1].
This study shows an alternative approach based on the combination of the SiGe condensation technique combined with a thick epitaxy (figure 1). We demonstrate, using 300mm industrial conditions, that a tight control of SiGe condensation parameters (initial SiGe thickness and composition) allows to improve the structural quality of the thin SGOI to reach ultimate reduction of dislocations. Subsequently, this thin SGOI is used as a pedestal above which is grown a thick layer of SiGe using a simple, constant-composition epitaxy. The slippery SiGe/BOX interface is expected to relax part of the stress, allowing the growth of high quality thick SGOI layer [2,3].
First, a thin epitaxy of 25nm fully strained Si0.8Ge0.2 is deposited by RP-CVD on a 300mm SOI wafer. The precursors gases are Germane, Dichlorosilane and Hydrochloric. Afterwards, SiGe condensation is performed using optimized high-temperature slow oxidation to generate thin SGOI structures, with Ge concentration varying from 40 to 55% [4]. Thickness and composition are characterized by Spectroscopic Ellipsometry. AFM and TEM cross-section allow the analysis of crystalline quality of both surface and core of the SGOI structures. The resulting thin SGOI structures exhibit typical defects at the surface revealing in-depth dislocations (figure 2). The defects density is around 105 cm-2 until 50% Ge concentration. Above this concentration, defects density increases rapidly toward 1010 cm-2, in agreement with literature [4,5]. Therefore, the next step focuses on thin SGOI with a maximum Ge concentration of 50%.
When reducing the initial SiGe thickness and Ge concentration, defect density of the thin SGOI is strongly improved (figure 3). It exhibits a crucial impact of the stress contained in the initial SiGe layer. Especially, strong influence of the initial Ge concentration is observed: for a 20nm thick initial SiGe layer, a 0.5% decrease of the Ge concentration avoids any defect formation at the surface and in depth of the thin S0.5G0.5OI (figure 4). Raman measurement is performed on a S0.45G0.45OI structure and exhibits 1.6% in-plain strain, showing the pseudo-morphic behavior of the SiGe layer. This study shows that a precise control of the initial SiGe thickness and content allows to fabricate a dislocation free thin S0.5G0.5OI structure.
Taking advantage of the weak SiGe/BOX interface achieving possibly stress relaxation, this SGOI structure is a promising compliant pedestal to limit defects creation during the subsequent thick Si0.5Ge0.5 epitaxy. A preliminary trial is achieved: above the defect-free thin S0.5G0.5OI structure, a thick SiGe epitaxy is grown using a constant Ge concentration during all the process. Ge concentration profile along the radius of the wafer was precisely tuned to match the one of thin SGOI (figure 5). The result is promising: no defects are observed in the top part of the layer, allowing a very smooth top surface and no noticeable interface is detected between the two SiGe layers, generating a homogenous crystal (figure 6). However, many crystalline defects are detected at the bottom of the SiGe layer. Analyzing several images, a defect density of 10⁹ cm⁻² is calculated. Though, a close look at the SiGe/BOX interface reveals the presence of SiO2 clusters, from which almost all defects are starting from. These clusters could be due to a bad surface preparation prior to the thick SiGe epitaxy, leaving Si-O or Ge-O residues that could migrate to nucleate into SiO2 precipitates. When growing, these precipitates create a stress field, helping defects formation. A somewhat similar issue was observed in literature [6]. A more efficient surface preparation is under development to completely remove these SiO2 clusters and drastically improve the final defects density.
[1] Hartmann et al., Semicond. Sci. Technol., vol. 19, no 3, p. 311-318, 2004
[2] Boureau et al., ECS, 2018
[3] Usuda, et al., Solid-State Electronics, 2013
[4] Valenducq et al., EUROSOI-ULIS, 2019
[5] Takagi et al., ECS Trans., 33 (6) 501-509 (2010)
[6] Kim et al., Opt Express. 2013 Aug 26;21(17):19615-23

Figure 1