Fabrication and Performance of InAlN/GaN-on-Si MOSHEMTs with LaAlO3 Gate Dielectric Using Gate-First CMOS Compatible Process at Low Thermal Budget
Authors: Bera Milan Kumar , Liu Yi , Kyaw Lwin Min , Ngoo Yi Jie , Singh Sarab Preet , Chor Eng Fong 
Published: February 2020

Introduction

Recently, lattice matched InAlN/AlN/GaN-on-silicon integration approach has attracted increasing attention due to the availability of high-quality GaN epiwafers with high throughput epitaxial growth on large area Si substrates for applications in power and RF devices with low power consumption [1-2]. Meanwhile, the development of gate-first process is useful to realize future self-aligned transistor structures. Conventional fabrication of InAlN/GaN high electron mobility transistors (HEMTs) or metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) involves gate-last process where high temperature (>800 oC) annealing is required to form Ti/Al/Ni/Au source and drain ohmic contacts [3]. This is a consequence of traditional gate metallization (e.g., Ni/Au) and gate dielectric not being able to survive such a high ohmic annealing temperature. Therefore, the development of good ohmic contacts with a low thermal annealing budget and thermally stable gate dielectric is required to realize the gate-first process integration for InAlN/GaN HEMTs/MOSHEMTs. In the present work, we report the fabrication and characterization of InAlN/GaN MOSHEMTs using a lift-off free, gate-first CMOS compatible process developed at low thermal budget.

Experiment

The lattice-matched In0.18Al0.82N/AlN/GaN-on-Si (111) HEMT structure used in this experiment is shown schematically in Fig. 1. The MOSHEMT fabrication using a gate-first process started from mesa isolation followed by 20 nm thick LaAlO3 (LAO) deposition using pulsed laser deposition (PLD) with a substrate temperature of 300 oC. Then, W was sputter deposited followed by gate definition using photolithography and dry etching method. Thereafter, Hf/Al/Ta layer was sputter deposited followed by rapid thermal annealing at 600 oC for 60 s in vacuum to form source and drain ohmic contacts.

Results and Discussion

The contact resistance and contact resistivity of Hf/Al/Ta ohmic contacts, as analyzed from linear transmission line method (LTLM), are found to ~0.60 Ω·mm and 6.7x10-6 Ω·cm2, respectively. At first, the thermal stability and reliability of the LAO gate dielectric upon 600 oC ohmic anneal in vacuum was optimized under several oxygen partial pressures during PLD. Comparison of capacitance-voltage and reverse gate leakage current characteristics of fabricated devices subject to different oxygen partial pressures in the range from 3.1×10-5 Torr to 5×10-3 Torr are shown in Figs. 2(a) and 2(b), respectively. It is found that LAO deposited under an oxygen partial pressure of 2.7×10-4 Torr exhibits the lowest gate leakage and highest accumulation capacitance, predominantly arisen by an increased dielectric permittivity (k~23.2). Finally, the gate-first CMOS compatible MOSHEMTs were fabricated by choosing the above optimized deposition condition for PLD (2.7×10-4 Torr @ 300 oC) of LAO. Devices having gate dimensions of W/L = 2×50/1 μm, gate-to-source distance of Lgs ~ 2 μm, gate-to-drain distance of Lgd ~ 6 μm, were used for DC output and transfer characterizations. The DC output and transfer characteristics are shown in Figs. 3 (a) and (b), respectively. The MOSHEMTs achieve a saturation drain current (Idsat) of 500 mA/mm at zero gate voltage, threshold voltage (Vth) of -12.6 V, maximum extrinsic transconductance (Gmax) of 44 mS/mm and on-resistance (Ron) of ~ 14 Ω/mm.

Conclusion

In conclusion, a gate-first CMOS compatible process for InAlN/AlN/GaN-on-Si MOSHEMTs fabrication has been developed. A low thermal budget (600 oC) for ohmic annealing is achieved through the use of Hf/Al/Ta source-drain contacts, thus allowing the fabrication of gate-first CMOS compatible MOSHEMTs using LaAlO3 as the gate dielectric as well as for device passivation purpose. The reasonable DC performance demonstrated (Idsat = 500 mA/mm, Gmax = 44 mS/mm, etc.) for a 1 μm gate length shows promising possibility for gate-first process integration of InAlN/GaN-on-Si MOSHEMTs.

References

[1] J. Kuzmik, 2001 IEEE Trans. Electron Dev. 22 510.
[2] F. Medjdoub, J. Carlin and M. Gonschorek, 2006 IEEE

Trans. Electron Dev.42 779.
[3] H. Sun, A. R. Alt, H. Benedickter, E. Feltin, J-F Carlin, M. Gonschorek, N. Grandjean and C. R. Bolognesi, 2010, IEEE Electron Device Lett., 31, 293.

Figure captions

Fig. 1: Schematic illustration of fabricated InAlN/GaN-on-Si MOSHEMT with LaAlO3as gate dielectric and passivation using a gate-first CMOS compatible process developed at low thermal budget.
Fig. 2: Comparison of (a) capacitance-voltage and (b) reverse gate leakage characteristics of MOS capacitors for 20 nm thick LaAlO3 deposited under different oxygen partial pressures and at substrate temperature of 300 oC.
Fig. 3: Measured (a) Ids-Vds
and (b) Ids-Vgs
characteristics of fabricated InAlN/GaN-on-Si MOSHEMTs with LaAlO3 as gate dielectric and passivation using a low thermal budget, gate-first CMOS compatible process.