(Dielectric Science and Technology Division Thomas D. Callinan Award Address) Dielectrics for MOS Integrated Circuits
Authors: Iwai Hiroshi 
Published: February 2020

Introduction

Insulator films are one of the fundamental elements of the semiconductor integrated circuits together with semiconductor substrate/films and metal/silicide interconnects. Functions of the insulator films in ICs (Integrated Circuits) are roughly classified into the following 6 categories; a) isolation between active devices, b) gate insulator of MOSFETs/MOS capacitors/MIM (Metal Insulator Metal) capacitors, c) sidewall insulation films for gate electrode, d) interlayer isolation films for interconnects, e) passivation films above the interconnects to cover and protect the IC chip surface, and f) insulator film between surface Si layer and Si substrate in SOI (Silicon On Insulator) wafer.
In this paper, author’s past works related to the insulator films used ICs are reviewed.

Introduction of BPSG reflow technique into NMOS LSI technology

One of the severe problems for ICs until the middle of 1970’s was the disconnection of the aluminum interconnects at the steps of insulation film over the edges of poly Si lines and field SiO2 regions. The author applied BPSG (BoroPhospho Silicate Glass) reflow technique for the first time in the world to his developed NMOS LSI technologies in Toshiba, making the steps completely smooth, verifying the yield, and long term reliability in the 1k bit SRAM products in 1975.

Finding of plasma induced damage to the gate oxide during ion-implantation and reactive ion etching

The author developed a 64k bit DRAM technology from late 1970’s to the beginning of 1980’s. The introduction of source/drain heavy ion-implantation and RIE (Reactive Ion Etching) techniques of poly Si gate electrodes (2nd poly Si) were necessary to fabricate the designed small cell size. The accumulated ionic charge to the capacitor poly electrodes (1st poly Si) during the ion-implantation and reactive ion etching broke the 3 nm gate oxide of the 1st poly Si capacitor, causing bit errors of DRAM. This phenomena were published at the late news of ECS for the first time in the world in 1982 (1).

Introduction of RTN gate oxide to prevent the boron penetration

In early 1990’s CMOS technology changed from that of single n+-poly Si gate to dual poly Si gate (n+-poly Si for NMOSFETs and p+-poly Si for PMOSFETs) technology, in order to suppress the short-channel effect of PMOSFETs. Because the boron diffusion through the gate SiO2 during the high temperature thermal process is very large, the high-concentration boron penetration from the p+-poly Si to the PMOSFET channel through the gate SiO2 became a big problem. This was known to be solved by introduction of nitrogen to the SiO2. The author and his colleagues demonstrated that the RTN (Rapid Thermally Nitrided) SiO2 gate film completely suppress the boron penetration even the nitrogen concentration in SiO2 is only several percent, for the first time in 1990 (2).

Introduction of direct-tunneling gate oxide for CMOS logic device

It has been assumed that the gate oxide thinning limit would be 3 nm, because of the significant increase of the gate leakage current by direct-tunneling mechanism. However, the author and his colleagues demonstrated that MOSFETs with 1.5 nm thick direct-tunneling gate oxide operate quite normally, even though there is the direct-tunneling leakage, when decreasing the gate length less than 0.1 um, because the ratio between the gate leakage current and the drain current deceases in proportion to the square of the gate length reduction rate (3).

Demonstration of the 0.4 nm EOT La-silicate gate oxide MOSFETs

In order to decrease the gate length of MOSFETs to 5 nm, EOT (Equivalent Oxide Thickness) of the gate oxide should be 0.4 nm. The author and his colleagues developed La-silicate high-k metal gate technology and demonstrated the excellent operation of 0.4 nm EOT MOSFETs (4).

Reference

S. Sawada, S. Maeda, Y. Matsumoto, H. Iwai, H. Nihira, and O. Ozawa, “Degradation of thin gate oxide under process induced electrical stress”, 162nd ECS Fall Meeting, Recent Newspapers, Detroit, USA, October, (1982).

T. Morimoto, H. S. Momose, K. Yamabe, and H. Iwai, “Prevention of boron penetration from p+ poly gate by RTP produced thin gate oxide”, ESSDERC 90, Nottingham, England, September, (1990), 73.

H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, H. Iwai, “Tunneling gate oxide approach to ultra-high current drive in small-geometry MOSFETs”, in IEDM Tech. Dig., December, (1994), 593

H. Iwai, T. Yasuda et al., “Research and development for second generation of ultra-thin gate insulator material”, NEDO Forum 2012 on energy saving technology, Tokyo, November, (2012): in Japanese