(Invited) New Developments in Magnetic Inductors for On-Chip Power Conversion, Including Fabrication
Authors: O'Sullivan E. J. , Wang Naigang , Deligianni Hariklia (Lili) , Doris Bruce , Bahgat Shehata Andrea , Webb Bucknell C. , Romankiw Lubomyr , Gallagher William J. 
Published: February 2020

Integrated dc-dc power converters have been the subject of intense research interest over the past 10 – 12 years because they offer so many potential benefits, not just in promising savings of up 20% of board space, but also enabling control of individual chip voltages and delivering power at high voltage and low current, thus reducing power train I2R loss. Among the various power converter options, the inductive Buck converter is the most attractive because it can deliver a wide output voltage range with an expected high efficiency (≥ 90%). However, for on-chip applications, the inductive Buck converter is the least developed power converter, there being at present no such inductor ready for use in a standard CMOS back-end-of-line (BEOL) fabrication facility.
Major strides towards the realization of on-chip power conversion have been made by IBM in case of its POWER8TM processor (1), and by Intel in case of its 4th generation (Haswell) processor (2), which uses near-chip- integrated power converters; although neither company’s new power converter used an integrated magnetic inductor. After highlighting the important role that magnetic inductors are expected to play in on-chip power conversion, this talk will describe new developments in magnetic materials for inductors, especially those employed at IBM, and the fabrication challenges faced in integrating these materials in inductors.
Yoke material and thickness (typically 1 - 5 microns) can be tailored to reach desired inductance values (i.e., 1 – 30 nH) in thin-film ferromagnetic inductors, while endeavoring to maintain a high enough operating frequency (i.e., 20 – 200 MHz). Electrodeposition was an enabling technology for the thin-film magnetic recording head, and was thus used for yoke fabrication of our earlier inductors (3, 4). IBM and Columbia University recently demonstrated an efficiency of 82% in a World's first 3D-integrated inductor/voltage regulator that employed thru-silicon via technology and electrodeposited Ni45Fe55 yokes (5). Nevertheless, significant advancements in eddy current suppression through electrodeposition of either sufficiently resistive or insulating-layer-laminated magnetic layers have proved elusive.
Thus, considerable efforts have gone into developing new, higher resistivity, sputtered magnetic alloys (> 100 µΩcm), usually with insulating lamination layers. A notable example produced by sputtering is amorphous Co91.5Zr4Ta4.5 (CZT), which has, for example, been used as the yoke material in inductors fabricated on top of 90 nm CMOS structures by Gardner et al. (6).
We chose to explore sputtered, laminated, amorphous Co20Fe60B20 magnetic films due to their extremely soft magnetic soft properties (Hc ≤ 0.1 Oe) and low, magnetic-permeability-related, loss tangent (≤ 0.1) for a wide range of frequencies, and thermal stability up to 350oC. This required development of a new fabrication scheme to integrate the blanket-deposited, sputtered magnetic layers with 200 mm CMOS substrates. We employed ion beam etching (IBE) patterning methods since no other method, e.g., wet etching, could anisotropically etch all of the inductor yoke stack materials.
Peak quality factors (Q) ≥ 12 (at 120MHz) were demonstrated on magnetic inductors containing laminated Co20Fe60B20 magnetic films as shown in Fig. 1, double the Q values of previous inductors that had electrodeposited Ni45Fe55. All inductor devices functioned across a 200 mm wafer, the consistent device performance observed indicative of a reliable, high-yield fabrication process.

Fig. 1.
Left: Comparison of Q values for inductors with sputtered Co20Fe60B20 materials and electrodeposited Ni45Fe55 (for the latter, see ref. 3). Right: Summary of Qpeak values for single-turn inductors on a 200 mm wafer.
[1] Z. Toprak-Deniz et al., ISSCC Digest, 112 (2014).
[2] E. A. Burton, et al., Proc. Applied Power Electronics and Expositions (IEEE-APEC), p. 432-439 (2014)
[3] N. Wang et al., J. Appl. Phys., 111, 07E732 (2012).
[4] N. Sturcken et al., ISSCC, 48, 244 (2013).
[5] K. Tien et al., in VLSI Technology (VLSI technology), 2015 Symposium on, Kyoto, 2015,
pp.C192-C193.
[6] D. S. Gardner et al., J. Appl. Phys., 103, 07E927 (2008).

Figure 1