Cu Pillar Wafer Pretreatment for Enhancing Wettability and Cleaning Cu Seed Layer
Authors: Park SooWoong , Kim Myung Jun , Kim Jae Jeong 
Published: December 2024

Semiconductor packaging serves the dual purpose of shielding semiconductor devices from external elements and facilitating electrical connections between chips and substrates. This intricate process, integral to transforming semiconductor devices into fully functional products, directly impacts the stability, reliability, and performance of electronic devices. With the semiconductor industry grappling with the physical constraints of miniaturization in recent years, the significance of packaging technology has surged. Modern packaging focuses not only on safeguarding devices but also on efficiently establishing electrical connectivity between chips and substrates or among different chips, transcending its conventional role.
In semiconductor packaging, the establishment of interconnections holds paramount importance in enabling electrical pathways between internal and external components of semiconductor devices. Various interconnection methods, including Redistribution Layers (RDL), Through Silicon Vias (TSV), microbumps, and microvias, are employed, linking different layers or integrating multiple chips into complex three-dimensional configurations. As the demand for higher integrity mounts, the density of interconnections within semiconductor packages undergoes a notable surge, necessitating structural adaptations in these connections. Notably, the adoption of copper pillars with solder caps has supplanted conventional bonding techniques reliant on solder balls to enhance performance. This transition stems from the risks associated with traditional solder balls, such as potential damage to component chips due to their high melting temperatures. In contrast, copper pillars with solder caps offer superior electrical conductivity while mitigating the drawbacks inherent in solder balls.
In contrast to methods like Damascene and TSV processes, the formation of copper micro pillars involves infusing copper into via holes created within a photoresist (PR) layer. However, PR patterning may inadvertently introduce organic impurities that hinder the adhesion of the copper seed layer. Moreover, PR exhibits relative hydrophobicity compared to metallic copper, facilitating air entrapment within PR vias. These challenges can lead to irregularities in copper electrodeposition and the formation of defects within copper pillars. Additionally, organic residues at the interface between the copper seed layer and the pillars can compromise their mechanical and electrical reliability while elevating electrical resistance. Consequently, post-treatment measures following PR patterning are imperative to optimize the copper electrodeposition process.
This presentation introduces pre-treatment procedures preceding significant copper electrodeposition to ensure the attainment of flawless copper pillars. Through this study, three distinct pre-treatment methods were explored to enhance the stacking properties of PR-patterned wafers, eliminate organic impurities from the copper seed layer, and regulate the hydrophobic nature of the PR layer while eradicating copper surface oxides. By fine-tuning parameters and evaluating the quality of copper electrodeposition resulting from these pre-treatments, an optimal pre-treatment protocol for achieving defect-free copper pillars is proposed.

Figure 1