bluuebunny/crossref_metadata_2025_split huggingface dataset:
Comparison of Cu-Sn Compound Formation Between Snag and Pure Sn Solder Bumps by EBSD
Authors: Lee Ui-Hyoung , Lee Hyo-Jong , Kim Sang-Hyuk , Park Chae-Min , Shin Han Kyun , Bae Jong-yong , Won Jaihyung 
Published: February 2020

Anisotropic behavior of Sn based solder during electromigration has been studied by many researchers, and it is very important to control the microstructure for more reliable bump joints[1]. Here, we prepared various SnAg bumps with different Ag concentrations including pure Sn[2]. Unary electroplating has various advantages such as easy handling bath, negligible bump composition and maintaining equipment with securing about environmental health and safety issue.
Figure 1 shows our preliminary experiments for the cross-sectional EBSD and EDS measurement of Cu pillar with pure Sn bump, and it is reflowed at 235°C for 6 min. In this study, we will report comparison of Sn microstructures according to various Ag inclusions by using cross-sectional EBSD(electron backscattered diffraction) analysis and EDS(energy dispersive spectroscopy) measurement. We carried out multiple reflows at various atmosphere how this impact IMC(intermetallic compound) growth along with microstructures. Through this crystallographic aspect approach, we will present optimum condition for resistance of electro migration and void formation.
[1] Yiwei Wang, Kuan H. Lu, Vikas Gupta, Leon Stiborek, Dwayne Shirley, Seung-Hyun Chae, Jay Im, Paul S. Ho, J. Mater. Res., 27, 1131 (2008)
[2] Ui-Hyoung Lee, Moongi Cho, Woojin Choi, Ha-Young You, Jinho Choi and Jaihyung Won, 224th ECS meeting, San Francisco, Oct. (2013)
Nanomechanical Properties of Standard and Strained SOI Films Fabricated by Wafer Bonding and Layer Splitting
Authors: Mamun M A , Zhang Kai , Baumgart Helmut , Elmustafa A A 
Published: February 2020

High demands for improved performance, better power consumption, and miniaturized devices prompted the migration to SOI technology. SOI fabrication process helps in achieving greater performance and offers less power consumption compared to the Bulk Si Process. In SOI fabrication technology, transistors are built on a Si layer grown on SiO2 (145 nm) insulating layer. The SOI is fabricated using the SMART CUT wafer bonding and layer splitting technology. The strained Si on insulator (sSOI) technology has recently been developed for high mobility channel devices [1-3]. Biaxial tensile strained Si layers grown on SiGe have attracted great attention for high performance CMOS devices. Strain engineering for mobility enhancement is an attractive option to improve CMOS device performance by introducing lattice strain into the Si channel. Epitaxial Si1-xGex and most recently Ge-free bi-axially strained sSOI are among the leading candidates for higher mobility channel material.
In this paper, we have analyzed how the fabrication of very thin single crystal Si device films by wafer bonding and SMART CUTTM film exfoliation technique is affecting their nanomechanical properties in comparison to bulk Si. Although both the handle wafer and the bonded thin device layer are single crystal Si, it turns out that their nanomechanical properties differ considerably. Using nanoindentation, we measured the properties of (SOI-88nm) and bi-axially tensile strained Silicon-on-Insulator (sSOI 15, 70, and 100 nm) and benchmarked the results against bulk Si.
The results of Figure 1 indicate that the hardness of these films vary significantly. The field emission scanning electron microscopy (FE-SEM) image of Figure 2 represents an sSOI film of 100 nm thick.

References

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Epitaxial Growth and Layer Transfer of InP through Electrochemically Etched and Annealed Porous Buried Layers
Authors: Chen Douglas , Kou Xiaolu , Sareminaeini Sahar , Goorsky M. S. 
Published: February 2020

Heterogeneous material integration, especially for III-V semiconductors, has enabled more possibilities in designing optoelectronic and electronic devices, and the ability to exfoliate the bonded devices layers and reuse the expensive substrates makes it economically advantageous. In our case, we propose a method using easily fractured porous layer to transfer an InP thin film from an InP substrate to an alternate substrate; e.g., glass or a flexible structure such as PDMS. Here, we demonstrate the formation of such a porous InP layer which exhibits a surface that is nearly fully dense as well as the ability to grow InP overlayers with low (< 106 cm-2) threading dislocation density. Also, we were able to transfer large area (> 1 cm2) InP layers onto PDMS substrates and glass slides.
In our studies on (001) InP, we have demonstrated that the pore formation can be controlled as a function of depth during electrochemical etching. For as-etched porous layers, AFM scans on a 40 X 40 μm2 area show the lowest surface r.m.s. less than 40 Å despite of the pore features. In order to achieve both high-quality epitaxial growth and facile layer fracture, a dual porous layer structure with a more porous (mechanically weaker) under-layer was designed and fabricated by either adjusting the etching current density or changing the switching electrolyte concentration.
The structures were annealed to understand the morphological evolution of the pore structure and to test the structural stability under simulated epitaxial growth condition. Under N2-purged environments, we observed that the surface remains stable (no change in surface pore morphology) with even slight improvement on roughness up to 550 °C and the layer maintained its porous structure at 650 °C. Large voids were observed after annealing at the interface between the high porosity buried layer and substrate, which is consistent with the ease by which it is to remove top layers from the substrate after annealing. Epitaxial layers were grown about 2 μm thick on porous surfaces with different porosities and both a cross-section TEM sample and a plan-view sample (> 35 μm2) were used to characterize the epitaxial growth. Since no observable threading dislocations were found in the plan-view sample, it sets a limit on the threading dislocation density in the mid-106 cm-2 range.
Samples with dual porous layers were bonded to flexible PDMS substrates and easily peeled off due to the fracture at the high porosity layer. Another set of samples were bonded to glass slides with epoxy glue and the fractured surface was characterized under SEM.
Chemical Mechanical Polishing of III-V Materials for Wafer Bonding Applications
Authors: McKay Jeffrey , Goorsky M. S. , Chen Douglas , Sareminaeini Sahar 
Published: February 2020

ABSTRACT
Wafer bonding of III-V cells offers opportunities to integrate materials with different bandgaps and different lattice parameters without forming high defect densities. However, growth conditions that produce the best cells do not necessarily produce epitaxial layer surfaces that are suitable for wafer bonding. The chemical mechanical polishing of III-V materials including GaAs, InP, InAs, and alloy layers used in high efficiency III-V solar cell structures is investigated with sodium hypochlorite and citric acid solutions. It is found that the surfaces can be polished to below 0.5 nm RMS surface roughness without the induction of crystalline damage using similar abrasive-free polishing solutions for all the materials with controlled polishing rates of 10 nm / min. The low removal rate is key for applications that include epitaxial layers that must be subsequently polished without l=excessive loss of material. The actual composition of the slurry is adjusted for the particular alloy composition. A balance between reduced sub-surface mechanical damage and smooth surface morphology is obtained by adjusting the amount of citric acid similar to Br-methanol polishing. However, the damage-free planarization in these cases may be aided by an oxide formation as predicted by Pourbaix diagrams. Subsequent bonding suing sulfur passivation on the CMP surface shows excellent electrical characteristics with low resistivity as well as high strength bonding after annealing at 400 °C. Additionally, triple axis x-ray diffraction is found to be an extremely sensitive, non-destructive method for evaluating damage induced by the CMP process.
Invited: Wafer-Bonding for MEMS – Status and Trends
Authors: Hausner Ralf 
Published: February 2020

The current sensor portfolio at Bosch is covering a large variety of different MEMS-based sensor products for automotive and consumer applications. Examples for automotive applications are pressure sensors for engine control, side impact detection and inertial sensors for airbag systems, navigation and vehicle-dynamics control (ESP). Examples for consumer applications are inertial sensors for gaming, freefall detection in laptops, switching in mobile-phones and pressure sensors used as altimeter, barometer and indoor navigation. Among the different wafer bonding techniques for wafer-level packaging that are shown in figure 1, anodic bonding, glass-frit and eutectic bonding are state-of the-art for MEMS sensors and the metallic bonding processes thermo-compression and solid-liquid interdiffusion (SLID) bonding have a high potential for future applications.
The basic features that wafer bonding technologies for MEMS must fulfil for a successful wafer-level packaging process are hermeticity, high bond strength and high temperature stability. Glass-frit and anodic bonding are well and long-term established standard technologies used for hermetic packaging of MEMS on wafer-level. But both technologies require comparatively large chip sizes that are not compatible with the requirements for miniaturization and cost reduction of new consumer sensors. Therefore metallic bonding processes like eutectic bonding with aluminium-germanium were used for new consumer sensors. Typically, the bond frame size with the eutectic bond can be reduced by a factor of 2 in combination with a frame that stops the liquid eutectic material in lateral extent. With eutectic bonding very small chip sizes are possible resulting in shrinking the size of Bosch accelerometers as shown in figure 2. One step further is the realization of hermetic encapsulation and electrical interconnection, if an ASIC wafer serves as a functionalized cap. Cu-Cu thermo-compression and Cu / Sn SLID bonding are promising techniques that are of high interest for MEMS products of the future.
The wafer bonding processes used and under development at Bosch, examples, advantages, disadvantages and challenges will be described.
Figure 1: Overview of waferbonding technologies.
Figure 2: Shrinking the chip-size for smaller accelerometers was promoted by the change from glass-frit to eutectic wafer bonding.
Detection of Ge and Si Intermixing in Ge/Si Using Multiwavelength Micro-Raman Spectroscopy
Authors: Yoo Woo Sik , Kang Kitaek , Ueda Takeshi , Ishigaki Toshikazu , Nishigaki Hiroshi , Hasuike Noriyuki , Harima Hiroshi , Yoshimoto Masahiro , Tan Chuan Seng 
Published: February 2020

To meet various physical property requirements of materials for advanced application specific devices, combinations of Si/Ge, Ge/Si, Si1-xGex/Si are frequently introduced in the device fabrication process. Epitaxy, condensation and annealing processes are commonly used. Since a small variation in composition, strain and crystallinity can result in reduced device performance or failure, the composition, strain and crystallinity must be carefully monitored and controlled throughout the manufacturing process.
In this study, we report the detection of Ge and Si intermixing in epitaxially grown Ge/Si after successive thermal anneals using multiwavelength Raman spectroscopy. We have studied dependence of Ge and Si intermixing on annealing temperature and Raman on excitation wavelength. Very strong excitation wavelength and film structure dependence of signal-to-noise (S/N) ratio of measurements was observed. Suitable excitation wavelengths must be chosen to properly detect and characterize Si and Ge intermixing, based on the stacking order of epitaxial films and thicknesses.
Figure 1 shows 514.5nm excited Raman spectra from reference Si, reference Ge and epitaxially grown Ge/Si wafers before and after thermal annealing. As grown Ge/Si wafers showed very distinct Ge and Si Raman peaks. Si and Ge intermixing was found in one annealing condition. Ge epitaxial was converted to Si1-xGexafter annealing.
S/N ratio of measurements and their dependence on excitation wavelength and film structure dependence will be discussed. Excitation wavelength selection guidelines will be proposed.
Paintable Thermoelectric Materials from Polymer Blends of Exfoliated 2D Nanosheets
Authors: Carroll Elaine , Buckley Darragh , Collins Gillian , O'Dwyer Colm 
Published: February 2020

In bulk form the thermoelectric material bismuth telluride (Bi2Te3) has a high figure of merit (ZT) at room temperature. When bulk Bi2Te3 is exfoliated to smaller dimensions, such as its 2D form (nanosheets), its thermoelectric effects are improved by reduction in thermal conductivity due to phonon confinement and scattering, thus increasing the ZT. The difficulty involved in incorporating nanosheets into energy harvesting systems motivated the search for a form of Bi2Te3 that retains the high ZT apparent at the nanoscale with the capability of being deposited or painted onto device infrastructures.
This work highlights a method whereby solvent exfoliation of Bi2Te3 into solution-dispersible 2D nanosheets can form a practical thin film that can be distributed across a surface. Optical transmission measurements quantify the relationship between efficient and stable exfoliation and the reduction in optical density. Optimized exfoliated suspension are also shown to form smooth, uniform blends when mixed with poly ethylene glycol and other polymers to produce a paintable Bi2Te3film that can be applied to surfaces using an innovative painting technique.
Atomic force microscopy, transmission electron spectroscopy, Raman spectroscopy and scanning electron spectroscopy are used to examine the structure of the 2D nanosheets and the highly reproducible Bi2Te3 thin films. Electrical transport studies show that the films have conductive pathways over a range of surfaces and various structural formations, linking the conductivity to the percolating conduction through the nanosheet ensemble. The combination of the facile preparation method and the scope for diverse surface coating as a cohesive and conductive thin film offers a methods for integration with heat producing devices for energy harvesting applications.
References

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B. Poudel, Q. Hao, Y. Ma, Y. Lan, A. Minnich, B. Yu, X. Yan, D. Wang, A. Muto, D. Vashaee, X. Chen, J. Liu, M. S. Dresselhaus, G. Chen and Z. Ren, Science, 320, 634 (2008).

M. Saleemi, M. S. Toprak, S. Li, M. Johnsson and M. Muhammed, Journal of Materials Chemistry, 22, 725 (2012).

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Graded Index Transparent Conducting Materials with Enhanced Optical Functionality
Authors: O'Dwyer Colm 
Published: February 2020

Transparent conducting oxides (TCO) have been extensively used in various technologically important applications including solar cells, flat panel displays, antireflective coatings, (organic)light emitting diodes and many other uses as advanced optical materials. Nanoporous and nanostructured films, assemblies and arrangements are important from an applied point of view in microelectronics, photonics and optical materials.
The ability to minimize reflection, control light output and use contrast and variation of the refractive index to modify photonic characteristics can provide routes to enhanced photonic crystal devices, omnidirectional reflectors, antireflection coatings and broadband absorbing materials.
This work demonstrates very high quality epitaxially grown (MBE) indium oxide, and indium tin oxide nanostructures and nanowires that are defect free and grown using homogeneous ITO seeds from glass or semiconducting surfaces. These branched and graded porosity layers grown directly on LEDs, glass coatings and other devices are shown to significantly enhance transparency or absorbance, depending on the visible wavelength range of interest and suppress Fresnel reflections for antireflection coatings. The benefit of controlling optical properties of nanoporous transparency conducting materials are shown for SiGe MQW LEDs, transparent Li-ion battery electrodes, antireflection coatings, and selective frequency absorbers across the visible range, and also demonstrates control over IR transmission without adversely affecting electronic conductivity.
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M. Osiak, W. Khunsin, E. Armstrong, T. Kennedy, C. M. S. Torres, K. M. Ryan and C. O'Dwyer, Nanotechnology, 24, 065401 (2013).

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Synthesis and Characterization of CuO Nanotubes (NTs) Formed By Anodization Sonoelectrochemical
Authors: Grez Paula Carolina , Ballesteros Luis Alberto , Celedón Carlos Eduardo , Schrebler Ricardo Silvio 
Published: February 2020

The CuO is an important semiconductor material because this presents a narrow bandgap value (~1.2 – 1.7 eV), p-type conductivity, low toxicity and abundance in nature. From comparison of the photoelectrochemical behavior between CuO and others semiconductor, it is concluded that this oxide is sensible to visible radiation whereas others, more widely used such as; TiO2, ZnO, which absorb in UV region.
Despite the above, the copper oxide has a low diffusion rate of charge carriers. Therefore, new synthesis routes leading to a nanostructured oxide is required, so that the photogenerated electrons are accumulated in the vicinity of the surface. This is to facilitate the transfer process of charge per on the recombination.
This report shows the results concerning the preparation sonoelectrochemical of CuO nanotubes (NTs). Synthesis of CuO NTs is carried out on a copper (Cu) foil in organic media (x% water in ethylene glycol + 0.5 wt % CuC2O4) using the electrochemical anodization method at a constant room temperature. The anodization is carried out for 10 min at an applied potential of 25 V. Cu foil acts as anode and electrode of carbon (C) acts as cathode. The anodized samples are properly washed with distilled water, to remove the occluded ions, and dried in a furnace.
The CuO NTs were characterized by sweep electronic microscopy (SEM), energy dispersive X-ray analysis (EDXA) and Raman spectroscopy.
The micrographs show an array of nanotubes on the substrate. The composition of the nanotubes immediately formed consisted mainly of copper, when the synthesis was conducted in a solution with a higher % of water. However, when the samples were heat treated in oxygen atmosphere, an array of CuO NTs was obtained.
Furthermore, these samples were characterized by Photoelectrochemical Studies.

Acknowledgment

The financial support of Fondecyt-Chile (Project N° 1140963) and DI-PUCV (Projects N° 037.305/2013) is gratefully acknowledged by the authors.
Simulation of the Cell Electrofusion Chip
Authors: Han Xianwei , Yang Jun , Hu Ning , Liao Yan-jian 
Published: February 2020

The process of cell electrofusion including cell alignment, cell electroporation cell electrofusion. Cell manipulation mainly related to the electric field gradient and electroporation is concerned with the intensity of the electric field. The first thing to consider in the design of Cell electrofusion chip is the control of the cell capacity , which depends on the intensity and distribution of the electric field, and this is associated with the applied voltage and the shape and distribution of the microelectrode. In the experiment, we can change the applied voltage, but the shape and distribution of the microelectrodes is hard to change. In order to improve the efficiency of the experiment, the optimum distribution and the size of the microelectrode in the chip should be determined before the experiment. Using COMSOL Multiphysics software to model and simulate the cell electrofusion chip to provide theoretical guidance for optimum chip design and experimental study late.
In this study, five different cell electrofusion chip are simulated. Using the finite element analysis method, combined with COMSOL simulation software, the electric field around the chip microelectrode is simulated and analyzed. Through the establishment of simulation model, to explore the influence on the internal electric field of the cell electrofusion chip be different parameters, including the distribution and spacing of microelectrode, , microelectrode length, width, and the size of the microstructure. Thus, best design parameters of chip microelectrode are achieved.
Design and Fabrication of Ag / AgCl Reference Electrode Based on PDMS Conductive Composite Material
Authors: Chen Li , Zheng Xiao-lin , Hu Ning , Jiang Fan , Zheng Fei , Luo Hong-yan , Yang Jun , Liao Yan-jian 
Published: February 2020

A vital part of any electrochemical sensing system is the reference electrode, which is a probe that is capable of measuring the potential on the solution side of an electrochemical interface. Ag/Agcl reference electrode is one kind of the most widely used among them. Common reference electrode is individually packaged and its volume is relatively large, which isn’t appropriate for microfludic systems. In microfluidic chips, electrochemical measurement is always challenging to realize, such as real-time monitoring of pH in micro-reactors.
In this paper, we introduce a kind of Ag / AgCl reference electrode in microchips based on PDMS-based conductive composites. This conductive composite of good electrical conductivity was synthesized by PDMS and silver powders via uniformly mixing. Two chloride methods, electrolysis and chemical immersion, were selected to the sample compared with pure silver wire as a reference. Packaging thin film was fabricated by mixing agar with saturated Kcl gel. A three-electrode system was used to measure the potential of Ag/Agcl reference electrode.
SEM pictures showed the surface profile of the reference electrode clearly. Here we demonstrate that electrolytic process and chemical immersion method both have great influence on the electrode surface. Fluffy and rough morphology increased the contact area between reference electrode and solution so as to improve the adequacy and accuracy of measurement.