(Invited) Raman Thermography of β-Ga2­O3 Nanomembrane FETs on Diamond
Authors: Tadjer Marko J , Noh Jinhyun , Culbertson James C , Alajlouni Sami , Si Mengwei , Zhou Hong , Shakouri Ali , Ye Peide D 
Published: February 2020

Despite the extremely low thermal conductivity of Ga2O3, remarkable progress in device technology has been achieved in a very short time since commercial HVPE epilayers were first introduced by Novel Crystal Technology, Japan. For example, Schottky barrier diodes with a forward current of 2 A were recently demonstrated, and thicker, low-doped epi has pushed breakdown voltage beyond 2 kV [1, 2]. Recent demonstrations of Raman thermography in Ga2O3 transistors, however, have proven that a heat spreading solution must be developed in order to realize the potential of Ga2O3 for high power operation [3]. As all devices eventually become thermally limited, effective heat dissipation will also assist in improving reliability and eventual commercialization of Ga2O3 devices. A number of approaches have been devised for GaN HEMTs in the past, where heat generated by the 2DEG under high electric field near the gate can push device temperatures above GaN reliability limits [4, 5]. In this work, we show for the first time that a reasonable operating temperature can be achieved in a Ga2O3 device at a practical power density. While wafer-scale thermal management solutions for Ga2O3 are still being developed, we have exploited the natural (100) cleave plane of Ga2O3 to mechanically exfoliate a highly-doped Ga2O3 membrane onto an insulating single-crystalline CVD diamond substrate and subsequently fabricate a Ga2O3-channel FET using standard electron-beam lithography techniques. Thermal characterization in the transistor channel was performed using a Raman thermography setup by first calibrating the Raman shift of the 169 cm-1 line as a function of temperature on a thermal chuck. This phonon line was chosen as its temperature dependent shift is relatively linear [6]. Independent measurements of the Au contact temperature using thermoreflectance imaging and modeling of the device produced a good agreement with the data [7, 8]. The combination of a thin, highly Sn-doped (2.7x1018 cm-3) Ga2O3 channel, high quality ALD Al2O3 gate dielectric, high thermal conductivity diamond substrate, and a very high critical field for both the channel and substrate (8 MV/cm for Ga2O3, 10 MV/cm for diamond) allowed for a high current density to be maintained under high drain bias. As a result, a maximum DC power density of about 60 W/mm and channel temperature of about 160 °C were simultaneously obtained before destructive failure occurred in the Ga2O3 FET channel. To the authors’ best knowledge, this is the highest power density demonstrated by any semiconductor device.
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