Design and Verification of an a-Igzo Tfts-Based Neuron Circuit with Threshold Voltage Variation Compensation
Authors: Yun Yumin , Park Junhyeong , Kang Kyeong-Soo , Park Ji-Hwan , Park Chanjin , Lee Soo-Yeon 
Published: December 2024

In this work, we implement an a-IGZO-based analog neuron circuit, which can prevent network accuracy loss due to fabrication fluctuation and bias stress during circuit operation. An a-IGZO TFT has extremely low leakage current, moderate mobility, and large-area deposition, making it well-suited for hardware-based neuromorphic systems [1, 2]. The neuron circuit collects input signals from synapses and generates an output based on an activation function. The type and uniformity of the activation functions significantly affect the classification accuracy of ANNs [3]. Due to its rapid convergence and simplicity, the rectified linear unit (ReLU) is the most common activation function [4]. However, when implementing the ReLU function in an analog neuron circuit, it can be susceptible to critical distortion caused by transistor variations, such as VTH variations.

To compensate for the transistor variation and achieve a uniform activation function, the proposed neuron circuit includes two capacitors for VTH compensation and integration, respectively. As shown in Fig. 1, the capacitor for VTH compensation (CVTH) detects and stores the VTH of an output TFT which triggers the output voltage of the neuron circuit. Another capacitor (Cmem) accumulates current from synapses in the previous layer and stores membrane voltage. Through the utilization of a-IGZO TFTs, we can minimize the voltage loss in both capacitors during operation. We validate the operation of the proposed circuit through HSPICE, and the simulation results present a highly accurate activation function even under VTH variations in the output transistor.
In an implementation of the neuromorphic system consisting of arrays of neurons and synapses, the connection between neurons and synapses and its loading effect in the transient waveform are crucial considerations [5]. We construct an appropriate load model emulating the synapse array RC load under the oscilloscope measurement. The load connected to the source node of the output transistor influences the gradient of the ReLU functions. We fabricate the a-IGZO-based neuron circuit and analyze its specific operations, including VTH compensation of the output transistor and integration of synapse currents. Then, we compare the simulation and measurement results and optimize the circuit operation according to the characteristics of the RC load. This result suggests that the proposed VTH compensation method can be an effective solution for achieving precise and reliable neuron circuits in large-scale neuromorphic systems.

Reference

[1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, Nature, vol. 432, no. 7016, pp. 488–492, 2004.
[2] T. Kamiya, K. Nomura and H. Hosono, Journal of Display Technology, vol. 5, no. 7, pp. 273-288, 2009.
[3] A. D. Rasamoelina, F. Adjailia, and P. Sinčák, IEEE 18th World Symposium on Applied Machine Intelligence and Informatics, pp. 281-286, 2020.
[4] S. Oh, Y. Shi, J. Del Valle, P. Salev, Y.Lu, Z. Huang, Y. Kalcheim, I. K. Schuller and D. Kuzum, Nature Nanotechnology, vol. 16, pp. 680-687, 2021.
[5] M. Milev and M. Hristov, IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1187-1200, 2003.
Fig 1. The schematic of the proposed neuron circuit with measurement setup and synapse array RC load

Figure 1