(Invited) Gate Stacks for Silicon, Silicon Germanium, and III-V Channel MOSFETs
Authors: Frank Martin M. , Zhu Yu , Bedell Stephen W. , Ando Takashi , Narayanan Vijay 
Published: February 2020

High-k gate dielectrics such as HfO2 and metal gate electrodes such as TiN have been deployed across a wide range of CMOS logic products in both the low-power (e.g., mobile) and the high-performance (e.g., server) space. Available device geometries include planar field-effect transistors on bulk Si, on partially depleted silicon-on-insulator (PDSOI), and on fully depleted SOI (FDSOI), as well as FinFETs. During the decade-long effort leading up to successful high-k/metal gate (HKMG) implementation, much has been learnt about the fundamental materials science underlying such gate stacks. Yet, research continues in order to ensure continued circuit density and performance scaling.
After reviewing the gate-first and gate-last (or replacement gate) approaches to HKMG implementation, I will discuss device challenges that can be resolved by materials engineering on the atomic scale. A prime example is the threshold voltage (Vt) challenge, which is caused by charged oxygen vacancies in hafnium-based gate dielectrics formed at elevated temperatures, thus increasing pFET Vt. These vacancies can be filled by lateral or top-down oxidation. As an alternative, additional Vt-setting techniques can be employed, such as metal oxide capping layers (e.g., Al2O3 or La2O3 for pFET and nFET, respectively) that form permanent electrical dipoles, or SiGe channels (cSiGe) which modulate the band offsets while additionally providing a welcome hole mobility boost. A second example is continued equivalent oxide thickness (EOT) scaling. We have developed the approach of metal-gate-induced remote oxygen scavenging, which results in a thinning of the SiO2 layer at the high-k/channel interface. In this way, EOT of 0.4-0.5 nm can be reached for both nFET and pFET. I will in particular discuss our recent results on aggressive cSiGe pFET scaling (Fig. 1), including the dependence of hole mobility (Fig. 2) and of negative bias temperature instability (NBTI) reliability on EOT and thus on interfacial SiO2thickness [1].
In the second part of my talk, I will show that HKMG not only provides the well-known gate-length scaling benefit through improved electrostatics, but it can also directly enable aggressive device pitch and density scaling through borderless (semi-self-aligned) source-drain (S/D) contacts [2]. Conventional gate-first high-k/metal gate (HKMG) CMOS technologies employ metal-inserted poly-Si stacks (MIPS) such as a-Si/TiN, where the amorphous Si serves as a precursor for low-sheet-resistance (Rs) self-aligned NiSi on the gates and as an oxygen barrier preventing high-k/Si interfacial SiO2 growth. A full metal gate (FMG, Fig. 3), instead containing a deposited low-Rs metal layer, can be encapsulated in a dielectric resistant to the S/D contact etch, resulting in borderless contacts. We have developed two FMG electrodes based on TiSix/TiN and W/TaMN/TiN (M = oxygen scavenging metal). With both FMG on Hf-based gate dielectrics, Si channel nFET and SiGe channel pFET parametrics and reliability similar to those of poly-Si/TiN control devices are achieved, with good EOT scalability [3,4].
Finally, I will provide an outlook on high-k gate dielectrics for high-mobility III-V channel materials. Specifically, I will compare three interface approaches to InGaAs channel nFET gate stack formation. The first is based on direct high-k deposition onto InGaAs, while the other two approaches rely on the insertion of an amorphous Si or an epitaxial InP capping layer to passivate the InGaAs. The impact of such caps on interface trap density and scalability will be discussed.
[1] M.M. Frank et al., ECS Solid State Lett. 2, N8 (2013).
[2] S.-C. Seo, et al., VLSI, p. 36 (2011).
[3] M. M. Frank et al., as discussed at SISC 2011.
[4] M. M. Frank et al., as discussed at SISC 2013.
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