Comparison of Physical and Electrical Characteristics of Memory Devices with NiO2 Charge Trapping Layer
Authors: Mahanty Rama Krushna , Kao Chyuan Haur , Lin Chun-Fu , Su Yen Lin 
Published: February 2020

In this study, a metal-oxide-high-k-oxide-silicon (MOHOS)-type nonvolatile memory structure using a high-k NiO2 film as the charge trapping layer is reported for nonvolatile memory application. We employ Rapid Thermal Annealing (RTA) to improve overall memory characteristics of the devices. We use structural and electrical analysis to study the performance of the devices. The crystalline structures and morphological features of NiO2 films were studied using atomic force microscopy and x-ray diffraction measurements.
The fabrication of the MOHOS memory structure using NiO2 charge trapping layer is started with single-crystal 4-inch n-type silicon (100) wafers were cleaned using a standard RCA process. First, a thin 3nm SiO2 was thermally grown by dry oxidation furnace system at 850°C. Then, a 15 nm NiO2 trapping layer was deposited by RF sputtering with pure nickel target (99.99% pure) with argon (20 sccm) and oxygen (5 sccm) mixture ambient. Next, the wafers were annealed to form NiO2 charge trapping layer at different temperatures by rapid thermal annealing (RTA) in nitrogen ambient for 30s at 600°C, 700°C,800°C and 900°C. Then a 20nm SiO2 film was deposited as blocking oxide layer by plasma enhanced chemical vapor deposition (PECVD). After deposition blocking oxide layer, the sample was deposited 300nm aluminium (Al) film by thermal evaporator followed by patterning the gate by lithography and wet etching. Finally, a 300nm thick Al was deposited by thermal evaporator on the backside to form metal contact.
Compared to the as deposited film, NiO2 film annealed at 900°C exhibited superior memory characteristics, such as a higher window of capacitance-voltage hysteresis loop, a larger flat-band voltage shift, and a lower charge loss rate at room temperature. These improvements might be attributed to the well-crystallized structure formation in the NiO2 with high trap density. Further, program/erase speed of the MOHOS structure has increased owing to larger flat-band shift. Samples with higher temperature annealing shows better charge retention (11%) owing to the reduction of local defects. We also studied charge retention at different temperature of 55°C and 85°C. We also utilize Arrhenius plots for shallow trap and deep trap fitting and activation energy of 0.18eV are extracted from the straight line. The endurance of the NiO2 MOHOS structure has measured using programming voltage of 13V for 1s and erasing voltage of -18V for 1s. NiO2 sample with 900°C RTA treatment can sustain the memory window of 2.4 V after 104 program/erase cycles. High temperature annealing improves the crystalline structure and strengthens the structure of trapping layer and resist the defect that produced during repeated program and erase cycle.
In this study, the memory device NiO2 trapping layer with 20nm blocked oxide and annealed at 900℃ can improve memory device performance, including larger C-V hysteresis, better data retention, better endurance and smaller charge loss of about 11% at 25°C. Therefore, NiO2 trapping layer with proper annealing is very promising for MOHOS nonvolatile memory applications