Spatial Revelations of Chemical and Electrochemical Kinetics into Defect Generations during Semiconductor Processing
Authors: Sheng Lieyi , Pan Wei 
Published: December 2020

Semiconductor processing is an extreme challenge due to the defect generations at a microscopic scale down to nanometers in size. Over the past several decades, the industry has been constantly experiencing dramatically increased complexities in manufacturing. A production flow is often made up of hundreds of steps and involves a variety of complicated equipment and chemicals. In addition to the common three states (i.e., solid, liquid, gas), plasma has also been extensively used in many steps involved in clean, deposition, and etch. Meanwhile, a lot of incidental events and sources, such as contaminations and problem tools, can readily occur from time to time. The list goes on and on. Consequently, some of these detrimental factors and variances can generate various defects in degrading or even crashing production lines.
When a defectivity issue occurs, a failure analysis (FA) is typically initiated for identifying the nature of defects and where and how they are embedded into the device stack. To start with, a voltage or current has to be applied to excite the defective spot for detecting a localized thermal or photonic signal. However, a small voltage application or current injection, even in nano-ampere, can easily destroy a microscopic defect. A subsequent cross-sectioning or delayering, even with great care, may miss the defect. Therefore, to nondestructively visualize defects has been a daunting task, and often concludes with a disappointment. Furthermore, the source or origin of an issue may need to be narrowed down by analyzing big data from many production lots and/or further confirmed by executing several designs of experiments (DOEs). All these steps towards root-cause clarification and process improvement can be time-consuming and costly. In addition, the process interactions among different steps can further weaken or cause inconsistencies to the correlations under extensive reviews.
Fifteen years ago, the novel concept of “Micro-View (on spots) ≈ Macro-View (on sites)” was first proposed by conceiving the transportation behavior of chemicals during spin cleaning (after L. Sheng et al., IRPS2006). Since that first success in promptly resolving a gate oxide integrity (GOI) crisis, we’ve been frequently searching for more instances of chemical and electrochemical kinetics being intricately tangled with wafer processing. As a result, we’ve gained broader insights by clarifying and resolving a range of intricate cases due to various defect generations.
The gate oxide layer, often representing the smallest feature in modern metal-oxide-semiconductor (MOS) technologies, is critically susceptible to a variety of defectivity issues. Many steps in the frontend-of-line (FEOL) processing, especially at cleaning operations with various wet chemicals, deteriorate the conditions on wafer surface, which later incur defects inside the gate oxide layer as well as along its bottom and top interfaces. Furthermore, various corrosions have also been observed in the backend-of-line (BEOL) metallization, such as for the bimetallic AlCu bonding pads. Driven by the built-in potential differences across semiconductor devices, galvanism is also a common mechanism, which, however, has been far less recognized as in typical alloy materials.
In this paper, the unique fundamentals of kinetic phenomena during semiconductor processing will be extensively reviewed for the first time. A comprehensive three-dimensional (3D) view provides the insights into chemical transportations along wafer surface and electrical cross-sections in device stack. In order to vividly illustrate the effectiveness of perceivably connecting these unique dynamics with critical defects generated, several case studies will be provided along complex process flows. Overall, these spatial revelations have made significant contributions to the solid technology development as well as the quality manufacturing of our most advanced high-voltage (HV) mixed-signal integrated circuit (IC) processes and products.