bluuebunny/crossref_metadata_2025_split huggingface dataset:
Failure Analysis of a Qualification Unit Injector for a Satellite Thruster
Authors: Lipschutz M. , Brannam R. , Nguyentat T. 
Published: December 2020

Abstract
This article details the results of a failure analysis performed on a Qualification Unit injector for a military satellite thrusters and explains that the failure was initially detected due to a shift in performance during qualification testing. Failure analysis involved non-destructive evaluation on the injector using micro-focus X-ray and scanning electron microscopy. Serial cross-sectional metallography was then performed, with each cross-section documented by optical microscopy and SEM. The failure analysis resulted in three main conclusions: (1) the root cause of the failure was attributed to multiple detonations in or around the damaged orifice; these detonations were likely caused by fuel and/or combustion products condensing in the orifice between pulses and then igniting during a subsequent pulse; (2) multiple damage mechanisms were identified in addition to the ZOT detonations; and (3) the material and platelet manufacturing process met all design parameters.
The Challenges of FIB Chip Repair and Debug Assistance in the 0.25μm Copper Interconnect Millennium
Authors: Herschbein S.B. , Fischer L.S. , Kane T.L. , Tenney M.P. , Shore A.D. 
Published: December 2020

Abstract
Copper will probably replace aluminum alloys as the interconnect metallurgy of choice for high performance semiconductor devices. This transition will challenge the suitability of established practices in focused ion beam (FIB) chip repair. A fundamental rethink in methodology, techniques, and process gases will be required to deal with the new metal films. This paper discusses the results of recent experiments in the areas of FIB exposure, cuts and connections to buried copper lines. While copper tends to mill faster than aluminum, etch rate variations due to grain structure tend to make reliable isolation cuts more difficult. The films also have been shown to suffer regrowth and surface reactions during long term storage following FIB exposure. Attempts at halogen gas assisted etch (GAE) mills result in undesirable removal characteristics, and in the case of bromine, the spontaneous destruction of all exposed copper in the immediate area. Resistance measurements and reliability of deposited tungsten connections to copper lines are also presented. In addition, the latest techniques developed for aluminum wiring isolation and device characterization are shown. These include 'cleanup' methods for achieving good circuit isolation without the extensive use of local oxide deposition, and the latest multilevel version of the FIB ‘wagon wheel’ for SRAM cell characterization. Also included is preliminary data from a custom built FIB chamber four manipulator prober module.
Non-Contact Probing of Integrated Circuits Using Electrostatic Force Sampling
Authors: Bridges G.E. , Thomson D.J. , Qi R. 
Published: December 2020

Abstract
We present a non-contact probing technique for measuring highfrequency voltage waveforms at the internal points of an operating integrated circuit. Internal circuit voltages are measured by sensing the local electrostatic force on a small micromachined probe that is held in close proximity to the circuit measurement point. The instrument currently has a 3GHz bandwidth and a capacitive loading on the test point of less than 1fF. The non-contact technique is capable of measuring signals on passivated interconnects
Mechanical/Plasma Decapsulation Method and Thermal Finite-Element Analysis Provide Explanation for SMB Zener Failures
Authors: Kime Kent , Reed Chuck , Di Silvestro Joe , Ruiz Ruth , Keeton Simon , Thome Gene P. 
Published: December 2020

Abstract
Failure analysis and finite-element analysis were used in conjunction to determine the cause of zener diode failures. A mechanical/plasma depot method was developed for the plastic-encapsulated SMB package and used to observe the presence of remelted extruded solder material on the die surface. That material provided a conductive path which manifested electrically as premature breakdown. Transient-thermal finite-element analysis was then used to show that a recent change of in-house surge test parameters could result in part temperatures during surge testing in excess of the solder melting temperature. These efforts lead to a respecification of the in-house surge test duration which resolved the problem.
Layout Overlay Techniques to Improve Failure Analysis
Authors: Burmer Christian , Görlich Siegfried , Pauthner Siegfried 
Published: December 2020

Abstract
New layout overlay technique has been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-ìm design rules, chemical mechanical polishing techniques (CMP) and autorouted design techniques. As the new technique is realized as an extension of a standard CAD-navigation software and as it makes use of standard image format "TIFF" for data input, which is available at all modern equipments for failure analysis, these technique can be applied to all modern failure analysis methods. Here examples are given for three areas of application: circuit modification using Focused Ion Beam (FIB), support of preparation for backside inspection and fault localization using emission microscopy.
Waveform Acquisition from the Backside of Silicon Using Electro-Optic Probing
Authors: Bruce Mike , Dabney Greg , McBride Shawn , Mulig Jason , Bruce Victoria , Bachand Charles , Kasapi Steven , Block Jeffrey A. 
Published: December 2020

Abstract
A new tool (Schlumberger IDS 2000) has become available for acquiring waveforms from C4 (also known as flip chip) packaged IC’s. The waveform acquisition technique is based on electro-optic sampling through the backside of silicon. After explaining the physics of electro-optic sampling, the technique is demonstrated through the backside of Si on a simple diode test structure and a flip chip microprocessor. Also, many of the issues and challenges with this tool are discussed.
Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy
Authors: Lim Soon , Bi Jian Hua , Goh Lian Choo , Neo Soh Ping , Tatti Sudhindra 
Published: December 2020

Abstract
The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.
In-Situ Use of an Optical Microscope for FIB Microsurgery of Planarized Devices
Authors: Wolpert Patrick J. , Lee Raymond A. 
Published: December 2020

Abstract
The extensive use of planarization in many of today's leading process technologies significantly reduces the effectiveness of FIB circuit modification and debugging. Planarization has played a significant role in the development of denser chips with increasingly smaller geometries. Fully planarized devices offer little or no surface features on which the FIB operator relies for orientation and alignment. These conditions lead to increased debug cycle times and decreased success rates using the FIB. Recent FIB tool advancements in the field of C4 (controlled-collapse chip connection) flip-chip packaged device modification and debug have also made it easier to work on highly planarized conventional wire-bond technology. The integration of an optical microscope with an infrared camera into the work chamber allows the operator to view the circuitry under the surface layer. This paper will offer several techniques for overcoming the challenges that planarized devices present by using this in-situ optical microscope. When properly implemented, these techniques can significantly improve the success rate and throughput time of device modification on highly planarized parts.
Optimizing Contact Resistance at a Resistor/Conductor Interface via Thin Film Microanalysis and Process Design of Experiments
Authors: Linn J.H. , Thompson T.K. , Shlepr M.G. 
Published: December 2020

Abstract
Electrical data from chromium-silicon-carbon (CrSiC) thin film resistors (tfr) consistently showed highly variable contact resistance (Rc) to the aluminum (Al) interconnect. Transmission electron microscopy data from CrSiC/Al interfaces exhibiting high Rc showed a conformal, amorphous layer sandwiched between the tfr and Al. Auger data from the tfr/Al interface showed this ‘crud’ layer to contain increased C, S, and SiOx. Auger data from CrSiC films on test wafers exposed to the process steps before Al deposition showed additional growth of the ‘crud’ layer after each photoresist (PR) operation. In addition, Rc variability was reduced on product wafers from split lots when 2x the normal PR strip time was used compared to the normal strip time. A Designed Experiment (DOE) to examine improving the removal of this ‘crud’ layer was run on product lots utilizing two factors: the standard strip and a two-step strip. Electrical results for both Rc and die yield were significantly improved using the two-step process. The variability of the Rc was also reduced.
Failure Analysis of Plastic Packaged GaAs and AlGaAs/GaAs LEDs
Authors: Mead Patricia F. , Burch Melody , McCluskey Patrick , Johnson F. G. 
Published: December 2020

Abstract
Failure and degradation mechanisms of plastic packaged LEDs that have been subjected to high levels of moisture, current bias, and elevated temperature conditions have been investigated and analyzed. The investigation included electrical characterization and a variety of failure analysis techniques including photoluminescence (PL), electroluminescence (EL), cathodoluminescence (CL), and environmental scanning electron microscopy (ESEM). Our results highlight the usefulness of simple screening techniques to monitor the quality of newly manufactured LED packages. Our results also indicate that for AlGaAs structures, degradation of the light output and electrical performance involves a complex interaction between temperature, relative humidity at the LED surface and voltage bias.
Integrated Circuit Device Repair Using FIB System: Tips, Tricks, and Strategies
Authors: Hooghan K. N. , Wills K. S. , Rodriguez P.A. , O’Connell S.J. 
Published: December 2020

Abstract
Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.
Current-Signature-Based Analysis of Complex Test Fails
Authors: Gattiker Anne E. , Nigh Phil , Maly Wojciech 
Published: December 2020

Abstract
This article provides an analysis of a class of failures observed during the SEMATECH-sponsored Test Methods Experiment. The analysis focuses on use of test-based failure analysis and IDDQ signature analysis to gain insight into the physical mechanisms underlying such subtle failures. In doing so, the analysis highlights techniques for understanding failure mechanisms using only tester data. In the experiment, multiple test methods were applied to a 0.45 micrometer effective channel length ASIC. Specifically, ICs that change test behavior from before to after burn-in are studied to understand the physical nature of the mechanism underlying their failure. Examples of the insights provided by the test-based analysis include identifying cases where there are multiple or complex defects and distinguishing cases where the defect type is likely to be a short versus an open and determining if the defect is marginal. These insights can be helpful for successful failure analysis.
Residual Photoresist Identified as Cause for Frequency-Dependent Signal-to-Noise Failure After Autoclave Stress Testing
Authors: McVeigh Martin J. 
Published: December 2020

Abstract
A case history is presented for the failure analysis of a 0.5u CMOS A/D converter in which high fallout occurred after autoclave stressing. The observed failure mode of degraded signal-to-noise distortion (SINAD) ratio (measured in dB) was found to affect devices within a specific bandwidth centered around 5MHz. From a circuit designer’s viewpoint, an explanation for this unique failure mode did not readily present itself. Yet, using straightforward failure analysis techniques, involving laser ablation of photoresist and selective etching of passivation, the specific failing circuit block was isolated. Crosssectional analysis, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) found evidence of residual photoresist at topography related voids in the nitride passivation layer. The photoresist reacts with moisture in the autoclave, resulting in increased capacitance at minimum-spaced top layer metal lines. This failure mechanism correlates with the observed maximum SINAD degradation around 5MHz: at this frequency the signals along the affected metal lines are at their maximum voltage swing. This failure mechanism is potentially an issue for any similar high-speed, high-resolution designs.
Application of the Infrared Microscope (IREM1) for Flip-Chip (C4) Failure Analysis
Authors: Zaplatin A. N. , Low F. J. , Seidel Steve , Rao Valluri R. , Loh T. H. 
Published: December 2020

Abstract
Today’s process technology requires ever-increasing number of metal layers to meet the power and layout needs of modern products. These advances have rendered many of the conventional fault isolation (FI) methods from the front side of the die obsolete. The flip-chip package not only brings about the need to localize defects at die level through the Si substrate, but also introduces the need to isolate new defects at the package level. Recently, an infrared (IR) emission microscope which utilizes the cryogenically cooled HgCdTe (MCT) imaging array having spectral response of 0.8μm- 2.5μm, for near IR emission detection was developed. This system supersedes the conventional CCD based emission microscope with a spectral response of 0.4 μm-1.1μm. Since spectral detection extends into the thermal spectral region, it also offers an added advantage of detecting thermal spots on the die and flip-chip package where liquid crystal hot spot detection method is not possible. This article is an account of the use of the Mercury-Cadmium- Telluride based IR detector for “real life” failures. The article will demonstrate key features of the system as well as several FI examples. Both emission and thermal detection modes will be discussed. The authors will present several problems, including melted die bumps and package copper trace shorts, that could not be detected through conventional failure analysis (FA) methods, such as liquid crystal or front side emission microscopy. The MCT detectors increased sensitivity and backside navigation capabilities coupled with backside die preparation has proven itself an indispensable FA tool in the high volume manufacturing environment.
Failure Analysis of CDM-ESD Damage in a GaAs RFIC
Authors: Poe Amy , Brockett Steve , Rubalcava Tony 
Published: December 2020

Abstract
The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.
The Use of TMAH to Etch Silicon and Expose Metal Bridging Failures
Authors: Morris Mark , Mohr James , Ortiz Esteban , Englebretson Steven 
Published: December 2020

Abstract
Determination of metal bridging failures on plastic encapsulated devices is difficult due to the metal etching effects that occur while removing many of the plastic mold compounds. Typically, the acids used to remove the encapsulation are corrosive to the metals that are found within the device. Thus, decapsulation can result in removal of the failure mechanism. Mechanical techniques are often not successful due to damage that results in destruction of the die and failure mechanism. This paper discusses a novel approach to these types of failures using a silicon etch and a backside evaluation. The desirable characteristics of the technique would be to remove the silicon and leave typical device metals unaffected. It would also be preferable that the device passivation and oxides not be etched so that the failure location is not disturbed. The use of Tetramethylammonium Hydroxide (TMAH), was found to fit these prerequisites. The technique was tested on clip attached Schottky diodes that exhibited resistive shorting. The use of the TMAH technique was successful at exposing thin solder bridges that extruded over the edge of the die resulting in failure.
Selective Au Etching in Au/Al Bonds in Current IC Technology
Authors: Vanzi M. , Serpe A. , Trogu E.F. , Deplano P. , Hartfield C. , Subido W. 
Published: December 2020

Abstract
A new Au etch, recently developed for selective Au etching on Ti/Pt/Au metallization of optoelectronic devices, has been tested on Au wires bonded on Al films. Contrary to theoretical expectations, Au wires are removed without Al damage, except for a very localized area around the bond interface. The role of the native Al oxide is discussed in preserving Al and allowing Au lift off.
Application of Scanning Acoustic Microscopy to Electric and Electronic Parts
Authors: Miyasaka C. , Tittmann B. R. 
Published: December 2020

Abstract
Ever since the invention of the scanning acoustic microscope (SAM), a key objective has been the enhancement of the resolution in an interior image. Thus, an acoustic lens that can form an interior image with a shear wave has been designed. The use of this lens gives benefits such as an increase of lateral resolution in the interior image, a reduction in background noise caused by surface roughness, and a reduction of spherical aberration. Significantly, with the current trend towards microminiaturization of microelectronic packages, acoustic microscopy with higher resolution and removal of surface roughness can play an important role in diagnostic examinations and failure analysis. In this paper, applications for the lens in microelectronic IC packages will be summarized.
Integrated Circuit SNR Improvement Using Dielectric Altering Compound, Laser Trim and FIB System
Authors: Dutt B.J. , Kroutch J.J. , Hooghan K.N. , Jenkins R.J. , Toth M.J. 
Published: December 2020

Abstract
Communication Signal Processors (CSP) did not have the Signal-to-noise ratio (SNR) performance expected. Significant differences were noticed between SNR values at wafer level and package testing. The analog section of the chip was suspected to be the culprit as the problem existed at the analog to digital conversion level. A Dielectric Altering Compound (DiAC) was chosen to simulate the packaged environment in decapsulated parts[1]. The DiAC was applied in and around the analog section, after application in other areas did not show the SNR degradation. The sampling capacitors in the A to D Converter section (ADC) were selectively coated with DiAC and laser trimmed to identify the offending circuit element. A signal trace running adjacent to the sampling caps, was isolated and suspected of coupling noise to the sampling caps. A FIB system was used to deposit a grounded metal shield that covered the suspect runner on a packaged part - subsequent testing showed no degradation. The above procedure was successful in isolating, verifying, and rectifying the SNR degradation. The SNR degradation was found on more than one code. The same procedure was used repeatedly on subsequent errant codes. Finally, a mask level fix on silicon achieved the desired SNR performance for all the codes.
Silicon Trenching Using Dry Etch Process for Backside FIB and Probing
Authors: Korchnoi Valentina , Fenigstein Amos , Barger Anastasia 
Published: December 2020

Abstract
The migration of microprocessor packaging from wire bond to flipchip technology in silicon "microsurgery" posed some challenges to on-chip circuit edit. The physical debug process through the backside silicon substrate was proposed as the common solution. The focus of this article is on step 2 of this process, namely the milling of large trenches over the edit area. Laser Chemical Etcher (LCE) was commonly used for this task. This article presents an alternative technique based on plasma dry etch process which consists of three steps: photolithography, plasma etching, and acoustic polishing. A detailed description of each step is provided, along with the details of experiments that were conducted for process optimization. The technique was successfully demonstrated in the preparation for backside FIB editing. However, the success rate of the proposed method is still lower than the LCE but this method can serve as a reliable backup process for the LCE.