bluuebunny/crossref_metadata_2025_split huggingface dataset:
Infra-Red Reflectance Microscopy (IRRM) for Daisy Chain Flip Chip Device Failure Analysis
Authors: Grilletto Carlo , Hsiung Steve , Komrowski Andrew , Soopikian John , Sullivan Daniel J.D. , Tan Kevan 
Published: December 2020

Abstract
This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.
SCM Application in Semiconductor Failure Analysis and Possible Solution for Well Inspection of Advanced Nanometer Process
Authors: Lin Coswin , Chao Chia-Hsing 
Published: December 2020

Abstract
Scanning capacitance microscopy (SCM) is a powerful technique that may readily be applied to semiconductor failure analysis yielding information on problems stemming from doping issues. This paper details the study of a current leakage failure and outlines the use of the SCM technique for shallow trench isolation applications. A two-step sample preparation technique involving firstly, Chemical Mechanical Polishing (CMP) followed by a wet etch, could improve the sample surface planarization allowing SCM inspection of the STI region.
Correction to 2003 Proceedings: ESD Failure Signature Differences in the Devices Core Logic and Protection Structures—A Case Study
Authors: Henry Leo G. 
Published: December 2020

Abstract
For certain programmable logic type devices, the electrical, morphological and failure location differences in the ESD signatures between ICC failures and I/O leakage failures have been identified. Based on these electrical, morphological and physical failure signature locations, this case study confirms that distinctions can be made between the signatures associated with the likely stress modes for pin combinations like I/O-to-Vss, I/O-to-Vcc, I/O-to-I/O, Vssto- Vcc and Vcc-to-Vss. This separation also facilitated the correct identification of core failures which are mostly due to the supply-to-supply pin combination stress, but in some cases are due to the pin-to-supply tests.
Quantitative Electrical Analysis of FIB Prepared Vias on BiCMOS and CMOS090 Designs
Authors: Domengès B. , Poirier P. 
Published: December 2020

Abstract
In this study, the resistance of FIB prepared vias was characterized by the Kelvin probe technique and their physical characteristics studied using cross-sectional analysis. Two domains of resistivity were isolated in relation to the ion beam current used for the deposition of the via metal (Pt). Also submicrometer vias were investigated on 4.2 µm deep metal lines of a BiCMOS aluminum based design and a CMOS 090 copper based one. It is shown that the controlling parameter is the shape and volume of the contact, and that the contact formation is favored by the amount of over-mill of the via into the metal line it will contact.
A Study of Low Leakage Failure Mechanism of X7R Multiple Layer Ceramic Capacitor (MLCC)
Authors: Wang Zhaofeng 
Published: December 2020

Abstract
This paper presents the result of a study of a particular failure mechanism of BaTiO3 MLCC (multiple layer ceramic capacitor). A unique technique of cross-section alternating with emission microscope analysis is developed to precisely locate the failure site for capacitors exhibiting low leakage current in μA range. Thermal Imaging Microscope, Photon Emission Microscope, SEM, STEM/EDS and TEM electron diffraction pattern are employed for the characterization of these low leakage failures. Evidence of high concentration impurities are detected in the dielectric layer of BaTiO3 grain boundaries as well as inside certain grains. TEM diffraction imaging at the failure site shows distinguishingly different diffraction patterns within the matrix of BaTiO3 crystal structure. The evidences point to a combination of impurities at grain boundaries and BaTiO3 crystal change induced by impurity as the failure mechanism.
Application of EDS Technique for OSP Film Thickness Measurement
Authors: Kongsubto Prong , Kongwudthiti Sirarat 
Published: December 2020

Abstract
Organic solderability preservatives (OSPs) pad is one of the pad finishing technologies where Cu pad is coated with a thin film of an organic material to protect Cu from oxidation during storage and many processes in IC manufacturing. Thickness of OSP film is a critical factor that we have to consider and control in order to achieve desirable joint strength. Until now, no non-destructive technique has been proposed to measure OSP thickness on substrate. This paper reports about the development of EDS technique for estimating OSP thickness, starting with determination of the EDS parameter followed by establishing the correlation between C/Cu ratio and OSP thickness and, finally, evaluating the accuracy of the EDS technique for OSP thickness measurement. EDS quantitative analysis was proved that it can be utilized for OSP thickness estimation.
A Fast Inspection of Well Implantation by Using Plane-View Stain Method
Authors: Lin Jian-Chang , Wu Wen-Sheng , Chen Kuo-Shiung , Yeh Jen-Hung , Hou Ying-Chin 
Published: December 2020

Abstract
In the field of failure analysis, electrical failures caused by improper implantation are often difficult to debug especially for fully processed products. Familiar implantation failure issues include improper implantation concentration, error doping types, incorrect doping ranges, and etc. Although some FA equipments, such as secondary ion mass spectrometry (SIMS), spreading resistance probe (SRP) and scanning capacitance microscope (SCM) [1] [2] [3], can do detail or quantitative analysis for these failure issues, most of these FA jobs are time-consuming and have a detection limitation at the size of failure area. This limitation may restrict the FA applications because the failure area is usually small at the fully processed products after fault isolation. In this paper, two examples with improper doping type and concentration will be analyzed by using a newly developed FA method. Instead of using traditional cross-section (X-S) stain method, we utilize a plane-view stain method to compare the doping type and doping concentration between normal and failed regions. With the aid of the plane-view stain method, we can have a quick check at the suspected failure area with improper front-end implantation before specific SCM analysis.
Voltage Noise and Jitter Measurement Using Time-Resolved Emission
Authors: Kasapi Steven , Woods Gary L. 
Published: December 2020

Abstract
In this paper, we demonstrate two applications of time-resolved emission (TRE): measurement of dynamic, local power-supply (Vdd) variations, and synchronous timing jitter induced by Vdd variations. The first technique measures the height of many peaks within a TRE waveform; differences in peak height are correlated with inter- pulse differences in Vdd. The second technique measures the timing of all of the peaks and extracts the inter-pulse timing variations. The measurement was automated and was performed on long (multiple-μs) acquisition windows containing hundreds of emission peaks. Our work advances the state of the art by using the peak heights and positions to extract this information, and by performing the measurements in an automated fashion.
The Techniques for Short Failure Isolation on Advanced Technology
Authors: Lin H. N. , Wang C. H. , Lin K. L. , Yang W. S. , Chen C. J. 
Published: December 2020

Abstract
Optical beam induced resistance change (OBIRCH) is one popular technique for isolating electrical shorts in process development test structures for 130nm and 110nm device technologies. However, OBIRCH inspection on 90nm technology is not always successful: since the OBIRCH signals of samples are very weak, or even comparable to noise. To overcome this, two alternative and complementary methods for isolating the failure have been developed. The first method is to calculate the coarse position of the defect directly from electrical resistance measurements. The second method is to enhance the OBIRCH signal using FIB circuit modification within the test structure. These methods can help locate defect at this structure by using electrical analysis only or enhancing the OBIRCH signal. The first method is an easy and quick method for short failure isolation, while the second can exactly locate the position of failure if the first method does not reveal a surface defect.
In Situ Electron Microscopy Study of Current-Induced Failure of Carbon Nanofibers
Authors: Suzuki Makoto , Ominami Yusuke , Ngo Quoc , Yang Cary Y. , Mcilwrath Kevin , Jarausch Konrad , Cassell Alan M. , Li Jun 
Published: December 2020

Abstract
We perform the in-situ scanning transmission electron microscopy (STEM) study of current capacity of carbon nanofibers (CNFs) suspended between two electrodes in vacuum. At an average current density of 4×106 A/cm2, CNFs show breakdown due to current stress. Current-induced failure results in many voids between graphitic layers in CNF, indicating that the structure of CNFs strongly affects their failure mechanism due to high current stress. These findings provide the insight of the failure mode of future carbon-based interconnects.
Effect of Die Chip-Outs and Reflow Temperature on the Mechanical Behavior of a 5-Die-Stacked Chip Scale Package
Authors: Evan Dennis , Balacano L. , De La Rama Lito P. 
Published: December 2020

Abstract
During package qualification, a 5-die-stacked chip scale package was being marginally triggered on high stand-by current collectively known as Power ICCS failure. Affected lots are subjected to 3x reflow at 240°C. Post reflow failures include blown_up, high standby current in Vcc pin (ISBLO), and high standby current in Vccq pin (ISBLOQ). Backside chip-outs are observed on Die 1 and Die 3 of the three failures. Electrical validation showed that only Die 3 is failing. Corner crack on Die 3 is common to the blown_up and ISBLO failing units while crack on Die 3 backside is observed to propagate toward the active area on ISBLOQ failing units. Fracture analysis results show that the crack of the three failures all originated from die backside chip-out. Thermo-mechanical model of the package shows that, by design, Die 3 generates the highest stress concentration. Results show that if chip-outs are present on the area of the die with the highest stress concentration and the unit is subjected to reflow temperature of 240°C, die crack will propagate from the chip-out. This paper presents the unique failure mechanism observed on a 5-die-stacked chip scale package and the corrective actions applied to solve the issue.
A New Methodology for Electrical Debugging Short in Packages with the Modified Daisy-Chain Die
Authors: Hsiung Steve K. , Tan Kevan V. , Soopikian John 
Published: December 2020

Abstract
Packages with the Modified Daisy-chain (MDC) die have been used increasingly to accelerate reliability stress testing of IC packaging during package development, qualification, and evaluation and reliability monitor programs [1]. Utilizing this approach in essence eliminates chip circuit failure mechanisms. Unlike packages with active die, in packages with the MDC die, when short occurred between two daisy-chain pairs of I/Os, there are four possibilities that can attribute to each pin of the two daisy-chain pairs. That makes the isolation of short failure difficult. Time Domain Reflectometry (TDR) is a well-described technique to characterize package discontinuity (open or short failure). By using a bare package substrate and a reference device, an analyst can characterize the discontinuity and localize it: within the package, the die-package interconnects, or on the die [2]. Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields generated by current. The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects [3]. In this paper, a new methodology that combines Resistance Analysis, TDR Isolation and SSM Identification for electrical debugging short in packages with the MDC die will be presented. Case studies will also be discussed.
Masking Technique to Enable Multiple Site Defect Analysis on a Microchip
Authors: Hahn James 
Published: December 2020

Abstract
As feature sizes are shrinking beyond 130nm, fresh subsets of failures are coming to light. Multiple site defect analysis with adjacent block comparisons and multiple site comparative nanoprobing have become mandatory for these extraordinary and non-visible defects. There are instances where inspection or analysis will be required at multiple sites over a wide area on a sample. Traditional mechanical deprocessing techniques do not allow us to maintain planarity over a relatively large area, typically tens of microns. This article presents a 'masking technique' that addresses the issue of 'adjusting' the level at several local sites on a microchip. This technique can be utilized at all deprocessing levels of defect analysis and comparative circuit analysis and is time, tools, and labor efficient. Additionally, it enables multiple site nanoprobing, a preferred and essential tool for electrical validation of non-visible failures at technologies 90nm and beyond.
Failure Analysis Methodology for Li-Ion Incidents
Authors: Loud John , Hu Xiaoyun 
Published: December 2020

Abstract
The purpose of this article is to lay out a scientific methodology for investigating lithium ion (Li-ion) product failures. The discussion provides possible causes for an overheating Li-ion cell failure and covers processes involved in preventing Li-ion incidents. Performing a scientific root cause failure analysis involves systematically performing the failure analysis, which is explained in detail, to eliminate branches from the fault tree and arrive at the root cause of a given failure. Statistical analysis of Li-ion cells is provided, along with a recall determination of issues in Li-ion cells. The article also presents snapshots from actual Li-ion investigations selected from hundreds of investigations that have been performed by the authors at Exponent as far back as 1995.
Tool-Related ESD Surface Damage (ESDFOS) on Wafers in Cu-Technology
Authors: Jacob Peter , Hartfield Cheryl 
Published: December 2020

Abstract
In many cases it is difficult to distinguish mechanical damage from electrostatic surface impacts. In recent years, several investigations have resulted in publications on ESDFOS (Electrostatic Discharge From Outside to Surface). While the diagnostics of the phenomena have been worked out quite well for wafers with aluminum metallization, no formal studies on ESDFOS impact to copper-metallized wafers have been published. This paper investigates physical features of Cu-metallized wafers artificially exposed to ESDFOS impacts of variable severity, producing an understanding of damage features to more easily facilitate recognition of EDSFOS events.
Low keV FIB Applications for Circuit Edit
Authors: Rue Chad , Shepherd Randall , Hallstein Roy , Livengood Rick 
Published: December 2020

Abstract
Focused ion beam (FIB) tools are used to perform "circuit edit," (CE), in which existing integrated circuit devices are modified to create prototype devices that simulate potential mask changes. Although ion milling at low keV is common in TEM sample preparation, the technique has not become commonplace for CE applications. This is because most commercial FIB systems are optimized for either 30 or 50 keV. Recent work in the laboratories of FEI and Intel have attempted to apply low keV FIB processing to cutting small copper lines on advanced IC devices. The majority of this paper focuses on water-assisted, low keV copper etching. Secondary objectives of this work are to raise general awareness among FIB users of the potential benefits of low keV processing, to speculate on the physical mechanisms involved, and to discuss some of the technical difficulties associated with low keV FIB operation.
Novel Dielectric Etch Chemistry for the Next Generation of Circuit Edit: Delicate to Low-k Dielectrics and Silicon
Authors: Makarov Vladimir V. , Krasnobayev Leo , Misquitta Sabina F. 
Published: December 2020

Abstract
A novel solution is presented for dielectric and silicon etching when using FIB for circuit edit. In contrast to commonly used XeF2, the new solution has a significantly higher activation threshold that allows it to be used for etching new sensitive low-k dielectrics and even thin silicon without the risk of damaging these materials spontaneously. Examples of operations presented are: etching through ultra low-k dielectrics on a front side device, exposure of a conductor through shallow trench isolation (STI), and trimming active silicon when performing circuit edit on a back side device. The advantages in comparison to XeF2 applications are discussed.
Start up of a Dual Beam FIB for Automatic STEM Sample Preparation
Authors: Demarest James J. , DeSouza Zubin 
Published: December 2020

Abstract
This paper deals primarily with the difficulties and solutions to STEM sample preparation. The dual beam focused ion beam (DBFIB) whole wafer platforms often come with scripting features which allow the tool to operate with a high level of automation. The main focus of the paper is on the variety of challenges which are encountered in trying to implement automated STEM and TEM sample fabrication with minimal operator input and the engineering solutions implemented to overcome the challenges. The paper demonstrates that the challenges with making STEM and TEM samples in a highly automated fashion by DBFIB, while difficult, are not insurmountable. It has highlighted a mechanical issue with the ion aperture motor mechanism, which required extensive troubleshooting to fully diagnose and correct. A long standing software routine had to be modified to fully enable script automation by extending the beam dwell time of the automatic brightness contrast routine.
Laser-Thermal Imaging
Authors: Falk R. Aaron , Pham Tram 
Published: December 2020

Abstract
Laser induced emission and photocurrents with exponential power scaling were discovered using a near IR Raman laser scanning microscope. The potential for utilizing these highly non-linear effects for sub-diffraction limited imaging has been explored both theoretically and experimentally. A three-fold improvement over the linear diffraction limit was predicted and experimentally validated.
Mobile Diffractive Solid Immersion Lens Design for Backside Laser Based Fault Localization
Authors: Goh S.H. , Cho J.Y. , Lam Jeffrey , Phang J.C.H. 
Published: December 2020

Abstract
In this paper, a mobile Diffractive Solid Immersion Lens (mDSIL) design is proposed to enhance spatial resolution for backside laser fault isolation techniques. By allowing for multiple failure sites analysis using a single DSIL, this design improves conventional static DSIL directly fabricated on silicon substrate. The feasibility of mDSIL is demonstrated experimentally and the resolution performance is shown to be comparable to a static DSIL.
Fault Isolation of Sub-Surface Leakage Defects Using Electron Beam Induced Current Characterization in Next-Generation Flash Memory Technology Development
Authors: Nagatani Go , Yu Kenneth , Rosario Amalia Del , Sidorov Max , Stallcup Richard E. , Gray Joel-Anthony 
Published: December 2020

Abstract
This paper covers methods used to isolate single leaky junctions in a test structure designed for Flash memory technology development. It may be possible to isolate this failure through micro probing or a combination of electrical testing and physical structure modification by FIB, but at the expense of spending numerous days. The paper shows that a combination of emission microscopy (EMMI), electron beam induced current (EBIC) characterization and a SEM nano-probing can drastically simplify the fault isolation process. Results of nano-probing are also shown to prove the level of leakage detected in the faulty junction. A combination of EMMI and EBIC characterization was able to pinpoint the problematic junction from approximately 2500 junctions in the structure. Furthermore, the nano-probing IV characterization proved the identified junction to be indeed high in leakage current, providing further confidence for physical failure analysis.
A Novel Wet Etch In-situ Decapsulation of Devices on Boards
Authors: Gonzales Michael A. , Kiljan Joanna 
Published: December 2020

Abstract
This paper presents a novel technique for decapsulation of integrated circuits (ICs) mounted on printed circuit boards. This technique overcomes wet etch related sidewall blowouts that damage or alter the performance of the IC and board under test. It also allows well defined etch geometries and better endpoint detection. This is accomplished by protecting the region of interest (ROI) with a fast-curing, acid-resistant maskant that peels off easily. The technique was successfully utilized on a densely populated board, which exhibited temperature sensitive failure mechanism, as discussed in this paper.
Low Temperature Plasma Decapsulation of Copper-Wire-Bonded and Exposed Copper Metallization Devices
Authors: Staller Kristopher D. 
Published: December 2020

Abstract
One method of reducing costs in the packaging sector is to switch from gold bond wires to copper. Thicker copper wires (over 2 mils) can be safely decapsulated using a ratio mixture of fuming acids. Some surface etching of the copper will occur, but the wire will remain electrically viable. Microwave Plasma can provide a safer alternative for decapsulating packages with copper bondwires and exposed copper metallization. In this paper, experimental deprocessing of copper bond wire and copper metallization using laser ablation and downstream microwave plasma has found that 1 mil stressed wires can be safely exposed and examined, showing slip plane fractures in the corner wires. Topside copper metallization remains intact, even the thin protective nickel plating. Sensitive copper metal structures on top of the passivation (such as antennas) will remain electrically viable following decapsulation with plasma, but are often lost and defective following acid decapsulation.
Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis
Authors: Chen Kuo Hsiung , Wu Wen Sheng , Shu Yu Hsiang , Lin Jian Chan 
Published: December 2020

Abstract
IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.