bluuebunny/crossref_metadata_2025_split huggingface dataset:
(Invited) in-Situ Impedance of Lithium-Ion Rechargeable Batteries during Charge and Discharge
Authors: Itagaki Masayuki , Hoshi Yoshinao , Shitanda Isao 
Published: February 2020

An electrochemical impedance spectroscopy (EIS) is useful method to investigate inner structure and conditions of lithium-ion rechargeable batteries (LIRB) because EIS is nondestructive method to discriminate time constants related to electrolyte/electrode interfaces and protective film formed on negative electrode. The almost impedance measurements of LIRB are generally carried out at an equilibrium-state. The authors would like to emphasize that the galvanostatic control should be employed to measure impedance spectra of LIRB because the information of batteries during operation is more important than that at the equilibrium-state. For example, high power batteries require low charge transfer resistance during the high rate discharge. Stoynov et al. [1] measured impedance spectra of lead acid battery during charge and discharge at galvanostatic polarization. Itagaki et al. [2-4] determined time-dependent impedance spectra of LIRB’s during charge-discharge sequence.
Figure 1 shows charge curve of a LIRB and 3D impedance spectra measured during the charge simultaneously. Three impedance spectra were determined by arranging a reference electrode in a laboratory cell of LIRB. The axes of 3D impedance are real and imaginary parts of impedance and time. For example, charge transfer resistance related to the diameter of capacitive loop of (c) positive electrode in high frequency range decreased with increasing the state of charge. In this presentation, the authors show the experimental results of 3D impedance spectra of LIRB, and discuss the intercalation/deintercalation mechanisms of lithium-ion at negative and positive electrodes.

References:
[1] Z. B. Stoynov, B. S. Savova-Stoynov, T. Kossev, J. Power Sourses,
30 (1990) 275.
[2] M. Itagaki, N. Kobari, S. Yotsuda, K. Watanabe, S. Kinoshita, M. Ue, J. Power Sources, 135 (2004) 255.
[3] M. Itagaki, N. Kobari, S. Yotsuda, K. Watanabe, S. Kinoshita, M. Ue., J. Power Sources, 148 (2005)78.
[4] M. Itagaki, K. Honda, Y. Hoshi and I. Shitanda, J. Electroanal. Chem., 737 (2015) 78.

Figure 1
Electrochemical Synthesis of Ammonia: Status, Challenges and Opportunities
Authors: Xu Hui , McCallum Tom 
Published: February 2020

Ammonia (NH3) is an extremely important feedstock producing nitrogen fertilizers that provide essential nutrition for crop vitality. The worldwide production of ammonia is more than 100 million tons per year. The conventional Haber–Bosch ammonia production process requires high pressure and temperature (up to 300 atm and 500°C) and is, as such, extremely energy-intensive.
Electrochemical synthesis of ammonia via an ion exchange membrane (IEM) may proceed at lower temperature and pressure thus potentially reducing the energy consumption 1. However, the application of this technology has been restricted by lower ammonia production (< 10-7 mol/s-cm2) and Faradic efficiency, making the initial capital cost very prohibitive.
This work will present current status and challenges of electrochemical synthesis of ammonia, based on our technology development and other noteworthy researches in this area. The strategies to improve the ammonia production rate, efficiency and stability have been elaborated, which include advanced catalyst development, alternative membranes 2 (e.g. alkaline membrane, proton or oxygen ion-conducting metal oxide electrolyte) and optimized operating conditions (e.g., temperature, pressure, and humidity). In particular, the electrochemical synthesis of ammonia using water (free of H2) and nitrogen as reactants is analyzed. Finally, the integration of this technology with off-peak renewable energy towards building distributed ammonia plants will be evaluated.
The successful application of this technology may lead to ammonia synthesis via a more environmentally-benign and economically viable approach, compared to the conventional Haber-Bosch process. The synthesized ammonia using renewable energy can be widely used as a feedstock for fertilizers in agriculture. The ammonia can also be considered as a means of storing surplus renewable energy during off-peak hours.
Reference:

Marnellos, G., and M. Stoukides, “Ammonia synthesis at atmospheric pressure,” Science, 282(2), 98-100 (1998).

Licht, S, Cui, B., Wang, B., Li, F-F, Lau, J., and Liu, S., “Ammonia syhthesis by N2 and steam electrolysis in molten hydroxide suspensions of nanoscale Fe2O3”, Science, 345, 637-640 (2014)
(Invited) Non-Visual Defect Monitoring with Surface Photovoltage Mapping
Authors: Findlay Andrew David , Marinskiy Dmitriy , Edelman Piotr , Wilson Marshall , Savtchouk Alexandre , Almeida Carlos , Lagowski Jacek 
Published: February 2020

Non-Visual Defects (NVD) is a category of semiconductor material and process induced defects that cause electrical failures, but are not detected with visual wafer inspection tools. This paper gives an overview of our non-contact electrical NVD metrology that uses fast whole wafer inspection with standard mm resolution Kelvin probe surface voltage mapping. In an advanced approach the detected NVD regions are imaged in high resolution (mm range) using Force Kelvin Probe Microscopy. In depth NVD characterization is done with the corona-Kelvin method that quantifies dielectric and interfacial properties in the defect sites. This characterization is performed in a non-invasive fluence range of corona charging and all measurements are non-contact, and do not require fabrication of test devices.
Principles of non-contact surface voltage are explained for whole wafer mapping using a high throughput dual Kelvin-probe approach, and for high-resolution micro-Kelvin Force Probe mapping of defect sites. Application examples are discussed in chronological order of the metrology development, starting with monitoring of plasma damage first introduced about 20 years ago. Further examples include surface voltage mapping of surface alkali-metals including novel high resolution micro-Kelvin Force Probe results. Recent trends in monitoring are illustrated with patterned wafer mapping and micro-scale intra die NVD’s. Finally an extension of the technique to defect mapping in SiC is presented together with in-depth corona-Kelvin characterization of defect sites. A broad application range is demonstrated with examples relevant to silicon IC, silicon photovoltaics and to wide bandgap epitaxial SiC.
Combined Effect of Rapid Thermal Annealing and Crystal Nature on the Gate Oxide Reliability of Czochralski Silicon
Authors: Shin Jung-Won , Lee Woo-Sung , Kim Ja-Young , Lee Anselmo Jaehyeong , Kang Hee-Bog , Lee Sung-Wook 
Published: February 2020

Internal gettering (IG) of metallic impurities (MI) in Czochralski silicon (CZ-Si) is one of the key techniques in modern microelectronic engineering to manufacture high-performance devices with high process yield. Various silicon substrates such as EPI wafers with heavily boron-doped substrates, ion-implanted wafers, and rapid-thermal annealing (RTA) treated wafers have been used to enhance IG ability [1-2] and retain denuded zone (DZ) for the active area of devices. Especially, RTA-treatment is an easy way to form IG and DZ simultaneously with a rapid heat process that injects the intrinsic point defects, mainly vacancies, into the bulk. However, it was reported that vacancy clusters, or ‘nano voids’ whose size was less than 50nm [2-3] could be formed in the near-surface region after RTA process via vacancy self-trapping [4], which can possibly degrade the performance and yield of device. In this study, we investigated the effect of RTA treatment on the gate oxide reliability and their relation to the crystal nature, i.e., as-grown point defect distribution in silicon wafers.
As shown in Fig. 1 a), we performed the Cu-contamination method [5] on the prepared samples to verify the crystal nature of each sample. After that, we separated the samples into two groups whether they treated by RTA or not, and carried out time-zero dielectric breakdown (TZDB) reliability tests on the patterned poly-Si/oxide/Semiconductor capacitors with the gate oxide thickness of 10 nm. As shown in Fig. 1 b), distribution of TZDB failed cell on the wafer was closely related to the crystal nature. Moreover, it was revealed that a vacancy-dominant region tends to have lower breakdown field than an interstitial-dominant region. These phenomena were only found in RTA-treated wafers and entire fail rate was drastically increases when RTA effect was combined with vacancy-dominated region, which was shown in Fig. 1 b). We assumed that as-grown vacancies contained in the vacancy-dominated region tend to enhance the supersaturation of vacancy beneath the oxide-semiconductor interface, so the formation of nano voids was accelerated and the breakdown field was lowered due to the presence of such defects. A detailed mechanism of the experimental result will be discussed.
Figure 1. a) Crystal nature measured by Cu contamination method and b) TZDB frequency with or without RTP

References

1. Jea-Gun Park, Gon-Sub Lee, Jin-Seo Lee, Kazunari Kurita, Hisashi Furuya, Mater. Sci. Eng., B, 134, 249 (2006).
2. G.Kissinger, D.Kot, W.Häckl, ECS transactions, 33(11), 113 (2010).
3. Thomas A. Frewen, Talid Sinno, Appl. Phy. Lett, 89, 191903 (2006).
4. M.Gao, X.F.Duan, L.-M.Peng, Appl. Phy. Lett., 73, 2311 (1998).
5. Sang-Wook Wee, Sung-Wook Lee, Ki-Man Bae, and Kwand-Salk Kim, U. S. Patent 7,901,132.

Figure 1
(Invited) Characterization of Group IV Based Nanowires Manufactured on Advanced Engineered Substrates
Authors: Radamson Henry H. , Noroozi Mohammad , Toprak Muhammet , Luo Jun , Wang Guilei , Zhao Chao 
Published: February 2020

Advanced substrate engineering is gaining new applications for nano-scaled devices where such substrates offer unique possibility to tailor the strain and the carrier transport. In general, XOI is a notation for wafers with a semiconductor-on-insulator where X is any alloy from SiGeSnC materials or III-V compounds.
In special, strained XOI substrates (s-XOI) are widely used to manufacture nanowire transistors where the carrier mobility is enhanced by strain.
So far, wafer bonding or condensation methods have been applied to manufacture XOI wafers. In case of SiGe-on-insulator (SGOI), a thin SiGe layer is grown on SOI and subsequently oxidized to create a single SiGe layer on oxide. During oxidation the Si atoms are preferably consumed and Ge atoms are driven toward the oxide box acting as a diffusion barrier. Therefore SGOI wafers suffer from point defects which have a strong influence on the carrier mobility, thermal conductivity and even optical properties. Post annealing may improve the layer quality and majority of the defects could be disappeared.
The wafer bonding is more complicated and sensitive method. This relates to the requirements e.g. surface flatness, layer quality of the semiconductor and the amount of exerting bonding force.
In manufacturing of Ge-on-insulator wafers, a high quality Ge layer is grown at 700-750 °C on a low quality Ge (grown at 300-400 °C). The Ge layers are transferred and bonded to oxide wafers by using a uniform force of few kNs. Afterwards, the wafers are annealed at 500-600 °C before etch back step (see Fig.1). It is important to mention here that the annealing step has to be decreased for bonding of GeSn-on-insulator wafers in order to avoid strain relaxation.
In this work, manufacturing methods for different sizes of XOI and s-XOI wafers are presented and an attention is paid for using the manufactured XOI wafers for the thermoelectric application, where lateral nanowires are formed. As an example, for SiGe nanowires the seebeck coefficient is enhanced in presence of defects, however, any kind of defects in XOI wafers degrade the channel mobility in the processed MOSFETs.
Characterization techniques e.g. high-resolution reciprocal maps using synchrotron x-ray beam, high resolution transmission electron microscopy, and photoluminescence were applied to detect the defects and estimate the strain relaxation. The experimental data is linked to explain the electrical properties of XOI wafers and finally to nanowires and MOSFETs.

Figure 1
Ab-Initio Studies of Acceptor Impurities and Stability of Complexes in Ge
Authors: Emmanuel Igumbor , Mapasha Edwin R , Richard Andrew C , Meyer Walter E 
Published: February 2020

The application of germanium (Ge) as a promising material for complementary metal-oxide semiconductors (CMOS) technology is attracting attention due to its narrow band gap, high carrier mobility and low voltage operations. Recent experimental and theoretical studies revealed that dopants in Ge cluster with vacancies forms with lower energies and contribute to low activation of dopants impurity in Ge. DFT electronic simulation have been used to provide concise information about the formation of defect clusters and complexes that influence diffusion mechanisms in Ge. Our main objective in this study is to use simulations based on ͑DFT to calculate the structural, electronic properties and interactions between acceptors and Ge in different configurations with a view to finding the most energetically stable configuration of various defect complexes in Ge.
By means of density functional theory (DFT), we present ab-initio calculation of interactions between A (A: Be,Mg, Ca, Sr, Ba, Ga, In) vacancy complexes (A-VGe) and vacancy-interstitial complexes (A-VGeIA) in two configurations of the hexagonal (H) and tetrahedral (T) in Ge. These calculations employed a projector augmented wave (PAW) pseudopotentials within the generalized gradient approximation (GGA). The geometric structures and formation energies of A-VGe and A-VGeIA in both the T and H configurations for the neutral charge state were obtained. The formation energies of A-VGe were low and energectically favourable with Ga-VGe and Ca-VGe forming with the lowest formation energies at -1.24 and -0.38 eV respectively. For the A-VGeIA, the results of the H configuration were more energetically favourable and forms with lower formation energies than the T configuration. The Ca-VGeICa and Be-VGeIBe forms with the lowest formation energies of -2.59 and -1.49 eV respectively. The stability of the A-VGeIA and A-VGe complexes in Ge were obtained from their binding energies. The binding energies (Eb ) which are defined as the energy required to split up the defects cluster into well separated non-interacting defect is given as
Eb = E(formation)(VGe) + E(formation)(AGe) - E(formation){defect-complex},
where E(formation)(VGe), E(formation)(AGe) and E(formation)(defect-complex) are the formation energies of the neutral charge state of the germanium vacancy, interstitials and defect-complexes. The above equation could be interpreted as the energy gain of the bonded structure with respect to the isolated components. Positive binding energies suggest that the defect complexes are stable and cannot easily dissociate. The calculated binding energies of both the A-VGe and the A-VGeIA displayed the ability of these complexes to form without dissociation. For the A-VGeIA, the H configuration forms with more favourable binding energies than the T configuration. In summary the detailed calculated results we have presented are expect to be useful in the process modeling of Ge-based devices.
Advanced Wet Clean Technology at Lightly Doped Drain Layers in FinFET
Authors: Li Jian , Sih Vincent , Zhan Hui 
Published: February 2020

Along with fast-paced development of semiconductor industry, circuit patterns become much smaller and finer. Currently the pattern design migrates from traditional planar structure to three-dimensional FinFET. Therefore how to remove surface particles in various sizes effectively without damaging the pattern structures in the higher aspect ratio is more and more essential to achieving critical rapid yield ramps in the advanced technology node.
In the FinFET process scheme, after formation of poly gate, Lightly Doped Drain (LDD) implants are invented to alleviate the short channel effect between Source and Drain Junction. In LDD layers, low density impurity of B+ and As+are implanted into PFET and NFET, respectively. The repeated implant steps will inevitably bring certain amount of surface particles, which are defined in higher killer ratio, since they can be embedded defect after few nitride spacer layers are deposited, causing the poor device performance and low product yield.
Figure 1 shows the typical SEM images of various surface particles generated during repeated LDD implant steps. Standard RCA Clean 1 (SC1) with the mixture of hydrogen peroxide, ammonium hydroxide and deionized water usually would be applied to reduce organic and surface particle. But particles removal efficiency (PRE) is not satisfied for advanced FinFET manufacturing. Aerosol or nanospray to dispense chemical solution with the mixture of nitrogen gas in high pressure is another candidate to possess higher PRE, however, the traditional aerosol technique would create liquid droplets in a large range of size, so the non-uniformed momentum of liquid droplet can result in severe pattern damage on poly gate at LDD layers.
In this paper, we report an advanced wet clean method based a single wafer clean toolset. By using this state-of-the-art wet clean technology, we can control the size and velocity of liquid droplets accurately during the clean chemical dispense. In this sense, with high PRE for surface particles, in the meantime, there is no sacrifice of gate pattern damage in LDD layers. It was demonstrated on FinFET production wafers that surface particles were reduced by as much as 30% with the new clean technology implementation. Also, about 5% yield improvement was observed for the new clean process.
Figure 1: Typical SEM images of surface particle defect in LDD layers

Figure 1
Impact of Sacrificial Cosumption of Substrate By Thermal Oxidation on Electron Mobility of 4H-SiC Mosfets
Authors: Kita Koji , Hirai Hirohisa 
Published: February 2020

4H-SiC MOSFETs are extensively studied for high-voltage power device applications, however, the control of MOS interface properties have been one of the most challenging issues to meet the requirements of low on-resistivity and high-reliability. A significant degradation of electron mobility in inversion channel has been often reported, however, the dominant factors which deteriorate the channel characteristics have not yet been clarified well. In this study we investigated the effects of thermal oxidation during MOSFET fabrication processes on the quality of substrate surface, from the view point of channel mobility degradation.
Lateral n-MOSFETs with various gate length, Lg=80~500 μm, were fabricated on p-type 4H-SiC (0001) wafers with Al-doped epitaxial layers. Source/drain (S/D) regions were formed by P implantation, followed by an activation annealing at 1650°C with a carbon cap. Ni Ohmic contacts for n+ S/D were formed by PMA at 1000°C for 1 min in N2 ambient. Finally Al was deposited and patterned as the gate electrode. Before the gate oxide formation, we intentionally consumed 5~60 nm of SiC substrate by a thermal oxidation followed by a chemical etching of SiO2 in HF solution. The gate oxide was thermally-grown in dry-O2 at 1300°C, followed by a post-oxidation-annealing in O2 at 800°C [1]. The consumed SiC thickness in total, including the gate oxide formation process as the final step, was varied from 9 to 72 nm. As a result, a degradation of field-effect-mobility was clearly observed when the sacrificially-consumed SiC thickness increased. To avoid the additional effects of surface damage due to the high-temperature activation annealing, we also prepared a MOSFET without 1650°C annealing, and successfully observed a further enhancement of channel mobility ~10% by minimizing the consumed SiC thickness during the device fabrication processes. Even though we expected the activation of only a few percentage of implanted P atoms, thanks to the thermal oxidation process at 1300oC for this sample, we could extract the channel mobility after the calibration of the effects of the parasitic resistance from Lg-dependence of channel resistance.
These results clearly indicate that the sacrificial consumption of SiC substrate surface results in a monotonic degradation of channel mobility. The mechanism of such deterioration has not been clarified yet, but we believe that a degradation of SiC surface quality, possibly due to an accumulation of Al dopants [2] or interstitial C atoms near the SiC surface during the oxidation processes, would explain such change of MOSFET performance.
[1] R. H. Kikuchi and Koji Kita, Appl. Phys. Lett. 105, 032106 (2014).
[2] T. Kobayashi et al., Appl. Phys. Express 7, 121301 (2014).
(Invited) Plasma-Enhanced Quasi-ALE and ALD Processing for Leading-Edge Microfabrication
Authors: Honda Masanobu , Katsunuma Takayuki , Tabata Masahiro , Tsuji Akihiro , Oishi Tomoyuki , Hisamatsu Toru , Ogawa Shuhei , Kihara Yoshihide 
Published: February 2020

In recent years, the progression of very large scale integration of semiconductor devices and miniaturization require extension of ultra-high selectivity process and CD control technique exhibiting atomic-layer-level control. We introduce herein a state-of-the-art self-aligned contact (SAC) etching process and multilayer patterning process developed by a new patterning technology using Atomic Layer Etch (ALE) and Atomic Layer Deposition (ALD) towards the 5/7nm generation.
SAC etch processes are known to require SiO2 etching capability with ultra-high selectivity to SiN. We developed a modified ALE process [Quasi-ALE] to make it more suitable for SiO2 etch. By adopting this technology to the SAC process, conventional trade-offs between SiO2 etch through capability and SiO2selectivity to SiN in the fine slit pattern is significantly improved. This achievement is enabled by Quasi-ALE’s independent controllability of the radical flux and ion flux, which precisely controls the reaction layer thickness on the surface, allowing etch process at lower ion energy region which is most effective to improve etch selectivity.
The advancement of EUV lithography toward manufacturability has accelerated the need for innovation in multilayer lithography stack etches. The patterning of high quality sub lithographic patterns is becoming more challenging, especially in regards to line-roughness (LER/LWR) reduction, and selectivity enhancement of thin EUV-resist. Furthermore, patterning with universal CD shrinkage independent of the pattern types (hole, oval, L/S) is also being required. As a result of various techniques were studied for enhancement of fine pattern formation, “fusion of ALD technology and etching” was confirmed to be very beneficial for its capability of atomic-level formation of surface protection film during the etch process. This technology enabled line-roughness reduction with CD shrink control independent of the pattern-size, since the ALD step is used according to the optimum timing during the etch process, which forms uniform deposition on any type of patterns.
As described, precise control of the microfabrication at atomic layer level utilizing Quasi-ALE and ALD technology is becoming mandatory in the generation of 5/7nm.