Charge Trapping Memory with 2.85-Nm Si-Nanoparticles Embedded in HfO2
Authors: El-Atab Nazek , Turgut Berk Berkan , Okyay Ali , Nayfeh Ammar 
Published: February 2020

Innovative means to reduce the operating voltage and increase the stored charge density in current non-volatile memory devices are imperative [1-5]. In this work, 2.85-nm Si nanoparticles (Si-NPs) embedded in an ultrathin HfO2 layer are investigated for charge storage in low-cost non-volatile charge trapping memory devices. The memory hysteresis at different gate voltages, the stored charge, and the energy band diagram of the memory structure are analyzed.
The memory cells are fabricated on an n+-type (111) (Antimony doped, 15-20 mΩ-cm) Si wafer. 5-nm-thick tunnel oxide Al2O3 is deposited at 250°C in Cambridge Nanotech Savannah-100 atomic layer deposition (ALD) system. Then, 1-nm-thick HfO2 is deposited by Plasma Assisted ALD at 195°C in an Oxford FlexAL system. Next, 2.85-nm Si-NPs are spin coated on the sample [6]. Again, a 1-nm-thick HfO2 is deposited by plasma assisted ALD at 195°C. Finally, an 8-nm-thick Al2O3 blocking oxide is deposited by ALD at 250°C. A 400-nm-thick Al layer for the gate contact is e-beam evaporated using a shadow mask with 10 μm feature size which eliminated the need for lithography steps. A cross-sectional illustration of the fabricated memory device is depicted in Fig. 1.
The fabricated memory devices are electrically characterized by measuring the high frequency (1 MHz) C-Vgate characteristics of the programmed and erased states. Using the Agilent B1505A Semiconductor Device Parameter Analyzer, the memory cells gate voltage was first swept from -6 V forward to 6 V then backwards. A 1.8 V threshold voltage (Vt) shift is observed. The C-V measurements are repeated at a gate sweeping voltage of 8/-8 V and both erased and programmed states shifted outwards as shown in Fig. 2 resulting in a 4.5 V memory window. This indicates that the charge trapping layer is storing mixed charges: electrons and holes, however, more charging is due to holes revealed by the greater shift of the erased state in the negative direction as shown in Fig. 2. Moreover, the Vt shift is measured at different gate sweeping voltages as sown in Fig. 3 and the charge trapping density in the Si-NPs is calculated [3] and found to be 2.32 ×1013 cm-3.
The analysis of the energy band diagram shows that the conduction band offset between Si and tunnel oxide is smaller than the valence band offset (ΔEC = 2.44 eV < ΔEV = 3.24 eV), thus the electrons tunneling probability is expected to be higher. However, the conduction band offset between the 2.85-nm Si-NPs [7] and tunnel oxide is much smaller than the valence band offset (ΔEC = 1.29 eV << ΔEV = 3.77 eV). This means that stored electrons can tunnel back to the Si channel much easier than holes. This confirms the observed larger charging due to holes in Fig. 2. Moreover, the addition of the high-dielectric constant (қ=20) HfO2 layer is expected to reduce the leakage of stored charges.
Finally, the fabrication of such memory structure is compatible with existing semiconductor processing thus has potential on low-cost integrated nanoscale memory applications.

Acknowledgment: This work was supported by ATIC, and TUBITAK Grants 109E044, 112M004, 112E052 and 113M815.

References

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Figure 1