bluuebunny/crossref_metadata_2025_split huggingface dataset:
Time Resolved Imaging Solving FPGA Logic Fault Localization by Pattern Matching Technique
Authors: Bascoul G. , Perdu P. , Di Battista J. 
Published: December 2020

Abstract
From a designer point of view, the analysis of a failure root cause can quickly become a nightmare if the number of hypothesis provided by a simulation tool is too high. To help solving this kind of problem the use of physical probing measurement can reduce drastically the number of assumptions made by the simulation by invalidating certain hypotheses. The purpose of this paper is to add to the simulation a new source of information based on light emission to solve this kind of problem. Virtual logic diagram computation is able to provide several hypotheses of fault for a given node and data coming from Time Resolved Imaging (TRI) measurement allows extraction of transition pattern for a given node where the assumption has been established. The cross-referencing of this information aims at eliminating wrong hypotheses and making the simulation more reliable.
A Novel Integrated Reliability Test System for BEOL TDDB Study
Authors: Chen Jifeng , Song Peilin , Shaw Thomas M. , Stellari Franco , Gignac Lynne , Breslin Chris , Pfeiffer Dirk , Bonila Griselda 
Published: December 2020

Abstract
In this paper, we propose a new methodology and test system to enable the early detection and precise localization of Time-Dependent-Dielectric-Breakdown (TDDB) occurrence in Back-End-of-Line (BEOL) interconnection. The methodology is implemented as a novel Integrated Reliability Test System (IRTS). In particular, through our methodology and test system, we can easily synchronize electrical measurements and emission microscopy images to gather more accurate information and thereby gain insight into the nature of the defects and their relationship to chip manufacturing steps and materials, so that we can ultimately better engineer these steps for higher reliable systems. The details of our IRTS will be presented along with a case study and preliminary analysis results.
Sample Preparation Challenges In WLCSP Epoxy Underfill Coating Removal
Authors: Lagar Jason H. , Sia Rudolf A. 
Published: December 2020

Abstract
Most Wafer Level Chip Scale Package (WLCSP) units returned by customers for failure analysis are mounted on PCB modules with an epoxy underfill coating. The biggest challenge in failure analysis is the sample preparation to remove the WLCSP device from the PCB without inducing any mechanical defect. This includes the removal of the underfill material to enable further electrical verification and fault isolation analysis. This paper discusses the evaluations conducted in establishing the WLCSP demounting process and removal of the epoxy underfill coating. Combinations of different sample preparation techniques and physical failure analysis steps were evaluated. The established process enabled the electrical verification, fault isolation and further destructive analysis of WLCSP customer returns mounted on PCB and with an epoxy underfill coating material. This paper will also showcase some actual full failure analysis of WLCSP customer returns where the established process played a vital role in finding the failure mechanism.
Delay Fault Model Evaluation Using Tester Response Data
Authors: Xue Cheng , Blanton R. D. (Shawn) 
Published: December 2020

Abstract
Most chip producers perform delay testing to detect chips that are affected by defects that adversely affect timing. Several delay fault models have been introduced to guide delay test generation. But similar to static (i.e., slow speed) testing, there is always the question of which fault models are best for ensuring quality. MEasuring Test Effectiveness Regionally (METER) is an approach for evaluating fault model effectiveness. Compared to the conventional test experiment, METER is extremely inexpensive and provides a more thorough evaluation of the quality achievable by a particular fault model. In this work, we describe an extension to METER (called DELAY-METER) that allows the effectiveness of delay fault models to be precisely evaluated. Application of DELAY-METER to the production fail data from an IBM ASIC demonstrates that new and existing delay fault models can be evaluated using conventional tester response data, i.e., data logs collected from production fails through the application of tests generated using conventional fault models.
TEM/FIB Technical Solutions to Electron Beam Induced Radiation Damage to Low K/Ultra Low K Dielectrics in Semiconductor Failure Analysis
Authors: Binghai Liu , Ye Chen , Zhiqiang Mo , Ping Zhao Si , Yuin Wang Chue , Jili Wang 
Published: December 2020

Abstract
Electron-beam induced radiation damage can give rise to large structural collapse and deformation of low k and ultra low k IMD in semiconductor devices, posing great challenges for failure analysis by electron microscopes. Such radiation damage has been frequently observed during both sample preparation by dual-beam FIB and TEM imaging. To minimize radiation damage, in this work we performed systematic studies on every possible failure analysis step that could introduce radiation damage, i.e., pre-FIB sample preparation, FIB milling, and TEM imaging. Based on these studies, we utilized comprehensive technical solutions to radiation damage by each failure analysis step, i.e., low-dose/low-kV FIB and low-dose TEM techniques. We propose and utilize the low-dose TEM imaging techniques on conventional TEM tools without using low-dose imaging control interface/software. With these new methodologies or techniques, the electron-beam induced radiation damage to ultra low k IMD has been successfully minimized, and the combination of single-beam FIB milling and low-dose TEM imaging techniques can reduce structure collapse and shrinkage to almost zero.
Two Step Fabrication of Tungsten Nanotips by AC Electrochemical Etching and Laser Irradiation for Nanoprobing on Advanced Technology Nodes
Authors: Dawood M. K. , Ng T. H. , Tan H. , Tan P. K. , Oh C. K. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
Rapid technology scaling results in ever shrinking device size. As such, sharper nanotips are required for application in nanoprobing systems. In this work, we present a two-step methodology of fabricating tungsten nanotips with radius of curvature down to 20 nm by using and optimized AC electrochemical etching of tungsten in KOH followed by laser irradiation in KOH. Finally we show the application of the fabricated nanotips with different radius of curvature (ROC) for nanoprobing.
Effective Defect Localization on Nanoscale Short Failures
Authors: Huang Jiang , Sweeney Ryan , Dumas Laurent , Johnston Mark , Chen Pei-Yi , Russell Jeremy 
Published: December 2020

Abstract
This paper presents two case studies, based on 32nm Silicon-On-Insulator (SOI) and 28nm bulk Si technology, on finding the root cause of nanometer scale short failures using Passive Voltage Contrast (PVC), Active Voltage Contrast (AVC) and Transmission Electron Microscopy (TEM). PVC/AVC is used as precision localization technique that is critical for a successful FA-TEM analysis. Combining planar TEM sample preparation and high sensitivity Energy Dispersive Spectroscopy (EDS) mapping, a small residual filament, which is not visible even at high resolution TEM, is found to short two metal lines. The effective usage of voltage contrast and TEM provides the need of high throughput, high precision, and high resolution in the advanced FA lab that serves leading-edge semiconductor manufacturing.
AFM-Based Chemical and Mechanical Property Characterization of Interconnects and Defects
Authors: Lo Michael , Dillon Eoghan , Hu Qichi , Kjoller Kevin , Shetty Roshan , Prater Craig , King Sean W. 
Published: December 2020

Abstract
Spectroscopic characterization of interconnects and circuits in semiconductor devices has become increasingly complicated as dimensions for breakthroughs and failure analysis are continuously shrinking. To achieve high spatial resolution infrared (IR) spectroscopic information, a pulsed infrared laser can be coupled to an atomic force microscope in the atomic force microscopy IR (AFM-IR) technique. The combination of AFM-IR and Lorentz contact resonance AFM (LCR-AFM) has great potential for providing high spatial resolution chemical and mechanical analysis. To demonstrate the feasibility of the AFM-based techniques, AFM-IR spectrum and images were obtained from the interlayer dielectrics of a test structure at a length scale shorter than the IR wavelength. Using the LCR-AFM technique, the relative mechanical properties of the components could be mapped distinctively by observing the contact resonance of the AFM probe. Finally, preliminary data suggest there may be AFM-IR spectral differences between contamination and the bulk material on a liquid crystal display.
Nanoprobing as an Essential and Fast Methodology in Identification of Failure’s Root Cause for Advanced Technology
Authors: Ma Yinzhe , Oh Chong Khiam , Nyi Ohnmar , Zhang Chuan , Nedeau Donald , Lim Seng Keat , King Ming Chu 
Published: December 2020

Abstract
This paper highlights the use of nanoprobing as a crucial and fast methodology for failure analysis (FA) in sub 20nm with an improved semi-auto nanoprobing system. Nanoprobing has the capability to localize as well as characterize the electrical behavior of the malfunctioning device for a better understanding of the failure mechanism. It provides a valuable guide to choose a proper physical FA technique to identify the root cause of the failure. This established methodology helps to accelerate the FA turnaround time and improve the success rate. Its application to a few of the front end of line and one back end of line issues is highlighted in the paper.
Memory Scramble Verification by Frontside and Backside FIB Modification
Authors: Tsai Chun Ming , Huang Yi Shiuan , Lu Ya Hui , Chang Jian 
Published: December 2020

Abstract
Backside FIB circuit edit is an effective way to modify circuit on flip chip or stacked chips. Directly damaging memory cell through bulk silicon by FIB can be used to locate bit address to verify that the scramble test program coordinates correspond to the physical cell location. This paper presents the application of FIB for chip editing, discusses the limitation of the FIB approach and reports the scramble test experiments about the front-side and backside FIB technique to correct scramble testing data.
Detectability of Automotive Power MOSFET On-Resistance Failure at High Current Induced by Wafer Fab Process Excursion
Authors: Weber Yann , Goxe Julien , Castignolles Maris 
Published: December 2020

Abstract
This paper presents the meaningful consequence of a minor Wafer Fab process variability, generating on-resistance drift on low voltage vertical power N-MOSFETs dedicated to microhybrid automotive application. The originality of this paper concerns the necessity to use complementary failure analysis investigations needed to determine the origin of the failure without any possibilities to perform any fault localization. The results enabled implementation of corrections and improvement of test screening to protect customers.
Reballing/Rebumping Ultra-Fine Pitch Packages Less Than 0.5 mm Pitch for FA
Authors: Wettermann Bob 
Published: December 2020

Abstract
As the pitch and package sizes of semiconductor devices have shrunk and their complexity has increased, the manual methods by which the packages can be re-bumped or reballed for failure analysis have not kept up with this miniaturization. There are some changes in the types of reballing preforms used in these manual methods along with solder excavation techniques required for packages with pitches as fine as 0.3mm. This paper will describe the shortcomings of the previous methods, explain the newer methods and materials and demonstrate their robustness through yield, mechanical solder joint strength and x-ray analysis.
Application of Fast Laser Deprocessing Techniques in Physical Failure Analysis on SRAM Memory of Advance Technology
Authors: Yap H.H. , Tan P.K. , Low G.R. , Dawood M.K. , Feng H. , Zhao Y.Z. , Zhou Y. , He R. , Tan H. , Huang Y.M. , Wang D.D. , Zhou Y. , Limin P.S. , James S. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (&gt;4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.
Failure Analysis Methodology on Resistive Open Defects
Authors: Quah A.C.T. , Ang G.B. , Nagalingam D. , Chen C.Q. , Ng H.P. , Neo S.P. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.
Delayering on Advanced Process Technologies Using FIB
Authors: Carleson Pete , Donnet David , Sidorov Oleg , Rue Chad 
Published: December 2020

Abstract
Good control over beam and chemistry conditions are required to enable uniform delayering of advanced process technologies in the FIB. The introduction of newer, thinner and more beam sensitive materials have made delayering more complicated. We shall introduce a new chemistry for device delayering and present results from both Ga and Xe ion beams showing its improvement over existing chemistries.
Failure Analysis Enhancement by Incorporating a Compact Scan Diagnosis System
Authors: Estores Rommel , Vercruysse Pascal , Villareal Karl , Barbian Eric , Sanchez Ralph , Ackerman Rich 
Published: December 2020

Abstract
The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.
Update on Draft SAE AS6171 Standard—Tools and Techniques for Detection and Mitigation of Counterfeit Electronics
Authors: Vanderlinde William E. , Sood Bhanu P. 
Published: December 2020

Abstract
The Society of Aerospace Engineers (SAE) AS6171 Aerospace Standard standardizes the test and inspection procedures, workmanship criteria, and minimum training and certification requirements to detect counterfeit electrical, electronic, and electromechanical parts. The standard comes in response to a significant and increasing volume of counterfeit electrical, electronic, and electromechanical parts entering the supply chain. This short manuscript and its accompanying talk update the audience on the risk based methodology for detecting potential counterfeiting related defects. The techniques that are discussed in AS6171 slash sheet include film radiography and filmless radiography such as digital radiography, real time radiography, and computed tomography. The analysis is performed on parts to verify that the internal package or die construction is consistent with an exemplar item. AS6171 will provide the counterfeit detection community with standardized test and inspection procedures, workmanship criteria, and minimum training and certification requirements to detect counterfeit electrical, electronic, and electromechanical parts.
Laser Stimulation Effect on FinFET and Case Study
Authors: Jin Kyeongju , Lee Sukho , Kim Keonil , Lee Yunwoo , Kim Yojoung 
Published: December 2020

Abstract
In the case of conventional planar FET, Dynamic Laser Stimulation (DLS) is a very effective method to isolate marginal failure. Depending on laser sources, DLS is divided by Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). SDL uses 1320nm wavelength laser source in order to induce localized heat. On the other hand, LADA uses 1064nm wavelength laser source to generate photo carriers. But for the FinFET the effect of laser stimulation is not clear yet. This paper introduces the effect of laser stimulation on FinFET transistors based on wavelength, the so called LADA and two-photon LADA. The experimental data show changes in Vth and Idsat with different character for a single FinFET transistor. A case study further explains this laser stimulation effect via scan chain LVcc marginal failure analysis localized with 1320nm CW laser stimulation and nano-probing analysis.
How to Locate Resistance VIA by Analysing Schematic Combined with EMMI Result on Integrated Circuit Failed at Cold Temperature
Authors: Wen Gaojie , Tian Li , Li Jinglong , Qi Changyan , Wang Dong 
Published: December 2020

Abstract
Due to the decreasing metal line size on complicated integrated circuit, non-destructive analysis strategy such as EMMI (Emission Microscope) is very significant to failure analysis, especially when special cold temperature failures are encountered. When combined with efficient schematic and layout analysis, the real defect can be localized without much microprobe work.
Non-Destructive Contamination Detection in Thick and Extremely Thin SOI Wafers Using Optical Second Harmonic Generation
Authors: Kryger M.C. , Changala J.P. , Alles M.L. 
Published: December 2020

Abstract
Non-destructive optical second harmonic generation (SHG) is shown to be an effective method for detecting interfacial surface and subsurface non-visual defects in commercial thick and extremely-thin (ET) SOI wafers. A method is demonstrated for removing contributions (noise) from layer thickness variations observed in thick SOI, increasing the sensitivity and enabling detection of trace surface metal contamination. Subsurface contamination, otherwise missed by the standard flow of non-destructive characterization methods, is shown to be detected by SHG.
Case Study—Doping Profile Analysis for 30 nm DRAM Devices Using SCM and SSRM
Authors: Chen Hsiu-Pin , Luo Jian-Shing , Sung Ching-Shan , Wei Chen-Kang , Chiang Kai-Lun , Yang Chia-Ming , Liao Hsueh-Chun , Suo Jahson , Lu Shifeng 
Published: December 2020

Abstract
This paper is to evaluate the doping profile analysis capability of Scanning Capacitance Microscope (SCM) and Scanning Spreading Resistance Microscope (SSRM) on 30nm Dynamic Random Access Memory (DRAM) devices and apply the SSRM technique on a real case to verify the junction depths of different doping recipes for device performance tuning. The results show SCM can be used on periphery devices in a 30nm DRAM due to they have larger feature size (&gt;90nm). For array devices with minimum feature size (~30nm) in a 30nm DRAM, only SSRM is capable with sufficient spatial resolution and sensitivity to identify the structures and doping profiles. For the real case, SSRM analysis results clarified there is approximate 10nm difference on the junction depth between 2 different doping recipes of samples and the result is consistent with the Technology Computer Aided Design (TCAD) simulation data. In addition, both SCM and SSRM techniques showed the analysis quality does highly rely on the surface cleanness and flatness of samples.
FASTKIT—A Software Tool for Easy Design Visibility and Diagnostic Enhancement for Failure Analysis
Authors: Auvray Etienne , Armagnat Paul 
Published: December 2020

Abstract
The present work is relative to a new software suite that features design comprehension and analogic/logic tracing capability with ease of setup in FA laboratory environment. It also expands and correlates FA measure data to design functionality. With this visibility enhanced environment, we show that FA process can be performed more efficiently. Up to now, very few systems have been built with aim to cover advanced diagnosis setup and real-time navigation with synchronized simulation. We address a general FA software tool which purpose is to automate the design database setup and provide to FA engineer capability to launch reading of all design database including capability of generating new patterns compatible with analytical tools. Based on the flow, we propose a series of tools that will allow the FA engineer to work efficiently.