bluuebunny/crossref_metadata_2025_split huggingface dataset:
Educação Profissional e Tecnológica
Authors: Arruda Fabio Pinto de , Zanotello Marcelo 
Published: December 2020

A discussão em torno da Educação Profissional e Tecnológica ressurge no Brasil sob um cenário desafiador. Robôs, Inteligência Artificial e outras formas de tecnologia contribuem para a eliminação de postos de trabalho e ao mesmo tempo promovem o surgimento de novas profissões. O presente artigo analisa uma possível integração entre o ensino de ciências e práticas profissionais, através da realização de atividades investigativas, que colabore efetivamente na formação dos estudantes diante de tal situação. Trata-se de uma análise qualitativa de uma intervenção planejada por três estudantes, acompanhada pelo professor orientador e realizada no laboratório de uma faculdade pública de tecnologia situada no Município de São Paulo. A coleta de dados ocorreu durante seis meses e o material empírico consistiu na produção escrita e nas observações feitas durante experiências numa máquina de refrigeração. Observou-se ações de condicionamento promovida por várias situações, inclusive pelos métodos empíricos disseminados pelas empresas. Por outro lado, as mediações para integrar práticas científicas e profissionais evidenciaram a relevância do vínculo entre os objetivos da atividade de ensino e os motivos particulares da aprendizagem dos estudantes, notando-se indícios de atribuição de sentidos entre o fazer da prática e o pensar das ciências. Tais resultados, além de servirem como subsídios aos professores da educação tecnológica, ajudam a repensar possíveis caminhos à formação profissional dos trabalhadores diante dos desafios das novas profissões e dos saberes que elas exigem.

Palavras-chave: Educação profissional e tecnológica. Ensino de ciências. Práticas profissionais.
Ventas, mesones y posadas en el reino de Granada (s. XVIII)
Authors: Ruiz Álvarez Raúl 
Published: December 2020

El objetivo de este trabajo es realizar un primer balance, a partir de los datos que nos aporta el Catastro del Marqués de la Ensenada, sobre los establecimientos de hospedaje del reino de Granada en el siglo XVIII. Para ello se ha indagado en tres aspectos: en primer lugar, el estudio de la localización, señalando su distribución y analizando los caminos que van desde Granada a Málaga por Alhama de Granada y Vélez-Málaga, desde Granada a Madrid por Alcalá la Real y desde Granada a Levante y a Almería; en segundo lugar sobre la propiedad y los perfiles socioeconómicos de los propietarios; y por último, se han estudiado algunas cuestiones como su aprovechamiento o la utilidad que se les regulaba por el trabajo.Esta investigación nos permitirá conocer el mapa de hospederías del Reino en el siglo XVIII.
Reskilling Teachers and Reclaiming Our Schools
Authors: Schoorman Dilys , Minor Iris 
Published: December 2020

This paper describes the Educational Equity Partnership Project (EEPP), a multi-week five-module partnership in professional development (PD) involving approximately 50 teacher leaders in 32 Title 1 schools in the sixth largest school district in the United States. The EEPP was designed to support teacher leadership praxis in the quest for equity and social justice in public education. This study highlights the learning outcomes of the first three modules, focusing on culturally relevant pedagogy, multicultural curriculum development, and equity in schools. The analysis of participants’ survey data following each module revealed that critical consciousness emerged along four dimensions, with the key concepts serving as a lens for recognizing inequitable structures and critical self-reflection and enhancing participants’ sense of agency. The results underscore the need for educational professionals to commit to long-term, ongoing PD in critical multiculturalism, where critical consciousness and mindset shift are central to the professional capital developed.
Scanning Capacitance Microscopy Use in the Failure Analysis of Vcc Shorts in an Advanced Microprocessor
Authors: Scott Wills Kendall , Edwards Hal , Nuygen Long , Raghunathan Rohini , Todd Charles , Vance Andy 
Published: December 2020

Abstract
This article analyzes the cause of Vcc shorts in advanced microprocessors. In one instance, an advanced microprocessor exhibited Vcc shorts at wafer sort in a unique pattern. The poly silicon was narrow in one section of the die. The gates were shown to measure small, but no electrical proof of the short could be seen. To prove the short existed as a result of the narrow gate, a Scanning Capacitance Microscope (SCM) was utilized to confirm electrical models, which indicated a narrow poly silicon gate would result in Vcc shorts. High frequency dry etching and UV-ozone oxidation were employed for deprocessing. The use of the SCM confirmed the proof that the Vcc shorts were caused by narrow gate length which causes its leaky behavior. This conclusion could have only been confirmed by processing of material through the wafer foundry at the cost of money and time.
Embedded Memory Analysis for Standard Cell ASIC Yield Enhancement
Authors: Gloor Cary A. 
Published: December 2020

Abstract
The advances made in process technology along with system-on-a-chip capabilities have made failure analysis ever more difficult and expensive to perform. Quick product time-to-market and the required high fabrication yields demand top quality performance from the failure analysis team. In this paper we present a methodology for embedded memory analysis (EMA) which provides design, layout, and process characterization, and yield and reliability enhancement for standard cell ASIC products. The methodology takes the power of memory testing and failure signature analysis and brings it to the logic chip to accurately predict root cause defects. We also present the application tool that is used to query, bitmap, analyze, and report the data, along with numerous case histories. This process has greatly improved failure analysis hit rates and provided much quicker turn-times for process improvement feedback and customer return root cause analysis.
A Study on the Yield Loss Due to Al(Cu) Interconnections with Spacing Failure
Authors: Hwang Ruey Lian , Huang Yung-Sheng , Wang Ying-Lang , Lee Ming-Jer 
Published: December 2020

Abstract
This paper presents the results of a study on yield loss in wafers produced using a 0.25-μm CMOS process. It describes how the authors determined that a short in the M1 metal layer was the major yield killer and how they traced the cause to excess Cu that they believe migrated to the bottom of the Al(Cu)/TiN interface, forming θ-phase Al2Cu precipitates known to interfere with metal etching processes. It explains how TiN bridges, the result of incomplete etching, were observed between adjacent metal lines in failed die, confirming the authors’ theory and shedding light on potential solutions to the yield problem.
Near IR Absorption in Heavily Doped Silicon – An Empirical Approach
Authors: Falk R. Aaron 
Published: December 2020

Abstract
Backside failure analysis techniques rely heavily on transmission of near infrared (IR) radiation through the silicon substrate. This statement applies both to emission techniques and active laser probing. Heavy doping of substrates causes them to become highly absorptive in the near IR due to band gap shifts, which effects phonon-assisted absorption, and to free-carrier absorption. Substrate thinning is often required to allow adequate optical transmission. This paper describes an empirical approach to determining the absorption coefficient in a heavily doped substrate and use of the coefficient in determining the amount of substrate thinning required.
Backside Fault Isolation Using a Magnetic Field Imaging System on SRAMs with Indirect Shorts
Authors: Knauss L. A. , Frazier B. M. , Cawthorne A. B. , Budiarto E. , Crandall R. , Melnik S. , Bennett C. 
Published: December 2020

Abstract
With the arrival of flip-chip packaging, present tools and techniques are having increasing difficulty meeting failure-analysis needs. Recently a magneticfield imaging system has been used to localize shorts in buried layers of both packages and dies. Until now, these shorts have been powered directly through simple connections at the package. Power shorts are examples of direct shorts that can be powered through connections to Vdd and Vss at the package level. While power shorts are common types of failure, equally important are defects such as logic shorts, which cannot be powered through simple package connections. These defects must be indirectly activated by driving the part through a set of vectors. This makes the magnetic-field imaging process more complicated due to the large background currents present along with the defect current. Magnetic-field imaging is made possible through the use of a SQUID (Superconducting Quantum Interference Device), which is a very sensitive magnetic sensor that can image magnetic fields generated by magnetic materials or currents (such as those in an integrated circuit). The current-density distribution in the sample can then be calculated from the magnetic-field image revealing the locations of shorts and other current anomalies. Presented here is the application of a SQUID-based magnetic-field imaging system for isolation of indirect shorts. This system has been used to investigate shorts in two flip-chip-packaged SRAMs. Defect currents as small as 38 μA were imaged in a background of 1 A. The measurements were made using a lock-in thechnique and image subtraction. The magnetic-field image from one sample is compared with the results from a corresponding infrared-microscope image.
New Developments in IR Lock-In Thermography
Authors: Breitenstein O. , Rakotoniaina J.P. , Al Rifai M. Hejjo , Gradhand M. , Altmann F. , Riediger T. 
Published: December 2020

Abstract
Lock-in thermography based on an infrared camera has proven to be a useful tool for failure analysis of integrated circuits (ICs). This article discusses four novel technical developments of lock-in thermography. These developments are blackening the IC surface with colloidal bismuth, the synchronous undersampling technique allowing the use of higher lock-in frequencies, displaying the 0deg/-90deg signal as a novel high resolution emissivity corrected image type, and removing the thermal blurring effect by mathematically deconvoluting the 0deg/-90deg; signal. The effect of these techniques is demonstrated by using a regularly working operational amplifier (pA 741) and a damaged capacitor as test devices. It is shown that blackening the IC surface improves the detection sensitivity in metallized regions by up to a factor of 10, whereas the other methods allow improvement of the effective spatial resolution. The article also discusses which of the spatial resolution improvement techniques is most appropriate in different situations.
Advanced Fringe Analysis Techniques in Circuit Edit
Authors: Jain R.K. , Malik T. , Lundquist T.R. , Tsao C.-C. , Walecki W.J. 
Published: December 2020

Abstract
Novel Fabry Perot [1] fringe analysis techniques for monitoring the etching process with a coaxial photon-ion column [2] in the Credence OptiFIB are reported. Presently the primary application of these techniques in circuit edit is in trenching either from the front side or from the backside of a device. Optical fringes are observed in reflection geometry through the imaging system when the trench floor is thin and semi-transparent. The observed fringes result from optical interference in the etalon formed between the trench floor (Si in the case of backside trenching) and the circuitry layer beyond the trench floor. In-situ real-time thickness measurements and slope correction techniques are proposed that improve endpoint detection and control planarity of the trench floor. For successful through silicon edits, reliable endpoint detection and co-planarity of a local trench is important. Reliable endpoint detection prevents milling through bulk silicon and damaging active circuitry. Uneven trench floor thickness results in premature endpoint detection with sufficient thickness remaining in only part of the trench area. Good co-planarity of the trench floor also minimizes variability in the aspect ratios of the edit holes, hence increasing success rates in circuit edit.
Active Voltage Contrast for Failure Localization in Test Structures
Authors: Rosenkranz R. , Döring S. , Werner W. , Bartholomäus L. , Eckl S. 
Published: December 2020

Abstract
The common Passive Voltage Contrast (VC) localization method has its limits in the case of substrate contact chains. Because of leakage currents it is not possible to charge up the open part of the chain. In two case studies it is shown, how the Active Voltage Contrast (AVC) method in FIB and SEM can help to localize faults in such structures.
Deposition of Narrow, High Quality, Closely Spaced, but Isolated Conductors
Authors: Makarov V.V. , Jain R.K. 
Published: December 2020

Abstract
Developed procedures to deposit narrow (&lt;100nm), closely spaced, low resistance conductors which exhibit good electrical isolation are demonstrated. The process parameters which limit how narrow a line can be deposited and the methods used to work-around these are discussed. For these depositions, 3pA ion beam current was used with a Mo(CO)6 precursor chemistry. The deposition method minimized the incorporation of non-conductive precursor by-products. To isolate adjacent conductors, a copper etch Credence FIB chemistry was used. The advantages of this procedure over the common practice when XeF2 chemistry is used is also discussed and demonstrated.
Study of a Systematic Low DPPM Reliability Defect without Common Electrical Signature
Authors: Zhang Fubin 
Published: December 2020

Abstract
Possible reliability failure mechanisms on mixed-signal IC are reviewed and categorized. Based on the nature of reliability and low DPPM failures on mixed signal IC, an analysis flow is proposed including identification of individual failure mechanisms, extraction of the systematic problems, and implementation of corrective actions. Finally, a case of successful isolation of a specific defect without common electrical signature on mixed-signal devices is presented.
A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology
Authors: Lin Hung-Sung , Hou Ying-Chin , Fu Juimei , Wu Mong-Sheng , Huang Vincent , Chou Ching-Heng , Lin Jian-Chang 
Published: December 2020

Abstract
The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.
Voiding in Cu Technology through Photovoltaic-Driven Electrochemical Dissolution
Authors: Baiocchi Frank A. , DeLucca John , Cargo James T. 
Published: December 2020

Abstract
It has been found that a process-design interaction involving very large capacitor arrays is capable of causing voiding in well-formed copper trenches. This voiding is believed to be caused by the electrochemical dissolution of copper driven by the photovoltaic effect realized at p-n junctions. A series of experiments was performed to reproduce this voiding in a laboratory environment using water and exposure to light or dark. The experiments were performed on two different size capacitor arrays. In addition, similar experiments were performed on a large capacitor array that uses the opposite dopant isolation scheme. Conversely, copper dendrite growth was observed at the features of interest instead of dissolution, even under flowing de-ionized water (DI) conditions. The results are discussed in the context of known copper-water electrochemical equilibria and design implications are discussed.
Advanced Fault Isolation Technique Using Electro-Optical Terahertz Pulse Reflectometry (EOTPR) for 2D and 2.5D Flip-Chip Package
Authors: Cao Lihong , Venkata Manasa , Tay Meng Yeow , Qiu Wen , Alton J. , Taday P. , Igarashi M. 
Published: December 2020

Abstract
Electro-optical terahertz pulse reflectometry (EOTPR) was introduced last year to isolate faults in advanced IC packages. The EOTPR system provides 10μm accuracy that can be used to non-destructively localize a package-level failure. In this paper, an EOTPR system is used for non-destructive fault isolation and identification for both 2D and 2.5D with TSV structure of flip-chip packages. The experimental results demonstrate higher accuracy of the EOTPR system in determining the distance to defect compared to the traditional time-domain reflectometry (TDR) systems.
Building the Electrical Model of the Photoelectric Laser Stimulation of an NMOS Transistor in 90 nm Technology
Authors: Sarafianos A. , Llido R. , Gagliano O. , Serradeil V. , Lisart M. , Goubier V. , Dutertre J.M. , Tria A. , Pouget V. , Lewis D. 
Published: December 2020

Abstract
This paper presents the electrical model of an NMOS transistor in 90nm technology under 1064nm Photoelectric Laser Stimulation. The model was built and tuned from measurements made on test structures and from the results of physical simulation using Finite Element Modeling (TCAD). The latter is a useful tool in order to understand and correlate the effects seen by measurement by given a physical insight of carrier generation and transport in devices. This electrical model enables to simulate the effect of a continuous laser wave on an NMOS transistor by taking into account the laser’s parameters (i.e. spot size and power), spatial parameters (i.e. the spot location and the NMOS’ geometry) and the NMOS’ bias. It offers a significant gain of time for experiment processes and makes it possible to build 3D photocurrent cartographies generated by the laser on the NMOS, in order to predict its response independently of the laser beam location.
EOS (Electrical Overstress) – The Old, Unknown Phenomenon?
Authors: Jacob Peter 
Published: December 2020

Abstract
Frequently, Electrical Overstress (EOS) is understood in a similar context like Electrostatic Discharge (ESD). However, when looking deeper, only 3-5% of EOS failure signatures are caused by ESD. The dominant root causes can be found on system level – often inaccessible for the device failure analyst. However, switching procedures and sometimes-hidden inductance loads are the unconsidered and undiscovered problem makers. This paper reviews and highlights these failure mechanisms.
Advanced Laser Probe Techniques Applied to FA of RF Integrated Circuits - A Case Study
Authors: Kimball Mark , Nemirow Christopher 
Published: December 2020

Abstract
Failure analysis of RFIC’s can be a challenging problem, particularly as frequencies ascend into the medium to high GHz region. As frequency goes up, active probes become less and less accurate due to capacitive loading of circuit nodes, and capacitive coupling of stray signals into the probe from nearby circuit traces. We have found that Laser Voltage Imaging (LVi) offers an alternative measurement technique that can avoid these problems. But our work also showed that there are unusual failure signatures which appear as signal frequencies go up. A combination of LVI and RF-SDL was found to yield the best result.
Fluorosilicate Glass (FSG) Outgassing Induced Aluminum Bond Pad Corrosion during Post-Fab Wafer Storage
Authors: Younan Hua , Ramesh Rao Nistala , Shuting Chen 
Published: December 2020

Abstract
A case study of Fluorine (F)-outgassing is presented in this paper that caused the corrosion of Aluminum bond pad. It will be shown that the source of F-contamination is not the typical residue left behind after the passivation etch with Fluorine-based gas chemistry and the subsequent removal of the etch polymer generated with solvent (chemical) clean. Rather, it is introduced as a result of F-outgas over a period of time from the intermetallic dielectric (IMD) film, fluorosilicate glass (FSG), during the post-fab wafer storage. The methodology used in our failure analysis (FA) lab to identify and characterize this type of failure mode is presented in the paper.
Fault Localization Improvement through an Intra-Cell Diagnosis Approach
Authors: Sun Zhenzhou , Bosio Alberto , Dilillo Luigi , Girard Patrick , Todri Aida , Virazel Arnaud , Auvray Etienne 
Published: December 2020

Abstract
Logic diagnosis is the process of isolating the source of observed errors in a defective circuit, so that a physical failure analysis can be performed to determine the root cause of such errors. In this paper, we propose a new “Effect-Cause” based intra-cell diagnosis approach to improve the defect localization accuracy. The proposed approach is based on the Critical Path Tracing (CPT) here applied at transistor level. It leads to a precise localization of the root cause of observed errors. Experimental results show the efficiency of our approach.
Thermal Performance and Fabrication Improvements of Glass Interposer in 3D Packaging Systems
Authors: Faqir M. , Bouya M. , Bouissa Y. , Elamrani A. , Sbiaa Z. , Gandhi S. , Demir K. , Sundaram V. , Tummala R. 
Published: December 2020

Abstract
Our initial thermal study has provided preliminary results for glass and silicon interposers. Both glass and silicon have their advantages and disadvantages. The glass interposer provides good insulation but lower heat dissipation, while the silicon interposer has better heat dissipation. These results are extremely useful for the reliability of the 3D packaging systems. Concerning the glass interposer fabrication, we have used two laser drilling methods, the first one using Excimer laser and the second using the UV laser. The results obtained are both interesting and provide the required targets both in dimensions and form.
Failure Localization of an Electrical Transient Behavior on a Mixed-Mode IC by Using Static Emission Microscopy Technique
Authors: Sienkiewicz Magdalena , Huynh Estelle , Vidal Alain 
Published: December 2020

Abstract
This paper presents a case study on reliability reject on a Freescale mixed-mode IC. It focuses on a novel use of one of most frequently used failure localization techniques: static emission microscopy (EMMI) to localize a failure due to an electrical transient behavior. This work helped Freescale to identify a wafer fab process limitation and contributed to test improvement.
The Role of Free Carrier Absorption in LADA
Authors: Erington Kent , Bodoh Dan , Dickson Kris , Lange George 
Published: December 2020

Abstract
Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuit. In this paper, the characterization of continuous wave 1340nm laser induced currents and the LADA failure rate show that a two photon absorption explanation for the LADA effect is not plausible. The following sections confirm the results of a 28nm-node nMOS transistor using a 2.45NA solid immersion lens. The effects of global heating to that of local laser heating are then compared. The paper shows that the LADA response time to approximately 1300nm irradiation is &lt;&lt; 100ns. It explains LADA at approximately 1300nm, free carrier absorption in the silicon and in the local silicide layers, and presents selected 1320nm LADA images on 28nm-node devices. Finally, it shows 1064nm LADA images on the same structure that indicate that 1064nm interaction with transistors is related to free carrier absorption, rather than electron-hole pair creation.