bluuebunny/crossref_metadata_2025_split huggingface dataset:
Genetic Algorithm Applied to the Optimized Design of Semiconductor Microcavity Lasers
Authors: Coelho Fernando C. da Silva , Cotta E. A. , Vilela Neto Omar P. 
Published: December 2020

Semiconductor microcavities have been used in important studies of several areas for technological or purely scientific purposes. However, the definition of the optimal parameters for the fabrication of microcavities is a difficult task. Moreover, some uncertainties related to the growth process can change the device features. These problems cannot be experimentally controlled, hindering the development of theoretical models. In this work we present a theoretical model to simulate the microcavities and also propose an evolutionary approach to optimize the device under uncertainty in order to ensure the growth with the desired features. Thus, based on the reflectance spectra of a AlxGa1-xAs semiconductor microcavity, the aluminum concentrations, x, and the number of layers that compose the heterostructure were optimized. This set of parameters may offer increased robustness in the growth process, while providing a considerable quality factor and the desired position of the cavity resonance, achieving the device’s operation limits. The device was optimized considering the cavity resonance between 700nm and 2000nm, where the results indicate that the proposed algorithm is able to find satisfactory solutions, minimizing the problems caused by inaccuracy in the growth process.
MogaMap2: Multi-Objective Mapping Algorithm with parameter control for Optimize Area, Performance and Power Consumption in FPGA
Authors: Souza V. L. , Silva Filho A. G. 
Published: December 2020

This article presents a new technology mapper, MogaMap2, the second generation of the technology mapper, MogaMap, based on a hybrid approach that use evolutionary algorithm associated with specific heuristics of the problem in order to find better trade-off results among area, performance and power consumption. Different from MogaMap, the new approach includes a deterministic parameter control that, during the process, modifies the mutation probability. In a set of 20 large designs, we find that this adjust of parameter allow to reduce, in average, the LUT count in 2% and the edge count in 4%. In comparison to state-of-the-art technology mapping, our approach is able to reduce the LUT counts in 3% and the edges count in 10%. Placing and routing the resulting netlists leads to an 3% reduction in the complex logic blocks count, a 7% increasing in estimated operation frequency and 8% reduction in energy consumption.
A Simulation Methodology for Wirebonds Interconnects of Radiofrequency Integrated Circuits
Authors: Cavalcanti Hercílio M. , Manera Leandro 
Published: December 2020

This work presents a methodology for the simulation of bonding wires under the circumstance when signals with RF frequencies are employed and thus, the impedances of the parasitic resistances, capacitances and inductances of these interconnections are no longer negligible. A s-parameters extraction strategy for each of the wirebonds will be shown with the help of Agilent’s EM simulator ADS resulting in a netlist in spectre which will be used in the test-bench of the designed IC to emulate the behavior of the bondwires and thus making possible a proper dimensioning and tuning of the RF chip to ensure a better performance of the encapsulated RF IC. Finally the design example of a power amplifier is proposed and some aspects of the interaction of this block with the wirebonds are studied.
Drop-casted Graphene Oxide Love wave sensor for detection of humidity and VOCs
Authors: Nikolaou I. , Hallil H. , Plano B. , Deligeorgis G. , Conedera V. , Garcia H. , Dejous C. , Rebière D. 
Published: December 2020

The rising demand for sensitive analytical techniques have led to a great deal of research interest in the recent years, which has also generated much public awareness of health risks caused by environmental humidity and air pollution. This study reports advancements in highly-sensitive detection methods using Love wave devices fabricated from Graphene Oxide (GO). Under this, solutions of GO were prepared and used to achieve improved efficiency of the oxidation process and enhance the sensitivity of Relative Humidity (RH) and Volatile Organic Compounds (VOCs) detections. This work demonstrates that the detection limit of RH could be set very low due to the certain sensitivity levels. Similarly, GO prepared by us exhibited low detection limit for VOCs, proving the multi-functionality of GO rather than alternative sensing materials. The experiments conducted at room temperature and realized fast response and recovery times. This Love wave sensor provides high accuracy under full scale exposure of target analytes. Eventually, these ultrasensitive GO based devices can pave the way for a wide range of high-sensitivity detection applications.
Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net
Authors: Silveira J. , Cadore A. , Barroso G. , Marcon C. , Webber T. , Czekster R. 
Published: December 2020

Network-on-Chip (NoC) is a power architecture that emerged to solve communication issues present in modern Systems-on-Chip (SoCs). NoC based architectures are very scalable and offer high levels of communication parallelism, among other features. Every efficient NoC implementation requires several design steps to accomplish indices of performance. Although there are many system level models, high-level models for NoC are representative in the context of design since they provide fast and accurate analysis, with low modeling effort, for further VHDL implementations. This work proposes a NoC model based on a Timed Colored Petri Net (TCPN) that computes performance indices seamlessly. Network latency and buffer occupation are of special interest in our approach as they represent the key indices when assessing NoC performance. As results, we have validated and refined the model of a 5×5 mesh NoC comparing its indices with equivalent VHDL RTL description under synthetic and real traffic situations. The proposed model is capable of analyzing the influence of the router service time on the average latency time, enabling internal NoC evaluation to optimize buffer length. Simulation results demonstrate the model suitability for latency evaluation with time estimation errors often below 1%. Furthermore, this paper discusses the effort required to extend the model with other NoC architectural features. We conclude that the use of a TCPN model of NoC generates accurate results providing as much detailed information as their equivalent experiments using VHDL description.
An Approach for Power Estimation at Electronic System Level using Distributed Simulation
Authors: Oliveira Helder F. A. , Brito Alisson V. , Araujo Joseana M. F. R. , Melcher Elmar U. K. 
Published: December 2020

The present research aims to develop an approach using HLA (High Level Architecture), enabling the cre-ation of a distributed and heterogeneous environment, composed by different tools and models to obtain a better trade-off between accuracy and run time in power estimation. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, an MPSoC (MultiProcessor System-on-Chip) ESL/TLM model, described in C++/SystemC, and an ESL model, created on Ptolemy framework, have been used. The experimental results show the flexibility of the approach, which promotes an integrated view of power estimation data.
Fabrication and Characterization of Zeolitic Imidazolate Framework-90 (ZIF-90) Absorbers for Carbon Dioxide Sensing at Near Infrared Band
Authors: Volponi Ademauro , Dos Santos Filho Sebastião Gomes 
Published: December 2020

In this work, layers of crystalline zeolites formed by tetrahedrally-coordinated Zn ions bridged by imidazolate (ZIF-90) were deposited in order to investigate the desorption and absorption of CO2 and apply these layers as pre-concentrators for CO2 detection. For the deposition of ZIF-90 layers by casting, it was proposed an alternative chemical solution which employs ethanol as solvent instead of methanol, as reported in the literature, to provide a less toxic process to humans and allows one applications of CO2 storage. Several layers were deposited using a solution prepared from a mixture of zinc nitrate (4.3g) and 2-methylimidazole (9.7g) with several dilutions in ethanol to vary the pH in the range of 7.2 to 8.2. As a result, repetitive layers of approximately 7.5μm in thickness were deposited on the silicon wafers by casting. After annealing these layers at a temperature of 150 °C for 48h in ultra-pure nitrogen, nanocrystals with size distributions in the range of 5 to 400nm with a ZIF-90 crystal structure were achieved only for pH next to 7.2. From infrared (IR) measurements of the ZIF-90 layers, it was observed a band located at 2337cm-1 that increases with the increase of the CO2 pressure and with the exposure time to this pressure. In addition to the band at 2337cm-1, it was observed a second band at 2360 cm-1 indicating two different responses: (i) the band at 2337cm-1 is related to a substantial quantity of the CO2 molecules absorbed into the layer along the contours of the nanocrystals or within the crystal structure and (ii) the band at 2360cm-1 is related to the portion of CO2 molecules adsorbed on the surface. Also, if the ZIF-90 layer is exposed to CO2 at atmospheric pressure for at least 2h, a 10ppm sensitivity to CO2 is achieved considering the minimum absorbance as being 0.001 and the loading time at the atmospheric pressure as at least 20min.
Table of Contents and Foreword
Authors: Pavanello Marcelo Antonio 
Published: December 2020

We are pleased to publish the 2017 issues of JICS, which represents the third year in the path to increase visibility and attraction of high quality papers, by publishing three issues instead of two. In this issue one can find some of the papers that have been selected from those presented at SBMicro2016 (31st Symposium on Microelectronics Technology and Devices) and SBCCI2016 (29th Symposium on Integrated Circuits and Systems Design), which have been held in Belo Horizonte, Brazil, in 2016. Among the contributions presented at both Symposia, only a few best rated were selected by the JICS Editorial Board and have been invited to submit an extended version to the Journal. These extended papers have passed through the usual reviewing process before acceptance. In addition to the best papers presented at the conference, spontaneous submissions passed through the usual reviewing process and have been accepted as regular papers. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their valuable contribution on paper evaluation and selection, which guarantees the scientific level of this issue. We sincerely hope that JICS readers will enjoy these contributions.
Marcelo Antonio Pavanello - JICS Editor-in-chief
Advantageous Sampling of Correlated Current Signals to Supress Fixed-Pattern Noise in CMOS Imagers
Authors: Souza R. A. , Ventura L. G. M. , Martins A. R. S. , Monteiro D. W. de Lima , Salles L. P. 
Published: December 2020

The Active Pixel Sensor (APS) has been a vastly used integrated circuit topology in CMOS imagers. Mismatch of physical parameters among pixels, caused by process variations, introduces Fixed-Pattern Noise (FPN) at the array output. Correlated Double Sampling (CDS) in voltage mode is a commonly used method to suppress the offset caused FPN. However, it increases the complexity as well as the demanded silicon area of either the pixel or the external circuitry, besides having its signal swing restricted by the supply voltage. An alternative CDS circuit operating in current mode to reduce FPN is presented in this paper. The correlated current signals are sampled and subtracted using a simpler circuitry, leading to a more efficient relation of FPN reduction for the required silicon area. Furthermore, this technique does not change the APS topology or basic operation cycle. A simulated and tested CDS alternative is presented, and a simulated further improved version is proposed. Simulation and experiments showed a 40% FPN reduction with the fabricated CDS, whereas the improved simulated version ensures 90% FPN reduction.
Table of Contents and Foreword
Authors: Pavanello Marcelo Antonio 
Published: December 2020

This issue continues the publication of selected papers from those presented at SBMicro2016 (31th Symposium on Microelectronics Technology and Devices) and SBCCI2016 (29th Symposium on Integrated Circuits and Systems Design), which have been held in Belo Horizonte, Brazil, in 2016. Among the contributions presented at both Symposia, only a few best rated were selected by the JICS Editorial Board and have been invited to submit an extended version to the Journal. These extended papers have passed through the usual reviewing process before acceptance. In addition to the best papers presented at these conference, spontaneous submissions passed through the usual reviewing process and have been accepted as regular papers. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their valuable contribution on paper evaluation and selection, which guarantees the scientific level of this issue. We sincerely hope that JICS readers will enjoy these contributions.Marcelo Antonio Pavanello - JICS Editor-in-chief
Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies
Authors: Itocazu V. T. , Sonnenberg V. , Martino J. A. , Simoen E. , Clayes Cor 
Published: December 2020

This paper presents an analysis of the silicon film thickness (6 nm and 14 nm), the gate dielectric material (SiO2 and High- κ material) and the Ground Plane influence on the analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices, based on experimental and simulation results. Two channel lengths (70 nm and 1μm) have been considered and the analog performance has been analyzed as a function of the back gate bias. It is shown that at zero back gate bias , the presence of a Ground Plane improves the transconductance in the saturation region due to the strong coupling between front and back gates in devices with a long channel (1 μm), thin silicon film (6 nm) and SiO2 as gate dielectric material. However, for the intrinsic voltage gain, output conductance and Early Voltage, the devices without Ground Plane present better results due to the higher drain electrical field penetration. Short-channel transistors (70 nm) with Ground Plane show an improvement of the analog parameters also due to the high drain electrical field penetration. Similar behavior is noticed in devices with a thicker silicon film (14nm). UTBB nMOSFETs with High- κ material present less influence of a Ground Plane on the parameters analyzed. Varying the back gate bias in devices with long channel (1 μm) and SiO2 as gate dielectric material, the analog parameters present better results in devices without Ground Plane, except for the transconductance in long channel transistors with a thin silicon film, for the reason explained before (strong coupling between front and back gates). Devices with High-κ material as gate dielectric show a minor improvement of the analog performance with a Ground Plane.
Power Constrained Design Optimization of Analog Circuits Based on Physical gm/ID Characteristics
Authors: Girardi Alessandro , Bampi Sergio 
Published: December 2020

This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimization guide. Our custom layout tool LIT implements and uses the ACM MOS compact model in the optimization loop. The methodology is implemented for automation within LIT and exploits all design space through the simulated annealing optimization process, providing solutions close to optimum with a single technology-dependent curve and accurate expressions for transconductance and current valid in all operation regions. The compact model itself contributes to convergence and to optimized implementations, since it has analytic expressions which are continuous in all current regimes, including weak and moderate inversion. The advantage of constraining the optimization within a power budget is of great importance for low-power CMOS. As examples we show the optimization results obtained with LIT, resulting in significant power savings, for the design of a folded-cascode and a two-stage Miller operational amplifier.
Buffer Sizing for Multimedia Flows in Packet-Switching NoCs
Authors: Tedesco Leonel P. , Calazans Ney , Moraes Fernando 
Published: December 2020

Wormhole packet switching, used in many NoC designs, introduces jitter. This may produce violations of application deadlines. Several works in the literature propose stream workload models, and techniques for buffer sizing. These works do not consider the concurrency between different flows, or the NoC model is too abstract, masking the jitter introduced by data packaging and router processing. One technique to deal with jitter is to introduce a decoupling buffer (D-buffer) on the target IP. This buffer receives data from the NoC with jitter, while the target IP consumes data from this buffer at the application rate, without jitter. Two problems must be solved to implement D-buffers: (i) which size must the buffer have? (ii) how much time should be expected before data consumption starts (threshold)? This work proposes a general method to define D-buffer size and threshold, considering the influence of packaging, arbitration, routing and concurrency between flows. A traffic model for stream applications is detailed and used to characterize jitter sources in wormhole packet switching. Experimental results demonstrate the impact on multimedia flows with fixed and variable packet sizes (from real traffic traces). Simple traffic models employing constant frame sizes result in small D-buffers. On the other hand, employing multimedia frames from application traces (i.e. real application data) increases buffer size and threshold while still suppressing jitter. Another parameter analyzed in the paper is the percentage of deadline violations as a function of D-buffer size. The method guarantees throughput with no deadline violation and does not modify the NoC structure. The cost of adding such D-buffers is an increased latency and extra silicon area.
Stress Analysis on Ultra Thin Ground Wafers
Authors: Teixeira Ricardo C. , De Munck Koen , De Moor Piet , Baert Kris , Swinnen Bart , Van Hoof Chris , Knüettel Alexsander 
Published: December 2020

Grinding wafers is a well established process for thinning wafers down to 100 μm for use in smart cards and stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in Si wafers thinned down to ~20μm by means of an IR time-of-flight like technique. Such aggressive thinning is a requirement for high density vias interconnect, stacked die packaging and flexible electronics. We found that the thinning process used did not add significant stress value on the thinned wafer.
Tradeoff of FPGA Design of a Floating-point Library for Arithmetic Operators
Authors: Mu`ñoz Daniel M. , Sanchez Diego F. , Llanos Carlos H. , Ayala-Rincón Mauricio 
Published: December 2020

Many scientific and engineering applications require to perform a large number of arithmetic operations that must be computed in an efficient manner using a high precision and a large dynamic range. Commonly, these applications are implemented on personal computers taking advantage of the floating-point arithmetic to perform the computations and high operational frequencies. However, most common software architectures execute the instructions in a sequential way due to the von Neumann model and, consequently, several delays are introduced in the data transfer between the program memory and the Arithmetic Logic Unit (ALU). There are several mobile applications which require to operate with a high performance in terms of accuracy of the computations and execution time as well as with low power consumption. Modern Field Programmable Gate Arrays (FPGAs) are a suitable solution for high performance embedded applications given the flexibility of their architectures and their parallel capabilities, which allows the implementation of complex algorithms and performance improvements. This paper describes a parameterizable floating-point library for arithmetic operators based on FPGAs. A general architecture was implemented for addition/subtraction and multiplication and two different architectures based on the Goldschmidt’s and the Newton-Raphson algorithms were implemented for division and square root. Additionally, a tradeoff analysis of the hardware implementation was performed, which enables the designer to choose, for general purpose applications, the suitable bit-width representation and error associated, as well as the area cost, elapsed time and power consumption for each arithmetic operator. Synthesis results have demonstrated the effectiveness of the implemented cores on commercial FPGAs and showed that the most critical parameter is the dedicated Digital Signal Processing (DSP) slices consumption. Simulation results were addressed to compute the mean square error (MSE) and maximum absolute error demonstrating the correctness of the implemented floating-point library and achieving and experimental error analysis. The Newton-Raphson algorithm achieves similar MSE results as the Goldschmidt’s algorithm, operating with similar frequencies; however, the first one saves more logic area and dedicated DSP blocks.
Packet-driven General Purpose Instruction Execution on Communication-based Architectures
Authors: Fernandes Silvio R. , Silva Ivan S. , Kreutz Marcio 
Published: December 2020

In the last few years, the development of Multi-Core architectures was driven by the crescent advance in integration technology. In this scenario, when the number of cores increases, problems found on shared communication media, such as busses, can be addressed by using a network approach. This paper proposes the usage of communication capabilities of Networks-on-Chip (NoCs) to execute general purpose instructions. The main idea behind this approach is to allow networks-on-chip architectures to execute general purpose instructions inside each router architecture. This paper addresses the main architectural concerns involved on creating datapaths for routers as well as the programming model suggested to pack instructions on messages. Simulation results on two case studies illustrate the benefits of the proposed architecture when compared to an equivalent NoC-based MP-SoC.