bluuebunny/crossref_metadata_2025_split huggingface dataset:
Conductance of Single- and Double-Gated Quantum Stub Transistor
Authors: Guerra Alexandre B. , Santos Edval J. P. 
Published: December 2020

Quantum stub transistors are low power, high frequency, and nanometer-size devices, and as such they are candidates for next generation electronic devices. In particular, such structures may be used in spintronics-based quantum computation, because of its ability to induce spin-polarized transport. In this paper, we present the simulation of the conductance of the quantum stub transistor (single and double-gated), modeled with a nearest-neighbor tight-binding Hamiltonian. The results suggest how the electrical behavior of the quantum stub transistor may be improved.
The Effect of Nitrogen Concentration at Oxynitride Gate Insulators Formed by 28N2 + Implantation into Silicon with Additional Conventional or Rapid Thermal Oxidation
Authors: Felício A. G. , Diniz José Alexandre , Godoy Fo. J. , Doi I. , Pudenzi M. A. A. , Swart Jacobus W. 
Published: December 2020

Silicon oxynitride (SiOxNy) insulators have been obtained by nitrogen ion implantation into Si substrates prior to conventional or rapid thermal oxidation. These films have been used as gate insulators in nMOSFETs and MOS capacitors. nMOSFET electrical characteristics, such as field effect mobility between 390 cm2/Vs and 530 cm2/Vs, and sub-threshold slope between 70 mV/decade and 150 mV/decade, were obtained. MOS capacitors were used to obtain capacitance-voltage (C-V) and current-voltage (I-V) measurements. The Equivalent Oxide Thickness (EOT) of the films were obtained from C-V curves, resulting in values between 2.9 nm and 12 nm. SiOxNy gate insulators with EOT between 2.9 nm and 4.3 nm have presented gate leakage current densities between 3 mA/cm2 and 50 nA/cm2. The electrical characteristics were compared and correlated with the nitrogen concentration profiles at SiOxNy/Si of the structures, obtained by Secondary Ion Mass Spectrometry (SIMS).
Study Of MOS Capacitors With TiO2 And SiO2/TiO2 Gate Dielectric
Authors: Albertin Katia F. , Valle M. A. , Pereyra I. 
Published: December 2020

MOS capacitors with TiO2 and TiO2/SiO2 dielectric layer were fabricated and characterized. TiO2 films where physical characterized by Rutherford Backscattering, Fourier TransformInfrared Spectroscopy and Elipsometry measurements. Capacitance-voltage (1MHz) and current voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness (EOT), leakage current density and interface quality. The results show that the obtained TiO2 films present a dielectric constant of approximately 40, a good interface quality with silicon and a leakage current density, of 70 mA/cm2 for VG = 1V, acceptable for high performance logic circuits and low power circuits fabrication, indicating that this material is a viable substitute for current dielectric layers in order to prevent tunneling currents.
A 40 MHz 70 dB Gain Variable Gain Amplifier Design Using the gm/ID Design Method
Authors: Cortes Fernando Paixão , Bampi Sergio 
Published: December 2020

This paper addresses the design and post-fabrication measurements of a 40 MHz CMOS Variable Gain Amplifier (VGA) with a 0 to 70 dB gain control range, using the gm/ID design methodology. The VGA architecture is based on a differential pair stage with an automatic continuous-time offset cancellation circuitry, providing an input offset voltage tolerance up to 50 mV. The 3-stage VGA was designed and fabricated through MOSIS service in an IBM 0.18 μm CMOS process. The VGA dissipates 2.6 mA from a 1.8 V supply, with 34,840 μm2 circuit area, excluding bond-pads.
Efficient and Flexible Dynamic Reconfiguration for Multi Context Architectures
Authors: Lallet Julien , Pillement Sébastien , Sentieys Olivier 
Published: December 2020

Dynamic reconfiguration is possible on both fine-grain and coarse-grain architectures. One of the used methodology used consists in the use of multi-context architectures. Unfortunately, the multiple contexts bring power and area overhead. This paper introduces the Dynamic Unifier and reConfigurable blocK (DUCK) concept, a new structure to perform efficiently dynamic reconfiguration on both custom designed fine-grain and coarse grain architectures. The DUCK allows to separate the configuration path and the configuration registers which facilitates simultaneous configuration and computing steps. The reconfiguration process is presented in detail, and synthesis results are given for different structures. Our solution is finally validated with the implementation of a WCDMA (Wideband Code Division Multiple Access) receiver on a multi-context embedded FPGA and on the dynamically reconfigurable processor DART. This implementation demonstrates the interest and the efficiency of the use of dynamic reconfiguration and the proposed flexible structure.
Analysis of Electromigration in Dual-Damascene Interconnect Structures
Authors: De Orio Roberto Lacerda , Ceric Hajdin , Selberherr Siegfried 
Published: December 2020

The effects of grain boundaries on electromigration failure are presented. The electromigration model incorporates the grain boundary as a separate medium which acts not only as fast diffusivity path for material transport but also absorbs and releases vacancies. Moreover, we analyze the void nucleation condition and its implication on electromigration failure is discussed. Our results show that high stress and a high vacancy concentration develop at the triple points formed on the interface between copper grains and the capping layer, where a void nucleation is likely to take place. This scenario of weak triple points in combination with a stress threshold also supports the mechanism of multiple void nucleation as it has been experimentally observed.
Table of Contents and Foreword
Authors: Martino João Antonio , Lubaszewski Marcelo 
Published: December 2020

This issue of Journal of Integrated Circuits and Systems (JICS) includes papers on process, materials, devices, and modeling. These papers have been selected from the presentations given at SBMicro2009 (24th Symposium on Microelectronics Technology and Devices), which has been held in Natal, Brazil in 2009. Among the contributions presented at SBMicro2009 conference, only a few best rated by the reviewers were selected by the JICS Editorial Board and have been invited to submit an extended version. These papers have been submitted to usual reviewing process with the help of external experts. In this issue also spontaneous submissions have been considered. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection, which guarantees the scientific level of this issue.We sincerely hope that JICS readers will enjoy these contributions.João Antonio Martino - JICS Editor-in-chiefMarcelo Lubaszewski - JICS Co-Editor
Impact of Selective Epitaxial Growth and Uniaxial/Biaxial Strain on DIBL Effect Using Triple Gate FinFETs
Authors: Dos Santos Sara Dereste , Martino João Antonio , Simoen Eddy , Claeys Cor 
Published: December 2020

The influence of Selective Epitaxial Growth (SEG) and the Uniaxial and Biaxial Strain are studied in triple gate FinFETs, analyzing the Drain Induced Barrier Lowering Effect (DIBL). The splits using SEG present better performance for strained devices than the unstrained ones but the inverse is observed for devices without SEG. The DIBL values are higher for SEG devices in all cases. For devices without SEG, the effect of mechanical stress is more pronounced and the mobility is higher in the uniaxially strained devices. These devices have lower VT values in the saturation condition causing the highest DIBL.
A 5.4 GHz Fully-Integrated Low-Noise Mixer
Authors: Ho Stanley S. K. , Saavedra Carlos E. 
Published: December 2020

An active mixer using a Gilbert-cell topology that incorporates a low-noise RF transconductance stage is presented in this paper. The chip operates at a frequency of 5.4 GHz and was fabricated in 180 nm CMOS technology. A current-bleeding circuit is used to provide different dc bias currents to the LO switching stage and the RF transconductors. The transconductor, designed using the power constrained simultaneous noise and input match technique, together with the bleeding circuit enables the mixer to have a measured single-sideband noise figure of 7.8 dB and a power conversion gain of 13.1 dB. The measured input-referred 1-dB compression point, IP1dB is -17.8 dBm while its OP1dB is -5 dBm. A two-tone test was carried out and the mixer exhibits an IIP3 of -6.2 dBm and an OIP3 of +6.9 dBm. All of the inductors are on-chip and the size of the mixer core is only 380 μm x 350 μm (0.133 mm2).
A GALS Pipeline DES Architecture to Increase Robustness against CPA and CEMA Attacks
Authors: Soares Rafael I. , Calazans Ney L. V. , Lomné Victor , Dehbaoui Amine , Maurine Philippe , Torres Lionel 
Published: December 2020

Side channels attacks (SCAs) are very effective and low cost methods to extract secret information from supposedly secure cryptosystems.The traditional synchronous design flow used to create such systems favors the leakage of information, which enables attackers to draw correlations between data processes and circuit power consumption, electromagnetic radiation or other sources of leakage. By using well known analysis techniques, these correlations may allow that an attacker retrieves secret cryptographic keys. Differential Power Analysis (DPA) and Differential Electromagnetic Analysis (DEMA) are among the most cited attack types. More accurate types of attacks have been proposed, including Correlation Power Analysis (CPA) that associates power quantities with a specific power model. In recent years, several countermeasures against SCAs have been proposed. Fully asynchronous and globally asynchronous locally synchronous (GALS) design methods appear as alternatives to design tamper resistant cryptosystems. However, according to previous works they use to achieve this with significant area, throughput, latency and power penalties and are not absolutely secure. This paper proposes a new GALS pipeline architecture for the Data Encryption Standard (DES) that explores the trade-off between circuit area and robustness to SCAs. Robustness is enhanced by replicating the DES hardware structure in asynchronously communicating module instances, coupled with self-varying operating frequencies. Designs prototyped on FPGAs with the proposed technique presented promising robustness against attacks, after submitted to differential and correlation analyses. This is true for both power and electromagnetic channels. Additionally the proposed architecture displays throughput superior to previously reported results.
A Novel Macroblock-Level Filtering Upsampling Architecture for H.264/AVC Scalable Extension
Authors: Da Silva Thaísa L. , Cruz Luis A. S. , Agostini Luciano V. 
Published: December 2020

The scalable extension of the H.264/AVC standard, also called H.264/AVC SVC standard or simply SVC standard uses spatial upsampling in the spatial scalability modes. This work presents a novel upsampling architecture designed for operation at macroblock level and dyadic upsampling ratio with QVGA as the base layer resolution and VGA as the enhancement resolution.The adoption of a macroblock-level solution translates into a more efficient use of hardware resources with savings of approximately 25% in the number of ALUTs and DLRs and using about two hundred times less memory bits, when compared to previously published works. The designed architecture was synthesized targeting four FPGAs: Altera Cyclone III and Stratix IV and Xilinx Spartan 3E and Virtex 4. The best throughput was reached by the Xilinx Virtex 4 device, with a processing rate of 506 VGA frames per second. The worst result was reached by the Xilinx Spartan 3E FPGA, with 249 VGA frames per second. All target FPGAs surpasses the necessary throughput to decode VGA videos in real time. This very high throughput is important especially when low power applications are considered, since with low operation frequencies (9.34MHz) it is possible to reach real time (30 frames per second) for all target FPGAs.
Table of Contents and Foreword
Authors: Lubaszewski Marcelo , Pavanello Marcelo Antonio 
Published: December 2020

This issue of the Journal of Integrated Circuits and Systems (JICS) features a very broad content, including papers on multiple gate devices, sensors, polymers and silicon photodiodes. Six of these papers have been selected from the presentations given at SBMicro2010 (25th Symposium on Microelectronics Technology and Devices), which has been held in São Paulo, Brazil in 2010. Among the contributions presented at Symposium, only a few best rated were selected by the JICS Editorial Board and have been invited to submit an extended version to the Journal. These papers have been reviewed by external experts and have been accepted for the special section on best SBMicro2010 papers. In addition to the best papers presented at the conference, spontaneous submissions passed through the usual reviewing process and have been accepted as regular papers. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection, which guarantees the scientific level of this issue. We sincerely hope that JICS readers will enjoy these contributions.Marcelo Lubaszewski - JICS Editor-in-chiefMarcelo Antonio Pavanello - JICS Co-Editor
Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion
Authors: Doria Rodrigo T. , Pavanello Marcelo Antonio , Trevisoli Renan D. , De Souza Michelly , Lee Chi-Woo , Ferain Isabelle , Akhavan Nima D. , Yan Ran , Razavi Pedram , Yu Ran , Kranti Abhinav , Colinge Jean-Pierre 
Published: December 2020

This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.
Electrochemical Migration on Lead-Free Soldering of PCBs
Authors: Mendes Luiz Tadeu Freire , Cardoso Valtemar Fernandes , Da Silva Ana Neilde Rodrigues 
Published: December 2020

It is well known that in printed circuits boards assembled by SMT technology may occur Electrochemical Migration (ECM). This phenomenon appears mainly because the new packaging has the terminals very close. Also the Electrochemical Migration may become a potential reliability problem in electronic soldering when lead free technology is used in soldering electronic devices. Electrochemical Migration is an electrochemical process where metal on an insulating material, in a humid environment and under an applied electric field, leaves its initial location in ionic form and redeposit. In a PCB two adjacent terminals may behave as electrodes so the dendrites grow from cathode to anode. It can show different morphologies with the different migration elements involved depending on the solder paste composition or PCB surface finishing. A structure with a comb shape printed on FR4 substrate was used in the experiments. The distance between the fingers in the structure was 102 or 254 micron, in order to simulate a real distance between dispositive terminals. The factors considered during the experiments were surface finishing (ENIG or HASL), solder paste composition, distance between terminals (102 or 254 micron) and applied voltage (2 or 3 V). All the experiments were done two times. It was observed that the solder paste and the surface finishing don’t influences the ECM process. Tin was the main metal that migrates. All the results obtained in these study agrees with the literature.
Distributed Shared Mamory for NoC-based MPSoCs
Authors: Chaves Tales Marchesan , Moraes Fernando Gehm 
Published: December 2020

As the number of cores and functionalities integrated in embedded devices increases, the amount of memory used on these devices also increases, justifying the development of memory architectures that present scalability, low energy consumption and low latency. Two factors impact the scalability of MPSoC systems: cache access latency and energy consumption. The distance of the processors to the cache banks and the cache coherence protocol influences both factors. This work proposes a physically distributed data L2 cache as the cache architecture for a NoC-based MPSoC, because it allows the concept of clustering, and the implementation of data migration algorithms to reducing cache access latency. Results show that the number of cycles required to execute a given application might reduce 23% with the appropriate number of L2 cache banks. Also, a directory-based cache coherence protocol was implemented, exploiting the NoC physical services to improve performance. Results show a reduction of 17% in the number of clock cycles and a reduction up to 86% (average reduction: 39%) in energy consumption for some cache transactions.
A Simple Electron Mobility Model Considering the Silicon-Dielectric Interface Orientation for Circular Surrounding-Gate Transistor
Authors: Perin André L. , Pereira Arianne S. N. , Agopian Paula Ghedini Der , Martino João Antonio , Giacomini Renato 
Published: December 2020

In this work, a simple model that accounts for the variation of electron mobility as a function of the silicondielectric interface crystallographic orientation is presented. Simulations were conducted in order to compute the effective mobility of planar devices and its results were compared to experimental data for several interface orientations. The error between experimental data and the proposed model remained bellow 4%. The model has been applied to nMOS circular surrounding gate (thin-pillar transistor - CYNTHIA) and allowed the observation of current density variations as a function of the interface orientation around the silicon pillar.
One Transistor Floating Body RAM Performances on UTBOX Devices Using the BJT Effect
Authors: Almeida Luciano M. , Sasaki Katia R. A. , Aoulaiche M. , Simoen Eddy , Clayes Cor , Martino João Antonio 
Published: December 2020

This work aims to analyze through 2D numerical simulations the minimum drain bias for the onset of the parasitic bipolar transistor (BJT) effect (VLatch) of a Ultra-Thin-Buried-Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) transistor used as a Single-Transistor-Dynamic-Random-Access-Memory (1TDRAM) cell at high temperatures. The buried oxide thickness (tBOX) and silicon film thickness (tSi) variation were also taken into account and initial studies of the retention time (RT) and the data degradation have been performed. It was verified that the latch voltage, the sense margin current, the latch time and the retention time decrease as the temperature rises.
Pressure Sensor Systems for Wide Pressure Ranges Integrated by a Combined CMOS- and MEMS- Technology
Authors: Schreiber-Prillwitz Wolfgang , Job Reinhart 
Published: December 2020

Monolithic integrated pressure sensor systems are realized by the combination of two different technologies: CMOS-technology for the electrical part and MEMS-technology for the pressure sensor part. The paper describes the modification of such pressure sensor systems to extend their original nominal pressure range from 600 mbar to the low pressure range of 40 mbar by keeping a sufficient signal to noise ratio and without changing the original mask set. The general methodology is described, and a comparison between theoretical signal evaluation and measurement is given. The study concentrates on the aspect of the different piezocoefficients for various Boron doping concentrations of the piezoresistors
A Novel Pseudo NMOS Integrated CC -ISFET Device for Water Quality Monitoring
Authors: Whig Pawan , Ahmad Syed Naseem 
Published: December 2020

The paper presents a performance analysis of Novel CMOS Integrated Pseudo NMOS CC –ISFET (PNCC-ISFET) having zero static power dissipation. The main focus is on simulation of power and performance analysis along with the comparison with existing devices, which are used for water quality monitoring. This approach can improve calibration of device to a fairly wide range without the use of a high speed digital processor. The conventional devices generally used, consume high power and are not stable for long term monitoring. The conventional devices have a drawback of low value of slew rate, high power consumption, and non linear characteristics. In the proposed design(PNCC-ISFET) due to zero static power, low value of load capacitance on input signals, faster switching, use of fewer transistors and higher circuit density the device exhibits a better slew rate, piece-wise linear characteristic, and is seen consuming low power of the order of 30mW. The functionality of the circuit is tested using Tanner simulator version 15 for a 70nm CMOS process model. The proposed circuit reduces total power consumption per cycle, increases speed of operation, is fairly linear and simple to implement. This device has a simple architecture, and hence is very suitable for water quality monitoring applications.
Nanowire Tunnel Field Effect Transistors at High Temperature
Authors: Martino Márcio D. V. , Neves Felipe S. , Agopian Paula Ghedini Der , Martino João Antonio , Rooyackers Rita , Claeys Cor 
Published: December 2020

The aim of this work is to study how the performance of nanowire tunnel field effect transistors (TFETs) is influenced by temperature variation. First of all, simulated energy band diagrams were presented to justify its fundamental working principle and this analysis was compared to experimental data obtained for temperature ranging from 300 to 420 K. This methodology was performed for different nanowire diameters and bias conditions, leading to a deep investigation of parameters such as the ratio of on-state and off-state current (ION/IOFF) and the subthreshold slope (S). Three different transport mechanisms (band-to-band tunneling, Shockley-Read-Hall generation/recombination and trap-assisted tunneling) were highlighted to explain the temperature influence on the drain current. As the final step, subthreshold slope values for each configuration were compared to the room temperature. Therefore, it was observed that larger nanowire diameters and lower temperatures tended to increase ION/IOFF ratio. Meanwhile, it was clear that band-to-band tunneling prevailed for higher gate voltage bias, resulting in a much slighter temperature effect on the drain current.
A CMOS Bandgap Reference Circuit with a Temperature Coefficient Adjustment Block
Authors: Ishibe Eder Issao , Navarro João 
Published: December 2020

A bandgap reference voltage source with a temperature coefficient adjustment block was proposed. The bandgap topology employs current summation and the circuit was designed through metaheuristic algorithms in a 0.35-mm CMOS technology. Simulations with typical parameters show that the designed circuit has temperature coefficient of 15 ppm/0C, line regulation of 263 ppm/V, and current consumption of 2.71 uA in 1.0 V power supply. An additional 3-bit temperature adjustment block allowed keeping the temperature coefficient values lower than 26.6 ppm/0C for 90% of the circuits, without interfering with the reference voltage output or line regulation values.