bluuebunny/crossref_metadata_2025_split huggingface dataset:
(Invited) Advanced Photonic Circuits Using III-V Semiconductors
Authors: Tauke-Pedretti Anna , Vawter G. Allen , Skogen Erik , Peake Gregory , Overberg M. E. , Alford Charles , Cajas Florante 
Published: February 2020

Advances in photonic integrated circuits (PICs) have enabled increased system performance and new photonic system capabilities. Integration leads to reductions in SWaP (size, weight and power) and packaging costs, while increasing reliability and mechanical robustness when compared to discrete components. The unique characteristics of compound semiconductors enable monolithically integrated PICs with efficient integrated light sources, amplifiers and high performance modulators and detectors. Additionally, specialized discrete devices can be heterogeneously integrated with other photonic circuits to form more complex circuits.
Sandia has developed a fundamental capability in InP-based PICs that enables the monolithic integration of a diverse set of lasers, modulators (both phase-based and absorption-based), photodetectors, amplifiers (both high-gain and high-saturation power varieties) and routing waveguides, in addition to electrical passive components such as resistors, capacitors, and transmission lines.The foundation of the capability is quantum-well-intermixing which enables the realization of multiple bandedges to be formed across the wafer with very low optical reflections (<1 dB) at the interfaces [1], coupled with simple blanket MOCVD regrowths
This InP-based PIC platform allows for high performance components including >40 Gbps EAMs (electroabsorption modulators) and photodetectors [2], <1 GHz passband optical filters and wavelength-tunable lasers with >40 dB side mode suppression ratio on a single monolithic chip.This variety of devices enables the creation of unique, highly-functional PICs for a variety of applications. In addition, this PIC technology can also be combined with photonic technologies, including Si photonics, using heterogeneous integration to reduce costs and expand the application space.
Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

References

[1] E.J. Skogen, J.S. Barton, S.P. DenBaars, and L.A. Coldren, “A Quantum-Well-Intermixing Process for Wavelength-Agile Photonic Integrated Circuits,” IEEE Journal of Sel. Topics in Quantum Electronics, Vol. 8, No. 4, 863-869 (2002).
[2] E.J. Skogen, G.A. Vawter, A. Tauke-Pedretti, C.R. Alford, M.E. Overberg, and C.T. Sullivan, “Integrated Guided-Wave Photodiode Using Through-Absorber Quantum-Well-Intermixing”, IEEE Photonics Technology Letters, 25, (17), pp.1684-1686 (September 1, 2013).
(Invited) Surface Activated Wafer Bonding; Principle and Current Status
Authors: Takagi Hideki , Kurashima Yuichi , Suga Tadatomo 
Published: February 2020

The surface activated bonding method originally uses cleaning of material surfaces by sputter etching using high energy ion/atom beam of inert gases, typically Ar. [1] The cleaning process removes adsorbed atoms and compound layers, typically oxides, which stabilize the surface. Therefore, after the cleaning process the surfaces become unstable “active” states. Mating two such activated surfaces in vacuum enables strong bond formation even at room temperature. This process is quite suitable for the wafer direct bonding. Because intimate contact is automatically achieved at the bonding interface by attractive force between two atomically smooth surfaces of polished wafers, the process requires not only heating process but also pressure application. [2,3]
This method has been successfully applied to various semiconductor wafers such as Si, GaAs, SiC, etc. [4,5] Most of the metals can be also bonded by the method in case of atomically smooth surfaces of, for example, metal layers finished by CMP and/or thin metal films deposited on well-polished wafers. [6,7] On the other hand, materials such as SiO2 and polymers cannot be directly bonded by the method. To bond such materials, deposition of very thin intermediate layers of metals or Si has been proposed. [8] The deposited metal atoms firmly adhere to the surface of SiO2 and/or polymers and simultaneously form active metal surface. The thin film deposition is regarded as a new process for the surface activation. This means that the concept of the surface activated bonding has been extended in order to apply the method to wide range of materials.
Various applications of the surface activated bonding have been developed in the field of wafer-level packaging and engineered substrates. In wafer-level packaging field, various MEMS devices have been already commercialized and 3D-integration of heterogeneous devices are under investigation. In engineered substrate application, RF filters have been already commercialized and still succeeding developments continue. Engineered substrates for micro-electronics, power-electronics, solar cells, etc. are now extensively developed by the method. We believe the surface activated bonding will be used in wide range of technological fields in the near future.
[1] T. Suga, et al., Acta Metall. Mater. 40 (1992) S113.
[2] H. Takagi, et al., Appl. Phys. Lett. 68(1996) 2222.
[3] H. Takagi, et al., Sens. Actuat. A 105 (2003) 98.
[4] M. M. R. Howlader, et al., J. Vac. Sci. Technol. B 19(2001) 2114.
[5] J. Suda, et al., Proc ICSCRM 2013, Miyazaki, Japan, (2013) 358.
[6] A. Shigetou, et al., J. Mater. Sci. 40 (2005) 3149
[7] T. Shimatsu, et al., J. Vac. Sci. Technol. B 28(2010) 706.
[8] R. Kondou, et al., Scripta Materialia 65(2011) 320.
A Study of Void Formation in Fluorine Containing Plasma Activated Wafer Bonding
Authors: Wang Chenxi , Liu Yannan , Suga Tadatomo 
Published: February 2020

Plasma activated bonding is one of promising candidates in wafer bonding field. In the past decade, much progress in terms of plasma generation, plasma treatment parameters, and annealing conditions has been achieved to allow high strength bonding at low temperatures with minimal defects. Since wafer bonding is often used as a middle process during device manufacturing, subsequent heated (or annealing) processes are inevitable for bonded wafers. However, void generation in annealing process (known as “annealing void”) is a serious problem in plasma activated bonding, especially for Si/Si wafer pairs. In particular, voids more frequently occur and are significantly severer as the wafer sizes further increase. Recently, our group has developed a fluorine activated bonding process enabling strong bonding of Si/Si bonded pairs (~2.2 J/m2 in surface energy) even at room temperature (~25ºC) without requiring annealing by introducing a small amount of carbon tetrafluoride (CF4) into oxygen plasma treatments. It seems that the fluorinated oxide allows water and hydrogen to diffuse out more easily from the interface at room temperature. But we have no idea how voids would be generated in elevated temperatures during subsequent annealing process. In this work, we demonstrate a quantitative evaluation of the void formation. As a comparison, void generation in the samples prepared by O2 plasma activated bonding is also systemically investigated. The void formation model is proposed to gain insight the mechanism of the fluorine containing plasma activated bonding.
8-inch silicon wafers (i.e. 200-mm diameters) were used in the experiments. To inspect void formation, a couple of bonded wafer pairs were prepared with different plasma treatment conditions. All the bonded wafer pairs were heated at 200, 300, 400, 500, 600, 700, and 800ºC for 8 h in ambient air. The heating steps do not aim to improve the bonding strength, but to investigate void formation at high temperatures. The IR imaging system was mainly used to characterize the voids in bonded pairs. To track the void emergence and growth, the digital image processing was employed to calculate void densities over the entire bonded wafer pairs. Water contact angle and x-ray photoelectron spectroscopy (XPS) measurements were made to investigate the plasma effects prior to bonding.
In conclusion, we found adding fluorine to oxygen plasma could effectively mitigate void formation in subsequent annealing process. Moreover, the plasma treatment time is a vital parameter to optimize the bonding strength as well as the void generation. Long plasma treatment may produce more porous surfaces and introduce undetected microdefects. Consequently, a short fluorine containing plasma treatment (e.g. ~10 s) is suitable to remove organic contaminants, it is thus nearly void-free at the bonding interfaces during heating from 200 to 800ºC. In practice, an optimum treatment time depends on the application requirements.

Figure 1
(Invited) A New Materials Concept for High Performance Organic Thin Film Transistors
Authors: Iino Hiroaki , Kunii Masafumi , Hanna Jun-ichi 
Published: February 2020

Various organic semiconductor materials for field effect transistors have been developed in these decades, since comparable FET mobility to that of amorphous silicon FETs was demonstrated in Pentacene FETs fabricated with its crystalline thin films. These includes small molecules and polymer materials for solution processes, some of which exhibit high mobility of over 10cm2/Vs. [1], [2] However, the small molecules have remained the problems to be solved such as quality and thermal durability of films, while the polymers need easy control of molecular orientation in a practical way, in addition to reliablities on material preparation from lot to lot and material purification.
We have established a new approach to solve the problems e in the small molecules, that is, utilization of highly-ordered smectic liquid crystals exhibiting self-organization and solid-like nature. 2-Phenyl-7-decyl-benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10) is a typical example in this approach and exhibits SmE phase at the temperature range from 142oC to 200oC, which allows high thermal durability at that range for thermal processes in device fabrication and high mobility of over 10cm2/Vs in solution processed polycrystalline FETs in bottom-gate and bottom-contact configuration [3]. In addition, we have succeeded in operating the FETs at low voltage lower than 5V with low-dielectric gate materials [4].
In this talk, we will discuss how the liquid crystallinity can solve the problems in small molecules for FET applications, and report the newest results on the FETs fabricated with this new material.
References
[1] K．H．Minemawari，T．Yamada，H．Matsui，J.Y．Tsutsumi，S．Haas，R．Chiba，R．Kumai，T．Hasegawa，Nature，475，pp．364–367 (2011).
[2] H-R Tseng，H．Phan ，C．Luo ，M．Wang ，L．A．Perez ，S．N．Patel，L．Ying ，E．J．Kramer ，T-Q Nguyen，G．C．Bazan ，and A．J．Heeger， Adv．Mater．DOI: 10.1002/adma.201305084 (2014).
[3] H. Iino, T. Usui, and J. Hanna, Nature Commn., 6:6828 | DOI: 10.1038/ncomms7828 (2015).
[4] M. Kunii, H. Iino, and J. Hanna, IEEE Electron Dev. Lett., 37, 486 (2016).

Figure 1
Highly Stable Zinc Oxynitride Thin-Film Transistors with Field-Effect Mobility Exceeding 100 cm2/Vs
Authors: Kim Yang Soo , Kim Hyun-Suk 
Published: February 2020

Ultra definition, large-area displays with three-dimensional visual effects represent the megatrend in the current and future display industry. On the hardware level, such a “dream” display requires faster pixel switching and higher current driving, which in turn necessitate thin-film transistors (TFTs) with high field-effect mobility values. Amorphous oxide semiconductors (AOSs) such as In-Ga-Zn-O have recently emerged as candidate materials that may satisfy the above requirements, but the trade-off between device performance (i.e., field-effect mobility) and stability (i.e., threshold voltage shift) under illumination critically limits their usability. Here we report on amorphous-like Zn-O-N (ZnON) TFTs that are Indium-free but still exhibit high field-effect mobility exceeding 100 cm2V-1s-1. Such devices have a superior stability over conventional AOS devices with respect to light radiation, which can be understood by studying the fundamental electronic band structure of ZnON. It is anticipated that high-mobility and high-stability ZnON TFTs will be extensively applied to next-generation flat-panel displays.
Inkjet-Printed Oxide TFTs with Solution-Processed Dual Semiconductors
Authors: Lee Seung-Hyun , Kwack Young-Jin , Lee Jun Seok , Choi Woon-Seop 
Published: February 2020

The solution process is a simple and low-cost thin film deposition method that enables a large area coating and high throughput because it can circumvent the need for photolithography and vacuum deposition. Direct patterning can be processed with screen printing, imprinting, ink-jet printing, and electrohydrodynamic-jet printing. Among them, inkjet printing is an attractive technique in device fabrication for the direct pattern writing and precise materials delivery. Recently, spin-coated double-active layer oxide TFTs, in which heterostructured channels, were reported to obtain improved electrical properties at relatively low processing temperatures. However, inkjet printing can provide a patterned active layer structure and give better properties compared to a simple spin-coated one.
To achieve the optimized electrical properties of an inkjet-printed double-active layer, the ZTO TFTs with various compositions of In2O3 solutions were examined. By controlling the annealing temperature and indium content, heterostructured In2O3/ZTO TFTs with improved mobility, threshold voltage and bias stability were obtained. The best electrical properties of the inkjet-printed double-active layer ZTO TFTs were obtained with 0.01 M of In2O3: a mobility of 8.6 cm2/ V s, a threshold voltage of 2.76 V, a subthreshold slope of 0.52 V/dec, and an on-to-off current ratio of 106 . The electrical properties of the inkjet-printed double-active layer oxide TFTs were superior to those of the single-active layered TFTs.
Low Temperature Processed Organic Tfts with Solution-Processable Al2O3 Gate Insulator Using Hydrogen Peroxide
Authors: Park Eung-Kyu , Wang Sihan , Cho Hyeong Jun , Lee So Young , Lee Dong-Hoon , Kim Yong-Sang 
Published: February 2020

Organic semiconductors are considered as a replacement for amorphous silicon in thin-film transistor (TFT) applications, since they have shown comparable electrical properties and potential advantages for their compatibility with plastic substrates. However, the high operating voltages of these TFTs still need to be reduced for any practical application. Among dielectric materials, aluminum oxide (Al2O3) appears to be promising due to its high dielectric constant, its robustness and its possibility to be prepared on different type of substrates under easy process. However, high quality and high dielectric constant films generally require annealing temperature above 400 oC, which is not suitable for high-throughput and flexible electronic devices.
In this study, we fabricated the bottom-gate and top-contact organic TFTs on glass substrate. Al gate electrode was deposited by thermal evaporation while Al2O3 thin films, used as gate insulators, were grown by spin coating. Employing hydrogen peroxide (H2O2) in the solution process helps reduce defects at the interface between channel and G/I through strong oxidation and minimize organic chemical-induced defects, such as pores, pin holes, and organic residues, through decomposing organic chemicals at low temperature. The growth of the Al2O3 thin films with H2O2 was studied with various annealing temperatures from 100 ~ 300 oC and solution concentration of 0.1 ~ 1 M. Pentacene was evaporated through shadow mask at a rate of 0.3 Å/s to form a 70 nm thick active layer. Gold source/drain (S/D) electrodes (100 nm) were patterned using shadow mask on the pentacene layer. The performance of the solution processed Al2O3 based TFT was validated using capacitance-voltage and current-voltage analysis.
Design of Bi-Directional Transmission Gate Driver in Amorphous Silicon Technology for TFT-LCD Application
Authors: Zheng Guang-Ting , Liu Po-Tsun , Wu Meng-Chyi , Lu i-Hsiang 
Published: February 2020

A novel bi-directional transmission gate driver circuit integrated by amorphous silicon thin film transistors (a-Si:H TFTs) has been proposed. In the proposed design, the noise suppression structure of the gate driver utilized the AC drive inverter to reduce the degradation of the pull down TFTs. The clock frequency of AC signal is 30 Hz, which could reduce dynamic power consumption of the circuit. In addition, the synchronous controlled method in this research could reduce the amount of device in gate driver.The simulated result shows the good output performance of the gate driver and match the circuit design.

Figure 1
(Invited) Flexible Transparent Conductors Based on Metallic Nanomesh
Authors: Ren Zhifeng 
Published: February 2020

Materials are often optically transparent but not electrically conducting like glass, or conducting but not transparent like metals, or transparent and conducting like indium-doped tin oxide (ITO) but not flexible. Flexible transparent conductors are required for many potential applications like foldable displays, impact resistant screens, etc., which demands transparent conductors very flexible. Nanowires such as silver, carbon nanotubes, etc., has been laid on flexible transparent polymers to achieve high electrical conductivity, but the contact resistance between the wires prevent the conductivity from being high enough. At the same time, graphene has also been studied as flexible transparent conductors without great success due to the large decrease of transparency when high enough conductivity is needed.
We discovered metallic nanomesh network exhibiting super flexibility, transparency, and conductivity by grain boundary masking and depsoition. These conductors exhibit sheet resistance lower than 10 ohms per square, transparency above 85%, stretchability more than 300%, bendability to a radius less than 1 mm, and can be repeatedly stretched for more than 100,000 times without fatigue. Further more, these materials are also very resistant to scratches.
Advances in AlGaN/GaN HEMT Surface Passivation
Authors: Koehler Andrew D. , Tadjer Marko J. , Anderson Travis J , Chojecki P. , Hobart Karl D , Kub Francis J 
Published: February 2020

The high efficiency and power density of AlGaN/GaN high electron mobility transistors (HEMTs) can be limited by parasitic charge trapping at sites on the semiconductor surface. Trapped electrons at the surface deplete the two-dimensional electron gas (2DEG), resulting in effects known as current collapse, increased dynamic on-resistance, DC-RF dispersion, among others. A SiN layer is conventionally implemented as surface passivation for GaN HEMTs, however the properties of this SiN layer and the impact of this layer on current collapse depend drastically on the deposition conditions of this film. Although passivation of GaN HEMTs has been studied extensively, the specific details behind the SiN passivation deposition are not frequently provided in literature. In this work, we investigate several passivation techniques and study their performance under dynamic switching conditions, under off-state stress, and implement hyperspectral electroluminescence imaging to identify electric field nonunifornities. We investigate plasma enhanced chemical vapor deposition (PECVD) SiN, a common GaN HEMT passivation method, and demonstrate how to optimize the deposition conditions to effectively passivate the HEMT. Generally, a mixed frequency PECVD SiN process is used, where a combination of low frequency (LF) e.g. 100-360 kHz and high frequency (HF) 13.56 MHz plasmas are used to create the SiN film. However, the LF step could create undesirable damage to the surface of the AlGaN barrier from N+ ion bombardment, degrading device performance. We developed a bilayer PECVD process, where a 10 nm thick layer is deposited using HF plasma only in order to protect the AlGaN surface, followed by a HF/LF mixed frequency SiN deposition. Annealing the 10 nm thick HF layer densified the film and resulted in a HEMT with significantly improved current collapse. On the other hand, SiN layers grown in situ during MOCVD growth of the GaN/AlGaN layers have also been demonstrated to serve as an effective protective layer for subsequent HF/LF PECVD SiN deposition, yielding HEMTs with low current collapse. Atomic layer epitaxy (ALE) deposition of a thin (10 nm) AlN layer is evaluated, and is shown to serve well as a passivation layer. This is particularly advantageous, since the thin layer is beneficial for reducing gate capacitance for high frequency operation. Finally, a nanocrystalline diamond (NCD) layer is incorporated on the surface of the GaN HEMT, primarily to improve thermal management, but this also is effective as a surface passivation layer, mitigating surface charge trapping. Effective passivation of the AlGaN/GaN HEMT surface is essential for mitigating current collapse, and we demonstrate recent advancements in passivation technology.
High Photoresponsivity Multilayer MoS2 Thin-Film Transistors with Local Bottom Gate Structure
Authors: Hong Seongin , Kim Ok Jin , Han Gyuchull , Kwon Junyeon , Liu Na , Hong Young Ki , Kim Dong Hak , Omkaram Inturu , Yoon Youngki , Kim Sunkook 
Published: February 2020

2D layered transition metal dichalcogenides (TMDs), especially MoS2, has received great attention for next-generation semiconductor devices because their thin film transistors (TFTs) show a nearly ideal subthreshold swing (SS ≈ 70 mV decade-1), high on/off current ratio (I
on/I
off ≈ 108), and high field-effect mobility (µ
eff > 100 cm2 V-1 s-1). In addition, TMDs have the optical characteristic of tuning bandgap from direct to indirect with increasing their layers. Even though photoresponsivity of multilayer MoS2 phototransistor due to its nature of indirect bandgap is lower than that of single layer MoS2, multilayer MoS2 has higher density-of-state and wider spectral response than single layer MoS2.
In order to enhance photoresponsivity of multilayer MoS2 phototransistor, we suggest the phototransistor with local bottom gate structure (LBGS), where the bottom gate length of the device is shorter than the channel length. The underlap regions of between gate and channel work like the series resistance in dark state due to ineffective gate modulation at the region. To demonstrate the enhancement of phototransistor performance using LBGS, we previously studied amorphous silicon TFT with LBGS. The photosensitivity enhancement up to 64 times as compared to the conventional a-Si TFT. And then, we used multilayer MoS2 as a channel material to constitute phototransistor with LBGS. The giant photoreponsivity of 342.6 AW-1 at 2 mW cm-1 shows three orders of magnitude larger than that of global gate multilayer MoS2 TFTs. This result of our experiment and simulation reveals that multilayer MoS2 phototransistor with local bottom gate can be used as various photosensing devices.