A New Method to Induce Tensile Stress in Silicon on Insulator Substrate: From Material Analysis to Device Demonstration
Authors: Maitrejean Sylvain , Loubet Nicolas , Augendre Emmanuel , Morin Pierre Francois , Reboh Shay , Bernier Nicolas , Wacquez Romain , Lherron Benoit , Bonnevialle Aurore , Liu Qing , Hartmann Jean-Michel , He Hong , Halimaoui Aomar , Li Juntao , Pilorget Sonia , Kanyandekwe Joel , Grenouillet Laurent , Chafik Fadoua , Morand Yves , Le Royer Cyrille , Faynot Oliver , Celik Muhsin , Doris Bruce , de Salvo Barbara 
Published: February 2020

Channel deformation has been proven as an effective way to increase performance of Field Effect Transistor [1]. In advanced technology nodes, in order to obtain good electrostatic control of the device, fully depleted channel become mandatory and devices such as FinFET or Fully Depleted Silicon On Insulator (FD-SOI) are developed. In these devices, channel deformation can be obtained by using strained SOI (sSOI) substrate fabricated by specialized manufactured companies. The traditional sSOI fabricaton required (i) a relaxed buffer of SixGe(1-x) in order to form a strain Si layer by epitaxy on the top of it and (ii) the use of a bond and split process suitable to strained layer [2]. Here, we propose an alternative methodology [3]. The new sSOI substrates are fabricated and analyzed. Si stress higher than 1.4GPa is obtained. The so-fabricated substrates are used to process Complementary Metal Oxide FD-SOI (sSOI CMOS FD-SOI) devices at 14nm node design rules. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates.
To elaborate sSOI substrates, starting materials are classical SOI wafers with Si layer thicknesses between 7 and 11nm. The process flow is shown in the figure. Epitaxial growth of 20nm thick Si0.73Ge0.27 is performed above SOI. Si ions are then implanted. Implantation conditions are chosen in order to totally amorphize the Si on insulator layer and to partially amorphize the bottom of the Si0.73Ge0.27 layer: indeed a crystalline layer is needed at the surface of the Si0.73Ge0.27 layer for further crystallization. The remaining crystal seed is shown in the TEM picture. Next; the sample is submitted to a crystallization anneal. During the implantation and annealing step the crystal seed is partially relaxed. Thereby, a relaxed Si0.73Ge0.27 lattice parameter is imposed to the Si on insulator during crystallization. The strain analysis by TEM shown in the figure demonstrates the partial relaxation of the Si0.73Ge0.27 and the tensile strain inside the Si. Some structural defects can be identified in the Si0.73Ge0.27 layer after anneal. These defects could play a role the Si0.73Ge0.27 relaxation. The relaxation mechanism will be in the presentation.
Finally the Si0.73Ge0.27 layer is selectively removed from the wafer surface. As measured by substrate bow variations, the stress in the Si film is in the range of 1.4 - 1.5GPa. This value is roughly the one expected for an epitaxial Si layer growth on a relaxed Si0.8Ge0.2.
CMOS FD-SOI devices have been processed at 14nm node design rules on the so-fabricated sSOI substrates as well as on standard SOI substrates for comparison. C doped Si is used as raised source drain for the n FET. The pFET features are a Si0.75Ge0.25 channel and a Si-Ge alloy raised source drain. Compared to devices built on standard SOI substrates, sSOI devices show threshold voltage shift coherent with tensile stress. Channel mobilities were extracted in short and long channel devices. As expected with tensile stress, sSOI devices showed increased mobility in nFET devices and decreased one in pFET devices.
[1] SW Bedell et al, MRS Bulletin, Vol 39, p 131, 2014
[2] M Bruel, US Patent, US 00 5 374 564A, 1994
[3] A. Halimaoui, et al., Patent EP 2 787 118 A1, 2014
Figure : Illustration of the process flow used for sSOI fabrication. TEM characterizations at various process steps.

Figure 1