bluuebunny/crossref_metadata_2025_split huggingface dataset:
Printed Circuit Board Propagating Faults
Authors: Slee Daren T. 
Published: December 2020

Abstract
This paper is a review of propagating faults in printed circuit boards (PCBs) from the perspective of using the resulting burn and melted copper patterns to identify likely locations of fault initiation. Visual examination and x-ray imaging are the main techniques for examining PCB propagating faults. Once the likely fault initiation location has been identified, fault tree analysis can be used to determine the root cause for fault initiation. The paper discusses the mechanisms by which PCB propagating faults occur. The method of determining the likely area of initiation of the fault using visual examination of the PCB burn pattern, x-ray imaging, and the layout artwork for the PCB is discussed. The paper then goes on to discuss possible root-causes for the initiation of PCB propagating faults and some of their considerations.
Enhanced Pixel by Pixel Emissivity Correction for Thermal Microscopy
Authors: Goh S.H. , Yim K.H. , Phang J.C.H. , Balk L.J. 
Published: December 2020

Abstract
In thermal microscopy, temperature error arises whenever a constant emissivity value is assumed for different materials. In this paper, we propose a new approach to eliminate these undesirable effects resulting from the ambiguous surface emissivity of materials. This method enables the compensated (true) temperature distribution of a device under test to be obtained from the measured temperature image. A transfer function that relates the measured and true temperature is formed to estimate the actual temperature distribution of a biased device to an accuracy of approximately 0.3-0.7K.
Fluorocarbon Precursor for High Aspect Ratio via Milling in Focused Ion Beam Modification of Integrated Circuits
Authors: Ray Valery 
Published: December 2020

Abstract
Gas Assisted Etching (GAE) is the enabling technology for High Aspect Ratio (HAR) circuit access via milling in Focused Ion Beam (FIB) circuit modification. Metal interconnect layers of microelectronic Integrated Circuits (ICs) are separated by Inter-Layer Dielectric (ILD) materials, therefore HAR vias are typically milled in dielectrics. Most of the etching precursor gases presently available for GAE of dielectrics on commercial FIB systems, such as XeF2, Cl2, etc., are also effective etch enhancers for either Si, or/and some of the metals used in ICs. Therefore use of these precursors for via milling in dielectrics may lead to unwanted side effects, especially in a backside circuit edit approach. Making contacts to the polysilicon lines with traditional GAE precursors could also be difficult, if not impossible. Some of these precursors have a tendency to produce isotropic vias, especially in Si. It has been proposed in the past to use fluorocarbon gases as precursors for the FIB milling of dielectrics. Preliminary experimental evaluation of Trifluoroacetic (Perfluoroacetic) Acid (TFA, CF3COOH) as a possible etching precursor for the HAR via milling in the application to FIB modification of ICs demonstrated that highly enhanced anisotropic milling of SiO2 in HAR vias is possible. A via with 9:1 aspect ratio was milled with accurate endpoint on Si and without apparent damage to the underlying Si substrate.
Front-End Failure Analysis of Integrated Circuits Using Scanning Capacitance Microscopy
Authors: Huang M.C. , Lin C.T. , Lin J.C. 
Published: December 2020

Abstract
Scanning capacitance microscopy (SCM), a powerful technique to identify front-end defects, is also helpful in understanding failure mechanisms. This article discusses three front-end doping failure examples that were clearly identified by SCM analysis. The first example was NMOS leakage between drain and source. SCM images showed that N+ junction distortion resulted in effective channel length shortage. The second one was by-field SRAM failure with power leakage. From SCM images, it is clarified that P-well was directly short to P+ in bad die and slight P-well boundary shift to P+ was observed in good die. The third example was regarding low threshold voltage failure analysis. It illustrates that combination of plane-view and cross-sectional SCM analysis could help to diagnose the failure mechanism. The resolution and precision in SCM is better than that in chemical etching combined with SEM technique.
SEM and AFM Investigation for Accurate Measurements of 193-nm Resist Profiles
Authors: Reiche Rainer , Bartkowiak René , Heller Marcel , Rosenkranz Rüdiger 
Published: December 2020

Abstract
SEM analysis of 193-nm photoresist profiles after cross section is seen to be critical because of the shrinkage of the photoresist material during electron beam exposure. With a combination of AFM and SEM investigations on AuPd sputter prepared samples an averaged shrinkage behaviour of height and width of resist lines of varying geometry can be quantitatively determined. This helps to a more accurate determination of resist line profiles.
Enhancement Method to Improve the Accuracy of Intermetallic Area Inspection on the Bonding Pad through Chemical and Mechanical Removal Process
Authors: Kongsubto Prong , Kongwudthiti Sirarat , Yousoom Yupa , Lochingchairit Rit , Kongjaroon Pakorn 
Published: December 2020

Abstract
In this work, we proposed new sample preparation technique (combination of mechanical and chemical method) for inspection of intermetallic bondballs. The use of this new method will provide more accurate estimation of the percentage of intermetallic formation area. The procedure to perform the sample preparation is: 1. Grind unit from the bottom side of the package until the bulk silicon die is visible. 2. Dipping the unit into KOH 50% solution at 100 to 110 degree C to remove the bulk silicon 3. Dip unit in HF : DI water (1:10) at room temperature to remove any diffusion layers, metal lines, barrier metal and inter-dielectric layers. Then clean the unit by using Hydrogen Peroxide (H2O2) 4. The images are imported into Image-Pro software to calculate the percentage values.
FIB Backside Circuit Modification at the Device Level, Allowing Access to Every Circuit Node with Minimum Impact on Device Performance by Use of Atomic Force Probing
Authors: Schlangen R. , Kerst U. , Boit C. , Schömann S. , Krüger B. , Jain R. , Malik T. , Lundquist T. 
Published: December 2020

Abstract
Direct measurements of circuit node signals without changing the performance of the circuitry are essential in modern FA but often impossible for recent IC technologies. This paper shows new methods, based on FIB backside circuit edit, allowing access to every existing circuit node at the device level, and discusses options for probing and discrete characterization.
STI Punch-through Degradation Related Standby Current Failure in HTOL Test – A Case Study
Authors: Chen Wen-Rong , Tseng Wei-Chun , Lee Yi-Ju , Liu Kuang-Wen , Kuo Li-Kuang , Yin Shaw , Lu Chih-Yuan 
Published: December 2020

Abstract
This report summarizes the analysis results of 0.13µm technology 256Mbits NBit HTOL (High Temperature Operational Life) induced standby current failures caused by STI (Shallow Trench Isolation) punch through induced leakage degradation. Electrical analysis, EMMI and stress experiment on test devices are employed to identify the failure mechanisms, root causes, and corrective solutions. From this study, improvements could be achieved by circuit layout modification.
Investigation of Bond-Pad Etching Chemistries for Determination of Probe/Bonding Related Sub-Pad Cracks
Authors: Korchnoy Valentina 
Published: December 2020

Abstract
Bond-pad integrity directly affects the performance of microelectronic devices. Bond-pad cracking and the related sub-pad cracking of Inter-Metal Dielectric (IMD) may introduce a high reliability risk and cause units to fail at environmental stress. Bond-pad cracks may be initiated by probing during wafer sort and the wire bonding process during assembly. This paper presents a comparative analysis of the various chemistries used for exposure and decoration of pad cracks. The investigation showed that a tri-iodine etch provides clean and artifact-free exposure of the TiN barrier layer of the pad and is the best (of the methods tried herein) for pad crack observation.
Wireless Advanced FA Tool (WAFT)
Authors: Chee Thim Fai , Zhang Mo 
Published: December 2020

Abstract
The existing failure analysis (FA) tool used in the manufacturing was unable to support multiple input multiple output (MIMO) analysis and it has poor user interface capability. The tool used by hardware engineers and design engineers is capable for all radio frequency (RF) analysis including MIMO, but yet it is an extremely expensive tool with rigid interface due to the need for automation. Wireless advanced FA tool (WAFT) was then designed, developed, and deployed as a single solution to FA engineers to perform all the RF analysis including MIMO in a user friendly interface and affordable setup. This article provides information on design planning, application, validation, and deployment of WAFT as well as on transmit quality and receive quality evaluation. WAFT has been validated in providing accurate measurement by benchmarking with the existing tools. WAFT provides the interactive controllability and comprehensive signal analysis capability including MIMO needed for FA.
Pseudo-Soft Defect Localization
Authors: Tangyunyong Paiboon , McFarland Rick , Flores Richard S. , Pearson Sean , Sanchez Marco O. 
Published: December 2020

Abstract
In this paper, we describe a modified soft defect localization (SDL) technique, PSDL (pseudo-soft defect localization), to localize pseudo-soft defects in integrated circuits (ICs). Similar to soft defects, functional failures due to pseudo-soft defects are sensitive to operating parameters (such as voltages, frequencies and temperatures) and/or laser exposures. Pass/fail states in pseudo soft defect failures are, however, not fully reversible after laser exposure or after changing operating parameters. PSDL uses the methodology of conventional SDL and/or TIVA in combination with a new scanning scheme for defect localization. An example will be shown to demonstrate the use of this technique to localize pseudo-soft defects.
Back-End-of-Line Quadrature-Clocked Voltage-Dependent Capacitance Measurements
Authors: Polonsky Stas , Solomon Paul , Ketchen Mark , Shiling Ernesto , Economikos Laertis , Bhushan Manjul 
Published: December 2020

Abstract
We compare different dc current-based integrated capacitance measurement techniques in terms of their applicability to modern CMOS technologies. The winning approach uses quadrature detection to measure mutual Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) capacitances. We describe our implementation of this approach, Quadrature-clocked Voltage-dependent Capacitance Measurements (QVCM), and its application to 45 nm node BEOL: wire capacitance variability measurements for analog design, and capacitive test structure to measure the effect of metal pattern density on Chemical-Mechanical Polishing (CMP) and Reactive Ion Etching (RIE).
Decapsulation Techniques for Cu Wire Bonding Package
Authors: Meng Dongmei , Rupley Joe , McMahon Chris 
Published: December 2020

Abstract
This paper presents decapsulation solutions for devices bonded with Cu wire. By removing mold compound to a thin layer using a laser ablation tool, Cu wire bonded packages are decapsulated using wet chemical etching by controlling the etch time and temperature. Further, the paper investigates the possibilities of decapsulating Cu wire bonded devices using full wet chemical etches without the facilitation of laser ablation removing much of mold compound. Additional discussion on reliability concerns when evaluating Cu wirebond devices is addressed here. The lack of understanding of the reliability of Cu wire bonded packages creates a challenge to the FA engineer as they must develop techniques to help understanding the reliability issue associated with Cu wire bonding devices. More research and analysis are ongoing to develop appropriate analysis methods and techniques to support the Cu wire bonding device technology in the lab.
Effectiveness of Nanoprober in Detecting Single/Multiple Bit Flash Data Gain & Data Loss Failures
Authors: Medikonduri Rajesh 
Published: December 2020

Abstract
This paper discusses the physics, definitions, and nanoprobing flow of a flash bit memory. In addition, a case study showing the effectiveness of nanoprobing in detecting the Single Bit Fail Data Gain and Data Loss in Flash Memory is also discussed. The paper also includes cases where no passive voltage contrast was observed at the SEM and no leakage was observed at AFM, yet the units failing SBF DG, SBF DL and depletion, were detected by nanoprobing of the single bit. The major finding of this paper is a way to resolve data gain, data loss, and depletion failures of flash memory by nanoprobing procedure, despite no PVC seen at the SEM and no leakage seen at the AFM.
Development of Laser-Based Variation Mapping Techniques – Another Way to Increase the Successful Analysis Rate on Analog & Mixed-Mode ICs
Authors: Sienkiewicz Magdalena , Sanchez Kevin , Cattaneo Luigi , Perdu Philippe , Firiti Abdellatif , Crepel Olivier , Lewis Dean 
Published: December 2020

Abstract
The failure localization on analog & mixed mode ICs in functional mode (AC signals) has become more and more challenging in the last few years. Due to an increasing integration and complexity of these devices, the number of defects, especially those named “soft”, raised considerably. The classical Dynamic Laser Stimulation (DLS) techniques showed some limitations when applied to analog & mixedmode ICs. The SDL (Soft Defect Localization) technique [1] based on binary output signal allows us to localize only the most sensitive areas. The defect in this type of circuits, which are very sensitive to the laser beam [2], is often characterized by a weaker sensitivity than that of “healthy” regions. Hence, xVM (Variation Mapping) techniques were introduced to map some parameters in an analog way (the different sensitivity levels are visualized). To date, the T-LSIM technique [3], the Delay and the Phase Variation Mapping techniques were published [4, 5]. We have already had some interesting results by using these techniques [6] but not every “soft” defect case study could be resolved in that way. In this paper we propose to look at some different parameters which characterize an analog signal and can be used as an input for laser mapping. By applying a simple setup, without any additional sophisticated tool, we show on a “golden” commercial IC the added value of this analysis. We also deal with amplifying the weak signal variations induced by the laser beam scan which often are hidden by the high signal variations in analog or mixed-mode ICs.
Analysis of a Media Processor Functional Failure
Authors: Putman Alan 
Published: December 2020

Abstract
A system-on-chip processor (90 nm technology node) was experiencing a high basic function failure rate. Using a lab-based production tester, laser assisted device alteration, nanoprobing, and physical inspection; the cause of failure was traced to a single faulty P channel transistor. The transistor had been partially subjected to N doping due to poor photo-resist coverage caused by halation.
A Case Study: Observation of Counter Doping of Gate Poly and Its Validation in High Density 90nm CMOS SRAM Bitcell
Authors: Tsang Yuk , Wang Xiang-Dong , Mendicino Michael , Blankenship Andrew 
Published: December 2020

Abstract
Threshold voltage (Vt) shift was measured, using atomic force probing (AFP) technique, in the pullup PFETs of high density SRAM bitcell arrays in 90nm CMOS bulk technology. This shift caused catastrophic yield loss. The direct measurements of dopant distribution both in plan view and x-section using Scanning Capacitance Microscopy (SCM) technique suggested counter doping of the P-poly had occurred. A single mask modification was shown to validate the observation and eliminated the counter doping resulting in drastic yield enhancement to about 60% from nearly no yield.
Advanced Sample Preparation Method for Lead Free Bump IMC and Solder Grain Image Enhancement
Authors: Sheu Ming-Song , Kuo Yian-Liang , Lee Jeng-Hun , Lin Yu-Ting , Chu Hui-Chen , Tsai Tsung-Fu , Chang Chih-Horng 
Published: December 2020

Abstract
An advanced method for LF (Lead Free) bump sample preparation to improve the surface of sample that can enhance the image of IMC (Inter Metallic Compound), solder grain boundary and micro-crack after TC (thermal cycle) reliability test is proposed. By this advanced method application, LF bump micro-crack location and propagation path can be observed easily for the reliability test fracture failure mechanism study and LF bump crack improvement further.
High Volume and Fast Turnaround Automated Inline TEM Sample Preparation for Manufacturing Process Monitoring
Authors: Kang Hyoung H. , King John F. , Patterson Oliver D. , Herschbein Steven B. , Nadeau James P. , Fuller Scott E. 
Published: December 2020

Abstract
This paper introduces a high volume and fast turnaround TEM sample preparation method and requirements for a 300 mm inline DualBeam (FIB/SEM) system with “hands-off” full automation. It requires a factory automation system, robust automated recipes, and an ex-situ TEM lamella liftout system. It describes the recipe structure and TEM lamella lift out procedures. The focus is on fully automated TEM sample preparation for process monitoring in manufacturing line. Two successful examples are described to demonstrate the benefit of this method. The first one is TEM sample for CA profile at M1 level. The second is TEM sample for poly crystalline (PC) line profile at post-etch.
Backscattered Electron Imaging for Embedded Subtle Defects in 32nm Processes
Authors: Song Z. G. , Song H. S. , Yu J. , Su T. 
Published: December 2020

Abstract
Although the overall spatial resolution of backscattered electron (BSE) imaging suffers in comparison to secondary electron (SE) imaging, its superior sensitivity to atomic number (Z) contrast and ability to image through overlying insulation levels can provide a complementary approach for imaging subtle buried defects. BSE enables the localization and imaging of embedded defects through overlying insulator levels without the risk of compromising them with reactive ion etch (RIE) or plasma etch exposure or by anisotropic wet chemical delayering process steps. Once the embedded defect is localized with BSE in situ, subsequent imaging by cross sectional Transmission Electron Microscopy (XTEM) combined with elemental analysis by energy dispersive X-Ray analysis (EDX) or electron energy loss spectroscopy (EELs) can be performed without the risk of introducing artifacts. In this work, BSE imaging was successfully employed to image embedded subtle defects in 32nm node technologies through overlying insulator films not possible with conventional SE imaging techniques.
Decapsulation of Copper Bonded Plastic Encapsulated Integrated Circuits Utilizing Laser Ablation and Mixed Acid Chemistry
Authors: Klein Jake E. , Copeland Lucas 
Published: December 2020

Abstract
By utilizing a NdYAG lamp pumped marking laser, along with unique mixes of specific acids, reproducible decapsulation of copper bonded devices without damage to the bond wires, packaging material, or to the silicon die circuitry itself can be achieved. With the copper bond wires, die, or substrate exposed, typical failure analysis methodology can then be applied to drive root cause failure analysis or device characterization.
Combined Electron Beam Induced Current Imaging (EBIC) and Focused Ion Beam (FIB) Techniques for Thin Film Solar Cell Characterization
Authors: Altmann Frank , Schischka Jan , Ngo Vinh Van , Stone Stacey , Kwakman Laurens F. Tz. , Lehmann Ralf 
Published: December 2020

Abstract
A novel analytical method applying combined electron beam induced current (EBIC) imaging based on scanning electron microscopy (SEM) and focused ion beam (FIB) cross sectioning in a SEM/FIB dualbeam system is presented. The method is demonstrated in several case studies for process characterization and failure analysis of thin film technology based Solar cells, including Silicon (CSG), Cadmium Telluride (CdTe) and Copper Indium Selenide (CIS) absorbers. While existing techniques such as electro-, photoluminescence spectroscopy and lock-in thermography are able to locate the larger, electrically active defects reasonably fast on a large area, the FIB-SEM EBIC system is uniquely capable of detecting sub-micron, sub-surface defects and of analysing these defects in the same system. In combination with a FIB, the localized region of interest can be easily cross sectioned and additional EBIC analysis can be applied for a three dimensional analysis of the p/n junction.
A Novel Technique for Localization of Low Level Leakage in Integrated Circuits
Authors: Chiang A. , Wu H. , Nguyen H. , Pratchayakun W. , Le P. 
Published: December 2020

Abstract
Electrical leakage can be either the cause or the effect of circuit failures. Existing detection tools that rely on heat (liquid crystal and fluorescent microthermal imaging) or near-infra-red radiation (thermal imager and emission microscope) associated with the leakage can be fairly effective provided that the ‘hot spot’ is not blocked by metal and, more importantly, the level of leakage is high enough to generate the heat or radiation above certain detection threshold. Using a unique property created by the knock-in implantation of oxygen, we introduce a novel technique that can be used to identify localized leakage at previously unattainable low levels.
Infrared and Visible—Near Infrared Electroluminescence Developments for FA in AlGaN/GaN HEMTS on SiC
Authors: Bouya M. , Carisetti D. , Clement J.C. , Malbert N. , Labat N. , Perdu P. 
Published: December 2020

Abstract
HEMT (High Electron Mobility Transistor) are playing a key role for power and RF low noise applications. They are crucial components for the development of base stations in the telecommunications networks and for civil, defense and space radar applications. As well as the improvement of the MMIC performances, the localization of the defects and the failure analysis of these devices are very challenging. To face these challenges, we have developed a complete approach, without degrading the component, based on front side failure analysis by standard (Visible-NIR) and Infrared (range of wavelength: 3-5 µm) electroluminescence techniques. Its complementarities and efficiency have been demonstrated through two case studies.
Scan Chain Debug Using Dynamic Lock-In Thermography
Authors: Forli L. , Picart B. , Reverdy A. , Schlangen R. 
Published: December 2020

Abstract
In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.
Effective Fault Isolation Using Memory BIST and Logic BIST Diagnostic Techniques
Authors: Kinger Rakesh , Tong Chuck , Chaudhry Ayyaz , Chowdhury Vijay , Sun Wenzhen , Deng Hongqi , Smith Steve 
Published: December 2020

Abstract
As device technologies are shrinking, developing new techniques for fault isolation and defect localization is becoming a crucial challenge. In this paper, we have shown that by using memory and logic BIST diagnostic techniques, we are able to isolate the defect to two suspected nets. Thirdparty electronic design automation (EDA) tools were used for both MBIST and LBIST hardware implementation and for running diagnostics on the failing part. Using experienced and sophisticated failure analysis support, we were able to confirm with confidence that the stuck-at zero type of defect was caused by a signal line short at metal-5 to the ground line at metal-6.