bluuebunny/crossref_metadata_2025_split huggingface dataset:
(Invited) Semiconductor Packaging Technology to Progress the IoT Era
Authors: Takeno Yasuhiko 
Published: February 2020

In the world economy there is a wave of the booming economy and the recession, the wave of the booming economy is going by the industry of technology innovation. Until now, the invention of the steam engine, transportation of development, has been repeated waves of good / recession of the economy by the invention of the electrical / communication. Now, the wave of major technological innovation has been visited by the progress of the Internet and the computer. It is a technique called IoT (Internet of Things) is connected and all of the places and things in the Internet, to accumulate an enormous amount of information, a wave of AI (Artificial Inteligence) is going to processing.
Server for IoT era is referred to as a sensor and the edge can be determined that data to collect the information, also AI server to handle Big Data is needed. Such sensors or servers, it is important to semiconductor development for processing data in high-density memory and fast. On the other hand due to the limit of the semiconductor of the fine or photolithography, it is no longer the case is Moore's Law. As a result, technology of packaging the device in a high density is important. DRAM is, TSV (Through Via Silicon) HBM using (High Band Width Memory) and HMC (Hybrid Memory Cube) has been mass-produced is already a memory. System connecting the GPU (Graphic Processor Unit) using the Si interposer called 2.5D is still being produced.
However, TSV Si Interposer called these 3D is in the advance in the future IoT because of the high cost, it is difficult to be used in general to modularize the large number of sensors. Development has been the development of new packaging technology, such as that in FOWLP.
I want to discuss the outlook and its Overview.
Effects of Brighteners on Throwing Power and Thermal Reliability of Plating through Holes in a Copper Plating Bath
Authors: Chen Tsu-Chi , Tsai Yao-Lin , Hsu Chia-Fu , Dow Wei-Ping 
Published: February 2020

High aspect ratio through holes are commonly designed in printed circuit boards (PCBs) with a high density interconnection. In order to achieve high copper throwing power of through holes by using plating, the copper plating bath has to be added with additives, like chloride ions, suppressors, brighteners and levelers. In this study, several brighteners were screened to understand their performance on copper throwing power of plated through holes (PTHs). The chloride ion concentration was fixed at 60 ppm and the suppressor, Polyethylene glycol, concentration was fixed at 200ppm.The brighteners were 3-mercapo-1-1-propanesulfonate（MPS）, 3-S-Thiuronium-propanesulfonate (UPS) and 3-(benzothiazolyl-2-mercapto)-proyl-sulfonate（ZPS）. Good throwing power of PTHs appeared at 1 ppm MPS, 20 ~ 100 ppm UPS or 20 ~ 60 ppm ZPS. Scanning Electron Microscope（SEM）shows that the electroplated morphology is related with the brightener concentration. Moreover, different brightener results in different plated copper orientation and stress in the copper deposit, which significantly influences the final thermal reliability of the PTHs. The results show that the PTHs with the highest copper TP, which were obtained at 1 ppm MPS, 10 ppm UPS, and 20 ppm ZPS, can pass the thermal shock for 5 cycles.
Key words: Throwing power, Reliability, Brightener, Through hole.
References:
1. W.-C. Tsai, C.-C. Wan, and Y.-Y. Wang, J. Electrochem. Soc., 150, C267 (2003).
2. C. Wang, J. Zhang, P. Yang, B. Zhang, and M. An, J. Electrochem. Soc., 160, D85 (2013).
(Invited) Interconnect Metals for Future Integrated Circuits
Authors: Besser Paul , Wu Hui-Jung , Jiang Yu , Chattopadhyay Kaushik , Brogan Lee , Zhao Larry , Doubina Natalia , Nalla Praveen , Kolics Artur 
Published: February 2020

The highest performing microprocessors, memory devices, and other computer chips require the most advanced technologies. Improving performance of the device is much more than just shrinking the dimensions: it requires novel materials innovations. BEOL interconnect performance has been improved by the migration from aluminum-based interconnects and oxide interlayer dielectrics to copper interconnects in a dual inlaid architecture and with low-k dielectrics. Inlaid Cu lines offer higher conductivity, improved electromigration resistance, and a reduced cost of manufacturing; however, as feature sizes continue to scale, metals to replace Cu are being researched. In this presentation, the novel materials innovations being researched to enhance performance, improve reliability, and enable technology scaling for the integrated circuit (IC) industry will be highlighted. A historical perspective on BEOL interconnect challenges and innovations to reduce capacitance and improve conductivity will be shown. Future BEOL interconnect metallizations will be critically reviewed.
Modeling Investigation of Influencing Factors on Li Plating of Li-Ion Battery
Authors: Zhang Zhenli , Jin Zhihong , Wyatt Perry M 
Published: February 2020

Lithium plating is a known issue of rechargeable lithium-ion cells with carbon-based anodes. Accumulated metallic lithium plating growth accelerates aging and internal short circuit failures. Preventing lithium plating is an important consideration for cell design and operations. In real world applications, the cells in battery pack will age and very likely they age differently and sometimes they are used in extreme conditions and then it raises questions of how to detect and control lithium plating in service. A variety of factors influence lithium plating including cell design variables, intrinsic material properties, manufacturing conditions, as well as cell operation conditions. Understanding these factors has significant value in points of view of design and controls. Where are the optimization rooms in battery design without raising plating risks? How to determine the charging current limits as function of temperature, state of charge and battery conditions? Using experimental means to investigate plating has limitations in sensitivity and timeliness because in many scenarios plating does not show up in a detectable quantity and sometimes they are not stable.
In this work, we develop a model to consider lithium plating. In the framework of electrochemical modeling the lithium plating reaction is included. The model is used to study lithium plating upon various design variables and application conditions. We are interested in how coating thickness, particle size characteristics, pulse current and duration, and driving cycles affect lithium plating. The aim of this modeling is to understand the relative impacts of these factors and provide guidance for cell designs and controls.
Fabrication and Characterization of SiGe on Insulator through Condensation and Wafer Bonding Techniques
Authors: Noroozi Mohammad , Hamawandi Bejan , Toprak Muhammet , Radamson Henry H. 
Published: February 2020

SiGe on insulator (SGOI) is desired to obtain microelectronic devices with high performance and low leakage current. The manufacturing of silicon on insulator (SOI) has been already developed and the wafers are on the market with different expenses and qualities. Nevertheless the fabrication techniques of SGOI is more complex than SOI wafers.
In this study two different techniques has been applied to fabricate SGOI wafers. The advantages and disadvantages of both techniques have been discussed in details and the wafers have been characterized in terms of defect density, roughness, uniformity and fabrication process parameters.
The original wafers for condensation technique were SOI with 50 nm Si top and 400 nm buried oxide. The 100 nm Si0.74Ge0.26 was epitaxially grown on SOI wafers followed by 10 nm Si cap layer using chemical vapor deposition (CVD) technique. The Si cap/ Si0.74Ge0.26/ Si structure went through condensation where Si cap layer oxidize immediately and Si0.74Ge0.26/Si was sandwiched between two oxide layers. The consequence of Ge diffusion to the beneath Si layer result single layer Si0.53Ge0.47on insulator (SGOI).
In the wafer bonding technique as second method, Si0.53Ge0.47 has grown epitaxially on a Si wafer. The direct bonding applied between donor and acceptor wafers. The bonded wafers are then annealed in order to strength the bonding. The etch-back process begins by thinning down the donor wafer to leave the Si0.53Ge0.47 on insulator.
The quality and electrical transport of condensed and bonded SiGe layer were examined using high resolution reciprocal lattice mapping (HRRLM), scanning electron microscopy (SEM), Rutherford back scattering (RBS), atomic force microscopy (AFM), hall measurement technique in van der pauw structure and four probe measurement technique. The results show the condensation layer undergo defects which originate from condensation process compared to bonding layer which possess lower defect density. This study will help to continue optimizing of substrate engineering of group IV alloys for implementation on next silicon technology.
Zno Nanowires Electrodeposited for UV Detector Applications
Authors: V. Manzano Cristina , Pethö Laszlo , Michler Johann , Philippe Laetitia 
Published: February 2020

In the last years, wide band gap semiconductors have received great interest due to their wide application range. Specifically, one-dimensional structures of these semiconductors are candidates for many applications. ZnO is an ideal candidate, as it is an n-type semiconductor with a hexagonal structure, a direct wide band gap of 3.36 eV, high electron mobility, and large excitation energy of 60 meV at room temperature. This semiconductor exhibits an efficient emission in the ultraviolet and visible range, so it is also promising for UV detection applications. ZnO one-dimensional structures (nanowires) are a promising candidate for efficient UV detectors if they fulfill three requirements: high aspect ratio (length/pore diameter) to obtain high on/off current ratios in UV detectors, oriented along the c-axis of the hexagonal structure to reach high electrical properties for the photodetector, and ZnO nanowires should be ordered perpendicular to the substrate to provide excellent light trapping and improve absorption.
In this study, ZnO nanowires have been grown at constant electrochemical deposition. Electrodeposition of ZnO was performed using a standard three-electrode cell, where the working electrode was home made anodic aluminum oxide (AAO) templates, the counter electrode was a Pt mesh, and the reference electrode was Ag/AgCl. The electrolyte used in the electrodeposition was peroxide solution (0.005 M ZnCl2 + 0.1 M KCl + 0.04 M H2O2). ZnCl2 concentration were changed from 0.001 M to 0.01 M. The electrodeposition temperature was 70, 75, and 80 °C. The morphology, uniform growth, and filling ratio were controlled by the ZnCl2 concentration, applied potential, and electrodeposition temperature. At 70 °C and using 0.005 M ZnCl2 in the electrolyte, high aspect ratio, uniform growth, and filling ratio ZnO nanowires were obtained by Scanning Electron Microscopy. The crystallographic structure of the nanowires was controlled by applied potential around the reduction potential of ZnO. X-Ray Diffraction confirms that the nanowires are pure ZnO. The main advantages of growing ZnO nanowires by electrodeposition into AAO are the order of the nanostructures, and perfect control nanowires geometry. Moreover, the electrical properties can be measured in ZnO nanowires embedded into AAO, after removing AAO, and single nanowires. The effect of the pore diameter and length of ZnO nanowires on IV curves, and photoresponse is a wide field waiting to be explored.
Surmofs and Cncs As Novel Tuneable Materials for Optical, Photonic and Solar Energy Materials
Authors: Redel Engelbert 
Published: February 2020

Here, I will present a particularly interesting class of surface-anchored (metal-organic frameworks and coordination network compounds) materials SURMOFs and CNCs for the fabrication e.g. of 1D (Photonic Band Gap) PBG materials [1] as optical sensors, low-k dielectric thin films [2], optoelectronic/ electrochromic switchable coatings/devices [3] PV devices [4] or as future artificial Light-Harnessing (LH) antenna array assemblies as well as novel hybrid-photocatalyst.[5]
Since these materials are highly porous and the size of their pores are highly adjustable, they can be further functionalized (e.g. with different metal/oxo connectors or clusters linked with various organic linkers) e.g. in order to specifically bind target analytes (optical sensing), to electrically load and unload small ions (optoelectronic applications) as well as to act as photon traps, which are able to efficiently absorb, transport and harness light energy over an artificial LH antenna array.
In addition, the RI (Refractive Index) as well as the optical properties of SURMOF and CNC materials can be tailored – a fact which makes these materials ideally suited for photonic, optical, optoelectronic, light-harnessing as well as for future solar energy systems like photocatalytic and PV applications.

Keywords: SURMOFs, porous thin films, artificial light harnessing, optics and photonics, PV applications, photocatalysis.

References:

[1] J. Liu, E. Redel, S. Walheim, Z. Wang, V. Oberst, J. Liu, S. Heissler, A. Welle, M. Moosmann, T. Scherer, M. Bruns, H. Gliemann, Ch. Wöll Chemistry of Materials (ACS)
2015,
27, 1991.
[2] E. Redel, Z. Wang, S. Walheim, J. Liu, H. Gliemann, Ch. Wӧll, App. Physics Lett.
2013
, 103, 091903
[3] J. Liu, W. Zhou, S. Walheim, Z. Wang, P. Lindemann, S. Heissler, J. Liu, P. G. Weidler, T. Schimmel, Ch. Wöll, E. Redel Optics Express (OSA)
2015, 23, 13725.
[4] J. Liu, W. Zhou, J. Liu, I. Howard, G. Kilibarda, S. Schlabach, D. Couprey, M. Addicoat, S. Yoneda, Y. Tsutsui, T. Sakurai, S. Seki, Z. Wang, P. Lindemann, E. Redel, T. Heine, C. Wöll
*VIP ≡ Very Important Paper (Angewandte Front Cover Issue 2015-54/25) Angewandte Chemie International Edition
(Wiley-VCH)
2015, 54, 7441.
[5] W. Guo, Z. Chen, C. Yang, T. Neumann, C. Kuebel, W. Wenzel, A. Welle, W. Pfleging, O. Shekhah, C. Wöll and E. Redel, Nanoscale (RSC)
2016, 8, 6468.
Resistance Switching in Individual Hydrogen Silsesquioxane (HSQ) Nanopillars
Authors: Ng Wing Hung , Buckwell Mark , Mehonic Adnan , Kenyon Anthony Joseph 
Published: February 2020

We demonstrate resistance switching in individual 100nm-diameter hydrogen silsesquioxane (HSQ) nanopillars. HSQ is commonly used as an insulating material and an electron beam resist in the electronics industry, as it forms silicon oxide upon exposure to an electron beam. In this paper, we present our recent work on resistance switching in HSQ.
Our metal-insulator-metal (MIM) type devices consist of titanium and molybdenum top and bottom contacts, respectively, sandwiching a 30 nm HSQ thin film applied using standard spin coating techniques. Ti/HSQ nanopillars were fabricated from this sandwich structure using electron beam lithography and reactive ion etching. The fabricated nanopillars had typical diameters and heights of 100 nm and 110 nm, respectively, with a centre-to-centre spacing of 180 nm. In order to verify the composition of the HSQ thin film, X-ray photoelectron spectroscopy (XPS) was carried out. Results showed an Si4+ peak at 104 eV, which suggests the film is SiO2-like.
The ability to fabricate nanometre-scale resistive memory (ReRAM) devices is of interest both to provide a fundamental understanding of switching mechanisms and ultimate scaling limits, and also to precisely define the position of conductive filaments in devices.
We characterised and switched our nanopillar ReRAM structures using conductive atomic force microscopy (CAFM). We scanned a 1 µm by 1 µm area with a tip voltage of 10 V to modify the conductivity of the nanopillars. Followed by scanning the same area with 0 V bias and 2 V bias to map the conductivity. With a 2 V bias scan, some nanopillars showed an increase of conductivity (Figure 1), whereas with a 0 V bias scan, all the nanopillars remain insulating. This indicates that individual nanopillars exhibit resistance switching, and we could address single nanopillars as switchable elements in a ReRAM array.

Figure 1
High-Performance Photodetectors Using Transition Metal Dichalcogenide (TMD)-based Hybrid Structures
Authors: Jo Seo-Hyeon , Park Jin-Hong 
Published: February 2020

Since the era of graphene, atomically thin transition metal dichalcogenides (TMDs) with a two-dimensional (2D) semiconducting layered structure have recently received increasing attention as suitable materials for post-silicon electronics and optoelectronics due to their exceptional electrical, mechanical, and optical properties. Particularly, TMDs present different energy band gaps depending on the type of TMDs and also exhibit strong optical absorption and ultrafast charge transfer, thereby providing many opportunities for researches in various optoelectronic devices, including photodetectors, solar cells, and light-emitting diodes. However, despite their superior optical properties, it is difficult for TMDs to absorb sufficient light due to their atomically thin body thickness, consequently restricting the successful integration of TMD-based optoelectronic device applications. In this light, various studies have been performed to improve the characteristics of TMD-based optoelectronic devices (especially photodetectors) through their hybrid structure, by applying the doping[1] or absorbing[2] (with very high absorption rate) layers, or inserting a passivating[3] layer (with suppression of carrier scattering), eventually improving the collection of photo-generated carriers.
Here, we demonstrate a high-performance TMD-based (WSe2 and ReSe2) photodetectors with a very high photoresponsivity (1.27×106 A/W for WSe2 and 1.18×106 A/W for ReSe2) and fast temporal photoresponse (rising/decaying time: 2.8/20.8 ms for WSe2 and 58/263 ms for ReSe2). This high-performance was accomplished by (i) applying a triphenylphosphine (PPh3)-based n-doping layer and (ii) inserting the passivating layers (hexagonal boron nitride (h-BN) or (3-aminopropyl)triethoxysilane (APTES) layers). The observed n-doping concentrations (Δn) were approximately 1.02 – 7.77×1011 cm-2 for TMD layers. By performing the PPh3-based n-doping process, the photoresponsivity of the TMD photodetectors increased (from 2.70×103 to 4.31×105 A/W for WSe2 and from 3.97×103 to 3.68×104 A/W for ReSe2). In particular, by additionally inserting a h-BN layer at the WSe2/SiO2 interface and an APTES layer at the ReSe2/SiO2 interface, we eventually obtained a very high photoresponsivity of 1.27×106 A/W for WSe2 and 1.18×106 A/W for ReSe2 while maintaining the other performance parameters (photoresponse times and photodetection range).

[1] D.-H. Kang, J. Shim, S. K. Jang, J. Jeon, M. H. Jeon, G. Y. Yeom, W.-S. Jung, Y. H. Jang, S. Lee, J.-H. Park, ACS Nano
2015, 9, 1099.
[2] S. H. Yu, Y. Lee, S. K. Jang, J. Kang, J. Jeon, C. Lee, J. Y. Lee, H. Kim, E. Hwang, S. Lee, J. H. Cho, ACS Nano
2014, 8, 8285.
[3] S. Wang, X. Wang, J. H. Warner, ACS Nano
2015, 9, 5246.
Medical Implants from a Unique Technology Combining a Highly Flexible Integration of Passives with Outstanding Performances
Authors: Bunel Catherine 
Published: February 2020

Many implantable medical devices such as pacemaker, cochlear implant have been developed and tremendously improved in battery power, functionality, electrical power consumption, system delivery, and wireless communication but there is still room for improvement and they are still facing challenges in size shrinkage and reliability. Many efforts have been engaged to miniaturize and to facilitate the implantation of the device in order to reduce the impact of the surgery. IPDiA technology is actively contributing to this progress by providing passive components such as capacitor arrays or RC networks, with a high level of miniaturization , very low profile , very low leakage current , and outstanding reliability. In this paper, the enablers such as design flexibility, co-integration, low leakage current, extended life time will be presented and illustrated by several examples of solutions. Firstly, the recent progress in the capacitor technology development will be presented , secondly the focus will be made on the key differentiators and finally some of the applications where this technology is inescapable will be depicted.
(Plenary) Doing More with Less: Challenges for Catalyst Layer Design
Authors: Putz Andreas Michael Vincent , Susac Darija , Berejnov Viatcheslav , Wu Juan , Hitchcock Adam P , Stumper Jürgen 
Published: February 2020

Proton exchange membrane (PEM) fuel cells are being developed as alternative energy sources for both residential and automotive application. In order for this technology to become fully commercial, the reduction of cost and improvements in performance and durability of PEM fuel cells membrane electrode assemblies (MEAs) are still required. To address the requirement for further cost reduction the Pt loading of the cathode catalyst layer (CCL) needs to be reduced to 0.2- 0.1 mg/cm2 while maintaining high efficiency of Pt-utilization at high power densities. Consequently, it becomes increasingly important to not only develop new catalyst materials, but also optimize the 3D structural arrangement of the CCL components such as catalyst, ionomer and void space so that all critical functionalities can be achieved simultaneously and optimize PGM utilization. In general terms this entails to provide sites catalytically active for ORR, and to further provide transport to/these sites for the reactants O2, protons, electrons and products H2O and heat, respectively. In order to be able to design CCL structures that meet the performance and durability requirements, it is necessary to obtain a better understanding of structure versus performance relationships. This requires the capability to fabricate different CCL structures, to characterize the spatial distribution of all components within the catalyst layer1,2 (carbon, Pt, ionomer and void), to measure the physico-chemical properties (both ex-situ and in-situ) and finally to use these experimental data as inputs for the development a model based understanding of the relationship between CCL structure and CCL performance and durability3.

References

A. P. Hitchcock, V. Berejnov, V. Lee, D. Susac and J. Stumper, “In situ methods for analysis of polymer electrolyte membrane fuel cell materials by soft X-ray scanning transmission x-ray microscopy”, Microscopy & Microanalysis 20(S3) 1532 (2014)

V. Lee, V. Berejnov, M. West, S. Kundu, D. Susac, J. Stumper, R.T. Atanasoski, M. Debe and A.P. Hitchcock, “Scanning Transmission X-ray Microscopy of Nano Structured Thin Film Catalysts for Proton-Exchange-Membrane Fuel Cells” J. Power Sources 263 163 (2014)

S. G. Rinaldo, W. Lee, J Stumper, M. Eikerling: “Nonmonotonic dynamics in Lifshitz-Slyozov-Wagner theory: Ostwald ripening in nanoparticle catalysts” Physical Review E 86, 041601 (2012)