3-Nm-Thick ZnO Nanoislands Charge Trapping Layer for Memory Devices Grown By Single ALD Step
Authors: El-Atab Nazek , Chowdhury Farsad Imtiaz , Ulusoy Turkan Gamze , Okyay Ali , Nayfeh Ammar 
Published: February 2020

Nonvolatile memory devices are essential components of almost all modern electronic equipment. However, in order to preserve the continuous scaling of current memory devices, the charge-trapping capability of the charge-trapping layer has to be further improved [1-4]. In this work, we demonstrate a MOS memory with charge trapping layer of ultra-thin 3-nm ZnO nanoislands grown by Atomic Layer Deposition (ALD). Atomic Force Microscopy (AFM), UV-Vis-NIR spectrophotometer, and high-frequency C-Vgate measurements are used to study the ZnO structures and the MOS memory.
The ZnO-nanoislands are grown by 20 thermal ALD cycles at a temperature of 180°C and pressure of 80-mtorr. The precursors used are Diethylzinc (DEZ) and H2O. The ALD process consisted of the following sequence: DEZ dose (0.02 s), N2 purge (10 s), H2O dose (0.1 s) and N2 purge (10 s). As a matter of fact, the growth-per-cycle in ALD can be less than a monolayer due to several reasons: steric hindrance, poorly reactive substrate with the reactants in ALD, large precursors, deposition at defect sites etc [5]. Therefore, islands growth is promoted, and as the film thickens, the islands start to coalesce and a continuous thin-film is obtained. The size and distribution of the nanoislands is studied using AFM tapping mode. The ZnO-nanoislands have an average width of around 20-nm as depicted in Fig. 1a. Fig. 1b shows a 3D image of the islands. The average height of the islands is 3-nm which is comparable with the Bohr radius of the excitons in ZnO (2.3-nm), therefore, quantum confinement effects in 1D are expected to be observed. A UV-Vis-NIR spectrophotometer is used to measure the transmittance and reflectance spectra of the ZnO-nanoislands and 18-nm continuous ZnO layer grown by ALD at the same temperature and pressure. The bandgap of both samples are calculated using the Kubelka-Munk function. The 18-nm ZnO layer shows a bandgap of 3.1 eV while the bandgap of the islands is increased to 3.4 eV which is consistent with quantum confinement effects.
The MOS memory cells are fabricated on highly doped n+ type Si wafer (111) (Antimony doped, 15-20 mΩ-cm) by a single ALD-step. First, a 4-nm of Al2O3 tunnel oxide is deposited at 300°C, followed by 20 cycles of ZnO deposited at 180°C. Then, 10-nm of Al2O3 blocking oxide is deposited by plasma assisted ALD at 200°C. The growth of the memory cells by single ALD step reduces contamination. Finally, the gate contacts are patterned by e-beam evaporating a 200-nm Al layer using a shadow mask with features size down to 10 μm. The cross-sectional illustration of the fabricated MOS-memory cells is shown in Fig. 2. High-frequency (1 MHz) C-Vgate measurements are conducted on the samples: first the gate voltage is swept from -10 to 10 V forward then backward with a hold time of 1-ms. A large threshold voltage (Vt) shift of 8.5 V is measured as depicted in Fig. 3 which indicates that ZnO-nanoislands have a large charge trapping density. Also, the memory is found to be fully programmed by storing holes in the ZnO. The measurements are repeated at different program/erase voltages as shown in Fig. 4, and the memory shows a large Vt shift at low operating voltages (4 V shift at 6/-6 V). In addition, the memory retention characteristic is studied by first programming/erasing the memory at 7/-7 V for 1 ms and measuring the Vt shift as a function of time. A loss of 15.3 % of the initial stored charge is observed after 10 years, which indicates that the holes are being confined well in the trap states available in the valence band offset and within the bandgap of ZnO. The endurance characteristic is also studied by measuring the Vt shift and plotting it as a function of programming/erasing cycles; an 11% loss of initial stored charge is lost after 104 cycles. Finally, the results indicate that ZnO-nanoislands grown by ALD are promising for future low-power charge trapping memory devices.
We gratefully acknowledge fund provided by the Office of Naval Research Global grant N62909-16-1-2031 and the L’Oreal-UNESCO For Women in Science Middle East Fellowship.
[1] N. El-Atab, et al. Physica Status Solidi (a), vol. 212, no. 8, pp. 1751-1755, 2015.
[2] A. Nayfeh, et al. 226th ECS meeting 2014, no. 37, pp. 1879-1879, 2014.
[3] A. Nayfeh, et al. ECS Trans., vol. 64, no. 17, pp. 45-49, 2014.
[4] N. El-Atab, et al. Nanoscale Res. Lett, vol. 10, no.1, p. 248, 2015.
[5] E. B. Yousfi, et al. Appl. Surf. Sci., vol. 153, no. 4, pp. 223–234, 2000.

Figure 1