Low Power FDSOI Technology and Devices for RF Applications
Authors: Schwan Christoph , Chew Kok Wai , Feudel Thomas , Kammler Thorsten , Faul Juergen , Kang Laegu , Taylor Richard , Huschka Andreas , Kluth Jon , Carter Rick , McKay Thomas , Nowak Edward , Watts Josef , Harame David L. 
Published: February 2020

Abstract: We report RF Characteristics in a Low Power High Performance Ultra-thin Body and Box (UTBB) FDSOI technology. The technology features Si-Channel nFETs and SiGe-Channel pFETS, a gate first HiKMG stack with a gate length (LG) of 20nm, BOX thickness (TBOX) of 20nm and is similar to that described previously[1]. The use of the backgate gate is shown to dynamically change the operating range and expand the dynamic range for RF. Competitive
f
T
s are reported for nFETs. The thin body architecture demonstrates high self gain. The technology is shown to be well optimized for applications like IoT where low power and RF performance are a premium.
UTBB FDSOI technology offers a superior technology for IoT because of the low power performance of the technology and RF performance. A TEM micrograph of the nFET silicon channel and pFET SiGe channel is sown in Figure 1. The high K metal Gate, thin channel silicon and SiGe channel, and raised source drains architecture can be seen clearly seen in the tem Micrographs. The FDSOI transistor has a back gate electrode which provides a unique capability to shift the threshold voltage and operating point of the transistor. This capability is shown in Fig. 2 and Fig. 3 which is a linear plot of Id versus Vgs for Vbg = -2, 0, and 2 Volt bias for the nFET and pFET respectively. The Drain current is well behaved and is shown to shift as the back bias changes the threshold voltage.
The digital low power performance of the technology is derived by the absence of drain to source leakage path and a steep subthreshold slope. The thin silicon channel and SiGe channel of 7nm prevents a leakage path and provides a fully depleted channel with superior electrostatics The technology Idsat current reaches 900μA/μm and 670μA/μm for NFET and PFET respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.8V. The Log Id vs Vgs plots for the nFET and pFET are shown in Fig. 4 at a gate length of 20nm. The subthreshold slope of 85 mV/decade demonstrates the steep subthreshold that enables a low threshold voltage to be maintained with low leakage. The output characteristic for nFET Lg=30nm is shown in Fig. 5. The flat shape of the curve also indicates both nFET has low gDs. Out conductance curves (not shown here) show no roll-off at high Vd indicating little if any self heating.
In this FDSOI technology the nFET tansconductance reaches gM ~ 1.8mS/um at Lg=20nm and the pFET transconductance reaches gMsat ~ 1.2.mS/um. The gMsat operating point may be adjusted with back gate bias as is shown in Fig. 6 for the nFET with a back gate bias with -2, 0, and 2 volts. The ratio of gMsat/gDS is the self gain wich is enhanced in fully depleted FDSOI technology. The self gain for the nFET is shown in Figure 7 with a back gate bias with -2, 0, and 2 volts.
RF Performance is extremely important for IoT and other applications. The RF simulated RF performance of the nFET achieves a peak
f
T
of over 300 GHz as is shown in Figure 8 which plots
f
T
vs Vgs for Vbg = -2, 0, and 2 Volts. Note how the operating point can be moved around just as in the gMsat figure by applying the appropriate back gate bias. This expanded dynamic range is also true for the pFET operation. These are the first FDSOI RF characterization results published on a 20nm Lgate HiKMG process.
References
[1] High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond, Q. Liu, et. al., IEDM, pp. 228-232, 2013

Figure 1