(Invited) Investigation of Plasma Defect Engineering in ZrO2-Based RRAM Devices for Low Power in-Memory Computing
Authors: Zeinati Aseel , Misra Durgamadhab , Triyoso Dina H. , Tapily Kandabara , Clark Robert D , Lombardo Sarah , Wajda Cory S , Leusink Gert J 
Published: December 2024

Resistive random-access memory (RRAM) is a promising candidate to be used for in-memory computing applications due to its low power consumption, high scalability, high density, significant endurance, good retention, and low cost [1-2]. The usage of zirconium dioxide (ZrO2) as the switching layer in RRAM stacks has garnered attention due to its high thermodynamic stability, simple structure, and CMOS process compatibility [3-5]. In addition, introducing a hydrogen (H) plasma treatment to the switching layer reduced the forming power since it improved the oxygen vacancies (Vo) and defects distribution near the top electrode (TE) and switching layer interface [6].
In this work, we investigated five ZrO2-based RRAM devices with titanium nitride (TiN) as top and bottom electrodes. Figure 1 shows the schematics for the devices that have been investigated in this work. Device-A that has stochiometric ZrO2 switching layer was compared with devices B, C, D, and E that have been treated with H-plasma. The treated devices vary by the insertion position of the plasma during the deposition of the oxide layer, optimized to reduce initial defect levels [7]. The oxide layer of device-B - 7nm of ZrO2 - was fully deposited, followed by the H-plasma. While device-C had the H-plasma at the midpoint of the 7nm oxide. Device-D oxide was deposited as 3.5nm ZrO2, followed by H-plasma followed by 4nm ZrO2 that has the interface with the TE. Device-E was deposited as 3.5nm ZrO2, followed by H-plasma, followed by 3nm ZrO2 that has the interface with the TE.
We studied the leakage current of the devices to investigate the number of defects in the oxide layer since it plays a significant role in reducing the forming power, as previously reported [8]. While it is well-known that the devices with higher leakage current have more defects [9], devices from wafer-A (7nm stochiometric ZrO2) show the lowest leakage current. The devices were then formed with a DC voltage sweep and compliance current between 1nA-100mA and observed a trend between the leakage current (number of defects) and the forming power, device-A consumed the highest forming power (122mW) as expected due to fewer defects in the oxide layer, which matched with the leakage current measurements.
The leakiest devices - device-C (TiN/3.5nmZrO2/H-plasma/3.5nmZrO2/TiN) and device-D (TiN/4nmZrO2/H-plasma/3.5nmZrO2/TiN) - consumed the lowest power while forming (0.46nW) and (0.24nW) respectively- which confirms that more defects inside the oxide layer support the electron transport and lead to reduction of the forming power [10]. While device-B (TiN/H-plasma/7nmZrO2/TiN) has higher leakage current and lower forming power (2.5nW) than device-E (TiN/3nmZrO2/H-plasma/3.5nmZrO2/TiN) that consumes (4.7nW) to form the conductive filament. A thinner layer can't passivate the defects, resulting in a uniform spread of Vo related defects throughout the dielectric thickness, which increases the forming voltage as observed in device-E (TiN/3nmZrO2/H-plasma/3.5nmZrO2/TiN). A thicker cap layer, on the other hand, allows for reoxidation, and the migration of oxygen vacancies towards the top, ultimately reducing the forming voltage as observed in device-D (TiN/4nmZrO2/H-plasma/3.5nmZrO2/TiN) [7].
Since the devices are expected to be used in memory computing, a pulse operation was performed with amplitude variation to quantize the conductance states. Device-C and device-D show a good quantization, with no overlap between the states and low fluctuations for each state compared to device-B, which shows degraded fluctuations and overlap between the states due to reduced defect distribution near the interface with the TE [11].

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Figure 1