bluuebunny/crossref_metadata_2025_split huggingface dataset:
Via Electromigration Related Functional Failure—A Case Study
Authors: Chowdhury Vijay 
Published: December 2020

Abstract
Specialized structures have been developed to understand how interconnect and via would link together in a circuit to bring out the weakest link in the interconnect-via system. This article reports a phenomenon where electromigration occurred in an actual circuit with signal lines connected by individual vias. A prediction is made into the weak link in the via-Interconnect system based on real time product. In the interconnect-via system used, the TiW barrier blocked the material flow from M2 to Ml. W plugs would block the material flow as they do with the barrier layers and the failures would occur at the via to interconnect interface as noticed in this case. Depending on the electron flow through the via, the material will either accumulate at the via-interconnect interface, which will induce inter-metal dielectric cracks, or deplete, causing discontinuity (opens) of the interconnect lines.
Experiment Study on Crystal/Amorphous Structure of TEM Samples Prepared by FIB Milling
Authors: Gao Qiang , Zhang Mark , Niou Chorng , Li Ming , Chien W.T. Kary 
Published: December 2020

Abstract
It has been reported that a sample prepared by ion beam milling has a sandwich structure with amorphous on two sidewalls and crystal in the middle. In this paper, the sandwich structure of such a single crystal TEM sample was studied experimentally. A novel sample and its fabrication process were reported. The sandwich structure can be observed directly in TEM with this sample. When the crystal layer in monocrystal silicon TEM sample is less than 18 nanometers, or when the sample is thinner than 64 nanometers, the sample will be observed as fully amorphous. Removal of the amorphous layer on the sample sidewalls is crucial to get TEM pictures of better quality.
A Study of Flip-chip Open Solder Bump Failure Mechanism
Authors: Wang Zhaofeng , Choudhry Mahmood 
Published: December 2020

Abstract
The present paper is a study on flip-chip open bump failure mechanism. Initial electrical testing showed open circuit condition. Scanning acoustic microscope (C-SAM) identifies delamination on particular bump(s). Initial cross-sectional images suggested that the separation took place at Al – TiW interface. However, EDS analysis on the separated surface indicated the presence of Al metal at both sides of the separation, which raises a question of why the Al layer is cracked or separated instead of interface de-lamination. Research in literature and investigation at assembly line points an ultrasonic cleaning step in manufacturing process as a contributor to the open bump failure. Examining virgin dice after bump removal observed crack in nitride passivation around the bump neck, indicating high stress level during passivation film deposition and/or bump formation process. Hence it is concluded that ultrasonic cleaning in device assembly aggravates preexisting stress in weak bump(s), resulting in latent failure in field application.
Realization of an Integrated IT System Covering the Complete Failure Analysis Process
Authors: Grützner Markus 
Published: December 2020

Abstract
In the failure analysis (FA) process, a large amount and variety of data are involved: product information, images created by lab equipment, requester and accounting information, etc. Instead of using separate tools for image handling, sample tracking, report creation, and email, workflows can be improved by integrating all these functions in one single IT system. This paper describes the process and result of developing a dedicated FA software tool. The discussion provides details of the specification, main features, and architecture of the system. This system has been rolled out at 15 labs and is used by approx. 500 analysts and several thousands of company-internal FA customers. The flexible architecture made the adaptation to all the different business processes possible and provides a future-proof solution.
Studies of Silicon Dust Corrosion on Microchip Al Bondpads and Elimination of Silicon Dust During Wafer Sawing Process
Authors: Younan Hua , Siping Zhao , Zhiqiang Mo , Ying Cho Jie 
Published: December 2020

Abstract
After wafer-die sawing process, sometimes silicon (Si) dust on microchip Al bondpads is difficult to be cleaned away by DI water, especially at pinhole/corrosive areas caused by galvanic corrosion, thus resulting in non-stick on pads (NSOP) problem in assembly process. To eliminate NSOP problem due to Si dust contamination, in this paper, we will study the mechanism of Si dust contamination and propose a concept of Si dust corrosion. A theoretical model will be introduced so as to explain Si dust contamination and corrosion problem during wafer die sawing process. Based on the mechanism proposed, Si dust contamination and corrosion is related to galvanic corrosion as OH- ions generated from galvanic corrosion will not only react with Al to cause Al corrosion, but also react with Si dust to cause Si dust corrosion. During Si dust corrosion, poly-H2SiO3 and Si-Al-O complex compounds will be formed on Al bondpads, especially at the pinholes/corrosive areas. Poly-H2SiO3 and Si-Al-O complex compounds are “gel-like” material and stick onto the surface of bondpads. It is insoluble in water and difficult to be cleaned away by DI water during or after wafer die sawing process and will cause bondpad discoloration or/and NSOP problem. Some eliminating methods of Si dust contamination and corrosion on Al bondpads during wafer die sawing process are also discussed.
Accelerated Corrosion of Printed Circuit Boards Due to High Levels of Reduced Sulfur Gasses in Industrial Environments
Authors: Mazurkiewicz Paul 
Published: December 2020

Abstract
Accelerated corrosion leading to system failure has been observed on printed circuit boards present in industrial environments that contain abnormal levels of reduced sulfur gasses, such as hydrogen sulfide (H2S) and elemental sulfur. The problem is compounded by the fact that elemental sulfur is regulated by OSHA as a nuisance dust, and is allowed in a human working environment at the parts per thousand levels. Anecdotal data shows clearly that elemental sulfur gas present at the parts per million level can cause computer systems to fail within 2 months of use. Newer technologies such as immersion silver plating are especially susceptible to this type of corrosion. With the rapid growth of organically coated copper (OCC) and immersion silver platings, the number of failures due to reduced sulfur gasses in the environment has risen substantially.
Ion Beam Imaging Methodology of Invisible Metal under Insulator Using High Energy Electron Beam Charging
Authors: Wang C.H. , Chang S.P. , Chang C.F. , Chiou J.Y. 
Published: December 2020

Abstract
Focused ion beam (FIB) is a popular tool for physical failure analysis (FA), especially for circuit repair. FIB is especially useful on advanced technology where the FIB is used to modify the circuit for new layout verification or electrical measurement. The samples are prepared till inter-metal dielectric (IMD), then a hole is dug or a metal is deposited or oxide is deposited by FIB. A common assumption is made that metal under oxide can not be seen by FIB. But a metal ion image is desired for further action. Dual beam, FIB and Scanning Electron Microscope (SEM), tools have a special advantage. When switching back and forth from SEM to FIB the observation has been made that the metal lines can be imaged. The details of this technique will be discussed below.
Cross-Sectional Sample Preparation Techniques for 2D Doping Profiling of Specific Site by SCM
Authors: Lee Tae-Kwon , Back Tae-Sun , Kim Jong-Hyeop , Park Yoon-Baek , Kim Ho-Joung , Lee Soun-Young 
Published: December 2020

Abstract
Scanning capacitance microscopy (SCM) is an SPM technique which measures capacitance variation between tip and sample generated by applied AC bias while the tip is scanning in contact mode. Focused ion beam (FIB) milling is the more precise method to perform cross-sectioning of a specific site. The surface amorphization and charge trap layers formed during FIB machining affect the SCM dC/dV signal. This article demonstrates that micro-cleaving and FIB milling are capable of preparing a cross-sectional sample for 2D doping profiling of a specific site for SCM observation. Using the Micro-cleaving technique, a cross-sectional sample can be prepared easily with higher accuracy and shorter time than using a polishing method. However, Micro-cleaving can't be used by itself in the case of cross-sectioning a pattern formed by front end processing of sub-micron patterns. The FIB technique can assist the Micro-cleaving technique in cleaving of front end patterns.
Combining the Nano-Probing Technique with Mathematics to Model and Identify Non-Visual Failures
Authors: Shen Cha-Ming , Chuang Tsan-Chen , Lin Shi-Chen , Wen Lian-Fon , Huang Chen-May 
Published: December 2020

Abstract
In this paper, we focus on how to identify non-visual failures by way of electrical analysis because some special failures cannot be observed by SEM (scanning electron microscopy) or TEM (transmission electron microscopy) even when they are precisely located by other analytical instrumentation or are symptomatic of an authentic or single suspect. The methodology described here was developed to expand the capabilities of nano-probing via C-AFM (conductive atomic forced microscopy), which can acquire detailed electrical data, and combining the technique with reasoned simulation using various mathematic models emulating all of the significant failure characteristics. Finally, a case study is presented to verify that such defect modes can be identified even when general PFA (physical failure analysis) cannot be implemented for investigating non-visual failure mechanisms.
Fault Isolation of Soft P-N Junction Break Down Due to Plasma Charging
Authors: Nguyen Dat , Dudar Taras 
Published: December 2020

Abstract
The P-N junctions are part of the construction of semiconductor devices. They are formed by the combination of P-type and N-type diffusions. This paper discusses a soft (small early conduction) P-N junction breakdown. The P-N junction in this work is a part of a differential amplifier, which is widely used in analog/mixed signal devices. The paper outlines the test techniques to detect the differential amplifier failure, the circuit analysis (design and simulation), the fault isolation, and the root cause analysis with data from the wafer fabrication process to support plasma charging on the emitter. The real physical defect was not observable. However, with the help of lab data, the failure can be explained as plasma charging.
From Static to Full Dynamic Laser Stimulation
Authors: Deyine A. , Sanchez K. , Perdu P. , Battistella F. , Deslandes H. , Lewis D. 
Published: December 2020

Abstract
Limitations of backside optical techniques for failure analysis of dynamically activated devices have underlined the need to extend the capabilities of Dynamic Laser Stimulation techniques (DLS). DLS techniques provide a precise localization of the dynamically failing area, but it lacks timing information as the fault is often related to a specific test vector. Optical probing techniques such as TRE and LVP [1, 2] are hardly applicable on cases with long test loop and for which no preliminary information is available on the time window of interest. Defect localization and electrical tests can be coupled in order to provide more accurate information about the failure, especially vector information in addition to x and y localization. We have developed a Full Dynamic Laser Stimulation (F-DLS) approach based on laser modulation by electro optic modulator to face this challenge. The purpose of this paper is to present DLS limitations, our motivations, comparisons with other DLS extensions, FDLS implementation on our system, application example and future F-DLS developments.
Global Die Ultra-Thin Silicon for Backside Diagnostics and Circuit Edit
Authors: Scott Dane , O’Donnell Erin , Malik Tahir , Jain Rajesh 
Published: December 2020

Abstract
For more than 10 years, silicon thinning techniques have been relegated to an art form of mere necessity to enable complex optical probing and circuit edit analysis. Silicon thinning is a fundamental aspect of diagnostic analysis and while it is well-understood that limitations in the area of silicon thinning can severely limit high-quality diagnostic results, poor thinning results have generally been accepted as standard environmental operating conditions with which optical probe and circuit edit engineers must cope. Presented here is a scientific approach to thinning silicon to enable predictable high-precision, high-quality results. Remaining silicon thickness (RST) has been debated throughout the years because it was uncertain how much thinning was excessive. Primary perceived limitations included mechanical constraints (package / die warping) and post-thinning thermal control. Adding to the complexity of the discussion has been the fact that RST has been largely uncertain because analysis usually involved determining how much silicon was removed rather than how much silicon remains. All of these challenges have been overcome. A novel process has been developed to ultra-thin bulk Si to as low as 10um remaining Si thickness, eliminating the need for the Laser Chemical Etcher for circuit edit and improving optical emission probing considerably. This sample preparation process has been used on Intel Core2 Duo products with a success rate of 98%. Post FIB unit testing is a critical step in this debug process. A technique was developed to calibrate the change in thermal resistivity of the ultra-thin unit such that it will remain within 100ps of its original FMax performance in 90% of tests.
In Situ Removal of Polyimide Layer Using Modified Decapsulator
Authors: Ramachandra C. , Sweety B.M. , Chandan U.G. , Jaypal D. , Dash Sarat Kumar , Ravindra M. , Khan A.M. 
Published: December 2020

Abstract
Removal of polyimide layer after decapsulation of IC package is essential for many of the failure analysis techniques. An alternative method for polyimide removal is described in this paper. The method suggests appropriate modification of dual acid decapsulation system for this purpose. Device integrity is verified after removal of polyimide layer. This method becomes promising for devices which are sensitive / vulnerable for exposure to plasma.
Studies on a Qualification Method (OSAT) of Microchip Al Bondpads in Wafer Fabrication
Authors: Younan Hua , Ramesh Rao Nistala , Adrian Ng , Tony Tsai 
Published: December 2020

Abstract
Non-stick on pad (NSOP) is a yield limiting factor that can occur due to various reasons such as particle contamination, galvanic corrosion, Fluorine-induced corrosion, process anomalies, etc. The problem of NSOP can be mitigated through a careful process characterization and optimization. In this paper, a bondpad qualification methodology (OSAT) will be discussed. It will be argued that by employing different physical analysis techniques in a failure analysis of wafer fabrication, it is possible to perform comprehensive characterization studies of the Aluminum bondpad so as to develop a robust far backend of line process. A good quality Al bondpad must meet the following four conditions-OSAT: (i) it should be no discoloration (using Optical inspection); (ii) should be defect free (using SEM inspection); (iii) should be with low contamination level (such as fluorine and carbon contamination should be within a control limit) (using Auger analysis) and (iv) should have a protective layer on bondpad surface so as to prevent bondpad corrosion (using TEM).
Degradation Analysis of Thick Film Chip Resistors
Authors: Sood Bhanu , Das Diganta , Azarian Michael H. , Pecht Michael 
Published: December 2020

Abstract
Negative resistance drift in thick film chip resistors in high temperature and high humidity application conditions was investigated. This paper reports on the investigation of possible causes including formation of current leakage paths on the printed circuit board, delamination between the resistor protective coating and laser trim, and the possibility of silver migration or copper dendrite formation. Analysis was performed on a set of circuit boards exhibiting failures due to this phenomenon. Electrical tests after mechanical and chemical modifications showed that the drift was most likely caused by moisture ingress that created a conductive path across the laser trim.
Copper to Aluminum Bonding: IMC Characterization through New Mechanical Sectioning Methods
Authors: Copeland Lucas , Saran Mukul 
Published: December 2020

Abstract
This paper presents a mechanical cross-sectioning approach that produces an image clarity not yet demonstrated in published literature. It demonstrates how a critical sequence of polishing, basic slurry optimization and staining, in conjunction with correct imaging parameters can be used to highlight the growth morphology of the intermetallic compound (IMCs). Utilizing this approach, the paper describes the results of a SEM imaging study of the intermetallic formation and growth at the Cu-Al bond interface during thermal ageing for up to 4000hrs at 150 deg C. The paper uses direct SEM imaging to catalog observations which are used to create an initial model for IMC and void growth at the wire bonded interface. It examines the effect of aluminum splash and concludes that growth of intermetallics at the Cu-Al interface is rapid into the bond-pad aluminum than into the Cu-ball, but the growth thickness uniformity is much higher into the Cu-ball.
Timing Characterization of a Tester Operated Integrated Circuit by Continuous and Pulsed Laser Stimulation
Authors: Kiyan Tuba , Brillert Christof , Boit Christian 
Published: December 2020

Abstract
The scope of this work is to investigate the timing characteristics of a state of the art fully functional IC through continuous wave (CW) and pulsed laser stimulation. The propagation delay of a gate depends on the drain current of nMOS and pMOS transistors, load capacitance and supply voltage. Localized photocurrent induced by laser beam alters some of these electrical characteristics, resulting in a change in the switching time of the gate. In addition to the desired local timing influence, a global effect on the timing throughout the full scanning period occurs as secondary phenomenon that - if not taken into account properly, may mask the local signal. This effect is strong under CW laser operation and can be drastically reduced in pulsed laser condition.
Fault Isolation on High Resistance Failure of 45nm ET Via Chains Using Combined Technique of SEM PVC and Nanoprobing
Authors: Tan P.K. , Mai Z.H. , Goh Y.W. , Zhu L. , Toh S.L. , Deng Q. , He R. , Tan H. , Li H.L. , Wang Q.F. , Ma Y.Z. , Lee W.Y. , Low G.R. , Lam Jeffrey 
Published: December 2020

Abstract
Electrical Test (ET) structures are used to monitor the health and yield of a process line. With the scaling down of semiconductor devices to nanometer ranges, the number of metal lines and vias increase. In order to simulate the electrical performance of devices and to increase the sensitivity for line health check, ET structures are designed to be more complicated with a larger area. Hence, fault isolation and failure analysis become more challenging. In this paper, the combined technique of Scanning Electron Microscope (SEM) Passive Voltage Contrast (PVC), Nanoprobing technique, and Divide and Conquer Method (DCM) are proposed to locate open failure and high resistance failure in an ET via chain.
Neon Ion Microscope Nanomachining Considerations
Authors: Tan Shida , Livengood Richard H. , Hallstein Roy , Shima Darryl , Greenzweig Yuval , Notte John , McVey Shawn 
Published: December 2020

Abstract
Nanomachining capability scaling both in the areas of machining precision and novel gas chemistries are required for focused ion beam technology to keep pace with process technology advancement. In this paper, we review the nanomachining potential for the Helium Ion Microscope (HIM) and the Neon Ion Microscope (NIM). The paper also includes an in depth analysis of NIM imaging resolution, subsurface material interaction, and nanomachining performance.
Characterization of MOS Transistors Using Dynamic Backside Reflectance Modulation Technique
Authors: Teo J.K.J. , Chua C.M. , Koh L.S. , Phang J.C.H. 
Published: December 2020

Abstract
The channel of metal-oxide-semiconductor (MOS) transistors at different modes of operation has been characterized using dynamic backside laser reflectance modulation technique for different NMOS and PMOS transistors with different channel lengths. The reflectance modulations contain a primary peak near the drain-end when the MOS transistor is in saturation mode. Comparison studies with a Pseudo-Two-Dimensional analytical model support the hypothesis that the observed peak corresponds to the pinch-off point.
Infrared Thermography Developments for III-V Transistors and MMICs
Authors: Carisetti Dominique , Bouya Mohsine , Bezencenet Odile , Servet Bernard , Clément Jean-Claude , Lambert Benoit , Caille Laurent , Malbert Nathalie , Labat Nathalie 
Published: December 2020

Abstract
This paper focuses on infrared (IR) thermography capabilities on III-V components for thermal measurements applications and failure analysis (FA). The first part discusses the thermal mapping on InGaAs/AlGaAs PHEMT structure and compares IR thermal measurement with the well-known techniques as Raman and SThM. The second part discusses IR thermography on challenging FA for hot spot detection on the most popular type of capacitor for III-V MMICs as the metal-insulator-metal capacitor. It shows how IR thermography can easily localize very small pinholes in SiN, where liquid crystal and OBIRCH techniques are not well adapted.
Near-Infrared Photon Emission Spectroscopy Trends in Scaled SOI Technologies
Authors: Kindereit Ulrike , Weger Alan J. , Stellari Franco , Song Peilin , Deslandes Hervé , Lundquist Ted , Sabbineni Prasad 
Published: December 2020

Abstract
In this paper, near-infrared photon emission spectroscopy measurements from ring oscillators in 45 nm and 32 nm SOI process technology are compared. Employing a cryogenically cooled camera, the measurements cover a broad spectral range from 1200-2200 nm. Both leakage and switching emission, increase monotonically with the wavelength, suggesting measurements should be made at longer wavelengths than has historically been practiced. The paper discusses the optimum cut-off wavelength for maximum signal-to-noise ratio and the obvious importance of reduced ambient temperature for performing measurements.
Improving the DLS Workflow
Authors: Bodoh Dan , Erington Kent 
Published: December 2020

Abstract
In this paper, we describe improved hardware to connect a semiconductor tester or applications board to a laser scanning microscope (LSM) for performing dynamic laser stimulation (DLS). The hardware, called DXGlue, simplifies the DLS workflow and enables new applications. We describe its precise monitoring of the fail rate and fail mode, its use for time resolved DLS and the enabling of long test loops with short laser dwell times.