bluuebunny/crossref_metadata_2025_split huggingface dataset:
Failure Analysis for Gate Oxide Breakdown
Authors: Chen Xianfeng , Li Ming , Guo Qiang , Chien Kary , Gao YanBo 
Published: January 2021

Abstract
Damage-free gate oxide is one of the important factors to ensure device performance and reliability. Special wafer accepts test structures such as a large size MOS capacitor must be laid on test line to monitor the oxide process issue and process window. However, it brings about many challenges to failure analysis engineer. To overcome the EFA and PFA limitations, fresh samples were taken from the passed wafer and the failed ones to identify the root cause of VBD failure. A novel lapping down method was used to access the capacitor structure. Two VBD failure cases were studied. In this study, poor wet clean process was defined as the cause of the silicon substrate surface damage and crystalline defect. It induced poor oxide deposition, which reduced breakdown voltage. Additionally, 12hrs BOE dip was shown to be an effective method for removing poly and oxide layers from large MOS capacitors.
Techniques for Identification of Silver Migration in Plastic Encapsulated Devices Assembled with Molding Compound Containing Red Phosphorus Flame Retardant Material
Authors: Hylton Ronald R. 
Published: January 2021

Abstract
This paper describes the electrical signatures and failure analysis techniques used to identify plastic encapsulated devices that have failed due to silver migration. This migration, which produces resistive leakages between adjacent pins, has been associated with molding compounds that utilize red phosphorous as a flame retardant material. A description of the failure mechanism is also presented.
An Analysis of Tungsten FIB-Fabricated Via Resistance
Authors: Niles David W. , Meyer Jay , Kee Ronald W. , DiBattista Michael 
Published: January 2021

Abstract
We present an analysis of tungsten vias fabricated by a focused ion beam with regard to the understanding of circuit editing strategies. The growth rate of W is ~10 times faster in high aspect ratio vias than on flat surfaces, and W in vias has 4 at. % more C but only one-tenth the Ga of surface-deposited W. We propose that vias act like small Faraday cups, trapping the energy of the Ga+ ions and the reaction byproducts to enhance the growth rate of W and to increase the C to W ratio in vias compared to flat surfaces. The resistivity of W in the vias determined by a least squares fit to resistance data is 250μΩ-cm, unchanged from the resistivity of W deposited on a flat surface. The resistances of the vias fabricated in a SiO2 layer to contact an underlying Al sheet layer fit well to either of two models: 1) an effective area model that invokes resistive via sidewalls that do not participate in conduction, and 2) an contact resistance model that invokes tapered vias with a constricted W/Al contact area.
Insulator Deposition for Through Conductor Editing
Authors: Richardson Chris , Martin Mark , Malik Tahir , Barone Jerrold P. 
Published: January 2021

Abstract
Circuit Edit (CE) through a conductor requires an insulator to isolate the connection transiting the conductor. We investigate several recipes to determine not just the optimum recipe but also the latitude to provide a means of throughput optimization for a given edit requirement. The results show that trade-offs in deposition rate, robustness and isolation quality can be made to enable this throughput optimization.
Photon Emission Spectral Signatures of AlGaN/GaN HEMT for Functional and Reliability Analysis
Authors: Glowacki Arkadiusz , Boit Christian , Lossy Richard , Würfl Joachim 
Published: January 2021

Abstract
Non-degraded and degraded AlGaN/GaN HEMT devices have been characterized electrically and investigated in various operating modes using integral and spectrally resolved photon emission (PE). In degraded devices the PE dependence on the gate voltage differs from the non-degraded devices. Various types of dependencies on the gate voltage have been identified when investigating local degradation sites. PE spectroscopy was performed at various bias conditions. For both devices broad spectra have been obtained in a wavelength regime from visible to near-infrared, including local performance variations. Signatures of the degradation have been determined in the electrical characterization, in integral PE distribution and in the PE spectrum.
A Novel OBIRCH Fault Isolation Method to Locate the Leakage Failure Point
Authors: Huang Chi-Lin , Shu Yu Hsiang 
Published: January 2021

Abstract
Conventional isolation techniques, such as Optical Beam Induced Resistance Change (OBIRCH) or photoemission microscopy (PEM) frequently fail to locate failure points when only applied to power pin of the semiconductor device. In this paper, a novel OBIRCH failure isolation technique is utilized to detect leakage failures. Different test conditions are presented to identify the differences in current when all input pins are pulled high in an OBIRCH system. In order to verify a failure point, it is necessary to perform electrical analysis of the suspected failure point in the failing sample. In general, Conductive Atomic Force Microscope (C-AFM) and a Nano-Prober is sufficient to provide the electrical data required for failure analysis. Experiment results, however, prove that this novel OBIRCH failure isolation technique is effective in locating the failure point, especially for leakage failures. The failure mechanism is illustrated using cross-sectional TEM.
Dynamic Laser Stimulation Technique for Device Qualification Process
Authors: Deyine-Barth A. , Perdu P. , Benetti G. , Sanchez K. , Battistella F. , Lewis D. 
Published: January 2021

Abstract
A key point to guarantee electronic device quality is device qualification. This part of the process is a significant contributor to the time and cost of the development and production of any electronic device. A device is required to perform a task and its operational lifetime is a key issue for the end user. The more sensitive the qualification technique is, the faster marginalities in the device parameters could be observed. Dynamic Laser Stimulation techniques fill this requirement and could be used in conjunction with traditional qualification procedures.
Lead Frame Metal Migration in an Encapsulated IC Package
Authors: Eslinger William 
Published: January 2021

Abstract
This case study details a latent integrated circuit (IC) failure mechanism caused by the migration of silver (Ag) inside the encapsulated package of a CMOS (complementary metal-oxide-silicon) device. The plating of the lead frame was the source of the migrated silver, which was redeposited along the interface between the die attach epoxy and the plastic encapsulate. The resulting metallic ‘stringers’ bridged adjacent lead frame legs over distances greater than 150 μm and created relatively low-resistance paths capable of carrying 100’s of micro-amps.
Reliability for Pure CMOS One-Time Programmable Memory Using Gate-Oxide Anti-Fuse (eFuse)
Authors: Wakai Nobuyuki 
Published: January 2021

Abstract
The reliability of a pure CMOS One-time Programmable (PCOP) Memory was investigated. The memory is programmed with and anti-fuse formed by the breakdown of the thin gate oxide. The results of reliability stress tests show that the PCOP memory is stable and reliable for normal using environmental conditions.
Single Die 'Hands-Free' Layer-by-Layer Mechanical Deprocessing for Failure Analysis or Reverse Engineering
Authors: Moor Tony , Malyanker Eli , Raz-Moyal Efrat 
Published: January 2021

Abstract
The idea behind Destructive Semiconductor Reverse Engineering (DSRE) is to investigate a device in part or as a whole using many of the techniques employed in the physical failure analysis (PFA) field. The device is usually examined for intellectual property/patent protection or competitive analysis purposes. This paper presents a technique for the full layer-by-layer deprocessing of a single semiconductor device using purely mechanical polishing for DSRE or FA. It describes a step-by-step method developed by Raw Science/Datel Design and Development and Gatan for the reliable, purely mechanical deprocessing of individual dice. The paper presents the two modifications made to the process to virtually eliminate the edge effects. A computer controlled mechanical polishing system coupled with a unique customized process allows for the investigation of those one of a kind samples as a whole with 100% success rate.
Characterization and Failure Analysis of Wafer Bonded Devices and Unfilled Through-Silicon-Vias (TSVs)
Authors: Cassidy C. , Kraft J. , Koppitsch G. , Brandlhofer E. , Steiner M. , Schrank F. , Erwin D. , Raz-Moyal E. 
Published: January 2021

Abstract
This paper is concerned with characterization and failure analysis challenges posed by 3D integration of semiconductor devices, with a particular focus on wafer bonded components and Through Silicon Vias (TSV). Requirements for sample preparation are discussed, along with advantages and limitations exhibited by various different techniques. Analysis examples with real devices are presented, along with successful sample preparation solutions enabled by a precision polishing toolset.
Timing Failure Debug Using Debug-Friendly Scan Patterns and TRE
Authors: Burmer Christian , Guo Ruifeng , Cheng Wu-Tung , Lin Xijiang , Benware Brady 
Published: January 2021

Abstract
In this paper, we describe a silicon debug flow that uses debug-friendly scan test patterns to improve the efficiency of physical fault isolation of timing failures using time-resolved emission (TRE) system. Several techniques have been developed to generate the debug-friendly test patterns. We further show a silicon debug case of a 90nm design based on the proposed debug flow.
Deterministic Localization and Analysis of Scan Hold-Time Faults
Authors: Hwang Jaecheol , Kim Daegyu , Seo Namsik , Lee Euncheol , Choi Wooseong , Jeong Yeongtaek , Orbon J. , Cannon S. 
Published: January 2021

Abstract
This paper presents a deterministic diagnosis analysis method for hold-time faults in scan chains. The defects discussed in this paper are primarily seen at low Vdd values, so called Vdd-min defects; Vdd -max defects can also be a problem. Traditional approaches require data collection, the creation of additional patterns, and an iterative trip back to the tester. This is a time consuming process and does not always lead to a closed end solution. This paper also presents a method to detect multiple hold-time faults in the chain using auto generated pattern, real-time on the tester. The approach includes validation of the hold-time fault model, characterization of the failure behavior in terms of Vdd and data dependencies and finally localization to a cone of logic including the data paths and the clock trees. This method of hold-time localization is organized into three steps. First, the chain integrity test is run at the safe voltage. Second, a set of new patterns is created and run at the failing voltage. Finally, the data is shifted out and compared with the simulation result. The data provides the locations of all of the hold-time faults for the selected failing voltage. Combined with silicon voltage probing, the technique allows the analysis to localize the faults and to measure timing slack on sub-nets in the failing circuitry. This allows very close correlation between timing models and silicon performance leading to more robust design/process matching.
Combining Refractive Solid Immersion Lens and Pulsed Laser Induced Techniques for Effective Defect Localization on Microprocessors
Authors: Quah A.C.T. , Goh S.H. , Ravikumar V.K. , Phoa S.L. , Narang V. , Chin J.M. , Chua C.M. , Phang J.C.H. 
Published: January 2021

Abstract
The spatial resolution and sensitivity of laser induced techniques are significantly enhanced by combining refractive solid immersion lens technology and laser pulsing with lock-in detection algorithm. Laser pulsing and lock-in detection enhances the detection sensitivity and removes the ‘tail’ artifacts due to amplifier ac-coupling response. Three case studies on microprocessor devices with different failure modes are presented to show that the enhancements made a difference between successful and unsuccessful defect localization.
Failure Analysis of Single Shared Column Fail in DRAM Using Nano-Probing Technique
Authors: Kim Suk Min , Lee Jung Ho , Lee Jong Hak , Kim Hyung Ki , Chang Myung Sick , Lee Jung Hoon , Hong Sung Joo 
Published: January 2021

Abstract
We report an analysis of a single shared column fail on DRAM technology using a nano-probing technique in this work. The electrical characteristics of the failed transistors show that the column fails were caused by two different failure mechanisms: abnormal contact and implant profiles. We believe that electrical analysis using nano-probing will be a powerful tool for non-visible failure analysis in the future because it is impossible to clearly reveal these two different failure mechanisms solely using physical failure methods.
Low Voltage, Low Current AFP Characterization of Non-Visible Soft Transistor Defects
Authors: Mulder Randal , Subramanian Sam , Chrastecky Tony 
Published: January 2021

Abstract
This paper presents case studies that examine low voltage, low current electrical characterization and analysis of data that could help identify root cause failure mechanisms for soft transistor failures, providing a review of Vt shifts and blocked LDD implants review. The case studies demonstrate the importance of getting the most information possible out of all aspects of the nanoprobe electrical characterization results for failing transistors. Technology computer aided design (TCAD) modeling of transistor defects will be a useful tool for the nanoprobe analyst to identify the subtle defects that can only be identified through careful electrical characterization in conjunction with process analysis and experiments by the manufacturing facility. However, modeling at the transistor level has its difficulties. The key will be to build a library of electrical signatures with corresponding defects as they are discovered.
Investigation on Focused Ion Beam Induced Damage on Nanoscale SRAM by Nanoprobing
Authors: Hendarto E. , Toh S.L. , Tan P.K. , Goh Y.W. , Cai J.L. , Ma Y.Z. , Mai Z.H. , Lam J. , Sudijono J. 
Published: January 2021

Abstract
As electronic devices shrink further in the nanometer regime, electrical characterization using nanoprobing has become increasingly important. Focused ion beam (FIB) is one useful technique that can be used to create markings for ease of defective site identification during nanoprobing. This paper investigates the impact of FIB exposure on the electrical parameters of the pull-up (PU), pull-down (PD) and pass-gate (PG) transistors of 6-Transistor Static Random Access Memory (6T SRAM) cells.
A Study of Pad Contamination Defect and Removal
Authors: Mohammad K.A. , Liu L.J. , Liew S.F. , Chong S.F. , Lee D.G. , Lee S.F. , Lee B.C. 
Published: January 2021

Abstract
The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.
Transient Latch-Up Analysis of Power Control Device with Combined Light Emission and Backside Transient Interferometric Mapping Methods
Authors: Heer M. , Pogany D. , Street M. , Smith I. , Riedlberger F. , Bonfert D. , Gieser H. A. 
Published: January 2021

Abstract
A case study of a transient induced latch-up (TLU) problem is presented, which was identified during the development of a 60 V, 0.8 µm BiCMOS power control device. The mechanism was characterized by controlled transient latch-up testing and found to be fairly unusual, being triggered by a fast decreasing not necessarily negative spike or glitch on the positive supply pin. Emission Microscopy (EMMI) and Transient Interferometric Mapping (TIM) successfully located the parasitic silicon controlled rectifiers (SCR) structure. TIM is an infra-red laser beam based technique for back side analysis. TIM analysis enables concurrent imaging of carrier injection and heating in nanosecond timescale providing more detailed information on the SCR action than more often used static photon emission or dynamic TLP / PICA imaging.
Dopant Analysis on Advanced CMOS Technologies
Authors: Siegelin Frank , Dübotzky Anja , Danzfuss Bodo , Schömann Stephan 
Published: January 2021

Abstract
This paper gives an overview of methods for imaging the distributions of dopant in semiconductor devices. Top view imaging by means of NanoSIMS and chemical etching will be discussed as well as cross section imaging on etched transmission electron microscopy (TEM) lamellas and Scanning Spreading Resistance Microscopy (SSRM).
3-D Image Reconstruction in the Scanning Electron Microscope
Authors: Vanderlinde William E. 
Published: January 2021

Abstract
This paper demonstrates that an SEM stereo-pair can be accurately translated into a Digital Elevation Model (DEM) using commercial software running on a desktop computer. The DEM is easy to view without any special equipment and can provide accurate measurements of the sample in all three dimensions. Vertical height measurements with high accuracy can be obtained from the elevation model when the sample has sufficient surface texture and a uniform baseline.
الأبعاد المقاصدية في منهجية مكافحة الجريمة في النظام الإسلامي
Authors: الغرابلي رزق , هنداوي حسن 
Published: January 2021

يسلط هذا البحث الضوء على الأبعاد المقاصدية في منهجية مكافحة الجريمة في النظام الإسلامي، فالإسلام تفرّد بمنهج ربّاني في الوقاية من الجريمة وعلاجها على أسسٍ أخلاقية، فاستبقت الشريعة إمكانية وقوع الجريمة بجملة من التشريعات الأخلاقية الكفيلة بمنع وقوعها، كما عالجت آثارها بأسس أخلاقية أخرى كفيلة بإصلاح الجاني وجبر نفس المجني عليه، وغيرها، بما يتوافق مع مقاصد الشارع الحكيم في تحقيق مصالح العباد في العاجل والآجل.
ويردّ هذا البحث على من يتهم الإسلام بالقوة والعنف والقسوة في التعامل مع المجرمين إجمالا، ويبرز منهجًا يعد الأرقى على مستوى المناهج التي تعاملت مع أنواع الإجرام كافة، يتحقق معه مقصود الشارع في جلب مصالح العباد ودرء المفاسد عنهم. ومن أجل تحقيق أهدف البحث اتبعت المنهج الاستقرائي لطائفة من الشواهد المتعلقة بالموضوع سيما من القرآن والسنة، ثم المنهج الاستنباطي لاستخراج القيم الأخلاقية والأبعاد المقاصدية المتضمنة في المنهج الإسلامي في مكافحة الجريمة، مستعينًا بالمنهج التحليلي في المواضع التي احتاجت إلى ذلك.
Curriculum Integration based on the Story of Prophet Musa and the Righteous Man in Chapter al-Kahf (Integrasi Kurikulum Berdasarkan kisah Nabi Musa A.S dan Seorang Pemuda Soleh (al-Khidr) di dalam Chapter Al-Kahf)
Authors: Abdulmaelk Yahya Al-Hidabi Dawood 
Published: January 2021

Curriculum integration at all levels of education is common practice and well-researched area. However, there is no consensus among scholars and educationists about the definition of curriculum integration. Different factors influence the definitions and models of curriculum integration. Philosophical, Ideological, cultural and historical perspectives lead to different definitions, types and models. The integration of curriculum, particularly in the west, passed through different phases since the early 1900s and produced different emphasis, types, processes and models. This paper attempts to present a new definition and model based on one case in the Qur’an. This case reflects the story of Prophet Musa and the righteous man (al-Kẖidr) in chapter al-Kahf. The new model has some similarities with specific elements in the western literature but has its unique characteristics which reflect the uniqueness of the revealed knowledge in this story. Different models of curriculum integration could be adopted for different topics/issues/problems and contexts. Further, research is needed in this area, particularly in Muslim societies and contexts.
Keywords: Integrated curriculum, Islamic perspective, the story of Prophet Musa and the righteous man (al-Khidr).
Abstrak
Integrasi kurikulum adalah perkara yang sering dikaji dan diamalkan didalam setiap tahap pendidikan. Namun begitu, tidak ada kata sepakat dikalangan para ilmuwan dan pendidik dalam menetapkan definasi integrasi kurikulum. Terdapat beberapa faktor yang mempengaruhi definasi dan model integrasi kurikulum. Dari sudut falsafah, ideologi, budaya, dan sejarah, ia membawa kepada maksud, jenis dan model yang berbeza. Integrasi kurikulum khususnya di barat telah melalui pelbagai fasa sejak awal tahun 1900 dan telah malahirkan kepelbagaian dari sudut penekanan, jenis, proses, dan model. Artikel ini bertujuan untuk mengemukakan definasi dan model baru berdasarkan satu kisah di dalam al-Quran. Kisah ini menggambarkan tentang kisah Nabi Musa A.S dan seorang pemuda soleh (al-Khidr) di dalam Chapter al-Kahf. Model baru tersebut mempunyai beberapa persamaan dengan unsur-unsur di dalam sastera barat akan tetapi ianya juga mempunyai ciri-ciri unik yang mencerminkan keunikan di dalam kisah yang telah diwahyukan. Model integrasi kurikulum yang berbeza dapat diadaptasikan untuk pelbagai topik, masalah, isu, dan konteks. Penyelidikan yang lebih terperinci diperlukan di dalam bidang ini, terutamanya dalam konteks masyarakat Islam.
Kata Kunci: Integrasi kurikulum, perspektif Islam, kisah Nabi Musa A.S. dan seorang pemuda soleh (al-Khidr).