(Invited) Some Recent Progress in Ferroelectric Memory Technology
Authors: Jiang Hao , Ma T.P. 
Published: May 2020

Ferroelectric memory, based on the persistent remnant polarization of certain ferroelectric materials that are switchable by an appropriate applied field, has rekindled tremendous interest ever since the discovery of HfO2-base ferroelectrics [1], and both the one-transistor-one-capacitor (1T1C) based ferroelectric random-access memory (FeRAM) and the single-transistor (1T) based ferroelectric-gated field-effect-transistor (FeFET) variety have made significant progress. In this paper, we will review some of the important progress that we have made in both areas, while standing on the shoulders of other previous contributors, starting with the FeRAM technology below.
The cell structure of FeRAM is similar to that of a DRAM structure, except that the storage capacitor is replaced by a ferroelectric one, leading to the possibility of nonvolatility without the need for a power-hungry refresh operation of the DRAM. Because of challenges concerning CMOS compatibility, physical thickness scalability, and inability to build 3D ferroelectric capacitors, the traditional perovskite-based ferroelectric materials (such as PZT and SBT) have prevented the FeRAM cell size from further scaling down beyond the 130-nm technology node, which has confined the current FeRAM products to very limited niche markets [1]. The introduction of hafnium oxide (HfO2)-based ferroelectrics has turned out to be a game changer, as high-quality and scalable ferroelectric capacitors have since been reported, including TiN/Al:HfO2/TiN-based 3D deep-trench capacitors [1]. Among various doped and even undoped HfO2 ferroelectric thin films, the HfxZr1-xO2 system has attracted extra attention because of its wide composition range and relatively low processing temperature (<= 400 0C), making it potentially compatible with Back-End-of-Line (BEOL) process [1]. Here we will present the results of our study on a leading foundry’s BEOL-processed Hf0.5Zr0.5O2-based ferroelectric capacitors over a wide range of areas (10-2 to 103 µm2) on 12-in wafers. Some critical issues, including wake-up behavior, endurance, retention, size dependence, temperature dependence, and uniformity across the wafers have all been systematically characterized and will be discussed, as well as their potential for automotive applications at elevated temperatures.
More coverage of this talk will be focused on FeFET cells made by the same foundry using their conventional front-end CMOS process except for the ferroelectric gate stack of the MOS transistor. It should be noted that the FeFET cell structure was proposed decades ago but failed to commercialize primarily because of the retention problem associated with the traditional perovskite-based ferroelectric materials [2,3]. The relatively short retention time of those perovskite-based ferroelectric FeFETs , although cannot meet the requirements of nonvolatile memory technology, is more than adequate for DRAM applications. And a 1-T ferroelectric DRAM technology based on FeFETs, named FEDRAM, was proposed [4,5]. One major attraction of the HfO2-based FeFET is its significantly longer retention. In this talk, we will discuss the underlying mechanisms contributing to the retention loss, including the presence of the depolarization field and gate leakage followed by trapping [2]. Moreover, we will present the reason why the FeFET cell based on the ferroelectric HfO2 can achieve better retention time compared with those based on PZT and SBT [6]. While the HfO2-based FeFETs have demonstrated impressive memory retention, they are suffering from limited endurance. We will discuss the causes of such reliability concerns [7]. It will be shown that the endurance failure is mainly attributed to the charge trapping and trap generation in the gate stack, rather than fatigue of polarization in the HfO2 ferroelectric layer. The understanding of the mechanisms behind the retention loss and the endurance issues will help us to formulate possible strategies for further advancing the pathway toward commercialization of the FeFET memory technology.
The nearly identical memory cell structure as well as the similar program/erase algorithm between FeFET and NAND-Flash memory naturally leads to the concept of 3D ferroelectric memory stacks based on FeFET cells, as proposed by the Yale group [8]. This patented 3D memory technology will also be briefly discussed.
This work was supported by the National Science Foundation (NSF) under Award No: 1609162.
References
[1] T. Mikolajick et al., MRS Bulletin 43 340 (2018).
[2] T.P .Ma and J.P. Han, IEEE Electron Dev. Lett. 23 (7) 386 (2002).
[3] X. Pan and T.P. Ma, Appl. Phys. Lett. 99 01305 (2011).
[4] J.P. Han and T.P. Ma, Integr. Ferroelect. 27 1053 (1999).
[5] K.-H. Kim et al., IEEE Electron Dev. Lett. 23 82 (2002).
[6] N. Gong and T.P. Ma, IEEE Electron Dev. Lett. 37 (9) 1123 (2016).
[7] N. Gong and T.P. Ma, IEEE Electron Dev. Lett. 39 (1) 15 (2017).
[8] X. Sun and T.P. Ma, U.S. Patent No. 9,818,848, (2017)