Notched Gate and Graded Gate Oxide Processing for Reduced Capacitance Application in RF MOSFETs
Authors: Antunes Lucas , Masson Pascal , Amouroux Julien , Dura Julien , Babic Julien , Richard Benoist , Vedovini Laetitia , Julien Franck , Regnier Arnaud , Fleury Alain , Monfray Stephane 
Published: December 2024

As the demands of RF applications are rising, optimization of internal MOSFETs capacitances is a key issue to improve the cut-off frequency. In this abstract we report the development of a novel N-MOS architecture processed on 8-inch SOI wafers. This architecture has a gate oxide with variable thickness along the channel and a reduced bottom gate length aiming at minimizing Gate to Drain/Source capacitance (1) (2). This improvement on Gate to Drain/Source capacitance mainly comes from a decrease in overlap capacitances as described in (3).
The new process flow is composed as usual until Poly-Si gate etching. By controlling the species flow and process time during plasma etching steps, over etch at the bottom of the gate is performed (fig.1(a,b)). Poly-Si gate notching engineering is possible due to reduction of the passivation layer thickness at the bottom of the gate during plasma etch. As described in (4) the gate is first etched using a HBr/CL2/O2 chemistry until reaching close to the bottom of the gate, allowing the formation of a passivation layer made of SiOxCly and the anisotropy of the etch. To etch the remaining thickness HBr flow is augmented while CL2 and O2 flow are reduced, preventing formation of passivation layer. This leads to isotropic etch of the bottom gate and reduction of the gate length as regard to the top Poly-Si dimension. This over-etch reduces the physical gate length without changing the effective and the on-mask gate lengths, leading to overlap capacitance reduction.
To produce gate oxide with variable thickness under gate sidewalls a two-steps process is performed. First, full plate oxide is grown before poly-Si deposition to act as middle gate thickness. Then undercut is performed, consisting of lateral etching of the gate oxide under gate sidewall after gate etch (fig.2.a). To achieve this undercut, hydrofluoric acid (HF) wet etch has been chosen. First trials with very low HF concentration become quickly saturated leading to small lengths under gate sidewalls (fig.2.b). Then more acidic solutions were used allowing satisfying undercut lengths (fig.2.c).
Finally rapid thermal oxidation (RTO) is performed to obtain an oxide bird beak at both gate side as both Poly-Si gate and Si from the active region react with ambient O2 in the chamber. This leads to a gate oxide with variable thickness along the channel (fig.3(a.b)) which has both effects: to get smoother poly-Si foot and a down step in the active between channel and Source/Drain regions. During this process step, a built-in spacer on the gate sides for LDD implantation is formed. RTO process step has grown a thicker oxide over Source/Drain areas which has to be reduced to allow an accurate LDD implantation, this is done by anisotropic etching. After these new steps, the process goes back to a standard N-MOS process flow.
Some early versions of the notched gate have been investigated (5), and these experiments and details on processing recipe seem promising for electrical results. As poly-Si foot has been smoothed and graded gate oxide (GGO) on top of overlaps region is formed. It would allow a reduction in parasitic capacitances improving cut-off frequency of RF applications.
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Figure 1