bluuebunny/crossref_metadata_2025_split huggingface dataset:
Electroplated Cu Grids on Crystalline Silicon Solar Cells and Its Long Term Degradation
Authors: Huang Qiang 
Published: February 2020

Replacing screen printed Ag with electroplated Cu for silicon solar cell metallization is of great interest because of the high conductivity, low cost, and easy integration with laser patterning of the latter approach. The contact resistance and adhesion between Cu grid and Si emitter as well as the concern of Cu diffusion into the Si has motivated the invention of Silicide-Ni-Cu metallization.[1,2] In addition, the method of light induced plating or light assisted plating was invented decades ago and enabled the electroplating on the photoelectric device.[3-5] While this approach has been proposed for more than a decade, the details of the electroplating process for this new metallization scheme is not well understood. Furthermore, the impacts of this new metallization scheme on the long term stability of solar cells has not been studied until very recently.[6,7]
This paper will present the light assisted plating of Ni and the silicide formation on single crystalline silicon solar cells as well as the thermal degradation of the Cu metalized cells. Solar cells in real operation in the field will be challenged not only by heat, but also by moisture, radiation, and other natural stresses. While the reliability tests for Si solar cells with screen-printed Ag grid have been standardized already, the impacts of these stress elements are unknown to the Cu grids and are typically convoluted.
In this study, solar cells with Cu metallization were annealed at different elevated temperatures to speed up the degradation. Degradation behaviors of the grids after up to 3 years were studied. Different materials were also evaluated and compared for improvement in the grid reliability. For example, figure 1 shows a comparison between the solar cells with the pure Ni layer and NiCo layer. The presence of Co apparently improved the stability of the final grids during the stress tests at elevated temperature. Further detailed discussion will be provided in the talk.

REFERENCES

D. A. Yates, US Patent 4,609,565 (1986).

K. Holdermann, US patent 5,543,333 (1996).

L. F. Durkee, Patent No. 4144139 (1979).

L. A. Grenon, US patent 4,251,327 (1981).

G. Hamm and D. L. Jacques, Patent No. 7955977 (2011).

J Bartsch, A Mondon, K Bayer, C Schetter, M Horteis, and S W Glunz, J. Electrochem. Soc., 157, H942 (2010).

J Bartsch, A Mondon, C Schetter, M Horteis, S W Glunz, IEEE 35th PVSC, Honolulu HI (2010).

Figure 1
Study of Nano-Filtration and Solvent Effects for Improving Efficacy of Organic Photovoltaic
Authors: Abdel-Fattah Tarek M , Younes Enas m , Namkoong Gon , El-Maghraby E M , Elsayed Adly , Abo Elazm A. H. 
Published: February 2020

Conductive polymer such as poly (3,4-ethylenedioxythiophene) and polystyrene sulfonate acid (PEDOT:PSS) plays an important role for improving performance of organic photovoltaics (OPVs).
In this study, we investigated the effect of filtrating the buffer layer between the indium tin oxide (ITO) and bulk heterojunction (BHJ); poly(3-hexylthiophene) and [6,6]-phenylC71 butyric acid methyl ester (P3HT:PC71BM) used in our organic photovoltaics (OPVs) as shown in Figure 1.
This buffer layer consists of poly (3,4-ethylenedioxythiophene) and polystyrene sulfonate acid (PEDOT:PSS) doping with different solvents [isopropyl alcohol (IPA), ethanol, and methanol]. For comparison, we also studied the OPV devices without filtering the buffer layers.
The OPV devices fabricated with filtered buffer layer show better performance than OPV devices without buffer layer filtration. The OPV devices with buffer layers; PEDOT:PSS/IPA, PEDOT:PSS/Ethanol, and PEDOT:PSS/Methanol after filtration showed 24 %, 16 %, and 11 % improvement in short circuit current density (Jsc) , respectively compared to the same OPV devices without filtration. The maximum exciton generation rates (Gmax), and the exciton dissociation probabilities [P (E, T)] were calculated for all fabricated OPV devices to explain the performance enhancement.
The data showed that the performance enhancement of OPVs devices after filtering the buffer layers originate from the large increase of Jsc. Filtering the buffer layers enhanced light absorption of BHJs, increased the surface roughness, and decreased the sheet resistance of buffer layer after filtration.

Figure 1. A schematic diagram of ITO/PEDOT:PSS:different organic solvents/P3HT: PC71BM/Al

Figure 1
Solution-Derived NiO Hole Transport Layers on the PTB7:PC71BM Organic Solar Cells
Authors: Kiriishi Koudai , Hashiba Kousei , Qiu Jiayu , Fujii Shunjiro , Kataura Hiromichi , Nishioka Yasushiro 
Published: February 2020

Energy demands are increasing all over the world, and renewable energy resources are needed. Photovoltaics is one of the attractive choice. Recently, organic solar cells have attracted great attention because of light weight and potentially low cost from printing at low temperature on flexible substrates. Traditional bulk heterojunction polymer solar cells consist of a transparent indium tin oxide (ITO) anode, a hole transport layer (HTL), a photoactive layer, and a top cathode. HTLs must have high optical transparency, good chemical stability, a large ionization potential, and good electron blocking capability. In a typical polymer solar cell, poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) has been used as an HTL, and has a work function (Φ) of 5.2 eV. However, The PEDOT:PSS HTLs caused inferior device performance and degrade long term reliability due to their acidity, tendency to absorb water, and inability to block electrons effectively. Accordingly, the oxides which do not have these problems have been considered to be used as potential HTLs. Nickel oxide (NiO) has recently attracted a lot of attention because it can replace a PEDOT :PSS of HTL in solar cells. On the other hand, bulk hetero-junction (BHJ) solar cells based on [4,8- biz[Poly[[4,8-bis[(2-ethylhexyl)oxy]benzo [1,2-b:4,5-b']dithiophene-2,6-diyl][3-fluoro-2-[(2- ethylhexyl)carbonyl]thieno[3,4-b]-thiophenediyl] (PTB7) and phenyl-C71-butyric-acid-methyl-ester (PC71BM) on ITO-coated glass substrates have recently been reported to have the efficiency as high as 9.2%. However, solar cells with a NiO HTL based on PTB7 / PC71BM have not been well investigated.
In this paper, we report on the performance of solar cells with a structure of glass/ITO/NiO/PTB7:PC71BM/LiF/Al, and also report the effects of the NiO thickness on the performance of the solar cells. To synthesize the precursor solution, we dissolved nickel acetate tetrahydrate (Ni(OAc)2·H2O) and mono ethanolamine (MEA) in 2-Methoxethanol. The NiO films were synthesized by spin-coating the NiO precursor followed by annealing on a hot plate in air at 350 °C.　The NiO thickness were optimized to realize better performance by changing concentration of nickel acetate tetrahydrate in 2-metxy ethanol solution used for spin coating deposition. The concentraton of Ni(OAc)2·H2O was prepared from 0.1 M to 0.4 M. Resulting in, the organic solar cell with NiO HTL using 0.2 M precursor shows highest performance, the device with NiO HTL using 0.4 M precursor shows worst performance. Furthermore, The solar cells with the NiO HTL layers showed improved long term reliability compared to the devices with PEDOT：PSS. As a result, the maximum power conversion efficiency of 5.14% was realized at 0.2 M of the nickel acetate tetrahydrate concentration. The PCE degradation of the solar cells with the HTL was compared to that of the control solar cells with PEDOT:PSS as an HTL.
Inverted Organic Solar Cells Based on PTB7:PC71BM with PFN Electron Transport Layer on ITO-Free Flexible PEN Substrate
Authors: Hashiba Kousei , Nagata Ryo , Kiriishi Koudai , Kataura Hiromichi , Fujii Shunjiro , Nishioka Yasushiro 
Published: February 2020

Polyfluorene: poly(9,9,-bis(3'-(N,N-dimethyl)-propyl-2,7-fluorene)alt- 2,7-(9,9-dioctylfluorene)) (PFN) has been recently reported as a good electron transport layer for organic bulk-heterojunction (BHJ) solar cells by Chang et al. [1]. They fabricated BHJ solar cells based on [4,8-biz[Poly[[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b']dithiophene-2,6-diyl][3-fluoro-2-[(2-ethylhexyl)carbonyl]thieno[3,4-b]-thiophenediyl]] (PTB7) and phenyl-C71-butyric-acid-methyl-ester (PC71BM) on indium tin oxide (ITO) glass substrates with PFN as an electron transport layer, and it showed the efficiency as high as 9.2%.
In this paper, we report on the improved long term reliability of similar solar cells with an ITO-free flexibleinverted solar cell structures of PEN/PEDOT:PSS/PFN/(PTB7:PC71BM)/MoO3/Au using, and found these devices showed much improved long-term reliability of the devices stored in air without any surface passivation layer. The J-C characteristics showed a slight reduction in the short cuircuit current density after storage in air for 4 days. The use of the PFN layer also significantly enhanced not only the open-circuit voltages and the power conversion efficiencies of the solar cells presumably due to the high electron transport efficiency and the better contact between the PEDOT:PSS cathode and the PTB7:PC71BM active layer. Although the resulted conversion efficiency was only 1.8% at this moment, and further process improvement will be continued.Furthmore we tried efficiency of the device change in the PFN thickness by spin-coating time.
[1] Yi-Ming Chang, and Chi-Yi Leu. Journal of Materials Chemistry A 1.21 (2013): 6446-6451.
(Invited) Topological States in Multi-Orbital Honeycomb Lattices of HgTe (CdTe) Quantum Dots
Authors: Beugeling Wouter , Kalesaki Efterpi , Delerue Christophe , Niquet Yann-Michel , Vanmaekelbergh Daniel , Morais Smith Cristiane 
Published: February 2020

Recent advancements in colloidal chemistry demonstrate that two-dimensional single-crystalline sheets of semiconductors forming a honeycomb lattice can be synthesized by oriented attachment of semiconductor nanocrystals [1,2]. Inspired by these results, we have performed atomistic tight-binding calculations of the band structure of CdSe [3,4] and HgTe [5] sheets with honeycomb nano-geometry. We have also considered honeycomb super-lattices of quantum dots that could be made using nano-lithography of HgTe layers.
In the case of CdSe sheets [3], we predicted that their conduction band exhibits Dirac cones at two distinct energies and nontrivial flat bands. The lowest Dirac conduction band has s-orbital character and is equivalent to the π bands of graphene but with renormalized couplings. The conduction bands higher in energy have no counterpart in graphene; they combine a Dirac cone and flat bands because of their p-orbital character.
We also present very recent results on HgTe [5]. We show theoretically that honeycomb lattices of HgTe can combine the effects of the honeycomb geometry and strong spin-orbit coupling. The conduction bands, experimentally accessible via doping, can be described by a tight-binding lattice model as in graphene, but including multi-orbital degrees of freedom and spin-orbit coupling. This results in very large topological gaps (up to 35 meV) and a flattened band detached from the others. Owing to this flat band and the sizable Coulomb interaction, honeycomb structures of HgTe quantum dots constitute a promising platform for the observation of a fractional Chern insulator or a fractional quantum spin Hall phase.
[1] W. H. Evers, B. Goris, S. Bals, M. Casavola, J. de Graaf, R. van Roij, M. Dijkstra, and D. Vanmaekelbergh, Nano Lett. 13, 2317 (2013).

[2] M. P. Boneschanscher, W. H. Evers, J. J. Geuchies, T. Altantzis, B. Goris, F. T. Rabouw, S. A. P. van Rossum, H. S. J. van der Zant, L. D. A. Siebbeles, G. Van Tendeloo, I. Swart, J. Hilhorst, A. V. Petukhov, S. Bals, and D. Vanmaekelbergh, Science 344, 1377-1380 (2014).

[3] E. Kalesaki, C. Delerue, C. Morais Smith, W. Beugeling, G. Allan, D. Vanmaekelbergh, Phys. Rev. X 4, 011010 (2014).

[4] C. Delerue, Phys. Chem. Chem. Phys., 2014, doi: 10.1039/C4CP01878H.

[5] Beugeling, W. et al, Nat. Commun. 6:6316 doi: 10.1038/ncomms7316 (2015).
Effect of Hydrogen Partial Pressure on in-Situ Steam Generation Oxide Layer
Authors: Yun Jin Hyuk , Park Se Geun , Lee Young Ho , Lee Che Young , An Jung Su , Cho In Su 
Published: February 2020

As device sizes are scaled down, it is very difficult to obtain the stable quality of gate oxide due to the lattice deformation and irregular oxide thickness in furnace type annealing system. In that reason, to eliminate the excessive heat budget and to improve oxide layer quality, In-Situ Steam Generation (ISSG) has been widely used in rapid thermal process (RTP) system. When the thermal heat is too low to break bond energy of oxygen molecular for O*(radical oxygen) , it is very difficult to grow the oxide layer in homogenous thickness and quality. So, to compensate this lack of O* for ISSG process, special reactant such as hydrogen gas is added. "H2 + O2 = H2O + O* + O2- + other species" is common chemical equation for ISSG process with H2 gas which helps to generate more radical oxygen.
In this study, we improved the gate oxide reliability In ISSG process depending on the influence of H2 partial pressure and process temperature. An increased H2 partial pressure under the same temperature, it is found that an oxide growth rate has increased. In Si-O bonds strain analysis in the Si/SiO2 interface layer, due to the repairs of structural defects (three major structural defects , such as Si dangling bonds, weak Si-Si, and strained Si-O bonds), compressive strain has been decreased and also gate induced drain leakage (GIDL) was improved. Based on the index of strain induced residual overlay values on the wafer surface, we confirmed that it became less sensitive than before. That implies less possibility of misalignment in lithography which brings about device failures.
The Effect of CoSi2 Formation Process on the CMOS Transistor Electrical Properties for Sub 100nm Memory Applications
Authors: Park Jeong Hoon , Kim Sang Jin , Lee Jung Ho , Yoo Chang Jun , Kang Hyo Jin , Lee Byung Cheol , Jeong Jae Goan 
Published: February 2020

We investigated the effect of various processing conditions on the abnormal CoSi2 formation, such as well-known Co spike and crystal phase agglomeration. We also focused on the effect of CoSi2 related defects on the electrical properties in real sub 100nm ULSI devices. The mechanism of electrical failure was proposed and employed to clarify the relation between the various process conditions and electrical properties of our ULSI chips.
We used the Co metal sputtering and next thermal treatment like RTP(rapid thermal process). The effect of ion implantation condition (dopant species and concentration) and different Co deposition methods (capping material and in-situ thermal treatment) has been studied. To evaluate the electrical failure of transistors, we tried to check the full chip level drain leakage current, which is represented by “DLC_chip”, and unit transistor level drain leakage current, which is called by “DLC_unit”, at the same time.
It was found that with varying dopant species and concentration, the source-drain junction depth, dopant spatial distribution and local electric field could change, which brought about the DLC(drain leakage current) phenomenon. And, since it is believed to affect the electrical property of every single transistor, DLC_chip and DLC_unit degrade or improve simultaneously.
The different deposition methods of Co material led to the changes in the characteristics of CoSix formation. When we used the Ti/TiN capping layer and hot temperature PVD, the abnormal growth was suppressed and the interface became smooth, which could prevent the agglomeration and Co spike. For electrical properties, the DLC_chip of both cases showed the significant improvement, however, the DLC_unit showed a negligible change or even degrade a little bit contrary to DLC_chip. We concluded that, in spite of the degradation of DLC(drain leakage current) in typical transistor, the overall level of DLC_chip has improved due to the significantly decreased amount of defective sites like abnormal growth. It was also proposed that the small amount of defective site was eligible to govern the chip level DLC and responsible for electrical failure of a single chip.

Figure 1
Influence of Hydrogen Post-Implantation on Threading Dislocation Density in Strain-Relaxed Sige Layer
Authors: Park Jun-Seong , Kim Il-Hwan , Lee Gon-Sub , Shim Tae-Hun , Park Jea-Gun 
Published: February 2020

According to International Technology Roadmap for Semiconductor (ITRS), the development of MOSFETs based on SiGe or Ge is necessary for the next generation technology beyond 10-nm C-MOSFETs, because electron and hole mobility of Ge substrate is three and four times higher than those of a conventional Si MOSFETs, respectively. However, due to the lattice mismatch of 4.2 % between Si and Ge, many threading dislocations are generated, resulted in increasing the leakage current of the C-MOSFETs. The threading dislocation density of graded SiGe layer utilized currently is higher than 105 cm-2, which is too high to be applied in mass production because of degrading productivity and performance of the C-MOSFETs. To overcome this drawback in realizing sub 10-nm C-MOSFETs, a novel process technology should be developed to reduce the threading dislocation density.
In this study, we designed a novel technology to reduce the threading dislocations in strain-relaxed Si1-xGex grown on Si substrate. We applied the H+ post-implantation which forms defect band at the dislocation clusters above the interface between the Si1-xGex layer and the Si substrate, acting as a dislocation sink. We investigated how the hydrogen-ion implantation followed by annealing affected the surface characteristics, such as dislocation pit and cross-hatch pattern density related the threading dislocation. In particular, the cross-hatch pattern density of the Si0.8Ge0.2 layer on the Si substrate was about 4x104 cm-1, as shown in Fig. 1(a). On the other hand, when hydrogen ions were implanted into the relaxed Si0.8Ge0.2 layer with an dose of 5x1015 cm-2, the cross-hatch pattern density was reduced to about 1.18x104 cm-1, as shown in Fig. 1(b). Also, there was a high threading dislocation density in the case of 30-at% Ge concentration, as shown in Fig. 2(a). However, for the case of hydrogen ion implantation, a dose of 5x1015 cm-2, both threading and misfit dislocations near the interface between Si0.7Ge0.3and Si substrate were significantly reduced, as shown in Fig. 2(b).
Therefore, we present the mechanism of the strain relaxation resulted in the formation of the threading dislocation in Si1-xGex/Si (100) substrate. In addition, we explain how H+ implantation affects the cross-hatch pattern density related the threading dislocation. Furthermore, we report the process technology and optimized the implanted energy, dose, and the position of dislocation sink in Si1-xGex/Si structure via ion implantation.
* This work was financially supported by the Brain Korea 21 Plus Program in 2015 and SiWEDS (Silicon Wafer Engineering and Defect Science).

Reference

[1] J. G. Park et al., Mat. Sci. Eng. B
134142-153 (2006)
[2] S. Takagi, Strained-Si CMOS Technology in Advanced Gate Stacks for High-Mobility Semiconductors, Springer Berlin Heidelberg 1 (2007)

Figure 1
(Invited) Is the Silicene a 2D Dirac Material?
Authors: Shirasawa Tetsuroh 
Published: February 2020

Silicene, a 2D honeycomb layer of Si, has attracted much attention, since a Dirac fermion character like graphene was predicted. Furthermore the silicene has a 2D topological insulator due to the 1000 times stronger spin-orbit coupling than graphene. The hypothetical silicene is a free standing layer, but in practice, experimentally fabricated silicenes so far are 2D layers of silicon epitaxially grown on substrates. We will discuss, on the basis of the structure determination on an atomic scale by using quantitative LEED analysis, the nature of the epitaxial silicenes on Ag(111) surface; the influence of the silicene-substrate interaction for the single layer silicene and if the multi-layer silicene fabricated on the substrate has the features expected for the free-standing silicene.
Plasma Dicing: Current State & Future Trends
Authors: Westerman Russ , Grivna Gordon , Mackenzie Ken , Lazerand Thierry , Doub Jason 
Published: February 2020

Die singulation by mechanical sawing has been the primary technology used in semiconductor device fabrication for decades. However as device structures continue to evolve to meet increasing performance requirements, the fundamental limitations of the sawing operation have been exposed. Obtaining reasonable dicing throughput and yield for die less than 100µm thick is a challenge for the sawing operation. An alternative to a saw-based dicing approach is die singulation using plasma etching. This paper compares and contrasts plasma dicing before grind (DBG) and plasma dicing on tape (PDOT) processes to conventional mechanical saw processes, laser processes, and one another. While saw and laser processes are serial in nature, plasma dicing is a parallel process that can offer higher equivalent cutting speeds and is supportive of the current trend to thinner wafers down to 50µm and beyond. In addition to a wafer per hour throughput advantage, plasma dicing allows more die per wafer due to narrower lithographically defined streets; 90µm saw street widths compared to 5-20µm wide plasma dicing streets. Along with higher die throughput, die singulated using plasma dicing have die strengths 9 times stronger than mechanically sawed die. In closing, the paper discusses issues and solutions related to PDOT process integration including maintaining tape integrity, street definition / masking approaches, and packaging compatibility.