bluuebunny/crossref_metadata_2025_split huggingface dataset:
La beauté de l’épouse selon Ben Sira
Authors: Lavoie Jean-Jacques 
Published: February 2025

Dans le livre de Ben Sira, trois textes portent sur la beauté de l’épouse (7, 19 ; 26, 13-18 et 36, 27[22 Hébreu]). Dans cet article, l’auteur cherche à répondre aux questions suivantes : quels sont les idéaux de Ben Sira au sujet de la beauté de l’épouse ? Ses idéaux sont-ils aliénants pour les femmes ou favorisent-ils leur autonomisation et leur émancipation ? De quelle manière les discours de Ben Sira sur la beauté des épouses sont-ils susceptibles d’affecter les rapports de pouvoir entre les sexes ? Les idéaux de Ben Sira au sujet de la beauté, tels qu’ils sont promus dans le texte hébraïque, correspondent-ils en tout point aux idéaux de son petit-fils, qui a traduit en grec le livre de son grand-père ? En somme, quels sont les enseignements du livre de Ben Sira au sujet de la beauté des épouses ?
Effect of Bonding Pressure on Thermal Performance of Graphene-enhanced Thermal Interface Materials for Immersion Cooling Applications
Authors: Harr Kristoffer , Wang Yuanyuan , Yasin Kurban , Chen Jiabin , Chen Jin , Möller Johan , Liu Johan 
Published: February 2025

Graphene, due to its exceptional mechanical, optical, electrical, physical and thermal properties, has attracted strong interest for both fundamental studies and real applications. Among all these properties, the extraordinary high thermal conductivity makes graphene an ideal cooling material for power devices and systems. In mean time, rapid growth of information and AI technology continues to push power density and integration level in electronics devices, leading to an increase in greater heat dissipation causing lower performance, and shorter operating life. In this paper, the technology of a new graphene-enhanced thermal interface material (GT-TIM) manufacturing process is described. The effect of bonding pressures on thermal performance of the GT-TIM with different thicknesses is presented. The immersion test up to 1-month in immersion condition was carried out. The results show that the GT-TIM can be exposed to very high bonding pressure without delamination, well beyond normally used bonding pressure regions and extremely low thermal resistance in the range of 4-5 Kmm2/W at 40 psi (276kPa) at a thickness of 0,2 mm. In a typical biocompatible coolant environment, the thermal performance is basically intact after one month´s exposure. It is thus concluded that that this class of the novel GT-TIM has very interesting feature that can potentially be used for many large power cooling applications, especially for immersion cooling.
Molded SiP Manufacturing with Integrated Shielding Layer for Optimized EMI Robustness
Authors: Becker Karl-Friedrich , Voges S. , Becker L. , Safak G. , Nallaweg O. , Müller F. , Tschoban Christian , Dreissigacker Marc , Younis M. A. , Maretzki R. , Wallrodt M. , Braun Tanja , Schneider-Ramelow Martin 
Published: February 2025

The functional reliability of microelectronics packages in harsh environment use not only depends on interconnect integrity and thermomechanical robustness, also signal integrity can play an important role for package performance. For industrial/automotive use, the shielding of packages against electromagnetic interference is a key process tep that defines package performance in challenging environments. Within the project AdaPEdge, Fraunhofer IZM, TUB and MST are cooperating to manufacture highly integrated packages using Flip Chip technology and MAP molding technologies for package realization. To ensure optimized shielding of the packages, a test vehicle has been designed that allows the determination of shielding efficiency of molded packages without and with shielding layers created in different technological approaches. These technologies can be applied to single packages and to full MAP areas and include direct metallization on molding compounds, contactless dosing of a conductive layer and laser direct structuring. As a result, the paper presents the manufacturing of Shielding Efficiency test samples in various technologies, the SE measurements over a wide frequency range for samples with varied shielding layer thickness. The measurements are validated using an analytical model developed in-house and there is good agreement between the measurement and the analytical model. Based on the analytical model, physical effects at the interface of material and in the material are separated and analyzed. Comprised, packaging boundary conditions and design rules for define EMC-robust packages will be provided that allow an efficient manufacturing of functional SiP packages.
HPC Packaging Platform Including Compression Molding
Authors: Adler Marius , Becker Karl-Friedrich , Braun Tanja , Dreissigacker Marc , Hoelck Ole , Gaebler A. , Maass Uwe , Ndip Ivan , Zoschke K. , Schiffer Michael , Schneider-Ramelow Martin 
Published: February 2025

Efficient high-performance computing (HPC), especially for applications in the field of artificial intelligence, requires the use of specialized computing and memory chips, short transmission paths and high packing densities. A key technology for HPC is therefore the integration of processors and memory stacks in a single System-in-Package (SiP) using silicon-based interposers. Manufacturing concepts have been developed for such a package, each of which utilizes different process flows to build an HPC module. Following a holistic approach, the process flow is evaluated from the processing of the interposer with high density organic redistribution layers, compression molding and balling. Evaluation methods were defined for the individual process steps and criteria established to enable the selection of suitable process steps and combinations for an optimized package. The process flow options were realized and analyzed for a reference HPC module. An important parameter for all these process steps is warpage, since an exceeding warpage can make processing impossible. For compression molding, a key process step, the influence of different materials and process parameters on the warpage was therefore investigated. The results of the process development are presented for the backend process flow with an emphasis on compression molding process step, an evaluation of the process variants is carried out according to the previously developed criteria and the most suitable variant of the process step for later production is selected on this basis.
Study of the Effect of Gravity Weight on Strip Warpage
Authors: Fortin Elizabeth , Whitchurch Nathan , Lin Wei , Sohn EunSook 
Published: February 2025

Strip level warpage control is critical for the manufacturing and assembly of advanced packages. Unfortunately, it is very challenging to simulate strip level warpage accurately. One of the challenges is the strip gravity weight effect. In this paper, nonlinear simulations were performed using Ansys Workbench to observe the effect of gravity on strip warpage. The model consisted of the strip on top of a supporting surface, or table, to more closely resemble how the warpage was actually measured. To account for the gravity effect in simulations with various warpage shapes, contact conditions were included to capture the interactions between the strip and the supporting surface. Simulation results show the weight effect greatly reduced warpage on pre-mold strips, resulting in more accurate warpage simulation results when correlating to actual strip warpage measurement data. There was a significant difference in the weight effect at the chip-attach stage compared to the post-mold stage, with the post-mold stage showing less of a reduction in warpage. Other strip configurations and geometry effects were also studied in this paper, such as: strip size, number of blocks, a slot placed between blocks, and a cored vs. coreless substrate.
Prediction of an Industrial Framework for Semiconductor Fabrication and Experimental Validation OF 300 mm Wafer
Authors: Jeong Da-Woon , Cha Se-hyun , Kim Tae-Hyun , Gwak Wangyu , Choi Yangwook , An HyeongGeun , Lee Eun-Ho 
Published: February 2025

In contemporary memory semiconductor manufacturing, optimizing recipes has emerged as a crucial strategy to align with RE100 commitments, bolster ESG ratings, and substantially reduce operational costs. The current landscape demands the development of low-power manufacturing recipes that not only curtail energy consumption but also trim operational expenses, thereby augmenting overall profitability. This underscores the critical necessity for meticulous recipe optimization to ensure both sustainability and economic viability in the industry. In response to these challenges, there is an urgent need for a predictive framework capable of accurately forecasting optimal recipes. Such a framework is essential for facilitating the industry’s adaptation to dynamic technological environments and stringent environmental standards. By enabling proactive adjustments to manufacturing processes, this predictive approach ensures companies remain competitive while advancing comprehensive sustainability objectives. To address these needs, this work introduces a predictive framework specifically tailored to forecast recipe steps for plasma processes in semiconductor manufacturing. The framework’s efficacy was empirically validated using measurements from 300mm wafers in semiconductor mass production equipment. Plasma behavior was meticulously modeled, with simulations meticulously aligning with particle-in-cell models and Electron Monte Carlo collision simulations. These validations, conducted across both bulk plasma and sheath regions, confirmed the framework’s reliability and accuracy. Furthermore, the framework integrates a machine learning model to evaluate results under various recipe input conditions. This comprehensive approach not only enhances the understanding of plasma behavior but also facilitates the identification of optimal manufacturing conditions. Through meticulous recipe optimization, the framework minimizes undesirable effects such as backside chucking force and variations in thin film thickness, thereby improving overall manufacturing competitiveness and sustainability. Despite the inherent challenges and limitations, the predictive framework showcased significant potential to revolutionize manufacturing processes in the semiconductor industry. Its high predictive power positions it as a valuable tool for enhancing operational efficiency, driving informed decision-making, and ultimately advancing sustainability goals within the semiconductor manufacturing sector.
Development of High Density, Enhanced Reliability Wafer Level Packages
Authors: Sharma Gaurav , Su MengYao , Thukral Varun , Beddingfield Craig , Lakhera Nishant 
Published: February 2025

Fan in and fan out wafer level packages are primarily used in the industry for applications in handheld consumer electronic products. The key benefits of wafer level package (WLP) are small form factor, reduced cost, improved electrical and thermal performance. WLP investigated in this study are directly surface mounted on PCB and have no intermediate substrate. Direct mount of package on PCB, leads to significant CTE mismatch between the package and board which stresses the package solder joint, leading to different failure modes like; cyclic fatigue induced solder joint cracking, package interconnect failure, silicon BEOL failure. Due to these reliability constraints WLP, are limited to relatively smaller sizes and less pin counts. This study investigates development of high pin count, high reliability WLP by ensuring chip package integration at all levels of interconnect; board to package, package to die and die BEOL. Package development was done with DOE variables like, multi-layer package routing, dielectric materials, solder alloys. Tradeoffs between different DOE variables must be achieved for overall package reliability improvement. Excellent reliability, functional performance, and chip package integration was achieved for highly integrated fan in and fan out wafer level packages.
Panel-level Fan-out: Relationship Between Panel Size and Cost Reduction
Authors: Lujan Amy 
Published: February 2025

Panel-level fan-out packaging is a growing segment of the packaging industry. Some analysts expect that 7% of fan-out packages will be built with panel-level fan-out technology by 2025. The key reason for designers to consider a change from wafer-level to panel-level fan-out is cost reduction. Most activities for fan-out packaging are batch activities performed on the entire wafer or panel at one time. The more die processed during batch activities, the greater opportunity for cost reduction. Although this economic concept is simple, the reality of implementation is complicated. Handling wafer warpage and die shift can be a challenge even at the wafer level; these must be considered at the panel level as well. There are a few panel sizes available, and using the largest panel size for economic advantage may involve a trade-off with yield. New equipment or materials may be required, so capital expenditure should be considered as well. It is one thing to recognize the potential cost advantage of producing more chips at once, but designers and fabricators must understand whether to expect a 5% or 50% cost reduction. This paper will analyze the cost of multiple designs built using wafer-level fan-out with a 300mm wafer, and panel-level fan-out using a 515x510mm panel and a 600x600mm panel. Key assumptions, such as package size and yield, will be tested to evaluate their impact on cost reduction. The goal of this paper is to analyze the cost reduction that can be reasonably expected when moving from wafer-level to panel-level fan-out.
Novel Approach Solder Paste Printing on 90μm Pitch Application
Authors: Kumar B. Senthil , Min Lim Chze (Jason) , Huei Yam Lip , Fen Zhang Rui , Olakkankal Edrina Risson , HanWen Zhang Rui , Sungsig SS Kang 
Published: February 2025

Smaller components in system in a package (SiP) addresses the needs of miniaturization by using cutting edge technology in advanced packaging applications, which involves integration of passive components, flip-chips, integrated devices, etc. Increasing demands for a reduced footprint requires solder paste technology to constantly reinvent SAC305 solder paste. The Type-7 (<11μm) powders were processed by Welco™ technology and formulated into water soluble (WS) solder paste that provided consistent print volume and prints for stencil opening (≥55μm) and pitch (≥90μm). Even though solder pastes can achieve the 90um pitch capability, other factors significantly contribute to printing defects such as substrate quality, printing parameter, printing accessory and equipment process capability limitation. The present paper discusses critical challenges contributing to printing defects in the 90μm pitch stencil printing application and provides a detailed explanation and control guidelines.
Using FEM Simulation to Predict the Mechanical and Thermal Performance of FO-EB-T Package
Authors: Lin Shane Lin , Lin Vito , Shih Teny , Kang Andrew , Wang Y.P. 
Published: February 2025

In order to solve the problems that high price and low process yield of single multi-functional large-size chip, homogeneous and heterogeneous integration has become the trend of modern high-end packaging technology due to faster signal transmission speed and also a benefit for space management. According to that, the development of chiplet advanced packaging technology is particularly important. During the chiplet packaging process, many structural mechanical warping problems may be encountered. In addition to the difficulty of the process, the accompanying challenges also have more severe thermal problems. Take server for example, The Thermal Design Power (TDP) of the server is increasing year by year. It can basically reach more than 500W per package. Above that, before the overall packaging is completed, the reliability issue and thermal problem must also be taken into consideration. So the selection and matching of packaging materials need to be carefully selected, including organic interposer, heat sink, adhesive, etc. The Fan-Out Embedded Bridge with TSV (FO-EB-T) structure is taken to be the test vehicle in this paper. The assembly process of chiplet integration is firstly studied for wafer warpage in silicon bridge die with TSV connection process, pre-molding, u-pad, die bonding, underfill, molding process and C4 bump process. The glass carrier and organic compound candidates are predicted to make the wafer warpage within the criteria of each process and also show good alignment with experimental data. Simultaneously, the package warpage investigation is checked by the best combination of organic compound selection. Finally, the overall reliability and thermal performance is simulated through structure and material parametric simulation such as heat sink type and core type. Overall, this paper proposes the simulation method to predict both in-process warpage and reliability stress performance and also take thermal performance into considered. Besides, the metrology of in-process warpage prediction will be explained which suffers the saddle shape warping performance. Above that, the FO-EB-T package development that can save the DOE and reduce the warpage and stress risk is been proposed.
Cause and Prevention of Large Void Formation in Flip Chip Solder Connections
Authors: Ramos J. Ramirez , Marinis T. , Hanson D. 
Published: February 2025

X-ray inspection of large die bonded into ceramic packages revealed a high incidence of voids, whose size approached 20 percent of the solder volume. All voids appeared to form on the chip bond pads. Die attachment was performed on a high precision bonder with in-situ reflow under a formic acid atmosphere. The die were bumped with 98.2 tin / 1.8 silver weight percent solder on nickel coated copper pads. The cofired ceramic packages were metallized with electroless gold over nickel. Our investigation determined that the voids were initiated by formation of a gold-nickel-tin intermetallic compound that released hydrogen gas at the solder interface. This compound formed preferentially on the chip pads because after completing reflow, the bonder cooled the assembly by blowing nitrogen on it, which caused the chip to cool faster than the package because of its much lower thermal mass. The propensity for void formation was all but eliminated by reducing the peak reflow temperature, time above reflow, and making modifications to the bonder cooling system to reduce the temperature difference between the chip and its package. We believe that after the voids nucleated at the solder-intermetallic interface, they continued to grow by release of hydrogen from the molten solder. Our calculations indicate that a concentration of 0.0048% hydrogen atoms in the solder is sufficient to grow voids of the size that we observed. Our hypothesis that release of dissolved hydrogen drives void growth was supported by a hydrogen degassing experiment that we conducted. As-received solder bumped chips were baked under high vacuum for several days, and then bonded to silicon chips with gold/ nickel metallized bond pads. X-ray inspection of these assemblies revealed no voids in contrast to the multiple voids observed in similar samples that were bonded without the hydrogen degassing step.
Editorial Comment on “<i>Lady Urologist</i> and male patients with prostate cancer”
Authors: Costantini Elisabetta , Illiano Ester 
Published: February 2025

As a member of the Editorial Board and a pioneering woman in the world of urology, I would like to make some comments on the letter published in the present issue of Archivio Italiano di Urologia e Andrologia about Suzanne Koven's book published in 2021...
Pulmonary hypertension – Diagnosis and management
Authors: Jain Dikshant , Isser H. S. 
Published: February 2025

Abstract:
Pulmonary hypertension is estimated to involve about 1% of the population. It presents with symptoms of exertional, breathlessness and occasional chest pain, fatigue, and pedal edema. it involves the obliteration of pulmonary micro circulation and decreased gaseous exchange leading to the classical symptoms. Routine Blood tests diagnose a failing right heart. ECG and 2D Echo show right sided hypertrophy along with signs of pulmonary hypertension. Management includes diuretics, calcium channel blockers for patients responsive to vasoreactivity test, endothelin receptor, antagonists, phosphodiesterase inhibitors, and prostacyclin analogues and receptor agonists. More research is in the pipeline to slow the progression of the disease and alter the course but concrete evidence is awaited.
Dermoscopic Findings in Patients with Hyperpigmented Lesions: A Study from a Tertiary Care Hospital
Authors: Grewal Lamya , Bhushan Himani , Goyal Parul , Narang Ranchit , Chhina Parneet Kaur , Gill Supreet Singh , Sood Anurag 
Published: February 2025

Abstract

Background:
Pigmentary disorders impair the quality of life of patients and impart significant psychological morbidity. Clinically, while most lesions are recognised diagnosing some can be difficult because of the overlapping clinical picture. Dermoscopy is a non-invasive methodology wherein by using a dermoscope a diagnosis can be arrived at by careful observation of the presenting features.

Objective:
The present study aims to evaluate the dermoscopic findings in patients with hyperpigmented lesions using a Dino-Lite Edge/AM7115 series dermoscope.

Materials and Methods:
A total of 100 patients having hyperpigmented skin lesions of any age or sex were included in the study. A detailed clinical/dermatological examination was carried out using a Dino-Lite edge/AM7115 series dermoscope, and all dermoscopic findings were recorded.

Results:
The mean age of the patients was 32.07 ± 9.08 years. There were 70% females and 30% males indicating a female predominance. The most common site of lesions was the centro-facial region, observed in 47% of cases. The background colour of pigmentation that was assessed by dermoscopy showed dark brown lesions in all the cases indicating a 100% preponderance. The morphological pattern assessment indicated that irregular pigments were the most common in 64% of the cases. Dark brown dots/globules were found in 100% of the cases. The predominant pattern of pigmentation observed was reticulated in 53% of cases. The follicular findings showed perifollicular sparing in 65% of cases, whereas telangiectasia was seen in 48% of the cases.

Conclusion:
The study offers information on dermoscopic findings in hyperpigmented lesions from a northern tertiary care facility. This study supports the findings of earlier research by recommending that non-invasive use of a dermoscope is essential for accurate diagnosis. Larger research in the future might help in reducing the number of needless biopsies when treating hyperpigmented patients.
Safe and Healthy Green Jobs
Authors: Albin Maria , Håkansta Carin , Bodin Theo , Wadensjö Eskil , Broberg Karin 
Published: February 2025

The green transition builds on a change to fossil-free energy and to a circular economy. In a European context, the major policy initiative is the Green Deal. While this transition needs to be rapid, gains and losses of jobs need to be considered. This may have profound positive and negative effects for different occupational groups as greening of the jobs may both eliminate current risks (e.g. associated with fossil fuels), and introduce new ones. This article provides examples of such risks to occupational safety and health. It also discusse employment conditions and worker bargaining power in relation to the twin digital and green transition. In order to reduce negative effects of the green transition on the health and safety of workers, we suggest that there is an urgent need to establish strategies for Safe and Healthy Green Jobs. We proceed tosuggest steps towards such a Roadmap, and also indicate some key knowledge gaps.

Keywords
Green Deal, job gains and losses (eller Creative destruction?), occupational safety and health, circular economy, chemical health risks, twin transition, road-map for safe and healthy green jobs