bluuebunny/crossref_metadata_2025_split huggingface dataset:
Advanced Failure Analysis of Junction Profile Defect by Using EBAC/EBIC
Authors: Lee Jong Hak , Lee Jae Yoon , Kim Dae Woo , Jung Kyoung Wook , Son Soo Yong 
Published: December 2020

Abstract
As semiconductor device geometries shrink due to process technology development and circuit density rapidly increases, it is becoming extremely difficult to effectively analyze defects. Against this background, more precise and efficient techniques to analyze the root cause of defects is in constant demand. This paper proposes a method to quickly and accurately identify the true cause of device failure by using a nano probe EBAC/EBIC analysis technique. The most significant benefit of the EBAC/EBIC analysis technique is the ability to identify normal or abnormal circuit behavior with an intuitive image. This benefit can minimize the damage to a sample during the initial analysis phase, which has been an issue in the analysis of existing physical properties of semiconductors. In this paper, we identified the root cause of a series transistor defect in CIS (CMOS Image Sensor) product by using EBAC/EBIC (analysis) technique, and verified this with the assistance of SSRM (Scanning Spreading Resistance Microscopy) and APT (Atomic Probe Tomography). By doing so, we confirmed that the analysis technique proposed in this paper is very effective in identifying and pinpointing the true cause and location of the defect.
Characterization of 14 nm Silicon Integrated Circuits with 1.55–2 μm Emission Microscopy—A Case Study
Authors: Serrels K.A. , Kalarikkal A. , Jakati A.M. , Schmidt C. , Dabney G. 
Published: December 2020

Abstract
We describe here the first demonstration of 14nm silicon device characterization using 1.55-2µm emission microscopy as a technique to interrogate the radiative properties of various physical defects. A study is presented and discussed for cases highlighting photo-emission only, hybrid photo-thermal-emission, and thermal-emission only.
Signature Analysis of Device Failure Mechanisms on 2.5D Package IC Devices
Authors: Nuez Daniel C. 
Published: December 2020

Abstract
The growing popularity of 2.5D SSIT (Stacked Silicon Interconnect Technology) & 3D package technology in the IC industry had made it more challenging for manufacturers and packaging assembly sites to perform failure analysis and identifying the root causes of failures. There had been some technical papers written on various failure analysis techniques on 2.5D SSIT and 3D IC packages using a variety of equipment for detecting and localizing failures [1, 2]. This paper explains a non-evasive, non-destructive approach of localizing failures on a 2.5D SSIT package by identifying and recognizing certain waveform patterns that the failing devices exhibit in the scanning acoustic microscope A-Scan and in Time domain reflectometry. There are noticeable waveform patterns that an analyst can recognize and used to determine certain types of failure mechanisms that may be present in the device. Please note that it is very important to use the exact same type of package sample when characterizing and comparing waveform patterns as package variability from vendor to vendor and material contents can certainly affect the results.
Combining Current Imaging, EBIC/EBAC, and Electrical Probing for Fast and Reliable In-Situ Electrical Fault Isolation
Authors: Kleindiek Stephan , Kemmler Matthias , Rummel Andreas , Schock Klaus 
Published: December 2020

Abstract
Using a compact nanoprobing setup comprising eight probe tips attached to piezo-driven micromanipulators, various techniques for fault isolation are performed on 28 nm samples inside an SEM. The recently implemented Current Imaging technique is used to quickly image large arrays of contacts providing a means of locating faults.
Verification of DLS Data by LVP in Case of Marginal Failure
Authors: Kim Keonil , Kim Sungjin , Lee Kunjae , Jin Kyeongju , Lee Yunwoo , Lee Euncheol 
Published: December 2020

Abstract
In most of the non-destructive electrical fault isolation cases, techniques such as DLS, Photon Emission, LIT, OBIRCH indicate a fault location directly. But relying on just one of these techniques for marginal failure mechanism is not enough for better fault localization. When Failure Analysis (FA) engineers encounter high NDF (No Defect Found) rates, by using only one of the techniques, they may need to consider the relationship between the responded locations by different techniques and fail phenomenon for better defect isolation. This paper talks about how a responded DLS location does not always indicate a fault location and how LVP data collected using DLS location can pin point the real defect location.
Authentication of Printed Circuit Boards
Authors: Iyengar Anirudh , Vobilisetti Nareen , Ghosh Swaroop 
Published: December 2020

Abstract
Printed Circuit Boards (PCBs) are easy target for reverse engineering and counterfeiting attacks due to the distributed supply chain. The integrated circuits (ICs) authentication techniques such as Physically Unclonable Function (PUF) are not easily extendible to PCBs. In this paper, we analyze various sources of variations in PCB and qualitatively study the quality metrics that can be used to quantify the PCB PUFs. We propose several flavors of PCB PUFs by exploiting the manufacture process variations. We also propose a multi-stage arbiter PUF with exponential challenge response pairs. Our preliminary simulations revealed an average 50.4% inter-PCB hamming distance.
Open Failure Localization by Using MOFM—Magneto-Optical Frequency Mapping System with 532 nm Light Source
Authors: Nakamura Tomonori , Otaka Akihiro 
Published: December 2020

Abstract
Magnetic current imaging (MCI) is an effective method for the isolation of individual integrated circuit (IC) current paths [1]. MCI is therefore useful in localizing open/short defects. In the case of a short, the failure current must be large enough to enable the detection of the magnetic field; however, in the case of the open failure, the current is very weak and detection can be limited by the wiring capacitance and modulation frequency. Often, magnetic sensor sensitivity is a function of the sensor size. Superconducting Quantum Interference Device (SQUID) sensors can detect weak current in an open failure, but the resolution is limited by the sensor size and can be difficult to utilize for IC applications. A Giant Magnetic Resistance (GMR) sensor has enough resolution [2], but cannot achieve enough sensitivity till now. This paper will present the use of Magneto-Optical Frequency Mapping (MOFM) using a 532nm light source. In addition, this paper will describe a specific IC application for an open failure measurement. For this technique, the MO crystal (sensor material) is placed directly on the DUT (a wiring test sample). This paper will demonstrate that the magnetic field modulation from AC current in open wirings can be detected. In addition, the details of the AC current path can be visualized using a Magneto-Optical based MCI measurement. Finally, the open point in the failing circuit will be shown to be isolated with an accuracy of a few tens of micrometers.
Fault Localization by Finding Schematic of Devices Connecting All Emission Sites in Photon Emission Microscope Image
Authors: Oberai Ankush , Yuan Jiann-Shiun 
Published: December 2020

Abstract
The work presented here is related to the utilization of computer aided design (CAD) Navigation tools in combination with images from Emission Microscope (EMMI) to improve the accuracy and efficiency of Failure Analysis. The paper presents the flow to quickly identify the failing device by taking the photon emission microscope image and CAD data as input. EMMI is used extensively for detecting leakage current resulting from device defects, e.g., gate oxide defects/ leakage, latch-up, electrostatic discharge (ESD) failure, junction leakage, etc. This emitted light is captured as hotspots on the image. A typical photon emission microscope image has a series of photon emission spots initiated by one physical defect. Not all emission spots may be defects; for example, emissions are shown during normal saturation or switching mode of the transistor. This results in multiple connectivity path between these spots which failure analysis (FA) engineer may want to analyze. The FA engineer wants to detect the one failed device which causes multiple other devices to show false hotspots. The work presented in this paper involves identifying all the devices beneath the hotspot areas, processing the connectivity of the found devices and extracting the schematic for all the devices beneath these hotspots. The connectivity between the devices could be direct connections through nets or indirect through “transmission gates”. The extracted schematic helps the FA engineer focus the FA work on critical devices such as a driver and enables faster and more accurate fault localization. The work in the paper shows the extraction of critical path of devices and their connectivity.
Laser Silicon Interaction Study on Ring Oscillators to Establish Temperature Voltage Dependency Trends on 14 nm and Future FinFET Technologies
Authors: Mattey Gaurav , Ranganathan Lava 
Published: December 2020

Abstract
Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.
Application of Conductive-AFM in Soft Failure Analysis
Authors: Zhang Chuan , Ma Yinzhe , Dabney Gregory , Khiam Oh Chong , Chen Esther P.Y. 
Published: December 2020

Abstract
Soft failures are among the most challenging yield detractors. They typically show test parameter sensitive characteristics, which would pass under certain test conditions but fail under other conditions. Conductive-atomic force microscopy (CAFM) emerged as an ideal solution for soft failure analysis that can balance the time and thoroughness. By inserting CAFM into the soft failure analysis flow, success rate of such type of analysis can be significantly enhanced. In this paper, a logic chain soft failure and a SRAM local bitline soft failure are used as examples to illustrate how this failure analysis methodology provides a powerful and efficient solution for soft failure analysis.
Magnetic Field Imaging on Stacked Flash Memories by Laser Probing and SQUID Scanning
Authors: Sanchez K. , Bascoul G. , Infante F. , Courjault N. , Nakamura T. 
Published: December 2020

Abstract
Magnetic field imaging is a well-known technique which gives the possibility to study the internal activity of electronic components in a contactless and non-invasive way. Additional data processing can convert the magnetic field image into a current path and give the possibility to identify current flow anomalies in electronic devices. This technique can be applied at board level or device level and is particularly suitable for the failure analysis of complex packages (stacked device & 3D packaging). This approach can be combined with thermal imaging, X-ray observation and other failure analysis tool. This paper will present two different techniques which give the possibility to measure the magnetic field in two dimensions over an active device. Same device and same level of current is used for the two techniques to give the possibility to compare the performance.
Pico-Second Laser and Broad Argon Beam Tools for Characterization of Advanced Packaged Devices
Authors: Wang Y. , Spence C. , Coyle S. , Hunt J. , Shearer M. Hassel 
Published: December 2020

Abstract
In this paper, a workflow consisting of a pico-second laser tool followed by a broad argon beam tool is proposed as a solution for extremely large area preparation with surfaces suitable for SEM and FIB based analysis directly after polishing in the broad argon beam tool. Results are presented discussing the advantages of this workflow in terms of speed, size and quality of the surface for electron microscopy analysis. The use of the broad argon beam tool to complete the process produces near perfect interfaces especially compared to mechanical preparation techniques on the multilayers with vastly different properties found in advanced packages. Additionally, the tool can be used for backside thinning and reducing front side delayering.
Halogen-Free Microwave Induced Plasma Decapsulation of System in Package Modules
Authors: Tang J. , Wang J. , Dixon-Warren St.J. , Beenakker C.I.M. 
Published: December 2020

Abstract
When it comes to complex system-in-package (SiP) with a wide spectrum of materials and packaging structures integrated into a single module, decapsulation and the following failure analysis become extremely complex. Previous work published by the authors' group has demonstrated that a halogen-free microwave induced plasma (MIP) system has great advantage compared to the conventional techniques mentioned before. This paper explores the applicability of the halogen-free MIP on the most complex SiP module decapsulation. Applications in special structures in SiP include 3D stacked-die, gallium arsenide, surface acoustic wave (SAW) and bulk acoustic wave filters, and copper re-distribution layer. The halogen-free MIP decapsulation process can expose and preserve all the dies and passive components as well as the original failure sites, which proves to be key to ensuring a high success rate in SiP failure analysis.
Efficient and Effective Failure Analysis of Low-Resistive Defect in Logic Device Using Layout-aware and Volume Diagnosis
Authors: Song Ho Seok , Park Eun Ji , Kim Tae Hwan , Kang Dong Hae , Hong Jong Taek , Kim Ju-Heon , Won Seok-Jun , Kim Jin Sung 
Published: December 2020

Abstract
Efficient and effective failure analysis (FA) of low-resistive defect was studied by using layout-aware and volume diagnosis. Small or marginal defect is one of the most difficult defectivities to identify during FA effort, especially if defect-induced resistance is not as high as the electrical isolation can detect. Here, we used new analysis methodologies, particularly using layout-aware and volume diagnosis, and prioritizing patterns in terms of a defective risk for following FA. The actual FA work verified that new analysis methodologies successfully identified low-resistive defect of Back-End-of-Line (BEOL) which was not detected by a conventional way and efficiently reduced the turn-around time (TAT) of physical failure analysis (PFA) by 57%, prompting fast feedback to fab.
Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis
Authors: Ting Seng Nguon , Lo Hsien-Ching , Nedeau Donald , Sinnott Aaron , Beaudoin Felix 
Published: December 2020

Abstract
With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.
High-Resolution Image Fusion of Linearly Polarized Subsurface Optical Images
Authors: Cilingiroglu T. Berkin , Leslie Neel , Somani Seema , Sabbineni Prasad 
Published: December 2020

Abstract
In high numerical aperture (NA) subsurface imaging, we can obtain higher resolution in selected directions at the expense of resolutions in other directions, utilizing the vectorial properties of polarized light. In this work, we propose an image fusion framework that produces a single image with higher resolution and image quality in all directions by processing multiple images acquired by varying the polarization direction of the linearly polarized input laser light.
Single Shot Logic Patterns: Increasing Diagnostic Resolution of Logic Failures Utilizing Single Fault Targeting and Constraints
Authors: Estores Rommel , Barbian Eric 
Published: December 2020

Abstract
ATPG diagnosis is an essential part in failure analysis and is proven to be an effective technique in isolating faults in the digital core. In many single failure cases however, ATPG diagnosis could yield either incorrect candidates or includes a large amount of equivalency which limits diagnostic resolution. While iterative ATPG diagnosis improves diagnostic resolution, there are many cases where the resolution is still insufficient. This paper will discuss a methodology that helps the analyst understand and complement ATPG diagnosis by using an approach called “single shot logic patterns”. New patterns that each target one singular fault in the area of interest provide the failure analyst with simplified analytical data. This process is repeated for each suspect candidate. The number of times a target fault is detected is increased for better resolution. Aggregating this analytical data with the layout and fan out of the net instances could provide greater resolution into the likely defective area. Furthermore, adding constraints can also be used to further simplify the test and/or control the fan out of failures. Only equivalencies where there is observable fan out can achieve greater diagnostic resolution. ATPG tools have been observed to not always maximize this fan out.
Backside Mechanical Preparation Methodology for Effective Failure Analysis on Small and Non-Exposed Die Paddle Package
Authors: Hoon Ong Pei , Kay Ng Kiong , Yen Gwee Hoon 
Published: December 2020

Abstract
Chemical etching is commonly used in exposing the die surface from die front-side and die backside because of its quick etching time, burr-free and stress-free. However, this technique is risky when performing copper lead frame etching during backside preparation on small and non-exposed die paddle package. The drawback of this technique is that the copper leads will be over etched by 65% Acid Nitric Fuming even though the device’s leads are protected by chemical resistance tape. Consequently, the device is not able to proceed to any other further electrical measurements. Therefore, we introduced mechanical preparation as an alternative solution to replace the existing procedure. With the new method, we are able to ensure the copper leads are intact for the electrical measurements to improve the effectiveness and accuracy of physical failure analysis.
High Resolution Mapping of Subsurface Defects at SiO2/SiC Interfaces by Time-Resolved Scanning Nonlinear Dielectric Microscopy
Authors: Yamagishi Yuji , Cho Yasuo 
Published: December 2020

Abstract
High resolution observation of density of interface states (Dit) at SiO2/4H-SiC interfaces was performed by time-resolved scanning nonlinear dielectric microscopy (tr-SNDM). The sizes of the non-uniform contrasts observed in the map of Dit were in the order of several tens of nanometers, which are smaller than the value reported in the previous study (&gt;100 nm). The simulation of the tr-SNDM measurement suggested that the spatial resolution of tr-SNDM is down to the tip radius of the cantilever used for the measurement and can be smaller than the lateral spread of the depletion layer width.
A Study of Clustering for the Enhancement of Image Resolution in Dynamic Photon Emission
Authors: Chef S. , Chua C. T. , Gan C. L. 
Published: December 2020

Abstract
Limited spatial resolution and low signal to noise ratio are some of the main challenges in optical signal observation, especially for photon emission microscopy. As dynamic emission signals are generated in a 3D space, the use of the time dimension in addition to space enables a better localization of switching events. It can actually be used to infer information with a precision above the resolution limits of the acquired signals. Taking advantage of this property, we report on a post-acquisition processing scheme to generate emission images with a better image resolution than the initial acquisition.
Case Study of Electro-Optical Probing Signal with High Signal-Noise Ratio
Authors: Xiao Ryan , Wang William , Li Ang , Xu Shengqiu , Liu Binghai 
Published: December 2020

Abstract
With the development of semiconductor technology and the increment quantity of metal layers in past few years, backside EFA (Electrical Failure Analysis) technology has become the dominant method. In this paper, abnormally high Signal Noise Ratio (SNR) signal captured by Electro-Optical Probing (EOP)/Laser Voltage Probing (LVP) from backside is shown and the cause of these phenomena are studied. Based on the real case collection, two kinds of failure mode are summarized, and simulated experiments are performed. The results indicate that when a current path from power to ground is formed, the high SNR signal can be captured at the transistor which was on this current path. It is helpful of this consequence for FA to identify the failure mode by high SNR signal.
Visualization and Measurements of 3D Structures in Memory and Logic Devices
Authors: Avishai A. , Buxbaum A. , Klochkov D. , Neumann J. T. , Korb T. , Foca E. 
Published: December 2020

Abstract
This paper describes the application of 3D FIB-SEM tomography as a method for quantifying process variations across the die and across the wafer, as well as layout investigations. In this study, the analysis of results acquired by 3D FIB-SEM tomography were applied to a 64L 3D-NAND device where process induced variation in the high aspect ratio vertical memory channels is measured and to a double stack 3D-NAND architecture, which is comprised of two 32-layer stacks where eccentricity of the pillars was evaluated for layers in both upper and lower stacks. In addition, a partial layout of a 14nm logic device is investigated by this method, demonstrating the capabilities for structural verification, and structural overlay of elements from a 7nm logic device were also evaluated. The results demonstrate the value of 3D FIB-SEM tomography for physical confirmation of the structural layout, which can be applied towards device debug and reverse engineering.