bluuebunny/crossref_metadata_2025_split huggingface dataset:
Elimination of Whisker Growth on Tin Plated Electrodes
Authors: Endo M. , Higuchi S. , Tokuda Y. , Sakabe Y. 
Published: December 2020

Abstract
At the surface of the tin-plated brass substrate placed at 50°C, the tin whiskers grew evidently within a short time, due to the formation of zinc oxide on the surface and alloying between plated tin and brass substrate as supposed. While at the surface of the brass substrate plated with tin on nickel, there was no trace of the tin whisker at all. Nickel greatly represses the diffusion of base metal materials into the tin layer. Nickel and tin plated monolithic chip capacitors placed at the same condition for 18 years were also observed and the tin whisker growth phenomenon has never taken place either. As a result, the tin plated film on the nickel over silver thick film does not provide the tin whisker growth. Nickel underplating plays an important role in tin plated capacitors for not only the solder leaching but also the tin whisker growth problems.
Characterization of CMOS Structures (0.6 µm process) Submitted to HBM and COM ESD Stress Tests
Authors: Meneghesso G. , Zanoni E. , Colombo P. , Brambilla M. , Annunziata R. , Pavan P. 
Published: December 2020

Abstract
In this work, we present new results concerning electrostatic discharge (ESD) robustness of 0.6 μm CMOS structures. Devices have been tested according to both HBM and socketed CDM (sCDM) ESD test procedures. Test structures have been submitted to a complete characterization consisting in: 1) measurement of the tum-on time of the protection structures submitted to pulses with very fast rise times; 2) ESD stress test with the HBM and sCDM models; 3) failure analysis based on emission microscopy (EMMI) and Scanning Electron Microscopy (SEM).
SEM Equipment Capabilities Evaluated for Sub-Half Micron Semiconductor Applications
Authors: Cowan J. , Taylor T. 
Published: December 2020

Abstract
Evaluation of Scanning Electron Microscopes (SEMs) was initiated for the purpose of purchasing a SEM that would improve the productivity of scanning electron microscopy during the cycle of analysis and deprocessing of semiconductor devices in a failure analysis lab. In addition to the need for high image resolution at low electron acceleration voltages, an accurate motorized stage is a major evaluation factor. It is necessary for the analyst to drive directly to a known location such as a memory cell with a high assurance that the site of interest was found. There are two main areas of focus in this paper. First, our SEM evaluation methodology will be presented along with the results of our evaluation. Second, the technology associated with motorized stages will be discussed in light of our requirements for a motorized, highly accurate stage. As a byproduct of this evaluation, this paper is presented so as to push the SEM industry to offer a SEM with an accurate stage for subhalfmicron products at reasonable cost.
An Effective and Practical Analysis Technique for Open Defect Isolation at IDD Leakage Failure by Observing Transient Photo Emission
Authors: Nishikawa A. , Kato N.I. , Matsuzawa J. , Takagi K. , Miura N. 
Published: December 2020

Abstract
A new analysis method using conventional emission microscopy (EMS) was developed for localizing open defects in CMOS LSIs. EMS is widely used for failure analysis of IDD (power supply current) leakage failures. The root cause of a failure is deduced by considering the emission characteristics associated with the IDD leakage current, emission shape, emission energy spectrum, and exact location on an Si die. Our new technique focuses on the observation of transient photoemission immediately after VDD application. During IDD leakage failure analysis, unique transient photoemission characteristics are observed. Immediately after VDD application, strong photoemission is briefly observed at the drain edge of an n-FET, but disappears after stabilization of the IDD current. We assumed that temporary photoemission would not be generated in transient behavior unless some kind of open defects were located at a specific conductor connected to the gate electrode. This mechanism was verified by nonbiased charge-up contrast of a conventional secondary electron image (SEI) and cross-sectional SEM observation at the defective open location. The dynamic method of observing transient photoemission proposed here is a very effective and practical way for detecting the locations of open failures in CMOS LSIs. Some examples of open mode failure analysis are described, along with cross-sectional TEM observations.
Identification of Charging Effects in Plasma-Enhanced TEOS Deposition with Non-Contact Test Techniques
Authors: Brozek Tomasz , Heddleson James 
Published: December 2020

Abstract
Use of non-contact test techniques to characterize degradation of the Si-SiO2 system on the wafer surface exposed to a plasma environment have proven themselves to be sensitive and useful in investigation of plasma charging level and uniformity. The current paper describes application of the surface charge analyzer and surface photo-voltage tool to explore process-induced charging occurring during plasma enhanced chemical vapor deposition (PECVD) of TEOS oxide. The oxide charge, the interface state density, and dopant deactivation are studied on blanket oxidized wafers with respect to the effect of oxide deposition, power lift step, and subsequent annealing.
Investigation of High Via Resistance of a 0.25μm CMOS ASIC Technology
Authors: Sur H. , Bothra S. , Lei R. , Hahn J. , Brugge H.J. 
Published: December 2020

Abstract
An investigation into a high resistance via problem during the development phase of an advanced 0.25µm CMOS ASIC process is presented. The electrical signature of the via problem was low yield on fully processed device wafers. Further testing revealed that the logic (cell-based) sections of the chip were functioning, however the 512K bit SRAM was consistently failing. Based on the failing bit pattern, the failure area was isolated to contact-via stacks in the cell. Advanced wafer level failure analysis techniques and equipment such as focused ion beam milling, precision cross-section, and planar polishing techniques were utilized to identify the layer that was failing. Analysis results indicated a thin foreign layer or void between the aluminum line and the cap barrier layer of the line. Placement of a via on this line resulted in a high resistance node and subsequent device failure. As a further verification of the electrical failing signature, SPICE simulation was run on the SRAM cell circuitry. Optimization of the metallization stack was performed through experiments which resulted in the elimination of the mechanism.
Non-destructive Chemical Decapsulation Techniques for TBGA Package Devices
Authors: Esfahani Lili 
Published: December 2020

Abstract
Failure analysis on TBGA (Tape Ball Grid Array) package devices is a rather difficult task, due to the material used for assembly. This paper will introduce two novel techniques for non-destructive deprocessing procedures used in performing analysis on TBGA devices. These new techniques do not introduce additional failures to the devices during the deprocessing procedure. The workable TBGA devices can then be powered up and analyzed using different techniques and equipment. In the first technique, molding compound (potting resin) is removed around the tab tape area or the chip is fully exposed. The first technique will allow the analyst to inspect any bonding problems. These devices can then be analyzed using probe stations and visually inspected using microscopes. In the second technique, molding compound is partially (tab tapes and protective diode areas are not exposed) removed. These partially decapped TBGA devices, can be analyzed using testers, emission microscopes, liquid crystal, multi-curve tracer, and FIB. The advantage of this technique is to be able to analyze devices without worrying about any additional failures (such as contact, functional, and leakage failures) introduced in to the devices during deprocessing.
Techniques to Remove the C4 Die from a Ceramic Package
Authors: Mahanpour Mehrdad , Gray Andy , Hulog Jose , Chang Pat 
Published: December 2020

Abstract
C4 (Controlled Collapse Chip Connection) failure analysis compared to conventional packages (DIP- LCC- QFP, etc.) is not trivial. For instance, one has to thin the C4 die for IR microscope inspection or for photon emission analysis. Then, after failure analysis on the die, it must be removed for deprocessing or further analysis. Three methods and techniques will be discussed for removing the C4 die from the package without damaging the die. However, for each technique it is very important to know the condition of the die and package prior to die removal. The method used will differ, for example, if the die is thinned or not.
Innovative Application of a Passive Device Failure Analysis Technique to a JFET
Authors: Erickson J.J. , Ditz M.J. 
Published: December 2020

Abstract
A technique normally used for the analysis of tantalum capacitor failures was successfully applied to a JFET. The JFET had a short from the source to the gate. The short was located at the source bond pad and had resulted from a combination of the use of too large a bond wire and excessive bonding pressure. The exact location of the site of the short was successfully determined by using a copper electroplating technique typically used for locating shorts or leakage sites on the tantalum slug of a tantalum capacitor.
Analysis of FSRAM Single Bit Failures Due to Unique Dislocations
Authors: Schani Phil , Subramanian S. , Soorholtz Vince , Liston Pat , Moss Jamey , Widener Ed , Chu Amy 
Published: December 2020

Abstract
Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.
Identifying Plastic Encapsulant Materials by Pyrolysis Infrared Spectrophotometry
Authors: Lowry Robert K. , Hanley Kristen L. 
Published: December 2020

Abstract
Most semiconductor devices are sealed in plastic. Virtually all plastic encapsulated microcircuits (PEMs) look alike. The particular electronic molding compound (EMC) used to encapsulate a device cannot be known except from production records or firsthand knowledge of people familiar with the device. For a variety of reasons, an EMC may need to be explicitly identified. Pyrolysis of the EMC, followed by Fourier Transform Infrared (FT-IR) chemical analysis of the condensates of organic substances evolved by the pyrolysis, and comparison of the spectra with a reference library of known EMCs, provides a rapid means of specific EMC identification.
Backside Emission Microscopy for Integrated Circuits on Heavily Doped Substrate
Authors: Chiang Ching-Lang , Khurana Neeraj , Hurley Daniel T. , Teasdale Ken 
Published: December 2020

Abstract
Backside emission microscopy on heavily doped substrate materials was analyzed from the viewpoint of optical absorption by the substrate and sample preparation technique. Although it was widely believed that silicon is transparent to infrared (IR) radiation, we demonstrated by using published absorption data that silicon with doping levels above 5 x 1018cm-3 is virtually opaque, leaving only a narrow transmission window around the energy bandgap. Because the transmission depends exponentially on the thickness of die, thinning to below 100µm is shown to be required. Even an advanced IR sensor such as HgCdTe would find little light to detect without thinning the die. For imaging the circuit, an IR laser-based system produced poor images in which the diffraction patterns often ruined the contrast and obscured the image. Hence, a precise, controlled die thinning technique is required both for emission detection and backside imaging. A thinning and polishing technique was briefly described that was believed to be applicable to most ceramic packages. A software technique was employed to solve the image quality problem commonly encountered in backside imaging applications using traditional microscope light source and a scientific grade CCD camera. Finally, we showed the impact of die thickness on imaging circuits on a heavily doped n type substrate.
Infrared Emission Spectroscopy as a Reliability Tool
Authors: Kim Q. , Kayali S. 
Published: December 2020

Abstract
In this paper, we report on a non-destructive technique, based on IR emission spectroscopy, for measuring the temperature of a hot spot in the gate channel of a GaAs metal/semiconductor field effect transistor (MESFET). A submicron-size He-Ne laser provides the local excitation of the gate channel and the emitted photons are collected by a spectrophotometer. Given the state of our experimental test system, we estimate a spectral resolution of approximately 0.1 Angstroms and a spatial resolution of approximately 0.9 μm, which is up to 100 times finer spatial resolution than can be obtained using the best available passive IR systems. The temperature resolution (&lt;0.02 K/μm in our case) is dependent upon the spectrometer used and can be further improved. This novel technique can be used to estimate device lifetimes for critical applications and measure the channel temperature of devices under actual operating conditions. Another potential use is cost-effective prescreening for determining the 'hot spot' channel temperature of devices under normal operating conditions, which can further improve device design, yield enhancement, and reliable operation. Results are shown for both a powered and unpowered MESFET, demonstrating the strength of our infrared emission spectroscopy technique as a reliability tool.
Investigation on the Corrosion of Cu Metallization in the Focused Ion Beam System due to a low I2 Background
Authors: Bender H. J. , Jin S. , Vervoort I. , Lantasov Y. 
Published: December 2020

Abstract
The corrosion effect of an I2 background during focused ion beam (FIB) analysis of Cu-metallization structures is investigated. In-situ Cu corrosion in the FIB system can occur even if the I2 gas has not been used anymore in the last 24 h before the loading of the Cu sample in the system including several vents and pump-downs of the chamber in that period. Hence the I2 can have a long-term memory effect and is not compatible with FIB analysis or modification of devices with Cu metallization. Compositional and structural analysis shows that the reaction product is CuI.
Temperature Measurement on Micromachined IR Bolometers Using an Infrared Microscope
Authors: Trigg A.D. , Sridhar U. , Lee H.S. , Karunasiri G. 
Published: December 2020

Abstract
Thermal properties are critical to the performance of micromachined silicon bolometers. In order to verify thermal models of the device, a means of measuring the local temperature distribution over the element is required, as it is heated by passing current through a thin film titanium meander. Because of the very low thermal mass of the membrane a non-contact method of temperature measurement is needed. Most conventional thermal imaging systems operate in the wavelength range 5-15 μm and offer poor spatial resolution but in this work an infrared microscope, operating at shorter wavelengths, was used. The microscope comprises an objective lens which focuses radiation onto a cooled (77K) cadmium mercury telluride focal plane array sensitive over the range 800 nm to 2500nm. For this application a bandpass filter centered at 2150 nm was used. Good agreement was obtained between finite element modeling of the temperature distribution, using ANSYS, and the measured data.
FMECA Modeling - A New Approach
Authors: Bot Yizhak 
Published: December 2020

Abstract
FMECA tools must be included into the designers tools suite in order to support the new vision for a concurrent engineering environment. To support this new vision we introduce a major enhancement to the Failure Mode Effects and Criticality Analysis (FMECA) to provide a more accurate, simpler, accessible and frequently used computerized analysis tool. We introduce new terminology to enhance the well-known standards, while assuring their full support. Using the new terminology, functional trees become very similar to the project trees and can be drawn as block diagrams, e.g. the time spent on constructing the functional trees is reduced by factors.
Advanced Statistical Tools for Improving Yield and Reliability
Authors: Kittler Richard C. 
Published: December 2020

Abstract
Analysis of manufacturing data as a tool for failure analysts often meets with roadblocks due to the complex non-linear behaviors of the relationships between failure rates and explanatory variables drawn from process history. The current work describes how the use of a comprehensive engineering database and data mining technology over-comes some of these difficulties and enables new classes of problems to be solved. The characteristics of the database design necessary for adequate data coverage and unit traceability are discussed. Data mining technology is explained and contrasted with traditional statistical approaches as well as those of expert systems, neural nets, and signature analysis. Data mining is applied to a number of common problem scenarios. Finally, future trends in data mining technology relevant to failure analysis are discussed.
Failure Analysis of Autoclave-Stressed SRAMs with Aluminum Fuses
Authors: Moss Jamey , Subramanian Sam , Soorholtz Vince , Thomas Michael , Gerber Mark , Chan C. M. 
Published: December 2020

Abstract
Several hundred units were subjected to autoclave stress as part of the qualification of a new fast static RAM. Many units failed after autoclave stress, and these parts recovered after conventional depotting using nitric acid and a hot plate. Based on the recovery of the units, the failures were determined to be fuse-related because the nitric acid cleared the fuse cavities during depotting. Chemical analysis after thermally extracting the die from the package revealed an antimony-rich material in failing fuse cavities. Source of the antimony was linked to antimony trioxide added to the plastic package as a fire retardant. However, it was unclear whether the antimony-rich material caused the failure or if it was an artifact of thermal depotting. A new approach that did not thermally or chemically alter the fuse cavities was employed to identify the failing fuses. This approach used a combination of back-side grinding, dimpling, and back-side microprobing. The antimony-rich material found in the fuse cavity was confirmed using SEM and TEM-based EDS analysis, and it is believed to be a major contributing factor to fuse failures. However, it is unclear whether the short was caused by the antimony-rich material or by a reaction between that material and residual aluminum (oxide) left in the fuse cavity after the laser blows.
New Techniques for Logic Fault Diagnosis with a Case Study on the 440BX Chipset
Authors: Venkataraman Srikanth , Drummonds Scott B. 
Published: December 2020

Abstract
Logic fault diagnosis or fault isolation is the process of analyzing failing random logic portions of a chip to isolate the cause of failure. Fault diagnosis or fault isolation (FI) plays an important role in multiple applications at different stages of design and manufacturing. Most currently deployed FI techniques for random logic fault isolation include physical techniques with limited automated diagnosis followed by e-beam and/or laser voltage probing (LVP) on packaged parts. This paper will present the methodology and FI results obtained by executing automated scan based diagnosis on a chipset product (440BX). The logic diagnosis techniques used are presented along with simulation and Failure Analysis (FA) results
Visualization of Local Gate Depletion in PMOSFETs Using Unique Backside Etching and Selective Etching Technique
Authors: Nishida Akio , Sekiguchi Tomoko , Yamanaka Toshiaki , Yamada Renichi , Nakamura Kuniyasu , Tomimatsu Satoshi , Umemura K. , Kakibayashi Hiroshi , Yoshida Yasuko , Funayama Kohta , Ikeda Shuji 
Published: December 2020

Abstract
A novel backside-analysis technique has been developed to identify the locations of failing transistors in manufactured LSIs. Local gate doping depletion in p+ salicide gates of PMOSFETs, which reduces drain current, was visualized for the first time. Our method consists of backside etching and subsequent selective wet etching of the gate electrode. Si substrate material was removed with a highly selective Si etchant without damaging the gate-oxide film. After the gate-oxide film removal, a locally depleted gate was selectively etched using the same etchant. Since the etching rates of nondoped Si and n+ Si are much higher than that of p+ Si for the etchant, the depleted p+ gates were well defined. Through TEM observation, we found that a large grain lay on an active channel region of a PMOSFET. This led us to attribute the gate depletion to the difference in the impurity diffusion between large and small grains. This demonstration confirmed that our technique should be quite useful for identifying failing transistor locations in manufactured memory and logic LSIs.
Advanced Micro-Surgery Techniques and Material Parasitics for Debug of Flip-Chip Microprocessor
Authors: Livengood Rick H. , Winer Paul , Giacobbe John A. , Stinson Jason , Finnegan John D. 
Published: December 2020

Abstract
Silicon microsurgery, also known as on-silicon circuit editing, has evolved into a critical capability for the ramp-up of a new microprocessor or complex integrated circuit (IC) from tapeout to production. The ability to perform edits directly on a packaged device serves two major purposes during a product’s ramp. The first is to perform in-situ verification of logic and timing related design changes, and the second is to provide engineering samples to enable further debug for system and tester level validation. In both cases, sample generation using silicon microsurgery technology can be performed in a fraction of the time it would take to tapeout a new mask layer and generate samples through the fabrication process. Silicon microsurgery techniques are also employed to assist with failure analysis. For this application, these techniques are applied to help isolate a stuck-at fault or open on a failing node. This is done by bi-passing the failure point, through signal rerouting or by performing isolation cuts to further localize the defect. This paper will review several advanced siliconmicrosurgery edit applications and supporting technologies, microsurgery RC material properties, and finally some results from 0.25 and 0.18 micron technologies.
Laser Voltage Probe (LVP): A Novel Optical Probing Technology for Flip-Chip Packaged Microprocessors
Authors: Yee Wai Mun , Paniccia Mario , Eiles Travis , Rao Valluri 
Published: December 2020

Abstract
A novel optical probing technique to measure voltage waveforms from flip-chip packaged complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) is described. This infrared (IR) laser based technique allows signal waveform acquisition and high frequency timing measurement directly from active PN junctions through the silicon backside substrate on IC’s mounted in flip-chip, stand-alone, or multi-chip module packages as well as wire-bond packages on which the chip backside is accessible. The technique significantly improves silicon debug & failure analysis (FA) through-put time (TPT) as compared to backside electron-beam (E-beam) probing because of the elimination of backside trenching and probe hole generation operations.