bluuebunny/crossref_metadata_2025_split huggingface dataset:
Time Resolved LADA Using a Modulated Pulsed Laser to Fault Isolate Bridging Defects and Framing High Accuracy Physical FA Plan in 14 nm FinFET Technologies
Authors: Mattey Gaurav , Ranganathan Lava 
Published: December 2020

Abstract
Dynamic Laser Stimulation using Continuous Wave (CW) Lasers has been a very important technique in fault isolating soft failures due to process defects and design speed paths in microprocessors. However, the rapid scaling down of the process technologies and the high density of logic laid out in silicon has made it difficult to precisely fault isolate using a conventional continuous wave laser which has a laser spot size of about ~300nm. Also, the remnant effects of a CW laser DLS like banding due to n-well interactions make it further difficult to achieve high resolution fault isolation. In this paper we discuss how by using a modulated pico-second pulsed laser, a DLS suspect is isolated to cell internal nets, which using a CW laser spanned across multiple cells. This is achieved by modulating the pulsed laser using an Electro-optical modulator and restricting the stimulation to only those parts of a test-pattern where the signal propagation occurs. Also, by synchronizing the pulsed laser with the clock of the test-program and changing the laser pulse delivery in time, high stimulation levels were achieved without being invasive. This revealed extra data points (DLS sites) that can help with making precisely accurate Physical FA plans that reduce turnaround time and also ensure high success rates. Specifically, in the case of a bridging defect between two nets wherein DLS sites were only seen on the victim net using conventional CW laser, the time resolved pulsed laser revealed DLS sites on the aggressor net as well. This confirmed the bridging between the two nets since the aggressor net was not electrically connected with the victim net. We discuss in detail how the DLS sites play their role in framing the perfect Physical FA plan. A detailed study of the resolution achieved using time resolved pulsed laser and its comparison with the same using a CW laser is shown on 14nm FinFET technology.
Process Flow Employed for Parametric Test Structure Shorts Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries
Authors: Kodali Satish , Nasimullah Mia , Wei Yuting , Oh Chong Khiam , Beaudoin Felix 
Published: December 2020

Abstract
With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. It becomes very important to understand the root cause of failures at fastest pace to take necessary corrective actions. The use of ultra low K dielectrics for back end of line wafer build for advanced nodes created significant constraints on conventional beam imaging methods for fault isolation. This paper provides a streamlined process flow for root cause identification on shorts on advanced 20 nm and sub-20 nm technologies. Three unique cases are presented to demonstrate three typical situations identified in the process flow. They are blown capacitors, gate leakage, and resistance ladder short isolation.
A Novel Method/Model for Fault Localization of a Subtle Open on a Large Thin-Film Resistor, Using Photon Emission Microscopy Technique and Electric Field Mechanism
Authors: Kumar Vikash , Udrea-Spenea Marian 
Published: December 2020

Abstract
Photon Emission Microscopy (PEM) is one of the commonly used and powerful techniques for fault localization which uses a sensitive camera (like CCD or InGaAs) to detect a light (photon) emission from an electrically biased device. The fault localization of an open anomaly can be a challenge for the failure analysis. This paper discusses a novel technique for localization of an open fault on a thin-film resistor using induced photoemission method. In this proposed method, an emission site is induced at the open fault location on the thin-film resistor. This method was found to be effective and it increases the success rate for an open fault localization on a thin-film resistor.
Resolve of OTP Failures through Electrical Simulation Using AFP Nanoprobing in Wafer Fabrication
Authors: Ang Ghim Boon , Chen Changqing , Ng Hui Peng , Ng Peng Tiong , Quah Alfred , Teo Angela , Tam Yong Seng , Mai Zhihong , Lam Jeffrey 
Published: December 2020

Abstract
This paper illustrated the beauty of AFP nanoprobing as the critical failure analysis tool in resolving the one-time programmable (OTP) non-volatile memory data retention failures through electrical simulation in wafer fabrication. Layout analysis, electrical simulation using Meilke’s method, UV erase methodology (to differentiate between mobile ion Meilke’s method contamination and charge trap centers) and a few other FA approaches were employed to determine the different root causes in the three OTP failure case detailed in this paper.. These include SiN trap center issue, poly stringers and abnormal layer at the initial CESL (Contact etch stop layer) nitride. This paper placed a strong emphasis on systematic problem solving approach, deep dive and use of right FA approach/tool that are essentially critical to FA analysts in wafer foundry since there is always minimal available data provided. It would serve as a good reference to wafer Fab that encountered such issue.
Novel IC Device Repackaging for SIL and Backside Analysis Capability
Authors: Muela Leandro , Kabadi Raj , Barbian Eric 
Published: December 2020

Abstract
A novel approach for solid immersion lens (SIL) assisted imaging and backside analysis of chip-on-board devices is presented. The procedure relies on complete die extraction from its original package, and repackage into a FA-friendly Plastic Quad-Flat Package (PQFP) chip carrier with inverted mold configuration, which enables access to the backside of the die through grinding/polishing or other methods. This procedure also relies on complementing use of device-specific DUT boards with generic arrangement of I/O, ground and power domains, coupled with a bench-test board equipped with the same pin-out configuration and a custom carrier built specifically for these DUT boards. This generic approach broadens the use of this solution to an entire family of devices and offers a balance of test capability leading to fault localization success and cost control.
Detection of Local Cu-to-Cu Bonding Defects in Wafer-to-Wafer Hybrid Bonding Using GHz-SAM
Authors: de Wolf Ingrid , Khaled Ahmad , Kim Soon-Wook , Kim Soon-Wook , Beyne Eric , Kögel Michael , Brand Sebastian , Djuric-Rissner Tatjana , Wiesler Ingo 
Published: December 2020

Abstract
This paper demonstrates the application of GHz-SAM for the detection of local non-bonded regions between micron-sized Cu-pads in a wafer-to-wafer hybrid bonded sample. GHz-SAM is currently the only available non-destructive failure analysis technique that can offer this information on wafer level scale, with such high resolution.
Non-Destructive Visualization of Bond Pad Defects using Acoustic Microscopy in the GHz-Band
Authors: Brand Sebastian , Kögel Michael , Altmann Frank , Oberhoff Stefan , Wiedenmann Michael , Krinke Jörg , Bosch Robert 
Published: December 2020

Abstract
GHz scanning acoustic microscopy (GHz-SAM) was successfully applied for non-destructive evaluation of the integrity of back end of line (BEOL) stacks located underneath wire-bond pads. The current study investigated two sample types of different IC processes. Realistic bonding defects were artificially induced into samples and the sensitivity of the acoustic GHz-microscope towards defects in BEOL systems was studied. Due to the low penetration depth in the acoustic GHz regime, a specific sample preparation was conducted in order to provide access to the region of interest. However, the preparation stopped several microns above the interfaces of interest, thus avoiding preparation artifacts in the critical region. Cratering related cracks in the bond pads have been imaged clearly by GHz-SAM. The morphology of the visualized defects corresponded well with the results obtained by a chemical cratering test. Moreover, delamination defects at the interface between ball and pad metallization were detected and successfully identified. The current paper demonstrates non-destructive inspection for bond-pad cratering and ball-bond delamination using highly focused acoustic waves in the GHz-band and thus illustrates the analysis of micron-sized defects in BEOL layer structures that are related to wire bonding or test needle imprints.
EBAC Analysis with Chemically Enhanced FIB Milling Assists Technique on Large Kerf/PCM Test Structure
Authors: Yap H.H. , Oh C.K. 
Published: December 2020

Abstract
The ability to expose a huge kerf/PCM (Process Control Monitor) test structure at the same level is limited from top down finger polishing. Also, in Scanning Electron Microscopy (SEM) the electron beam (e-beam) shift for electron beam absorbed current (EBAC) analysis is not able to cover the whole structure. The recently implemented technique described herein combines the focus ion beam (FIB) chemical enhanced milling method with EBAC analysis to stop the polishing at the upper layer and split the EBAC analysis into portions from the test structure. These help to improve the area of interest (AOI) evenness and enable the extension of the EBAC analysis.
Localization of Electrically Active Extended Defects in GaN Using a DualBeam FIB
Authors: Nshanian T. , Tracy B. , Ho H. 
Published: December 2020

Abstract
The Dual Focused Ion Beam (DFIB has been used to expose electrical fields associated with the charge of electrically active extended defects (ED) – (e.g. threading dislocations - TDs) in GaN structures. The localized electrical fields above electrically active defects in piezoelectric materials are shown to capture sputtered low energy ions, turning them back toward the surface and redepositing them on top of defects (TDs), forming Gallium-rich islands. This “Ga droplet” decorates EDs and significantly simplifies the process of locating EDs for TEM sample preparation and analyses. The size and shape of the Ga islands is correlated with the accumulated piezoelectric charge density at the EDs.
Analysis of Induced End-of-Life Failures in SRAM Through Nanoprobing
Authors: Dixon-Luinenburg Oberon , Fine Jordan 
Published: December 2020

Abstract
In this paper, we demonstrate a novel nanoprobing approach to establish cause-and-effect relationships between voltage stress and end-of-life performance loss and failure in SRAM cells. A Hyperion II Atomic Force nanoProber was used to examine degradation for five 6T cells on an Intel 14 nm processor. Ten minutes of asymmetrically applied stress at VDD=2 V was used to simulate a ‘0’ bit state held for a long period, subjecting each pullup and pulldown to either VDS or VGS stress. Resultant degradation caused read and hold margins to be reduced by 20% and 5% respectively for the ‘1’ state and 5% and 2% respectively for the ‘0’ state. ION was also reduced, for pulldown and pullup respectively, by 4.5% and 5.4% following VGS stress and 2.6% and 33.8% following VDS stress. Negative read margin failures, soft errors, and read time failures all become more prevalent with these aging symptoms whereas write stability is improved. This new approach enables highly specific root cause analysis and failure prediction for end-of-life in functional on-product SRAM.
Special Sample Preparation Methodology for Cu Pillar Bump Characterization on Advance Thin Small Leadless Flip Chip with Copper Pillar Bump Interconnect Technology
Authors: Yen Gwee Hoon , Heng Chong Hock 
Published: December 2020

Abstract
Today, copper pillar bumping now in high volume production for mobile electronics is also a transformative technology for next generation flip chip [1] interconnects which offers advantages in many designs while meeting current and future requirements. With the continuous shrinking dimensions of semiconductor devices, the package’s design and size are approaching the dimensions of the singulated die. Moreover, failure analysis involving copper pillar packages would be the major challenges faced by analysts as copper pillar devices in nature hides its solder joints beneath its die causing obstruction in quality inspection as well as judging its solder joint strength. Chemical wet etch or deprocessing [2] by using potassium hydroxide (KOH) to remove all silicon die have disadvantages of over etching on silicon substrate and tin (Sn) surrounding the Cu pillar. Therefore, quality of sample preparation is critical and new methodology is needed.
Modern 2D & 3D X-ray Technologies for Testing and Failure Analysis
Authors: Villaraga-Gómez Herminso , Bell Joshua D. 
Published: December 2020

Abstract
Modern 2D and 3D X-ray technologies are among the most useful non-destructive testing methods that enable the inspection of an object's internal features without cutting or disassembling the sample. This paper discusses the basic operating principle, advantages, and disadvantages of 2D and 3D X-ray based approaches for testing and failure analysis and describes how these different methods have practical application for failure analysis and dimensional metrology. The techniques discussed are radiography, classical laminography, computed tomography, and computed laminography.
Machine Learning Assisted Signal Analysis in Acoustic Microscopy for Non-Destructive Defect Identification
Authors: Kögel Michael , Brand Sebastian , Altmann Frank 
Published: December 2020

Abstract
Signal processing and data interpretation in scanning acoustic microscopy is often challenging and based on the subjective decisions of the operator, making the defect classification results prone to human error. The aim of this work was to combine unsupervised and supervised machine learning techniques for feature extraction and image segmentation that allows automated classification and predictive failure analysis on scanning acoustic microscopy (SAM) data. In the first part, conspicuous signal components of the time-domain echo signals and their weighting matrices are extracted using independent component analysis. The applicability was shown by the assisted separation of signal patterns to intact and defective bumps from a dataset of a CPU-device manufactured in flip-chip technology. The high success-rate was verified by physical cross-sectioning and high-resolution imaging. In the second part, the before mentioned signal separation was employed to generate a labeled dataset for training and finetuning of a classification model based on a one-dimensional convolutional neural network. The learning model was sensitive to critical features of the given task without human intervention for classification between intact bumps, defective bumps and background. This approach was evaluated on two individual test samples that contained multiple defects in the solder bumps and has been verified by physical inspection. The verification of the classification model reached an accuracy of more than 97% and was successfully applied to an unknown sample which demonstrates the high potential of machine learning concepts for further developments in assisted failure analysis.
Contact Leakage Failure Analysis by EBIC, C-AFM and Nano-probing
Authors: Ho Kuang-Tse , Wu Chien-Wei , Chang Te-Fu , Yen Chia-Hsiang , Chan Ching-Hsiang 
Published: December 2020

Abstract
This research sets up failure analysis flow to verify failure mechanisms and root causes of different kinds of contact leakage. This flow mainly uses EBIC, C-AFM and nano-probing to do fault isolation and confirm electrical failure mechanisms. Appropriate sample preparation is also mandatory for FIB, SEM and TEM inspection.
Thermal Failure Analysis of Functional Failures by IR Lock-in Thermal Emission
Authors: Llamera Paul Hubert P. , Garcia-Awitan Camille Joyce G. 
Published: December 2020

Abstract
Lock-in thermography (LIT), known as a powerful nondestructive fault localization technique, can also be used for microscopic failure analysis of integrated circuits (ICs). The dynamic characteristic of LIT in terms of measurement, imaging and sensitivity, is a distinct advantage compared to other thermal fault localization methods as well as other fault isolation techniques like emission microscopy. In this study, LIT is utilized for failure localization of units exhibiting functional failure. Results showed that LIT was able to point defects with emissions in the mid-wave infra-red (MWIR) range that Photo Emission Microscopy (PEM) with near infrared (NIR) to short- wave infra-red (SWIR) detection wavelength sensitivity cannot to detect.
MBIST Driven SRAM Failure Analysis Using Laser Voltage Imaging and Laser Voltage Probing
Authors: Yang Jessica , Rengaraj Omprakash , Gupta Puneet , Schlangen Rudolf 
Published: December 2020

Abstract
Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on &lt;14 nm advanced process silicon.
A New Approach to IDDQ Failure Fault Localization Using Single Shot Logic (SSL) Patterns
Authors: Estores Rommel , Verleye Stefaan 
Published: December 2020

Abstract
In this paper the authors will discuss an application of Single Shot Logic (SSL) patterns used for further localizing IDDQ failures using ATPG constraints and targeted faults. This new method provides the analyst a possibility of performing circuit analysis using IDDQ measurement results as a pass/fail criterion rather than logic mismatches. Once a defective area was partially isolated through fault localization, SSL patterns were created to control individual internal node logic states in a deterministic way. IDDQ was measured at each SSL iteration where schematic analysis can further isolate the failure to a specific location. Two case studies will be discussed to show how this technique was used on actual failing units, with detailed explanation of the steps performed that led to a more precise determination of the fault location in the suspect cell.
Applying a Significant Protection Layer on Double Ex Situ Lift-out TEM Specimens to Protect Against Ion Beam Impact
Authors: Lin Chun-Hung , Hsu Hsin-Cheng , Lin Tsung-Yi , Lin Ru-Hui , Chen I-An , Hsu Pei-Lin , Chen Chao-Kun , Hsieh Iris , Yeh Chin-Chih , Lian Nan-Tzu , Yang Ta-Hone , Chen Kuang-Chao 
Published: December 2020

Abstract
Protection layers on double ex situ lift-out TEM specimens were investigate in this paper and two protection layer approaches for double INLO or double EXLO were introduced. The improved protection methods greatly decreased the damage layer on the top surface from 90 nm to 5 nm (or lower) during FIB milling. According to the property of different sample and its preliminary treatment in the FIB, we have the satisfactory approaches to be applied. Using this improved protection method, we demonstrate the structures within the TEM lamella can be observed without ion beam damage/implantation during FIB
Development of a Characterization Workflow for Reliable Porous Copper Films using SEM-FIB Tomography and Advanced Image Analysis
Authors: Wijaya Andi , Rosc Jördis , Sartory Bernhard , Brunner Roland , Eichinger Barbara , Mischitz Martin 
Published: December 2020

Abstract
The development of a characterization workflow for reliable pore characterization of porous metals especially for microelectronics applications is very important. This will help to provide design guidelines for the production and for the improved reliability of the devices. In this paper, we set up a workflow to accurately evaluate the porosity, of four different porous copper materials. The porous thin films are fabricated by using stencil printing. Within the workflow we use for the measurement non-destructive micro-X-ray computed tomography (ƒÝ-XCT) and destructive high-resolution scanning electron focused ion beam nano-tomography (nano-FIB tomography). The latter will be also used to calibrate the threshold for the ƒÝ-XCT image data, since a direct evaluation of the porosity from the non-destructively obtained ƒÝ-XCT image data due to resolution and contrast is not possible. Therefore, we develop an indirect histogram based evaluation method to get the porosity of the porous copper thin films. We validate and discuss the obtained results with respect to further studies.
New Paradigm for EBIC Amplifier on FIB X-section
Authors: Sanna Valle Valerio , Perez Guy , Bascoul Guillaume , Chauvin Helene , Viallet Benoît , Mura Giovanna , Apeddu Gian Paolo 
Published: December 2020

Abstract
Electron Beam Induced Current is a powerful tool for Scanning Electron Microscopy (SEM) imaging mode. In this paper, the history and evolution of this technique are discussed. Some important defects are presented as well as their technological interpretation. A new custom amplifier is presented and its implementation in Time Resolved EBIC (TREBIC) is also proposed, the main differences with EBIC are pointed out.
Capacitance Characterization of Gate to LDD Overlap Region to Understand Subtle Fail Modes in Advanced Node Technologies
Authors: Kodali Satish , Banghart Edmund , Davidson Kevin , Zhang Yu , Singh Jagar , Oh Chong Khiam 
Published: December 2020

Abstract
This paper demonstrates capacitance-voltage (CV) measurements using Nanoprobing to characterize different fails and better understand the defect mode. Three case studies are conducted using the CV technique. DC Nanoprobing measurements are first used to identify the failure mode. Subsequently, CV measurements are employed to further narrow down the root cause, to understand the process mechanism leading to the failure. A pathway to use the CV technique to isolate defects with-in a device under test is also demonstrated. It has been shown that the gate to lightly doped drain CV measurements will be a very useful characterization tool to understand various fail modes. This finding, along with DC measurement, serves to narrow the issue primarily to gate stack work function related matters.