bluuebunny/crossref_metadata_2025_split huggingface dataset:
Focused Ion Beam Induced Effects on MOS Transistor Parameters
Authors: Campbell Ann N. , Tangyunyong Paiboon , Jessing Jeffrey R. , Hembree Charles E. , Fleetwood Daniel M. , Swanson Scot E. , Soden Jerry M. , Antoniou Nicholas , Vanderlinde William E. , Abramo Marsha T. 
Published: December 2020

Abstract
We report on recent studies of the effects of 50 keV focused ion beam (FIB) exposure on MOS transistors. We demonstrate that the changes in transistor parameters (such as threshold voltage, Vt) are essentially the same for exposure to a Ga+ ion beam at 30 and 50 keV under the same exposure conditions. We characterize the effects of FIB exposure on test transistors fabricated in both 0.5 μm and 0.225 μm technologies from two different vendors. We report on the effectiveness of overlying metal layers in screening MOS transistors from FIB-induced damage and examine the importance of ion dose rate and the physical dimensions of the exposed area.
Relay Failures Specific to Space Applications
Authors: Teverovsky Alexander 
Published: December 2020

Abstract
Low-pressure conditions, as experienced in space applications, are considered benign for many electronic components. However, for switching devices the probability of failure may be significantly greater than at normal atmospheric pressure due to arcing-at-break processes. This study was stimulated by a relay failure in a 60-V power bus in a spacecraft module, and it was intended to analyze failure modes and the probability of their occurring under lowpressure conditions. The effects of gas pressure, power bus voltage, and load current on arc duration and probability of arc flashover have been investigated. It was shown that arc duration mostly depends on switching power and gas pressure, significantly increasing when power is rising and pressure is decreasing. Failure analysis indicated two major mechanisms in low-pressure conditions: (1) contact damage (excessive erosion and/or microwelding) and (2) arc flashover to a grounded case and/or grounded coil post. For a relay operating in a vacuum, the effect of leak rate on the time to failure at low-pressure conditions is discussed.
Characterization of Gold Embrittlement in Solder Joints
Authors: Bunis Carl B. 
Published: December 2020

Abstract
Mechanical strength, integrity, and reliability of solder connections used in the microelectronics industry are important factors in overall quality and reliability of the finished product. In most cases tin (Sn) rich solders are attached to a base metal plated with nickel (Ni) and then with gold (Au). Formation of AuSn4 intermetallics in the solder may result in loss of more than 80% of the initial impact toughness, resulting in loss of reliability of the connection. Gold (Au) embrittlement is a major concern in tin/lead (Sn/Pb) soldering or any other joining process with Au and Sn as major constituents. Noncompliance to Au plating-thickness specifications by vendors or insufficient Sn wicking of Au surfaces can result in embrittled joints and unreliable parts.
Die Backside FIB Preparation for Identification and Characterization of Metal Voids
Authors: Campbell Ann N. , Filter William F. , Antoniou Nicholas 
Published: December 2020

Abstract
Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.
Identification of Subtle Isb Failure Mechanisms
Authors: Wang N. , Zou R. , Wu J. , Daniel S. , Stevenson W. 
Published: December 2020

Abstract
Reliability of low standby current (Isb) CMOS circuits is impacted by extremely small non-fault resistive defects which, without compromising logic functionality or timing specifications, cause Isb currents well in excess of device specifications. A primary cause of high Isb, identified through failure analysis, is due to Crystal Originated Pits (COPs) defects, whereat thin oxide is more prone to electrical breakdown.
BGA and Advanced Package Wire to Wire Bonding for Backside Emission Microscopy
Authors: Colvin Jim B. 
Published: December 2020

Abstract
A new method of preparation will be shown which allows traditional fixturing such as test heads and probe stations to be utilized in a normal test mode. No inverted boards cabled to a tester are needed since the die remains in its original package and is polished and rebonded to a new package carrier with the polished side facing upward. A simple pin reassignment is all that is needed to correct the reverse wire sequence after wire to wire bonding or wire to frame bonding in the new package frame. The resulting orientation eliminates many of the problems of backside microscopy since the resulting package orientation is now frontside. The low profile as a result of this technique allows short working distance objectives such as immersion lenses to be used across the die surface. Test equipment can be used in conjunction with analytical tools such as the emission microscope or focused ion beam due to the upright orientation of the polished backside silicon. The relationship between silicon thickness and transmission for various wavelengths of light will be shown. This preparation technique is applicable to advanced packaging methods and has the potential to become part of future assembly processes.
Measurement of Interfacial Adhesion and its Degradation in Multi-Layer Packages, Devices, and Blanket Films Using the Laser Spallation Technique
Authors: Gupta Vijay , Hernandez Robert , Dias Rajen , Atluri Vasudeva , Raiser George , Mello Mike , Skoglund Lars , Zimmerman Paul 
Published: December 2020

Abstract
A laser spallation technique to measure the tensile strength of thin film interfaces is introduced. In this technique, a laser-generated stress wave of nanosecond duration in the substrate spalls off (completely removes) a coating deposited on the substrate’s front surface. The threshold laser energy is converted into the tensile stress (strength) at the failure site (usually the interface) by using an optical interferometer. Because of the ultra-short duration of the stress wave loading, all plastic deformation processes that usually accompany the coating decohesion event are suppressed such that the measured value can be regarded as fundamental or intrinsic to the material system (including the defects, if any). Application of this technique to test planar as well geometrically heterogeneous interfaces in IC’s, substrates, and packages is demonstrated. The technique is used to quantify the degrading effects of moisture and in-situ temperature rise on the tensile strength of a polyimide/Si3N4/Si interface system whose strength was systematically degraded by exposing the samples to controlled humidity (50-70% RH) conditions for varying duration (12-96 hrs) and temperatures (30°C-150°C). These measurements of strength degradation can now be used to predict device reliability from a fundamental standpoint in conjunction with simulations capable of predicting time-dependent stress concentrations, moisture accumulation, and temperature rise at critical interfaces during processing and service environment in actual systems.
New FIB-Supported Approach for Wire-Bondpad Characterization
Authors: Jacob Peter , Nicoletti Giovanni 
Published: December 2020

Abstract
Bond pad characterization is usually performed by mechanical cross-sectioning as well as pull and shear tests. However, since all these methods apply mechanical forces to the bond pad, artifacts may result. Focused Ion Beam (FIB) characterization is a mechanically stress-free characterization method, which allows more accurate conclusions regarding the intermetallic behaviour of the bonding area. Some new approaches presented here show how to improve the FIB characterization procedure and to combine it with classical characterization methods.
In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results
Authors: Segal Julie , Sagatelian Arman , Hodgkins Bob , Ho Tom , Chu Ben , Singh Tony , Berman Harvey 
Published: December 2020

Abstract
Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.
Failure Analysis from the Backside of a Die
Authors: Liebert Silke 
Published: December 2020

Abstract
A back side failure analysis flow has been developed in order to enable failure analysis of flip-chip, lead-on-chip dies and within multi-metal-level dies. A combination with frontside failure analysis methods is possible too. The back side flow consists of stepwise bulk silicon removal, electrical and physical failure analysis methods. Four different methods for bulk silicon thinning in order to localize electrical defects using PEM are compared. A method to remove the bulk silicon after PEM analysis to expose the gate oxide level of a die has been developed. Different back side applications like physical analysis of gate oxide defects, passive voltage contrast and microprobing with an AFM tip for detection of interrupts within conductive interconnects are described.
Evaluation of On-Chip ESD Supply Clamp Robustness by In-Situ Floating Power Bus Monitoring
Authors: Fliesler Michael , Morgan Ian H. 
Published: December 2020

Abstract
Continuous improvements over time to a CMOS Flash Memory technology resulted in significant improvement in Human Body Model (HBM) ESD immunity for “I/O’s” to Vcc power supply and Vss ground pins. Remaining low level failure modes in the die core included elevated standby current that in some cases could not be localized even with extensive chip de-processing. In addition an apparent functional failure upon post stress ATE test was isolated for certain part revisions. Routine separation of Vss/Vcc supply pin combinations from “all other pins” during HBM ESD test allowed identification of the several failures occurring in the die core. Failure analysis and corrective action is described. Additional diagnostic testing using separate polarity HBM pulses aided in tracing the conduction path causing the apparent functional failure and prompted investigation of HBM tester dynamic properties. It was determined that the magnitude of the “second” HBM pulse in certain testers was sufficient to cause a false powerup condition which results in apparent functional failure upon subsequent ATE test. In-situ monitoring of the Floating Power Bus response (in this case Vss) during application of HBM stress to the Input-pad to Vcc-pin combination revealed a transient caused by the “second” pulse that allowed such apparent failures to be invalidated. Further more, monitoring the in-situ floating Vss bus response to the HBM allowed conclusions to be drawn as to the utility of different power bus and Vss/Vcc supply clamp layouts, thereby allowing improvements to die layout to be implemented.
Transmission Line Pulse Testing of the ESD Protection Structures in ICs – A Failure Analyst’s Perspective
Authors: Henry Leo G. , Barth Jon , Richner John , Verhaege Koen 
Published: December 2020

Abstract
The IC industry continues to find ways to improve the ability to correlate the electrical failure signature of devices with the physical failure location using different techniques. The purpose of this work is to show that improved transmission line pulse (TLP) testing technique of ESD (ElectroStatic Discharge) protection structures can provide accurate identification of leakage current to better identify where ESD stress testing should stop and failure analysis should begin. Besides the traditional current and voltage measurements at the Device Under Test (DUT), this new TLP testing technique includes the ability to correct for the measurement system losses for improved accuracy. The pulse width of the TLP is chosen to provide the same current amplitude damage level (electrical) as is found in the Human Body Model (HBM) ESD stress testing. This allows a one to one correlation between the two methods and hence the means to correlate the electrical damage of the device and the physical location of the failure site. An SCR (Silicon Controlled Rectifier) device is used as an example.
Thermal Fatigue Induced Voiding in LDMOS Transistors Submitted to Multiple Energy Discharges
Authors: Percheron-Garcon I. , Bosc J.M. , Levade C. , Cabié M. , Vanderschaeve G. 
Published: December 2020

Abstract
The repetitive energy discharge test (power cycling) is an accelerated stress test (AST) that can be used to characterize the long-term behavior of power transistors taking into account stress on customer final application. This paper describes the application of this test to an LDMOS transistor in order to optimize both design and size while preserving final reliability of the product. We will detail this reliability characterization program, emphasizing the power cycling tests performed in extreme conditions in order to reach and study physical limit of LDMOS devices. Analysis of LDMOS devices under these extreme conditions indicated evidence of metal voiding: the conditions of formation of these thermal fatigue induced voids will be discussed. The effect of major parameters like power cycling energy, ambient temperature will also be discussed. Electrical characterization of stressed devices will be presented. Finally, the results of the Transmission Electron Microscopy characterization of the metal microstructure will be discussed.
Contrast Inversions in Scanning Acoustic Microscopy (C-SAM) of Glue Die-Attach
Authors: Plikat Boris 
Published: December 2020

Abstract
The quality of the die attach is crucial for almost all power devices, as in most cases thermal and electrical transport is vertical through the die and its backside. For glue inspection, C-SAM through the lead frame is widely used. Ordinarily, one of the three following states of delamination is found: (A) no delamination, (B) delamination at the die, or (C) delamination at the lead frame. A general rule for the assignment of the brightness in C-SAM amplitude images to these states of delamination cannot be given. This is evidenced by contrast inversions observed with frequency variation of the applied ultrasound or variation of the glue thickness. Contrast inversions at images through the lead frame occur between areas of states (A) and (B). The calculation of ultrasonic echoes for a three-layer model (copper, glue, silicon) shows that the contrast inversions are connected to the first resonance of the glue in state (B). Here complicated shapes of the echoes are found in experiments and calculations, which helps to correctly assign brightness levels to delamination states. Additionally a flow for reliable glue investigation with the use of through-transmission SAM inspection is proposed.
Focused Ion Beam Analysis of Low-K Dielectrics
Authors: Bender H. J. , Donaton R. A. 
Published: December 2020

Abstract
The characteristics of an organic low-k dielectric during investigation by focused ion beam (FIB) are discussed for the different FIB application modes: cross-section imaging, specimen preparation for transmission electron microscopy, and via milling for device modification. It is shown that the material is more stable under the ion beam than under the electron beam in the scanning electron microscope (SEM) or in the transmission electron microscope (TEM). The milling of the material by H2O vapor assistance is strongly enhanced. Also by applying XeF2 etching an enhanced milling rate can be obtained so that both the polymer layer and the intermediate oxides can be etched in a single step.
Temperature Distributions in III-V and SiC Micro-Wave Power Transistors Using Spatially Resolved Photoluminescence and Raman-Spectrometry Mapping Respectively
Authors: Martin P. , Bisaro R. , Dua C. , Noblanc O. , Delage S. L. , Floriot D. , Lemaire F. , Galtier P. , Landesman J. P. , Brylinski C. 
Published: December 2020

Abstract
This paper describes a new method for the mapping of local temperatures in the active region of highpower III-V semiconductor transistors for microwave applications. The measurement technique involves scanning a focused laser beam at the surface of a chip inside its package, while the photoluminescence (PL) or the Raman spectra produced are recorded sequentially for each position of the laser beam. The local temperature is deduced either from the corresponding wavelength shift of the PL (which represents changes in the band-gap due to heating) or from Raman Stokes peak shift or from the Stokes to anti-Stokes intensity ratio (which correspond to changes in optical phonon frequencies and population respectively due to heating). Results are shown both for SiC-based field effect transistors and for bipolar type transistors (heterojunction bipolar transistors – HBTs – in the GaAs/Ga1-xInxP system). A spatial resolution of 1 µm and an accuracy in the temperature determination of ± 3 °C are demonstrated, especially for the HBTs. Finally, procedures are proposed to implement the information on local operating temperatures provided by this method into thermal resistance calculations.
New Laser Ablation Method for Non-Destructive Backside Sample Preparation
Authors: Beaudoin F. , Perdu P. , Saviot F. , Lewis D. , Salin F. 
Published: December 2020

Abstract
A new ultra-short pulse laser ablation based backside sample preparation method has been developed. This technique is contact-less, non-thermal, precise, repetitive and adapted to each type of material present in IC packages. Backside preparation examples are presented on a conventional DIL plastic package, on a TSOP plastic package with an oversized silicon die, on a DIL ceramic package and on a CCD device. Feasibility of silicon thinning using laser ablation is also discussed.
Intel® Component Diagnostic Technology: Tools and Education for Intel Component Defect Reduction
Authors: Doll Julie S. 
Published: December 2020

Abstract
To enable efficient, accurate debug of Intel architecture components to take place within contract manufacturing sites, and to provide alternatives for the removal of Intel components from, Intel is deploying a diagnostic capability and attendant educational collateral known as to achieve these objectives Intel® Component Diagnostic Technology. This paper will describe details of Intel® Component Diagnostic Technology, including the diagnostic fixture and user interface, diagnostic scripts and analytical coverage, data management and reporting, and on-site and Web-based educational offerings.
Identification and Characterization of Ultra-Thin (&lt;100 nm) Flakes Using a Combination of Face-Lapping, High Energy (10 kV) SEM Imaging, and TEM
Authors: Mitro D. , Subramanian S. , Yeung S. (Wai Lung) , Chrastecky T. , Hagedorn B. , Widener E. 
Published: December 2020

Abstract
Ultra-thin (&lt;100 nm) flakes shorting metal lines are difficult to detect and often cause the device to fail after reliability stress or at the customer site. In most cases, the common technique of inspecting the device in an optical microscope followed by conventional low energy (&lt;3.0 kV) scanning electron microscopy (SEM) is often not able to detect this type of defect. In rare cases, where the defect is successfully exposed by the traditional procedure, it is very challenging to perform additional transmission electron microscopy (TEM) characterization of the defect without introducing arifacts during sample preparation of the exposed flake. A new procedure to identify these defects using a combination of face-lapping and high energy (&gt;10 kV) SEM imaging is described in this paper. In this method, the failing device is carefully face-lapped and inspected frequently using a high energy (&gt;10 kV) scanning electron beam. The high energy electron beam penetrates through the oxide layer and detects features embedded below the oxide. This technique greatly incresases the chances of detecting the flake, as the method is capable of detecting the defect at a larger range of oxide thickness as opposed to the traditional method. Additionally, TEM results were improved when the ultra-thin flakes were detected below the surface with the high energy SEM technique. Several examples of ultra-thin flakes found using the high energy SEM vs. low energy SEM will be presented.
Classification of IC Process Deformation Characteristics Using Memory Fail Bitmaps
Authors: Zanon T. , Maly W. 
Published: December 2020

Abstract
Building a portfolio of deformations is the key step for building better defect models for the test and yield learning domain. A viable approach to achieve this goal is through geometric characterization and classification of failure patterns found on memory fail bitmaps. In this paper, we present preliminary results on how to build such a portfolio of deformations for an IC technology of interest based on a fail bitmap analysis study conducted on large, modern SRAM memory products.
Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology
Authors: Wu Huixian , Cargo James , Wu Huixian , White Marvin 
Published: December 2020

Abstract
The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.