Temperature-Dependent and Dielectric Relaxation of Porous Silicon Prepared by Electrochemical Etching
Authors: Fonthal Rico Faruk , Oliveros Edward Steven , Chavarria Mario 
Published: February 2020

In the electronic devices based on porous silicon (PS) is important understand the physical mechanisms governing the electrical behaviour in the PS/c-Si structure. In order to investigate the conduction mechanisms in the PS/p-Si heterojunction, we prepared the PS by electrochemical etching. The temperature dependence of the porous silicon was studied in the range from 240 K to 320 K. On the other hand, the AC electrical measurements were performed from 101 to 107 Hz in a range of 0,7 to 1,2 V, at room temperature. The calculated activation energies were close to 0,90 eV. The physical mechanisms involved in the Ag/porous silicon contacts and porous silicon/p-Si interface can be obtained from the voltage dependence of the fitting parameters according to electrical model circuits in DC and AC. We found the dielectric behavior of the samples; the relaxation region is presented at high frequency and at low temperatures resulting in a long dielectric relaxation time.
The best known metalloid element for semiconductor manufacturing is the chemical element silicon; technologies based on this element are present in our daily lives, but silicon has its limitations. In crystalline form, it is not considered useful as magnetic, biomedical, or optical material. Thereby, this is where development and research for this material are important. Porous silicon has attracted much attention because of its low dimensional semiconductor structure. Since the first work by Koshida et al. [1] there have been published several papers dedicated to the DC and AC electrical characterization of porous silicon layers [2-4]. The electrical properties of these devices are strongly dependent not only on the properties of porous silicon, also on the quality of the metal/PS or PS/Si interfaces [5-7]. AC impedance analysis is a powerful tool and has been widely used to analyze the electrical performance of both metal-semiconductor junctions and p-n junctions [1,5]. The analysis of the frequency-capacitance-voltage characteristics present in an ideal abrupt junction has to be studied to understand the three capacitances effects in the heterojunction PS/c-Si as Low-Frequency Dispersion phenomenon (LFD), depletion capacitance (Cdep) and geometric capacitance (C0) [7]. An important aspect in these structures is the electrical contacts analysis on the PS layer and what is the dependence behavior when the voltage and temperature is variable [4]. Various authors have been reported different mechanism, Schottky junctions due to the metal contact [8], the Ohmic conduction is dominated by the bulk resistance [9] and the power law Space Charge Limit Current (SCLC) [7].
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