bluuebunny/crossref_metadata_2025_split huggingface dataset:
Marginal Failure Diagnosed with LADA—Case Studies
Authors: Lee Sukho , Kim Keonil , Lee Yunwoo , Lee Euncheol , Kim Yojoung , Kapilevich Izak 
Published: December 2020

Abstract
During the early stage of process development, the major activities are yield ramp up with DFT test such as Memory BIST and SCAN test. There are plenty of commercial and inhouse diagnostics tools for DFT so in case of failure FA procedures are rather simple and standardized: run EDA tool, get fail location, perform pFA then feedback to process engineering. However in the case of marginal failure FA procedures are generally more complicated. FA engineer should consider many different scenarios to find the root cause. The marginal voltage fail is caused by many different reasons. The analysis of marginal fail is of course very important to screen out healthy devices and detect any problem of process technology or design methodology. In this paper, the authors deal with three marginal voltage fail case studies: scan chain fail, digital function fail and analog function fail. Throughout these case studies, LADA was successfully used to define the fault location. The reason of device alteration was well explained with further study. It is obvious that LADA is a very effective way to analyze marginal failures in cases where the FA engineer doesn’t have much design information because the results are very intuitive and clear. There is little doubt of LADA results accuracy because LADA is utilizing the tester to make an accurate Pass/Fail decision. LADA results are direct indication of device sensitivity to parametric changes, in our case voltage margin.
Metal Bridge Defects Localization by a Tiny Leakage between One of Bridged Signals and VDD (GND)
Authors: Wu Chunlei , Yao Suying 
Published: December 2020

Abstract
As semiconductor technology continues to advance to smaller dimensions and more complex circuit designs, it is becoming more challenging to locate the resistive short directly between two metal lines (signals) due to a metal bridge defect. Especially these two metal lines are very long and relevant to many functional modules. After studying the failed circuit model, we found there should be a tiny leakage between one of the bridged signals and one of common power signals (such as VDD and GND) on a failed IC compared with the reference one, if there is a metal bridge defect between these two bridged signals. The tiny leakage between one of the bridged signals and one of power signals is an indirect leakage that is a mapping of the direct resistive short between these two bridged signals. The metal bridge defect could be pinpointed with the tiny leakage between one of the bridged signals and one of power signals by Lock-in IR-OBIRCH. It is an easier and faster way to locate the metal bridge defects. In this paper, the basic and simple circuit model with a metal bridge defect will be presented and two cases will be studied to demonstrate how to localize a metal bridge defect by the tiny leakage between one of the bridged signals and one of power signals.
Quantitative Analysis of Heterogeneous Materials by SEM/EDS by Use of Rapid Phase Decomposition
Authors: Konopka John 
Published: December 2020

Abstract
Algorithms for quantification by SEM/EDS always specify that the material being analyzed should be homogeneous. Every instruction on analysis by SEM/EDS warns against analyzing heterogeneous samples. However, in day-to-day analysis, it is extremely common to encounter samples which are heterogeneous and these samples must be analyzed. It is very common for an analyst to simply scan an entire field of view in the SEM, acquire an x-ray spectrum from this field of view, press the button for standardless quantification, and hope for the best. This work explores the magnitude of this problem and characterizes it with measurements. A solution is then proposed for performing this kind of analysis. The results of analyses of multiple areas showed larger variations than the variation between the area-weighted and gross spectrum calculations. The results obtained were consistent with the nominal bulk concentrations for homogeneous materials.
Temperature-Dependent Logic Failure in a GaAs Power Amplifier-Duplexer Module Caused by a Subtle Parasitic Schottky Diode
Authors: Emergo Rose , Brockett Steve , Hamilton Pat 
Published: December 2020

Abstract
A single power amplifier-duplexer device was submitted by a customer for analysis. The device was initially considered passing when tested against the production test. However, further electrical testing suggested that the device was stuck in a single power mode for a particular frequency band at cold temperatures only. This paper outlines the systematic isolation of a parasitic Schottky diode formed by a base contactcollector punch through process defect that pulled down the input of a NOR gate leading to the incorrect logic state. Note that this parasitic Schottky diode is parallel to the basecollector junction. It was observed that the logic failure only manifested at colder temperatures because the base contact only slightly diffused into the collector layer. Since the difference in the turn-on voltages between the base-collector junction and the parasitic Schottky diode increases with decreasing temperature, the effect of the parasitic diode is only noticeable at lower temperatures.
A Novel Method for the Specified Site Planar View TEM Sample Preparation
Authors: Duan Shuqing , Zhao Yanli , Li Ming 
Published: December 2020

Abstract
This paper reports a novel method for site specific plan view transmission electron microscopy (TEM) sample preparation. The detailed procedure is introduced step by step. To demonstrate the practicality of this technique in failure analysis, case studies on 45nm and below technology nodes using the novel method are reported. The results showed that the method is very useful for the analysis of the specified failure location and is helpful to improve the success rate of failure analysis.
Tri-Directional TEM Failure Analysis on Sample Prepared by In-Situ Lift-Out FIB and Flipstage
Authors: Zhu Jie , Du An Yan , Liu Bing Hai , Er Eddie , Zhao Si Ping , Lam Jeffrey 
Published: December 2020

Abstract
In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.
Cross-Section Sample Preparation Method for Imaging Dopant Related Anomalies Using Scanning Probe Microscopy Techniques
Authors: Subramanian Swaminathan , Ly Khiem , Chrastecky Tony 
Published: December 2020

Abstract
Visualization of dopant related anomalies in integrated circuits is extremely challenging. Cleaving of the die may not be possible in practical failure analysis situations that require extensive electrical fault isolation, where the failing die can be submitted of scanning probe microscopy analysis in various states such as partially depackaged die, backside thinned die, and so on. In advanced technologies, the circuit orientation in the wafer may not align with preferred crystallographic direction for cleaving the silicon or other substrates. In order to overcome these issues, a focused ion beam lift-out based approach for site-specific cross-section sample preparation is developed in this work. A directional mechanical polishing procedure to produce smooth damage-free surface for junction profiling is also implemented. Two failure analysis applications of the sample preparation method to visualize junction anomalies using scanning microwave microscopy are also discussed.
Soft Defect Localization on Analog and Mixed-Signal ICs Using an OBIRCH Tool
Authors: Wu Chunlei , Li Xiaocui , Che Yi 
Published: December 2020

Abstract
It is difficult to localize the soft defect on analog and mixed-signal ICs only by OBIRCH, because OBIRCH laser scanning module could not synchronize with the IC under functional test, and the failure modes on analog and mixed-signal ICs are complicated. In this paper, a dynamic synchronization method is proposed to localize the soft defect precisely only with an OBIRCH tool on analog and mixed-signal ICs. The methodology and system configuration are presented. A case is studied successfully on an analog and mixed-signal IC using this method.
Comparison of Photon and Thermal Emission Microscopy for Dynamic Fault Isolation
Authors: Goh S.H. , You G.F. , Tan Alan , Bharadwaj C.V. , Hao Hu , Yeoh B.L. , Lam Jeffrey 
Published: December 2020

Abstract
Unlike photon emission microscopy which is usually the first go-to technique in tester-based or dynamic electrical fault localization, infrared thermal microscopy does not play a similar routine role despite its comparable ease in application. While thermal emission lacks in optical resolution, we demonstrate superior sensitivity and accuracy over photon emission on dynamic fault localization of backend-of-line short defects.
Alleviating Sample Charging during FIB Operation
Authors: Liu Q. , Kor H.B. , Siah Y.W. , Gan C.L. 
Published: December 2020

Abstract
Dual-beam focused ion beam (DB-FIB) system is widely used in the semiconductor industry to prepare cross-sections and transmission electron microscopy (TEM) lamellae, modify semiconductor devices and verify layout. One of the factors that limits its success rate is sample charging, which is caused by a lack of conductive path to discharge the accumulated charges. In this paper, an approach using an insitu micromanipulator was investigated to alleviate the charging effects. With this approach, a simple front side semiconductor device modification was carried out and the corresponding stage current was monitored to correlate to the milling process.
An Infrared Microscope for Use on a Focused Ion Beam for Circuit Edit and Backside Edit Applications
Authors: Richards Alexander , Weschler Matthew , Durller Michael 
Published: December 2020

Abstract
To help solve the navigational problem, i.e., being able to successfully locate a circuit for probing or editing without destroying chip functionality, a near-infrared (NIR), near-ultraviolet (NUV), and visible spectrum camera system was developed that attaches to most focused ion beam (FIB) or scanning electron microscope vacuum chambers. This paper reviews the details of the design and implementation of the NIR/NUV camera system, as instantiated upon the FEI FIB 200, with a particular focus on its use for the visualization of buried structures, and also for non-destructive real time area of interest location and end point detection. It specifically considers the use of the micro-optical camera system for its benefit in assisting with frontside and backside circuit edit, as well as other typical FIB milling activities. The quality of the image obtained by the IR camera rivals or exceeds traditional optical based imaging microscopy techniques.
Analysis of Integrated Current Sense in Multiphase Buck Converters
Authors: Kearney Ian 
Published: December 2020

Abstract
Accurate and lossless current sensing is vital for high performance multiphase buck converters used in the latest voltage regulation modules (VRMs). A synchronous FET onstate resistance based approach is an alternative topology to DCR based sensing and is compatible with any controller, which requires inductor current information. The MOSFET driver has built-in sense circuitry, which when co-packaged with the MOSFETs reduces total footprint and ease of design. The Powerstage embodiment virtually eliminates the parasitic inductance and resistance between Control and Synchronous power MOSFETS; and using thick copper clips substantially reduce the parasitics associated with the input supply voltage (VIN) and the switch node output voltage (VSW) connections when compared to wire-bonded solutions. This paper presents a novel investigation into a contradictory low on-resistance paradox in a stacked 3D configuration. Through analysis, characterization and simulation the author deciphered the conundrum leading to a root cause explained by a mismatch of internal gain and referenced on-resistance. Building on previous metrology improvements the innovative insights drove analysis toward root-cause.
SIMS Quantitative Analysis and Optimization for Ion Implantation Angle Deviation
Authors: Shi JiangBei , Chien WeiTing , Zhang QiHua , Li AiMin , Liu ChuanJun 
Published: December 2020

Abstract
The accuracy of ion implantation is very important in semiconductor manufacturing and will directly affect the performance of the individual devices and even the whole chip. The deviations of ion implantation energy, dose and angle often result from abnormality of implant equipment or process design limit. The information of ion implantation energy, dose and angle can be qualitatively and quantitatively analyzed by SIMS (Secondary Ion Mass Spectrometry) [1], which provides a way to diagnose ion implanter issue. Based on SIMS analysis results, we can judge whether ion implanter meets the requirements and whether the process design achieves the expected goal. In this paper, we report a SIMS data analysis method determine the deviation of ion implantation angle. A term of deviation rate is defined and a related calculation method was introduced, which is proportional to the deviation angles of the ion implanter. Then, a statistical analysis on a large number of data of deviation rates and ion implantation angles showed that the sampling data followed normal distribution, and thus the corresponding 3 sigma could be obtained. Using the determined 3 sigma range of the deviation rates, we can define the acceptable range for deviation rate. Further, we can use the actual deviation rate to judge if the implant equipment needs maintenance or not, or suggest the direction for improvement. Finally, we set up an oriented and quantitative optimization method of angle deviation by the full mapping of SIMS depth profiles, which can directly set the relationship between the angle deviation and the adjustment parameters of ion implantation disk (Δ alpha, Δ beta). The equipment’s maintenance time and cost can thus be minimized. This method can be used as early detection to the abnormity of ion implant equipment.
Failure Analysis Induced by Bit Line Sense Amplifier Noise in High Density DRAM
Authors: Lee Myungjae , Ko Sanghoon , Bae Daegi , Hong Heeil , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung 
Published: December 2020

Abstract
The open bit line architecture scheme is an effective method to achieve higher density memory devices. With the scaling of DRAM, we have adopted a bit line sense amplifier (BLSA) design using a shared local power line for reducing the circuit layout dimensions. As a result of this new design, the write time of the memory cell was sometimes degraded because of an increase in initial sensing noise. This paper gives a detailed analysis of the problem caused by the initial sensing noise by examination of the behaviour of the opposite data portion of the cell array matrix when the word line is not activated. Finally, we propose a design improvement to reduce the magnitude of noise peaks and the results of this improvement when implemented in the test vehicle.
High Resolution Electron Beam Induced Resistance Change for Fault Isolation with 100 nm2 Localization
Authors: Buchea Brett A. , Butler Christopher S. , Ryu H.J. , Chuang Wen-hsien , von Haartman Martin , Tong Tom 
Published: December 2020

Abstract
A novel fault isolation technique, electron beam induced resistance change (EBIRCh), allows for the direct stimulation and localization of eBeam current sensitive defects with resolution of approximately 100nm square, continuing a history of beam based failure isolation methods. EBIRCh has been shown to work over a range of defects, significantly decreasing the time required for isolation of shorts through straightforward high resolution imagery, allowing for explicit visual defect isolation with a linear resolution of approximately 10nm. This paper discusses the operational setups for the source and amplifier while performing an EBIRCh scan, describes the processes involved in the Intel test vehicle that was used to test EBIRCh, and provides information on two independent functional theories for EBIRCh that operate in conjunction to a greater or lesser extent depending on the defect type. EBIRCh is expected to improve through-put and resolution on various defect types compared to conventional fault isolation techniques.
A Simple Method to Fabricate a Tunable In Situ SIL
Authors: Kimball Mark 
Published: December 2020

Abstract
The SIL is now an essential component of the modern FA lab. But the SIL has very specific requirements to produce good results: and the aplanatic SIL (or ASIL) has even more stringent requirements. In particular, it requires a very specific sample thickness, and a very flat surface. In addition, there are situations where a commercial SIL lens is not compatible with the requirements at hand. This paper describes a method for fabricating an in-situ SIL that can be adjusted for different sample thicknesses, using a combination of materials and techniques that are both readily available and easily learned. In contrast to diffractive lenses, our SILs are much more efficient with regard to delivering a focused laser beam to the spot of interest, and do not require the use of a FIB to fabricate them.
The Changing Role of Advanced Sample Preparation in X-Ray Inspection Supporting 2.5D and 3D Sample Failure Analysis
Authors: LaVoy Rosanne M. , Babian Fred , Mulholland Matthew , Silverman Scott 
Published: December 2020

Abstract
The X-ray inspection of fully assembled samples is becoming ever more important as the benefits of using area array packages/chip scale packages/flip chips are applied to more and more products. Sample preparation has traditionally been used to improve access to geometry or a specific location with a known defect that requires verification. The novel paradigm is an integrated approach to sample preparation and X-ray inspection to optimize resolution and throughput time performance with minimally deprocessed sample. This paper, covering the limitations of X-Ray imaging and 3D tomographic reconstruction, discusses the development of models for throughput time and resolution by failure analysis labs. It also discusses the processes involved in advanced sample preparation techniques and global BGA removal to obtain improved resolution at die level.
Decapsulation of Multichip BOAC Devices with Exposed Copper Metallization Using Atmospheric Pressure Microwave Induced Plasma
Authors: Tang Jiaqi , Staller Kristopher D. , Beenakker Kees 
Published: December 2020

Abstract
With the introduction of new packaging technologies and the great variety of semiconductor devices, new decapsulation tools are needed to improve failure analysis with a higher success rate, and to improve quality control with a higher confidence level. Conventional downstream microwave plasma etchers use CF4 or other fluorine containing compounds in the plasma gas that causes unwanted overetching damage to Si3N4 passivation and the Si die, thus limiting its use in IC package decapsulation. The approach of atmospheric pressure O2-only Microwave Induced Plasma (MIP) successfully solves the fluorine overetching problem. Comparison between MIP, conventional plasma, acid etching based on several challenging decapsulation applications has shown the great advantage of MIP in preserving the original status of the die, wire bonds, and failure sites. One of the challenging failure analysis cases is Bond-Over-Active-Circuit (BOAC) devices with exposed thin copper metallization traces on top of Si3N4 passivation. The BOAC critical die structures present a challenge to both conventional plasma and acid decapsulation. The use of MIP to solve the BOAC device decapsulation problem will be discussed in detail through multiple case studies. It appears that the MIP machine is the only approach to decapsulate BOAC devices without causing any damage to the exposed copper on passivation critical structure, which demonstrates the failure analysis capabilities of the MIP system.
Contactless Fault Isolation for FinFET Technologies with Visible Light and GaP SIL
Authors: Lohrke Heiko , Scholz Philipp , Beyreuther Anne , Boit Christian , Uhlmann Eckart , Kühne Stefan , Jagodzinski Marco , Ganesh Ulrike , Iwaki Yoshitaka , Chivas Robert , Silverman Scott 
Published: December 2020

Abstract
The visible approach of optical Contactless Fault Isolation (VIS-CFI) serves the perspective of application in FinFET technologies of 10 nm nodes and smaller. A solid immersion lens (SIL) is mandatory to obtain a proper resolution. A VISCFI setup with SIL requires a global polishing process for sub-10 µm silicon thickness. This work is the first to combine all these necessary components for high resolution VIS-CFI in one successful experiment. We demonstrate Laser Voltage Imaging and Probing (LVI, LVP) on 16/14 nm technology devices and investigate a focus depth dependence of the LVI/LVP measurement in FinFETs.
Localization of Nonlinear Defects in Sub 14 nm BEOL Structures
Authors: Kane Terence , Tenney Michael 
Published: December 2020

Abstract
This paper explains how SEM two-point specimen current localization combined with TEM imaging/elemental mapping overcomes the limitations of conventional SEM and gallium ion beam FIB voltage contrast methods, pinpointing the location of nonlinear defects in advanced technology (&lt;14nm) nodes.
Analysis of an Asynchronously Generated Race Condition
Authors: Howard Clifford , Dickson Kris , Erington Kent 
Published: December 2020

Abstract
An asynchronous Low Voltage Detect (LVD) interrupt during the self-test portion of the reset sequence of a microcontroller randomly caused a corrupted clock state that was not recoverable except through a power on reset, or POR. This paper discusses the techniques used to overcome the many obstacles encountered to determine the root cause of the race condition that corrupted the clock state machine registers.
Physical Failure Analysis Techniques for Front-End-of-Line Defect Analysis
Authors: Doyle Dirk , Benedict Lawrence , Awitan Fritz Christian 
Published: December 2020

Abstract
Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.