(Invited) Polycrystalline Ge-Based Thin Films with High Carrier Mobility
Authors: Toko Kaoru 
Published: December 2020

Low-temperature synthesis of high-performance semiconductor thin films on insulators is a key technology to integrate functional devices into Si-LSIs, flat panel displays, and various sensors surrounding us. Ge and Ge-based semiconductors, such as SiGe and GeSn, have higher carrier mobility and lower crystallization temperature than Si, in addition to good compatibility with conventional Si process. In recent years, Ge-MOSFET mobilities have exceeded those of Si-MOSFETs because of the development of device technologies including gate stacks. Conversely, a thin film structure is preferable to a bulk structure to suppress leakage current derived from the narrow band gap. For these reasons, Ge-based thin films are very promising as a channel material for advanced thin film transistors (TFTs). However, the performance of Ge-TFTs is currently limited by the crystallinity of the Ge thin film itself. To improve the device performance, it is essential to innovate the synthesis technology of Ge thin films on insulators.
Generally, a polycrystalline Ge (poly-Ge) layer has a high hole concentration because of defect-induced acceptors and a low carrier mobility due to grain boundary scattering.1 In low-temperature (< 500 °C) solid-phase crystallization (SPC) process, we found that the densification of the amorphous Ge (a-Ge) precursor significantly enlarged the grain size and reduced the grain boundary barrier height of the resulting poly-Ge.2 Based on the finding, we have continuously updated the Hall hole mobility of Ge layers formed on insulators (Fig. 1 (a)).3,4 It is attractive that the hole mobility exceeds that of a single-crystal Si wafer, even though the Ge layers are polycrystalline formed by a simple process. The TFT based on the Ge layer exhibited the highest performance among low-temperature Ge-TFTs.5 Because the densified a-Ge crystallizes even at < 400 °C, a flexible plastic can be used for the substrate.4 An n-type poly-Ge layer with a high electron mobility is also achieved by SPC of a-Ge containing n-type dopants (Fig. 1(b)).6,7 Further, we have demonstrated that the advanced SPC technique is useful for SiGe8 and GeSn9,10 alloys. This technique may be universally applicable to other materials, and is currently being applied to III-V compound semiconductors.
In this talk, I will discuss (i) the effects of density modulation and doping in Ge precursors on subsequent SPC and (ii) the composition effects of SiGe and GeSn alloys on the growth and electrical properties.
[1] K. Toko et al., Solid State Electronics 53, 1159 (2009).
[2] K. Toko et al., Sci. Rep. 7, 16981 (2017).
[3] R. Yoshimine et al., Appl. Phys. Express 11, 031302 (2018).
[4] T. Imajo et al., Appl. Phys. Express 12, 015508 (2019).
[5] K. Moto et al., Appl. Phys. Lett. 114, 212107 (2019).
[6] D. Takahara et al., Appl. Phys. Lett. 114, 082105 (2019).
[7] M. Saito et al., Sci. Rep. 9, 16558 (2019).
[8] D. Takahara et al., J. Alloys Compd. 766, 417 (2018).
[9] K. Moto et al., Sci. Rep. 8, 14832 (2018).
[10] K. Moto et al., Appl. Phys. Lett. 114, 112110 (2019).

Figure 1