(Invited) Ferroelectric-HfO2 Devices: Physics and Applications
Authors: Kobayashi Masaharu 
Published: December 2020

1. Introduction

Ferroelectric-HfO2 (FE-HfO2) is a key technology enabler for energy-efficient memory devices because of its high scalability and CMOS-compatibility [1]. FE memory device is low-power, high-speed and high reliability by field-driven operation. FE memory device can be implemented in the form of capacitor, resistor, and transistor, which provides us design flexibility of memory system. Thanks to the material break-through and the device architecture innovation, FE memory device opens up new opportunities in memory market. In this talk, I will overview our recent research progress on FE-HfO2 memory devices and discuss future perspectives.

2. Capacitor memory - NVSRAM

The most mature device structure is capacitor type. It is natural to replace conventional FE-material by scalable FE-HfO2. We can take an advantage of low power operation of FE-HfO2 for smart power management in IoT application. IoT sensor node devices are expected to operate in an intermittent mode. The active rate of a transistor is much lower than clock frequency in IoT device. In order to suppress standby leakage power, especially in SRAM, it is important to bring the transistors in sleep mode as much as possible. Normally-off computing is the idea that stores the current state data in NV memory, turns the power off, and restore the data after power-on without much latency and power overhead. NV-SRAM [2] has been revisited by using FE-HfO2 which realizes good scalability as well as cost effective process. NV-SRAM has been designed, fabricated by integrating FE-HfO2 capacitor [3] in back-end process as shown in Fig. 1. Store, power-off, and recall operation are successfully demonstrated.

3. Resistive memory - FTJ

Ferroelectric Tunnel Junction (FTJ) memory is an emerging memory for high capacity memory. A ferroelectric thin film is sandwiched by two electrodes, which works as resistive change memory, as shown in Fig. 2. FTJ was proposed back in 1970s [4] and current state-of-the-art nanoscale ferroelectric thin film technologies are to finally realize it. FTJ utilizes polarization switching to change on-sate and off-state tunneling electroresistance (TER). Design guideline and high TER as much as >30 has been recently demonstrated by FE-HfO2 (Fig. 2) [5]. FTJ also shows multi-level cell operation and high resistance, which are useful for hardware AI application. Moreover, scalability has been thoroughly investigated by self-consistent potential and non-equilibrium Green function method to compete with other high capacity memories (Fig. 3) [6].

4. Transistor memory - FeFET

Ferroelectric FET (FeFET) memory is a transistor which has a thin FE layer as gate insulator. This is another type of device structure for high capacity memory. Recently, 3D stacked FeFET has been proposed [7], which can possibly compete with NAND flash memory in terms of memory capacity.
There are several challenges to realize such 3D stacked FeFET using conventional poly-Si channel. Poly-Si channel has low mobility and forms a low-k interfacial layer which causes voltage loss and reliability degradation by charge trapping. In this work, we propose to use amorphous oxide semiconductor, IGZO [8], as an alternative channel material. IGZO channel provides high mobility as a deposited channel and prevent low-k interfacial layer formation. We have demonstrated ferro- electricity in the combination of FE-HfO2 and IGZO (Fig. 4), and large memory window with nearly ideal subthreshold swing and high endurance operations [9].

5. Conclusions

FE-HfO2 is a key technology enabler for energy-efficient computing because of its high scalability and CMOS-compatibility. NVSRAM serves for smart power management in IoT applications. FTJ and FeFET have a potential for low power and high capacity memory as well as machine learning accelerator.

Acknowledgment

The author acknowledges Nozomu Ueyama, Yusaku Tagawa, Fei Mo, Kiyoshi Takeuchi, Takuya Saraya and Toshiro Hiramoto for technical discussion and help. This work is partly supported by JST CREST 16815651, JST PRESTO 15656058, MEXT KAKENHI 16K18085 and 18H01489.

References

[1] J. Muller et a., Nano Lett., 12, p.4318 (2012), [2] T. Miwa et al.,IEEE JSSC, 36, 3, 522 (2001), [3] M. Kobayashi et al., IEEE Journal of Electron Dev. Soc., 6, p. 280 (2018), [4] L. Esaki et al., IBM Tech. Disc. Bulletin, 13, 8, p. 2161 (1971), [5] M. Kobayashi et al., IEEE J. Electron Dev. Soc., 7, p. 134 (2019), [6] F. Mo and M. Kobayashi et al., IEDM Tech. Dig., p. 372 (2018), [7] K. Florent et al., IEDM Tech. Dig., p. 43 (2018), [8] K. Nomura et al., Nature, 432, 25, 488 (2004), [9] F. Mo and M. Kobayashi et al., VLSI Tech. Symp., p. 42 (2019).

Figure 1