Electrochemical Pore Formation in InP: Understanding and Controlling Pore Morphology
Authors: Quill Nathan , Green Laura , O'Dwyer Colm , Buckley D. Noel , Lynch Robert Patrick 
Published: February 2020

Research on semiconductor nanostructures is motivated by two key considerations. The first is the continuing call for smaller and more efficient versions of existing semiconductor devices. The second is the characterisation and exploitation of the unique characteristics that are often exhibited by structures at the nano-scale. While a wide variety of semiconductor nanostructures can be produced without difficulty (e.g. by self-assembly or preferential etching), precise control over the morphology of these structures is often much harder to achieve.
The electrochemical formation of nano-scale porosity in semiconductors has been studied extensively1-5 and has found some application due to its bulk characteristics e.g. the use of porous silicon as a passivation layer6. However, the exploitation of the nano-scale properties of these structures is unlikely until a comprehensive understanding of the factors affecting pore morphology has been obtained.
We have previously demonstrated7-9 the formation of nano-scale porosity in n-type InP anodised in KOH. Pores emerge form pits in the electrode surface10 and grow and branch along the <111>A crystallographic directions9 forming tetrahedral porous domains8. Under certain conditions, current-line oriented pores can also be obtained.11

In order to understand the factors effecting pore morphology, porous InP was formed under a range of different temperatures, electrolyte concentrations, carrier concentrations and current densities. The morphology of the resulting porous layers was analysed in detail. In particular, the pore width, layer thickness and porosity of the layers were all measured. We show that at low current densities, the pore width is dominated by the magnitude of the current density. At higher current densities, we show that both the pore width and the porosity are inversely related to the kinetics of the electrochemical reaction: the pore width being lowest at high temperatures and intermediate KOH concentrations. The pore width decreases with increasing carrier concentration, which is likely due to the associated decrease in the space charge layer thickness. Porosity varies in a similar manner to pore width and the maximum porous layer thickness is correlated to the pore width in all cases.
These results support a model9of pore formation based on competition in kinetics between hole supply at the pore tip and the electrochemical reaction at the semiconductor electrolyte interface. It will be shown that this model makes the correct qualitative predictions for the variation of pore morphology with temperature, electrolyte concentration, carrier concentration and current density. Such an understanding of the factors affecting the morphology of these porous layers is an essential step in achieving the process control necessary for them to be integrated into standard semiconductor fabrication techniques.

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Figure 1