bluuebunny/crossref_metadata_2025_split huggingface dataset:
Electrical and Nanoprobing Analysis on the Implantation-Related Invisible Defect
Authors: Chen C.Q. , Ng P.T. , Ang G.B. , Rivai Francis , Quah A.C.T. , Ng H.P. , Ang P.C. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically, especially for implantation related problems [1] [2]. Implantation related defects, or invisible defects, are the most challenging defect types for the application of fault isolation in all of the failure analysis jobs. The key challenge for these kinds of analyses is to make the defect visible. Sometimes, it is difficult or even impossible to visualize the defective point. Then, sufficient electrical evidence and theory analysis are important to bring the issue to resolution. For these kinds of analyses, a nanoprobing system is a necessary tool to conduct the detailed analysis. Combined with the device physics and electrical theory analysis, nanoprobing can bring out the perfect failure mechanism and problematic process step. There are two popular nanoprobing systems in our lab, one is SEM based and the other is AFM based. Both systems have their advantages and disadvantages in the electrical characterization and fault isolation field. In this paper, an implantation related issue was analyzed. Gross leakage was observed on the failed units as compared with good units. Global fault isolation, TIVA and EMMI failed to find the exclusive hotspot. With the GDS and process analysis, the nanoprobing was employed to the performance check on some of the suspected structures. Finally, the defective location was successfully isolated by nanoprobing. Combined with device physics and electrical analysis, the problematic process was successfully isolated.
Case Study—Failure Analysis of a Multiplexer
Authors: Woo Michael , Campos Marcos , Aranda Luigi 
Published: December 2020

Abstract
A component failure has the potential to significantly impact the cost, manufacturing schedule, and/or the perceived reliability of a system, especially if the root cause of the failure is not known. A failure analysis is often key to mitigating the effects of a componentlevel failure to a customer or a system; minimizing schedule slips, minimizing related accrued costs to the customer, and allowing for the completion of the system with confidence that the reliability of the product had not been compromised. This case study will show how a detailed and systemic failure analysis was able to determine the exact cause of failure of a multiplexer in a high-reliability system, which allowed the manufacturer to confidently proceed with production knowing that the failure was not a systemic issue, but rather that it was a random “one time” event.
Successful Identification of a Subtle Oxide Defect in between Tungsten Plug and Titanium Liner in a Bipolar Transistor
Authors: Mendaros Raymond G. , Calanog Richard , Bawlady Raghavendra 
Published: December 2020

Abstract
Analog Devices General Trias (ADGT) received a challenging customer return unit (CRU) for failure analysis (FA). The CRU is a frequency synthesizer failing to lock at the customer’s application frequency at cold temperature condition. The failure has been simulated during bench testing at the ADGT FA laboratory at ambient temperature with VDD supply voltage lowered to 2.38V from nominal value of 3.0V. Series of fault isolation analyses using Light Emission Microscopy (LEM) and Optical Beam Induced Resistance Change (OBIRCH) localized the failure to a bipolar transistor (NPN) in the feedback divider block of the frequency synthesizer. Circuit level spice simulation replicated the functionality failure when a 2.6K-ohms resistance is connected to the emitter of the transistor. Physical failure and elemental analyses found traces of native oxide in the Nitrogen (N2) rich Titanium Nitride (TiN) layer between the Tungsten (W) plug and Titanium (Ti) liner in the emitter plug of the failing transistor. The oxide interface acts as a barrier to the flow of charge carriers in the emitter leading to the temperature dependency failure; failing at cold temperature and passing at ambient temperature. Corrective actions have been put in-place as a result of the successful identification of the defect.
Light-Induced Capacitance Alteration for Nondestructive Fault Isolation in TSV Structures for 3D Integration
Authors: Jacobs K.J.P. , Khaled A. , Stucchi M. , Wang T. , Gonzalez M. , Croes K. , De Wolf I. 
Published: December 2020

Abstract
We report on a new non-destructive electrical fault isolation (EFI) technique to localize interconnection failures in through-silicon via (TSV) structures for three-dimensional (3-D) integration. The scanning optical microscopy (SOM) technique is based on light-induced capacitance alteration (LICA) and uses localized photon probing of TSV interconnect capacitance to localize interruptions of electrical connectivity. The technique is applicable to passivated devices and allows rapid, efficient, and non-destructive fault isolation at wafer level. We describe the physics behind signal generation of the technique and demonstrate the TSV photocapacitance effect. We further demonstrate the LICA technique on open failed TSV daisy chain structures and confirm our results with microprobing and voltage contrast measurements in a scanning electron microscope (SEM).
Implementing Time Resolved Laser Assisted Device Alteration Using Pulse on Demand Nanosecond Laser Diode
Authors: Ravikumar V.K. , Ranganathan G. , Phoa S.L. , Chin J.M. , Pey K.L. , Yang J.K.W. , Kok W.L. , Koh L.S. 
Published: December 2020

Abstract
Time-resolved laser assisted device alteration (TR-LADA) has interesting applications to reduce the spatial spread of LADA site, as well as benefit device design debug. This paper describes an implementation using a 1063nm wavelength nanosecond pulse-on-demand laser diode to obtain a timing resolution of 1-2 tester cycles and spatial resolution enhancements to LADA sites. We also present potential capabilities of TR-LADA in the debug of analog circuitry.
Experimental Demonstration of the Effects of Laser Pulse Duration on SEU and LADA in CMOS Devices
Authors: Goh S.H. , Yeoh B.L. , Hao Hu , Chan Y.H. , Lin Zhao , You G.F. , Lam Jeffrey , Koh L.S. , Chua C.M. 
Published: December 2020

Abstract
This paper proves the effects of laser pulse width on the lowering of LADA and SEU threshold laser energy. The soft failure rate is found to increase with reducing pulse widths from 100 μs to 2 μs. The results obtained suggest that pulsed-LADA for soft defect characterization and localization could offer notably improved SNR and turnaround time. This is because it is no longer critical to assign the test point close to the shmoo boundary which is well known to give rise to spurious signals. With a less noisy signal image, the overall debug cycle time can be shortened since multiple frames average is not required. Further driven by the motivation to seek a viable alternative to overcome the challenge of weak LADA signals due to poor transmittance of 1064 nm wavelength laser through full wafer thickness and a solid immersion lens, preliminary results based on 1122 nm wavelength laser is also presented. It is observed that though the OBIC quantum efficiency at 1122 nm is 80% lower than at 1064 nm, it is 25% higher when a solid immersion lens is used.
Plasma-FIB Sample Preparation for X-Ray Tomography of 3D-IC Interconnects
Authors: Audoit G. , Bleuet P. , Delpy G. , Kwakman L. 
Published: December 2020

Abstract
Prior to x-ray tomography, cylindrically-shaped samples are obtained using an innovative milling strategy on a Plasma-FIB. The method presented consists of tuning the ion dose as a function of pixel coordinates along with optimization of the scan geometries, drastically reducing the preparation time and significantly improving the overall workflow efficiency.
Battelle Barricade—Microelectronic Device Authentication and Counterfeit Detection Utilizing Power Analysis
Authors: Liszewski Katie , Bergman Thomas 
Published: December 2020

Abstract
Battelle has developed a technology to nondestructively classify electronic components as authentic or counterfeit. The technology uses a method that creates feature vectors for each class of devices using a reconfigurable side channel power analysis test fixture. This test fixture monitors the power fluctuations of the device either via connection to a power or a ground pin while test signals are sent to the device. Power waveforms are processed, undergo dimensionality reduction techniques, and the resultant data is plotted in Principal Component Analysis (PCA) space to reveal information related to the authenticity of the device under test. To scale this technology to the full catalog of parts available to a production test house, unique tools have been created that provide automated test generation and scoring of feature vectors.
Acceptable Laser Dose of 28 nm FDSOI Technology—Correlation of Experiment and Simulation
Authors: Penzes Maxime , Dudit Sylvain , Parrassin Thierry , Lewis Dean , Perdu Philippe 
Published: December 2020

Abstract
Previous study on the invasiveness of the CW 1340 nm laser source used in failure analysis, pinpointed silicide diffusions issue and experimentally defined a safe experimental area. In this paper the area of interaction between the laser and the device has been measured more finely by frequency mapping. Then a simulation is used to predict the threshold of degradation. To reinforce the correlation between the simulation and the experiments, we also make a comparison with the area defined in the previous study. Finally, we give the areas of interaction in function of the temperature and show how it can change in function of the device (geometry and metal layers).
In-Situ Carbon Deposition in FIB for Reducing TEM Lamella Curtains Caused by Air Gaps in NAND Flash Memory
Authors: Hsu Hsin-Cheng , Lin Chun-Hung , Ku Huai-San , Zhuang Dun-Fan , Lin Ru-Hui , Chen Yi-An , Hsiao Wei-Ming , Yeh Chin-Chih , Lian N.-T. , Yang Ta-Hone , Chen K.-C 
Published: December 2020

Abstract
An in situ air gaps fill-in approach was investigated by conducting a convenient way in dual-beam FIB. We employed a well-controlled deposition to precisely fill carbon into air gaps. It greatly reduced formation of the artifacts and avoided the profiles of air gaps by reducing striations and damages during FIB milling. Generally, the effect of air gaps between wordlines or between metal lines, as well as some unexpected defect voids can be eliminated in most cases if this ideal method is applied.
Automated Schematic Transformation to Enhance Circuit Failure Design Debug
Authors: Gupta Varun , Lau Wee Yee Wendy , Goh S.H. , Ho H.W. , Yeoh B.L. , Hao Hu , Dawood Khalid , Lam Jeffrey 
Published: December 2020

Abstract
In a failure event, circuit schematic analysis usually follows after fault isolation to increase the success rate. However, analyzing an extracted netlist of the isolated sub-circuit can be messy. Manual circuit translation from layout where the analyst is in control of the cell instance placement is one way to overcome this challenge. Although it is neater and intuitive for analysis, it can be time consuming to create the schematic. To analyze circuits in a systematic manner, cross-mapping between layout and schematic contents is the most commonly recognized approach. However, at times, cross-mapping alone is insufficient and some further simplification procedures are favorable. This paper describes the challenges and illustrates using real case studies, how schematics re-ordering and substitutions can be useful to simplify and enhance circuit analysis. These procedures can be implemented in an automated manner to enhance turnaround time for analysis.
Root Cause Analysis and Correction of Single Metal Contact Open-Induced Scan Chain Failure in 90 nm Node VLSI
Authors: Ting Chao-Cheng , Liu Ya-Chi , Chen Hsuan-Hsien , Tsai Chung-Ching , Shih Liwen 
Published: December 2020

Abstract
In this paper, the localization of open metal contact for 90nm node SOC is reported based on Electron Beam Absorbed Current (EBAC) technique and scan diagnosis for the first time. According to the detected excess carbon, silicon and oxygen signals obtained from X-ray energy dispersive spectroscopy (EDX), the failure was deemed to be caused by the incomplete removal of silicate photoresist polymer formed during the O2 plasma dry clean before copper plating. Based on this, we proposed to replace the dry clean with diluted HF clean prior to the copper plating, which can significantly remove the silicate polymers and increase the yield.
Influence of Sample Preparation on Intrinsic Stress Inside a Model Chip—Comparison of Results from Electric Read-Out and Raman Spectroscopy
Authors: Schaffus T. , Pfaff H. , Albert P. , Schaffus M. , Kroninger F. , Krumschmidt J. , Debie D. , Breuer W. , Mack W. 
Published: December 2020

Abstract
The given project is to benchmark typical preparation methods under the aspect of the influence of initial intrinsic stresses inside electric components. Raman spectroscopy has been applied as well as the piezo resistive readout on a specifically designed model stress monitoring chip.
Combining Volume Scan Diagnosis and Dynamic Failure Analysis for Precise Isolation of Manufacturing Defects
Authors: Jakati A.M. , Deshpande R. , Serrels K.A. , Babighian P. , Dabney G. , Kalarikkal A. 
Published: December 2020

Abstract
Advances in semiconductor manufacturing technologies have led to newer types of defects that are difficult to identify, causing longer yield ramp times. Traditionally, yield has been limited to random particle defects but layout systematic defects are increasingly dominating the fail paretos on advanced technologies. Identifying systematic defects precisely and rapidly is a must. This paper codifies a methodology that combines volume scan diagnosis and non-destructive electrical fault isolation techniques such as photon-emission microscopy, soft defect localization and laser voltage imaging/probing to debug manufacturing defects precisely.
Confocal Laser Scanning Microscopy (CLSM), A Tool for Counterfeit Detection
Authors: Simard-Normandin M. , Rahman R. 
Published: December 2020

Abstract
This paper explains the CLSM technique and presents surface roughness measurement data from several groups of known authentic and suspect counterfeit parts. Surface roughness is an important characteristic of plastic encapsulated or metal lidded parts because counterfeit parts are often blacktopped or re-polished and remarked.
Automated Contactless Defect Analysis Technique Using Computer Vision
Authors: Stellari Franco , Lin Chung-Ching , Wassick Thomas , Shaw Thomas , Song Peilin 
Published: December 2020

Abstract
In this paper, an automated contactless defect analysis technique using Computer Vision (CV) algorithms is presented. The proposed method includes closed-loop control of optical tools for automated image collection, as well as advanced image analysis methods to improve image quality and detect potential defects. As an example, the technique was successfully used to identify delamination defects along the perimeter of a large test chip.
Case Study of ESD-induced Pin Leakage Failure Solved Using Novel Powered TIVA Technique
Authors: Mishra Sneta , Bockelman Daniel R. 
Published: December 2020

Abstract
A case study is presented of a core CPU product where FA/FI debug is performed for an ESD-related pin leakage issue on an IO family to root cause and qualify the product. A Powered TIVA technique is used to localize the damage to the termination resistor circuitry of the affected IO block when the pin is tristated using a device tester. Failure characterization shows a gate to drain short on the transistor, with nanoprobing confirming a solid short on gate to drain and TEM finding a short at the location indicated by the TIVA hits.
Localization of Embedded Memories using EeLADA
Authors: Thor M.H. , Goh S.H. , Zhao Lin , Yeoh B.L. , Ngow Y.T. , Hao Hu , Chan Y.H. , Lam Jeffrey 
Published: December 2020

Abstract
Bitmapping based on memory built-in self-test is the most efficient method to locate embedded memory defects in system-on-chips. Although this is the preferred approach to memory yield improvement, the procedure to enable bitmapping can be both time and resource-consuming. Therefore, it is not supported on chips that are not produced in high volume due to the low return on investment. EeLADA was explored as an alternative. Although its feasibility has been proven in a previous report, the localization capability or diagnostic resolution is limited to at best failing bit-lines. This work enhances this technique to achieve a resolution down to bit-cell level with an accuracy of less than 5 µm.
Comparative Assessment of Optical Techniques for Semi-Invasive SRAM Data Read-out on an MSP430 Microcontroller
Authors: Kiyan Tuba , Lohrke Heiko , Boit Christian 
Published: December 2020

Abstract
This paper compares the three major semi-invasive optical approaches, Photon Emission (PE), Thermal Laser Stimulation (TLS) and Electro-Optical Frequency Mapping (EOFM) for contactless static random access memory (SRAM) content read-out on a commercial microcontroller. Advantages and disadvantages of these techniques are evaluated by applying those techniques on a 1 KB SRAM in an MSP430 microcontroller. It is demonstrated that successful read out depends strongly on the core voltage parameters for each technique. For PE, better SNR and shorter integration time are to be achieved by using the highest nominal core voltage. In TLS measurements, the core voltage needs to be externally applied via a current amplifier with a bias voltage slightly above nominal. EOFM can use nominal core voltages again; however, a modulation needs to be applied. The amplitude of the modulated supply voltage signal has a strong effect on the quality of the signal. Semi-invasive read out of the memory content is necessary in order to remotely understand the organization of memory, which finds applications in hardware and software security evaluation, reverse engineering, defect localization, failure analysis, chip testing and debugging.
Thermal Transient Phenomenon Analysis for Design Debug
Authors: Mousnier M. , Bascoul G. , Lombardi T. , Faure A. , Goxe J. , Turpin P. , Kamamen H. , Zirilli T. , Ng C.C. , Bley V. , Lebey T. 
Published: December 2020

Abstract
Thermal issues management is a daily design challenge for teams working with analog mixed-signal technologies such as “SmartMOS”, with the integration of analog circuitry, high power density devices and logic control. A case study based on an NXP new product introduction will illustrate the use of Thermography as a complementary technique to standard Design debug activities, leading to the demonstration of a thermal crosstalk phenomenon in the analyzed analog mixed signal device. Based on InfraRed Thermography principle and specific Trigger Delay and Thermal Mapping modes, a transient thermal event was fully characterized, in addition to more common techniques such as Design and Layout study, electrical characterization, simulation, Microprobing, and Thermal Laser Stimulation. The added value of the thermography, as well as the limitations of the technique, will be discussed in that paper.
V-Pulse Technique For Optical Isolation Of Latchup Triggers In Sub-14 nm Standard-Cell Logic And Memory
Authors: Lo William , Gupta Puneet , Lin Yen-Tzu , Venkatesh Rakshith , Schlangen Rudolf , Li Jane , Zhang Chuan , Marks Howard , Cory Bruce 
Published: December 2020

Abstract
High core-Vdd overvoltage latchup margins in CMOS ICs are required to enable many reliability screens (e.g., DVS and HTOL testing). We introduce an efficient way to isolate defects that degrade these margins using PEM and 1064/1340 nm CW laser-stimulation. Current pulses from a current amplifier are used to rapidly charge and discharge the DUT power rail to repetitively ramp Vdd to (or near) the latchup threshold. The characteristic drop in Vdd when latchup is induced is used to generate a latchup flag for laser-stimulation mapping. Latchup events are automatically terminated and latchup durations are minimized, leading to high stability/repeatability of the technique. Isolations down to the cell level were successfully performed in sub-14 nm FinFET test vehicles. This level of isolation is unmatched and this is the first reported use of thermal laser stimulation for latchup investigations. In one provided example, the latchup trigger was isolated to FET based decoupling capacitors (decaps) widely used as fill.
Speeding up Chip Layer Imaging with a Multi-Beam SEM
Authors: Eberle A. L. , Garbowski T. , Nickell S. , Zeidler D. 
Published: December 2020

Abstract
Reverse engineering of today’s integrated circuits requires proper sample preparation, high speed imaging and data processing capabilities. The electron-optical design and the data handling architecture of our multi-beam scanning electron microscopes are scalable over a large range of beam numbers, providing sufficient imaging speed - also for the foreseeable future. A first step in data processing for reverse engineering on images acquired with a multi-beam scanning electron microscope has been successfully shown in preliminary tests.
A Simple and Efficient Tensor Calculus for Machine Learning
Authors: Laue Sören , Mitterreiter Matthias , Giesen Joachim 
Published: December 2020

Computing derivatives of tensor expressions, also known as tensor calculus, is a fundamental task in machine learning. A key concern is the efficiency of evaluating the expressions and their derivatives that hinges on the representation of these expressions. Recently, an algorithm for computing higher order derivatives of tensor expressions like Jacobians or Hessians has been introduced that is a few orders of magnitude faster than previous state-of-the-art approaches. Unfortunately, the approach is based on Ricci notation and hence cannot be incorporated into automatic differentiation frameworks from deep learning like TensorFlow, PyTorch, autograd, or JAX that use the simpler Einstein notation. This leaves two options, to either change the underlying tensor representation in these frameworks or to develop a new, provably correct algorithm based on Einstein notation. Obviously, the first option is impractical. Hence, we pursue the second option. Here, we show that using Ricci notation is not necessary for an efficient tensor calculus and develop an equally efficient method for the simpler Einstein notation. It turns out that turning to Einstein notation enables further improvements that lead to even better efficiency. The methods that are described in this paper for computing derivatives of matrix and tensor expressions have been implemented in the online tool www.MatrixCalculus.org .