bluuebunny/crossref_metadata_2025_split huggingface dataset:
Making the Most of the Internet for Failure Analysis
Authors: Bodoh Dan J. 
Published: December 2020

Abstract
The growth of the Internet over the past four years provides the failure analyst with a new media for communicating his results. The new digital media offers significant advantages over analog publication of results. Digital production, distribution and storage of failure analysis results reduces copying costs and paper storage, and enhances the ability to search through old analyses. When published digitally, results reach the customer within minutes of finishing the report. Furthermore, images on the computer screen can be of significantly higher quality than images reproduced on paper. The advantages of the digital medium come at a price, however. Research has shown that employees can become less productive when replacing their analog methodologies with digital methodologies. Today's feature-filled software encourages "futzing," one cause of the productivity reduction. In addition, the quality of the images and ability to search the text can be compromised if the software or the analyst does not understand this digital medium. This paper describes a system that offers complete digital production, distribution and storage of failure analysis reports on the Internet. By design, this system reduces the futzing factor, enhances the ability to search the reports, and optimizes images for display on computer monitors. Because photographic images are so important to failure analysis, some digital image optimization theory is reviewed.
ESD Protection Using Active Area Bonding
Authors: Bernier Joe C. , Teems Larry 
Published: December 2020

Abstract
In the never ending battle for smaller, faster, cheaper semiconductors, ESD protection is more and more becoming a driving factor. Since scaling the ESD protection devices usually means scaling the level of protection as well, methods for providing good ESD robustness in less real estate are required. By placing some ESD circuitry under the bond pads and maintaining good control over the wire bond process, good ESD levels can be obtained, excellent reliability can be achieved and significant die area can be saved.
The Effect of Ball Pad Metallurgy and Ball Composition on Solder Ball Integrity of Plastic Ball Grid Array Packages
Authors: Zhong C.H. , Yi Sung 
Published: December 2020

Abstract
Ball shear forces of plastic ball grid array (PBGA) packages are found to decrease after reliability test. Packages with different ball pad metallurgy form different intermetallic compounds (IMC) thus ball shear forces and failure modes are different. The characteristic and dynamic process of IMC formed are decided by ball pad metallurgy which includes Ni barrier layer and Au layer thickness. Solder ball composition also affects IMC formation dynamic process. There is basically no difference in ball shear force and failure mode for packages with different under ball pad metallurgy before reliability test. However shear force decreased and failure mode changed after reliability test, especially when packages exposed to high temperature. Major difference in ball shear force and failure mode was found for ball pad metallurgy of Ni barrier layer including Ni-P, pure Ni and Ni-Co. Solder ball composition was found to affect the IMC formation rate.
Failure Analysis of Advanced Microprocessors through Backside Approaches
Authors: Davis D. , Diaz de Leon O. , Hughes L. , Pabbisetty S. V. , Parker R. , Scott P. , Todd C. , Widaski J. , Wilhite G. , Wills K.S. , Zhu J. 
Published: December 2020

Abstract
The advent of Flip Chip and other complex package configurations and process technologies have made conventional failure analysis techniques inapplicable. This paper covers the ways in which conventional techniques have been modified to meet the FA challenges presented by these new devices – specifically, by forcing analysis to be done from the backside of the device. Modifications to the traditional FA process steps, including new sample preparation methods, changes in hardware, and alterations to physical failure analysis processes are described. To demonstrate the use of backside analytical approaches, some examples of applications and a case study are also included.
Terahertz Imaging: A New Technique for Inspection of Dielectric Materials
Authors: Mittleman Daniel M. 
Published: December 2020

Abstract
Terahertz time-domain spectroscopy (THz-TDS) is a promising new technology which provides a relatively simple means of generating and detecting single-cycle pulses of far-infrared (or terahertz) radiation. One of the most interesting aspects of this system is its insensitivity to the thermal background. This obviates the need for cryogenic apparatus; as a result, this may be the first portable far-infrared spectrometer. Recent work has demonstrated the possibility of tomographic imaging using THz-TDS. In this imaging mode, a reflected pulse train is used to construct a three-dimensional representation of a composite material, using the timing between reflected pulses to determine the spacing between adjacent dielectric interfaces. Here, the transverse resolution is determined by the diffraction-limited focus of the THz beam, and is typically ~300 microns. The longitudinal (depth) resolution of ~100 microns is determined by the coherence length of the radiation, although the location of isolated surfaces can be determined with far higher precision. Since many common packaging materials have high transparency in the THz range, this suggests the possibility of exploiting this new imaging system for non-invasive testing and on-line monitoring. The operation of the THz “T-ray” imaging system will be described, and several examples will be provided which illustrate its capabilities and limitations.
Temperature Profile Measurement and Failure Characterization of ESD Protection Devices Using Spectroscopic Photon Emission Microscopy and Raman Spectroscopy
Authors: Rasras Mahmoud , De Wolf Ingrid , Groeseneken Guido , Chen Jian , Bock Karlheinz , Maes Herman E. 
Published: December 2020

Abstract
In this paper, Photon Emission Microscopy (PEM) and micro-Raman Spectroscopy (μRS) are applied for temperature profile measurements and failure characterization in gg-nMOS ESD protection devices. The measurements were carried out in avalanche and snapback biasing conditions. A correlation between the temperature profile obtained by μRS and the light emission location, measured by PEM, is observed for non-degraded devices. In addition, ESD-degraded devices were studied. PEM, μRS, Spectroscopic Photon Emission Microscopy (SPEM) and electrical measurements were used to investigate the origin of the light emitted at the failure site. They showed that the light emission occurring at the failure site is due to impact ionization.
Automatic TEM Sample Preparation
Authors: Kaplan Wayne D. , Kisslinger Kim , Oviedo Ron , Raz Efrat M. , Smith Colin 
Published: December 2020

Abstract
The rising demand in the semiconductor industry for higher spatial resolution in the analysis of device defects has focused attention on the use of transmission electron microscopy (TEM). However, conventional TEM sample preparation may be difficult and time-consuming, and depending on the operator may result in a low yield of quality specimens. One solution to this problem is the use of focused ion beam (FIB) milling for the final stage of TEM sample preparation. However, specimens have to be mechanically thinned prior to FIB processing, and the need to characterize specific devices requires a pre-FIB preparation method to isolate specific regions on the wafer. An innovative and automated solution that isolates specific devices and prepares TEM specimens for subsequent thinning by FIB has been developed. Based on controlled microcleaving technology, the system automatically performs the pre-FIB preparation in less than 30 minutes. An important added benefit is that the target area to be analyzed can be positioned at a specific distance from the sample edge, thereby facilitating the final FIB milling stage. The thinned specimen is automatically packaged for subsequent FIB processing and TEM. Details of the method and examples showing TEM results from tungsten filled vias are presented.
A Technique for Measuring Device Temperature with High Accuracy in Accelerated Operational Life Tests
Authors: Takeda K. , Harigaya M. , Miyazaki Y. 
Published: December 2020

Abstract
This paper describes a new technique for measuring junction temperature with high accuracy in accelerated operational tests (junction temperature ≥200°C) based on the measurements of temperature dependence of gate-leakage current on a GaAs FET (gate-leakage method). The gate-leakage current on the GaAs FET is monitored in the accelerated operational tests. Then, junction temperature and thermal resistance are calculated from the temperature dependence of the gate-leakage current, especially from the temperature dependence in high temperature region. We have measured the junction temperature and the thermal resistance using this method in accelerated operational tests, and have confirmed that the junction temperature can be estimated within a range of ten degrees. The results by this method have been compared with data of simulation, and the validity has been confirmed.
Modeling and Optimizing XeF2-enhanced FIB Milling of Silicon
Authors: Bassom Neil J. , Mai Tung 
Published: December 2020

Abstract
Wide variations in the dose enhancement factor observed when milling silicon using Focused Ion Beam (FIB) XeF2 Gas Assisted Etching (GAE) prompted the development of a simple model of the GAE process. The model accounts for three material removal mechanisms: regular sputtering; gas-assisted sputtering; and spontaneous chemical reactions. An expression linking the dose enhancement factor, εd, to the gas and milling parameters has been derived. Experiments show that εd behaves as predicted; good quantitative agreement is achieved over wide ranges of milling parameters for εd values between 20X and 2500X. Conditions required to minimize variations in d and maximize material removal rates, M, are derived. It is shown that if the dose per unit area per raster is below a threshold value then εd and M depend only on the average current density J (the area of the box divided by the beam current). A consideration of the J regimes used for front-side and back-side FIB work shows why changes in εd have not previously been a problem but are inevitable when milling the large trenches characteristics of Flip Chip circuit modification work. While εd changes dramatically there is a region of J values for which M is approximately constant.
In-Situ Dual Beam (FIBSEM) Techniques for Probe Pad Deposition and Dielectric Integrity Inspection in 0.2 μm Technology DRAM Single Cells
Authors: Zimmermann Gunnar , Chapman Richard 
Published: December 2020

Abstract
Dual beam FIBSEM systems invite the use of innovative techniques to localize IC fails both electrically and physically. For electrical localization, we present a quick and reliable in-situ FIBSEM technique to deposit probe pads with very low parasitic leakage (Ipara &lt; 4E-11A at 3V). The probe pads were Pt, deposited with ion beam assistance, on top of highly insulating SiOx, deposited with electron beam assistance. The buried plate (n-Band), p-well, wordline and bitline of a failing and a good 0.2 μm technology DRAM single cell were contacted. Both cells shared the same wordline for direct comparison of cell characteristics. Through this technique we electrically isolated the fail to a single cell by detecting leakage between the polysilicon wordline gate and the cell diffusion. For physical localization, we present a completely in-situ FIBSEM technique that combines ion milling, XeF2 staining and SEM imaging. With this technique, the electrically isolated fail was found to be a hole in the gate oxide at the bad cell.
FIB Micromachining and Nano-Structure Fabrication
Authors: Lee Raymond A. , Wolpert Patrick J. 
Published: December 2020

Abstract
FIB Micromachining has long been an established technique, but until recently it has been overshadowed by the more mainstream semiconductor application of the Focused Ion Beam system. Nano- Structure fabrication using the FIB system has become more popular recently due to several factors. The need for sub-micron structures have grown significantly due to a need for enhanced optical and biological applications. Another reason for the growth in micromachining is the improvement made in the ability of FIB systems to produce geometric shapes with high precision. With the latest high-end FIB systems, it is possible to produce microstructures with tens of nano-meters of precision. Optical lens, AFM tips, and nano-apertures are all part of the growing application for FIB Micromachining. This paper will discuss the ability and limitations of the FIB system and some possible application for FIB Micromachining.
Investigation of High Frequency Failures on a 0.35μm CMOS IC
Authors: Kennen Alan , Guravage John F. , Foster Lauren , Kornblum John 
Published: December 2020

Abstract
Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.
Recent Advances in Broad Ion Beam Based Techniques/Instrumentation for SEM Specimen Preparation of Semiconductors
Authors: Alani R. , Mitro R. J. , Hauffe W. 
Published: December 2020

Abstract
The semiconductor industry routinely prepares crosssectional SEM specimens using several traditional techniques. Included in these are cleaving, mechanical polishing, wet chemical etching and focused ion beam (FIB) milling. This presentation deals with a new alternate method for preparation of SEM semiconductor specimens based upon a dedicated broad ion beam instrument. Offered initially as an alternative to wet chemical etching, the instrument was designed to etch and coat SEM and metallographic specimens in one vacuum chamber using inert gas (Ar) ion beams. The system has recently undergone further enhancement by introducing iodine Reactive Ion Beam Etching (RIBE) producing much improved etching/cleaning capabilities compared with inert gas ion beam etching. Further results indicate Ar broad ion beam etching can offer a rapid, simple, more affordable alternative (to FIB machines) for precision cross sections and for “slope cutting,” a technique producing large cross-sections within a short time frame. The overall effectiveness of this system for iodine RIBE etching, for precision cross sectioning and “slope cutting” will be shown for a number of traditional and advanced semiconductor devices.
X-Ray Tomography for Electronic Packages
Authors: Goyal Deepak 
Published: December 2020

Abstract
Next generation assembly/package development challenges are primarily increased interconnect complexity and density with ever shorter development time. The results of this trend present some distinct challenges for the analytical tools/techniques to support this technical roadmap. The key challenge in the analytical tools/techniques is the development of non-destructive imaging for improved time to information. This paper will present the key drivers for the non-destructive imaging, results of literature search and evaluation of key analytical techniques currently available. Based on these studies requirements of a 3D imaging capability will be discussed. Critical breakthroughs required for development of such a capability are also summarized.
Time Domain Reflectometry as a Device Packaging Level Failure Analysis and Failure Localization Tool
Authors: Searls Damion T. , Don Anura , Dy Emilie , Goyal Deepak 
Published: December 2020

Abstract
Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).
Combining FIB Sequential Cross-Sectioning with TEM for Small Defect Analysis in SRAM Array
Authors: Wang Nathan , Fang Rei 
Published: December 2020

Abstract
To find defects and their root cause in semiconductor devices has become more and more difficult as chip size dramatically drops. A novel method combining FIB sequential cross-sectioning and TEM is described in this paper. This combination has provided a powerful tool for defect mechanism analysis. FIB slicing through a failed cell can be controlled to a precision of 0.1 micron. Passive voltage contrast imaging with FIB enhances defect detection. After a defect is found, in-situ TEM sample is prepared with FIB milling. By putting together the series FIB images along side with the TEM images and its associated high resolution EDS data, the detailed defect formation mechanism was discovered and feedback to process engineering for process improvement.
Failure Analysis of Stacked-Chip Scale Package
Authors: Flores Christopher C. 
Published: December 2020

Abstract
Stacked-chip scale package (S-CSP) is a new packaging technology introduced in the memory components market to effect chip miniaturization, a challenging trend in semiconductor assembly. The package is built by molding two stacked dice (Flash and SRAM) on bismaleimide triazine (BT) substrate. As this novel packaging technology offers solution to the challenge, it also poses complexity in the field of failure analysis in cases that the bottom die is the interest. Deprocessing these stacked dice while maintaining the functionality of the bottom die will be explained in detail. Prior the conduct of failure analysis (FA) and fault isolation (FI), deprocessing the failing unit containing only one die normally consists of chemical decapsulation. S-CSP sample preparation also adheres to this treatment in case the top die is the aim for analysis. On the other hand, if the concern shifts to the bottom die, sequential techniques involving precision polishing to die-to-die adhesive layer, chemical etching of adhesive and residual molding compound, and rebonding the bottom die on ceramic interposer, are employed. With the rebonded S-CSP bottom die, fault isolation could be performed further. This paper will also feature the mechanism behind the blown-up failure, a power test failure in memory devices, encountered during the package development when two types of die-to-die adhesives were selected and used. Consistent with the results of electrical characterization suggesting that S-CSP bottom die as the failing die, passivation damage is uncovered on the bottom die upon separation of the stacked dice. Material comparison points out that the hard, angular glass fillers of the die-to-die adhesive induce the damage. Polymer-filled adhesive performs better than the glass-filled adhesive as indicated by the results of the package characterization. Generally, this case exemplifies a packaging material-related failure. Moreover, the paper could serve as a reference material in the event that feasibility of packaging non-memory components in S-CSP is to be evaluated. The developed methodology of recovering the S-CSP bottom die would be a keystone in proacting for its FA readiness.
Advanced Analytical Chemistry Techniques Enable Rapid, Cheap and Concise Electronic Failure Analysis
Authors: Mazurkiewicz Paul 
Published: December 2020

Abstract
This article introduces several analytical chemistry techniques that are extremely useful in the electronics failure analysis (FA) laboratory, but are not normally found in FA laboratories. It presents the techniques in simple language and makes a case for the inclusion of chemists in the rapidly evolving and ever-shrinking world of microelectronic failure analysis. The article discusses the following techniques in terms of their applications, advantages, and operating principles: gel permeation chromatography, gas chromatography-mass spectrometry, Fourier transform-infrared spectroscopy, and electron spectroscopy for chemical analysis (ESCA). As we move into the world of nanotechnology, these techniques will become key in analyzing failures that cannot be visualized using traditional FA methods.
A Novel Electrical Test by C-AFM to Differentiate Gate-to-S/D Gate Oxide Short From Non-Gate Oxide Short Defect in Real Products
Authors: Lin Cheng-Piao , Wu Cheng-Hsu , Ting Cheng-Chun 
Published: December 2020

Abstract
A method to differentiate Gate-to-S/D Gate Oxide Short from non-Gate Oxide Short defect in real products by analyzing the I-V curves acquired by Conducting-Atomic Force Microscopy (C-AFM) is presented. The method allows not only the correct short path to be identified, but also allows differentiation of gate-to-S/D GOS from non-GOS problems, which cannot be reached by passive voltage contrast (PVC) only.