Highly Parallelized Carbon Nanotubes for Field-Effect Device Applications
Authors: Keyn Martin , Schwalke Udo 
Published: February 2020

In this work we report on a custom made contact layout which utilizes large scale parallelization of in situgrown carbon nanotubes (CNTs). If parallelization of CNTs is adapted to a carbon-silicon-hybrid technology for producing field-effect devices, it is for example possible to increase the on-state current of a field-effect transistor. The effect can be compared to increasing a transistor’s gate width in conventional silicon technology.

Introduction

The growth of CNTs is done on a thermally oxidized silicon wafer with the aid of a metallic double stack and chemical vapor deposition from a methane feedstock. The metallic stack is composed of aluminum and nickel. By annealing prior to CVD the stack is converted into an insulator of AlxOyand nickel nanoclusters. These clusters act as catalyst for CNT growth during CVD – thus, called “catalytic chemical vapor deposition” (CCVD).
By this fabrication technology carbon nanotubes are grown on the whole wafer surface, which are finally connected statistically by specially patterned contacts (Fig. 1). Whether the final device has a “normal” or high on-state current (Fig. 2) is only depended on the used contact layout. A layout allowing only one CNT between on pair of source/drain contacts creates single-CNTFETs whereas as a layout dedicated to large scale parallelization creates multi-CNTFETs by allowing thousands of CNTs to be linking on pair of source/drain contacts.

Contact layout

The mentioned layout uses the fact that CNTs are grown everywhere on the wafer surface with our technology. The CNT density and electrical properties can be adjusted by a mild plasma treatment [1] of the metallic double stack and the annealing step which is carried out prior to annealing. We report on the effect of annealing in a different work [2]. If the density of CNTs is high enough every enlargement in channel width will directly correspond to a higher amount of linking CNTs between one pair of source/drain contacts. Therefore, the on-state current will increase with increasing channel width.
The layout has different comb-shaped transistors. Every finger of the comb is 25 µm wide and 250 µm long and one pair of “source/drain fingers” generates a channel width of 200 µm. In this manner the effective channel width is determined by the amount of finger pairs. Every finger of source or drain is connected by a large bus-contact. Buses are 200 µm wide to reduce their electrical resistivity (Fig. 3).

Summary & Outlook

Our process is a convenient and time-saving way for growing high quality CNTs for field-effect devices. It is flexible and results in damage-free CNTs since they are grown in situin contrast to being deposited by spin coating of CNT solutions or the like.
Although recent devices still use a backgate it possible to realize an additional Π-topgate. As gate dielectric atomic layer deposited Al2O3seems promising.

References

[1] M. Keyn and U. Schwalke, “Multi-CNTFETs for power device applications: Investigation of CCVD grown CNTs by means of atomic force microscopy,” in 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 26.-28.03.2013.
[2] M. Keyn, A. Kramer and U. Schwalke, “Dependence of annealing temperature on cluster formation during in situ growth of CNTs,” in 9th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 06.-08.05.2014.