(Invited) Dielectrics in Nanoelectronic Computing
Authors: Chen An 
Published: May 2020

As the CMOS scaling driven by the Moore’s Law approaching some fundamental limits, high power consumption and heat dissipation have been recognized as the most critical device challenges. The Nanoelectronics Research Initiative (NRI) was launched 14 years ago by the semiconductor industry to explore alternative switching devices with significantly lower power based on unconventional mechanisms, materials, and devices. NRI has investigated a broad range of devices, including steep-slop transistors, spintronics, van der Waals devices, as well as new architectures to utilize unique characteristics offered by these devices [1]. Novel materials, including various dielectrics, have been the foundation of NRI research. For example, dielectric layers for gating and electrical insulation have been a great challenge for low-dimensional devices; magnetic insulators are promising for low-power high-efficiency spintronic devices; ferroelectric materials have been utilized to realize the so-called “negative-capacitance” transistors for low-power applications [2]. Despite abundant scientific breakthroughs achieved in over a decade of research in NRI, no beyond-CMOS devices have been demonstrated to significantly outperform CMOS for Boolean logic and von Neumann architectures. Comprehensive benchmarking of beyond-CMOS devices conducted in NRI has revealed the limitations of these devices quantitatively [3].
As the semiconductor industry shifts toward novel computing paradigms, beyond-CMOS materials and devices may find more suitable opportunities for applications beyond Boolean and von Neumann computing. In-memory computing and analog computing (including neuromorphic computing) have stood out in this promising direction. Ferroelectric materials, binary and complex oxides, and chalcogenides have been utilized in a wide range of nonvolatile memories and analog devices, which may enable highly efficient in-memory and analog computing solutions. However, stringent requirements exist for these devices to significantly outperform CMOS in these applications, e.g., high density, fast speed, low power, high endurance, long retention, wide analog tunability, etc. [4] More specific requirements also exist and vary from application to application. Device-architecture design and co-optimization can help to address some of these requirements, but more fundamental solutions are rooted in material engineering and optimization to enable devices capable of native implementation of these novel computing paradigms. This holistic approach from basic material exploration to device engineering and further up to architecture co-design has become the guiding principle of the follow-on program of NRI, known as nanoelectronic Computing Research (nCORE) [5].
This paper will review NRI research and lessons learned, which laid the foundation for new directions and research in the nCORE program. The importance, challenges, and opportunities of dielectric materials in nanoelectronic research will be discussed in this context.

References:

[1] K. Bernstein, R.K. Cavin, W. Porod, A. Seabaugh, and J. Welser, “Device and architecture outlokk for beyond CMOS switches,” IEEE Proc. 98(12), 2169-2184 (2010).
[2] S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Lett. 8, 405-410 (2008).
[3] C. Pan and A. Naeemi, “Non-Boolean computing benchmarking for beyond-CMOS devices based on cellular neural network,” IEEE J. Explor. Solid-State Comp. Dev. & Circ 2, 36-43 (2016).
[4] G.W. Burr, et al, “Neuromorphic computing using non-volatile memory,” Adv. in Phys.: X, 2(1), 89-124 (2017).
[5] A. Chen, “New directions of nanoelectronics research for computing,” 14th IEEE ICSICT (2018).