bluuebunny/crossref_metadata_2025_split huggingface dataset:
The Complete Water-Based Ceramic Coating Process for Lithium Secondary Batteries By Plasma Treatment
Authors: Jeon Hyunkyu , Lee Hongkyung , Kim Hee-Tak , Lee Yong Min , Ryou Myung-Hyun 
Published: February 2020

Abstract

Numerous numbers of polyolefin-based microporous separators containing thermally stable inorganic/polymer composite layers have been developed to improve safety of lithium-ion batteries [1-3]. Because of hydrophobic surface property of polyolefin-based separators, the use of non-polar organic solvent, which is generally toxic and expensive, is prerequisite to introduce ceramic coating layers containing polymeric binders. Not only to price down the coating process but also to guarantee an environmentally friendly coating process, an aqueous ceramic coating process should be developed.
Herein, we developed the complete water-based ceramic coating process to prepare inorganic/polymer composite coating layers on commercial polyethylene (PE) separators using plasma treatment. The plasma treatment introduced polar functional groups onto the surface of PE separators, thereby changed the surface properties of the PE separators from hydrophobic to hydrophilic. Consequently, the coating solution based on water uniformly covered the plasma treated PE separator surfaces without defects. We investigated the physical properties of ceramic-coated separators (CCSs), including their morphology changes, gurley number, thickness, and ionic conductivity. We also studied the electrochemical properties of cells containing the CCSs. CCS exhibits superior power capability and cycle performance compared to bare PE in unit cells based on lithium metal anodes.

Acknowledges

This research was supported by the Ministry of Trade, Industry & Energy (MOTIE), Korea Institute for Advancement of Technology (KIAT) through the Encouragement Program for The Industries of Economic Cooperation Region (G02A01280032701)

Reference

[1] Y. Lee, H. Lee, T. Lee, M.-H. Ryou, Y.M. Lee, J. Power Sources 294 (2015) 537-544.
[2] D. Yeon, Y. Lee, M.-H. Ryou, Y.M. Lee, Electrochim. Acta 157 (2015) 282-289.
[3] H. Jeon, D. Yeon, T. Lee, J. Park, M.-H. Ryou, Y.M. Lee, J. Power Sources 315 (2016) 161-168.
Localized Electrochemical Analysis of Polyacrylate Binders on Graphite-Silicon Negative Electrodes in Lithium-Ion Batteries
Authors: Kumatani Akichika , Watanabe Tetsuya , Yasufumi Takahashi , Kubota Kei , Ida Hiroki , Shiku Hitoshi , Komaba Shinichi , Matsue Tomokazu 
Published: February 2020

Graphite-silicon composite negative electrodes are expected to satisfy one of recent demands for creation of high performance lithium-ion batteries because of their high-capacity (above 1000 mAh/g). A major issue for their practical application is a control of large volume expansion/shrinkage of silicon materials, which is a key to realize their good reversible cyclability. Recently, Komaba et al. reported that polyacrylate binders improve their cyclability because of well-dispersion of graphite/silicon materials by coating them with polyacrylate homogeniously.1,2 Also, polyacrylate can suppress a formation of decomposition of organic electrolyte during lithiation process, which induces poor cyclability. For further investigation of existence of the decomposition, we have applied a scanning electrochemical cell microscopy with single barrel nano-pipette filled with organic electrolyte and a reference electrode, called nanoSECCM in Figure 1 a.3NanoSECCM can measure electrochemical properties (such by cyclic voltammetry, CV) with sub-micrometer scale locally. From localized CV results (scan rate at 100 mV/s) as shown in Figure 1 b, we have observed current response related to the formation of decomposition. This response was not observed by typical bulk CV measurement, suggesting that our technique is sensitive to investigate graphite-silicon composite negative electrodes for realization of high performance electrodes in lithium-ion batteries.
[1] N. Yabuuchi et al., Adv. Energy Mater., 2011, 1, 759.
[2] Z-J. Han et al., Phys. Chem. Chem. Phys., 2015, 17, 3783.
[3] Y. Takahashi et al., Nat. Commun. 2014, 5, 6450.

Figure 1
Melt Synthesis of LiFePO4: Fundamentals, Versatility and Application
Authors: Talebi-Esfandarani Majid , Rousselot Steeve , Jin Liling , Bibienne Thomas , Gauthier Michel , Chartrand Patrice , Sauriol Pierre , Seifitokaldani Ali , Liang Guoxian , Dollé Mickael 
Published: February 2020

With its good thermal stability, abundance in nature and benign environmental impact, LiFePO4 (LFP) cathode material is seen as one of the most promising candidate for the next generation of Li-ion batteries. Many synthetic routes have already been used for preparing LFP material, best known being solid state, sol-gel, hydrothermal, co-precipitation and microwave preparations. All of them are performed at moderate temperature and/or in a wide range of pressures. Melt process of LFP, advanced by Gauthier et al. in 2003[1], operates in the liquid phase above 1000⁰C and then benefits from increased reaction kinetics and from the thermodynamic stability of LFP in a mild reducing atmosphere. The melt synthesis allows the use of a wide range of simple raw materials as well as a possible purification strategy during the melt step or upon solidification, potentially enabling for usage of less pure non-expensive raw materials.
In this work, thermodynamic considerations are first addressed for deep understanding of the Li-Fe-P-O systems. A model has recently been developed and is supported by experimental data. On this basis, recent experimental observations and progress on raw material selection (including direct use of iron ore concentrates) and systems will be reported. Eventually, melt-synthesis conditions and the latest results in controlling the purification of LiFePO4 from major phase impurities will also be covered. All these considerations allow the selection of the best conditions to prepare a high purity LiFePO4 by melt-process.
This work is part of an Automotive Partnership of Canada supported program to develop and pilot the molten-synthesis process to make high purity C-LiFePO4with excellent electrochemical properties for using as a cathode material in Li-ion batteries for EVs and PHEVs application.

[1] M. Gauthier, L. Gauthier, D. Lavoie, C. Michot, N. Ravet, US Patent 7,534,408 B2. (2003).
(Invited) Epitaxial Transition Metal Nitrides for III-Nitride Devices: Application for Epitaxial Lift-Off and Transfer
Authors: Downey Brian P. , Meyer David J. , Katzer D. Scott , Nepal Neeraj , Wheeler Virginia D. , Storm David F. , Anderson Travis J , Hardy Matthew T 
Published: February 2020

Integration of epitaxial metallic layers within a semiconductor device structure has long been desired for a variety of applications; however, the practical realization of this goal has remained elusive. We have recently demonstrated the epitaxial growth of a transition metal nitride, Nb2N, on 6H-SiC substrates using plasma-assisted molecular beam epitaxy [1]. The films, ranging from 4 to 100 nm in thickness, exhibited single phase, sub-nm rms roughness, and low resistivity. Furthermore, high quality III-nitride layers can be grown on the Nb2N/SiC templates, either in a continuous growth run or after removing and re-loading the Nb2N/SiC template [2], without observable reaction between any of the layers. III-nitride material quality has been verified by growing a high-electron-mobility transistor (HEMT) device structure on a Nb2N/SiC template, achieving a two-dimensional electron gas (2DEG) mobility of 1400 cm2/V-s, a sheet carrier density of 1.2x1013 cm-2, and a maximum drain current in excess of 1 A/mm [3]. One unique application of this HEMT/Nb2N/SiC structure is utilizing the Nb2N layer as a sacrificial release layer for HEMT lift-off and transfer to alternative substrates of interest [4]. We have found that the intact HEMT structure can be released from the substrate without observable degradation of the 2DEG electrical properties by selective etching of the buried Nb2N layer using XeF2 vapor phase etching [3]. This process opens the door for the integration of GaN devices with various other technological platforms (heterogeneous integration) or onto alternative substrates such as plastic or diamond. Additionally, this process could allow for the reuse of SiC substrates after device lift-off. This presentation will focus on the materials development of epitaxial Nb2N layers and their use as a sacrificial release layer for III-nitride device transfer from SiC substrates.
[1] D.S. Katzer et al., Appl. Phys. Express, vol. 8, no. 8, 085501 (2015).
[2] N. Nepal et al., Appl. Phys. Express, vol. 9, no. 2, 021003 (2016).
[3] D.J. Meyer et al., CS MANTECH Conference, May 16 – 19, Miami, USA (2016).
[4] D.J. Meyer and B.P. Downey, “Lift-off of epitaxial layers from silicon carbide or compound semiconductor substrates,” US patent application no. 14/331,440. PCT application no. PCT/US14/46609.
Band Gap Engineering of Wurtzite-Type Narrow Band Gap Oxide Semiconductor β-CuGaO2
Authors: Omata Takahisa , Mizuno Yuki , Nagatani Hiraku , Suzuki Issei , Kita Masao 
Published: February 2020

β-CuGaO2 is an oxide semiconductor possessing wurtzite-derived β-NaFeO2 structure. Its band gap is 1.47 eV in near-infrared region, and the first principles calculation indicates that it is a direct band gap semiconductor. Therefore, this material is expected to be applicable to optoelectronic devices working in near-infrared region. When the band gap of β-CuGaO2 is widened into visible region, the material is expected to be applicable to visible LEDs and lasers, photocatalyst and so on. In the present study, we demonstrated band gap engineering of β-CuGaO2 by alloying with β-CuAlO2 and β-LiGaO2 possessing wurtzite-derived β-NaFeO2 structure in order to widen the band gap. Cu(Ga1-xAlx)O2 alloys were prepared by ion-exchange of Na+ ions in β-Na(Ga1-xAlx)O2 with Cu+ ions in CuCl at 250 °C for 48 h under vacuum. (Cu1-xLix)GaO2 alloys were prepared by ion-exchange of Cu+ ions in β-CuGaO2 with Li+ ions in LiCl at 300 °C for 48 h under vacuum. Wurtzite-type β-phases were obtained in 0≤x≤0.7 for Cu(Ga1-xAlx)O2 system and in 0≤x≤1 for (Cu1-xLix)GaO2 system.
In β-Cu(Ga1-xAlx)O2, the optical band gap increased linearly with the increasing alloying level; no band gap bowing appeared in the present system. The band gap of β-CuGaO2 was widened up to 2.1 eV at β-Cu(Ga0.3Al0.7)O2; this energy corresponds to red light. In β-(Cu1-xLix)GaO2, the energy band gap increased almost linearly with the increasing alloying level up to x~0.9; the largest band gap in this composition range was 3.0 eV corresponding to violet light at β-(Cu0.11Li0.89)GaO2. When the alloying level increased further, the band gap steeply increased from 3.0 eV at x=0.89 to 5.6 eV at x=1. The valence band X-ray photoelectron spectra of β-(Cu1-xLix)GaO2 indicated that the steep increase in energy band gap from x~0.9 to 1 is attributed to that the Cu 3d contribution around the top of the valence band electronic states vanishes for the alloys with x>0.9. These results indicate that the energy band gap of β-CuGaO2 is highly controllable in the wavelength region from near-infrared to entire visible lights. Thus, it is expected that β-CuGaO2 opens new applications of oxide semiconductors in devices working in visible region.
Necessary Thickness of Au Capping Layers for Room Temperature Bonding of Wafers in Air Using Thin Metal Films with Au Capping Layers
Authors: Uomoto Miyuki , Shimatsu Takehito 
Published: February 2020

Room temperature bonding of wafers using thin metal films is applicable to any mirror-polished wafers, moreover, the bonded metal films can be used for electrical/thermal conductions and optical reflections. For this study, room temperature bonding of wafers in air using 10~300 nm-thick Ag, Cu, Al films with 2~30 nm-thick thin Au capping layers was examined, and necessary thickness of Au capping layer to bond wafers in air was discussed.
2-inch diameter micro-polished quarts glass wafers were used for this study. The Ti films (1 nm thickness) were used as underlayers to enhance the adhesion strength of the deposited films on the wafer surface. After the sputter film deposition on the surfaces of two wafers, bonding was accomplished in air of a clean room (20°C, 50% moisture level, class 100). No substrate heating was conducted during deposition or the bonding processes.
Bonding in air could be accomplished using 20 nm-thick Ag, Cu films with 2 nm-thick Au capping layers without any loading pressure: once the nucleation of recrystallization at Au–Au interface of capping layers was formed, the recrystallization was propagated immediately, and the bonding was completed over the entire bonded area. 2 nm-thick Au capping layer was effective to avoid oxidation of the surfaces of these metal films in air and to nucleate the recrystallization between the connected films in the bonding process. Actually the surface energy at the bonded interface, evaluated using the blade method, was much higher than the surface energy of Au films.
Necessary thickness of Au capping layer for 20 nm-thick Al films was 6 nm or more, which is 3 times thicker than those for Ag and Cu films. It is reasonable to infer that the small surface energy of Al films caused island-like initial film-growth of Au films deposited on Al films, resulting in the increase of Au capping layer thickness. Actually AMF images supported this consideration.
Au capping layer thickness necessary for bonding increased as the thickness of metal films increased. For instance, 20 nm-thick Au capping layer was necessary for bonding using 300 nm-thick Al films. Moreover, loading pressure was necessary for bonding using thick metal films. These were mainly caused by an increase of the surface roughness of the metal films. Necessary thickness of Au capping layer depended on materials of metal films, however, was 1/10 or less of the thicknesses of the metal films in the present thickness range.
Combined Surface Activated Bonding Technique for Hydrophilic SiO2-SiO2 and Cu-Cu Bonding
Authors: He Ran , Fujino Masahisa , Yamauchi Akira , Suga Tadatomo 
Published: February 2020

As an evolution of the Cu-Cu bonding and SiO2-SiO2 bonding, Cu/SiO2 hybrid bonding is a promising approach to the emerging three-dimensional (3D) integration of microelectronic/photonic systems, since it obtains both direct metal interconnection and enhanced thermal/mechanical stability with a seamless bonding structure during the single bonding process.1,2 However, because of the different features of Cu-Cu and SiO2-SiO2 bonding, Cu/SiO2 hybrid bonding at low temperatures of no more than 200 °C remains challenging. For instance, the Cu-Cu thermo-compression bonding is typically conducted in vacuum or dry protecting/reducing atmospheres after removal of surface oxides,3–7 while the SiO2-SiO2 bonding needs a humid environment to facilitate termination of Si-OH bonding sites.8–12 It is highly desired to develop a new bonding process that is effective for both Cu-Cu and SiO2-SiO2 bonding in H2O-free ambient, such as vacuum, for improvement of the Cu/SiO2 hybrid bonding.
Recently, we proposed a combined surface-activated bonding (SAB) method, which involves a combination of surface bombardment using a Si-containing Ar beam and prebonding attach-detach procedure prior to bonding in vacuum. High SiO2-SiO2 bonding strength of close to the Si bulk fracture strength has been realized at 200 °C. In this paper, we report our recent results of Cu-Cu and SiO2-SiO2 bonding by using the combined SAB method. The mechanism is discussed to understand the present low-temperature bonding technique.

References

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7. A. Shigetou, T. Itoh, K. Sawada, and T. Suga, IEEE Trans. Adv. Packag., 31, 473–478 (2008).
8. Q.-Y. Tong and U. M. Gösele, Adv. Mater., 11, 1409–1425 (1999).
9. T. Suni, K. Henttinen, I. Suni, and J. Mäkinen, J. Electrochem. Soc., 149, G348–G351 (2002).
10. F. Fournel et al., ECS J. Solid State Sci. Technol., 4, P124–P130 (2015).
11. H. Takagi, J. Utsumi, M. Takahashi, and R. Maeda, ECS Trans., 16, 531–537 (2008).
12. R. He, M. Fujino, A. Yamauchi, and T. Suga, Jpn. J. Appl. Phys., 54, 030218 (2015).
(Invited) Low-Temperature Processed and Self-Aligned InGaZnO Thin-Film Transistor with an Organic Gate Insulator for Flexible Device Applications
Authors: Furuta Mamoru , Toda Tatsuya , Tatsuoka Gengo , Magari Yusaku 
Published: February 2020

Recently, metal-oxide thin-film transistors (TFTs) have attracted considerable attention for use in next-generation flat panel displays. An amorphous InGaZnO (IGZO) semiconductor is widely accepted as a promising channel material for TFT applications owing to its outstanding electrical properties. Moreover, since oxide semiconductor can be deposited even at room temperature by sputtering, it is recognized as a promising material for flexible device applications. From the standpoint of flexible devices, an organic insulating material is a good candidate for gate insulator (GI) even for the oxide thin-film transistors (TFTs).
In this presentation, a self-aligned and top-gated IGZO TFT with an organic gate insulator was demonstrated at a maximum processing temperature of 150 ºC. First, the controlling methods of the hybrid interface between the InGaZnO channel and the organic gate insulator were investigated. It was demonstrated that an organic protection layer of the IGZO channel and controlling the oxygen content in the IGZO channel are effective to achieve good performance TFTs at low processing temperature; however, it was also revealed that an excess oxygen acted as an electron trap existing at the IGZO/GI interface and degraded the TFT’s reliability. Second, carrier concentration in the IGZO was selectively controlled by helium plasma treatment with a substrate bias for source and drain (S/D) regions of self-aligned TFT. It was revealed that lateral diffusion from S/D extension to the IGZO channel was influenced by the doping methods.
We achieved a self-aligned and top-gated IGZO TFT with an organic gate insulator that was fabricated at a maximum processing temperature of 150 ºC. Field effect mobility of over 10 cm2/Vs and subthreshold swing of below 0.2 V/dec. have been obtained. Details will be discussed at the conference.
(Invited) Selection of Channel Layer for the Vertical Oxide TFT
Authors: Park Sang-Hee Ko , Yeom Hye-In , Hwang Chi-Sun , Moon Geumbi , Ko Jong-Beom , Nam Yunyong 
Published: February 2020

With the development of the virtual reality and augmented reality displays, ultra-high resolution displays become one of the big concerns. People would not be bothered by display pixels when taking closer look at display with the resolution higher than 2000 ppi. The most important factor in the ultra-high resolution display is the pixel area and the smallest TFT size would be the first criteria in the TFT point of view.
Although back channel etch (BCE) TFT and self-aligned (SA) TFT have been used for driving high resolution LCD and OLED, respectively, typical planar structured TFT would not permit display with ultra-high resolution. The vertical TFT with the smallest pixel pitch value among the TFT structures is suitable candidate. Furthermore, channel length of the vertical TFT can be precisely controlled by the thin film thickness of spacer. This results in high and uniform on-current of TFT. Meanwhile, vertical TFT can also provide channel length longer than the sub-pixel length. When we have to apply high gate voltage depending on the display mode, TFT with longer channel length within smaller sub-pixel size would be necessary.
One of the advantages of oxide TFTs lies in the freedom of selection of architecture, materials, and process depending on the device application. Considering the main issue in the vertical TFT, the step coverage of active layer, oxide TFT seems to be the best selection. Oxide semiconductor and gate insulator used for the oxide TFT can be deposited by means of plasma enhanced atomic layer deposition (PEALD), which provides excellent step coverage of films.
One of the issues in vertical oxide TFT is the relatively high off-current depending on the mobility of TFT due to the short channel length. Here, we compare the performance of vertical oxide TFTs with the variation of semiconductor’s carrier density. By virtue of the easiness for the modifying carrier concentration of InOx based semiconductor, we could adjust the mobility of vertical TFT with low off-current. Vertical TFT with InOx shows 1.26 mA at Vg = 5 V and Vds = 2.1 V, S.S of 0.14 V/dec., on/off ratio of 107, and Von of -1.8V. Meanwhile at the same driving condition, IGZO shows on-current of 0.23 mA, S.S of 0.12 V/dec., on/off ratio of 108 and Von of -0.2V.
We will discuss the best selection for the channel layer of vertical TFT depending on the display mode and show the optimized TFT performance depending on the carrier concentration of semiconductors.