Simulation Comparison of Self-Heating Effects in Junctionless Nanowire Transistors and FinFET Devices
Authors: Mariniello Genaro , Pavanello Marcelo 
Published: February 2020

I. Introduction
In order to reduce the short channel effects, junctionless nanowire transistors (JNT) can be a very interesting option once it avoids the lateral diffusion of impurities from source and drain regions to the channel. In addition, as they are a multiple gate devices it is possible to improve the electrostatic control over the channel charges [1-4]. While the channel in state-of-art nFinFET devices is undoped or lightly doped with p-type impurities, n-type JNT have a uniform heavy concentration of donor impurities from source to drain, which simplifies the device fabrication, once it dispenses complicated annealing techniques [5-6]. A schematic view and a longitudinal-section of n-type JNT and FinFET devices are shown on Fig. 1.
As demonstrated in Fig. 1 JNT and FinFET are made using Silicon-On-Insulator (SOI) substrates. The thermal resistance associated to the buried oxide is in order of 100 times larger than silicon. Thus, both device alternatives can suffer from the difficulty of dissipating the heating of the silicon film caused by the Joule effect thanks to the current conduction, the so-called self-heating effect (SHE). This paper aims at comparing the self-heating effects (SHE) between FinFET and JNT devices using three-dimensional simulation. II. Devices Characteristics
The comparison of SHE between JNT and FinFET devices by means of three-dimensional numerical simulations has been performed with Synopsys Sentaurus Device simulator [10]. Both JNT and FinFET devices have been simulated with gate oxide thickness of 2nm, channel length (L) of 0.5 µm and 1 µm, fin width (Wfin
) of 10 nm and 20nm, fin height (Hfin
) of 60 nm and 10nm. For the JNT P+ polysilicon was used as gate material. The JNT has been doped uniformly with 5x1018 cm-3 and 1x1019 cm-3 with n-type impurities, while the channel region of FinFET has been doped with 1x1015 cm-3with p-type impurities. In order to avoid the series resistance, the drain and source extensions were simulated with 5nm. The buried oxide thickness is 100 nm. The simulations have been done with isothermal grid at 300K where there is no self-heating effect (hereafter mentioned as without SHE) as well as with thermal contact at the buried oxide allowing the thermal generation to be accounted in the several grid points (hereafter mentioned as with SHE). III. Results and analysis
Fig.2 and Fig. 3 present the behavior of the drain current as a function of gate voltage for FinFET and JNT. It is possible to compare the simulations with and without SHE, which present the same behavior i.e., there is no clear SHE due to the lower VD (50mV) resulting in lower static power (P = VD.ID
). According to the results obtained for lower VD, it is possible to confirm that those simulations are calibrated for analysis with higher VD values since their behavior are the same, independently if accounting or not the silicon film heating. On the other hand, when the VD increased to 1.5V, it is clearly visible the presence of the SHE in both JNT and FinFET as the current with non-isothermal grid is smaller than with isothermal one, thanks to the mobility degradation due to temperature rise. Finally, Fig. 4 shows the curves for the difference between drain current without SHE and with SHE (ΔID
), for the same VGT as a function of the power with SHE. The results show that, for the same power level, the ΔID is higher in FinFET devices i.e, the self-heating effect degrades the drain current much more than compared in JNT. Conclusions
According to the results simulated, JNT suffer less self-heating effect when compared with a similar FinFET devices due to the decreasing of the mobility variation with temperature.
acknoledgment
The authors acknowledge CAPES, FAPESP and CNPq for the financial support.
References

D. Hisamoto et al., IEEE Transactions on Electron Devices, vol.47 , pp. 2320-2325, 2000.

J. T. Park et al., IEEE Electron Device Letters, vol.22, pp. 405-406, 2001.

J. P. Colinge et al., IEEE Electron Device Letters, vol.24, pp. 515-517, 2003.

J. P. Colinge et al., Proceeding of IEEE International SOI Conference, pp. 1, 2009.

C. W. Lee et al., Appl. Phys. Lett., vol. 94, no. 5, p. 053 511, Feb. 2009.

J. P. Colinge et al., Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.

G. Mariniello et al., Symposium on Microelectronics Technology and Devices (SBMICRO) 2013 v.1 p1-4.

A. Kranti et al., Solid-State Electronics, vol. 65-66, pp. 33-37, Dec. 2011.

S. Zimin et al., Proc. ICSICT, 1998, pp. 572-574.

Sentaurus Device User’s Manual, Synopsys, 2013.

Figure 1