SiC Wafer Bonding and Deep Reactive Ion Etching Towards High-Aspect Ratio SiC MEMS Fabrication
Authors: Luna Lunet E , Hobart Karl D. , Tadjer Marko J , Myers-Ward Rachael L. , Anderson Travis J. , Kub Francis J 
Published: February 2020

Recent advances in SiC substrate quality and in the development of high aspect ratio reactive ion etching of SiC microstructures [1] have increased SiC fabrication feasibility and its potential for adaption in scalable optoelectronics [2] and microelectromechanical systems (MEMS). SiC is a wide band gap semiconductor that is suitable for high-power, high-temperature, highly reactive and mechanically strenuous environments. While the ability of SiC to withstand extreme conditions is desirable for harsh applications, it is this same durability that instigates restrictions or difficulties in SiC processing that are not present for Si; however, such process challenges do not outweigh the benefits of SiC.
This work specifically tackles the processing challenges for SiC MEMS based on semiconductor-on-insulator structures. The importance of this topic can be viewed through the success of silicon-on-insulator (SOI); SOI wafers expanded the versatility of Si technology by enabling devices with increased switching speed and increased radiation hardness [3] as well as a platform for MEMS devices [4]. In the same vein, silicon carbide-on-insulator (SiCOI) wafers cast an even wider net, enabling SiC MEMS technology that leverages standard Si-based bulk micromachining processes [5] to produce unique device performance [6] and releasable microstructures [7]. However, in progressing towards monolithic SiC MEMS, feasible SiC wafer bonding techniques along with deep etching of high aspect ratio SiC microstructures is still needed to level the playing field between Si and SiC processing capabilities.
In this work, the use of Si is avoided entirely and a high-yield wafer bonding and etch process of SiC/Insulator/SiC stacks is presented. The replacement of Si with SiC as a handle wafer allows for the design of all SiC-based MEMS devices for high shock resistant and temperature applications. The fabrication process begins with a thorough cleaning of 4H-SiC wafers followed by SiO2 deposition with a tetraethyl orthosilicate (TEOS) precursor via low-pressure chemical vapor deposition (LPCVD) at 750 °C. The oxide covered wafers were annealed to 1100 °C for 2 hours to densify and outgas the oxide. The SiO2 (up to 4 µm) on the Si-face was then chemically mechanically polished down to a final thickness of 3 µm thickness and a root-mean squared (RMS) roughness < 0.5 nm suitable for bonding (Figure 1). Prior to bonding, the wafers undergo additional cleaning processes to ensure a clean bonding interface. Direct wafer bonding of the Si faces of two SiC wafers was achieved in a class-100 cleanroom using a modified plasma bonding technique. The bonding was initiated by applying a local force to the center of the aligned wafers; the bond then propagates from the center to the wafer edge. Additionally, a post bond anneal at 1100 °C was used to achieve fusion strength.
The bonded SiC wafers were electroplated with 1.7 - 2 μm Ni hard mask [1] and then diced into 10 mm x 10 mm coupons for anti-bosch etch experiments to produce deep SiC trenches [8]. An anti-bosch process describes a recipe that alternates between two SF6/O2 segments; one segment is designed to etch SiC, while the other segment is designed to remove sidewall passivation. This is contrary to the well-established Bosch process for Si which uses one segment to etch Si and the other to passivate the sidewalls. The anti-bosch process for SiC was designed to etch through the device layer and stop on the buried oxide; after which, the hard mask and seed metals were removed. Lastly, the etched microstructures were released with vapor hydrofluoric acid (HF). Figure 2 summarizes the process flow and Figure 3 shows the etch results achieved on 4H-SiC and 4H-SiC/SiO2/4H-SiC samples. The efficacy of the outlined process is demonstrated through successful actuation of fabricated structures (Figure 4). Overall, this work demonstrates a process for effective SiC wafer bonding and SiC etching in the presence of buried oxide in order to fabricate high-aspect ratio SiC MEMS.
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Figure 1