(Invited) Full Wafer CMOS-Compatible Integration of Ge with Si By Direct Wafer Bonding
Authors: Gity Farzan 
Published: February 2020

Silicon is the base material for electronic technologies and has emerged as a very attractive platform for photonic integrated circuits (PICs). PICs allow optical systems to be made more compact with higher performance than discrete optical components. Some of the applications of PICs are in the areas of fibre-optic communications, biomedical devices, photovoltaics and imaging. Germanium, due to its low bandgap, maturity and compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infrared wavelengths. In the integration of Ge with Si a high-quality defect-free, 100% Ge layer is desirable for realising high-performance photodiodes. Low defect density in the Ge layer will lower the dark current by minimising the leakage mechanisms and noise sources. There are two main approaches for Ge/Si integration: epitaxial growth [1] and wafer bonding [2]. Lattice mismatch of ~4.2% between Ge and Si is the main problem of the former technique leading to high density of dislocations and hence increased leakage current, while the bond strength and conductivity of the interface are the main challenges of the latter. Both result in the formation of trap states which are expected to play a critical role in the device performance. Understanding the physics of the interface is key in the design of Ge/Si devices.
In this talk, an alternative integration approach of low-temperature CMOS-compatible plasma activated direct wafer bonding, developed in order to accommodate the lattice mismatch, will be discussed. Electronic and optical devices fabricated exploiting this full wafer integration technique will be demonstrated. The focus will be on the physics of the heterojunction interface and its role in the band alignments. In the first part, a proof of concept of Ge/Si integration by using wafer bonding and layer exfoliation (Smart Cut™ process) with low thermal budget will be outlined. Mesa diodes made by transferring a 700nm-thick Ge layer onto Si using this technique will be reported. Fabrication, characterisation, and analysis of the electrical transport across the interfacial oxide present between the Ge and Si wafers will also be discussed. Highly-doped n-type Si and p-type Ge wafers are used to allow the electric field distribution to drop within short distances from the interface enabling us to investigate the influence of bonded interface on carrier transport through the p-n junction. Effects of low-temperature annealing on the device performance and on the conductivity of the interface will be reviewed. The carrier transport mechanism is shown to be dominated by generation-recombination before anneal and direct tunnelling in forward bias and band-to-band tunnelling in reverse bias after annealing which are defined by the role of interface traps.
In the next part of the talk, we report on a remarkably-high responsivity photodiodes especially at low incident powers made by integrating low-doped p-Ge with highly-doped n-Si (p
−-Ge/n
+-Si heterojunction) by direct wafer bonding. The p
−-Ge/n
+-Si photodiode arrangement was selected to enable collection of electrons into the Si due to the more favourable band-offset. Responsivities in excess of 3.5 A/W at wavelength of 1.55 µm under surface normal illumination is measured for photodiodes with 5.4 µm Ge layer transferred onto Si by wafer bonding followed by chemical mechanical polishing (CMP). Detailed analysis regarding the temperature-dependent carrier transport across the junction and the band alignments at the interface will be presented. The high responsivity of the detectors is shown to be due to light-induced potential barrier lowering at the interface. To our knowledge, this is the first report of light-gated responsivity for vertical illuminated Ge/Si photodiodes.
The developed wafer bonding process followed by either layer exfoliation or CMP is a low-temperature wafer-scale process. The unique results discussed in this talk are compatible with surface normal illumination and are capable of being integrated with CMOS electronics and readout circuits in the form of 2D arrays of detectors. One potential future application is a low-cost back-end-of-line compatible dual-band near infrared/visible cameras.
[1] Y. Kang, et al., Nature Photonics, pp. 59-63, 2009.
[2] H. Kanbe, et al., Japanese Journal of Applied Physics, pp. L644-L646, 2006.
The figure shows a schematic illustration of a Ge/Si photodiode made by wafer bonding followed by CMP. The XTEM images confirm the presence of interfacial amorphous layer at the bonded interface. Photoresponse of the detector as a function of input optical power at a wavelength of 1.55 µm is also presented at two different temperatures. Schematic representation of the band diagram at the Ge/Si interface at equilibrium and under illumination is shown indicating the potential barrier lowering due to filling of acceptor-type traps at interface by the photogenerated carriers.

Figure 1