(Invited) A Deep Level Transient Spectroscopy Study of Hole Traps in GexSe1-x-Based Layers for Ovonic Threshold Switching Selectors
Authors: Hsu P.-C. , Simoen Eddy Roger , Lin D , Stesmans Andre , Goux Laurent , Delhougne Romain , Kar Gouri Sankar 
Published: February 2020

GeSe-based amorphous compounds are excellent candidates for the fabrication of Ovonic Threshold Switching (OTS) selectors in two-terminal high density Storage Class Memories (SCM) [1]. In the as-deposited state, the layer is amorphous but it can be transformed into a low-resistive state above a certain threshold voltage. Good thermal stability of the layers is of crucial importance [1] and is closely linked to the defectiveness [2], which also defines the carrier transport. In such OTS materials, the current cannot be described in terms of the classical drift-diffusion theory, assuming a well-defined band gap. Instead, it has been shown that carriers are localized in the deep potential of attractive traps, where they move by field-assisted hopping [3]-[5]. Characterization of the trap states is thus key to the understanding of the transport and the stability/drift of the layers. One of the standard methods to study deep level traps in semiconductors is Deep Level Transient Spectroscopy (DLTS), which has also been applied in the past to amorphous materials. The aim of the present paper is to apply this method to the study of the Physical Vapor Deposited GeSe layers on p-type silicon substrates. As will be shown, the observed hole traps around activation energies in the range of 0.2 eV to 0.5 eV exhibit a broad distribution of states and non-exponential trap filling kinetics. This will be discussed in view of the transport mechanisms in the layer.
For DLTS, Metal-Insulator-Semiconductor (MIS) structures have been prepared by the deposition of 20 or 50 nm of GexSe1-x with x~0.5 on p-type CZ silicon substrates; deposition of an Al gate completes the fabrication of the devices, with a structure schematically represented in Fig. 1. The Capacitance-Voltage (C-V) characteristics typically exhibit a significant flat-band voltage shift with temperature T (Fig. 2), which should be accounted for when performing DLTS on such capacitors by adjusting the reverse and pulse bias. Comparing the results of two layers deposited under different conditions in Figs 3 and 4 indicates that the hole trap peak in DLTS changes both in amplitude (the trap concentration) and temperature position, i.e., the activation energy. The latter is derived from the slope of the modified Arrhenius plot of Fig. 5. Values in the range of 0.2 eV to 0.5 eV with respect to the valence band maximum in GeSe have been observed, which is in line with the density of states extracted from ab initio Density Functional Theory (DFT) calculations [2]. A final experimental observation is demonstrated in Fig. 6, showing the evolution of the hole trap filling as a function of the bias pulse time tp. Widely different behavior can be observed, which is not typical for point defects. In conclusion, it can be stated that the feasibility (and reproducibility) of DLTS on these structures has been validated. At the same time, it is clear that a meaningful extraction of the trap parameters should account for the specific transport mechanisms in the amorphous GeSe material.
[1] B. Govoreanu et al., in 2017 Symp. On VLSI Technol. Dig. Of Techn. Papers, IEEE Explore, p. 92 (2017).
[2] S. Clima et al., in Int. Electron Devices Meeting (IEDM17) Techn. Dig., IEEE Explore, p. 79 (2017).
[3] D. Ielmini and Y. Zhang, J. Appl. Phys., 102, 054517 (2007).
[4] D. Ielmini, Phys. Rev. B, 78, 035308 (2008).
[5] A. Calderoni, M. Ferro, D. Ielmini and P. Fantini, IEEE Electron Device Lett., 31, p. 1023 (2010).

Figure 1