Copper Oxide Direct Bonding of 200mm CMOS Wafers with Five Metal Levels and TSVs: Morphological and Electrical Characterization
Authors: Cavaco Celso , Peng Lan , Lavizzari Simone , Claes Jesse , Hoovels Nele V. , Guerrieri Stefano , Tezcan Deniz Sabuncuoglu , Osman Haris 
Published: February 2020

Copper oxide bonding using standard damascene process is a top candidate in 3D integration schemes and successful bonding is reported [1]–[3]. Some of the main challenges in this technology are the dishing of the copper pads, the oxide erosion and the bonding accuracy, which are difficult to control and optimize as the wafer size increases and the device size decreases.
Although challenging, we report for the first time complete data on 200mm wafer to wafer aligned copper oxide direct bonding of wafers with five metal levels each and with through-silicon-vias (TSVs) as backside connection. TSVs are used as backside connection as they are known to have several advantages for CMOS image sensors. Main advantages are allowing the size of the camera module to be reduced by using TSVs (and eventually microbumps) as an alternative to wire bonding, as well as simplifying the image sensor wafer level packaging [4].
The reported 200mm wafers are representative of a real CMOS device as they are processed with five metal levels in 130nm Cu BEOL CMOS technology. A copper damascene process was employed in which both via and metallization levels required a sequence of material deposition, chemical mechanical polishing (CMP) and cleaning for each layer in both wafers. The bonding was performed at low temperature under atmospheric pressure and an alignment accuracy below one micron was reached. After bonding, the top wafer was thinned down to the required final thickness and electrical connection to either chip was achieved through a via last process [5].
Void free wafer level scanning acoustic microscope (SAM), Figure 1, as well as focused ion beam (FIB) of the Cu TSVs connection to the bond pad and bonding interface, Figure 2, are shown to evidence the morphologic quality of both bonding interface and TSV backside connection process.
Resistance and kelvin structures, as well as daisy chains with up to 2500 pads and different geometries, linear and interwoven, were used to assess the electrical behaviour of the bonded structures. To evaluate the quality of the bonded stack, electrical data here shown was measured between the bottom metal of each wafer of the bonded wafer pair, referred in Figure 3 as M1 Top and M1 Bottom.
By means of a four-point measurement, resistance structures with 300-micron length by one-micron width, allow extracting a sheet resistivity of 55±3 mOhm/square, which is in line with the target value of 57 mOhm/square.
For kelvin structures between M1 Top and M1 Bottom, where four vias between each metal connection are used, a contact resistance of 1.40±0.05 Ω/contact was measured. However, the measured value is higher than the target value of 1.05 Ω/contact. The observed discrepancy in resistance might be explained by a lower than expected via yield between connections. Simulations considering a 75% via yield between metal levels show a target contact resistance that matches the measured value of 1.40 Ω/contact.
For daisy chains between M1 Top and M1 Bottom, a contact resistance of 1.90 ± 0.05 Ω/contact was measured, which is in line with target value of 1.91 Ω/contact.
Regarding yield, measured kelvin structures show a 95% yield, while daisy chains show a yield up to 80% for chains with 8 pads and up to 45% for chains with 2500 pads, Figure 4. Yield was defined as target value ± 0.2Ω/contact.

References

[1] L. Di Cioccio, I. Radu, P. Gueguen, and M. Sadaka, ‘Direct bonding for wafer level 3D integration’, in 2010 IEEE International Conference on IC Design and Technology (ICICDT), 2010, pp. 110–113.
[2] L. D. Cioccio, I. Radu, G. Gaudin, T. Lacave, F. Baudin, M. Sadaka, and T. Signamarcheix, ‘(Invited) Low Temperature Direct Bonding 3D Stacking Technologies for High Density Device Integration’, ECS Trans., vol. 58, no. 9, pp. 17–28, Aug. 2013.
[3] P. Enquist, ‘Scalable direct bond technology and applications driving adoption’, in 3D Systems Integration Conference (3DIC), 2011 IEEE International, 2012, pp. 1–5.
[4] J. P. Gambino, S. A. Adderly, and J. U. Knickerbocker, ‘An overview of through-silicon-via technology and manufacturing challenges’, Microelectron. Eng., vol. 135, pp. 73–106, Mar. 2015.
[5] C. Cavaco, L. Peng, K. De Leersnijder, S. Guerrieri, D. S. Tezcan, and H. Osman, ‘Copper Oxide Direct Bonding of 200mm CMOS Wafers: Morphological and Electrical Characterization’, Int. Symp. Microelectron., vol. 2015, no. 1, pp. 594–597, Oct. 2015.

Figure 1