bluuebunny/crossref_metadata_2025_split huggingface dataset:
A Simple FIB Method for Constructing Electrically Isolated Microprobe Pads for the Electrical Analysis of Failing 0.12μm Technology SRAM Bit Cells
Authors: Mulder Randal 
Published: December 2020

Abstract
This paper provides failure analysis engineers a simple method for constructing probe pads on failing 0.12um SRAM bit cells using the FEI 820 Focused Ion Beam (FIB) tool. This method allows for the easy location of the failing bit cell, results in good electrical isolation, and only takes a minimal amount of FIB time (2 hours for 6 pads). The method is effective for all technologies 0.12um or greater with a high success rate once the analyst is proficient in its use. Once probe pads have been constructed, it is then relatively easy for an analyst to perform electrical analysis to identify the defect type and location causing the bit cell failure before the physical analysis is performed.
On-Die Parametric Analysis of SRAM
Authors: Mauck Benjamin M. , Ravichandran Vishnumohan , Mughal Usman Azeez 
Published: December 2020

Abstract
Parametric analysis of microprocessor SRAM through special design for test features (DFT) is used extensively by fault isolation and failure analysis engineers to find and characterize defects. While regular raster and special cache patterns (i.e. weak-write test mode) detect many stuck-at faults, a parametric analysis is needed to identify which defect mechanism is the cause of a cache failure. Pico-probing is the most common method of parametric analysis on SRAM cells, but is becoming increasingly difficult on smaller geometries. These curves can also be taken non-destructively by muxing any bitline (BL) and bitline_bar (BL#) of an internal cache to an I/O pin and sweeping these pins with an external PMU (a test mode known as low yield analysis, or LYA). Unfortunately, a growing amount of leakage on each new process is distorting these LYA testmode I-V curves, making it increasingly difficult to find and differentiate defects. The goal of this paper is to discuss the simulation and silicon results of a concept On-Die LYA (ODLYA) circuit implemented in a 65 nm CMOS process technology. ODLYA is used to curve-trace individual transistors within an SRAM cell and read out results in an automated fashion. Taking measurements on-die eliminates interconnect-dominated IR drop and leakage distortion from several levels of multiplexing. The proposed implementation enables non-destructive high-speed parametric analysis with less dependency on growing cache sizes, number of cores, and scaling process technologies.
The Root of All “IVA”—A Quantitative Analysis of LSIM Bias/Detection Systems
Authors: Levin T. M. 
Published: December 2020

Abstract
The transfer functions of the bias/detection circuits used in various laser signal injection microscopy (LSIM) techniques, especially for those using constant current bias/detection schemes, are largely unknown. This article provides both qualitative and quantitative measures of various LSIM bias/detection schemes to develop a more complete understanding of the varying measurement systems. The authors have measured the characteristics of a variety of bias/detection circuits in ways that are similar to the characterization of a linear integrated circuit. They have concentrated on examining the frequency response, pulse response, and noise levels. It was found that the LSIM bias/detection systems have widely varying characteristics which, in turn will affect how they can be optimized. Furthermore, the relationship between the frequency and noise characteristics of the bias/detection systems and the input signal that is to be detected point to differing ways in which the systems can be modified for improved performance.
Logical-to-Physical Device Navigation using Place-and-Route Data as an Alternative to LVS
Authors: Nicholson Roger 
Published: December 2020

Abstract
Logical-to-physical device navigation for failure analysis is often used to drive physical probers and focused ion beam tools. Traditional methods of creating navigation data rely upon the use of time consuming Layout-versus-Schematic (LVS) based methods. By using existing place-and-route data, full cross-linked navigation between schematic and physical layout may be achieved in a fraction of the time that it takes for the LVS methods to be used. Place-and-route data offers significantly more information to the analyst than LVS based data.
Development of a Circuit Edit Process Scalable in Dimension and Material
Authors: Makarov Vladimir V. , Antoniou Nicholas 
Published: December 2020

Abstract
The ability to edit a circuit in silicon quickly and confidently is extremely valuable as it permits verification of changes or fixes without the need to generate new reticles and fabricate new silicon. However, dramatic changes in the material used in IC’s combined with the downward scaling of dimensions required the development of a scalable process not only in three dimensions but also in material. Details of this process and results are presented in this paper.
A Novel Method to Inspect Deep Trench Capacitor Planar Profiles in DRAM
Authors: Lue J. L. , Huang A. , Wang T. 
Published: December 2020

Abstract
This paper presents a novel method to inspect deep trench (DT) planar profiles at any particular depths using the mechanical polishing method instead of the Focused Ion Beam (FIB) milling method. The sample is polished at a small beveled angle and then inspected in the Scanning Electron Microscope (SEM). This method creates a large area for the inspection of DT profiles. It is accurate and fast in providing the result on process evaluation and failure analysis. Since the FIB is not needed, it is also simple and cost effective.
Microelectronic Packages (FC with Ceramic Substrates) Solder Removal Method for Failure Analysis
Authors: Shih T. I. , Chen Tung Hung 
Published: December 2020

Abstract
In order to do the failure analysis on flip chip connected with ceramic substrate, solder bump should be completely removed from chip surface. The die soldered on ceramic substrate of flip chip package is likely damaged during the removing process for the high etching and abrasion resistance of ceramic substrate as well as the poor uniformity of mechanical polish. In this paper, a thermal method for the decapsulation of flip chip package is developed, which included heat sink removal, ceramic substrate and solder bump separation, and solder residue clean out from the chip surface. In the last step, three temperature levels of H2N2O6 – H2O (fuming Nitric acid) were selected for the removal of eutectic, high-lead and lead free solders, respectively.
Note on the Use of Principal Component Analysis (PCA) and Clustering for the Analysis of Wafer Level ATPG data
Authors: Ramanujachar Kartik , Draksharam Satish 
Published: December 2020

Abstract
This article explores the use of principal component analysis (PCA) and hierarchical clustering in the analysis of wafer level automatic test pattern generation (ATPG) failure data. The principle of commonality is extended by utilizing hierarchical clustering to collect die that are more similar to one another in their manner of failure than to others. Similarity is established by PCA of the patterns that the die in a wafer fail. Results demonstrated that PCA analysis and clustering are useful tools for dimensionality reduction and commonality analysis of wafer level ATPG data. The utility of PCA analysis and clustering in the extraction of die for physical failure analysis is also illustrated.
130nm Backend Reliability Failures—Analysis to Corrective Action
Authors: Garteiz Gil , Zylberman Amir 
Published: December 2020

Abstract
Tower successfully completed a product qualification of its 130nm copper process this year. The key to this achievement was finding and eliminating a dominant failure mechanism, which appeared during HTOL stress. This paper will cover the failure analysis, in-line problem identification, and corrective actions taken that eventually lead to successful product qualification.
Analysis of Delta Iddq Soft Fails on Pass Chips
Authors: Österreicher I. , Eckl S. , Tippelt B. , Döring S. , Prang R. , Werner W. 
Published: December 2020

Abstract
Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.
Challenges in Evaluating Thickness, Phase, and Strain in Semiconductor Devices Using High Resolution Transmission Electron Microscopy
Authors: Rai Raghaw , Conner James , Murphy Sharon , Subramanian Swaminathan 
Published: December 2020

Abstract
The aggressive scaling of metal oxide semiconductor field effect transistor (MOSFET) device features, including gate dielectrics, silicides, and strained Si channels, presents unique metrology and characterization challenges to control electrical properties such as reliability and leakage current. This paper describes challenges faced in measuring the thickness of thin gate oxides and interfacial layers found in high-K gate dielectrics, determining Ni silicide phase in devices, and characterizing strain in MOSFETs with SiGe stressors. From case studies, it has been observed that thin layers (gate oxide, high-K film thickness, and interfacial layer) can be measured using high-resolution transmission electron microscopy (HRTEM) with good accuracy but there are some challenges in the form of sample thickness, damage-free samples, and precise sectioning of the sample for site-specific specimens. Complementary information based on HRTEM, annular dark field, and image simulation should be used to check the accuracy of thin gate dielectric measurements.
Vanishing TiN ARC Coating as an Indicator of EOS in Aluminum Top Metal Lines
Authors: Barbieri Thomas J. , Wang James , Kottke Mike , Theodore David , Wetz Richard 
Published: December 2020

Abstract
Multiple parts failed during a 96 hour HAST (highly accelerated stress test) run. Electrical failure occurred on several pins stressed at 48V during the run. Visual inspection identified possible corrosion damage occurring on a top layer aluminum metal line linked to the failed pins. Additionally, significant lengths of this line and metallization at six other sites appeared white and reflective when viewed through an optical microscope. The device technology utilized a TiN ARC. Aluminum metal with a TiN ARC has a dull, amber color when viewed through an optical light microscope, as opposed to bare aluminum, which appears white and shiny. The initial assumption was that the passivation had lifted off during mold compound removal, along with the top TiN ARC layer at these seven locations. SEM inspection found that final passivation film was still intact over these shiny Al lines, but it was cracked extensively. Neighboring Al lines did not show cracked passivation. A hypothesis was generated that suggested that the TiN ARC was not removed, but rather was altered in some way so as to change its optical appearance. The change in the TiN was believed to be due to a combination of factors that resulted from electrical overstressing of the lines during HAST. A series of experiments utilizing FIB cross-sections, Auger mapping, Auger depth profiling, TEM inspection and EDS were used to show that the TiN ARC layer was still present on the affected lines but had been oxidized. The conclusions drawn from this investigation can be used to rapidly determine the root cause of failure through signature analysis. Shiny Al metal lines are easy to see with optical microscopes and are therefore a useful failure analysis tool to identify electrically and mechanically overstressed lines and circuits.
Nanoprobing Application on Characterization of 6T-SRAM Single Bit Failures with Different Gox Breakdown Defect
Authors: Lin Cheng-Piao , Tang Chin-Hsin , Wu Cheng-Hsu , Ting Cheng-Chun 
Published: December 2020

Abstract
This paper analyzes several SRAM failures using nano-probing technique. Three SRAM single bit failures with different kinds of Gox breakdown defects analyzed are gross function single bit failure, data retention single bit failure, and special data retention single bit failure. The electrical characteristics of discrete 6T-SRAM cells with soft breakdown are discussed and correlated to evidences obtained from physical analysis. The paper also verifies many previously published simulation data. It utilizes a 6T-SRAM vehicle consisting of a large number of SRAM cells fabricated by deep sub-micron, dual gate, and copper metallization processes. The data obtained from this paper indicates that Gox breakdown location within NMOS pull-down device has larger a impact on SRAM stability than magnitude of gate leakage current, which agrees with previously published simulation data.
A New Approach for SRAM Soft Defect Root Cause Identification
Authors: Egger Peter , Müller Stefan , Stiftinger Martin 
Published: December 2020

Abstract
With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.
Laser Assisted Lock-In Phase & Spectral Analysis Techniques at Advanced IC Failure Analysis with Application to Jitter and Soft-Defects
Authors: Brillert Christof , Qian Zhongling , Burmer Christian 
Published: December 2020

Abstract
New developments concerning lock-in phase detection and spectral analysis techniques applied to accessible IC signals are introduced in detail. These techniques combine the thermal laser stimulation (TLS) with the high sensitivity of lock-in to phase variation or the selectable frequency detection in spectrum analyzer. The difference to normal lock-in techniques utilizing pulsed lasers is exemplary pointed out. Moreover the applications to phase related soft-defects and to a design related jitter problem are shown. The power of such techniques for direct mapping a signal path is shown. Further benefits of lock-in phase methodology and spectral analysis technique applied to 65 nm and 90 nm technology is presented and illustrated using different case studies.
Localization of Cu/Low-k Interconnect Reliability Defects by Pulsed Laser Induced Technique
Authors: Tan T.L. , Quah A.C.T. , Gan C.L. , Phang J.C.H. , Chua C.M. , Ng C.M. , Du A.-Y. 
Published: December 2020

Abstract
In this paper, the application of pulsed-TIVA for the localization of Cu/low-k interconnect reliability defects in comb test structures is described. Two types of subtle dielectric defects which are otherwise not detectable with conventional TIVA can be detected with pulsed-TIVA.
Silicon Dislocation Enhanced by Dynamic Voltage Stress
Authors: Lin Yu-Cheng , Chen Rock , Liang Sanan , Liao Scott , Niou Chorng , Chien W.T.Kary 
Published: December 2020

Abstract
In reliability test some chips suffered functional failure. Through a series of failure analysis experiments, the root cause was determined to be a silicon dislocation across LDD (Lightly Doped Drain) area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocations already existing before CP and FT. To prove this hypothesis, an experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD area, which may induce reliability failure. Moreover, reliability concerns on this finding will be discussed in this paper.
Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) Localization of 32nm SOI SRAM Array Failure
Authors: Kane Terence , Tenney Michael P. 
Published: December 2020

Abstract
The technique of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identfication of FEOL defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed [1]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) of discrete MOSFET and SOI embedded dynamic ramdon access memory devices (eDRAM) without the time consuming delayering methods of conventional scanning capacitance microscopy have also been highlighted [2]. This paper is intended to describe the advantages of NCVS to localize defects in specific MOSFET devices at CA level as well as to identify resistive BEOL via interconnections and FEOL defective high k metal gate structures without the attendant time consuming delayering steps employed with classical SCM methods. Localization of a FEOL defect in a discrete 32nm SOI MOSFET device in SRAM array causing a vertical pair cell failure signature will be discussed.
The Novel TEM Sample Preparation Approach for Targeted via with Barrier/Cu Seed Layer Inspection
Authors: Hsieh Wen-Fei , Tseng Shih-Hsiang , She Bo Min 
Published: December 2020

Abstract
In this study, an FIB-based cross section TEM sample preparation procedure for targeted via with barrier/Cu seed layer is introduced. The dual beam FIB with electron beam for target location and Ga ion beam for sample milling is the main tool for the targeted via with barrier/Cu seed layer inspection. With the help of the FIB operation and epoxy layer protection, ta cross section TEM sample at a targeted via with barrier/Cu seed layer could be made. Subsequent TEM inspection is used to verify the quality of the structure. This approach was used in the Cu process integration performance monitor. All these TEM results are very helpful in process development and yield improvement.
Failure Analysis Methodology on Systematic Defect in ADC_PLL Ring Pattern Due to Plasma De-Chuck Process
Authors: Boon Ang Ghim , Changqing Chen , Quah Alfred , Magdeliza  , Jony Indahwan , Tat Lee Mern , Zhu David , Ping Neo Soh 
Published: December 2020

Abstract
In this paper, a low yield case relating to a systematic array of failures in a ring pattern due to ADC_PLL failures on low yielding wafers will be studied. A systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current imaging, layout path tracing, PVC and XTEM together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical in a wafer foundry in which there is minimal available data on the test condition setup to duplicate the exact failure. The ring pattern was due to systematically open via as a result of polymer built-up from plasma de-chuck issue. It would serve as a good reference for a wafer Fab that encounters such an issue.
Dynamic Power Analysis under Laser Stimulation: A New Dynamic Laser Simulation Approach
Authors: Deyine A. , Perdu P. , Sanchez K. , Courrège J.C. , Lewis Dean 
Published: December 2020

Abstract
Dynamic Laser Stimulation (DLS) techniques proved to be very efficient in soft defect localization bringing a lot of information about the device internal behavior. We need to use external parameter measurements such as frequency, delay, voltage etc to perform these techniques. So they can't be used to study internal signal propagation problems in latched device since signals are resynchronized. We will show that we can use the power analysis coupled with DLS techniques set up to characterize soft defect when we don't have a direct access to monitored signal propagation such as in some transistor transition issues. Laser stimulation in addition of power analysis is used to decrypt security codes in security chip, but in failure analysis it is a new way to reach internal information in order to localize soft defects.
Two-Photon Absorption Laser Assisted Device Alteration Using 1340nm CW Laser: Critical Timing Fault Isolation & Localization for 32nm MPU and Beyond
Authors: Niu Baohua , Pardy Pat , Davis Joe , Ortega Mel , Eiles Travis 
Published: December 2020

Abstract
In this paper, we report on the first observation and study of two-photon absorption (TPA) based laser assisted device alteration (LADA) using a continuous-wave (CW) 1340nm laser. The study was conducted using LADA systems equipped with high numerical aperture (NA) liquid and solid immersion lens objectives on Intel’s 45 nm and 32 nm multiprocessor units (MPU) and test chips. The power densities achievable using these lenses are similar to those reported in the literature for TPA in silicon of CW 1455nm light [1]. We show that the induced photocurrent has a quadratic dependence on the input laser power, a key indicator of two-photon phenomenon. Our results imply that even when using 1340nm wavelength CW lasers, there is a potential for laser invasiveness with the high power densities achievable using high NA objectives. Laser induced damage of the DUT is also a possibility at these high power densities, particularly with the solid immersion lens (SIL). However, we show that the DUT damage threshold can be increased by reducing the DUT’s temperature. Finally, we present results demonstrating a &gt;40% improvement in localization of critical timing faults using TPA based LADA, when compared to traditional 1064nm wavelength (single-photon absorption) LADA.
Advanced Laser Preparation of Microsystems for Further FIB Processing
Authors: Walter Juergen , Martens Stefan , Mack Walter 
Published: December 2020

Abstract
The trends towards 3D integration in microsystems technology and electronic packaging require that failure-analysis methods and target-preparation procedures are adapted to these emerging packaging technologies. The feasibility of laser-target preparation in microsystems is addressed in this paper, especially 3D integrated electronic devices. Various laser technologies were evaluated and the laser of choice was demonstrated to be appropriate for use with stacked packages. In addition, the laser preparation related Heat-Affected Zones (HAZs) were studied. The laser-energy absorption was determined by in situ heating-rate measurement, which enables precise prediction of HAZ extension by the use of Finite Element (FE) simulation. The advantage of this technique for removal rates compared to conventional techniques is discussed, as well as the combination of the excellent ablation rates of pulsed-laser ablation with the high accuracy of Focused Ion Beam (FIB) milling.