bluuebunny/crossref_metadata_2025_split huggingface dataset:
Fast and Precise 3D Tomography of TSV by Using Xe Plasma FIB
Authors: Hrnčíř Tomáš , Hladík Lukáš 
Published: December 2020

Abstract
3D tomography of TSVs was performed by combining Xe plasma FIB milling and lift-out techniques. This approach allows analyzing the structure of TSVs in detail using a method faster than the usual 3D tomography by Ga FIB and more precise than X-ray tomography. Both well-filled TSVs and TSVs with voids were analyzed and the results were compared. The analysis procedure was optimized in order to reduce the analysis time and to increase the throughput. The lift-out of the analyzed block of material was performed to obtain 90° angle between TSV and the ion beam axes, which is critical to reduce the curtaining effect and which allowed to increase FIB beam current significantly, reducing the analysis time.
Defect Isolation Tools Accelerate the Failure Analysis Process
Authors: Winterstrom Adam , Meehan Kevin , Sanchez Ralph , Ackerman Rich 
Published: December 2020

Abstract
This paper presents case studies that highlight the use of novel scan technologies and techniques to quickly test, diagnose, localize, and isolate the root cause of the defects, demonstrating that the solution meets the rapid and constant changing demands of industry. Cases include a device that has seemingly passed the functional test, but not the scan test with emission; a device with emission requiring resolution to its location; and a device having a timing issue that does not have emission. All case studies concluded with successful completion of finding the root cause of the defect. The diagnosis time for each of the three devices was within a period of one to three days per device. The confirmation stage of the defect is the longest lead time of the diagnostic process.
Implications of Helium and Neon Ion Beam Chemistry for Advanced Circuit Editing
Authors: Wu H. , Ferranti D. , Stern L.A. , Xia D. , Phaneuf M.W. 
Published: December 2020

Abstract
Gallium focused ion beams (Ga-FIB) have been used historically in the semiconductor industry for failure analysis, as well as circuit edit. However, in spite of the best of these efforts, as integrated circuit dimensions continue to shrink, Ga-FIB induced processes are being driven to their physical limits. The main purpose of this paper is to report the helium and neon ion beams' induced chemistry, including metal deposition, dielectric deposition, and chemically enhanced etching. Two simple examples are shown as proofs of concept demonstrating gas field ion source (GFIS) development for circuit edit applications. The paper summarizes the general utility of helium and neon ion beams for metal deposition, dielectric deposition, and sputtering and etching processes, and discusses some of the technical challenges associated with current GFIS technology. Using GFIS ion beams, it has been observed that the top and buried metal lines can be cut precisely and then reconnected.
Failure Analysis Due to Slightly Unetched Hard Mask Using Nano Probe
Authors: Lee Jong Hak , Kim Jong Eun , Park Chang Su , Kim Nam Il , Moon Jang Won , Kim Jong Chae , Son Soo Yong , Yoo Kyung Dong , Hong Sung Joo 
Published: December 2020

Abstract
In this work, a slightly unetched gate hard mask failure was analyzed by nano probing. Although unetched hard mask failures are commonly detected from the cross sectional view with FIB or FIB-TEM and planar view with the voltage contrast, in this case of the very slightly unetched hard mask, it was difficult to find the defects within the failed area by physical analysis methods. FIB is useful due to its function of milling and checking from the one region to another region within the suspected area, but the defect, located under contact was very tiny. So, it could not be detected in the tilted-view of the FIB. However, the state of the failure could be understood from the electrical analysis using a nano probe due to its ability to probe contact nodes across the fail area. Among the transistors in the fail area, one transistor’s characteristics showed higher leakage current and lower ON current than expected. After physical analysis, slightly remained hard mask was detected by TEM. Chemical processing was followed to determine the gate electrode (WSi2) connection to tungsten contact. It was also proven that when gate is floated, more leakage current flows compared to the state that the zero voltage is applied to the gate. This was not verified by circuit simulation due to the floating nodes.
A New Approach for Screening Retention Time Failure Bits in DRAM Device
Authors: Sung Bonggu , Kim Daejung , Park Yongjik , Choi Joo-Sun 
Published: December 2020

Abstract
In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.
Leveraging Root Cause Deconvolution Analysis for Logic Yield Ramping
Authors: Pan Yan , Chittora Atul , Sekar Kannan , Huat Goh Szu , Feng You Guo , Viswanatha Avinash , Lam Jeffrey 
Published: December 2020

Abstract
The root cause deconvolution (RCD) provides an easy-to-understand defect Pareto, together with targeted physical failure analysis candidates. Unfortunately, even the RCD analysis also has some assumptions and limitations, and its result cannot always be interpreted literally. This calls for a variety of conventional yield analysis techniques to be adopted in parallel to improve the confidence in the RCD results. This paper briefly introduces the RCD analysis and explains how it distinguishes itself from other conventional volume diagnosis analysis techniques. Its typical inputs and outputs are discussed as well. Next, the paper focuses on two case studies where the authors leverage RCD for logic yield improvement together with other conventional analysis techniques. It then proposes a comprehensive analysis system that is backed up by accumulating RCD results over time and across different design IPs.
Defect Localization Enhancement Using Light Induced CI-AFP
Authors: Dayanand N. , Quah A.C.T. , Chen C.Q. , Neo S.P. , Ang G.B. , Gunawardana M. , Mai Z.H. , Lam J.C. 
Published: December 2020

Abstract
This paper describes the effectiveness of using light induced Current Imaging – Atomic Force Microscopy (CIAFP) to localize defects that are not easily detected through conventional CI-AFP. Defect localization enhancement for both memory and logic failures has been demonstrated. For advanced technology nodes memory failures, current imaging from photovoltaic effects enhanced the detection of bridging between similar types of junctions. Light induced effects also helped to improve the distinction between gated and nongated diode, as a result enhanced localization of gate to source/drain short.
Novel NIR Camera with Extended Sensitivity and Low Noise for Photon Emission Microscopy of VLSI Circuits
Authors: Shehata Andrea Bahgat , Stellari Franco , Weger Alan , Song Peilin , Deslandes Herve , Lundquist Ted , Ramsay Euan 
Published: December 2020

Abstract
This work presents a new photon emission microscopy camera prototype for the acquisition of intrinsic light emitted from VLSI circuits during their normal operation. This novel camera was designed to be sensitive to longer wavelengths in order to maximize the signal intensities from modern VLSI chips which are characterized by a red shift in the intrinsic emission spectrum. In this paper, we will characterize the performance of the camera using 32 nm and 22 nm SOI chips. The novel camera is able to collect emission images with the circuit under test operating at a supply voltage down to 0.5 V, exceeding the performance of a state-of-the-art InGaAs camera.
Comparative Study on Decapsulation for Copper and Silver Wire-Bonded Devices
Authors: Kerisit François , Domenges Bernadette , Obein Michael 
Published: December 2020

Abstract
The introduction of silver as bonding material led to new failure analysis issues. This study compares the efficiency of wet and dry chemistries for decapsulation on Cu and Ag-based alloy wires. It is shown that dry chemistry allows better control and selectivity on the EMC/ Cu and Ag-based bond wires.
Introduction of Spectral Mapping through Transmission Grating, Derivative Technique of Photon Emission
Authors: Parrassin Thierry , Dudit Sylvain , Vallet Michel , Reverdy Antoine , Deslandes Hervé 
Published: December 2020

Abstract
By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.
Efficient Nondestructive 3D Defect Localization by Lock-in Thermography Utilizing Multi-Harmonics Analysis
Authors: Naumann Falk , Altmann Frank , Grosse Christian , Herold Rolf 
Published: December 2020

Abstract
Lock-in Thermography in combination with spectral phase shift analysis provides a capability for non-destructive 3D localization of resistive defects in packaged and multi stacked die devices. In this paper a novel post processing approach will be presented allowing a significant reduction of measurement time by factor &gt;5 in comparison to the standard measurement routine. The feasibility of the approach is demonstrated on a specific test specimen made from ideal homogenous and opaque material and furthermore on a packaged hall sensor device. Within the case studies the results of multiple single LIT measurements were compared with the new multi harmonics data analysis approach.
Automated Defect Analysis in Solar Cells Using EBIC
Authors: Moldovan Grigore , Lotharukpong Shark , Wilshaw Peter 
Published: December 2020

Abstract
Electron Beam Induced Current (EBIC) characterization is unique in its ability to provide quantitative high-resolution imaging of electrical defects in solar cells. In particular, EBIC makes it possible to image electrical activity of single dislocations in a Dual-Beam Focused Ion Beam (FIB) Scanning Electron Microscope (SEM), to cut and lift out a micro-specimen containing a particular dislocation, and then transfer it for further structural or chemical analysis. As typical solar cell material presents a complex array of defects, it is important to observe statistical variations within a sample and select key sites for analysis. This paper describes a method for automated defect identification and characterization, and shows an application to multi-crystalline silicon (mc-Si) solar cell wafers selected from different heights along the manufactured ingot. Information presented here includes the experimental setup for data acquisition, as well as the basic algorithms used for identification and extraction of dislocation contrast.
Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices
Authors: Dawood M.K. , Chen C. , Tan P.K. , James S. , Limin P.S. , Tan H. , Yap H.H. , Low G.R. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.
Understanding the Cu Void Formation by TEM Failure Analysis
Authors: Liu Binghai , Zhu Jie , Chen Changqing , Er Eddie , Zhao Siping , Lam Jeffrey , Elizabeth Sebastian , Ye Chen 
Published: December 2020

Abstract
In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.
Site-Specific, Wide Field-of-View Cross-Sectional Sample Preparation, Imaging and Analysis in a Plasma Ion Source Helios DualBeam™ Microscope
Authors: Alvis Roger , Kelley Ron 
Published: December 2020

Abstract
A Plasma-source focused ion beam (Helios PFIB) DualBeam™ microscope with sub-nanometer 1kV SEM resolution was used to investigate the structure of a state-of-the-art organic light-emitting diode (OLED) display. The capability of the Helios PFIB to produce and manipulate millimeter-scale samples for wide field-of-view crosssectional SEM analyses was demonstrated by lifting out a 570μm long by 40μm wide x 10μm deep and mounting it on a copper half-grid. An angled face was cut into the chunk and high-resolution back-scattered SEM tiles across the entire exposed face were automatically acquired within a modular automated processing system (MAPS).
Automatic Emission Spots Identification in Static and Dynamic Imaging by Research of Local Maxima
Authors: Boscaro A. , Chef S. , Jacquir S. , Sanchez K. , Perdu P. , Binczak S. 
Published: December 2020

Abstract
For VLSI, internal electrical measurements are key steps to solve design debug issues and to perform failure analysis. Due to multiple metal layers, active areas of the chip are only accessible from the backside of the die. The ability of optical contactless techniques to operate through the silicon substrate and the few sample preparation required have widely contributed to promote them as unavoidable tools of the defect localization workflow. Timing issue or unusual consumption can be detected by static and dynamic photon emission analysis. The identification of the emission spots is an essential step of the process. Due to scaling, more and more emission nodes are located within the acquisition area so that large variations of emission intensity can exist. Because of various limitations, former thresholding techniques cannot ensure an exhaustive localization. In this paper, an automated process is reported to locate spots in these complex areas. We will underline the challenge and define application boundaries of this technique.
Static Fault Isolation on the Functional Failure Analysis
Authors: Chen C.Q. , Mai Z.H. , Ang G.B. , Liu B.H. , Ng P.T. , Yip K.H. , Khalid D. , Lam J. 
Published: December 2020

Abstract
As the technology keeps scaling down and IC design becomes more and more complex, failure analysis becomes much more challenging, especially for static fault isolation. For semiconductor foundry FA, it will become even more challenging due to lack of enough information. Static fault isolation is the major global fault isolation methodology in foundry FA and it is difficult to access and trigger the failing signal detected by scan and BIST test, which is widely applied in modern IC design. Because, in most of the time, the normal two pin bias (Vdd and Vss) can only get the comparable IV result between bad unit and the reference unit for function related fail. There are two possibilities from reverse engineering perspective. Firstly, the defect location may not be accessed by the DC bias. Secondly, even if the defect can be accessed, but the defect induced current or voltage change is too small to be differentiated from the overall signal. So it will be concealed in the overall current. However, it is still possible for us to do global fault isolation for the second situation. In this paper, a unit with Iddoff failure was analyzed. Although, no significant IV difference was observed between failed and reference units, a distinct Photon Emission (EMMI) spot was successfully observed in the failed unit. Layout analysis and process analysis on this EMMI spot further confirmed the reality of the emission spot.
Test Circuit Conditioning for Soft Defect Localization
Authors: Staller Kristopher D. , Goodrich Corey 
Published: December 2020

Abstract
Soft Defect Localization (SDL) is a dynamic laser-based failure analysis technique that can detect circuit upsets (or cause a malfunctioning circuit to recover) by generation of localized heat or photons from a rastered laser beam. SDL is the third and seldom used method on the LSM tool. Most failure analysis LSM sessions use the endo-thermic mode (TIVA, XIVA, OBIRCH), followed by the photo-injection mode (LIVA) to isolate most of their failures. SDL is seldom used or attempted, unless there is a unique and obvious failure mode that can benefit from the application. Many failure analysts, with a creative approach to the analysis, can employ SDL. They will benefit by rapidly finding the location of the failure mechanism and forgoing weeks of nodal probing and isolation. This paper will cover circuit signal conditioning to allow for fast dynamic failure isolation using an LSM for laser stimulation. Discussions of several cases will demonstrate how the laser can be employed for triggering across a pass/fail boundary as defined by voltage levels, supply currents, signal frequency, or digital flags. A technique for manual input of the LSM trigger is also discussed.
Ultra-Low Voltage Time-Resolved Emission Measurements from 32 nm SOI CMOS Integrated Circuits
Authors: Shehata Andrea Bahgat , Stellari Franco , Weger Alan , Song Peilin , Anant Vikas , Sunter Kristen , Berggren Karl K. , Lundquist Ted , Ramsay Euan 
Published: December 2020

Abstract
This work presents a comparison of two generations of Superconducting nanowire Single-Photon Detector (SnSPD) prototypes used for Time-Resolved Emission (TRE) measurements from VLSI chips. The performance of the systems is compared in order to understand the figures of merit that a single-photon detector should have to enable the acquisition of time resolved emission waveforms for ultra-low voltage applications. We will show that measurements down to a new World record low 0.4 V supply voltage were made possible by a careful optimization of the detector front-end electronics. We also characterized the emission from devices with different threshold voltages in order to understand how the emission contributions depend on this parameter and how this affects the resulting waveform SNR.
Debugging Phase-Locked Loop Failures in Integrated Circuit Products
Authors: Goh S.H. , Lau Wendy , Yeoh B.L. , Ho H.W. , You G.F. , Hao Hu , Koh Y.E. , Lam Jeffrey 
Published: December 2020

Abstract
A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.
Investigation of Protection Layer Materials for Ex-Situ Lift-Out TEM Sample Preparation with FIB for 14 nm FinFET
Authors: Feng H. , Low G.R. , Tan P.K. , Zhao Y.Z. , Yap H.H. , Dawood M.K. , Zhou Y. , Du A.Y. , Chen C.Q. , Tan H. , Huang Y.M. , Wang D.D. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).
Application of Passive Voltage Contrast (PVC) to Dual Beam Focused Ion Beam (FIB) Based Sample Preparation for the Scanning/Transmission Electron Microscope (S/TEM)
Authors: Senowitz Corey , Nguyen Hieu , Vollrath Ruby , Yuan Caiwen , Rassolzadeh Fati , Graupera Theresa , Lyons Don , DiBattista Michael 
Published: December 2020

Abstract
The modern scanning transmission electron microscope (S/TEM) has become a key technology and is heavily utilized in advanced failure analysis (FA) labs. It is well equipped to analyze semiconductor device failures, even for the latest process technology nodes (20nm or less). However, the typical sample preparation process flow utilizes a dual beam focused ion beam (FIB) microscope for sample preparation, with the final sample end-pointing monitored using the scanning electron microscope (SEM) column. At the latest technology nodes, defect sizes can be on the order of the resolution limit for the SEM column. Passive voltage contrast (PVC) is an established FA technique for integrated circuit (IC) FA which can compensate for this resolution deficiency in some cases. In this paper, PVC is applied to end-pointing cross-sectional S/TEM samples on the structure or defect of interest to address the SEM resolution limitation.
Advanced Failure Analysis on Silicon Pipeline Defects and Dislocations in Mixed-Mode Devices
Authors: Weber Y. , Goxe J. , Alves S. , Zirilli T. , Castignolles M. , Subramanian S. , Tsang Y. , Harber K. 
Published: December 2020

Abstract
The presence of crystalline defects, including dislocations and pipeline defect, is detrimental to both the processing and the intrinsic quality of semiconductor devices. The electrical parametric or functional failures generated by those defects require accurate identification and proper classification in a continuous improvement mindset. Depending on the failure analyst choice of the investigation technique, the distinction between a dislocation and a pipeline defect can be difficult. In this paper, based on case studies of mixed-mode devices, the various electrical and physical FA investigation techniques are explored and compared. From an electrical investigation standpoint, fault localization techniques will be reviewed (Thermal Laser Stimulation and Photon Emission Microscopy) as well as the direct electrical measurements means (external measurement and nanoprobing AFP). From a physical analysis standpoint, the use of various methods after deprocessing will be considered: top down delineation etch, Atomic Force Microscopy (AFM), Scanning Microwave Microscopy (SMM), and Transmission Electron Microscopy (TEM). The position of the defect as well as its physical signature observed through the various methods will determine its proper classification and will determine the appropriate corrective actions. The paper will be concluded with a discussion on the physical differences between a dislocation and a pipeline defect, as well as insights into the wafer fab manufacturing process.