bluuebunny/crossref_metadata_2025_split huggingface dataset:
Resistivity Engineering of Atomic Layer Deposited Tungsten Carbonitride Thin Films Via Carbon Concentration Control for Cross-Point Memory Electrodes Applications
Authors: Na Seunggyu , Yoo Namkyu , Seo Jeongwoo , Kim Jaehyeok , Kim Tae Hyun , Park Seungwon , Lee Minkyu , Kim Myoungsub , Chung Seung-min , Kim Hyungjun 
Published: December 2024

As the demand for data storage and processing continues to rise exponentially, the development of phase change memory (PCM) has gained significant attention. In particular, three-dimensional (3D) vertical cross-point (VXP) array architecture is one of the most promising solutions for PCM fabrication, offering increased integration density and cost-effectiveness compared to the conventional planar memory structures, realized by atomic layer deposition (ALD) due to its excellent controllability and conformality.1) However, the implementation of a 3D VXP structure necessitates selectors, such as an ovonic threshold switch (OTS), to suppress sneak current from unselected cells. The switching behavior of the OTS selector depends heavily on electrode materials, constituting an essential part of the OTS device.2) Thus, detailed engineering of electrode material is required to obtain desirable properties for 3D VXP. Electrodes for 3D VXP require moderate resistivity because of the trade-off between thermal efficiency and power consumption. Moreover, the resistivity of film can be shifted by carbon incorporation. In this regard, we controlled the resistivity of the electrode with varying carbon concentration of the film utilizing ALD technique.
In this study, we focus on the development of thermal ALD tungsten carbonitride electrodes for 3D VXP arrays. Tungsten nitride is mainly used as an electrode due to its high thermal stability and conductivity. We present a novel ALD process with intentional carbon control of tungsten nitride to change film properties, including resistivity, by adjusting process parameters. Through systematic control of ALD process parameters, we investigated the impact of carbon concentrations on film characteristics and subsequently analyzed how these variations influence the electrical properties of OTS devices. This research opens the possibility of tuning electrode characteristics in detail, ultimately enhancing the overall electrical performance of the next-generation cross-point memory devices.
(Invited) Recent Advancements and Emerging Applications in Atomic Layer Deposition (ALD) on High-Porosity Materials
Authors: Bechelany Mikhael 
Published: December 2024

Atomic Layer Deposition (ALD) represents a state-of-the-art technology facilitating the production of thin films utilizing high-quality materials on substrates featuring high aspect ratios. This method delivers precise control over thickness, uniformity, and exceptional conformality, making it especially suitable for modifying the structure and tailoring the pores of highly porous materials like synthetic membranes. ALD coatings have found successful applications across a broad spectrum of membrane substrates, ranging from inorganic templated supports to porous polymers.
In this presentation, we seek to provide a comprehensive overview of the progress achieved in employing ALD on highly porous materials such as those used in membrane technology. Drawing upon a carefully curated selection of our research endeavors, we will demonstrate how ALD can be effectively harnessed to enhance the operational efficiency of various membrane types, including inorganic, organic, hybrid, or composite membranes. We will showcase examples illustrating how ALD plays a crucial role in designing membranes with precisely adjustable geometries, facilitating a systematic exploration of the relationship between physical-chemical properties and geometric parameters. This methodology enables thorough investigations into membrane performance across diverse applications such as renewable energy, encompassing tasks like gas separation and osmotic energy harvesting, as well as environmental applications like water treatment and sensor technologies.
Furthermore, we will delve into the challenges and prospects associated with employing ALD in membrane applications. This presentation aims to provide an exhaustive overview of the benefits of ALD and its applications across various aspects of membranes and related engineering processes. It endeavors to shed light on the myriad opportunities within this emerging and swiftly advancing field.

Selected References:

Chemistry of Materials 2018, 30, 7368-7390
Journal of Membrane Science, 2015, 475, 39–46
Journal of Membrane Science, 2020, 596, 117701
ACS Appl. Mater. Interfaces, 2017, 9, 16669–16678
Separation and Purification Technology, 2023, 312, 123377
Journal of Materials Chemistry A, 2019, 7, 8107-8116
Sensors and Actuators B: Chemical, 2021, 344, 130302
Self-Driving Tool, Digital Twin, and Machine Learning Algorithms for the Real Time Optimization of the ALD Growth of Multicomponent Thin Films Using in Situ Techniques
Authors: Yanguas-Gil Angel , Elam Jeffrey W. 
Published: December 2024

The design of optimal sequences for multicomponent ALD processes can be a time-consuming procedure: transient effects can appear each time that one switches to a different precursor, making it hard to predict beforehand the desired composition. Consequently, researchers usually resort to trial runs to calibrate the film composition, and combination of precursors with well-behaved nucleation behaviors and fast transients are highly prized. While effective for processes involving two different precursors, this empirical approach makes it hard to extend ALD to explore more complex materials involving ternary or quaternary compounds.
In this work we explore an alternative approach that uses machine learning integrated with in-situ techniques to optimize the composition of multicomponent films. Our approach relies on digital twins to train, optimize, and benchmark algorithms that build the sequence of ALD cycles in real time from the feedback of in-situ data. These models allow us to generate a wide range of processes with different types of nucleation behaviors, providing the ideal testbed for the development of robust algorithms. We then transfer these algorithms into our experimental reactors for the exploration and optimization of processes involving two and three different types of oxide materials. Our results show that it is possible to drive the optimization of binary and ternary ALD processes using solely the growth per cycle of the individual processes as input, with the algorithm being robust across different nucleation behaviors. The main limitation of the proposed approach is that, for techniques showing a net change in the material, such as quartz crystal microbalance, it is not possible to consider systems that exhibit a substantial amount of etching, such the ZnO/Al2O3 process involving diethyl zinc and trimethyaluminum precursors. This would not be a limitation for techniques providing direct compositional information, such as X-ray fluorescence, or those focusing on materials properties, such as in-situ spectroscopic ellipsometry.
This research is based on the work supported by the Laboratory Directed Research and Development (LDRD) funding from the Argonne National Laboratory, provided by the Director, Office of Science, of the U.S. DOE under Contract No. DE-AC02-06CH11357.
(Invited) Prospects of New Cleaning Technologies for Future Device Development
Authors: CHA JI Hoon 
Published: December 2024

As devices shrink, new materials and new stacked structures are being introduced to improve performance and overcome structural limitations. For memory devices, the higher stacked structure, which was mainly used in Flash devices, is being extended to Dram devices. The structure for logic devices is transitioning from planar, Finfet and GAA to Forksheet and CFET.
In order to develop processes for a future device, the cleaning process has also become increasingly sophisticated and difficult. In particular, the requirements for fundamental cleaning techniques such as highly selective and narrow gap etching, small particle removal and extreme uniformity control are being pushed to the limit.
In this presentation, we will review trends in device roadmaps and suggest new cleaning technologies needed for future devices. New chemicals with inhibitors and dry cleaning processes using radical or etching gas are being evaluated for highly selective etching of materials with different Ge content, such as SiGe 5~50%. New concepts will be suggested for small particle removal without pattern damage using polymers and for selective deposition by Wet SAM (Self -Assembly Monolayer) which could have various applications. In terms of small particle removal, we use polymers that can be attached to small particles, like sticky materials, which remove them without any other residues. In this process, it is important to remove small particles without causing any other damages to the pattern. For SAM, it can chemically adsorb in the area where material does not want to be deposited and stays during subsequent deposition, resulting in a selective deposition. Any SAM after deposition should be removed by plasma treatment.
In addition, reclaimable chemicals have been expanding to promote environmental sustainability and cost efficiency. To achieve this, a real-time chemical analyzer that accurately and quickly monitors the chemical composition of elements is essential. The development of recyclable chemicals, as well as hardware equipment, is also needed.
メガヘルツ周波数範囲のクォーツトランスデューサー超音波洗浄機を使用したポリスチレンラテックス粒子の除去の評価
Authors: Seike Yoshiyuki , Takagi Rai , Hikita Tomomi , Honda Yuji , Taoka Noriyuki , Ichino Yusuke , Mori Tatsuo 
Published: December 2024

This paper describes the newly developed quartz transducer ultrasonic cleaners (QTCs) operating at frequencies of 1 MHz to 3 MHz, designed to physically remove particles, including a few nano-sized particles, without causing damage to wiring patterns. The paper also discusses the potential of QTC by conducting experiments to remove submicron polystyrene latex (PSL) particles using QTC.
In recent years, with the refinement and increased integration of semiconductors, there is a growing need to remove nanometer-sized particles. Conventional spray-type ultrasonic cleaners have the disadvantage of easily disrupting wiring patterns due to fluctuating sound pressure impacting the substrate surface. the QTCs were developed with the consistent sound pressure fluctuation. The QTC transmits ultrasonic waves from an ultrasonic oscillator through an elliptical quartz column and then impacts the particles on the wafer surface through the pure water between the QTC and the wafer surface. Therefore, the variation of sound pressure on the wafer surface is small. We measured the sound pressure emitted by the QTCs and confirmed that its fluctuation is significantly smaller than that of conventional spray-type ultrasonic cleaners, which exhibit large and random fluctuations in sound pressure.
Subsequently, PLS particles ranging from 100 nm to 1 µm were coated onto the surface of silicon wafers with oxide film. These particles were then removed using QTCs operating at frequencies of 1, 2, and 3 MHz to elucidate the physical particle removal mechanism. The experimental results showed that the particle removal rates (PREs) tended to decrease as the particle size decreased. Regarding frequency dependence, the PREs increase with higher frequencies and also with higher amplitudes of the QTC. The removal of PSL particles in spray-type ultrasonic cleaning has been confirmed using drag force analysis. It has been observed that smaller PSL particles result in lower drag forces, leading to a decrease in the PRE. The same trend is observed in the present experiment. However, when the relationship between drag forces and PREs was confirmed using QTCs, the variations of PRE became significantly smaller as the frequency of QTCs increased. From this result, it was confirmed that the cleaning method developed this time with QTCs is easy to control with less turnover using a high frequency in the megahertz band.
(Invited) Silicon Carbide Technology Scaling: Challenges and Opportunities across the Value Chain
Authors: Singh Navab , Chand Umesh , Kumar Shiv , Nguyen Xuan Sang Xuan , Bera Lakshmi Kanta , Chung Surasit , Gong Xiao , Yeo Yee Chia 
Published: December 2024

Silicon Carbide (SiC) technology has emerged as a promising solution to address the growing demand for high-performance power electronics in various applications, ranging from automotive to renewable energy systems. As the industry continues to push the boundaries of SiC technology, scaling opportunities and challenges arise across the entire value chain, from material to device fabrication and new package architectures. In addition, it should be noted that scientific understanding, especially in the areas of defect behaviour in the SiC epitaxy layer, threshold voltage instability, interface trap density, and integrity of the gate insulator, would be increasingly important and necessary for the further development of SiC power devices. To address the economics, and mass produce ultra-high-power electronics devices with improved performance and reliability, we partnered with ecosystem players across the value chain from substrate to power module packaging and set up a 200mm SiC specialty open innovation process line.
This talk will provide an overview of the key challenges and opportunities associated with SiC technology. We will discuss the high grow rate (≥50µm/hr) SiC epitaxy process and share methodologies to achieve high-quality epitaxy layer with good doping control (≤10%), tight thickness uniformity (≤3%), low surface roughness (≤3Å) and low crystal defect densities (≤0.4 cm-2) on 200mm 4H-SiC substrate. Moving on to the metal oxide semiconductor (MOS) device interface engineering, we will discuss strategies for achieving low interface trap densities (~1011eV-1 cm-2) and improved threshold voltage instability. Beyond device fabrication, we will highlight the importance of the power module packaging technique in realizing the full potential of SiC technology. This includes the double-side liquid cooling system and the power dissipation capability with different designs and material options for the proposed 6-in-1 power module.
Overall, by addressing these challenges collaboratively, we can accelerate the adoption of SiC technology and unlock its full potential to drive power semiconductor technology and beyond.

Figure 1
(Invited) Epitaxial Growth and Development of Complimentary Field-Effect Transistors
Authors: Arora Himani , Tolle John 
Published: December 2024

The semiconductor industry is currently at a pivotal juncture, with major chip fabrication facilities having exhausted FINFET technology and now transitioning to a new device architecture of gate all around (GAA). The next architecture in this progression (beyond 1nm), crucial for scaling down is Complementary Field-Effect Transistors (cFETs). In cFETs, nMOS and pMOS are stacked on top of each other, eliminating the gap and resulting in significant reduction of area and maximization of channel width and drive current.[1-3]

In this work, we present our research on epitaxial growth of cFET stacks and discuss our design strategies and the key evaluation metrics in accordance with the downstream processes. We delve deeper into the bottom-up growth of cFETs using Chemical Vapor Deposition (CVD) epitaxy and explore the impact of temperature, precursor gases, and Germanium content on the quality and strain engineering of cFETs. We exploit various characterization techniques to quantify defects, strain, uniformity, and composition of the epitaxial layers comprising the cFET stacks, followed by tuning of the process parameters accordingly to achieve a high-quality, fully-strained stack. Through this study, we aim to provide valuable insights into the growth and optimization of cFET structures, thereby facilitating their integration into future transistor nodes.
[1] P. Schuddincket al., 2022 IEEE Symp. on VLSI Techn. & Circuits, Digest of Technical Papers, p. 365.
[2] S. Subramanian et al., 2020 IEEE Symp. on VLSI Techn. & Circuits, Digest of Technical Papers, TH3.1.
[3] A. Vandooren et al., 2022 IEEE Symp. on VLSI Techn. & Circuits, Digest of Technical Papers, p. 330.
(Invited) Millimeter-Wave and THz Circuits and Sub-Systems in Si-Ge Bi-CMOS Technology
Authors: Zeinolabedinzadeh Saeed 
Published: December 2024

SiGe BiCMOS technology offers high-speed, low-noise characteristics, coupled with a high breakdown voltage and favorable integration capability with high yield, making it ideal for developing high performance complex integrated circuits and systems in silicon. Recent advancements have resulted in devices with an fmax exceeding 500 GHz, enabling the creation of circuits operating at higher millimeter-wave (mmW) and sub-mmW frequencies. The trajectory of SiGe technology indicates its potential to extend operational speeds toward THz frequencies, possibly surpassing CMOS devices through scaling path. Moreover, SiGe technology demonstrates favorable performance under extreme environments, particularly exhibiting improved performance at low temperatures.
In parallel with progress in device technology, significant advancements in circuit technology have been achieved, leading to the realization of sophisticated integrated RF front-end circuits for various commercial applications such as 5G/6G communication, automotive radar, and THz imaging.
This presentation will showcase recent research conducted by the author’s team at Arizona State University (ASU), focusing on the design and development of integrated mmW and THz transceiver circuits and subsystems utilizing SiGe BiCMOS technologies. Our research incorporates device, circuits, and electromagnetic co-design practices, demonstrating close alignment between the designed and measured characteristics of the circuits at mmW and THz frequencies.
The presentation will feature implemented examples of transceiver front-end circuits and coherent transceiver arrays. These chip-scale circuits were specifically designed for centralized and distributed beamforming, incorporating high precision synchronization capabilities tailored for 5G mmW and ranging applications. Additionally, fully integrated THz circuits will be presented, demonstrating their effectiveness for chip-scale spectroscopy and THz imaging applications.
Deposition of SiC Thin Films By Using R. F. Power Ramps
Authors: Perez Ladron de Guevara Hector , Esparza Ramírez Kevin Manuel , Rosendo Andrés Enrique , Zarazua Macias Isaac , Medel Ruíz Carlos Israel 
Published: December 2024

SiC is a broadly researched and utilized material in a wide variety of known applications like coatings, MOSFETs and other miscellaneous devices; Regardless of this, SiC technology still has potential growth in new material engineering and devices through use of modern growth techniques and methods. In this study, we attempted to deposit SiC films on Si and glass substrates by using low temperature and different R. F. power ramps in a Magnetron Sputtering.
The experiment presented successful growth of SiC thin films through a novel ramping method that allowed us to deposit a thin film at room temperature. The films were characterized by using AFM Microscopy, Spectroscopic Ellipsometry and Micro-Raman Spectroscopy. The valuable information obtained on surface morphology, band gap energy and crystal structure will fuel further endeavors to continually develop this material for future applications.
AFM measurements presented a periodic grain pattern akin to terraces with quadrilateral grains and a meaningfully different geometry when compared to traditional semiconductor surfaces. Ellipsometry data provided a band gap energy from 3.3 eV. Raman spectra revealed broad peaks pertaining to multiple SiC polytypes.
Pathways Toward High-Energy Li-Sulfur Batteries, Identified Via Multi-Reaction Chemical Modeling
Authors: DeCaluwe Steven C. , Korff Daniel M. 
Published: December 2024

Lithium-sulfur (Li-S) batteries, which promise high gravimetric capacity and use Earth-abundant raw materials, could accelerate global energy decarbonization. Currently, Li-S performance is limited by non-conductive cathode phases (solid sulfur S8(s), lithium disulfide Li2S(s)), PS shuttling and precipitation at the anode, and sluggish Li+ transport. Mitigation often aims to control the reaction pathways or prevent PS shuttle, but a better understanding of the underlying phenomena is needed to guide development.
Here we present a 1D model of a Li-Sulfur battery with physically derived geometric parameters and thermodynamically consistent electrochemical kinetics. The approach enables straightforward comparison of proposed Li-S mechanisms and provides insights into the influence of polysulfide intermediates on battery discharge. Comparing predictions from multiple mechanisms demonstrates the need for both lithiated and non-lithiated polysulfide species and highlights the challenge of developing parameter estimates for complex electrochemical mechanisms. The model is also used to explore cathode design strategies. Discharge performance and polysulfide concentrations for electrolyte/sulfur ratios in the range 2–4 μL mg−1 identifies trade-offs that limit battery energy and power density and highlights the risk of polysulfide precipitation. New cathode and electrolyte approaches must limit polysulfide concentrations in the electrolyte, both to unlock better rate capabilities in Li-S technology and to prevent capacity fade due to polysulfide precipitation. Moreover, the tools developed and presented here present a pathway to flexibly incorporate atomistically-derived reduction-oxidation thermos-kinetics and polysulfide transport properties to unlock predictive models for design and control of high-performance Li-S batteries.