(Invited) Low Contact Resistance on Buried Interfaces in Oxide Thin-Film Transistors by Selective-Area Reduction Using Hydrogenation Catalyst Electrode
Authors: Tsuji Masatake , Shi Yuhao , Cho Hanjun , Ueda Shigenori , Kim Junghwan , Hosono Hideo 
Published: December 2024

As the focus on amorphous oxide semiconductor (AOS) in memory applications deepens, there is a push for higher packing densities and more efficient read-write efficiencies, leading to increasingly complex AOS transistor structures with dimensions scaled down to the nanometer size. In pursuit of high density for AOS-based dynamic random-access memory (DRAM), 3D-stacked vertical IGZO transistor devices have been employed, wherein the contact interfaces of these vertical devices are buried and located internally within the device, and these vertical or buried interfaces are prone to causing contact issues. However, conventional methods to addressing contact resistance in thin-film transistors (TFTs) used for flat-panel displays are not applicable to buried interfaces. The development of novel methods to resolve this issue is a current challenge for the future development of complex structured AOS memory devices.
In this work, the contact resistance of a-IGZO TFT was reduced by three orders of magnitude by utilizing hydrogenation catalyst electrodes for a selective area reduction reaction at the interface and constructing a hydrogen transfer pathway1. The key to effective hydrogenation on the internally buried interface is the selection of the optimal catalyst metal electrode and passivation materials that satisfy the following requirements. 1) High hydrogen diffusion rate and moderate hydrogen solubility for reversible hydrogen transfer. 2) Catalytic hydrogen dissociation to highly active H0 atoms on/in the metal electrode for low-temperature reaction [Fig. 1(a)]. 3) Dense oxide passivation layer with hydrogen tolerant electronic structure to hydrogen, in which a shallower CBM than the charge transition level of E(H+/H−), to isolate the effective channel from hydrogen. Pd was selected as the best electrode for this strategy owing to its flexible lattice and unique properties of hydrogen permeability without brittleness to hydrogen. Also, amorphous Zn–Si–O (ZSO
x
), which can be easily deposited by sputtering, was used as the passivation layer.
Detection through hard X-ray photoelectron spectroscopy indicates that the high reactivity of H0 reduces metal oxides at the interface, forming a metallic interface layer. Fig. 1(b) shows the hydrogen annealing condition dependence of the contact resistance and effective channel length deviation estimated by TLM measurements. By optimizing hydrogen annealing conditions, the company succeeded in achieving both a small effective channel length deviation of ~40 nm and contact resistance that was reduced by approximately three orders of magnitude. The field-effect mobility was enhanced from 3.2 to ~20 cm2 V–1 s–1 as a consequent effect of the improved contact resistance. Furthermore, as shown in Fig. 1(c), the prepared a-IGZO TFTs also demonstrated excellent bias-stability, further proving the reliability of using catalytic electrodes and hydrogen tolerant passivation layer in the process.

References:
(1) Shi, Y.; Tsuji, M.; Cho, H.; Ueda, S.; Kim, J.; Hosono, H. Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway. ACS Nano
2024,
18 (13), 9736–9745.

Figure 1