bluuebunny/crossref_metadata_2025_split huggingface dataset:
Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs
Authors: Oliveira Alberto V. , Agopian Paula Ghedini Der , Martino João Antonio , Simoen Eddy , Claeys Cor , Mertens Hans , Collaert Nadine , Thean Aaron 
Published: December 2020

One of the main challenging issues for germanium (Ge) devices is the gate stack engineering which determines the interface state density (NIT) and the associated channel/oxide interface quality. This paper shows how this issue can play a role in p-channel Ge MOSFETs considering both the operation mode, i.e., comparing conventional, dynamic threshold voltage (DT, where VBS = VGS) and enhanced dynamic threshold voltage (eDT, where VBS=k*VGS) modes, and the main analog parameters like the Early voltage (VEA) and intrinsic voltage gain (AV). Moreover, the impact of different HfO2/Al2O3 gate stack thicknesses is under evaluation. Although the thinnest Al2O3 layer degrades all evaluated parameters, specifically: lower VEA and AV, higher drain current hysteresis and subthreshold swing (SS) due to the higher NIT, the dynamic threshold voltage showed to be an effective mode to strongly minimize the hysteresis effects and improves up to 60% in eDT (k = 2) mode compared to the conventional mode (k = 0), thanks to the dynamic threshold voltage reduction.
Development of MCM-D Technology with Photosensitive Benzocyclobutene
Authors: Adamo Cristina B. , Flacker Alexander , Cavalcanti Hercílio M. , Teixeira Ricardo C. , Rotondaro Antonio L. P. , Manera Leandro T. 
Published: December 2020

This paper evaluates and compares the development of Multi-Chip Module Deposited (MCM-D) technology using photosensitive benzocyclobutene (BCB) with the non-photosensitive BCB to fabricate passive devices. The polymer was used to isolate the metal/interconnection layers and also as the dielectric for the capacitors. Ni-P/Au was used as the conductor film and Ta2N as the resistor film. The resistors’ sheet resistance was measured with both transfer length method (TLM) and direct measurement while the measurements of the capacitors and inductors required the use of a Vector Network Analyzer (VNA) and some mathematical algorithms.
Low Temperature Sensitivity CMOS Transconductor Based on GZTC MOSFET Condition
Authors: Toledo Pedro , Klimach Hamilton , Cordova David , Bampi Sergio , Fabris Eric 
Published: December 2020

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/oC.
Hierarchical Group-key Management for NoC-Based MPSoCs Protection
Authors: Sepulveda Johanna , Flórez Daniel , Immler Vincent , Gogniat Guy , Sigl Georg 
Published: December 2020

Group keys can be used in order to communicate secretly sensitive data among IP cores. However, the flexibility and dynamic nature of MPSoCs force reshaping the security zones at runtime. Members of a zone must be able to efficiently compute the new group key while former members must be prevented for data disclosure. Efficiently creating security zones for achieving sensitive traffic isolation in MPSoC environments is a challenging problem. In this work we present the implementation of hierarchical group-key management for NoC-based systems in order to efficiently perform the rekeying process. We implement three hierarchical protocols and we show that by decentralizing the security management of the rekeying process, it is possible to achieve an improvement of the performance when compared to the previous flat approaches.
An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α-Power MOSFET Model
Authors: Kalra Shruti , Bhattacharyya A. B. 
Published: December 2020

Aggressive technological scaling continues to drive ultra-large-scale-integrated chips to higher clock speed. This causes large power consumption leading to considerable thermal generation and on-chip temperature gradient. Though much of the research has been focused on low power design, thermal issues still persist and need attention for enhanced integrated circuit reliability. The present paper outlines a methodology for a first hand estimating effect of temperature on basic CMOS building blocks at ultra deep submicron technology nodes utilizing modified α-power law based MOSFET model. The generalized α-power model is further applied for calculating Zero Temperature Coefficient (ZTC) point that provides temperature-independent operation of high performance and low power digital circuits without the use of conditioning circuits. The performance of basic digital circuits such as Inverter, NAND, NOR and XOR gate has been analyzed and results are compared with BSIM4 with respect to temperature up to 32nm technology node. The error lies within an acceptable range of 5-10%.
Table of Contents and Foreword
Authors: Pavanello Marcelo Antonio , Kastensmidt Fernanda 
Published: December 2020

This second issue is composed by some of the papers that have been selected from those presented at SBMicro2015 (30th Symposium on Microelectronics Technology and Devices) and SBCCI2015 SBCCI2014 (28th Symposium on Integrated Circuits and Systems Design), which have been held in Salvador, Brazil, in 2015. Among the contributions presented at both Symposia, only a few best rated were selected by the JICS Editorial Board and have been invited to submit an extended version to the Journal. These extended papers have passed through the usual reviewing process before acceptance. In addition to these selected best papers, spontaneous submissions passed through the usual reviewing process and have been accepted as regular papers. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their valuable contribution on paper evaluation and selection, which guarantees the scientific level of this issue. We sincerely hope that JICS readers will enjoy these contributions.Marcelo Antonio Pavanello - JICS Editor-in-chief Fernanda Kastensmidt - JICS Co-Editor
A 1 to 10-bit, 85.3 fJ/Conv-step ADC for RFID Sensors
Authors: Zurita Marcos , Freire Raimundo C. S. , Tedjini Smail 
Published: December 2020

This paper presents the design results of an ultra-low power 1 to 10 bit arbitrary resolution switched capacitor analog to digital converter. In addition to using low-power elements, his project also used a library specifically optimized for the proposed converter rather than a standard library as in traditional approach. This approach enabled the overall converter consumption to be reduced by about 70 %. Consuming 7.29 μA at 1 V supply and taking less than 9 μs per conversion (10 bit mode) it can be used in LF, HF or UHF RFID passive sensor tags. The presented converter was designed in 180 nm CMOS technology occupying about 0.052 mm2 of silicon area. A simulation result shows a figure of merit equal to 85.3 fJ/Conversion-step and 9.5 effective number of bits.
Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation
Authors: Aguilera Carlos J. G. , Chenet Cristiano P. , Balen Tiago R. 
Published: December 2020

This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.
Analysis and Design of a Low Noise Shunt-Shunt CMOS Transimpedance Amplifier for 10 Gbps Optoelectronic Receivers
Authors: Ponchet André F. , Swart Jacobus W. , Bastida Ezio M. , Finardi Célio A. , Panepucci Roberto R. , Tenenbaum Stefan , Finco Saulo 
Published: December 2020

This article presents a complete design flow of a low noise transimpedance amplifier for 10 Gbps optoelectronic receivers. The proposed topology is based on the shunt-shunt structure with negative feedback. A set of equations was deduced from the frequency analysis and noise analysis. An optimization algorithm is proposed in order to maximize the bandwidth and improve the noise performance simultaneously. Experimental results shown a 51 dBΩ transimpedance gain, a 10.54 Ghz bandwidth and an input referred current noise equal to 6.8, the lowest one between other state-of-art designs. The circuit was manufactured in 130 nm RF CMOS technology.
Asynchronous AES Crypto-Processor Including Secured and Optimized Blocks
Authors: Bouesse Fraidy , Renaudin M. , Germain Fabien 
Published: December 2020

This paper presents the first study of an asynchronous AES architecture compliant with the NIST standard. It exploits the fundamental properties of quasi delay insensitive asynchronous circuits. First, 1 to N encoding is extensively used in order to minimize hardware cost, thus optimizing area and speed. Most importantly, it is shown how the quasi delay insensitive logic style gives the opportunity to design balanced architectures, particularly well suited to improve differential power analysis resistance. Indeed, the proposed design methodology enables the generation of logic circuits which always involve a constant number of logical transitions, independently of data values processed by the circuit. Based on a 32-bit data-path, a balanced and optimized QDI asynchronous architecture of the AES is described. In addition, several architecture trade-offs are considered, and their area and speed estimated. Simulation results show that with the proposed design approach, throughputs ranging from 36 Mbit/s to more than 569 Mbit/s can be achieved, well suited to target smart-card applications.
Designing Mixed-Signal Programmable Fuzzy Logic Controllers as Embedded Subsystems in Standard CMOS Technologies
Authors: Dualibe Carlos , Jespers Paul , Verleysen Michel 
Published: December 2020

A digitally programmable analog Fuzzy Logic Controller (FLC) is presented. Input and output signals are processed in the analog domain whereas the parameters of the controller are stored in a built-in digital memory. Some new functional blocks have been designed whereas others were improved towards the optimization of the power consumption, the speed and the modularity while keeping a reasonable accuracy, as it is needed in several analogue signal processing applications. A nine-rules, two-inputs and one-output prototype was fabricated and successfully tested using a standard CMOS 2.4μ technology, showing good agreement with the expected performances, namely: a 2.7% RMSE, from 2.22 to 5.26 Mflips (Mega fuzzy logic inferences per second) at the pin terminals (@CL=13pF), 933 μW power consumption per rule (@Vdd=5V) and 5 bits of resolution. Since the circuit is intended for a subsystem embedded in an application chip (@CL≤ 5pF) up to 8 Mflips may be expected.
A Switched-MOSFET Programmable Low-Voltage Filter
Authors: Marques Luís Cléber C. , Serdijn Wouter A. 
Published: December 2020

This paper describes a digitally programmable low-voltage low-power analogue filter that can be used in hearing-aid circuits. The filter employs the recently introduced switched-MOSFET technique, a sampled-data technique suitable for low supply voltage operation since it avoids the conduction gap of the switches and does not need any dedicated process. The filter was implemented using the DIMES 1.6μm CMOS process and achieves 64 dB dynamic range. The total current consumption, drawn from a 2.2V supply, equals 93μA.
In-Situ and Ion Implantation Nitrogen Doping on Near Stoichiometric a-SiC:H Films
Authors: Oliveira A. R. , Carreño M. N. P. 
Published: December 2020

In this work we study the nitrogen n-type electrical doping of a-Si0.5C0.5:H films obtained by plasma enhanced chemical vapor deposition (PECVD) utilizing and comparing two doping techniques: in-situ (during the material growth) and ion implantation. The in-situ doped a-SiC:H films were obtained adding different amounts of N2 to the precursor gas mixture. For ion implantation four different nitrogen implanted concentrations were studied (between 1018 and 1021 atoms/ cm3) using multiple energies and doses to define a homogeneously doped layer. The doping experiments are carried out on a-SiC:H samples that present different structural order. The results show that high levels of electrical conductivity can be obtained with ion implantation technique. For in-situ technique the doping effect is also observed but must be improved in order to attain higher electrical conductivities. In the best case the room temperature dark conductivity for the sample implanted with 1021 nitrogens/cm3 was ~10-7 (Ω.cm)-1 and the activation energy was 0.2 eV. For in-situ doping the electrical dark conductivity reached values near 10-10 (Ω.cm)-1 at high temperatures and the activation energy was ~0.6 eV. Despite of the apparent low values of the electrical conductivity, these results are promising because we are dealing with a wide gap material and the doping processes are still not optimized.
Measuring the Efficiency of Cache Memory on Java Processors for Embedded Systems
Authors: Beck Antonio Carlos S. , Rutzig Mateus B. , Carro Luigi 
Published: December 2020

Java, with its advantages as being an overspread multiplatform object oriented language, has been gaining popularity in the embedded system market over the years. However, because of its extralayer of interpretation, it is also believed that it is a slow language while being executed. Nevertheless, when this execution is done directly in hardware, Java advantages caused by its stacknature start to appear. One of these advantages concerns memory utilization, impacting in less accesses and cache misses. In this work we analyze this impact in performance and energy consumption,comparing a Java processor with a RISC one based on a MIPS architecture with similar characteristics.
Communication Aware Optimization of the Task Binding in Hardware/Software Reconfigurable Networks
Authors: Streichert Thilo , Strengert Christian , Koch Dirk , Haubelt Christian , Teich Jürgen 
Published: December 2020

In this paper, a new methodology for tolerating link as well as node defects in self-adaptive reconfigurable networks will be presented. Currently, networked embedded systems need a certain level of redundancy for each node and link in order to tolerate defects and failures in a network. Due to monetary constraints as well as space and power limitations, the replication of each node and link is not an option in most embedded systems. Therefore, we will present a hardware/software partitioning algorithm for reconfigurable networks that optimizes the task binding onto resources at runtime such that node/link defects can be handled and data traffic on links between computational nodes will be minimized. This paper presents a new hardware/software partitioning algorithm, an experimental evaluation and for demonstrating the applicability, an implementation on a network of FPGA-based boards.
Plasma Etching of Polycrystalline Silicon using Thinning Technology for Application in CMOS and MEMS Technologies
Authors: Nunes A. M. , Moshkalev S. A. , Tatsch P. J. , Daltrini A. M. 
Published: December 2020

This work presents results of the study of profile evolution for Si-poly structures during plasma etching using the thinning technology in SF6/CF4/CHF3 gas mixtures. Structures with an aspect ratio (height/width) up to 5, widths end in the range of 0.3 – 0.1 μm and 0.3μm thick, were produced. Sipoly structures with high anisotropy (anisotropy factor up to 0.92-0.98) after etching were demostrated. The method can be used for fabrication of sub-micron Si-poly gates in CMOS and in fabrication of MEMS devices.
Bridging Electrical and Structural Interface Properties: a Combined DFT-GW Approach
Authors: Fonseca L. R. C. , Prodhomme PY. , Blaise P. 
Published: December 2020

The selection of a proper metal for replacement of polycrystalline silicon as the metal gate in future generation transistors has been hampered by pinning of the metal Fermi level at the metal/dielectric interface. Using monoclinic hafnia and zirconia as the gate dielectric we compare three different metal gate/gate dielectric interface structures where the oxygen affinity of the metal gate varies from low to high under normal processing conditions. For each of the metal gate/gate dielectric combination we considered a number of interface stoichiometries and tried to identify the most likely interface composition by comparing the calculated and measured valence band offsets (VBO). Because density functional theory (DFT) underestimates the dielectric band gap, it also underestimates the VBO thus requiring a correction to the band edges, which we accomplished using GW for cubic and monoclinic hafnia. Our GW shift value for monoclinic hafnia (0.3 eV) indicates mostly reduced interfaces in all metal/dielectric combinations considered.
Table of Contents and Foreword
Authors: Martino João Antonio , Carro Luigi 
Published: December 2020

This issue of Journal of Integrated Circuits and Systems (JICS) includes 6 papers on process, materials, devices, and modeling. These papers have been selected from the presentations given at SBMicro2007 (22nd Symposium on Microelectronics Technology and Devices), which has been held in Rio de Janeiro, Brazil in 2007. Among the contributions presented at SBMicro2007 conference, only a few best rated by the reviewers were selected by the JICS Editorial Board and have been invited to submit an extended version. These papers have been submitted to usual reviewing process with the help of external experts. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection, which guarantees the scientific level of this issue.We sincerely hope that JICS readers will enjoy these contributions, as we have enjoyed listening to them at the SBMicro2007 conference. This year marks a new challenge for JICS as the journal will allow the spontaneous submission of papers additionally to the best papers of Symposium on Microelectronics Technology and Devices and Symposium on Integrated Circuits and Systems Design. We hope the community will support our decision submitting high quality papers that will contribute to the excellence of JICS Journal. João Antonio Martino Luigi CarroJICS Editor-in-chief JICS Co-Editor
A Study of Flicker Noise in MOS Transistor Under Switched Bias Condition
Authors: Miguez Matías , Arnaud Alfredo 
Published: December 2020

This manuscript examines in detail the mechanisms and behavior of flicker noise in switched biased MOS transistors. Firstly, the PSD of a DC biased transistor is deduced using only Shockley-Read-Hall (SRH) statistics and the autocorrelation formalism. Then the analysis is extended, by means of simulations and using simple physical hypotheses, to a switched bias condition. The results allow explaining several reported experimental data. Particularly, the 1/f form of flicker noise at very low frequencies is observed in simulations.
Gate Oxide Thickness Influence on the Gate Induced Floating Body Effect in SOI Technology
Authors: Agopian Paula G. D. , Martino João Antonio , Simoen Eddy , Claeys Cor 
Published: December 2020

In this work, we explore the gate oxide thickness influence on the Gate Induced Floating Body effect (GIFBE). This study was performed through two-dimensional numerical simulations and electrical measurements. The available devices are from 130nm and 65nm Silicon-On-Insulator (SOI) MOSFET technologies. The GIFBE and threshold voltage are evaluated as function of the gate oxide thickness reduction and an overlap tendency of the first and the second transconductance peaks is observed.
Study of the Metal Filling Impact on Standard Cells and their Associated Interconnects Using Ring Oscillators: Definition of the Metal Fill Corner Concept
Authors: Remy Laurent , Coll Philippe , Picot Fabrice , Mico Phillipe , Portal Jean-Michel 
Published: December 2020

The objective of this paper is to evaluate the delay impact of staggered metal filling on the standard cells and their associated local interconnect on several metal levels. A Design of Experiment (DOE) is used to define a large range of filling pattern shapes and positions. This set of filling patterns is then inserted in a Ring Oscillator (RO). From the filled RO simulations, the RO delay is expressed as a function of the filling pattern features. The maximal timing error between the model and the simulation is 1.3%, validating the model. The filling impact on RO delay magnifies the one introduced by the front-end process variations (PVT). Consequently, the filling influence is introduced for the minimal, typical and maximal corners, defined now with Process (P), Voltage (V), Temperature (T) and Filling density (F) characteristics.
Table of Contents and Foreword
Authors: Martino João Antonio , Lubaszewski Marcelo 
Published: December 2020

This issue of Journal of Integrated Circuits and Systems (JICS) includes papers on process, materials, devices, and modeling. These papers have been selected from the presentations given at SBMicro2008 (23rd Symposium on Microelectronics Technology and Devices), which has been held in Gramado, Brazil in 2008. Among the contributions presented at SBMicro2008 conference, only a few best rated by the reviewers were selected by the JICS Editorial Board and have been invited to submit an extended version. These papers have been submitted to usual reviewing process with the help of external experts. An invited paper from Dr. Carlos Mazure on SOI technology and its applications is included in this issue and also spontaneous submissions have been considered. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection, which guarantees the scientific level of this issue.We sincerely hope that JICS readers will enjoy these contributions.João Antonio Martino - JICS Editor-in-chiefMarcelo Lubaszewski - JICS Co-Editor
A Review of SOI Technology and its Applications
Authors: Nguyen Bich-Yen , Celler George , Mazuré Carlos 
Published: December 2020

Classical scaling is no longer possible to follow Moore’s law. In addition to the material innovations such as high K/metal gate and stressors, a transition to SOI is essential to meet scaling and performancerequirements alike. The advances in SOI for fully depleted devices and some key SOI applications are described.