(Invited) Process Variability for Devices at and Beyond the 7 Nm Node
Authors: Lorenz Juergen Klaus 
Published: February 2020

Introduction

Advanced CMOS devices are increasingly affected by various kinds of process variations. Whereas the impact of statistical process variations such as Random Dopant Fluctuations (RDF), see Fig. 1 (right), has for several years been discussed in numerous publications, the effect of systematic process variations which result from non-idealities of the equipment used has got much less attention, although the diversity of processes and equipment leads to many different sources of variations. Fig. 1 (left) shows an example for the effect of defocus and dose in optical lithography on the pattern size generated in the photoresist. In order to assess and minimize the impact of variations on device and chip performance, relevant systematic and statistical variations must be simulated in parallel, from equipment through process to device and circuit level. Correlations must be traced from their source to the final result. This enables variation-aware Design Technology Co-Optimization (DTCO). This topic is being addressed by the cooperative European project SUPERAID7 [1].

Approach and examples of results

The SUPERAID7 project especially addresses highly three-dimensional devices as shown in Fig. 2, which are mandatory for advanced CMOS below 10nm. In turn, the development of an integrated topography simulator is one of the core activities of the project. Background tools from IISB and TU Wien for the simulation of lithography (Dr.LiTHO [2]), etching and deposition have been closely integrated, and new models for specific etching and deposition steps have been implemented. Fig. 3 gives an example for the influence of the photoresist shape, which resulted from lithography, on the structure etched into the underlying layer. Simply starting from the resist footprint would lead to erroneous results. Current multipatterning steps are considerably affected by variations in the lithography, etching and deposition steps used, with their propagation strongly depending on details of processing, device and circuit architecture, and circuit layout. For the simulation of subsequent doping steps, Sentaurus Process [3] is employed. The device structures fabricated are subsequently simulated with the variability-aware device simulator GARAND [4]. In order to meet the requirements of very small device cross sections and variations such as surface roughness, several improved physical models for confined carrier transport in nanowires are being developed. Fig. 4 shows the results of quantum mechanical calculations of the electron dynamics in presence of surface potential variations caused by surface roughness, using the so-called Wigner approach. After 400 fs evolution, the systems reach stationary states. High productivity drift-diffusion simulations employing GARAND are required to enable the large number of device simulation runs needed to investigate the impact of statistical variability, such as RDF and surface roughness. Corrections to the drift diffusion approach used are extracted from more sophisticated device modeling work, and implemented as enhancements of GARAND. Furthermore, GARAND has been extended to include the extraction of interconnect resistance and capacitance including effects of metal granularity and wire scaling, and providing SPICE-like netlists for enabling circuit simulations. Fig. 5 shows as an example of an interconnect structure for a 14 nm FinFET based double inverter used as a testbed, namely a sample metal grain granularity (left) and the electric field streamlines calculated with GARAND (right). Finally, using the novel compact model for nanowires LETI-NSP [5] and a hierarchical compact model extraction approach presented earlier [6], both the device without variations (“uniform device”) and the impact of several kinds of variations can be described. Fig. 6 shows the IDVG characteristics of a statistical ensemble of 100 nMOS devices. The overall software system is being bechmarked against experimental data of the project partner CEA/Leti.

Conclusions

Hierarchical variability-aware simulation spanning from equipment through process and device to circuit level is needed to assess and minimize the impact of systematical and statistical process variations on circuits and devices. Especially for highly three-dimensional devices the impact of equipment-induced variations on device topography and performance must be included. In the full presentation several examples will illustrate these effects and solutions provided by the SUPERAID7 project.

Acknowledgement

The research leading to these results has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 688101 SUPERAID7. The author wants to thank the contributors from CEA/Leti, Fraunhofer IISB, Glasgow University, GSS/ Synopsys, and TU Wien.

References

[1] EC Horizon 2020 project SUPERAID7, see www.superaid7.eu
[2] IISB R&D lithography simulator, see www.drlitho.com
[3] Synopsys TCAD, see https://www.synopsys.com/silicon/tcad.html
[4] Garand User Guide, {online}, https://solvnet.synopsys.com, Synopsys, Inc. , 2017
[5] O. Rozeau et al, Proc. IEDM 2016, pp. 7.5.1-4
[6] X. Wang et al., Proc. SISPAD 2015, pp. 325 - 328

Figure 1