bluuebunny/crossref_metadata_2025_split huggingface dataset:
Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique
Authors: Hendarto E. , Toh S.L. , Sudijono J. , Tan P.K. , Tan H. , Goh Y.W. , Zhu L. , Deng Q. , Lin H.B. , He R. , Li H.L. , Mai Z.H. , Lam J. 
Published: December 2020

Abstract
The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.
Comparative Failure Analysis of Photovoltaic Devices
Authors: Colvin Jim 
Published: December 2020

Abstract
Photovoltaic devices (PV) or more commonly “solar cells” are analyzed using LBIC/LBIV (Light Beam Induced Current/Voltage) PL (Photoluminescence) and EL (Electroluminescence) as well as INSB thermal Methods. This paper will show the advantages and pitfalls of the techniques as well as a novel way to perform EL imaging without a dark box and thermal imaging through glass panels.
The Novel Dopant Profile Inspection Methodology by FIB
Authors: Chou Po Fu , Lu Li Ming 
Published: December 2020

Abstract
Dopant profile inspection is one of the focused ion beam (FIB) physical analysis applications. This paper presents a technique for characterizing P-V dopant regions in silicon by using a FIB methodology. This technique builds on published work for backside FIB navigation, in which n-well contrast is observed. The paper demonstrates that the technique can distinguish both n- and p-type dopant regions. The capability for imaging real sample dopant regions on current fabricated devices is also demonstrated. SEM DC and FIB DC are complementary methodologies for the inspection of dopants. The advantage of the SEM DC method is high resolution and the advantage of FIB DC methodology is high contrast, especially evident in a deep N-well region.
Characterization of Green and Ultraviolet LEDs by Laser-Based FA Techniques
Authors: Miller M. A. , Cole E. I. , Tangyunyong P. 
Published: December 2020

Abstract
This work modifies existing nondestructive, laser-based techniques, such as thermally-induced voltage alteration (TIVA) and light-induced voltage alteration (LIVA), to determine precursors to failure in green and UV LEDs. Both TIVA and LIVA have been shown to be effective tools in localizing defects in Si-based integrated circuits and GaAs vertical cavity surface-emitting lasers. In a previous work, TIVA was also used to demonstrate failed InGaN LEDs in the III-V material system. This article expands the use of these techniques to localize potential precursors that lead to premature failures in deep green and deep UV LEDs. The paper shows how the TIVA/LIVA techniques were successfully used to characterize defects in wide bandgap AlGaN- and InGaN-based LEDs. The defects in the green LEDs appear to be electron-hole pair recombination sites and the observed voltage signals are primarily due to a LIVA effect.
Wafer Level Atomic Force Probing
Authors: Kane Terence , Pendyala Sweta , Tenney Michael P. 
Published: December 2020

Abstract
The laboratory practice of employing atomic force probing (AFP) using AFP current imaging and Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identfication of front end of line (FEOL) defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed [1,2,3]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) on bulk silicon wafers and silicon on insulator (SOI) wafers to characterize discrete MOSFET and SOI embedded dynamic ramdom access memory devices (eDRAM) without the time consuming delayering methods of conventional scanning capacitance microscopy has also been highlighted [1,2,3,4,5,6]. Typically, this laboratory AFP characterization is employed on die fragments sampled from whole wafers following back end of the line (BEOL) metallization processing and test. The process vintage of this hardware can be as much as three months after the critical FEOL processing has occurred. This paper is intended to describe for the first time the methodology of applying AFP on whole 300mm wafers at the post CA chemical-mechanical polishing (CMP) process level to provide a real time insight into yield issues that would not be detected until subsequent BEOL metallization processing and testing. This new AFP tool incorporates enhanced features enabling both DC measurements as well as AC capacitance voltage measurements of discrete deep trench embedded DRAM (eDRAM) devices for 32nm, 28nm, and 20nm node technologies.
Use of Lock-In Thermography for Non-Destructive 3D Defect Localization on System in Package and Stacked-Die Technology
Authors: Schlangen Rudolf , Motegi Shinobu , Nagatomo Toshi , Schmidt Christian , Altmann Frank , Murakami Hiroaki , Hollingshead Stewart , West John 
Published: December 2020

Abstract
With the growing variety, complexity and market share of 3D packaged devices, package level FA is also facing new challenges and higher demand. This paper presents Lock-In Thermography (LIT) for fully non-destructive 3D defect localization of electrical active defects. After a short introduction of the basic LIT theory, two slightly different approaches of LIT based 3D localization will be discussed based on two case studies. The first approach relies on package internal reference heat sources (e.g. I/O-diodes) on different die levels. The second approach makes use of calibrated 3D simulation software to yield the differentiation between die levels in 8 die µSD technology.
Identification of Extension Implant Defect in Sub-Micron CMOS ICs – Analysis Technique, Model, and Solution
Authors: Tsang Yuk L. , Nallapati Giri , Skarupa Ron , Anthony Brian 
Published: December 2020

Abstract
A major failure mode known as ROMBIST (logic and memory) that topped the yield loss pareto and plagued a 0.13 m technology chipset production was analyzed. This MCUROM fail exhibited a unique failing pattern where every 4th row failed. A detailed electrical microprobing analysis had led to an exact model that was able to explain the failure mechanism. This model pinpointed a PFET extension implant blockage. Subsequent silicon etch analysis directed by the model prediction brought out the non visual defect (NVD). Inline inspection at the extension implant photo step identified the root cause. A greater than 45% reduction in die cost was realized in lots with photo resist fixes implemented.
Fault Isolation of Dense High Rc Array by Using Conductive Atomic Force Microscopy
Authors: Hu Wei-Shan , Yang Hui-Wen , Huang Yung-Sheng 
Published: December 2020

Abstract
Integrated circuit complexity and density are continuously increasing with the rapid progress of advanced technology nodes. The density of wafer acceptance test (WAT) pattern is also becoming higher as the device continuing to shrink. Failure analysis (FA) techniques have been developed to improve the precision of defect isolation. A technique with more precise fault isolation capability is needed when the test pattern density increased. In this paper we have isolated faults within a dense high Rc array by using conductive atomic force microscopy (C-AFM). The fault sites in the array can be located efficiently with nano-scale precision. Point contact I-V measurements provide a quantitative comparison of the fault sites.
Failure Analysis on Integrated Power Devices
Authors: Chiang Arthur , Le David , Wu Huixian 
Published: December 2020

Abstract
Integrated power devices (IPD, IC+MOSFETs) have gained popularity for their excellent power management performance and compact size. During the development, it was soon found that exposing the multi-die device for debug could be challenging. In the article, we will show how the traditional decapsulation method fails to expose the device properly for follow up analysis. We will then present a new technique using laser ablation + chemical/plasma etch that proves to work for IPD products. We will then present a complete FA example combining this decapsulation technique and many other advanced FA techniques to solve an elusive failure during the development phase of an IPD product.
Deprocessing Methodologies for Detection of IBC and Cell-to-Cell Shorts in Submicron DRAM
Authors: Chitakudige Ramachandra , Dash Sarat Kumar , Khan A.M. 
Published: December 2020

Abstract
Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.
A Practical Method for Trace Exposure and Roughness Measurements and Implementation in High Speed Package Design
Authors: Korchnoy Valentina , Brener Jacov 
Published: December 2020

Abstract
High frequency signal propagation through transmission lines has been an important discipline for RF engineers. With advancements in digital technologies, especially when data rates reached multiple Gb/s, package designers have to consider parameters such as transmission loss and trace impedance in order to maintain signal integrity. For high frequency signals, the surface roughness of the copper trace becomes increasingly significant in determining conduction loss, due to current confinement to the conductor surface by the skin effect. Accurate 3D conductor surface maps are required for correct trace insertion loss simulation. Practical methods for package trace exposure and 3D surface height map acquisition are discussed in this paper. Advantages and disadvantages of these methods, and their implementation to real packages are shown. Using electrical parameters resulting from a 3D trace surface map, the error between electrical simulations and actual measurements of insertion loss in an FCBGA package have been reduced from 6% to nearly zero, enabling tighter margins in 10GB/s high speed serial design.
Sample Preparation Strategies for Fast and Effective Failure Analysis of 3D Devices
Authors: Kwakman Laurens , Straw Marcus , Coustillier Gaëlle , Sentis Marc , Beyersdorfer Jens , Schischka Jan , Naumann Falk , Altmann Frank 
Published: December 2020

Abstract
In this paper different sample preparation strategies for fast and efficient failure analysis of 3D devices are reviewed and further explored. It will be shown that a combined workflow using laser ablation and plasma FIB milling provides best flexibility to cover most of the FA use cases. Laser ablation guarantees fast, coarse material removal and the subsequent plasma FIB milling provides fast removal of any damage or imperfections induced by the laser ablation, precise navigation to the region of interest, a high quality surface finish allowing direct SEM imaging and analytics such as EBSD and, if required the preparation of a thin lamella for TEM analysis.
Glass Interposer Reliability Improvement by Transient Thermal Modelling and Physical Analysis
Authors: Benali A. , El Amrani A. , Bouissa Y. , Bouya M. , Faqir M. , Ghogho M. , Benlahoucine Y. , Sbiaa Z. 
Published: December 2020

Abstract
In this paper we develop a failure analysis approach based on software weaknesses prediction on the glass interposer packaging. The main objective of this work consists of the reliability improvement of through glass via (TGV) by modeling and simulating the transient thermal cycling load on the glass interposer. Our study consists in a single TGV and the whole package models analysis. Then, we will discuss the benefits and issues of each one. Furthermore, a thermal cycling test and physical analysis in critical areas are done in order to identify the defects failure modes.
TEM Sample Fabrication of Sub 22 nm Three-Dimensional Test Structures
Authors: Demarest James J. 
Published: December 2020

Abstract
With the 14nm technology node becoming a reality at today's state-of-the-art semiconductor manufacturing plants and the 10nm node actively being planned for, device structures have shrunk well beyond the minimum conventional transmission electron microscope (TEM) sample thickness: 50-100nm. This paper addresses the challenges in TEM sample preparation of sub 22nm three-dimensional test structures. As semiconductor device technology continues to shrink and become more complicated with the addition of three-dimensional device integration, unique sample preparation challenges will continue to arise. This opens the door to novel solutions for these problems like the one presented in this paper: an issue that arose where TEM projection effects interfered with proper characterization of a finFET test structure.
Early Inline Detection of Systematic Defects Using ATPG and Commonality Analysis on Product-Like Logic Yield Learning Vehicle
Authors: Beaudoin Felix , Song Zhigang , Lucarini Stephen , Mechler Thomas F. , Wu Stephen , Cohen Todd L. , Lagus Mark , Wendel Dieter , Spruth Bruno , Stanley Kevin , Bogdan David 
Published: December 2020

Abstract
This paper presents the successful use of the novel inline product-like logic vehicle (PATO) during the last technology development phases of IBM's 22nm SOI technology node. It provides information on the sequential PATO inline test flow, commonality analysis procedure, and commonality signature trending. The paper presents examples of systematic defects uniquely captured by the product-like back end of the line layout. Moreover, this complex logic vehicle also uncovered a rich Pareto of more than 20 types of systematic and random defect mechanisms across the front end of the line, the middle end of the line, and the back end of the line. And more importantly, the non-defect found rate was kept below 20%. This achievement was possible by: leveraging high volume inline test ATPG scan fail data through the novel commonality analysis approach; and selecting the highest ATPG confidence defects representing a known commonality signature to physical failure analysis.
SAM Assisted Contour Milling
Authors: Hollerith Christian , Krüger Bernd , Waginger Stefan , Plabst Doris , Fritz Matthias 
Published: December 2020

Abstract
Contour milling by high precision CNC-milling offers the possibility to delayer precisely into warped and tilted package interfaces e.g. to expose the die backside. The needed data about the warpage of the surface of interest is in this case derived from SAM time of flight- measurements. The combination of these two approaches solves emerging challenges for backside preparation process.
MicroPREP—A New Laser Tool for High-Throughput Sample Preparation
Authors: Krause Michael , Ebert Martin , Höche Thomas , Wagner Uwe 
Published: December 2020

Abstract
Over the past fifty year, lasers have found many, often groundbreaking applications in science and technology. The most important features of lasers are that photons are inherently free of contamination, extremely high energy densities can be focused in very small areas and the laser beam can be precisely positioned using deflection mirrors. By reducing pulse lengths from a few nanoseconds down to the picosecond or femtosecond range, material ablation is becoming increasingly “athermal”, i.e. structure damage by local heating is reduced to well below a few microns. In view of these outstanding characteristics of lasers, it is very surprising that sample preparation for microstructure diagnostics did not derive the advantages from laser micromachining. microPREPTM, is a new laser-micromachining tool developed by 3D-Micromac capable of making fast, clean, and efficient laser ablation available for the preparation of samples for transmission electron microscopy (TEM). The workflow follows a three-stage approach. First, a supporting basic structure is cut from the feedstock. Second, the supported structure is laser-thinned down to a few microns and third, the supported and laser-thinned structure is thinned using a focused ion beam or an ion broad beam. The examples presented in this paper support this approach and show it is ready to be applied in different areas of microstructure diagnostics and has very high potential for failure diagnostics.
A Case Study of Failure Analysis on ESD-Induced Degradation of 405 nm LD
Authors: Liu Hongmin , Li Zhe , Weng Zheng , Jiang Hao , Shen Yuanting 
Published: December 2020

Abstract
A field failing Ondax’s 405nm Laser Diode (LD) was under failure analysis. The failure analysis (FA) results showed that the LD was very sensitive to ESD and the degradation was ESD induced. Some mechanism explanation is also given in this paper.
Application of Scanning Acoustic Microscopy for Micro Delamination Detection
Authors: Kim Hyunsoo , Lee Seunghyuck , Kim Hakbeom , Kim Sanga 
Published: December 2020

Abstract
This paper describes the detection capability of micro delamination in ICs according to the transducer frequency of SAM (Scanning Acoustic Microscopy) equipment through a case study of non-destructive failure analysis. The analysis of scanning acoustic microscopy is non-destructive, but is difficult to define micro de-lamination or micro crack. In this study, two SAM systems and various transducer frequencies were used to detect micro de-lamination on the lead finger area. In the results of non-destructive analysis by utilizing two systems, one SAM detected the micro delamination but the other SAM did not define micro delamination with C-scan mode. To confirm an accurate delamination phenomenon, we analyze the destructive analysis under cross-sectional inspection and the micro de-lamination was observed. The cause of non-detection for micro delamination is not due to the difference between equipments, but due to the transducer frequency. This paper will be concluded with a discussion on what kind of transducer frequency are selected according to distance from package surface to chip surface, package materials, and micro de-lamination thickness.
Method of Recovering SEM Inspection Induced MOSFETs Degradation before Electrical Characterization
Authors: Lin Qi , Pan Hans , Chang Jonathan , Lin Rung-Jiun , Chang Shih-Hsin , Kuo Pau-Sheng , Chu Chih-Hsun 
Published: December 2020

Abstract
With technology scaling, semiconductor devices have become more prone to damage induced by SEM inspection. In this work, we find that today’s widely-used 0.5KeV SEM can also alter the electrical performance of the devices at 20nm technology node. Vts shift with SEM exposure time on nMOS and pMOS has been studied extensively. The cause of the degradation is the positive charge trapped in the gate oxide during SEM radiation. A conventional UV_eraser for EPROM was applied to SEM-damaged devices. The measurement data show that UV exposure can cure most of SEM-induced damage. In the future, if a regular SEM inspection is followed by nanoprobing device characterization, UV curing or another curing methods is required to recover the electric characteristics of the device before nanoprobing.
Multiphoton OBIC for Device Characterization and Defect Localization
Authors: Johnson Gregory M. , Smith Lloyd , Xu Ziyan , Nakamura Tomonori 
Published: December 2020

Abstract
Applications of MpOBIC (Multi-photon Optical Beam Induced Current) are discussed for use in defect localization. The MpOBIC signals in a ring oscillator under static conditions are examined and demonstrate the superior optical resolution of the system over traditional OBIRCH. A 5-fin diode test structure is examined under passive conditions, demonstrating that true multi-photon OBIC has occurred from the backside. The same diode is examined in forward bias, and the resulting discussion concludes that both OBIC and OBIRCH signals are present in the sample. Thus, we claim that both OBIC and OBIRCH signals can provide device characterization information from an MpOBIC system.
Investigation of Radiation-Induced Response in Advanced Microprocessor
Authors: Bossev Dobrin P. , Duncan Adam R. , Gadlage Matthew J. , Roach Austin H. , Kay Matthew J. , Berger Tammy J. , York Darin A. , Williams Aaron , Ingalls James D. , Szabo Carl M. , LaBel Kenneth A. 
Published: December 2020

Abstract
This work investigates the origin of the single event hard failures of an advanced commercial FinFET microprocessor induced by heavy ions using a combination of failure analysis tools. It focuses on elucidating the reason behind the hard and catastrophic failures of Intel 5th Generation MCP Broadwell microprocessors due to exposure to ionizing radiation. The failure analysis techniques point toward the same area on the platform control hub (PCH) die. Contrary to the initial (intuitive) hypothesis, the hard failures observed in the Intel 5th Generation MCP Broadwell are caused by 32-nm planar PCH die. These failures do not seem to be anyhow related to the FinFET technology, but the exact physical mechanism has yet to be identified. In conclusion, no critical issues or showstoppers were observed during heavy ion testing of Intel 14-nm Tri-Gate FinFET commercial microprocessors, which would prevent these devices from being considered as future space candidate parts.
Optimizing Ex-Situ Lift Out for Frontside or Backside FIB Milling
Authors: Giannuzzi Lucille A. 
Published: December 2020

Abstract
Ex situ lift out is fast, easy, and reproducible, and adds flexibility for either frontside or backside manipulation of focused ion beam milled specimens. ex situ lift out methods may be enhanced by eliminating electrostatic forces. In addition, optimizing the geometry of the specimen relative to the probe improves the Van der Waals forces responsible for the lift out and subsequent manipulation of focused ion beam prepared specimens.
Steps Toward Automated Deprocessing of Integrated Circuits
Authors: Principe E.L. , Asadizanjani Navid , Forte Domenic , Tehranipoor Mark , Chivas Robert , DiBattista Michael , Silverman Scott , Marsh Mike , Piche Nicolas , Mastovich John 
Published: December 2020

Abstract
This paper discusses the development of an extensible programmatic workflow that leverages evolving technologies in 2D/3D imaging, distributed instrument control, image processing, and automated mechanical/chemical deprocessing technology. Initial studies involve automated backside mechanical ultra-thinning of 65nm node IC processor chips in combination with SEM imaging and X-ray tomography. Areas as large as 800μm x 800μm were deprocessed using gas-assisted plasma FIB delayering. Ongoing work involves enhancing the workflow with “intelligent automation” by bridging FIB-SEM instrument control and near real-time data analysis to establish a computationally guided microscopy suite.