Selective-Area Growth of Vertical InGaAs Nanowires on Ge for Transistor Applications
Authors: Yoshida Akinobu , Tomioka Katsuhiro , Ishizaka Fumiya , Chiba Kohei , Motohisa Junichi 
Published: February 2020

1. Introduction

Hybridized integration of III-V compound semiconductors and Ge is expected as a building block for high-performance and low-power III-V/Ge hybrid integrated circuits due to their prospects for high-mobility channel materials of the field effect transistors (FETs). Among III-V compound semiconductors, InGaAs is especially promising channel materials because of its high electron mobility. Furthermore, we can expect good heterointerfaces at InGaAs/Ge when the composition of In in InGaAs is about 70%, thus FETs based on InGaAs channel are expected to outperform their InAs counterpart. However, there are serious issues to integrate III-V materials with Ge, such as mismatches in lattice constant, polarity, and carrier mobility. Selective-area growth of InGaAs nanowires (NWs) would solve these issues because NW-footprint suppress a formation of misfit dislocation due to lattice mismatch. Also, vertical architecture using the NW can shrink their occupied area compared to conventional integrated circuits. Here we report direct integration of vertical InGaAs NWs on Ge substrate by selective-area MOVPE.

2. Experimental procedure

The growth process of NWs started with the preparation of Ge(111) substrates partially masked with SiN for selective-area growth. After a 22nm-thick SiN film was deposited on Ge(111) substrates by plasma enhanced chemical vapor deposition, mask opening was defined by electron-beam lithography, and wet chemical etching. The source precursors for MOVPE growth were trimethylgallium (TMGa) and trimethylindium (TMIn) and arsine (AsH3). To form (111)B polarity on non-polar Ge(111) surfaces, following procedures were taken[1,2]. After the removal of native oxide on Ge surfaces by thermal cleaning in a hydrogen atmosphere, AsH3 was supplied for the replacement of outermost Ge with As. Then, InGaAs layers were grown, firstly by flow-rate modulated epitaxy (FME), that is, by supplying TMIn/TMGa, and AsH3 alternately with hydrogen intervals, followed by conventional MOVPE growth. The growth temperature was 670°Cand composition of TMIn in group III precursors were 63% in vapor.

3. Result and discussion

When AsH3 treatment was performed at 400°C, at which it was successful for InAs[2], only part of the InGaAs NWs grew vertically on Ge. On the other hand, AsH3treatment at 670°C greatly improved the vertical alignment, indicating that (111)B polarity was successfully formed on the Ge(111) and growth direction of InGaAs nanowires was controlled into the vertical <111> direction. Optimization of the NW growth was possible by controlling AsH3 partial pressure [AsH3]. At high [AsH3], the InGaAs had a tendency to grow laterally rather than vertically, and some of the grown InGaAs exhibited short, thick, and/or hillock-like shape and unclear vertical facets. However, the percentage of NWs with vertical facets was increased under low [AsH3] because of the suppression of lateral over growth.To further enhance the yield of NW growth, we optimized number of cycles in the FME. The reduction in the FME cycles markedly increased the yield of vertical NWs, over 90%. This suggests that FME layer thinner than SiN-mask is important to suppresses lateral over growth. We analyzed InGaAs NW with 150nm in diameter and 700nm in height by energy dispersive x-ray (EDX) line profile and transmission electron microscope (TEM). EDX line-profile exhibited that the In-composition of InGaAs NW was about 80% which was larger than that of TMIn in the vapor phase and almost constant throughout the NW expect for its bottom. This suggests that the surface diffusion length of In atom is longer than that of Ga atom, thus In incorporation is enhanced in the NW growth. TEM showed that InGaAs NWs had no threading dislocations due to polarity mismatch. Instead, periodic misfit dislocations were observed at the InGaAs/Ge heterointerface. The period of misfit dislocation was 8.95nm, which was longer than the calculated value (4.37nm) based on their lattice mismatch(5.3%). This clearly indicate that the nanometer-scale footprint of NWs allows lateral deformation and limitations originating from lattice mismatch are less important than in the planer structures.

4. Summary
We accomplished the growth of vertical InGaAs NWs on Ge(111) substrate along the <111>B direction by using selective-area MOVPE. We found that the percentage of NWs with clear vertical facets was improved by the optimization of the AsH3 treatment temperature, number of FME cycles, and partical pressure of AsH3. We also showed the composition of InGaAs NWs and analysis of InGaAs/Ge heterointerface. Further reduction of mask opening and NW diameter is expected to realize dislocation-free interfaces.

5. Reference

[1]K. Tomioka et al., Nano Lett. 8, 3478 (2008).
[2]K. Tomioka et al., Nano Lett. 15, 7253 (2015).