bluuebunny/crossref_metadata_2025_split huggingface dataset:
Monolithic Thin Wafer Stacking Using Low Temperture Direct Bonding
Authors: Burggraf Jürgen , Bravin Julian , Wiesbauer Harald , Dragoi Viorel 
Published: February 2020

Due to the high process temperature required for fusion bonding (e.g. ~1000°C) this process was not attractive for 3D applications. In the recent years low temperature fusion bonding processes were developed for addressing such applications: in such process the maximum temperature ranges typically between 200°C – 400°C.
A low temperature thin wafer stacking process was developed. The low temperature fusion bonding process was used in combination with standard thin wafer manufacturing processes based on temporary bonding/debonding technology in order to demonstrate thin layer direct bonding with subsequent multi-layer stacking capability.
Temporary bonding is an enabling technology to manufacture and securely handle wafers with a thickness of < 20 µm. Thin wafer processing is enabled by temporary bonding the device wafer to a rigid carrier wafer using temporary bonding adhesives which allow subsequent thinning and backside processing of the device wafer. Two different processes for the thin wafer manufacturing and thin wafer stacking capability were evaluated. The process flow for thin wafer stacking is shown in Figure 1 and can be divided into four major tasks: thin wafer manufacturing, surface preparation, wafer bonding and carrier removal.
Experimental data of temporary bonded wafers with a wafer thickness of < 10 µm and a TTV ≤2 µm for 300 mm silicon wafers will be presented.
Low temperature oxide deposition followed by a Chemical Mechanical Polishing (CMP) process was evaluated on the thinned wafers to enable a direct bonding process and to first layer an extensive layer preparation process was performed to enable the stacking of the second layer [2].
The process is compatible with the high cleanliness levels required by CMOS technology and can be used for various application scenarios involving Through-Silicon Vias (TSV) technology.
Optimization of Low Temperature Cu-Cu Wafer Bonding Using Advanced Analytical Methods
Authors: Rebhan Bernhard , Wimplinger Markus , Hingerl Kurt 
Published: February 2020

Metal thermo-compression wafer bonding is a promising candidate for three-dimensional integration of Integrated Circuits (3D ICs). 3D ICs are very interesting as they allow for higher performance due to shorter interconnect paths fabricated in a wafer-level integration approach, even for wafers processed in different technologies. For example, Complementary Metal Oxide Semiconductors (CMOS) and Micro- Electro- Mechanical Systems (MEMS) may be integrated this way. Due to its high electrical and thermal conductivity, low cost, and current availability in numerous IC fabrication facilities Cu is a very attractive bonding material for 3D integration. During the past decade processes were developed for Cu-Cu thermo-compression bonding using about 1 h at 400°C under high contact pressure. A substantial bonding temperature reduction is required in order to optimize post-bond wafer-to-wafer alignment accuracy, to minimize thermo-mechanical stresses, to prevent device degradation (as it is the case for Dynamic Random Access Memories - DRAMs), and to increase the throughput of the bonding process.
The aim of this work was to study the physical mechanisms of Cu-Cu bonding, develop a deep knowledge of the effects of these mechanisms, and then apply this knowledge to optimize the bonding process for low temperatures. This was achieved by preparing 150 mm silicon sample wafers by two alternative methods (Cu sputtering and electroplating) either with or without Chemical Mechanical Polishing (CMP), running a set of experiments covering combinations of wet chemical ex-situ and dry in-situ oxide reducing pre-treatments and then evaluating the results using analytical techniques, such as Atomic Force Microscopy (AFM), Electron Back- Scatter Diffraction (EBSD), Transmission Electron Microscopy (TEM), C-mode Scanning Acoustic Microscopy (C-SAM), several elemental analysis techniques and a qualitative version of the Maszara crack test. Here the used wet chemistry was diluted citric acid (1wt%) and the reducing gas was forming gas (96% Ar + 4% H2). Subsequent to the wafer bonding process, the post-bond annealing was performed in order to increase the bond strength while keeping the retention time in the wafer bonding system as short as possible.
It was determined that for successful low temperature Cu-Cu thermo-compression wafer bonding the following classes of variables have to be considered (i) the contact of the two Cu surfaces, even at atomic scale, (ii) the cleanliness of the Cu surfaces, (iii) the diffusion properties of the two Cu layers and (iv) process conditions. In this paper the measured experimental results are compared with current knowledge and theory. In addition, key variables for establishing a successful bonding process were discussed. Using the fundamental information learned in these experiments it was possible to perform Cu-Cu thermo-compression wafer bonding at and below 200°C (see Figure 1); even room temperature direct bonding is achievable.
Second Order Intermodulation Linearity of a 200 GHz SiGe HBT Technology
Authors: Li Zhen , Niu G. , Wei Xiaoyun 
Published: February 2020

Intermodulation linearity is an important consideration for RF technologies. Third order intermodulation linearity is typically considered, as third order output is close to the fundamentals. Second order intermodulation outputs are far away from the fundamentals, and thus can be filtered [1]. However, the same second order nonlinearity also produces dc offset, which presents a significant problem for direct-conversion receivers [2]. While differential circuits can decrease second order nonlinearity, cancellation is not complete, and is worsened by transistor mismatch.
We present here characterization of the second order intermodulation linearity on 200 GHz peak fT SiGe HBTs. The second order input intercept point, IIP2, is characterized on IC-VCE plane for different breakdown voltages. The measurement system is set up and calibrated according to [3].
Fig. 1 (a) and (b) show the measured IIP2 and fT versus IC for VCE = 1.0, 1.3, 1.6, and 1.9 V on a standard breakdown voltage (SBV) HBT. For comparison, the third order input intercept point (IIP3) is shown in Fig. 1 (c). IIP2 increases with IC before fT roll-off, and then decreases. A higher VCE effectively delays IIP2, fT and IIP3 roll-off overall. The impact is more obvious for IIP2 and IIP3 than for fT. Observe that the IIP3 peak is reached at a much smaller IC, well before peak fT is reached. IIP2 peaks either reside inside the flat fT region or closely lag behind fT roll-off. At high IC, higher VCE shifts IIP2 to higher level, implying that a higher VCE can be used to effectively improve IIP2 at higher currents.
In Fig. 2 (a) and (b) , the current dependence of IIP2 and fT are compared for three HBTs of different breakdown voltage. IIP2 first increases with IC, peaks, and then decreases sharply before rising again. The IIP2 peak occurs approximately at the same current as the fT peak for all breakdown voltages. Before 1 mA, IIP2 is the same for all, indicating that the collector-base junction difference does not affect IIP2 so long as high injection does not occur. A higher VCE could be used with higher breakdown devices to extend the current range of high fT and IIP2, which is also confirmed by measurement.

References

[1] P. Wambacq, W. Sansen, Distortion Analysis of Analog Integrated Circuits, Kluwer, 1998
[2] B. Razavi, RF Microelectronics, Prentice-Hall, 2012
[3] G. Niu, et al., BCTM, pp. 1-4, 2006.
Structural and Optical Properties of Ge1-XSnx Alloys Grown on GaAs (001) by R. F. Magnetron Sputtering
Authors: Pérez Ladrón de Guevara Héctor , Rodríguez A. G. , Navarro-Contreras H. , Vidal M. a. 
Published: February 2020

Ge1-xSnx alloys were grown on GaAs (001) substrates in a conventional R. F. magnetron sputtering system with two independent plasmas not simultaneous focus to substrate. We determined the in-plane and in-growth lattice parameters for different Sn concentrations by high resolution X-ray diffraction (HRXRD). We observed that Ge1-xSnxlayers with low Sn concentrations have pseudomorphic characteristics. But this layers relax at Sn concentrations higher than the ones growth on Ge (001) substrates.
We also determined the band gap transitions and we found that the indirect-direct band gap crossover occurs as is predicted in Ge1-xSnx alloys growth on Ge (001). Raman spectroscopy confirms the presence and Sn concentrations of the Ge1-xSnx layers.
(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of III-V on Si: What About Defect Density?
Authors: Merckling Clement , Waldron Niamh , Jiang Sijia , Guo Weiming , Barla Kathy , Heyns Marc , Collaert Nadine , Thean Aaron , Vandervorst Wilfried 
Published: February 2020

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. The heterogeneous integration of III-V high mobility semiconductors on a silicon platform in a 3D architecture such as Fin-Field-Effect-Transistor is a winning combination to further boost the performance of future CMOS devices.
Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active layers on Si. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy.
We report here on the growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline <111> V-groove structure in Si. We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor.
As a conclusion, this study of the InP selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on patterned Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is an original achievement and confirms the potential of heterogeneous integration approach on a common Si platform.
(Invited) High Ge Content SiGe Thin Films: Growth, Properties and Integration
Authors: Hikavyy Andriy Yakovitch , Rosseel Erik , Dhayalan Sathish Kumar , Witters Liesbeth , Mertens Hans , Bender Hugo , Favia Paola , Loo Roger 
Published: February 2020

Although SiGe with low Ge content was used in BiCMOS devices for a relatively long time, its integration in pMOS transistors at 90 nm technological node opened for SiGe totally new horizons. During the course of years Ge content in SiGe gradually increased, as well as its influence. Nowadays, practically every pMOS transistor is using SiGe either as a strain booster in the case of high performance pMOS or as a SiGe channel allowing Vt correction of low power pMOS transistors. Integration of high mobility materials (SiGe, Ge) in the fin FET fashion seem to be rather logical step in order to move to the next 10 nm technological node and beyond.
In this contribution we will first discuss the growth of SiGe with high Ge content with different precursors like silane, disilane, germane and digermane (Fig. 1).
Next we will elaborate on relaxation of SiGe thin films (plastic and elastic (Fig. 2)) and SiGe processes selectivity.
Finally we will present the integration of high Ge content SiGe in different types of pMOS transistors: Si FinFETs, strained SiGe core FinFETs, strained SiGe cladding FETs and strained Ge FETs (Fig. 3).
Challenges and possible solutions for different pMOS approaches listed above will be put forward.

Acknowledgements

The imec core CMOS program members, European commission, local authorities and imec pilot line are acknowledged for their support.

Fig.1 Ge concentration of SiGe grown with different precursors at different temperatures.

Fig.2 An example of elastic relaxation of SiGe caused by too high process temperature.

Fig.3 Examples of SiGe integration in different device structures. 1) SiGe S/D of Si fin; 2) SiGe core pMOS; 3) SiGe cladding pMOS. 4) SiGe S/D on rGe pMOS.
(Invited) Integrating Classical Semiconductor Devices with Si/Sige Quantum Dots
Authors: Ward Daniel R , Foote Ryan H , Gamble John King , Savage Donald E , Lagally Max G , Coppersmith Susan N , Eriksson Mark A 
Published: February 2020

As semiconductor based quantum devices scale up from single to multiple qubits there is an increasing need to integrate classical semiconductor based devices to manage and generate control signals. We discuss progress on integrating field-effect transistors with planar quantum dot devices to achieve a high level of device throughput by creating on-chip multiplexers for our devices. Using the on-chip multiplexers we can overcome the challenge of the limited number of electrical connections available in a typical dilution refrigerator while still working at the milli-Kelvin temperatures necessary for quantum operations. Additionally, we report on recent work on gate designs for scaling up to multiple, coupled Si/SiGe qubits. In particular we discuss the design, fabrication and initial characterization of quadruple quantum dot devices.
This work was supported in part by the U.S. Army Research Office (W911NF-08-1-0482, W911NF-12-1-0607), the United States Department of Defense, and by the Laboratory Directed Research and Development program at Sandia National Laboratories. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressly or implied, of the US Government. Development and maintenance of the growth facilities used for fabricating samples is supported by DOE (DE-FG02-503ER46028).
Enhanced Thermoelectric Efficiency of Si-Ni Nanocomposite Films Grown on SOI and SOQ Substrates
Authors: Uchida Noriyuki , Ohishi Yuji , Miyazaki Yoshinobu , Kurosaki Ken , Yamanaka Shinsuke , Tada Tetsuya 
Published: February 2020

To improve the poor thermoelectric performance of Si, reduction of the high thermal conductivity k
(~142 Wm–1K–1) is essential, and one of the effective methods to reduce the k
is making Si nanostructures such as Si nanocrystals (NCs) [1, 2] and nanowires[3], where the k
is dramatically reduced by enhancement of phonon scattering at the interfaces of the nanostructures. Recently, we developed semiconducting composite films of Si and Ni silicide NCs (Si-Ni nanocomposite film) deposited on SiO2 substrates [2]with the power factor of 1.9×10-3 W/mK2 , the thermal conductivity k of 4.4 W/mK, and the dimensionless figure of merit ZT of 0.13 for the B-doped (p-type ) nanocomposite film [2], which is much higher than that of bulk Si (ZT<0.01).
In this paper, we demonstrate the further improvement of the thermoelectric performance of B doped Si-Ni nanocomposite films by growing them on silicon-on-insulator (SOI) or silicon-on-quartz (SOQ) substrates. The B doped Si-Ni nanocomposite films were synthesized from amorphous Si-Ni-B films deposited on the SOI or SOQ substrates at room temperature (RT) with Ar sputtering of the B doped Ni-Si target (Ni:Si=1:20, 2mol% B). The amorphous films were annealed at 800°C in N2gas ambient, leading to crystallization and the phase separation of the films. After this annealing , rapid annealing of 10 sec at 1200°C was carried out to activate the B atoms.
In Fig.1, the ZT values are plotted against the k
valuesof Si-Ni nanocomposite films on SOI, SOQ, SiO2 substrates [ 2], and Si nanocomposite by Bux et al. [1] at RT. We observed low k
values (< 4 W/mK) of Si-Ni nanocomposite films on SOI and SOQ, which were similar k with Si-Ni nanocomposite film on SiO2, due to phonon scattering at interfaces on NCs. As seen, the ZTs (0.23-0.36) of the Si-Ni nanocomposite films on SOI and SOQ substrates were much higher than those of the Si-Ni nanocomposite films on SiO2 and the Si nanocomposite. We observed with cross-sectional transmission electron microscopy that Si NCs in Si-Ni composite films were epitaxially grown from thin Si crystal layers of SOI /SOQ substrates, leading to improvement of the crystal quality of Si NCs in the nanocomposite films and increase of the carrier conductivities, the Seebeck coefficients and the ZTs.
This work was partly supported by ALCA-JST.
[1] S. K. Bux, et al., Adv. Funct. Mater. 19, 2445 (2009). [2] N. Uchida et al., J. Appl. Phys. 114, 134311 (2013). [3] A. I. Hochbaum, et al., Nature 451,163 (2008).
Study on Thermal Stability of Dendritic Silver-Coated Copper Powders Fabricated by Galvanic Displacement Reaction
Authors: Zhuo Kai , Park Yu-Seon , Seo Nary , Chung Chan-Hwa 
Published: February 2020

Metals of Group IB due to their higher electrical and thermal conductivities have been thoroughly studied. Particularly, silver electronic slurry extensively used as electrode material in various resistance devices and electromagnetic interference(EMI) shielding materials. But Ag ions cause electro-migration phenomena in hot and humid conditions, which results in decreasing the conductivity and increasing the coating resistance in certain conditions. Copper relatively lower in cost and having good conductivity as silver, but the problem is copper oxidizes when exposed to air. To prevent oxidation of copper, silver coating on copper powder have been reported in many articles.
In structural perspective, the dendritic structure has many superior properties, such as large surface area and good conductivity. Therefore, it is commendable to explore the mechanism of dendritic copper metallic materials formation.
In this presentation, we are reporting a simple fabrication method for copper powder and silver coated copper powder with dendritic morphology at low temperature. To improve the dendritic structure, the galvanic displacement reaction and hydrogen evolution reactions have been applied together. The formation mechanism of Cu dendritic structures on the basis of effect of concentration, termination time, anion concentration, and additives have been prudently analyzed. In addition, we have also analyzed the thermal stability of silver-coated copper powders performance at different temperature.

Figure 1. SEM images of (a) dendritic copper powders and (b) cross section of silver-coated copper powders fabricated by galvanic displacement reaction.

References:

1. B. K. Min and C. M. Friend, Chem. ReV., 107, 2709 (2007).
2. X. Zhu, X. Gan, J. Wang, T. Chen and G. J. Li, Mol. Catal. A: Chem., 239, 201(2005).
3. X. Chen, C. H. Cui, Z. G, J. H. Liu and X. J. Huang, small, 7(7), 858 (2011).
4. X. G. Cao and H. Y. Zhang, Electron. Mater. Lett., 8(4), 467 (2012).
5. M. Wu, B. P. Lin, Y. Cao, J. G. Song, Y. Sun, H. Yang and X. Q. Zhang, J. Mater. Sci.: Mater. Electron., 24, 4913(2013).
6. Y. K. Zeng, T. T. Li, M. F, S. L. Jiang and G. Z. Zhang, J. Alloy Comp., 585, 277 (2014).
7. R. Qiu, H. G. Cha, H. B. Noh, Y. B. Shim, X. L. Zhang, R. Qiao, D. Zhang, Y. I. Kim, U. Pal and Y. S. Kang, J. Phys. Chem. C, 113, 15891 (2009).
Invited: Scaling Mosfets with Self-Aligned Super-Steep-Retrograde-Well
Authors: Zhu Huilong 
Published: February 2020

With aggressively reducing of MOSFET area or IC manufacturing costs, the design space to satisfy both device performance and power consumption requirements becomes very limited. Although strain engineering and high-k/metal gate (HKMG) technique were successfully used to scale planar bulk device down to 28nm technology node, further reduction of gate length requires use of fully depleted channel (FDC) to control short channel effect (SCE). FinFET [1] and UTBB SOI [2] are two typical device structures using FDC. However, significant structural and process changes are involved for both FinFET and UTBB SOI implementations. Super steep retrograde well (SSRW) [3] can be used to reduce depleted depth in the channel of bulk MOSFETs with minor process changes. Two major drawbacks for the devices with SSRW are 1) large band-to-band tunneling (BTBT) or leakage between SSRW and source/drain/extension caused by high doping level and 2) difficult to keep abruptness of SSRW due to large thermal budget used in fabrication process, especially source/drain annealing. To fully take the advantage of state-of-the-art integration flow of all gate last HKMG [4], we propose a new method, called self-aligned SSRW, which forms a SSRW self-aligned to the gate of a bulk MOSFET in replacement gate process. The formation of self-aligned SSRWs can avoid source/drain annealing step and reduce the overlap between SSRW and source/drain/extension. A steep retrograde well can be achieved by a relatively low temperature spike annealing or laser annealing.
Self-aligned SSRW CMOS devices have been fabricated on 200mm Si wafers in our lab. In this paper, we will review and report the first self-aligned SSRW nMOSFETs and pMOSFETs with all-last HKMG process. To investigate the SCE control and BTBT effect by SSRW, an asymmetrical device structure, replaced metal spacer gate (RMSG) MOSFET with an asymmetrical SSRW doping is also introduced. The MOSFETs with self-aligned SSRWs show good SCE control and low off current at a gate length of 25 nm. Dramatically improved DIBL and Ion/Ioff characteristics have been achieved when SSRW doping is used to replace the conventional halo doping. It turns out that with self-aligned SSRW drain-to-body leakage is reduced by upto two decades due to reduction of BTBT leakage current between channel and SD/extension. We have demonstrated that the self-aligned SSRW process is simple and fully compatible with state-of-the-art all gate last CMOS technology, promising for device performance improvement and mass production towards scaling of MOSFETs. Simulations and further improvements for bulk and SOI MOSFETs with self-aligned SSRWs are also discussed.
[1] C. H. Jan et al., IEDM Tech. Dig., pp. 44-47 (2012)
[2] L. Grenouillet et al., IEDM Tech. Dig., pp. 64-67 (2012).
[3] Z. Ren et al., IEDM Tech. Dig., pp. 733 – 736 (2005).
[4] P. Packan et al., IEDM Tech. Dig., pp. 2841-2844 (2009)