bluuebunny/crossref_metadata_2025_split huggingface dataset:
Detecting Power Shorts from Front and Backside of IC Packages Using Scanning SQUID Microscopy
Authors: Knauss L. A. , Frazier B. M. , Christen H. M. , Silliman S. D. , Harshavardhan K. S. , Fleet E. F. , Wellstood F. C. , Mahanpour M. , Ghaemmaghami A. 
Published: December 2020

Abstract
As process technologies of integrated circuits become more complex and the industry moves toward flipchip packaging, present tools and techniques are having increasing difficulty in meeting failure analysis needs. One of the most common failures in these types of ICs and packages is power shorts, both during fabrication and in the field. Many techniques such as Emission Microscopy and Liquid Crystal are either not able to locate power shorts or are inhibited in their effectiveness by multiple layers of metal and flip-chip type packaging. A scanning SQUID microscope can overcome some of these difficulties. A SQUID (Superconducting Quantum Interference Device) is a very sensitive magnetic sensor that can image magnetic fields generated by magnetic materials or currents (such as those in an integrated circuit). The current density distribution in the sample can then be calculated from the magnetic field image, and resolutions approaching 5 times the near field limit can be obtained. We present here the application of a SQUID microscope to physical failure analysis and compare it with other techniques to detect shorted current paths in flip-chip mounted ICs and packages.
Picosecond Imaging Circuit Analysis of the IBM G6 Microprocessor Cache
Authors: McManus Moyra , Sanda Pia , Steen Steven , Knebel Dan , Manzer Dennis , Polonsky Stas , Huott Bill , Wilson Steve , Pelella Tony , Chan Yuen 
Published: December 2020

Abstract
Picosecond Imaging Circuit Analysis (PICA) is a new technique shown here to be applicable to the analysis of complex VLSI circuits. PICA was used to diagnose a timing failure in the early design of the G6 microprocessor chip. The fault occurred at high frequencies upon consecutive writes. Using PICA, combined with programmable array built-in self test (RAMBIST) techniques, the problem was traced to a race condition in the write control circuits. This allowed timely correction of the design for product implementation.
Automated Translation of Final Test Programs to Inexpensive FA Testers
Authors: Bodoh Dan J. 
Published: December 2020

Abstract
To isolate defects in microprocessors, the failure analyst must exercise the device under the failing conditions. Exercising the device with a tester and the final test program is a natural choice. However, populating a lab with production testers can be prohibitively expensive. Bench top testers are an inexpensive alternative. The constraints of these testers make automated test program translation tools hard or impossible to use. In this paper, we describe an automated translation tool that approximates the original test program with very small engineering time, taking into account the target bench top tester's constraints. The tool consists of three parts. First, the production test is simulated, creating a file that represents the waveforms an oscilloscope would see at the device pins. The second step is the most complex and unique part of the tool. It guesses the setup and hold time built into the production test, and manipulates the timing to fit within the constraints of the bench top tester. The final step reduces vector memory requirements and does the final format translation.
Characterization and Fault Identification of Copper BEOL sub-0.25μm Six Level Metal Microprocessor Designs
Authors: Kane T. L. , DeVries K. L. , Tenney M. T. , Patel A. K. 
Published: December 2020

Abstract
Characterizing and fault localizing sub 0.25μm six level copper BEOL microprocessor RISC designs operating above 450 MHz clock speeds pose significant challenges in functional defect localization and identification. The flip chip designs of these microprocessors with high numbers of I/O outputs can involve backside and frontside fault localization techniques such as emission microscopy, OBIC (Optical Beam Induced Current) using I.R. laser scanning microscopy, LIVA (Light Induced Voltage Alteration) [1,2], and PICA (Picosecond Imaging Circuit Analysis)[3,4], to identify the source of functional failures. Refined backside thinning techniques have been applied to optimize I.R. laser scanning microscopy and PICA localization of functional failures. In addition, products using highly structured test methods such as LSSD(Level Sensitive Scan Design) lend themselves to a highly software diagnosable category [5,6]. Such software diagnostics (LSSD diagnostics) when combined with image based fault localization has proven highly effective in pinpointing defects causing functional failures. Examples of electrical and physical characterization of functional logic failures in the six levels electroplated copper BEOL microprocessors will be described. In addition, the electrical characterization of submicron sized SRAM transistor devices using FIB (Focused Ion Beam Microscopy)deposited probe pads [7] will be detailed along with SEM and TEM micrographs of defects identified in this manner.
Analysis of Ohmic Contact Metal Deposition Defect Using FIB/SEM for a GaAs MESFET Clock Buffer IC Device
Authors: Tsai Pei Y. , Bornstein William 
Published: December 2020

Abstract
A major yield detractor in wafer final testing and outgoing production testing of a vendor supplied high frequency Gallium Arsenide (GaAs) clock buffer was encountered. The electrical failure modes are open, short, high Idd and gross functional fails. Physical analysis revealed the ohmic contact extrusion with a burst of Gallium from the substrate (GaAs) like a “mushroom” at the ohmic contact of the active layers of the MESFET and the MIM capacitors. The anomaly was not induced by ESD as it was proved by the ESD simulation test. The ESD test showed a much worse catastrophic damage than the extrusion anomaly. EDAX analysis identified high concentration of Ga in the extrusion. Focused Ion Beam (FIB) and Scanning Electron Microscopy (SEM) analysis of the extrusion showed large voids under the contact area at the defect location. Mis-alignment of interconnect metal to ohmic contact (Au-Ge-Ni) and pinholes in ohmic contact metal to active layers in substrate were found throughout the analysis. The pinholes causes the diffusion area to contact directly to the first level gold (Au) interconnect metal (M1). This results in Au-GaAs interdiffusion (mainly Ga) leaving a large void in the bulk substrate similar to kirkendahl voiding. Additional defects were found when the device was electrically biased. The problem was quickly fixed by slightly adjusting an angle in the sputtering process to provide a complete ohmic contact metal coverage on the diffusion contact and subsequently a yield improvement was resulted.
Identification of Yield Limiting Defects in a 0.5 Micron, Shallow Trench Isolation Technology
Authors: Henderson Christopher L. , Hembree Charles E. , Soden Jerry M. , Headley Thomas J. , Draper Bruce L. 
Published: December 2020

Abstract
During the development and qualification of a radiation-hardened, 0.5 μm shallow trench isolation technology, several yield-limiting defects were observed. The 256K (32K x 8) static-random access memories (SRAMs) used as a technology characterization vehicle had elevated power supply current during wafer probe testing. Many of the die sites were functional, but exhibited quiescent power supply current (IDDQ) in excess of 100 μA, the present limit for this particular SRAM. Initial electrical analysis indicated that many of the die sites exhibited unstable IDDQ that fluctuated rapidly. We refer to this condition as “jitter.” The IDDQ jitter appeared to be independent of temperature and predominately associated with the larger 256K SRAMs and not as prevalent in the 16K SRAMs (on the same reticle set). The root cause of failure was found to be two major processing problems: salicide bridging and stress-induced dislocations in the silicon island.
A Combined Infrared/Visible Photoemission Microscope
Authors: Trigg A.D. 
Published: December 2020

Abstract
The photoemission microscope (PEM) is a powerful and widely used tool for location and identification of failure sites on integrated circuit (IC) chip and wafers. A PEM operating in the infrared (IRPEM) offers several advantages over systems operating in the visible part of the spectrum.. A combined PEM/IRPEM has been built having a cooled (77K) mercury cadmium telluride (MCT) focal plane array (FPA) sensitive in the range 800 to 2500 nm, an intensified charge coupled device (CCD) camera sensitive in the range 350 to 900 nm and a conventional, colour CCD camera. A cooled filter wheel enables the user to select the spectral range of the FPA. Direct comparison of photoemission images obtained in the IR and visible parts of the spectrum is straightforward, while the colour camera permits easy navigation around the device and facilitates probing of wafers. Comparing the sensitivity of the IRPEM with a conventional PEM camera (GEN III intensifier) indicates that for forward bias emission and NMOS emission the IRPEM is approximately 500 times more sensitive. Applications of the system to failure analysis in ICs, sensor devices and electronics packaging are described.
Correlation of Electronic and Thermal Properties of Short Channel nMOSFETS
Authors: Palaniappan M. , Ng V. , Heiderhoff R. , Phang J.C.H. , Fiege G.B.M. , Balk L.J. 
Published: December 2020

Abstract
Light emission and heat generation of Si devices have become important in understanding physical phenomena in device degradation and breakdown mechanisms. This paper correlates the photon emission with the temperature distribution of a short channel nMOSFET. Investigations have been carried out to localize and characterize the hot spots using a spectroscopic photon emission microscope and a scanning thermal microscope. Frontside investigations have been carried out and are compared and discussed with backside investigations. A method has been developed to register the backside thermal image with the backside illuminated image.
Failure Analysis of Flip-Chip Bumps After Thermal Stressing
Authors: Hooghan Tejpal K. , Hooghan Kultaransingh , Nakahara Sho , Wolf Robert K. , Privette Robert W. , Moyer Ralph S. 
Published: December 2020

Abstract
This paper describes a new diagnostic technique for analyzing microstructural changes occurring to flip chip joints after accelerated thermal tests. Flip chip reliability was assessed at high temperatures, with and without the application of electrical bias. A combination of standard metallurgical polishing techniques and the use of a focused ion beam (FIB) lift out technique was employed to make site-specific samples for transmission electron microscopy (TEM) cross-sections. We studied evaporated 95Pb/5Sn bumps, on sputtered Cr/CrCu/Cu/Au as the under bump metallization (UBM). Thermally stressed samples were tested for electrical continuity and evaluated using 50 MHz C-mode scanning acoustic microscopy (C-SAM). Failed samples were crosssectioned and large voids at the UBM were observed optically. TEM specimens taken from the predefined UBM region of degraded flip chip devices provided critical microstructural information, which led to a better understanding of a cause of degradation occurring in the flip chip joints.
Passive Voltage Contrast Application on Analysis of Gate Oxide Failure in 0.25 μm Technology
Authors: Zhigang Song , Khim Loh Sock , Redkar Shailesh 
Published: December 2020

Abstract
With further miniaturization of MOS devices, the thickness of gate oxides becomes thinner and thus more sensitive to damage. Emission microscopy has shown its capability in analysis of these failures. However, emission site is not always the exact location of the physical defect. High-density devices with multi-metal layers make the situation worse. But when it is combined with Passive Voltage Contrast (PVC) technique, the success rate of isolating such failures can be greatly increased. In a case study, a unit of 1M bits Static Random Access Memory (SRAM), fabricated by 0.25 µm technology with 5 metal layers, failed after 500 hours burn-in. We successfully isolated the leaky poly and subsequently found gate oxide pinholes with the combination of PVC technique and emission analysis.
Failure Analysis Process Flows and Common Failure Mechanisms in Flip-Chip Packaged Device
Authors: Hsiung Steve , Chan Victer 
Published: December 2020

Abstract
With the increasing complexity of packaging technology, especially Flip-chip, package failure analysts face challenges to identify failure root cause. Due to the complex construction of Flip-chip packages, the conventional failure analysis process flow needs to be enhanced. Thus, generating a bench marked failure analysis process flow specifically for Flip-chip packaged devices becomes necessary. In this paper, the failure analysis process flow for Flip-chip package devices along with different failure mechanisms will be discussed and demonstrated. For instance, even in a simple continuity-open failure, instead of cross-sectioning the device as the initial fault identification step, the process flow details how to start from non-destructive C-SAM, TDR, to destructive die removal, polishing and finally cross-sectioning.
Characterization and Isolation Techniques in Silicon on Insulator Technology Microprocessor Designs
Authors: Kane T. , Cambra M. , Tenney M. , McGinnis P. , Domenicucci A. , Wang Y. , Falcon D. 
Published: December 2020

Abstract
This paper discusses the challenges involved in testing microprocessors incorporating silicon-on-insulator (SOI) technology and assesses new characterizations tools, such as scanning capacitance microscopy (SCM), focused ion beam (FIB) analysis, and AFM electrical probing, that show promise when used to examine SOI device anomalies and failure modes.
Polarization Difference Probing: A New Phase Detection Scheme for Laser Voltage Probing
Authors: Lo William , Nataraj Nagamani , Boiadjieva Nina , Vedegarbha Praveen , Wilsher Kenneth 
Published: December 2020

Abstract
A novel laser based technique for waveform probing of integrated circuits is presented. This new technique exploits polarization-dependent opto-electronic effects in silicon integrated circuits to give phase sensitivity via a simple common-path interferometer design. The system utilizes a 10 ps pulse-width mode-locked laser to generate equivalent-time sampling pulses. A custom wavelength-tunable and spectrally matched external-cavity laser diode source is used for noise cancellation. A 20-GHz intrinsic system bandwidth with a 2x lower noise-floor, in comparison to current laser voltage probing technology, is shown.
Cavity Up and Stack Die Backside Failure Analysis for Thin Die and High Pin Count Devices
Authors: Nguyen Dat , To Thao , Harrison Ray , Phan Cuong , Drummond John 
Published: December 2020

Abstract
Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.
Improved Electrical Failure Analysis/Fault Isolation Tool Development on Server Motherboard Platforms Based on Historic Failure Modes
Authors: Opdahl Patrick G. 
Published: December 2020

Abstract
Electrical fault isolation constitutes the first steps in characterizing and isolating the failure modes and root causes of a failing motherboard. Ideally the Failure Analysis Test tools provide complete coverage of all motherboard buses and silicon devices. Time and resource constraints for tool development prevent complete coverage, however, so the challenge is to provide the highest level of debug test coverage in the shortest development schedule. A simplified Fault Isolation process has been created based on historical failure analysis data to reduce the development time and resources to create tools which allow diagnosing failure root causes on high-end server motherboards. This strategy prioritizes the most common types of electrical failure modes and the types of Electrical Failure Analysis / Fault Isolation (EFA-FI) tools best suited to diagnose these modes. The benefits of this strategy include shorter EFA-FI development times, equivalent success rates in failure root cause, lower costs, and more effective EFA-FI tools that can be used within the Design Team and at either OEM or Contract Manufacturing sites.
Analysis of 0.13 μm CMOS Technology Using Time Resolved Light Emission
Authors: Ouimet Peter , Goertz Jason , Rinaudo Olivier , Long Lousinda , Yeung Simon 
Published: December 2020

Abstract
This paper describes case histories of 0.13 um bulk CMOS technology analyses using Time Resolved Light Emission (TRLEM). Using this technique, scan chain, timing, and logic failures are shown to be quickly and decisively identified thereby meeting the need for rapid feedback on 1st silicon failures and process excursions.
Scanning Electron Microscope Induced Electrical Breakdown of Tungsten Windows in Integrated Circuit Processing
Authors: Shuttleworth David M. , Drummond Roby Mary 
Published: December 2020

Abstract
Interaction of inline SEM inspections with tungsten window-1 integrity were investigated. Multiple SEMs were utilized and various points in the processing were inspected. It was found that in certain circumstances inline SEM inspection induced increased window-1 contact resistance in both source/drain and gate contacts, up to and including electrical opens for the source/drain contacts.
Semiconductor Inter-Material Analysis Using an FIB Sample Preparation Method and Auger Depth Profiling
Authors: Mulder Randal , Subramanian Swaminathan , Chrastecky Tony , Laberge Paul , Howard Cliff 
Published: December 2020

Abstract
The identification of foreign material at metal-oxide interface or at the poly-substrate interface by means energy dispersive spectroscopy (EDS) is very difficult. Auger depth profiling can be used as an alternative method to cross-section EDS analysis for the identification of very thin layers of foreign material in semiconductor devices. This article presents a sample preparation method adapted from a planar transmission electron microscopy sample preparation method so that Auger depth profiling can be used as a practical tool for identifying very thin layers of foreign materials at interfaces buried deep within semiconductor devices. The discussion covers the advantages, applications, and the procedure for performing the analysis. The high degree of control provided by the method gives an analyst the ability to easily thin down material layers to less than 100nm of a target layer, thereby significantly reducing sample preparation time as well as analysis time on the Auger tool.
Scanning Capacitance Microscopy at Transistor Contact Level
Authors: Ramanujachar Kartik 
Published: December 2020

Abstract
Traditionally, planar scanning capacitance microscopy has been conducted on samples which have been deprocessed to the level of the substrate and an oxide re-grown over the sample. However, HF used to etch the sample to the substrate can also dissolve shallow junctions. This article documents the ability of scanning capacitance microscopy to be utilized at the level of the contacts leaving the pre-metal dielectric intact. It demonstrates the scalability of this technique across three process generations spanning 0.18 micron, 0.13 micron, and 90 nm nodes. The article documents preliminary data on anomalous contrast observed in contacts at both 0.13 micron node and 90 nm node products. It also demonstrates the ability to distinguish between contacts going to a n-type diffusion, p-type diffusion, and transistor gate. The article also presents a simple model for the CV curves of defective contacts to source/drain diffusions.
Multi-Level Approach for High-Precision Cache Fault Isolation—Case Study: Itanium® II Processor Low Voltage Cache Yield Improvement
Authors: Kong Chia Ling , Islam Mohammed R. 
Published: December 2020

Abstract
Fault Isolation / Failure Analysis (FI/FA) of increasingly complex embedded memory in microprocessors is becoming more difficult due to process scaling and presence of subtle defects. As physical failure analysis (PFA) is destructive and involves expensive and time-consuming processes, fault diagnosis needs to be as precise as possible to ensure successful physical defect sighting. This paper introduces a cache Fault Isolation methodology that focuses on exhaustive data collection to derive concrete hypothesis of physical fault location and to overcome the existing FA/FI challenges. The methodology involves a novel application of existing DFT techniques in combination with circuit analysis, pattern hacking, defect localization and PFA tools. Some of the techniques, for example pattern modification or circuit simulation, are applied repeatedly in order to obtain higher-level of isolation – from cell/logic level to transistor/gate level, and finally down to physical structure/layer level. This multi-level FI approach is the key to localize the failing area to greater precision, which had proven itself in Intel Itanium® II processor yield improvement process.
Integrating Logical and Physical Analysis Capabilities for Diagnostics
Authors: Bartenstein Thomas , Koenemann Bernd , Todd Lee , Vallerie Lisa 
Published: December 2020

Abstract
This paper describes and shows some anticipated application examples for an integrated logical/physical analysis environment that utilizes the public-domain OpenAccess database as a key infrastructure element. Using an electronic design automation (EDA) database makes it possible to enrich the failure analysis and debug environment with useful EDA-type utilities and applications. The article introduces the industry-standard OpenAccess data base and illustrates how this database can be used for better integration of a more comprehensive postsilicon debug, diagnostics, and characterization environment. It provides a summary of OpenAccess and highlights the possible role for OpenAccess/Unified Data Model as a complementary technology that captures the more static information about a product's design, design analysis, and design intent information. An initial integrated logical/physical analysis environment for logic diagnostics has been established for prototyping purposes. The article also presents examples of logical/physical analysis: signal interaction analysis and probing and circuit edit.
Single Cell Failures Caused by a Lateral Gate Effect
Authors: Versen M. , Schramm A. , Beer P. , Lindolf J. 
Published: December 2020

Abstract
A single cell failure (SCF) is a common fail signature in dynamic random access memories (DRAMs). Generally write and read problems can be observed if a cell capacitor is not connected properly to its bitline. If the critical resistance of this connection exceeds a given threshold a failure might occur. In this analysis this threshold can be varied by a lateral gate effect of neighboring trenches. The first section gives a short introduction to the problem. An experimental analysis follows in the second section. Simulation results are presented in the third part and a short summary is given at the end.