(Invited) Transistors, Integrated Circuits and Nano-Technology: A Historical Review
Authors: Huff Howard R. 
Published: February 2020

Bardeen and Brattain negated the influence of surface states on Nov 21st and, on Dec 16th, 1947, achieved transistor action – point-contact semiconductor amplification (of minority-carriers) in polycrystalline Ge. Shockley achieved minority-carrier injection over the electrostatic barrier at the source / base interface, into the base region, where the minority-carriers were transported to the collector in polycrystalline Ge (Jan 23rd, 1948). Three years later, Teal achieved (grown) junction transistor action in single-crystal Ge.

Single-crystal silicon was achieved by Teal (Texas Instruments) in 1954, exhibiting higher operating temperature and enhanced minority-carrier lifetime, compared to single-crystal Ge. Although the personnel involved were looking to develop a majority-carrier device, they were amply prepared to absorb lessons they learned with minority-carriers and the solid-state electronics era was initiated. Inasmuch as GeO2 was water soluble, however, it became clear that the goal of a solid-state amplifier and switch, established by Mervin Kelly (Bell Labs) after WW II, could only meaningfully be achieved with single-crystal Si.
With the advent of growing single-crystal Si, a host of solid-state and metallurgical issues arose, described as the process / structure / property methodology. The growth of single-crystal Si and subsequently shaping the Si crystal into slices (the cumulative process), resulted in the unique structure of the silicon slice, facilitating the Si material properties whichdirectly impacted the performance, yield and reliability of the devices and the newly developed Integrated Circuits (ICs), independently introduced by Kilby and Noyce in the mid-1950's. Moore's insightful Moore’s Law(s) and Dennard’s scaling methodology, applied to the DRAM IC, led to unique device structures and configurations, including FinFETS and multiple gate structures, 3D device / IC configurations and quantum wire MOSFET concepts. Silicon wafer product design (see Figure) configured to achieve the desired IC performance, was developed rather concurrently by Lawrence and Huff (America), Takasu (Japan) and Richter (Europe), a direct consequence of the process / structure / property methodology.
The high-temperatures (1200° - 1250°C) utilized during fabrication of bipolar {111} oriented Si ICs was often accompanied by formation of non-equilibrium defects (point, line and surface). The formation of line defects – dislocations – and the associated deleterious effects of plastic deformation during epitaxial deposition and bipolar IC fabrication generally degraded device / IC performance. In a related manner, the control and selective utilization of point-defects was critically important. Oxygen, a point-defect impurity in Si (dissolved from the quartz crucible utilized to hold liquid Si during growth of the silicon crystal) was of immense importance. This included the concept of internal gettering and led to thedevelopment / formationof the multi-zone silicon configuration in the near-surface regions of the silicon slice, including the related de-nuded zone concept around 1980 (see Figure).
A key bipolar device fabrication process, “drive-in” of donor dopant typically in H2 (≥1100°C), often led to the Si surface becoming eroded, pitted or destroyed. Frosch's analysis in the mid '50s led to the utilization (with Derrick) of a wet ambient, creating a protective oxide on silicon during device fabrication, resulting in the formation of planar n-type regions of any desired pattern on p-type silicon (or vice-versa). All other device fabrication procedures were immediately rendered obsolete.
Attala (Bell Labs) showed that SiO2 on properly cleaned and annealed {100} Si slices exhibited a significant decrease of surface states and passivation of the Si surface. Hoerni (Fairchild) pulled all these strands together showing that the SiO2 resulted in the passivation, patternable mask and insulating film for selective, adherent and patterned conducting films for device / IC configurations. The Mesa Silicon Transistor structure gave way to the Planar Silicon Transistor configuration (1960) which accompanied the increase of the silicon wafer diameter from about 0.5-inch (1960) to the current 300mm and now toward the IC industry considering implementation of 450mm.

Introduction of the {100} n-channel MOSFET device configuration likewise required precise control of the silicon surface structure, micro-roughness and site flatness. The thickness / uniformity of the silicon dioxide gate dielectric with equivalent oxide thickness (EOT) <1 nm was critically important for device scaling methodology as described by Dennard. To overcome the high leakage current due to 1nm and below EOT for SiO2, the industry began mining the Periodic Table for higher dielectric constant materials for a sub-1nm EOT gate dielectric, as discussed in a 2004 book edited by Huff and Gilmer. Here also, the silicon wafer product design and the process / structure / property methodology were crucial for MOSFET ICs. Indeed, the IC industry entered the Nano-Technology Era in the early years of the 21st Century!

Figure 1