(Invited) Ultra Fine Pitch 3D Interconnects
Authors: Cheramy Séverine , Bana Franck , Bresson Nicolas , Garnier Arnaud , Arnaud Lucile , Jouve Amandine , Lattard Didier 
Published: February 2020

3D technologies are now in production for high end products. TSV (middle or last) as well as copper pillar have been extensively published over the last few years, specifically for high end memory cubes.
Nevertheless, when talking about very high performance systems (HPC or datacenter) or for imaging application (direct stacking of backside illuminated sensor on Logic device), finer pitch technologies are necessary.
This paper proposes to enter into details on fine pitch Chip-to-Chip interconnections. More particularly, copper pillar and hybrid bonding technologies will be introduced. Two use cases will then be described; first for HPC application and secondly for high end imager application.
1- Chip-to-Chip interconnection
Copper pillars lowest pitch currently available on the market is 40µm. If copper pillar will classically follow the shrinkage trend, the increasing complexity of its integration as well as of the final stacking will make shrink cost prohibitive. Additionally, resistance and capacitance increase due to miniaturization could also discourage designers from using them for advanced partitioning. Thereby, pitch from 20µm to 10µm appear to be the limit. It is one of the reasons why Leti has introduced since few years Cu-Cu hybrid bonding. The latter allowing hermetic bonding without underfill, low resistance and capacitance electrical interconnects and interesting perspectives for ultra-fine pitch.
1.1 20µm pitch copper pillar
After introducing the process flow and optimizations required to adapt to fine pitch, a specific focus will be made on critical process steps: impact of barrier and seed layers nature and thickness, lithography, barrier and seed layers etching.
Morphological characterization of our 3D interconnects has been achieved through interferometric measurements and FIB/SEM technique. A high uniformity over interconnects height has been obtained at wafer scale. Assembly process including pre-applied underfill will also be deeply described.
A test vehicle including daisy chains ranging from 1 to more than 20000 interconnections, has been used to assess process and assembly quality. Electrical tests enable to quickly screen the best assembly configurations. After assembly process optimization, good electrical yields have been obtained and electrical resistance per interconnect is in the range of 45 to 55mΩ.
1.2 Hybrid bonding
The hybrid bonding principle will be introduced. The main advantage of this technology is that neither compression nor underfill is needed. Here, fine pitch interconnect is possible thanks to high accuracy equipment. Furthermore, larger pitch application can also take benefit from the process robustness.
Last results of wafer level fine pitch technology leading to less than 10µm pitch will be detailed. Extensive electrical data as well as wafer level reliability results are given. A resistance contact around 10mOhms/µm² is obtained. Roadmap and early work on more aggressive pitch (in a perspective of a 2µm to 1µm pitch) are presented.
Chip level bonding from its part is based on a similar surface preparation. The complexity here comes from die handling after the wafer level surface preparation: dicing, plasma and chip-to-wafer bonding itself. Process flow will be detailed and daisy chain vehicle test will be described. Electrical data per interconnection show that resistance is very similar to the one obtained at wafer level scale.
2 – Some of potential use cases
2.1 HPC application
It is clear now that we are entering the era of zettabytes of information (1021 bytes). For datacenters, the zettabyte era will have to be a “green” computing era. Interposers are key technologies to provide a cost- and power-effective solution. The performances are nevertheless limited in the case of the passive interposer, which only consists in a copper re-routing. To go further, we propose the new concept of “CMOS interposer,” a high-performance but smaller interposer that embeds some logic functions and power management.
This concept is only valuable if we have very high density of interconnects from die to die, so through the interposer. Pitch of 20µm was simulated and sufficient considering the whole system, knowing that the interposer embeds 150K interconnections.
2.2 Imager application
Stacked imagers, since 2 to 3 years, and more particularly Backside illuminated sensor over logic stack, have been reported by major players in the industry.
Connect as nearer as possible pixels to data treatment is a clear advantage of 3D Stack for imaging.
Wafer level bonding integration is well suited to this application, as both wafers can be prepared in parallel, their yield are supposed to be good (mature process), top and bottom can be designed to have similar size. A test vehicle will be described and electrical data will be given. Early work on reliability (thermal cycling and electromigration) will be detailed.

Figure 1