bluuebunny/crossref_metadata_2025_split huggingface dataset:
Resistive Interconnection Localization
Authors: Cole Edward I. , Tangyunyong Paiboon , Hawkins Charles F. , Bruce Michael R. , Bruce Victoria J. , Chong Wan-Loong , Ring Rosalinda M. 
Published: December 2020

Abstract
Resistive Interconnection Localization (RIL) is a new scanning laser microscope analysis technique that directly and rapidly localizes defective IC vias, contacts, and conductors from the front side and backside. RIL uses a scanned laser to produce localized thermal gradients in IC interconnections during functional testing. A change in the pass/fail state with localized heating of the IC identifies the failing site. The technique reduces the time to locate a resistive via from months to minutes. The sources of defective vias, the physics of RIL signal generation, and examples of RIL analysis are presented.
From Microns to Molecules – Can FA Remain Viable Through the Next Decade?
Authors: Vallett David P. 
Published: December 2020

Abstract
This paper examines the challenges facing IC failure analysis through the projected end of the CMOS roadmap and into the establishment of nextgeneration. nanoelectronic. devices. It will review technology forecasts and assess their effects on major FA categories. The growing importance of fault isolation is highlighted, especially for nanoelectronic ICs where deviations on the order of one atom or electron will find current instruments two orders of magnitude removed in capability. The potential impacts of self-assembled chips and fault-tolerant architectures are also discussed.
Soft Defect Localization (SDL) on ICs
Authors: Bruce Michael R. , Bruce Victoria J. , Eppes David H. , Wilcox Jacob , Cole Edward I. , Tangyunyong Paiboon , Hawkins Charles F. 
Published: December 2020

Abstract
We have developed a new scanning laser microscopy methodology, Soft Defect Localization (SDL), that directly locates soft defects from the front side and backside of an IC. The method combines localized laser heating with the pass/fail state of a device to successfully localize soft defects. Subtle, thermally sensitive soft defects can be localized by careful selection of the IC voltage, temperature, and operating frequency. Several examples are shown.
Evaluation of Package Defects by Thermal Imaging Techniques
Authors: Liu Yongmei , Dias Rajen 
Published: December 2020

Abstract
Study presented here has shown that Infrared thermography has the potential to be a nondestructive analysis tool for evaluating package sublayer defects. Thermal imaging is achieved by applying pulsed external heating to the package surface and monitoring the surface thermal response as a function of time with a high-speed IR camera. Since the thermal response of the surface is affected by the defects such as voids and delamination below the package surface, the technique can be used to assist package defects detection and analysis.
Backside Photoemission and Infrared Microthermography for Rapid Debug of Compound Semiconductor Devices
Authors: Mitra S. , Kiefer S. , Nair M. , Sanders P. , Steele J. , Sutton M. , Wilson S. , Henry H. , Hill D. , Sadaka M. 
Published: December 2020

Abstract
Visible to infra-red photon emissions can be readily observed in compound semiconductor devices through the semi-insullating substrate and are useful in fault identification when analyzing yield problems. The techniques described here have uncovered several yield-limiting mechanisms and have lead to rapid and effective corrective measures.
Thin-Die Flip Chip Physical-FA Process Flow
Authors: Komrowski Andrew J. , Somcio N. S. , Sullivan Daniel J. D. , Silvis Charles R. , Curiel Luis , Baca Jeff P. , Scott Steven , Sandoval Mary 
Published: December 2020

Abstract
The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.
Beam-Based Localization Techniques for 0.18um IC Failure Analysis After Reliability Test
Authors: Chiu Re-Long , Zhang Hui , Chung Wen-Szu , Cherng Mark , Liu Xu 
Published: December 2020

Abstract
Locating the defect site in current devices is complicated by their density and size. Voltage contrast (VC) imaging and backscattered electron (BSE) imaging are non-destructive beam-based location techniques. We can locate the defect to single poly line, contact and via by combining EMMI, LC, layout and bit map address information. Some reliability failure analysis cases are presented to demonstrate the effectiveness of the beam-based techniques. VC imaging and BSE imaging are used to locate the defect site precisely. The subsequent steps include deprocess and precision FIB cut for sample preparation. SEM or TEM is then used to identify failures caused by gate oxide pinhole, contact junction leakage, high butted contact resistance or tungsten residue.
Application of Various Fault Localization Techniques to Different Types of 6T-SRAM Column Failures
Authors: Lin Cheng-Piao , Ting Cheng-Chun , Tang Chin-Hsin , Wu Cheng-Hsu , Kuo Chih-Ming , Huang Yung-Sheng 
Published: December 2020

Abstract
In this paper, we demonstrate different techniques of fault isolation from front-side of 6T-SRAM column failures. We show how to choose proper and suitable methods to solve column failures with a variety of characteristics. The capabilities and physical mechanisms of OBIRCH, photoemission microscope and LCA are reviewed utilizing these SRAM column failures.
Failure Analysis of Polysilicon Micromirror Arrays
Authors: Walraven Jeremy A. , Cole Edward I. , Tanner Danelle M. , Mani Seethambal S. , Garcia Ernest J. , Polosky Marc A. 
Published: December 2020

Abstract
Surface micromachined micromirror technologies are being employed for various commercial and government applications. One application of micromirror technologies in the commercial sector can be found in Digital Light Projection (DLP™) systems used for theater and home entertainment centers. DLP™ systems developed by Texas Instruments uses DMD™ technology (Digital Mirror Device), an array of micromirrors, to project light onto a screen [1]. This technology is also used by Infocus™ projection systems and widescreen tabletop televisions [2]. Here, the micromirrors act as individual pixels, reflecting light onto the screen with high ¡§digital¡¨ resolution. The most recent application of surface micromachined micromirror technology is optical switching [3], which uses micromirrors to switch optical signals from fiber to fiber for lightwave telecommunications [4]. Companies such as Lucent have fabricated entire optical micromirror switching systems based on their Microstar™ technology [5]. For government applications, surface micromachined micromirror arrays have been developed for potential use in a spectrometer system planned for NASA's Next Generation Space Telescope (NGST) [6]. Various processing technologies are used to fabricate surface micromachined micromirrors. The micromirror arrays developed by TI and Lucent [1,4] uses metal for their structural and reflective components. Micromirrors fabricated at Sandia National Laboratories use the SUMMiT™ (Sandia's Ultra-planar MEMS Multi-level Technology) process with metal deposited on the surface of mechanical polysilicon components to reflect light. Optical micromirror arrays designed and fabricated at Sandia for potential use in the NGST have undergone reliability testing and failure analysis. This paper will discuss the failure modes found in these micromirrors after reliability testing. Suggestions and corrective actions for improvements in device performance will also be discussed.
A Standardized Scientific Method Formulation for Failure Analysis Application
Authors: Ferrier S. 
Published: December 2020

Abstract
Methodology remains an underdeveloped segment of the semiconductor Failure Analysis discipline. This paper describes a general formulation of scientific method for semiconductor Failure Analysis. The formulation creates a rigorous, customized analysis flow that flags both poorly-understood cause-effect relationships and missing techniques. It eases the application of basic inferential logic to the resulting analysis process, helping reduce errors in the analysis thought process. Finally, the methodology provides a uniform nomenclature and representation of the analysis process that lets the analyst describe complex flows in a simple and informative way. This general material has been presented by SDG Analytic, Inc. (now Metatech Corporation) in a public training course called “Precision Failure Analysis Logic.”
Picosecond Imaging Circuit Analysis of Leakage Currents in CMOS Circuits
Authors: Polonsky Stas , Weger Alan , McManus Moyra 
Published: December 2020

Abstract
The light emission from ever increasing OFF-state leakage currents in advanced CMOS technologies can now be reliably measured using existing photon detectors. The measurements of such an emission provide valuable information about the operation of ICs. In this paper we suggest and experimentally confirm two new techniques based on such measurements - Transient Logic State Detection and Power Supply Noise Analysis.
Tin Whiskers on Discrete Components: The Problem
Authors: Siplon Jocelyn P. , Ewell Gary J. , Frasco Eric , Gibson Tom , Brusse Jay A. 
Published: December 2020

Abstract
This paper discusses the issues of tin whisker growth on discrete electronic components. It presents both a critical analysis of existing published documents on tin whisker nucleation and growth and a summary of very recent experiments that provide further understanding of the potential means of whisker formation mitigation. Many of the proposed techniques for reducing the likelihood of whisker formation are inadequate, including control of the immediate underplating material, use of conformal coating, regulating the thickness of the tin coating, use of matte tin electroplating, and annealing or fusing of the tin layer. They likely reduce the incidence of nucleation or growth but do not provide guaranteed protection from lack of whisker formation. The first report of tin whiskers on electronic components dates back to 1946 [16]. Since that time whisker-related problems have been reported consistently. Today the concern is for the of increased number of whisker-related problems due to circuit geometry reductions, lower application voltages and the probability of more suppliers (rapidly) introducing pure tin plated alternatives to comply with pending Pb-free legislation.
Failure Analysis of LCD Drivers: A Case Study
Authors: Telles A. C. C. , Felix L. R. , Comerlato M. H. , Mammana A. P. , Rozario D. S. , Eleutério Filho S. 
Published: December 2020

Abstract
A manufacturer of computer based products in Brazil has experienced a sudden increase of failures in the LCDs (Liquid Crystal Displays) used in its products returned from field. The failures appear as dark columns. This paper describes the technique applied to find out the root cause of the failures. Conclusions pointed to a problem in the process for curing the adhesive conductive film (ACF), which provides connection of flip chip drivers to the LCD.
Plastic BGA Module FA Process Flow Development
Authors: Wang Zhaofeng , Wagner Lars , Cheah Chuan 
Published: December 2020

Abstract
A failure analysis process flow development for a board mount plastic BGA multichip module is described. Both front and backside approaches are investigated. Following the probing (at both front and backside), front side chemical de-cap procedure is also developed to expose the components without disturbance. The development of this failure analysis process flow has successfully isolated defective IC dice, identified a die attach interface corrosion mechanism, and assembly related die top mechanical defects. This process can be adopted to failure analysis for other plastic BGA modules.
Microprobing on Sub-Micron Features on ICs Using an AFM Based Technique
Authors: Goruganthu Rama R. , McBride Shawn , Santana Mike , Mahanpour Mehrdad 
Published: December 2020

Abstract
Traditional microprobing on conventional wirebonded packages is difficult on sub-micron feature sizes. The problem becomes even more complex with flip-chip packaged devices as access to circuitry is limited because of the substrate silicon. We describe here an Atomic Force Microscope (AFM) based tool for microprobing that we term “nanoprobing” because of the feature sizes that can be probed with this tool. Three applications have been described here where voltage levels or waveforms are measured. These include probing on: A single metal-layer test chip that is wire-bonded to a 40-pin DIP package, a 3-layer CMOS circuit that is wire bonded to a 48 pin DIP package, and a 5-metal layer CMOS circuit that is flip chip packaged to a 321 pin PGA package.
Microstructure Studies of Under Bump Metallization Systems Using Transmission Electron Microscopy
Authors: Tung Chih-Hang , Teo Poi-Siong , Lo Marvin C.Y. , Sheng George T.T. 
Published: December 2020

Abstract
In this study, the interface reactions between eutectic SnPb solder and two Ni-based UBM systems are reported, namely the sputtered Cu/Ni(V)/Al and the electroless Au/Ni(P) systems. Comparisons are made to the conventional Au/Al ball bonding system in terms of microstructure evolution, and metallurgical stability. TEM sample preparation is critical in this analysis. The capability of TEM in UBM microstructure studies is demonstrated.
Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail
Authors: Weizman Yoav , Baruch Ezra , Zimin Michael 
Published: December 2020

Abstract
Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.
Laser Beam Based ESD Defect Localization in ICs
Authors: Beaudoin Félix , Perdu Philippe , Desplats Romain , Doche Emmanuel , Wislez Alain , Beauchêne Thomas , Lewis Dean , Carisetti Dominique , Trémouilles David , Bafleur Marise 
Published: December 2020

Abstract
The application of laser beam based techniques for ESD defect localization in silicon and gallium arsenide integrated circuits is studied. The Thermal Laser Stimulation technique (OBIRCH, TIVA) is shown to precisely localize electrostatic discharge (ESD) defects under low voltage and current consumption, thus avoiding device or defect degradation upon testing. It is also shown that nonbiased Thermal Laser Stimulation (SEI) tests can localize ESD defects in the silicon substrate. Physical analysis revealed that a thermocouple composed of molten silicon with crystalline silicon generated a Seebeck voltage sufficiently large to be detected. Finally, the pulsed Optical Beam Induced Current technique (OBIC) under no bias condition was evaluated and compared to both biased and nonbiased Thermal Laser Stimulation techniques. It proved to be complementary as it offers a different insight into the ESD induced degradation.
Advanced sub 0.13µm Cu Devices – Failure Analysis and Circuit Edit With Improved FIB Chemical Processes and Beam Characteristics
Authors: Casey J. David , Gannon Thomas J. , Krechmer Alex , Monforte David , Antoniou Nicholas , Bassom Neil , Huynh Chuong , Silva Brian , Hill Raymond , Gu George , Ray Valery , Saxonis Andrew , Chandler Clive , Megorden Michael , Carleson Peter , Phaneuf Michael , Li Jian 
Published: December 2020

Abstract
Advances in FIB (focused ion beam) chemical processes and in the Ga (gallium) beam profile are discussed; these advances are necessary for the successful failure analysis, circuit edit and design verification of advanced, sub-0.13µm Cu devices. Included in this article are: a novel FIB method (CopperRx) for smoothly milling thick, large grained Cu lines; H2O and O2 processes for cleanly cutting thin, smaller grained Cu lines, thereby forming electrically open interconnects; a XeF2 GAE (gas assisted etching) process for etching low k, CVD dielectrics such as F and C doped SiO2; H2O and XeF2 GAE processes for etching low k, spin-on, organic dielectrics such as SiLK; a recently developed recipe for the deposition of SiO2 based material with intermediate resistivity (106 µohm·cm) which is useful in the design verification of frequency sensitive, high speed analog and SOC (system on chip) circuits; an improved, more Gaussian Ga beam with less current density in the beam tails (VisION column) which provides higher resolution, real time images needed for end-point detection on sub 0.13µm features during milling.
Microwave Frequency Signal Propagation in Backside Focused Ion Beam (FIB) Fabricated Interconnects
Authors: Rowlette Jeremy A. , DiBattista M. , Fortuna Seth , Livengood Richard H. 
Published: December 2020

Abstract
We present for the first time the results of a comprehensive study of the increase in propagation delay of multi-GHz digital signals due to backside FIB fabricated interconnects. Signal propagation delays were measured in 90nm CMOS technology circuits as a function of interconnect material properties and physical dimensions. We compare the empirical results of this study to SPICE calculations, which were based on an equivalent circuit element model of the interconnect. We show that the empirical data obtained in these experiments supports the validity of the equivalent electrical model for the frequency range typically encountered in modern microprocessor debug. Based on the results or our analysis, we comment on the future capability of backside FIB circuit edit (CE) interconnection technology as it pertains to the debug of flip-chip packaged IC’s operating at multi-GHz frequency.
Driving Baseline Yields on ASICs Using Logic Mapping
Authors: Benware Brady R. 
Published: December 2020

Abstract
Logic mapping is the process of automatically correlating inline inspection defects with diagnosed faults from electrical testing. This paper presents a software based tool for this purpose and focuses on its specific use for impacting baseline yield enhancement. A detailed approach to utilizing logic mapping for this purpose is also presented. Results from a 10 wafer study using this tool are analyzed and show a defect correlation success rate of 31%. Additional work is presented for improving the logic mapping success rate and diagnosability of failures.
Boundary-Scan’s Next Plateau: Testing and In-System Configuration at the System Level
Authors: Collins Pete , Dellecker Ray 
Published: December 2020

Abstract
Boundary-scan is a technology that’s been around for over ten years and is delivering the results foreseen by the IEEE working group that developed the 1149.1 specification. Many SMT (surface mount) production lines around the world use boundary-scan to solve the testing challenges presented by today’s complex designs. These users are realizing the vision of the specification, using it to restore test access and fault coverage to assemblies with few physical test points relative to the number of electrical nets to be tested. As the boundary-scan standard has gained acceptance and credibility, users, chip vendors and tools providers have developed important extensions of the original vision. Among the extensions already available or under active consideration is the use of boundary-scan for analog testing, concurrent programming of multi-vendor cPLD’s, dynamic verification of high-speed communication channels, and application within higher-level electronic assemblies beyond printed circuit boards i.e. to subsystems and systems. This paper describes the effectiveness of boundaryscan at the system level, focusing on the use of IEEE Std. 1149.1 compatible devices and ATPG tools to accomplish system level testing and in-system configuration.
Case Studies of IR Based Rapid PC Motherboard Failure Analysis
Authors: Swart Jan , Woo John , Zumwalt Randall , Birdsley Jeff , Taffese Yitages 
Published: December 2020

Abstract
This article discusses the techniques useful in the failure discovery process in PC motherboard. It discusses the application of infrared (IR) camera in failure analysis, which overcomes time consumption problems. The article focuses on the experience gained from nine different case studies, where IR thermography system was used to both measure relative temperatures as well as absolute temperatures of components. The failures investigated are overdriven components, finding end-of-life but still functional components, correctly specified components with quality defects, incorrect component placement, internal voltage common collector to ground low resistance integrated circuits failures, PCB defects resulting in power to ground failures, soldering defects resulting in lead opens or solder bridges, and copper trace manufacturing defects or stress-induced cracks.
Circuit Voltage Probe Based on Time-Integrated Measurements of Optical Emission From Leakage Current
Authors: Stellari Franco , Song Peilin , Tsang James C. , McManus Moyra K. , Ketchen Mark B. 
Published: December 2020

Abstract
Hot-carrier luminescence emission is used to diagnose the cause of excess quiescence current, IDDQ, in a low power circuit implemented in CMOS 7SF technology. We found by optical inspection of the chip that the high IDDQ is related to the low threshold, Vt, device process and in particular to transistors with minimum channel length (0.18 μm). In this paper we will also show that it is possible to gain knowledge regarding the operating conditions of the IC from the analysis of optical emission due to leakage current, aside from simply locating defects and failures. In particular, we will show how it is possible to calculate the voltage drop across the circuit power grid from time-integrated acquisitions of leakage luminescence.