Optimization of Copper Electrodeposition in High Aspect Ratio through Silicon Vias
Authors: McDow Jessica , Coleman Jonathan , Hirabayashi Mieko , Jordan Matthew B. 
Published: December 2024

Copper-filled through silicon vias (TSVs) are a key technology for 3D integration of microelectronic devices. 3D integration enables system miniaturization, increases bandwidth per volume, and improves device performance. In general, TSV copper filling processes are designed to be used with thinned wafers (<200 um), but some TSV last and microelectromechanical systems (MEMS) require full wafer thicknesses, where additional mass of the full wafer is advantageous. For high-power devices, large scale vias or via arrays can be used both to supply power and for thermal management. Copper (Cu) is a preferred material for TSV filling because of its high electrical and thermal conductivity and can be deposited through electrochemical deposition (ECD) to fill high aspect ratio features. Although Cu ECD has been historically performed using three additive systems, recent work has demonstrated that Cu deposition can be achieved in a simplified CuSO4-H2SO4 electrolyte with only a single suppressor additive and halide salt.1,2 The cyclic voltammetry (CV) scan for this electrolyte exhibits s-shaped negative differential resistance (S-NDR), observed as hysteresis in the CV voltage-current relationship between forward and reverse scans. Hysteretic voltammetry indicated bifurcating behavior in the electrolyte system, where bottom-up filling is possible in the vias, while the field surface remains passivated. In systems with limited suppression, performing ECD with a sustained potential leads to localized Cu deposition at specific depths within the vias. An increasingly negative potential waveform can be implemented to progressively move deposition vertically through the vias. Typically, a bottom-up, void-free fill is achieved with this additive-based electrolyte through a potentiostatic plating process with a reference electrode. Voltage-controlled ECD parameters have been developed through the S-NDR mechanism for bottom up filling of high aspect ratio vias, where potential stepping was performed from -500 mV (MSE) to -560 mV (MSE) in -10 mV increments, and each potential was held for 2 to 5 hours to ensure a void-free fill.3 Currently this is a time consuming procedure, with a 17 hour plating process excluding sample preparation.
This work shows an optimization method for filling high aspect ratio through silicon vias (TSVs) that provides insights into the fluid replenishment as well as the diffusion and suppression kinetics for this superfilling electroplating chemistry. Both experimental results and computational predictions are shown to better understand the effects of applied plating potentials and the fluid mechanics of this plating process. Understanding the chemical transport of cupric ions and additives is important to both the adsorbed suppression layer formation and disruption within the feature. The S-NDR suppression/fill mechanism is sensitive to the via geometry, ion replenishment, as well as the overpotential during the electroplating process. We demonstrate a time-dependent process window where early on too high of an overpotential results in suppressor breakdown and too low of an overpotential results in complete suppression of the deposition process. Figure 1(a) shows that by controlling the voltage between -520 mV (MSE) and -560 mV (MSE), we were able to demonstrate complete fill of the TSVs in 30% of the time previously required for filling. We also hypothesize that there is a maximum void-free fill rate for suppressor only chemistries. To understand the dependence on solution replenishment and applied bias in a given electrolyte, a series of investigations were performed on samples rotated at different rates as shown in Figure 1(b). This investigation was also shown computationally to optimize void-free, bottom-up plating when changing to different via geometry and array densities. Understanding the filling kinetics and fluid dynamics provides a throughput target for microelectronic devices.

Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. SAND

(1) Josell, D.; Moffat, T. P. Superconformal Copper Deposition in Through Silicon Vias by Suppression-Breakdown. J. Electrochem. Soc.
2018, 165 (2), D23–D30. https://doi.org/10.1149/2.0061802jes.
(2) Menk, L. A.; Josell, D.; Moffat, T. P.; Baca, E.; Blain, M. G.; Smith, A.; Dominguez, J.; McClain, J.; Yeh, P. D.; Hollowell, A. E. Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology. J. Electrochem. Soc.
2019, 166 (1), D3066–D3071. https://doi.org/10.1149/2.0091901jes.
(3) Schmitt, R. P.; Menk, L. A.; Baca, E.; Bower, J. E.; Romero, J. A.; Jordan, M. B.; Jackson, N.; Hollowell, A. E. Void-Free Copper Electrodeposition in High Aspect Ratio, Full Wafer Thickness Through-Silicon Vias with Endpoint Detection. J. Electrochem. Soc.
2021, 167 (16), 162517.

Figure 1