bluuebunny/crossref_metadata_2025_split huggingface dataset:
Quantitative Phase Shift Analysis for 3D Defect Localization Using Lock-in Thermography
Authors: Schmidt Christian , Altmann Frank 
Published: December 2020

Abstract
It was already demonstrated, that the method of Lock-in Thermography (LIT) enables 3D localization of thermal active defects, e.g. electrical shorts and resistive opens, on die level and within fully packaged single and multichip devices [1,2]. The depth of a defect can be derived from phase shift measurements of the defective compared to a reference device For a general approach of this method, thermal modeling is used and verified by experimental data to investigate the internal heat propagation under periodic stimulation in correlation to the LIT measuring process. [3]. A basic requirement for the successful application of the method is a precise and reproducible measurement of both the thermal material properties of each material layer and the phase shift between the internal heat excitation and thermal response measured by LIT. Significant influences from the material and measurement setup to the detected phase shift have to be identified and taken into account. However, to identify and distinguish the relevant influences measurements with defined internal heat sources are necessary which are presented in this paper. First, the relationship between geometrical thickness of a material layer and the resulting thermal parameters for both homogeneous and heterogeneous materials are measured and discussed. A new measurement setup generating a defined point heat source will be presented to calibrate the LIT system for quantitative phase shift measurements and to determine the phase shift to thickness parameters of single material layers. In addition the variation of the phase shift caused by the defect geometry and the defect environment will be investigated. Finally, a case study is presented comparing the experimental results to the obtained results from a real stacked die device.
Development of an Automated TDR System for Package Failure Analysis
Authors: Basilioa Christopher C. , Nguyenb Hieu Trong , Aguinaldoc Arlene , Arboledac Jan Paul , Angd Richmond , Anod Daniel , Paranald Paul , Magpantayd Armand 
Published: December 2020

Abstract
This paper describes the successful effort to develop the Time Domain Reflectometry (TDR) tool by automating the equipment process. The current challenges in the tool usage brought about by miniaturization in the package technology presented itself as an opportunity for the tool improvement. The authors were able to devise an automated TDR system which is ergonomically safe, yielded a significant through put time reduction and provide a consistent and accurate result. This comes at a lower cost in comparison to the current system available in the Virtual Factory (VF).
Methodology and Application of Backside Physical Failure Analysis
Authors: Lai Li-Lung , Chen HungLing , Gao Huimin 
Published: December 2020

Abstract
There are some advantages to performing physical failure analysis from the backside as opposed to normal frontside analysis. However, there are challenges to be overcome with regard to sample preparation and scanning electron microscopy. Thus, we introduce this unusual technique to overcome the barrier of difficulty. This technique can eventually lead to the development of a versatile methodology that can be used in actual applications for failure analysis.
Leaky Device Channel Anomaly Identification and Case Study by Nano-Probing Technique, Curve Fitting, and Model Analysis
Authors: Wang Wei-Chih , Sung Ching-Shan , Lin Ya-Hsiu , Chen Haw-Shan , Luo Jian-Shing 
Published: December 2020

Abstract
This paper demonstrated the use of curve fitting method on device transfer characteristic curve for device carrier mobility analysis and failure mechanism verification. In the content, a systematic device characterization was performed to identify device failure mode and failure site. Based on physical observations and electrical results, a device gate oxide boron penetration failure mechanism and an unexpected subtle p-type dopant at p-MOS device channel area was conjectured. However, this unexpected p-type dopant was successfully proved by subsequent carrier mobility analysis results, and the gate oxide boron penetration failure mechanism was accordingly verified.
Dual-Phase Interferometric Confocal Imaging for Electrical Signal Modulation Mapping in ICs
Authors: Yurt A. , Ramsay E. , Köklü F. H. , Stockbridge C. R. , Lu Y. , Ünlü M. S. , Goldberg B. B. 
Published: December 2020

Abstract
This paper demonstrates a differential dual-phase interferometric imaging method in which the reflected probe beam modulated weakly by the charge carriers is mixed separately with two reference beams with a known phase shift in between. Performing a balanced detection scheme on these two channels, the common-mode-noise associated with strong DC background and its noise can be significantly reduced. The performance of the interferometric technique is systematically compared with the conventional mapping method through investigating inverter chains on two test chips of 180nm bulk silicon technology and 32nm SOI technology. The future work will focus on adapting the method for GHz frequency regime and time-domain implementation of the method. The method will find applications in failure analysis and testing of advanced technology IC chips for which the high sensitivity in modulation mapping is required.
Energy-Filtered Imaging of Polysilicon Defects, Gate Dielectric and Silicon Nanocrystals Using Plasmon Energy-Loss Electrons
Authors: Subramanian Swaminathan , Ly Khiem , Chrastecky Tony 
Published: December 2020

Abstract
Transmission electron microscope based elemental analysis techniques utilize X-ray photons in EDS and inelastically scattered electrons or the energy-loss electrons in electron energy-loss spectroscopy and energy-filtered transmission electron microscopy (EFTEM). This paper discusses the applications of EFTEM to visualize polysilicon defects, gate dielectric and silicon nanocrystals using inelastically scattered low energy-loss electrons. It focuses on features that are primarily composed of silicon and silicon-oxide. Various benefits of using plasmon energy-loss electrons to image silicon nanocrystals layer in thin film storage device are also outlined. Even though this work has focused on low-loss imaging of features and defects in the front-end of the process based on silicon/silicon-oxide integrated circuits, these techniques can also be applied to technologies based on other materials by selecting appropriate plasmon peaks corresponding to those materials.
A Superconducting Nanowire Single-Photon Detector (SnSPD) System for Ultra Low Voltage Time-Resolved Emission (TRE) Measurements of VLSI Circuits
Authors: Stellari Franco , Weger Alan J. , Kim Seongwon , Maliuk Dzmitry , Song Peilin , Ainspan Herschel A. , Kwark Young , Baks Christian W. , Kindereit Ulrike , Anant Vikas , Lundquist Ted 
Published: December 2020

Abstract
In this paper, we present a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to ultra low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits. The 9 µm-diameter detector is housed in a closed loop cryostat and fiber coupled to an existing Emiscope III tool for collecting spontaneous emission light from the backside of integrated circuits (ICs) down to a world record 0.5 V supply voltage in a few minutes.
Optical Nanoprobe Electrical Microscopy
Authors: Ippolito Stephen , Tenney Michael , Pendyala Sweta , Fischer Larry , Sylvestri John , Miles Darrell , Oldrey Rich , Villalobos Manuel , Dinkel Scott , Kane Terry , Redder Bruce , McGinnis Pat 
Published: December 2020

Abstract
This paper describes novel concepts in equipment and measurement techniques that integrate optical electrical microscopy and scanning probe microscopy (SPM) capabilities into a single tool under the umbrella of optical nanoprobe electrical (ONE) microscopy. Optical imaging ONE microscopy permits non-destructive measurement capability that was lost more than a decade ago, when the early metal levels became electrically inaccessible to microprobers. SPM imaging techniques do not have sensitivity to many types of defects, and nanoprobing all of the transistors in an area pinpointed by optical electrical microscopy is often impractical. Thus, in many cases, ONE microscopy capability will permit analytical success instead of failure.
Electrical Modeling of the Effect of Photoelectric Laser Fault Injection on Bulk CMOS Design
Authors: Hériveaux Laurent , Clédière Jessy , Anceau Stèphanie 
Published: December 2020

Abstract
Fault injection from infrared laser is a common practice among Information Technology Security Evaluation Facility (ITSEF) labs for testing CMOS circuits, and obtained effects are very versatile. However, from our point of view, the details of the phenomenona that occur in the integrated circuit have yet to be investigated. The common hypothesis is that the photoelectric current created during the light stimulation flows through the P-N junctions, and corrupts voltage outputs of the cells. In this paper, we consider the vertical parasitic bipolar junction transistors inherent to CMOS bulk devices. We show that these parasitic transistors contribute to the injected fault at a higher rate than just the P-N junctions of the OFF MOS side. There are two features of such results. First, the space charge region of the N-well / P-substrate junction is wide and will induce a stronger photocurrent. Second, this current will be amplified by the parasitic bipolar transistor and thus lead to more effects. These results are obtained by electrical simulations on a CMOS inverter. The size of the laser spot is taken into account via neighboring cells that are also illuminated. To induce an effect, small spot size needs a very high-power density, which is not always achievable. Increasing the illuminated area to inject more power is then a solution; simulations illustrate this point.
Gate Bridge to Drain Contact Characteristic in Floating Gate Memory
Authors: Chiang Pei Wei , Ling Yu Ting , Chen Bo Chih , Chang Hsiao Tien 
Published: December 2020

Abstract
Gate-to-drain contact short issue in floating gate memory has been studied. Two cases will be discussed, floating-gate to drain contact short, and control-gate to drain contact short, both caused by leakage bridge defect. The abnormal electrical device characteristic combined with modeling gives further insight into the failure mode. Nano-prober measurement results not only provide an evidence of short-contact issue but also measures the current behaviors between drain and gate in floating gate configuration. These results help to predict the defect location and successfully monitor the bridge-failure through electrical analysis.
Backside Sample Preparation Challenges for Fault Localization Analysis of Flip Chip Package
Authors: Cao Lihong , Wallace Donna , Tuttle Lynda , Martin Kirk 
Published: December 2020

Abstract
Mechanical thinning of Si die backside was introduced to support fault isolation for flip chip package in this paper. The backside milling system provides two types of thinning with good die planarity and mirror polishing to yield a high image quality for fault isolation techniques such as laser base thermal emission and photon emission techniques. In this paper, two mechanical thinning techniques were applied by using the 3D die curvature thinning and 2D planar thinning on flip chip Si backside. The impact of process parameters on die planarity and fault isolation were also discussed. The experimental results demonstrate the milling system’s high uniformity across the large die size and provide a very good solution for fault isolation techniques.
Application of Laser Deprocessing Techniques in Physical Failure Analysis
Authors: Yap H.H. , Tan P.K. , Lam J. , Ng T.H. , Low G.R. , He R. , Feng H. , Zhao Y.Z. , Dawood M.K. , Tan H. , Huang Y.M. , Wang D.D. , Mai Z.H. 
Published: December 2020

Abstract
With the scaling of semiconductor devices to nanometer range, ensuring surface uniformity over a large area while performing top down physical delayering has become a greater challenge. In this paper, the application of laser deprocessing technique (LDT) to achieve better surface uniformity as well as for fast deprocessing of sample for defect identification in nanoscale devices are discussed. The proposed laser deprocess technique is a cost-effective and quick way to deprocess sample for defect identification and Transmission Electron Microscopy (TEM) analysis.
Alternative Sample Preparation Technique for Die Level Parallel Lapping Analysis
Authors: Gwee Hoon Ye , Ng Kiong Kay 
Published: December 2020

Abstract
Parallel lapping (often called delayering) is a commonly used process in failure analysis of integrated circuits. However, parallel lapping commonly gives rise to the issue of weak sample preparation method especially on specimen mounting. The traditional specimen mounting technique was done by mounted a single die to polishing fixture using drop of super glue. Using conventional methods, problems such as losing the die during polishing, serious edge rounding are often encountered. Further, loading the whole polishing fixture into Scanning Electron Microscopy machine for SEM imaging or Passive Voltage Contrast (PVC) fault localization can be complicated due to the size of polishing fixture. Therefore, an alternative, relatively fast and simple method to overcome the above mentioned obstacles is proposed.
Visible Light LVP on Ultra-Thinned Substrates
Authors: Beutler Joshua , Clement J. Joseph , Miller Mary A. , Stevens Jeffery , Cole Edward I. 
Published: December 2020

Abstract
Visible light laser voltage probing (LVP) for improved backside optical spatial resolution is demonstrated on ultra-thinned samples. A prototype system for data acquisition, a method to produce ultrathinned SOI samples, and LVP signal, imaging, and waveform acquisition are described on early and advanced SOI technology nodes. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.
Using Energy Dispersive Spectroscopy (EDS) to Determine the Resistance of FIB Jumpers for Circuit Edit
Authors: DiBattista Michael , Senowitz Corey , Faraby Hasan , Bandaru Prabhakar 
Published: December 2020

Abstract
A key capability of focused ion beam (FIB) tools is the ability to deposit conductive materials by introducing organometallic precursors such as tungsten hexacarbonyl [W(CO)6] or (methylcyclopentadienl) trimethyl platinum [C9H17Pt]. The FIB deposited metal is often used in applications such as the modification of integrated circuits (ICs) by creating new electrical connection on the device. The electrical properties of the FIB material are of particular concern to high speed digital and radio frequency (RF) circuit designers because the resistivity of the FIB deposited metal is orders of magnitude higher in value than the near bulk resistivity value of the metals used in IC manufacturing. In this paper, we developed a correlation between the chemical composition of the FIB deposited metal and the electrical resistivity using an effective media theory (EMT) model. Analysis shows that gallium from the ion beam is the dominant contributor to lowering the resistivity of the jumper. The results of this work and model allow us to understand the role the chemical elements play in the electrical resistance of the FIB electrical jumper and to estimate the FIB metal resistance from energy dispersive spectroscopy (EDS) analysis and the geometry.
Auto-Metrology on TEM Images of FinFET
Authors: Biring Sajal 
Published: December 2020

Abstract
The FinFET has been introduced in the last decade to provide better transistor performance as the device size shrinks. The performance of FinFET is highly sensitive to the size and shape of the fin, which needs to be optimized with tighter control. Manual measurement of nano-scale features on TEM images of FinFET is not only a time consuming and tedious task, but also prone to error owing to visual judgment. Here, an auto-metrology approach is presented to extract the measured values with higher precision and accuracy so that the uncertainty in the manual measurement can be minimized. Firstly, a FinFET TEM image is processed through an edge detecting algorithm to reveal the fin profile precisely. Finally, an algorithm is utilized to calculate out the required geometrical data relevant to the FinFET parameters and summarizes them to a table or plots a graph based on the purpose of data interpretation. This auto-metrology approach is expected to be adopted by academia and/or industry for proper data analysis and interpretation with higher precision and efficiency.
Characterization and Simulation of a Body Biased Structure in Triple-Well Technology under Pulsed Photoelectric Laser Stimulation
Authors: Borrel N. , Champeix C. , Lisart M. , Sarafianos A. , Kussener E. , Rahajandraibe W. , Dutertre J-M. 
Published: December 2020

Abstract
This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions inside an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed laser on a triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. It reveals possible bipolar transistor activation at high laser power. This activation threshold revealed its dependence on laser power and wells biasing. Based on the measurements made during our experiments, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.
Introduction to Verification and Test Using a 4-Bit Arithmetic Logic Unit Including a Failure Module in a Xilinx XC9572XL CPLD
Authors: Versen Martin , Hayn Michael 
Published: December 2020

Abstract
In order to educate students in a practical way, a test object for a lab course is created: shorts and opens in an electrical model of physical defects are injected to a net list of a 4-bit arithmetic logic unit and are implemented in a Xilinx CPLD 9572XL. The fails are electrically controllable and observable in verification and electrical hardware test. By using a Test Access Port (TAP), the fails are analyzed in terms of their root cause. The arithmetic logic unit is used as a key component for lab exercises that complement the test part of an Integrated Circuit System Design and Test course in the master program Electrical Engineering and Information Technology at the University of Applied Sciences in Rosenheim. The labs include an introduction to a HILEVEL Griffin III test system, creation of pin and test setup, the import of vector files from verification test benches, control of a scan test engine and analysis of scan test data.
Electrically-Enhanced LADA (EeLADA) Technique
Authors: Goh S.H. , Yeoh B.L. , You G.F. , Hao H. , Sio W.L. , Lam J. , Chua C.M. 
Published: December 2020

Abstract
A modulated laser beam in the form of a continuous pulse train is explored on Laser Assisted Device Alteration (LADA). We term this pulsed-LADA to differentiate from conventional continuous wave (cw)-LADA. It is found that a duty cycle of less than 0.9 at low frequency above 1 kHz is sufficient to experience significant enhancements in laser stimulation. Following this, a new derivative of LADA technique called Electrically-enhanced LADA (EeLADA) is developed. Experimental results to demonstrate its capability in improving diagnostic resolution and potential application to hard failure debug will be presented.
Circuit Tracing on Integrated Circuit Using FIB Passive Voltage Contrast Effect
Authors: Sorkin Alexander , Pawlowicz Chris , Krechmer Alex , Phaneuf Michael W. 
Published: December 2020

Abstract
Competitive circuit analysis of Integrated Circuits (ICs) is one of the most challenging types of analysis. It involves multiple complex IC die de-processing/de-layering steps while keeping precise planarity from metal layer to metal layer. Each step is followed by Scanning Electron Microscope (SEM) imaging together with mosaicking that subsequently passes through an image recognition and Graphic Database System (GDS) conversion process. This conventional procedure is quite time and resource consuming. The current paper discusses and demonstrates a new inventive methodology of circuit tracing on an IC using known FIB Passive Voltage Contrast (PVC) effects [1]. This technique provides significant savings in time and resources.
Fast Feature Based Non-Destructive Fault Isolation in 3D IC Packages Utilizing Virtual Known Good Device
Authors: Lee K.C. , Alton J. , Igarashi M. , Barbeau S. 
Published: December 2020

Abstract
We combine Electro Optical Terahertz Pulse Reflectometry (EOTPR), with full three dimensional device-under-test (DUT) modeling utilizing virtual known good device to quickly and non-destructively isolate faults in advanced 3D IC packages. Computation power required for modeling can quickly become prohibitive with the design complexities of modern IC packages. In this study we adopt a piecemeal modeling approach that bypasses this exponential requirement. A PFA study verifies the accuracy of our model. This shows that feature-based fault analysis with a distance-to-defect accuracy of less than 10 μm can be readily attained through the combination of these techniques.
Failure Mechanism Studies and Elimination of Galvanic Corrosion (Al-Cu Cell) on Microchip Aluminum Bondpads in Copper Process
Authors: Younan Hua , Yixin Chen , Chao Fu , Xiaomin Li 
Published: December 2020

Abstract
In the authors' previous papers, the failure mechanism and elimination solutions of galvanic corrosion (Al-Cu cell) on microchip Al bondpads in the Al process (0.18un and above) have been studied [1-2]. In this paper, the authors will further study the failure mechanism and root cause of galvanic corrosion (Al-Cu cell) on microchip Al bondpads in the Cu process (0.13um and below) with Ta barrier metal. Based on our results, the root cause of galvanic corrosion (Al-Cu cell) in the Al process is only one way and Al-Cu cell is from Al alloy (Al + 0.5%Cu) on Al bondpads. However, in the Cu process it may be from two ways and Al-Cu cell can be from both Al alloy (Al + 0.5%Cu) on Al bondpads and the Cu metal layer below the barrier metal Ta when Ta has weak points or pinhole. As such, the pinhole defects on Al bondpad caused by galvanic corrosion (Al-Cu cell) in the Cu process might be more serious than that in the Al process. In this paper, TEM is used for root cause identification. Based on the TEM results, galvanic corrosion was due to the weak point/pinhole at the Ta barrier metal layer and Al-Cu diffusion.
A More Rapid Approach in Revealing the Physical Status of Polyfuses and Thin Film Fuses in a Multilayer Integrated Circuit
Authors: Lagar Jason H. , Sia Rudolf A. , Cajita Melanie S. 
Published: December 2020

Abstract
This paper aims to discuss the processes involved in establishing a more rapid approach in exposing the polyfuse and thin film fuse using the reactive ion etching, chemical deprocessing and parallel lapping techniques. The results proved that parallel lapping technique in combination with chemical deprocessing and reactive ion etching is a faster approach in exposing the physical status of the fuses.