bluuebunny/crossref_metadata_2025_split huggingface dataset:
Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits
Authors: Shen Cha-Ming , Chang Yen-Long , Wen Lian-Fon , Chuang Tan-Chen , Lin Shi-Chen , Huang Chen-May , Chou Jin-Hong 
Published: December 2020

Abstract
Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.
Measurement of Bit Leakages in a Functional SRAM
Authors: Deng Xiaowei , Loh Wah Kit , Pious Beena , Raval Jayesh , Khan Bashar , Liu Larry , Lowry Taylor , Yoon DB , Houston Theodore W. , McKee Randy , Kasper Abha Singh , Corum Dan 
Published: December 2020

Abstract
A direct bit leakage measurement (DBLM) scheme is proposed and implemented in 8Mb and 32Mb SRAM’s in 45nm and 28nm technologies. It allows, for the first time, direct and nondestructive measurement of various defect induced leakages in each bit in a functional SRAM. It thus enables collection of various defect induced bit leakage data for low-cost and fast failure analysis. It also enables collection of massive bit leakage data for statistical evaluation and location sensitivity assessment.
The SRAM Soft Failure Analysis with SNM & TR Characterization by Nanoprobing in Sub 45nm
Authors: Hong Jakyung , Cho S.J. , Han Y.W. , Choi H.S. , Kim T.E. , Son S.J. , Kim H.S. , Kwon S.D. , Oh Y.S. 
Published: December 2020

Abstract
This paper presents the process of measuring static noise margin (SNM), write noise margin (WNM) with 6 pin nanoprober, and characterization and analysis of SRAM cell stability through case studies of 45nm devices SRAM soft failures. It highlights that the local mismatch in the bit cell caused by slight variations in the transistor characteristics, such as Vth shift and Idsat, off variation, also can easily induce a soft failure. The analysis of the SNM TR characteristic is successfully demonstrated through the case study of 45nm SRAM devices. The chapter explains SNM measurement in the metal layer and transistor measurements in the CA layer. Measuring the SNM TR's characteristics is an important methodology in understanding the stability of each bit cell and failure mechanism depending on voltage, defects, and other factors. The next generation of nanoprobing analysis can be expanded.
A Versatile Design of Solid Immersion Lenses in Bulk Silicon Using Focused Ion Beam Techniques
Authors: Scholz P. , Kerst U. , Boit C. , Tsao C.-C. , Lundquist T. 
Published: December 2020

Abstract
The topic of this work is the sequential use of Solid Immersion Lenses (SILs), created in bulk silicon in less than 20 minutes of processing time, using a focused ion beam and a bitmap milling process. Fibbed SILs can be removed by polishing, and the silicon back surface resumes a perfect planar shape for further backside analysis or the creation of more SILs. The influence of the progressively thinner sample thickness on the magnification of the SIL was analyzed. As fibbed SILs in this work are about 1.4 µm thick and have an additional magnification of 2.4, a second process after removal has been found to decrease magnification not more than 20%. The presence of interference rings in the SIL image could be almost completely removed by anti-reflective coating. Photon emission microscopy, performed using fibbed SILs, allowed to clearly distinguish between sources that were separated by 240 nm wide structures.
Localized Epoxy Layer Formation on Surface Defect Using a Micro-Brush in a Plucking System
Authors: Lin Kun-Lin , Luo Jian-Shing , Lee Hsiu-Ting , Russell Jeremy D. 
Published: December 2020

Abstract
This paper provides details of a novel method developed to cover a tiny epoxy layer as an intermediate buffer on the site-specific surface defect using a micro-bush on the tip of a glass needle in a plucking system without sample surface damage and localization problems. It describes the method and some real cases. The microstructures are investigated using an FEI Tecnai TF20 field emission gun transmission electron microscopy equipped with a high angle annular dark field detector, an energy dispersive X-ray spectroscopy, and Gatan image filter systems. The paper explains the micro-brushes and buffer layer preparation though figures and illustrations.
Evaluation Trial of MEMs Devices by LSI Process Diagnostics
Authors: Shimizu Wataru , Kubota Hidehisa , Murahara Daisuke , Nakamura Noriko , Kamiyama Hirokazu , Oda Tamiko , Yabe Kazuhiro 
Published: December 2020

Abstract
The goal of this paper is to construct a process diagnostic system of the MEMS device based on this "Large Scale Integrated (LSI) Diagnostic system" and then to perform a structural evaluation of the devices based upon the data. The paper explains the methods of analysis for the assembly process and the wafer process. The evaluation of the wafer process indicated that changes were required for MEMS devices vs. conventional LSI diagnosis. It was confirmed that "a peculiar inspection point to MEMS", "Sample making technology", and "Judgment criteria of the defect" were necessary. It is also necessary to do preliminary studies of each MEMS device and to restructure the inspection menu corresponding to the structure based on the inspection results.
UV Emission Microscopy Development for High Band Gap Components
Authors: Bouya M. , Carisetti D. , Clement J.C. , Malbert N. , Labat N. , Perdu P. 
Published: December 2020

Abstract
HEMT (High Electron Mobility Transistor) are playing a key role for power and RF low noise applications. As well as the improvement of the MMIC performances, the localization of the defects linked with hot electron and the failure analysis of these devices are very challenging. To face these challenges, we have developed a complete approach, without degrading the component, based on front side failure analysis by UV electroluminescence or UV light emission. Its feasibility and efficiency have been demonstrated through two case studies. So, a specific UV microscopy technique has been developed and is presented in this paper.
Ultimate Resolution for Current Localization by Means of Magnetic Techniques
Authors: Infante Fulvio , Gabarrot Mathieu , Perdu Philippe , Lewis Dean 
Published: December 2020

Abstract
Defect localization is a very important step in the process of failure analysis for Integrated Circuits. A very important technique, allowing the localization of the defects with a certain degree of precision, is Magnetic Current Imaging. However, this technique has strict limitations related to the working distance and the maximum current magnitude detectable. We overcame these limitations by using a simulation approach, allowing us to sensibly increase the technique resolution and to map currents which are much weaker. This is done by comparing the measurement of the Magnetic Induction Field to a set of simulations of defect assumptions.
Challenges Facing the Detection of Leakage Current in Integrated Circuit (IC) Devices
Authors: Toh S.L. , Hendarto E. , Sudijono J. , Tan P.K. , Goh Y.W. , Lin H.B. , Deng Q. , Tan H. , Zhu L. , Wang Q.F. , Li H.L. , He R. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
Electrical characterizations were needed to identify the root cause of leakage issues in IC devices. The methodology required was dependent on the failure mode obtained during testing and global or nano-scale isolations had to be implemented accordingly. As such, challenges encountered in sample preparation or due to detection methodology choices for every isolation technique have to be addressed in order to localize the defective sites.
The Helium Ion Microscope for High Resolution Imaging, Materials Analysis, Circuit Edit and FA Applications
Authors: Thompson William B. , Notte John , Scipioni Larry , Ananth Mohan , Stern Lewis , Sanford Colin , Ogawa Shinichi 
Published: December 2020

Abstract
Currently, the helium ion microscope (HIM) can be operated in three imaging modes; ion induced secondary electron (SE) mode, Rutherford backscatter imaging (RBI) mode, and scanning transmission ion imaging (STIM) mode. This paper will provide an overview of microscope’s ion source, its ion optics, the system architecture, the fundamentals of these three imaging modes and many FA related examples. Recently integrated with the microscope are a Rutherford Backscatter (RBS) detector for materials analysis and a gas injection system (GIS) for material modification. We will describe this new hardware and suggest how these additions could also contribute to the helium ion microscope being an important failure analysis tool.
Characterization and Failure Analysis of 3D Integrated Semiconductor Devices—Novel Tools for Fault Isolation, Target Preparation and High Resolution Material Analysis
Authors: Altmann Frank , Petzold Matthias , Schmidt Christian , Salzer Roland , Cassidy Cathal , Tesch Paul , Smith Noel 
Published: December 2020

Abstract
In this paper we will introduce novel methodical approaches for material and failure analysis of 3D integrated devices. The potential and advantages of the new concepts and tools will be demonstrated for flip-chip-like interconnects but in addition, for the first time, for Through Silicon Vias (TSV). The employed techniques combine non-destructive fault localization with efficient and accurate target preparation to get access for following microstructure diagnostics, forming a subsequent failure analysis workflow. The concept presented here involves the application of improved Lock-In Thermography (LIT), and three different innovative concepts of high rate Focused Ion Beam (FIB) techniques.
Design Diagnosis with E-Beam Probing to Improve Reliability Issue Due to Competitive Signal Error
Authors: Chuang T.C. , Shen C.M. , Wen L.F. , Lin S.C. , Huang C.M. , Lee Jon C. 
Published: December 2020

Abstract
Tiny circuit design reliability issue related to competitive signal was investigated in a sense amplifier (SA) circuitry of SRAM by E-Beam probing technique in this paper. The irregular output signals then traced back to former stage circuit and identified associated waveforms. With such design concept and technique tracing, the invisible and cunning circuit mismatch reliability issue could be revealed successfully.
Leveraging the Power Grid for Localizing Trojans and Defects
Authors: Plusquellic Jim , Acharyya Dhruva 
Published: December 2020

Abstract
The finite, non-zero resistance of the metal wires that define the power grid of chips require the insertion of multiple ports between the grid and the external power supply in order to meet voltage stability requirements across the 2-D plane of the chip. The ports connect to the power grid along its edges for peripheral pad configurations, while, for C4 or array pad configurations, the ports are distributed across the 2-D surface of the chip. In either case, the availability of multiple power ports can be leveraged for detecting and localizing defects and/or Trojan circuits. A localization technique is investigated in this paper that analyzes anomalies introduced by defects and/or Trojans in the measured IDDQs from these ports. The localization accuracy of the technique can be improved significantly through the use of calibration and additional information collected from simulation experiments. The method and model are validated using data collected from a set of chips fabricated in an IBM 65 nm SOI process.1
Success! &gt; 90% Yield for 65nm/40nm Full-Thickness Backside Circuit Edit
Authors: Niles David W. , Kee Ronald W. 
Published: December 2020

Abstract
The authors present a detailed analysis of a full-thickness backside trenching and contact level circuit editing methodology used to achieve a success yield of greater than 90%. The methodology involves both full-thickness backside trenching and contact level circuit modifications on flip-chip parts produced with 90nm, 65nm, and 40nm foundry processes and mounted on laminated package technology. Having successfully edited &gt;150 parts with this methodology, the authors prove that full-thickness trenching is a viable alternative to a traditional die-thinning process, and that circuit edits at the contact layer, to avoid milling into the copper metal layers, greatly reduces risk and uncertainty.
Combining Time Resolved Emission and Analog Simulation for Fault Localization
Authors: Burmer Christian , Hopsch Fabian , Vermeiren Wolfgang 
Published: December 2020

Abstract
In this paper, we describe a fault localization strategy for scan designs based on Time Resolved Photon Emission (TRE) and analog simulation. After characterizing the defect’s electrical footprint using TRE, analog fault simulation is applied. A user - friendly software package with an easy to use interface to scan diagnosis, layout tool and simulator was created.
Identification of a Non-LDD Induced Vt Shift Failure Mechanism via Nano-Probe Characterization
Authors: Mulder Randal , Tsang Yuk 
Published: December 2020

Abstract
The relationship between blocked or depleted lightly doped drain (LDD) implants and threshold voltage (Vt) shifts resulting in suppressed drive current has been thoroughly investigated and characterized through nano-probe analysis. In this paper, a review for a technique for characterizing Vt shift failures is presented as well as a brief review of the LDD Vt shift failure. A case study is also presented showing the characterization, identification, and the physical analysis results for the symmetrical Vt shift failure mechanism. The method presented allows the analyst to differentiate between a Vt shift failure caused by a depleted LDD implant mechanism and a failure caused by dopant depletion in the gate poly-silicon. The results demonstrate that there are now at least two failure mechanisms that can be responsible for threshold voltage failures and it is likely that there are more that have yet to be discovered.
Frequency Sensitive Soft Fails in SRAM Arrays
Authors: Pendyala Sweta , Kane Terence , Tenney Michael , Oldrey Richard , Villalobos Manuel , Sylvestri John 
Published: December 2020

Abstract
Root cause analysis of frequency sensitive “soft” failures in SRAM arrays pose unusual challenges to the failure analyst. Conventional atomic force probe (AFP) DC measurements cannot reliably identify the failure source. The employment of tester based schmoo screening have been shown to correlate with AFP AC quantitative capacitance measurements for the first time. The technique of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for localization has been previously described [1,2,3]. By exploiting the dC/dV component of the NCVS signal shown in Figure 1 and integrating this output, a quantitative capacitance versus voltage measurement can be demonstrated. This quantitative capacitance measurement identified a frequency sensitve horizontal pair failure (HPF) in the SRAM array. Subsequent process vintage analysis identified the source and eliminated these frequency sensitive HPF characterisics. Given the sensitive nature of these fails, conventional physical analysis methods of TEM EELS, and cross section scanning capacitance analysis were not successful in finding the root cause. This underlies a paradigm shift in failure analysis. Electrical measurements may be the only means to identify a process problem and follow-up process vintage analysis is required to solution the root cause.
The Challenges of Backside Focused Ion Beam (FIB) Editing in the Presence of Deep Trench Decoupling Capacitors
Authors: Herschbein Steven B. , Scrudato Carmelo F. , Worth George K. , Hermann Edward S. 
Published: December 2020

Abstract
For most advanced semiconductor products, Focused Ion Beam (FIB) circuit modification and node access through the backside of the chip is the only viable approach. The high density of interconnect wiring and the presence of C4 solder bumping for chip to module attachment has made complex edits virtually impossible with long standing conventional frontside techniques. Unfortunately, the presence of buried circuit elements on the very latest designs greatly complicates the backside editing formula. The introduction of deep trench capacitors as a distributed circuit element in logic designs has had a profound impact on the established methods of backside FIB chip editing. In many cases wide area preparatory trenching down to the underside of circuitry cannot be done without damage to structures that penetrate the silicon adjacent to active transistors by as much as 10 microns. The decision whether to remove these devices or attempt to work around them requires an analysis of the impact on circuit performance and an assessment of the working space (control of anisotropy of etch, aspect ratio issues, etc.) available for executing the edit. IBM is in the process of developing a new set of procedures for performing FIB backside edits on circuits that incorporate these buried structures.
Circuit Edit and Optical Probe Development and Validation for Next Generation Process Nodes
Authors: Giacobbe John A. , Pardy Patrick , Peterson Charles A. , Shykind David , Zickel Scot E. 
Published: December 2020

Abstract
Circuit Edit and Optical Probe technologies must scale with Intel’s 2 year process cycle and the tick-tock design model. Geometry shrinking combined with revolutionary and evolutionary process changes such-as high-k and metal gate, lower-k interlayer dielectrics, and non-planar devices, make this very challenging. To develop new tools, analytical processes, and validate if the current tool suite can analyze next generation process node and architectures, a special debug block has been designed into Intel’s process test vehicle. In this paper the authors first provide an overview of the Debug Block, we then provide an overview of the LADA, IREM, LVP, TRE, and FIB tools and their corresponding technical challenges for Intel’s next generation microprocessors. Finally we discuss the circuits, layout, and 32nm results.
Improving Wire Sweep Performance by Measuring Degree of Cure of Epoxy Mold Compounds
Authors: Dal Sheila Liza B. 
Published: December 2020

Abstract
The choice of epoxy mold compound (EMC) for an electronic package is based mostly on how much protection it provides to the active components in the package. But the choice is not a straightforward process. Rather it is mostly trial and error using different assembly parameters to find the most robust material while assembly defects are monitored. One such defect associated to EMC processing is wire sweep, and many studies have shown that it is mainly caused by viscosity changes in the EMC. In this study, samples of EMC in various stages of shelf life and staging times were analyzed for degree of cure using a method called differential scanning calorimetry (DSC). Samples are then processed at assembly for wire sweep measurement. It was found out that degree of cure increases with staging time at different rates for each shelf life. It was also found out that wire sweep did not only increase with degree of cure but it was also found to be predictable with respect to the latter. Using this information, the age and staging limit for each material was identified that would not cause wire sweep issues.
Whisker Formation in Copper Electroplating
Authors: Han Theresa , Cho Eunin , Heo Jinwoo , Lee Seoung Jae 
Published: December 2020

Abstract
In the manufacture of Printed Wiring Boards (PWB), unwelcome structures, such as nodules and whiskers can be formed during copper electroplating with copper sulfate. Copper (Cu) whiskers with lengths of up to a few hundred micrometers can lead to electrical shorts between layers or patterns. In this paper, we document factors that can affect the growth of Cu whiskers; decomposition of additives in the Cu electroplating solution, surface stress, acidic cleaner, and the ingredients of a dry film. Contaminants from outside of the electroplating bath and the ingredients of the dry film were shown as key components in the formation of Cu whiskers.
Failure Analysis on Power Trench MOSFET Devices with Copper Wire Bonds
Authors: Wu Huixian , Chiang Arthur , Le David , Pratchayakun Win 
Published: December 2020

Abstract
With gold prices steadily going up in recent years, copper wire has gained popularity as a means to reduce cost of manufacturing microelectronic components. Performance tradeoff aside, there is an urgent need to thoroughly study the new technology to allay any fear of reliability compromise. Evaluation and optimization of copper wire bonding process is critical. In this paper, novel failure analysis and analytical techniques are applied to the evaluation of copper wire bonding process. Several FA/analytical techniques and FA procedures will be discussed in detail, including novel laser/chemical/plasma decapsulation, FIB, wet chemical etching, reactive ion etching (RIE), cross-section, CSAM, SEM, EDS, and a combination of these techniques. Two case studies will be given to demonstrate the use of these techniques in copper wire bonded devices.
New Front Side Access Approach for Low-k Dielectric/Cu Technologies in Plastic Package
Authors: Aubert Amandine , de Morais Lionel Dantas , Pétremont Stéphanie , Labat Nathalie , Frémont Hélène 
Published: December 2020

Abstract
This paper presents a new sample preparation process for front side access for die with organic dielectric layers that are encapsulated in plastic packages. The limitation of the standard failure analysis flow is firstly described, showing the damage caused by wet etching. Then, the decapsulation method combining laser ablation and plasma etching is presented. It is completed by the process optimization. The final process makes it possible to perform failure analysis on low-k/Cu technologies in plastic package either by the front side or by the backside of the die.
TEM Sample Preparation by Single-Sided Low-Energy Ion Beam Etching
Authors: Nan Liew Kaeng , Lung Lee Meng 
Published: December 2020

Abstract
Conventional FIB ex-situ lift-out is the most common technique for TEM sample preparation. However, the scaling of semiconductor device structures poses great challenge to the method since the critical dimension of device becomes smaller than normal TEM sample thickness. In this paper, a technique combining 30 keV FIB milling and 3 keV ion beam etching is introduced to prepare the TEM specimen. It can be used by existing FIBs that are not equipped with low-energy ion beam. By this method, the overlapping pattern can be eliminated while maintaining good image quality.
Fast Diagnosis and Failure Mechanism of Phosphorous Contamination in Arsenic-Implanted Silicon
Authors: Zhu Lei , Teo H. W. , Ong K. , Huang Y.H. , Koh R. , Chew P.Y. , Hua Y.N. 
Published: December 2020

Abstract
A particular failure analysis case where phosphorous contamination occurred in arsenic-implanted Si is presented. Time-of-Flight secondary ion mass spectroscopy (TOF-SIMS) can be used for fast diagnosis of this contamination which shows 300% surface density change relative to the baseline. It is found that the cause of the phosphorous contamination is due to a combination of implanter chamber re-deposit cross contamination and rapid thermal annealing (RTA) process induced drive-in effect.