(Invited) Strained Germanium Nanowire MOSFET with Low-Parasitic Resistance Metal Source/Drain
Authors: Ikeda Keiji , Kamimuta Yuuichi , Moriyama Yoshihiko , Ono Mizuki , Oda Minoru , Irisawa Toshifumi , Tezuka Tsutomu 
Published: February 2020

Introduction

High mobility channel materials are extensively investigated to replace strained-Si in MOSFET devices to reduce power consumption by lowering supply voltages, V
dd, without degrading circuit performance. Among the various high mobility channel materials, strained-Ge[1-4] is recognized as the most promising option for p-channel FETs due to its significantly high hole-mobility and compatibility with Si-CMOS process. This paper presents metal S/D nanowire pFETs having a high-mobility strained Ge channel formed by doping-free processes for channels and S/D. The large compressive strain as high as -3.9% resulted in a record high hole mobility (μ
eff = 1992 cm2/Vs @ N
s = 1.7x1012
cm-2) and a low contact resistivity (ρ
c ~ 3.8x10-8
Ω cm2).

Device fabrication

Uniaxially strained-Ge nanowire channel was formed by the two-step Ge condensation technique, which induced uniaxial stress along the channel direction. As a gate insulator, GeOx interlayer and 3.2 nm- Al2O3 were grown by using MMT-plasma[4,5] and ALD, respectively. NiGe-metal S/D structures were formed by SALICIDE-like process on the unintentionally doped Ge nanowire. Detailed device fabrication process was shown in [3,4]. Figure 1(a) shows a XTEM of the narrowest channel with a wire width (W
wire) of 15 nm. The Relationship between the W
wire and strain applied to the channel was measured by a Raman spectroscopy. The dependence of strain along the channel direction ε
xx on W
wire is shown in Fig. 1(b). Extremely high (over -3.9%) strain, which is almost identical with the misfit strain between Ge and Si, was evaluated for sub W
wire=40 nm devices.

Device characterization

Hole mobility was extracted by a split CV method for long-channel and multi-wire devices. Figure 2(a) shows hole-mobility of the fabricated multi-wire MOSFETs. The W
wire = 40nm device, which has 95% Ge channel, showed a peak hole mobility of 1922 cm2/Vs at N
s = 1.7x1012cm-2, which exceeds that of -3.8% strained-Ge nanowire MOSFET with Al2O3 gate stack[3]. Moreover, the obtained mobility at N
s = 5x1012cm-2 is corresponding to 5.8 times of the counterpart of a state-of-the-art strained-Si pMOSFETs[1]. Ion / Ioff
~ 105 has also been attained for the strained-Ge nanowire pMOSFET with a gate length (Lg
) of 40 nm (Fig. 2(b)).
A metal S/D MOSFET is an attractive candidate because of its low extension sheet resistance properties without a heavy doping in extension regions. However, parasitic resistance (R
para) which is dominated by contact resistance (R
c) between the extension metal and the inversion layer in this device, have been still an issue because of the decreasing contact area. Here, we demonstrate low R
c characteristic due to low Schottky barrier height (SBH) for NiGe/ strained-Ge interface. The W
wire dependence of parasitic resistance (R
SD) were evaluated as shown in Fig. 3. Reduced R
SD as low as 490 Ωμm for W
wire = 54 nm device is achieved by using undoped Ge nanowire formed by two-step Ge condensation. The specific contact resistivity, ρ
c of NiGe / strained-Ge interface was estimated by using previously proposed model[3]. Extremely low ρ
c, that is as low as ~ 3.8x10-8
Ω cm2 has been achieved in spite of doping-free Schottky contact presumably due to the strong Fermi-level pinning to the valence band edge of the strained-Ge and reduction of SBH at Ni(Si)Ge/(Si)Ge interface by rising valence subband top energy for higher Ge concentration and strain.

Conclusion

Record high hole mobility (μ
eff = 1922 cm2/Vs) and extremely low S/D contact resistivity (ρ
c ~ 3.8x10-8
Ω cm2) were achieved for the highly strained-Ge nanowire pMOSFET. These results indicate that strained-Ge channels have a potential to serve as pFET channel of ultimately-scaled future CMOS.

References

[1] R. Pillarisetty et al., IEDM p.150 (2010). [2] W. Chern et al., IEDM p.387 (2012). [3] K. Ikeda et al., VLSI Symp. p.165 (2012). [4] K. Ikeda et al., VLSI Symp. p.T31 (2013). [5] Y. Kamimuta et al., ISTDM. p.34(2012).

Acknowledgements

This work was granted by JSPS through FIRST Program initiated by the Council for Science and Technology Policy (CSTP).