bluuebunny/crossref_metadata_2025_split huggingface dataset:
TDR Analysis on Short Transmission Lines
Authors: Konkol Nicholas 
Published: December 2020

Abstract
Transmission line analysis is done in electrical failure analysis labs in order to find root causes that result in system level failures. After a fault is narrowed to a particular signal in a system, a Time Domain Reflectometer (TDR) can be used to analyze the physical transmission line associated with the signal. The transmission lines on smartphones often have inaccessible signal vias, few or no ground vias, probe points that are difficult to see, and short transmission lines. One solution that can alleviate these problems is to design a TDR Accessory Card. This paper discusses the processes involved in testing long and short transmission lines, providing the comparison between the expected and actual TDR measurement and the advantages and disadvantages of TDR, explaining four main points for using a TDR Accessory Card and two reasons for not using the TDR Accessory Card.
Productive Polishing TEM Sample Preparation Methodology Development
Authors: Yu Huisheng , Duan Shuqing , Li Ming , Zhang Qihua , Chien Wei-Ting Kary 
Published: December 2020

Abstract
In this paper, three productive polishing transmission electron microscopy (TEM) sample preparation methods are reported. The methods are studied to improve the efficiency and expand the application fields. Method 1 and 2 address expanding conventional polishing method application on same or similar pattern samples. Method 1 used a laser mark to identify one of the sample; and method 2 used a Pt coated glass inserted between samples or a direct deposition of Pt on one of the samples. Method 3 was developed facilitate stacking three or more samples into a single, batch process block and improved the efficiency greatly.
Determination of the Source of an Electrical Overstress Event to a Digital Variable Gain Amplifier Module
Authors: Htun Thiri , Brockett Steve 
Published: December 2020

Abstract
This paper presents a systematic approach of failure analysis to determine the source of electrical overstress condition to a digital variable gain amplifier (DVGA) module where the failure was due to attenuation accuracy. Having consideration of the physical evidence on the failed devices and the root cause of the failure gives an insight of how the mechanical damage caused an electrical overstress exposure to the devices. The paper provides information on destructive analysis and non-destructive analysis conducted for determining the root cause of the failure of the DVGA module. Analysis revealed that devices failed due to an electrical overstress exposure through mechanical damage to the passivation of the metal-2 lines. The mechanical damage occurred during die-sort testing due to misalignment of the probes which delivered unintended electrical stress to the devices.
Failure Analysis Induced by Memory Cell Plate Noise in High-Density DRAMs
Authors: Jung Mingu , Lee Myungjae , Kwon Hyungshin , Hong Heeil , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung 
Published: December 2020

Abstract
As the DRAM structure is miniaturized, the cell capacitance is reduced and resistance is increased. Because of this change, the DRAM operation is more sensitive than previous generations to changes of the device elements. The device elements consist of cell capacitance, Bit Line (BL) capacitance, cell node resistance, supply-voltage and the surround noise. The elements were changed by decreasing the cell node dimensions. The write time (tWR) is degraded by changing the elements. In particular, the noise is very variable element on change of surrounding cell phase which is data1 or data 0. In this paper, we show that one of the most dominant contributors to failure is the plate noise and explain how plate voltage level affects tWR delay. The effect of the plate voltage modulation can be correlated with ∆Vbl which is bit line level difference to read out the data. We define this phenomenon as the plate dc noise effect and propose a model in miniaturized DRAM.
Intra-Device Defect Localization through EBIC/EBAC Combined with Electrical Nanoprobing for FinFET Devices Composed of Multiple Sub-Elements
Authors: Dahanayaka Daminda H. , Bader Daniel A. , Prevost Dennis P. , Coster Michael T. , Mccullen Erik F. , Masters Mark E. , Stevens Keith C. 
Published: December 2020

Abstract
Physical failure analysis of nanoelectronic devices is typically performed using plan view or cross-sectional TEM, SEM or SPM techniques. While plan view SPM and SEM analyses are limited by the depth sensitivity of the technique, cross-sectional analysis requires at least approximate localization of the fail location within the device for effective sample preparation. Multi-finger wide 2D planar devices and multi-FIN 3D devices are structures which require an additional step in pinpointing the fail area within the device. This paper describes successful use of EBIC/EBAC techniques to localize the fail location within such devices in both the 22 nm and 14 nm technology nodes.
MEMS Failure Analysis In Wafer Fabrication
Authors: Ng Hui Peng , Teo Angela , Ang Ghim Boon , Quah Alfred , Dayanand N. , Xu Naiyun , Chen Chang Qing , Mai Zhi Hong , Lam Jeffrey 
Published: December 2020

Abstract
This paper discussed on how the importance of failure analysis to identify the root cause and mechanism that resulted in the MEMS failure. The defect seen was either directly on the MEMS caps or the CMOS integrated chip in wafer fabrication. Two case studies were highlighted in the discussion to demonstrate how the FA procedures that the analysts had adopted in order to narrow down to the defect site successfully on MEMS cap as well as on CMOS chip on MEMS package units. Besides the use of electrical fault isolation tool/technique such as TIVA for defect localization, a new physical deprocessing approach based on the cutting method was performed on the MEMS package unit in order to separate the MEMS from the Si Cap. This approach would definitely help to prevent the introduction of particles and artifacts during the PFA that could mislead the FA analyst into wrong data interpretation. Other FA tool such as SEM inspection to observe the physical defect and Auger analysis to identify the elements in the defect during the course of analysis were also documented in this paper.
Conductive Thin Film Fail Detection in 20 nm and 14 nm Technologies
Authors: Kodali S. , Zhang C. , Schaeffer T. , Arva S. , Nedeau D. , Yu J. , Ma Y. , Vijay T. , Kalaiazhagan K. , Oh C.K. , Beaudoin F. 
Published: December 2020

Abstract
Conductive thin film residues often referred to as puddles could be challenging fails to detect. A large extant film with no distinct boundaries would make the task more challenging for a comparison between good and bad region. Advanced node 20nm and 14nm technologies mandate use of several conductive thin films in the front end of line processes, and hence a potential for high defects during initial product development stage. Use of other electrical characterization techniques in combination with scanning electron microscopy inspection will be a very powerful tool to detect the root cause affirmatively. Cross-sectional images are necessary to understand the root cause of the fails for corrective actions. This work uses three cases of power supply shorts as a platform to demonstrate the idea, demonstrating a few situations where traditional techniques might reach its limits while the authors depend on additional characterization tools to confidently detect and confirm fails.
Failure Analysis of Single-Bit Charge Loss after Stress and Studies on Silicon Dopant Profile
Authors: Gong Rong-Wei , Chang Hsiao-Tien , Chan Hui-Wen , Lee Lian-Feng , Shih Chih-Ching , Kuo Albert , Lin Ting-Chang , Wang Tse-Jen 
Published: December 2020

Abstract
The single-bit charge loss of flash memory after stress has been investigated using TEM with selective chemical etching and TCAD simulation for the effect of silicon dopant profile and electrical failure analysis technique. However, the abnormal dopant profile on the drain-side of the failing bit observed in the TEM does not match the leakage behavior from the simulation. A qualitative model for the degradation process is proposed based on the electrical failure analysis results, it is suggested that the hole generated by avalanche breakdown captured by oxide traps on the drain-side during the stress is the source of leakage current.
A Case Study of Failure Analysis and Root Cause Identification on ESD-Induced Breakdown
Authors: Liu Hongmin , Li Zhe , Weng Zheng 
Published: December 2020

Abstract
This paper describes the detailed process of failure analysis (FA) of a 16-bit transceiver. The FA included six steps: electronic parametric testing, visual inspection, optical beam induced resistance change to isolate failure location, SEM inspection of the breakdown, electro static discharge (ESD) root identification, and ESD test to prove the identification. FA showed that the short circuit was the result of a breakdown between the I/O resistor and the substrate, and the cause of the breakdown was most likely an ESD event. In a series of electrical over stress/ESD tests performed, the field failure signature was replicated with a MM ESD model, thereby identifying the root cause of the ESD failure.
Failure Analysis Process Improvement Using Barcode Equipment Management System
Authors: Sabate Andrew C. , De La Cruz Em Julius , Rieck Christopher 
Published: December 2020

Abstract
Failure Analysis (FA) process improvement is vital to cope with increasing demand on FA cycle time reduction from end customer. Real time failure analysis update, equipment usage data collection, and equipment security enhancement plays significant factor on cycle time reduction. This paper aims to discuss the barcode equipment management system in aiding FA Lab for process improvement.
Accelerating Technology Development and Yield Ramp on First Silicon Utilizing a Wafer-Level Dynamic EFA System
Authors: Chen Li-Qing , Sun Ming-Sheng , Chao Jui-Hao , Ng Soon Fatt , Izak Kapilevich , Tsao Chun-Cheng 
Published: December 2020

Abstract
This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.
Power Distribution Analysis of an Integrated Circuit Using FIB Passive Voltage Contrast
Authors: Sorkin Alexander , Pawlowicz Chris , Krechmer Alex 
Published: December 2020

Abstract
Competitive circuit analysis of an Integrated Circuit (IC) is one of the most challenging types of analysis. It involves various high technology steps of IC die de-processing/de-layering; keeping precise planarity from metal layer to metal layer, Scanning Electron Microscope (SEM) imaging and images mosaicking, image recognition and Graphic Database System (GDS) segmentation processes and finally logic and architecture level analysis. One of the most complicated analysis is Power Management and Power Distribution [2] on the entire IC die when no datasheet or other IC’s information is available. Power Distribution analysis requires the highest level of architecture analysis, not feasible by conventional Reverse Engineering (RE) methods or extremely costly. The current paper discusses and demonstrates a new inventive methodology of Power Distribution analysis using known FIB Passive Voltage Contrast (PVC) effects [1]. This patented technique provides significant time and resources saving.
Effects of Barrier Metal and Etch Profile on Galvanic Corrosion of Al Pad
Authors: Youn Sang Bae , Choi Pil Mook , Seong Suk Hyun , Cho Don Koo 
Published: December 2020

Abstract
Recently a phenomenon has been found that shows different corrosion rates over Al bond pad regardless of different densities of Cl, F components on Al bond pads in different products. According to the results of analysis, the products showed different corrosion rates for different etch conditions of the bond pad opening. For the cause analysis, we conducted a cross-sectional profile comparison between two products with Al bond pads. Based on the result of comparison, we discovered that the side wall profile of the Al bond pad is affected by the etch conditions of the bond pad opening. In some severe cases, it was observed that a small void was formed between the side wall and Al bond pad. Under moist conditions, this void provided moisture between Al bond pad and TiN barrier metal that the electricity contacted. Through this study, we could conclude that the moisture in the void between Al bond pad and TiN barrier metal may create a galvanic corrosive condition.
A Detailed Analysis Scheme to Interpret Multiple Photon Emissions Micrograph for Improved Diagnostic Resolution on Open Defects
Authors: Goh S.H. , Manlangit Edmund C , Susanto Edy , Yeoh B.L. , Hao Hu , Tan Alan , Ma Hnin Hnin W , Lin Zhao , Chan Y.H. , Lam Jeffrey 
Published: December 2020

Abstract
Photon Emission Microscopy is the most widely used mainstream defect isolation technique in failure analysis labs. It is easy to perform and has a fast turnaround time for results. However, interpreting a photon emission micrograph to postulate the suspected defect site accurately is challenging when there are multiple abnormal hotspots and driving nets involved. This is commonly encountered in dynamic emission micrographs that are caused by open defects in digital logic. This paper presents a methodology incorporating layout-aware trace analysis and post schematic extraction with test bench analysis to enhance the diagnostic resolution on the suspected defective net(s).
Fault Isolation of Leakage for a Device with Nonuniform Epoxy Encapsulation
Authors: Lin Ke-Ying , Ssang Hsiu-Li , Huang Shou-Ming 
Published: December 2020

Abstract
In this article, we demonstrate using lock-in thermography (LIT) to perform fault isolation of leakage on a board-mounted device with rough, heterogeneous epoxy encapsulation. It is interesting to observe LIT spot shifting either on the failing unit’s reference pin or the failed pin using a different lock-in frequency. The protection diode of the reference pin is triggered by LIT and the electrical behavior should not be affected by varying lock-in frequencies (0.1 Hz to 25 Hz). The reason for the shifting hot spot is a non-uniform morphology in the epoxy encapsulation, which consists of different thicknesses and voids. This complicated epoxy encapsulation morphology results in a non-uniform heat conduction pathway when a different lock-in frequency is used. In this study, a LIT hot spot will stabilize and remain in a fixed position when the lock-in frequency is increased to greater than 5 Hz and the phase shift is directly proportional to the square-root of the lock-in frequency. This indicates that the heat conduction becomes stable under such a condition, and the phase shift value can still be used for relative depth localization. By overlaying LIT and X-ray imaging, an accurate position of the fault location in the X-Y plane can be detected. A quick and non-destructive 3D fault isolation method for complicated system level failure can be achieved in this way.
Overcoming the Challenges on Electrically Damaged Devices
Authors: Norico Allan , Sabate Andrew 
Published: December 2020

Abstract
Finding the real root cause of electrically damaged devices is often challenging where it can mask out the real failure mechanism. The electrical damages might (might probably, one doubtful word is enough) be a consequence of the real failure mechanism. This paper aims to present cases and techniques to overcome the challenges of electrically damaged devices in identifying the real failure mechanism.
Zynq SOC Low-Voltage and Temperature-Dependent L2 Cache Failure Diagnosis and Defect Localization Case Study
Authors: Bai Haonan , Lee Lan Yin , Jing Yang , Salinas Peter Floyd , Chua Kok Keng 
Published: December 2020

Abstract
Failure analysis and defect localization on 28nm All Programmable Zynq System-on-Chip (SoC) device is extremely challenging. While conventional FPGA, which only consists of the Programmable Logic, has greater ease and flexibility in pattern generation during fault isolation, the all programmable SoC device integrates a dual ARM Cortex-A9 cores with Programmable Logic (PL) in a single chip. The cache data access in-between processor and PL is more complex and test methodology has lesser degree of control on cache data flow and stack sequence. This paper introduced an advanced fault isolation test methodology combining Software Development Kit (SDK) with scan based diagnostic test for cache failures. It successfully pinpoint to failure locations with physical defects found. As conventional physical failure analysis approaches using SEM based passive voltage contrast could not observe any abnormalities, current imaging and nano-probing measurement using AFP played critical roles in detecting nano-ampere leakages prior subsequent TEM analysis. The findings were then feedback to the foundry for process improvement. Furthermore, a new screening methodology is innovated where an extreme low-voltage test at high temperature in Automatic Test to detect and eliminate the process marginal leakage failure.
Quantitative FIB-SEM 3D Tomography for Failure Analysis in Data Storage Industry
Authors: Li Zhi-Peng , Fang Jianxin , Wang Haifeng 
Published: December 2020

Abstract
Technology evolution in the data storage industry is driven by the continuous scaling down of devices and by an increasing complexity of the critical elements in the devices. Focused ion beam - scanning electron microscope (SEM) tomography can enable characterization of a device over its entire volume, while maintaining the resolution of the SEM. This study introduces the quantitative 3D tomography technique developed in the data storage industry to specifically address the industrial process development needs. In the detail section, the methodology of 3D reconstruction is introduced, key parameters are reviewed, and the steps for a successful 3D tomographic reconstruction are described. The study presents typical applications of 3D analysis for device design and process development to illustrate the benefits and unique learning opportunities. By reconstructing all slice-view 2D images quantitatively, 3D device structures and related 3D metrology data can be obtained.
Magnetic Head Shorting Failure Analysis
Authors: Hong Liang , Li Jia , Wang Haifeng 
Published: December 2020

Abstract
This paper provides an innovative root cause failure analysis method that combines multiple failure analysis (FA) techniques to narrow down and expose the shorting location and allow the material analysis of the shorting defect. It begins with a basic electrical testing to narrow down shorting metal layers, then utilizing mechanical lapping to expose over coat layers. This is followed by optical beam induced resistance change imaging to further narrow down the shorting location. Scanning electron microscopy and optical imaging are used together with focused ion beam milling to slice and view through the potential shorting area until the shorting defect is exposed. Finally, transmission electron microscopy (TEM) sample is prepared, and TEM analysis is carried out to pin point the root cause of the shorting. This method has been demonstrated successfully on Western Digital inter-metal layers shorting FA.
Combining Electron Beam Methods, EBIC and EBAC, with Traditional Approaches for Highly Effective Fault Isolation
Authors: Fredrickson Ryan , Kuebrich Tim , Le Andrew , Snider Derek , Winiarski Lucas 
Published: December 2020

Abstract
Fault isolation is an important initial component of the failure analysis investigation as it provides the first indicator of the defect physical location. The most broadly familiar fault isolation techniques include photoemission microscopy (PEM), optical beam induced resistance change (OBIRCH) and liquid crystal analysis (LCA). Each of these techniques has their own strengths but also drawbacks which can impede the analysis by either not providing a well isolated defect location or causing damage to the defect region. For some types of defects, photoemission and liquid crystal analysis may create local heating of the device which can distort the defect and mask the root cause of the failure. These techniques also rely on optical microscopy which has low resolution compared to the feature size of current technologies. In addition, each technique may not highlight the defect site itself; only pointing the analyst to the defective circuit within the sample. Electron Beam Induced Current (EBIC) and Electron Beam Absorbed Current (EBAC) microscopy provides solutions to these complications. In this paper we describe some very effective approaches by using these beam-based techniques in conjunction with traditional methods. As introduction, we have provided some interesting case studies whereby EBIC/EBAC have been used in conjunction with FIB circuit edits and scan diagnostic results to narrow the defect search areas. We focus the paper on some less common applications of cross sectional EBIC/EBAC as well as utilizing an AC coupled configuration to activate more subtle defect sites. We conclude with two examples where AC coupled cross-sectional EBIC is needed to highlight the cause of the failure.
Using Volume Scan Diagnosis and Data Mining in the Electrical Failure Analysis Flow for Production Yield Ramp
Authors: Shen Hao , Shen Lance , Xu Pierce , Yang Wu , Zhong Junna , Cheng Wu-Tung 
Published: December 2020

Abstract
Electrical failure analysis (EFA) is usually time consuming and expensive. It is a critical step bridging data failure analysis (DFA) and physical failure analysis (PFA). This paper presents experiments on using volume scan diagnosis as a component in building up an efficient EFA solution for digital circuits and discusses practical considerations in the production yield flow. It provides a brief review of the existing methods and the requirement to build an efficient flow, followed by a discussion on the proposed solution. The proposed solution can be used systematically in different stages of the production yield flow. The paper then shows industrial case studies and their results and benefits.
Accurate Defect Localization of Stacked Die Devices by Lock-in Thermography
Authors: Lin Ke-Ying , Tang Chih-Yi , Wang Yu Chi 
Published: December 2020

Abstract
The paper demonstrates the moving of lock-in thermography (LIT) spot location by adjusting the lock-in frequency from low to high. Accurate defect localization in stacked-die devices was decided by the fixed LIT spot location after the lock-in frequency was higher than a specific value depending on the depth of the defect in the IC. Physical failure analysis was performed based on LIT results, which provided clear physical defect modes of the stacked-die devices.
Evaluation on the Effectiveness of Removal VSON Package from FR4 Substrate Board
Authors: Yin Gan Sue 
Published: December 2020

Abstract
This paper is focused on the de-soldering process on VSON package which was mounted on FR4 substrate board after being subjected to environmental stress. Abnormalities were found at package level during Scanning Acoustic Microscopy (SAM) inspection which is considered to be one of the non-destructive failure analysis processes. Root cause finding involved the investigation of the de-soldering equipment which is suspected to be one of the culprits to contribute to the defect during de-soldering process.