bluuebunny/crossref_metadata_2025_split huggingface dataset:
Electrochemical Removal of NOx on Pt-Ba Impregnated Lscf/GDC Electrode
Authors: Wang Xi , Shi Xiang Yi , Alexandre Westermann , Viricelle Jean-Paul , Rieu Mathilde , Vernoux Philippe 
Published: February 2020

The NOx (mainly NO and NO2) pollutions that come from the exhaust of the thermal engines can give rise to a serious threat to the environment and human health. The design of more efficient and stable catalysts to reduce NOx to nitrogen in atmospheres containing excess oxygen (typically, from exhaust gas emitted by diesel and lean-burn gasoline engines) has attracted so much attention in the last years. The two actual technologies are using an additional reducing agent to remove NOx, i.e. Diesel fuel post-injection for the NOx storage reduction process and urea for the selective catalytic reduction. An alternative solution could be the electrochemical reduction of NOx in solid oxide electrolysis cell (SOEC)[1,2]that can save the huge reducing agents storage system.
This study reports the electrochemical properties for NOx reduction of a Mixed Ionic Electronic Conducting (MIEC) porous electrode promoted by Pt nanoparticles, as efficient catalyst for oxidation reactions, and BaO, as sorbents to store NOx. Pt and BaO nanoparticles were finely dispersed in the porosity of a MIEC film, based on a composite between LSCF (La0.6Sr0.4Co0.8Fe0.2O3-δ) and GDC (Gd0.2Ce0.8O1.9), which was deposited using screen-printing. This catalytic layer was interfaced on a dense pellet of gadolinium doped ceria (GDC), an O2- ionic conductor. The Ba and Pt loadings were around and 150 and 5 µg/cm², respectively. The catalytic performances, upon positive and negative polarizations, have been measured as a function of temperature in the range 200°C-500°C, partial pressure of oxygen and in the presence of propene in the feed. The NOx electrochemical conversion into N2 was found to be driven by the current (Figure 1) and the catalytic activity of the electrode for NO oxidation. In parallel, electrochemical properties have been carried out by using cyclic voltammetry and electrochemical impedance spectroscopy to investigate the electrocatalytic mechanism. Finally, the Pt and BaO nanoparticles in the LSCF/GDC film were characterized by transmission electronic microscopy.
References

T.J. Huang, C.Y. Wu, S.H. Hsu, C.C. Wu, Energy Environ.
Sci., 4, 4061 (2011).

R. M. L. Werchmeister, J. J. Bentzen, K. B. Andersen, and K. Kammer Hansen, J. Electrochem. Soc., 161(10) H663-H669 (2014)

Figure 1
(Science for Solving Society’s Problems Challenge Grant Winner) In-Situ Electrochemical Generation of the Fenton Reagent for the Treatment of Human Wastewater
Authors: Godinez Mora-Tovar Luis Arturo , Rodriguez Valadez Francisco Javier , Garcia Orlando , Fernandez Dennys , Zarate Ana I. 
Published: February 2020

It is well known that water contaminated with human waste is an important problem in a large part of the world; particularly in developing countries where substantial investments must be made in physical infrastructure so that water treatment plants could be used. In this regard, a feasible approach to face this problem is the development of on-site technologies using affordable and small devices that could be installed in every household. The aim of this project was therefore to design, build, and characterize a small Electro-Fenton reactor for human wastewater treatment.
The approach that was employed is based on the cathodic generation of H2O2 from oxygen reduction in activated carbon (AC) packed electrodes along with the combination of this species with H+ and Fe2+ ions provided by a cation exchange resin. In this way, a three-chamber reactor was built coupling an AC packed electrochemical system (middle compartment) with two additional compartments that contained a cation exchange resin that will change between source and collecting cation functions in cycles with a frequency 1/t1. In this way, setting the flow rate in any given direction, one resin chamber provided protons and ionic iron as water flows trough it, taking these chemical species to the middle compartment where the Electro-Fenton process takes place. The second resin chamber collected the cations as they come out from the middle compartment and after t1, when the resin-loaded chamber was loaded, the direction of the water flow and the potential in the electrode compartment was switched so that the process started over again.
From measurements of iron and proton desorption and adsorption along with electro-Fenton experiments, it was possible not only to obtain cycling-working conditions for the reactor under study but also to observe the successful coupling between the adsorption an cathode functions of the polarized AC packed in the central chamber of the reactor. Furthermore, using this small prototype to treat water contaminated with Helminth eggs (HE) of Ascaris lumbricoides (a human parasite that is highly resistant to the disinfection processes due to its robust external layers) it was possible to observe that the performance of the reported approach is promising since preliminary results showed a more efficient disinfection than that obtained using electrochemically generated hypochlorite.

Figure 1
Memcapacitive Characteristics of Metal-Oxide-Semiconductor Capacitor Structures by Compositional Redistribution
Authors: Yang Paul , Noh Young Jun , Baek Yoon-Jae , Zheng Hong , Kang Chi Jung , Yoon Tae-Sik 
Published: February 2020

Memcapacitive characteristics defined to be a memorized capacitance change has been recently suggested and experimentally demonstrated. Di Ventra et al. noted that the memcapacitive characteristics involve the capacitance change in metal-oxide resulting from microscopic geometry change or history-dependent permittivity change [1]. Wang et al. reported the memcapacitive characteristics in ionic transport through SiO2 conical nanopore in KCl solution caused by redistribution of mobile ions [2]. We previously reported the analog memcapacitive characteristics in pn junction diode structures [3]. The pn heterojunction with the assembly of n-type Fe2O3 nanoparticles having Pt core (called Pt-Fe2O3 core-shell nanoparticles) on p+-Si substrate exhibited gradually changing capacitance as repeating the application of voltage with respect to the polarity of voltage. The analog memcapacitive characteristics also emulated the biological synaptic potentiation and depression motions, which is indicative of potential application to neuromorphic devices as well as analog nonvolatile memory and circuits. Since the memcapacitive phenomenon exhibits the memorized capacitance change, the memcapacitor has a potential to modulate the forward and reverse current in diode structure through altering the barrier height and depletion width at the interface.
Also, the memcapacitance can modulate the drain current in MOSFETs and TFTs as variable gate stack capacitor, named memcapacitor, which gives the functions of memory, logic, neuromorphic operation, and so on. In this presentation, we discuss the memcapacitive characteristics in metal-oxide-semiconductor (MOS) capacitor structure consisting of reactive electrode (Mo, Al) and hafnium oxide (HfOX) on n-type Si and indium-gallium-zinc-oxide (IGZO) semiconductor substrates. The capacitance-voltage curves exhibited sequentially changing capacitance as repeating the voltage sweeps. The saturation capacitance was decreased as repeating +V application, while the depletion capacitance was barely changed as –V application. Also, the capacitance-time curves disclosed the same tendency of capacitance change. On the other hand, the MOS structure with inert electrode (Pt) did not show the capacitance change. These memcapacitive behaviors were induced by the migration of oxygen ions between reactive electrodes (Mo, Al) and HfOX, which modulated the permittivity and effective capacitor area. These results demonstrated the memcapacitive characteristics in MOS structure through voltage-driven oxygen migration for the application to memory, logic, and neuromorphic devices.
[1] M. Di Ventra, Y. V. Pershin, and L. O. Chua, Proc. IEEE 97 1717 (2009).
[2] D. Wang, M. Kvetny, J. Liu, W. Brown, Y. Li, and G. Wang, J. Am. Chem. Soc. 134, 3651 (2012).
[3] Y. J. Noh, Y.-J. Baek, Q. Hu, C. J. Kang, Y. J. Choi, H. H. Lee, and T.-S. Yoon, IEEE Trans. Nanotechnol. 14, 798 (2015)
Influence of Doping and Tunneling Interface Stoichiometry on n+In0.5Ga0.5As/p+GaAs0.5Sb0.5 Esaki Diode Behavior
Authors: El Kazzi Salim , Alireza A , Bordallo Caio Cesar Mendes , Smets Quentin , Desplanque Ludovic , Wallart Xavier , Richard Olivier , Douhard Bastien , Verhulst Anne , Collaert Nadine , Merckling Clement , Heyns Marc , Thean Aaron 
Published: February 2020

Due to energy-filtering by band-to-band quantum mechanical carrier tunneling, Tunnel FETs promise the possibility of steeper subthreshold swings (SS < 60 mV/dec) than MOSFETs. Even if the ideal material combination is still unclear, simulations show that for a confined channel (width<10nm), the broken gap InAs-GaSb system is the most promising to have the lowest SS with the highest Ion at low supply voltages. On the other hand, it is demonstrated that Esaki diodes can be used to accurately measure Band to Band Tunneling (BTBT) for TFET performance prediction. Since the tunnel junction is key for the operation of both TFET and Esaki diodes operation, the effect of different kind of defects (dislocations, etc...) can be seen directly from the TAT current in the diode I-V trace. In this vein, we study in our work the Molecular Beam Epitaxy (MBE) growth and fabrication of n+InAs-p+GaSb Esaki diodes on three types of substrates: GaSb, GaAs and Si.
We first present the pseudomorphic growth of n+InAs(Si)-p+GaSb(Si) Esaki diode on a (001) p+ GaSb substrate (ED1). We particularly show the influence of the InAs/GaSb interface nature on both structural and electrical quality. After choosing the right interface stoichiometry between InAs and GaSb, the growth of n+InAs(Si)-p+GaSb(Si) Esaki diode on GaAs is investigated (ED2). In here, 90° misfit dislocations (MDs) array at the GaSb/GaAs interface is used to accommodate the mismatch strain between GaSb and GaAs. After presenting the influence of the growth conditions on the MDs array formation, the electrical results of ED2 are compared to the ones of ED1. This learning is crucial to study the effect of dislocations on BTBT behavior in tunneling devices. In the last step, the integration of n+InAs(Si)-p+GaSb(Si) Esaki diode on (001) Si is presented (ED3) using a 300 mm GaAs on Si template grown by MOCVD. After presenting the detailed growth stack, we demonstrate a high quality n+InAs(Si)-p+GaSb(Si) growth on exactly oriented (001) Si substrate exhibiting a RMS surface roughness of 1.4 nm and a dislocation density (TD) of 9x107/cm2
, as determined by XRD analysis.
In summary, this study gives a broad insight on the influence of different types of defects on the tunneling current. We demonstrate that this learning is crucial for the integration of TFETs onto large area commercial Si substrates.
(Invited) Hardware Security to Mitigate Threats to Networked More-Than-Moore Sensors
Authors: Obeng Yaw S. 
Published: February 2020

More-than-Moore devices (MTM) devices and application platforms have their origin in the convergence of wireless technologies, advancements of microelectromechanical systems (MEMS) and digital electronics. Such application platforms comprise many small, inexpensive single-function devices and sensors, with varying operating systems, CPU types, memory, etc. How these devices connect to other devices, and the device-human interfaces, are changing how we work and live. Hardware security for these interconnected devices is a critical design consideration, just like performance, power, and reliability. However, due to increased globalization, the whole IC design flow and application phases are distributed world-wide, and the resultant reduced control over the IC life cycle make hardware security a serious concern. For example, hardware security threats in the integrated circuit (IC) supply chain, including hardware counterfeiting and intellectual property piracy cost the US economy more than $200 billion annually.
This paper examines the current issues pertaining to the hardware security and how they could affect the overall security of MTM applications, such as the internet of things. Specifically, we review the ongoing industry-led activities aimed at mitigating the hardware threats through supply chain assurance. The paper is illustrated with the ongoing work of the ITRS hardware security working group, the counterfeit risk mitigation efforts from iNEMI, and the High-Density Package User Group (HDPUG), as well as published standards from SEMI and the Open Group. All these efforts are aimed at mitigating counterfeits in the electronics supply chain through product traceability and authentication. Finally, we will discuss how existing and emerging technologies can be used for product authentication throughout the supply chain.
(Keynote) Challenges of 10 Nm and 7 Nm CMOS for Server and Mobile Applications
Authors: Divakaruni Rama , Narayanan Vijay 
Published: February 2020

CMOS scaling has served the semiconductor industry and transformed the world exceedingly successfully over the past several decades. In recent times, the transition to hi-K dielectric interfaces enabled CMOS to shrink circuits to below the 32nm node. The advent of fully depleted devices (FDSOI, FINFETs) have enabled CMOS scaling to the limits of conventional 193nm optical immersion lithography.
Over the past decade, CMOS scaling has transformed mobile technologies. The cell phone and smartphone have become ubiquitous as increased performance has been garnered to increase functionality on the form factor at constant power (Watt regime). The resulting boom in data has transformed industries and fueled the social network and the "app" world. 14nm FINFET technology is now available on cutting edge mobile devices. The 10nm node will see various incarnations across the major semiconductor fabricators. The pressure on density to reduce cost will result in the adoption of multiple patterning techniques for the FIN, Gate and various MIddle Of Line (MOL) and Back End Of Line (BEOL) wiring levels. The need to reduce doping in the FINFETs will result in Multi-Workfunction-Gates. Novel materials will be needed to reduce parasitic capacitance and resistance in the MOL and BEOL levels. Some incarnations of the 10nm node will be called "7nm", but the true "7nm" node circuit densities will require the next generation of lithography -- Extreme Ultra Violet (EUV) at 13.6nm wavelength. The key to adoption in the commodotized mobile space is thus the cost of the chip which is challenged by the need for novel cost intensive patterning techniques and new materials.
While power and form factor are key to the mobile world, Server applications have required performance at much higher power (100+ Watt regime). CMOS scaling has served this market very well over the decades as improved transitors have always been utilized for increased performance (high end servers run > 5 GHz). The growth in the server market has migrated to large datacenters for cloud applications and away from standard transaction processing (which still remains important in many areas). Parasitic components on FINFETs are thus much more critical in this market and has thus driven early adoption of "next generation" materials and processes. The adoption of 10nm and 7nm nodes in this space will be determined less by cost than by ability to get better performance at constant chip power given the increased parasitics in the MOL and BEOL. This drives the need for introduction of new novel materials for improved performance and reliability.
Vapor Phase Self-Assembled Monolayers for CMOS BEOL Barrier Layers
Authors: Naik Tejas RAJENDRA , Ravikanth M , Rao Valipe RAMGOPAL 
Published: February 2020

As the Back - End - of - Line (BEOL) Interconnects are scaling down to nanometer regime with multiple levels of metallization , need for ultra thin diffusion barrier layers arise. Self assembled monolayer (SAM) is an ideal solution to satisfy the requirement of an ultra thin barrier layer to avoid Copper difussion. However, wet chemical processes are preferably avoided in Complimentary - Metal - Oxide - Semiconductor (CMOS) fabrication process. Accordingly , a novel technique to form SAM of Zinc (||) tetraphenyl hydroxy porphyrin (ZnTPPOH) in vapor phase on Inter - Layer Dielectric (ILD) materials is developed in present work to suit the industry process flow and be integreable in CMOS fabrication. The vapor phase SAM formation of ZnTPPOH is investigated employing different techniques and studies from simple contact angle measurements, spectroscopic measurements such as x-ray photoelectron spectroscopy (XPS) , fourier transform infrared spectroscopy (FTIR) , Ultra Violet - Visible Spectroscopy (UV - Vis) , and the atomic force microscopy (AFM) , etc. The vapor phase SAM of ZnTPPOH was formed on different ILD materials such as Black Diamond , Hydrogen silsesquioxane , etc and also on Silicon dioxide substrates. Selective formation of SAM in vapor phase was studied using different substrates such as Gold , Copper , etc .
The vapor phase SAM was incorporated in Metal - Oxide - Semiconductor Capacitor (MOSCAP) structure. Copper was used as metal and the Vapor phase SAM was formed on Oxide / ILD materials so as to sandwich between the Copper and ILD, to repel and isolate the Copper in order to avoid any diffusion of Copper into the ILD materials. Capacitance - Voltage (CV) measurements , Current - Voltage characterization were done under bias and temperature stress on the MOSCAP devices to investigate the electrical performance of MOSCAP device and efficiency of ZnTPPOH vapor phase SAM as a barrier layer. Similarly blanket MOSCAP stack was formed and subjected to temperature stress and the extent of copper diffusion was investigated using (SIMS). Scanning electron microscopy (SEM) and scotch tape tests were done to observe improvement in adhesion of Copper to the ILD materials.
The vapor phase SAM process was optimized and devloped to suit the CMOS technology and demonstrated as an effective copper diffusion barrier layer for interconnects. This technique opens up a whole new set of opportunities to scale down the barrier layer thickness. Integrating such bottom-up approach within the CMOS fabrication process would make scaling to 7nm and beyond possible where interface layers, dielectrics, and semiconductor films will be on a molecular level.

Figure 1
(Invited) III-V / Si Integration for Photonics
Authors: Reithmaier Johann Peter , Benyoucef Mohamed 
Published: February 2020

In the last decade a large progress took place in the development of a Si-based fabrication technology platform for integrated photonics, however, mainly for passive devices, such as filters, waveguides, splitters and combiners. The integration of active devices remains very challenging. The talk will start with a brief review of different epitaxial approaches for III-V material growth on Si before a new approach will be presented, which may combine high Si process compatibility with full III-V material functionality.
Currently, active photonic devices on a silicon platform are obtained by bonding techniques, either on a single device chip or a full III-V wafer level. However, in this case the majority of III-V material is wasted by substrate removal. Direct epitaxy on silicon overcomes these problems but suffers in most cases from the lattice mismatch and the differences in expansion coefficients. This can be partially accommodated by thick relaxation layers and using quantum dot active regions to reduce the sensitivity against threading dislocations or using complex material compositions, like Ga(N,As,P), which allow lattice matching. However, the III-V layers have to be processed completely separate from the silicon.
A new approach based on III-V-Si nanocomposite is under development, which may overcome most of those problems. This approach is based on the growth of III-V quantum dots (QDs) directly on silicon. Based on a GaAs/InAs core-shell geometry high quality optical emission could be obtained. By overgrowing InAs QDs with silicon a defect free single crystal planar silicon layer can be formed with embedded InAs nano clusters. Transmission electron microscope investigations show that the nanoclusters fully relax by closed loop interface dislocations but without initiating threading dislocations in the silicon matrix.
Comprehensive Characterization of Dual Implanted Silicon after Electrical Activation Annealing
Authors: Yoo Woo Sik , Jeon Bong Seok , Kim Sang Deok , Ishigaki Toshikazu , Kang Kitaek 
Published: February 2020

Formation of low resistivity junctions is essential for fabricating high performance devices with advanced device modes. Significant effort has been expended, industry wide, to develop low resistivity junctions, over the years. However, the understanding of implant activation and implant damage recovery process is not sufficient. Development of noncontact implant residual damage monitoring techniques would be beneficial in process development for advanced node devices.
In this study, we have investigated the effect of annealing temperature and time on the sheet resistance (Rs) of dual (P+ 1.0MeV, 4.0 x 1013 cm-2 + B+ 10keV, 3.0 x 1014cm-2) implanted p--Si(100) wafers using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system over a wide range of annealing conditions (350-800oC, 60-150s). Room temperature photoluminescence (RTPL) spectra were measured from all wafers under two different excitation wavelengths (650 and 785 nm) for additional clues on electrical properties of pn junctions, which cannot be obtained from the Rs measurements. Multiwavelength (457.9, 488.0 and 514.5 nm) Raman characterization was done on all wafers for additional insights on the degree of residual lattice damage, after RTA, under different conditions. After all on wafer measurements were completed, secondary ion mass spectroscopy (SIMS) dopant (P and B) depth profiling was done to assess dopant diffusion during the annealing process.
Rs values showed strong and systematic change with RTA temperature and time, as expected. RTPL spectra also showed large variations in intensity and wavelength distribution corresponding to the RTA temperature and time. Multiwavelength Raman characterization results showed gradual increase of intensity with the RTA temperature. Three regions of different Raman shift values, corresponding to the Si lattice stress and possibly the degree of residual implant damage, were also noted. SIMS P and B depth profiles did not show significant changes. Correlation among characterization results from various techniques and RTA conditions will be presented.