bluuebunny/crossref_metadata_2025_split huggingface dataset:
A Comprehensive Failure Analysis Method and Mechanism Study on Ultra-Low-K Film Adhesion Failure
Authors: Shuting Chen , Lei Zhu , Wei Teo Han , Binghai Liu , Yanhua Huang , Kenny Ong , Zhiqiang Mo , Younan Hua , Zhaoxin Yuan , Seng Heng Yong , Yong Li Chao 
Published: December 2020

Abstract
The back-end-of-line (BEOL) structure of current IC devices fabricated for advanced technologies is composed of film stacks with multiple interfaces. The requirement of high interfacial strength is therefore necessary between the different layers in the BEOL stacks to ensure device reliability. To enhance the IC performance for new technologies, inter-level dielectric (ILD) made of SiO2 is replaced by low-k and ultra low-k (ULK) dielectrics, which possess a low dielectric constant but have poor mechanical strength. Therefore, the challenge in maintaining BEOL film stack integrity and reliability becomes even greater for advanced technologies. In this paper, we show failure analysis results on a case study of ULK adhesion failure during the IC manufacturing process. The symptoms of the BEOL failure are due to debris dropping on the wafer during chemical mechanical polishing (CMP) after Cu thin film deposition and failure of focusing at wafer extreme edge during the subsequent photolithography process. Extensive mechanical and chemical analyses were conducted on the ULK and adjacent thin films. It was revealed that the interface of ULK and Silicon Nitride from a suspected problematic machine showed abnormally low adhesion energy and high carbon composition. Troubleshooting on that suspected machine found a clog in the foreline. Based on the failure analysis and machine troubleshooting results, the failure mechanism of the case was discussed.
TEM Failure Analysis and Root Cause Understanding of Nitride Spacer Bridging in 45 nm Semiconductor Manufacturing Processes
Authors: Binghai Liu , Zhiqiang Mo , Ping Zhao Si , Yuan Yao , Hong Teo Kim , Ye Chen , Irene Tee , Li Lee Gek , Changqing Chen , Boon Ang Ghim , Yogaspari  , Tan Robin 
Published: December 2020

Abstract
Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.
First in Operando SEM Observation of Electromigration-Induced Voids in TSV Structures
Authors: Gousseau Simon , Moreau Stéphane , Bouchu David , Farcy Alexis , Montmitonnet Pierre , Inal Karim , Bay François 
Published: December 2020

Abstract
Since the early beginning of the integrated circuits, electromigration is a reliability issue of first interest. In 3-dimensional structures, electromigration is responsible for the formation of voids in lines connected to the Through Silicon Via (TSV). To our knowledge, this paper presents the first in operando electromigration experiment in a Scanning Electron Microscope (SEM) performed for 3D integration. The experimental protocol, including sample preparation and temperature regulation, is detailed. A current of 25 mA is injected in a structure heated at 350 °C for about 900 h. The evolution of voids is monitored and explained. Void growth occurs step by step, so that the microstructure may be assumed to play a major role in the depletion mechanism. The behavior of the electrical resistance is analyzed using the SEM micrographs.
Automatic Registering and Stitching of TEM/STEM Image Mosaics
Authors: Lin Chung-Ching , Stellari Franco , Gignac Lynne , Song Peilin , Bruley John 
Published: December 2020

Abstract
Transmission Electron Microscopy (TEM) and scanning TEM (STEM) is widely used to acquire ultra high resolution images in different research areas. For some applications, a single TEM/STEM image does not provide enough information for analysis. One example in VLSI circuit failure analysis is the tracking of long interconnection. The capability of creating a large map of high resolution images may enable significant progress in some tasks. However, stitching TEM/STEM images in semiconductor applications is difficult and existing tools are unable to provide usable stitching results for analysis. In this paper, a novel fully automated method for stitching TEM/STEM image mosaics is proposed. The proposed method allows one to reach a global optimal configuration of each image tile so that both missing and false-positive correspondences can be tolerated. The experiment results presented in this paper show that the proposed method is robust and performs well in very challenging situations.
Device Characterization Using AFP Nanoprobing for the Localization of New Product Design Weakness
Authors: Ang Ghim Boon , Quah Alfred , Chen Changqing , Zhao Si Ping , Nagalingam Dayanand , Li Yan , Neo Soh Ping , Shailesh Redkar 
Published: December 2020

Abstract
This paper illustrated the beauty of AFP nano-probing as the critical failure analysis tool in localizing new product design weakness. A 40nm case of HTOL Pin Leakage due to Source/Drain punch-through at a systematic location was discussed. The root cause and mechanism was due to VDS overdrive testing issue. This paper placed a strong emphasis on systematic problem solving approach, deep dive and use of right FA approach/tool that are essentially critical to FA analysts in wafer foundry since there is always minimal available data provided. It would serve as a good reference to wafer Fab that encountered such issue.
A Study of Electron Beam Irradiation Influence on Device Contact Junction Characteristics of Advanced DRAM Using Atomic Force Probing
Authors: Wang Wei-Chih , Luo Jian-Shing 
Published: December 2020

Abstract
In this paper, we revealed p+/n-well and n+/p-well junction characteristic changes caused by electron beam (EB) irradiation. Most importantly, we found a device contact side junction characteristic is relatively sensitive to EB irradiation than its whole device characteristic; an order of magnitude excess current appears at low forward bias region after 1kV EB acceleration voltage irradiation (Vacc). Furthermore, these changes were well interpreted by our Monte Carlo simulation results, the Shockley-Read Hall (SRH) model and the Generation-Recombination (G-R) center trap theory. In addition, four essential examining items were suggested and proposed for EB irradiation damage origins investigation and evaluation. Finally, by taking advantage of the excess current phenomenon, a scanning electron microscope (SEM) passive voltage contrast (PVC) fault localization application at n-FET region was also demonstrated.
Adaptive Optics Compensation of Aberrations Introduced by Sample Thickness Error in aSIL Confocal Scanning Microscopy
Authors: Lu Y. , Bifano T.G. , Ünlü M.S. , Goldberg B.B. 
Published: December 2020

Abstract
We report on aberration compensation in an aplanatic solid immersion lens microscope used for high-resolution backside inspection of silicon integrated circuits. The imaging quality of aplanatic SIL microscope is shown to be significantly degraded by aberrations, especially when the silicon integrated circuit samples have thicknesses that are more than a few micrometers thicker or thinner than ideal. We describe and demonstrate a technique to recover near-ideal imaging quality by compensating those aberrations using a MEMS deformable mirror. The mirror, located in an optical plane conjugate to the microscope objective, is shaped in a way that counteracts spherical aberration errors associated with non-ideal sample thickness.
An Effective SIMS Methodology for GOI Contamination Analysis
Authors: Huang Yanhua , Zhu Lei , Ong Kenny , Teo Hanwei , Hua Younan 
Published: December 2020

Abstract
Contamination in the gate oxide layer is the most common effect which cause the gate oxide integrate (GOI) issue. Dynamic Secondary Ion Mass Spectrometry (SIMS) is a mature tool for GOI contamination analysis. During the sample preparation, all metal and IDL layers above poly should be removed because the presence of these layers added complexity for the subsequent SIMS analysis. The normal delayering process is simply carried out by soaking the sample in the HF solution. However, the poly surface is inevitably contaminated by surroundings even though it is already a practice to clean with DI rinse and tape. In this article, TOFSIMS with low energy sputter gun is used to clean the sample surface after the normal delayering process. The residue signals also can be monitored by TOF SIMS during sputtering to confirm the cross contamination is cleared. After that, a much lower background desirable by dynamic SIMS. Thus an accurate depth profile in gate oxide layer can be achieved without the interference from surface.
Die Level Defect Analysis Using Combined Techniques of AFP with Electron Microscopes
Authors: Yin Lee Lan , Haonan Bai , Keng Chua Kok , Meng Chow Yew , Tan Grace 
Published: December 2020

Abstract
With the device geometries shrinking, defect isolation becomes more challenging with the reduction of operating voltage and current levels. In this failure analysis study, a combination of AFP current contrast imaging and nanoprobing at the contact layer successfully isolated the defect location to a specific poly feature, where prior PVC analysis had been unsuccessful. The diagnosis was validated with subsequent high beam SEM inspection and TEM analysis, which revealed residual material beneath the suspected failing poly feature causing the poly to N+ diffusion short failure.
Enabling Scanning Acoustic Microscopy Inspection of Materials Underneath the Chamfer of the Package
Authors: Cajita Melanie S. , Grancapal Marlyn C. , Sia Rudolf A. 
Published: December 2020

Abstract
This paper describes how scanning acoustic microscopy can be used to inspect materials under the chamfer of electronic device packages. The technique involves the use of copper tape to locate the areas affected by the chamfer during X-ray radiography. The results are then correlated with known critical package and assembly geometries to determine how far parallel lapping should proceed to ensure that the areas of interest will become observable under acoustic microscopy without interfering with the functionality of the device.
High Resolution C-Mode Scanning Acoustic Microscope Techniques for the Failure Analysis of Microelectronic Packages
Authors: Li Yan , Hu Liang , Li Gang , Dias Rajen , Goyal Deepak 
Published: December 2020

Abstract
Fault isolation and failure analysis for Si related issues in microelectronic packages need non-destructive and high resolution techniques to reduce the analysis time. This paper illustrates non-destructive and high resolution CSAM techniques, which are shown to be very effective in subtle thin film defect and die edge defect CSAM imaging.
Localization of a Complex Failure by Combining ATPG and Customer-Oriented Application Testing
Authors: Wang Kai , Weaver Rhys , Johnson David 
Published: December 2020

Abstract
A systemic analysis was chosen to evaluate a real case Bluetooth (BT) radio failure in the aspects of RF communication, digital design, firmware, application software, semiconductor device physics and processing, and failure analysis. This paper explores the range of testing, including customer application testing, required to confirm and localize a BT RF communication failure. It shows that the radio communication failure was not, as expected, caused by faulty radio hardware; it was rather linked to problematic encryption hardware at the assistance of the Synergy BT to mobile application. The paper also explores that the digital fault can only be detected by the timing sensitive transition fault scan patterns and how to obtain the physical failure location. Thus, the combination of ATPG and application testing provides a consistency between electrical diagnostics which yields a higher success rate at subsequent physical failure analysis of complex modern RF System on a Chip.
Micro-Abrasive Blasting—A Novel Approach to Local Silicon and Mold Compound Material Removal
Authors: Sun Zhenzhou , Bosio Alberto , Dilillo Luigi , Girard Patrick , Todri Aida , Mulholland Matthew M. , Nguyen Hien 
Published: December 2020

Abstract
Post silicon validation techniques on Integrated Circuits (IC) specifically FIB circuit editing require backside sample preparation done by local mold compound and silicon machining. Conventional methods such as Computer Numerically Controlled (CNC) machining and chemical etching preparation platforms are commonly used. This paper will investigate a simple alternative approach to local sample preparation by using micro-abrasive blasting. This approach will display its simple natured set-up along with extremely quick process duration.
Study of Static Noise Margin and Circuit Analysis on Advanced Technology Node SRAM Devices by Nanoprobing
Authors: Dawood M.K. , Ng T.H. , Tan P.K. , Tan H. , James S. , Limin P.S. , Huang Y. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
With further technology scaling, it becomes increasingly challenging for conventional methods of failure analysis (FA) to identify the cause of a failure. In this work, we present three case studies on the utilization of advanced nanoprobing for SRAM circuit analysis and fault identification on 20 nm technology node SRAM single bit devices. In the first 2 case studies, conventional failure analysis by passive voltage contrast (PVC) failed to identify any abnormality in the known failed bit. In the third case study, an abnormally bright PVC was observed by PVC inspection. In all three case studies, static noise margin of the SRAM bits during hold and read operations were performed to understand the circuit behavior of the failed bit cell. Next, nanoprobing on the individual transistors were performed to determine the failing transistor within the bit and the possible cause of the failure. TEM analysis was performed to identify and verify the failure mechanism.
High-Resolution Backside GMR Magnetic Current Imaging on a Contour-Milled Globally Ultrathin Die
Authors: Vallett D. , Gaudestad J. , Richardson C. 
Published: December 2020

Abstract
Magnetic current imaging (MCI) using superconducting quantum interference device (SQUID) and giant-magnetoresistive (GMR) sensors is an effective method for localizing defects and current paths [1]. The spatial resolution (and sensitivity) of MCI is improved significantly when the sensor is as close as possible to the current paths and associated magnetic fields of interest. This is accomplished in part by nondestructive removal of any intervening passive layers (e.g. silicon) in the sample. This paper will present a die backside contour-milling process resulting in an edge-to-edge remaining silicon thickness (RST) of &lt; 5 microns, followed by a backside GMR-based MCI measurement performed directly on the ultra-thin silicon surface. The dramatic improvement in resolving current paths in an ESD protect circuit is shown as is nanometer scale resolution of a current density peak due to a power supply shortcircuit defect at the edge of a flip-chip packaged die.
Correlation of Thin Film Measurement Techniques for Device Packaging Processes
Authors: Walter J. , Mack W. , Lee C.Y. , Gspan C. 
Published: December 2020

Abstract
The analysis of thin layers in semiconductor components represents a central point in the quality control of semiconductor companies. Not only to control production processes, but to successfully operate also reverse engineering, reliable thin-film measurement methods are essential. In this work, non-destructive thin film EDX (energy dispersive X-ray micro analysis) software and μXRF (micro x-ray fluorescence analysis) were compared with TEM analysis. These methods ensure a high lateral resolution which is essential in the analysis of semiconductor structures. As an example, four different, for the semiconductor industry interesting, very thin coating systems in the nanometer range have been tested. In the individual cases best TEM detector contrast settings could be found, as well as optimum fluorescence lines settings on the EDX to minimize the errors. The TEM measurements, in thickness and composition, were compared to the thin film EDX software and the μXRF method results to determine their accuracy. It turns out that depending on the layer system recalibration with multilayer standards or at least with elemental standards is recommended. It could be shown that with μXRF and thin film EDX a reliable, rapid and non-destructive layer analysis is possible.
Failure Mechanism Studies and Root Cause Identification of Nonstick on Pad on Microchip Al Bondpads
Authors: Younan Hua , Yongkai Zhou , Yixin Chen , Chao Fu , Xiaomin Li 
Published: December 2020

Abstract
It is well-known that underetch material, contamination, particle, pinholes and corrosion-induced defects on microchip Al bondpads will cause non-stick on pads (NSOP) issues. In this paper, the authors will further study NSOP problem and introduce one more NSOP failure mechanism due to Cu diffusion caused by poor Ta barrier metal. Based on our failure analysis results, the NSOP issue was not due to the assembly process, but due to the wafer fabrication. The failure mechanism might be that the barrier metal Ta was with pinholes, which caused Cu diffused out to the top Al layer, and then formed the “Bump-like” Cu defects and resulted in NSOP on Al bondpads during assembly process.
Pulsed Laser Stimulation Coupled with Optical Failure Analysis Technique—A Methodology to Help Space Application Electrical Designers
Authors: Bascoul G. , Sanchez K. , Perez G. , Bezerra F. , Chauvin H. 
Published: December 2020

Abstract
Pulsed laser for radiation sensitivity evaluation has become a common tool used in research and industrial laboratory. This paper aims to highlight an approach to understand weaknesses of a component under radiation environment using a short pulsed width laser beam coupled to thermography technique, heavy ions test inputs and physical analysis. This paper is based on a study of a PWM device embedded on voltage converter.
WISE and ICARUS—New X-Ray Algorithms to Improve the Detection of Counterfeit Components
Authors: Cardoso Bill 
Published: December 2020

Abstract
The drive towards miniaturization has created increasing challenges to the overall failure analysis and quality inspection of electronic devices. This trend has equally challenged the image quality of x-ray inspection systems – engineers need to see more details in each inspection. Image quality is paramount to the ability of making actionable decisions on the information acquired from an x-ray machine. Previous generations of x-ray technologies have focused on hardware improvements – better x-ray sources and better x-ray sensors. Although further improvements can still be achieved in hardware, our focus will be on the latest wave of technology breakthroughs and innovation in radiography systems: algorithms.
Materials Analyses for Parts Validation
Authors: Wolfgong W. John , Izzo James 
Published: December 2020

Abstract
The most common methodologies for determining whether a component should be judged suspect counterfeit, or not, rely on visual examination, electrical test, and X-ray examinations. While these are commonly sufficient at such determinations, more thorough examinations may be pursued - in particular materials characterizations. In this paper, examples are given in which such “non-standard” methods are employed. Additionally, the results of an investigation as to the applicability of such methods towards detection of surface alteration to facilitate repackaging are described.
Comparison of Magnetic Field Imaging and Thermal Laser Stimulation for Detecting Electrically Shorting Defects within a Die BEOL
Authors: Distelhurst Kevin A. 
Published: December 2020

Abstract
Magnetic Field Imaging (MFI) and Thermal Laser Stimulation (TLS) failure analysis (FA) techniques (e.g. OBIRCH, XIVA, ect.) both have advantages and disadvantages. The obstacles encountered from these techniques may hinder further fault isolation (FI), lengthen turn-around-time and/or detract from actionable results. MFI using a Giant Magneto Resistance (GMR) sensor is compared to TLS techniques to understand the capability of the MFI technique at finding shorting defects. A short within a capacitor bank is successfully isolated using both techniques.
TEM Sample Preparation Tricks for Advanced DRAMs
Authors: Sung Ching Shan , Lee Hsiu Ting , Luo Jian Shing 
Published: December 2020

Abstract
Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.
Failure Induced by a Progressive Defect in Memory Device
Authors: Nam Incheol , Ryu Hodong , Kim Jinseon , Lee Kwangwon , Kim Daesun , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung 
Published: December 2020

Abstract
System failure due to a progressive defect in memory cell-array of DRAM was studied with automated test equipment. In order to find out relationship correctable single-bit fault and system failure, memory cells with single-bit fault by a cross-defect were selected. After high voltage and temperature stress, a soft cross-defect was changed into a hard cross-defect. Consequentially, invalid operation by a degraded cross-defect causes array-failure. Based on the failure analysis, methods to prevent array-failure are proposed, and applied to DRAM successfully.