bluuebunny/crossref_metadata_2025_split huggingface dataset:
Design Based Failure Analysis of a Voltage Sensitive Memory Defect
Authors: Bowsher Andrew , Gloor Cary A. , Griffiths Bruce , McMahon Chris 
Published: December 2020

Abstract
The semiconductor failure analyst’s tool box is a vast and resourceful set of capabilities that more than ever needs meaningful Memory Failure Signature Analysis (Memory FSA) as an important part of that suite. Today, this is driven by advanced process technology nodes that are producing virtually invisible defects to confound manufacturing and reliability. This demands greater attention to characterizing memory failures in order to theorize causes for failure and to implement suitable FA approaches and corrective action plans. Design Based FA (DBFA) techniques aim to extend this philosophy by focusing on a deep understanding of the chip’s Intellectual Property (IP), in terms of both content and architecture. It uses this knowledge to gain important insights into the behavior of the failure that otherwise may have been hidden or unobservable. This disciplined methodology leads to quicker closure for problems through implementing improved test screens, providing recommendations under a closed-loop Design for Manufacturing (DFM) system, enacting process enhancements, or some combination of all these areas. Here we present a clever technique to further aid in the failure signature analysis process and use it as an example for this Design Based FA methodology.
Novel Plasma FIB/SEM for High Speed Failure Analysis and Real Time Imaging of Large Volume Removal
Authors: Hrnčíř T. , Lopour F. , Zadražil M. , Delobbe A. , Salord O. , Sudraud P. 
Published: December 2020

Abstract
The standard Ga focused ion beam (FIB) technology is facing challenges because of a request for large volume removal. This is true in the field of failure analysis. This article presents the first combined tool which can fulfill this requirement. This tool offers the combination of a high resolution scanning electron microscope (SEM) and a high current FIB with Xe plasma ion source. The article focuses on failure analysis examples and discusses the different steps of extra large cross sections (deposition of protective layer, rough milling, and polishing). Several applications of the novel Xe plasma FIB/SEM instrument are shown with respect to the failure analysis. The performance of the instrument is tested and discussed in comparison to gallium liquid metal ion source FIB systems. Results show that the Xe plasma FIB offers much higher milling rate, greatly reducing the time necessary for many failure analysis tasks.
Failure Analysis Using Scanning Acoustic Microscopy for Diagnostics of Electronic Devices and 3D System Integration Technologies
Authors: Czurratis Peter , Hoffrogge Peter , Brand Sebastian , Altmann Frank , Petzold Matthias 
Published: December 2020

Abstract
New semiconductor chip technologies and technologies for 3D integration require information’s of packaging and interface defects in 3 dimensions, that means the lateral dimension of the defect and the location inside the device or package must be defined. In this paper, new methodical approaches for non destructive failure analysis on 3D integrated TSV samples are introduced. The concepts combine improved scanning acoustic microscopy (SAM) imaging hardware with unique software solutions for defect identification and quantitative analysis of mechanical properties using scanning acoustic investigations. In case of MEMS 3D integration, e.g. based on direct bonding, related interface defects must be investigated by SAM. With respect to 3D integration applications, the potential of recent SAM improvements applying specifically adapted hardware and custom-made signal processing algorithms will be discussed. Examples of SAM-based failure detection techniques for the application in 3D integration are demonstrated. New technologies are shown to improve the through put of fully wafer scanning using scanning acoustic microscopy. To improve the defect resolution, a new transducer design was developed to increase defect resolution and signal to noise for interface characterisation.
SIMS Analysis for the Threshold Voltage Shift of Power MOS Caused by Abnormal Dopant Diffusion
Authors: Huang Yanhua , Zhu Lei , Ong Kenny , Teo Hanwei , Chen Shuting , Hua Younan , Shen Miao , Gong Hao 
Published: December 2020

Abstract
Threshold Voltage (Vt) of MOSFET controls transistor’s on and off state. Vt is usually depends on gate oxide thickness and operating temperature. Systematic failure analysis for a Vt shift issue, should also consider the channel doping which affects the inversion layer formation. In this article, the failure case of a shift in the Vt of a Power MOSFET V is studied. Secondary Ion Mass Spectrometry (SIMS) is found to be the most direct way for detecting any abnormality in the channel doping profiles. A comprehensive simulation is performed showing that the Phosphorus level diffusion from substrate was so high that it affects the doping concentration of channel.
Lock-in Thermography for Flip-Chip Package Failure Analysis
Authors: Cao Lihong , Venkata Manasa , Huynh Jeffery , Tan Joseph , Tay Meng-Yeow , Qiu Wen , Wadhwa Kannu , Schlangen Rudolf 
Published: December 2020

Abstract
This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.
Metallic Nanoneedles Arrays for TEM Sample Preparation “Lift-Out”
Authors: Jalilian Romaneh , Mudd David , Torrez Neil , Rivera Jose , Yazdanpanah Mehdi M. , Miller Brian 
Published: December 2020

Abstract
The sample preparation for transmission electron microscope can be done using a method known as "lift-out". This paper demonstrates a method of using a silver-gallium nanoneedle array for a quicker sharpening process of tungsten probes with better sample viewing, covering the fabrication steps and performance of needle-tipped probes for lift-out process. First, an array of high aspect ratio silver-gallium nanoneedles was fabricated and coated to improve their conductivity and strength. Then, the nanoneedles were welded to a regular tungsten probe in the focused ion beam system at the desired angle, and used as a sharp probe for lift-out. The paper demonstrates the superior mechanical properties of crystalline silver-gallium metallic nanoneedles. Finally, a weldless lift-out process is described whereby a nano-fork gripper was fabricated by attaching two nanoneedles to a tungsten probe.
Failure Analysis of Nickel Silicide Piping Failures: A Case Study
Authors: Howard Clifford , Tsang Yuk , Subramanian Sam , Ly Khiem , Chrastecky Tony , Erington Kent , Ybarra Juan 
Published: December 2020

Abstract
As semiconductor geometries decrease, the size of a defect that leads to circuit failure also decreases. While many defects will cause photoemission or observable leakage paths, occasionally a defect will occur in an area that cannot be easily analyzed. In this analysis, a yield issue in nickel-silicide (NiSi) piping is investigated. The failure had characteristics that fell into areas that avoided detection. A planar transmission electron microscope of the substrate at the defect site was performed to look for evidence of crystalline defects that would allow a conduction path across the channel. This analysis found that NiSi encroachment was the root cause of the yield issue. All analyzed units had the defect between stacked nFET transistors. Because the defect was between stacked nFET gates, the results show that the failure characterization required control of multiple gates to measure the transistor off-state drain to source current.
A Novel Scan-Based Yield Enhancement Methodology for Faster Yield Ramp
Authors: Goh S.H. , Lee H.C. , Lim T.Y. , Ting Fei , Ngow Y.T. , Ng J.H. , Kong F.L. , Lau W.Y. , Lim S.K. , Lam Jeffrey , Yan Pan , Liu Y.J. 
Published: December 2020

Abstract
Scan chain integrity yield loss is a common concern, especially in early stage of product yield ramp. Typically, scan chain failure diagnosis can only proceed upon full silicon build and structural test. In this work, we propose a proactive methodology which enables failure debug step to be initiated as early as the onset of device fabrication, to bring forward yield learning. Scan chain cells and nets information are extracted from design data file and converted to inline optical wafer inspection care areas. In this way, the inspection recipe can be optimized for the detection of scan chain related defects. It is shown experimentally that such approach can potentially enhance general defect detection sensitivity by 50% and increase the defect hit probability on scan chain nets. Any findings serve as useful early data for process improvement feedback. Furthermore, marginal defects, which otherwise are not easily revealed using conventional approach, can also be detected to provide early warning for process drifts or variations.
Thermal Investigations on CMOS Integrated Micro-Hot-Plates Using IR Thermography
Authors: Schmidt Christian , Altmann Frank , Mutinati Giorgio C. , Brunet Elise , Steinhauer Stephan , Koeck Anton , Siegele Martin , Gamauf Christoph , Nemecek Alexander , Teva J. , Kraft J. , Siegert J. , Schrank F. , Kruschke Hans 
Published: December 2020

Abstract
In this paper, investigations on absolute temperature measurements using IR-Thermography of CMOS integrated micro-hot-plates (μHP) are presented. The results of using two different approaches, emissivity correction and black paint coating, are presented and compared with respect to simulation and electrical testing results. In addition, FIB/SEM investigations were used for surface investigations and determination of possible influences to the thermal behaviour by black paint coating process.
Studies of Buried Voids Capturing with e-Beam Inspection System and Confirmation with Physical Failure Analysis
Authors: Xiao Hong , Jiang Ximan 
Published: December 2020

Abstract
In this paper, a novel inspection mode of electron beam inspection (EBI) that can effectively detect buried voids in tungsten (W) plugs is reported for the first time. Buried voids in metal are a defect of interest (DOI) that cannot be captured by either optical inspection or traditional EBI modes. The detection of buried voids is achieved by using energetic electron beam (e-beam) with energy high enough to penetrate into metal and reach the buried void. By selecting desired secondary electrons to form the inspection images, strong contrast between the defective tungsten plugs and normal ones can be achieved. Failure analysis was performed on the DOI that is unique to this new EBI mode. After optical microscope locating and laser marking, we successfully recaptured DOI with scanning electron microscope (SEM) and capped the DOI with e-beam assisted platinum (Pt) deposition. Later a dual-beam focused ion beam (FIB) system was used to re-locate the Pt-capped DOI and prepare samples for transmission electron microscope (TEM). TEM images confirmed the unique DOI were buried voids in the metal plugs, which could affect resistance of interconnect in integrated circuit (IC) chip and impact the IC yield.
Conversion of a D-Mode FET to an E-Mode FET via Electrostatic Discharge in a GaAs Power Amplifier Duplexer Module
Authors: Emergo Rose , Brockett Steve 
Published: December 2020

Abstract
This paper outlines the systematic isolation of an electrostatic discharge defect on a depletion-mode FET. Topics covered are fault isolation, FIB-STEM cross-section and EDS analysis, and defect simulation. Multiple GaAs PA devices were submitted for analysis after failing different reliability stresses. Fault isolation revealed ESD damage on a DFET connected to the VMODE0 pin. Simulation of the failure showed that, most likely, the defect was caused by CDM stress. A design change of inserting a resistor between the VMODE0 pin and the DFET made the device more robust against CDM stress.
Pump-Probe Imaging of Integrated Circuits
Authors: Stoker David , Bruce Michael , Lavelle Eric , Matlin Erik , Potthast James , Sakai Christopher , Troy Neil 
Published: December 2020

Abstract
We present a new method of imaging integrated circuits (ICs) using a dual-laser scanning confocal microscope. In this method we introduce physical and/or functional changes to the integrated circuit using the first ‘pump’ laser and then image the response of the circuit using the second ‘probe’ laser. We propose several novel applications of this imaging method. Specifically, we show how to image the flow of injected charge carriers and use the derived images to improve the resolution of material interfaces. We also show how to image changes to activity and laser voltage-probed waveforms and use the information to discover electrical connections between logic cells.
Tester-Based Methods to Enhance Spatial Resolvability and Interpretation of Time-Integrated and Time-Resolved Emission Measurements
Authors: Stellari Franco , Song Peilin , Weger Alan J. , Maliuk Dzmitry , Ainspan Herschel A. , Kim Seongwon , Kwark Young , Baks Christian W. 
Published: December 2020

Abstract
In this paper, we discuss the use of a tester-based methodology to enhance the spatial resolvability and interpretation of time-integrated and time-resolved emission measurements. This technique, first presented at [1] for chip diagnostics and failure localization, is very powerful for extending the capability of modern analytical tools beyond the limits of existing optics and detectors. In particular, we will discuss how the proposed method works and present several test cases for both static and dynamic emission measurements that allow signals from gates 150 nm apart to be resolved.
Advanced FIB CE Combined with Static Analysis for Functional Failure Analysis
Authors: Loh S.K. , Chen C.Q. , Yip K.H. , Quah A.C.T. , Tao X. , Ng P.T. , Ang G.B. , Zhao S.P. 
Published: December 2020

Abstract
It is difficult to simulate functional failures using static analysis tools, therefore, debugging and troubleshooting devices with functional failures present a special challenge for failure analysis (FA) work and often result in a root-cause success rate is quite low. In this paper, the application of advanced FIB circuit edit (CE) processes combined the static FA analysis yielded successful localization of a bipolar junction transistor (BJT) device soft failure. Additional FA techniques were incorporated within the FA flow, resulting in characterization of the electrical behavior of a suspected transistor and detection of an abnormal implant profile within the active area.
Application of AFP in Resolving Systematic Issue in Wafer Fabrication
Authors: Ng Hui Peng , Ang Ghim Boon , Chen Chang Qing , Quah Alfred , Teo Angela , Lee Mern Tat , Indahwan Jony , Zhao Si Ping 
Published: December 2020

Abstract
With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]
Memory Address Verification Using NIR Laser
Authors: Hoe Wilson Lee Cheng , Saku Leena , Kok Ong Wei , Kian Yau Moi , Ren Felix Yue 
Published: December 2020

Abstract
The upward trend in memory to chip ratio in novel chip design had increase the possibility of a defect to fall on the memory area. There are a number of ways of performing memory address verification in the industry. This paper describes some of the methodologies as well as introduces an efficient approach using near infra-red (NIR) laser to perform the memory address verification. Current methodologies include analyzing physical chip with memory hard failure, the green laser (532nm) method, and the focus ion beam method. The advantages and disadvantages of each methodology are mentioned. As long as the failing orientation is correct and the test program failing address is within the NIR laser damage zone, a failure analyst can have more confidence to analyze a real chip with memory failure without any doubt that he/she might be looking at the wrong location.
TEM Sample Preparation Methods for MEMS Floating Structure Analysis
Authors: Yu Huisheng , Duan Shuqing , Li Ming 
Published: December 2020

Abstract
The MEMS structure has its particular character like hollow areas inside, and “floating” structures. Traditional TEM sample preparation method usually leads to distortion and dissociation defects of the floating structure. This paper introduces two innovative practical methods of TEM sample preparation using focused ion beam (FIB) for MEMS floating structure analysis. Method 1 used glass needle to lift out the separated film onto glue coated blank wafer; method 2 used in situ pick up system to lift out L- or C-shaped cut film onto TEM half-grid. And then the sample can be applied to normal TEM membrane preparation procedure.
Design Debug for Intermittent Power up Failure in Analog/Mixed Signal Devices
Authors: Karki Sagar , Sule Oladele , Zhihong You 
Published: December 2020

Abstract
To maintain product reliability and robustness, current generation submicron integrated circuits need to pass high quality and exhaustive testing programs before being shipped off to the customer or released into the market. Precise and reliable silicon debug is essential to the semiconductor industry. It identifies problems caused by design changes, process anomalies and rarely used applications. This is essential to drive the corrective action at the earliest stage of production. This paper describes the systematic approach of a complex design debug in one of the ASIC device.
Optical Fault Isolation and Nanoprobing Techniques for the 10 nm Technology Node and Beyond
Authors: von Haartman Martin , Rahman Samia , Ganguly Satyaki , Verma Jai , Umair Ahmad , Deborde Tristan 
Published: December 2020

Abstract
Resolution of optical fault isolation (FI) and nanoprobing tools needs to keep pace with the device downscaling to be effective for semiconductor process development. In this paper we present and discuss state-of-the-art FI and nanoprobing techniques evaluated on Intel test-chips fabricated on next generation process technology. Promising results were obtained but further improvements are necessary for the 7nm node and beyond.
Device Ioff Mapping—Analysis of Ring Oscillator by Optical Beam Induced Resistance Change
Authors: Johnson Greg M. , Xu Ziyan , D’Aleo Christopher 
Published: December 2020

Abstract
The ring oscillator is an important tool for inline monitoring during technology development, as it contains the most important front end of line technology features, is testable at first metal, and generally shows a good correlation to SRAM yield. This work explores various failure analysis techniques for the ring oscillator, during the development of 14 nm FinFET technology. OBIRCH, which is typically a DC technique, was operated with voltages as low as 0.15 V to find multiple defect mechanisms affecting the yield of ring oscillators, which operate at a frequencies in the GHz range. In contrast to typical photon emission analysis of ring oscillators, examines the devices which are flipping on, it is here proposed that the OBIRCH spots which are generated are indications of the Ioff, or the leakage of devices in the inverter stages across the ring. The results from this failure analysis approach enabled a rapid improvement in yield not only of the ring oscillator itself but of the SRAM.
2015 ISTFA Presentation #1: 2010–2015—The Evolving Counterfeit Machine
Authors: Sharpe Thomas 
Published: December 2020

Abstract
This presentation is chronologically-progressive to the author's ISTFA Keynote given in 2010: "Counterfeiters' Techniques: Constantly Improving to Avoid Detection - National Security Depends on Us to Keep Up". It shares, in detail, the forensic test methodologies utilized by SMT and ultimately the research breakthroughs which gave the labs crystal-clear insight into the counterfeiters specific step-by-step rework process. The presentation includes all forensic work utilized in exposing the "Micro-blast" & "Flat-Lap" counterfeit processes identified at SMT labs during 2011, as well as unpublished novel process threats and refinements identified in 2013 & 2014. It also covers the counterfeit mitigation work that SMT supported with the GAO and Senate Armed Services Committee's investigation into counterfeits within DoD supply chains during the 2011-2012 time period.
Techniques for Reverse Engineering and Functionality Extraction of Mixed-Signal ICs for Security Applications
Authors: Stellari Franco , Lin Chung-Ching , Gignac Lynne , Robertazzi Raphael , Weger Alan , Song Peilin 
Published: December 2020

Abstract
In this paper, we discuss a set of techniques and analysis methodologies for the reverse engineering and functionality extraction of complex mixed-signal ICs with a special focus for security applications. Front and back side reflected light pattern images at different magnifications are used to identify circuit blocks. Time-integrated and time-resolved photon emission data is used to identify gate logic states, sequences of events, and specific functional activity. Backscattered electron and scanning transmission electron images mosaics are used to reverse engineer individual gates and observe local interconnects. Thermal imaging is used to aid in the functional block identification and analog gates analysis. Different advanced methodologies for tool automation, focusing, mapping, and image processing are also discussed in the context of our proposed electro-optical tester based technique.
Root Cause Analysis for Pin Leakage
Authors: Song Zhigang , Nxumalo Jochonia , Villalobos Manuel , Pendyala Sweta 
Published: December 2020

Abstract
Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.