bluuebunny/crossref_metadata_2025_split huggingface dataset:
Spatial Evaluation of Resolution in a Scanning Ultrasonic Microscope. Microassembling Technologies Characterization: Differences Between A-Scan and C-Scan Analysis Modes
Authors: Bechou L. , Ousten Y. , Danto Y. , Leclavé J.-E. , Aude M. 
Published: December 2020

Abstract
The major interest presented by a Scanning Acoustic Microscope (SAM) for microassembling technologies is to characterize system integrity without alteration in internal structures of the different samples. But ultrasonic waves nature, propagation diversity and spatial resolution obtained close to optical one, induce instructive information contained into images. So the interpretation quality images will be directly linked with samples nature, used tool thorough and spatial ultrasonic probe resolution. In this paper, we present first an analytical approach of spatial resolution of SAM. Moreover, we propose calculations about field depth within media. Then, we correlate theoretical results by performing tests on special calibrated samples with two microscopes: commercial one and specific acoustic system developed in IXL Laboratory. In a second time, we characterize few microassembling technologies with two techniques: A-SCAN and C-SCAN analysis modes. Both methods highlight some differences in ability detection of weak defects due to highest interface view (best resolution and contrast) in particular with the C-SCAN mode. In fine, we show typical microassembling technologies analysis and we conclude about the place of SAM in failure control and reliability analysis.
Liquid Metal Embrittlement of Copper Wires
Authors: Brown L. E. 
Published: December 2020

Abstract
Intermittent opens in hand-assembled electronic components have a number of expected causes. In this case the failure mechanism that was identified is of concern in certain industries, but is unexpected in the electronics business. Solder in solder pots and in flow solder systems is expected to become contaminated with the various metals and other materials that the solder contacts during use. In the analysis presented here, the solder was determined to be contaminated with mercury. This contaminated solder caused wires tinned in the solder to fracture due to liquid-metal embrittlement. Liquid-metal embrittlement (LME) is the reduction in metal ductility caused by contact with liquid metal.
Automatic IC Die Positioning in the SEM
Authors: Tan H.W. , Phang J.C.H , Thong J.T.L 
Published: December 2020

Abstract
This paper presents a new automatic die positioning system for failure analysis work in the scanning electron microscope (SEM). The system makes use of machine vision to automatically locate a prespecified failure site on an integrated circuit (IC) sample, without the need for a high-accuracy specimen stage or modifications to existing SEM hardware. Depending on the appearance of the desired failure site, either image registration or feature tracking is used to locate the site. To locate failure sites containing unique and distinguishing features, such as those found on logic ICs, an image registration procedure is used. Experiments carried out on a microprocessor and an analogue-to-digital converter show that the new system is able to accurately locate the failure site, even in the presence of IC sample rotation and image scaling. Moreover, the accuracy of the technique has been shown to be independent of the complexity and minimum feature size of the sample used. To locate failure sites containing repetitive IC patterns, such as those from DRAM samples, a feature tracking approach was incorporated into the original die positioning algorithm. The final system can therefore locate many types of failure sites, regardless of whether they have unique features or repetitive IC patterns.
Spray Cooling for Time Resolved Emission Measurements of ICs
Authors: Goruganthu Rama R. , Bethke David , McBride Shawn , Crawford Tom , Frank Jonathan , Cotton Dan , Cader Tahir 
Published: December 2020

Abstract
Spray cooling is implemented on an engineering tool for Time Resolved Emission measurements using a silicon solid immersion lens to achieve high spatial resolution and for probing high heat flux devices. Thermal performance is characterized using a thermal test vehicle consisting of a 4x3 array of cells each with a heater element and a thermal diode to monitor the temperature within the cell. The flip-chip packaged TTV is operated to achieve uniform heat flux across the die. The temperature distribution across the die is measured on the 4x3 grid of the die for various heat loads up to 180 W with corresponding heat flux of 204 W/cm2. Using water as coolant the maximum temperature differential across the die was about 30 °C while keeping the maximum junction temperature below 95 °C and at a heat flux of 200 W/cm2. Details of the thermal performance of spray cooling system as a function of flow rate, coolant
Failure Analysis of Short Faults on Advanced Wire-Bond and Flip-Chip Packages with Scanning SQUID Microscopy
Authors: Hsiung Steve K. , Tan Kevan V. , Komrowski Andrew J. , Sullivan Daniel J. D. , Gaudestad Jan 
Published: December 2020

Abstract
Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.
Failure Mechanisms of Contact Vias in Organic Light Emitting Diode Displays
Authors: Lowes T.D. , Wu L. , Eden K. , Trujillo J. 
Published: December 2020

Abstract
A new via interconnect failure mode found in organic light emitting diode (OLED) displays has been documented. Physical appearance, electrical performance, response to environmental stresses and root cause analyses have been studied using both simplistic and sophisticated failure analysis tools including focused ion beam etching and time of flight secondary ion mass spectroscopy (TOF-SIMS).
Sampling and Reference Considerations for Very High Resolution AFM Analysis
Authors: Gondran Carolyn F. H. , Michelson Diane K. 
Published: December 2020

Abstract
The geometries of several proposed new electronic device structures put constraints on the size of the AFM images that can be obtained in the gate areas. The images that can be obtained on these structures are of a significantly smaller area, at a much higher resolution, than is typically measured. The analysis areas are limited to ~ one-tenth of what is normally scanned. The micro-roughness and feature size information contained in AFM measurements changes with scan size. Care must be taken when introducing such a dramatic change in the measurements being made. Several factors should be considered to determine an appropriate sampling plan and select a proper reference set for these high-resolution measurements. In this paper, several of these factors are discussed in the context of determining a sampling plan and reference targets for sidewall micro-roughness of fins that allow 50 nm analysis areas.
Application of Innovative Wafer-Sort Test Methods for Effective Fault Isolation
Authors: Goh Ivan A. N. , Miu Kenneth , Zhang Johnny , Ma Harley , Yin Wancy 
Published: December 2020

Abstract
During the wafer-sort stage, critical electrical data on the IC chip performance is collected. As technology advances, smaller geometries are continuously implemented to the production line and, as a result, there may be some issues that are difficult to detect and eliminate at the typical wafer-sort or final-test techniques. This paper presents two successful applications of innovative wafer-sort techniques to solve some difficult issues. In the first case, voltage-stress is implemented in the wafer-sort to draw out yield issues which otherwise go undetected. This additional test component helps to screen-out marginal dies and analyze the post-stress spatial pattern. By applying the MERCAD detection system to localize the fault area and the appropriate delayer techniques, metal microbridge is found. In the second case, wafer-sort collects the testing information for the failing scan chains. This information is mapped to the netlist, schematic, and design layout of the chip. Given this information, together with the design layout, the authors are able to narrow down these issues to some metal pattern defects.
“On Wafer” Design Validation Through Complementary Dual-Side Circuit Editing using FIB
Authors: Thompson Mark A. , Chen Calvin , Tsao Chun-Cheng , Han Ming , Tsai Hun Lian 
Published: December 2020

Abstract
We present, a novel solution to focused ion beam (FIB) circuit edit, performed through the back and front surfaces of the same semiconductor device under test (DUT). This complementary dual-side FIB modification was performed at wafer level test, on a wafer piece, utilizing a coaxial photon-ion focused ion beam system. The DUT was found to have excessive Iddq leakage current due to a fault in a tri-state driver circuit, and was determined that two FIB edits were required to validate the proposed correction. Wafer level editing provides a more flexible approach to access the edit sites. We accessed one site via the front side circuitry of the DUT and the other through the backside silicon. A wafer piece was used for this dual-side edit to demonstrate relatively uncomplicated sample preparation for FIB access, and still allow wafer level probing afterward. The silicon was locally thinned by mechanical means over the specific die for backside FIB editing. Following the backside edit, the front side edit was performed, with minimal sample preparation. The modifications were validated following these edits, where Iddq and emission measurement were nominal.
Failure Analysis of SOI Bipolar Device Using Photon Emission Microscopy
Authors: Simons Todd M. , Davis Bob 
Published: December 2020

Abstract
Photon emission microscopy (PEM) provides a valuable first step in the failure analysis process. An analysis of a mixed signal bipolar/CMOS silicon on insulator (SOI) device revealed an abnormal emission site that appeared to emanate from the oxide isolation ring. Subsequent mechanical probing of the emitting bipolar transistor revealed node voltages nearly identical to a known good reference unit that had no emission site at the affected transistor. This article analyzes the reasons for the emission site on one transistor and not the other even though the node voltages were the same. It was observed that while the node voltages were nearly identical, the available current paths were not. The different paths directly related to the amount of available carriers for recombination in the base. The construction of the SOI device creates unique optical paths for emission sites not observed in non-SOI devices. It can be concluded that the failure mechanism does not always reside at the abnormal PEM site.
Failure Analysis of Broken Stitch Bonds in TSSOP Packages Using Scanning Acoustic Microscopy (SAM) and Time Domain Reflectometry (TDR)
Authors: Abd-AlRahman Bilal , Lewis Corey , Simons Todd 
Published: December 2020

Abstract
A failure analysis application utilizing scanning acoustic microscopy (SAM) and time domain reflectometry (TDR) for failure analysis has been developed to isolate broken stitch bonds in thin shrink small outline package (TSSOP) devices. Open circuit failures have occurred in this package due to excessive bending of the leads during assembly. The tools and their specific application to this technique as well as the limitations of C-SAM, TDR and radiographic analyses are discussed. By coupling C-SAM and TDR, a failure analyst can confidently determine whether the cause of an open circuit in a TSSOP package is located at the stitch bond. The root cause of the failure was determined to be abnormal mechanical stress placed on the pins during the lead forming operation. While C-SAM and TDR had proven useful in the analysis of TSSOP packages, it can potentially be expanded to other wire-bonded packages.
Red Phosphorous Induced Shorts in Plastic Packages
Authors: Huerta Rafael , Wu Nevil 
Published: December 2020

Abstract
Red phosphorous is one of the inorganic phosphorous compounds used as a flame retardant in microelectronic applications. One of the concerns is a red phosphorus induced pin-to-pin short in the molding compound. This paper discusses the red phosphorous-induced shorts in a 100 Lead TQFP (14x20x1.4mm) plastic package. The devices first failed on boards in the field. After de-soldering them from the boards, the devices were tested and found to have resistive pin-to-pin shorts. Common failure analysis techniques, including parallel lapping, cross sectioning, and X-ray, failed to reveal the resistive shorts and the shorting mechanism. Removing the molding compound by means of a wet chemical etching method using sulfuric acid on a hot plate worked very well and enabled to expose particles in three dimensions. It was concluded that the resistive shorts were not necessarily due to a single large phosphorous particle, but due to small and fragmented pieces of phosphorous.
Temperature and Humidity Dependent Reliability Analysis of RGB LED Chips
Authors: Fu Jun-Xian , Souri Shukri , Harris James S. 
Published: December 2020

Abstract
Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.
Laser Based Analysis on Analog Circuits with Feedback Loops and a Case Study
Authors: Zhang Fubin , Maxwell David 
Published: December 2020

Abstract
Based on the understanding of laser based techniques’ physics theory and the topology/structure of analog circuit systems with feedback loops, the propagation of laser induced voltage/current alteration inside the analog IC is evaluated. A setup connection scheme is proposed to monitor this voltage/current alteration to achieve a better success rate in finding the fail site or defect. Finally, a case of successful isolation of a high resistance via on an analog device is presented.
The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage
Authors: Li Tsung-Te , Wu Chao-Chi , Chuang Jung-Hsiang , Lee Jon C. 
Published: December 2020

Abstract
This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.
Rapid Yield Learning with Effective Integration of FMEA design for DOE on Test Chip
Authors: Goh Ivan A. N. , McMullan Russell , Fairchild Brock , Ilzhoefer John 
Published: December 2020

Abstract
As semiconductor technology advances from one node to the next, fabrication also becomes increasingly challenging to ramp up production with the most desirable yield and reliable product in a timely manner. At an advanced technology node such as 65nm, the interaction between product design, process margin, and process equipment continues to limit the product yield and reliability performance. Traditional methods, which usually rely on sequential feedback of each experimental lot, require too many learning cycles to achieve target performance, yield, and reliability levels. This paper describes a methodology that potentially accelerates the progression of identifying process and product-design interactions and marginalities during the development stage. It demonstrates the successful application of a failure mode effect analysis design design-of-experiments reticle for extracting process-design interaction information. This approach provides insights to early learning cycles in achieving accelerated critical learning for yield and reliability improvements.
Techniques for Analyzing Solder Joint Properties and Damages in FBGA Packages
Authors: Leinert S. , Jansen S. , Martin N. , Breuer D. , Werner W. 
Published: December 2020

Abstract
The demand for shifting from lead-containing to lead-free solder materials as well as the ongoing efforts for an improvement of the solder joint robustness for fine-pitch ball grid array packages requires ongoing testing of fresh solder alloys, changes in landing pad metallization and reflow processes. This testing includes mechanical and thermal stress tests and a detailed failure and material analysis. Besides the commonly used analysis methods like optical microscopy, scanning electron microscope (SEM) imaging of cross sections, fracture planes and energy dispersive X-ray compositional analyses, other techniques such as ion channeling contrast and transmission electron microscope (TEM) imaging can provide valuable information on intermetallic compounds (IMC) formation at solder joint interfaces. This paper discusses the advantages of SEM imaging of IMC morphology at the pad interface resulting from solder ball etching, focused ion beam imaging of solder ball cross sections with ion channeling contrast, and TEM analyses of failures.
Failure Localization & Design Debug on Mixed-Mode ICs by Using the Dynamic Laser Stimulation Techniques
Authors: Sienkiewicz Magdalena , Sanchez Kevin , Firiti Abdellatif , Crepel Olivier , Perdu Philippe , Lewis Dean 
Published: December 2020

Abstract
Soft defect localization techniques based on laser stimulation have become key techniques for a wide range of FA/debug issues. In this paper, we demonstrate the ability of these techniques to solve critical design issue in mixed-mode device for automotive application which includes analog, logic, RF and power. Utilizing a wide range of laser stimulation techniques, we have determined the most efficient approach for this device to achieve the shortest cycle time. We have established a clear link between fault isolation by laser stimulation techniques and the abnormal behavior of the device with relevant and complete simulation at transistor level.
Real-Time FTIR Etch Depth Measurements in Passive Integrated Silicon Substrates
Authors: Roullier F. , Domengès B. , Poirier P. , Blanvillain J.P. 
Published: December 2020

Abstract
This paper deals with real-time FTIR (Fourier Transform Infrared Reflectometry) etch depth measurements performed on passive integrated silicon substrates. High-density trench capacitors are non-destructively characterized using an FTIR Michelson type spectrometer. Based on effective medium approximations, an effective index associated to the capacitor layer is introduced which allows a good evaluation of the capacitor hole depth. Obtained results correlate well with those from SEM (Scanning Electron Microscopy) measurements performed on cross-sections, on a range going from 12µm to 30µm depth.
Failure Analysis of Multi-Fingered HV Symmetric Devices for Charge-Pumping Circuit Applications
Authors: Wen Liang-Feng , Wang Ting-Chien , Chen Chien-Hui 
Published: December 2020

Abstract
The purpose of this paper is to present a systematic analysis methodology for a newly taped-out High Voltage (HV) product that has encountered a 0% yield issue. In order to identify the root cause and improve the yield, a series of electrical analysis experiments designed to reveal the failure phenomenon of the charge-pumping circuit were applied. Combining spice simulation data, I-V curve measurements, CAFM measurements and nano probing, the difference in resistance for a multi-fingered symmetric device was revealed. A deductive method was then used to conduct layout analysis, and an in-line split experiment was developed to explain the failure phenomenon experienced by the multi-fingered HV symmetric device for a charge-pumping circuit.
Analysis of Bridge Failure between PPG and LPP in Fin Cell Transistor
Authors: Lee Jungho , Chung Sung-Woong , Park Seung Pyo , Chang Myung Sick , Lee Jung Hoon , Hong Sung-Joo 
Published: December 2020

Abstract
As a promising candidate for DRAM scaling beyond 40nm technology, the fin cell transistor (FCT) utilizing p-type poly silicon gate (PPG) was proposed. However FCT makes a lot of bridge failure between word-line and landing-plug poly (LPP) connecting source and drain regions in a cell transistor. But this bridge point is so insignificant that the failure was hardly detected by existing read modify write (RMW) pattern. We analyzed this failure with a particular test method. It mostly has been observed to single and odd parity address. We found out that when adjacent gate is active for reading its cell, only the forward bias can run into the LPP with n-type poly-silicon, and low status data would be taken high level turn unlike recess cell array transistor utilizing n-type poly silicon gate (RCAT-NPG) which both high and low status would be reversed.
Subsurface Imaging of Multi-Level Integrated Circuits Using Scanning Electron Acoustic Microscopy
Authors: Meng L. , Phang J.C.H. , Street A.G. 
Published: December 2020

Abstract
The capability of the Scanning Electron Acoustic Microscopy (SEAM) technique for high resolution non-destructive subsurface imaging at different depths for a multi-level integrated circuit is assessed. Experimental results using a beveled DRAM IC sample are used to quantify the effect of the electron beam energy and modulation frequency on contrast, spatial resolution and depth of focus of SEAM amplitude and phase images.
Deterministic Polishing Applications in Failure Analysis
Authors: Kimball Mark 
Published: December 2020

Abstract
Development of a reliable mechanical decapsulation procedure for an IC process incorporating Cu and organic passivation layers resulted in a better understanding of the polishing process. The improved polishing technique --Deterministic Polishing-- is an adaptation of an advanced polishing technology employed by the optics industry to fabricate highly accurate optical elements. These results can be applied to a broad class of polishing applications.