bluuebunny/crossref_metadata_2025_split huggingface dataset:
Ausentismo escolar en estudiantes asmáticos de una institución educativa de la ciudad de Cali
Authors: Cruz Mosquera Freiser Eceomo , Arango Arango Ana cristina , Gallon Figueroa Ana Lucia , Yela Benavidez Ana Marìa , Franco Castrillón Lorena , Avila Ovalle Ivon , Banguera Montaño Edwar Antonio , Lozano Gomez Katherine , Jimenez Duran Diana Patricia , Moreno Reyes Sandra Patricia 
Published: December 2020

Introducción: El asma como una enfermedad crónica inflamatoria de las vías aéreas que se caracteriza por sibilancias, dificultad respiratoria, opresión torácica y tos, la cual se da principalmente en la noche o en las primeras horas de la mañana. A pesar de los avances diagnósticos y terapéuticos, la prevalencia de esta patología a nivel mundial sigue en aumento, afectando principalmente la población infantil y adolescente, en las que genera limitaciones en la actividad física diaria, interferencias en el sueño, ausencias a las jornadas escolares y bajo rendimiento académico. El objetivo del presente estudio fue determinar la frecuencia de ausentismo escolar en estudiantes asmáticos de una institución educativa de la ciudad de Cali.
Metodología: Un total de 385 estudiantes de 5 a 14 años fueron incluidos en el estudio, a los cuales se les suministro el cuestionario ISAAC, los cuales fueron diligenciados por los cuidadores. A partir de los datos obtenidos se realizó el análisis estadístico en el paquete SPSS versión 20.
Resultados: La prevalencia de asma encontrada fue del 27%, con relación el ausentismo en este grupo de estudiantes se evidenció que en total 776 días de clases se habían perdido durante el año, con un promedio de 7.5 días (DE +/- 7) por estudiante. El 45% faltó de 1-5 veces y un 6% más de 20 veces.
Conclusiones: A partir de los hallazgos se concluye que el asma una enfermedad que puede traer claras repercusiones a nivel escolar.
Favorable outcome of SARS-CoV-2 infection in a patient with pituitary insufficiency
Authors: Fux Otta Carolina , Moreno Laura , Vitaloni Roberto , Iraci Gabriel S 
Published: December 2020

Background: Severe Acute Respiratory Syndrome Coronavirus 2 (SARS-CoV-2) outbreak originated in Wuhan (China) rapidly turned into a pandemic. Due to a national compulsive decree of quarantine, office visits for chronic disease control were delay.
Hypopituitarism includes all clinical conditions that result in partial or complete failure of the pituitary gland's ability to secrete hormones. Pituitary insufficiency per se has been associated with an increase in both morbidity and mortality, particularly due to cardiovascular disease, which is an important risk factor for COVID-19 disease severity.
Objective: To report the first case of SARS-CoV-2 infection in a patient with hypopituitarism, discuss the implications of the treatments the patient was taking and grade up the value of telemedicine in the present scenario.
Methods: Report of the clinical record of a patient with hypopituitarism and infection with SARS-CoV-2.
Results: During the span of the infection, the patient remained on the same hormonal therapeutic scheme (thyroid, gonadal and adrenal axis). The dose of hydrocortisone was not changed during the course of the infection as she was asymptomatic. We use telemedicine to control and advise her on the treatment.
Conclusion: Health care professionals should carefully follow up on the evolution of patients with hypopituitarism to provide them a safer outcome. The use of telemedicine as a methodology for selected patients acquires relevance in the present epidemiological context.
Failure Analysis of a Half-Micron CMOS IC Technology
Authors: Liang A.Y. , Tangyunyong P. , Bennett R.S. , Flores R.S. , Soden J.M. , Cole E.I. 
Published: December 2020

Abstract
We present the results of recent failure analysis of an advanced, 0.5 um, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.
TEM Sample Preparation Using A Focused Ion Beam and A Probe Manipulator
Authors: Herlinger L.R. , Chevacharoenkul S. , Erwin D.C. 
Published: December 2020

Abstract
Cross-sectioning is a necessary technique for the failure analysis of integrated circuits. Historically, the majority of samples have been prepared for scanning electron microscope (SEM) analysis. Today's smaller geometry devices, however, increasingly require the improved spatial resolution afforded by the transmission electron microscope (TEM), both in imaging analysis and in elemental analysis. Specific-area cross-section TEM (SAXTEM) analysis allows the failure analyst to identify defects that may go undiscovered in the SEM. A procedure is described for a timely preparation of SAXTEM samples using a focused ion beam (FIB) instrument and a manipulator probe. This procedure extends the state-of-the-art in several key respects: A) no mechanical grinding is necessary, B) samples as large as the FIB chamber can be accommodated, e.g., whole wafers, C) multiple samples can be prepared from one die, D) the procedure is faster and more repeatable than previously reported procedures.
Temperature Dependence of Quiescent Currents as a Defect Prognosticator and Evaluation Tool
Authors: Seo J.S. , Lee S.S. , Daniel S. , Yoon C.K. 
Published: December 2020

Abstract
The dependence of a defective device's voltage-current characteristics on temperature is studied, both from a theoretical perspective and through a series of actual case studies. The shape of the current vs. temperature curve is shown to be a good prognosticator of the defect type, and as such a valuable complement to other non-destructive defect characterization techniques such as photoemission spectrum analysis [1].
A New Robust Backside Flip-Chip Probing Methodology
Authors: Ullmann P.F. , Talbot C.G. , Lee R.A. , Orjuela C. , Nicholson R. 
Published: December 2020

Abstract
The increasing popularity of flip-chips brings new challenges to those who must perform device analysis (1). Its ability to accommodate high pin-count and high bandwidth microprocessors, DSPs and complex logic devices is increasing the demand for this technology. Conventional e-beam and mechanical probing techniques currently allow quick and efficient analysis of conventional semiconductor devices. When the surface of the device is not exposed, however, conventional analysis techniques are insufficient and new techniques must be developed. Conventional packaging technologies allow design debug and failure analysis to be performed in a relatively straightforward manner. Analysis from the topside is clearly the preferred technique when possible (2), using specially prepared engineering prototypes, but backside access for dynamic timing analysis is required when topside techniques are exhausted. The flipchip process, however, makes topside analysis impractical in most situations. There are several different techniques that are currently being used for backside analysis. These are emission microscopy (3), optical beam induced current (OBIC) (4), and a combination of software and built in self-test/scan methods (5). These techniques are valuable in helping engineers to analyze and isolate faults for functional failures. These techniques do not, however, provide precise analog waveforms which may be used to perform timing analysis on the device. A backside pulsed laser electro-optic technique for measuring internal node timing (6) has been developed for waveform acquisition. Although this technique permits acquisition of waveforms from a bi-polar device which has had its substrate thinned, it has limited application to CMOS devices, particularly in long duty cycle applications. Milling the backside of devices in order to facilitate backside waveform acquisition is considered by some researchers as a potential approach, but the authors are not aware of any published data on this subject.
Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage
Authors: De Wolf I. , Groeseneken G. , Maes H.E. , Bolt M. , Barla K. , Reader A. , McNally P.J. 
Published: December 2020

Abstract
It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.
Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification
Authors: de Luna J. N. C. , del Fierro M. O. , Muñoz J. L. 
Published: December 2020

Abstract
An advanced flash bootblock device was exceeding current leakage specifications on certain pins. Physical analysis showed pinholes on the gate oxide of the n-channel transistor at the input buffer circuit of the affected pins. The fallout contributed ~1% to factory yield loss and was suspected to be caused by electrostatic discharge or ESD somewhere in the assembly and test process. Root cause investigation narrowed down the source to a charged core picker inside the automated test equipment handlers. By using an electromagnetic interference (EMI) locator, we were able to observe in real-time the high amplitude electromagnetic pulse created by this ESD event. Installing air ionizers inside the testers solved the problem.
Automatic Determination of Optimal FIB Operations for Improved Circuit Probing and Fast Reconfiguration
Authors: Desplats Romain , Dargnies Timothee , Courrege Jean-Christophe , Perdu Philippe , Noullet Jean-Louis 
Published: December 2020

Abstract
Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.
Microscopy at the Nanoscale
Authors: Vanderlinde William E. , Ballarotto Vincent W. 
Published: December 2020

Abstract
Nanoscale devices such as carbon nanotubes, fluorescent nanoparticles, and molecular conductors serve as a benchmark for the tools and techniques that will be required in the future to analyze processing defects and determine the cause of electronic device failures. In this paper, the authors compare and contrast the nanoscale capabilities of several imaging techniques, including STEM-in-SEM, forward scattered electron imaging, photoelectron emission microscopy, and atomic force microscopy. Along with the results of the various characterization techniques, the paper also includes a survey of the more common nanoscale devices, showing that many require more than one imaging method to make a complete and accurate assessment.
Towards High Accuracy Fault Diagnosis of Digital Circuits
Authors: Hora Camelia , Eichenberger Stefan 
Published: December 2020

Abstract
Due to the development of smaller and denser manufacturing processes most of the hardware localization techniques cannot keep up satisfactorily with the technology trend. There is an increased need in precise and accurate software based diagnosis tools to help identify the fault location. This paper describes the software based fault diagnosis method used within Philips, focusing on the features developed to increase its accuracy.
Hardware Results Demonstrating Defect Localization Using Power Supply Signal Measurements
Authors: Acharyya Dhruva , Plusquellic Jim 
Published: December 2020

Abstract
The power supply transient/quiescent signal (IDDT/IDDQ) methods that we propose for defect localization analyze regional signal variations introduced by defects at a set of power supply ports on the chip under test (CUT). The methods are based on the comparison of the CUT with a golden reference chip, either simulated or determined to be defect-free, with the objective of distinguishing anomalous signal behavior introduced by a defect from that introduced by process variations. However, variations in contact resistance between the probe card and the CUT introduces anomalies in the measured power supply signals that complicates the task of comparing data between chips. This paper presents hardware results that demonstrate the effectiveness of a previously developed calibration technique designed to eliminate these types of signal anomalies introduced by the testing environment. The CUT hardware data presented in this work is calibrated using simulations of the CUT’s power grid and special on-chip sources of stimuli called ‘calibration circuits’. Several novel Look-Up Table based defect localization techniques are proposed that analyze the calibrated power supplies signals. The results of predicting the locations of emulated defects in nine copies of a test chip demonstrate the effectiveness of the techniques.
Extracting Acoustic Signatures of Solder Bump Defects Using Wavelet Power Spectra and Their Classification Using Normalized Cross-Correlation
Authors: Ramanujachar K. 
Published: December 2020

Abstract
In a previous contribution we highlighted the potential use of spectral analysis of acoustic signals reflected from solder bumps as a means to identify anomalies in the bump. With numerous interfaces in contemporary solder bump geometries, time domain interpretation of acoustic signals is not straightforward. Frequency domain analysis is hence another route to utilizing information contained about defects in acoustic signals emanating from suspect bumps. In this contribution we highlight the use of Wavelet transforms and power spectra in analyzing acoustic signals and demonstrate with a few examples how the transform may be used to obtain unique finger prints of anomalies. We also discuss how cross correlation technqiues may be used to classify a fingerprint once a comprehensive library of finger prints is empirically constructed.
Reliability of Polycrystalline MEMS: Prediction of the Debugging-Time
Authors: Millet O. , Bertrand P. , Legrand B. , Buchaillot L. , Collard D. 
Published: December 2020

Abstract
The debugging-time for polycrystalline MEMS structural layers is the aim of this paper. A description of the fatigue phenomenon for elementary structure in the case of microactuators is presented. It is obtained by combining elementary in situ test benches of varying dimensions and cyclic actuation; in the same way, the debugging-time is determined according to the design and the structural material. Test benches have been developed allowing performance of bending fatigue tests of polycrystalline structural layers, describing the fatigue phenomenon and obtaining a constant debugging-time for a same polycrystalline layer, whatever the excitation frequency and the beams length.
Characterization of VCSEL-Array Degradation Induced by Elevated Temperature and Humidity
Authors: Lopez L. D. , McElfresh D. K. , Melanson R. , Vacar D. 
Published: December 2020

Abstract
The need for high bandwidth, high speed interconnects with optimum routing through computer backplanes has led to the use of optical interconnects in multiprocessor computing systems [1]. Most of the current commercially available optical interfaces are based upon 850nm vertical-cavity surface-emitting lasers (VCSELs). Extensive studies conducted by the VCSEL manufacturers show that the reliability of these devices continues to improve [2-4]. In order to understand the risks and implications of using VCSELbased modules in computer systems, we have conducted an experiment designed to provide insight into the emission degradation and failure of VCSEL devices. In this paper we briefly describe the experiment and review the results of the subsequent failure analysis on degraded VCSEL arrays.
FiberQA-AVIT System for Fiber Endface Inspection
Authors: Roche Brian , Duffy John , Mitcheltree Thomas , Wilson Douglas , Lootsma Wayne , Lewandowski Mike , Trotabas Rémy 
Published: December 2020

Abstract
This paper discusses the requirements, challenges, and capabilities of a fully automated visual inspection tool (AVIT) designed to improve the evaluation of fiber optic endfaces. The FiberQA™-AVIT system is based on the FiberQA™-EFI (Endface Inspection) software from PVI Systems, Inc.
A Novel FIB Method to Prepare TEM Samples for 3D Observation
Authors: Mcllwrath Kevin , Wang Nathan 
Published: December 2020

Abstract
This article describes a novel way to prepare TEM samples from existing FIB lift out samples for third dimensional observation. An in situ needle in a FIB column is applied to handle the sample and a special sample holder is used that tilts the sample rapidly to 90º in the FIB column. The application of this technique is also discussed.
Ion Beam Polishing for Embedded Cross-Sections and Its Advantages for FESEM Analysis in Electronic Packaging
Authors: Mack W. , Seidl B. , Fischer R. , Ort T. , Walter J. , Grünewald J. , Berthold L. , Petzold M. 
Published: December 2020

Abstract
Microstructural diagnostics for electronic packaging development and failure analysis under industrial manufacturing conditions require fast but reliable preparation routines which result in samples of high quality without preparation artefacts. The aim of the presented paper is to introduce a time- and cost efficient ion beam-based preparation procedure for high resolution Field Emission- Scanning Electron Microscopy (FESEM) analysis for packaging components. In particular, the considerable advantages of the proposed method compared to standard metallographic approaches will be demonstrated by discussing results of typical failure analysis examples as a function of the preparation procedure.
An Effective Failure Analysis Strategy for the Successful Introduction of New Products Designed in 90 and 65 nm CMOS Technologies
Authors: Lorut F. , Lamy M. , de la Bardonnie M. , Fabre S. , Ross R. , Ly K. , Wyon C. 
Published: December 2020

Abstract
IC manufacturers, among other things, have to define a global failure analysis (FA) strategy that is best adopted to the challenges associated to the introduction of the 90 and 65 nm CMOS technologies. This article reviews the existing FA techniques and then describes an FA strategy that is aiming at fast, efficient, and economic learning in the latest 120-65 nm CMOS technologies. The strategy is based on a well-balanced mix and usage of in-line defectivity data, voltage contrast analyses, SRAM bitmap analysis results, OBIRCH fault isolation, and various advanced physical characterization techniques. A SRAM bitmap strategy has demonstrated to be very effective in driving most relevant process improvements, and also OBIRCH applied to parametric test structures has helped significantly in identifying major yield detractors.
Three Dimensional Imaging of Microelectronic Devices Using a CrossBeam FIB
Authors: Lifshin Eric , Evertsen James , Principe Edward , Friel John 
Published: December 2020

Abstract
Increased insight into the internal structure of microelectronic devices can be achieved through the use of three dimensional (3D) imaging based on image stacks of serial sections obtained with a combined electron and ion beam (CrossBeam) FIB. This study describes how such data can be collected and presented, some of the factors that need to be optimized to get the best images, and the limitations of the method. It can be viewed as a first step in the emerging area of high resolution 3D microscopy, a technique that can lead to more accurate characterization of the shapes of internal structures and their interconnectivity at the nanoscale.
Materials Characterization and Model of PCB Thermal Expansion for Laminates With Various Copper Densities and Thicknesses
Authors: Cunningham William J. , Casali Dick , Armendariz Norman J. 
Published: December 2020

Abstract
The SEMATECH/SEMI roadmap forecasts increased density requirements for printed circuit board manufacturing to accommodate smaller form factor interconnects, increased pin counts, and routing densities on a range of PCB sizes and thicknesses. As a result, the effect of materials. thermal expansion properties may further impact the structural or physical integrity and subsequent electrical properties for high speed and thermal management requirements. This study demonstrated that various sample coupons selected from PCB boards with different amounts of copper showed a corresponding coefficient of thermal expansion (CTE) correlation in the Z-axis (CTEZ) and can be modeled using a constitutive equation. Moreover, samples were further evaluated from the effect of increasing temperature and showed that the CTE indeed affects copper-interconnect physical structures such as copper vias and barrels in terms of elongation or strain.
OBIRCH Driven Failure Analysis for Process Development of 120 nm to 65 nm Technology Nodes
Authors: Ross R. , Ly K. , de la Bardonnie M. , Kwakman L.F.Tz. , Lorut F. , Lamy M. , Wyon C. 
Published: December 2020

Abstract
Given the ever increasing complexity of conducting failure analysis on today's latest generation manufacturing processes, the authors have investigated and implemented OBIRCH techniques into process development failure analysis practices. They describe their applications of OBIRCH to 120, 90, and 65 nm samples and their methods for interpreting the results. The OBIRCH technique has the ability to address faults within most structure types and quickly give information on a number of failing sites. It has proven itself as a necessary tool for failure analysis at advanced technology nodes, where fault characterization is getting difficult due to extremely small critical dimensions. The results obtained using the OBIRCH tool have been excellent on 120nm and initial 90nm results. The authors have not yet analyzed enough 65nm samples to form any type of conclusion regarding the tools ability at this technology node.