Amorphous Si-Zn-Sn-O/Si-in-Zn-O Bilayer Transistors with P(VDF-TrFE) for Synaptic Integration in Neuromorphic Systems
Authors: Maurya Sandeep Kumar , Kim Hyeondong , Lee Sang Yeol 
Published: December 2024

Synaptic devices, such as memristors and transistors, are at the forefront of neuromorphic computing, designed to replicate the complex functions of the human brain. Unlike traditional computing systems (von Neumann architecture) that rely on the sequential processing, these synaptic devices excel in performing highly efficient parallel computations. This makes them particularly well-suited for tasks that require vast amounts of data processing, similar to how the brain processes information. Field-effect transistors (FETs), in particular, offer significant advantages in emulating synaptic behaviour. Their versatility in material selection, coupled with the ability to fine-tune parameters, makes them ideal for creating devices that mimic synaptic functions. Moreover, the established working principles of FETs provide a reliable foundation for developing sophisticated neuromorphic systems, pushing the boundaries of what's possible in next-generation computing.
Our previous work on bilayer (SZTO/SIZO) thin-film transistors demonstrated remarkable high field-effect mobility exceeding 30 cm²V⁻¹s⁻¹, coupled with excellent stability under thermal stress, negative gate bias, and positive gate bias stress. These enhancements in performance and stability suggest significant potential for achieving high-performance artificial intelligence (AI) synaptic devices. Therefore, in this study, we present an AI synaptic device based on a bilayer thin-film transistor. The device features an amorphous SiZnSnO/SiInZnO (SZTO/SIZO) channel layer combined with a flexible copolymer, poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)), serving as the gate insulator. The complete device structure includes Al/Ti/P(VDF-TrFE)/ZrO₂/SZTO/SIZO/substrate, with a channel width of 250 µm and a length of 50 µm. The transfer curve of the bilayer-based synaptic devices exhibits counterclockwise hysteresis during gate voltage sweeps of ±30 V, ±20 V, ±10 V, and ±5 V, indicating the presence of a ferroelectric layer as the gate insulator as shown in Figure 1. A memory window greater than 15 V was observed during sweeps from -30 to 30 V, with a saturation current exceeding 10 µA at 30 V.
Postsynaptic currents (PSCs) were measured using 50 potentiation and 50 depression input pulses of ±10 V. The resulting maximum conductance exceeded 175 nS, derived from the relationship between the presynaptic gate voltage and the postsynaptic drain current. A neural network simulation was conducted using "MLP NeuroSim+ V3.0" software to model a multilayer perceptron (MLP) with 400 input neurons, 100 hidden neurons, and 10 output neurons, connected by artificial synapses. The model was trained on handwritten digit data from the Modified National Institute of Standards and Technology (MNIST) database and achieved a recognition accuracy of over 75% for the digits. Further enhancements in the ferroelectric layer and a deeper understanding of the gate insulator-channel interface could lead to even more advanced synaptic devices in the future.

Figure 1