bluuebunny/crossref_metadata_2025_split huggingface dataset:
Effect of erector spinae plane block for rib fractures on postoperative analgesia for elbow surgery: A case report
Authors: Bhattarai Prajjwal Raj , Sharma Achyut , Sharma Rinku , Sharma Apurb 
Published: December 2020

The erector spinae plane block is an emerging technique for analgesia. It has shown to provide reliable analgesia in abdominal and thoracic surgery. Erector spinae plane block may be efficacious for analgesia of pain in the upper limb. The advantage of this modality would be in a patient with polytrauma with rib fractures and upper limb fracture/injury as it assists in the physiotherapy of the chest and upper limb.
Intestinal Malrotation in Children: Experience of a Tertiary Care Hospital in a Developing Country
Authors: Emeka Chukwubuike Kevin 
Published: December 2020

Background and Objectives: Intestinal malrotation is a congenital disorder resulting from abnormal rotation of the intestine during fetal development. The aim of this study was to evaluate our experience in the management of pediatric patients with intestinal malrotation.
Material and Methods: This was a retrospective study of children aged 3 years and below who were treated for intestinal malrotation between January 2014 and December 2018 at the pediatric surgery unit of Enugu State University Teaching Hospital (ESUTH) Enugu, Nigeria.
Results: Sixty-one patients had laparotomy for intestinal malrotation during the study period. There was predominance of male neonates and the age range was 10 days to 3 years. Abdominal pain and upper gastrointestinal tract contrast study were the most common symptom and investigation respectively. Intestinal obstruction caused by congenital (Ladd’s) bands was the most common intraoperative finding and Ladd’s procedure was the most performed surgical procedure. Most patients did not develop any post-operative complications. However, surgical site infection was the most common complication following surgery. Mortality occurred in 8 (13.1%) patients.
Conclusion: Intestinal malrotation symptoms occur mainly in male neonates and abdominal pain is a common and consistent symptom. Upper gastrointestinal contrast study is diagnostic. There are morbidity and mortality associated with treatment of intestinal malrotation.
Immunity and Mental Health: Towards COVID-19
Authors: Malhotra Varun , Bharshankar Rajay , Mukherjee Sukesh , Gupta Akriti , Gautam Namita 
Published: December 2020

Introduction: The Corona virus that originated in China in December 2019, has now spread rapidly globally. It is highly contagious & to date no cure in form of vaccine or medicines is available.
COVID-19 and Immunity: Enhancing body’s natural defense system plays an important role in maintaining optimum health. The serum levels of IL2R and IL-6 in patients with COVID-19 are positively correlated with the severity of the disease . studies have found that, compared with COVID-19 patients from general wards, patients in the intensive care unit [ICU] display increased serum levels of granulocyte colony-stimulating factor, IP-10, MCP-1, macrophage inflammatory protein-1A, and TNF-α.
COVID-19 and Mental Health: Patients who had positive COVID-19 diagnosis reported significantly elevated levels of corona virus anxiety compared to their non-infected, but anxious peers, this highlights the clinical utility of the Corona Anxiety Scores [CAS]&the importance of assessing, treating the psychological needs of those infected with the virus. The need to formulate psychological interventions to improve mental health and psychological resilience during COVID-19 pandemic is the need of the hour. We need to tackle and fight the stigma, fear &anxiety related to the virus that is greater than the disease itself. Governments have provided mental health services to their citizens by varied channel including hotline, online consultation & course and outpatient consultation, but have indicated that more attention should be paid to depression and anxiety. As India’s cases increase, the importance of following the government laid precautions becomes all the more important.
Synods and Synodality in Austrian Church after the Second Vatican Council
Authors: Rees Wilhelm 
Published: December 2020

Synods have a long tradition in the ecclesiastical history, though their significance varied in different epochs of the Roman Catholic Church. Within the European area, synods gained in importance after the Second Vatican Council, although they appeared in a new or rather modified form. This also applies to the diocesan synods and the Austrian Synodal Process (1973/1974), which took place after and has been celebrated by the supporters of the Second Vatican Council.
Swiss Synodality after the Second Vatican Council
Authors: Loretan-Saladin Adrian 
Published: December 2020

Quod omnes tangit, ab omnibus tractari et approbari debent. (Cardinal Congar) The canonists have been developing the rule of law of Western Europe. After there had been much debate (Acts 15:7), they decided together with the Holy Spirit. The Apostolic Nuncio gave the permission for lay persons (including women) to participate at the Synod. Synod ’72 is a process involving seven synods of local Churches in Switzerland. As an instrument of “processing” Vatican II, Synod ’72 discussed implementation options like Ecclesiastical Offices of the local Church. (LG 33; Paul VI’s Ministeria quaedam; John Paul II’s Christifedles laici; c. 228 CIC 1983). The tradition of shared decision-making of the baptised was been activated.
Plenary Council in the Czech Republic (1997—2005)
Authors: Menke Monika 
Published: December 2020

This article analyses the preparation, process and conclusions of the Plenary Council of the Catholic Church in the Czech Republic held in 1997—2005. The Plenary Council was one of the few manifestations of the collegiality of the Czech Church, because the diocesan synods are not used here as a tool. The Decree on convocation of the Assembly was announced by the Czech and Moravian bishops on 5 July 1997 in Velehrad. The council was also an opportunity for priests and laity in the country to realise their responsibility for the Church and the co-responsibility of the Church for the condition of society. The Council had a preparatory phase (1997—2003), a stage of the 1st Session (July 2003), and a second phase of the Session (July 2005) where the project was completed and followed by the process of post-conciliar steps. Three final messages were the immediate output from the Second Plenary Session: the Message of the Council to the Public; the Message of the Council to the Believers of the Catholic Church and the Message of the Council to Christians in the Czech Republic. The resulting document was published in 2007 under the title The Life and Mission of Christians in the Church and the World. It was a document of a pastoral nature, in no way of a normative nature (no rules were actually adopted despite the work of the commission and the proposals). The Czech situation is described as “post-Christian missionary territory” there and — estimated the course of the conciliar process and of the Council itself — as an introduction of more intensive implementation of synodality in the Czech Church.
Charismatic Renewal in the Documents of the Episcopal Commissions for Theology around the World]. Eds. Salamon, J. A. Liberadzka, M. Sowińska. Cieszyn: Wydawnictwo Zacheusz, 2019, 334 pp.
Authors: Sawa Przemysław 
Published: December 2020

Wiosna Kościoła. Odnowa Charyzmatyczna w dokumentach episkopatów i komisji teologicznych różnych krajów świata [Spring of the Church.Charismatic Renewal in the Documents of the Episcopal Commissions for Theology around the World]. Eds. Salamon, J. A. Liberadzka, M. Sowińska. Cieszyn: Wydawnictwo Zacheusz, 2019, 334 pp. - the review.
„A chłopaki w brecht” — komentarz do Bibliografii przekładów literatury polskiej w Czechach w 2018 roku
Authors: Derdowska Joanna 
Published: December 2020

The bibliography of Polish literature translated into Czech in 2018 is characterized by a tendency to publish popular and commercially attractive titles: genre fiction and literature for children. The author is concerned with sample passages from Ziemowit Szczerek’s translations of prose published in the A2 literary magazine and discusses possible consequences for the target language of the euphemisation of slang and vulgarisms in the translation of gonzo journalism texts.
X-Ray Nanotomography (XRMT) Tool for Non-Destructive High-Resolution Imaging of ICs
Authors: Yun Wenbing , Wang Steve , Scott David , Nill Kenneth W. , Haddad Waleed S. 
Published: December 2020

Abstract
A high-resolution table-sized x-ray nanotomography (XRMT) tool has been constructed that shows the promise of nondestructively imaging the internal structure of a full IC stack with a spatial resolution better than 100 nm. Such a tool can be used to detect, localize, and characterize buried defects in the IC. By collecting a set of X-ray projections through the full IC (which may include tens of micrometers of silicon substrate and several layers of Cu interconnects) and applying tomographic reconstruction algorithms to these projections, a 3D volumetric reconstruction can be obtained, and analyzed for defects using 3D visualization software. XRMT is a powerful technique that will find use in failure analysis and IC process development, and may facilitate or supplant investigations using SEM, TEM, and FIB tools, which generally require destructive sample preparation and a vacuum environment.
Evaluation of Alternative Preparation Methods for Failure Analysis at Modern Chip and Package Technologies
Authors: Dübotzky A. , Krüger B. 
Published: December 2020

Abstract
We evaluated laser ablation and sandblasting as preparation methods for package related failures and for backside analysis of ICs. With laser ablation we uncovered gold wedges on an internal board of a PLFBGA package without damage of the gold wires and the board metallization. This was possible by optimization of the laser pulse energy and the pulse repetition rate and by limitation of the ablation area. Sandblasting showed to be a gentle way for backside thinning down to 60 μm silicon thickness. For a surface smoothness sufficient for IR imaging a subsequent planarization treatment is necessary.
SEM / SThM-Hybrid-System: A New Tool for Advanced Thermal Analysis of Electronic Devices
Authors: Altes A. , Heiderhoff R. , Balk L.J. , Joachimsthaler I. , Zimmermann G. 
Published: December 2020

Abstract
A resistive probe based Scanning Thermal Microscope (SThM) was implemented in an analysis chamber of a Scanning Electron Microscope (SEM). By means of this hybrid-system thermal device, specific characteristics are detectable. Variable punctual heat sources can be simulated and the influence of ambient parameters can be investigated.
Failure Analysis Strategy for 2 Stacked Die CSP
Authors: Mohamed Shamsul , Francis Caroline , Saad Rodzaki , Jaffar Rosli 
Published: December 2020

Abstract
Multi chip packages provide higher functionality in a module using multiplicity of dice. One specific packaging technology known as Stacked Chip-Scale Packaging raises new challenges for the failure analysis community. A methodology to perform full electrical isolation and failure analysis without damaging the electrical connectivity on either package or any of the dies in a stacked 2-die package is described. A second challenge is to obtain analysis result in a limited time frame in order to improve manufacturing yield and perform corrective action effectively. Example of successful failure analysis following this methodology on units with failure in packaging unit and units in failure in the die are presented.
Application of Focused Ion Beam in Debug and Characterization of 0.13 µm Copper Interconnect Technology
Authors: Yuan Caiwen , Mahanpour Mehrdad , Lin Hung-Jen , Hill Gene 
Published: December 2020

Abstract
Focused Ion Beam (FIB) has been widely accepted in circuit modification and debugging of new chips and process technologies [1]. It has the advantages of rapid confirmation of design fixes and reducing the cost and time to build new masks. In this paper, we will describe the latest application of FIB to debugging Static Random Access Memory (SRAM) test chips processed on a dense copper metallization technology. Examples of finding leaky capacitors will be given. Individual transistors in the cell array have also been “fibbed” and characterization curves were measured. We compare the measurement with the SPICE simulation and discuss possible damage to the underlying transistors during FIB pad creation. Resistors in the periphery circuit were fibbed and measured with two and four point probes. Contact resistance was characterized and compared to that of Al interconnects. Example of finding problem vias with the help of cross-section and voltage contrast is given.
New Techniques to Improve the Efficiency of TEM Sample Preparation
Authors: Lue Jen-Lang , Lee Jack , Luo Jian-Shing 
Published: December 2020

Abstract
Three techniques have been developed for TEM sample preparation to improve efficiency in terms of time reduction and success rate. The first technique is to closely control the thickness of a sample for a specific area to less than 10µm by mechanical polishing before undergoing FIB thinning. The second one is to repair cracks produced during mechanical polishing before further milling in the ion miller. The last one is to provide an in-FIB remedy for face-to-face cross-sectional samples, which peel from each other during mechanical polishing. These new techniques will substantially enhance the success rate and turnaround time for TEM sample preparation.
Sample Preparation for Vertical Transistors in DRAM
Authors: Ruprecht Michael W. , Wen Shengmin , Vollertsen Rolf-P. 
Published: December 2020

Abstract
This paper describes a newly developed preparation technique for vertical transistors in DRAM. The recently developed concept of DRAM cells combining a deep trench storage capacitor and a vertical access transistor promises a significant reduction in cell size. In the vertical transistor concept two gates are used to access one storage cell, which creates a challenge for the analysis of gate oxide fails. A gate oxide breakdown is determined and localized in the memory array by electrical probing and photoemission microscopy. The preparation technique combines focused ion beam (FIB) milling and selective wet chemical etching to expose both gates of the transistor simultaneously. Gate oxide pinholes are decorated by the wet etch to allow efficient inspection in a secondary electron microscope (SEM).
CMOS Backside Deprocessing With TMAH / IPA as a Sample Preparation Procedure for Failure Analysis
Authors: Prejean Seth , Bruce Victoria , Burke Joyce 
Published: December 2020

Abstract
This paper is about a sample preparation technique that is based on a previous research publication1. The technique was initially used for the investigation of salicide formation for CMOS process development. The initial results were very good and proved to be helpful with root cause failure analysis. Once the technique proved to be a viable failure analysis (FA) tool, a research team was formed to continue the development. This paper is written in conjunction with this team. The team is presently focused on developing a repeatable and reliable methodology of deprocessing CMOS devices from the backside. The team is also developing a methodology for post deprocessing analysis once the backside silicon is removed. The research that is presented here focuses on packaged as well as unpackaged devices. Etch rates and selectivity of tetramethylammoniumhydroxide (TMAH) is investigated along with temperature dependencies. Package material and chemical interference issues were discovered and remedied with special preparation techniques. Post deprocessing analysis is considered and many ideas are proposed as part of future research.
Comparison of Differential Scanning Calorimetry and Energy Dispersive X-ray Microanalysis for Measuring Low Gold Concentrations in Sn/Pb Solder Bumps
Authors: Mohr James , Sullivan Eileen , Deal Paul , Seddon Michael 
Published: December 2020

Abstract
The presence of gold within a Sn/Pb solder joint accelerates diffusion between the Sn and Ni of the Ni- V/Cu underlying bump metallurgy (UBM), generating early failures. A concentration of 1.2 wt% gold in the solder joint can accelerate time to failure by a factor of 400 [3]. The EDS x-ray microanalysis detection limit for gold in tin / lead solder of about 1.2 wt% gold was found to be above the concentration range of interest (0.1 – 0.5 wt% gold). Due to the reliability impact that even a low concentration of gold can have on solder joints employing Ni-V/Cu UBM, a method using differential scanning calorimetry (DSC) was developed to accurately measure gold concentrations of less than 1 wt% in solder bumps.
Targeted Defect Analysis for Yield Improvement
Authors: Andrade Luis , Bynum Timothy , Doyle Richard , Flaherty Brian , Grammer David , Jacobs Chris , Luzar Mark , McDaniel Eric , Ricks Dave , Stanley Randall , Taylor Tom 
Published: December 2020

Abstract
Defect analysis and reduction is a focus in all wafer fabs, but there are many approaches to minimizing defect related yield losses. This paper describes the analysis for defect learning and our methodology for defect reduction within our manufacturing line including wafer selection, optimum allocation of engineering resources, details of the learning process, and objectives (both short and long term) of the defect analysis. The focus of the paper is on our 140nm DRAM technology products.
Methodology to Correlate Defect Reduction Systems to Electrical Test Data via Artificially Manufactured Defects
Authors: Santana Mike , Herrera Alfredo V. 
Published: December 2020

Abstract
This paper describes a methodology for correlating physical defect inspection/navigation systems with electrical bitmap data through the fabrication of artificial defects via reticle alterations or circuit modifications using an inline FIB. The methodology chosen consisted of altering decommissioned reticles to create defects resulting in both open and shorted circuits within areas of an AMD microprocessor cache. The reticles were subsequently scanned using a KLA SL300HR StarLight inspection system to confirm their location, while wafers processed on these reticles were scanned at several layers using standard inline metrology. Finally, the wafers were electrically tested, bitmapped, and physically deprocessed. All defect data was then analyzed and cross-correlated between each system, uncovering some important system deficiencies and learning opportunities. Data and images are included to support the significance and effectiveness of such a methodology.
Real Time Fault Site Isolation of Front-End Defects in ULSI-ESRAM Utilizing In-Line Passive Voltage Contrast Inspection
Authors: Patterson Oliver D. , Drown Jennifer L. , Crevasse Brian D. , Salah Ahmed , Harris Keiko K. 
Published: December 2020

Abstract
Electrical failures due to front-end defectivity may be detected in-line using large area PVC inspection. Application of this method to a self-aligned contact module of a memory chip is presented. Most of the defectivity affecting this module is non-visual. The PVC inspection results allow representative defects to be cross-sectioned and fully characterized soon after they are created. This approach to FA offers much faster results and much larger sampling of the defectivity affecting each lot than end of line FA. Current experiments to debug the principal defect types are described.
Prospects of Time-Resolved Photon Emission as a Debug Tool
Authors: Vickers Jim , Pakdaman Nader , Kasapi Steven 
Published: December 2020

Abstract
Dynamic hot-electron emission using time-resolved photon counting can address the long-term failure analysis and debug requirements of the semiconductor industry's advanced devices. This article identifies the detector performance parameters and components that are required to scale and keep pace with the industry's requirements. It addresses the scalability of dynamic emission with the semiconductor advanced device roadmap. It is important to understand the limitations to determining that a switching event has occurred. The article explains the criteria for event detection, which is suitable for tracking signal propagation and looking for logic or other faults in which timing is not critical. It discusses conditions for event timing, whose goal is to determine accurately when a switching event has occurred, usually for speed path analysis. One of the uses of a dynamic emission system is to identify faults by studying the emission as a general function of time.
Defect Localization Using Time-Resolved Photon Emission on SOI Devices that Fail Scan Tests
Authors: Bodoh Dan , Black Ed , Dickson Kris , Wang Ron , Cheng Tim , Pakdaman Nader , Vickers Jim , Cotton Dan , Lee Birk 
Published: December 2020

Abstract
Time-resolved photon emission has been shown to be useful in analyzing clock skews and timing-related defects in flip-chip devices. In practice, time-resolved photon emission using the S-25 Quantar detector cannot be used at long loop lengths (typically &gt;10 μs). This paper discusses a near-infrared (NIR) optimized time-resolved emission system to demonstrate that even with long loop lengths time-resolved photon emission can be extremely useful for defect localization. Specifically, it describes time-resolved photon emission system, and shows how time-resolved photon emission was used to solve two different issues that caused scan fails on silicon-on-insulator devices, and briefly discusses the interpretation of optical waveforms. The two issues are presented as case studies.
The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages
Authors: Gaut George F. 
Published: December 2020

Abstract
Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.
Parametric Variation or Defects?: Statistical Post-Processing Analysis of Wafer-Sort Data
Authors: Daasch W. Robert 
Published: December 2020

Abstract
The subject of this paper is statistical post-processing of wafer-sort test data. Statistical post-processing (SPP) has successfully separated many of the effects of defects from normal wafer-to-wafer variation. The data-driven method is used with parametric data such as IDDQ, minVDD, and others. The neighboring die are used to form an estimate of a die’s expected value. The resulting SPP residual has smaller variance than the original measurement variance and filters most of the spatial patterns that obscure data outliers from normal variation. The method is applicable to a wide variety of process parameter variation issues of concern to both test and FA communities.