bluuebunny/crossref_metadata_2025_split huggingface dataset:
Multiple-Post In-Situ Lift-Out Grids Preparation Using a Dicing Saw
Authors: Luo Jian-Shing , Lee Hsiu-Ting , Liew San-Lin , Sung Ching-Shan , Wu Yi-Jing 
Published: December 2020

Abstract
The use of in-situ lift-out combined with focused ion beam milling has become a favorable choice as it offers several indispensable advantages compared to the conventional mechanical and ex-situ lift-out sample preparation techniques. This paper discusses the procedures of the multiple-post in-situ lift-out grids preparation using a dicing saw. In addition, a real case is described to show that the multiple-post in-situ lift-out grids have been successfully applied to failure analysis. The multiple-post in-situ lift-out grids provide more positions and flatter surfaces for TEM sample mounting. The flat surface greatly increases the mounting efficiency and success rate. For the real case application, a thick Al fluoride oxide layer and Al corrosion were found above the Al bond pads, which had NOSP problem, and their neighbor area, respectively.
Influence of Laser Radiation on Embedded Non Volatile Memories and Its Application for Descrambling Verification
Authors: Österreicher I. , Skuras J. , Haase A. 
Published: December 2020

Abstract
This paper presents a fast method for descrambling verification of a flash array using an IR laser. The basic effect of how the flash cell reacts to the irradiation is studied first; and then, it is shown how to take advantage of this reversible effect to quickly verify the descrambling of the flash array of a modern microcontroller. The goal of this study is to find a way to deliberately affect the programming state of a specific flash memory cell, so the altered state can be read out by standard test equipment and be correlated to the physical position of the cell. Information on the mechanism of Fowler Nordheim tunneling, ONO-tunneling, hot electrons, and laser-induced hot electron injection is provided. The application for fast descrambling of a NVM array is shown.
Novel Gox Inspection Methodology in Advanced Silicon Process
Authors: Wang Kuo Yu , Chen Kuo Hsiung , Lin Jian Chang , Wu W. S. 
Published: December 2020

Abstract
This paper describes a new gate oxide (Gox) inspection method that uses nanoprobing and capacitive-atomic force microscopy (C-AFM) along with optimized etch chemistries and polishing techniques. It presents several examples showing how the new method outperforms conventional Gox inspection approaches in its ability to locate defects such as oxide pin holes and impurities that cause leakage current. It also discusses the electrical behavior of pin holes and soft defects.
Chromatic Aberration Correction of Silicon Aplanatic Solid Immersion Lens for Photon Emission Microscopy of Integrated Circuits
Authors: Yurt A. , Ramsay E. , Köklü F. H. , Ünlü M. S. , Goldberg B. B. 
Published: December 2020

Abstract
We investigate a complementary objective lens design for correcting chromatic aberration in the use of a silicon aplanatic solid immersion lens for back-side photon emission microscopy of metal-oxide-semiconductor circuits. Our simulations demonstrate that the chromatic aberration due to material dispersion of aplanatic silicon solid immersion lenses can be reduced by more than an order of magnitude in the spectral window 1.5µm-2.1µm, providing new diffraction limited performance. On-axis and off-axis imaging performance of the proposed optical design is evaluated.
Microstructural Considerations on the Reliability of 3D Packaging
Authors: Huang Zhiheng , Wu Zhiyong , Xiong Hua , Ma Yucheng 
Published: December 2020

Abstract
Microstructure and its effect on mechanical behavior of ultrafine interconnects have been studied in this paper using a modeling approach. The microstructure from the processes of solidification, spinodal decomposition, and grain growth in ultrafine interconnects has highlighted its importance. The size, geometry and composition of interconnects as well as the elastic energy can influence microstructure and thus the mechanical behavior. Quantification of microstructure in ultrafine interconnects is a necessary step to establish the linkage between microstructure and reliability.
Photon Emission Spectra of FETs as Obtained by InGaAs Detector
Authors: Glowacki Arkadiusz , Boit Christian , Yokoyama Yoshiyuki , Perdu Philippe 
Published: December 2020

Abstract
In this work we present spectrally resolved photon emission microscopy (SPEM) measurements for short-channel FETs acquired through the backside of the Si substrate using InGaAs detector. Two spectrum resolution methods have been used: continuous using a prism and discrete using a set of interference band-pass filters. The photon emission (PE) spectra have been corrected for the background / noise of the detector; they have been calibrated with respect to the system optical transmission function and corrected for the absorption on free carriers in the remaining layer of Si substrate. We discuss all the standardization aspects thoroughly as they are crucial in order to obtain correct device-intrinsic PE spectral information. Finally, we present the spectral results for FET devices operated in various operating conditions.
3D Tomography Analysis of Dark Voltage Contrast Failure in PCRAM Device
Authors: Oh Jangwon , Kim Jonghyeop , Lee Taekwon , Jeon Seungjoon , Kim Won , Kim Hojoung , Kim Changreol 
Published: December 2020

Abstract
The failure analysis using transmission electron microscopy (TEM) has been actively preceded in semiconductor industry. But due to the overlap issue and structural complexity of devices, it has become harder and harder to perform failure analysis using normal projected bright field (BF) and high angle annular dark field (HAADF) TEM images. To overcome these problems, 3-dimensional (3D) tomography technique has been suggested. In this work, we clarify the root cause of dark voltage contrast (DVC) failure at the bottom electrode contact region in PCRAM by using 3D tomography analysis. The 3D tomography samples were prepared in lamella shape by using focused ion beam (FIB). The electron energy loss spectroscopy (EELS) and 3D tomography analysis in scanning transmission electron microscope (STEM) HAADF mode were carried out. Through 3D tomography image reconstruction by AMIRA program, we observed ‘open contact fail’ between the BEC (Bottom Electrode Contact)-1 and the BEC (Bottom Electrode Contact)-2 at DVC region that could not be shown in 2D image.
A Proof for the Possibility of Ce-Oxide from CMP Residuals in Si-Wafers by Analytical TEM
Authors: Zhao Wayne , Thanh Liem Do , Gribelyuk Michael , Zaitz Mary-Ann , Lai Wing 
Published: December 2020

Abstract
Inclusion of cerium (Ce) oxide particles as an abrasive into chemical mechanical planarization (CMP) slurries has become popular for wafer fabs below the 45nm technology node due to better polishing quality and improved CMP selectivity. Transmission electron microscopy (TEM) has difficulties finding and identifying Ce-oxide residuals due to the limited region of analysis unless dedicated efforts to search for them are employed. This article presents a case study that proved the concept in which physical evidence of Ce-rich particles was directly identified by analytical TEM during a CMP tool qualification in the early stage of 20nm node technology development. This justifies the need to setup in-fab monitoring for trace amounts of CMP residuals in Si-based wafer foundries. The fact that Cr resided right above the Ce-O particle cluster, further proved that the Ce-O particles were from the wafer and not introduced during the sample preparation.
Tomographic Study of Silicon Nanoparticles in Nanocrystalline Non-Volatile Flash Memory Devices by EFTEM
Authors: Zhou YongKai , Zhu Jie , Du AnYan , Hua YouNan , Mo ZhiQiang , Zhao SiPing 
Published: December 2020

Abstract
The distribution of Si nanoparticles, both dimensional and spatial, is a key factor affecting the performance of non-volatile flash memory devices. A new FIB method has been developed to prepare ultra-thin plan view specimens, containing only the Si nanoparticle matrix thin film layer, from fully processed nanocrystalline flash memory devices. The morphology and distribution of Si nanoparticles were then studied by EFTEM 3D tomographic reconstruction.
Simple and Fast Backside Sample Preparation Technique for Backside Fault Localization Analysis by Using Chemical Etching Method
Authors: Yen Gwee Hoon , Kay Ng Kiong 
Published: December 2020

Abstract
Deprocessing from the die backside provides a means of circuit inspection especially when the front side of die is fully covered with metallization. One of the most common techniques used is mechanical milling. It can provide good accuracy and consistency in backside preparation. However, the disadvantage of using this technique is the milling process is very time consuming. It takes at least 1-2 hours to complete the thinning and polishing process for only one unit. In addition, the equipment investment cost and later the maintenance cost (e.g. milling tools) is high. Therefore, an alternative way of backside opening is being proposed by chemical etching which is relatively fast and simple. It saves time and cost as the task can be done in less than 10 minutes while at the same time this new proposed method is still able to preserve the electrical functionality of the device.
Preparation of Wafer Level Packaged Integrated Circuits Using Pulsed Laser Assisted Chemical Etching
Authors: Chivas Robert , Dandekar Niru , Silverman Scott , Cruz Roddy , DiBattista Michael 
Published: December 2020

Abstract
Pulsed Laser Assisted Chemical Etching (PLACE) is an advanced method of surface preparation that etches backside silicon to ultra-thin remaining layer thickness for Focused Ion Beam (FIB) circuit edit and failure analysis of Wafer Level Packages (WLP). PLACE can achieve ultra-high purity and fine dimensional control since it is a dry process relying on pyrolytic vapor phase reactions initiated, and constrained, by a pulsed laser.
3D Void Imaging in Through Silicon Vias by X-Ray Nanotomography in an SEM
Authors: Laloum David , Lorut Frédéric , Bleuet Pierre , Audoit Guillaume , Ribiere Celine 
Published: December 2020

Abstract
We have exploited an innovative X-ray tomography system, which is hosted in a Scanning Electron Microscope (SEM). The resolution reached by this equipment is closed to 160nm in 2 dimensions. We imaged Through Silicon Vias (TSV) which have undergone a manufacturing defect and characterized voids within these interconnections.
Computed Tomography as Failure Analysis Insurance
Authors: Martinez Gerald M. 
Published: December 2020

Abstract
Failure analysis of electronic components is almost always destructive, and there’s no going back once a destructive step is performed. Or, that’s the way it used to be, before the development of some of the more sophisticated nondestructive techniques such as computed tomography (CT). This paper presents a case study of an optocoupler, the suspected failure of which could not be confirmed until the last day of the month-long analysis, when the cause of failure was conclusively determined by a CT model captured weeks earlier.
Failure Analysis for SRAM Logic Type Failures
Authors: Song Zhigang , Beaudoin Felix , Lucarini Stephen , Sylvestri John , Safran Laura , Villallobos Manuel , Oldrey Richard 
Published: December 2020

Abstract
Failure analysis for Static Random Access Memory (SRAM) is the major activity in any microelectronic failure analysis lab. Originating from SRAM array structure, SRAM failure can be simple as single bit, paired bit or quad bit failures, whose defect is located at the failure location, or complicated as logic type failure involving WL or BL patterns or entire blocks, whose defect is often not at the failure location. For such SRAM logic type failures, failure analysis is more challenging and detailed fault isolation is necessary prior to physical failure analysis. This paper has demonstrated how to use SRAM decoder scheme knowledge, detailed layout tracing and Photon Emission Microscope (PEM) analysis to deal with the challenges and find the root causes for several cases of SRAM logic type failures.
Circuit Edit Geometric Trends
Authors: DiBattista Michael , Parley Martin , Lyons Don , Cruz Roddy , Wu Alan , Langley Jamie , Lau Jonathan , Stevens Ray 
Published: December 2020

Abstract
Focused ion beam (FIB) tools for backside circuit edit play a major role in the validation of integrated circuit (IC) design modifications. Process scaling is one of many significant challenges, because it reduces the accessible area to modify transistors and IC interconnects in the design. This paper examines the geometries available for FIB nanomachining, via milling/etching, and deposited metal jumpers by analyzing polygon data from computer aided design (CAD) virtual layers gathered across four process technologies, from 180nm down to 28nm. The results of this analysis demonstrate that the combination of silicon nanomachining box length and FIB via box length identifies the most challenging aspects of the FIB edit. The smallest geometries include a 300 nanometer silicon access area with a FIB milled 200 nanometer via inside it. More advanced technology nodes will require the ability to make smaller geometries without the help of integrated design features typically referred to as design for FIB/Debug.
Gate Leakage Characterization and Fail Mode Analysis on 20 nm Technology Parametric Test Structures
Authors: Kodali Satish , Zhao Wayne , Johnson Greg M. , Beaudoin Felix 
Published: December 2020

Abstract
Test structure characterization plays a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of line (HOL). One of the key principles in successfully monitoring the HOL is to establish passing and failing electrical criteria to various test structures. This paper shows electrical and physical characterization of one such test structure. Further, a novel way of establishing electrical signatures to specific defect fail mode finger prints for early identification and monitoring of process-related defects is proposed.
Comparison of C.W. Electro Optical Probing and Light Emission Techniques
Authors: Sanchez K. , Perdu P. , Melendez K. , Nakamura T. 
Published: December 2020

Abstract
Recent developments and improvements of laser probing techniques are a good complement to traditional techniques like emission microscopy (static and dynamic) or laser stimulation (also static and dynamic, based on thermal or photoelectric stimulus) for the investigation of failure analysis and diagnostic of integrated circuits. Laser probing techniques have in fact evolved from mainly pulsed approach with high bandwidth [1] to other methodologies based on Continuous Wave (CW) [2,3,4,5]. The bandwidth of these CW approaches is generally lower than pulsed techniques and fine characterization of rising and falling edges or measurement of very small timing shifts can be more difficult or not possible for high speed devices. This bandwidth limitation is most of the time due to the amplification chain. But, CW probing bandwidth is good enough, and continuously improving, to identify directly or indirectly timing issues and to identify bad digital or analog behavior. The setup is also much easier than pulsed laser systems which require complicated synchronization between the system timebase and the device. On this other side new internal analysis modes have been introduced with for example some mapping mode based on frequency analysis or on timing degradation identification through second harmonic analysis [6,7]. At the same time these techniques have pushed the capabilities of a lot of existing tools to investigate low current, low voltage and/or low frequency devices such as analog parts, transmission gates and configurations when the defect cannot be activated at normal or high voltage. Comparison with EMission MIcroscopy (EMMI) in dynamic mode, which can have the higher bandwidth [8] is then possible.
Dynamic Differential Thermal Measurements for Reliability and Failure Analysis
Authors: Falk R. Aaron , Pham Tram , Ruiz Anthony 
Published: December 2020

Abstract
Differential thermal measurements have been extended beyond simple fault isolation to quasi and fully dynamic test conditions. A new technique of Dynamic Digital Modulation has been developed that allows highly sensitive differential thermal measurements during active device operations. A quadrature version of the modulation also produces a thermal time constant map that allows for direct visualization of heat flow within a device structure. A wide range of potential applications in failure analysis, reliability and reverse engineering are opened up. Examples include in situ identification of resistive bonds, internal heat flow in packaged devices and die, dynamic heat loading, and localization of structural elements for reverse engineering.
A Reduction of Off-Leakage Current of SWD (Sub-WordLine Driver) pMOSFET for NWL-Based Mobile DRAM
Authors: Jeon Sanghyeon , Ha Taehong , Kim Youngwoo , Jung Hyuckchai , Lee Taewoo , Lee Kyupil , Cho Insoo 
Published: December 2020

Abstract
We demonstrate an effective way of reducing off-leakage current in sub-wordline driver pMOSFETs with lightly-doped source/drain, where gate-induced drain leakage current is much relaxed, compared with those of asymmetric source/drain. In mobile DRAM, one of key parameters is to achieve an extremely low level of standby current in power consumption. What has been found is that an increase of offleakage current in the pMOSFET is related closely to a contact-formation process, in particular, TiSi2 in p+/n junction. When a direct contact becomes close to a source/drain region, a titanium atom in TiSi2 tends not only to diffuse into a depletion region of p+/n junction but to play a critical role in leakage current. Maximizing a distance between p+ gate and its direct contact should be emphasized in order to control offleakage current in such a pMOSFET.
Rapid Failure Analysis of Low-Yielding Electrical Test Structures Using E-beam Physical and Voltage Contrast Inspection
Authors: Patterson Oliver D. , Ryan Deborah A. , Tang Xiaohu , Lei Shuen Cheng 
Published: December 2020

Abstract
In-line E-beam inspection may be used for rapid generation of failure analysis (FA) results for low yielding test structures. This approach provides a number of advantages: 1) It is much earlier than traditional FA, 2) de-processing isn’t required, and 3) a high volume of sites can be processed with the additional support of an in-line FIB. Both physical defect detection and voltage contrast inspection modes are useful for this application. Voltage contrast mode is necessary for isolation of buried defects and is the preferred approach for opens, because it is faster. Physical defect detection mode is generally necessary to locate shorts. The considerations in applying these inspection modes for rapid failure analysis are discussed in the context of two examples: one that lends itself to physical defect inspection and the other, more appropriately addressed with voltage contrast inspection.
Spectrum Sharpening on Rotation Averaged TEM Nano Beam Electron Diffraction Patterns
Authors: Zhou Yongkai , Hua Younan , Li Xiaomin 
Published: December 2020

Abstract
The Rotation Averaged Spectrum of TEM diffraction patterns can be sharpened by a Maximum-Likelihood deconvolution algorithm. The sharpened spectrum will help to improve the precision of TEM diffraction-based techniques, e.g.: phase identification and strain analysis.
Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause
Authors: Tsang Yuk L. , VanVianen Alex , Wang Xiang D. , Theodore N. David 
Published: December 2020

Abstract
In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.
Failure Localization of Intermittent Short Failures Caused by Vertical Conductive Anodic Filament Formation
Authors: Nuez Daniel , Tan Phoumra 
Published: December 2020

Abstract
Conductive anodic filament (CAF) formation is a mechanism caused by an electrochemical migration of metals from a metal trace in ICs or in PCBs. This is commonly caused by the moisture build-up in the affected metal terminals in an IC package or PC board caused by critical temperature, high humidity and high voltage gradients conditions. This phenomenon is known to have caused catastrophic field failures on various OEMs electronic components in the past [1,7]. Most published articles on CAF described the formation of the filament in a lateral formation through the glass fiber interfaces between two adjacent metal planes [1-6, 8-12]. One common example is the CAF formation seen between PTH (Plated through Hole) in the laminated substrate with two different potentials causing shorts [1-6, 8-12]. In this paper, the Cu filament grows in a vertical fashion (z-axis formation) creating a vertical plane shorts between the upper and lower metal terminals in a laminated IC package substrate. The copper growth migration does not follow the fiber strands laterally or vertically through them. Instead, it grows through the stress created gaps between the impregnated carbon epoxy fillers from the upper metal trace to the lower metal trace with two different potentials, between the glass fibers. This vertical CAF mechanism creates a low resistive short that was sometimes found to be intermittent in nature. This paper presents some successful failure analysis approaches used to isolate and detect the failure locations for this type of failing devices. This paper also exposes the unique physical appearance of the vertical CAF formation.
Safe Decapsulation Techniques Using Viton Caulk
Authors: Staller Kristopher D. 
Published: December 2020

Abstract
The decapsulation process in today’s failure analysis labs can become complicated with the smaller size of the package and the surface mount methods of attachment. Some failure modes recover when a part is removed from the application and remounted after decapsulation, and some parts are simply too fragile to handle for re-mounting after decapsulation. Decapsulating the failing device in-situ (on the board or DIP adapter) allows us to analyze the part in its original mounting condition, without exposing it to additional solder temperature stress, broken wires, or tweezer damage. This poses a challenge, as the fuming acids used for decapsulation most likely will spill onto the circuit board, dissolving the package leads, damaging the resin layers, and potentially corroding and shorting the circuit board traces.