bluuebunny/crossref_metadata_2025_split huggingface dataset:
Study of SiGe Surface Cleaning
Authors: Komori Kana , Wostyn Kurt , Rondas Dirk , Prado Jana Loya , Conard Thierry , Loo Roger , Ragnarsson Lars-Åke , Horiguchi Naoto , Holsteyns Frank 
Published: February 2020

Recently Si can be replaced with SiGe in FinFETs (field-effect transistors) and GAA (gate all around) structures in order to get the higher carrier mobility. However, Ge oxide concentration of SiGe oxide causes an increase in interface trap density (Dit) and becomes a defect of device. Although Si and Ge surface treatments have been studied so far, SiGe surface treatment is still not well understood. Recently cleaning of SiGe surface is required and began to be studied for Ge concentration of SiGe oxide by dry and wet cleaning has been reported [1-2].
For cleaning of SiGe surface, this study focused on wet process solutions of O3 water and acids (HF and HCl) with Si1-xGex (X=25-45%) wafer. The behavior of oxide is shown by using these chemical solutions individually or in combination. XPS measurement showed differences of Ge oxide concentration.
As first experiment, native oxide shows Ge concentration of oxide and substrate are same or slightly less than substrate. On the other hand, chemical oxide by using O3 water showed concentration of Ge oxide is 10% less than substrate on Si75Ge25 wafer.
This study shows the behavior of SiGe surface can be controlled by changing chemical concentration or chemical combination. Details of results will be reported in presentation.
[1]S.L.Heslop,et al.,in:ECS Transactions,69 (8) 287-293 (2015)
[2]Sang Wook Park,et al., in:J.Vac.Sci.Technol.A,Vol.33,No.4,Jul/Aug 2015
Nearly Anhydrous Undissociated HF for the Removal of Hf / Ta / Zr Based Polymers after Plasma Etch, Selectively to Aluminum
Authors: Cazes Marine , Broussous Lucile , Garnier Philippe , Pizzetti Christian , Gabette Laurence , Besson Pascal 
Published: February 2020

The removal of tough Ta, Zr or Hf based polymers selectively to aluminum is a challenging concern in the fabrication of High-K capacitors or specific metals stacks with thick Tantalum layers for example (fig.1, 2 ). Most of actual commercial chemistries only barely touch some of the toughest polymers generated by plasma etch process as seen in Fig 3. HF is sometimes employed but has shown moderate efficiency (fig 4,5) associated with a serious risk of metals and oxide consumption if not well controlled for some critical structures.
HF is commonly used to pattern amorphous or damaged HfO2 highK gates, and the selectivity to thermal silicon oxide has been studied in details by V. Paraschiv [2] showing the relative importance of each species in the etching mechanism. Moreover, in early studies around the use of HF for silicon dioxide etching, the need and the role of condensed water or alcohol together with HF vapor is well documented.[1, 3], and the detailed mechanism involved in the silicon dioxide dissolution in diluted HF is widely accepted [4]. Finally the hydration of hydrogen fluoride is not as rapid and straightforward as other halides like chlorine and Bromine [5] therefore at low water content hydrogen fluoride can be seen as nearly anhydrous solution.
This paper describes the work that has been done in collaboration with STMicroelectronics to evaluate a newly released chemistry IK 73 from TECHNIC France which combines the advantages of being nearly anhydrous and avoids the HF dissociation at any dilution ratio with water (see graph 1), for the removal of Ta, Hf and Zr based polymers after dry etch and ash, selectively to Aluminum eventually exposed.
The main features of the chemistry and its behavior on blanket films at different dilutions ratios will be first exposed. Morphological results (SEM-TEM) on various kinds of structures are presented, as illustrated in fig.6,7.
From the results obtained we conclude that it is possible to efficiently dissolve Ta, Zr, Hf based polymers (or their amorphous oxides) selectively to aluminum, thanks to TechniClean IK 73.

Reference

[1] Won Ick Jang, Chang Auck Choi, Myung Lae Lee, Chi Hoon Jun and Youn Tae Kim .
J. Micromech. Microeng. 12 (2002) 297–306
[2] V. Paraschiv, M. Claes, M. R. Baklanov, W. Boullart, S. De Gendt, S. Vanhaelemeersch, Solid State Phenomena Vols. 103-104 (2005) pp 97-102
[3] Ron Hanestad ; Jeffery W. Butterbaugh ; Abdselem ben-Hamida ; Ilaria Gelmi Proc. SPIE 4557, Micromachining and Microfabrication Process Technology VII, 58 (September 28, 2001); doi:10.1117/12.442986
[4] D. Martin Knotter J. Am. Chem. Soc., 2000, 122 (18), pp 4345–4351
[5] Odde S, Mhin BJ, Lee KH, Lee HM, Tarakeshwar P, Kim KS

T
he Journal of Physical Chemistry A 110(25):7918-24 · July 2006

Figure 1
(Invited) Thermal Cyclic Atomic-Level Etching of Nitride Films: A Novel Way for Atomic-Scale Nanofabrication
Authors: Shinoda Kazunori , Miyoshi Nobuya , Kobayashi Hiroyuki , Kurihara Masaru , Izawa Masaru , Ishikawa Kenji , Hori Masaru 
Published: February 2020

Because the structure of semiconductor devices has changed to miniaturized three-dimensional (3D) structures, etching technologies that enable 3D atomic-scale control have received increasing interest. Therefore, atomic level/layer etching (ALEt), which is a counterpart of atomic layer deposition (ALD), has attracted much attention due to its potential in atomic-scale 3D nanofabrication. ALEt typically involves a cyclic repetition of self-limiting formation and desorption of surface modified layers. Thus, geometric loading effects are mitigated when using ALEt because of the self-limiting behavior.
The authors have developed a novel isotropic ALEt process for SiN using cyclic repetitions of hydrofluorocarbon-based plasma exposure and thermal annealing [1]. The first step of the etching cycle for SiN is exposing the sample surface at room temperature to hydrofluorocarbon-based radicals that form ammonium hexafluorosilicate ((NH4)2SiF6) on SiN. The second step is thermal annealing above 100°C to sublimate the ammonium hexafluorosilicate. SiN film with an atomically thin layer can be etched away by repeating the cycle of forming and by removing the ammonium hexafluorosilicate. This cyclic etching shows self-limiting behavior because the formation of the ammonium hexafluorosilicate saturates as the plasma exposure time increases. This technology is applicable to other nitride films besides SiN. The authors have demonstrated selective isotropic ALEt of TiN [2], which is widely used as a gate electrode and barrier metal in semiconductor devices.
In this paper, we present our results with the isotropic ALEt process for SiN and TiN. This method features a variety of promising characteristics, such as high selectivity with respect to SiO2and poly Si, atomic-level control of the etching amount, and isotropic etched profiles. The authors developed a novel etching apparatus as an ALEt tool for 300-mm wafers. This apparatus utilizes an infrared (IR) lamp for thermal annealing to achieve rapid temperature cycles. Particular attention is devoted to the surface reaction mechanism in the novel isotropic ALEt process for SiN. The results of in situ X-ray photoelectron spectroscopy (XPS) and thermal desorption spectroscopy (TDS) are described; they reveal the formation and decomposition of ammonium hexafluorosilicate on SiN during the cycle of plasma exposure and annealing. The potential industrial applications of these two processes are also described.
[1] K. Shinoda et al., Appl. Phys. Express 9, 106201 (2016).
[2] K. Shinoda et al., AVS Symposium and Exhibition, PS+TF-WeM10 (2016).
(Invited) Research to Manufacturing: ALD Design for Precision Atomic Layer Fabrication
Authors: LaVoie Adrien R. , Kumar Purushottam 
Published: February 2020

Novel atomic layer engineering technologies have emerged as key developmental tools for <2X node fabrication in the modern semiconductor manufacturing. Today’s applications include front-end-of-line (FEOL) spacers and liners, isolation gapfill, FinFET conformal doping, multi-patterning layers, through-silicon via liners, sacrificial layers, encapsulation, selective deposition/etch, conformal etch, and surface smoothening to name a few.
In the first section, industrial drivers including intelligent devices, economics, and inflection points will be correlated to atomic layer engineering market applications. The advantageous qualities of self-limiting and saturation technologies will be reviewed with a focus on implications for throughput, unit film property optimization, and controlling process variation. An alternative paradigm shift for processing in the “sub-saturated regime” will be reviewed with attention to the pros and cons. The complementary nature of ALD and ALE will be considered with a predictive look at the future of atomic layer engineering.
ALD of Fluorine-Free Boron-Containing Composite Layers for Shallow Dopant Source Applications
Authors: Mane Anil U. , Liu Jian , Farha Omar , Letourneau Steven , Pupek Krzysztof Z. , Hupp Joseph T. , Elam Jeffrey W 
Published: February 2020

Conformal coating of boron-containing films via atomic layer deposition (ALD) could be used as a shallow dopant source for advanced 3D-transistor structures in VLSI manufacturing. Aiming this application, fluorine (F) -free precursors of boron such as boric acid (B(OH)3) and trimethyl borate (B(OCH3)3) were explored as ALD precursors in a combination with Al2O3 ALD process. The ALD of Al2O3 was performed using trimethyl aluminum (Al(CH3)3) and Deionized H2O. The complex chemistry resulted in deposition of boron containing composite films of (BxAl2-xO3). In-situ quartz crystal microbalance study was performed to evaluate the optimum ALD precursors dose times as well as confirms the self-limiting behavior of the ALD processes. Growth rate of composite BxAl2-xO3 processes under various ALD conditions are in the range of 0.8-1.1Å. The resultant boron containing BxAl2-xO3 films was analyzed for composition by x-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), ellipsometry, and electrical capacitance measurements. Atomic composition of B was tailored by adjusting relative ratio of the B to Al precursors cycle during ALD process. A rapid thermal annealing was performed as a function of time and temperature and confirms B-diffusion in the Si(wafer) as well as changes in optical properties of the BxAl2-xO3 layers. Here we will present detailed investigation of ALD grown BxAl2-xO3 layers.
Digital Doping of ALD VO2 for Thermochromic Applications
Authors: Kozen Alexander C , Currie Marc , Jungjohann Katherine L , Downey Brian P. , Eddy Charles R , Wheeler Virginia D. 
Published: February 2020

Vanadium Dioxide (VO2) is an interesting thermochromic material that undergoes a first order crystalline phase transition at a critical temperature (Tc) of 68˚C. This structural phase transition is accompanied by major changes in electrical and optical properties, particularly in the infrared. As such, VO2 is suitable for many applications including microbolometers, adaptive thermal coatings, and passive spacecraft thermal shielding.
While the Tc of VO2 is convenient for many applications, it is desirable to modify the Tc to other values for either new applications or improved performance in the previously stated applications. The Tc of VO2 is known to be strain-mediated.[1] Strain in VO2 has been induced via deposition of thin films onto lattice mismatched epitaxial substrates, as well as by doping with other transition metal elements besides vandium.[2], [3]
For the first time, we are investigating digital doping of ALD VO2 using other elements such as Al, Ti, Nb, and W by incorporation of their oxides into the binary ALD VO2 process (TEMAV + O3). We will discuss the fundamentals and limitations of doped ALD VO2 growth and basic materials characterization, and will demonstrate the impact of dopant concentration and identity on the optical and electrical phase transition properties of the resulting films.
Generally, inclusion of dopants such as Ti and Al into the ALD VO2 process in amounts between 1% and 10% results in surfactant-like film growth behavior, with increasing dopant concentrations reducing RMS roughness of the ALD films from ~2 nm to ~0.2 nm. Higher concentrations of dopants also interfere with film crystallization during annealing, inhibiting the magnitude of the metal-insulator transition. Smaller concentrations of dopants, between 1% and 3%, can lower the Tc of the VO2 films while maintaining acceptable optical behavior, depending on dopant identity and concentration. In particular, we find that Nb doping at these low concentrations decreases Tc of VO2 by -13.5˚C/Nb%.
[1] J. M. Atkin, S. Berweger, E. K. Chavez, M. B. Raschke, J. Cao, W. Fan, and J. Wu, “Strain and temperature dependence of the insulating phases of VO 2near the metal-insulator transition,” Phys. Rev. B, vol. 85, no. 2, pp. 020101–4, Jan. 2012.
[2] W. Burkhardt, T. Christmann, B. K. Meyer, and W. Niessner, “W-and F-doped VO 2 films studied by photoelectron spectrometry,” Thin Solid Films, vol. 345, no. 2, pp. 229–235, 1999.
[3] X. Wu, Z. Wu, C. Ji, H. Zhang, Y. Su, Z. Huang, J. Gou, X. Wei, J. Wang, and Y. Jiang, “THz Transmittance and Electrical Properties Tuning across IMT in Vanadium Dioxide Films by Al Doping,” ACS Appl. Mater. Interfaces, vol. 8, no. 18, pp. 11842–11850, May 2016.
Reusable Sorbent for Oil Spill Cleanup Fabricated Using Sequential Infiltration Synthesis
Authors: Elam Jeffrey W , Avila Jason R , Barry Edward F. , Darling Seth B. , Libera Joseph A. , Mane Anil U. 
Published: February 2020

Crude oil spills in the ocean can be devastating to the environment and extremely expensive to mitigate. Furthermore, while oil on the surface can be removed by skimming or burning, there are currently no technologies for the cleanup of subsurface oil droplets in the ocean. To address this need, we have developed a reusable sorbent material, OleoSponge. To synthesize this material, we begin with commercial polyurethane foam, and first treat the foam using sequential infiltration synthesis (SIS). SIS is similar to ALD in that it uses alternating, self-limiting exposures between gaseous precursors and a substrate. However, whereas the ALD substrate is a solid surface, in SIS the substrate is a polymer, and the precursors react on organic functional groups within the polymer to seed the nucleation of metal oxide clusters. We performed in situ infrared spectroscopy and mass spectrometry to elucidate the mechanism for metal oxide SIS within the polyurethane foam, and we have studied the effects of temperature, time, and partial pressure on the resulting SIS deposits. The next step is to graft an oleophilic monolayer onto the SIS-treated foam, either through gas-phase or solution phase treatment. The resulting material is simultaneously hydrophobic and oleophilic, and is able to rapidly extract oil from water. We have performed extensive bench-scale testing using 1” cubes of the OleoSponge and found that it absorbs >40x its weight in oil, and can be simply squeezed out and used again. Next, we performed a 10,000 scale up, and tested the material at the Ohmsett facility in Leonardo, New Jersey, using the largest outdoor saltwater tank facility in North America. The OleoSponge performed very well in extracting subsurface crude oil and diesel fuel from seawater under realistic conditions.
(Keynote) Interface Control for High Performance N-Channel Ge FETs
Authors: Toriumi Akira 
Published: February 2020

The demonstration of high electron mobility Ge n-MOSFETs was not an easy task. To overcome such big challenge, three carrier scattering mechanisms in Ge MOS inversion layer such as Coulomb scattering, phonon scattering, and surface roughness scattering were carefully investigated. The first step was to improve the peak electron mobility by reducing the interface states density (Dit
). We succeeded in the reduction of Dit
(<1011 eV-1cm-2) at Ge/GeO2 interface by employing the high-pressure O2 (HPO) oxidation [1]. This is quite reasonable thermodynamically [2]. However, there still remained two critical challenges. One was how to suppress the significant degradation of high-Ns electron mobility. The other one was how to keep electron mobility high in thin EOT region [3].
It is generally considered that high-Ns electron mobility is dominated by the interface roughness scattering. Since we demonstrated that Ge(111) was the best surface orientation for electrons to achieve the highest peak electron mobility, we challenged to realize the atomically flat Ge(111) surface by using H2 annealing [4]. Then, MOSFETs on Ge(111) with and without atomically flat surface were fabricated with HPO. N-channel MOSFETs fabricated by HPO on atomically flat Ge(111) exhibited greatly improved high-Ns electron mobility [5].
EOT reduction was also challenging because HPO should naturally form thicker GeO2. This fact was a big hurdle on Ge FET technology. Meanwhile, it was interestingly found that the low-temperature HPO (LT-HPO) reduced the oxidation rate [6]. This fact enabled us to achieve ~2 nm EOT GeO2 on Ge with superior interface and bulk GeO2. Another way to reduce EOT is obviously to replace HPO-GeO2 with other high-k oxides which are appropriate for Ge. We have fortunately found that Y2O3 is very friendly with Ge [7]. Furthermore, in our recent experiments Y2O3-doped GeO2 (YGO) is much better than pure Y2O3 on Ge. Significantly improved electron mobility in n-channel Ge FETs in a wide range of electron density has been achieved, when YGO in addition to H2 annealing has been used for the interfacial layer in gate stacks [8].
Poor electron mobility in n-channel Ge FETs is not true now. We can engineer the Ge interface through understanding of thermodynamics in gate stack formation and of kinetics of both surface planarization and oxidation. Thus, we can safely conclude that Ge is very promising not only for p-channel but also for n-channel FETs.

References

[1] C. H. Lee et al., TED 58 (2011)1295.
[2] K. Nagashio et al., MRS Symp. Proc. 1155 (2009) C06-02.
[3] M. Caymax et al., IEDM 2009-461.
[4] T. Nishimura et al., APEX 5 (2012)121301.
[5] C. H. Lee et al., IEDM 2013-32.
[6] C. H. Lee et al., APEX 5 (2012)114001.
[7]A. Toriumi et al., “Advanced Gate Stacks for High-Mobility Semiconductors", Chap. 11, (Springer, Berlin, 2007).
[8] C. H. Lee et al., IEDM 2013-40.
Three-Layered Stacking Process by Au/SiO2 Hybrid Bonding for 3D Structured Image Sensors
Authors: Honda Yuki , Goto Masahide , Watabe Toshihisa , Hagiwara Kei , Nanba Masakazu , Iguchi Yoshinori , Saraya Takuya , Kobayashi Masaharu , Higurashi Eiji , Toshiyoshi Hiroshi , Hiramoto Toshiro 
Published: February 2020

A 3D structured CMOS image sensor is investigated wherein two layers (photodiode array layer and signal processing circuit layer) are stacked using a low-temperature Au/SiO2 hybrid bonding technique [1]. We previously reduced the pitch of Au electrodes from 40 μm to 6 μm and confirmed that the Au electrodes could be electrically interconnected via the bonding technique [2]. To further enhance its performance, higher integration by multilayer stacking is essential. Therefore, we developed a multilayering technique by direct bonding and manufactured a three-layered daisy-chain test device to examine the numerous interconnections.
The device is fabricated by the process described in Fig. 1 using the following steps: (a) an aluminum wiring layer is formed in a SiO2 dielectric layer on a Si substrate; (b) first via holes are formed on the surface of the SiO2 layer and are embedded with electroplated Au; (c) an Au/SiO2 bonding surface is formed by chemical–mechanical polishing (CMP), and the wafer is diced into the top-, middle-, and base-layer chips; (d) the bonding surfaces of the top- and middle-layer chips are activated by O2 plasma; (e) the top- and middle-layer chips are directly bonded by applying a force of 20,000 N for 60 min at 330 °C; (f) the Si substrate of the middle-layer chip is removed by grinding and XeF2 vapor-phase etching; (g) second via holes are formed on the exposed backside of SiO2 of the middle-layer chip and are embedded with an electroplated Au; (h) an Au/SiO2 bonding surface is formed on the backside of the middle-layer chip by CMP; (i) the bonding surfaces of the middle- (backside) and base-layer chips are activated by O2 plasma; and (j) the bonded (top- and middle-layer) chip and the base-layer chip are directly bonded by applying a force of 20,000 N for 60 min at 330 °C. Figure 2 shows a cross-sectional scanning electron microscopy (SEM) image of the three-layered daisy-chain test device. No voids were observed at the two bonded interfaces. Details of the three-layered stacking process and experimental results will be discussed in the presentation.
1. M. Goto et al., IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3530–3535, (2015).
2. Y. Honda et al., ECS Trans., vol. 75, no. 9, pp. 103–106, (2016).

Figure 1
(Invited) FinFET Technology
Authors: Cheng Kangguo 
Published: February 2020

FinFET has been emerged as the leading device architecture for continuing CMOS scaling. It has entered mainstream CMOS manufacturing since 22nm node. In this paper, I will provide an overview on the challenges associated with CMOS scaling and articulate how FinFET circumvents those scaling challenges. Meanwhile, FinFET has its own unique issues related to device design and process integration. A detailed discussion on challenges and opportunities of FinFET will be discussed in detail. A general guidance for further scaling FinFET will be provided including channel materials, high-k/metal gate, strain techniques, device isolations. Advanced FinFET manufacturing techniques such as self-aligned multiple patterning and EUV lithography, selective epitaxy, and high-aspect ratio dielectric deposition will also be covered. Some common misconceptions about FinFET technology such as confusing technology node names adopted by different companies will be clarified. Finally, FinFET will be compared with other device architectures such as fully depleted SOI (FDSOI) and nanowire transistors. The advantages and drawbacks of each device architecture will be summarized.