(Invited) Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in Finfet, Stacked Nanowires and Monolithic 3D Integration
Authors: Porret Clement , Hikavyy Andriy Yakovitch , Gomez Granados Juan Fernando , Baudot Sylvain , Vohra Anurag , Kunert Bernardette , Douhard Bastien , Bogdanowicz Janusz , Schaekers Marc , Kohen David , Margetis Joe , Tolle John , Lima Lucas , Sammak Amir , Scappucci Giordano , Rosseel Erik , Langer Robert , Loo Roger 
Published: February 2020

Microelectronic devices enable the continuous improvement in mobile data exchange and mobile communication. This exciting technological progress has been achieved by transistor scaling, resulting in an increased performance for lower energy consumption and cost. As CMOS device scaling proceeds, the number of epitaxial growth steps in device fabrication schemes increases. Examples are SiGe or Ge as high mobility channel materials [1-3], SiGe/Si or SiGe/Ge multi-layers to define nanowires in lateral Gate All Around (GAA) devices [3-5], and Source/Drain (S/D) stressor layers which also allow to reduce the S/D contact resistance [3,6-8]. In this contribution we will describe the characteristics of the epitaxial growth schemes as used for Fin and Gate-All-Around (GAA) devices.
For Si- and SiGe-channel GAA devices, strained SiGe/Si multi-layers, which are used to define lateral nanowires, can be grown with conventional precursors (SiH4 or SiCl2H2 and GeH4). The compositional gradient is sufficiently steep to allow efficient wire release by selective SiGe or Si removal [2,5,9]. In case of Ge GAA, epitaxial growth of Ge-rich SiGe/Ge on SiGe Strain Relaxed Buffers is more challenging. Extremely low process temperatures are required to avoid strain relaxation. These layers need to be grown with higher order precursors, since conventional precursors become ineffective [4].
The epitaxial growth of ultra-thin Si layers on (strained) Ge fins or lateral nanowires used to passivate Ge surfaces in the high-k gate module has been discussed at the ECS Fall meeting of 2017 [10] and will not be covered in this presentation.
A major challenge is to increase the active doping concentration in epitaxial S/D layers. Current scaling of gate and fin pitch reduces contact area and the contact resistance becomes a key contributor to device parasitics [7,11]. In addition, monolithic 3D integration, requires to reduce the thermal budget of the complete epitaxial growth scheme (including pre-epi surface cleaning). For Si:P, we demonstrated that P doping activation can be increased by post-epi anneals (>1e21 cm-3) without major strain loss [8]. Nearly similar active doping concentrations (up to 8e20 cm-3) are obtained by using Si3H8 instead of SiCl2H2 and low growth temperatures without the need for a post epi thermal treatment. For SiGe:B, we obtained similar active boron concentrations using conventional precursors [12,13]. Because of the low boron solubility in Ge, it is more challenging to fabricate S/D Ge pMOS contacts with the right lattice constant (to act as a stressor) and with a sufficiently high active doping concentration. Effort is ongoing to increase the active boron concentration by moving the growth process further away from equilibrium. This is done at low growth temperatures by either using Ge2H6 as high-order precursor or by assessing new materials such as GeSn. On blanket wafers, higher active doping concentrations have been reported but it is extremely challenging to translate this into a selective growth process without Sn precipitation. This triggered the research community to assess alternative dopants. For Ge, the Ga doping solubility is significantly higher than that of B. Epitaxial growth schemes are preferred above ion implantation as the latter one requires an unwanted high thermal budget for doping activation and on patterned wafers it does not allow conformal doping profiles. First Ge:Ga layers with a resistivity below 0.4 mΩ.cm have been grown without any detectable C incorporation. In addition, Ga + B co-doping enables to reduce the resistivity of SiGe:B:Ga, which confirms the potential of Ga as an add-on.

Acknowledgements

The imec core CMOS program members, European Commission, the TAKEMI5 ECSEL project, local authorities and the imec pilot line are acknowledged for their support. Air Liquide Advanced Materials is acknowledged for providing advanced precursor gases.

References

[1] C. H. Lee et al., IEDM 2017, p. 820.
[2] H. Mertens et al., VLSI 2015, p. 142.
[3] L. Witters et al., IEEE Trans.
On Electr.
Dev.
64 (4), 4587 (2017).
[4] A. Hikavyy et al., Mater Sci Semicond Process
70, 24 (2017).
[5] H. Mertens et al., VLSI 2016, p. 158.
[6] K.D. Weeks et al., Thin Solid Films
520, 3158 (2012).
[7] E. Rosseel et al.,
ECS Trans.
75 (8), 347 (2016).
[8] A. Hikavyy et al., ECS Trans.,
60 (1), 497 (2014).
[9] K. Wostyn et al. ECS Trans. 69 (8), 147 (2015)
[10] R. Loo et al., ECS J. of Solid State Sci. Techn.
7 (2), P66 (2018).
[11] P. Raghavan et al., Proc.
IEEE Cust. Integr. Circuits Conf., p. 1 (2015).
[12] A. Hikavyy et al. ECS Trans.,
64 (6) 831 (2014),
[13] A. Hikavyy et al., Thin Solid Films
602, 77 (2016).