bluuebunny/crossref_metadata_2025_split huggingface dataset:
Microsecond Crystallization of Amorphous Silicon Films on Glass Substrates by Joule Heating
Authors: Hong Won-Eui , Ro Jae-Sang 
Published: February 2020

Abstract

Large area crystallization of amorphous silicon (a-Si) thin-films on glass substrates is one of the key technologies for manufacturing flat displays on commercial scales. Low-temperature polycrystalline silicon (LTPS) is a crucial active-layer material for polycrystalline silicon thin-film-transistors (poly-Si TFTs) mounted on thermally susceptible glass substrates. LTPS-TFT backplanes are required for fabricating flat panel displays such as active-matrix liquid-crystal-displays and active-matrix organic-light-emitting diodes (AMOLEDs). The LTPS-TFT backplanes are strongly preferred over a-Si TFTs since several devices, AMOLEDs in particular, operate in a current-driven mode. The crystallization methods used for producing LTPS include solid phase crystallization, metal induced crystallization, and excimer laser crystallization (ELC). The ELC method is currently used for crystallizing the a-Si films in mass production lines.
Recently, we developed a novel and highly promising crystallization method named Joule-heating induced crystallization (JIC) by which an entire a-Si film could be crystallized on a glass backplane within tens of microseconds. However, arc instability was observed during the crystallization, which is attributed to the dielectric breakdown in the conductor/insulator/a-Si sandwich-structures at high temperatures during electrical pulsing for crystallization. We devised a method for crystallizing the a-Si films while preventing arc generation; in this method an a-Si active layer was pre-patterned into islands followed by the deposition of a gate oxide and gate electrode. An electric pulse was then applied to the gate electrode formed using a Mo layer. The Mo-layer was used as a Joule-heat source for the crystallization of the pre-patterned active islands of the a-Si films located below the Mo-layer. The JIC-processed poly-Si TFTs were fabricated successfully and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.
In this report, we will discuss some critical issues concerning the arc generation, glass backplane deformation, and phase-transformation phenomena observed during the JIC process on the basis of theoretical investigations as well as in-situ and ex-situ experiments. Finally, we will discuss the procedure for fabricating stable JIC poly-Si TFTs and optimize the process flow and processing conditions such as the power density and pulsing time for fabricating the JIC poly-Si TFTS.

Figure 1
Charge-Trap Inactivation of Multi-Line-Beam Clc Poly-Si Tfts Using Channel Impurity Doping
Authors: Hiraiwa Mitsuhisa , Nguyen Thuy Thi , Kuroki Shin-Ichiro 
Published: February 2020

Linearly-arranged long silicon crystal grains have been formed by using Multi-Line-Beam Continuous-wave laser Lateral Crystallization (MLB-CLC). Crystallinity of the laser-crystallized poly-Si thin film are biaxially oriented to (110)-(111)-(211) crystal orientation. The low-temperature poly-Si thin film transistors (LTPS-TFTs), however have a high-OFF leakage current and ON/OFF ratio become small. Charge traps on the long grain boundaries between source and drain would induce the high-OFF leakage current. In this work, we introduce a channel doping for inactivation of the traps, and high ON/OFF ratio is achieved.
Poly-Si TFTs were fabricated as follows. Buffer SiO2 film (1 μm), a-Si (150 nm) and cap SiO2 (100 nm) were deposited on a quartz substrate. CW laser lateral crystallization with multi-line laser-beam spot was carried out on the a-Si films. The wavelength of the laser was 532 nm, and laser power and scan speed were 7.5 W and 0.5 cm/s, respectively. After the laser crystallization, the cap SiO2 was etched with buffered HF aqueous solution (BHF). In order to pattern the poly-Si active layer, lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm) were performed. Channel doping on channel region was carried out by boron (B) ions with 3 conditions (ion dose: 5×1012 cm-2, 7×1012 cm-2, 9×1012 cm-2, acceleration voltage: 19 keV). Gate SiO2 (42 nm) was deposited with ICP- CVD. Mo gate electrode (300 nm) was deposited by sputtering method. After resist patterning, the gate electrode was etched with an aqueous solution of H3PO4: HNO3: CH3COOH: H2O = 400: 25: 50: 25. A self-aligned S/D regions were formed by As ion doping (ion dose: 2×1015cm-2, acceleration voltage: 66 keV). Activation anneal was carried out at 550℃ in N2 ambient for 30 minutes. A sacrificial oxide layer in the S/D region was removed with BHF. After the removal, interlayer SiO2 film was deposited with APCVD. Contact holes were formed on the APCVD interlayer dielectric film with BHF. Mo metal pad was deposited by sputtering method, and finally the samples were sintered at 400°C in H2 ambient for 30 minutes. The IDS - VGS characteristic of the fabricated poly-Si TFTs are shown in Fig.1. As the boron impurity concentration increased, the off-leakage current was reduced. It is considered that boron impurity compensated the defect traps in the channel region. At the concentration of 1.3×1020 cm-3, the off leakage current at Vg=0 V was 3×10-11 A and ON/OFF ratio was 106. ON current was reduced by introducing the channel impurity. The electron field-effect mobilities for the boron impurities of 7.1×1019 cm-3, 1.0×1020 cm-3 and1.3×1020 cm-3 were 398, 333, and 261 cm2/Vs, respectively. By introducing boron impurity, the Coulomb scattering was occurred and the electron mobility was reduced.

Figure 1
Ultra-Thin Flexible Electronics with the Enhancement Inverter Based-on Pentacene Thin Film Transistor
Authors: Lee Dong-Hoon , Cho Hyeong Jun , Kim Min Su , Oh JongSu , Park Eng-kyu , Wang Sihan , Kim Yong-Sang 
Published: February 2020

Thin film technology is advancing the research on fully flexible system for new applications in various fields, such as electronics, sensors and energy harvesting. In particular, thin film transistor (TFT) based flexible circuits have been studied for diagnostic devices, solar-cells, and flexible display. Although many companies and research groups have presented semi-flexible devices; a fully flexible system has not shown the sufficient result in terms of mechanical and electrical performance. Recently, inorganic-organic hybrid type TFTs have been developed and it shows the useful performance. However, the devices show limited performance at extremely small bending radius (< 1mm). In order to overcome the limitations, many researchers have suggested various solutions such as new materials of high mechanical strength, neutral strain position fabrication and ultra-thin substrates. Among these solutions, ultra-thin substrate is promising in the field of smart-skin, implantable device and patch-type biosensor. Depending on the decreasing substrate thickness, the strain strength also decreases dramatically. In this study, we demonstrate a nm-level ultra-thin device based on pentacene TFT, using de-bonding-technology. For de-bonding, a double layer of PVA and PAA based water soluble release layer was spin coated on the glass substrate. Subsequently, we coated the buffer layer on the release layer. The Al as gate electrode was deposited on the buffer layer by thermal evaporation. PMMA was then spin-coated and baked at 100 °C for 30 min. The pentacene and gold layer was deposited using thermal evaporation. CYTOP material was used for the passivation of the device. Finally, the device was de-bonded in double deionized water followed by curing at 75 °C for 30 min. Based on this process, we fabricated the nm-level thick TFT and enhancement inverter. After de-bonding process, the nm-level ultra-thin device showed good performance compared with the initial device before de-bonding.
Investigation of High Current Tetracene-TFT Using Surface Nitrided SiO2 Gate Insulator Film
Authors: Nakao Hiroki , Hori Kabuto , Iwazaki Yoshitaka , Ueno Tomo 
Published: February 2020

The use of surface nitrided SiO2 film as gate insulator of tetracene-TFT (Thin Film Transistor) has been proposed. Using Ar/N2 plasma, the nitridation has been carried out on the SiO2 surface to remove carrier trapping sites due to hydroxyl groups. As a result, transistor output characteristics have been drastically improved with extremely high current level using tetracene film as organic semiconductor material.
Recently, there has been widely interested in organic-TFT because of its flexibility, ability to have a lot of material designs, applicability to large area devices and so on. However, the surface of conventional gate insulator such as SiO2and other metal oxide films often contain charge trapping sites due to the existence of hydroxyl (-OH) groups and surface defects. The carriers of organic-TFT have to move at the surface layer in the organic film adjacent to the gate insulator. Therefore it is important to control the surface and/or interface of organic film and gate insulator to avoid the carrier scattering at the charge trapping sites.
Now, commonly used method to overcome this problem is deposition of SAM (Self-Assembled-Monolayer) film on the gate insulator. As a result, it is reported that electrical characteristics have been drastically improved. But it takes time about at least half a day to deposit the SAM film.
In this paper, we have attempted to improve the carrier mobility in the tetracene film as organic semiconductor material, with surface nitride SiO2 film as the gate insulator for a short processing time. Figure1 shows transistor output characteristics with the channel length (L) = 70[um] and channel width (W) = 2000[um], respectively. It is clearly shown the extremely high current have been achieved from the tetracene-TFT on surface nitrided SiO2. On the contrary, no modulation due to gate bias could be achieved on SiO2film without the nitridation.
Also, to clarify the difference, the property of tetracene/SiO2 interface of each sample, C-V measurement has been carried out. After the nitridation have been done on the SiO2 surface that had been etched with dil-HF to make hydroxyl groups, the width of C-V hysteresis is decreased. Therefore we can conclude the surface nitridation of SiO2 films with Ar/N2 plasma is effective method to remove charge trapping sites related to hydroxyl groups and improve transistor output characteristics.

Figure 1
Heterostructure Source-Gated Transistors: Challenges in Design and Fabrication
Authors: Sporea Radu Alexandru , Jayawardena K. D. G. Imalka , Constantinou Marios , Ritchie Munroe , Brewin Alistair , Wright William , Silva S. Ravi P. 
Published: February 2020

Source-gated transistors (SGTs) [1, 2] use a potential barrier at the source to produce low-voltage saturation and flat saturated characteristics. This, in turn, results in excellent power efficiency and amplification performance [3-5].
Usually, SGTs are made with a Schottky source contact which acts as the current-control mechanism. These devices are easy to fabricate in a multitude of semiconductor systems, but may suffer, depending on design, from reduced dynamic range of the current above the threshold, and from significant temperature dependence of the on-current.
We propose an alternative method of making SGTs, using an ohmic source contact and a bulk barrier. We call devices realised following this principle bulk unipolar barrier source-gated transistors (BUSGTs). Several strategies for realising the bulk barrier exist, which depend on the material system and fabrication process considered [6].
Here, we realise the bulk barrier at the source with a tri-layer semiconductor heterostructure (Figure 1, top). The advantages of this architecture include improved dynamic range (Figure 1, bottom) and reduced temperature dependence of drain current, as well as the usual energy and gain characteristics of SGTs.
Measurement results on C70/C60/C70 n-type devices show: low hysteresis, indicating good quality interfaces; a large threshold shift due to the bulk barrier and residual charge in the heterostructure; and FET-like saturation, due to the interplay between semiconductor mobility and barrier height. A strong correlation is found between measurements and simulations using Silvaco Atlas.
We discuss the benefits of such structures, and also the fabrication and design challenges associated with this type of transistor (chemistry and materials, barrier realisation, interface properties, requirements on charge carrier mobility).
[1] S. D. Brotherton, Introduction to Thin Film Transistors: Physics and Technology of TFTs, Springer, 453–480, Cham (2013); [2] A. Valletta et al., J. Appl. Phys. 114 064501 (2013); [3] R. A. Sporea et al., Scientific Reports
4 4295 (2014); [4] R. A. Sporea, ULSI vs TFT V (2015); [5] R. A. Sporea et al., AA3.07, MRS Fall, Boston (2015); [6] J. M. Shannon, APL 35 (1) 63–65 (1979).
Figure 1 – Top: fabricated tri-layer fullerene heterostructure, showing the position of the bulk barrier at the source; bottom: transfer characteristic of the fabricated devices, illustrating high dynamic range above threshold, low hysteresis, and significant threshold shift as due to the bulk barrier.

Figure 1
Amplifier Circuit with Oxide TFT
Authors: Han Ye Lin , Kang In Hye , Jeon Young Eun , Lee Young Jin , Bae Byung Seong 
Published: February 2020

Oxide TFT (thin film transistor) has higher electron mobility and less leakage current than amorphous silicon TFT. Among oxide TFTs such as ZnO, InZnO, InGaZnO and so on, the IGZO TFT has being studied by many researchers and being used in the display backplane. In this presentation, an amplifier circuit with oxide TFTs was developed for the higher voltage gain.
Most commonly used type of power amplifier is the Class A Amplifier. The Class A amplifier is the most common and simplest form of power amplifier, in which transistor is always biased on-state so that it conducts during one complete cycle of the input signal waveform producing minimum distortion and maximum amplitude to the output. The efficiency of this type of circuit is low and delivers small power outputs.
To get high amplification gain, we designed an amplifier circuit based on inverter and optimized the channel width of each TFTs. The circuit developed is a common source amplifier, which is a single transistor amplifier that the input terminal is the gate and the source, output terminal is the drain and the source. In that type of amplifier circuit, the ratio of the widths of load transistor and drive transistor should be optimized for the highest gain. The DC operating voltage for the input gate electrode is also important, and the conventional way to get the operation voltage is using resistor divider, in which we should design the resistor divider according to the characteristics of TFT. In this presentation, we proposed the auto setting operation voltage scheme instead of resistor divider, and obtained the voltage gain of 14.
The Oxide TFT with Solution Based Gate Insulator
Authors: Hong Min-Taek , Shin Seong Min , Lee Jong mo , Jacques Emmanuel , Mohammed-Brahim Tayeb , Bae Byung Seong 
Published: February 2020

Low temperature poly-Silicon (LTPS) thin film transistor (TFT) and Oxide TFT are developed for the better performance of the active matrix display. Recently, oxide TFT has been investigated intensively due to simple process and higher mobility than amorphous silicon TFT.
Typical parameters of TFT are mobility, threshold voltage and On/Off ratio which are influenced by gate insulator. The widely used material for gate insulator is SiO2 which is rich in the earth and inexpensive. But vacuum equipments like the plasma enhanced chemical vapor deposition (PECVD) and the RF Magnetron sputter need large investment and maintenance cost than non-vacuum process.
Oxide TFT of top gate structure reduces the parasitic capacitance between source-drain and gate metal. The plasma damage during deposition of gate insulator on an oxide active layer cause the defects which deteriorate TFT characteristics. However, the gate insulator by solution process reduces the defects by plasma process.
SU-8 which is a negative photoresist (PR) has been being used widely in micro electro mechanical system (MEMS). It is constituted with octuple epoxy groups and includes photosensitize to react with UV light. The polymer network generated by cross-linking has mechanical and chemical stabilities and high electrical resistance. In this experiments, SU-8 was used for the gate insulator of the oxide TFT and investigated the effect of the SU-8 gate insulator on the oxide TFT.
In this paper, we investigated the characteristics of gate insulator of SU-8 as changing UV exposure time to SU-8. SU-8 was coated by spin coating with 2000 rpm on a p-type Si wafer. After soft-bake for 1.5 min at 95˚C, UV of 365 nm was exposed at an energy of 320mJ/s. Exposure times were varied as 30s, 60s, 120s, and 240s. After UV exposure, hard bake was done for 20 min at 115˚C. An Al layer was deposited on SU-8, and electrical properties of the SU-8 were measured after post-annealing.
Figure 1 shows the current densities of the SU-8 insulators for various exposure time from 30s to 240s. As shown in Fig. 1, the leakage currents decreased as the exposure time increased from 30s to 240s. For the gate insulator of the oxide TFT, the proper UV exposure is important.

Figure 1
Operational Amplifier Circuits with Oxide Thin Film Transistors
Authors: Kang In Hye , Hwang Jun Young , Hong Min-Taek , Lee Jong Mo , Bae Byung Seong 
Published: February 2020

Amorphous silicon thin film transistors (TFTs) have been used widely due to good uniformity and low process cost. However, They are not suitable for a circuit due to the low carrier mobility. Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistor (a-IGZO TFT) exhibits higher mobility and lower leakage current than amorphous silicon TFT and it is common to use only n-type a-IGZO TFT due to a poor electrical property of p-type TFT. In this paper, we developed operational amplifier (op-amp) circuit using only the n-type a-IGZO TFTs.
Recently, medical device circuits for measuring bio-signals are being implemented on a wearable devices. Oxide TFTs are suitable for the integrated circuit for such applications. The analog signal processing such as amplification, and filtering of much noise are necessary for analog electrical signals introduced from bio-sensors.
The op-amp is most widely used amplifiers due to ideal linear performance characteristics. An op-amp is composed of two input voltages (+Vin, -Vin), two power supply voltages (+VDD, -VDD) and one output voltage (Vout). It amplifies the voltage difference between the two input voltages of the non-inverting and inverting inputs (+Vin, -Vin).
The op-amp with a-IGZO TFTs has lower gain than that of the op-amp by CMOS process and need increase of the gain by cascaded amplifier stages. We developed a single power supply (+VDD = +15V) OP amp with improved gain. The circuit is composed of three stages: the first is differential amplifier(T1~T8) of input stage, the second is common-source amplifier(T9~T17), and the third is output buffer(T18~T19) of the output stage.
The differential amplifier of the first stage amplified the differential voltage for given input signals (+Vin, -Vin). The output voltage was amplified at the common-source amplifier stage of the second stage. Common-source amplifiers were used for a large voltage gain. After optimization of the circuits, the input voltage of 0.05V was amplified to about 13V.
Improvement of Stress Stability in Back Channel Etch-Type Thin Film Transistors with Post Process Annealing
Authors: Ochi Mototaka , Hino Aya , Goto Hiroshi , Hayashi Kazushi , Kugimiya Toshihiro 
Published: February 2020

Because of their superior performances to amorphous silicon (a-Si) semiconductors, amorphous oxide semiconductors have been attracting considerable attentions as backplanes for liquid crystal displays (LCDs) and organic light emitting diode displays (OLEDs). For mass production, the back channel etch (BCE)-type TFTs have considerable advantages owing to lesser process steps, lesser parasitic capacitances and shorter channel length than those of the etch stop layer (ESL)-type TFTs. However, the BCE-type TFTs often suffer from the unstable TFT operation against the transfer conditions and the various stress conditions due to the back channel damages to the oxide semiconductor [1-3]. Our study clearly demonstrates an addition of annealing process (post-annealing) that acts as recovery annealing is effective between SiNx deposition and SiOx deposition as passivation layer for the BCE-type TFTs application. The post-annealing effect to improve the stability of the BCE-type TFTs is investigated.
The Oxide TFTs were fabricated on glass substrates with gate electrodes and gate insulator. The IGZO (Indium Gallium Zinc Oxide) thin film was deposited on the substrate by DC magnetron sputtering. Next, source and drain electrodes were formed by wet-etching process using a H2O2-based etchant. The passivation layer composed of double layered SiNx/SiOx was formed by PECVD, and some samples were treated with the aforementioned post-annealing at 300 ℃ in air during the passivation layer formation. It is confirmed that the stability under the negative bias thermal illumination stress (NBTIS) of the BCE-type TFTs with the post-annealing was superior to that of the BCE-type TFT without the post-annealing. In order to clarify the variation of the chemical composition of the IGZO thin film surfaces due to the post-annealing, X-ray Photoelectron Spectroscopy (XPS) was examined as well as electronic state analysis such as photoinduced transient spectroscopy (PITS) [4,5].
[1] G. Wang, Z. Song, X. Xiao, and S. Zhang; AM-FPD 2015 Symposium Digest, pp.111.
[2] M. Nag, A. Bhoolokam, S. Steudel, A. Chasin, K. Myny, J. Maas, G. Groeseneken, and P. Heremans; Jpn. J. Appl. Phys, Vol. 53, No. 11, 111401 (2014).
[3] R. Zhan, C. Dong, P.-T. Liu, and an H.-P. D. Shieh; Microelectronics Reliability, 53, pp.1879 (2013).
[4] J. C. Balland, J. P. Zielinger, M. Tapiero, J. G. Gross, and C. Noguet; J. Phys. D: Appl. Physics, Vol. 19, No. 1 (1986).
[5] A. Hino, Y. Takanashi, H. Tao, S. Morita, M. Ochi, H. Goto, K. Hayashi, and T. Kugimiya; J. Vac. Sci. Technol. B 32 (2014) 031210.

Figure 1