Analysis of Lattice Damage in Annealed 4H-SiC Epiwafers after Heated Implantation with High Energy Al Ions
Authors: Chen Zeyu , Cheng Qianyu , Hu Shanshan , Raghothamachar Balaji , Ghandi Reza , Kennerly Stacey , Carlson Charles , Steski Dannie , Dudley Michael 
Published: December 2024

Silicon Carbide (SiC) is a semiconductor with a wide bandgap having substantial potential for power devices. Its characteristics, including wide bandgap, high breakdown voltage, and thermal stability, enable SiC devices to operate in severe conditions such as high temperature, voltage, and high frequency [1]. High voltage devices made of 4H-SiC, capable of withstanding 1.7 to 6.5 kV, are sought for in uses like hybrid systems, shipboard and power grid systems, and high-speed trains. These devices are typically produced on 4H-SiC wafers with thick epilayers to enhance breakdown voltages [2], but achieving uniform doping in such thick epilayers is challenging. One solution is to employ multi-step high energy ion implantation system established at Brookhaven National Laboratory’s Tandem Van de Graaff accelerator facility [3], which can conduct the implantation at energies up to 150 MeV. This system has been used to demonstrate medium voltage charge balance devices, 2 kV and 3.8 kV superjunction structure PIN diodes [4-6]. However, high energy ion implantation causes significant lattice strain by displacing host atoms in the epilayer, so it is crucial to characterize the strain to understand the damage induced by high energy implantation. Further the process of implantation and subsequent activation annealing must be optimized to completely heal lattice damage.
Previously, the distribution of strain within the 12 µm epilayer of a 4H-SiC epiwafer, implanted with high energy Al ions at a dose of 5.56 x 1013 cm-2 at room temperature, was characterized using synchrotron X-ray plane wave topography (SXPWT) and reciprocal space mapping (RSM). The analysis revealed that the strain level in the implanted region was approximately 2.5 x 10-4 higher than in the unimplanted region [7], as depicted in Fig.1 (a). The intensity profile obtained from the topograph was fitted using Rocking Curve Analysis by Dynamical Simulation (RADS) (Fig. 1(b)), and corresponding strain profile within the epilayer (Fig.1 (c)) also indicate a maximum strain of about 2.4 x 10-4. To completely alleviate this strain, an annealing temperature as high as 2000 °C is required [8]. However, such elevated temperature results in the wafers having rough surfaces, which is undesirable for device fabrication. One strategy to reduce the annealing temperature involves conducting high energy implantation at elevated temperatures, as the dynamic annealing effect can partially reduce the lattice strain in the as-implanted wafer. 4H-SiC epiwafers implanted at room temperature (RT), 300 °C, and 600 °C with a dose of 5 x 1016 cm-3 were characterized by RSM, as illustrated in Fig. 1(d). The strain estimated from vertical peak separation was 4.1 x 10-4, 3.3 x 10-4, and 2.0 x 10-4 for wafers implanted at RT, 300°C, and 600°C, respectively. The reduction of strain with increasing implantation temperature indicates that the dynamic annealing process was successfully initiated. These wafers will undergo activation annealing at standard temperatures, and the lattice strain will be measured and analyzed. The effectiveness of high temperature implantation will be assessed through these studies and reported in this paper.
Reference:
[1] J. Guo, Y. Yang, B. Raghothamachar, T. Kim, M. Dudley, J. Kim, J. Cryst. Growth 480 119-125. (2017)
[2] T. Liu, S. Hu, J. Wang, G. Guo, J. Luo, Y. Wang, J. Guo and Y. Huo, IEEE Access, 7 145118-145123. (2019)
[3] P. Thieberger, C. Carlson, D. Steski, R. Ghandi, A. Bolotnikov, D. Lilienfeld, P. Losee, Nucl. Instrum. Methods Phys. Res. B: Beam Interact. Mater. At. 442 36-40. (2019)
[4] R. Ghandi, C. Hitchcock, S. Kennerly, ECS Transactions 104 67 (2021)
[5] R. Ghandi, A. Bolotnikov, S. Kennerly, C. Hitchcock, P.-m. Tang, T.P. Chow, 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), IEEE, 126-129 (2020)
[6] R. Ghandi, C. Hitchcock, S. Kennerly, M. Torky and T. P. Chow, 2022 International Electron Devices Meeting (IEDM), pp. 9.1.1-9.1.4 (San Francisco, CA, USA, 2022)
[7] Z. Chen, H. Peng, Y. Liu, Q. Cheng, S. Hu, B. Raghothamachar, M. Dudley, R. Ghandi, S. Kennerly and P. Thieberger, Materials Science Forum 1062, 361-365 (2022)
[8] Z. Chen, Y. Liu, H. Peng, Q. Cheng, S. Hu, B. Raghothamachar, M. Dudley, R. Ghandi, S. Kennerly and P. Thieberger, ECS J. Solid State Sci. Technol. 11 065003 (2022)

Figure 1