bluuebunny/crossref_metadata_2025_split huggingface dataset:
Identification and Analysis of Parasitic Depletion Mode Leakage in a Memory Select Transistor
Authors: Colvin Jim B. , Roy Anirban 
Published: December 2020

Abstract
Low yield was reported for a non-volatile embedded memory array. In one case, the n-channel transistor was observed to exhibit single bit OFF leakage in a 32K array. In another case, there was general leakage observed between drain junctions of neighboring transistors, even though these were isolated by field oxide. The objective of the failure analysis described in this article was to characterize the electrical behavior of the leakage and determine the exact location and cause of the leakage. Focused Ion Beam was used to make electrical contact to drain regions, which lacked a contact for microprobing. Once the electrical parameters were obtained, photoemission analysis was performed with modified probes for higher spatial resolution to pinpoint the leakage path. Finally, scanning capacitance microscopy methods were used to prove the presence of the n-type depletion path. Very clear and positive confirmation of the presence of the parasitic n-type dopant was confirmed.
Electronic Package Failure Analysis Using TDR
Authors: Smolyansky Dima A. 
Published: December 2020

Abstract
The visual nature of Time Domain Reflectometry (TDR) makes it a very natural technology that can assist with fault location in BGA packages, which typically have complex interweaving layouts that make standard failure analysis techniques, such as acoustic imaging and X-ray, less effective and more difficult to utilize. This article discusses the use of TDR for package failure analysis work. It analyzes in detail the TDR impedance deconvolution algorithm as applicable to electronic packaging fault location work, focusing on the opportunities that impedance deconvolution and the resulting true impedance profile opens up for such work. The article examines the TDR measurement accuracy and the comparative package failure analysis, and presents three main considerations for package failure analysis. It also touches upon the goal and the task of the failure analysts and TDR's specific signatures for the open and short connections.
Failure Analysis of Tungsten Stud Defect from the CMP Process
Authors: Takagi K. , Kohno Y. , Nukii S. 
Published: December 2020

Abstract
This paper describes a failure analysis that effectively combined multiple analytic techniques to find the cause of I/O leakage in a flawed chip produced for an OEM (Original Equipment Manufacturer) product. Internal probing was initially used for defect isolation and a Tungsten (W) stud open circuit flaw was isolated by electrical characterization with internal probing. SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy, and FE-AES (Field Emission Auger Electron Spectroscopy) analysis with FIB (Focused Ion Beam) preparation were used for physical analysis. Cross-sectional SEM and TEM observations showed a gap with foreign material (FM) between the bottom of the metal line and the top of the W stud, possibly from the W CMP (chemical mechanical polish) process. FE-AES is effective for the analysis of light materials and their chemical composition, so a flat milling FIB process was used to prepare a cross-section for FE-AES analysis of the FM and the interfaces of the open defect. The spectra showed that the FM was traceable to the W CMP process. From these analytical results and problem reproduction experiments in the W CMP process on the manufacturing line, the failure mechanism was identified.
Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects
Authors: Wenger George M. , Coyle Richard J. , Solan Patrick P. , Dorey John K. , Dodd Courtney V. , Primavera Anthony , Erich Robert 
Published: December 2020

Abstract
A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.
High Temperature Solder (Au/Sn) Failures from Nickel Plating Impurities
Authors: Bunis Carl B. 
Published: December 2020

Abstract
High temperature gold/tin eutectic (80 Au/ 20 Sn) solder is used in manufacturing for multiple reasons. These motives may include the ability to post solder a part/device without reflow, high temperature field applications, and allow soldering to thick Au layers without the possibility of precipitating AuSn4 brittle intermetallics. In the following military case, Au/Sn eutectic was employed because of high temperature service and the guarantee of no occurrence of gold embrittlement when soldering to the thick Au outer plating. The Au was plated over an electroplated nickel (Ni) layer on a Kovar (iron/nickel/cobalt) housing. The soldering resulted in an extremely poor bond strength of a duroid circuit to the Kovar housing. The results showed contamination in the supplier’s electroplated Ni bath caused the plating to have poor bond strength. The failure occurred within the Ni plating layer.
Semiconductor Wear Out at Nuclear Power Plants
Authors: Riddle James B. 
Published: December 2020

Abstract
This paper will examine semiconductor wear out at San Onofre Nuclear Generation Station (SONGS). The topics will include case studies, failure mechanisms, diagnostic techniques, failure analysis techniques and root cause corrective actions. Nuclear power plants are unique in that instrumentation and control circuits are continuously energized, are periodically tested, and have been in operation for greater than 25 years. Root cause evaluations at SONGS have identified numerous semiconductor failures due to wear out. Case studies include light output deterioration in opto-isolators, junction alloying failures of transistors and integrated circuits and parametric shifts in operational amplifiers. In most cases the devices do not fail catastrophically but degraded to the point of circuit level functional failure. Failure analysis techniques include circuit analysis, board level troubleshooting to identify the degraded components. Intermittent failures require power cycling, thermal cycling, and long term monitoring to identify the responsible components. Corrective actions for semiconductor wear out at SONGS include enhanced monitoring and proactive change out of identified part types.
UTC Clinic Hospital Network: Description of International Network of Failure Analysis Labs and Case Studies
Authors: Wilkins Timothy C. 
Published: December 2020

Abstract
This paper describes the organization, process, and challenges of an international network of electrical and mechanical failure analysis labs that leverage lessons learned, resources, failure analysis techniques, and benchmarking of current common problems. Formed 11 years ago as just an electrical/electronic part failure analysis council within Otis Elevator and Carrier, this group has grown to be a network of 16 electrical and 22 mechanical labs. This council is a one of a kind network that also includes suppliers of parts to UTC. This paper will also illustrate the advantages of cross-functional and divisional leveraging with case study examples.
Specific Area Planar and Cross-Sectional Lift-Out Techniques: Procedures and Novel Applications
Authors: Rai Raghaw S. , Subramanian Swaminathan , Rose Stewart , Conner James , Schani Phil , Moss Jamey 
Published: December 2020

Abstract
Conventional focussed ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (&lt;0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.
Failure Analysis of a Transistor Lead
Authors: Deguchi Yasushi , Matsuda Sumio , Aoki Jiro , Tamura Takashi , Iwai Yasunobu , Kikui Shigeki 
Published: December 2020

Abstract
We investigated the cause of the whisker/discoloration which were found in the transistor lead of stocks (package type TO-18, low power use). In process of the investigation, we estimate two corrosion models that the first model is the remnant of sulfuric acid in cracks of the nickel-phosphorus plating layer in the transistor lead, the second model is the out-gassing or the dissolved ions from the stock container and conductive mat. As the results of the investigation which includes analyses of the whisker/discoloration cross section made by FIB (Focused Ion Beam), a reproductive experiment and so on, the whisker/discoloration were the corrosion reacted between the solder (Pb-Sn) on the transistor lead and SO42- ions of the stock container. We estimate that the new corrosion will not occur and grow in mounted devices because of rejecting the source of corrosion (stock containers). Further, in the worst case of the corrosion occurrence, protective coatings were applied to the mounted transistor lead, as the measure against falling away from the transistor lead.
Planar TEM Analysis of Nanoindented Samples Using the Focused Ion Beam Lift-Out Technique
Authors: Shofner T. L. , Brown S. R. , Rossie B.B. , Decker M. A. , Obeng Y. S. , Stevie F. A. , Drown J.L. 
Published: December 2020

Abstract
The focused ion beam system (FIB) has become a valuable tool for the preparation of transmission electron microscope (TEM) samples. Several FIB preparation techniques exist but of particular interest is the lift-out technique, which allows for the extraction of a thin membrane from a bulk material. This technique has seen great success in the preparation of cross sectional samples. We explore the use of this technique for planar sample preparation to examine grain deformation due to nanoindentation in a reference copper material.
Scanning SQUID Microscopy for New Package Technologies
Authors: Pacheco Mario , Wang Zhiyong 
Published: December 2020

Abstract
New package technologies are getting more complex, and thus isolating defects is becoming more challenging [1]. Analytical tools like Scanning SQUID Microscopes (SSM) are thus gaining relevance based on the capability to non-destructively detect electrical fails in very complex package technologies [2]. In this paper we report the use of SSM for the nondestructive isolation of electrical fails in novel microelectronic packages, where SSM has been found to be a unique fault isolation technique.
Fault Isolation of Large Nets Using Bridging Fault Analysis
Authors: Ontko George 
Published: December 2020

Abstract
Bridging faults are a common failure mechanism in integrated circuits and scan-based diagnosis does a good job of isolating these defects. Diagnosis, however, can sometimes result in large search areas. Typically, these areas are caused by long repeater nets. When this happens, physical failure analysis will become difficult or impossible. This paper concerns itself with using a bridging fault analysis as a means of reducing these large search areas.
Dislocation Induced Leakage of p+-Implanted ESD Test Macros in 90nm Technology
Authors: Zimmermann Gunnar , Riess Philipp , Chang W.T. , Tang Howard , Ou Homy , Cerva Hans 
Published: December 2020

Abstract
The introduction of p+ implanted areas at the drain side of source-drain-gate salicide-blocked electro-static discharge (ESD) protection diodes resulted in a better ESD robustness, however at the expense of increased leakage currents in up to 40% of the 90nm technology test structures. Leaky devices are found to be randomly distributed across a wafer. The leakage current exhibits only weak temperature dependence and is linearly increasing with the p-implanted area. Photoemission microscopy revealed spots located exclusively in the p+ implanted areas. TEM imaging visualized, that the leakage path is caused by dislocations, reaching from the silicon surface through the p+n junction zone into the substrate. Based on these results and the implant conditions, a theory of dislocation formation was postulated and countermeasures had been defined.
A Novel Approach for Enhancing Critical FIB Imaging for Failure Analysis and Circuit Edit Applications
Authors: Myers Joseph , Abramo Marsha , Anderson Michael , Phaneuf Michael W. 
Published: December 2020

Abstract
As semiconductor device features continue to decrease in size from merely sub micron to below 100 nanometers it becomes necessary to mill smaller and higher aspect ratio FIB vias with reduced ion beam current. This significantly reduces the number of secondary electrons and ions available for endpoint detection and imaging. In addition FIB gas assisted etching introduces a gas delivery nozzle composed of conductive material. This component is grounded to prevent charge build up during ion beam imaging or milling. The proximity of the nozzle to the sample surface creates a shielding effect which reduces the secondary electron detection level as well [1]. The ability to enhance secondary electron imaging for end point detection is required for successful FIB circuit edit and failure analysis applications on advanced technologies. This paper reviews the results obtained using FIB Assist, an image and signal enhancement product for the FEI / Micrion platform, for critical FIB endpoint determination. Examples of FIB fabricated probe points with 30 x 30 nm FIB vias and circuit edit applications endpointing on metal 1 with high aspect ratio holes are presented.
Timing Analysis of a Microprocessor PLL Using High Quantum Efficiency Superconducting Single Photon Detector (SSPD)
Authors: Song Peilin , Stellari Franco , Eckhardt James P. , McNamara Timothy , Tong Ching-Lung 
Published: December 2020

Abstract
This paper describes the analysis of a Phase-Locked Loop (PLL) internal phase detection circuit built in IBM’s 0.13 µm Silicon On Insulator (SOI) CMOS technology by using the Picosecond Imaging Circuit Analysis (PICA) [1,2] tool equipped with the high quantum efficiency Superconducting Single-Photon Detector (SSPD) [3,4]. Signals corresponding to the internal nodes of the PLL are for the first time measured and compared to circuit simulations in order to characterize the behavior of the different components of the circuit.
The Effect of Temperature and Strain Rate on Selected Lead-Free Solder Alloys
Authors: Vijayen Jayamalar , Maveety James G. , Allen Emily L. 
Published: December 2020

Abstract
The temperature and strain rate effects on the shear properties of selected Pb-free solders were investigated. The experiments were performed using single lap shear specimens. All testing was performed using a standard tensile test metrology. The following results were found: 1) Sn-3.5 wt.% Ag outperformed all the other solders in terms of its mechanical strength at all test conditions due to the formation of Ag3Sn precipitates in the bulk solder and Cu6Sn5 intermetallic formation along the interface. However, ductility was sacrificed as this solder strain hardens. 2) The strength and ductility of the solder joint is strongly dependent on the test temperature and strain rate. Data in this work reflects a decrease in strength and ductility when the test temperature is increased. This phenomenon can be attributed to the increase in energy as temperature is increased to overcome dislocation barriers such as impurities and grain boundaries that impede the motion of dislocation. When strain rate is increased, the amount of plastic deformation experienced by the solder increases and more dislocations are formed. Due to the increase in proximity and number of the dislocations, the net result is that motion of the dislocations are hindered thus requiring more stress to deform the material.
Measurement of Solder Joint Strength and Its Dependence on Thermal Aging in Freestanding and Board-Mounted Packages using a Laser Spallation Technique
Authors: Gupta Vijay , Tian Jun , Hartfield Cheryl , Zeng Kejun , Chiu Cheng , Stierman Roger 
Published: December 2020

Abstract
The continuing evolution of semiconductor packages to finer solder ball pitches, shrinking solder ball volume, and new solder materials, mandates the availability of methods to accurately assess solder joint reliability both at the component and at the board level. Many tests in use for this purpose cannot provide direct measurements of solder joint interfacial strength. This paper reports on the investigation of laser spallation for interfacial strength assessments and understanding of failure mechanisms on chip scale package (CSP) solder joints.
In-Line Repair of Detectable, Same-Level, Killer Defects Affecting IC Chips
Authors: Patterson Oliver D. , Shuttleworth David M. , Jamison Michelle , Albers Brad J. 
Published: December 2020

Abstract
In-line repair of same-level killer defects is suggested as a method of the future for achieving higher yields. A methodology describing selection of killer defects and how to repair them is presented. A proof of concept experiment is presented where killer defects are removed from comb test structures using a FIB. An economic analysis is also included which indicates that this technique is economically viable for more costly chip designs. Therefore additional development work is merited.
Characterization Complex Voltage Contrast Image Using Atomic Force Microscopy
Authors: Chen C.H. , Shen C.M. , Huang C.M. , Hsia Y.F. 
Published: December 2020

Abstract
The passive voltage contrast (PVC) in this experiment was widely used to detect open/short issues for most failure analyses. However, most of back-end particles were visible, but front-end particles were not. And sometimes only used PVC image, the failure mechanism was un-imaginable. As a result, we needed to collect some electrical data to explain complex PVC image, before physical failure analysis (PFA) was started. This paper shows how to use the scanning probe microscope (SPM) tool to make up PVC method and overcome the physical failure analysis challenge. From our experiment, the C-AFM could provide more information of the defect type and give faster feedback to production lines.
Precise Defect Localization of Scan Logic Failures by Thermal Laser Stimulation (TLS)
Authors: Qian Zhongling , Brillert Christof , Burmer Christian , Egger Peter 
Published: December 2020

Abstract
Scan design in modern advanced ICs has enabled the software-based fault diagnosis. It is a powerful tool for localization of defects. However, according to fault diagnosis, there are sometimes many defect candidates and each defect candidate can have many equivalent nets. These nets may be distributed widely, even over the whole chip. Therefore, an additional method of precise defect localization is needed as a complement. In this paper, the TLS method (Thermal Laser Stimulation) is utilized with a simplified setup for this purpose. It shows that the correlation between TLS inspection and scan diagnosis significantly saves analysis time due to the improvement of localization accuracy of the corresponding physical defect.
Correlation of Flash Memory Defects Detected With Passive and Active Localization Techniques
Authors: Quah A.C.T. , Phang J.C.H. , Li S. , Massoodi M. , Yuan C. , Koh L.S. , Chan K.H. , Chua C.M. 
Published: December 2020

Abstract
This article describes a series of experiments that were conducted on flash memory devices to correlate the defects that are detected by photon emission microscopy (PEM) and laser-induced techniques. Currently, there are two main categories of fault localization techniques for failure analysis, namely passive and active techniques. The article discusses defect localization by PEM and SOM. Three types of defects are described: Type 1 defects are those that can be accurately localized by both PEM and laser-induced techniques; Type 2 defects are defects which can only be detected with PEM and are not observable with laser-induced techniques; and Type 3 defects are those that are detectable with laser-induced techniques but cannot be detected by PEM. While PEM is able to capture the symptoms of existing leakage defects, laser-induced techniques can precisely localize temperature sensitive defects.
DuPont EKC265™ PERR as a Copper Metallization Etchant for the Physical Deprocessing of Failing 0.12 μm Technology Devices
Authors: Mulder Randal 
Published: December 2020

Abstract
DuPont EKC265 Post Etch Residue Remover has been available for many years as post reactive ion etch photo-resist etchant for semiconductor wafer processing. It has also proven useful for the physical analysis of failing semiconductor devices. This paper shows how EKC265 can be used as copper metallization wet etchant to aid in the physical deprocessing. It provides the EKC265 copper metallization etch results and physical deprocessing results using EKC265. An ancillary effect of wet etching copper metallization rather than removing by means of mechanical polishing is that only the thin layer of underlying barrier metal layer has to be removed by means of mechanical polishing. As the barrier metal is a metal-silicon nitride compound, the polishing rate to remove it is close to that of the surrounding oxide. Therefore, less total polishing time is required to remove the copper metallization layer when EKC is used.