Readout Circuit Design Using Experimental Data of Line-TFET Devices
Authors: Gonçalez Walter , Rangel Roberto , Martino Joao Antonio , Agopian Paula Ghedini Der 
Published: May 2020

Different applications in modern analog circuit design, ranging from Internet of Things to biosignal acquisition, require integrated circuits with minimum power consumption and circuit area. The line-tunneling transistor (Line-TFET) (1), an emerging device fabricated at imec/Belgium, depicted in Figure 1, presents characteristics that could help to overcome some of the issues that arise with the very tight design constraints imposed by modern analog applications. This device presents extremely high intrinsic voltage gain, which simplifies circuit topology, and low current levels that are suitable for low-power and low-frequency applications (2)(3). Moreover, TFETs have been shown to be resistant to noise (4) and temperature variation (5).
Readout circuits are frequently necessary in order to realize signal amplification of the outputs of a sensor or a sensor array within a determinate bandwidth. Circuit area is especially critical in implantable sensors, for instance, or in applications that use large sensor arrays, as the readout circuit must be replicated for each node (6). The reading error is inversely proportional to the amplifier’s gain, which is an important constraint when performing the acquisition of small signals (7). This fact results in a compromise between reading error and circuit area, as short MOSFET devices present small intrinsic voltage gain. Furthermore, in some applications of biosignal acquisition, such as EEG or ECG, the bandwidth of the bandpass amplifier must cover very small frequencies, thus often requiring big capacitance and resistance values in the closed-loop configuration, which greatly increases circuit area (6)(7). Therefore, this work proposes the use of Line-TFET devices in order to perform the design of a readout circuit with high gain (above 45dB, open-loop configuration) and bandwidth from f<1Hz (common mode suppression) to about f=100Hz. Device modeling was performed using lookup tables from experimental data for the DC characteristics while the parasitic capacitances were estimated through TCAD simulation. In order to simplify the analysis, P and N-type Line-TFET transistors are considered symmetric and gate leakage current was disregarded. The circuit was also designed with 130nm conventional MOSFET technology in order to make comparisons with the Line-TFET design.
Figure 2.a) shows the readout circuit including the pseudo-resistor structure using gate-source connected Line-TFET devices (8) and diode-connected MOSFETs, while Figure 2.b) shows the transistor level implementation of the operational amplifier. Pseudo resistors in the Line-TFET design require two transistors in parallel because of the unidirectionality of the current in these devices (8), while in the MOSFET design 6 diode-connected devices in series were necessary to increase the resistance. The gate dimensions of the input transistors is 100nm x 1µm and 250nm x 4µm for the Line-TFET and MOSFET designs, respectively. Figure 3 depicts the Bode diagram of gain and phase comparing both designs, while Table I summarizes the results. In the MOSFET design, the output and bias connections draw larger current, thus consuming more power. The lower transistor efficiency and higher Vdd for Line-TFETs hinder its power consumption because the Line-TFET is prone to degradation of the saturation region with low Vgs, especially for small devices, due to source-to-drain parasitic tunneling, and to transistor efficiency degradation because of trap and phonon assisted tunneling (2). However, the Line-TFET design presents 51dB open-loop DC gain, reducing the reading error in 2 times in comparison with the MOSFET design (45dB open-loop gain), while using a simple topology. Circuit area was greatly reduced when designing pseudo-resistors with Line-TFET devices as their drain current is proportional to the gate area, increasing the differential resistance of small devices. Therefore, it achieves up to 50 Gohm in a 120nm x 100nm device, which enables cut of frequencies below 1Hz while using nanometer devices and smaller capacitance values (Ci, Cn and Cl).
Table II exhibits the results of this work in comparison with other readout circuit designs. Even with higher Vdd and not biasing the devices in the subthreshold regime, the Line-TFET design achieves similar power consumption of some nW, thanks to the lower current level of this device, which is suitable for low-frequency amplifications. Greater intrinsic voltage gain and resistance to temperature variation of Line-TFETs allow the simplification of the topology, by using pseudo-resistors instead of a dc servo loop (DSL) in order to define a mHz high-pass corner frequency, a simple one-stage amplifier and smaller capacitors.

acknowledgment

The authors thank CAPES and FAPESP for the financial support and imec for supplying the samples.

Figure 1