bluuebunny/crossref_metadata_2025_split huggingface dataset:
Amyloid Beta42 oligomers up‐regulate the excitatory synapses by potentiating presynaptic release while impairing postsynaptic NMDA receptors
Authors: Marcantoni Andrea , Cerullo Maria Sabina , Buxeda Pol , Tomagra Giulia , Giustetto Maurizio , Chiantia Giuseppe , Carabelli Valentina , Carbone Emilio 
Published: April 2020

Key points

NMDA receptors (NMDARs) are key molecules for controlling neuronal plasticity, learning and memory processes. Their function is impaired during Alzheimer's disease (AD) but the exact consequence on synaptic function is not yet fully identified.
An important hallmark of AD onset is represented by the neuronal accumulation of Amyloid Beta42 oligomers (Abeta42) that we have recently shown to be responsible for the increased intracellular Ca2+ concentration through ryanodine receptors (RyRs).
Here we characterized the effects of Abeta42 on NMDA synapses showing specific pre‐ and post‐synaptic functional changes that lead to a potentiation of basal and synchronous NMDA synaptic transmission.
These overall effects can be abolished by decreasing Ca2+ release from RyRs with specific inhibitors that we propose as new pharmacological tools for AD treatment.

AbstractWe have recently shown that Amyloid Beta42 oligomers (Abeta42) cause calcium dysregulation in hippocampal neurons by stimulating Ca2+ release from ryanodine receptors (RyRs) and inhibiting Ca2+ entry through NMDA receptors (NMDARs). Here, we found that Abeta42 decrease the average NMDA‐activated inward current and that Ca2+ entry through NMDARs is accompanied by Ca2+ release from the stores. The overall amount of intraellular Ca2+ concentration([Ca2+]i) increase during NMDA application is 50% associated with RyR opening and 50% with NMDARs activation. Addition of Abeta42 does not change this proportion. We estimated the number of NMDARs expressed in hippocampal neurons and their unitary current. We found that Abeta42 decrease the number of NMDARs without altering their unitary current. Paradoxically, the oligomer increases the size of electrically evoked eEPSCs induced by NMDARs activation. We found that this is the consequence of the increased release probability (p) of glutamate and the number of release sites (N) of NMDA synapses, while the quantal size (q) is significantly decreased as expected from the decreased number of NMDARs. An increased number of release sites induced by Abeta42 is also supported by the increased size of the ready releasable pool (RRPsyn) and by the enhanced percentage of paired pulse depression (PPD). Interestingly, the RyRs inhibitor dantrolene prevents the increase of PPD induced by Abeta42 oligomers. In conclusion, Abeta42 up‐regulates NMDA synaptic responses with a mechanism involving RyRs that occurs during the early stages of Alzheimer's disease (AD) onset. This suggests that new selective modulators of RyRs may be useful for designing effective therapies to treat AD patients.
Kv3.1 and Kv3.3 subunits differentially contribute to Kv3 channels and action potential repolarization in principal neurons of the auditory brainstem
Authors: Choudhury Nasreen , Linley Deborah , Richardson Amy , Anderson Michelle , Robinson Susan W. , Marra Vincenzo , Ciampani Victoria , Walter Sophie M. , Kopp‐Scheinpflug Conny , Steinert Joern R. , Forsythe Ian D. 
Published: April 2020

Key points
Kv3.1 and Kv3.3 subunits are highly expressed in the auditory brainstem, with little or no mRNA for Kv3.2 or Kv3.4. Changes in Kv3 currents and action potential (AP) firing were analysed from wild‐type, Kv3.1 and Kv3.3 knockout (KO) mice.
Both Kv3.1 and Kv3.3 immunostaining was present and western blots confirmed loss of subunit protein in the respective KO.
Medial nucleus of the trapezoid body (MNTB) AP repolarization utilized Kv3.1 and/or Kv3.3; while in the lateral superior olive (LSO) Kv3.3 was essential.
Voltage‐gated calcium currents were unchanged between the genotypes. But APs evoked higher [Ca2+]i in LSO than MNTB neurons; and were highest in the Kv3.3KO, consistent with longer AP durations.
High frequency stimulation increased AP failure rates and AP latency in LSO neurons from the Kv3.3KO, underlining the physiological consequences for binaural integration.
LSO neurons require Kv3.3 for functional Kv3 channels, while MNTB neurons can utilize either Kv3.1 or Kv3.3 subunits.AbstractKv3 voltage‐gated potassium channels mediate action potential (AP) repolarization. The relative importance of Kv3.1 and Kv3.3 subunits for assembly of functional channels in neurons of the auditory brainstem was examined from the physiological perspective that speed and precision of AP firing are crucial for sound source localization. High levels of Kv3.1 and Kv3.3 mRNA and protein were measured, with no evidence of compensation by Kv3.2 or Kv3.4 in the respective knockout (KO) mouse. Using the KOs, composition of Kv3 channels was constrained to either Kv3.1 or Kv3.3 subunits in principal neurons of the medial nucleus of the trapezoid body (MNTB) and lateral superior olive (LSO); while TEA (1 mm) was employed to block Kv3‐mediated outward potassium currents in voltage‐ and current clamp experiments. MNTB neuron APs (half‐width 0.31 ± 0.08 ms, n = 25) were fast, reliable, and showed no distinction between channels assembled from Kv3.1 or Kv3.3 subunits (in the respective KO). LSO AP half‐widths were also fast, but absolutely required Kv3.3 subunits for fast repolarization (half‐widths: 0.25 ± 0.08 ms, n = 19 wild‐type, 0.60 ± 0.17 ms, n = 21 Kv3.3KO, p = 0.0001). The longer AP duration increased LSO calcium influx and AP failure rates, and increased AP latency and jitter during high frequency repetitive firing. Both Kv3.1 and Kv3.3 subunits contribute to Kv3 channels in the MNTB (and compensate for each other in each KO); in contrast, LSO neurons require Kv3.3 subunits for fast repolarization and to sustain AP firing during high frequency stimulation. In conclusion, Kv3 channels exhibit both redundancy and Kv3.3 dominance between the brainstem nuclei involved in sound localization.
Induction and Regulation of Th1-Inducing Cytokines by Bacterial DNA, Lipopolysaccharide, and Heat-Inactivated Bacteria
Authors: Huang L.-Y. , Krieg A. M. , Eller N. , Scott D. E. 
Published: April 2020

ABSTRACTTh1 immune responses, characterized by production of gamma interferon (IFN-γ), are associated with protective immunity to viruses and intracellular bacteria. Heat-killedBrucella abortuspromotes secretion of Th1-inducing cytokines such as interleukin-12 (IL-12) and IFN-γ and has been used as a carrier to induce Th1 responses to vaccines. To explore which bacterial constituents could mediate this response and how it is regulated, murine spleen cells were cultured withB. abortusderived DNA, lipopolysaccharide (LPS), or whole killed organisms. Each constituent induced similar, substantial amounts of IL-10. However, onlyB. abortusandB. abortusDNA induced high levels of IFN-γ and IL-12.B. abortusandB. abortusDNA-stimulated IL-12 production was maximal by 6 to 18 h, while IL-10 production steadily accumulated over this time period. These kinetics suggested that IL-10 may eventually downmodulate the Th1-like cytokine response toB. abortusandB. abortusDNA, which was confirmed by using neutralizing antibody. In the absence of IL-10,B. abortusLPS induced strong IFN-γ responses, but IL-12 p70 levels were still undetectable from BALB/c spleen cells. LPS induced IL-12 if the spleen cells were primed with IFN-γ and IL-10 was neutralized, indicating that LPS can stimulate IL-12 production under the most favorable conditions. Responses toEscherichia coliLPS and DNA mirrored the responses toB. abortuscomponents, suggesting that immune effects observed with these constituents may be generalizable to many microbial species. In vivo experiments demonstrated the same hierarchy of responses for IL-12 production. These findings support the likelihood that microbial components, if used as carriers or adjuvants, can differ substantially in their ability to effect a Th1 response.
Selective Recruitment of T-Cell Subsets to the Udder during Staphylococcal and Streptococcal Mastitis: Analysis of Lymphocyte Subsets and Adhesion Molecule Expression
Authors: Soltys Jindrich , Quinn Mark T. 
Published: April 2020

ABSTRACTDuring bacterial infection of the bovine mammary gland, large numbers of leukocytes migrate into the udder, resulting in the establishment of a host response against the pathogen. Currently, the specific leukocyte populations mediating this immune response are not well defined. In the studies described here, we analyzed blood and milk from healthy cows and cows with naturally occurring mastitis to determine if distinct αβ and γδ T-lymphocyte subsets were involved in the response of the udder to a mastitis pathogen and if the type of mastitis pathogen influenced the subset composition of these responding leukocytes. Although blood samples from cows with confirmed staphylococcal and streptococcal mastitis were characterized by increased numbers of γδ T cells, the most dramatic changes in leukocyte distributions occurred in milk samples from these cows, with a 75% increase in αβ T-cell levels and a 100% increase in γδ T-cell levels relative to the levels in milk samples from healthy animals. Interestingly, the increase in αβ T-cell numbers observed in milk from cows with staphylococcal mastitis was primarily due to increased numbers of CD4+T cells, while the increase in αβ T-cell numbers observed in cows with streptococcal mastitis was due to a parallel increase in both CD4+and CD8+T-cell numbers. The increased numbers of γδ T cells in milk from cows with staphylococcal and streptococcal mastitis were due to a selective recruitment of a distinct γδ T-cell subset (GD3.1+), while no change in the numbers of GD197+γδ T cells was observed. We also analyzed adhesion protein expression on blood and milk leukocytes and found that, in comparison to the situation for healthy cows, L-selectin was down-regulated and CD18 was up-regulated on leukocytes from cows with mastitis. Thus, shedding of L-selectin and up-regulation of CD18 by neutrophils may provide a sensitive indicator of early inflammatory responses during bovine mastitis. Overall, these studies suggest that distinct αβ and γδ T-cell subsets are involved in the host defense of the udder against mastitis infection and that selective recruitment of these T-cell subsets depends on the infectious agent involved.
Subtyping and intersection types revisited
Authors: Pfenning Frank 
Published: April 2020

Church's system of simple types has proven to be remarkably robust: call-by-name, call-by-need, and call-by-value languages, with or without effects, and even logical frameworks can be based on the same typing rules. When type systems become more expressive, this unity fractures. An early example is the value restriction for parametric polymorphism which is necessary for ML but not Haskell; a later manifestation is the lack of distributivity of function types over intersections in call-by-value languages with effects.
In this talk we reexamine the logical justification for systems of subtyping and intersection types and then explore the consequences in two different settings: logical frameworks and functional programming.
In logical frameworks functions are pure and their definitions observable, but complications could arise from the presence of dependent types. We show that this is not the case, and that we can obtain soundness and completeness theorems for a certain axiomatization of subtyping. We also sketch a connection to the type-theoretic notion of proof irrelevance.
In functional programming we investigate how the encapsulation of effects in monads interacts with subtyping and intersection types, providing an updated analysis of the value restriction and related phenomena. While at present this study is far from complete, we believe that its origin in purely logical notions will give rise to a uniform theory that can easily be adapted to specific languages and their operational interpretations.
Loop-aware optimizations in PyPy's tracing JIT
Authors: Ardö Håkan , Bolz Carl Friedrich , FijaBkowski Maciej 
Published: April 2020

One of the nice properties of a tracing just-in-time compiler (JIT) is that many of its optimizations are simple, requiring one forward pass only. This is not true for loop-invariant code motion which is a very important optimization for code with tight kernels. Especially for dynamic languages that typically perform quite a lot of loop invariant type checking, boxed value unwrapping and virtual method lookups. In this paper we explain a scheme pioneered within the context of the LuaJIT project for making basic optimizations loop-aware by using a simple pre-processing step on the trace without changing the optimizations themselves.
We have implemented the scheme in RPython's tracing JIT compiler. PyPy's Python JIT executing simple numerical kernels can become up to two times faster, bringing the performance into the ballpark of static language compilers.
HOTL
Authors: Xiang Xiaoya , Ding Chen , Luo Hao , Bao Bin 
Published: April 2020

The locality metrics are many, for example, miss ratio to test performance, data footprint to manage cache sharing, and reuse distance to analyze and optimize a program. It is unclear how different metrics are related, whether one subsumes another, and what combination may represent locality completely.
This paper first derives a set of formulas to convert between five locality metrics and gives the condition for correctness. The transformation is analogous to differentiation and integration used to convert between higher order polynomials. As a result, these metrics can be assigned an order and organized into a hierarchy.
Using the new theory, the paper then develops two techniques: one measures the locality in real time without special hardware support, and the other predicts multicore cache interference without parallel testing. The paper evaluates them using sequential and parallel programs as well as for a parallel mix of sequential programs.
To hardware prefetch or not to prefetch?
Authors: Kang Hui , Wong Jennifer L. 
Published: April 2020

Most hardware and software venders suggest disabling hardware prefetching in virtualized environments. They claim that prefetching is detrimental to application performance due to inaccurate prediction caused by workload diversity and VM interference on shared cache. However, no comprehensive or quantitative measurements to support this belief have been performed.
This paper is the first to systematically measure the influence of hardware prefetching in virtualized environments. We examine a wide variety of benchmarks on three types of chip-multiprocessors (CMPs) to analyze the hardware prefetching performance. We conduct extensive experiments by taking into account a number of important virtualization factors. We find that hardware prefetching has minimal destructive influence under most configurations. Only with certain application combinations does prefetching influence the overall performance.
To leverage these findings and make hardware prefetching effective across a diversity of virtualized environments, we propose a dynamic prefetching-aware VCPU-core binding approach (PAVCB), which includes two phases - classifying and binding. The workload of each VM is classified into different cache sharing constraint categories based upon its cache access characteristics, considering both prefetch requests and demand requests. Then following heuristic rules, the VCPUs of each VM are scheduled onto appropriate cores subject to cache sharing constraints. We show that the proposed approach can improve performance by 12% on average over the default scheduler and 46% over manual system administrator bindings across different workload combinations in the presence of hardware prefetching.
OWL
Authors: Jog Adwait , Kayiran Onur , Chidambaram Nachiappan Nachiappan , Mishra Asit K. , Kandemir Mahmut T. , Mutlu Onur , Iyer Ravishankar , Das Chita R. 
Published: April 2020

Emerging GPGPU architectures, along with programming models like CUDA and OpenCL, offer a cost-effective platform for many applications by providing high thread level parallelism at lower energy budgets. Unfortunately, for many general-purpose applications, available hardware resources of a GPGPU are not efficiently utilized, leading to lost opportunity in improving performance. A major cause of this is the inefficiency of current warp scheduling policies in tolerating long memory latencies.
In this paper, we identify that the scheduling decisions made by such policies are agnostic to thread-block, or cooperative thread array (CTA), behavior, and as a result inefficient. We present a coordinated CTA-aware scheduling policy that utilizes four schemes to minimize the impact of long memory latencies. The first two schemes, CTA-aware two-level warp scheduling and locality aware warp scheduling, enhance per-core performance by effectively reducing cache contention and improving latency hiding capability. The third scheme, bank-level parallelism aware warp scheduling, improves overall GPGPU performance by enhancing DRAM bank-level parallelism. The fourth scheme employs opportunistic memory-side prefetching to further enhance performance by taking advantage of open DRAM rows. Evaluations on a 28-core GPGPU platform with highly memory-intensive applications indicate that our proposed mechanism can provide 33% average performance improvement compared to the commonly-employed round-robin warp scheduling policy.
Portable performance on heterogeneous architectures
Authors: Phothilimthana Phitchaya Mangpo , Ansel Jason , Ragan-Kelley Jonathan , Amarasinghe Saman 
Published: April 2020

Trends in both consumer and high performance computing are bringing not only more cores, but also increased heterogeneity among the computational resources within a single machine. In many machines, one of the greatest computational resources is now their graphics coprocessors (GPUs), not just their primary CPUs. But GPU programming and memory models differ dramatically from conventional CPUs, and the relative performance characteristics of the different processors vary widely between machines. Different processors within a system often perform best with different algorithms and memory usage patterns, and achieving the best overall performance may require mapping portions of programs across all types of resources in the machine.
To address the problem of efficiently programming machines with increasingly heterogeneous computational resources, we propose a programming model in which the best mapping of programs to processors and memories is determined empirically. Programs define choices in how their individual algorithms may work, and the compiler generates further choices in how they can map to CPU and GPU processors and memory systems. These choices are given to an empirical autotuning framework that allows the space of possible implementations to be searched at installation time. The rich choice space allows the autotuner to construct poly-algorithms that combine many different algorithmic techniques, using both the CPU and the GPU, to obtain better performance than any one technique alone. Experimental results show that algorithmic changes, and the varied use of both CPUs and GPUs, are necessary to obtain up to a 16.5x speedup over using a single program configuration for all architectures.
DDOS
Authors: Hunt Nicholas , Bergan Tom , Ceze Luis , Gribble Steven D. 
Published: April 2020

Nondeterminism complicates the development and management of distributed systems, and arises from two main sources: the local behavior of each individual node as well as the behavior of the network connecting them. Taming nondeterminism effectively requires dealing with both sources.
This paper proposes DDOS, a system that leverages prior work on deterministic multithreading to offer: 1) space-efficient record/replay of distributed systems; and 2) fully deterministic distributed behavior. Leveraging deterministic behavior at each node makes outgoing messages strictly a function of explicit inputs. This allows us to record the system by logging just message's arrival time, not the contents. Going further, we propose and implement an algorithm that makes all communication between nodes deterministic by scheduling communication onto a global logical timeline.
We implement both algorithms in a system called DDOS and evaluate our system with parallel scientific applications, an HTTP/memcached system and a distributed microbenchmark with a high volume of peer-to-peer communication. Our results show up to two orders of magnitude reduction in log size of record/replay, and that distributed systems can be made deterministic with an order of magnitude of overhead.
On the treeness of internet latency and bandwidth
Authors: Ramasubramanian Venugopalan , Malkhi Dahlia , Kuhn Fabian , Balakrishnan Mahesh , Gupta Archit , Akella Aditya 
Published: April 2020

Existing empirical studies of Internet structure and path properties indicate that the Internet is tree-like. This work quantifies the degree to which at least two important Internet measures--latency and bandwidth--approximate tree metrics. We evaluate our ability to model end-to-end measures using tree embeddings by actually building tree representations. In addition to being simple and intuitive models, these trees provide a range of commonly-required functionality beyond serving as an analytical tool.
The contributions of our study are twofold. First, we investigate the ability to portray the inherent hierarchical structure of the Internet using the most pure and compact topology, trees. Second, we evaluate the ability of our compact representation to facilitate many natural tasks, such as the selection of servers with short latency or high bandwidth from a client. Experiments show that these tasks can be done with high degree of success and modest overhead.
DRAM errors in the wild
Authors: Schroeder Bianca , Pinheiro Eduardo , Weber Wolf-Dietrich 
Published: April 2020

Errors in dynamic random access memory (DRAM) are a common form of hardware failure in modern compute clusters. Failures are costly both in terms of hardware replacement costs and service disruption. While a large body of work exists on DRAM in laboratory conditions, little has been reported on real DRAM failures in large production clusters. In this paper, we analyze measurements of memory errors in a large fleet of commodity servers over a period of 2.5 years. The collected data covers multiple vendors, DRAM capacities and technologies, and comprises many millions of DIMM days.
The goal of this paper is to answer questions such as the following: How common are memory errors in practice? What are their statistical properties? How are they affected by external factors, such as temperature and utilization, and by chip-specific factors, such as chip density, memory technology and DIMM age?
We find that DRAM error behavior in the field differs in many key aspects from commonly held assumptions. For example, we observe DRAM error rates that are orders of magnitude higher than previously reported, with 25,000 to 70,000 errors per billion device hours per Mbit and more than 8% of DIMMs affected by errors per year. We provide strong evidence that memory errors are dominated by hard errors, rather than soft errors, which previous work suspects to be the dominant error mode. We find that temperature, known to strongly impact DIMM error rates in lab conditions, has a surprisingly small effect on error behavior in the field, when taking all other factors into account. Finally, unlike commonly feared, we don't observe any indication that newer generations of DIMMs have worse error behavior.