(Invited) (ECS Electronics & Photonics Division Award )Wafer-Level Step-Stressing of InGaP/GaAs HBTs
Authors: Baca Albert G. , Kotobi Joshua A. , Fortune Torben R. , Gorenz Alan , Klem John F. , Briggs Ronald D. , Clevenger J. B. , Patrizi Gary A. 
Published: February 2020

Since InGaP/GaAs heterojunction bipolar transistors (HBTs) are utilized in a wide variety of RF and other applications, a great deal has been learned about their reliability. Nevertheless, this knowledge is limited by the fact that most reliability studies heavily emphasize the stress-related evolution of a single parameter, the DC current gain, beta. We have found that interrupted stressing experiments, with complete characterization of HBTs during the interruption, can give a more complete picture of the degradation that occurs during bias stressing of HBTs. We have previously correlated electrical signatures with degradation in step-stressing of packaged InGaP/GaAs HBTs [1]. In this work we will present some results of step-stress experiments which have been conducted at the wafer level for InGaP/GaAs HBTs. Wafer-level evaluation is advantageous due to the potential for greater automation and flexibility in the testing as well as the ability to identify problems at an earlier stage in the process.
The HBTs are stressed at room temperature at a constant collector voltage. Stressing is initiated at a given base current, held for a fixed time, which is typically 10 s. The applied stress is stepped up to a higher level of base current and the process is iterated until a failure is recorded. Full DC parametric electrical characterization of the HBT gets carried out initially and after certain predefined stress steps. Although the stress is typically carried near room temperature, it is understood that the junction of the HBT is effectively self-heated and can reach extremely high temperatures.
A certain set of degradation processes are responsible for stress-induced failures and these occur singly or in combinations. In addition, many HBTs within a wafer and among duplicate wafers have not only a number of common failure modes, but a tendency towards a consistently realized destructive power limit. The consistency of these results and the utility of electrical signature analysis lead us to conclude that wafer-level step-stressing is an excellent tool for quickly monitoring the HBT quality. We have also found many commonalities in the wafer-level and package level results for the ceramic packages used in a previous study [1].
The degradation of HBTs by these stressing methods leads eventually to a large drop in current gain. Thus, the interrupted step stressing method arrives at the same end state as continuous, single-parameter monitoring, but with much more clarity about the degradation processes that occur on the way to the end state.
The interrupted step-stress process in combination with electrical signature analysis is very likely to find the weak link in an HBT process. We will discuss the utility of the technique in terms of the opportunities to ruggedize the process. It is also possible that the identified weak link is fundamental to the technology or inconsequential in terms of meeting reliability requirements. In that case, wafer-level step-stressing is still an excellent tool for early identification of quality issues that may affect reliability through monitoring the consistency (or lack thereof) in degradation observed across different wafers over different periods of time.

A.G. Baca, A.J. Scruggs, A. Gorenz, T.R. Fortune, J.F. Klem, R.D. Briggs, J.B. Clevenger, G.A. Patrizi, and C.T. Sullivan, “A Survey of Electrical Signatures Characteristic of Step-Stressed InGaP/GaAs HBTS,” ECS Transactions vol. 50 (6), pp. 273-282 (2012).

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