Performance Improvement of Flexible Charge-Trap Memory Transistors Using Conducting Polymer Electrodes and Sacrificial Layer on Plastic Poly(ethylene naphthalate) Substrates
Authors: Yang Ji-Hee , Yun Da-Jeong , Kim Seong-Min , Yoon Myung-Han , Yoon Sung-Min 
Published: February 2020

Flexible and wearable electronic systems implemented on the plastic substrates have been energetically researched. Nonvolatile memory device (NVMs) with mechanical flexibility is one of the most important device elements to realize next-generation consumer electronic systems, because the NVMs can be embedded for both functions of an information storage as well as a power saving. In this purpose, we could successfully fabricated the charge-trap memory thin film transistors (CTMs) on poly(ethylene naphthalate) (PEN) substrates. Although good electrical and mechanical bending characteristics could be verified,1) for practical uses of flexible electronic systems, higher device performances are quite demanding even under harsh bending situations. However, there were intrinsic limitation at bending conditions with smaller curvature radius, because the brittle indium-tin-oxide (ITO) was employed as source/drain (S/D) electrodes for the previously demonstrated devices. Therefore, in order to significantly improve the bending performance of CTMs, brittle oxide-based electrodes should be replaced with a material having inherent flexibility, such as conducting polymer.
From these backgrounds, poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS), which is one of the most widely used conducting polymers, was introduced for the oxide-semiconductor-based CTMs as flexible S/D electrodes. This approach can be quite promising from the fact that the conducting polymer electrodes with mechanical flexibility and the oxide semiconductor channels with excellent electrical properties can be simultaneously exploited.
However, to realize highly-functional CTM devices combined with electrical and mechanical merits, following points should be considered: (1) high electrical conductivity, (2) lithography process compatibility of conducting polymers, and (3) overall TFT-process compatibility. From these viewpoints, H2SO4-treated PEDOT:PSS films were prepared and transferred on PEN substrates, by which the PEN surfaces could be effectively protected from harsh acidic condition. In preliminary experiments, the PEDOT:PSS film was transferred on SA7 (3-µm-thick, synthesized by Dongjin Semichem Co. Ltd.)-treated PEN substrate, which is organic barrier for the surface planarization.2) Even though an inorganic barrier (Al2O3) was desirable to be embedded for improving the water vapor transmission rate of the PEN substrate, in this work, Al2O3 barrier was eliminated so as to secure the lithography compatibility because of the poor adhesion between Al2O3 and PEDOT:PSS films. With this approach, the CTMs were successfully fabricated by using PEDOT:PSS S/D electrode, amorphous In-Ga-Zn-O (a-IGZO) active, and ZnO charge-trap layers. Clockwise hysteresis attributed to the charge-trap mechanism was obtained and memory windows (MWs) were soundly modulated by changing the gate voltage (VGS) sweep range. However, compared to the devices using ITO S/D’s, the CTMs fabricated with PEDOT:PSS S/D electrodes exhibited deteriorated subthreshold swing (SS) and asymmetric memory hysteresis, which may inevitably induce higher power consumption and slower operating speed. These inferior device characteristics were examined to be caused by terribly-rough back-channel region, because organic barrier of SA7 was severely damaged during dry etching patterning process for the PEDOT:PSS S/D electrodes.
In order to solve these problems, SA7 thin film was inserted between the organic/inorganic barrier and PEDOT:PSS film as a sacrificial layer, which should be chosen to satisfy following two requirements: (1) the thickness of the sacrificial layer should be sufficiently thin not more than 100 nm so that it can be completely etched during the S/D patterning process and the inorganic barrier can be faced with active channel as a back channel. (2) Sufficient adhesive properties with the PEDOT:PSS should be obtained even with a thinner film thickness. The film thickness and formation conditions of proposed sacrificial layer could be optimized for guaranteeing the smooth back channel and good adhesion with PEDOT:PSS film.
The PEDOT:PSS could be transferred and patterned on sacrificial layer and fully compatible with CTM fabrication process. As results, smaller SS value without marked gate leakage current and symmetric MWs with higher memory on/off ratio could be accomplished for the CTM devices fabricated by introducing sacrificial layer. The detailed descriptions on the flexible memory characteristics will be extensively discussed at presentation.
Although there remains room for the improvement of device characteristics, the introduction of suitable sacrificial layer was an effective remedy for improving the back-channel properties. This strategy proposed in this work can provide good chance to realize highly-functional and fully-bendable nonvolatile memory devices for flexible consumer electronics.
1) S. J. Kim, M. J. Park, D. J. Yun, W. H. Lee, G. H. Kim and S. M. Yoon, IEEE Trans. Electron Devices vol. 63, no. 4, 1557 (2016)
2) M. J. Park, D. J. Yun, M. K. Ryu, J. H. Yang, J. E. Pi, O. S. Kwon, G. H. Kim, C. S. Hwang, J. Y. Bak and S. M. Yoon, J. Mater. Chem. C, vol. 3, no. 18, 4779 (2015)