bluuebunny/crossref_metadata_2025_split huggingface dataset:
Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis
Authors: Pan Hui , Gibson Thomas 
Published: December 2020

Abstract
In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.
Fault Isolation of High Resistance Defects Using Comparative Magnetic Field Imaging
Authors: Orozco Antonio , Talanova Elena , Gilbertson Anders , Knauss L.A. , Wang Zhiyong , Skoglund Lars , Smith David G. , Dias Rajen 
Published: December 2020

Abstract
As integrated circuit packages become more complicated, the localization of defects becomes correspondingly more difficult. One particularly difficult class of defects to localize is high resistance (HR) defects. These defects include cracked traces, delaminated vias, C4 non-wet defects, PTH cracks, and any other package or interconnect structure that results in a signal line resistance change that exceeds the specification of the device. These defects can result in devices that do not run at full speed, are not reliable in the field, or simply do not work at all. The main approach for localizing these defects today is time domain reflectometry (TDR) [1]. TDR sends a short electrical pulse into the device and monitors the time to receive reflections. These reflections can correspond to shorts, opens, bends in a wire, normal interfaces between devices, or high resistance defects. Ultimately anything that produces an electrical impedance change will produce a TDR response. These signals are compared to a good part and require time consuming layer-by-layer deprocessing and comparison to a standard part. When complete, the localization is typically at best to within 200 microns. A new approach to isolating high resistance defects has been recently developed using current imaging. In recent years, current imaging through magnetic field detection has become a main-stream approach for short localization in the package [2] and is also heavily utilized for die level applications [3]. This core technology has been applied to the localization of high resistance defects. This paper will describe the approach, and give examples of test samples as well as results from actual yield failures.
Dynamic Infrared System Level Fault Isolation
Authors: Naoum John A. , Rahardjo Johan , Taffese Yitages , Chagny Marie , Birdsley Jeff , Woo John C. , Morris Aaron 
Published: December 2020

Abstract
The use of Dynamic Infrared (IR) Imaging is presented as a novel, valuable and non-destructive approach for the analysis and isolation of failures at a system/component level.
XRF Correlation of Board Reseats Due to Intermittent Failures from the Use of Thin Gold Plating finish on the Contact Fingers
Authors: Stein Dan , Hernandez Victor , Nailos Mary Ann 
Published: December 2020

Abstract
This paper correlates the reseat failure rates of a PCI option card to the use of thin gold plating across the contact fingers. This failure mechanism results in increased contact resistance and is often misdiagnosed due to its intermittent failure mode. As many new manufactures appear in Asia, the push for global competitiveness to achieve high volume and reduced costs can result in insufficient plating finishes being applied to the contact fingers. Compounding this problem is the fact the many companies use multiple raw board suppliers to meet these volume requirements. Many times the end user of the option card is unaware of the wide variation in contact plating thickness that may be present from one raw board source to another. Intermittent failures are one of the most common defects experienced in high volume assembly. Unless properly diagnosed, these failures can be attributed to finger debris, rework flux, solder paste contamination and even connector related issues. The typical fix, whether approved by the process or not, is for the manufacturing assembler to reseat all of the option cards and memory into the Motherboard connector sockets. Unless the proper troubleshooting approach is followed, isolating the true root cause of the actual failure can be missed. The difficulty in identifying the reseat problem is compounded by the fact that the failures are often intermittent in nature. While reseating may temporarily achieve sufficient mating between the board’s contact fingers and the connector contacts, it provides no long term fix. These unnecessary reseats also reduce the long-term durability of already thin plating affecting customer satisfaction and warranty costs. In the paper, we will expand on the theory behind the XRF plating thickness testing, including: • System theory • Test calibration • Part orientation • Test measurement criteria Additional analysis of metallurgical cross-sectioning was performed to correlate the XRF test readings to the actual plated layers. The measurements were completed by use of a SEM (Scanning Electron Microscopy).
Real Time SEM Imaging of FIB Milling Processes for Extended Accuracy on TEM Samples for EFTEM Analysis
Authors: Gnauck P. , Zeile U. , Hoffrogge P. , Benner G. , Orchowski A. , Rau W-D. 
Published: December 2020

Abstract
We present application examples of site specific energy filtered transmission electron microscopy (EFTEM) analysis using advanced focused ion beam (FIB) specimen preparation techniques. Specifically, we address topics such as throughput and reliability enhancement by chemically assisted broad ion beam milling and on-line monitoring of the etch process. We discuss how integrated elemental analysis by EFTEM can be used to gain quantitative information on the broad variety of new material systems currently entering front end and back end of the IC manufacturing process line. The accelerating pace of device integration results in extreme demands for quantitative analysis in process development, yield ramp-up and process control with spatial resolution and elemental sensitivity at the very limits of currently available instrumentation. Historically, the high resolution performance of TEM analysis has been hampered by long turn around times for the required sample preparation. Meanwhile the routine use of FIB systems for “trench” and “lift-out” preparation techniques allows for an enormous increase in the efficiency of TEM analysis.
VLSI Design for Functional Failure Analysis in the &lt; 90 nm and Flip-Chip Era
Authors: Weizman Yoav , Baruch Ezra 
Published: December 2020

Abstract
In recent years, two new techniques were introduced for flip chip debug; the Laser Voltage Probing (LVP) technique and Time Resolved Light Emission Microscopy (TRLEM). Both techniques utilize the silicon’s relative transparency to wavelengths longer than the band gap. This inherent wavelength limitation, together with the shrinking dimensions of modern CMOS devices, limit the capabilities of these tools. It is known that the optical resolution limits of the LVP and TRLEM techniques are bounded by the diffraction limit which is ~1um for both tools using standard optics. This limitation was reduced with the addition of immersion lens optics. Nevertheless, even with this improvement, shrinking transistor geometry is leading to increased acquisition time, and the overlapping effect between adjacent nodes remains a critical issue. The resolution limit is an order of magnitude above the device feature densities in the &lt; 90nm era. The scaling down of transistor geometry is leading to the inevitable consequence where more than 50% of the transistors in 90nm process have widths smaller than 0.4um. The acquisition time of such nodes becomes unreasonably long. In order to examine nodes in a dense logic cuicuit, cross talk and convolution effects between neighboring signals also need to be considered. In this paper we will demonstrate the impact that these effects may have on modern design. In order to maintain the debug capability, with the currently available analytical tools for future technologies, conceptual modification of the FA process is required. This process should start on the IC design board where the VLSI designer should be familiar with FA constraints, and thus apply features that will enable enhanced FA capabilities to the circuit in hand during the electrical design or during the physical design stages. The necessity for reliable failure analysis in real-time should dictate that the designer of advanced VLSI blocks incorporates failure analysis constraints among other design rules. The purpose of this research is to supply the scientific basis for the optimal incorporation of design rules for optical probing in the &lt; 90nm gate era. Circuit designers are usually familiar with the nodes in the design which are critical for debug, and the type of measurement (logic or DC level) they require. The designer should enable the measurement of these signals by applying certain circuit and physical constraints. The implementation of these constraints may be done at the cell level, the block level or during the integration. We will discuss the solutions, which should be considered in order to mitigate tool limitations, and also to enable their use for next generation processes.
Microhardness Testing on Via Fill Material for Via In Pad Technology
Authors: Armendariz Norman J. , McCormick Carolyn 
Published: December 2020

Abstract
Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.
Via Chain Failure Analysis Using a Combination of E-Beam and Optical Beam Techniques
Authors: Perungulam Srikanth , Gleason Albert 
Published: December 2020

Abstract
This paper outlines some of the optical and e-beam based techniques that can be used to isolate via chain failures. The Scanning electron microscope based techniques discussed are Passive Voltage Contrast (PVC) and Substrate Current Imaging (SCI). The optical beam technique discussed is Thermally Induced Voltage Alteration (TIVA) on the Laser Scanning Microscope. A combination of these techniques can be used to effectively analyze all types of via chain failures.
Semi-Automated Cross-Section Preparation Process for Complex Multi-Face Perimeter Samples
Authors: McDonald Todd 
Published: December 2020

Abstract
The fixed position sample mover plates currently offered to the industry only facilitate two sided grinding and polishing. 3 and 4-sided requests cannot be accommodated with these fixed position mover plates. Ultimately this means performing some or all of the work manually. Described here is a fixture and process solution that makes semi-automation possible through the entire process.
Near IR Continuous Wavelength Spectroscopy of Photon Emissions from Semiconductor Devices
Authors: Len W.B. , Liu Y.Y. , Phang J.C.H. , Chan D.S.H. 
Published: December 2020

Abstract
A spectroscopic photon emission microscope (SPEM) which is capable of high resolution spectroscopy for a continuous wavelength range between 300 nm to 1700 nm has been developed. Photon emissions were observed at energy levels below silicon bandgap from pn junctions and MOSFET devices at different biases. The experimental results indicate significant emission activity in this range. It was also found that the spectra is closely correlated to the electric fields present in the devices.
Defect Isolation and Characterization in Contacts by Using Primary Voltage Adjustment
Authors: Chen Yuan-Shih , Lee Jeng-Han 
Published: December 2020

Abstract
Voltage contrast(VC) is a popular method for failure site isolation[1]. After study we find some weakness on tradition voltage contrast. This paper presents a new voltage contrast procedure that can conquer the weakness. For a CMOS technology, there are four kinds of contact node were used. They are N+/PW node, P+/NW node , poly gate node and well node. Traditional voltage contrast condition uses constant SEM primary energy like 1KV can not distinguish these four kinds of node well. For example a contact lead to P+/NW will be bright in tradition VC[2], but a contact connected to well will also be bright. It means tradition VC can not distinguish difference between contact lead to P+/NW and contact lead to well. To improve the weakness of the traditional VC, we will present a new Voltage Contrast technique, which could distinguish all contact types in CMOS technology.
A Flexible, Low Cost Test System for Failure Analysis of High Power Mixed Signal ASICs
Authors: Kolasa T. , De La Torre J. C. , Bertram L. 
Published: December 2020

Abstract
In this paper, we will present our solution to the problem of test based fault localization in the failure analysis laboratory environment. The test system described herein is currently used for a number of high power mixed signal application specific integrated circuits (ASICs) that incorporate functions including switching power supplies, charge pumps, high current drivers, precision references, ADCs/DACs, comparator circuits, and digital cores. The solution addresses the shortcomings of alternative options through modular construction, compact size, and use of a commercially available graphical software compiler to create the control code and graphical user interface (GUI).
Modeling Secondary Electron Emission from High Aspect Ratio Holes
Authors: Wang Q. S. , Thompson M. A. , Schultz W. , Lundquist T. R. 
Published: December 2020

Abstract
The success of circuit editing depends not only on x-y navigation to precise coordinates on the integrated circuits (IC), but also on precise z navigation. Certainly, secondary electron (SE) emission has proven to be the most accurate monitoring technique to accomplish this z precision. Even so, it has been amazing that SE monitoring works in high aspect ratio holes—reports have been made of high aspect ratio holes near 30:1. To explain why this occurs, therefore, is of interest and, by understanding how it works, we may improve the technique.
Characterization of Interconnect Defects Due to Electromigration Using Scanning Thermal Microscopy
Authors: Wu E.X.W. , Zheng X.H. , Phang J.C.H. , Balk L.J. , Lloyd J.R. 
Published: December 2020

Abstract
In this paper, the temperature distributions around interconnect defects due to electromigration are presented. A method to overlay the temperature distribution over the optical microscope image of the physical defect has also been developed. This allows a direct correlation of the temperature distribution and the physical structure of the defect.
Indium Tin Oxide (ITO) Film Removal Technique for Failure Analysis on Packaged Optoelectronic Devices
Authors: Elliott Shawn , Gordon Jean , Plourde Peter 
Published: December 2020

Abstract
Various detector chips in optocoupler devices have a thin indium tin oxide (ITO) film deposited over the passivation. This transparent, conductive film is found over the photodetecting area of the die. When this film is electrically connected to ground potential through contacts, it acts as a shield to avoid inversion failures by sinking any charge buildup to ground. In order to perform a full electrical failure analysis on these optocoupler detector chips, the ITO layer must be removed. An extensive search found numerous papers on etching this film over glass substrates, but no known technique was found to selectively remove the ITO layer on a packaged die. This paper discusses an approach to remove this film using an argon gas etch technique. The ideal characteristics of any process used to remove this film on a finished die would be to completely etch the ITO layer, electrically isolating it from ground, while leaving the underlying passivation and metallization fully intact. This would allow for further electrical failure analysis of the die without causing additional damage or affecting the failure mechanism. The results of an experiment using various chemical and gas etchants found that an argon gas etch would remove the ITO layer while only slightly etching the phosphosilicate glass (PSG) passivation beneath. Electrical failure analysis of the die continued at this point, and a subsequent buffered oxide etch (BOE) removed the remaining passivation, leaving the exposed metallization and oxide completely intact. This technique has been used successfully on device failures to find passivation contamination shorting the aluminum metallization to the ITO film.
Power Supply Noise Analysis Using Neural Network and Genetic Algorithm Based on Automatic Test Equipment
Authors: Liau Eric , Schmitt-Landsiedel Doris 
Published: December 2020

Abstract
Power supply noise (PSN) is becoming more severe as technology scales, and can cause signal distortion and increase gate delay. This can further result in improper circuit operation. In this paper, we propose a novel approach based on ATE (automatic test equipment) that teaches neural networks (NN) to correctly classify a set of worst case input patterns with respect to the maximum instantaneous current. This can be thought of as a learning behavior of chip power consumption change due to different input patterns. Then a genetic algorithm (GA) was applied to further optimize this set of NN worst case patterns. A final set of worst case patterns were expected to detect a small critical sequence of high switching currents that was directly related to the worst case power supply noise. This novel diagnosis approach can efficiently identify the defective design or weakness due to PSN as well as locate the defect or weaknesses within the design.
Dopant Region Imaging on Front Surface of Silicon Devices Using a Coaxial Photon-Ion Column
Authors: Pajak Robert G. , Baiocchi Frank A. , Roy Erwan Le 
Published: December 2020

Abstract
An n-well contrast enhancement process, which is used for backside navigation has been further developed to observe dopant regions on top-down prepared devices. Dopant regions for the following structures were delineated: ▪ p-active regions in n-wells; ▪ n-active regions in p-wells; ▪ n-well to p-well interface; ▪ p+/p interface. The enhancement process to obtain this contrast was done on a Credence OptiFIB using a coaxial FIB/optical column. Illumination of the sample is a critical component of the process. First, the high contrast level obtained at a p/n junction was only achieved by using light assisted FIB oxide deposition. Second, sample illumination was found to enhance contrast while imaging the region of interest using the focused ion beam. The contrast becomes permanent only after the oxide is deposited. Contrary to chemical etch techniques imaged in a SEM, this enhancement process as well as the imaging process were completed in-situ. Further, this process proved to be very reproducible. This dopant contrast enhancement process provides an alternative to wet chemical delineation methods for the verification of dopant photomask registration, for accomplishing reverse engineering and for observing missing implants.
Failure Analysis of Soft Single Column Failure in Advanced Nano SRAM Device with Internal Probing Techniques
Authors: Lin Hung-Sung , Chang Wen-Tung , Chao Chia-Hsing , Wang Jesse , Lin Chang-Tan , Lin Coswin 
Published: December 2020

Abstract
Single column failure [1], one of the complex failure modes in SRAM is possibly induced by multiform defect types at diverse locations. Especially, soft single column failure is of great complexity. As physical failure analysis (PFA) is expensive and time-consuming, thorough electrical failure analysis (EFA) is needed to precisely localize the failing area to greater precision before PFA. The methodology involves testing for failure mode validation, understanding the circuit and using EFA tools such as IR-OBIRCH (InfraRed-Optical Beam Induced Resistance CHange) and MCT (MerCad Telluride, HgCdTe) for analysis. However, the electrical failure signature for soft single column failure is usually marginal, so additional techniques are needed to obtain accurate isolation and electrical characterization instead of blindly looking around. Thus in this discussion, we will also present the use of internal probing techniques like C-AFM [2] (Conductive Atomic Force Microscopy) and a nanoprobing technique [3] for characterizing electrical properties and understanding the root cause.
The Effectiveness of OBIRCH Based Fault Isolation for Sub-90nm CMOS Technologies
Authors: De la Bardonnie M. , Kwakman L.F.Tz. , Ly K. , Ross R. , Lorut F. , Lamy M. , Wyon C. , Hiruma Y. , Roux J. 
Published: December 2020

Abstract
Even though failure analysis performed with a latest generation Phemos 2000 Optical Beam Induced Resistance Change (OBIRCH) tool has given excellent results for 120nm and 90nm technology developments, the limitations of tool and technique become apparent when used for the 65nm technology node and beyond. This article discusses the use of a pulsed laser in combination with a lock-in amplifier for OBIRCH-based fault isolation in latest generation CMOS devices. Using such set-up with appropriate settings for laser pulse frequency, scan speed, and phase shift off-set, a ten-fold signal-to-noise ratio gain is achieved. This improved S/N ratio allows detecting faulty circuitry with higher sensitivity and isolating faults that cannot be detected with the traditional OBIRCH set-up. Various case studies on latest technology devices are presented to illustrate the interest of adding the lock-in capability to the standard OBIRCH tool.