An Insightful Review of Galvanic Formations and Dynamic Interactions in Selectively Corroding Silicon Surfaces during Wafer Manufacturing
Authors: Sheng Lieyi 
Published: February 2020

Surface cleaning has been playing an essential role in semiconductor technology since early 1950s. It can be safely assumed that in advanced integrated circuit (IC) manufacturing at least one third of all operations performed on the wafer are cleaning operations [1], where a variety of chemicals, mostly in solution, is used. Meanwhile, wafer surface is highly susceptible to various contaminants, such as metal particles. During spin rinses (incl., with DI water), electrical charges can easily build up on surface of wafer. With all these factors in wet chemical environments, electrochemical reactions are expected to readily occur in wafer cleaning processes.
However, among the numerous publications in semiconductor cleaning technology, galvanic corrosions during wafer manufacturing have been very rarely addressed. Due to the extreme complexity of manufacturing ICs in a largely variable environment, a galvanic corrosion can easily be a hidden event due to subtle interactions in process, but can induce interfacial and/or dielectric defects.
In this review, the fundamentals of galvanism will be extensively examined on the surfaces of silicon, which is almost exclusively used in semiconductor industry. The views from our published [2-4] (after L. Sheng et al., IRPS2006, UCPSS2006, ASMC2013) and unpublished cases along with other references [5-8] provide a number of unique electrochemical features in the galvanic corrosion on silicon surfaces.
There are four fundamental elements needed to form a galvanic corrosion cell: anode, cathode, electrolyte, and conductive path. When a galvanic corrosion occurs on silicon surface, silicon atoms are dissolved to silicon ions due to anodic oxidation, resulting in surface pitting or cratering. The occurrences of corrosion can be counted by inline optical/SEM inspection and/or more statistically quantified by electrically measuring the defect density (D0) of gate oxide.
An anodic corrosion on silicon surface strongly tended to occur on highly localized spots predefined by other process incidents, such as metal particles. An implant damage or micro-arcing event could be too weak to be detectable during implantation or by inline inspections afterwards, which, however, served as a reservoir of accumulating charges. With an appropriate type (+/-) and sufficient charges trapped, the spot could potentially become a lonely anode. Meanwhile, the anodic potential could be easily alternated by several factors. For instance, on a structure susceptible to an accumulation of electron flooding from the photoresist sidewalls, the potential could be lowered. Alternately, a corrosion cell could be energized by the potential difference in a p-n junction, thus resulting in the pMOS-specific corrosion on n-well.
Moreover, an electrons-limited corrosion process has been typically observed. Therefore, due to a reduced cathode/anode ratio on smaller structures, the acceleration of corrosion process could be slowed, resulting in a drastically lower D0.
Acidic solutions or residuals could readily act as efficient electrolytes. Without the addition of NH4F [to form a buffered oxide etchant (BOE)], a HF solution was much less electrically conductive by orders-of-magnitude and the corrosion was thus largely shunted. Meanwhile, the surface transportation behavior of chemicals could be vividly reflected on a microscopic scale well inside the failure patterns of gate oxide at a wafer level. A surface topological change has served as an anti-dispersion barrier against the surface mass transportation in a spray-cleaning, thus enhancing a localized accumulation of chemical residues (incl., sulfuric acid).
The stacked wafer-patterns of failures could be quite different on bulk and epi wafers. Epi-base has much lower R, which provides more chances for a spot to form reaction cells with others, thus globally resulting in more failures. Interestingly, a skew bull’s-eye pattern appeared with a good zone in the center of epi-wafers. The high-R of bulk silicon constricts reaction cells to their local areas. However, a low-R epi-base facilitates dispersion and sharing of a corrosion current with more reaction cells involved, and a center site statistically experiences less corrosion currents than an edge site. Also, very different corrosions occurred on two adjacent copy-exact structures.
To vividly illustrate the various formations of galvanic cells and their dynamic interactions in wafer processing, dozens of figures and tables will be provided in the full-length publication.
In summary, this insightful review will summarize for the first time a number of unique electrochemical features in selectively corroding silicon surfaces and their significant impacts on interfacial quality and dielectric reliability. These insights are critical to quickly identify and solve the hidden or intricate galvanic occurrences in a highly dynamic and variable environment of wafer manufacturing.