bluuebunny/crossref_metadata_2025_split huggingface dataset:
Non Invasive Failure Analysis of Passive Electronic Devices in Wireless Modules Using X-ray Micro Tomography (MicroCT)
Authors: Pendleton Tyler , Hunter Luke , Lau S. H. 
Published: January 2021

Abstract
Conventional microCTs or 3D x-ray upgrades from existing 2D x-ray systems have two major drawbacks when they are used for failure analysis of advanced packages: Insufficient resolution to image small (1 to 5 microns) materials and the lack of imaging contrast to visualize cracks, whiskers, and defects within low Z materials. This paper discusses some of the failure analysis (FA) case studies of wireless modules using a high resolution micro x-ray CT (XCT). These examples show the value of high resolution XCT as a novel approach to some common package level defects, including some interesting case examples, where failure mechanisms have been uncovered which could not have been done, using conventional means. The non-invasive FA technique for RF modules technique has been shown to dramatically improve the FA engineers' chances of identifying defects over conventional 2D x-rays and avoid the need for physical and tedious cross sectioning of these devices.
Scanning Acoustic Microscopy for Solder Joint Failure Analysis and Design Improvements
Authors: Varma Ramesh , Bartolovitch Jeffrey , Brzozowski Victor , Sokolowski Carl 
Published: January 2021

Abstract
This paper reports using Scanning Acoustic Microscopy for solder joint failure analysis and process and design improvements. There are reliability concerns associated with solder voids or non-wetting of the solder to the bond pads which is particularly important for higher electrical power or temperature applications. Defects in solder can also occur and grow during operation and thermal cycling. Sonoscan is an attractive non-destructive test to characterize solder joints and is often used to study the growth of defects during life test simulations. X-ray imaging cannot identify very small defects, particularly non-wetting and delamination because of poor resolution. The instrument used in this study was a CSAM (C-Mode Scanning Acoustic Microscopy) operating in reflection mode at 30-100 MHz. We have identified voids inherent in the solder layer as well as delamination at the package to solder and solder to heat-sink interfaces. C-SAM results confirmed that the delamination was caused by CTE mismatch of the materials as well as the mechanical stresses caused by higher level package integration and module assemblies. Thermal cycling studies have shown that typically the voids do not grow whereas delamination does. These results were used to improve thermal heat-sinking and product reliability by minimizing defects in solder joint by changes in process and mechanical designs.
Lock-In-Thermography for 3-Dimensional Localization of Electrical Defects inside Complex Packaged Devices
Authors: Schmidt C. , Altmann F. , Grosse C. , Lindner A. , Gottschalk V. 
Published: January 2021

Abstract
It has been shown that microscopic Lock-in-Thermography (LiT) can be used for localization of electrical active defects like shorts and resistive opens in integrated circuits. This paper deals with the application of LiT for non-destructive failure analysis of fully packaged single and multi chip devices. In this case inner hot spots generated by the electrical defects typically can not be imaged directly because the mold compound or adhesives above are not IR transparent. Inner hot spots can only be detected by measuring the corresponded temperature field at the device surface. By means of failed and test devices will be shown, that LiT is sensitive enough to measure such temperature fields. In addition to the lateral localization of inner hot spots its depth can also be determined by measuring the phase shift between the electrical excitation and the thermal response at the device surface. Furthermore, the influence of the lock-in-frequency and mold compound thickness to lateral resolution and signal to noise ratio will be discussed. Using real failed single chip and stacked die devices two analysis flows were demonstrated to locate inner defects.
An Analytical Technique to Assess the Risk of Laser Damage to Encapsulated Integrated Circuits during Package Laser Marking
Authors: Patterson Joseph , Schuring Cliff 
Published: January 2021

Abstract
Damage to encapsulated integrated circuits has recently been reported due to Laser marking of the package. A method to assess the risk of such damage is presented. The method is an analytical technique using Thermally Induced Voltage Alteration (XIVA) and Optical Beam Induced Current (OBIC) imaging.
Emerging Techniques for the Characterization of Nano-Mechanical Properties of Integrated Circuit Components
Authors: Randall Nicholas , Nair Rahul Premachandran 
Published: January 2021

Abstract
With the growing complexity of integrated circuits (IC) comes the issue of quality control during the manufacturing process. In order to avoid late realization of design flaws which could be very expensive, the characterization of the mechanical properties of the IC components needs to be carried out in a more efficient and standardized manner. The effects of changes in the manufacturing process and materials used on the functioning and reliability of the final device also need to be addressed. Initial work on accurately determining several key mechanical properties of bonding pads, solder bumps and coatings using a combination of different methods and equipment has been summarized.
Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification
Authors: Herschbein Steven B. , Kang Hyoung H. , Jansen Scott L. , Dalton Andrew S. 
Published: January 2021

Abstract
Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.
Creation of Solid Immersion Lenses in Bulk Silicon Using Focused Ion Beam Backside Editing Techniques
Authors: Scholz P. , Kerst U. , Boit C. , Tsao C.-C. , Lundquist T. 
Published: January 2021

Abstract
This work describes how Solid Immersion Lenses (SILs) can be created in bulk silicon using a focused ion beam and a bitmap milling process. The optical properties are in good agreement with the expected results for the achieved lens geometries. An improvement in lateral spatial resolution by a factor of 1.8 and in image contrast by 170 % for backside analysis is demonstrated. The presented SILs are 32 µm in diameter with a field of view of about 10 μm. This process can be an alternative when a regular SIL placement on the chip is impossible or complex. The advantages of this method are the use of a single kind of material (no air gaps and no additional lens material with different n value), the ability to precisely position the SIL on the circuitry and the fact that a SIL may be created in less than twenty minutes of processing time.
S/D LDD Junction Stain/Delineation by Electrochemical Displacement with Illumination
Authors: Chiu Re-Long , Chen Tammy , Chen Shannon 
Published: January 2021

Abstract
This article describes the use of an optimized electrochemical delineation technique with illumination to clearly delineate the P-N junction on Si in short channel devices. In this process, the samples are exposed to a light source while in an aqueous CuSO4/HF/H2SO4 solution which induces a junction voltage between N- and P- type silicon. The N+/P+ dopant regions become the cathode/anode electrode plates. The treatment is simple and reproducible which makes it a practical method for identifying junction related problems at localized areas on a chip. Examples are provided to show the effectiveness of this technique in identifying (1) junction implant shift, (2) N+/P-well junction leak, (3) partially blocked NLDD implant, and (4) P+/N+ junction in high voltage device.
A New Method of Wafer Level Plan View TEM Sample Preparation by DualBeam
Authors: Kang Hyoung H. , Gribelyuk Michael A. , Patterson Oliver D. , Herschbein Steven B. , Senowitz Corey 
Published: January 2021

Abstract
Cross-sectional style transmission electron microscopy (TEM) sample preparation techniques by DualBeam (SEM/FIB) systems are widely used in both laboratory and manufacturing lines with either in-situ or ex-situ lift out methods. By contrast, however, the plan view TEM sample has only been prepared in the laboratory environment, and only after breaking the wafer. This paper introduces a novel methodology for in-line, plan view TEM sample preparation at the 300mm wafer level that does not require breaking the wafer. It also presents the benefit of the technique on electrically short defects. The methodology of thin lamella TEM sample preparation for plan view work in two different tool configurations is also presented. The detailed procedure of thin lamella sample preparation is also described. In-line, full wafer plan view (S)TEM provides a quick turn around solution for defect analysis in the manufacturing line.
Embedded Gold Markers for Improved TEM/STEM Tomography Reconstruction
Authors: Luo Jian-Shing , Huang Chia-Chi , Russell Jeremy D. 
Published: January 2021

Abstract
Electron tomography includes four main steps: tomography data acquisition, image processing, 3D reconstruction, and visualization. After acquisition, tilt-series alignments are performed. Two methods are used to align the tilt-series: cross-correlation and feature tracking. Normally, about 10-20 nm of fiducial markers, such as gold beads, are deposited onto one side of 100 mesh carbon-coated grids during the feature-tracking process. This paper presents a novel method for preparing electron tomography samples with gold beads inside to improve the feature tracking process and quality of 3D reconstruction. Results show that the novel electron tomography sample preparation method improves image alignment, which is essential for successful tomography in many contemporary semiconductor device structures.
Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation
Authors: Kiyan T. , Boit C. , Brillert C. 
Published: January 2021

Abstract
In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.
Dual Port RAM MBIST Failure Analysis Using Time Resolved Dynamic Laser Stimulation
Authors: Shaw Jonathan , McMahon Christopher , Ng Yin Shyang , Beaudoi Félix 
Published: January 2021

Abstract
This paper presents the use of Dynamic Laser Stimulation (DLS) and Time-Resolved DLS (TR-DLS) to provide fail site localization and complementary information on a failed embedded memory IC. In this study, an embedded dual port RAM within a 90nm IC that failed one of the Memory Built-In Self Tests (MBISTs) was investigated. This technique rapidly localized the failing area within the memory read/write circuitry. The TR-DLS provided maps for each operation of the MBIST pattern. With this information, the failure was clearly identified as a read operation failure. The TR-DLS technique also provided much refined site signature (down to just one net) within the sense amp of the Port B of the dual port RAM. This information provided very specific indication on how to improve the operation of that particular sense amp circuitry within the dual port RAM Memory.
Mixed Frequency Detection of Thermal Laser Stimulation (MF-TLS) and Its Application in Failure Analysis
Authors: Qian Zhongling , Brillert Christof , Burmer Christian 
Published: January 2021

Abstract
A new localization method called MF-TLS is introduced and applied in failure analysis praxis. The method combines local periodic thermal stimulation technique with periodic excitation of the electrical fails. The mixed frequency signal is detected by a lockin amplifier. MF-TLS was demonstrated on fabricated opens in a metal line and shown to be in semi-quantitative agreement with a capacitance modulation model. The technique was also applied to a scan shift problem and produced a higher sensitivity compared with other dynamic TLS methods. Limits and prospects of this new methodology are described.
Analysis of Deep Trench Node Leakage Depth by Applying Current Imaging Technique at Silicon Level
Authors: Doering S. , Seitz M. , Zimmermann U. , Rodger P. , Werner W. 
Published: January 2021

Abstract
In case of a node leakage failure in DRAM products, the location of the defect can be spread over the entire deep trench depth of up to six microns, making it very difficult to precisely localize the defects. In addition, the use of surface area enlarging techniques makes it even more difficult to pinpoint the node leakage defect. In this study, first, the node leakage was verified at contact level using the nano-probing technique. In the second step, the sample was deprocessed into the p well level and a current image was obtained, confirming the node leakage to be located below this level. In the third step, the sample was further deprocessed to the edge of the n well level. AFM-based probing provided additional information regarding the location of the node leakage. With these three measurements, the authors confined the node leakage to the small n well region.
Laser Scanning Localization Technique for Fast Analysis of High Speed DRAM Devices
Authors: Versen Martin , Schramm Achim , Schnepp Jan , Hoch Sascha , Vikas Tapan , Diaconescu Dorina 
Published: January 2021

Abstract
Soft defect localization (SDL) is a method of laser scanning microscopy that utilizes the changing pass/fail behavior of an integrated circuit under test and temperature influence. Historically the pass and fail states are evaluated by a tester that leads to long and impracticable measurement times for dynamic random access memories (DRAM). The new method using a high speed comparison device allows SDL image acquisition times of a few minutes and a localization of functional DRAM fails that are caused by defects in the DRAM periphery that has not been possible before. This new method speeds up significantly the turn-around time in the failure analysis (FA) process compared to knowledge based FA.
Novel Application of the OBIRCh Amplifier for Timing Failure Localization
Authors: Sienkiewicz M. , Perdu P. , Brule S. , Firiti A. , Crepel O. 
Published: January 2021

Abstract
Soft defects localization by laser techniques on dynamically working ICs is widely used for Failure Analysis (FA). In this context, many AC signal-oriented analysis methods have been introduced to date (SDL, LADA…) or are under development (xVM…). Sophisticated tools are available to localize these kinds of failures but not every FA laboratory has them. By fully exploiting the capabilities of static localization tools, it is possible to deal with timing issues. In this paper, we propose a novel application of the OBIRCh amplifier related to the timing issues on a real case study (mixed-mode device). This novel and very simple application makes the analysis flow time-attractive and enlarges the application field of mapping techniques on the existing tools.
Novel Sample Preparation Technique for Backside Analysis of Singulated Die
Authors: Elliott S. , LaPierre M. , Plourde P. 
Published: January 2021

Abstract
A case study of a transient induced latch-up (TLU) problem is presented, which was identified during the development of a 60 V, 0.8 µm BiCMOS power control device. The mechanism was characterized by controlled transient latch-up testing and found to be fairly unusual, being triggered by a fast decreasing not necessarily negative spike or glitch on the positive supply pin. Emission Microscopy (EMMI) and Transient Interferometric Mapping (TIM) successfully located the parasitic silicon controlled rectifiers (SCR) structure. TIM is an infra-red laser beam based technique for back side analysis. TIM analysis enables concurrent imaging of carrier injection and heating in nanosecond timescale providing more detailed information on the SCR action than more often used static photon emission or dynamic TLP / PICA imaging.
Innovative Method & Use of UV Technologies for Dye Penetrant Sample Preparation
Authors: McDonald Todd R. 
Published: January 2021

Abstract
Today’s high volume FA labs are constantly looking for ways to improve the data to customer cycle. Current dye & pull sample preparation materials and methods have some time to completion requirements that cannot be avoided without compromising data. This paper demonstrates that significant improvements in data cycle time and quality can be realized by using a combination of the latest UV cure adhesives, masks, and complimentary equipment such as LED cure lights and gantry dispensing robots.
Next Generation Laser Voltage Probing
Authors: Ng Yin S , Lo William , Wilsher Kenneth 
Published: January 2021

Abstract
We present an overview of Ruby, the latest generation of backside optical laser voltage probing (LVP) tools [1, 2]. Carrying over from the previous generation of IDS2700 systems, Ruby is capable of measuring waveforms up to 15GHz at low core voltages 0.500V and below. Several new optical capabilities are incorporated; these include a solid immersion lens (SIL) for improved imaging resolution [3] and a polarization difference probing (PDP) optical platform [4] for phase modulation detection. New developments involve Jitter Mitigation, a scheme that allows measurements of jittery signals from circuits that are internally driven by the IC’s onboard Phase Locked Loop (PLL). Additional timing features include a Hardware Phase-Locked Loop (HWPLL) scheme for improved locking of the LVP’s Mode-Locked Laser (MLL) to the tester clock as well as a clockless scheme to improve the LVP’s usefulness and user friendliness. This paper presents these new capabilities and compares these with those of the previous generation of LVP systems [5, 6].
A Study of the Photoelectric Effect Caused by a Laser Beam Used in a Beam Bounce Technique in a C-AFM System
Authors: Lin Hung-Sung , Wu Mong-Sheng 
Published: January 2021

Abstract
The use of a scanning probe microscope (SPM), such as a conductive atomic force microscope (C-AFM) has been widely reported as a method of failure analysis in nanometer scale science and technology [1-6]. A beam bounce technique is usually used to enable the probe head to measure extremely small movements of the cantilever as it is moved across the surface of the sample. However, the laser beam used for a beam bounce also gives rise to the photoelectric effect while we are measuring the electrical characteristics of a device, such as a pn junction. In this paper, the photocurrent for a device caused by photon illumination was quantitatively evaluated. In addition, this paper also presents an example of an application of the C-AFM as a tool for the failure analysis of trap defects by taking advantage of the photoelectric effect.
Applications of C-AFM and CBED Techniques to the Characterization of Substrate Dislocations Causing SRAM Soft Single-Column Failure Contained in a Wafer with (001) Plane/[100] Notch
Authors: Lin Hung-Sung , Chen Tung-Hung , Shu Wen-Cheng 
Published: January 2021

Abstract
SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture. However, the success rate of defect detection, especially for soft single-column failures, is decreasing when traditional physical failure analysis (PFA) with only the bitmap is available for guidance. This is due to a variety of invisible or undetectable defects that cause leakage in the device. In order to understand the leakage behavior in advanced high voltage (HV) processes, a Conductive Atomic Force Microscope (C-AFM) [1-4] is introduced to perform junction-level fault isolation prior to attempting PFA. According to J. P. Morniroli [5], crystalline defects affect convergent-beam electron diffraction (CBED) and large angle convergent-beam electron diffraction (LACBED) patterns, so CBED and LACBED techniques were also applied to the specimens containing dislocations to allow further characterization of these defects. In this study quantified data extracted using the C-AFM is also used to establish a connection between the failure mechanism discovered and the soft single column failure mode.
Electroluminescence Analysis by Precise Tilt Polish Technique of Edge-Emitting Laser Diode
Authors: Ichikawa Hiroyuki , Sasaki Kouichi , Hamada Kotaro , Yamaguchi Akira 
Published: January 2021

Abstract
We have employed electroluminescence (EL) analysis of an edge-emitting laser diode (LD) to detect possible defects. To extract EL emission from a LD, we developed a tilt polish technique of the bottom electrode. We can successfully observed clear EL emission. A high yield of 99.2 % was achieved by the introduction of the precise tilt polish technique.