bluuebunny/crossref_metadata_2025_split huggingface dataset:
Laser Logic State Imaging Using Transient Voltage Collapse Circuits
Authors: Baek Gwanghyeon , Keane John , von Haartman Martin 
Published: December 2020

Abstract
A laser based logic state imaging (LLSI) by activating transient voltage collapse (TVC) circuits of SRAM blocks is demonstrated. In order to induce a voltage modulation on a power rail, significant numbers of TVC units are activated. The image quality of LLSI strongly depends on a number of activated TVC circuits. From this experiment, it is concluded that an additional circuit or experimental setup is not necessary for LLSI.
Near Field EMC Scanning Method Based on an E-Field Collapse
Authors: Dunnihoo Jeff , Tamminen Pasi , Viheriäkoski Toni 
Published: December 2020

Abstract
In this study we present a novel method to use a field collapse method together with fully automated near field scanning equipment to construct E- and H-field information of a system during transient ESD events. This inexpensive method provides an alternative way for system designers to validate and analyze the EMC/ESD capability of electronic systems without TLP pulsers, ESD simulators, or precision inductive current probes.
Time Domain Reflectometry—Case Studies in Electrical Failure Isolation
Authors: Wheeler Jason , Fasolino Stephen 
Published: December 2020

Abstract
Time Domain Reflectometry (TDR) is an analysis technique for characterizing a transmission environment (PCB traces, cable assemblies, etc.) and identifying the physical location of defects or impedance discontinuities which can quickly narrow the focus of an investigation. This paper introduces the capability and presents several case studies spanning different applications where TDR was useful as a non-destructive analysis technique.
Isolating Electrically Open Laminate Defects Using Space Domain Reflectometry with a Superconducting Quantum Interference Device
Authors: Distelhurst Kevin A. 
Published: December 2020

Abstract
An electrically open defect on a laminate may not always be found timely or successfully due to the lack of fault isolation techniques for this type of defect. This is partly due to needing high frequency techniques to isolate the location of the open. Magnetic field imaging (MFI) using a Superconducting Quantum Interference Device (SQUID) is a technique that maps, in this case, an RF signal through a trace, up until the open defect boundary. Several obstacles are introduced when using an RF signal, one of which is the shielding of the signal from the external world. Despite this obstacle, analysis of an open in an arbitrary location along a laminate under a copper plane is proven successful using this technique.
A Study of How Different FIB Beam Current Intensities Locate Possible Defects
Authors: Shu Wen Cheng , Shu Yu Hsiang 
Published: December 2020

Abstract
Voltage contrast (VC) is a useful technique and used widely in failure analysis of integrated circuit (ICs). This paper will demonstrate different FIB current intensities in a specific VC case and, by means of the technique, locate possible defect sites quickly. With the help of conductive atomic force microscopy (C-AFM), we can get an electrical verification at the same time. We discuss the relationship of VC and C-AFM as well as what the root cause of failure is in this case.
Selective Etching of Heavily-Boron-Doped Si Substrate Using Lightly-Boron-Doped Si Epi as an Etch Stop Layer
Authors: Korchnoy Valentina 
Published: December 2020

Abstract
A sample preparation technique for flip chips (FC) deprocessing from the back side proposed. The technique uses HNA chemistry (consisting of a mixture of acids: hydrofluoric, nitric and acetic) to wet-etch the heavily-boron-doped Si bulk substrate selectively to the lightly-boron-doped Si epi. The procedure can be used as a FC device sample preparation technique for back-side optical probing and FIB editing.
Environmental Control Scanning Nonlinear Dielectric Microscopy Measurements of p-n Structures, epi-Si Wafers, and SiC Crystal Defects
Authors: Yu Jing-jiang , Yamaoka T. , Hasumura S. , Hirose R. , Ando K. , Mizuguchi K. 
Published: December 2020

Abstract
Scanning nonlinear dielectric microscopy (SNDM) has improved significantly, achieving low-concentrated observations. Therefore, it is of great interest to observe how adsorbed water and other measurement environments influence SNDM measurements so that the material's dielectric properties can be detected. This study investigates how specific measurement environments, namely air, dry nitrogen, and vacuum environments, influence the SNDM and C-V curve measurements of semiconductor samples. The p-n structure created by ion implantation was measured by applied-DC-voltage SNDM, and in these environments, the corresponding C-V curves were obtained. As with the p-n structure sample, an abnormal result was obtained when a positive DC voltage was applied to an epi-Si sample in air. A low concentration level was clearly measured in vacuum. From these results, it can be concluded that measurement in a high vacuum is an effective way to obtain highly precise carrier distributions.
Tester Assisted Multiple Emission Microscopy
Authors: Hollerith Christian , Borgmann Gerhard , Schaller Wolfgang , Burmer Christian , Brillert Christof 
Published: December 2020

Abstract
Multiple emission microscopy can be used to obtain a comprehensive overview of device emission during IDDQ-test. In this new approach an emission microscopy image is taken for each pattern of the IDDQ-test. Then the extensive amount of images is analyzed for correlation with IDDQ current levels. As a result, for each increased current level concurrent spots can be identified and further analyzed.
Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges
Authors: Ismail Hashim , Keow Ang Chung , Siong Kenny Gan Chye 
Published: December 2020

Abstract
An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.
Body Effect Measurement in DRAM Cell Transistor Using Memory Test System
Authors: Jung Ilwoo , Choi Byoungdeok , Sung Bonggu , Kim Daejung , Kim Ilgweon , Kim Hyoungsub , Jin Gyoyoung 
Published: December 2020

Abstract
Body effect is the key characteristic of DRAM cell transistor. Conventional method uses a TEG structure for body effect measurement. But this measurement is not accurate, because TEG structure has only several transistors and it is located outside of the DRAM die. This paper suggests a viable method for measuring DRAM cell transistor body effect. It uses a memory test system for fast, massive, nondestructive measurement. Newly developed method can measure 100,000 DRAM cell body effects in two minute, without sample damage. The test gives one median value and 100,000 individual values of body effects. Median value of measured body effects is equal to the TEG body effect. An individual DRAM cell body effect has a correlation with the fin height.
Sample Chemical Staining and Latest Generation SEM Imaging—Characterizing Process Robustness in Semiconductor Manufacturing
Authors: Meyer Andreas , Langer Eckhard 
Published: December 2020

Abstract
Physical characterization of individual process steps and their interaction with other processes is a key element during development as well as manufacturing of semiconductor technology. This paper presents a number of examples that illustrate the usefulness of the combination of sample wet-chemical staining techniques with the latest generation SEM imaging capabilities. The examples show how sample preparation and imaging conditions have to be tailored to the specific needs. The combination of application-tailored chemical decoration with high-resolution material contrast SEM imaging has proven to be a powerful technique for the characterization of manufacturing process steps. Only with the novel imaging modes available in the latest generation SEM instruments, it became possible to perform investigations with fast turnaround times and on large sample areas.
Electrical Invasiveness of Grinding and Polishing Silicon Integrated Circuits Down to 1 μm Remaining Silicon Thickness
Authors: Chivas Robert , Silverman Scott , DiBattista Michael , Kindereit Ulrike 
Published: December 2020

Abstract
Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (&lt; 5 um global, ~ 1 um local) remaining thickness is presented.
Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset
Authors: Goxe Julien , Vanhuffel Béatrice , Castignolles Marie , Zirilli Thomas 
Published: December 2020

Abstract
Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.
Failure Analysis of Automotive Ultrasonic Parking Sensors
Authors: Flores Miguel Angel Neri , Villafañe Alberto Martinez , Carreño Caleb 
Published: December 2020

Abstract
Automotive ultrasonic parking sensors were analyzed using X- ray computed tomography (XCT or microtomography), in order to determine if there were internal failures generated on the soldering process between copper wires and piezoelectric ceramic on these sensors. This paper reports the use of X-ray radiography and computer image processing for the study of internal defects. By using X-ray tomography technique, pores, cracks, holes, solder balling, insufficient solder, lead related defects, device related defects, and solder bridging may be identified (1-2). When coupled with a real time radiographic detector and image processor, X-ray technology allows instantaneous radiographic imaging and semi-automatic or totally automatic inspection. Analysis was conducted on six produced test samples showing that the application of XCT as a method of quality control of specimens produced by electronic packaging offers a wide range of possibilities to detect defects within materials. There were determined that five sensors contain internal defects on the soldered joints, between the copper wire, and the piezo electric ceramic covered with silver paint, as shown on the computed tomography. Accuracy of XCT method strongly depends on the size of the samples analyzed, but the possibility of obtaining information in 3D nondestructively shows considerable advantages of XCT method over traditional metallographic cross-sectional analysis.
Studies and Application of Auger Monitoring System for Quality Control and Assurance of Al Bondpads
Authors: Younan Hua 
Published: December 2020

Abstract
In wafer fabrication (Fab), Fluorine (F) based gases are used for Al bondpad opening process. Thus, even on a regular Al bondpad, there exists a low level of F contamination. However, the F level has to be controlled at a lower level. If the F level is higher than the control/spec limits, it could cause F-induced corrosion and Al-F defects, resulting in pad discoloration and NSOP problems. In our previous studies [1-5], the theories, characteristics, chemical and physical failure mechanisms and the root causes of the F-induced corrosion and Al-F defects on Al bondpads have been studied. In this paper, we further study F-induced corrosion and propose to establish an Auger monitoring system so as to monitor the F contamination level on Al bondpads in wafer fabrication. Auger monitoring frequency, sample preparation, wafer life, Auger analysis points, control/spec limits and OOC/OOS quality control procedures are also discussed.
A New Methodology to Protect PCBs from Nondestructive Reverse Engineering
Authors: Guo Zimu , Shakya Bicky , Shen Haoting , Bhunia Swarup , Asadizanjani Navid , Tehranipoor Mark , Forte Domenic 
Published: December 2020

Abstract
Reverse engineering of electronic hardware has been performed for decades for two broad purposes: (1) honest and legal means for failure analysis and trust verification; and (2) dishonest and illegal means of cloning, counterfeiting, and development of attacks on hardware to gain competitive edge in a market. Destructive methods have been typically considered most effective to reverse engineer Printed Circuit Boards (PCBs) – a platform used in nearly all electronic systems to mechanically support and electrically connect all hardware components. However, the advent of advanced characterization and imaging tools such as X-ray tomography has shifted the reverse engineering of electronics toward non-destructive methods. These methods considerably lower the associated time and cost to reverse engineer a complex multi-layer PCB. In this paper, we introduce a new anti–reverse engineering method to protect PCBs from non-destructive reverse engineering. We add high-Z materials inside PCBs and develop advanced layout algorithms, which create inevitable imaging artifacts during tomography, thereby making it practically infeasible for an adversary to extract correct design information with X-ray tomography.
Device Dielectric Quality Analysis and Fault Isolation at the Contact Level by Scanning Microwave Impedance Microscopy
Authors: Hu Wei-Shan , Lee Jeng-Han , Kao Ming-Hong , Yang Hui-Wen , De Wolf Peter , Amster Oskar 
Published: December 2020

Abstract
Dielectric film quality is one of the most important factors that will greatly impact device performance and reliability. Device level electrical analysis techniques for dielectric quality monitoring are highly needed. In this paper we present results using a new electrical AFM mode, scanning Microwave Impedance Microscopy (sMIM), for characterization of device oxide quality and for fault isolation. Devices with poor oxide quality show sMIM nano C-V and dC/dV hysteresis behavior during forward and reverse bias sweep. The sMIM capacitance sensitivity is below 1 aF allowing one to capture C-V spectra from the MOS structure formed by the gate and gate oxide with excellent signal/noise ratio and observe subtle variations between different sites.
Failure Analysis Work Flow for Dislocation Identification and Characterization by Electron Channeling Contrast Imaging Using SEM and FIB
Authors: Zhou Yongkai , Han Luyang 
Published: December 2020

Abstract
A failure analysis work flow is presented demonstrating dislocation visualization, site isolation, TEM lamella preparation and defect characterization. A novel beam control technique allows visualizing dislocations with significantly improved spatial resolution in SEM using Electron Channeling Contrast Imaging. Site-specific TEM preparation on dislocations is therefore possible. The prepared thin lamella can be inspected in the SEM using STEM to study dislocations. This is a cost effective work flow without using TEM.
Advanced X-Ray Inspection Techniques for Counterfeit IC Detection
Authors: LaVoy Rosanne M. , Babian Fred , Reid Andrew 
Published: December 2020

Abstract
It is known by both the commercial and government suppliers, one of the best ways to guarantee the security and reliability of IC's is to image the IC directly using an x-ray microscope. These images can be inspected for many signs of counterfeit electronics. Unfortunately, previous generations of x-ray imaging systems have not kept up with the increasingly sophisticated counterfeiting techniques. Traditional 2D X-ray inspection techniques are becoming inadequate for imaging and verifying features due to the limited resolution of these systems for thick samples and because 2D images contain too many overlapping features to easily discern, making identification very difficult. This paper discusses the development of advanced sample preparation techniques for counterfeit IC detection. It presents information on the limitations of X-ray imaging and 3D tomographic reconstruction, and on the models for resolution configuration improvement.
Acoustic and Photoacoustic Inspection of Through-Silicon Vias in the GHz-Frequency Band
Authors: Brand Sebastian , Kögel Michael , Altmann Frank , DeWolf Ingrid , Khaled Ahmad , Moore Michael J. , Strohm Eric M. , Kolios Michael C. , Strohm Eric M. 
Published: December 2020

Abstract
Through Silicon Via (TSV) is the most promising technology for vertical interconnection in novel three-dimensional chip architectures. Reliability and quality assessment necessary for process development and manufacturing require appropriate non-destructive testing techniques to detect cracks and delamination defects with sufficient penetration and imaging capabilities. The current paper presents the application of two acoustically based methods operating in the GHz-frequency band for the assessment of the integrity of TSV structures.
Optical Investigations of Temperature Effects in 14/16 nm FinFETs
Authors: Vogt Ivo , Boit Christian , Nakamura Tomonori , Motamedi Babak 
Published: December 2020

Abstract
This paper provides a detailed analysis on the optical detection of temperature effects in FinFETs via (spectral) photon emission microscopy (SPEM/PEM) with InGaAs detector and electro-optical frequency mapping (EOFM, similar to LVI) for 14/16 nm Qualcomm Inc. FinFETs. It analyzes physical parameters of the FinFETs such as electron temperature and the relation between signal curve and operating condition of the device by photon emission slopes and spectra. The paper also traces device self-heating effects within the FinFETs by means of EOFM signal courses. With EOFM it was possible to detect self-heating effects of the FinFETs providing a further method to estimate device and substrate heating. Results showed that it is possible to obtain valuable device parameter information (for example, electron temperatures and self-heating) via optical investigations (PEM/ EOFM), which are not accessible electrically in modern integrated circuits. This information adds further details to device reliability and functionality approximations.
Conductive-AFM for Failure Analysis of Parametric Test Structures in Advanced Technology Development
Authors: Zhang Chuan , Chen Esther P.Y. 
Published: December 2020

Abstract
A variety of parametric test structures were designed with the purpose of characterizing parameters tied to failure modes for specific structures, and the electrical test of the parametric test structures are typically conducted earlier inline, which could be months ahead of the functional test. Due to the unique advantages, conductive-atomic force microscopy (CAFM) was introduced to parametric test structure failure analysis during advanced technology development, and has been proven to be a powerful solution to many challenging failure analysis (FA) problems. This paper uses several case studies to illustrate how CAFM can be used to successfully localize defects in challenging parametric test structures that would otherwise be invisible with conventional FA techniques.
Exploring the Physical Limits of Gallium-Based Focused Ion Beam Chip Circuit Editing
Authors: Herschbein Steven B. , Scrudato Carmelo F. , Hermann Edward S. , Wagner Raymond L. 
Published: December 2020

Abstract
This paper describes a circuit editing procedure in which the authors used a gallium column Focused Ion Beam (FIB) tool to divide a merged 32nm multi-finger planar transistor into two separate operating components. Rather than rely on live imaging or the various endpoint detection techniques commonly used during an active mill, the authors opted for a ‘blind’ dose-driven technique. The paper explains how the authors made multiple attempts on practice material in order to determine the exact beam placement location and the depth of cut required to perform the operation with a minimum of lateral damage. The loss of a pair of poly gate fingers in the middle of the multi-gate structure seemed to have minimal impact on the final electrical parameters and the separate data paths worked per design specifications.
Backside Protection Structure for Security Sensitive ICs
Authors: Amini Elham , Muydinov Ruslan , Szyszka Bernd , Boit Christian 
Published: December 2020

Abstract
Modern integrated circuits (ICs) are in permanent risk of hardware attacks on sensitive data. But, proper and affordable protection of the IC backside against Focused Ion Beam (FIB) and optical fault injection attacks is missing. In this work, we investigate a patent [1] that uses p-n junctions as light emitters (forward bias) and detectors. We improved the backside detection mechanism presented in the patent by developing a test structure and adding an optically active layer on the backside as protective element to detect an attacked backside with electrical signals in the IC. The angle dependent reflection provided by the layer acts as the protective function. We demonstrate how the light emission and detection concept is quantitatively working and how the active layer produces a backside layer integrity related signal in the IC which can act as attack indicator. We also show that, due to the weak light emission intensity of silicon and the high excitation current, influences such as multi-angle reflection and stray current are reducing the angle-dependent effect on the signal and have to be taken into account in practical use.
Power MOSFET Failure Analysis and Package Effects in 3-Phase, Half-Bridge Applications and Design Improvements
Authors: Dipsey Mark , Kearney Ian 
Published: December 2020

Abstract
The degraded performance of a power MOSFET affects customer system reliability and consumer perceptions of quality. Building a reliable product and associated application specific lifetime models to predict the suitability of a power device for a given solution can enable competitive advantages, increased quality, enhanced performance and result in market share gains. This paper describes the methodology employed to configure an application specific reliability test, the failure rates and modes observed, the package modelling, and design improvements implemented. The validation of such relative to its original form and competitor products is discussed where we demonstrate a doubling in performance and an approximate 50% increase in current handling capability. This type of analysis and application specific approach to innovation enables one to focus design improvements in areas most relevant to customer concerns while at the same time adding credibility to specified product limits.