Post-Annealing on the Ohmic Contact and Gate Recess Simultaneously in AlGaN/GaN MIS-Hemt
Authors: Shen Pei-Chien , Ho Wei-Cheng , Tsai Ming-Yan , Hsin Yue-Ming 
Published: February 2020

AlGaN/GaN HEMTs have been widely used in RF power amplifiers and power switching circuits. The primary reasons are because of high electron mobility and high breakdown electric field in GaN materials. Moreover, a 2DEG formed from polarization effects at the AlGaN/GaN heterojunction enables a low channel resistance and thus a low on-resistance. However, devices fabricated with the inherent 2DEG channel are depletion-mode FETs. For practical applications, it prefers an enhancement-mode (E-mode) device with the threshold voltage > 0 V. The common approaches to implement an E-mode device include gate recess, p-GaN layer, and F-ion treatment. The p-GaN layer used to deplete the channel underneath the gate at 0V and induce 2DEG with positive gate bias. But the gate swing voltage is limited due to the gate leakage current. The F-ion treatment under the gate has a reliability issue. The gate recess combined an insulator layer device (MIS-HEMT) is practical for E-mode operation to achieve the high gate voltage swing and low gate leakage current. However, the damage from gate recess and the relatively poor MOS interface between GaN and the insulators are problems to be overcome. Conventional E-mode MIS-HEMT fabrication starts with high-temperature annealing to ohmic contact then gate recess for gate metallization. Second annealing is required to reduce the gate recess damage. In this study, we did not anneal the device for ohmic contact first but anneal the device after the gate recess with suitable conditions to achieve a good ohmic contact and reduce recess damage. By the post-annealing on the ohmic contact and gate recess simultaneously, the interfacial density of state (Dit) of MIS in the E-mode MIS-HEMT was improved with low contact resistance.
The epitaxial layers were grown by MOCVD including a ~3900-nm buffer layer, a 325-nm GaN channel layer, a 1-nm AlN spacer layer, a 21.5-nm Al0.25Ga0.75N barrier, and a 4.1-nm in-situ SiN cap layer. First, device isolation was implemented by ICP etching down to the buffer layer. The ohmic contact was made by the deposition of Ti/Al/Ni/Au (25/125/45/55 nm) without annealing. Using ICP to perform gate recess, and then annealed by RTA at 875 °C in an N2 circumstance for 40 s. The gate dielectric SiN was deposited at 300 °C by PECVD, then annealed by RTA at 450 °C for 1 min in an N2 circumstance. Ni/Ti/Al/Ti/Au (30/25/250/25/200 nm) metal stack was used to form gate metal contact. Finally, the devices were passivated by a 200-nm SiN deposited by PECVD.
The C-V and I-V characteristics of fabricated devices were measured by the Agilent B1500A and B1505A. The leakage current was reduced in the devices with proposed annealing. Double sweep C-V characteristics at 100-kHz of devices with proposed annealing step show a smaller hysteresis and lower flat band voltage shift than devices with traditional ohmic annealing. Moreover, the frequency dependent C-V measurements show that device with proposed annealing step effectively reduces the dispersion phenomenon. Conductivity method was applied to extract interface trap density as a commonly used analytical method for the III-V materials [3]. The calculated Dit of the device with proposed annealing step shows lower interface trap density than the device with traditional ohmic annealing. The calculated Dit was reduced from 7.1E12 to 4.8E12 eV-1cm-2. As a result, annealing after gate recess can really improve the interface quality and reduce the damage from dry etching, and form good ohmic contact without the extra annealing step.

Figure 1