Self-Aligned Bottom-Gate InGaZnO Thin-Film Transistor with Source and Drain Regions Formed by Selective Deposition of Fluorinated SiNx Passivation
Authors: Furuta Mamoru , Jiang Jingxin , Tatsuoka Gengo , Wang Dapeng 
Published: February 2020

Since the report of an amorphous InGaZnO thin-film transistor (IGZO TFT)[1], many researches have been focused on achieving high performance and high stable oxide TFTs for next generation display. Bottom-gate type with a SiOx etch-stopper have been widely employed for IGZO TFTs. However, one of serious drawbacks of this structure is a large parasitic capacitance of gate-to- drain (CGD) and source (CGS) due to overlap between gate and source/drain (S/D) electrodes. It is known that large parasitic capacitance reduces operation speed of the TFT circuits and induces signal delay of the TFT backplane. Moreover, large CGDof select TFTs in organic light emitting diode (OLED) display strongly influences uniformity of the luminescence of the pixels because the CGD is the main cause of kickback/feedthrough voltage which influences an operation voltage of driving TFTs. Self-aligned (SA) structure is an essential for reducing parasitic capacitance in the TFTs. There are several reports of IGZO homojunction with highly conductive IGZO for source/drain regions which were formed by selective exposure of Ar, H2, or He plasma or ion implantation. [2-4] On the other hand, the IGZO homojunction was demonstrated by hydrogen diffusion from hydrogenated SiNx (SiNx:H) deposited on top of the IGZO.[5] In this paper, we developed the IGZO homojunction with thermally stable S/D regions that was formed by a direct deposition of fluorinated SiNx (SiNx:F) on top of the IGZO. By combining the back-side exposure (BSE) technique and IGZO homojunction formed by the direct deposition of SiNx:F, the SA IGZO TFT are demonstrated.
Figure 1(a) and 1(b) show cross sectional views of the SA IGZO TFT with SiOx and SiN:F passivation, respectively. First, Cr gate electrode was formed on a glass substrate. Next, a 150-nm thick SiOx for gate insulator, a 45-nm-thick IGZO for active channel, and a 100-nm-thick SiOx for etch stopper (ES) were deposited. Then, ES layer was aligned by the BSE technique used gate electrode as a mask, and was etched by a dry etching with CF4/O2 plasma. After patterning of the IGZO channel as an active channel, fluorinated SiNx (SiN:F) for passivation was deposited by an inductively-coupled plasma chemical vapour deposition using SiF4+N2 gas mixture as shown in FIg. 1(b). Note that hydrogen-free gas chemistry was used for the SiNx:F deposition. An IGZO TFT with SiOx passivation (deposited by conventional plasma-CVD using SiH4/N2O/N2 gases) was also fabricated for comparison as shown in Fig. 1(a). S/D electrodes were formed by ITO via contact holes. It is noted that there is no overlap region between gate and S/D electrodes. The TFT properties were measured after post fabrication annealing at 300 ºC in N2 for 1h.
Figure 1(c) and 1(d) show transfer characteristics of the IGZO TFTs with SiOx and SiNx:F passivation, respectively. On current of the IGZO TFT with SiOx passivation was suppressed due to series resistance of the S/D region. This result indicates that ES dry etching with CF4/O2 plasma did not contribute to form highly conductive S/D region. In contrast, the TFT with SiNx:F passivation exhibited good electrical properties with the field effect mobility of ~10 cm2/Vs. The bottom-gate SA IGZO TFT with homojunction can be achieved by a direct deposition of SiNx:F on the S/D regions.
Authors would like to thank Tokyo Electron Co., Ltd. for their supports and useful discussion regarding the SiNx:F films. This work is supported in part by JSPS KAKENHI Grant No. 23560408.
[Ref]
1) Nomura et al., Nature 432, 488 (2004)
2) J.-S. Park et al., Appl. Phys. Lett. 90, 262106 (2007)
3) H. Jeong et al., Appl. Phys. Lett. 104, 022115 (2014)
4) R. Chen et al., IEEE Elec. Dev. Lett., 33, 1150 (2012)
5) A. Sato et al, Appl. Phys. Lett. 94, 133502 (2009)