bluuebunny/crossref_metadata_2025_split huggingface dataset:
(Invited) Defect Engineering in Ge QDs for Light Emission in Si Photonics
Authors: Brehm Moritz 
Published: February 2020

The search for a practical, low-cost and monolithic light source that allows for straightforward implementation on CMOS-based microprocessors and that can be easily coupled to existing active and passive Silicon photonics components is ongoing. In this presentation, we will demonstrate an alternative approach to hybrid III-V on Si and strained bulk group-IV (Ge, GeSn) light emitters. This concept makes use of epitaxially grown Ge quantum dots (QDs) in a defect-free crystalline Si matrix, as they are known since the early nineties [1-3]. However, we will show that the light emission properties of such Ge/Si QDs can be boosted by intentional, low-dose and low-energy implantation of heavy ions (such as Ge and Si) into the QDs. We demonstrate CMOS-compatible lasing from these novel QDs in which defined point-defects states spatially confine electrons after their tunnelling into the nanostructures [1-4]. This leads to optically direct transitions and, hence, efficient light emission. In contrast to conventional epitaxial Ge/Si QDs - these defect-enhanced QDs (DEQDs) exhibit dramatically shortened carrier lifetimes and negligible thermal quenching of the photoluminescence above room-temperature (RT) [1]. Embedding the DEQDs into microdisk resonators leads to lasing characteristics up to RT upon optical excitation [3]. Contact doping and hence fabrication of electrically driven devices is straightforward in this nanosystem since DEQDs are embedded into a defect-free Si matrix. LEDs containing DEQDs show bright emission up to 100°C, the temperature limit of the measurement setup [5].
[1] Grydlik, M.; Hackl, F.; Groiss, H.; Glaser, M.; Halilovic, A.; Fromherz, T.; Jantsch, W.; Schäffler, F.; Brehm, M. ACS Photonics
2016, 3 (2), 298–303
[2] Grydlik, M.; Lusk, M. T.; Hackl, F.; Polimeni, A.; Fromherz, T.; Jantsch, W.; Schäffler, F.; Brehm, M. Nano Lett.
2016, 16 (11), 6802–6807
[3] Brehm M. and Grydlik, M. Nanotechnology
2017, 28, 392001
[4] Groiss H., Spindlberger L., Oberhumer P., Schäffler F., Fromherz T., Grydlik M. and Brehm M, Semicond. Sci. Technol.
2017 32 (2), 02LT01
[5] Rauter P., Spindlberger L., Schäffler F., Fromherz T., Freund J., and Brehm M., ACS Photonics
2018, 5 (2), pp 431–438
(Invited) Scalable, Layer-Controlled Synthesis of 2D Semiconductors
Authors: Chiappe Daniele , El Kazzi Salim , Afanasiev Valeri , Leonhardt Alessandra , Ludwig Jonathan , Celano U. , Brems Steven , Pourtois Geoffrey , Caymax Matty , Schram Tom , Huyghebaert Cedric , Asselberghs Inge , De Gendt Stefan , Radu Iuliana 
Published: February 2020

The rapid cadence of MOSFET scaling is stimulating the development of new technologies and accelerating the introduction of new semiconducting materials as silicon alternative. In this context, transition metal dichalcogenides (TMDs) with a unique layered structure have attracted tremendous interest in recent years mainly motivated by the characteristic 2D nature together with distinctive and tunable optoelectronic properties which make them appealing for a wide variety of applications. Their ultra-thin body nature, in particular, is expected to provide superior immunity to short channel effects therefore extending the potential to scale transistors down to the few-nanometer-scale. [1-4] Another key feature of 2D materials is the absence of surface dangling bonds. The latter property has the potential to eliminate lattice mismatch constraints thus paving the way for hybrid integration of TMDs into artificial heterostructures with sharp interfaces and designed band alignment. As researchers explore the physics and applications of layered semiconductors, it is now becoming important to find a wafer-scale path towards technology implementation and integration of these novel materials.
In this context, it has been recently demonstrated that metal-organic chemical vapor deposition (MOCVD) can be used to manufacture large area 2D semiconductor materials. [5]. The goal of this work is to unravel some of the fundamental aspects of film formation and provide a pathway towards a layer-controlled, wafer-scale synthesis of TMD films. More in details, we will provide insights on the different growth mechanisms of TMD films on amorphous and crystalline templates. In this framework, we will discuss the key aspects to enable and control a real van der Waals epitaxy of TMD films. The target, of course, is to achieve unidirectional and high quality monocrystalline domains by forcing an epitaxial relationship between the 2D film and the underlying substrate. In-depth structural AFM, XPS, TEM analyses along with Raman, Photoluminescence and lifetime measurements are used in our study. In order to establish a direct link between electrical performance and material quality, FET devices using our layers are also fabricated. A careful link between the structural analyses and the electrical results is made in order to asses material quality and offer a step further on the understanding of 2D TMDs for nanoelectronics.

B. Radisavljevic et al. Nature Nanotechnol., 6, 147 (2011).

R. Ganatra and Q. Zhang, ACS Nano, 8, 4074 (2014).

A. Nourbakhsh et al. Nano Lett., 16 7798 (2016).

A. Nourbakhsh et al. Nanoscale, 18, 6122 (2017).

K. Kang et al. Nature volume 520, 656 (2015)
(Invited) Epitaxy and Applications of Group-IV Semiconductors in Quantum Computing
Authors: Scappucci Giordano 
Published: February 2020

The first quantum revolution provided a microscopic understanding of nature and underpinned the development of transistors, originally made in germanium. The following assembly of silicon transistors into integrated circuits triggered the digital age, which completely changed our daily life. We are now in the midst of the second quantum revolution, in which quantum matter is engineered to develop disruptive technologies beyond the reach of classical understanding.

Quantum computing is considered by many the man on the moon goal of such second quantum revolution. How will we get there? In this talk I will discuss, from a materials perspective, how we are turning everyday silicon into the quantum computing wonder material by using quantum dots defined electrostatically in SiGe heterostructures.

Group-IV semiconductors Si and Ge offer several advantages for the realization of spin quantum bits. Si and Ge can be isotopically purified into a nuclear spin free materials, which allows long spin coherence time. A quantum dot defined by metallic gates in a strained Si/SiGe heterostructure can trap a single electron, such that the electron spin can be operated as a quantum bit, the elementary unit of quantum computation. Quantum dots in Si/SiGe heterostructure are promising because bear similarities from a materials and integration perspective to the transistors used in advanced semiconductor manufacturing. Advanced quantum control in Si qubits allows to run quantum algorithms on two qubit processors. Strong spin-photon coupling has been achieved in Si, a first step towards realizing large networks of quantum dot based spin qubit registers.[1] Additionally, SiGe heterostructures allows us to explore high mobility holes in strained Ge as a complementary option for fast quantum hardware due to the different band structure properties of Ge compared to Si. Recently, gate-controlled stable quantum dots were demonstrated in planar Ge, a first step towards Ge hole qubits.[2]
However, to deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. In this talk we will focus on carrier mobility and energetic valley splittings in SiGe heterostructures, which are two key electrical metrics of substrate quality relevant for qubits. To ensure rapid progress in quantum wells development we have implemented fast feedback loops from materials growth, to innovative heterostructure field effect transistor fabrication, and low temperature characterization. In this direction we show progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

[1] N. Samkharadze, G. Zheng, N. Kalhor, D. Brousse, A. Sammak, U. C. Mendes, A. Blais, G. Scappucci, and L. M. K. Vandersypen, Science , eaar4054 (2018).
[2] N. W. Hendrickx, D.P. Franke, A. Sammak, M. Kouwenhoven, D. Sabbagh, L. Yeoh, R. Li, M. L. V. Tagliaferri, M. Virgilio, G. Capellini, G. Scappucci, M. Veldhorst, arXiv:1801.08869 (2018)
(Invited) Compact Telluride Films Prepared By Electrochemical Deposition and Their Applications for Integrated Micro- Thermoelectric Devices
Authors: Li Guodong , Garcia Javier , Sieger Tom , Schnatmann Lauritz Ule , Lara Ramos David Alberto , Barati Vida , Perez Rodriguez Nicolas , Reith Heiko , Schierning Gabi , Nielsch Kornelius 
Published: February 2020

Thermoelectric materials of Tellurium (Te) and its based compounds (binary Bi2Te3 and Sb2Te3, or ternary Bi2(TexSe1-x)3 and (BixSb1-x)2Te3) as the n-type and p-type materials, respectively), possess the best thermoelectric figure-of-merit in the temperature range of room temperature up to 200 °C. Preparing thick and compact Telluride films with thickness in the range of tens of micrometers by electrochemical deposition (ECD) allows to realize on-chip integration of thermoelectric devices. ECD offers additional advantages regarding up-scalability, cost effective processing, and compatibility with microelectromechanical systems processing.
In our work, we firstly put efforts on growing thick and compact Telluride films for both n- and p- type materials by ECD technique. Secondly, various measurement techniques (in-situ and ex-situ) are utilized to characterize the thermoelectric transport properties, which are further analyzed to tune the ECD parameters to optimize the material properties. Thirdly, integrated micro- thermoelectric coolers (µTECs), with a leg pair packing density over 5000/cm2 are successfully fabricated by combining conventional techniques of ECD and photolithography. Long-term performance and stability of the as-fabricated µTECs are systematically studied using a CCD-based thermoreflectance imaging setup. Finally, model simulations based on finite-element method show consistency with the experimental results, indicating high quality thermoelectric materials (for both n and p legs) and negligible contact resistances in the as-fabricated µTECs.
(Invited) Controlling Electron and Photon Transport Via Nanoengineering
Authors: Xiong Ze , Tang Jinyao 
Published: February 2020

Nanostructured materials behave dramatically different from their bulk counterpart in both electronic properties as well as thermal transport properties. With the immerging low dimensional materials such as nanowires or two-dimensional materials, the research interest has been focused on nanoengineering these materials for different applications including high-performance thermoelectric generator and effective thermal management. On the other hand, these newly developed material systems also arises new scientific questions and offers great opportunities to fundamentally understand the transport physics in nanostructures.
In this work, we would like to present two examples of nanoengineering low dimensional materials to modify their thermoelectric and thermal transport properties which addresses both graphene and semiconductor superlattice nanowires respectively. It is well known that graphene is an excellent candidate electronic material due to its high carrier mobility as well as it is ultrahigh thermal conductivity. Notably, with high thermal conductivity, the thermal management in graphene-based electronic circuit is considered a superior to silicon-based devices. However, this conclusion is based on previous studies on the pristine graphene sheet instead of nanopatterned graphene. We studied the thermal transport behavior of graphene nanomesh with high-density nanoholes and discovered the substantial thermal conductivity suppression with the introduced patterns. This study highlighted the importance of the phonon backscattering inside the two-dimensional graphene system and the thermal management may be more difficult than previously estimated in graphene electronics.
On the other hand, while the thermal conductivity reduction in nanoengineered materials has been demonstrated in many studies, the Seebeck enhancement in nanomaterials was seldom observed. Previously, it has been predicted that the energy filtering effect in superlattice materials may induce an enhanced Seebeck coefficient in nanomaterials. However, since the superlattice materials is usually prepared by high-cost vapor-phase method which cannot be applied to large-scale application. Here, we harnessed the lattice strain of the epitaxy junctions and developed a solution based chemical synthesis method to prepare superlattice nanowires. We compared the Seebeck coefficient and electrical conductivity of the superlattice nanowire which demonstrated energy filter effect and enhanced thermoelectric properties.
Reference:

Z. Xiong, X. Wang, H. K. Lee, J. Zhan, Y. Chen, J. Tang, Thermal Transport in Supported Graphene Nanomesh.
ACS Appl. Mater. Interfaces

Article ASAP (2018)

Z. Xiong, Y. Cai, X. Ren, B. Cao, J. Liu, Z. Huo, J. Tang, Solution-Processed CdS/Cu2S Superlattice Nanowire with Enhanced Thermoelectric Property.
ACS Appl. Mater. Interfaces
9 (38), 32424 (2017)

Figure 1
Using Electrochemically Exfoliated Graphene As a Conductive Layer of a Printed Circuit Board
Authors: Chang Shuo-Wen , Dow Wei-Ping 
Published: February 2020

Graphene is a popular material because of its unique two-dimensional (2D) structure and intrigued physical and chemical properties. Graphene obtained from chemical exfoliation is usually prepared by oxidizing graphite in a mixing solution containing strong acids and oxidants, which severely destroys the honeycomb lattices of graphene and deteriorates its performance even though these defects could be recovered partly by subsequent reduction process.[1, 2] Recently, electrochemical exfoliation of graphite has attracted attention due to its easy, fast and environmentally friendly nature to produce high quality graphene.[3] In this study, one step electrochemical process not only can synthesize exfoliated graphene oxide (GO) but also can dop in the GO with heteroatoms. After grafting the exfoliated GO on a printed circuit board (PCB), the subsequent reduction of GO sheets to graphene recovers the graphitic structure as a conductive layer. We discussed the effect of electrochemically exfoliated GO on copper electroplating on a PCB. The operating parameters which influence the electron transfer on the electrochemically exfoliated GO, such as electrolytes, operating currents and graphite source, were investigated by using several analysis methods, such as atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS) and Raman spectroscopy techniques.

Keywords:

Electrochemical exfoliation, Graphene oxide, Conductive layer, Printed Circuit Board

Reference:

[1] S. Park, and R. S. Ruoff, “Chemical methods for the production of graphenes,” Nature nanotechnology, vol. 4, no. 4, pp. 217, 2009.
[2] X. Li, H. Wang, J. T. Robinson, H. Sanchez, G. Diankov, and H. Dai, “Simultaneous nitrogen doping and reduction of graphene oxide,” Journal of the American Chemical Society, vol. 131, no. 43, pp. 15939-15944, 2009.
[3] K. Parvez, R. Li, S. R. Puniredd, Y. Hernandez, F. Hinkel, S. Wang, X. Feng, and K. Müllen, “Electrochemically exfoliated graphene as solution-processable, highly conductive electrodes for organic electronics,” ACS nano, vol. 7, no. 4, pp. 3598-3606, 2013.
(Invited) Fine Temperature Monitoring of Si Wafer for Plasma Processing
Authors: Ito Masafumi , Tsutsumi Takayoshi , Ohta Takayuki , Hori Masaru 
Published: February 2020

One of the critical parameters in many semiconductor-processing steps such as plasma etching, chemical vapor deposition, and so on, is the substrate temperature. For example, the etch rate and etch profile are sensitive to the substrate temperature in the plasma etching process. However, contact measurement such as thermo-couples and fluorescent temperature sensor cannot measure the accurate temperature, especially in low pressure due to poor thermal transfer between the wafer and the probe.
We have developed the non-contact temperature measurement of substrates by using optical low-coherence interferometer. [1-6] The low-coherence interferometry is based on Michelson interferometry, and a white light such as a super-luminescent diode (SLD) was used as a low-coherence light source. SLD has the central wavelengths of 1325 nm and the full width at half maximum of 64.5 nm. The light which is reflected at the surface of Si substrate interfered with the light reflected at the scanning reference mirror. The interfered light was detected with a spectrometer and the signal which is a frequency domain spectrum was converted to a time domain signal by inverse Fourier transformation. The temperature of the Si substrate is derived from the change in the optical path length of Si substrate due to thermal expansion and changes in the refractive index.
The temperatures of Si wafer and chamber parts made of Si were successfully monitored in the SiO2 plasma etching using capacitively coupled plasma. The performance was compared with that of fluorescent temperature sensor. From these results, we have demonstrated highly precise and rapid response measurement of the temperature of Si wafer at real time by using Fourier domain low coherence interferometer.

References

[1] K. Takeda et al., “Temperature-Measurement System Using Optical Fiber-Type Low-Coherence Interferometry for MultiLayered Substrate” Jpn. J. Appl. Phys., 43, 7737 (2004).
[2] T. Ohta et al., “Simultaneous measurement of substrate temperature and thin film-thickness on SiO2/Si wafer using optical fiber-type low-coherence interferometry”, J. Appl. Phys., 105, 013110 (2009).
[3] C. Koshimizu et al., “Low-coherence interferometry - based non-contact temperature monitoring of a silicon wafer and chamber parts during plasma etching”, Appl. Phys. Express, 3, 056201 (2010).
[4] C. Koshimizu et al., “Simultaneous In situ Measurement of Silicon Substrate Temperature and Silicon Dioxide Film Thickness during Plasma Etching of Silicon Dioxide Using Low-Coherence Interferometry”, Jpn. J. Appl. Phys., 51 046201 (2012).
[5] H. Yamamoto et al., “Feature Profiles on Plasma Etch of Organic Films by a Temporal Control of Radical Densities and Real-Time Monitoring of Substrate Temperature”, Jpn. J. Appl. Phys., 51 016202 (2012).
[6] T.Tsutsumi et al., “Rapid measurement of substrate temperatures by frequency-domain low-coherence interferometry”, Appl. Phys. Lett. 103, 182102(2013).
Solution Based Al2O3 Gate Insulator for Low Temperature Poly Silicon TFT
Authors: Yang Hee Chan , Hwang Sang Ho , Baek Yeong Jo , Lee Sang Min , Okada Tatsuya , Noguchi Takashi , Bae Byung Seong 
Published: February 2020

Solution based insulator was applied for low temperature poly silicon thin film transistor (TFT). Solution process has several advantages of low cost, short process time and no plasma damage. Several kinds of solution-based materials were tested for TFTs, including organic insulators. In this paper, we present the aluminum oxide gate insulator based on solution process.
For poly-silicon process, amorphous silicon is deposited by sputtering and crystallized by blue laser diode annealing. After pattering of the poly-silicon, gate insulator of Al2O3 was formed by solution process. After gate insulator etching, source/drain metal was deposited and patterned. Low temperature process below 400℃ for all TFT fabrication with low cost has been developed and reported.
The insulator was characterized with the metal-insulator-semiconductor (MIS) structure. 0.8 M Al(NO3)39H2O solution with DMAC (Di-methyl-acetamide) was coated on the Si-wafer. The surface of silicon wafer was treated with oxygen plasma before coating to improve the adhesion. After spin-coating, it was baked at 150℃ for 5 min. It was annealed finally at 300℃ for 1 h.
To improve the insulator performance, the multi coating was tested. After coating and baking, it was coated again. Figure 1 shows the I-V characteristics for the sample coated for three times. As the number of coating increased, leakage current was reduced and the break down voltage increased.

Figure 1
Clock-Generator Embedded Charge Pump Circuit Using Oxide TFT
Authors: Kang Min Su , Kang In Hye , Han Ye Lin , Hwang Sang Ho , Baek Yeong Jo , Lee Sang Min , Bae Byung Seong 
Published: February 2020

Wearable device refers to a device that is always in contact with the body beyond the carrying smartphone. For wearable applications, flexibility is important, which need the integration of the circuit on a substrate. With the discrete devices, it is difficult to bend.
In wearable device, information should be displayed. For the display, drive circuit is necessary. With a battery, we need some boost up circuit such as charge pump for driving of the display. The charge pump need clocks which should be supplied by separate source. In this paper we embedded the clock generator in charge pump circuit.
Charge pump are used in almost all mobile devices and provide a stable output voltage under unstable power condition. Among several types of charge pumps, Dickson type charge pump has been used widely in traditional industrial applications.
In the charge pump circuit, two square waves are alternately applied. At the first stage, the capacitor is charged equal to the supply voltage. In the second stage, the circuit is connected in series with the power supply and the load.
Finally, the voltage across the load increases to twice the sum of the supply voltage and the capacitor voltage. Figure 1 shows proposed charge pump circuit with embedded clock generator and the output voltage of it. The circuit that generates the clocks CK and CKB is necessary for driving the charge pump circuit. The clock generator has the same configuration as the RC oscillator and alternately outputs square wave of 1.5 V.
As shown in Fig. 1, the output voltage is about 6 V when the input voltage is 1.5 V. The output voltage increases linearly with respect to the input voltage. The output voltage variation according to the number of TFTs are also investigated. As the number of TFTs increases, the output voltage increases.

Figure 1