bluuebunny/crossref_metadata_2025_split huggingface dataset:
A Study of Photoelectron Emission Microscopy Contrast Mechanisms Relevant to Microelectronics
Authors: Ballarotto Vincent , Siegrist Karen , Williams Ellen , Vanderlinde William 
Published: December 2020

Abstract
We report on a quantitative investigation of doping-induced contrast and topography-induced contrast in photoelectron emission microscopy (PEEM). Calibration samples were fabricated using standard photolithography and focused ion beam writing to test both types of contrast. Using a near-threshold light source, we find that the doping-induced contrast increases monotonically with B concentration over the measured range of 1017 – 2x1020 cm-3. The variation in doping-induced contrast as incident photon energy is varied was also investigated. Optimal doping-induced contrast and PEEM sensitivity is achieved by imaging with photon energy slightly above the highest nominal photothreshold of interest. The photoemission model, based on near-threshold emission, used to describe doping-induce contrast gives good agreement with the measured intensities. Thus, measuring the relative intensity ratio provides a robust technique for determining doping levels. Topography-induced contrast was investigated by imaging Ti samples of various step heights (75, 150, 290, and 550 nm). Image data suggests that edge contrast increases with step height. Numerical simulations show that non-uniform electrostatic fields at step edge are responsible for this contrast. Experimentally, we systematically vary the lateral field strength and show that edge contrast can be controlled. This technique could be useful in failure analysis by identifying breaks in metal lines.
Orientation Imaging Microscopy Applications in Cu- Interconnects and Cu-Cu Wire Bonding
Authors: Ratchev Petar , Carbonell Laureen , Ho Hong Meng , Bender Hugo , De Wolf Ingrid , Verlinden Bert 
Published: December 2020

Abstract
In this paper we described a technique which is not commonly used for failure analysis: Orientation Imaging Microscopy (OIM). We demonstrated that it offers unique opportunity for failure analysis of Cu bonding and interconnects. Additionally to its main application: texture analysis, it can also reveal early stages of oxidation of Cu bond pads and interconnects. A link has been made between oxidation and bondability. OIM can also show areas of the wire bond where the deformation concentrates due to the bonding process.
Passivation Damage and Residue-Induced Package Failure Analysis for a 16 Lead SOIC GaAs RF/IF Package
Authors: Cavasin Daniel 
Published: December 2020

Abstract
Recently, Motorola was notified that certain of their RFIC devices had failed electrically during Accelerated Life Testing (ALT) at their customer’s board-mounting facility. These devices were assembled in both 8 and 16 lead narrow-body SOIC packages, and had been previously qualified ‘by comparison’ as JEDEC Moisture Sensitivity Level (MSL) 1, indicating that the packages could be shipped without dry packing and left indefinitely at factory-level temperature and humidity, without the need for pre-baking before surface mount reflow. The returned parts exhibited delamination of the mold compound from the die surface, in some cases resulting in wire bond lifting. Since the parts had been shipped as MSL1 for several years in some cases, it was not deemed necessary to investigate whether the customers, Motorola N.S.S. in Fort Worth, TX, and Swindon, U.K., had implemented any changes in their handling procedures which may have impacted the MSL performance of the packages. At the beginning of February, 2000, because of the fact that the SOIC packages were assembled at an external subcontract facility, the issue was brought to the attention of the Motorola External Manufacturing Quality (EMQ) and External Final Manufacturing (eFM) organizations. A containment action was immediately implemented at the assembly site, which consisted of large-scale Scanning Acoustic Microscope (SAM) inspection of the assembled devices, to identify delamination after post mold cure (PMC). A separate series of more in-depth engineering analyses were also initiated, centering on three main areas: 1, Possible die surface contamination; 2, Possible mold compound material issues, and 3, Possible molding process variation. All such activities were conducted with the support and assistance of the IC packaging subcontractor. Results gathered from these activities are summarized below.
A Broadband Model for Ultrasonic Pulses in the Presence of Thin Layers in Microelectronics
Authors: Canumalla Sridhar 
Published: December 2020

Abstract
A broadband model is proposed to describe the nature of ultrasonic pulses in multilayered systems with a sub-wavelength thickness layer. This model, which is targeted towards acoustic microscopy of microelectronic devices, can incorporate measured ultrasonic properties of electronic materials and predict the complete ultrasonic pulse-train for all the interfaces in an electronic device. The model is robust, and incorporates material and geometric variables commonly encountered in microelectronics applications. Results are presented to illustrate how delaminations and cracks with foreign material or moisture ingress can appear to be well-bonded and why acoustic images of interfaces with thin layers can sometimes give erroneous indications of the bond state.
High Resolution Backside Thermography Using a Numerical Aperture Increasing Lens
Authors: Thorne S. , Ippolito S. , Eraslan M. , Goldberg B. , Ünlü M.S. , Leblebici Y. 
Published: December 2020

Abstract
As the feature size in integrated circuits (ICs) become smaller, the techniques we use to localize defects must also progress to the level that they can resolve potential errors. Additionally, because most errors cannot be identified by visual inspection alone, it is necessary to develop techniques, such as thermography, with the capability of localizing failures to the specific component or defect at fault. This paper will review the theory and application of an advanced subsurface (through the substrate) analytical technique for IC failure analysis – solid immersion lens thermal emission microscopy.
New Applications of Thermal Laser Signal Injection Microscopy (T-LSIM)
Authors: Falk R. Aaron , Bauersfeld Neil , LaPierre Mark , Elliott Shawn 
Published: December 2020

Abstract
Thermal laser signal injection microscopy (T-LSIM) (aka TIVA and OBIRCH) has shown considerable promise in stateof- the-art digital integrated circuits. The technique has been utilized to locate shorts, leakage currents, problem vias, and timing issues in these devices. However, little has been published on the utility of this technique for analog and mixed signal devices. In this paper we demonstrate the application of T-LSIM on two different analog devices with defects that conventional FA technology and fault isolation techniques were unable to locate. Analog devices produce several unique challenges to the basic T-LSIM technique as typically utilized in the digital regime. Extensions of the basic T-LSIM technique were utilized to locate the failures, which produced unexpected results. The T-LSIM technique has proved essential in the quick identification and localization of failure sites. The T-LSIM technique provides the failure analyst with the analytical power not previously available on conventional fault isolation tools such as emission microscopy and liquid crystal.
Solder Bump Defects in Ceramic Flip Chip Packages and Their Acoustic Signatures
Authors: Ramanujachar Kartik , Rusli Darwin , Agarwal Reena , Widaski James 
Published: December 2020

Abstract
Solder bumps are frequently the sites of defects that cause continuity failures in ceramic flip chip packages. In concurrent technology the solder bump is a multi-layered structure containing several interfaces. Conventional c-SAM imaging alone cannot delineate subtle bump defects. In this article we present experimental results that document the nature of interface defects in multi-layered solder bumps as well as their acoustic signatures. The acoustic signatures obtained from defective bumps are contrasted with the signals obtained from pristine bumps and the sensitive nature of these signatures to defects is highlighted.
Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis
Authors: Prejean Seth J. , Shannon Joseph 
Published: December 2020

Abstract
This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside deprocessing of bulk CMOS integrated circuits [1]. The focus of these improvements was to provide a repeatable and reliable methodology of deprocessing CMOS devices from the backside. We describe a repeatable and efficient technique to deprocess flip chip packaged devices and unpackaged die from the backside. While this technique has been demonstrated on SOI and bulk devices, this paper will focus on the latest SOI technology. The technique is useful for quick and easy access to the transistor level while preserving the metal interconnects for further analysis. It is also useful for deprocessing already thinned or polished die without removing them from the package. Removing a thin die from a package is very difficult and could potentially damage the device. This is especially beneficial when performing physical failure analysis of samples that have been back thinned for the purpose of fault isolation and defect localization techniques such as: LIVA (Laser Induced Voltage Alteration), TIVA (Thermally Induce Voltage Alteration), SDL [2] (Soft Defect Localization), and TRE (Time Resolved Emission) analysis. An important fundamental advantage of deprocessing SOI devices is that the BOX (Buried Oxide) layer acts as a chemical etch stop when etching the backside or bulk silicon. This leaves the transistor active silicon intact for analysis. Further delayering allows for the inspection of the active silicon, gate oxide, silicide, spacers, and poly. After deprocessing the transistor level, the metal layers are still intact and, in most cases, still electrically connected to the outside world. This can provide additional failure analysis opportunities.
A Novel Approach to Front-Side Deprocessing for Thinned Die after Backside Failure Isolation
Authors: Nguyen Dat , Phan Cuong , Conner Jeff , Smith Martin , Drummond John 
Published: December 2020

Abstract
This paper describes a novel approach for safe handling of the thinned die from the front; a technique that can also be successfully applied to preserve cracked die. The discussion provides details on the characteristics and processes involved in backside reconstruction, thinned die reconstruction, and front-side deprocessing of thinned die. The finished backside reconstruction sample was cross-sectioned for examination using a diamond saw. After 6 hours of bake, no cracking of the thinned die was observed. Front-side deprocessing was then applied to the backside reconstructed sample. The sample remains intact. The technique has proven to be easily applied and highly reliable, and provides a solution for front-side deprocessing for both high pin count ball grid arrays and flip chips.
A Method for Exact Determination of DRAM Deep Trench Surface Area
Authors: Russell Jeremy D. , Tseng Yuan-Wei 
Published: December 2020

Abstract
A technique is described which allows the precise measurement of the surface area of the dielectric layer of a DRAM deep trench (DT) capacitor. It uses precision FIB sectioning, and allows determination with arbitrary accuracy. It can be used for measuring random DTs in a region of interest for process monitoring, and can also be used for a single target trench in the case of failure analysis.
A Review of TEM Observations of Failures of the Memory Cell in a Deep Trench Capacitor DRAM
Authors: Lue Jen-Lang , Lee Jack , Chen Esther , Luo Jian-Shing 
Published: December 2020

Abstract
Application of the high resolution of Transmission Electron Microscopy (HRTEM) plays a very important role in structural analysis and materials characterization for process evaluation and failure analysis in the Integrated Circuit (IC) industry. We summarize TEM observation experience of the common memory failures of a BEST deep trench cell with an N-MOS gate used in CMOS DRAM technology. Memory cell failures are categorized into three areas for discussion – the deep trench (DT) capacitor, the transfer gate (GC), and the borderless bit-line contact (CB) between a transistor and a bit line. Typical examples that occurred in these three areas are presented and provide a basic understanding of normal DRAM cell failures.
The Effect of TEM Specimen Preparation Method on Ultra-Thin Gate Dielectric Analysis
Authors: Du A. Y. , Tung C. H. , Freitag B. H. , Zhang W. Y. , Lim S. , Ang E. H. , Ng Danny 
Published: December 2020

Abstract
The three typical TEM specimen preparation methods are investigated for two different ultra-thin gate dielectric materials analysis. The results show that the mechanical polishing with short time, low angle ion milling is best specimen preparation method for both samples. FIB finial thinning can be used for SiON gate dielectric specimen analysis, but is not suitable for HfO2 gate dielectric analysis. After FIB thinning, severe Ga and Pt contamination on the specimen surface is found when using HR-STEM/HAADF imaging.
Forward Scattered Scanning Electron Microscopy for Semiconductor Metrology and Failure Analysis
Authors: Vanderlinde William E. 
Published: December 2020

Abstract
Continuing decreases in electron device feature size have strained the resolution limits of scanning electron microscopy (SEM). In this paper a simple method is demonstrated for producing significantly improved resolution in SEM imaging without making any special sample preparation or modifications to the SEM. This method images with the lowloss forward scattered electron signal by using a modified sample holder. The method was found to be particularly useful for observing low atomic number materials such as photoresist and molecular semiconductors in their natural state, i.e. without sputter coating.
Contributions of a Formal Analysis Metaprocess to Breakthrough Failure Analysis Results
Authors: Ferrier Steve , Martin Kevin D. , Schulte Donald 
Published: December 2020

Abstract
Application of a formal Failure Analysis metaprocess to a stubborn yield loss problem provided a framework that ultimately facilitated a solution. Absence of results from conventional failure analysis techniques such as PEM (Photon Emission Microscopy) and liquid crystal microthermography frustrated early attempts to analyze this low-level supply leakage failure mode. Subsequently, a reorganized analysis team attacked the problem using a specific toplevel metaprocess.(1,a) Using the metaprocess, analysts generated a specific unique step-by-step analysis process in real time. Along the way, this approach encouraged the creative identification of secondary failure effects that provided repeated breakthroughs in the analysis flow. Analysis proceeded steadily toward the failure cause in spite of its character as a three-way interaction among factors in the IC design, mask generation, and wafer manufacturing processes. The metaprocess also provided the formal structure that, at the conclusion of the analysis, permitted a one-sheet summary of the failure's cause-effect relationships and the analysis flow leading to discovery of the anomaly. As with every application of this metaprocess, the resulting analysis flow simply represented an effective version of good failure analysis. The formal and flexible codification of the analysis decision-making process, however, provided several specific benefits, not least of which was the ability to proceed with high confidence that the problem could and would be solved. This paper describes the application of the metaprocess, and also the key measurements and causeeffect relationships in the analysis.
Novel Application of Transmission Electron Microscopy and Scanning Capacitance Microscopy for Defect Root Cause Identification and Yield Enhancement
Authors: Tangyunyong P. , Hill T. A. , Nakakura C. Y. , Soden J. M. , Cole E. I. , Flores R. S. , Shaneyfelt M. R. , Dockerty R. C. , Headley T. J. , Rye M. J. 
Published: December 2020

Abstract
Transmission electron microscopy (TEM) [1] and scanning capacitance microscopy (SCM) [2] have become common failure analysis tools at Sandia for new product development, process validation, and yield enhancement. These two techniques provide information that cannot be obtained with other analytical techniques. The information provided by these two techniques has been instrumental in identifying the root causes of several yield-limiting defects in CMOS IC technologies at Sandia. This paper describes an example of how TEM and SCM have been used to identify the root causes of SOI device failures. The corrective actions taken to reduce defects and improve yield are also described.
Contact Failure Due to Particulate Defect in a 0.13 µm CMOS Process
Authors: Bagchi Sandeep , Arunachalam Valli , Saenz Javier , Beck James , Duncan Lupe , Conner Jim 
Published: December 2020

Abstract
Random single bit failures were encountered in cache areas of Motorola’s 0.13 µm CMOS products under development. Extensive in-line probe data and end-of-line probe data in conjunction with failure analysis indicated the presence of particles at the upper surface of tungsten contacts. This paper describes how TEM based techniques were used to analyze the origin of the defect which in turn enabled process optimization and yield improvement.
ESD: Correlation between Electrical Signature and Failure Modes
Authors: Korchnoy V. , Lisenker B. , Posimeinik I. 
Published: December 2020

Abstract
The correlation between electrical characteristics and failure modes in some common cases of ESD protection circuitry is described. The investigation is based on experimental results obtained during the qualification of highly integrated CPUs and chipsets manufactured by 0.18 µm CMOS technology. The implementation of these data during qualification of 0.13 µm CMOS products allowed the decrease of qualification throughput time (TPT), and, in some cases, reduction of FA efforts. Some process related and designs related ESD concerns are discussed herein.
Recent Developments in Automated Sample Preparation for FESEM
Authors: Cerchiara R. R. , Fischione P. E. , Gronksy J. J. , Hein W. F. , Martin D. D. , Matesa J. M. , Robins A. C. , Smith D. W. 
Published: December 2020

Abstract
Standard analytical practice in the semiconductor industry depends on fast, efficient and reliable sample preparation prior to FESEM. “In lens” imaging technology and orientation mapping (EBSD) demand sample surfaces free of physical damage and residual contamination. An integrated preparation tool has been developed that incorporates the functionality necessary for argon – oxygen plasma cleaning, ion beam etching (IBE), reactive ion beam etching (RIBE), reactive ion etching (RIE), and ion beam sputter coating (IBSC). Control, monitoring and sequential automation of the processes is accomplished through a novel combination of software and hardware. FESEM results for Al and Cu based microelectronic materials will be discussed, as well as EBSD results for bulk metals. Improvements in throughput and subsequent materials characterization will be demonstrated.
Improvements of Secondary Electron Imaging and Endpoint Detection in Focused Ion Beam Circuit Modification
Authors: Ray Valery , Antoniou Nicholas , Krechmer Alex , Saxonis Andrew 
Published: December 2020

Abstract
Secondary electron signal is widely used in Focused Ion Beam (FIB) systems for imaging and endpointing. In the application of integrated circuit modification, technology has progressed towards smaller dimensions and higher aspect ratios. Therefore, FIB based circuit modification processes require the use of primary ion beam currents below 10 pA and Gas Assisted Etching (GAE). At low beam currents, short pixel dwell times and high aspect ratios, the level of available secondary electrons for detection has declined significantly. FIB GAE and deposition requires delivery and release of a gaseous agent near the beam scanning area, and involves insertion of a gas delivery nozzle made of conductive material and grounded for charge prevention purposes. The proximity of a grounded gas delivery nozzle to the area being milled and/or imaged creates a “shielding” effect, further lowering secondary electron signal level. The application of a small positive bias to the gas delivery nozzle provides an effective way of reducing the “shielding” effect. Depending on the geometrical arrangement of the gas delivery system and other conductive objects in the chamber, an optimized nozzle bias potential can create conditions favorable for enhanced extraction and collection of secondary electrons. The level of the secondary electron image signal, collected in an FEI Vectra 986+ system, from a grounded copper sample with the nozzle extended and biased can be enhanced as much as six times as compared to the grounded nozzle. Secondary electron intensity endpoint is improved on backside samples, however shielding of the nozzle field by the bulk silicon substrate limits the electron extraction effect from within a via. For front side edits the improvement of endpoint signal level can be dramatic. Lateral image offset induced by the electrostatic field of a biased nozzle, can be removed by software position compensation.
Fault Localization of a Scan Shift Problem on Integrated Logic Designs
Authors: Burmer C. , Egger P. , Huber A. , Cerva H. , Petit D. , Grellner F. 
Published: December 2020

Abstract
Effort and complexity for failure analysis are increasing on state of the art logic designs. As chips become more and more complex, functional tests are not possible anymore [1] and are replaced with automatic test pattern generation (ATPG) using a full scan design approach. Analysis of failing devices, however, becomes more complex as scan chains contain a large number of flip flops and localization of the failing net is a prerequisite for subsequent physical failure analysis (PFA). This becomes especially true for flip chip products, since access to the chip front side is not easily possible any more. This report describes the necessary failure analysis steps in order to identify the root cause of scan shift problems associated with two products fabricated in deep sub-micron technology
Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy
Authors: Lee Jon C. , Chuang J. H. 
Published: December 2020

Abstract
As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.