bluuebunny/crossref_metadata_2025_split huggingface dataset:
Voltage Regulator Output Shifts Due to Systematic Oxide Non-Uniformities: Failure Analysis, Layout and Process Solutions
Authors: Jumpertz R. , Muigg D. , Oberhuber R. , Ploss W. , Chatterjee T. , Trogolo J. 
Published: December 2020

Abstract
High volume productions of analog devices require usually more than one production facility. These facilities could be part of the company or in a foundry organization. A smart technology transfer is a key requirement to success. Nevertheless, small deviations of parametric key indices can lead to substantial differences in analog device performance. This paper describes an instructive case study to isolate the root cause of a parametric shift of a low drop output (LDO) voltage regulator. This shift caused a significant yield loss in one of the production facilities. The LDO shift was traced back to a current mirror mismatch. Physical failure analysis shows small differences in the gate oxide thickness which consequently vise versa led to threshold voltage mismatch. Further process analysis identified an unwanted topography in the silicon surface as the root cause of the non-uniform gate oxide growth.
Observations of Crystal Damage on the Sidewalls of TEM Samples Prepared by FIB Milling
Authors: Gao Qiang , Zhang Mark , Niou Chorng , Li Ming , Kary Chien W.T. 
Published: December 2020

Abstract
In this paper, crystal damage on TEM sample sidewalls induced by FIB milling during sample preparation was studied. A novel method was invented to prepare the sample, which facilitates the direct observation of amorphous layers on the sidewall. The ion beam acceleration voltage is the dominant factor that affects the damaged layer thickness. The measured amorphous thickness is about 23 nanometers at 30Kv and 10 nanometers at 10Kv. The damage layer thickness is constant with different beam currents over the range from 30pA to 1000pA. Amorphous layer thickness also stays constant with the sample tilt angle.
Electrostatic Discharge (ESD) Damage Simulation on RF MMIC Device
Authors: Chhong Tan Ewe 
Published: December 2020

Abstract
This paper presents electrostatic discharge (ESD) damage simulation results on good units of the RF monolithic microwave integrated circuit device. Two ESD test models, human body model and machine model, simulators were used to simulate the ESD damage on the good units of the RF MMIC devices in different pin configurations. The paper presents the failure analysis results on the field returned units, the ESD damage simulation results, and the failure analysis results on radio frequency operating life failure units. Based on the simulation results obtained, it was concluded that the ESD wounded devices would exhibit a short failure (catastrophic failure) and a low Id failure (latent failure) after being used in the application or field. It is recommended that the static electricity should be eliminated in the workplace at customer site by grounding the operators, equipment and devices in order to prevent the ESD damage.
Near-field Scanning Microwave Probe for Rapid Detection of Nonvisual and Parametric Defects in Cu/low-k Interconnect on Production Wafers
Authors: Talanov Vladimir V. , Schwartz Andrew R. 
Published: December 2020

Abstract
We demonstrate the use of a near-field scanned microwave probe (NSMP) for failure analysis (FA) of parametric defects in Cu/low-k interconnect that leave no physical remnant (sometimes referred to as “non-visual defects”). This technique is rapid, quantitative, non-contact, and provides direct electrical measurements.
Identification of Root Cause Failure in Silicon on Insulator Body Contacted nFETs Using Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy
Authors: McMurray J.S. , Molella C.M. 
Published: December 2020

Abstract
Root cause for failure of 90 nm body contacted nFETs was identified using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). The failure mechanism was identified using both cross sectional imaging and imaging of the active silicon - buried oxide (BOX) interface in plan view. This is the first report of back-side plan view SCM and SSRM data for SOI devices. This unique plan view shows the root cause for the failure is an under doped link up region between the body contacts and the active channel of the device.
Microstructure Analysis of Wafer Bump Nodule
Authors: Chen Xianfeng , Ge Tingfeng , Tsou Lisa , Li Ming , Niou Chorng , Kary Chien W.T. 
Published: December 2020

Abstract
The bump nodule growing in electroplating process could be large enough to induce bump to bump short even if the nodule would be weaken by re-flow process. In this work, the microstructure of PbSn eutectic bump and Au bump nodules was analyzed with FIB, SEM and EDS. In PbSn eutectic bump nodule, void defects can be observed with FIB imaging. In Au bump nodule, radiation-like grain structure around the center of Silicon-contained particle can be observed. Based on those analysis results, voids and particles are the source of bump nodule growth. The reason for bump nodule formation is that particles, voids and cathode morphology defects change the roughness of cathode surface, which induces a higher current density area and accelerate local electrocrystallization. Generally, particles, voids and cathode morphology defects are caused by poor photolithography process, tank corrosion and anode contamination such as passivation membrane. Therefore, three conclusions are proposed in this work: 1) where and when the nodules grow can be identified according to their microstructures; 2) cleaning tank and anode periodically can effectively prevent the bump nodules; 3) Qualified photo resist (PR) coating and PR opening process are essential to prevent bump nodule defects.
Root Cause Finding of a Diode Leakage Failure Using Scanning Magnetic Microscopy and ToF-SIMS as Key Methods
Authors: Preu H. , Mack W. , Kilger T. , Seidl B. , Walter J. , Alpern P. , Kirchberger M. 
Published: December 2020

Abstract
One challenge in failure analysis of microelectronic devices is the localization and root cause finding of leakage currents in passives. In this case study we present a successful approach for failure analysis of a diode leakage failure. An analytical flow will be introduced, which contains standard techniques as well as SQUID (superconducting quantum interference device) scanning magnetic microscopy and ToFSIMS as key methods for localization and root cause identification. [1]
Case Studies in Atomic Force Probe Analysis
Authors: Mulder Randal , Subramanian Sam , Chrastecky Tony 
Published: December 2020

Abstract
The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.
Applications of Transmission Electron Microscopy and Secondary Ion Mass Spectrometry on Crystal Defect Analysis and Electronic Characterization of Advanced 512Mb DRAM
Authors: Lu Serena , Chen Esther , Huang Lang-Yu , Luo Jian-Shing , Russell Jeremy D. 
Published: December 2020

Abstract
The capabilities of analytical transmission electron microscopy (TEM), such as high spatial resolution, micro-chemical analysis, etc., have led to an increasingly essential role for TEM-based analysis in process development, defect identification, yield enhancement, and root-cause failure analysis with the dynamic random access memory (DRAM) industry. In this article, several examples are reported to carry out the applications of TEM and secondary ion mass spectrometry on crystal defect analysis and electronic characteristics of advanced 512 Mb DRAMs.
Advanced Manual Package Pulling System for Removing PCB Components in Preparation for Crack Area Measurement and Disbond Type Mapping
Authors: McDonald Todd R. 
Published: December 2020

Abstract
Existing tools used by industry to manually remove PCB components for disbond type mapping or crack area measurement present significant ergonomic and process quality concerns. The most common tool designs often cause damage to some of the solder joints on components during pull, and frequently, operators using these designs report safety concerns. This paper evaluates these concerns and proposes a design solution that eliminates them. With a manual T-handle pull tool system introduced here, there is no prying, lever or angular force applied to remove the component. The pull tool rotates using vertical threads to apply vertical removal force. It demonstrates a reduction in manual operator force by an average of 93% compared to the cam lobe lever design. Additionally, the pull tool reduces bending of pull bolts and angular pull direction that may interfere with availability and interpretation of subsequent disbond data.
Failure Analysis Navigation System Connecting Hardware Analysis to Software Diagnosis
Authors: Shimase Akira , Uchikado Akihito , Matsumoto Yoshikazu , Watarai Shinichi , Kawanabe Shinji , Suzuki Takeshi , Majima Toshiyuki , Hotta Kazuhiro , Terada Hirotoshi 
Published: December 2020

Abstract
In the failure analysis of semiconductors, layout analysis to pick up suspect nets is getting to be a time consuming work due to finer wiring pitch and multi-layer structure. This article proposes a failure analysis navigation system (FA-Navigation System), which can make it easier to extract the nets passing through the signals detected by the hardware analysis tool, such as emission microscopes or OBIRCH analysis tools. It introduces the functions of the system and shows some case studies in actual failure analyses. The IDDQ fault diagnosis is especially useful for case studies. The result of the software diagnosis can be loaded in the analysis window of the FA-navigation system, and the system correlates the result to the nets extracted by the hardware analysis and displays coincident nets in a sorted manner to make the failure analysis easier.
Usage of SAM on Fatigue Crack of Solder Joint Induced by Thermal Reliability Test
Authors: Chen Tung Hung , Shih T. I. 
Published: December 2020

Abstract
Thermal fatigue cracking of lead-free solder joints within flipchip packages was investigated in this study by using scanning acoustic microscope (SAM) and SEM. The distribution of substrate delaminations was mapped with SAM of high depth resolution and observed in cross-section with SEM to find the mechanism of crack growth during thermal reliability tests. The study revealed that the interfacial crack always initiated from the pad edge. This is attributed to the coefficient of thermal expansion (CTE) mismatch between underfill and the PCB substrate. The propagation of fatigue crack within solder joint is closely related to the morphology of interfacial/intergranular intermetallic compound (IMC) formed at the elevated temperature of thermal cycle.
Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor
Authors: Talacka Ray , Tendolkar Nandu , Paquette Cynthia 
Published: December 2020

Abstract
The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.
Buttons and Threads—Tailoring Defect Analysis
Authors: Gondran Carolyn F. H. , Paul Dennis F. , Das Sanjit K. , Foran Brendan J. , Clark Mark H. 
Published: December 2020

Abstract
A framework is presented for considering the relative strengths of Auger electron spectroscopy (AES)/scanning Auger microscopy (SAM) and scanning transmission electron microscopy–electron energy loss spectroscopy (STEM-EELS) when selecting a defect analysis technique. The geometry of the analysis volumes for each technique is visualized. The analysis volume for AES/SAM is shaped like a button while the STEM-EELS analysis volume is more like a thread extending throughout the thickness of the prepared sample. The usefulness of this framework is illustrated with the example of small defect particles. In this example the size and shape of the AES/SAM analysis volume is a better fit to the defect, thus it provides better chemical analysis while STEM provides better images of the defects.
Reduction of Acquisition Time for RIL, SDL, and LADA
Authors: Mels Arjan , Zachariasse Frank 
Published: December 2020

Abstract
Although RIL, SDL and LADA are slightly different, the main operating principle is the same and the theory for defect localization presented in this paper is applicable to all three methods. Throughout this paper the authors refer to LADA, as all experimental results in this paper were obtained with a 1064nm laser on defect free circuits. This paper first defines mathematically what 'signal strength' actually means in LADA and then demonstrates a statistical model of the LADA situation that explains the optimal conditions for signal collection and the parameters involved. The model is tested against experimental data and is also used to optimise the acquisition time. Through this model, equations were derived for the acquisition time needed to discern a LADA response from the background noise. The model offers a quantitative tool to estimate the feasibility of a given LADA measurement and a guide to optimising the required experimental set-up.
Challenges of Atomic Force Probe Characterization of Logic Based Embedded DRAM for On-Processor Applications
Authors: Kane Terence , Tenney Michael P. , Erickson Andrew , Phan Sebastien 
Published: December 2020

Abstract
Nanoprobing logic based SOI embedded DRAM cells for on-processor designs poses different challenges than probing conventional six transistor SRAM designs. This paper will describe nanoprobing logic based embedded DRAM (eDRAM) cells in 65nm SOI applications. We will also describe probe placement and measurement methodology for electrical characterization of leakage between deep trench capacitors composing those eDRAM designs. The introduction of nano CV metrology and scanning capacitance imaging for use in characterizing DRAM capacitors will also be discussed.
Applications for Parallel Grinding as an Alternative to Chemical Decapsulation in Preparing Packaged Samples for Failure Analysis
Authors: Nail Carl 
Published: December 2020

Abstract
Acid etching of plastic packages can both remove key evidence and introduce artifacts on decapsulated samples. Parallel grinding offers a non-chemical option for removing package material that can minimize these risks. This technique was used successfully on three different types of failure analysis investigations. It also has potential for supporting the analysis of corrosion defects, though additional work is needed to confirm the utility of parallel grinding in this application.
Near-IR Photon Emission Spectroscopy on Strained and Unstrained 60 nm Silicon nMOSFETs
Authors: Tan S.L. , Toh K.H. , Isakov D. , Chan D.S.H. , Phang J.C.H. , Ang K.W. , Yeo Y.C. , Chua C.M. , Koh L.S. 
Published: December 2020

Abstract
Spectral analysis of near IR photon emissions was performed on unstrained as well as uniaxial tensile strained nMOSFETs with physical gate length of 60 nm. The significant differences in the observed spectra could be attributed to the strain-induced bandgap narrowing. This shows that photon emission spectroscopy could potentially be used as a tool to monitor strain in the nMOSFET channel.
Al Pad Corrosion Mechanism Study When Dicing Saw
Authors: Duan Shuqing , Li Ming , Yu Qinqin , Su Jie , Lin Sanpen , Niou Chorng , Chien W.T.Kary 
Published: December 2020

Abstract
The corrosion phenomenon was found at the edge area of bond pad under OM images after dicing saw. Experiment showed that the corrosion was related with the feed speed of dicing saw. From SEM and OM results, there were some abnormal contaminations around the corrosive area. Auger and TEM with EDX system were used to characterize the corrosive region and the related Al pad corrosion mechanism was discussed. In this paper, Cu rich and O rich layers were identified by TEM and EDX, which could be induced by galvanic cell reaction.
Study of FBGA Burn Failure under THB Test
Authors: Zhou Jianwei , Zheng Wei , Lou Minyi , Feng Nufeng , Lee Jaisung , Lee Taekoo 
Published: December 2020

Abstract
Temperature humidity bias (THB) test is widely used to evaluate the moisture resistance of non-hermetic packages in semiconductor industry. During THB test, one kind of 90FBGA was found severely burned and the evidence has been completely destroyed. This brings a great challenge to failure analysis. In this paper, a double daisy chain structure substrate was designed to reproduce the short and burn failure. The substrate layout design, bias and high humidity environment were proved to be the three key factors inducing dendrite growth and burn failure. A “corner-missing” phenomenon inspected through nano-focus X-ray was reported and it could finally verify the theory of electrochemical migration. The countermeasure to prevent burn failure was proposed to the designers. The insulation property degradation due to THB test was evaluated.
A Simple Adapter for Soft Defect Localization Using OBIRCH
Authors: Kolasa Ted 
Published: December 2020

Abstract
Equipment manufacturers have developed peripherals for their tools that add soft defect localization (SDL) capability to existing optical beam tools, in many cases providing excellent results. However, these upgrades add significant cost to the tool. This paper presents the design considerations for a simple adapter that was developed in house to add SDL capability to optical beam induced resistance change (OBIRCH) tool, including resolution of some unexpected problems. This solution represents a simple, low cost method to add SDL testing capability to the OBIRCH tool and can also be used in conjunction with OBIC and XIVA tools with little or no modification. An early example of the SDL results provided by this adapter is also presented.
Construction of a 3-D Current Path Using Magnetic Current Imaging
Authors: Felt Frederick , Knauss Lee , Gilbertson Anders , Orozco Antonio 
Published: December 2020

Abstract
The need to miniaturize in the electronics industry is driving smaller form factors, and resulting in complex packaging innovations such as structures with multiple devices stacked inside a three dimensional package. These structures present a challenge for non-destructive fault isolation. Two such modules recently exhibited failures on the NASA Goddard Space Flight Center Solar Dynamic Observatory (SDO) during board-level testing. Each module consisted of eight vertically-stacked mini-boards, each mini-board with a single EEPROM microcircuit and capacitor, and connected by external gold metallization to module pins. Both failed modules exhibited low-resistance shorts between multiple pins. The orthogonal structure of the module prompted the use of magnetic current imaging (MCI) in three planes in order to construct an internal three-dimensional current path for each of the failed modules. Magnetic current imaging is able to “look through” non-magnetic, or de-gaussed packaging materials, allowing global imaging without physical deprocessing of the stacked EEPROM modules, in order to construct the internal current path and localize defects. To our knowledge, this is the first time that this has been done. Following global isolation of the defects, two types of magnetic sensors were used in parallel with limited deprocessing in order to more precisely characterize suspect failure locations before actually physically exposing the defects. This paper will show the process for using magnetic current imaging with both SQUID and magnetoresistive (GMR) sensors to isolate defects in two stacked EEPROM packages along with the final physical analysis of the defects. The failure analysis found that these devices were damaged by external heat, possibly during oven pre-conditioning or hot air soldering onto the board. The manufacturer, 3-D Plus, was not implicated in the failure.
Analysis of DC Failure in Advanced Memory Devices Using Nanoprobing and Scanning Capacitance Microscopy
Authors: Lue Jen-Lang , Lin Chin-Shun , Chiou Atup , Liao Hsuen-Cheng , Liu Hsienwen , Pai Brian , Fan Sam , Wang Tings 
Published: December 2020

Abstract
This paper discusses the failure analysis process of a DC failure using an in-FIB (Focused Ion Beam) nanoprobing technique with four probes and a scanning capacitance microscope (SCM) in advanced DRAM devices. Current-Voltage (I-V) curves measured by the nanoprobing technique indicate the curve of the failed device is different from that of the normal device. The failed device causes a high leakage current in the test. The cross-sectional 2-D doping profile of SCM verifies the region of the P-Well has shifted to create a leakage path that causes this failure.
Localized Die Metallization Damage Induced During Laser-Marking of a Semiconductor Package
Authors: Parañal Paul Eric B. 
Published: December 2020

Abstract
This paper presents a new fail mechanism for laser-marking induced die damage. Discovered during package qualification, silica spheres – commonly used as fillers in the molding material, was shown to act as a propagation medium that promote the direct interaction of the scribing laser beam and the die surface. Critical to the understanding of the fail mechanism is the deprocessing technique devised to allow layer by layer examination of the metallization and passivation layers in an encapsulated silicon die. The technique also made possible the inspection of the molding compound profile directly on top of the affected die area.
BGA Package Level Failures Due to Contamination
Authors: Roepsch Jodi 
Published: December 2020

Abstract
Two instances of BGA package level failures were identified during in-circuit electrical test. The electrical opens occurred as a result of contamination issues originating at the board supplier. Analytical techniques including optical inspection, SEM/EDS, Raman and FTIR were key in identifying photoresist on the board surface in the first case study and nickel carbonate contamination on the board surface in the second case study. In the first case study, resolution was achieved with a Plasma etch process. In the second case study, CCAs were cleaned with a wet chemical etch process formulated specifically to attack the nickel carbonate.
Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices
Authors: Versen Martin , Diaconescu Dorina , Touzel Jerome 
Published: December 2020

Abstract
The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.