(Invited) Si-Cap-Free Low-DIT SiGe Gate Stack for High-Performance pFETs
Authors: Arimura Hiroaki , Wostyn Kurt , Ragnarsson Lars-Åke , Conard Thierry , Chasin Adrian , Franco Jacopo , Mitard Jerome , Horiguchi Naoto 
Published: December 2020

As the continuous physical device scaling is facing increasing challenges in today’s CMOS technology, introduction of high mobility channel material has further increased its potential value as performance booster. Low-Ge-content SiGe is the leading candidate for p-channel devices, as it is process-compatible with state-of-the-art Si CMOS fabrication platform and requires no strain relaxed buffer layer. In order to benefit from the high intrinsic carrier mobility at a low VDD operation, an efficient SiGe channel passivation with low interface state densities (Dit) needs to be developped. However, the presence of GeO is known to increase Dit [1]. One of the effective passivation schemes for SiGe-based channel surface uses an epitaxially-grown ultrathin Si cap [2]. It suppresses the formation of GeO and enables to fabricate a high-k/SiO2 gate stack equivalent to the one in Si devices. The outstanding improvement achieved with this approach was previously highlighted on pure Ge channel devices, where the formation of GeO is inevitable without the use of Si-cap [3]. On the other hand, it poses some concerns such as EOT penalty and process controllability, making the Si-cap-free route the desired option as long as the interface and oxide bulk trap densities can be kept under control. In this contribution, we will review our recent studies towards the realization of a low-Dit Si-cap-free SiGe gate stack [4].
Selective GeO scavenging from Si1-xGexOy interface layer was previously reported as the key process to reduce Dit of SiGe gate stack [1]. Wostyn et al., demonstrated on Si0.75Ge0.25 that the annealing of chemical oxide in inert ambient (i.e. H2) reduces GeO in Si1-xGexOy IL thanks to the conversion of the thermally-unstable GeO into SiO [5]. A MOS capacitor experiment confirmed a clear Dit reduction by H2 anneal, although at an increased EOT. Additional NH3 anneal on IL was found to further reduce the Dit down to 5×1011 cm-2eV-1 while cancelling out the H2-anneal-induced EOT increase (EOT=10.1 Å). We also found that the metal gate deposition process has a strong impact on Dit even for the same metal. While the PVD W/TiN led to low Dit and EOT, both of them increased as the PVD was changed to ALD (or ALD followed by CVD) process. This can be explained by the PVD-TiN-induced additional GeO scavenging from IL [6] and/or oxygen diffusion from ALD-based metal to IL through HfO2 inducing GeO formation. A nitridation of HfO2 was found to suppress the negative impact from ALD-based metal electrode. XPS confirmed that the significant Dit reduction coincides with the nitridation of HfO2. By replacing the HfO2 with other dielectrics in which lower oxygen diffusivity is expected such as SiO2, the Dit of SiGe gate stack became insensitive to the metal deposition process and nitridation, indicating that the high oxygen diffusivity of the HfO2 layer was, together with the GeO formation, the root cause of the process-sensitive Dit. These results emphasize the importance of the oxygen depth profile control for the realization of a low-Dit SiGe gate stack.
References:
[1] C. H. Lee et al., VLSI Tech. Dig., p. 36 (2016).
[2] S. Iyer et al., IEEE Electron Device Lett., vol. 12, p. 246, (1991).
[3] J. Franco et al., IEDM Tech. Dig., p. 397 (2013).
[4] H. Arimura et al., IEDM Tech. Dig., p. 677 (2019).
[5] K. Wostyn et al., ICSI/ISTDM, p. 71 (2019).
[6] L. Wu et al., VLSI-TSA Tech. Dig., p. 90 (2010).