Au / SiO2 Hybrid Bonding with 6-μm-Pitch Au Electrodes for 3D Structured Image Sensors
Authors: Honda Yuki , Hagiwara Kei , Goto Masahide , Watabe Toshihisa , Nanba Masakazu , Iguchi Yoshinori , Saraya Takuya , Kobayashi Masaharu , Toshiyoshi Hiroshi , Higurashi Eiji , Hiramoto Toshiro 
Published: February 2020

Pixel counts and frame rates of broadcasting TV cameras are increasing to meet the escalating demands for high quality pictures. The pixel count could be as high as 133 million [1] in the state-of-the-art CMOS video image sensor, and the frame rate could 120 fps [2], which will further keep increasing in coming years. Owing to large pixel count, the sensors are designed to share the signal processing circuits in a form such as column-parallel processing [2], and hence the conventional image sensors face difficulties in processing the signals at fast frame rate. In other words, the signal processing speed at each pixel is the bottleneck that limits the pixel count and the frame rate. To overcome this problem, we developed a 3D structured CMOS image sensor that can process signals pixel-wise in parallel as a means to increase the pixel count and the frame rate at same time, as shown in Fig. 1 [3]. The image sensor uses stacked signal processing circuits for each pixel by placing the circuits immediately below the photodiodes. Compared to conventional image sensors, the new structure enables us to maintain a higher frame rate even if the pixel count increases.
The pixel-pitch interconnection is one of a key technology to realize the 3D structured CMOS image sensors. We have previously developed an 8×8 pixel prototype 3D structured CMOS image sensor with Au interconnections in each pixel [3]. The sensor’s pixel pitch was 80 μm. To further enhance the resolution, we recently reduced the Au electrode dimension to 6-μm-pitch that could be electrically interconnected using a direct bonding technique. We also have developed a daisy-chain test device to examine the large number of interconnection.
The device was fabricated by the process described in Fig. 2 that consists of the following steps: (a) Al wiring layer was formed on a fully depleted silicon-on-insulator wafer. (b) Via holes were formed in the top intermediate SiO2 layer by dry etching. (c) Ti and Au seed layers were deposited by sputtering, and then the via holes were embedded with an electroplated Au layer. (d) Au/SiO2 bonding surface was formed by chemical mechanical polishing, and the wafer was diced into chips of 20-mm and 18-mm square each. Fig. 3 shows an atomic force microscopy (AFM) image of this chip surface. The height of the Au electrode above the SiO2 surface was approximately 18 nm. The average roughness (Ra) of the polished SiO2 and Au surfaces were less than 0.4 nm and approximately 1 nm, respectively. The diameter and the pitch of the Au electrode were 3 μm and 6 μm, respectively. (e) The bonding surface was activated sequentially by Ar and O2 plasmas. (f) Two chips were directly bonded at 2,000 N for 60 min at 200 °C. Fig. 4 shows the cross-sectional scanning electrode microscopy (SEM) image of the bonded electrodes. No voids were observed at the bonded interface. Fig. 5 shows the measured daisy-chain resistance. We confirmed that a series of electrical interconnections exceeded 230,000 contacts, and that the chain resistance was proportional to the number of electrodes. The Au contact resistance for one connection was approximately 23.6 mΩ, which is considerably smaller than that of the plug electrodes of LSI circuits.
To summarize, a daisy-chain test chip with 6-μm-pitch Au electrode interconnects was successfully fabricated using Au/SiO2 hybrid bonding. The result was promising to realize 3D structured CMOS image sensors for pixel-parallel signal processing.

[1] R. Funatsu et al., ISSCC Digest of Technical Papers, 6.2, pp. 112-113, 2015.
[2] K. Kitamura et al., IEEE Trans. Electron Devices, vol. 59, No. 12, pp. 3426-3433, 2012.
[3] M. Goto et al., IEEE Trans. Electron Devices, vol. 62, No. 11, pp. 3530-3535, 2015.

Figure 1