Development of Vertical Structured TFT Using Interfacial Oxidation
Authors: Choi SeYong , Hwang Byung Seol , Hwang Sang Hun , Hwang Sang Ho , Moon Seung Jae , Bae Byung Seong 
Published: December 2024

As advancements in display technology persist, ongoing research endeavors into Thin-Film Transistors (TFTs) to move forwards display evolution endure. Among the various semiconductors in TFT technologies, oxide TFTs have garnered considerable attention due to their manifold advantages, including heightened electron mobility in comparison to a-Si, superior transmittance, and suitability for medium to large-scale applications.
Recent developments in display engineering suggest that Augmented Reality (AR), Virtual Reality (VR), and flexible displays are the vanguards of next-generation displays. These rapidly expanding applications desire several specifications for TFTs, such as minimalized occupied area, high resolution, low-power operation, etc. Given the challenges associated with fulfilling these mentioned requirements using conventional TFT technologies is difficult due to the facing physical limitations. Therefore, a novel enhancement methodology becomes necessary. In response to this necessity, there has been a rapidly growing interest in Vertical TFTs (VTFTs), which represent a structural refinement of next-generation TFTs in recent years.
VTFT was propounded by Professor Y. Uchida of Japan in 1984 utilizing a-Si [1]. In the V-TFT structure, the source and drain electrodes are vertically separated by an insulator spacer. The annel lies between them, attached to the spacer's sidewall, directing carrier flow vertically. Therefore, VTFTs can easily achieve short channel lengths under 1µm, larger aspect ratios W/L, and higher packaging density, greatly reducing the occupied area over conventional TFTs. Nevertheless, the development of previously proposed VTFTs facing into unresolved challenges, including process complexity attributable to the requisite spacers and interlayer dielectrics (ILDs), as well as reduced yields due to the process complexity.
M. Chandra Sekhar et al., have postulated a methodology [2] employing the oxide layer formed at the interface as a leading layer during the deposition of metal and oxide, subsequently evaluating its reliability. This oxide film is termed Interfacial Oxidation.
As illustrated in Figure 1, our study introduces a novel VTFT processing methodology assured to improve process complexity and low yield rates, which represent inherent challenges in conventional VTFT fabrication.
Tantalum (Ta), characterized by low Gibbs's free energy, is harnessed as the gate electrode, while Indium Tin Oxide (ITO) serves as the source and drain electrodes. Concurrently, an interfacial oxide film occurs through the heat treatment-induced interfacial oxidation reaction between ITO and Ta, serving as an insulating film. This innovative VTFT processing protocol offers the following advantages: 1) Substituting the gate electrode prevents the necessity for conventional spacers and prevents the deposition of an interlayer insulating film, thereby simplifying the fabrication process considerably. 2) The insulating layer conforms to the contour of the gate electrode, obviating the deposition process for the insulating layer. This prevents defects that may emerge during additional insulating layer processing, mitigating electrode damage and averting diminished yields. 3) As a result, VTFT configuration offers an exceedingly short channel in the nm range, corresponding to the gate thickness, thereby producing a low power consumption—an outstanding advantage for driving applications.
Consequently, this research holds the potential to substantially contribute to the advancement of low-power electronic devices and the realization of next-generation display applications, encompassing form factor innovations, automotive integration, and AR/VR implementation, while simultaneously addressing the challenges posed by vertical TFT technology.

Figure 1