bluuebunny/crossref_metadata_2025_split huggingface dataset:
Development of PECS Application for Sample Preparation
Authors: Chen Xianfeng , Li Ming , Guo Qiang , Kary Chien W.T. 
Published: January 2021

Abstract
Cross-sectional polishing has been widely used in the semiconductor industry. As demand for higher throughput increases, the time spent manually performing a final polish is an improper method for cross-section preparation. Etching is the major function of Precise Etching and Coating System (PECS). In this article, the focus is on Ar plasma cleaning performance on a sample after rough polishing and a sample after a short time final polishing using PECS. To evaluate performance of Ar plasma cleaning, two samples were prepared for SEM observation. X-SEM images before and after Ar plasma cleaning revealed that Ar plasma cleaning is not an effective method to correct micro scratches. The combination of final polishing and stain into one step was found to improve sample quality and throughput. PECS Ar plasma was found to be an effective sample cleaning method when compared to the time spent on final polishing.
Automated Sample Preparation of Packaged Microelectronics for FESEM
Authors: Cerchiara R. R. , Fischione P. E. , Boccabella M. F. , Robins A. C. 
Published: January 2021

Abstract
A packaged device based on a ball grid array or other design presents a challenge to the failure analyst. Accessing one of the metal levels from the topside requires decapsulation by either a wet, predominantly dry (RIE) or a completely dry (mechanical) treatment. To reveal the details of the gate including the gate oxide, new approaches to selective etch delineation by RIE are required. This article presents an automated sample preparation method for packaged microelectronic materials by combining plasma cleaning, ion beam etching, reactive ion etching and ion beam sputter coating. A single etch gas chemistry was effective in phase delineation by RIE. Future work to further delineate the gate oxides could support accurate metrology by means of FESEM rather than field emission transmission electron microscope.
Studies of Fluorine-Induced Corrosion and Defects on Microchip Al Bondpads and Elimination Solutions
Authors: Younan Hua , Rao Nistala Ramesh , Jennifer Teong 
Published: January 2021

Abstract
In this paper, a comprehensive study of Fluorine-induced Aluminum bondpad corrosion will be presented. Fluorine corrosion is detrimental to Al pad quality resulting in non-stick on pad (NSOP). In wafer fabrication, NSOP refers to lift-off of Au wire-bond from the surface of Al bondpad due to its poor adhesion to the contaminated pad surface. It will be shown that besides the well-known corrosion mechanism that causes NSOP, namely, via the formation of Al fluoride defect ([AlFx](x-3)-), it can also happen due to Al fluoride oxide defect, AlxOyFz. Unlike the Al fluoride defect, which has a unique “flower-like” shape, Al fluoride oxide defects exist in a variety of shapes: “Crystal-like”, “Oxide-like” and “Cloud-like”. The physical dimensions of these defects (including Al fluoride) can be dramatically different, varying all the way from micron to nanometer. In this paper, each of these morphological shapes and their respective failure mechanisms will be covered. Solutions to mitigate F-corrosion and ways to control/monitor contamination on Al pad surface in wafer fab will be presented.
Optimization of SEM Analytical Conditions for Low K and Ultra Low K Dielectric Materials
Authors: Binghai Liu , Zhiqiang Mo , Younan Hua , Jennifer Teong 
Published: January 2021

Abstract
Electron beam induced radiation damage presents great challenges for the electron microscopy analysis of low k and ultra low k dielectrics due to their beam sensitive nature. In order to minimize the radiation damage, it is necessary to understand the mechanisms behind the damage. This work presents detailed studies regarding the mechanisms behind the effects of probe currents, accelerating voltage and anticharging coating layers on the radiation damage to low/ultralow K dielectrics. The results indicate that the probe current shows a stronger dependence on the size of the condenser lens aperture than the accelerating voltage. Therefore, in terms of the probe current, the condenser lens aperture plays a decisive role in affecting the radiation damage process. In order to minimize the radiation damage, SEM imaging should be conducted with not only a low accelerating voltage but also a small condenser lens aperture to reduce probe current. Based on simulation results, the effects of a coating layer and accelerating voltage are related to the interaction volume and the penetration depth of the electron beam. Pt coating can act as not only an anti-charging layer, but also an effective barrier layer for reducing electron flux that interacts with the low/ultra-low dielectrics.
Using Cross-Triggering in Oscilloscope for Debugging Multiphase Converter Circuit of Personal Computer (PC) Motherboard
Authors: Nguyen Binh , Diaz Orlando 
Published: January 2021

Abstract
Analyzing a failure on multiphase converter circuit on PC motherboards presents significant challenges due to the high number of nodes and the timing relationship between them. Typically a standard 4-channel oscilloscope can not capture the necessary timing relationship to effectively analyze the whole circuit. This article presents a simple and low-cost solution that can effectively help the users overcome the challenges of debugging multiphase converter circuit of PC motherboards.
Doping Profile Measurements in a 65-nm Commercial Product Using Atom Probe Tomography
Authors: Klibanov Lev , James Dick , Isheim Dieter 
Published: January 2021

Abstract
Doping profile measurements in extremely small features like transistor gates or source/drain regions is a challenging task for the semiconductor industry. In our article, we successfully used an atom probe tomography (APT) tool to measure the doping concentration and profile of the dopant elements in a commercial 65 nm product. APT not only delivers doping concentrations but also gives the highest spatial resolution (sub-1 nm) three-dimensional compositional information of any microscopy technique.
Failure Analysis of Nitride-Trapping Memory Cell Failures
Authors: Chen Wen-Rong , Chen Yu-Ju , Chang I-Cheng , Chiang Hsin-Hsu , Kuo Li-Kuang , Yin Shaw , Lu Chih-Yuan 
Published: January 2021

Abstract
The 2-bit/cell nitride-trapping device (NROM/Nbit) is an important type of NVM (Non-Volatile Memory). The NROM/Nbit is a potential candidate for replacing FG-type NVM devices below the 45nm node. In this study, electrical and physical failure analyses (PFA) were used. The failure mechanisms and root causes of failure for the test vehicle, a 130nm NBit device, were determined. Because cell dimensions and spacing requirements for high-density memory are quite aggressive, these observations help to optimize process and improve yield.
Advanced Methodologies for Backside Circuit Edit
Authors: O’Donnell E. , Scott D. , Malik T. , Jain R. , Lundquist T. , Schlangen R. , Kerst U. , Boit C. 
Published: January 2021

Abstract
Editing inside an integrated circuit (IC) is critical to debug new devices. Current flipchip circuit edit techniques are limited by spot resolution and chemistry constraints of Focused Ion Beam (FIB) systems. The newly proposed technique for circuit edit (CE) employs FIB to contact circuit nodes directly on transistor level, offering a wide range of applications since it allows accessing every signal on a chip. The general functionality and the influence on chip performance are evaluated for an Intel 65nm process technology.
High Precision Ion Beam Milling with Time of Flight Compensation
Authors: Holtermann Theresa , Graupera Anthony , Rosenberg Steve , DiBattista Michael 
Published: January 2021

Abstract
Advanced semiconductor process technologies demand that patterns are milled precisely and without beam overshoot, which could damage adjacent transistors or expose neighboring interconnects. As mill box size becomes small enough and contains fewer pixels, the probability of the beam landing accurately at any given pixel for the prescribed pixel time becomes low. This has forced operators to employ higher than desired pixel times in order to preserve pattern acuity at the expense of optimized gas enhancement. In this article, the authors demonstrate the ability to machine and fill 50nm vias in advanced semiconductor process technologies. This capability is enabled directly by time of flight (ToF) operations. ToF compensation provides a significant advantage for patterning accuracy in advanced circuit edit applications. It enables FIB operators to use drastically shorter dwell times and pixel rates to enhance gas milling and deposition activities.
Applications of In-situ Sample Preparation and Modeling of SEM-STEM Imaging
Authors: Young R.J. , Buxbaum A. , Peterson B. , Schampers R. 
Published: January 2021

Abstract
Scanning transmission electron microscopy with scanning electron microscopes (SEM-STEM) has become increasing used in both SEM and dual-beam focused ion beam (FIB)-SEM systems. This paper describes modeling undertaken to simulate the contrast seen in such images. Such modeling provides the ability to help understand and optimize imaging conditions and also support improved sample preparation techniques.
Sample Preparation Technique for Bond Pad IMD (Inter-Metal Dielectric) Damage Observation
Authors: Huan Y. S. , Kuo Y. L. , Lin Y.T. , Chen Jeff , Lee K.Y. 
Published: January 2021

Abstract
Wire bonding is the most highly used interconnection technology in the packaging of integrated circuits. One of the potential risks of wire bonding is the damage on the oxide layers underneath the bond pad. Oxide damage monitoring is necessary to ensure bonding has no impact on the oxide layers under the bond pad. Since the oxide layer is not seen by visual inspection, bond pad stripping is necessary. Three bond pad stripping chemicals KOH, Aqua regia, and phosphoric acid were investigated in this study. Results obtained by dipping the chemicals at different temperatures, and time scales will be given. An optical microscope (OM) and scanning electron microscope (SEM) are used to observe the oxide conditions from the top view. To understand the mechanism of the oxide damage caused by wire bonding, a focused ion beam was used to observe the cross-section of the defect.
Latent Flash Single Bit and Multiple Bits Systematic Approach to Failure Analysis
Authors: To Hoang-Yen , Nguyen Dat , Dunn Clyde , Davis Detric 
Published: January 2021

Abstract
The flash considered for failure analysis in this paper is a non volatile memory with a NOR architecture in the array and a stacked gate for the bit cell. The flash failure was from data gain reported from various stages and at different temperatures after leaving the wafer fabrication. The failure can be single bit failure (SBF) or multiple bit failure (MBF). The FA process is comprised of two steps termed electrical failure analysis (EFA) and physical failure analysis (PFA). This paper discusses the method to differentiate failure modes and the efforts of fault isolation. Micro probing and nano probe characterization were important in the understanding of the failure mechanism. As seen in the EFA/PFA section, the reported SBF/MBF failures were actually due to a defect in the Mux and not at the bit cell.
Laser Failure Isolation Techniques Demonstrated On Test Structures
Authors: Arnold Frank S. 
Published: January 2021

Abstract
To be better prepared to use laser based failure isolation techniques on field failures of complex integrated circuits, simple test structures without any failures can be used to study Optical Beam Induced Resistance Change (OBIRCH) results. In this article, four case studies are presented on the following test structures: metal strap, contact string, VIA string, and comb test structure. Several experiments were done to investigate why an OBIRCH image was seen in certain areas of a VIA string and not in others. One experiment showed the OBRICH variation was not related to the cooling and heating effects of the topology, or laser beam focusing. A 4 point probe resistance measurement and cross-sectional views correlated with the OBIRCH results and proved OBIRCH was able to detect a variation in VIA fabrication.
Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages
Authors: Schwindenhammer P. , Murray H. , Descamps P. , Poirier P. 
Published: January 2021

Abstract
Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.
Improving Fault Isolation Using Iterative Diagnosis
Authors: Gearhardt Kevin , Schuermyer Chris , Guo Ruifeng 
Published: January 2021

Abstract
This paper presents an iterative diagnosis test generation framework to improve logic fault diagnosis resolution. Industrial examples are presented in this paper on how additional targeted pattern generation can be used to improve defect localization before physical failure analysis of a die. This enables failure analysts to be more effective by reducing the dependence on the more expensive physical fault isolation techniques.
Evaluating PICA Capability for Future Low Voltage SOI Chips
Authors: Stellari Franco , Song Peilin , Vickers Jim , Shaw Chris , Kasapi Steven , Ispasoiu Radu 
Published: January 2021

Abstract
In this paper we evaluate the possibility of extending Time Resolved Emission (TRE) technology towards future low voltage SOI technologies. In particular, we investigate and quantify the gain offered by the InGaAs detector improvements devised by Credence Corp., now DCG Systems, the manufacturer of the Emiscope III PICA system used in this analysis. Experiments on a test chip fabricated in the IBM SOI 65 nm technology will demonstrate that the improved tool guarantees the same Signal-to-Noise Ratio (SNR) even at ~90 mV lower supply voltages. In the second part of the paper we also discuss various other acquisition optimizations of the system. Although the analysis presented here refers to a specific tool, the large majority of the results and discussions can easily be generalized and applied to other PICA systems and detectors, as well as low voltage bulk silicon technologies.
An Application of a Nanoprobe Technique in the Characterization of Advanced SRAM Devices
Authors: Lin Hung-Sung , Chen Chun-Ming 
Published: January 2021

Abstract
The importance of understanding mismatched behavior in SRAM devices has increased as the technology node has shrunk below 100nm. Using the nanoprobe technique [1-3], the MOS characteristics of failure bits in actual SRAM cells have been directly measured. After transistors that are failing were identified, the best approach for identifying nanoscale defects was determined. In this study, several types of nanoscale defects, such as offset spacer residue, salicide missing from the active area, doping missing from the channel, gate oxide defects, contact barrier layer residue, and severed poly-gate silicide were successfully discovered.
Oxidation of TiN ARC Layer as a Reliability Issue for ICs
Authors: McVeigh Martin , Raz Avi , Kindt Willem J. , Gomes Alfred , Wong Kar Yee , Inamine Tricia , Bold Thomas J. 
Published: January 2021

Abstract
During moisture-and-bias reliability stress tests of THBT (temperature and humidity biased test) and HAST (highly accelerated stress test) extensive electrochemical oxidation of a TiN ARC layer is seen to occur. This oxidation proceeds at the nominal temperatures and humidity levels associated with such THBT and HAST tests; excessive heating due to EOS (electrical overstress) or other anomalous electrical conditions was not involved. The oxidation rate increases with applied voltage. Metal line width also affects the spread of oxidation. Oxidation requires the presence of adequate humidity to act as an electrolyte, and therefore is seen to propagate wherever moisture penetration can occur in the passivation dielectrics. The presence of a silicone gel die coating is found to render the die more susceptible to TiN oxidation. Electrical failures – typically open circuits or increased resistance due to corrosion – are found to occur as a consequence of this oxidation and its effect on the surrounding structures. This mechanism is a concern for integrated circuits with TiN in the upper metal layers, operating at voltages &gt;5V in humid conditions. Two approaches at reducing this electrochemical reaction are offered.
Timing Problems Due to Spacer Bridging in a Sub-100 nm Product
Authors: van Hassel Jan 
Published: January 2021

Abstract
In this paper, a comprehensive study to find a memory related yield loss in 90 nm technology will be discussed. The loss was related to spacer bridging, blocking silicide formation and Lightly Doped Drain (LDD), source/drain implant. Soft Defect Localization (SDL) techniques [1], sub-micron Atomic Force Microscope (AFM) probing [2] and Time Resolved Emission (TRE) measurements were necessary to obtain an accurate understanding of the problem and the mechanism. Electrical results were compared to simulations. Modified test structures were implemented to monitor the process stability with respect to bridging failures.
A Study to Remove Heavy Polymer Remain on Thick Metal (&gt; 3 micron) Sidewall Profile after Metal Etch Solvent Clean Step
Authors: Liew S. F. , Mohammad K. A. , Liu L. J. , Chong S.F. , Lee D. G. , Lee S.F. , Lee B.C. 
Published: January 2021

Abstract
Heavy polymer residue has been observed on the sidewall of thick metal during the process release. The thickness of metal line is more than 3 micron. This thick polymer residue on the aluminum metal sidewall is seen from tilt Scanning Electron Microscope (SEM) profile analysis. This polymer residue on the metal sidewall with chlorine (Cl2) trapped will result in metal corrosion. The focus on this paper is on the removal of this polymer residue on the thick metal sidewall. The experiments were run with splits of varying the chemical dispensing time and the rinsing time in the process. The success criteria are determined by passing the Defect Source Analysis (DSA) and tilt SEM profile analysis. These wafers are sent for electrical test, wet box test (corrosion test) and electrical sort test to ensure the reliability of the post metal cleaning condition.
Yield Enhancement Using a Combination of Wafer Level Failure Analysis and Defect Isolation Software: Case Studies
Authors: Simon Pierre , Thétiot Michel , Picart Bernard , Kardach Cathy , Deslandes Herve , Dudkiewicz Fabien , Roux Jean-Philippe 
Published: January 2021

Abstract
Yield enhancement has always been an important topic but even more when processes are moving towards smaller geometries. Today, latest FA flow intends to check wafer quality to monitor production in real-time. The purpose is to adjust any derivation coming from the process as fast as possible. The Atmel-CIMPACA laboratory located in Rousset, France, can do Failure Analysis on wafer, thanks to its wafer prober designed to work on DCG systems equipment and integrated CAD software (Meridian, Emiscope, NEXS software suite). Wafer level yield analysis typically requires long setup and multiple dies analysis. Each of the die can be studied with a set a failure analysis (FA) techniques (photo or thermal) emission microscopy [1], laser stimulation techniques [2] or even dynamic probing using time resolved emission [3],[4] or laser based techniques, for the most common ones [5].
A Procedure for Identifying the Failure Mechanism Responsible for a Pin-To-Pin Short Within Plastic Mold Compound Integrated Circuit Packages
Authors: Nail Carl , Rocha Jesus , Wong Lawrence 
Published: January 2021

Abstract
Packaging-based short circuits are inherently difficult to analyze due to the unprotected nature of the shorting material in the package. A combination of SQUID, low-power x-ray and OBIRCH techniques were used in conjunction with parallel grinding to identify the location of the short and reveal it for subsequent characterization. This procedure can reliably identify metal-based shorts in most plastic packaging material.
Mis-identified Failures in FETs
Authors: Gores Mark 
Published: January 2021

Abstract
Several recent failure analyses have found that what appeared to be typical source to drain over current damage, was actually caused by intermittently open circuited gate bonds. In power switching applications, such as inverters and switching power supplies, the timing of the transistor’s turn ons and turn offs can be critical. For example in an inverter if the transistor between the positive supply and phase A does not turn off before the transistor between the negative supply and phase A turns on there will be a short circuit between the positive and negative supplies resulting in a high current condition and the failure of both transistors. The original cause of the failure can be masked after the catastrophic failure of the die. The gate does not necessarily remain open circuited. It can reestablish continuity due to the short circuiting of the gate on the die, which causes arcing at the open bond. It is easy to overlook this mechanism in the normal FA process, since there is obvious and sometimes spectacular damage to the die and usually pressure to make a rapid determination of the root cause of failure. The gate wires are more likely to become open circuited because there is usually only 1 wire and it is sometimes a much smaller wire. The wires can become open circuited for a variety of reasons: Mechanical damage to the leads. Inadequate bonds at either end of the wire. Excessive intermetallic formation. Several case histories of open gate wires as well as other open bonds, how they were discovered, and possible screening methods will be discussed.
Intermittent Failures, Challenges and Strategies Involved with Finding Root Cause
Authors: Konkol Nicholas 
Published: January 2021

Abstract
It is often difficult to find the root cause of motherboards that exhibit intermittent failures. This is due to irregularity and inconsistency. When failures occur at irregular intervals or symptoms are inconsistent, it poses challenges to effectively discovering root cause. This article presents strategies that can be used to analyze motherboards that involve failure irregularity, symptom inconsistency, or both. It also discusses the challenges faced in the analyses.
3D STEM Tomography Based Failure Analysis of 45 nm CMOS Devices
Authors: Lorut Frederic , Delille Dominique 
Published: January 2021

Abstract
For a certain class of defects substantial time has to be invested to be able to pinpoint the exact electrical failure location and to perform an accurate and conclusive physical characterization. This article shows that 3D scanning transmission electron microscopy (STEM) tomography in conjunction with an original sample preparation method is a valuable technique to tackle this class of defects and that it can provide very accurate and useful information on these defects. The developed method is applied to analyze several failing devices that are all designed with 45nm design rules and fabricated using a 45 nm technology, and is illustrated with 3 different case studies, each referring to one fault localization method. It is concluded that 3D STEM tomography can provide conclusive 3-dimensional analytical and morphological information on the localized defect, provided that special care is taken to prepare a well-adapted sample.