bluuebunny/crossref_metadata_2025_split huggingface dataset:
Laser Milling Techniques for Stacked Die Package Applications
Authors: Skoglund Lars , Dias Rajen 
Published: December 2020

Abstract
Ultraviolet (UV) lasers can be used as microsurgery tools to deprocess electronic packages to expose the device and internal package features. A UV laser milling tool was characterized for various applications on multiple die stacked packages to assist in fault isolation and failure analysis. Laser milling procedures evaluated were package delayering to expose traces, trace cutting so that fails can be isolated between the die and package, wire bond exposure and cutting, multiple stacked die exposure through mold compound decapsulation and device milling. Results show excellent selectivity of the laser in removing organic material without etching copper traces at multiple layers in the organic package. Mold compound removal above the die was limited to within ~15 microns of the die surface to prevent any die damage. Mold compound decapsulation outside the die area to expose multiple layers of wire bonds for probing and inspection was developed after overcoming issues related to wire damage. In conclusion, laser milling procedures developed and evaluated show that the technique has a unique advantage in performing local package microsurgery with minimal damage or change in the global stress state of the package.
A Correlation Study between XPS and AES Quantitative Analysis of Nitrogen Concentration in Gate Oxide
Authors: Wu LinFeng , Li Ming , Lee J.H. , Zhou Jecy , Niou Chorng , Kary Chien W.T. 
Published: December 2020

Abstract
Accurate characterization of the nitrogen concentration and distribution in ultra thin nitrided silicon gate oxide plays the same important role as the fabrication technology itself during the development of 90nm and beyond gate oxide manufacturing process. Based on the measurement results of XPS (X-ray photoelectron spectroscopy) as reference, a correlation study was taken between XPS and AES (Auger electron spectroscopy) data in this paper. The study shows that, by optimizing the experiment conditions of AES such as beam energy, beam current and take off angle, and introducing proper corrective factor, AES can be used as a useful and reliable characterization tool during the monitoring measurement of Nitrogen concentration in ultra thin (&lt;2nm) nitrided silicon gate oxide.
Fault Isolation for a Nanometer-Scale Poly Protrusion Causing Single Column Failure in SRAM Device
Authors: Radaelli Daniele , Wang Nathan N. , Nguyen Francis , Daniel Sabbas 
Published: December 2020

Abstract
A common failure mode such as a faulty single full column in an SRAM can be caused by a wide range of defect types at various locations. Fault isolation by thorough electrical analysis and circuit behavior understanding is needed to precisely pinpoint the defect minimizing the destructive physical analysis. This case study shows the process and the techniques used to identify a nanometer scale poly defect.
Electrical Characterization of the Access Transistor of Deep Trench Based DRAM Products via Backside Contacting
Authors: Lehner Werner , Pauthner Siegfried , Radeck Herbert , Weber Udo , Touzel Jérôme 
Published: December 2020

Abstract
Dynamic Random Access Memory (DRAM) is the one most widespread commodity product of the microelectronic industry. Although the basis structure is quite simple, an indepth electrical characterization of the single cell is mostly correlated with huge efforts in terms of test patterns due to the multiple possibilities for leakage of the cell itself [1]. A direct characterization of the access transistor is not possible because of the missing contact on the drain side (Deep Trench side). A tentative method to overcome this problem has been reported by G. Zimmermann, by using a front side Focused Ion Beam (FIB) contact to access the drain [2]. Unfortunately this method is limited to “coarse” technologies down to 0.15µm due to the resolution of the FIB probe. In addition, the backside contacting via trench allows the measurement of resistance and/or leakage elements at the interface buried strap, Poly 1-Poly 2 within DT (process conditioned). This paper presents an innovative way to contact the access transistor from the backside of the die, using the deep trench of the cell itself as connection to the drain of the investigated device. The backside contact to the polysilicon filled DT is the key aspect of the method and is realised by backside Focused Ion Beam.
High Aspect Ratio via Milling Endpoint Phenomena in Focused Ion Beam Modification of Integrated Circuits
Authors: Ray Valery 
Published: December 2020

Abstract
Precision detection of endpoint after the milling has reached targeted conductor during circuit modification by focused ion beam system is important. While the sensitivity of the endpoint detection can be enhanced by improved secondary electron collection and sample absorbed current monitoring, a detailed understanding of the endpoint signal distribution within a high aspect ratio (HAR) via is of great interest. This article presents an alternative model of HAR via milling endpointing mechanism in which a phenomenon of spatial distribution of the endpoint information within the HAR via is explained based on sputtering of the material from the targeted metal line and redeposition of the spattered material on the via sidewalls. Increased emission of the secondary electrons, resulting from the subsequent bombardment of this conductive re-deposition by the primary ion beam, is detected as the endpoint. A methodology for the future experimental verification of the proposed model is also described.
System Failure Analysis Process and Case Study
Authors: Konkol Nicholas 
Published: December 2020

Abstract
Failure analysis at the system level requires a well-defined process and methodology in order to drive quality improvements onto motherboards or other subsystems of a personal computer. This process needs to be structured around the type of failure mechanisms that an FA group desires to understand. This paper discusses a specific case study involving electrical overstress in a personal computer that impacted the motherboard of the system. The case study resulted in a solution to increase quality on motherboards in the context of electrical overstress prevention.
FA/LIT Instrument Adjustments for Successful Analysis of Packaged Semiconductor Devices
Authors: Sullivan Daniel J. D. , Hsiung Steve K. , Soopikian John 
Published: December 2020

Abstract
Failure analysis laser inspection tool (FA/LIT) is a tool for the analysis of packaged devices. FA/LIT can routinely expose bond wires for inspection; however, concerns develop for the exposure of stitch bonds, the examination of small trace cracks, and any requirements to maintain electrical functionality of devices. Matching the FA/LIT settings based upon operation and sample material is critical in achieving good exposure of areas of interest with minimal damage. The use of practice samples, or areas away from the area of interest, to verify results before operations on actual FA parts is strongly recommended in this article. The installation of a grounded sample holder has been shown to greatly improve electrical integrity of samples during the laser ablation procedure. Use of the grounding sample holder improved electrical test results from 0% pass to 100% pass in advanced CMOS devices.
Failure Analysis of Laser Blown Metal Fuse Failures in Submicron Technology by C-AFM
Authors: Wen Liang-Feng , Chen Chien-Hui , Chang Allen Timothy 
Published: December 2020

Abstract
This paper presents a method of using a conductive atomic force microscope (C-AFM) to characterize a submicron metal fuse that has been blown open inadequately by laser. In order to obtain a proper I-V curve measured using the C-AFM without affecting the incompletely opened fuse, the paper proposes a method of preserving the fuse by coating its surface with spin-on glass. The paper explains how differences in laser cutting machines resulted in the high failure repair rate of customer product despite equivalent energy and spot size settings. Analysis of the fuse bank circuitry on wafers helped to find the critical physical differences between a fully blown and a poorly blown fuse. By overcoming difficulties in preserving the blown fuse failure sites for C-AFM measurement, laser settings could be easily optimized to ensure proper fuse opening.
Correlation Study of Delamination Gap Detection Capability of SAM and Cross Section/SEM Analysis
Authors: Leng Tan Soo , McKeon James C. P. , Jang Hyo Seong 
Published: December 2020

Abstract
Previous work on determining the minimal air gap detectable in scanning acoustic microscope (SAM) focused on the gap thickness detectable in an idealized Newton ring sample using a 75 MHz transducer. However, air gaps thinner than 0.130 microns have been detected by SAM. These findings have prompted a return to the question of what is the minimal air gap detectability of SAM. To answer this question, further, Newton Ring experiments using transducers across the SAM frequency range have been performed. This article discusses the processes involved in these experiments and provides the results of SAM from actual packages. The procedure involved in cross-sectioning and scanning electron microscopy (SEM) imaging for correlating samples is also provided. Based on the SAM-cross-sectioning-SEM analysis, a detection of 0.056 - 0.183 micron air gaps was concluded for the delamination areas detected by SAM using a 35 MHz 12 mm transducer.
Nondestructive Defect Imaging through Image Intensity Analysis
Authors: Demarest J. , Bearup D. , Dalton A. , Hahn L. , Redder B. , Wallingford F. 
Published: December 2020

Abstract
The continually shrinking dimensions of today’s semiconductor technology occasionally allow for novel approaches in imaging defects. It has become desirable to image subsurface voids prior to cross sectioning and some efforts have been made to address this need including the construction of specialized instrumentation [1]. The thickness of the metallization levels at the 65 nm technology node and smaller now allow for the use of the electron beam in a scanning electron microscope (SEM) as a material sensor. At high accelerating voltages (between 20-30 kV) in backscatter imaging mode the numerical gray level values at each pixel location can correlate to the amount of material directly under the electron beam at that location. This is particularly evident when dealing with defined geometries and material sets offering high contrast changes between materials such as those found in semiconductor technology like copper (Cu) metal and conventional dielectric materials. As a result, subsurface voids can be mapped to a reasonable representation prior to cross sectioning and precise pinpointing of the defect location in test structures can occur. This paper discusses this methodology on 65 nm technology with Cu metal lines in a low-k dielectric material for a two level metal test structure. To some extent this work represents a natural extension of a paper presented previously by the author [2].
Combining High-Resolution Pulsed TIVA and Nanoprobing Techniques to Identify Drive Strength Issues in Mixed-Signal Circuits
Authors: Ravikumar V.K. , Ho M.Y. , Goruganthu R.R. , Phoa S.L. , Narang V. , Chin J.M. 
Published: December 2020

Abstract
This paper uses an interesting case study to highlight high-resolution pulsed thermal-induced voltage alteration (TIVA) with solid immersion lens (SIL) as a technique to isolate a temperature-sensitive failure in mixed-signal circuitry, followed by circuit analysis and nanoprobing to confirm a drive strength issue caused by a process change.
Simulation Studies of Fluorine-Induced Corrosion and Defects on Microchip Al Bondpads in Wafer Fabrication
Authors: Younan Hua , Rao Nistala Ramesh 
Published: December 2020

Abstract
Fluorine-induced corrosion is one of the well-known failure modes of Al bondpad leading to non-stick on pad (NSOP) issues. Exposure to moisture (H2O) and atmosphere (O2) play an important role in determining the shape and size of the Al-F corrosion defects on the Al bondpad surface. In this paper, we will propose a laboratory simulation methodology that can reproduce F-induced defects observed either at the wafer fab or the assembly house. The methodology, known as SLAT (Shelf Lifetime Acceleration Test), is used to study the relationship between the F-corrosion defects and the relative temperature (T) and humidity (RH %). It is observed that Al-F corrosion defects simulated are similar to the real defects found in wafer fab and assembly house in our previous studies. A relatively higher T and lower RH % results in the formation of the “crystal-like” defects, but if a relatively lower T and higher RH % condition is used, the “oxide-like” defects were formed. In this paper, we will compare the simulation results to the real defects found in the previous cases and discuss the failure mechanism. From the present study, the importance of controlling T and RH % during wafer storage to eliminate F-induced defects will be highlighted.
Pulsed Spot Milling and Deposition to Enable Next Generation Circuit Edit Via Development
Authors: Scott Dane , Lundquist Ted , Malik Tahir 
Published: December 2020

Abstract
Pulsed spot milling (PSM) and deposition (PSD) extends gallium ion beam technology for circuit edit. Similar to continuous spot mill, a single-point ion beam defines the basic milling profile, however, PSM utilizes a high-speed beam blanker to “pulse” the ion beam. This beam modulation replaces beam rastering by introducing a delay time which is fundamentally equivalent to refresh time during a typical scan pattern to enable and manage chemistry adsorption. Vias with a base diameter &lt;50nm have been enabled by PSM in combination with advanced ion column designs, beam control parameters and endpointing techniques.
Root-Cause Investigations of Stitch Bond – Shearing by Means of 3D-X-ray Computer Tomography (XCT), Metallographic Polishing and FIB
Authors: Jacob Peter , Jerjen Iwan , Nicoletti Giovanni 
Published: December 2020

Abstract
Since new packaging technologies came up, sensitive failure modes, which were difficult to prove, increased. In many cases, an interaction of bending properties, thermomechanical stress and the material compounds used, cause intermittent failures related to electrical connections. Since any decapsulation might falsify analysis results, non-destructive characterization approaches are of utmost importance for future failure analysis. By means of a typical case study, the capabilities and limitations of a highly developed X-ray tool in such application has been outlined as well as the complexity of root cause findings.
Advanced Scan Chain Failure Analysis Using Laser Modulation Mapping and Continuous Wave Probing
Authors: Kasapi Steven , Lo William , Liao Joy , Cory Bruce , Marks Howard 
Published: December 2020

Abstract
A variety of EFA techniques have been deployed to improve scan chain failure isolation. In contrast to other laser techniques, modulation mapping (MM) does not require electrically perturbing of the device. Beginning with a review of MM and continuous-wave (CW) probing as well as shift debug using MM, this paper presents three case studies involving scan chains with subtle resistive and leakage failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of these techniques. Combining modulation mapping with laser probing has proven to be a very effective and efficient methodology for isolating shift defects, even challenging timing-related shift defects. So far, every device submitted for physical failure analysis using this workflow has led to successful root cause identification. The techniques are sufficiently non-invasive and straightforward that they can be successfully applied at wafer level for volume, yield-oriented EFA.
Thermal Frequency Imaging: A New Application of Laser Voltage Imaging Applied on 40nm Technology
Authors: Celi Guillaume , Dudit Sylvain , Parrassin Thierry , Perdu Philippe , Reverdy Antoine , Lewis Dean , Vallet Michel 
Published: December 2020

Abstract
For Very Deep submicron Technologies, techniques based on the analysis of reflected laser beam properties are widely used. The Laser Voltage Imaging (LVI) technique, introduced in 2009, allows mapping frequencies through the backside of integrated circuit. In this paper, we propose a new technique based on the LVI technique to debug a scan chain related issue. We describe the method to use LVI, usually dedicated to frequency mapping of digital active parts, in a way that enables localization of resistive leakage. Origin of this signal is investigated on a 40nm case study. This signal can be properly understood when two different effects, charge carrier density variations (LVI) and thermo reflectance effect (Thermal Frequency Imaging, TFI), are taken into account.
Highly Automated Transmission Electron Microscopy Tomography for Defect Understanding
Authors: Demarest James J. , Zhai Hong-Ying 
Published: December 2020

Abstract
Imaging tomography by transmission electron microscopy (TEM) is a technique which has been growing in popularity in recent years, yet it has not been widely applied to semiconductor defect studies and root cause determination [1- 3]. In part this is due to the complex equipment, computing needs, and microscope time required to generate the various images which ultimately compose the data set. However, the latest generation of TEMs—with their high level of stability and automation—are greatly reducing the resource needs to create high quality and informative movies of defects rotating about a central axis. One significant advance is the reduction in time required to fabricate a sample and perform the data acquisition by TEM. Today’s microscopes allow for sample fabrication to take place in a few hours or less and can acquire more than 100 images in about an hour at different sample tilt conditions with minimal analyst intervention. This paper describes using automated TEM sample preparation with dual beam focused ion beams (previously reported [4]) in conjunction with automated tomography software on a state-of-the-art TEM. By using an advanced tomography holder ±70° of tilt can be obtained. This is a powerful way to view defects as the failure can be viewed through more than 90° of rotation. Consequently a more complete understanding of the failure site can be obtained over a typical single projection TEM image. This can greatly facilitate root cause determination in a timely manner.
Photon Emission Spectra through Silicon of Various Thicknesses
Authors: Glowacki Arkadiusz , Pagano Carlo , Boit Christian , Yokoyama Yoshiyuki , Jankowski Arkadiusz , Perdu Philippe 
Published: December 2020

Abstract
In this work we present spectrally resolved photon emission microscopy (SPEM) measurements originating from short-channel MOSFETs acquired through the backside of the silicon substrate. Two commonly used detectors have been chosen for the detection of electroluminescence (EL) in the visible and near-infrared spectral regime, namely Si-CCD and InGaAs. As the backside photon emission (PE) inspection is strongly influenced by the absorption of light in a substrate material, the SPEM experiments have been carried out through thinned silicon layers as obtained by mechanical grinding and local focused-ion-beam (FIB) assisted Si material removal. Intrinsic Si absorption (generation of electron-hole pairs) and absorption on free carriers have been modeled to be able to calibrate experimental results and obtain devicerelated PE spectra. The results show no evidences of specific transitions and lead to a conclusion that photon emission from MOSFETs is fully electrical field related.
Advanced Backside Defect Isolation Techniques Using Electron Beam Absorbed Current to Locate Metal Defectivity on Bulk and SOI Technology
Authors: Erington K. , Dickson K. , Lange G. , Garcia J. Z. , Ybarra J. , Wetterling N. 
Published: December 2020

Abstract
This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the backside of the device as a means of locating metallization defects on state of the art bulk silicon and SOI based microprocessor technologies. It builds on previous work which focused only on flip-chip SOI samples. This paper will demonstrate additional EBAC techniques and the ability to analyze devices processed in bulk silicon technology. Also included are the results obtained from an SOI device mounted in a non flipchip package type. Additional details related to sample preparation, equipment used, and improved practices are described.
Split-Gate Flash Memory Cell Odd/Even Fail Pattern Failure Analysis
Authors: Chiu Re-Long , Higgins Jason , Ying Shu-Lan , Chung Jones , Wang Gang , Liu Xu , Lim Ty 
Published: December 2020

Abstract
A NOR-type split gate embedded Flash memory product program marginal fail with odd/even word line failure pattern. Based on cell current comparison, programming cycling tests and voltage drop measurements, the invisible cause of even/odd cells weak program failure mechanism was verified and confirmed visibly by cross sectioning and junction stain treatment. This problem was then solved by tightening photo alignment control and exposure conditions.
Failure Localization by Using a Novel Backside Passive Voltage Contrast Methodology
Authors: Chen Kuo Hsiung , Chang Chih-Chung , Lin Jian Chan 
Published: December 2020

Abstract
Contact resistance from wafer acceptance test (WAT) data is one of the critical parameter to significantly affect fabrication process. While WAT data shows open/short fail, high resistance fail and leakage fail in contact chain structure, the first job in failure analysis (FA) field is to localize failure site. For example, High resistance failure and leakage failure sites can be localized by Infrared Ray Optical Beam Induced Resistance Change (IR-OBIRCH) detection. Most of open failure modes could be isolated by front side passive voltage contrast (PVC) technique. However, there is still a limitation to this technique while contacts are still connected to substrate in metal-1/contact/active chain structure. Active Voltage Contrast (AVC) [1, 2] is a good method to overcome this problem, but the major concern is how to mark the failure location in SEM based probing system. In this paper, we provide a novel backside passive voltage contrast method to improve the failure analysis technique. By thinning down silicon substrate to the active area, a new contact chain from active area is created. Therefore, novel backside PVC is applied to locate the failed site.
Laser Voltage Probing in Failure Analysis of Advanced Integrated Circuits on SOI
Authors: Ravikumar V.K. , Wampler R. , Ho M.Y. , Christensen J. , Phoa S.L. 
Published: December 2020

Abstract
Laser voltage probing is the newest generation of tools that perform timing analysis for electrical fault isolation in advanced failure analysis facilities. This paper uses failure analysis case studies on SOI to showcase the implementation of laser voltage probing in the failure analysis flow and highlight its significance in root-cause identification.