Development of Silicon Polish on 450mm CMP Tool
Authors: Lee Chu-An , Huang Vincent , Cormican Enda , Ku Felix , Lin John , Sin Garrett , Lum Robert 
Published: February 2020

It is becoming more difficult, as the semiconductor technology shrinks, to maintain historical cost reduction trends due to rapidly increasing technology complexities. The progression toward 450mm wafer integration is one of the greatest opportunities to both reduce the die cost and enable greener manufacturing. However, the raw wafer cost may increase by > 2X compared to the 300mm, and 450mm wafer reclaim chain can have a tremendous impact by limiting the number of new fabs built1. To make 450mm processes cost effective, we need to lower development costs on 450mm wafers by developing 450mm silicon polishing process to reclaim 450mm wafers.

Transition of the CMP platform from 300mm to 450mm

The major concerns of CMP process from 300mm to 450mm are considered to be the slurry distribution and the uniformity control by polish head. To fulfill the 450mm wafer planarization within a tight specification for sub-20nm nodes, some innovations or changes in both hardware and consumables are thought to be a must. The schematic view of figure 1 shows the concept of the transition. For example, more zone control is required for profile tuning; higher efficiency dressing or bigger disk design is required for compensating the extra pad size; higher slurry flow rate or multiple-slurry-dispenser is required for better slurry distribution. From the consumable perspective, the characteristics of slurry, e.g. the concentration of additive, may significantly affect the wafer uniformity which may not be seen in 300mm CMP process. Surely, pad groove design for better slurry distribution, lower slurry usage and sub-pad material selection for wafer uniformity are all key factors for 450mm CMP applications.

Improvement of recycled wafer

Based on the 450mm wet clean process results2, surface roughness might be an issue for specific film-stripped wafer, e.g. Poly-Si/SiO2 film or wafers with several wet clean processes history. To improve the surface roughness of those wafers, some CMP process sequences were evaluated. Here, bulk polish was fulfilled by fumed silica and buff polish was fulfilled by colloidal silica on one hard pad. SC-1 and H2O2 were used for the cleaning step. By increasing the buff polish down force, the surface roughness trends down slightly. The same trend can be seen if the process time increases from 1 min to 3 min at the buff polish down force of 2 psi. The roughness can be improved around one order (see figure 2). Regarding the particle performance after silicon CMP, particles can be reduced by increasing the buff polish time as shown in figure 3. However, the particle is extremely high when polishing wafers with bulk slurry. When the particle count of a full process (bulk and buff polish), is compared with buff only process, the difference is more than one order. The particles caused by bulk polish may remain before buff polishing. If the bulk polishing is required for improving some scratches, 2 steps polishing would be a reasonable idea to optimize the defect result. Further consumable study will be done for improve the recycled wafer to M76 specification.
The data, charts, and illustrations in this paper were created by the authors.