bluuebunny/crossref_metadata_2025_split huggingface dataset:
Backside Imaging and AFM Profiling of Tunnel Oxide, Poly 1, ONO and Poly 2 Layers on Flash Devices
Authors: Upadhyaya Kaushal , Blacker Patrice W. 
Published: December 2020

Abstract
With increasing density of metal interconnects and shrinking device sizes with each process generation, there has been a growing interest in the Flash failure analysis (FA) community to approach the devices from the backside. Looking at the process layers like Tunnel Oxide, Poly 1 (floating gate), Oxide Nitride Oxide (ONO) and Poly 2 (control gate) from the backside provides useful information about failure location, failure type and failure mechanism which may be obscure from the front side. This work describes a novel combination of mechanical polishes and chemical etches to delayer Intel’s Flash memory devices from the backside to enable viewing of the bottom of the previously mentioned process layers. In addition to Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) has been attempted to gather more information about the surface details. This technique has been used successfully on Intel’s latest 90 nm flash process and has been verified on earlier process generations.
Diffractive Lenses for High Resolution Laser Based Failure Analysis
Authors: Zachariasse Frank , Goossens Martijn J. 
Published: December 2020

Abstract
In this paper we present a new method to increase the lateral resolution available in laser scanning failure analysis tools. By fabricating a diffractive lens on the back side of the die, the area of the circuit of interest, directly underneath the lens, may be studied with a lateral resolution up to 3.5 times better than without the lens. This method is easily implemented with standard equipment already present in most failure analysis laboratories, and overcomes some significant problems encountered with alternative resolution enhancing schemes.
Scanning Optical Microscopy Application in Micron® Memory Devices
Authors: Yuan Wong Yaw , Poh T.L. Edmund , Lam David 
Published: December 2020

Abstract
The migration to smaller geometries has translated to an increase in the number of transistors possible in each integrated circuit. Failure analysis of such complex circuits presents a major challenge to the semiconductor industry and is a driving force behind the considerable interest in nondestructive, cost-efficient, “shortcut” fault isolation techniques. In this paper, we present the application of thermal-induced voltage alteration (TIVA) for failure analysis of 0.11µm technology memory devices and demonstrate the key aspects of this technique. The back side TIVA results are compared with analysis performed using back side emission microscopy (EMMI), and the limitations of EMMI are highlighted. The advantages and limitations of the TIVA technique are also discussed.
Advanced Electrical Characterization of 90 nm Soft Bit Failure by Nano Probing Technique
Authors: Giret Christelle , Faure Damien 
Published: December 2020

Abstract
The Soft Bit failure (Single Bit Failure sensitive to voltage) of a 90nm SRAM cell presented a difficult challenge for the Failure Analysis (FA) group. Physical analysis of these Soft SRAM failures did not show any visual defects; therefore the FA required an accurate electrical characterization. The transistor characteristics of the failing SRAM transistors are needed in order to speculate on the possible failure mechanism. The Nano-Probing technique performed at Nice Device Failure Analysis of Laboratory (NDAL) allowed us to identify anomalies of I/V characteristics like Vt imbalance, low Gain, asymmetrical Vt, ID (Drive current) and Ron. Case studies of an asymmetry phenomenon reported here lead to a correlation between the failure mode and the electrical measurements. This paper demonstrates a suitable electrical methodology and characterization by Nano-Probing in order to successfully manage a FA approach on this type of failure.
Guideline for Interpreting IR Laser Stimulation Signal on Semiconductors for Materials and for Improving Failure Analysis Flow
Authors: Firiti A. , Haller G. , Beaudoin F. , Perdu P. , Lewis D. , Fouillat P. 
Published: December 2020

Abstract
Infra-red Thermal Laser Stimulation (TLS) signatures obtained on semiconductor materials can be difficult to interpret and to distinguish from signatures from metallic materials. Investigations presented here consist in the study of TLS signals on unsilicided/silicided polycrystalline and diffused silicon resistors of 0.18µm technology. The influence of each process parameter on the TLS signal has been observed and evaluated from the front and back side of the circuit. This allowed us to quantify the effect of the silicon substrate thickness on TLS signal detection and to determine the ideal silicon thickness for sample preparation. This study also completes our methodology based on the TCR parameter which aims at improving defect localization in the depth (Z) of circuitry. As it will be shown through failure analysis case studies, this methodology increases the physical analysis success rate and reduces the turnaround time.
Lock-In Assisted Soft Defect Localization (LIA-SDL) and Its Application in Scan Shift Problems
Authors: Qian Zhongling , Brillert Christof , Burmer Christian , Grützner Markus 
Published: December 2020

Abstract
A new localization method called LIA-SDL is introduced and applied to scan shift problems. The method combines local thermal stimulation technique with lock-in technique applied to periodical test pattern. The localization capability on soft defects is shown in comparison with SDL. Same localization results are obtained. LIA-SDL technique requires no special LSM (Laser Scan Microscope) facilities and is quite easy to handle. Limits and prospects of this new methodology are shown at several analysis examples.
Unique Failure Modes from use of Sn-Pb and Lead-Free (mixed metallurgies) in PCB Assembly: Case Study
Authors: Toth Frank , Shade Gary F. 
Published: December 2020

Abstract
Printed Circuit Board (PCB) assemblies are moving toward lead-free (LF) alloys and away from the traditional Sn-Pb alloy [1]. This change is creating new and unique failure modes as the process adapts to accommodate the higher temperatures of the new process [2]. In addition, mis-processed lots are more likely due to the complexity of assembling a mix of Sn-Pb and leadfree solders, components, PCBs, solder pastes, and fluxes. This case study helps to highlight the challenge and provides an example of what can happen, how to detect it, and how the defects can cause reliability failures.
Stacked Die Analysis Using C-mode Scanning Acoustic Microscope
Authors: Na Li , Khan Jawed , Adams Lonnie 
Published: December 2020

Abstract
For stacked die package delamination inspection using C-mode acoustic microscope, traditional interface and thorough scan techniques cannot give enough of information when the delamination occurs in multi-interfaces, and echoes from adjacent interfaces are not sufficiently separated from each other. A thinner thickness in the stacked-die package could complicate C-mode scanning acoustic microscopy (CSAM) analysis and sometimes may lead to false interpretations. The first objective of this paper is to briefly explain the CSAM mechanism. Based on that, some of the drawbacks of current settings in detecting the delamination for stacked-die packages are presented. The last objective is to introduce quantitative B-scan analysis mode (Q-BAM) and Zip-Slice technologies in order to better understand and improve the reliability of detecting the delamination in stacked-die packages. Therefore, a large portion of this paper focuses on the Q-BAM and Zip-Slice data acquisition and image interpretation.
Method of Detecting Trace Metal Contamination in Thick-Film SOI Device
Authors: Goto Yasunori , Eguchi Hiroomi , Iida Masaru 
Published: December 2020

Abstract
In the automotive IC using thick-film silicon on insulator (SOI) semiconductor device, if the gettering capability of a SOI wafer is inadequate, electrical characteristics degradation by metal contamination arises and the yield falls. At this time, an automotive IC was made experimentally for evaluation of the gettering capability as one of the purposes. In this IC, one of the output characteristics varied from the standard, therefore failure analysis was performed, which found trace metal elements as one of the causes. By making full use of 3D perspective, it is possible to fabricate a site-specific sample into 0.1 micrometre in thickness without missing a failure point that has very minute quantities of contaminant in a semiconductor device. Using energy dispersive X-ray, it is possible to detect trace metal contamination at levels 1E12 atoms per sq cm. that are conventionally detected only by trace element analysis.
The Radio Probe™: A New Measurement Tool for High Speed Integrated Circuits
Authors: Kimball Mark 
Published: December 2020

Abstract
This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.
Dynamic Electroluminescence Imaging (DEI) as an “Optical Oscilloscope” Probe
Authors: Hulse John , Sarault Keith , Simard-Normandin Martine 
Published: December 2020

Abstract
Dynamic Electroluminescence Imaging (DEI) is a technique used to observe semiconductor devices as they operate. Much like a traditional oscilloscope, the technique delivers waveform information that is useful for assessing the operation of the circuits that comprise a device. It can be thought of as a non-contact “optical oscilloscope probe”. The technique has two major advantages over traditional electrical oscilloscope probing. The technique is noninvasive and has a theoretical bandwidth approaching 100 GHz. This means that very fast signals can be observed without unduly loading or otherwise interfering with the circuitry under test. Moreover, the characterization of signals at individual nodes along a signal path allows problems that arise from intervening interconnects and transmission lines to be identified. This paper will show several examples of the radio frequency (RF) measurement capabilities of this technique that have been demonstrated in our laboratory.
Root Cause Analyses of Metal Bridging for Copper Damascene Process
Authors: Song Z. G. , Neo S. P. , Loh S. K. , Oh C. K. 
Published: December 2020

Abstract
New process will introduce new failure mechanisms during microelectronic device manufacturing. Even if the same defect, its root causes can be different for different processes. For aluminum(Al)-tungsten(W) metallization, the root cause of metal bridging is quite simple and mostly it is blocked etch or under-etch. But, for copper damascene process, the root causes of metal bridging are complicated. This paper has discussed the various root causes of metal bridging for copper damascene process, such as those related to litho-etch issue, copper CMP issue, copper corrosion issue and so on.
Transmission Electron Microscopy and Scanning Capacitance Microscopy Analysis of Dislocation-Induced Leakages in n-channel I/O Transistors
Authors: Anderson M.L. , Tangyunyong P. , Hill T.A. , Nakakura C.Y. , Headley T.J. , Rye M.J. 
Published: December 2020

Abstract
By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.
Statistical Evaluation of Scan Test Diagnosis Results for Yield Enhancement of Logic Designs
Authors: Burmer Christian , Erb Hans-Peter , LemMger Andreas , Gruetzner Markus , Schwemboeck Thomas , Trost Stefan 
Published: December 2020

Abstract
During yield ramp, quick turnaround times between production failures and the results of physical failure analysis are essential. In spite of the growing complexity of today's logic designs, a fast defect localization can be done by using diagnostic features implemented within standard test pattern generation tools. The diagnosis result can not only be used for fault localization but also for statistical analysis based on a large number of failing chips. This statistical approach enables the search for systematic yield detractors and leads to a faster product or technology ramp. This paper describes the necessary steps in order to set up statistical scan diagnosis, discusses the main failure analysis strategies and gives experimental results.
Deprocessing of Integrated Sealing Structures from MEMS Devices for Failure Analysis
Authors: Barbieri Thomas J. , Vandemeer Jan 
Published: December 2020

Abstract
Freescale Semiconductor is employing a new, multi-layer integrated seal (IS) on its next generation accelerometers. The IS, which encloses the moveable sensing element, consists of alternating layers of poly-Si and PSG. A technique needed to be developed to remove the integrated seal in order to permit failure analysis. Mechanical methods were attempted first, but these resulted in severe damage to the sensing element. Chemical deprocessing was considered, but eventually abandoned because there seemed to be no way to protect the sensing elements from the wet etchants that would be used on the IS. Eventually, Reactive Ion Etching (RIE) with an Inductively Coupled Plasma (ICP) source proved to be a successful means for removing the IS without impacting the sensing element. As the design of the integrated seal underwent multiple redesigns, the removal process was successfully modified multiple times to comply with these changes. By using the right gases in the correct order, a high level of selectivity was maintained, allowing for removal of successive layers of different materials (poly-Si, PSG) without harming the sensing element. After removal of some IS designs, a wispy residue was observed on the sensing element and remaining IS support pillars. Chemical analysis identified this material as a by-product of the RIE process, and methods were devised to eliminate it.
Recent Developments in TEM Applications for the IC Industry
Authors: Fu L. F. , Wang Y. C. , Jiang B. , Shen F. , Strauss M. , Van Leer B. , Senowitz C. , Buxbaum A. 
Published: January 2021

Abstract
Recent developments in aberration-corrected transmission electron microscopy have drawn much attention from the semiconductor characterization community. Two new developments in transmission electron microscopy, image aberration correctors and probe aberration correctors, are discussed in term of their applications in characterizing gate oxide dielectrics for the IC industry.
Automated Serial-Section Polishing Tomography
Authors: Hunt J.A. , Prasad P. , Raz E. 
Published: January 2021

Abstract
Tomographic reconstruction of a wide range of materials can be accomplished via mechanical polishing serial-sectioning – alternately polishing away material and imaging the remaining polished surface with optical (or electron) microscopy. Under computer control it is possible to acquire 2-D images of hundreds of sections without user intervention and assemble them for 3-D visualization and measurements. In general, the resulting 3-D images permit significantly better understanding of the structure of complex systems than would be possible with a few strategically acquired 2-D images at various depths. Herein we report what we believe is the first general implementation of automated Serial-Section Polishing Tomography (SSPT) and reconstruction using light microscopy.
New Developments in High-Resolution X-ray Computed Tomography for Non-Destructive Defect Detection in Next Generation Package Technologies
Authors: Pacheco Mario , Goyal Deepak 
Published: January 2021

Abstract
The development of a next generation high-resolution x-ray Computed Tomography (CT) tool and its applications are reported in this paper. Some of the key features are region of interest capability, improved time-to-data, improved usability, and data collection automation capability. We also discuss the key technical challenges that are faced by x-ray CT technology. Critical cases that are hard or not possible to isolate by alternative methods are also discussed. Examples include Controlled Collapse Chip Connection (C4) bump cracking and “invisible” non-wetting analysis, ball grid array (BGA) solder joint cracking, and wirebond microcracking and wirebond shorting, as well as demonstration of progressive testing capability.
Flip-Chip Bump Interface Failure Mechanisms In Plastic BGA Packages and Failure Analysis Process Flow
Authors: Wang Zhaofeng 
Published: January 2021

Abstract
The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.
PCB Pad Cratering – Characterization Techniques and Challenges
Authors: Parupalli Satish , Newman Keith , Ahmad Mudasir 
Published: January 2021

Abstract
Some standard characterization techniques (solder ball pull, solder ball shear, etc.) exist for the assessment of solder ball mechanical fracture strength; however, it is not clear if these test methods would also provide characterization of printed circuit board (PCB) pad cratering susceptibility. This paper provides an overview of test methods being investigated by a PCB pad crater industry working group. The scope of this industry working group is two-fold: standardization of PCB pad crater crack characterization and measurement methods and development of a quantitative quality metric for PCB pad cratering. Though the test methods were successful in creating pad craters; there was not enough distinction between the various laminate material types based on the output parameters. Based on the readings from Phase 1 study and available literature, the team is in the process of completing the Phase 2 study which will be reported at a later stage.
Stitch-Bond-Shearing in Optoelectronic Devices, Caused by Lead-Free-Wave-Soldering – Do We Need Improved Wire-Bonding Methods?
Authors: Jacob Peter , Rütsch Michael 
Published: January 2021

Abstract
This case study shows a typical example of a manufacturing-chain-induced reliability problem. All participants of the chain do their work within specifications, but, looking at the system level, severe reliability problems have been observed. In order to get back into the system-level process window, several corrective actions are possible. In this case, the most promising approach is an improvement of the stitch bond robustness, combined with a clear user specification.
Lead-Free Solder/Gold Metallization Interdiffusion in Electronic Interconnects – Challenges and their Control
Authors: Asrar Nausha 
Published: January 2021

Abstract
While considerable amount of researches and investigations have been made on lead-free solder joint reliability, limited number of literatures are available on the effect of gold content on lead-free solder joint performance. The challenges of lead-free solder/gold metallization interdiffusion during high temperature application/test are: gold embrittlement, intermetallics growth, void formation, and tin-whisker formation. Tin whiskers causing system failures in earth and space-based applications have been reported. This paper illustrates a few case histories of such challenges. The results confirmed that the synergistic effects of void formation, intermetallic compounds formation due to the thick gold plating, and coefficient of thermal expansion mismatch between organic and ceramic substrates resulted in brittle fracture of the solder joint. The tin whisker formation was attributed to the compressive stress in the tin solder material, which was caused by diffusion of the end-cap metallization, formation of intermetallics, and thermal cycling of the soldered components.
A Logical Problem Solving Process for High Via Resistance Root Cause Analysis
Authors: Li K. , Liu P. , Teong J. , Lee M. , Yap H. L. 
Published: January 2021

Abstract
This paper presents a case study on via high resistance issue. A logical failure analysis process EDCA (Effect, Defect, Cause, and Action) is successfully applied to find out the failure mechanism, pinpoint the root cause and solve the problem. It sets up a very good example of how to do tough failure analysis in a controllable way.
Vdd Leakage Analysis by a Combination of Various Failure Analysis Techniques
Authors: Song Z. G. , Ippolito S. B. , McGinnis P. J. , Shore A. , Paulucci B. , Kane T. , Tenney M. P. , Trudeau F. G. , Kozaczka A. W. 
Published: January 2021

Abstract
It is generally accepted that the fault isolation of Vdd short and leakage can be globally addressed by liquid crystal analysis (LCA), photoemission analysis and/or laser stimulating techniques such as OBIRCH or TIVA. However, the hot spot detected by these techniques may be a secondary effect, rather than the exact physical defect location. Further electrical probing with knowledge of the circuit schematic and layout may still be required to pinpoint the exact physical defect location, so that a suitable physical analysis methodology can be chosen to identify the root cause of the failure. This paper has described a thorough analysis process for Vdd leakage failure by a combination of various failure analysis techniques and finally the root cause of the Vdd leakage was identified.
Fast Root Cause Analysis Based on Electrical Defect Localization
Authors: Schmidt Michael , Dworkin Larry , Hess Christopher , Squcciarini Michele , Yu Shia , Burrows Jonathan 
Published: January 2021

Abstract
The ability to rapidly perform root cause analysis (RCA) on yield limiting defects is critical to a fab’s ramp. Here we present two methodologies for RCA using specially designed high density test structure arrays and a FIB/SEM DualBeam. These methodologies have been proven to identify the root cause of both hard and soft electrical failures. Correlation between electrical test results and the yield-impacting defects are presented.