(Keynote) Fully-Depleted SOI Technology for High-Power RF Applications
Authors: Dinh Thanh Viet 
Published: May 2020

FDSOI has shown its benefits, compared to other planar bulk technologies, in low power applications by a better electrostatic control, a reduction in leakage currents and device variability. Thanks to the isolation box in the substrate and the intrinsic channel, the parasitic capacitances are also reduced significantly, including the capacitance between source and drain, and between drain and body. These features help to boost the transistors’ RF performance. The published data shows the measured fT (cut-off frequency) and fMAX (maximum oscillation frequency) of RFMOS in FDSOI processes reach 400 GHz, which is the highest among all advanced CMOS nodes. Moreover, by the process construction (gate-first vs. gate-last), the gate resistance of the transistors in FDSOI processes is smaller, which is beneficial to their RF noise performance. These benefits have been used for small-signal RF blocks in Front-end modules, e.g. LNA, VCO and mixers.
In this work, the FDSOI capability for the large-signal RF blocks consisting of integrated power amplifiers (PA) is explored. In previous mobile generations (3G/4G), the base stations need to deliver the peak power more than 100 W, which is solely enabled by GaN or GaAs technologies. Their corresponding handsets also need to transmit a few Watts, which is out of the reach of CMOS-based PA. By moving to massive MIMO with a large number of antennas, the power per RF PA is reduced significantly for both base-stations and handsets in 5G network, with the PMAX per PA varying from 20 dBm to 25 dBm. Such sub-Watt power range opens the opportunities for making silicon-based RF PA, enabling a much larger scale of RF Front-end modules integration. In this paper, two key aspects to make the FDSOI process possible for high-power RF applications in 5G are presented. First, it shows the development of critical active and passive components of high-breakdown and high RF-performance. Second, the 4-port RF test structure designs and in-house characterization to explore the capability of back-bias on RF performance are discussed.
Regarding the high-voltage transistors, 3.3V and 5V RF LDMOS have been designed and fabricated without any additional dedicated mask in a sub-28nm FDSOI process. The device was constructed in a non-SOI area. A record high RF-performance, with fT larger than 50 GHz for 5V LDMOS and 100 GHz for 3.3V device, has been achieved. For passive elements, 7V fringe capacitators, inductors and transformers have been developed. The fringe capacitors show their robustness at 7V, with best-in-class quality factor at both 5 GHz and 30 GHz. The matching performance of these capacitors are comparable to the best MOM capacitor mismatch performance in other modern CMOS technologies, which makes them also suitable for high-precision signal processing and filtering. Inductors and transformers have been designed in top 3 metal layers to have state-of-the-art quality factors. An excellent matching between RF measurements and EM simulations has been obtained for these passive elements. Such matching proves that the performance of the passive devices is very well predictable, enabling full design optimization for fringe capacitors and transformers / inductors.
To capture the impact of back-bias on RF performance, and facilitate the RF model against silicon validation in the presence of back-bias, this paper shows a 4-port test structure design (GSGSG). The RF measurements for an RFMOS with a back-bias varying from strong reverse to forward are discussed. These results initiate various scenarios for using back-bias in RF applications, e.g. reducing the supply voltage to have the same RF performance, or extending the maximum current density at the same peak fT to have enough RF power.
In summary, this paper shows the development of high-voltage RF active and passive devices in a sub-28nm FDSOI process, which are required for building integrated RF power amplifiers at Watt-level in high-performance cost-effective RF front-end ICs. The 3.3V / 5V RF-LDMOS with a cutoff frequency beyond 100GHz has been achieved in silicon, which brings a breakthrough for RF PA designs, both at sub-6GHz and 28GHz. For passive devices, by combining the novel RF design with an RF-compatible metal stack and accurate EM simulation, a record high Q-factor for a 7V-fringe capacitor, a 2-way transformer and 8-shaped inductors are obtained. The developed 4-port measurement for GSGSG structures has been proven as an indispensable tool for RF-FDSOI. These results show FDSOI process can be comparable to RF-HV-centric non-CMOS processes, e.g. SiGe and GaAs, for Watt-level power RF applications.