Temperature and Environmental Effects on Resistance of Nano-Resistor Devices
Authors: Lin Wen-Shan , Liu Lingguang , Kuo Yue 
Published: February 2020

The solid-state incandescent light emitting device (SSI-LED) emits the broadband warm white light [1-5]. The light emission principle is the thermal excitation of the nano-resistors formed from the dielectric breakdown of a MOS capacitor with a nm-thick high-k gate dielectric layer [5]. Besides the light emission, the nano-resistor device shows the diode-like characteristics, i.e., current flow in one direction but not the other direction [1]. Since the nano-sized structures are easily subject to the environmental effect, e.g., oxidation in air [6,7], it is important to understand how the temperature and high humidity affect the electric resistance of the nano-resistors in the SSI-LED.
MOS capacitors of 50 μm, 100 μm, 200 μm, 300 μm, and 400 μm diameters were fabricated on a pre-cleaned p-type (10-5 cm-3) (100) Si wafer. Each capacitor contains 1) a 9 nm thick zirconium-doped hafnium oxide (ZrHfO) high-k gate dielectric (including the interface layer with Si), 2) an 80 nm thick ITO gate electrode, and 3) a Mo back side contact layer. Nano-resistors, as shown in Figure 1, were formed after the gate dielectric was broken. The current density vs. voltage (J-V) curve of the nano-resistor device was measured between Vg
= 0 V and -20 V at room temperature, 50˚C, 80˚C, 100˚C, and 120˚C. The resistance was extracted from the linear portion of the curve, i.e., between -10 V and -18 V. Then, the sample was loaded in an environmental chamber (Associated Environment System BHD-403 7136) under relative humidity 80% at 80 ̊C for 1 hour. The J-V curve was measured in air at room temperature.
Figure 2 shows resistances of various sized nano-resistor devices at 50ºC, 80ºC, 100ºC, and 120ºC. With the increase of temperature, the resistance increases. Since the resistance is contributed by elements in the current path, i.e., the ITO gate electrode, nano-resistors, interfaces, and the Si wafer, each of which can affect the result. Although the Mo resistance is affected by the temperature [8], the value is much smaller than that of the nano-resistor device in Fig. 2. The resistance of the p-type Si (1015 cm3) changes little in the room temperature to 120ºC range [9]. The resistance of ITO also remains in the same temperature range [10]. Therefore, the temperature effect must be contributed by nano-resistors and interfaces.

Figure 3 shows the size effect on the resistance after the 80% humidity and 80℃ annealing. The resistance decreases nonlinearly with the increase of the diameter. Assuming that all nano-resistors are of the same dimension and evenly distributed underneath the gate electrode of area, the resistance vs. device size relationship should follow the Pouillet’s law of

R = ρ⋅L/A [1]
where R is the resistance, ρ is the resistivity, L is the length, and A is the cross-sectional area. The prediction curve in Fig. 3 was calculated based on the resistance of a 400 µm diameter device. It deviates from the measured data especially in the small diameter range. It was reported that the density of nano-resistors near the edge of the gate is larger than that in the center region [1]. As the device diameter is reduced, the area ratio of the edge region to the total gate electrode increases. Therefore, the density of the nano-resistors increases with the shrinking of the device size, which results in the reduction of the resistance. Also, nano-resistors near the gate electrode edge may be of different sizes from those away from the edge. Moe detailed discuss of the environmental effect will be presented.
Lingguang Liu acknowledges the financial support of National Natural Science Foundation of China (Grant Number 61771382) and the Shaanxi International Science and Technology Cooperation and Exchange program (2018KW-034).
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Figure 1