bluuebunny/crossref_metadata_2025_split huggingface dataset:
Gate-Level Netlist Reverse Engineering Tool Set for Functionality Recovery and Malicious Logic Detection
Authors: Meade Travis , Zhang Shaojie , Jin Yier , Zhao Zheng , Pan David 
Published: December 2020

Abstract
Reliance on third-party resources, including thirdparty IP cores and fabrication foundries, as well as wide usage of commercial-off-the-shelf (COTS) components has raised concerns that backdoors and/or hardware Trojans may be inserted into fabricated chips. Defending against hardware backdoors and/or Trojans has primarily focused on detection at various stages in the supply chain. Netlist reverse engineering tools have been investigated as an alternative to existing chip-level reverse engineering methods which can help recover functional netlists from fabricated chips, but fall short of detecting malicious logic or recovering high-level functionality. In this work, we develop a netlist reverse engineering tool-set which recovers high-level functionality from the netlist, thereby aiding malicious logic detection. The tool-set performs state register identification, control logic recovery and datapath tracking, which facilitates validation of encrypted/obfuscated hardware IP cores. Relying on 3-SAT algorithms and topology-based computational methods, we demonstrate that the developed tool-set can handle netlists of various complexities.
Advanced Package FA Flow for Next-Gen Packaging Technology Using EOTPR, 3D X-Ray and Plasma FIB
Authors: Schmidt Christian , Pichumani Pradip Sairam , Alton Jesse , Igarashi Martin , Chan Lisa , Principe Ed 
Published: December 2020

Abstract
Within this paper, the authors present an adapted FA flow for state-of-the-art Package Failure Analysis for 20nm technology and below. As a key aspect, three methods (EOTPR, 3D Xray & PFIB) are introduced as the next-gen FA standard methods for emerging package technologies such as TSV, u-pillar bumping and stacked-die devices. By showing different types of daily Package FA requests, the paper compares & discusses important factors such as turn-around-time (TAT), success yield and results quality. In the end, an outlook is given how recent developments on these techniques will help to establish a new standard FA flow.
How to Achieve Artifact-Free FIB Milling on Polyimide Packages
Authors: Hrnčíř Tomáš , Šikula Marek , Oboňa Jozef Vincenc , Gounet Pascal 
Published: December 2020

Abstract
High speed FIB cross-sectioning of polyimide material was traditionally very difficult because of artifacts created by FIB on the cross section plane. Therefore we propose a simple method, which retains the high speed of the FIB process, but significantly improves the quality of the cross section plane. The method involves a hard mask positioned close to the intended place of the cross section using a precise manipulator. This then enables highly accurate and site-specific FIB cross-sectioning. Cross sections can be made very quickly and with the excellent quality in comparison to standard procedures based on gas-assisted deposition of a protection layer.
Charge-Induced Damage on SOI Wafers—A Case Study
Authors: Miller Mary A. , Udoni Darlene M. 
Published: December 2020

Abstract
This work outlines a case study of charge-induced damage to SOI wafers that caused gate leakage in discrete transistors and static leakage in packaged integrated circuits (ICs). The consequential yield fallout occurred primarily at wafer center. Electrical, optical, and laser-based failure analysis techniques were used to characterize the damage and determine root cause of electrical failure. The failure mechanism was localized to a rinse step during chemical mechanical planarization (CMP). Furthermore, both current-voltage (IV) sweeps and characteristic spatial patterns generated by thermally-induced voltage alteration (TIVA) were used to capture the trends on both packaged ICs and SOI wafers for this type of charge-induced damage; this led to quick identification of another source of charge-induced damage that affected the post-fab yield.
Ultra-Low Frequency Laser Voltage Imaging of Mixed-Signal Designs
Authors: Schmidutz Tobias , Hoyler Charlotte , Qian Zhongling , Brillert Christof , Burmer Christian 
Published: December 2020

Abstract
During the last years, laser reflectance modulation measurements (i.e. LVI, CW-SIP etc.) have become indispensable tools for the analysis of logic circuits at frequencies in the megahertz range. In this paper we present a method to extend the usefulness of these methods to mixedsignal circuits driven at ultra-low frequencies in the kilohertz range. We show that by toggling the main power supply, information of the electric behavior can be easily obtained from analog structures, removing the need for tester-based stimulation. This method proved especially useful for the debugging of chip startup failures. We demonstrate this with two case studies. In a first case, a defect in the analog part shut down the digital part of the chip. This prevented the use of debugging methods such as the read-out of error registers or the use of scan chains. Conventional methods like photon emission microscopy and thermal laser stimulation were also not successful at finding the problem. However, laser-voltage imaging (LVI) of the analog circuit at key locations while toggling the chip power supply in the kilohertz range led us to the failing net. In a second case on a different product, we similarly identified a failing capacitor in the error logic by modulating the chip enable pin in the kilohertz range.
Electrical Characterization and Failure Analysis Using Operando TEM
Authors: Pivak Yevheniy , Perez-Garza H.H. , Zintler Alexander , Molina-Luna Leopoldo 
Published: December 2020

Abstract
We present here the development of a system that allows for in-situ studies inside the Transmission Electron Microscope (TEM). Functionalized Microelectromechanical Systems (MEMS) used as sample carriers, referred to as Nano-Chips, contain up to eight electrodes used for simultaneous biasing and heating purposes, enabling electro-thermal characterization of various sample types inside the TEM under real life dynamic conditions. This operando approach is an ideal method to study failure analysis of semiconductor materials, performance of resistive switching devices, batteries, fuel cells, piezoceramics and many more.
Automation to Enable Energy Dispersive X-ray Spectroscopy for High Throughput Failure Analysis and Metrology
Authors: Roller Justin , Zhong Zhenxin , Strauss Michael , Bidiuk Oleksii , Blackwood Jeff , Verheijen Martin , Ugurlu Ozan , Donald Jason 
Published: December 2020

Abstract
Automated S/TEM (auto-S/TEM) and by extension automated energy dispersive x-ray spectroscopy (auto-EDS) enable the collection of large volumes of data that historically was not feasible on a sustained basis using manual S/TEM operation. Automation removes variabilities attributed to operator training and bias while enabling repeatable, precise, and consistent data. This paper examines general considerations for high volume and auto-EDS metrology. Maps are evaluated relative to analysis time and the requisite signal-to-noise (SNR) necessary for adequate measurement precision. Auto-EDS parameters (dwell time and mapping time) were investigated to maximize EDS net counts and SNR for throughput. A methodology was presented to monitor the SNR ratio of critical dimensions which can be extended to further understand the minimum value needed to maintain an acceptable measurement precision. It is important to further study other means of increasing the SNR, such as beam current, accelerating voltage, and larger solid-angle detectors.
New Insight into Interconnect Defect Analysis for DRAM
Authors: Kim Youngil , Jeon Hyungchae , Chung Jaeguen , Yoo Donggyun , Kim Seonmi , Nam Incheol , Baek Chijong , Koo Jahyun , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jang Seongjin 
Published: December 2020

Abstract
As various types of DRAM package have been developed, new defects in interconnection in chip have been discovered after assembly process such as flip chip bump mount or wire bonding. There are lots of regular inspections in manufacturing process to detect assembly defects, but it is not easy to find all of the defects. We used a method to classify physical failures based on electrical measurements. Conventional open and short tests by using ISVM were used to support the mass production. External voltage sweep is employed to distinguish weak defects from strong defects of interconnection. Finally, a proposed method was verified with statistical analysis of 800,000 FBGA DRAM chips and physical analysis of failure chips.
Latest Advancements in Nanoscale IR Spectroscopy for Characterization and Failure Analysis of Electronic Devices
Authors: Roy Anirban , Hu Qichi , Cook Debra , Dillon Eoghan , Kjoller Kevin 
Published: December 2020

Abstract
Atomic force microscopy infrared (AFM-IR) technology combines the best of both worlds of AFM and IR spectro-microscopy offering high spatial resolution chemical characterization. Recent developments in the AFM-IR technique, such as tapping AFM-IR pushes the spatial resolution limit below 10 nm, making it ideal for chemically characterizing directed self assembly (DSA) components and defects for failure analysis. This paper demonstrates the chemical characterization of DSA nanopatterns using tapping AFM-IR technology with spatial resolution beyond 10 nm. Tapping AFM-IR experiments is performed on different block copolymers routinely used to fabricate directed self-assemblies on Si wafers. Along with chemical mapping, mechanical properties, such as relative stiffness and damping yielding complete chemical and mechanical property information in nanoscale to achieve material contrast, can be simultaneously probed.
Scan Chain Fault Isolation using Single Event Upsets Induced by a Picosecond 1064nm Laser
Authors: Serrels Keith A. , Dickson Kris , Bodoh Dan , Erington Kent , Weerakoon Anusha , Foot Eric 
Published: December 2020

Abstract
We present the first experimental demonstration of stuck-at scan chain fault isolation through the exploitation of Single Event Upsets (SEU) in a Laser-Induced Fault Analysis (LIFA) system. By observing a pass/fail flag, we can spatially map all flops after a defect in a failing scan chain through induced SEU sites produced by a fiber-amplified 25 ps 1064 nm diode laser. In addition, a custom fault isolation methodology is presented in which the result highlights only the first working flop immediately after the defect mechanism causing the stuck-at chain failure. This work demonstrates a novel method for rapid scan chain fault isolation that significantly improves localization efficacy over conventional best-known methods (BKM) based on frequency mapping. Moreover, experimental results are presented to demonstrate that LIFA can be extended to interrogate the data state of flip flops in a scan chain. Results are also presented to establish that LIFA can be configured as a hardware-based diagnostics platform.
Integration of Probing Capability into Plasma FIB for In-Situ Delayering, Defect Inspection, and EBAC on BEOL Defects of Sub-20nm FinFET Devices
Authors: Zudhistira D. , Wei M.S. , Narang V. , Chin J.M. , Šikula Sharang, M. , Novotný K. , Goupil G. , Oboňa J. Vincenc , Rummel A. , Kemmler M. , Kleindiek S. 
Published: December 2020

Abstract
Deprocessing and probing are two quintessential steps in the physical failure analysis (PFA) and competitive analysis of integrated circuits (ICs). Typically, these steps are accomplished using multiple tools, which include polishers, electron microscopes, and probers. To combat the aggressive back-end-of-line (BEOL) scaling which has significantly decreased the controllability of manual polishing, gas-assisted Xe plasma FIB has been employed to achieve large area uniform delayering. Combined with an in-situ probing capability within the plasma FIB, the iterative process of juggling between tools is streamlined into a seamless process. In this paper, the successful integration of Prober Shuttle and plasma FIB to isolate and visualize real defects on sub-20 nm microprocessor chips are presented.
Improved Burn-In Stress Methodology for Stress Uniformity
Authors: Ko Jungsuk , yang Hoonchang , Jeon Hyungchae , Nam Gyuyoung , Ryu Youngseok , Park Changyu , Hwang Hongsun , Oh Taeyoung , Kim Jonghoon , Jang Seongjin 
Published: December 2020

Abstract
The necessity of hot temperature stress is widely recognized as the initial stress methodology to maintain the stability of products from infant defects in device [1, 2]. However, hot temperature stress has a disadvantage in terms of stress uniformity because temperature variation according to stress environment such as chamber, board, and tester accelerates different stress effects per chips. In addition, this stress condition can cause serious reliability problem in the mass production environments. Therefore, the stress temperature should be lowered to minimize the temperature deviation due to the production environments. The reduction of stress temperature cause the lack of stress amount, so optimized stress voltage and time to maintain the stress condition is required. In this study, various stress voltage and time with decreasing temperature were evaluated in consideration of lifetime that unit elements such transistors and capacitors did not degrade by any stress conditions. In addition, it was confirmed that stress uniformity can be improved in the stress condition obtained by the evaluation. Furthermore, the enhanced initial failure screen ability was proven with mass evaluations.
Gallium Arsenide Integrated Circuits Decapsulation Technique Using Mixed Acid Chemistry For Die-Level Failure Analysis
Authors: Consigo Harold Jeffrey M. , Calanog Ricardo S. , Caseria Melissa O. 
Published: December 2020

Abstract
Gallium Arsenide (GaAs) integrated circuits have become popular these days with superior speed/power products that permit the development of systems that otherwise would have made it impossible or impractical to construct using silicon semiconductors. However, failure analysis remains to be very challenging as GaAs material is easily dissolved when it is reacted with fuming nitric acid used during standard decapsulation process. By utilizing enhanced chemical decapsulation technique with mixture of fuming nitric acid and concentrated sulfuric acid at a low temperature backed with statistical analysis, successful plastic package decapsulation happens to be reproducible mainly for die level failure analysis purposes. The paper aims to develop a chemical decapsulation process with optimum parameters needed to successfully decapsulate plastic molded GaAs integrated circuits for die level failure analysis.
Infrared Lock-In Thermography: From Localization of Low Power and Masked Defects to Absolute Temperature Mapping for Product Debug
Authors: Jalink J. , Firiti A. , van den Biggelaar J. , Reverdy A. , Lai B. 
Published: December 2020

Abstract
The application of IR-Lock-In Thermography (IRLIT) has been extended from 2D and 3D package fault isolation to on-die level analysis. In addition, the technique has become more sensitive allowing for detection of much lower dissipated power. In this paper, several fault localization cases covering PCB assemblies down to die level analysis are discussed using IR-LIT and absolute temperature mapping. Where possible, the analysis is complemented with physical defect verification. The fault isolation cases include an ultra-low power dissipation (&lt;150 nW) and several case studies with high ohmic connections. For the latter a new method based on phase mapping is discussed allowing for 2D localization of thermally invisible defects. The method will be demonstrated on a test vehicle where phase data extracted from a visible feature of the device under test is studied. After this, a case study at die level is presented in an attempt to distinguish the phase information from two stacked M2-M3 metallization layers of the Back-End Of the Line (BEOL). Finally, temperature mapping results of a 5 micron wide aluminum feature in silicon-oxide is presented that is pushing the optical resolution of the tool.
Artefacts of SEM/TEM Observations Cases on Seal Ring Structure and Correctives Samples Preparations to Avoid Them
Authors: Charles Christophe , Margain Alain 
Published: December 2020

Abstract
FIB/SEM and TEM are standard characterization techniques for evaluation of process modification of microelectronics samples. In this paper, artefacts from these techniques are studied. The sample preparation methods are optimized to avoid damages. Seal-ring structures are chosen as an example in this study to show artefacts and difficulties in SEM and TEM observations. Two cases of artefacts are considered: one with TEM sample preparation followed by TEM imaging, and the other one with SEM observations after FIB cross-sectioning. In the first case, electronic chips that failed during stress tests are investigated, while in the second case a part has been dismissed during robustness qualification test. In the former, thickness of TEM lamellae has been evidenced as a key factor for delamination between layers under beam, whereas in the latter, it was observed that the electron beam lead to a shrink of oxide layers, which induced the break of underlying contacts.
Isolating an Open in 2.5D µBump & Chip Bump Chains using SDR, EBAC and Capacitive Measurements
Authors: Distelhurst Kevin , Hunt Doug , Bader Dan 
Published: December 2020

Abstract
The limitations of Moore’s Law have led to alternatives in semiconductor packages that provide more functionality. Stacking multiple chips in 2.5D and 3D configurations has become a common solution. During the development of these technologies, test chains of chip to chip micro bumps and thru silicon via’s (TSV’s) at various regions within the stack are often employed. These present new challenges to the already difficult process of localizing open and resistive chain fails deep within the stack for root-cause analysis. A combination of quick and effective fault isolation techniques is often required to reliably isolate an open in a time critical situation. Capacitive measurements is a useful technique in some cases for obtaining a quick general location of an open. Magnetic Field Imaging (MFI), specifically Space Domain Reflectometry (SDR), is a non-destructive technique that can provide a relatively accurate location of an open. Electron Beam Absorbed Current (EBAC) is another useful technique in confirming and further isolating the open as the region of interest of the sample is approached via cross-sectioning or planar deprocessing. Case studies using these three techniques are presented and their strengths and weaknesses are discussed. The case studies focus on ìbump and chip bump chains in 2.5D samples.
2D carrier Density Mapping Using SNDM-dC/dV and dC/dz of SiC Power MOSFET
Authors: Yu Jing-jiang , Yamaoka T. , Aiso T. , Watanabe K. , Shikakura Y. , Kudo S. , Tamura K. , Mizuguchi K. 
Published: December 2020

Abstract
Scanning nonlinear dielectric microscopy is continuously developed as an AFM-derived method for 2D dopant profiling of semiconductor devices. In this paper, the authors apply 2D carrier density mapping to Si and SiC and succeed a high resolution observation of the SiC planar power MOSFET. Furthermore, they develop software that combines dC/dV and dC/dz images and expresses both density and polarity in a single distribution image. The discussion provides the details of AFM experiments that were conducted using a Hitachi environmental control AFM5300E system. The results indicated that the carrier density decreases in the boundary region between n plus source and p body. The authors conclude that although the resolutions of dC/dV and dC/dz are estimated to be 20 nm or less and 30 nm or less, respectively, there is a possibility that the resolution can be further improved by using a sharpened probe.
Знахідка монет XVIII століття з Литвинівки Вишгородського району на Київщївщині
Authors: Potyl’chak Oleksandr 
Published: December 2020

Аналізується комплекс монет XVII ст., знайдених автором навесні 1989 р. поблизу с. Литвинівки Вишгородського району Київської області. Описано обставини виявлення та географічну локалізацію знахідки. Зроблено спробу класифікувати та атрибутувати монети, типологізувати й датувати нумізматичну пам’ятку, що складається з 21 монети Речі Посполитої, Баварії та Прибалтійських володінь Швеції, які за монетною регалією поділяються на три групи. Група А – два білонних соліди та подвійний денарій карбування Сигізмунда ІІІ (1587-1632); два мідних соліди (“боратинки”) Яна ІІ Казимира (1648-1668). Група В – 2 крейцери (“напівбатцен”) Герцогства Баварія, білон, карбування Максиміліана І (1598-1651). Група С – 15 білонних солідів Прибалтійських володінь Швеції карбування Христини Августи (1632-1654), Карла Х Густава (1654-1660) та Карла ХІ (1660-1697). Характерну для грошового обігу українських земель другої половини XVII ст. підгрупу монет знахідки становлять 6 ризьких солідів із монограмами королеви Христини Августи та Карла Х Густава, що мають явні ознаки належності до сучавських імітацій. Порівняно невелика кількість монет знахідки, їх дрібні номінали, належність до одного періоду грошового обігу, а також приблизно однаковий ступінь зношеності вірогідно свідчать, що виявлена нумізматична пам’ятка не належить до категорії монетних скарбів, а є загубленим або прихованим, а пізніше втраченим гаманцем, що належав небагатому власнику, найімовірніше селянину. Всі обставини вказують на те, що ці гроші було відкладено господарем не для тривалого зберігання, а для здійснення поточних дрібних купівель. Найбільш пізньою за датою карбування монетою у складі виявленої нумізматичної знахідки є білонний солід Лівонського герцогства із монограмою Карла ХІ зі значними слідами зношення. Введені до наукового обігу дані про карбування солідів цього шведського короля на державному монетному дворі в Ризі дозволяють стверджувати, що монета цього номіналу з монограмою Карла ХІ могла потрапити у “гаманець” із Литвинівки не раніше початку 70-х рр. XVII ст. Виявлені монети складають єдиний нумізматичний комплекс та є типовими для грошового обігу Правобережної Київщини другої половиниXVII ст.
Фальшивомонетництво в Україні в роки Першої світової війни
Authors: Orlyk Svitlana , Boiko-Gagarin Andrii 
Published: December 2020

Стаття присвячена проблемам фальшивомонетництва в Україні в роки Першої світової війни. До наукового обігу вводяться раніше неопубліковані джерела, що дозволяють відкрити нову сторінку в історії грошового обігу. Як відомо, зразками для підробки частіше стають найбільш популярні серед населення гроші. Такими грошима в роки Першої світової війни стають золоті та срібні монети, кредитні білети, випущені під час війни за довоєнним зразком (відрізняючись підписом касира на банкноті), розмінні марки та казначейські знаки, різноманітні грошові сурогати. Всі зазначені види грошей були відтворені фальшивомонетниками в зазначеному періоді. Аналізуючи архівні джерела, нам вдалося встановити факти вчинення спроб економічної диверсії з боку Австро-Угорщини та Німеччини стосовно Російської імперії шляхом виготовлення якісних підробок російських кредитних білетів та їхній збут на окупованих російськими військами територіях Західної України. Прослідкувавши повідомлення на сторінках газет зазначеного періоду, нам вдалося вивчити та описати діяльність підпільних угрупувань фальшивимонетників, що виготовляли розмінні марки в Києві та Одесі. Показано, що для фальсифікаторів інтерес складали не лише грошові знаки, а й інші ліквідні активи: цінні папери, гербові марки на сплату податку, відрізні купони отримання прибутку по облігаціях, а також підроблені паспорти, мобілізаційні свідоцтва, документи для виїзду за кордон та ін. Внаслідок розвалу Російської імперії та серйозних політичних перетворень кардинально змінюється структура грошового обігу в Україні, а відповідно – й фальшивомонетництво набирає зовсім іншиого характеру, що є темою окремого глибокого дослідження.