(Invited) Enabling Fan-out Wafer-Level Package (FOWLP) through Innovative Copper Electrodeposition Processes
Authors: Buckalew Bryan , Thorkelsson Kari , Oberst Justin , Banik Stephen , Ponnnuswamy Thomas 
Published: February 2020

IC packaging technology has evolved in a quite diverse manner over the past decade, addressing both high-end and low-end applications, resulting in approaches such as package-on-package (PoP), fan-out wafer-level package (FOWLP), 3D IC integration with through-silicon via (TSV), and 2.5D with TSV-Si interposer. FOWLP technology offers significant cost and performance advantages relative to other packaging approaches and is therefore receiving widespread adoption throughout the industry for applications such baseband processor and applications processor (AP). It is anticipated that this technology may be extended for high-end devices such as field-programmable gate array (FPGA) and graphics processing unit (GPU). As a result, FOWLP technology is expected to ramp at a strong growth rate over the immediate future. FOWLP technology comprises conventional under-bump metallization (UBM) and pillar/micro-pillar, as well as new routing/connection applications such as fine-line redistribution layer (RDL) (sub 5x5 mm), integrated via-RDL structures, and mega pillars (>150 mm). These new applications drive fundamental challenges in electrodeposition.
Fine-line RDL applications present challenges for both lithography and electrochemical deposition (ECD) processes. For wafer handling, the reconstituted wafers used in FOWLP can exhibit significant warpage and maintaining feature dimensions across wafer topography becomes challenging. New electroplating technology is required to prevent physical degradation of the fine-line RDL. Etchants used for copper (Cu) wet etch will preferentially attack the interface between the Cu ECD line and the Cu physical vapor deposition (PVD) seed layer, resulting in an undercut that degrades the mechanical reliability. This undercut can be minimized by using innovative electroplating technology to reduce the thickness of the Cu PVD seed layer. Thermal cracking of the Cu line has also been posed as a key integration challenge. Grain engineering is discussed as one potential solution to overcome this issue.
Many of the current FOWLP approaches include the adoption of multi-layer RDL which are fabricated from low dielectric polymer passivation layers and Cu ECD lines. Multi-layer RDL patterns can result in significant topography variation, which can impact other process integration challenges such as control of critical dimensions (CDs). To minimize topography variation, a new ECD reactor design is used to provide ultra-uniform Cu ECD.
Mega pillars consist of 180-220 mm (200 mm average) Cu thickness while standard Cu pillar applications typically vary between 20 and 40 μm (30 mm average) thickness. This large disparity in thickness can translate to approximately 6x longer plating times if a similar deposition rate is used. The process of plating large features employed as interconnects often encounters mass transport limitations that can curtail the deposition rate. This effect is explored in detail via computational modeling. The aspect ratio of through-resist features is shown to have a severe impact on minimum fill time, where a high (4:1) aspect ratio feature takes more than 7.5 times as long to fill as a low (1.2:1) aspect ratio feature. Convection of the electrolyte above the surface of the photoresist, which is largely influenced by the ECD reactor design, is shown to have a pronounced impact on fill times over the range of feature dimensions. Furthermore, some integration requirements for mega pillars warrant extremely high within-die uniformities and flat bump shape. Attaining such high-quality plating performance can greatly minimize the downstream planarization requirements.
This paper will focus on new innovations in Cu ECD processes for fine line RDL, multi-layer RDL, and mega pillar to enable FOWLP technology.