(Invited) Atomic-Scale Design of Advanced Transistors Via Ultrathin Negative Capacitance Gate Stacks
Authors: Cheema Suraj 
Published: December 2024

Negative capacitance [1,2] has emerged as a promising solution to overcome fundamental energy-efficiency limits in conventional electronics, in which internal ferroelectric order within the gate stack of a field-effect transistor can enable low-power operation. Thus far, claims of negative capacitance have been primarily demonstrated in perovskite-structure thick films or through misleading “S-curve” transient experiments in fluorite-structure thick films. However, integration into advanced semiconductor technology nodes will require stabilization at the ultrathin regime and evidence of capacitance enhancement (i.e. lower equivalent oxide thickness, EOT) to enable highly-scaled lower-power operation.
Here, we present evidence of negative capacitance in atomic-scale HfO2-ZrO2 heterostructures down to two-nanometers and one-nanometer thickness [3,4], leveraging our recent work examining the atomic limits of fluorite-structure ferroelectricity on silicon [5,6]. ALD HfO2-ZrO2-based heterostructures on Si-SiO2 demonstrate ultralow EOT without having to scavenge the SiO2 interlayer, in stark contrast to conventional high-κ metal gate (HKMG) technology [7]. Accordingly, in comparison to industrial HKMG benchmarks, these SiO2-buffered antiferroelectric-ferroelectric gate stacks boast favorable performance and can provide multiple node technology boosts [8]. Due to seamless integration and transition from high-κ HfO2-based dielectrics to negative-κ HfO2-ZrO2-based ferroelectrics, these NC stacks have already been validated and integrated by prototyping foundries [8] and semiconductor foundries [9].
In this talk, key differences between static versus transient negative capacitance will be highlighted to clarify misleading literature and explain their relative benefits for logic transistors [3,4] versus other applications [10]. Perspectives on further routes to EOT scaling via negative capacitance gate stacks for beyond-1-nm-node logic technology will also be discussed.

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