bluuebunny/crossref_metadata_2025_split huggingface dataset:
Enhanced Visible-Light Photoelectrochemical Performance of Titana Nanotubes Modified by Atomic Layer Deposited Cobalt Oxide
Authors: Huang Bin , Wen Yanwei , Shan Bin , Chen Rong 
Published: February 2020

TiO2 is widely considered as one of the promising materials to fulfill photoelectrochemical water splitting requirements for its low cost, nontoxicity, photostablity, and strong photo oxidation ability. Several synthesis approaches have been reported to fabricate TiO2 nanostructures, including template assisted hydrothermal, anodization, and sol-gel. Among them, anodization method is capable of producing highly ordered, well aligned TiO2 nanotubes (NTs) with controlled diameters and tube length. The unidirectional tubular structure provides the charge transport channels from electrolyte/photoanode interface to conductive substrate.
The intrinsic band gap of TiO2 (3.2eV for anatase and 3.0eV for rutile), however, limits its optical absorption only within UV region. The rapid recombination rate of photo-excited electrons and holes also severely hinders its practical application.1 Many approaches have been developed to promote the photo response of TiO2 in visible light region. For example, by hetero coupling, the holes and electrons can be photo excited from the narrow-gap semiconductor and separated effectively, which significantly promotes the visible light response. To form hetero coupling, cobalt oxide, a typical P-type semiconductor with band gap of ~2.1eV is chosen. Recent report shows cobalt oxide coupled with TiO2 exhibit could enhance the photo oxidation activity under visible light illumination.2 CoOx/TiO2 nanoparticles also show great photocatalytic activity on water splitting.
Here we report the formation of CoOx/TiO2 NTs hetero coupling by atomic layer deposition (ALD). ALD is ultrathin film deposition technique to have sub-nanometer control of film thickness. As a promising method to passivate and modify photoanode,3 ALD could form chemical bonds on substrate and operate at a relatively low temperature. We will show that by uniformly depositing a layer of cobalt oxide film onto the TiO2 nanotubes, CoOx/TiO2 NTs system exhibits one fold improvement on photocurrent response under visible light illumination compared with pristine TiO2 NTs, and about two times the efficiency of CoOx/TiO2 synthesized via wet-chemistry method. The structure was detailed studied and optimized, and mechanism will also be discussed.
References:
1. S. Kurian, H. Seo and H. Jeon, The Journal of Physical Chemistry C, 2013, 117, 16811-16819.
2. T. Q. Ngo, A. Posadas, H. Seo, S. Hoang, M. D. McDaniel, D. Utess, D. H. Triyoso, C. B. Mullins, A. A. Demkov and J. G. Ekerdt, Journal of Applied Physics, 2013, 114, 084901-084908.
3. S. C. Riha, B. M. Klahr, E. C. Tyo, S. Seifert, S. Vajda, M. J. Pellin, T. W. Hamann and A. B. F. Martinson, Acs Nano, 2013, 7, 2396-2405.
R&D Overview of 3D Integration Technology Using TSV in Japan
Authors: Kada Morihiro 
Published: February 2020

The electronic industry which towed Japanese industry is making a desperate effort for the second prosperity. The past several years a decline of Japanese electronic industry, especially semiconductor industry is severe and must come back again.
3D Integration Technology using Thorough Si Via (TSV) is expected as the engine for strengthening of global competitiveness. This technology, as a core technology of More than Moore, that importance has been recognized and development has been performed all over the world. However, full-scale volume production is not started yet, since killer applications which can accept the higher cost are not found. But the adoption to High band memory such as HMC, HBM, Wide/IO SDR, NAND memory, FPGA products, Logic+ Memory, CIS and so on including 3D and 2.5D will be expected in the near future.
In this presentation, the history of R&D of 3D Integration Technology using TSV in the world and the latest R&D are overviewed. Then, R&D results of Japanese national R&D project "Development on Functionally Innovative 3D-Integrated Circuit (Dream Chip)” which had been conducted through FY2008 to FY2012 is introduced. These consisted of six following subjects which lead to volume production were developed.
-Thermal Management & Chip Stacking Technology
-Thin Wafer Technology
-Ultra-wide Bus SiP 3D Integration Technology
-Digital-Analog 3D Integration Technology Heterogeneous 3D Integration Technology
-3D-Integration Basic Technology
Moreover, is explained the outline of "Next Generation Smart Device Project" newly started by the schedule of from FY2013 to FY2017. These are development of the key device of the system for grasping the circumference information on a car and realizing safe driving support.
-In-vehicle obstacle sensing device
-Obstacle detection and a risk cognition application-processor
Electrodeposited Copper Wire for Transparent Conductive Film
Authors: Kondo Kazuo , Ikeda Yuichi , Yokoi Masayuki , Okamoto Naoki , Saito Takeyasu 
Published: February 2020

Introduction

ITO(indium tin oxide) is the most common transparent conductive film used for touch panel and solar cell. However, the Indium is the rare metal and sputtering tool is expensive. Hence there are drastic demands for the ITO substitutes.
Silver nano-wire is a good candidate for the ITO substitute(1), however, cost is 60 times expensive than copper. Furthermore, the resistivity of copper is almost same as silver. Most conventional copper wire is produced by etching of photo lithographed copper foil(2), however, etching consumes most of the copper area, since we need high transparent film.
By using the chromium electrodeposited mold, the copper electrodeposits preferentially into the mold cracks and forms copper wire. Hence, the copper wires have been electrodeposited into the mold cracks and their characteristics as the transparent conductive film have been measured.

2.Experimantal

The electrodeposits substrate is SUS 304. The chromium mold has been electrodeposited onto this SUS 304 with Sargent bath at 600mA/cm2 for 72min. Then annealed at 150℃ for 5hours. The copper wire has been electrodeposited preferentially into the chromium mold crack. The bath consist of 25g/l of H2SO4, 200g/l of CuSO4・5H2O and the additive. The current density is 10 to 50mA/cm2with 5 to 150s at room temperature.
The openings of copper wire(=Transparency) has been measured on the chromium mold. The wire width, wire resistance and transmittance have been measured by removing the copper wire from the chromium mold. Chromium etching solution has been used to remove the copper wire.

3.Results

1.Figue 1 shows the top view of copper wire and chromium mold. Numerous numbers of copper wires are running along the chromium mold cracks.
2.For the copper wire of 30second electrodeposition time, the wire resistance is 0.18Ω/□ , wire width is 9.8μm and the transmittance is 84%. These wire resistance, width and transmittance satisfy the requirements for the transparent conductive film.
3.Figure 2 shows the photo of display with the copper wire has been placed on the LCD. Our copper wire have enough transmittance
References

http://www.cambrios.com/technology

http://panasonic.co.jp/news/topics/2013/112371.html

Nikkei Electronics,7-22,P14(2013)
Cu Displacement Plating on Electroless Plated CoWB Layer on SiO2 and Its Adhesion Property
Authors: Ohta Kohei , Inoue Fumihiro , Shimizu Tomohiro , Shingubara Shoso 
Published: February 2020

Fabrication of TSV is one of key technology for 3D-ICs. For realizing conformal barrier layers against Cu diffusion with a low temperature process is important to achieve highly reliable TSVs. Electroless plated metals such as CoW-alloy and NiW-alloy are widely studied as a capping layer on Cu, and they are also considered to have a high potential as a barrier layer.
We succeeded in conformal electroless plating of CoWB on SiO2, using DMAB as a reducing agent after forming self-assembled monolayer (SAM) of silane coupling agent on SiO2 [1-3], assisted with Pd nanoparticle catalyst. Electroless Cu plating on CoWB using reducing agent showed insufficient adhesion strength. The adhesion strength of CoWB decreased with an increase in film thickness [1], which might be due to an increase of film stress with increasing film stress. In this study, we tried to form electroless Cu seed layer by displacement plating without reducing agent, and investigated improvement of adhesion property.
The Cu plating bath composed of sulfuric acid and copper sulfate , and its pH were varied between 1.5 to 3.5. Fig.1 shows cross-sectional SEM view after the Cu displacement plating in the case of pH 2.5 on CoWB film. Initially CoWB thickness was 70 nm (Fig.1-a), and 60 nm Cu layer was formed on the CoWB, while the thickness was decreased to 25 nm due to replacement reaction. Oxidation of Co atoms and reduction of Cu ions occurred concomitantly by displacement plating.
The adhesion strength were evaluated by a stud-pull test. Table 1 shows the adhesion strengths of various films such as CoWB (70nm), displacement plated Cu/CoWB, electroless Cu plated with reducing agent on CoWB. The adhesion strength of the 70 nm CoWB film was 20MPa. That of displacement plated Cu/CoWB was 50 MPa. The adhesion strength of electroless plated Cu reducing agent was very poor. We were able to get enough adhesion strength with displacement plating.
We are going to examine Cu displacement plating of various pH conditions. Furthermore, application of this process to TSV structure is in progress.

References

[1] F. Inoue, T. Shimizu, H. Miyake, R. Arima,T. Ito, H.Seki,Y. Shinozaki, T. Yamamoto, and S.Shingubara, Microelectronic Engineering, 106(2013) 164–167.
[2] F.Inoue, T.Shimizu, T. Yokoyama, H. Miyake, K. Kondo, T. Saito, T. Hayashi, S. Tanaka, T. Terui and S. Shingubara, Electrochimica Acta, 56-17 ,6245-6250, (2011).
[3]W. J. Dressick, C. D. Dukey, J. H. Georger. Jr, G. S. Carabrese, and J. M. Calvert, J Electrochem. Soc., 141 (1) 210 (1994)
Enhancement of Bonding Strength for Low Temperature Si3N4/Si3N4 Direct Wafer Bonding by Nitrogen-Plasma Activation and Hydrofluoric Pre-dip
Authors: Lo F. -S. , Chiang C. -C. , Li C. , Lee T. -H. 
Published: February 2020

Applying the hydrofluoric (HF) pre-dip treatment on the surfaces of one pair of bare silicon wafers before performing plasma-activation wafer bonding approach, the annealing temperature for achieving silicon fracture bonding strength can be drastically reduced as low as 75°C. In comparison, the annealing temperature is 700°C or higher in the case of a conventional HF-dip hydrophobic wafer bonding or 300-400°C through the assistance of hydrogen trapping defective surface layer caused by boron ion implantation.
Applying the same bonding approach to the Si3N4/Si3N4 wafer bonding, we found the bonding strength reaches the level of silicon fracture through a 200°C annealing less than 24 hours compared with 400 hours done by HF-dip only. The bonding mechanism is proposed as following: the HF-dip treatment passivated the Si dangling bonds on the Si surface or the broken Si-N network of the Si3N4 surface to form sufficient high density of Si-H bonds. And then the application of N2 plasma treatment increases the density of Si-H-N bonds for forming hydrogen bonds which bridges the two bonding surfaces resulting in high bonding strength after annealing.
Formic Acid Treatment with Pt Catalyst for Cu Direct Bonding at Low Temperature
Authors: Suga Tadatomo 
Published: February 2020

The paper describes a new process of Cu-Cu direct bonding at a temperature lower than 200ºC in atmospheric pressure. The method consists of reduction process of Cu oxide using formic acid treatment and subsequent generation of Cu nano-particles by means of Pt catalyst. The main idea of the proposed method is that due to Pt catalytic effect, combined to the conventional formic acid treatment, a part of the formic acid is decomposed to generate hydrogen radicals to reduce the oxide of the Cu surface, CuO and produce Cu formats very effectively. As the result, nano-particles of Cu are precipitated from the formats on the Cu surface and a tight bonded interface can be formed at a temperature below a 200ºC. Cu surface was heated in water vapor to enhance the oxidation process and compared regarding to the precipitation of the Cu nano-particles.
The mechanism of precipitation of Cu nano-particles and Cu direct bonding at low temperature using formic acid treatment was investigated. It was assumed that the top of the oxide layer of Cu surface, probably CuO, is reduced effectively by H radicals which are generated from formic acid by means of Pt catalyst. The surface layer of Cu after the reduction, probably Cu2O, is reduced subsequently by formic acid, leading to precipitation of Cu nano-particles according the conditions of the heat treatment and the formic acid treatment. It was shown also that the precipitation of Cu nano-particles may contribute the direct bonding of Cu surfaces at low temperature.
Fast and Accurate in-Line Monitor of Boron Implantation Energy and Dose by Spectroscopic Ellipsometry
Authors: Wen Tsai-Yu , Lu Tsuo-Wen , Wang Yu-Ren , Lin Chin-Fu , Wu J Y , Chang Shao-Ju , Chiu Sheng-Min , Huang Chien-Jen , Cheng Chao-Yu , Cheng Juli , Raphael Getin , Jiang Zhiming , Tan Zhengquan 
Published: February 2020

Ion implantation is a key process for front end of line semiconductor manufacturing and directly correlates to device performance. Inability to rework mandates precise control. As of today, there is still limited production worthy solution for in-line boron implanted energy and dose monitor on product wafer. This paper describes a fast and accurate in-line method for monitoring Boron (B) implantation energy and dose measurement, simultaneously, in a production environment using spectroscopic ellipsometry (SE) after the source-drain PMOS implant process step. The implanted species damage the silicon substrate lattice, producing amorphous-Si like characteristics and a different refractive and absorption indexes compared to crystalline silicon substrate. Furthermore, the damaged depth is a function of implant energy. SE spectra are very sensitive to measure the optical properties variation of these materials (Figure 1).
In this work, a single look-up optical model is created to monitor the damaged layer. The look-up components relate to implanted dose behavior, the thickness of the damage layer to the implanted depth (energy) behavior.
Secondary Ion Mass Spectrometer (SIMS) is used as a reference tool. Excellent correlation (R2> 0.99) can be achieved between SE results and SIMS (Figure 2). The damaged layer thickness correlates to SIMS depth (Rp); and the look-up model components correlate to SIMS dose.
Q-time limitation must be considered to achieve stable implantation monitoring before annealing. The implanted surface is unstable and damaged depth and implanted dose decay rapidly within a few hours. Q-time correlation formula is used to compensate the implanted decay behavior (Figure 3).
As a result, 1.64% depth and 0.43% dose range variation can be achieved after Q-time correlation is applied. This research also shows that SE metrology is sensitive to other species used for source-drain implantation and can be extended to control NMOS implant process using Arsenic (As) species.
(Invited) Si Waveguide-Integrated High-Speed Ge Photodetector
Authors: Fujikata Junichi , Miura Makoto , Noguchi Masataka , Arakawa Yasuhiko 
Published: February 2020

Silicon photonics has recently become a subject of intense interest because it offers an opportunity for low cost, low power consumption, and high bandwidth of optoelectronic solutions for applications ranging from telecommunications down to chip-to-chip interconnects. By the integration of germanium into silicon photonics circuit, very efficient photodetection has been demonstrated for the past several years. However, higher performance with low drive voltage and small footprint has not been achieved.
In this paper, we present a Si waveguide (WG)-integrated PIN-type Ge-PD (photodetector), which shows high speed of 50 GHz bandwidth with small footprint. We also compare Si waveguide-integrated PIN and Schottky Ge PDs, which showed very low dark current density with high efficiency.
We fabricated two types of PIN Ge-PDs, which were evanescently coupled and butt-joint coupled with the Si WGs. The optimized evanescently coupling type of a PIN Ge-PD showed good photoresponsivity of 0.8 to 1.0 A/W and low dark current density of 0.6 nA/um2. It showed 50 GHz bandwidth at Vdc more than 3 V, and 30 GHz at 0 Vdc in case of 10 um optical coupling length. Furthermore, we developed a butt-joint type PIN Ge-PD and achieved 46 GHz bandwidth and high-efficiency with only 5 um optical coupling length.
We also studied PIN and Schottky type Ge PDs. Both PIN and Schottky type Ge PDs showed good photoresponsivity of about 1.0A/W, and a low enough dark current density of 0.4 nA/um2 for the PIN Ge PD and 0.8 nA/mm2 for the Schottky Ge PD. The frequency of the 3 dB bandwidth was 40 GHz for the PIN Ge PD and 30 GHz for the Schottky Ge PD in case of 1 um-thick Ge layer. At lower dc bias voltage (Vdc), a much larger bandwidth was obtained for the PIN Ge PD. From the equivalent circuit model fitting, the Schottky Ge PD showed much larger capacitance around the zero bias voltage.
The PIN Ge PD showed a larger bandwidth with decreasing Ge thickness. About 50 GHz bandwidth was obtained with a voltage more than 3 Vdc, and at even zero bias, 30 GHz bandwidth was obtained.
Finally, we studied a PIN Ge PD with a small footprint and low consumption CMOS TIA circuit. To achieve a smaller footprint and larger impedance gain, we used an inverter-type TIA circuit. We demonstrated large sensitivity and high-speed response of 12.5 Gbps.
Virtual Substrate Technology for Ge1-XSnX Heteroepitaxy on Si Substrates
Authors: Kostecki Konrad , Oehme Michael , Koerner Roman , Widmann Daniel , Gollhofer Martin , Bechler Stefan , Mussler Gregor , Buca Dan , Kasper Erich , Schulze Joerg 
Published: February 2020

The fabrication of GeSn layers is one of the worldwide current areas of research in material science. The driving force behind it, is the possibility to realize a group IV direct bandgap semiconductor. Theoretical calculations show values between 10 % for relaxed GeSn crystals and 6 % for tensile-strained GeSn crystals. However, only its synthesis on Si substrates is of interest for the photonic components applications. For the manufacture of GeSn based components on Si substrates, a specific Ge VS (virtual substrate) has to be first realized in order to overcome the large lattice mismatch (≥ 4.2 %). This method has been developed by Kasper et al. for SiGe heterostructures on Si and its here used to provide, without epitaxial break, the desired lattice constant for the grow of Sn based alloys. The use of such VS minimize the number of the threading dislocations as required for high performance optical devices.
The significant progress made in recent years allowed the demonstration of GeSn based electro-optical components integrated on Si.
A compressively strained heterostructure can by relaxed by various methods. These are, for example, special annealing steps, increasing the layer thickness over the critical thickness tcrit or by means of point defects introduced during low temperature growth. If a Ge or GeSn film is deposited directly on Si it relaxes very quickly since the critical thickness is only a few nanometer thick. At the same time the threading dislocation density is extremely high. An alternative is an ultra-thin Ge VS developed in the last few years. The threading dislocation density is significantly reduced by high temperature annealing steps close to the melting point of Ge. This technology is used here as a basis for GeSn structure growth.
The optical properties of the GeSn layers with 2 % and 4 % Sn content are addressed via pin photodetectors fabrication (see Fig. 1). As a reference the GeSn pin detectors were manufactured without VS directly on Si. An overview of the layer structures are shown in figure 2.
The strain statuses of the individual samples were analyzed by RSM (reciprocal space mapping). These show that the samples on Si are 100 % strain relaxed and the samples on Ge VS are still under 50 % rest compressive strain.
The dark current of the individual samples are shown in the figure 3. The GeSn samples grown directly on Si show a much higher dark current due to the significantly higher threading dislocation densities compared to the samples on Ge-VS. At a bias of -1 V, the dark current is increased by more than one order of magnitude. In Figure 4, the optical responsivity of each sample is shown as a function of wavelength.
Phonon Transport and Scattering in Rough and Porous Silicon Nanowires
Authors: Glynn Colm , Jones Kim , McSweeney William , Lotty Olan , Geaney Hugh , Sotomayor Torres Clivia M , Holmes Justin D , O'Dwyer Colm 
Published: February 2020

Silicon nanostructures and methods to grow them and influence their structure and morphology has recently been demonstrated to offering a useful strategy to control thermal conductivity and light-matter interactions. The transport and scattering of phonons in Si has demonstrated effective thermoelectric performance largely due to effects caused by surface roughening and nanoscale irregularities in the crystal structure that contribute to diffuse boundary scattering mechanisms. When confinement effects are introduced in crystalline materials the electron and phonon transport can be significantly due to three discrete effects: increased boundary scattering, changes in phonon dispersion, and quantization of phonon transport. Using both room-temperature and in-situ thermal Raman scattering spectroscopy the transport of phonons within Si and its nanostructures can be probed quickly and with little sample preparation. Both ambient and high temperature characteristics of the Si are examined and phonon transport changes between the b-Si and the SiNWs can be linked to scattering effects due to the different morphologies possible using metal-assisted chemical etching to form NWs with tunable porosity and surface roughness. This work demonstrates that by increasing the number of available scattering sites in nanostructured Si within the structure (not just boundary scattering at rough surfaces), the role of four phonon processes on the phonon transport within Si can be optimised. This study is important for providing information on the phonon transport within Si and its nanostructures allowing morphologies that affect phonon transport to be exploited for engineering the thermoelectric properties of future Si devices.
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