bluuebunny/crossref_metadata_2025_split huggingface dataset:
Failure Analysis of the Die-Attach in a Metal-Type Package
Authors: Acki J. , Murakami A. , Akutsu T. , Matsuda S. , Maruyama A. , Iwamoto T. , Kirihata H. 
Published: December 2020

Abstract
RECENTLY POWER MOSFETS have been used for satellite power supplies. NASDA has developed such a Power MOSFET for the space projects. It has a metal-type package, and the die is attached by Au-Si alloy to achieve high temperature operation (Tj=200°C). The fabricated device failure was detected thermal resistance tests after high temperature storage test at 200°C for 1000 hours. This failure is caused by the die peeling between the Au-Si eutectic alloy layer and the Ni plating surface on the Cu-W substrate. In this paper, we describe the failure mechanism and improvements in the package design and fabrication process. The newly developed power MOSFET for space use exhibits good performance in the high temperature storage test.
A CAD-Based Approach to Failure Diagnosis of CMOSLSI with Single Fault Using Abnormal IDDQ
Authors: Sanada M. 
Published: December 2020

Abstract
A CAD-based fault diagnosis technique for CMOS-LSI with single fault using abnormal IDDQ has been developed to indicate the presence of physical damage in a circuit. This method of progressively reducingthe faulty portion, works by extracting the inner logic state of each block from logic simulation, and by deriving test vector numbers with abnormal IDDQ. To easily perform fault diagnosis, the hierarchical circuit structure is divided into primitive blocks including simple logic gates. The diagnosis technique employs the comparative operation of each primitive block to determine whether one and the same inner logic state with abnormal IDDQ exists in the inner logic state with normal IDDQ or not. The former block is regarded as normal block and the latter block is regarded as faulty block. The fault of the faulty block can be localized easily by using input logic state simulation. Experimental results on real faulty LSI with 100k gates demonstrated rapid diagnosis times of within ten hours ani reliable extraction of the fault location.
Test and Failure Analysis Implications of a Novel Inter-Bit Dependency in a Non-Volatile Memory
Authors: Boyne D. , Goertz J. , Parsons D. 
Published: December 2020

Abstract
Failure analysis of non-volatile memory arrays can be complicated by the history of bits elsewhere in the array. This generally is in contrast to volatile memories, in which the state of all bits can quickly be reset by over-writing the bits, or by simply removing power from the array. On one of our products, EEPROM bits failed to program if certain patterns of bits were programmed elsewhere in the EEPROM array. During programming, high voltages (&gt;18 volts) are present within the EEPROM array. Such voltage levels caused a narrow field oxide region to break down, thereby pulling down the programming voltage and preventing the successful programming of EEPROM transistors. What complicated the analysis, however, was that the breakdown only occurs if a checkerboard pattern is being programmed in one part of the array, while specific other EEPROM bits had previously been programmed elsewhere in the array. Until the failure mechanism was well understood, electrical screens were difficult to implement, because they typically do not account for complicated interactions between bits. This is especially true for nonvolatile memories, for which test time costs often prohibit the use of complicated test patterns with improved test coverage. This paper reviews the failure analysis, and proceeds to highlight the importance of knowing the contents of nonvolatile arrays prior to performing either failure analysis or automated testing on such an array. The case study therefore applies to both test and failure analysis engineers.
Thermal and Optical Enhancements to Liquid Crystal Hot Spot Detection Methods
Authors: Ferrier S. 
Published: December 2020

Abstract
Three enhancements to Liquid Crystal hot spot detection improve thermal and optical sensitivity while substantially maintaining simplicity, safety and relative low cost. These enhancements have permitted detection of hot spots unidentifiable by traditional LC methods. Details, capabilities and limitations of the enhancements are discussed, results of rudimentary defect thermal modeling are presented, and an improved metric for evaluating LC technique sensitivity is proposed.
The Identification of Thermal Fatigue Testing Method of Soldered Joints for Space Use
Authors: Yonemaru M. , Shimizu A. , Matsuda S. , Seo I. 
Published: December 2020

Abstract
Electronic devices have been used under various thermal conditions in space applications. The temperature range often exceeds 100°C, and the electronic devices are stressed by both high and low temperatures and thermal cycles. Since repairing and reworking of the spacecraft electronic hardware cannot be performed after launch, verifying the reliability of the hardware on the ground before the launch is essential. The thermal stresses to the electronic devices' soldered joints have recently tended to increase because the devices must be made smaller and lighter. The thermal fatigue of the soldered joints must be addressed in order to achieve highly reliable flight hardware. We studied a test method to estimate the thermal fatigue life of soldered joints for space use. This paper examines the thermal fatigue life using two kinds of test methods as heat-resistant evaluation tests of soldered joints for space use, and evaluates the effect of the test parameters on the thermal fatigue life of soldered joints. We conclude that the thermal fatigue life of soldered joints cannot be estimated accurately, if the test parameters are instituted uniformly.
Failure Analysis for Micro-Electrical-Mechanical Systems (MEMS)
Authors: Peterson K. A. , Tangyunyong P. , Barton D. L. 
Published: December 2020

Abstract
Micro-Electrical Mechanical Systems (MEMS) is an emerging technology with demonstrated potential for a wide range of applications including sensors and actuators for medical, industrial, consumer, military, automotive and instrumentation products. Failure analysis (FA) of MEMS is critically needed for the successful design, fabrication, performance analysis and reliability assurance of this new technology. Many devices have been examined using techniques developed for integrated circuit analysis, including optical inspection, scanning laser microscopy (SLM), scanning electron microscopy (SEM), focused ion beam (FIB) techniques, atomic force microscopy (AFM), infrared (lR) microscopy, light emission (LE) microscopy, acoustic microscopy and acoustic emission analysis. For example, the FIB was used to microsection microengines that developed poor performance characteristics. Subsequent SEM analysis clearly demonstrated the absence of wear on gear, hub, and pin joint bearing surfaces, contrary to expectations. Another example involved the use of infrared microscopy for thermal analysis of operating microengines. Hot spots were located, which did not involve the gear or hub, but indicated contact between comb structures which drive microengines. Voltage contrast imaging proved useful on static and operating MEMS in both the SEM and the FIB and identified electrostatic clamping as a potentially significant contributor to failure mechanisms in microengines. This work describes MEMS devices, FA techniques, failure modes, and examples of FA of MEMS.
Interpretation of Sudden Failures in Pump Laser Diodes
Authors: Bonfiglió A. , Vanzi M. , Casu M. B. , Magistrali F. , Maini M. , Salmini G. 
Published: December 2020

Abstract
The occurrence of sudden failures has been reported for 980 nm SL SQW InGaAs pump lasers. The post-mortem analysis reveals failure modes that are consistent with the formation of defects at the active area. The problem calls for two separate efforts: monitoring the degradation at suitable time resolution and structural characterization of defects. This article reports about the optical power and overall voltage monitoring results during a constant current lifetest, in which "sudden failures" switched off the lasers in a few hours, after 1500 hours of regular life, and about their interpretation based on TEM cross-sectional images across an EBIC-detected high recombination site. The hypothesis that Recombination Enhanced Defect Reaction (REDR) is a suitable mechanism for defect growth in forward biased GaAs-based diodes is proposed and discussed that REDR is the origin of the observed sudden failures, starting from native defects located in "cool" regions.
Laser Microchemical Technology: New Tools for Flip-Chip Debug and Failure Analysis
Authors: Silverman S. , Aucoin R. , Mallatt J. , Ehrlich D. 
Published: December 2020

Abstract
Laser microchemical (LMC) technology has become an important element of the FIA and debug tool set by supplying key steps not well addressed by previous tools. In this paper we report the optimization of the LMC technology to solve key issues for flip chip FIA. Specific processes have been developed for localized thinning of flip chips, in order to enable access of conventional FIA tools. Additional applications include dramatic enhancement of focused ion beam (FIB) rework and 3-D micromachining for prototyping, in-situ trimming, and mastering of microelectromechanical systems (MEMS). Laser etching of silicon is with a high pressure chlorine assist and is l000X the rate of the fastest focused ion beam methods. In contrast to grinding methods, the process introduces no process stress or contamination and retains an average surface roughness of several hundred angstroms. Micronthickness metal lines are laid down in a one-step vapor phase deposition at 200 μm/s writing speed. Rapid deposition combined with the superior quality of the laser interconnect, translates into writing with a conductance per unit writing time of 1000 to 10,000 times the rate of a focused ion beam.
Automatic Fault Tracing Using an E-Beam Tester with Reference to a Good Sample
Authors: Wada S.-I. , Nakamura T. 
Published: December 2020

Abstract
Locating fault origins of defective logic LSls requires expensive equipment, such as electron beam testers and LSI testers. In order to maximize the utilization of such equipment in achieving high fault analysis throughput as well as to save manpower, the authors are developing an automatic fault tracing system which locates the fault origin overnight without human assistance through control of an electron beam tester and an LSI tester. The system traces backwards via the fault propagation path and locates the fault origin by comparing the behavior of a faulty LSI sample with that of a good LSI sample. Sample exchange in a vacuum chamber is achieved through a dual chip loading mechanism. After initial setting, fault location is accomplished without human assistance by fully automated operations, such as fine tuning SEM images of LSI surfaces, aligning points by robust pattern matching between SEM images and layout data, acquiring voltage contrast images with high contrasts and judging logical voltage levels from the images. A prototype version of this system successfully backtraced to the fault origin of an LSI with 20 k gates in 8 hours.
Failure Isolation of Mobile Ions Using Secondary Ion Mass Spectroscopy
Authors: John R. 
Published: December 2020

Abstract
Secondary Ion Mass Spectroscopy (SIMS) can be applied to all elements, and it facilitates the quantitative analysis of solid surfaces, including monolayers. The method is widely used in studies of adsorption, oxidation, corrosion, catalysis, diffusion and in characterization of thin films and coatings. [1] This technique can very well be applied in semiconductor failure analysis for not only detecting the source of failure, but also isolating the failure to a particular location, which is very important for corrective action procedures. SIMS analysis was performed on a CMOS VLSI sample with suspected mobile ionic problem, and it proved to be very effective in providing details of the specific mobile ionic elements involved, source of contamination, and resident location of the mobile ions.
Spin-On-Glass (SOG) Contamination Causing Single Via Failure
Authors: Isakanian P. , Hunjan S. 
Published: December 2020

Abstract
Several device failures were experienced after they went through the board assembly process. The failure caused severe transmit pulse attenuation from circuit block called AUI (Attachment Unit Interface). The AUI serves as a medium independent communication port in Local Area Networks. After careful observation and a series of Failure Analysis processes, the malfunction, which caused severe transmit pulse attenuation was attributed to a defective metal 1 to metal 2 via. The via in question is a tie between a pair of cascoded PMOS transistors in the analog section of the chip. These transistors serve as the main biasing leg for the AUI current sink. Since the via in question was bake recoverable at temperatures as low as 175°C for 20 minutes but would show the same failure signature when operated under temperature, the exact failure location was difficult to pinpoint. After a lengthy analysis procedure, the malfunction was attributed to contamination due to Spin On Glass (SOG) outgassing.
Use of Failure Analysis Techniques to Optimize the Passivation Process for a TLM 0.35 µm Process
Authors: Bothra S. , Sur H. , Brugge H. , Pramanik D. 
Published: December 2020

Abstract
Optimization of the passivation scheme for a 0.35 μm TLM process is presented. The passivation layer is required to provide mechanical and chemical protection during the assembly and packaging process and long term environmental protection. The passivation scheme was optimized by testing a product-like test vehicle at accelerated environmental stress conditions of high humidity and high temperature. The initial passivation scheme showed a unique electrical test signature - a voltage dependent failure with open circuit at low voltage/pass at high voltage. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the failure site. Further cross-section analysis revealed that the failure site was a fracture across a via and adjoining IMO. This cracking was attributed to stress corrosion fracture of the IMO based on root cause analysis. This hypothesis required a path for moisture to the stressed IMO-2 location to cause the fracture. The moisture path was identified by further analysis and process changes to eliminate this were implemented. All subsequent parts passed the accelerated environmental tests confirming the stress corrosion fracture hypothesis.
Focused Ion Beam Application in Solving RFIC Oscillation Problem
Authors: Zhao S.P. , Ma H.N. , Fang S.J. , Goh G.P. , Wang J. 
Published: December 2020

Abstract
Focused Ion Beam (FIB) technique has been widely used to directly modify device functionality by adding ion-induced conductive lines and cutting signal traces with chemical enhance etching. However, in this work, FIB technique is employed to add a 15 ohm resistor to a RF circuit to solve its oscillation problem. After the modification, the oscillation problem is solved and the performance of the RF device is improved significantly. The successful FIB application of adding a defined resistor to modify a circuit is reported in this paper for the first time.
Preliminary Study of Alternative Material Development of Ballistic Attributes
Authors: Kim Dal Sun , Nemat-Nasser Sia. , Seon Kim Yun 
Published: December 2020

Abstract
The purpose of this research is to examine the performance of tungsten heavy alloy (WHA) susceptible to adiabatic shear failures and to identify the microscopic findings of shear band and its effect on the engineering behavior. Experimental results show that the binder-phase (Fe-Ni) and tungsten particles (W) have the high work-hardening rate at low-strain-rate compression (10-3/sec). Thermal softening behavior is dominant at high-strain-rate (&gt;103/sec), and this material is relatively insensitive to strain rate in the range of 3000-5000/sec. The microscopic analysis by SEM reveals that most fractures in the shear band are intergranular where the Fe-Ni matrix has the least resistance to fracture. Transgranular fracture is also observed, but not significantly. With the constant strain rate, no shear band was observed under 30% compressive strain, whereas the extensive shear band was formed at the 50% strain with significant crack formation along the shear band zone and extends through the specimen thickness forming a cone shape inclined at an angle 40° to 50° to the loading direction. The measured surface temperature of the 40%-strained specimen is approximately 250 °C using high speed infrared temperature technique. A significant decrease in the ultrasonic velocities is measured with extension of the shear band.
Effects of Prior Processing on the Performance of PH 13-8 Mo Stainless Steel
Authors: Pepi Marc S. , Grendahl Scott M. 
Published: December 2020

Abstract
This article deals with an investigation to determine the root cause of the differences noted in the fatigue test data of main rotor spindle assembly retaining rods fabricated from three different materials. The US Army Research Laboratory - Materials Directorate (ARL) subjected the failed tie rods to visual examination and light optical microscopy and then performed dimensional verification and measured the respective surface roughness of the rods in an effort to identify any discrepancies. Next, mechanical testing (hardness, fatigue, and tensile) was performed, followed by metallography, and chemical analysis. Finally, the ARL performed laboratory heat treatments at the required aging temperature. The results suggested that the difference in performance could not be directly linked to chemical composition, dimensional intolerance, surface roughness or any metallographic variance and that the likely explanation for the difference observed in the mechanical performance of materials lies within a variation of the heat treatment.
In-Situ Electrical Monitoring and Contactless Measurement Techniques for Enhanced FIB Modifications
Authors: Desplats Romain , Benbrik Jamel , Perdu Philippe , Benteo Bruno , Marc François , Danto Yves 
Published: December 2020

Abstract
Recent planar technologies with 3 metal layers or more challenge current physical design modification capacities using Focused Ion Beam tools. Image visibility on the FIB is drastically reduced, making accurate positioning and milling operations in the area of interest more difficult, and the use of power planes increases the risk of short circuits while accessing inferior metal lines. Despite the complexity of FIB modifications, however, the demand for circuit modifications continues to increase. To respond to this demand for successful, time efficient, FIB modifications, step by step monitoring of operations is imperative. In this paper, we will present an innovative method which brings in-situ electrical monitoring and contactless measurement capabilities to FIB systems. Electrical connection of the circuit inside the vacuum FIB chamber is done using a commercial load module and logic waveform acquisition with the FIB is obtained without modifying FIB hardware using a voltage contrast approach. With this method, it is possible to verify the completion of FIB milling and depositing operations by temporarily suspending FIB action so that a test pattern can be run allowing electrical testing and measurements of the circuit without damaging it.
Graphical Representation of Permanent Defects in Hard Disk Drives
Authors: Mohr Josef , Agness John 
Published: December 2020

Abstract
This paper discusses the utilization of a specifically designed magnetic media defect plotting utility. This utility provides the analyst with the ability to view the physical locations of data errors on the disk drive and identify damage to magnetic media. With the failure signature understood, the analyst can now go on to isolate the underlying failure mechanism, without electrical analysis. Further, with the failure mechanism identified critical feedback can be provided to appropriate engineering areas so that the cause of failure can be limited at its source.
Evaluation of the Resistance of Individual Si Die to Cracking
Authors: Berriche R. , Lowry R.K. , Rosenfield M.I. 
Published: December 2020

Abstract
The present work investigated the use of the Vickers micro-hardness test method to determine the resistance of individual die to cracking. The results are used as an indicator of resistance to failure under the thermal and mechanical stresses of packaging and subsequent thermal cycling. Indentation measurements on die back surfaces are used to determine how changes in wafer backside processing conditions affect cracks that form around impressions produced at different loads. Test methodology and results obtained at different processing conditions are discussed.
Electromigration in Gold Line of GaAs IC
Authors: Ohta A. , Yajima K. , Higashisaka N. , Heima T. , Hisaka T. , Tanino N. 
Published: December 2020

Abstract
This paper describes voids in a gold line, which is a new failure mechanisms of GaAs IC using gold line as interconnection. We have found voids in both first and second metal under DC bias test, current density of 0.67 to 1.27 106 A/cm2 in high temperature range of 230 °C to 260 °C. We have observed carefully the movement of voids during the test and found that voids moved toward a cathode, in the opposite direction of electron flow. The velocity of voids increased with the current density almost proportionally. The moving mechanisms of a void can be explained by assuming that gold atoms move toward an anode by electromigration. The activation energy of the void velocity was 0.84 eV at the cathode side. This was nearly equal to 0.6 eV - 0.9 eV reported on the velocity of the gold island on molybdenum surfaces [1]. The GaAs IC failed at the almost same time as the voids appeared. The activation energy of mean time to failure of the IC was 0.89 eV, which was nearly equal to that of the void velocity at the cathode edge of 0.84 eV.
Simple Flip Chip Analysis Strategies
Authors: Tubbs Richard L. 
Published: December 2020

Abstract
Recent customer demands and advances in technology are expanding the use of flip chip ICs. The higher coefficients of thermal expansion differences and fragile nature of assemblies have made underfilling mandatory for product survival in the field. This article describes a few techniques employed for failure analysis of these complex devices: epoxy development, substrate pre-encapsulation, universal polishing media, cyanoacrylate use, substrate analysis, plan view sectioning/inspection, die backside polishing for infra-red inspection, and chemical deprocessing. Almost all of the techniques presented will involve traditional cross sectioning tools which can be applied to flip chips. These techniques include improvements to the traditional material analysis cross section as well as aids for die level electrical analysis and visual inspection methods. The article demonstrates that with the use of the described techniques, and literally no investment, any lab which can presently perform semiconductor related cross-sections, will be able to confidently expand into flip chips.