bluuebunny/crossref_metadata_2025_split huggingface dataset:
Wafer Conserving Full Range Construction Analysis for IC Fabrication and Process Development Based on FIB/Dual Beam Inline Application
Authors: Weiland R. , Boit C. , Ebersberger B. , Meis P. , Dawes N. , Dziesiaty A. , Zimmermann H. , Demm E. , Hirsch A. , Frey L. , Lehrer C. , Geyer S. , Kamolz M. , Rettenmaier H. , Tittes W. , Lezec H. , Treichler R. 
Published: December 2020

Abstract
The step into the production line environment is a quantum leap for physical failure analysis (PFA) and will change its work in the near future. Wafer sacrifice for analysis becomes obsolete. The main benefits are: 1. reduction of wafer costs, 2. more splits per development lot, 3. reduced cycle time of analysis and technology development. Machines needed for that purpose are dual beam SEM/FIB tools. In the following we present solutions how PFA in a broad range can be carried out inside of a production line. The analyzed wafers can be fed back into the production flow which results in lower overall costs and the feedback loop to production engineers is dramatically shortened leading to reduced down times of production tools etc. The highest risk that has kept the majority of semiconductor manufacturers from proceeding into this direction is the contamination of the productive wafer with Ga, the FIB beam particle, that may diffuse into productive parts of the wafer during heat cycles after the analysis step. We show that the risk of contamination by Ga and other materials can be controlled.
Investigation of Substrate Dislocation Induced Bit Line Soft Failure
Authors: Lin Jian-Chang , Hsu Yung-Tsai , Huang Chih-Kuo , Tsai Wu-Chin , Chou Yung-Hua 
Published: December 2020

Abstract
In modern integrated circuits (IC) using sub-micron or deep sub-micron process rules, substrate dislocation is a common failure mechanism in SRAM or embedded SRAM products. Depending on the position of substrate dislocation in the SRAM cell, it may result in problems including junction or contact leakage, gate oxide early breakdown, low threshold voltage, and poor data retention. In this paper, we’ll focus on the test methodology and physical failure analysis to dig out the failure mechanism, substrate dislocation under SRAM pass gate and node contact. In addition, we will measure the electrical behavior of such substrate dislocation. Several FA techniques, such as Passive Voltage Contrast (PVC) [1] pad deposition by Focus Ion Beam (FIB), and electrical micro probing [2] will be used during leakage verification and measurement.
A Purpose-Driven Decision-Based Methodology for Debug and Failure Analysis
Authors: Maher Steven P. 
Published: December 2020

Abstract
There are many different discussions and perspectives on processes for product debug and failure analysis (FA) of integrated circuits [1][2][3][4], with some even minimizing the aspect of process for FA. Most attempts to-date at a process for FA have been either task-oriented or capability-oriented. In this paper, a high-level purpose-driven decision-based methodology is proposed, with goals of: 1) Establishing a high-level discussion of Debug process; 2) Initiating a high-level discussion of FA process; 3) Encouraging a broader “world view” in the context of the product life cycle; 4) Emphasizing clarity of purpose (of Debug or FA actions) - “why do we (the analysts) do what we are doing?” 5) Establishing context for synergy between Debug and FA.
Capacity Management Solutions
Authors: Drummond John , Wolfe Jeff , Smith Martin , Conner Jeff , Brawley Ken , Seefeldt Bart , Davis Cary 
Published: December 2020

Abstract
This paper will cover some of the options available to manage the failure analysis process when it is capacity constrained. This paper will provide a method to model a failure analysis operations capacity to aid in the decision process of where the constraints are. Several examples of solutions to some typical constraints will be presented also.
FIB Chip Repair: Improving Success by Controlling Beam-Induced Damage and Thermal/Mechanical Stress
Authors: Herschbein Steven , Rue Chad , Scrudato Carmelo , Hermann Edward 
Published: December 2020

Abstract
Focused Ion Beam (FIB) success has become more difficult as microchip process technology advances, requiring new techniques for damage control both during the microsurgery procedure and before the finished product can be electrically tested. Ultra thin gate dielectrics, shallower junctions, less ‘white space,’ and new materials surrounding active devices all create additional challenges for imaging, targeting, controlling instantaneous charge damage, and the removal of residual implanted charge. On the macro level, global thinning of bulk silicon housed in hybrid packages is causing new problems with thermal management and mechanical stress. Techniques and procedures used to control electrostatic discharge type damage become ever more critical when working on poorly buffered or isolated device elements, especially from the backside. Implanted gallium and residual charge perturb electrical characteristics, and must be dispersed prior to power-up thru carefully controlled bake steps. Left in place, these FIB-induced perturbations are likely to cause poor functionality or even latchup. The mechanical rigidity and thermal dissipation properties of newer, complex package types must also be restored post-FIB, otherwise cracked silicon or a thermal overload event might be the outcome. In this paper, we will attempt to address some of the common causes of FIB-induced failure on newer silicon and package technologies, and how they might be overcome. FIB techniques and preparatory processes must continue to evolve in order to deal effectively with the problems of direct beam damage, residual charge elimination, and sample stress management.
Precise Fail Site Isolation Using a Combination of Global, Software and Tester Based Isolation Techniques
Authors: Gopu Deepa , Ontko George , Phan Chin , Ramanujachar Kartik , Wills Scott , Hales Alan 
Published: December 2020

Abstract
Precise fail site isolation plays a very important role today in the world of semiconductors. Its importance increases more, as the devices are of cutting edge technology with increasing complexity and decreasing dimensions. Global fail site isolations techniques (like XIVA, Photo Emission, FMI etc) and tester based techniques (using automatic test equipment, Fastscan etc) alone, are no longer sufficient and may not be successful. Long net lists and large fail sites isolated by these methods pose problems for physical failure analysis. Planarity of these large areas during parallel lap and inspection times using the SEM is difficult and tedious, thus leading to long cycle times and low resolution rates. There exists a need for precise fail site isolation. In many cases, no single technique can be used to narrow down a fail site significantly. Instead a combination of different techniques must be used. In this paper we present a case study, where a combination of complimentary techniques are used to successfully isolate a fail area of more than 1300 microns in length to less than 100 microns on a single failing net.
Doping Mapping by SSRM–Reaching Maturity and Sub-10nm Resolution
Authors: Schömann Stephan , Álvarez David 
Published: December 2020

Abstract
For years there has been a discrepancy between the importance of complex doping implantation schemes for advanced technology device performance and the ability to accurately measure the carrier concentrations with the gap widening at each technology node. With scanning spreading resistance Microscopy (SSRM) a major step forward in terms of resolution and quantification was achieved especially since the emergence of full diamond tip manufacturability and improvements in sample preparation techniques. This article discusses the non-trivial prerequisites for this success and some examples from the failure analysis routine that show the promising capabilities of SSRM. The examples include technology monitoring and failure analysis in SOI transistors and vertical surrounded gate transistors, as well as failure analysis on yield and performance issues. SSRM has reached a development stage that allows its application as routine tool for 2D-carrier profiling.
DEI Analysis of an OTP EPROM: Dynamic Electroluminescence Imaging (DEI) Applied to an OTP EPROM Memory Device
Authors: Hulse John , Frank David J. , Simard-Normandin Martine 
Published: December 2020

Abstract
Dynamic electroluminescence imaging (DEI) is a noninvasive means of obtaining high-resolution timing information from a CMOS circuit. This article reports timing measurements made on a 512K-bit EPROM enabled by the use of optical methods alone. The equipment to observe DEI is comprised of a Karl Suss probe station equipped with a position dissecting photomultiplier tube called a MEPSICRON. To demonstrate the power of the technique a 512Kbit EPROM in ~1 micron technology was prepared for DEI Measurement. The EPROM circuitry was exposed for DEI measurement by decapsulating the part with acids. DEI images are recorded in the region of the tri-state drivers for bond pads D0 through D3 and in the region of bond pad D0. The results demonstrate timing information with up to 11 ps time resolution that is correlated with the chip circuitry. DEI has obvious applications in performance evaluation, failure analysis, intellectual property evaluation, and prototype testing.
Development of Backside Scanning Capacitance Microscopy Technique for Advanced SOI Microprocessors
Authors: Narang Vinod , Muthu P. , Chin J.M. , Lim Vanissa 
Published: December 2020

Abstract
Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.
A Technique for Reliably Preparing Full-Length Metallographic Cross-Sections of Integrated Circuit Bond Wires
Authors: Nail Carl 
Published: December 2020

Abstract
To overcome the obstacles in preparing high-precision cross-sections of 'blind' bond wires in integrated circuits, this article proposes a different technique that generates reliable, repeatable cross-sections of bond wires across most or all of their lengths, allowing unencumbered and relatively artifact-free analysis of a given bond wire. The basic method for cross-sectioning a 'blind' bond wire involves radiographic analysis of the sample and metallographic preparation of the sample to the plane of interest. This is followed by tracking the exact location of the plane on the original radiograph using a stereomicroscope and finally darkfield imaging in which the wire is clearly visible with good resolution.
Focused Ion Beam Grounding to Alleviate Sample Charging for Scanning Auger Electron Spectroscopy
Authors: Gondran Carolyn F. H. , Morales Emily 
Published: December 2020

Abstract
It is shown that a focused ion beam (FIB) grounding technique can be used to alleviate charge buildup on samples that would otherwise charge in the electron beam to the point where analysis by Auger electron spectroscopy (AES) was limited or impossible. FIB grounding alleviates the sample charging and permits AES analysis. The grounding technique is quick, easy and well understood as it has been used extensively for voltage-contrast analysis. The technique is shown to be useful for enabling analysis on electrically isolated conductive features as well as insulating samples.
Investigation on the Influence of Focused Electron Beam on Electrical Characteristics of Integrated Devices
Authors: Doering S. , Harzer R. , Werner W. 
Published: December 2020

Abstract
This paper addresses two questions related to electrical characterization of devices at the contact level in a semiconductor failure analysis: Is it possible to use scanning electron microscope/focused electron beam based probing system to do electrical characterization at device level despite the fact that there is beam induced device degradation? What are the effects to consider if a beam exposed sample has to be characterized by a nano-probing technique during the failure analysis flow? To answer these questions, an experimental setup with a drive transistor of a single port SRAM manufactured in a 90nm CMOS process was employed. Results confirmed the effect of electron beam induced alteration on integrated devices and it was shown that several parameters influence the investigated device, e.g., beam acceleration voltage and dose used for radiation. The alteration was due to trapped charge located in the gate oxide and also electrons trapped in interface states.
Photo Process Margin Leading to IC Failure – A Case Study
Authors: Chowdhury Vijay , Hsu Clement , Yu Ada 
Published: December 2020

Abstract
Inherently small process margins in patterning are a dominant cause of device yield variability, when process conditions or production lines change. This paper highlights the fact that in spite of a perfect lithographic model, the post OPC variation can be substantial due to manufacturing variability. Pattern integrity is a non-intuitive complex mix of manufacturing process practices combined with manufacturable design practices. Failure analysis is the only effective means for filling the understanding gap for yield management in this case. A case study of yield drop due to layout dependent process marginality and a methodical approach to get to the root of the problem are described in this paper.
Using Statistical Methods to Optimize Patterning Parameters for Tungsten Deposition
Authors: DiBattista Michael , Skinner Kimball , Kneedler Rick , Vasilvey Leonid , Drybcak Lukas , Zbranek Jiri , Hartigan Gavin , Oosting Michiel 
Published: December 2020

Abstract
Circuit edit and failure analysis require tungsten deposition parameters to accomplish different goals. Circuit edit applications desire low resistivity values for rewiring, while failure analysis requires high deposition rates for capping layers. Tungsten deposition can be a well controlled process for a variety of beam parameters. For circuit edit, tungsten resistivity approaching below 150 µohm-cm and 50 μm3/nC is predicted. Material deposition rates of 80 μm3/nC can be achieved with reasonable pattern accuracy using defocus as a parameter.
Extended Circuit Edit, Analysis and Trimming Capabilities Based on the Backside Focused Ion Beam Created Ultra Thin Silicon Platform
Authors: Schlangen Rudolf , Leihkauf Rainer , Kerst Uwe , Boit Christian , Egger Peter , Lundquist Ted 
Published: December 2020

Abstract
Highly integrated microelectronic devices drive an ever increasing effort in engineering, manufacturing and failure analysis. Almost all established failure analysis techniques and conventional circuit edit procedures are facing the severe challenges and limits of aggressive downscaling. While device design and manufacturing cooperate closely, failure analysis often is considered as an add-on service upon request. If physical limitations are hard to overcome, extending the application of an established method to promote synergy with other aspects of IC making is one option for future progress. Traditionally circuit edit FIB is a post-fix procedure to allow for fast design changes in the wiring of a chip. Device performance remains unchanged. A different aspect is the deposition of FIB probe pads which permits electrical probing in locations difficult to reach. Probing results in critical regions of a circuit provide tremendous value for general debug or first silicon analysis. Device performance can be monitored. This paper adds a another dimension with new CE and functional chip analysis techniques where device performance can be directly monitored and altered; therefore connecting integrated circuit design, device development and failure analysis for shorter development cycles.
Low Temperature O2 Plasma Process for Scanning Capacitance Sample Preparation
Authors: Schulte Donald W. , McMahon Terry , Hall David D. , Johnson Mark , Stickle William , Sanders Craig , Long Greg , DeHaan Gary , Cai Ruhua 
Published: December 2020

Abstract
A novel SCM oxide preparation technique using a low temperature O2 plasma treatment is presented. Experimental results demonstrated that oxides of sufficient quality for scanning capacitance measurement analysis can be obtained on both top down and epoxy potted polished cross sections. SCM results obtained from samples processed using the plasma process were comparable to those obtained using more common thermal oxide growth techniques.
X-Sectional Scanning Capacitance Microscopy (SCM) Applications on Deep Submicron Devices at Specific Sites
Authors: Wang Xiang-Dong , Tsang Yuk , Howard Clifford 
Published: December 2020

Abstract
In this paper, we present our recent applications of scanning capacitance microscopy (SCM) on specific devices with sampling window as small as 100nm. The dopant related root causes were successfully identified on those devices fabricated with 90nm CMOS technology. The key step in our approach is the development of a sample preparation technique that allows us to precisely x-section through a transistor without being affected by focused ion beam (FIB) artifacts. FIB was used to mark the area of interest with high precision, but it did not expose the devices of interest. Optical microscope and atomic force microscope (AFM) were used to inspect the mechanically polished surface, thus avoiding beam effects from FIB or SEM. In the first application, a doping anomaly was identified in a PFET poly gate, in a single bit failed SRAM cell. In the second application, an asymmetry of a PWell implant profile in a window of 150nm was identified as the cause of leakage in a capacitor array. Our approach may be applied to other scanning probe microscopy (SPM) techniques in the same category, i.e., scanning spreading resistance microscopy (SSRM) or scanning microwave microscopy (SMM).
Product Debug: Speed Problem Related to Unexpected RC Delay
Authors: van Hassel J.G. , Zachariasse F. 
Published: December 2020

Abstract
In new product designs increasing effort is needed to observe and prove failure mechanisms or process marginalities. For advanced failure analysis Soft Defect Localization (SDL) [1] and Time Resolved Emission (TRE) [2,3] have now become a standard analysis method. Both techniques require a close co-operation between designers and analysts. In this paper we will discuss a comprehensive study to find the mechanism behind a speed problem in the digital part of an audio signal processor. The additional delay was related to unwanted routing through poly-silicide in timing critical circuitry.
Detecting Internal “ESD-Like” Damage on CMOS Gates
Authors: Gores M. , Dicken H. 
Published: December 2020

Abstract
Normally, ESD-type of damage will be located near the bonding pads for the input pins. However, there have been several cases where ESD-type damage has been detected on CMOS gates at internal locations on the die, two or more transistors away from any input or output pin. This paper describes two examples of this type of failure and the unique approaches to the analysis and the special procedures needed to locate the damage sites. It shows some possible approaches to apply to device failures, which do not follow the typical pattern. One of the approaches is a sequence of steps ranging from benign to destructive as shown. The special conditions are usually: the device has functionally failed; curve tracing of the external pins shows no abnormalities; optical and/or SEM inspection of the die will not show any damage sites; and liquid crystal or other thermal techniques will not be effective.
Fundamental Study of Al Pad Grain Size Measurement and Its Effectiveness
Authors: Zhao Yaobin , Dai Haibo , Gao Baolin , Wu Linfeng , Liang Sanan , Niou Chorng , Guo Qiang 
Published: December 2020

Abstract
Grain size monitor of Al pad is necessary to assure pad quality and electrical performance in IC manufacturing. Currently, the sample is prepared either without pretreatment or with 4.9% HF stain or ion milling before grain size measurement. In this paper, we demonstrate the pretreatment has a pronounced effect on the grain size measurement and the method with ion milling pretreatment shows more reliable results. The mechanism is further discussed.
Correcting for Spherical Aberrations in Solid Immersion Microscopy Using a Deformable Mirror
Authors: Lu Y. , Ramsay E. , Stockbridge C. , Koklu F. H. , Yurt A. , Mertz J. , Bifano T. G. , Ünlü M. S. , Goldberg B. B. 
Published: December 2020

Abstract
We present a method for correcting spherical aberrations in solid immersion microscopy through the use of a deformable mirror. Aberrations in solid immersion imaging for failure analysis can be induced through off-axis imaging, errors in lens fabrication or mismatch of design and substrate wafer thickness. RMS wavefront error correction of 30% is demonstrated in the case of substrate wafer thickness error.
Development of a Protective Coating for Application of Ion Cross-Section Polishing on Thermal Inkjet Printhead Heater Chips
Authors: Zhang Q. , Wu X. M. 
Published: December 2020

Abstract
Thermal Inkjet printhead heater chips have a unique construction; getting quality cross-sections using traditional methods is very difficult. This paper describes the development of a new protective coating material, which enables the application of Ion cross section polishing technique for Inkjet heater chip analysis. Applications of this technique are also discussed.
Can Illuminated IV-Characteristics of Micro-Regions in Solar Cells be Measured by Laser-Induced Stimulation?
Authors: Boostandoost M. , Glowacki A. , Bakaeva O. , Kerst U. , Boit C. 
Published: December 2020

Abstract
In this paper, IR-LBIC (Infrared Light Beam Induced Current) is applied using the laser wavelength of 1064 nm in order to analyze polycrystalline thin-film solar cells. The spatially high-resolved map of the short circuit current (~3 µm) has been obtained by performing the IR-LBIC measurement. The results of the measurement showed higher signal response from the grain boundary compared to that from the grain interior. This difference has been explained by the light trapping effect due to the trench-shaped grain boundary profile, which is possibly accompanied by two stage excitation effects via electronic grain boundary states. It has been additionally investigated, whether LBIC measurement could be used to extract local illuminated cell characteristics. However, since the dark current, which has a decisive influence on the solar cell characteristic, is flowing in the entire cell area, this is not possible. A circuit network simulation demonstrates that LBIC cannot be used for extraction of the local open circuit voltage, and the short circuit current is the only parameter that can be locally defined and therefore clearly observed.