GaN/Si(111) Device Defects and HFET Degradation Mechanisms
Authors: Christou Aristos , Shahin David 
Published: February 2020

High Voltage AlGaN/GaN Switching HEMTs

The recent advances of AlGaN/GaN HEMTs grown on Si for addressing the needs of the power electronics market in the 0-900 V range have indicated that GaN on Si may be the most cost effective solution. The main problem with this technology is the large lattice and thermal mismatch between Si and III-nitride layers, which result in several electrically active defects affecting both device performance and reliability. Furukawa Electric initially reported that to increase breakdown voltage it is necessary to compensate the GaN buffer layer by using p-type dopants. Such an approach allowed Furukawa to report a breakdown voltage as high as 525 V with a low specific on resistance. This investigation, using elaborate buffer layer configurations did show the direct relationship between threading dislocation density and breakdown voltage. These results and our present investigations show that to achieve a high breakdown voltage, thick buffer layers and carefully designed structures are required. However the growth of thick buffer layers either by MOCVD or MBE is challenging due to both the thermal mismatch as well as the lattice mismatch.
The presence of mismatch in lattice parameter and coefficient of thermal expansion between GaN on common substrates like Al2O3, SiC, and (111) Si results in a variety of defects that adversely affect device performance. Among the potential defects, threading dislocations (TDs) are the primary defects seen in GaN epitaxial layers. These dislocations can be categorized as pure edge dislocations, pure screw dislocations, or mixed dislocations. Edge dislocations, defined by the Burgers vector , run parallel to the basal (c-) plane of the wurtzite GaN structure. Screw dislocations are defined by a Burgers vector and run perpendicular to the GaN basal plane/parallel to the c-axis. While dislocations have been observed in all heteroepitaxially grown GaN films, TDs are especially prevalent in GaN on (111) Si substrates. The GaN-(111) Si lattice parameter mismatch (≈17%) and coefficient of thermal expansion mismatch (≈56%) are significantly larger than the mismatch with SiC or Al2O3 substrates, leading to the introduction of greater tensile stresses in the GaN layer during and after growth at elevated temperatures. This stress translates into a greater dislocation density or, in more extreme cases, cracking of the GaN film. A variety of techniques have been employed in order to reduce the negative effects of these tensile stresses. Buffer layers of AlN between the GaN and substrate, buffer stacks of AlN, GaN, AlGaN, or SiN, AlN/GaN superlattice layers, special patterning of the substrate, and lower temperature GaN growth processes have received much attention in attempts to prevent film cracking and reduce the TD concentrations. In any case, the TD areal density in GaN-on-Si still remains on the order of 108-1010 defects/cm2 near the upper film surface; these densities are much higher than the TD densities observed in GaN on Al2O3 or SiC.

Effects of Threading Dislocations on Device Performance

Threading edge and screw dislocations present near the upper GaN surface regions degrade electronic device performance in several ways. Both varieties of TD can hamper carrier mobility in the active device regions of the GaN films. The dangling bonds associated with edge defects can act as electron acceptor traps that introduce electrostatic interactions and reduce electron mobility in the conduction channel or two-dimensional electron gas in GaN MOSFETS or HEMTs. The associated negative charging of edge defects has been observed experimentally through use of Scanning Kelvin Probe Microscopy by Simpkins, et al. Screw dislocations can also hamper charge transport through scattering interactions as the defects continue upward through the GaN film. However, since edge dislocations are the predominant defect near the upper GaN surfaces, screw dislocations play a lesser role in reducing carrier mobility. Also, the likelihood of charge carrier interactions with TDs has been shown to be highly dependent on the angle between the dislocation line and the carrier velocity; edge and screw defects that are parallel to the electron velocity have minimal effects on the carriers. Therefore, construction of vertical devices in which screw dislocations have minimal effect on carrier transport is possible, leading to higher carrier mobility and lower resistivity.
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