bluuebunny/crossref_metadata_2025_split huggingface dataset:
Nanometric Particles Removal during Photoresist Stripping
Authors: Lallart Adeline , Garnier Philippe , Pizzetti Christian , Lorenceau Elise , Cartellier Alain , Charlaix Elisabeth 
Published: February 2020

Microelectronics devices dimension have followed the Moore’s law in the last decades. In order to keep a high yield during integrated circuits production, a continuous improvement has been carried out in the particles cleaning area, switching from brushes and acoustic cleans to high velocity sprays. With the device nodes shrink, tinier and tinier particles are to be removed. Even though their adhesion and removal are well understood and documented for years [1], our industry still misses robust solutions to clean nanoparticles, keeping finest features integrity, and extremely low material consumption [2].
Well chosen resist stripping conditions enable an excellent particles removal without materials consumption nor damaging 14nm node polysilicon gates. The cleaning mechanism is investigated and key parameters involving the photoresist and wet stripping will be discussed. The aim of this work is to transfer this knowledge into an industrial optimized sequence. Previous studies deal with the fluids viscoelasticity role on the particles removal from a substrate [3]. It is thought non newtonian properties are involved during the resist removal process, with the fluid generated on the wafer through the well-known interface gel formation.
This paper will present results obtained through the use of 300 mm wafers intentionally contaminated with 45nm silica particles, then coated by different polymers, stripped thanks to various methods. The particles counting before and after the complete resist removal step is assigned to a KLA Surfscan SP3 blue laser diffraction tool.
The stripping conditions are a key parameter to enable an excellent defects removal. Indeed the PRE (Particles Removal Efficiency) varies from a few % to 70% when switching from SPM (Sulfuric acid / hydrogen Peroxide Mixture) conditions: too chemically active (radicals rich) with a stripping rate of few hundreds of nanometers per seconds on a single wafer platform to mild conditions, requiring few minutes to remove the resist on a batch spray tool, enabling the resist transition into a gel like phase (figure 1). Two samples have also been used as reference: first a resist removal by plasma ashing that doesn’t remove any particle, proving the particles removal doesn’t occur during the resist coating step and another one without resist, with the wet stripping to quantify the PRE brought by the SC1 (Standard Clean 1). Further tests are done with various solvents to substitute the SPM, but keeping the gel phase, required for the particles lift off.
Not only results on blanket but also challenging patterned wafers will be presented, showing absence of fine feature damage and PRE data, with a fair comparison with high velocity spray methods.
Eventually a basic mechanism will tentatively be proposed. Moreover, such results tend to prove an interest in continuing using resist stripping in wet instead of plasma ashing.

Figure 1
Reduced Anisotropy in Tetramethylammonium Hydroxide Based Silicon Etchants
Authors: Westwood Glenn , Hsu Chien-Pin Sherman 
Published: February 2020

At sub-10 nm technology nodes, silicon etching is critical to FEOL processes such as FinFET thinning, gap filler removal, pre-III-V deposition etch, and nanowire release etching. The key to developing solutions for these applications is being able to control the anisotropy of the Si etch, or the etch selectivity between Si (111), Si (100), and Si (110). For this study, we focused on the impact of modifications to tetramethylammonium hydroxide (TMAH) on Si etch selectivity, with the ultimate goal of developing an isotropic Si etchant based on TMAH.
Initial studies focused on etch selectivity testing of TMAH based chemistries on Si (SOI) wafers of varying orientations. Etch rates were based on measuring thickness changes by cross-sectional SEM. Differences in surface roughness were also characterized by atomic force microscopy. Finally, solutions were evaluated for anisotropy by performing an etch of patterned pSi wafers.
As expected, aqueous TMAH solutions showed a high level of anisotropy (111/100/110 = 1:5:5) and significant level of surface roughening. In contrast, some of the modified TMAH solutions tested had decreased surface roughening and an decreased level of anisotropy (111/100/110 = 1:2:2). Pattern etching on implanted pSi wafers is used to highlight the differences in anisotropy between TMAH and the different modifications.
Dielectric-MoS2 Interfaces Grown By Atomic Layer Deposition
Authors: Letourneau Steven , Mane Anil U. , Elam Jeffrey W , Graugnard Elton 
Published: February 2020

Molybdenum disulfide (MoS2) has become a prototypical transition metal dichalcogenide (TMDC) atomic-layered material because of its unique materials properties. For example, bulk MoS2 exhibits an indirect band-gap of 1.3 eV, while a single monolayer has a direct band-gap of 1.8 eV. Recently, nanometer scale transistor devices have been made with MoS2 and graphene, yet much of this work relies on layered materials prepared using chemical vapor deposition (CVD) and mechanically exfoliation. Multiple reports have demonstrated the growth of MoS2 via CVD, but only a few studies have reported MoS2 growth using atomic layer deposition (ALD), which offers potential advantages for high volume semiconductor manufacturing. Here, we report the ALD of few-layer MoS2 films using MoF6 and various sulfur precursors on various ALD-grown dielectric surfaces and the ALD of metal oxides on the ALD MoS2 films at temperatures between 100-300 °C. In particular, we used in-situ quartz crystal microbalance measurements to investigate the nucleation of MoS2 ALD on oxide surfaces and vice versa. In general, self-limiting growth of MoS2 was observed on a wide range of dielectric surfaces including alumina, magnesia, and hafnia. The ALD MoS2 films were amorphous as-deposited, but crystallized into a layered atomic structure upon annealing at 800 °C. Using in-situ spectroscopy and electrical measurements, growth inhibition of MoS2 was seen depending on the growth substrate. These studies provide insight into the low-temperature ALD of MoS2 and provide guidance for the ALD of additional TMDC films.
(Invited) Area-Selective Atomic Layer Deposition: Role of Surface Chemistry
Authors: Mameli Alfredo , Karasulu Bora , Verheijen Marcel A. , Mackus Adriaan J.M. , Kessels W. M. M. , Roozeboom Fred 
Published: February 2020

Area-selective atomic layer deposition (AS-ALD) is being considered as the next paradigm shift in future device fabrication. Given the chemical nature of the deposition technique, ALD is very sensitive to surface functional groups and deposition conditions. This characteristic often leads to different nucleation delays when growing a material on one surface (growth surface) as opposed to another (non-growth surface). This feature has been exploited by several research groups to obtain area-selective growth of various materials.1,2 The approaches that have been developed for achieving AS-ALD can be categorized as either area-activation1 or area-deactivation3. When no subtractive steps are employed, area-activation is referred to as direct-write (i.e. maskless) ALD.
In this contribution, results will be presented based on recently developed direct-write ALD approaches for two relevant metal oxides: In2O3:H, and ZnO. The method exploits the difference in nucleation delay on OH- and H-terminated Si surfaces. As shown in Figure 1, direct-write ALD can be achieved by locally activating an H-terminated Si starting surface using an O2-fed µ-plasma printer or by electron beam induced deposition (EBID) of a SiO2 seed layer. This allows to define OH-rich regions with dimensions ranging from a few microns (µ-plasma) down to tens of nanometers (EBID). Therefore, high-quality materials provided by ALD can be combined with the patterning capabilities of direct-write techniques to obtain patterns in a bottom-up approach.
The area-selective characteristics for these two different processes was probed by X-ray photoelectron spectroscopy and electron dispersive X-ray spectroscopy for micro- and nanoscale patterns, respectively. As shown in Figure 2, in-situ spectroscopic ellipsometry was used to investigate the nucleation behaviours of the ALD processes on the growth and non-growth surfaces. Finally, the key reasons for the selectivity have been unveiled using density functional theory (DFT) simulations.

References

1. Mameli, A. et al. Area-Selective Atomic Layer Deposition of In2O3:H Using a µ-Plasma Printer for Local Area Activation. Chem. Mater.
29, 921–925 (2017)
2. Longo, R. C. et al. Toward Atomic-Scale Patterned Atomic Layer Deposition: Reactions of Al2O3 Precursors on a Si(001) Surface with Mixed Functionalizations. J. Phys. Chem. C
120, 2628–2641 (2016)
3. Chen, R. and Bent, S. F. Chemistry for Positive Pattern Transfer Using Area-Selective Atomic Layer Deposition. Adv Mater
18, 1086–1090 (2006)

Figure 1
(Invited) Epitaxial Ge/GeSn High Mobility Channel Transistors
Authors: Liu C. W. , Wong I-Hsieh , Lu Fang-Liang , Huang Yu-Shiang 
Published: February 2020

To boost the drive current of transistor and/or reduce power consumption, new channel materials with high carrier mobility such as SiGe/Ge/GeSn have been considered as the promising candidates for the continuous scaling of Moore’s law. SiGe channel have been used in the industry for pFETs, and the addition of Sn into Ge to further enhance the hole mobility is the attractive area of research. The strained GeSn on Ge/Si grown by CVD provides higher hole mobility than Ge due to the biaxial compressive strain and effective mass reduction by Sn incorporation.
To ensure the gate stack quality, and reduce the scattering of holes in the GeSn channel by oxide/interface charges and surface roughness, the epitaxy Ge cap with significant ΔEV has been integrated. The Ge-cap/GeSn/Ge quantum well structure with [Sn] up to 9% is grown by CVD on SOI, and the low temperature process is used to fabricate the devices without Sn segregation/diffusion. By optimizing the cap thickness and thermal budget of gate stack formation, the high mobility (~430cm2/V-s) of the CVD-grown GeSn quantum well p-MOSFETs is achieved to demonstrate the possible integration of GeSn material in industrial fabrication. The high hole mobility and reduced low frequency noise are obtained using quantum well structures with optimal cap thickness of 1 nm. The Ge cap also reduces the defects formed by Sn diffusion into dielectric. To improve the gate controllability and increase drive current with same footprint, the gate-all-around (GAA) pFETs using GeSn channels will be reported.
For Ge nFETs, junctionless GAAFETs with high drive current and high Ion/Ioff are investigated. To boost the drive current and to suppress short channel effects, the optimized doping profile is needed. Since the subthreshold characteristic of JL FET is highly related to the channel cross-section and channel doping, the channel doping of 1.2x1019cm-3 is used. However, it is too low for the S/D region, and heavily doped Ge (~1.2x1020 cm-3) is used in S/D by selective laser annealing with NiGe contact to reduce the parasitic resistance. The optimized doping profile is achieved by selective laser annealing in the S/D, with Pt as hard mask on channel region to reflect the laser light in the channel. The demonstrated Ge JL nGAAFET with fin width (Wfin) down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/μm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. Note that the increasing mobility with increasing temperature indicates the impurity scattering is dominant.
With Ge/GeSn CVD growth and optimized process, GAA transistors with high mobility channels can be realized as promising candidates for future CMOS scaling.
(Invited) Past, Present and Future Challenges of Thermal Management of Electronics Packaging
Authors: Refai-Ahmed Gamal 
Published: February 2020

The present and future use of the electronics devices of 7nm and beyond shall be supporting a complete heterogonous integration. This heterogonous integration will be more addressing the end customers need from system level point of view.
In the past few years there has been a tremendous increase in the power dissipation of the electronic devices especial general purpose GPU, CPU, as well as, FPGA in order to address the growing applications and support requirements for IoT features. In this talk, more discussion on the challenges of enabling heterogonous integration from thermal prospective will be given. This will be given based on the present thermal management devices of the present and future generation will be identified. The intent of this talk is to challenge the researchers on hot issues which need to be addressed on the coming five years.
(Invited) Thermoelectric Thin Films and Nanocomposites Synthesized Via Solution-Phase Chemistry
Authors: Wang Robert 
Published: February 2020

Solution-phase processing routes to thermoelectric materials have the potential to decrease costs and enable novel device architectures. The best thermoelectric materials are crystalline inorganic semiconductors, which makes finding solution-phase routes to these materials of high interest. Unfortunately, inorganic semiconductors are generally insoluble due to their strong covalent bonds. One way around this hurdle is to create soluble semiconductor precursors that can be transformed into crystalline semiconductors after deposition. Furthermore, these precursor chemistries can be combined with colloidal nanocrystals to create nanostructured thin films with controlled composition and microstructure.
We first present the synthesis of CuSeS and Ag-doped CuSeS thin films via soluble precursors and then report their thermoelectric properties. Specifically, we study the effect of Cu vacancies, Se:S ratio, and Ag-doping. We find that Ag-doping leads to appreciable improvements in thermoelectric performance by increasing Seebeck coefficient and decreasing thermal conductivity, while having little to no change in electrical conductivity. Overall, we find that the room temperature thermoelectric properties of these solution-processed materials are comparable to measurements on CuSeS alloys made via conventional thermoelectric material processing methods. Achieving parity between solution-phase processing and conventional processing is an important milestone and demonstrates the promise of this approach to making thermoelectric materials.
Next, we present new chemical syntheses for soluble PbSe, PbTe, SnSe, and SnTe precursors. These precursors are especially relevant because PbSe and PbTe are the best-performing conventional thermoelectric materials in the moderate-to-high temperature regime. This chemical discovery is also important because soluble precursor routes to PbSe and PbTe thin films have not been reported in the literature. In addition, SnSe has the highest thermoelectric figure of merit of any known material, which makes our SnSe synthesis of interest as well.
Lastly, we combine these precursors with colloidal nanocrystals to create nanostructured thin films with controlled composition and microstructure. Colloidal nanocrystals are made via solution-phase chemistry and consist of an inorganic core with short ligand molecules bound to its surface. These nanocrystals can be made with excellent control over size, shape, and composition. We demonstrate that our precursors can replace the typical organic ligands used in colloidal nanocrystal synthesis. This creates new pathways to inorganic nanostructured thermoelectric thin films with controlled composition and microstructure, and we report on the thermoelectric properties of said films.
(Invited) Atomistic Simulations for Understanding Microscopic Mechanism of Amorphous-Tantalum-Oxide-Based Resistive Switching Devices
Authors: Watanabe Satoshi , Xiao Bo , Li Wenwen 
Published: February 2020

Among oxide-based resistive switching devices, amorphous-TaOx based ones show good endurance and switching performances. Their switching behaviors are understood based on the formation/rupture of conductive filaments (CFs). However, the atomistic structures of CFs and their microscopic formation/rupture processes have not been sufficiently clarified yet. In this talk, we present the results of our atomistic simulations (most of which are with the density functional theory (DFT)) and discuss several aspects related to the nature and formation processes of CFs as follows.
1) CFs in the Cu/amorphous-Ta2O5/Pt heterostructure: Our simulations reveals that single Cu chains in Ta2O5 cannot work as conductive filaments (CFs), while Cu nanowires with a diameter of three atoms or larger can work as CFs. The stability of the Cu nanowires has been checked by ab initio molecular dynamics [1].
2) CFs in the Pt/TaOx/Pt heterostructure with x < 2.5: Our results suggest that not O vacancy chain but the Ta-Ta bonding mainly contributes to the CFs [2].
3) Difference in the atomistic features between Cu/ Ta2O5 and Pt/Ta2O5 interfaces: In the former, considerable portion of interface Cu atoms tend to migrate to the amorphous Ta2O5 layer, while similar behavior is not seen in the latter [3].
4) Ion migration behaviors in TaOx: Our results of ab initio molecular dynamics and nudged elastic band calculations show that the diffusion coefficient in TaOx strongly depends on x [3].
5) Construction of neural network interatomic potentials: We constructed interatomic potential combining the DFT calculations and neural network for simulations of Cu migration behavior in amorphous-Ta2O5 to achieve computation speed and reliability simultaneously. The pathways and barrier energies for Cu diffusion calculated using the NN potential agree well with those obtained from DFT calculations [5].
The final part of the present works was partly supported by the Support Program for Starting up Innovation hub from Japan Science and Technology Agency (JST), and CREST-JST, Japan.
[1] B. Xiao, T. Gu, T. Tada and S. Watanabe, J. Appl. Phys. 115, 034503 (2014).
[2] B. Xiao and S. Watanabe, Nanoscale 6, 10169 (2014).
[3] B. Xiao and S. Watanabe, ACS Appl. Mater. Interfaces 7, 519 (2015).
[4] B. Xiao and S. Watanabe, Extended abstract of SSDM2014 (September 8-11, 2014, Tsukuba, Japan).
[5] W. Li, Y. Ando and S. Watanabe, submitted.
(Invited) Local Redox Reaction By Ion Transport Probed By in-Situ PES Measurements
Authors: Yamaguchi Shu 
Published: February 2020

It is now evident that ion migration in oxides governs the memristive behavior of oxide thin film. After various approaches, still there are some uncertainties about the relation between ion migration and memristive behaviors. Complexities lie in the the ion migration behavior and redox reaction in oxides and at interface between oxide electrolyte and electrode. The mode change from frost-like to filament growth of reduced domains are of another issue to be discussed. In the present study, the author employed in-situ measurement of photoemission spectroscopy (PES) using synchrotron radiation to look at the redox reaction in oxide just underneath the electrode. The author employed thin Au electrode with 3-5 nm in thickness, using hard X-ray, for the excitation of photoelectrons 3-5nm underneath the Au electrode. Various type of “electrolytes,” Gd-doped ceria(GDC), amorphous TaOx(a-TaO
x
), amorphous silica(a-SiO2), and so on, are employed to look at the electrochemical redox reaction in the vicinity of electrode. In case of GDC, XAS measurements have been also made to look at the redox reaction in deeper region from the electrode/oxide interface.
In-situ PES measurements on various oxide thin film systems examined with MIM-type two-electrode cells revealed the variation of Fermi level upon electrochemical polarization, suggesting variations of local electrochemical redox state by the ion migration. Surprisingly narrow electrochemical windows were suggested limited by a pinning at the donor state of component cations and a chemical pinning due to oxygen evolution, in contrast to the ultra-wide band gap of these almost insulating oxides systems. The importance of the reversibility and how to control the kinetics at the anodic electrode should be emphasized. One important conclusion is the system is identical to the simple two-electrode cell composed of the electrolyte that shows variation of Fermi level within an electrochemical window of oxide system by ion migration or electrochemical reaction and modulated overpotential at electrolyte/electrode interfaces, the latter of which gives huge influence to the cell behaviors. These suggest that oxide memristor is governed by the electrochemical properties of the cell. Finally, the author proposes both a new Pourbaix-type E-pO diagram to understand the redox and acid/base reaction in addition to new proposal of the definition of basicity of complex oxide based on electronic band structure, as a necessary framework of solid state electrochemistry for oxide systems.
(Invited) What's Next after GaN? How about More GaN!
Authors: Meyer David J. , Downey Brian P. , Hardy Matthew T. , Storm David F. , Katzer D. Scott , Ancona Mario G. , Nepal Neeraj , Roussos Jason A. 
Published: February 2020

Over the course of the past few years, transistors based on gallium nitride (GaN) and related III-N materials have proven to be clear contenders for solid-state power amplifier applications in the commercial and military market spaces. In microwave technology nodes of lateral GaN high-electron-mobility transistor (HEMT) technology (with gate lengths greater than 0.25 microns), the material-driven electrical performance of GaN has been demonstrated with exceptional reliability in production-released processes.
While a power density of several W/mm can be easily achieved at S- and X-band with GaN HEMTs based on an AlGaN/GaN heterojunction, it generally becomes more difficult to obtain the same output power level at higher frequency nodes. This is primarily due to limitations on the operating voltage that can be used; as device dimensions scale shorter, internal electric fields increase and field management techniques, such as source-connected field plates, generally are not used because they introduce undesirable parasitic capacitance. To address these shortcomings, significant technical research and development has been carried out over the past few years focusing on extending GaN HEMT frequency performance into the millimeter wavelength (MMW) range of 30 – 300 GHz.
To prevent the onset of short-channel effects in short gate length devices, vertically-scaled barrier heterostructures have been investigated. In a number of examples, materials growth development of novel III-N materials has enabled heterojunctions with desirable two-dimensional electron gas transport properties. In this talk, we will review a number of recent developments in the community related to MMW GaN HEMT technology. In addition to reported literature, we will discuss NRL’s internal materials and MMW device development using molecular beam epitaxy. Novel HEMT heterostructures based on AlN, ScxAl1-xN, and InxAl1-xN (metal- and N-polar) will be discussed.
(Invited) Towards a Si Foundry-Compatible, GaN-on-Si Mmic Process on 200 Mm Si with a Cu Damascene BEOL
Authors: Laroche J. , Ip K. , Kennedy T. , Soirez L. , Trimble T. , Kazior T. 
Published: February 2020

In 2013 Raytheon began to integrate deep submicron (≤0.25 µm gate) 200mm GaN on Si HEMT processes within a commercial CMOS Si Foundry environment. When fully realized, these processes will demonstrate multi GHz GaN on Si MMICs by leveraging a fully subtractively processed transistor coupled with multi level copper based back end of line (Cu BEOL) processes. This work provides a status update on the progress towards that goal.