bluuebunny/crossref_metadata_2025_split huggingface dataset:
PC Card Based Optical Probing of Advanced Graphics Processor Using Time Resolved Emission
Authors: Marks Howard Lee , Ton Tung , Block Jeffrey A. , Kasapi Steven , Shaw Chris 
Published: December 2020

Abstract
Internal node timing probing of silicon integrated circuits (ICs) has been a mainstay of the microelectronics industry since very early in its history. In recent years, however, due in part to the increase in the number of interconnection layers and continued proliferation of packaging techniques exposing only the silicon substrate, conventional probing technologies such as e-beam and mechanical probing have become cumbersome or impractical. In an effort to continue transistor-level probing, backside optical probing technologies have been developed and adopted [1]. Chronologically, such techniques include picosecond image circuit analysis (PICA)[2], laser voltage probing (LVP)[3], and dynamic or time-resolved emission (TRE)[4]. In typical examples of backside probing the device under test (DUT) relies on device stimulation from automatic test equipment (ATE) or equivalent bench top setup. This generally requires a specially designed DUT card designed to accommodate a low-profile socket and lid. The DUT card, which is significantly smaller than the tester motherboard, is designed to fit within the chamber opening of the probe system in order to interact with the optical column. Tester stimulation of packaged parts, however, does not address the need to probe the DUT in-situ and in the intended application, such as a PC board. It is often desirable to probe the DUT under conditions typical of the final product or running standardized application based tests. We present here this application and have addressed some of the challenges associated with PC card based optical probing and show successfully performed time-resolved emission on a second-generation advanced graphics processor in a standard graphics card.
Time-Resolved Optical Measurements from 0.13μm CMOS Technology Microprocessor Using a Superconducting Single-Photon Detector
Authors: Stellari Franco , Song Peilin , Weger Alan J. , McManus Moyra K. 
Published: December 2020

Abstract
In this paper we examine the use of the Superconducting Single-Photon Detector (SSPD) [1] for extracting electrical waveforms on an IBM microprocessor fabricated in a 0.13µm technology with 1.2V nominal supply voltage. Although the detector used in our experiments is prototype version of the one discussed in [1] demonstrating lower performance, we will show that it provides a significant reduction in acquisition time for the collection of optical waveforms, thus maintaining the usability of the PICA technique for present and future low voltage technologies.
IC Diagnostic with Time Resolved Photon Emission and CAD Auto-Channeling
Authors: Desplats Romain , Eral Alban , Beaudoin Felix , Perdu Philippe , Chion Alain , Shah Ketan , Lundquist Ted 
Published: December 2020

Abstract
The use of time resolved photon emission (TRPE) to compare internal measurements with simulations can dramatically reduce the time required for IC analysis. During debug, this technique makes it possible to probe only transistors of interest. Two limitations must be overcome: precise location of transistor photon emission areas and distinction between photons emitted by closely spaced transistors. Otherwise results may be seriously biased. Introducing CAD auto-channeling for TRPE makes it possible to generate virtual layers where emissions are expected. As a result, transistor TRPE areas can be automatically located and emission from nearby transistors is taken into account, thus significantly reducing the duration of IC analysis.
Copper Bond Over Active Circuit (BOAC) and Copper Over Anything (COA) Failure Analysis
Authors: Nguyen Dat , Davis Bob , Lewis Corey 
Published: December 2020

Abstract
In today's electronic industry of shrinking circuit boards and shrinking semiconductor integrated circuits (IC), semiconductor companies have to be creative in providing devices with more circuitry on less silicon. Copper Bond over Active Circuit (BOAC)/Copper over Anything (COA) processes allow routing and bonding to thick top level metallization on the LinBiCMOS technology node. This paper discusses failure analysis (FA) techniques and approaches on un-passivated BOAC, and explains a generic BOAC/COA process. The approach to FA of BOAC involves package inspection-non intrusive analysis, decapsulation, die inspection, and defect identification/root cause analysis. Case studies are presented to explain the specific FA steps. Fault isolation involving BOAC requires the strategic removal of copper traces and selective analysis of the failed circuitry. Liquid crystal and micro-probing have been used effectively in failure isolation.
Identification of an IDDQ Failure Mechanism Using a Variety of Front and Backside Analytical Techniques
Authors: Shearer Jim , Le Kim , Yang Xiaoyu , Cleeves Monty , Meeks Al 
Published: December 2020

Abstract
This article presents a case study to solve an IDDQ leakage problem using a variety of failure analysis techniques on a product. The product is fabricated using a 3-metal-layer 0.25 μm CMOS process with the addition of Matrix's proprietary 3-D memory layers. The failure analysis used both top and backside analytical techniques, including liquid crystal, photon emission microscopy from both front and back, dual-beam focused ion beam cross-sectioning, field emission scanning electron microscopy imaging, parallel-lap/passive voltage contrast, microprobing of parallel-lapped samples, and scanning capacitance microscopy. The article discusses how the application of each of the techniques narrowed down the search for this IDDQ leakage path. This leakage path was eliminated using the two corrective actions: The resist is pre-treated prior to ion implantation to produce a consistent resist sidewall profile; and the Nwell boundaries were adjusted in the next Nwell mask revision.
Application of ToF-SIMS to Airborne Organic Contamination Analysis
Authors: Lu Dong , Trigg Alastair , Xing Zhenxiang , Kumar Rakesh , Chang Chang Kuo 
Published: December 2020

Abstract
Airborne molecular contamination poses a serious problem for advanced wafer fabrication as the devices are continually scaled down. The amount of this contamination may be only a few monolayers, which are extremely difficult to detect by the commonly used analytical techniques, such as FTIR. ToF-SIMS has extremely high surface sensitivity for the analysis of trace contaminants on wafer surfaces. The high mass resolution of ToF-SIMS is also a powerful tool for the identification of the contaminants. In the current study, ToF-SIMS is used to monitor the build-up of airborne amine contamination on Black Diamond1 surfaces. It has been found that cleaning of the Black Diamond surfaces using wet chemicals can lead to photoresist poisoning. Thermal desorption-GC-MS analysis revealed that wet cleaning would result in the accumulation of hydrocarbons on the Black Diamond surfaces. ToF-SIMS shows that amines can build up gradually on the Black Diamond surfaces after wet cleaning, probably via airborne molecular contamination. For the Black Diamond wafers which did not go through the wet cleaning process, there was no significant increase of amines on the wafer surfaces. The amount of amines on the Black Diamond surfaces depends on the chemicals used in the cleaning processes and the wafer storage conditions. The level of amine contamination can be significantly reduced after the samples are heated up to 300°C for a few minutes in inert atmosphere.
Yield-Modeling and Test Oriented Taxonomy of IC Structure Deformations
Authors: Maly W. , Zanon T. , Vogels T. 
Published: December 2020

Abstract
This paper proposes a taxonomy of process-induced deformations of IC structures. Such a taxonomy is envisioned as a foundation for yield modeling and development of test strategies, as well as, for design of ICs with redundancy. It is proposed to address the rapidly growing complexity of interaction between process-induced deformations of IC structures and steadily shrinking geometry of deep submicron ICs.
An Evolution in Plastic Decapsulation Process Improvement
Authors: Somcio N.S. , Komrowski Andrew J. , Curiel Luis , Silvis Charles R. , Sullivan Daniel J.D. 
Published: December 2020

Abstract
Decapsulating wire-bonded plastic packages using fuming nitric or sulfuric acid is one of the most widely used methods for exposing a die during failure analysis [1]. The need to have physical access to the die in a packaged semiconductor device is often essential in the FA process. Regularly, the entire surface of the die must be exposed to take full advantage of techniques such as Emission Microscopy or Liquid Crystal. However, removing the plastic encapsulant using corrosive acids, such as fuming sulfuric acid, presents a challenge: achieving a fully exposed die surface while maintaining the device’s electrical functionality. Here we describe how our decapsulation process has evolved to address this challenge, resulting in improved survival rates for plastic packages decapsulated in the lab.
The Impact of Feature Packing Density on FIB Editing of Advanced Technology ICs
Authors: Marchman H. , Herschbein S. , Scrudato C. , Rue C. , Fischer L. , Abramo M. 
Published: December 2020

Abstract
FIB techniques have provided a means for the nanometer-scale spatially confined etching and deposition processes required during repair or editing of advanced integrated circuit (IC) prototypes and lithographic masks. Primary sample properties that can lead to limitations on the applicability of FIB for IC repair are the material composition, aspect ratio, and feature packing density. The typical aims when developing a gas-assisted-etch (GAE) process for IC repair applications are enhancement of etch rate, increased volatilization of reaction products, and improved material selectivity. This paper presents results from a novel two-step process for clearing large areas of one micron thick (upper-level metal) layers. Better equalization of etch rates was achieved using the novel developed FIB GAE process. The paper describes the preliminary results obtained using non-gallium-ion beam based approaches for controlled surface modification during the editing of IC repair samples.
Small Via High Aspect Ratio Circuit Edit: Challenges, Techniques and Developments
Authors: Ray Valery , Antoniou Nicholas , Balasubramanian Ravi , Bassom Neil , Clabby Marie , Gannon Tom , Huynh Chuong , Tiani Gary 
Published: December 2020

Abstract
As semiconductor device manufacturing technologies move below the 100 nm node constrains on using Focused Ion Beam (FIB) systems to perform circuit edit operations tighten dramatically. Phenomena associated with via milling and deposition processes, considered minor side effects in the past, may become performance-limiting factors. Obstacles, associated with editing deep sub micron technologies beyond 100nm node, which include navigational accuracy, beam placement stability, and small via milling and filling processes, cannot be completely overcome without advances in overall FIB system performance and operation. We present a detailed technical overview of the challenges, associated with silicon microsurgery on devices, manufactured with sub 100 nm process technology and describe recent advancements in FIB technology and techniques which address these areas and allow successful modification of today’s most advanced designs.
Improved SRAM 6T Bit Cell Failure Analysis Using MCSpice Bit Cell Defect Modeling
Authors: Mulder Randal , Subramanian Sam , Widener Ed , Chrastecky Tony 
Published: December 2020

Abstract
Single bit failures are the dominant failure mode for SRAM 6T bit cell memory devices. The analysis of failing single bits is aided by the fact that the mechanism is localized to the failing 6T bit cell. After electrically analyzing numerous failing bits, it was observed that failing bit cells were consistently producing specific electrical signatures (current-voltage curves). To help identify subtle bit cell failure mechanisms, this paper discusses an MCSpice program which was needed to simulate a 6T SRAM bit cell and the electrical analysis. It presents four case studies that show how MCSpice modeling of defective 6T SRAM bit cells was successfully used to identify subtle defect types (opens or shorts) and locations within the failing cell. The use of an MCSpice simulation and the appropriate physical analysis of defective bit cells resulted in a &gt;90% success rate for finding failure mechanisms on yield and process certification programs.
Characterization of Sub 130 Nanometer Gate Length SOI MOSFET Devices Exhibiting Short Channel Effects
Authors: Kane Terence , Tenney Michael P. , Bruley John 
Published: December 2020

Abstract
As MOSFET device gate lengths shrink below the 130 nanometer node, the effects of short channel effects (SCE) and gate line edge roughness (LER) have an increasingly more pronounced affect on device performance [1-8, 10]. The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts increasingly tighter critical dimensions (CD) control limits on LER from 2.7 nm in 2004 to 1.3 nm in 2010 [9,11]. As gate lengths shrink, resist etch processes emerge as the most significant contributor to LER [1-8, 11]. In addition, another contributing factor to SCE is junction implant defects. Examples of gate LER effects and junction defects in 130 nanometer node SOI SRAM MOSFET devices identified by sub-micron electrical characterization with analysis by high resolution transmission electron microscopy (TEM) are discussed.
Atomic Force Probing in Analog MOSFETs Measurement
Authors: Chen Kaiyuan , Chatterjee Tathagata , Christensen Kim , Rosal Juan , Edwards Hal 
Published: December 2020

Abstract
Accurately measuring parameter mismatch for analog MOSFETs, such as the threshold voltage (Vt) or W/L ratio, is often required in analog circuit failure analysis. The challenge in probing analog MOSFETs using atomic force probing (AFP) is contact resistance. Contact resistance between AFP tips and tungsten contacts can cause large error at high current. This paper discusses measurement error caused by contact resistance and the techniques to identify and reduce the contact resistance effect.
In-line High-Resistance Tungsten Plug Defect Monitoring with an Advanced e-beam System
Authors: Tsai Mingsheng , Yeh J. H. , Liu Hermes , Lin Scott , Wang Kirin , Lei Shuen Chen , Wu Wei-Yih , Wu Hong-Chi , Xiao Hong , Jau Jack 
Published: December 2020

Abstract
In-line e-beam inspection is performed to detect dark voltage contrast (DVC) defects on normally bright W-plugs. Cross-sectional SEM and TEM in an FA lab verified that the different gray level values (GLV) of DVC defects are caused by different resistances of the W-plugs. We found that DVC defects with lower GLV (GLV1) are W-plugs that are open and almost open. DVC defects with GLV2 are caused by partially open W-plugs and in-plug voids.
وسيلة الأوراق الممزقة وتأثيرها على مهارة القراءة: دراسة تجريبية في معهد توانكو لنتاو العصري المتحدي
Authors: Fajri Awalul 
Published: December 2020

الغرض لهذا البحث هو لمعرفة تأثير استعمال وسيلة الأوراق الممزقة على مهارة قراءة النصوص العربية فى معهد توانكو لنتاو العصري المتحدي بمحاظة تانة داتر.أما منهج البحث المستعمل فهو البحث شبه التجريبي مع عينة البحث 40 تلميذا المقسمين إلى الفرقتين، 20 تلميذا للفرقة التجريبية و الباقية منهم للفرقة الضبطية. استعمل هذا البحث طريقة اختبارية مع تحليل إحصائى فى تحليل البيانات. دلت نتيجة البحث أن استعمال وسيلة الأوراق الممزقة له آثار على مهارة قراءة النصوص العربية ودلّ عليها تفريق نتيجة التلاميذ فى قراءة النصوص العربية بين الفصل التجريبى و الفصل الضبطي. أن النتيجة باختبار-ت (14,2) أكبر من نتيجة-ت فى الجدول (2,86) على الدرجة 1%.
تأثير الطريقة التركيبية على مهارة القراءة: بحث تجريبي في المدرسة الابتدائية الإسلامية الحكومية الواحدة تاناه داتار
Authors: Rudiamon Septika , Yasmadi Yasmadi , Faisol Yufni 
Published: December 2020

الغرض من هذا البحث لمعرفة تأثير الطريقة التركيبية على مهارة القراءة لدى التلاميذ في المدرسة الابتدائية الإسلامية الحكومية الواحدة تاناه داتار. استخدم الباحث منهج شبه تجريبي مع تصميم مجموعة ضابطة غير معادلة. وكان المجتمع 457 طالبًا ، بينما تكونت العينة من 50 طالبًا مقسمين إلى مجموعتين ، و 25 طالبًا في المجموعة التجريبية تم تدريسهم باستخدام طريقة تركيبية و 25 طالبًافي المجموعة الضابطة الذين تم تعليمهم باستخدام الطريقة السمعية الشفهية. تم جمع البيانات عن طريق إجراء الاختبارات. بعد ذلك ، تم تحليل البيانات باستخدام اختبار t. وأظهرت النتائج أن نتيجة to = 7.14 كانت أعلى من نتيجةt فى الجدول عند درجة 1٪ = 2.80، فالفرضة العدمية مردودة والفرضة التبادلية مقبولة. فالخلاصة أن الطريقة التركيبية تؤثر على مهارة القراءة إيجابيا في هذه المدرسة.
A DESIGN OF DIGITAL CHAIN CUSTODY FOR REPUBLIC OF IRAQ
Authors: Abed Zaid Shireen M. , Sabbar Bayan M. 
Published: December 2020

Chain of custody (COC) is a concept and process designed to ensure the integrity of evidence including digital evidence (DE). Also, it defines a set of procedures to document files according to its chronological [1]. In this paper, the authors design a Chain of custody application software in order to document all digital evidence in order to ensure its integrity. Thus, a chain of custody application design to document the digital evidence from the time it collected to the time where the evidence actually presented at the court to ensure the digital evidence integrity and authenticity. It can help the investigator to follow clear documentation during the investigation process because of the conventional method considered a problematic issue when it used for digital evidence. In addition to physical evidence and digital evidence have different features and characteristics.The Chain of Custody application for digital evidence is designed using the SQL and XML [3] schema approach to save case information and compute DE hash value. then compare it with its value stores in the COC tab. This solution comes as one of the solutions to enrich the existing solution of the digital chain of custody.
Nanoencapsulation and identification of phenolic compounds by UPLC-Q/TOF-MS2 of an antioxidant extract from Opuntia atropes
Authors: Martínez-Flores Héctor E. , Tranquilino-Rodríguez Eunice , Rodiles-López José O. , Martínez-Avila Guillermo C. G. 
Published: December 2020

Background: Nanoencapsulation is a technique that protects bioactive compounds such as polyphenolic compounds from environmental factors, through a biopolymer that acts as a wall system. Cladodes of O. atropes are an important source of polyphenolic compounds, flavonoids being the most abundant, these are mainly in the form of glycosides and their consumption has been related to a decrease in glucose and lipid profile through the elimination of intracellular radicals.Purpose of the study: To study the formulation and process parameters that allow obtaining the best experimental conditions to nanoencapsulation and protect the polyphenolic compounds of the O. atropes extract.Methods: Wall materials applied for nanoencapsulation (soy protein isolate, calcium caseinate , and maltodextrin). A Box Behnken 33 design was used; wall material extract of O. atropes (1/1, 2.5 / 1, 4/1), temperature (95, 105 and 115 ° C) and spray (40, 70 and 100%), to evaluate the yield, feeding speed, particle size, encapsulation efficiency, phenolic acids, flavonoids, DPPH• and ABTS•+. Polyphenolic compounds were identified by UPLC-Q / TOF-MS2.Results: Maltodextrin presented better properties in the encapsulation of the extract of O. atropes. The Box Behnken 33 design made it possible to identify the treatment with the appropriate quality characteristics for the nanoencapsulation process; Formulation 2.5 / 1 (maltodextrin / O. atropes extract), 115 ° C and 100% spray, to obtain 85.22% yield, feeding speed of 9 mL / h, the particle size of 154.77 nm, 55.69 % encapsulation efficiency, phenolic acids of 0.95 mg GAE / g, flavonoids of 7.02 mg QE / g, and antioxidant activity in DPPH• of 0.29 mg GAE / g and ABTS•+ of 0.45 mg GAE / g. The polyphenolic profile was characterized, and it was confirmed that nanoencapsulation protects some isomers of isorhamnetin 3-O-rhamnosido-7-O- (rhamnosyl-hexoside) and p-coumaric acid 4-O-glucoside.Conclusion: Maltodextrin is an excellent encapsulating material of the O. atropes extract, the formulation and process conditions that favored all the response variables were identified and it was shown that nanoencapsulation protects the polyphenolic compounds.Keywords: O. atropes extract, nanoencapsulation, polyphenolic profile, UPLC-Q / TOF-MS2.
Prediction of mechanical behavior of friction stir welded joints of AA3003 aluminum alloy
Authors: Chekalil Ismail , Miloudi Abdelkader , Planche Marie-Pierre , Ghazi Abdelkader 
Published: December 2020

Friction stir welding (FSW) is an extremely complex process because it depends on the intrinsic and extrinsic factors of the material under consideration. The purpose of the present work is to formulate a set of recommendations concerning the choice of the different factors that are likely to influence the quality of the FSW joint and to find a mathematical model that allows predicting the mechanical behavior of the junction. An experimental design was therefore used to highlight the effect of the welding parameters on the behavior of the aluminum alloy FS-Welded joint. The most influential parameters were shown to be in the order of rotational speed, feed rate and tool tilt angle. The study of the interactions between these different parameters made it possible to establish a number of combinations of the different factors for the purpose of achieving the quality optimization of the FSW joint by obtaining a tensile strength of the weld joint equal to of that of the base metal.
What is the Normal Value of Tpe Interval and Corrected Tpe Interval?
Authors: Koca Hasan , Koç Mevlüt 
Published: December 2020

Objective: Increased T wave peak and end distance (Tpe interval) shows abnormal spread in ventricular repolarization, it is associated with increased risk of ventricular arrhythmia and poor prognosis. However, Tpe interval, corrected Tpe (Tpe-c) upper limit value, and normal reference interval have not been reported in healthy population. In our study, it was aimed to determine the normal reference range of Tpe and Tpe-c interval in healthy population.
Materials and Methods: 414 healthcare professionals who had no complaints were included in the study. Tpe and Tpe-c measurements of all patients were performed on 12-lead electrocardiography taken at rest. Average and standard deviation, median, minimum, maximum, 95% confidence intervals (95% CI) values of these parameters were obtained.
Results: According to the data obtained in our study; Tpe mean and standard deviation, median, minimum, and maximum values were found to be 70.3 ± 12.3 ms, 70 ms, 50 ms and 100 ms, respectively. The 95% CI value of the Tpe interval was detected as 50-90 ms. Tpe-c mean and standard deviation, median, minimum, and maximum values were found to be 76.1 ± 14.6 ms, 75 ms, 48 ms and 128 ms, respectively. The 95% CI of the Tpe-c interval was detected as 53-100 ms. It was determined that Tpe and Tpe-c intervals were not affected by demographic and clinical parameters.
Conclusion: As a result of our study, it was determined that the upper limit of Tpe and Tpe-c interval values in adult, not-elderly and healthy normal population were 90 ms and 100 ms, respectively. It was thought that this information could be used for prolonged Tpe interval, which shows an increased risk of arrhythmia in daily practice. However, it was concluded that studies should be done in other communities and races on this subject as well.