bluuebunny/crossref_metadata_2025_split huggingface dataset:
(Invited) Present and Future of LTPS Technology
Authors: Kaneko Toshiki , Nakamura Takashi , Kimura Hiroyuki 
Published: February 2020

Japan Display Inc. has developed excellent quality TFT-LCD displays based on precise LTPS technology and progressive LCD-cell technology [1]. Their advantages are less than half the power consumption and a contrast ratio of 2000:1 using unique RGBW technology, photoalignment technology, and an in-cell touch panel technology with 1mmΦstylus input simultaneously.
We have recently developed two high resolution displays with more than 500-ppi which one can realize higher response rate with higher frame rate driving and another can reduce the power consumption by 30% with a lower frame rate driving. One is the 17.3-inches 8K4K display with 550ppi and 120-Hz frame rate driving and another is the 8-inches 4K2K with 510-ppi with 30-Hz frame rate driving.
We adopted two technologies for the LTPS backplanes, one was a 1.5-µm high resolution process, and the other was an increase of the pixel capacitance. Figure 1 shows the cross sectional SEM image of a poly-Si layer. I-line photolithography was adopted and the dry etching condition of the poly-Si patterning process was optimized in order to obtain poly-Si islands 1.5-µm wide with a good taper angle.
In addition, a thinner insulator for the storage capacitance Cs was fabricated almost by half to increase the CSvalue with care in terms of coverage over other layers.
The adoption of a 1.5-µm short channel LTPS process and thinner insulator thickness can contribute two benefits. One is a decrease in load capacitance which is considerably increased as the number of pixels increase up to 8K4K. Another is a decrease in feed through voltage ΔVth which is described by equation (1), which causes cross talk especially on higher resolution display. The developed 17.3-inches 8K4K LTPS-LCD with 510-ppi resolution in collaboration with NHK is shown in Figure 2 [2]. We realized uniform transmittance distribution and sufficiently small cross talk much less than 2% on this prototype display which attributes its small load capacitance and small feed through voltage.
We also developed 8-inches 4K2K display with 510-ppi. By adopting the same LTPS technologies, we also realized 30-Hz frame rate driving with acceptable flicker level which is defined as the range of the maximum and minimum liminance. We could decrease the total power consumption for drinving by 32% adopting 30-Hz frame rate driving as shown in Figure 3.
Reference:
[1] T. Kaneko, et al., "Innovative 5-inch FHD and 7-inch WQXGA Displays for Next Generation Smartphones and Tablets", Proc. SID'13, 2013, pp693-296.
[2] K. Mochizuki, et al., "A 510-ppi 8K4K LTPS TFT-LCD with 120-Hz Frame Rate Driving" SID'16, Digest paper, 67.2, 2016

Figure 1
(Invited) Microcrystalline Silicon Based TFTs and Resistors for Reliable Flexible Electronics
Authors: Kervran Yannick , Kandoussi Khalid , Dong Hanpeng , Janfaoui Sabri , Coulon Nathalie , Simon Claude , Jacques Emmanuel , Mohammed-Brahim Tayeb 
Published: February 2020

Silicon based flexible electronics is shown here as the right way when considering the reproducibility of the process and the long-term reliability, the only way leading to commercially available products. Microcrystalline silicon films are deposited directly on plastic substrates (PEN and Polyimide) at low temperature. Films are highly crystallized. Crystalline volume is higher than 73% for 50nm thick film as calculated from Raman spectra.
Using such film, resistances are fabricated and checked as deformation gauges. The mechanical behaviour of microcrystalline silicon films under longitudinal as well as transversal tensile (Figure 1) and compressive stress is studied. The effect of the nature of the substrate and its thickness on this behaviour is studied also. These studies led to determine the maximum strain that can hold microcrystalline silicon film. This strain limit is reached by bending the film at different curvature radii depending on the thickness of the substrate. Lower curvature radius is reached with thinner substrate. Lower than 1 mm radius, leading to fold in half the film, is reached without breaking it (Figure 2). This high flexibility together with demonstrated reliability led the use of a matrix of microcrystalline silicon based gauges in the determination of any form and in the characterization of human pulse (Figure 3).
Thin-film transistors are also fabricated on previous substrates at the same low temperature. Undoped microcrystalline silicon forms the active layer of these transistors. Phosphorus doped microcrystalline silicon is used as source and drain regions. The gate insulator is also deposited at low temperature. TFTs show very high flexibility. TFTs support lower than 1 mm curvature radius leading to compressive as well as tensile strain, without breaking (Figure 4). More than 200 times of such extreme bending are done without changing the TFT’s characteristics (Figure 5).

Figure 1
Controllably Aligned Ultra-Flexible and High-Performance Organic Single-Crystal Arrays Via Solvent Vapor Annealing for Large Area Soft Electronics
Authors: Kang Jingu , Kim Jaehyun , Jo Jeong-Wan , Kim Myung-Gil , Kim Jaekyun , Park Sung Kyu 
Published: February 2020

Recently, semiconducting organic materials have been actively investigated for achieving high performance organic thin-film transistors and applying to diverse electronic applications. Particu-larly, in order to control the location and direction of organic single crystals with a densely packed molecular structure, several techniques such as inkjet printing and sheared deposition us-ing a self-assembled mono-layer pattern have been suggested. In this presentation, we used sol-vent vapor anneal (SVA) process of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) organic films, forming diverse patterns of their organic single crystals. Room-temperature photochemical patterning of polymer dielectric layer by using deep ultraviolet (DUV) enables the determined organization of C8-BTBBT single crystals with controlled-position and orientation. In SMSVA process, C8-BTBT small molecules become mobile on soluble polymer layer and re-assembled into micro rod-shaped single crystal only at pristine polymer dielectric region.
Using the novel SVA, C8-BTBT single crystal arrays were easily produced on narrow trench of pristine polymer dielectric while their diverse patterns such as a multi-lines, zigzags and star shape were readily possible as well. Based on these arrays of C8-BTBT single crystals, we fabricated high performance and large current organic single crystal transistor on a 3-μm-thick flexible film in which the saturation mobility of devices exceeds ~ 3 cm2 V-1s-1 for one single crystal micro-rod. It was also found that the high performance of single crystal transistor remained functional following the aggressive bending test. We rolled up the device on optical fiber (bending radius:150 μm). After the bending test, the devices show reliable performance without significant degradation from its initial characteristics.
Investigation on the Gate Electrode Configuration of IGZO TFTs for Improved Channel Control and Suppression of Bias-Stress Induced Instability
Authors: Mudgal Tarun , Edwards Nicholas , Ganesh Prashant , Bharadwaj Anish , Powell Eli , Pierce Michael S , Manley Robert G. , Hirschman Karl D 
Published: February 2020

The classic bottom-gate IGZO TFT structure requires a passivation layer application over the back-channel for stability and process integration. However, the passivation material deposition process usually degrades the interface quality and presents defect states at the back-channel interface which are difficult to compensate by a controlling gate electrode positioned on the opposite side of the semiconductor. A top-gate configuration takes advantage of a superior back-channel interface between the substrate and the sputtered IGZO film. The gate dielectric must be deposited on the IGZO which presents an inferior interface, however the influence of defect states can be reduced by annealing in an oxidizing ambient prior to the gate electrode deposition. As positioned directly above the inferior interface, there is an improvement in the ability of the gate potential to control the device operation in the presence of remaining defect states.
This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance (see fig. 1). Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Results from all three gate electrode configurations will be compared. Device testing performed over a temperature range from 10 K to 400 K allows a comprehensive assessment of transport behavior (see fig. 2), with results used to refine a material and device model for TCAD simulation.

Figure 1
A Current Supply with Single Organic Thin-Film Transistor for Charging Supercapacitors
Authors: Keshmiri Vahid , Larsen Christian , Edman Ludvig , Forchheimer Robert , Tu Deyu 
Published: February 2020

Supercapacitors (also referred to as ultracapacitors, electric double-layer capacitors) bridge the gap between rechargeable batteries and electrolytic capacitors with moderate capacity and fast charging and are very promising for electric energy storage. Compared with lithium-ion batteries, supercapacitors are also superior regarding cycle life, specific power, and operating temperature. However, the cost per kWh of supercapacitors are tenfold to lithium-ion batteries. Printed electronics offers a route to a low-cost manufacturing platform that enables mass production of supercapacitors at low cost. Supercapacitors are usually charged with constant current supply, for example, Keithley 2200 programmable power supply. Here we present a current supply with single organic thin-film transistor (OTFT) to charge supercapacitors. The current supply takes power directly from the electric grid (115 V AC, US standard), converts the AC voltage to a quasi-constant current (~0.1 mA) regardless of the impedance of loads, and charges the supercapacitors. This work demonstrates steps towards all printable supercapacitor energy storage systems integrated with chargers that enable direct charging from the power outlet.
Solution-processed OTFTs based on the popular polymer semiconductor P3HT have been developed to rectify 115 V AC voltage. The P3HT OTFTs were fabricated on glass substrates and Au electrodes for drain and source were patterned with a standard UV-lithographic lift-off process. The thickness of the spin-coated P3HT layer is around 35 nm. In order to operate the transistors at such high voltage, a rather thick (2500 nm) polymer PMMA was deposited on the P3HT as the gate dielectric. For gate electrodes, 100 nm Al was subsequently deposited by thermal evaporation through a shadow-mask. The channel length and width are 50 um and 55 mm respectively. The transistors delivers 0.7mA current when the drain voltage and the gate voltage are both at -200V. The average mobility is 2.6x10-2 cm2/Vs while the average threshold voltage is 2V.
A diode-configured OTFT was used to rectify 115 V AC as a half-wave rectifier. Paralleling a 15-uF capacitor with the load, the ripples were smoothed and a DC output was obtained. With a 10-kΩ load, the output current is 0.1 mA at a voltage of 1 V. Varying the load from 10 kΩ to 100 kΩ, the voltage across the load increased to 8 V (eight times higher) while the output current dropped only 20% to 0.08 mA. The rectifier thus provides quasi-constant current output for different loads. In addition, no other voltage step-down devices, for instance, transformers, are required to take the 115 V AC voltage down to a few volts. During charging of the supercapacitors, the load resistor also works as a protection device that protects against overcharging. This single OTFT current source was demonstrated to charge a 430mF supercapacitors to 1 V directly using 115 V AC voltage from power outlet.
(Invited) Physical Properties of Novel 2D Semimetal WTe2: From Microscopic Study to Devices
Authors: Pan Minghu , Yuan Hui 
Published: February 2020

In this study, multiple measurements, including scanning tunneling microscopy (STM), electrical transport, corroborated by DFT calculations are performed on freshly cleaved surfaces of semimetallic tungsten ditelluride (WTe2) crystals. High sample quality with very low density of defects is confirmed by STM observation and in-plane anisotropic conductance (originated from quasi-one dimensional Fermi surfaces) can be conclude based on transport measurement and DFT calculation.We reveal that strong Rashba type spin-orbit effects due to the non-centrosymmetric structure splits the electron and hole bands crossing the Fermi level and lifts the spin degeneracy of these bands. Low temperature STM/S measurements show the umklapp-type interference pattern on WTe2 surface at 4.2 K, proven to be a spectroscopic feature dominated by spin-conserving processes. Furthermore, we investigate electronic properties of devices made from few-layer WTe2 down to a few nanometers. Our results reveal that few-layer WTe2 could be an ideal candidate for future 2D electronic, optoelectronic after solving the ambient sensitivity of device process.
(Invited) Performance Limit and Potential of Layered MoTe2 Transistors
Authors: Lin Yen-Fu 
Published: February 2020

Atomically thin flaks were obtained to fabricate field-effect transistors by using mechanical exfoliation of 2H-type α-molybdenum ditelluride (MoTe2) bulk crystal grown by chemical vapor transport. Both static and dynamic charge transport of these layered transistors were systematically investigated to explore the underlying mechanism of charge transport. In the quasi-static measurements, carrier ambipolarity was observed and originated from the formation of tunable Schottky barriers at the metal/MoTe2 contacts. In the dynamic measurements, .the 1/f dependence of the noise was observed in the conducting channels in vacuum and followed the carrier number fluctuation model. Moreover, the noise spectrum in ambient conditions changed to a Lorentzian, possibly because a large number of gas molecules absorbed at the chalcogen vacancies, enhancing the trapping and emission of carriers between two discrete energy states. Using such unique layered transistors, we further realized complementary-like inverters, amplifiers and environmental sensors, demonstrating their feasibility for future digital and analog circuit applications.
A Novel Core-Shell Structure of Anti-Reflection Layer for Cu(In,Ga)Se2 Solar Cell Application
Authors: Chen Chia-Wei , Tsai Hung-Wei , Su Teng-Yu , Lin Wei-Sheng , Thomas Stuart Richard , Chueh Yu-Lun 
Published: February 2020

Copper-indium-gallium- diselenide (CIGS) is one of the potential candidates for high conversion efficiency solar cells with direct band gap of 1~1.7 eV and high absorption coefficient of 104~105 cm-1. Introducing an anti-reflection layer on top of CIGS solar cell can enhance light scattering in the device, prolong optical path and therefore increase the photocurrent. Surface texture is one of the approaches to reduce the reflectance, and creating nanostructures by chemical etching or electrochemical method for anti-reflection layer has been reported. However, those approaches have concomitant disadva ntages including the complex mold fabrication and the etching solution remaining on the device.
In this regard, we utilize glancing angle deposition system to fabricate mold-less self-synthesizing TiO2 helical nanostructure on the top of CIGS device as anti-reflection layer. In order to create gradient refractive index for further decreasing the reflectance, an oxide shell is deposited surrounding the TiO2 helical nanostructure by chemical bath deposition. The core-shell nanostructure is observed by transmission electron microscopy (TEM). According to UV-Vis spectroscopy, the reflectance is dropped after the nanostructure created on the device, which means that the CIGS layer can absorb more light and create more carriers. At last, the cell performance is improved due to the enhanced short circuit current (Jsc), which results from the decreasing reflectance. The basic research from this project will be beneficial to development in photovoltaic field both in research and industry fields.
Enhancement of Light Extraction Efficiency in Organic Light Emitting Diode with Nano-Scaled Random Patterns
Authors: Lee Heon , Kim Yangdoo 
Published: February 2020

Fast response, true color representation, and applicability to flexible display, organic light emiting diodes (OLED) become prominent next generation display devices. However, light extraction efficiency of OLED is still limited to below 30% due to surface plasmon polaritons (SPP) and total internal reflection phenomena at each layer. In order to improve the lower value of light extraction efficiency, various works are investigated. The main reasons of trapped light inside OLED device are total internal reflection and waveguide and SPP mode.
Total internal reflection effect can be decreased by application of micro-lenz array and surface scattering structures. However, the clarity of image can also be damaged as an unwanted side effect. Captured light inside the device, due to waveguide and SPP mode can be decreased by photonic crystal pattern or moth-eye pattern. In both cases, device fabrication process is the key issue.
In order to fabricate highly efficient OLED display without blurring of image, nano-scaled random pattern was formed on glass substrate using direct ptinting method[1]. Nano-scaled random pattern has low haziness and smoothed curvatures on the surface. It was formed by direct printing of spin on glass (SOG)materials such as hydrogen silsesquioxane (HSQ). After proper heat treatment, HSQ becomes SiO2. Current efficiency and power efficiency of OLED, formed on glass substrate with nano-scaled random pattern, exhibit 25% and 35% increase, compared to OLED device on flat glass substrate, respectively. External quantum efficiency of OLED device on nano-patterned substrate also shows 28% of increase[1].

Keywords: optical scattering pattern, nanoimprint, OLED, light extraction efficiency

References:

[1] Optic Letter 40 (2015) 5838-5841
ZnO Nanowire Device Fabricated By Hydrothermal Synthesis and Dielectrophoresis Method for Gas Sensor Applications
Authors: Lyu Cheng-Han , Sun Kai-Heng , Wang Yu-Hung , Hsu Hsun-Feng 
Published: February 2020

Recently, metal-oxide semiconductor-based gas sensors have gotten a great attention due to their special advantages, such as low cost, high performance and easily fabricated. ZnO has been extensively studied, because it can be applied to sense various gases. One-dimensional ZnO nanostructures can enhance the sensing performance. The vertical nanowire array is a common structure for ZnO nanowire-based gas sensor. However, the seed layer under the nanowire array reduces the sensing capability. Therefore, in this study, the gas sensing devices were fabricated by the arrangement of nanowires between the electrodes.
ZnO nanowires were synthesized on the ZnO seed layer by hydrothermal method. The alternating current electrical field was used to align ZnO nanowires of different lengths between the electrodes. For gas sensing application, two types of the nanowire structured devices were used to detect CO.
The results show that a flat surface and small grain of seed layer was received by annealing at 300℃, and it can be used to fabricate ZnO nanowires with small fluctuation in length and width by hydrothermal method. ZnO nanowires had the highest aspect ratio when the concentration of precursors was 0.04M. The length of nanowires increased by adding an appropriate concentration of Polyetherimide (PEI). In the process of ZnO nanowires aligment by dielectrophoresis method, the parallel and crossed ZnO nanowire-based devices were achieved by adjusting the frequency and the peak-to-peak voltage of alternating current electrical field. For the CO sensing , the sensing sensitivity and stability of the crossed structure nanowires-based devices were enhanced after annealing. The sensing sensitivity and limit-of-detection of the crossed nanowire-based devices were better than the parallel nanowire-based ones due to the potential barrier modulation at the nanojunctions between two nanowires.
(Invited) RF Power Performance of Nanocrystalline Diamond Coated InAlN/AlN/GaN HEMTs
Authors: Downey Brian P. , Meyer David J. , Ancona Mario G. , Feygelson Tatyana I , Pate Bradford B , Roussos Jason A. , Tadjer Marko J. , Anderson Travis J , Hardy Matthew T , Nepal Neeraj , Eddy Charles R. 
Published: February 2020

While GaN high-electron-mobility transistors (HEMTs) provide the highest achievable RF power densities among all commercially available solid-state technologies, their rated output power densities are typically backed off substantially from the intrinsic limit of the device to ensure robust reliability. Power dissipation during RF operation is typically localized to an area near the drain-edge of the gate. The combination of this “hot spot” and the high electric fields that are present causes acceleration of known degradation mechanisms that limit device lifetime. In order to meet system reliability requirements, the rated output power is therefore constrained to keep the dissipated power, and thus the HEMT channel temperature, below a fixed limit. We previously showed that a high thermal conductivity nanocrystalline diamond (NCD) coating, 0.4 µm to 0.5 µm in thickness, on the top-side of the device nearest to the area of high power dissipation, can reduce channel temperature [1] while improving RF power performance [2] of AlGaN/GaN HEMTs compared to similar devices with SiNx passivation only.
Here we continue this development with new designs that lead to further improvements in reduced junction temperature, RF output power, and operating frequency. The crucial design enhancements introduced here include a combination of thicker NCD coatings (>1 µm) and sub-micron gate lengths. Instead of a conventional AlGaN barrier, an InAlN barrier layer was used to reduce parasitic source/drain resistance, increase transconductance, and support gate lengths for millimeter wavelength operation (>30 GHz). In addition, the InAlN barrier is lattice-matched to GaN, which may provide reliability benefits by reducing the intrinsic strain in the layer compared to an AlGaN barrier. For devices with a 0.75 µm gate length and a 5 µm source-drain spacing, a maximum drain current of 1.8 A/mm, a peak fT
of 29 GHz, and a peak fmax
of 60 GHz was measured. Output power densities exceeded 5 W/mm and 3 W/mm with power-added efficiency of 52% and 42% for 4 GHz and 10 GHz operating frequencies, respectively. The effects of device design on electrical performance and the reduction in junction temperature will be discussed. Thermal simulations will be presented that verify the reduced channel temperature extracted through a calibrated pulsed I-V measurement technique [3] for NCD coated devices.
[1] M.J. Tadjer et al., IEEE Electron Dev. Lett., vol. 33, no. 1, pp. 23-25 (2012).
[2] D.J. Meyer et al., IEEE Electron Dev. Lett., vol. 35, no. 10, pp. 1013-1015 (2014).
[3] J. Joh et al., IEEE T. Electron. Dev., vol. 56, no. 12, pp. 2895-2900 (2009).