bluuebunny/crossref_metadata_2025_split huggingface dataset:
Conductive Atomic Force Microscopy Application for Semiconductor Failure Analysis in Advanced Nanometer Process
Authors: Lin Kun , Zhang Hang , Lu Shey-shi 
Published: December 2020

Abstract
Conductive Atomic Force Microscopy (C-AFM) is a useful tool for both electrical failure analysis (EFA) and physical failure analysis (PFA). In this paper, the root cause of a physical failure in an analysis image was verified from the evidence of two-dimensional AFM profile depth measurement. The other analysis technique, which is electrical parameter extraction by contacting I-V spectroscopy measurement, was also utilized to locate the possible defects. As a result, the failure mechanism was illustrated with an AFM topography image, which showed the silicon surface profile after removal of cobalt salicide (self-alignment silicide) by dilute HF. The vertical junction leakage path was identified with a C-AFM image.
Combine Nanoprobing Technique with Difference Analysis to Identify Nonvisual Failures
Authors: Shen Cha-Ming , Chuang Tsan-Cheng , Chang Jie-Fei , Chou Jin-Hong 
Published: December 2020

Abstract
This paper presents a novel deductive methodology, which is accomplished by applying difference analysis to nano-probing technique. In order to prove the novel methodology, the specimens with 90nm process and soft failures were chosen for the experiment. The objective is to overcome the difficulty in detecting non-visual, erratic, and complex failure modes. And the original idea of this deductive method is based on the complete measurement of electrical characteristic by nano-probing and difference analysis. The capability to distinguish erratic and invisible defect was proven, even when the compound and complicated failure mode resulted in a puzzling characteristic.
Defect Localization Technique for Logic Circuits in Sub 90nm SOI Microprocessors
Authors: Kane Terence , Tenney Michael P. , Bruley John , Boettcher Steven 
Published: December 2020

Abstract
The emergence of multiple core, high speed microprocessors in sub 90nm node technologies present challenges for defect localization, especially in SRAM logic circuits involving Array Built In Self Test (ABIST). Voltage sensitive, temperature sensitive and frequency sensitive soft defects in these ABIST logic circuits can spell the difference between pass and failure, especially for Silicon on Insulator (SOI) designs. High density SRAM arrays with ever shrinking critical dimensions in multiple core, high speed microprocessor designs dictate an increased number of ABIST logic circuits of complex hierarchical design. Scan chain diagnostics to pinpoint the failing scan latch logic circuit following ABIST testing frequently results in ever greater uncertainty; increased number of suspect circuits related to the failure. A case study analysis successfully applied to pinpointing a voltage sensitive logic circuit defect in a 90nm SOI design is described here, followed by root cause TEM analysis.
Fine MCP Decapsulation Technology Development
Authors: Zhou Jianwei , Zheng Wei , Lee Taekoo 
Published: December 2020

Abstract
Multi-Chip Package (MCP) decapsulation is now becoming a rising problem. Because for traditional decapsulation method, acid can’t dissolve the top silicon die to expose the bottom die surface in MCP. It makes inspecting the bottom die in MCP is difficult. In this paper, a new MCP decapsulation technology combining mechanical polishing with chemical etching is introduced. This new technology can remove the top die quickly without damaging the bottom die using KOH and Tetra-Methyl Ammonium Hydroxide (TMAH). The technology process and relative application are presented. The factors that affect the KOH and TMAH etch rate are studied. The usage difference between the two etchant is discussed.
Measurement Techniques for Thermally Induced Warpage to Predict Ball-Grid Array Package-on-Package Solder Compatibility
Authors: Davis Thomas B. , Morrison Mike , Krawzak Thomas , Reeder Jeff , Jiang Tom 
Published: December 2020

Abstract
The semiconductor industry is recognizing an increasing need to define the compatibility of various products joined in package-on-package configuration by solder reflow. Within the scope of the application, this paper discusses: sample preparation; warpage data collection methods; extraction of usable images and numerical data from the measurements; creation of visual warpage patterns for the top and bottom components of stacked package sets; mathematical determination of variation or separation of parts at critical locations during reflow; and finite element analysis of parts and processes to understand and predict reactions to design changes.
Backside 3D Analysis of Power Device Using an ITO Electrode
Authors: Goto Yasunori 
Published: December 2020

Abstract
The power device has a vertical structure and analysis of defective products generally occurs from the backside because the surface is covered in an aluminum electrode and the backside in a metallic electrode. We will discuss the development of backside 3D analysis technique using defective products that emerged due to the marginal valuation of the power device development. First, it was verified that applying a DC voltage uniformly to the entire backside would be effective in placing a glass with an ITO (Indium Tin Oxide) transparent electrode in contact with the backside; therefore it was able to specify a failure point using the IR-OBIRCH (Infra Red-Optical Beam Induced Resistance CHange) method [1]. Then, a micro-sample was extracted without missing the failure point and observed the 3D perspective method; thus it was clear that existence of crystal lattice defects were thought about as the cause of failure.
Automated TEM Sample Preparation on Wafer Level for Metrology and Process Control
Authors: Rijpers Bart , Verkleij Dick , Langer Eckhard 
Published: December 2020

Abstract
As the feature size of semiconductor technology shrinks, cross-section metrology becomes more and more challenging. The generation of cross section metrology data is important for the introduction of new advanced integration schemes, rapid yield learning, and continuous process control for stable manufacturing. In this paper an automated way of TEM cross-section preparation by FIB is described to ensure fast cycle time for preparation and analysis. A dual column FIB/SEM system is used to prepare TEM samples from multiple locations of a 300 mm wafer batch. Subsequently, the TEM lamella is transferred to a grid using an ex-situ lift-out station. Two dedicated applications are shown, a Focus Exposure Matrix (FEM) on patterned photo resist and a process control case study on an etched poly-silicon transistor gate.
Applications of Electron Tomography on Advanced DRAM
Authors: Luo Jian-Shing , Russell Jeremy D. , Huang Lang-Yu , Chen Tsang-Pei 
Published: December 2020

Abstract
It is well known that pursuing the miniaturization of devices to lower the cost and increase high-speed performance are extremely important goals for dynamic random access memory (DRAM). Therefore, electron tomography has a high potential for application to novel generation DRAMs. In this article, several real-case examples of electron tomography on 90 nm technology DRAM, including barrier layer step coverage, via fill process observations and defect analysis are reported. These cases were demonstrated to show the applications of bright field-transmission electron microscope (BF-TEM) and HADDF- scanning transmission electron microscope (STEM) tomography to analyze barrier layer step coverage, defects, and W fill quality in advanced DRAM. By appropriate use of BF-TEM or HAADF STEM tomography, optimal information for failure analysis, root cause clarification, and subsequent process improvements can be obtained. Electron tomography holds significant advantages in comparison to traditional TEM imaging for appropriate cases.
Ultra Low Voltage Probing on 45 nm CMOS by Time Resolved Emission (TRE) Technology
Authors: Young Chi-Lin , Ng Paul , Contreras Francisco , Ispasoiu Radu , Vickers Jim , Cotton Dan , Shaw Chris 
Published: December 2020

Abstract
Ultra low voltage probing by time resolved emission (TRE) technology below 1.0V is very challenging for micro-processor debug in practical operation condition. This is because the photo-emission rate reduces exponentially as the power supply voltage decreases. In this paper, a novel technology with improved detector in solid immersion lens (SIL) TRE system was demonstrated for low voltage and small node probing. An improved detecting scheme was developed to collect 30% more photon detection efficiency than the previous system. The SIL TRE with low dark noise detector technology has been successfully applied to optical probing for 45nm product debug. The performance gain improvement in strong and weak signal regime has been demonstrated against the current detector technology. It has also demonstrated the capability on probing the ultra low voltage at 0.75 V for sub micron node of 45nm process.
The Failure Site Localization Using Absorbed Current Image and Voltage Distribution Contrast
Authors: Nokuo Takeshi , Eto Yoshiyuki , Marek Zane 
Published: December 2020

Abstract
This paper describes the detection range of two failure site localization methods developed by the authors. One method, known as the absorbed current image (AEI) technique, is ideally suited for analyzing test element group interconnects on a huge scale, while the other method, known as voltage distribution contrast (VDIC), works best for interconnects in actual devices which have relatively low resistance.
Series Capacitance in High Speed Differential Pairs – A Failure Analysis Case Study
Authors: Konkol Nicholas 
Published: December 2020

Abstract
Series capacitors, under certain conditions, within high speed differential pair signals were found to have negative effects on mother board functions inside a personal computer (PC). It was noted in one case study that three conditions affected capacitors with this type of application: capacitor aging, DC offset voltage, and cold temperatures. These conditions led to the decrease in capacitance which then disabled the network connection inside the PC. It was concluded that a strategically chosen capacitor type alleviates these conditions. The capacitor type primarily depends on the dielectric material.
Latch-Up Root Cause Analysis for New ASIC Design
Authors: Danielak W. , Machado W. , Jaffer M. , Waldstein S. , Jordan A. , Sachdev M. , Li D. 
Published: December 2020

Abstract
The analyzed new Application Specific Integrated Circuit (ASIC) design failed latch-up test on two input pins during current stress. In order to determine the root cause, the Failure Analysis (FA) with use of backside Emission Microscopy (EMMI) was performed. The EMMI results were followed by detailed layout and circuit analysis. It was found that the root cause of the latch-up is an abutment of two specific cells (called “cell C” and “cell D”), where the N-well was grounded creating a parasitic NPN transistor sustaining the latch-up. A detailed calculation of parasitic interconnection resistances from the layout revealed some differences between latching and non-latching pins. The analytical model to explain the latch-up behavior based on parasitic resistances was applied successfully to root cause analysis. Summarizing, the latch–up behavior can be explained by the abutment of cells C and D, parasitic interconnect resistances and cell location with respect to the substrate bumps. In conclusions the following recommendations were made: 1. Remove the n-well in cell D; 2. Connect specific cells (B and D) to higher supply voltage; 3. Implement p+ guard rings for cells C and D; 4. Optimize placement of ground bumps; 5. Eliminate abutment of cell C and D.
FAMOS Fail Bit Verification/Characterization via NanoProbe
Authors: Dexter Mark , Stallcup Richard , Gunturi Sarma 
Published: December 2020

Abstract
The nanoprobe technique has been widely adapted to many circuit analyses from 6T SRAM bitcells to analog circuit failure analysis. But among the applications widely reported, little has focused on the flash bitcell analysis. This paper presents the more unusual case where fail device isolation is insufficient to determining the defect and/or the root cause. It provides information on measuring floating gate bitcell characteristics and understanding the fail through the customer fail mode and soft programming. In this case, the nanoprobe technique is established to understand the electrical signature of a customer return 1T flash bit fail. By using nanoprobe DC bit characterization, it was determined that data gain failures were due to thin or compromised interpoly dielectric.
Failure Analysis of Breakdown Sites in Silicon Solar Cells
Authors: Breitenstein Otwin , Bauer Jan , Wagner Jan-Martin , Blumtritt Horst , Zakharov Nikolai , Lotnyk Andriy 
Published: December 2020

Abstract
In this contribution the use of electroluminescence imaging, bias-dependent lock-in thermography, special dark and illuminated lock-in thermography techniques, and electron microscopy techniques is demonstrated for investigating the physical mechanism of breakdown in multicrystalline silicon solar cells. Two dominant breakdown mechanisms are identified, which are breakdown at recombination-active crystal defects, showing a relatively soft breakdown, and avalanche breakdown at dislocation-induced etch pits, which occurs very steep (hard breakdown) and dominates in our cells at high reverse bias.
Writing Better Research Reports
Authors: Davis Thomas B. 
Published: December 2020

Abstract
In the world of failure analysis and material characterization, compiling a final report may not be on our priority project list yet we will discover that the layout, syntax, and format of our reports can have as large an impact on the reader as the data we have collected. In an industry where the transmission of valid and understandable information from the lab floor to the requestor is vital, it becomes necessary for each of us to search for resolution to this quandary. In answering the question of how can we write better research documents and reports, this paper will present research to discuss 1) the needs of each group involved with research documents and reports; 2) the difference in expectations between readers and writers; 3) the techniques used to teach report writing; and 4) what makes an effective report. The conclusion of this paper will form a generalized statement of the factors that lead to better-written research documents and reports and will point out areas of consideration for future research.
Instrumental Discrepancy and Relation of Stress Condition between ESD Association and JEDEC Standards on ESD CDM Test
Authors: Satirakul Yuparwadee , Butngam Tanawat , Phunyapinuant Surapol 
Published: December 2020

Abstract
Instrumental difference including characteristic aspects between ESDA and JEDEC standards on CDM test have been investigated and discussed. ESDA test systems provides higher discharge current, lower rise time and lower full width at half maximum at the same stress level, which is due to the higher inductance in the discharge path. We have succeeded in finding out the linear relation of the stress condition between these 2 standards. Furthermore, the current monotonically increases with the stress level for all capacitances and depends on the package size as expected. The relationship between current and package area is proportional because a larger package affords a higher capacitance. The current tends to saturate with a package size over 250 mm2 in both standards. The electrical failure yield of each standard system can be predicted by a stress condition of the other. The stress condition in JEDEC standard is undoubtedly a subset of the ESDA standard.
Picosecond Single-Photon and Femtosecond Two-Photon Pulsed Laser Stimulation for IC Characterization and Failure Analysis
Authors: Pouget V. , Faraud E. , Shao K. , Jonathas S. , Horain D. , Haller G. , Goubier V. , Picart B. , Forli L. , Lewis D. 
Published: December 2020

Abstract
This paper presents the use of pulsed laser stimulation with picosecond and femtosecond laser pulses. We first discuss the resolution improvement that can be expected when using ultrashort laser pulses. Two case studies are then presented to illustrate the possibilities of the pulsed laser photoelectric stimulation in picosecond single-photon and femtosecond two-photon modes.
Volume Electrical Failure Analysis for Product-Specific Yield Enhancement
Authors: Kasapi Steven , Liao Joy , Cory Bruce , Kapilevich Izak , Portune Richard , Ng Yin Shyang , Kardach Cathy , Cheng Elaine 
Published: December 2020

Abstract
Yield on specific designs often falls far short of predicted yield, especially at new technology nodes. Product-specific yield ramp is particularly challenging because the defects are, by definition, specific to the design, and often require some degree of design knowledge to isolate the failure. Despite the wide variety of advanced electrical failure analysis (EFA) techniques available today, they are not routinely applied during yield ramp. EFA techniques typically require a significant amount of test pattern customization, fixturing modification, or design knowledge. Unless the problem is critical, there is usually not time to apply advanced EFA techniques during yield ramp, despite the potential of EFA to provide valuable defect insight. We present a volume-oriented workflow integrating a limited set of electrical failure analysis (EFA) techniques. We believe this workflow will provide significant benefit by improving defect localization and identification beyond what is available using test-based techniques.
Sample Preparation and Analysis on Full-Thickness Silicon Wafers for Wafer-to-Wafer Bonding Process Development
Authors: Young Richard J. , Buxbaum Alex , Senowitz Corey , Deeb C. , Teh W.H. 
Published: December 2020

Abstract
Focused ion beam (FIB) systems use a gallium liquid metal ion source as the source of the ions, providing a typical beam current range of 1 pA to 20-60 nA. Using a reactive gas in addition to the FIB usually enhances the etch rate from 1 to 15 times, but with the combination of xenon difluoride gas and a silicon substrate the enhancement can be over 1000 times. Such an enhancement makes the removal of large volumes of Si more practical, even with the typical upper end of FIB currents of 20-60 nA. This paper discusses the application of full-thickness silicon trenching to the process development of WtW bonding. With the increase in 3DIC, it is expected that fresh process characterization and failure analysis techniques will be required. The work presented shows the feasibility of extending FIB techniques to the process development of wafer-to-wafer bonded samples even on full-thickness wafers.
Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation
Authors: Ng William , Weaver Kevin , Gemmill Zachary , Deslandes Herve , Schlangen Rudolf 
Published: December 2020

Abstract
This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.
Scanning Capacitance Microscopy for Failure Analysis of SOI-Based Advanced Microprocessors
Authors: Huat Lim Soon , Hnin-Ei Lwin , Narang Vinod , Chin J.M. 
Published: December 2020

Abstract
Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.
Tester-Driven Dynamic Laser Stimulation for Hard Functional Failure
Authors: Goh S.H. , Chan Y.H. , Zheng F. , Tan H. , Ting J.W. , Chen Robin , Mai Z.H. , Lam Jeffrey , Hsia L.C. , Chua C.M. , Phang J.C.H. 
Published: December 2020

Abstract
Dynamic Laser Stimulation (DLS) fault isolation techniques involve using an Automated Test Equipment (ATE) to run the device under certain test patterns together and a scanning laser beam to localize sites sensitive to laser stimulation. Such techniques are proven effective for localizing soft failures. In this paper, we demonstrate the feasibility of using such dynamic techniques for functional hard failures and design debug applications. We illustrate experimentally the significance of achieving sufficient signal to noise ratio (SNR) before such applications can be realized effectively, due to the large irregular noise that couples through as the functional pattern is run. We adopted a combination of hardware noise reduction and test program modification to overcome this challenge.
Characterizing Gate Disturb Embedded Flash Memory Cells by Atomic Force Probing
Authors: Hoffmann M. , Nowak C. , Haase A. , Eckl S. 
Published: December 2020

Abstract
There are two known failure mechanisms that cause Gate Disturb failures in flash devices. One main electrically classified failure is the Gate Disturb failure. A second mechanism is the Floating Gate charging caused by high energetic electrons, so-called channel hot electrons, jumping above the energetic barrier of tunnel oxide. This paper describes the characterization of a single transistor Flash cell with the nano-probing approach and introduces a test algorithm to distinguish between these mechanisms at a Gate Disturb affected Flash cell. A Keithley parameter analyzer in combination with Atomic Force Probing (AFP) has been used for the Flash cell device characterization. A Gate Disturb defect can be induced by different defect mechanisms. Two of them, TRAP's in tunnel oxide and channel hot electrons as a result of leaky PN-junctions, were identified as the main root causes. These mechanisms can be distinguished by AFP-analysis with the tests presented in the paper.
Debugging an Invisible Flaky Scan Chain Defect
Authors: Shukla Rahul , Billings Richard , Bakhshi Anurag , Schulze John , Gorti Atchyuth , Tamarapalli Nagesh 
Published: December 2020

Abstract
In general, scan shift failures are difficult to debug. Usually we use the compressed-mode chain test or scan capture-based chain diagnosis to ascertain the small chain segment or the position of the sequential element in the chain that is the cause of the failure. This method of diagnosis works well when the failures are static and limited to a chain segment, but fails to give results when the failure is caused by intra chain or inter chain segment interactions. This paper presents a scenario in which the root cause of the chain failures was due to interaction between chains. We call it the “invisible flaky chain defect” because -- although we were able to replicate failure at a test point (voltage-frequency) on the Shmoo -- the failing cycles changed from run to run.