FinFET Devices and Integration
Authors: Bu Huiming 
Published: February 2020

Through more than a decade of industry wide R&D effort, 3D-FinFET has found its way into manufacturing. In this abstract, we review the key progress in process and integration which has enabled the fabrication of 3D-FinFET on 300mm wafer for mainstream CMOS technology node. The superior short channel electrostatic and reduced random dopant fluctuation from the elimination or reduction of channel doping in FinFET, are both critical to enable aggressive Vdd scaling. Recent progress in channel material innovation towards transport enhancement in Fin architecture has also provided a path to enable a potential high-performance / low-power solution for 7nm node and beyond.

FinFET Process, Module & Integration

IBM and the Joint Development Alliance (JDA) have more than a decade of R&D experience on 3D-FinFET. [1] We have reported previously on solutions to overcome the challenging processes and modules to fabricate FinFET using a state-of-the-art 300mm tool set. [2,3] A patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for Fin formation. The process is carefully optimized to mitigate Fin layout effect. The progress in dry etch has enabled the formation of gate and spacer on 3D-Fin. A novel junction formation technique based on in-situ doped epi has been developed for FinFET for short channel control and external resistance co-optimization. To reduce the extra parasitic capacitance introduced by Fin in addition to device pitch scaling, a low-k material has been implemented for spacer together with aggressive gate height scaling. A co-optimization of source/drain epi and silicide is needed to avoid silicide encroachment and provide good metal/semiconductor contact resistance.
3D-FinFET has been adopted as early as in 22nm node [4,5], though it is generally recognized that FinFET gets its prime time in 16/14nm node industry wise especially in foundry business. [6] The development focus in the industry has now shifted to 10nm node land, which is considered the 2nd generation of FinFET technology.

FinFET Device Design & Scalability

The short channel electrostatic benefit from the 3D gate control in FinFET has been reported in many publications. [2-6] It is worthwhile noting that unlike planar device where short channel effect is strongly modulated by Equivalent Oxide Thickness (EOT) of gate stack, the Fin thickness (Dfin) is the most determining factor in short channel electrostatic in FinFET. [7] It is naturally the choice to explore the benefit of critical dimensions such Fin Pitch (FP) scaling, Fin Height (Hfin) increase, Dfin reduction to fully utilize the performance and density in 2nd generation of FinFET. After the tremendous effort in process, integration, groundrule and device engineering to introduce Fin into FEOL, also of importance is the fact that a BEOL M1/Mx design optimization is needed to accommodate the Fin quantization effect and achieve the density required by technology scaling.
Channel doping has been comprehensively studied and reported as an effective knob for Vt tuning in FinFET with tradeoff in carrier mobility and random dopant fluctuation (RDF). [8] Doping together with gate length modulation as a traditional Vt tuning knob by device designer in planar technology, has provided an acceptable multiVt solution for 1st generation of FinFET. However, RDF has historically been a critical parameter limiting Vdd scaling. Thus Fin scaling benefit has not been fully utilized in the dopant-based multiVt scheme. For the same technical reason, the junction isolation in bulk FinFET is considered a key detractor in the tradeoff between source/drain leakage control and Vdd scaling. [9] Recently we have reported remarkable results on an SRAM array fabricated with SOI FinFET architecture, with full read and write operation down to 400mV, without any assist circuitry. [10] Even though as mentioned before that short channel effect can be further improved with aggressive Dfin scaling, significant Vt variability issue due to quantum confinement effects was reported when Dfin is less than 5nm. [11] Therefore it is inevitable to find alternative isolation solution other than conventional junction isolation for bulk FinFET, and equally important to find non-doping based multiVt solution for both bulk and SOI FinFET to enable aggressive Vdd scaling for advanced technology nodes.

Channel Material Innovation & Next-Gen FinFETs

Compatibility of conventional extrinsic stressor such as eSiGe, SMT were reported in early FinFET R&D. [2,5,12] The drive current enhancement from extrinsic stressors is expected to be less effective due to volume constraint associated with device pitch scaling. We reported lately that unlike extrinsic stressor, the strain generated by channel material is a more effective way to boost short channel device performance in aggressively scaled pitch. [13]
Recently there has been a lot of enthusiasm in the research on high mobility channel materials targeting mainstream CMOS technology application. [14-18] The revival of research on high mobility channel materials such as SiGe, Ge, III-V was firstly triggered by the replacement of thermal oxide by deposited high-k as gate dielectric. Secondly, the successful enablement of 3D-FinFET in mainstream technology has provided a superior device architecture with better electrostatic to explore such materials for short channel device application. Thirdly industry is now on the path actively pursing multiVt and isolation solutions other than conventional doping to enable Vdd scaling. Despite of the tremendous challenges remaining in channel defectivity, gate/channel Dit, junction grading, thermal budge constraint, contact resistance and B2B tunneling associated with high mobility channel materials, it appears the gate has now opened for such materials to be considered as strong contenders for a low-temperature CMOS solution targeting high-performance / low-power application for 7nm and beyond.

Conclusion

In conclusion, we have reviewed recent progress in FinFET device and integration. Several key perspectives are discussed in order to enable further device scaling. High mobility channel materials in FinFET architecture can provide a potential path to high-performance / low-power application with aggressive Vdd scaling.

Acknowledgements

This work was performed by the Alliance Teams at various IBM Research and Development Facilities.

References

[1] E. Nowak et al, IEDM 2002
[2] V.S. Basker et al, Symp. VLSI Tech. 2010
[3] T.Yamashita et al., Symp. VLSI Tech. 2011
[4] C. Auth et al, Symp. VLSI Tech. 2012
[5] C.H. Jan et al, IEDM 2012
[6] S.Y. Wu et al, IEDM 2013
[7] H. Bu et al, SOI conference 2011
[8] C.H. Lin et al, Symp. VLSI Tech. 2012
[9] H. Bu et al, SOI conference short course 2012
[10] T. Hook et al, http://www.advancedsubstratenews.com/2013 /11/finfet-on-soi-potential-becomes-reality/
[11] J.B. Chang et al, VLSI 2011
[12] C.C. Wu et al, IEDM 2010
[13] A. Khakifirooz et al, SOI conference 2013
[14] R. Pillarisetty et al, IEDM 2010
[15] M. Radosavljevic et al, IEDM 2010
[16] P. Hashemi et al, VLSI 2013
[17] B. Duriez et al, IEDM 2013
[18] Y. Sun et al, IEDM 2013