bluuebunny/crossref_metadata_2025_split huggingface dataset:
Application of Soft Defect Localization Technique for SRAM Soft Failure Debug
Authors: Je Moon Seung , Lian Yeoh Boon , Huat Goh Szu , Chithambaram Shaalini , Quah A.C.T , Lam Jeffrey 
Published: December 2020

Abstract
Dynamic Laser Stimulation (DLS) technique have met with great success over the past few years in helping failure analysis engineer to tackle different type of soft failures. DLS is widely applied to devices presenting an abnormal behavior for any electrical parameter, such as operating voltage and frequency. This paper showcase another successful implementation of DLS technique, combined with design analysis to reveal the root cause for SRAM soft failure.
Continuous-Wave 1064 nm Laser for Laser Voltage Imaging and Probing Applications
Authors: Ravikumar Venkat-Krishnan , Phoa Angeline , Sabbineni Prasad , Skvortsov Dmitry , Lundquist Ted 
Published: December 2020

Abstract
Laser-voltage probing (LVP) and imaging (LVI) using a continuous-wave (CW) 1320-1340nm laser have become mainstream techniques for electrical fault isolation. A 1064nm laser with a 20% shorter wavelength offers immediate resolution advantages compared to 1320nm at a cost of increased intrusion. This paper explores the potential of CW 1064nm laser and identifies opportunities in fault isolation
Development of DPA (Destructive Physical Analysis) Method for Cu Wire Device
Authors: Tateyama Hirohumi , Shimizu Wataru , Kubota Hidehisa , Murahara Daisuke , Hattori Tamiko , Ootani Naoki , Yasuda Yujiro , Yabe Kazuhiro 
Published: December 2020

Abstract
Destructive physical analysis (DPA) is one of the reliability evaluation methods, which observes defects and faults in a device, and it can classify the reliability level of the device. After a description of the current method for Au wires, this paper explains the DPA for a Cu wire device. The DPA for semiconductor devices is divided roughly into three steps: a non-destructive inspection, an assembly process inspection, and a wafer process inspection. Investigation of DPA for Cu wire device includes wire material identification, optimization of decapsulation for Cu wire device and wire pull strength test, and observation of package cross-section. From the result, novel sample preparation (embedding a sample in molding package and forming the package to be suitable for cross-sectional observation by ion polishing) enables the observation of the thin alloy layer at the wire/pad interface.
A Case Study on the Benefits of Functional Memory Access during ATE Test and Electrical Fault Isolation Techniques for Embedded SRAM
Authors: Goodrich Corey 
Published: December 2020

Abstract
Test coverage of embedded memories is often split between test modes. A BIST solution is typically used to isolate and test the memory array through test specific ports. The functional interconnect between logic and memory is tested with traditional ATPG test modes where a bypass cell on the scan chain is used to clock data through the memory. This approach may miss test coverage if the functional path is different from the test path[1]. Although commercial ATPG tools provide some capability in this area, the most advanced type of fault models which target small delay defects or cross talk faults are not as streamlined as they are for traditional fault models. Additionally, more advanced fault types don’t typically have the same diagnostic capability. In this paper, capabilities are developed for maximizing the effectiveness of test on embedded SRAM interconnects in an ATPG context. Also, a method is outlined to characterize and validate the timing robustness of the memory ports and provide a silicon diagnostic capability for localizing critical paths and isolating physical defects.
Functional Electronic Clones—The Most Dangerous New Counterfeit Threat Facing the Entire Electronics Industry Today
Authors: Sharpe Thomas 
Published: December 2020

Abstract
The entire electronics industry is now facing a much more insidious counterfeit threat than at any time in the past. The existence of cloned electronic components bearing the markings of major component manufacturers in today’s global supply chains has been clearly established within SMT’s labs over the past 3 years. The most worrisome aspect of these “made from scratch” fakes is their ability to easily pass current Industry-Standard counterfeit inspection processes and electrical testing to the manufacturers’ data sheet. My presentation will focus on several actual examples of this most concerning advanced counterfeiter capability and some of the processes utilized by SMT as an obsolescence component supplier and testing lab to mitigate this new and growing threat from making it to our OEM & CM customers.
In-Line Detection of Deep Trench Moat Underetch Defects Using eBeam Inspection
Authors: Hafer Richard F. , Messenger Brian , Dekker Mark T. , Patterson Oliver D. , Feng Yi , Lei Shuen-Cheng , Tang Xiaohu 
Published: December 2020

Abstract
E-beam Inspection (EBI) is used for in-line detection of defects in semiconductor manufacturing. This paper highlights a physical defect mode application where traditional defect inspection techniques, such as broadband plasma and dark field inspection were ineffective in finding the defects of interest. It describes the inspection setup and verification with failure analysis and the application of the technique. This inspection was implemented as a process monitor to detect excursions. The amount of process "ON" time after an etch-chamber part's change was identified as the main factor in MOAT defectivity. The correlation between EBI defect detection and leakage at in-line electrical test was further investigated by looking at each individual die and the leakage associated with the MOAT only. It was observed that the increased leakage could be due to another process factor in the process than a MOAT etch or a MOAT defect that was missed during the EBI inspection.
Studies on a Qualification Method (OSSD) for Microchip Al Bondpads
Authors: Younan Hua , Yue Shen , Yixin Chen , Chao Fu , Xiaomin Li 
Published: December 2020

Abstract
In authors’ previous paper, an OSAT [Optical, SEM (Scanning Electron Microscopy), Auger (Auger Electron Spectroscopy) and TEM (Transmission Electron Microscopy)] methodology was developed for qualification of microchip aluminum (Al) bondpads. Using the OSAT methodology, one can qualify microchip Al bondpads. In this paper, we will further study the NSOP (Non-Stick On Pad) problem on microchip Al bondpads. A new qualification methodology, OSSD [(Optical, SEM, and Surface and Depth profiling X-ray Photoelectron Spectroscopy (XPS)] will be proposed, in which XPS surface analysis is used to check the contamination level of fluorine and carbon on bondpad surfaces instead of Auger analysis. XPS depth profiling analysis will also be used to measure Al oxide thickness instead of TEM analysis. By using OSSD, Al bondpads can be qualified with both reduced costs and shortened turnaround times versus OSAT.
Carrier Redistribution Analysis of Gate-Biased SiC Power-MOSFET Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy
Authors: Chinone Norimichi , Cho Yasuo 
Published: December 2020

Abstract
Gate-bias dependent depletion layer distribution and carrier distributions in cross-section of SiC power MOSFET were measured by newly developed measurement system based on super-higher-order scanning nonlinear dielectric microscope. The results visualized gate-source voltage dependent redistribution of depletion layer and carrier.
Failure Modes Associated with Plastic Packages and Copper Bond Wires
Authors: Berger Kevin , Lilani Sultan Ali 
Published: December 2020

Abstract
The Aerospace and Defense (A&D) markets are starting to use plastic packages more significantly for Space and Military ruggedized applications. But plastic packages are also inherently less reliable than ceramic devices for A&D applications. The key to the successful use of plastic devices in A&D application is to qualify the devices for the intended application using industry accepted plastic encapsulated microcircuit (PEM) qualification techniques. This paper briefly recaps the test techniques known to be effective in assessing plastic part reliability. But more importantly, it presents actual PEM qualification data gathered over the last 15 years involving over 400 individual PEM Qual lots. The paper also shows the failures modes associated with plastic packages and Cu bond wires. SEM, X-Ray, and Acoustic Microscope images were obtained for the failure modes associated with plastic packages and Cu bond wire.
X-Ray Microscopy and Root Cause Analysis in Electronic Packaging
Authors: Mirkarimi L. , Gu A. , Hunter L. , Guevara G. , Huynh M. , Katkar R. 
Published: December 2020

Abstract
Advances in electronic packaging are fueled by the insatiable appetite that consumers have for bandwidth in mobile appliances. The technological answer to this demand is increase the interconnect count and shrink the pitch, solder volume and height. The features of interest and the defects in these packages are becoming increasingly smaller. Consequently, the characterization of these defects becomes more challenging due to the smaller size and new material structures. New package structures must pass the JEDEC standard tests and a critical part of qualifying new packages as products is proper identification of the root cause of failures. Therefore, innovative solutions to correct the fundamental problems in the development process enable new package solutions to be brought to the market. In this paper we describe an alternative failure analysis workflow involving X-ray microscopy which offers several advantages over standard imaging techniques. The nondestructive nature of x-ray microscopy enables engineers to image parts throughout the entire environmental stress cycle for more accurate determination of the root cause of failures. Additionally, a larger number of interconnects may be sampled, defect isolation in z direction for stacked die packages is made easier and subsequent imaging techniques may be used to complement the data. Both 3 dimensional images of defects as well as 2 dimensional cross sections will be shown to effectively analyze the true root cause of failures.
Root Cause Analysis of a Connector Time-Delayed Fracture
Authors: Singh Prabjit , Yu Ying , Davis Robert E. 
Published: December 2020

Abstract
A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.
Adaptive Grinding and Polishing of Silicon Integrated Circuits to Ultra-Thin Remaining Thickness
Authors: Chivas Robert , Silverman Scott , DiBattista Michael 
Published: December 2020

Abstract
Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. Ultra-thin RST enables VIS light techniques such as laser voltage probing. In this work we investigate the lower RST limit due to sub-surface damage from grinding and a one-step polishing method to achieve 3 um RST (+/- 0.8 um) over 121 mm2 die (11 x 11 mm) test package as well as 5 um (+/- ) over 109.2 mm2 (8.0 x 13.7mm) active device.
Study on Effect of Electron Beam Irradiation in SEM-Based Nanoprobing on MOS Transistor
Authors: Noriko Hara , Nanami Bito , Mai Ebisuda , Suguru Tabata , Naoki Numazaki , Kazunori Masuda , Naoya Kami 
Published: December 2020

Abstract
Nanoprobing is an indispensable method for failure analysis to identify failure cells and to approach the root causes, providing electric characteristics of the failure of the MOS transistor. In this paper, the characteristic degradation on MOS transistors with SEM-based nanoprobing is studied to find out the critical accelerating voltage, comparing it to the characteristic obtained by the mechanical prober. In this experiment, n-type MOS transistors with thick gate oxide layer (40nm) were used. The effect of electron beam irradiation was also investigated. Significant change was not observed in n+(drain)/p-well IV curves. The paper looks at the influence of the additional phenomena during SEM-based nanoprobing analysis on a characteristics change of a specimen. For MOS transistor with thick gate oxide used in this study, irradiation influence is possibly more notable than normal voltage cell cases.
Analysis of SRAM Function Failure Due to Unformed CoSi2 Using Nanoprober and Transmission Electron Microscopy
Authors: Kim Jong Eun , Lee Jong Hak , Cho Jong Kyu , Ban Sang Hyun , Park Chang Su , Kim Nam Il , Kim Dae Woo , Wi Su Cheol , Sa Seung Hoon , Kim Sung Man , Kim Do Hwan , Lee Jae Won , Cho Min Su , Park Dong Bin , Park Ji Suk , Yi Su Hyun , Ha Jae Beom , Byun Kyung Su , Gu Tae Lim , Sung Jin Woo , Lee Jong Hwan , Son Soo Yong , Park Tae Su , Kim Jong Chae , Cho In Wook 
Published: December 2020

Abstract
In this article, an analysis of a failure in the embedded SRAM in a CMOS Image Sensor is investigated. The failure was due to unformed CoSi2. Because unformed CoSi2 causes a varying degree of response, a nano-prober was used to find the abnormally operating transistors among a 1-bit SRAM cell consisting of six transistors(6T). After measuring and analyzing the current-voltage relationships between each transistor, the current magnitude of one pull-down transistor was found to be less than the expected range and particularly lower than that of a connected access transistor. To visualize the failure phenomenon and find the root cause of this, TEM analysis was conducted. Using the EELS (Electron Energy Loss Spectroscopy) elemental mapping, unformed CoSi2 was detected between the contact and substrate, where the contact corresponds to the VSS of the pull-down transistor. This caused an increase in the contact resistance, thus lowering the current magnitude of the abnormal transistor to a greater degree than expected.
Visible Light Probing Sample Thinning Using Targeted Lapping
Authors: Schlangen Rudolf , Lo William , Li Jane , Halteh Elia , Aguada John , Yang Jessica , Marks Howard 
Published: December 2020

Abstract
Visible Light (or Laser) Probing (VLP) is an exciting new development in Laser Voltage Probing (LVP) technology because it promises a dramatic improvement in resolution over current Near Infrared (NIR) solutions [1-3]. To have adequate visible light transmission for waveform probing and modulation mapping, however, ultrathinning of the silicon backside to &lt;2-5 μm is required. The use of solid immersion lens (SIL) technology places additional requirements on sample preparation. In this paper, we present a simple, SIL compatible technique for VLP sample preparation.
Studies on a Novel Qualification Method of Silicon Nitride Layer
Authors: Hua Younan , Khoo Bingsheng , Leong Henry , Chen Yixin , Chan Eason , Wang Jingyuan , Li Xiaomin 
Published: December 2020

Abstract
In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.
Decapsulation of IC Package by Atmospheric Microwave Plasma Needle
Authors: Kral Martin , Tsujita Yoichi , Suzuki Satoshi , Yamaichi Yasutoshi , Kando Masashi , Blajan Marius Gabriel 
Published: December 2020

Abstract
We present experimental results of IC package decapsulation carried out using Ar and O2 gas mixture remote plasma generated by atmospheric microwave plasma needle (“a-MPN”). Depth etch rate of up to 6.5 µm/min and volume etch rate of up to 0.1 mm3/min were shown to be obtained by a-MPN process operated at 15 W microwave power. SEM imaging suggested no damage to the bonding wire, pads, or passivation.
Failure Localization in a Multistage S-Band Power Amplifier
Authors: Rebello Clarence , Kolasa Ted , Modi Parag 
Published: December 2020

Abstract
During the search for the root cause of a board level failure, all aspects of the product must be revisited and investigated. These aspects encompass design, materials, and workmanship. In this discussion, the failure investigation involved an S-Band Power Amplifier assembly exhibiting abnormally low RF output power where initial troubleshooting did not provide a clear cause of failure. A detailed fault tree drove investigations that narrowed the focus to a few possible root causes. However, as the investigation progressed, multiple contributors were eventually discovered, some that were not initially considered.
Measuring the Effect of FIB Diffusion Exposure/Damage with a Gallium Focused Ion Beam for Semiconductor Circuit Edit Applications
Authors: Jain Rajesh , DiBattista Michael 
Published: December 2020

Abstract
Shrinking transistor geometries present ongoing challenges for backside FIB circuit edit operations. The available space to gain access to critical signal lines has diminished to the order of hundreds of nanometers. Several previous works have shown that the diffusion of active devices can be exposed. This paper explores the effects of exposing and selectively damaging the active diffusion layer of advanced finFET process technology. STEM cross section images show that the devices are unaffected when the silicon substrate is on the order of 1-2ums. When the silicon substrate is removed to less than 100nm, the effect can be seen electrically on a set of ring oscillators.
3D Fault Isolation in 2.5D Device Comprising High Bandwidth Memory Stacks and Processor Unit Using 3D Magnetic Field Imaging
Authors: Orozco Antonio , Rusli Florencia , Rowlett Christopher , Zee Bernice , Qiu Wen , Chin J.M. , Foo Fang-Jie 
Published: December 2020

Abstract
Process challenges and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered delays, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. These 3D devices (System-in-Package (SiP), wafer-level packaging, Through-Silicon-Vias (TSV), stacked-die, etc.) present major challenges for Failure Analysis (FA) that require novel nondestructive, true 3D Failure Localization techniques. 3D Magnetic field Imaging (MFI), recently introduced, proved to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allowed for submicron vertical resolution. In this paper, we apply this novel technique for 3D localization of an electrically failing complex 2.5D device combining 4Hi-High Bandwidth Memory (HBM) devices and a processor unit on a Si interposer.
Automated Emission Data Registration and Segmentation for IC Analysis
Authors: Stellari Franco , Song Peilin 
Published: December 2020

Abstract
In this paper, the development of advanced emission data analysis methodologies for IC debugging and characterization is discussed. Techniques for automated layout to emission registration and data segmentations are proposed and demonstrated using both 22 nm and 14 nm SOI test chips. In particular, gate level registration accuracy is leveraged to compare the emission of different types of gates and quickly create variability maps automatically.
Making Synchrotron Tomography a Routine Tool for 3D Integration Failure Analysis through a Limited Number of Projections, an Adapted Sample Preparation Scheme, and a Fully-Automated Post-Processing
Authors: Fraczkiewicz A. , Moreau S. , Mourier T. , Bleuet P. , Autran P.-O. , Capria E. , Cloetens P. , Da Silva J. , Lhostis S. , Lorut F. 
Published: December 2020

Abstract
3D integration takes more and more importance in the microelectronics industry. This paper focuses on two types or objects, which are copper pillars (25 micrometer of diameter) and hybrid bonding samples. It aims at a statistical morphology observation of hybrid bonding structures, which underwent an electromigration test at 350 deg C and 20 mA. The goal of the study is two-fold. It is both to limit the overall time needed to perform a whole process flow, from sample preparation to reconstructed volume, and to limit the time of human intervention. To achieve this goal, three strategies are presented: improving the sample preparation scheme, reducing the number of projections with iterative algorithms and the Structural SIMilarity function, and automating the post-processing. The post-processing of the data is fully automated and directly renders the reconstructed volume. The high signal to noise ratio allows for further segmentation and analysis.
A Review of Well Imaging Techniques
Authors: Johnson Gregory M. , Nxumalo Jochonia , D’Aleo Christopher , Yates Brian , Khan Zaheer , Mollela Christopher 
Published: December 2020

Abstract
The timely and accurate imaging of problems in p/n junctions is increasingly important. Scanning Capacitance Microscopy is a current standard for precise 2D-mapping of carrier profiles, but care must be taken to choose the correct field of view because of the slow scan time. This paper provides commentary on the usefulness and possible pitfalls of a wide range of techniques available to the modern FA analyst, with examples from problem solving in a process development environment. SEM passive voltage contrast may provide imaging of junctions, but may be limited to N-well / P-well after special sample prep. OBIRCH provides reliable information on any current flows, but may not be selective specifically to those involving junction problems. Electron Beam Induced Current provides junction information at SEM resolution, but it may be hard for subtle problems to not be swamped out by massive signals. Multi-photon OBIC shows promise for high-resolution laser-based imaging, but may require highly special wiring. Photon Emission is an old standby. A case study is given which shows that one must be careful to match camera type and defect mechanism type in order to be able to see actual junction leakage.
Debugging Signal Corruption in Scan Chain Using Phase Laser Voltage Imaging
Authors: Ranganathan G. , Ravikumar V.K. , Phoa S.L. , Nemirow C. , Leslie N. 
Published: December 2020

Abstract
Laser Voltage imaging (LVI) is an established and widely used technique for isolating scan chain failures, especially those that are stuck-at a particular state. Enhancements such as second harmonic mapping have been beneficial in detecting a fault that is not stuck, but caused a shift in duty-cycle of the injected signal. In this paper, we describe Phase LVI which is constructed by integrating a lock-in amplifier as an enhancement to LVI for studying the relative phases between scan flops. Additionally we showcase case studies of successful fault isolation using phase LVI, where traditional LVI techniques were not successful.