bluuebunny/crossref_metadata_2025_split huggingface dataset:
Instant Solid Immersion Lens Creation in Silicon with a Focused Ion Beam – Comparing Refractive and Diffractive Methods
Authors: Scholz P. , Kerst U. , Boit C. , Kujawa T. , Lundquist T. 
Published: December 2020

Abstract
The theoretical fundamentals of diffractive solid immersion lenses (dSILs) were revised and adapted to a new application: the direct single-step chemistry-assisted creation of binary dSILs in silicon with a focused ion beam (FIB). Current results were able to prove the general functionality of this technique, but also showed the limitations still present. These limitations were identified; the underlying problems were analyzed and were addressed by optimizing several aspects of the process. The presented dSIL has a diameter of 150 ìm and is created in 15 minutes of processing time. It is designed for a sample thickness of 70 µm, which can be well adjusted if needed. For this sample thickness, the theoretical numerical aperture is about 2.5, offering a significant improvement in resolution. Furthermore a comparison of diffractive and refractive solid immersion lenses is presented, both created in a similar process. Apart from general aspects of dSILs and rSILs (refractive SILs), details of the designs presented in this work are compared. This leads to the insight of which method (dSIL or rSIL) has its advantages for which type of application.
3DIC Fault Isolation Using the OBIRCH Approach
Authors: Hsu Ming-Sung , Kuo Yian-Liang , Lin Yu-Ting , Huang Ru-Ying , Ku Min-Feng , Chang Chih-Horng 
Published: December 2020

Abstract
This paper uses an interesting specific case study to highlight the non-destructive fault isolation demonstration of 3DIC stacked dies applied the optical beam induced resistance change (OBIRCH) approach.
Addressing Stress-Memorization-Technology (SMT) Induced Defects
Authors: Kane Terence , Wang Yun Yu , Tenney Michael , Oldrey Richard , Villalobos Manuel , Sylvestri John , Tverskoy Genadi 
Published: December 2020

Abstract
High performance source/drain (S/D) stress-memorization technology (SMT) has been previously demonstrated to enhance electron mobility in leading edge SRAM NMOS designs. Dislocations initiating from SMT induced stacking faults cause electrical fails in the device. Transmission electron microscopy (TEM) results show that these dislocations can be reduced by controlling certain processing steps following SMT processing.
Electroless Cobalt Plating on Copper Structures for Nano-Probing
Authors: Chuang Wen-Hsien , Zhong Ting , Niu Baohua 
Published: December 2020

Abstract
As device dimensions continue to shrink, process defects tend to become more subtle. For most failure analysis (FA) studies, it is important to identify the defect location for the subsequent material analysis. To achieve this, nano-probing has been widely used in the FA community. Copper (Cu) contacts posed a significant challenge to nano-probing since Cu is soft and tends to deform during measurements. In addition, Cu oxidizes quickly in air, increasing contact resistance significantly between the probes and devices. This paper introduces electroless cobalt (Co) plating on Cu contacts for nano-probing to overcome these technical problems. As Cu is soft and oxidized quickly in air, the technique presented in this paper provides a technical solution for nano-probing on Cu contacts. With carefully characterized Co plating time, this technique can be used not only on Cu contacts but also on Cu interconnection.
CHIPSCANNER: Reverse Engineering Solution for Microchips at the Nanometer-Scale
Authors: Klingfus Joseph , Burcham Kevin , Rasche Martin , Borchert Thomas , Damnik Niklas 
Published: December 2020

Abstract
Chipscanning is the high-resolution, large-area, SEM image capture of complete (or partial) IC devices. Images are acquired sequentially in matrix-array fashion over an area of interest and large image mosaics are created from the collection of smaller images. Chipscanning is of keen interest to those involved with component obsolescence, design verification, anti-counterfeiting, etc. Chipscanning, and subsequent processing of the images, can also be used to reverse engineer an IC device. The reverse engineering process can be broken down into three main tasks; sample preparation, data collection, and data processing. We present practical insight into the data collection and data processing tasks and discuss an instrument platform uniquely suited for imaging such devices.
Advanced Physical Analysis Methodology for Yield and Reliability of 28-nm, Bulk-Si, Flip-Chip ICs Using SEM and Backside Deprocessing
Authors: Li Yuanjing (Jane) , Scott Steven , Marks Howard Lee 
Published: December 2020

Abstract
This paper presents a backside chip-level physical analysis methodology using backside de-processing techniques in combination with optimized Scanning Electron Microscopic (SEM) imaging technique and Focused Ion Beam (FIB) cross sectioning to locate and analyze defects and faults in failing IC devices. The case studies illustrate the applications of the method for 28nm flip chip bulk Si CMOS devices and demonstrate how it is used in providing insight into the fab process and design for process and yield improvements. The methods are expected to play an even more important role during 20-nm process development and yield-ramping.
Study of Si Crystal Defects by Chemical Preferential Etching and Its Application on Si Dislocation Defects Caused by Laser Spike Annealing (LSA)
Authors: Shuting Chen , Lihong Li , Anyan Du , Younan Hua 
Published: December 2020

Abstract
In this work, delineation of crystal defects in Si by preferential chemical etching (Wright etch) is discussed. Investigation of defects in Si wafers by preferential chemical etching enables the study of various types of crystal defects for large area defect distribution (up to full wafer) and root cause analysis. In the case of dislocation defects, the shapes of etch pits are different for different etching duration. We show the mechanism of the pit shape evolution under preferential etching and suggested the appropriate etching duration for defect type identification with inspection by optical microscopes. The dislocation delineation method has been applied to a case of functional failure of devices caused by abnormal process in Laser Scanning Annealing (LSA). It was shown that the distribution of dislocation defects depends largely on the direction of LSA scan direction. We discuss the relationship between dislocation defect distribution and the density and uniformity of the active-Si patterns as well as possible solutions for elimination of dislocation defects in LSA process.
Four Stages of Defect Creation in Epitaxial Structures: High Resolution X-Ray Diffraction and Transmission Electron Microscopy Characterization
Authors: Faleev Nikolai N. , Honsberg Christiana B. , Smith David J. 
Published: December 2020

Abstract
Different epitaxial structures have been studied by high-resolution x-ray diffraction and x-ray topography, Transmission Electron Microscopy and Atomic Force Microscopy to establish correlations between epitaxial growth conditions and crystal perfection. It was confirmed that epitaxial growth under initial elastic stress inevitably leads to the creation of extended crystal defects like dislocation loops and edge dislocations in the volume of epitaxial structures, which strongly affect crystal perfection and physical properties of future devices. It was found that the type of created defects, their density and spatial distribution strongly depended on growth conditions: the value and sign of the initial elastic strain, the elastic constants of solid solutions, the temperature of deposition and growth rate, and the thickness of the epitaxial layers. All of the investigated structures were classified by their crystal perfection, using the volume density of extended defects as a parameter. It was found that the accommodation and relaxation of initial elastic stress and creation of crystal defect were up to four stages “chain” processes, necessary to stabilize the crystal structure at a level corresponding to the deterioration power of particular growth conditions.
Non-Chemical Solder Bump Removal Technique for Repackaging Flip Chip ICs
Authors: Sutton Mauri , Geoghegan George , Schopen Kenneth , Kingma Kathleen , Castro Steve , Wesley Kyle , Yahl Jack , Soto Frank 
Published: December 2020

Abstract
In this paper we will discuss an empirically discovered technique to remove residual solder bumps or remnants using reflow and wicking to a gold plated surface rather than mechanical or chemical means. Extraction of flip chip ICs, for the purpose of repackaging, can leave bond pads in inconsistent and undesirable conditions such as 1) retaining remnants of the solder bumps or 2) damaged or eliminated pad metal caused by acid or mechanical means used to separate the IC from the board. These conditions hinder subsequent wire bonding and probe card use. Though other techniques have been found to be suitable at times, the technique described in this paper consistently leaves the bonding area in an acceptable, more predictable condition, as the bulk of the solder bump material is removed. This lends to a higher wire bonding success rate.
VIS-NIR LED Illumination in Backside Circuit Edit and Optical Probing Applications
Authors: Tan Shida , Livengood Richard H. , Scott Dane , Hallstein Roy , Pardy Pat , Giacobbe John 
Published: December 2020

Abstract
High resolution optical imaging is critical in assisting backside circuit edit (CE) and optical probing navigation. In this paper, we demonstrated improved optical image quality using VIS-NIR narrow band light emitting diode (LED) illumination in various FIB and optical probing platforms. The proof of concept was demonstrated with both common non-contact air gap lenses and solid immersion lenses (SIL).
Novel Failure Analysis Sample Preparation Techniques for PoP Packaging
Authors: Chooi Ng Sea , Hock Chor Theam , Thye Ma Choo , Tshin Khoo Poh , Bockelman Dan 
Published: December 2020

Abstract
Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.
Simulation Studies on Fluorine Spec Limit for Process Monitoring of Microchip Al Bondpads in Wafer Fabrication
Authors: Hua Younan , Rao Nistala Ramesh , Yang Yanjing , Zhao Siping , Shailesh Redkar 
Published: December 2020

Abstract
In wafer fabrication, Fluorine (F) contamination may cause fluorine-induced corrosion and defects on microchip Aluminum (Al) bondpads, resulting in bondpad discoloration or non-stick on pads (NSOP). Auger Electron Spectroscopy (AES) is employed for measurements of the fluorine level on the Al bondpads. From a Process control limit and a specification limit perspective, it is necessary to establish a control limit to enable process monitor reasons. Control limits are typically lower than the specification limits which are related to bondpad quality. The bondpad quality affects the die bondability. This paper proposes a simulation method to determine the specification limit of Fluorine and a Shelf Lifetime Accelerated Test (SLAT) for process monitoring. Wafers with different F levels were selected to perform SLAT with high temperature and high relative humidity tests for a fixed duration to simulate a one year wafer storage condition. The results of these simulation results agree with published values. If the F level on bondpad surfaces was less than 6.0 atomic percent (at%), then no F induced corrosion on the bond pads was observed by AES. Similarly, if the F level on bond pad surfaces was higher than 6.0 atomic per cent (at%) then AES measured F induced corrosion was observed.
Surface Microstructure Evolution Upon Silicidation of Ni(Pt) and the Different Responses to Metal Etch
Authors: Qin Wentao , Iyer Dorai , Morgan Jim , Casteel Carroll , Watkins Robert , Crowder Rod , Thomason Mike 
Published: December 2020

Abstract
Ni(5 at.%Pt ) films were silicided at a temperature below 400 °C and at 550 °C. The two silicidation temperatures had produced different responses to the subsequent metal etch. Catastrophic removal of the silicide was seen with the low silicidation temperature, while the desired etch selectivity was achieved with the high silicidation temperature. The surface microstructures developed were characterized with TEM and Auger depth profiling. The data correlate with both silicidation temperatures and ultimately the difference in the response to the metal etch. With the high silicidation temperature, there existed a thin Si-oxide film that was close to the surface and embedded with particles which contain metals. This thin film is expected to contribute significantly to the desired etch selectivity. The formation of this layer is interpreted thermodynamically.
Two-Photon-Absorption-Enhanced Laser-Assisted Device Alteration and Single-Event Upsets in 28 nm Silicon Integrated Circuits
Authors: Serrels K.A. , Leslie N. , Lundquist T.R. , Vedagarbha P. , Erington K. , Bodoh D. , Farrell C. , Reid D.T. 
Published: December 2020

Abstract
By inducing two-photon absorption within the active layer of a 28nm test chip, we demonstrate nonlinear laser-assisted device alteration and single-event upsets by temporarily perturbing the timing characteristics of sensitive transistors. Individual qualitative and quantitative evaluations are presented for both techniques, with lateral resolutions demonstrated with sub-100nm performance. A simplistic signal response rate comparison analysis of these two technologies is also presented.
Physical and Electrical Performance Comparison of Identical 28 nm Qualcomm Telecommunication Die Produced by Samsung and TSMC
Authors: Riley Anton , Zumwalt Sean , Dixon-Warren Sinjin , Tomkins Gary 
Published: December 2020

Abstract
In today’s competitive semiconductor environment, product performance and market timing has never been more valuable. Design IP, speed to market, and taking advantage of the most advanced technology are three ways fabless companies can maintain an advantage over the competition. Foundries target these demands by offering superior support, competitive technology, and rapid development cycles. Using the advanced tool suites of SEM, FIB, TEM, and Atomic Force NanoProbing (AFP) the failure analysis community now has the ability to investigate and compare foundry performance on the device level. The 28 nm LP Qualcomm “SHELBY” die is dual-sourced from both Samsung and TSMC, and is the primary die in the MDM9215 4G/LTE modem used in several smartphones. This represents a unique case of leading technology, available to the public, to qualify for electrical performance on the device level using the AFP and the corresponding physical differences using SEM and TEM. These advanced FA techniques were employed and were able to identify manufacturing differences between foundries. They were then used to relate the physical variations with the electrical device performance. The HG11-N3877 fabricated by TSMC and the HG11-N9204 fabricated by Samsung were the subjects of this comparison (see Error! Reference source not found.). The investigation located spatial and geometric variations of the SRAM devices using cross sectioning and TEM imaging. This was followed by Electrical Characterization of multiple SRAM Cells using the AFP. The electrical measurements showed clear differences in device parameters. These differences highlight manufacturing process differences between the two companies that could directly relate to chip performance.
dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits
Authors: Pendyala Sweta , Albert Dave , Hawkins Katherine , Tenney Michael 
Published: December 2020

Abstract
Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.
32 nm CMOS SOI Test Site for Emission Tool Evaluation
Authors: Weger Alan J. , Stellari Franco , Kim Seongwon , Ainspan Herschel A. , Kwark Young , Baks Christian W. , Maliuk Dzmitry , Song Peilin 
Published: December 2020

Abstract
We describe a test chip designed and fabricated in 32nm CMOS SOI. The test chip was developed to assist in the characterization and testing of hot electron emission based test systems for both existing and forthcoming technology nodes, and contains circuit structures of increasing density and complexity. We also describe some unique circuit functions that may be of use in other applications
Realizing Dynamic Thermal Laser Stimulation by Lock-in IR-OBIRCH Assisted with a Current Detection Probe Head
Authors: Wu Chunlei , Yao Suying 
Published: December 2020

Abstract
Lock-in IR-OBIRCH analysis, as a kind of static thermal laser stimulation (S-TLS) technique, is very effective to isolate a fault for the parametric failure cases. However, its capability is limited to localize a defect when the IC is operated under a defined operating condition. Whereas the dynamic thermal laser stimulation (D-TLS) technique is good at locating a fault while the IC is operated under some functions to activate the failure. In this paper, a novel method is presented to realize DTLS just by Lock-in IR-OBIRCH assisted with a Current Detection Probe Head. Two cases are studied to demonstrate the effectiveness of this method.
Silicon Fringe Sample Metrology—A Thickness Measurement Technique
Authors: Kimball Mark 
Published: December 2020

Abstract
Silicon’s index of refraction has a strong temperature coefficient. This temperature dependence can be used to aid sample thinning procedures used for backside analysis, by providing a noncontact method of measuring absolute sample thickness. It also can remove slope ambiguity while counting interference fringes (used to determine the direction and magnitude of thickness variations across a sample).
A Sample Preparation Methodology for Effective Failure Analysis of Trench Power MOSFET
Authors: Li Yan , Loh S.K. , Chen C.Q. , Ang G.B. , Quah A.C.T. , Neo S.P. , Oh C.K. , Yao Y.J. , Zhao S.P. 
Published: December 2020

Abstract
This paper describes a sample preparation methodology for Trench Power MOSFET that significantly improved our failure analysis success rate for trench bottom defect. With precise fault localization and subsequent a unique physical failure analysis using parallel polishing method on Trench Power MOSFET, This enabled defect detection from the trench top to the trench bottom.
Evolution of Wafer Level Tester-Based Diagnostic System—More Than Just a Dynamic Electrical Fault Isolation Tool
Authors: Goh S.H. , You G.F. , Yeoh B.L. , Chan Y.H. , Yap C.P. , Lam Jeffrey , Chua C.M. 
Published: December 2020

Abstract
Wafer level tester-based fault isolation (FI) tool exists back in 2008 but is not widely adopted by industry. This is expected because such tool is commonly known for its primary role in dynamic electrical FI. Since packages are readily available, there is little motivation in using wafers. This paper provides a different perspective to consider such tool as part of a wafer level debug solution to enhance current failure pre diagnostic and diagnosis capabilities, to meet requirements for fast and effective yield ramp. Test cases are presented to support this perspective and a roadmap that guides next generation wafer level FI tool is also proposed at the end of the paper.
Resolution Improvement through Sparse Image Reconstruction Techniques for Dark Field Subsurface Microscopy of Integrated Circuits
Authors: Cilingiroglu T. Berkin , Karl W. Clem , Konrad Janusz , Grogan Michael D.W. , Yurt Abdulkadir , Tuysuzoglu Ahmet , Goldberg Bennett B. , Unlu M. Selim 
Published: December 2020

Abstract
Sparse image reconstruction techniques have been used to recover high frequency information lost during the acquisition process in different imaging domains, such as ultrasound, synthetic aperture radar, optical microscopy, and astronomical and microscopic imaging. In this work, a signal processing framework is proposed to estimate the Point Spread Function (PSF) of the dark-field subsurface microscopy system from observation data. This PSF is incorporated into an image reconstruction framework, which can be formulated with two different image reconstruction techniques, regularized image reconstruction and dictionary-based image reconstruction. It is observed that both techniques provide at least 12% resolution improvement; lines with 224 nm spacing were localized after resolution improvement while lines with 252 nm spacing are at the limit of localization in experimental data. However, dictionary-based image reconstruction provides higher edge resolution and maintains the homogeneity of the intensity within the structures.
Analysis of InGaAs Epi Defects by Conductive AFM
Authors: Cordes Aaron , Dyer Tom , Hand Sean 
Published: December 2020

Abstract
As the semiconductor industry continues to push the boundaries of Moore’s law, new device structures and materials are being introduced to increase device speed and lower power consumption. This work uses InGaAs as representative samples to investigate the capability of conductive AFM to image and characterize electrical defects in thin films. As the AFM is a non-destructive technique, the defects may be re-located by complimentary reference metrology techniques. Once the capability of defect detection and characterization of AFM is demonstrated with respect to the reference metrology techniques, conductive AFM is used to characterize the defect density of a set of InGaAs samples grown under varying process stressed epitaxial conditions.
Failure Analysis Methodology on Systematic Missing Cu in RAM Due to Cu CMP
Authors: Ang Ghim Boon , Chen Changqing , Ng Hui Peng , Quah Alfred , Teo Angela , Yip Kim Hong , Neo Soh Ping , Lam Jeffrey , Mai Zhihong 
Published: December 2020

Abstract
This paper places a strong emphasis on the importance of applying Systematic Problem Solving approach and use of appropriate FA methods and tools to understand the “real” failure root cause. A case of wafer center cluster RAM fail due to systematic missing Cu was studied. It was through a strong “inquisitive” mindset coupled with deep dive problem solving that lead to uncover the actual root cause of large Cu voids. The missing Cu was due to large Cu void induced by galvanic effects from the faster removal rate during Cu CMP and subsequently resulted in missing Cu. This highlights that the FA analyst’s mission is not simply to find defects but also play a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically/ physically) to Fab.
Ex-Situ Lift Out of Plasma Focused Ion Beam Prepared Site Specific Specimens
Authors: Chan Lisa , Hiller Jon M. , Giannuzzi Lucille A. 
Published: December 2020

Abstract
Ex situ lift out (EXLO) was historically the first lift out technique to be developed for site specific removal and manipulation of focused ion beam (FIB)-prepared specimens to a suitable carrier. In this paper, fast plasma FIB (PFIB) preparation of large scanning/transmission electron microscope specimens is combined with fast conventional EXLO and EXpressLO "pick and place" solutions. The combination of large material removal rates with PFIB and EXLO allows for efficiency and high throughput of FIB lift out specimens.