A Computational Study of Tunneling Field-Effect Transistors: Challenges and Design Optimizations
Authors: Liang Gengchiau , Low Kain Lu 
Published: February 2020

Complementary-metal-oxide-semiconductor (CMOS) transistors have been commonly employed in the electronics industry for the past decades thank to their excellent scalability, low cost, and high performance. The semiconductor industry follows the Moore’s law which predicts that the number of transistors in an integrated circuit (IC) approximately doubles every two years. High packing density enables more logic circuits to be fabricated on a given IC chip area which lowers the cost per function. However, exponential growth of the number of transistors per IC chip leads to a drastic increase in the power density. Basically, power consumption of an IC can be categorized into two components: active power (PActive
) and passive power (PPassive
). PActive
is given by αfCVDD
2
, where α is the activity factor, f is the operating frequency, C is the load capacitance, and VDD
is the power supply voltage. PPassive
is the power dissipation of transistors that are at the OFF state. Its magnitude is proportional to the product of OFF state current (IOFF
) and VDD
. With the shrinking of physical dimensions of CMOS devices into sub-10 nanometer regime, direct source to drain tunneling and gate leakage can significantly increase the IOFF
, which in turn increases the static power. In other words, power consumption has imposed a serious issue for advanced technology nodes.
Since both active and passive powers are strongly dependent on the VDD
, one effective way to reduce the power consumption is to scale down the VDD
. The threshold voltage (VTH
) of the conventional MOSFETs needs to be reduced so that the same ION
can be sustained at reduced VDD
. However, decreasing VTH
without scaling the subthreshold swing (S) will result in a high IOFF
. This causes high passive power consumption. In the conventional MOSFET, the high energy electrons following the Fermi-Dirac distribution contribute to the subthreshold current which sets the lower limit of the subthreshold swing. Thus, a steeper switching characteristic is required in order to retain the same ION
and IOFF
when VDD
is reduced. In this context, tunneling field-effect transistors (TFET) based on band-to-band tunneling (BTBT) is a promising candidate to overcome the 60mV/dec swing limitation at room temperature faced in conventional MOSFETs.
Although a steeper switching characteristic can be achieved in TFETs, the ION
of TFETs is still too low to satisfy the drive current requirement for low power application projected by the International Technology Roadmap for Semiconductors (ITRS). The performance of TFET can be enhanced via a few innovations, such as the employment of direct band gap materials, heterostructures with staggered band alignments, and inventive device structure designs. Recent advancements in TFET shows that enhancement in TFET is attained when the BTBT direction is aligned to the gate induced electric field, so-called vertical TFET (VTFET). This is due to the greater efficiency of the gate to control the band bending.
In this work, we investigate the performance of the vertical TFET based on group IV and III-V materials. The vertical TFET considered is the Electron-Hole Bilayer TFET. The device Hamiltonians for all channel materials are constructed based on the full-band sp3d5s*tight-binding (TB) model. The atomistic TB model offers a realistic calculation which captures the properties of nano-scale structures more accurately. The carrier transport of VTFET is calculated using a quantum simulator based on the formalism of non-equilibrium Green’s function (NEGF). Subsequently, the atomic charge obtained from NEGF is coupled with the Poisson solver to solve for the atomic potential self-consistently.
The optimization of VTEFT is carried out in terms of ON-current and subthreshold swing. The materials considered consist of silicon, germanium, and indium antimonide, and hetero-structures from III-V semiconductors. The effects of the device geometries, such as the length of overlap (LOV
) and underlap (LUN
) regions, are studied in order to provide insights in enhancing the electrical performance of VTFETs. Our study shows that heterojunction consisting of GaSb (source) and InAs (drain) offers higher current than that of Si homojunction. The electrical performance of VTEFT is further benchmarked with that of the conventional lateral PIN structure. In conclusion, this work presents the challenges and key design considerations of VTEFT.