(Keynote) Low Temperature SmartCutTM Process for 3D Integration
Authors: Schwarzenbach Walter , Reboh Shay , Ghorbel Aymen , Gaudin Gweltaz , Besnard Guillaume , Mazen Frédéric , Loup Virginie , Maitrejean Sylvain , Brunet Laurent , Nguyen Bich-Yen , Maleville Christophe 
Published: May 2020

Abstract— To support 3D Sequential integration with a cost-effective layer transfer, SmartCut™ process at low temperature (below 500 °C) is proposed. Excellent SOI & BOX layer thickness uniformities are demonstrated, while layer integrity, electron and hole mobility performances are already compliant with development grade requirements.

Keywords—SmartCut, 3D Integration, Low Temperature, CMOS

I. SmartCut Proposal for 3D Sequential Integration
In support of the semiconductor evolution, 3D integration is considered, addressing several challenges: integration of multiple types of devices including specialized components, continuous footprint reduction as well as optimization of performance and cost [1]. However, a key challenge for 3D integration, shown on Figure 1 reported in reference [2], is the preparation of a top tier device using as handle surface a fully processed bottom tier device. Hence, the top tier device thermal budget needs to be reduced to avoid degradation of the bottom devices [3]. A mandatory 500 °C thermal budget limitation for 3D Sequential Top layer transfer and MOSFET fabrication is then considered [2, 4].
In order to take advantage of the SmartCut process to transfer at reduced cost (i.e. avoiding a conventional but costly SOI bonding & grinding process) a high quality, highly uniform crystalline layer, we propose the use of a new Low Temperature SmartCut process as an alternative for 3D integration. This paper reports on our findings from such transfer demonstrations on bare handle materials, including for the first time SOI-like layer electrical characterization results.
II. Low Temperature SmartCut for 3D Integration
For 3D integration, SmartCut process is adapted as schematically shown on Figure 2 in order to transfer at low temperature ultra-thin layers compatible with fully depleted requirements. This process option includes the use of engineered, epitaxial processed donor wafers. The epitaxial process on conventional bulk material allows creation of a first Silicon-Germanium layer, to be used as an etch stop layer after SmartCut splitting. Then a subsequent Si layer, defined accordingly to the SOI film thickness target, is epitaxied. Implant, surface preparation, bonding, splitting process steps, all being compliant with maximum 500 °C low temperature requirement, benefit from conventional FD-SOI experience. Finishing process includes selective etching to recover SOI layer [5]. Then a dedicated curing process step is considered in order to optimize SOI layer electrical properties. Silicon Phase Epitaxial Regrowth (SPER) as described in reference [6] is proposed.
Figure 3 highlights such low temperature layer transfer process on a patterned handle wafer. Picture is obtained after SmartCut splitting process step. A visual defect free layer is obtained.
III. Low Temperature SOI Performance on Bare Handle wafer
The SOI layer thickness variability, over the full spatial wavelength spectrum from device to wafer scale, is driven by the donor epitaxy performance. Figure 4 shows Atomic Force Microscopy (AFM) roughness performance, through 30x30 µm² scan. RMS of 1.0 and 0.9 Å are measured on high and low temperature process options respectively. Best in class performance is then obtained thanks to Low Temperature SmartCut.
Figure 5 shows (a) BOX and (b) SOI layers ellipsometry thickness mapping, on a 12 nm SOI / 20 nm BOX sample. BOX layer variability is primarily driven by thermal oxide growth, thus demonstrating a within wafer uniformity << 10 A. SOI layer thickness variability is mainly driven by epitaxy performance on the engineered donor wafer.
Figure 6 shows typical KLA Tencor SP3 @ 65 nm threshold defect mapping, as measured on 12 / 20 nm low temperature R&D sample. Micro-defect density on this early development product already demonstrates less than 0.1 defect / cm² performance.
Then Figure 7 compares PsiMOS measured electron and hole mobility in the SOI layer using High and Low Temperature SmartCut processes. A as low as 10% mobility performance difference between both processes vintage is already demonstrated.
IV. Conclusion
To support 3D sequential integration, layer transfer at low temperature (< 500 °C) is demonstrated thanks to an adapted SmartCut process. Next research step will confirm this capability with low temperature layer transfer on patterned substrate for 3DS device assessment.
V. References
[1] J. Macri, Proc. IEEE S3S Conference, 2018
[2] L. Brunet et al., Technical Digest – IEDM Conference, 2018, pp 7.2.1 – 7.2.4
[3] A. Vandooren et al., Proc. IEEE S3S Conference, 2018
[4] C. Fenouillet-Beranger et al., Proc. IEDM Conf., 2014.
[5] J. Widiez et al. ECS Trans., 2014, vol. 64(5), pp. 35-48
[6] G. Gaudin et al., ECS J. Solid. State. Sci Tech., 2(12), 2013, pp 534 - 538

Figure 1