Multi-Bit Non-Volatile Organic Transistor-Based Memory Using Lithium-Ion-Encapsulated Fullerene As a Charge Trapping Layer
Authors: Tran Cuong Manh , Sakai Heisuke , Kawashima Yuki , Ohkubo Kei , Fukuzumi Shunichi , Murata Hideyuki 
Published: February 2020

Organic field-effect transistor (OFETs) based memory devices have been intensively researched in recent years because of their simple structure using a single transistor, reduced data storage losses, and easy integration in electronic circuits.[1] The memory effect in OFETs is achievable by inserting a charge trapping layer such as a thin film of star-shape poly((4-diphenylamino)benzyl methacrylate) between an active layer and a gate dielectric.[2] Charges can be injected to the charge trapping layer by applying a programming voltage, and will be stored after voltage removal. The stored charges affect on the drain current (I
D) of the OFETs,
and cause a shift of the threshold voltage (V
th), which corresponds to the change of logic state. The stability of each state contributes to the memory effect. Expansion of the storage capacity of OFETs has been the object of many researches.[2,3] Lithium-ion-encapsulated fullerene (Li+@C60) would be a potential material for the charge trapping layer of multi-bit memories, because its three-fold degenerated lowest unoccupied molecular orbital (LUMO) is expected to accept up to 6 electrons by an applied voltage.[4] In this presentation, we demonstrate a multi-bit memory OFETs using Li+@C60 as the charge trapping layer.
The top-contact OFETs using heavily doped p-type silicon wafers with a 400-nm-thick silicon dioxide were fabricated (Fig 1a). The layers of bis(trifluoromethylsulfonyl)imide Li+@C60
salt (Li+@C60NTf2
-, Fig. 1b) (island-formed) and Cytop (10 nm) were spin-coated on the silicon dioxide. Subsequently, a 50-nm layer of pentacene and copper electrodes (50 nm) were deposited at the pressure of 2.5 × 10-5 Torr. The length (L) and width (W) of the channel were 50 μm and 2000 μm, respectively. The electrical characteristics of the memory devices were measured with a semiconductor characterization system (Keithley) in a dry nitrogen atmosphere at room temperature.
The as prepared OFET memories exhibited a good performance with low threshold voltage (V
th) of -5.98 V and high electron mobility (μ) of 0.84 cm2V-1s-1. Then, to bring the transfer curve to the erased state, a negative voltage of -150 V was applied to the gate for 5 s, which results in V
th of -19.79 V. For programming, a voltage of 150 V was applied to the gate for 0.5 s. The transfer curve shifted to the positive V
G region with a V
th of -9.99 V, reflecting a memory window (ΔV
th) of approximately 10 V. To erase memory, a negative voltage of -150 V was applied to the gate for 0.17 s. The transfer curve shifted back to the erased state. The memory OFETs were subsequently programmed with a voltage of 150 V for 5 s or 50 s, and then erased with a voltage of -150 V for 1.7 s or 17 s, respectively. The transfer curve shifted to positions with a V
th of -3.40 V and 12.40 V, respectively, and was brought back by erasing exactly to the erased state. Estimated values for ΔV
th
of 16 V and 32 V were clearly observed (Fig 1c). In our memory OFETs, the transfer curve of programmed states can go back to that of erased state. It is clear that the memory OFETs with Li+@C60 operated as multi-bit memories. In addition, to evaluate the long-time operation of the memory OFETs, the retention times of both the programmed and erased states were measured at a V
D of -60 V and a V
G of 0 V. A clear difference in logic states was observed for more than 3000 sec. (Fig 1d)
To clarify the origin of the multi-bit memory effect of memory OFETs with Li+@C60, OFETs without Li+@C60
were also fabricated and compared the memory behaviors. The memory OFETs without Li+@C60
exhibit a 1-bit memory characteristics, which is in line with the results reported by Dao in 2012 [5]. In constrast, the memory OFETs with Li+@C60 exhibited muti-bit characteristics due to the difference in number of trapped electrons at the Li+@C60
layer under different programming conditions. This would result from the high electron acceptability of the three-fold degenerated LUMO of Li+@C60.[4] We therefore conclude that the electron-trapping ability of the Li+@C60 layer is at the origin of the multi-bit effect in our memory OFETs.
[1] S.-T. Han et al., Adv. Mater. 25 (2013) 5425 - 5449.
[2] Y.-C. Chiu et al., NPG Asia Mater. 5 (2013) e35.
[3] K.-J. Baeg et al., Adv. Mater. 22 (2012) 2915 - 2926.
[4] Y. Kawashima et al., Chem. Asian J. 10 (2015) 44 - 54.
[5] T.T. Dao et al., Org. Electron. 13 (2012) 2709 - 2715.

Figure 1