bluuebunny/crossref_metadata_2025_split huggingface dataset:
The Joy of SOI: As Viewed from a Backside FIB Perspective
Authors: Herschbein Steven , Rue Chad , Scrudato Carmelo 
Published: December 2020

Abstract
For most advanced semiconductor products, the preferred methodology for achieving Focused Ion Beam (FIB) circuit modification and node access is through the backside of the chip. The high density of interconnect wiring and the presence of C4 solder bumping has made complex edits virtually impossible with conventional frontside techniques. IBM has developed a set of procedures for performing backside edit on circuits built using the Silicon-On-Insulator (SOI) process. While the basic approach and techniques parallel many of the established practices developed for handling transistors built in conventional bulk silicon, there are a number of key and critical differences. In this paper, we will address the basic instruction set developed for successful FIB work on SOI product. This will include backside silicon surface preparation, charge control, endpointing during high volume silicon removal, global and local coordinate lock techniques, floor voltage contrast phenomena, floor preparation and preservation, fill pattern issues and advantages, and finally the target structure alignment, access, connection and/or removal. Post process bake and handling will also be discussed.
Furthering the Business Proposition of a Robust System Level Failure Analysis Framework: A Focus on Enabling Product Services
Authors: Bjork Roger 
Published: December 2020

Abstract
A few years ago, along with colleagues from Intel and Dell, we shared with you the importance of Failure Analysis as a business proposition[1], This paper will identify even more business processes which will benefit from a robust System Level Failure Analysis framework. More and more companies strive to differentiate themselves from their competition by focusing not just on product features and price, but also on how well they serve their customers. An effective Service Plan (Figure 1) is fundamental in the provision of this service. No matter how broad a company’s service offering portfolio, a fundamental enabler of any Fault Management system is the ability to identify and predict failures. Further, a robust Knowledge Management system must exist to enable the collection and dissemination of services intellectual property (IP) in an effective manner, and facilitate a broad level commonality analysis that provides the ability to monitor trends and shifts in product performance.
Developing a More Inclusive System Level ESD Characterization Methodology
Authors: Rahardjo Johan , Miller Socorro , Lopez Leo , Williams Steve L. 
Published: December 2020

Abstract
ESD (Electrostatic Discharge) has become an increasing problem on electronic devices. The electronics industry is always looking for ways to improve the reliability of electronic devices by enhancing their test methods. The industry has found that the current ESD test methods do not encompass all possible scenarios to which electronic devices are exposed at the customer site. This paper describes a novel method to bridge the gap between current system level ESD specifications and customer real world situations. Field failure investigations led us to discover a new customer situation where ESD is induced on a computer system through a peripheral/cable that is already attached (different than hot-plug event). To simulate this scenario, ESD was injected directly into the signal pins of the bus being tested, creating what we call the DCD (Direct Contact Discharge) test methodology. This paper compares DCD against the current ESD standards and demonstrates that introducing DCD into the current ESD testing methodology will significantly lower the system field failures. DCD is not a replacement for current ESD testing practices in the industry; DCD is a complement that allows a more inclusive ESD test coverage
X-ray Fluorescence Imaging for High Resolution Elemental Mapping
Authors: Feser M. , Yun W. , Lyon A. , Wang Y. , Sehadri S. 
Published: December 2020

Abstract
X-ray fluorescence imaging is a novel non-destructive method to obtain sub-100nm spatial resolution elemental maps with short data acquisition times. The method has a wide range of applicability in the field of semiconductor manufacturing and semiconductor failure analysis. Imaging of copper interconnects on ICs for the location of voids and shorts is one particular application that is relevant for current and future needs of nondestructive inspection and failure analysis of backend processes.
3-D EBIC Technique using FIB and EB Double Beam System
Authors: Yoshida Eiji , Tanaka Tomohiro , Oyamada Taro , Koyama Tohru , Komori Junko , Maegawa Shigeto 
Published: December 2020

Abstract
We propose visualizing techniques of a diffusion layer using an electron beam induced current (EBIC) for a site-specific cross-section formed by focused ion beam (FIB) treatment. Moreover, we present a three-dimensional (3-D) EBIC technique using a double beam (FIB & EB) system to understand the diffusion structure. This 3-D application of the EBIC technique is very useful for delineating PN junctions and pointing out implant defects in ULSI devices. Furthermore, we applied the EBIC technique to backside circuit editing with FIB. The end-point of the silicon trench etching can be easily decided by observing the plane EBIC images. Highly reliable backside circuit editing becomes possible together with a DUV laser marking technique using an IR-optical microscope system.
Case Studies of the Use of Image Processing in Metrology and Failure Analysis
Authors: Ramanujachar Kartik 
Published: December 2020

Abstract
This paper describes the use of image processing techniques in metrology and failure analysis with the help of three case studies. The first study concerns a technique that significantly automates the process and hence enables both a rapid and accurate extraction of cumulative distribution function for transistor CD through the use of edge detection and quantification of image intensities. The second study is about utilizing a cross correlation algorithm and an appropriately chosen sample and image to estimate the "on image" spatial resolution of an scanning electron microscope. The last case study uses image data acquired with an atomic force microscope. The paper describes how information theoretic concepts like entropy and mutual information combined with image segmentation and nearest neighbor extraction can be used to isolate those regions of the AFM scan that can potentially benefit from further analysis.
DuPont EKC265™ as a Copper Metal Etchant to Assist FIB Edits through Large Copper Power Supply Lines
Authors: Mulder Randal E. 
Published: December 2020

Abstract
State-of-the-art semiconductor technologies use multiple copper metallization layers to route power and signals throughout the semiconductor device. These devices have four to six metal layers with the top layers predominately used to route the large power supply lines. To gain access to these lower signal lines, focused ion beam (FIB) must be used to cut large windows through the large power supply lines; this is very difficult. This paper demonstrates how EKC265 can be used as a copper metal etch to remove the copper of the power supply lines. This allows the FIB to cut large windows through the material layers to gain access to the lower metal layers for probing or FIB edits. Results are shown for FIB work using EKC265 and for FIB work without the using EKC265. EKC265 eliminates the need to use the FIB to remove copper giving a much more uniform milling result.
Nanomechanical Characterization in the FIB
Authors: Moore Thomas M. 
Published: December 2020

Abstract
The availability of the focused ion beam (FIB) microscope with its excellent imaging resolution, depth of focus and ion milling capability has made it an appealing platform for materials characterization at the sub-micron, or "nano" level. This article focuses on nanomechanical characterization in the FIB, which is an extension of the FIB capabilities into the realm of nano-technology. It presents examples that demonstrate the power and flexibility of nanomechanical testing in the FIB or scanning electron microscope with a probe shaft that includes a built-in strain gauge. Loads that range from grams to micrograms are achievable. Calibration is limited only by the availability of calibrated load cells in the smallest load ranges. Deflections in the range of a few nanometers range can be accurately applied. Simultaneous electrical, mechanical, and visual data can be combined to provide a revealing study of physical behavior of complex and dynamic nanostructures.
High Resolution Acoustic Microscopy with Low Frequency and Its Applications in Analysis of Ferroelectrics
Authors: Yin Q.R. , Yu H.F. , Zeng H.R. , Li G.R. , Ding A.L. 
Published: December 2020

Abstract
Nondestructive observation of domain structure of ferroelectrics, dynamic behavior under external field and related phenomena is becoming significant. As a nondestructive and subsurface characterizing technique, the authors developed acoustic microscopy based on a commercial scanning probe microscope for direct observation of local ferroelectricity, elasticity and defects on several inorganic functional materials, transparent PLZT ceramics, relax-based PMN-PT crystal and lead-free bismuth titanate ceramics without any special processing (polishing or etching) to the sample. The direct observation is particularly useful and convenient for analyzing ferroelectrics/semiconductor integrated material and devices. The excitation frequency is in the range of several kHz to decades of kHz, which is much lower than that of the traditional acoustic imaging techniques. But several applications of scanning probe acoustic microscope (SPAM) involving ferroelectric samples with the resolution of 10nm were obtained. The expanding scope of application for SPAM shows exciting possibilities for non-destructive analyses in the microelectrics industry.
Depth Measurement of Dislocations in Si Substrate by Stereo TEM
Authors: Bow Jong-Shing , Yu Speed 
Published: December 2020

Abstract
Traditional plane-view TEM images, which have large fields of view and are usually used to check the existence of dislocations, cannot tell whether a dislocation goes through the p-n junction or not. While XTEM images tell the local depth of a small part of a dislocation only, other methods have to be developed to explore how a dislocation goes in the substrate. In this article, the authors have modified the technique of stereo TEM, which was used to study the 3D shapes of precipitates, to study how a dislocation runs in the Si substrate. Three images recorded after tilting the TEM sample were used for measuring the dislocation depth profile. The distances between a few chosen points on the dislocation and the reference line were measured from above three images. Results suggested that the depth profiles of dislocations in the Si substrate can be accurately determined by stereo TEM.
Gate Oxide Defect Localization and Analysis by Using Conductive Atomic Force Microscopy
Authors: Lee Z. H. , Lin C. J. , Lai S. W. , Chou J. H. 
Published: December 2020

Abstract
This paper describes gate oxide defect localization and analysis using passive voltage contrast (PVC) and conductive atomic force microscopy (C-AFM) in a real product through two case studies. In this paper, 10% wt KOH was used to etch poly-Si and expose gate oxide. In the case studies, different types of gate oxide defects will cause different leakage paths. According to the I-V curve measured by C-AFM, we can distinguish between short mode and gate oxide related leakage. For gate oxide leakage, KOH wet etching was successfully used to identify the gate oxide pinholes.
The Enhancement of Abnormal Photon Emission Identification for Advanced Processes using a Backside Cooling PEM System
Authors: Wang C. H. , Lai S. W. , Lee Z. H. , Chou J. H. 
Published: December 2020

Abstract
Modern semiconductor devices are continuing to be scaled down and the complexity of the processes involved in producing the devices keeps increasing, in conjunction with this, sample preparation and analysis are increasingly important for accurately determining the sources of defects and failure mechanisms in terms of process integration. This paper discusses ways to characterize integration-driven defects using deprocessing techniques and cross-section imaging to obtain 3-D views of such defects. As an example a single-via test structure is evaluated. The article focuses on the techniques used to deprocess the single-via structure using a combination of RIE, FIB, and wet etching to expose the single via while maintaining the integrity of the structure. The resulting 3-D view of the structure and associated defect allowed for improved understanding of the defect and its origin. This understanding enabled process optimization to minimize such defect formation.
Single Via Deprocessing Techniques to Enable Physical Analysis for Semiconductor Process Integration
Authors: Hammett Jacob E. , Qin Wentao , Theodore David 
Published: December 2020

Abstract
Modern semiconductor devices are continuing to be scaled down and the complexity of the processes involved in producing the devices keeps increasing; in conjunction with this, sample preparation and analysis are increasingly important for accurately determining the sources of defects and failure mechanisms in terms of process integration. This paper discusses ways to characterize integration-driven defects using deprocessing techniques and cross-section imaging to obtain 3-D views of such defects. As an example, a single-via test structure is evaluated. The article focuses on the techniques used to deprocess the single-via structure using a combination of RIE, FIB, and wet etching to expose the single via while maintaining the integrity of the structure. The resulting 3-D view of the structure and associated defect allowed for improved understanding of the defect and its origin. This understanding enabled process optimization to minimize such defect formation.
Stacked Polysilicon/Metal Capacitors Failure Analysis
Authors: Nguyen Dat T. , Huang Frank 
Published: December 2020

Abstract
Poly/metal stacked capacitors present challenges in terms of capacitor access and defect localization. As for defect localization, liquid crystal or thermal localization (also OBIRCH/TIVA) and passive voltage contrast (PVC) are used. PVC was found to be effective in terms of finding the bad stacked capacitor and a bad capacitor within the stack. This paper highlights brief process steps in 3-layer polysilicon/metal stacked capacitors. It discusses FA on stacked capacitors, providing information on fault isolation and capacitor access. It presents a case study on differentiating defective capacitors which failing due to vertical shorting. Internal probing between the capacitors within a stack allowed the differentiation between capacitor leakage and capacitor-capacitor shorting. For capacitor leakage, the defect can be identified by parallel lapping to remove the upper capacitor plate. For capacitor-capacitor short, if there is no visual defect seen, Pt chemical etch can be applied for PVC inspection.
Failure Analysis Techniques for Lead-Free Solder Joints
Authors: Castello Todd , Rooney Dan , Shangguan Dongkai 
Published: December 2020

Abstract
Printed circuit board assembly with lead free solder is now a reality for most global electronics manufacturers. Extensive research and development has been conducted to bring lead free assembly processes to a demonstrated proficiency. Failure analysis has been an integral part of this effort and will continue to be needed to solve problems in volume production. Many failure analysis techniques can be directly applied to study lead free solder interconnects, while others may require some modification in order to provide adequate analysis results. In this paper, several of the most commonly applied techniques for solder joint failure analysis will be reviewed, including visual inspection, x-ray radiography, mechanical strength testing, dye & pry, metallography, and microscopy/photomicrography, comparing their application to lead bearing and lead free solder interconnects. Common failure modes and mechanisms will be described with examples specific to lead free solders, following PCB assembly as well as after accelerated reliability tests.
The Versatile Application for In-situ Lift-out TEM Sample Preparation by Micromanipulator and Nanomotor
Authors: Lee Jon C. , Lee B.H. 
Published: December 2020

Abstract
The device features have shrunk to sub-micron/nano-meter range, and the process technology has been getting more complicated, so TEM has become a necessary tool for PFA imaging and element analysis. Conventional FIB ex-situ liftout is the most common technique for precise sample preparation. But this method has some limitations: samples cannot be reprocessed for further analysis; the carbon film supported grid affects the EDS analysis for carbon elements. A new installation will be introduced in this article, which is set up in FIB chamber for in-situ lift-out application. It not only overcomes the above problems, but also covers a wide application of TEM sample preparation.
Physics of Failure Investigation of Dark VCSEL Devices: Detection of Reverse-Bias Electroluminescence by Emission Microscopy
Authors: McElfresh D. K. , Lopez L. D. , Melanson R. , Vacar D. 
Published: December 2020

Abstract
We present a new failure analysis technique for dark (optically degraded) vertical-cavity surface-emitting lasers. Measurements of spatially and spectrally resolved light emission under reverse bias provide key information on the failure mechanism.
X-Ray Nanoanalysis in the SEM
Authors: Vanderlinde William E. , Chernoff Don 
Published: December 2020

Abstract
Scanning electron microscopy (SEM)/energy dispersive x-ray spectroscopy (EDS) is generally thought of as a bulk analysis technique that is not suited for nano-scale analysis. This paper discusses several options for reducing or eliminating the interaction volume size and obtaining x-ray data with much higher spatial resolution and surface sensitivity than is typically achieved in the SEM. These include collecting data at very low accelerating voltages to minimize beam spread in the sample, tilting the sample to keep the interaction volume near the surface, and analyzing thin sections to reduce or eliminate the problem of beam spread in the sample. Computer software simulations, in conjunction with experimental data are used to illustrate these methods. The paper also discusses issues effecting EDS analysis in the environmental SEM. It has been shown that computer modeling is a useful tool for determining the optimum beam conditions to improve energy dispersive analysis in the SEM.
Kinematical Simulation of HOLZ Pattern for Uniaxial Strain Determination
Authors: Chen Tung-Hung , Bow Jong-Shing 
Published: December 2020

Abstract
Strained silicon induced by the CMOS device process has been considered an important technology for improving the performance of MOSFETs by increasing local carrier mobility in the current channel. In order to evaluate the feasibility of using convergent beam electron diffraction (CBED) in lattice strain determination, high-order Laue zone (HOLZ) lines inside the center disc of a CBED pattern with specific zone axes were kinematically simulated. The intersecting HOLZ lines shift was plotted against the lattice parameter for the determination of uniaxial strain.
Using High Speed Camera Metrology in Support of Failure Analysis and Product Development
Authors: Hezeltine Wade , Williams Richard L. , Liang Frank Z. 
Published: December 2020

Abstract
Typical failure analyses metrologies for dynamic failures are cross-sections, microscopy, dye-and-pull, optical and SEM. Using these traditional metrologies to find root cause for a dynamic event can be very time consuming and often the results cannot point directly to the root cause itself. The standard approach is to work backward to reconstruct the “event” that caused or initiated the failure. Often the root cause is not immediately obvious and iterative testing to identify the true root cause is costly in time, materials and resources. At Intel we have been using high speed imaging and motion analysis (HSIMA) to identify the failure at the point of initiation. Using the point of initiation concept with reconstructive modeling allows a design team to identify potential initiating sources and better match and implement corrective action. HSIMS has proven to decreases development time, minimized product design cycle and increases market opportunities by decreasing cycle times to root cause of failures.
Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning
Authors: Eddleman Chris , Tamarapalli Nagesh , Cheng Wu-Tung 
Published: December 2020

Abstract
Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.
Diagnosis of Multiple Scan Chain Faults
Authors: Kong Chia Ling , Islam Mohammed R. 
Published: December 2020

Abstract
Precise isolation and resolution of scan chain defects are more critical than ever due to increased reliance on scan-based design to achieve desired test content. At the same time, its diagnosis is becoming more difficult as product design increases in complexity alongside shrinking fabrication processes. In this paper, we present a new scan chain diagnosis procedure that is centered on Load Pass Unload Fail/Load Fail Unload Pass (LPUF/LFUP) and Scan Shift Logic State Mapping (SSLSM) techniques to isolate both stuck-at and timing scan chain faults without the design overhead and defect assumptions of previously proposed methods. More importantly, this procedure is extended to analyze scan chain with multiple defects, which is becoming a more frequent occurrence as process scales down in size.