bluuebunny/crossref_metadata_2025_split huggingface dataset:
Limit: An Ambiguous Dimension Even In The Theatre
Authors: Teampău Radu 
Published: December 2020

Abstract
This paper intends to deal with the problem of transcending the limit from the performing arts perspective. To achieve this goal, we proceed to an analysis of the concept of limit from both philosophical and theatrical perspectives. There is a wide range of possible definitions of limit as the concept in itself turns out to be ambiguous. To reflect upon different ways of surpassing the limit firstly requires the identification and investigation of the meanings of the concept of limit which is to be surpassed. Some examples of going beyond the limit in the theatre are briefly reviewed.
Theater, Between Technology and Visual Arts
Authors: Dragoş Răzvan 
Published: December 2020

Abstract
Since Antiquity, there have been biunivocal links between theater, technology and visual arts, each of these branches being, if not decisively influenced by the others, at least stimulated. Technology was put at the service of theater either as a logistical part or in “main” roles, sometimes in competition with the actor, in other words with the man. In the first case we are dealing with elevators, cranes, light or sound devices and so on. In the second, with automatic machines, largely autonomous. Applied arts, costumes, scenery, stage props and everything related to scenography are largely synonymous with the performing arts. On the other hand, the technicalartistic commands and requirements coming from the theater have always been a step forward for those directions. Technology and art have also influenced each other, if we take into account, for example, Leonardo da Vinci’s utopian sketches, endowed rather with artistic qualities, but at the same time often functional as stage props. This article points out the idea written above through several representative case studies for the subject approached in a historically evolutionary perspective, relating them to the philosophical concepts or social phenomena behind them.
Amniotic band syndrome with double encephalocele: A case report
Authors: Silva Aldo Jose Ferreira da , Silva Carolina S. Magalhães e , Mariano Sonaly C. R. 
Published: December 2020

Background:
Amniotic band syndrome (ABS) is a rare condition of controversial etiology that is associated with varying degrees of anomalies. This study reports a case of a newborn with ABS associated with double encephalocele in the frontal region.

Case Description:
A 29-year-old primiparous woman with no history of prenatal infection or consanguineous marriage had a cesarean section at gestational week 38, giving birth to a newborn who was well but had limb anomalies (constriction rings, amputations, and syndactyly) and craniofacial anomalies, mainly double frontal encephalocele. The patient underwent surgical repair and subsequent placement of a ventriculoperitoneal shunt.

Conclusion:
Studies clarifying this uncommon association with double encephalocele are limited. ABS associated with double encephalocele is rare and even more complex when associated with other anomalies. Thus, the conditions in such children are severe and require multidisciplinary monitoring.
The Application of Novel Failure Analysis Techniques and Defect Modeling in Eliminating Short Poly End-Cap Problem in Submicron CMOS Devices
Authors: Hong Y.E. , We M.T.T. 
Published: December 2020

Abstract
As transistor dimension shrinks down below submicron to cater for higher speed and higher packing density, it is very important to characterize the shrinkage carefully to avoid unwanted parametric problems. Leakage current across short poly end-cap is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre wafer striping' functional failure problem. This paper presents the advanced failure analysis techniques and defect modeling used to narrow down and identify this new mechanism. Post process change by loosening the marginal poly end-cap criteria eliminated the problem completely.
Failure Analysis of DRAM Storage Node Trench Capacitors for 0.35-Micron and Follow-On Technologies Using the Focused Ion Beam for Electrical and Physical Analysis
Authors: Benstetter G. , Bomberger G. , Coutu P. , Danyew R. , Douse R. 
Published: December 2020

Abstract
Reducing the cell size of DRAMs in 0.35 micron and follow-on technologies requires failure analysis techniques that can analyze single storage node trench capacitors on both test sites and actual product. A combination of electrical microprobing, probeless voltage contrast and physical delayering procedures, all based on focused- ion-beam (FIB) techniques, are described. Because of precise fail localization, high resolution scanning electron microscope (SEM) imaging enables the distinction between process defects and intrinsic breakdowns of node dielectric defects. Isolated storage cells can be electrically characterized by depositing small probe pads, using FIB for contact hole milling and probe-pad deposition. To localize trench capacitors with a leakage path to the surrounding substrate, the trenches are isolated by mechanical polishing and probeless voltage contrast in the FIB tool. Failing trench capacitors can be marked in the FIB tool. Physical isolation of leaking trench capacitors can be achieved by recessing the adjacent trench capacitors, with the FIB used for milling and a subsequent wet chemical removal added for the remaining substrate material. Alternatively, trench capacitors can be inspected from the backside when stabilized by a quartz deposition on top, followed by mechanical polishing from the side and a wet chemical etching of the remaining substrate material. In both cases, the dielectric of the node trench capacitors can be inspected by high resolution SEMs and the defect areas precisely analyzed.
High Spatial Resolution OBIRCH and OBIC Effects Realized by Near-field Optical Probe in the Analysis of High Resistance 200 nm wide TiSi Line
Authors: Nikawa K. , Saiki T. , Inoue S. , Ohtsu M. 
Published: December 2020

Abstract
The identification of voids and Si nodules in the Al stripes of integrated-circuit-device chips is a key part of failure analysis and process monitoring in the semiconductor industry. The optical-beam-induced resistance-change-detection (OBIRCH) method has been shown to be more useful in void detection than other methods. In this study, the wavelength of the laser used for heating the Al stripes on the Si chips has been changed from 633 to 1300 nm and the OBIRCH method has been modified to use a near-field (NF) optical probe as the heat source instead of a laser beam. Results showed that NF-OBIRCH method has three advantages over the conventional OBIRCH method: its spatial resolution is higher; the OBIRCH caused by heating can be observed using the metallized probe without interference from the optical beam induced current; and the OBIC can be observed using the apertured probe, in a high spatial resolution.
Advanced Failure Analysis of Deep-Submicron CMOS Device Dopant Profiles Using Scanning Kelvin Probe Microscopy
Authors: Moszkowicz L. , Kaszuba P. , Slinkman J. , Doezema L. 
Published: December 2020

Abstract
The use of scanning kelvin probe microscopy (SKPM) for analyzing two-dimensional dopant profiles on production-level silicon CMOS devices is described, with images of topography and dopant profiles presented. Both plan-view and crosssectional analyses are performed to measure CMOS device effective channel length (Leff), source-drain and well-junction depths. SKPM data not only tracked variations in Leff but uncovered anomalies in dopant that were responsible for device failure. For example, a nonfunctional ring-oscillator in a 0.25μm technology was debugged with SKPM. Details of sample preparation and the fabrication of durable, highly conductive (silicided) silicon kelvin probe tips which are key to acquiring reproducible, consistent data is also given.
Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication
Authors: Hua Y. N. , Guo Z. R. , An L. H. , Redkar Shailesh 
Published: December 2020

Abstract
In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.
Application of KOH Electrochemical Etch and Passive Voltage Contrast Techniques for Deep Sub-Micron CMOS Leaky Gate Detection
Authors: Chang Fred Y. , Chan Victer 
Published: December 2020

Abstract
This paper describes a novel de-process flow by combining cobalt silicide / nitride wet etch with KOH electrochemical wet etch (ECW) to identify leaky gate in silicided deep sub-micron process technology. Traditionally, leaky gate identification requires direct confirmation by gate level electrical or emission detection technique. Ohtani [1] used KOH electrochemical etch application to identify nonsilicided leaky gate capacitor in DRAM without using the above confirmation. The result of the case study demonstrates the expanded application of ECW etch to both silicided 0.18um logic and SRAM devices. Voltage contrast at metal 1 to assist leaky gate localization is also proposed. By combining both techniques, the possibility for isolating gate related defects are greatly enhanced. Case studies also show the advantages of the proposed technique over conventional poly level voltage contrast in leaky gate identification especially with devices that use local interconnect and nitride liner process.
A Comparison of Backside Emission Microscopy Systems
Authors: Davis Brennan V. 
Published: December 2020

Abstract
The need for failure analysis from the backside of the die has introduced new challenges in device analysis applications. Standard silicon based detectors are no longer as efficient due to the absorption of emission signals by the silicon substrate, which is now in the optical path between the device and the detector. The emergence of infrared detectors has offered a solution since emissions in this regime are not attenuated. This paper will describe a comparison made between a silicon detector and two of the most common IR detector materials.
EOS Simulation and Failure Analysis of Metallurgically Bonded Silicon Diodes
Authors: Teverovsky Alexander 
Published: December 2020

Abstract
Metallurgically bonded, glass-bodied DO-35 power rectifier diodes were electrically overstressed by applying forward and reverse current pulses. Forward current pulses varied from 0.1 to 3 ms with current amplitudes varying from 200 to 1000 A were applied to one group of diodes. Reverse bias current pulses in the microsecond range with amplitudes from 2 to 400 mA (above breakdown voltage) were applied to another group. A small-step cross sectioning in combination with electrical probing, light emission microscopy, liquid crystal technique, and chemical staining were used to reveal and compare damage in three groups of diodes: two overstressed groups and the third group which had failed during burn-in electrical testing. Failure mechanisms and peculiarities of damage created in these diodes and several case histories related to different types of diodes are discussed.
Computerized Quantification of the Dicing Process: The First Step Toward Related Die Cracking Failure Analysis
Authors: Glover Doug , Lynch John R. , Huseby Irvin 
Published: December 2020

Abstract
Die cracking is one of the primary failure areas in semiconductor manufacturing and in product longevity. Often die cracking emanates from stress concentrations formed on chips during the dicing process. In order to properly characterize and analyze die cracking relating to the dicing process, we must first properly and accurately quantify and characterize the dicing process. This paper describes the methodology to perform this first step in a premier fashion. In the past, quantification of the dicing process has been a manual operation usually under a microscope. Now there is a new state-of-the-art metrology tool (KIS2010 Inspection System) for quantifying all parameters associated with the dicing process. The system provides computer controlled robotic inspection combined with onboard statistical data reduction software to display results. The goal of this paper is to provide other engineers working in defect and failure analysis an insight into the power of this metrology tool and how it can provide a firm basis for characterizing failures related to the dicing process.
Application of TIVA in Design Debug
Authors: Kolachina Siva , Taylor Bill , Wills Kendall Scott , Cole Edward I. 
Published: December 2020

Abstract
Thermally-Induced Voltage Alteration (TIVA) is a relatively new technique for locating electrical defects in integrated circuits [1,2]. This paper describes a novel application of TIVA, to locate design anomalies. A newly designed integrated circuit with high and inconsistent Quiescent Power Supply Current (IDDQ) was initially diagnosed with limited success using various failsite isolation techniques. The TIVA technique was successful in accurately locating design anomalies. Results from TIVA identified a spurious ring oscillator in the design. Design modifications carried out using a focussed ion beam (FIB), verified the accuracy of the results from TIVA. This study clearly extends the use of TIVA beyond that of locating electrical defects and anomalies into the realm of design debugging.
Grafting FIB “Lift-Out” TEM Sample for Further Ion Milling and Its Application for Semiconductor Devices
Authors: Wang Nathan , Wu Jin , Daniel Sabbas 
Published: December 2020

Abstract
A technique to “graft” a FIB lift-out TEM sample onto a scrapped wedge polished sample was introduced. In this way, the sample can be ion milled with lower accelerating voltage to avoid FIB caused problems. This technique does not require special attachment for the FIB. Improved imaging quality and potential applications are discussed.
Advanced Acoustic Micro Imaging Applications: Deciphering Multiple Acoustic Echoes and Reflections
Authors: Komrowski Andrew J. , Curiel Luis A. , Sullivan Daniel J. D. , Nguyen Quang , Logan-Willams Lisa 
Published: December 2020

Abstract
The acquisition of reliable Acoustic Micro Images (AMI) are an essential non-destructive step in the Failure Analysis (FA) of electronic packages. Advanced packaging and new IC materials present challenges to the collection of reliable AMI signals. The AMI is complicated due to new technologies that utilize an increasing number of interfaces in ICs and packages. We present two case studies in which it is necessary to decipher the acoustic echoes from the signals generated by the interface of interest in order to acquire trustworthy information about the IC package.
IDDQ Testing—Conceptual Idea and Application in LED Integrated With IC Module
Authors: Joh Ng Joh , Hong Kong Boon 
Published: December 2020

Abstract
This paper presents IDDQ testing for LED integrated with IC module (ICM) circuit. To begin, brief introduction to IDDQ testing, the purpose and failure detectable with this method in CMOS IC context will be discussed. Then, the explanation will be focalized to ICM package and failure detectable with this method. A simulation and case study will be presented to show the usefulness of this testing. The results show that IDDQ testing is not only efficient in detecting intrinsic IC failure but also SMT process related problem like intermittent contact. Nonetheless, the discussion is merely conceptual and intended to give reader an idea of how IDDQ testing can be fully utilized in IC module testing, not the details of implementation.
Backside Application of Acoustic Micro Imaging (AMI) on Plastic Ball Grid Array (PBGA) and Plastic Quad Flat Pack (PQFP) Packages
Authors: Curiel Luis A. , Komrowski Andrew J. , Sullivan Daniel J.D. 
Published: December 2020

Abstract
Acoustic Micro Imaging (AMI) is an established nondestructive technique for evaluation of electronic packages. Non-destructive evaluation of electronic packages is often a critical first step in the Failure Analysis (FA) process of semiconductor devices [1]. The molding compound to die surface interface of the Plastic Ball Grid Array (PBGA) and Plastic Quad Flat Pack (PQFP) packages is an important interface to acquire for the FA process. Occasionally, with these packages, the standard acoustic microscopy technique fails to identify defects at the molding compound to die surface interface. The hard to identify defects are found at the edge of the die next to the bond pads or under the bonds wires. This paper will present a technique, Backside Acoustic Micro Imaging (BAMI) analysis, which can better resolve the molding compound to die surface interface at the die edge by sending the acoustic signal through the backside of the PBGA and PQFP packages.
A Novel Approach of Identifying Silicon Defects Using Passive Voltage Contrast Techniques Leading to Utilization of In-Line SEM Based Voltage Contrast Inspections to Drive Closed Loop Process Optimization and Defect Elimination
Authors: Fredrickson R. , Young R. , Cournoyer J. , Schmidt M. 
Published: December 2020

Abstract
The formation of silicon defects in 0.18um and smaller technology nodes has become a challenging device level defect to identify and eliminate. In this paper, we present a new method of passive voltage contrast that was initially used to locate silicon defects, experimental results revealing the key contributors to the formation of these defects, and a method of in-line identification by correlating SEM based in-line defect inspections to end of line SRAM fail bit maps. Silicon defects that form along the edge of an active region connect the source and drain with a low resistance leakage path that are successfully detected at later processing layers using voltage contrast techniques with a SEM based In-line inspection tool as well as after processing by using our method of passive voltage contrast. The systematic nature of this defect produces a consistent SRAM memory fail mode of single column fails. When these silicon defects are present, single column fails dominate the usual single and double bit fail modes. The physical location of the failing columns can be mapped back to the defect locations produced from the in-line inspections. This method was utilized to interpret experimental results in an effort to determine process parameters that produce silicon defects. It was found that STI depth plays a key role in the formation of these defects. Experiments were run where the depth was intentionally put at worst case so that the effectiveness of several alternative processes to repair the defects could be evaluated. It was shown that modulating the STI liner oxidation temperature had the largest effect compared to several other process parameters.
Time Domain Reflectometry Technique for Failure Analysis
Authors: Long Teoh King , Fern Ko Yin 
Published: December 2020

Abstract
In time domain reflectometry (TDR), the main emphasis lies on the reflected waveform. Poor probing contact is one of the common problems in getting an accurate waveform. TDR probe normalization is essential before measuring any TDR waveforms. The advantages of normalization include removal of test setup errors in the original test pulse and the establishment of a measurement reference plane. This article presents two case histories. The first case is about a Plastic Ball Grid Array package consisting of 352 solder balls where the open failure mode was encountered at various terminals after reliability assessment. In the second, a three-digit display LED suspected of an electrical short failure was analyzed using TDR as a fault isolation tool. TDR has been successfully used to perform non-destructive fault isolation in assisting the routine failure analysis of open and short failure. It is shown to be accurate and reduces the time needed to identify fault locations.
Multi-Layer Automatic Front Side Delayering Technique for Constructional Analysis
Authors: Coulson H. , Williamson K. , Shafrir Z. , Grimberg I. , Raz E. 
Published: December 2020

Abstract
Front side mechanical polishing of integrated circuits poses several technological complexities. This paper describes a unique automatic front side polishing technique, based on polishing at a shallow angle and exposing several layers, for NMOS/PMOS devices. This polishing technique is based on polishing at a very shallow angle up to 0.50 with plus or minus 0.1 micrometer accuracy to the target exposing several layers. The paper provides information on the several steps in the delayering process, namely deprocesing, chemical etching, and physical analysis. The benefits of the automatic polishing method developed are: exposing several metal layers without the need to deprocess to each layer separately, thus reducing both the polishing and the analysis time; the polishing can be stopped at any specific layer; direct and simultaneous measurements of structure overlays; direct inspection of embedded defects; and reducing artifacts associated with the etching process such as oxide steps, over etch, differential etching.
Advanced Mounting System and Method: To Establish and Maintain Predictable and Accurate Grind Plane Reference for Solder Joint Cross-Section Processing
Authors: McDonald Todd , Repko Thomas A. 
Published: December 2020

Abstract
Today's smaller structures, increasing standards and automation, amplify the demand for accurate and reliable cross-section mounting and grinding processes. This article presents an advanced and operated, finger adjustable, surface mount component fixturing device directly addressing these problems by holding components aligned during the encapsulation and grinding processes with greater accuracy, stability, and robustness. In the advanced method, samples are milled out of the PCB, but instead of using clips to hold the PCB, advanced mounting fixtures were employed to hold components in a true parallel and straight state, gripping the package edges and not the PCB. This advanced method for mounting and grinding cross-section samples is significantly more accurate and reliable for results establishing and maintaining the planarity of samples. When properly used, more accurate, consistent results will be achieved, and less data will be lost when compared to results of samples processed using regular mounting and grinding methods.