bluuebunny/crossref_metadata_2025_split huggingface dataset:
A Case Study—Improving FIB Passive Voltage Contrast Imaging for Deep N-Well Circuits
Authors: Mulder Randal 
Published: December 2020

Abstract
This paper presents a case study of a customer return that failed functional testing on the production tester. Investigation by applications and design engineering identified several analog circuit blocks where a possible failure mechanism could be located causing the functional failure mode seen at test. The identified circuit blocks all resided in deep n-well structures preventing traditional passive voltage contrast imaging (PVC) from being used to isolate the fault location. Neither functional probing nor active voltage contrast imaging were viable options to isolate the failure mechanism to a specific node. The analyst, having a good understanding of the principles of PVC and the difficulties associated with PVC imaging of deep n-well circuits, took advantage of a design feature in the device to restore the ability to perform passive voltage contrast imaging on these circuits. Using this enhanced PVC capability, two polysilicon capacitors with degraded oxide integrity were easily identified. This degraded oxide was verified to cause abnormal leakage to the substrate by means of nanoprobe analysis. Without identifying and taking advantage of a design feature not intended for failure analysis, locating these damage poly capacitors would have been extremely difficult because existing analysis techniques could only localize the failure to a number of circuit blocks. This paper presents a brief detailed over-view of PVC imaging, the issues with PVC imaging of deep n-well circuits, and an example of a previous attempt to overcome the deep n-well PVC problem. This review is then followed by the case study demonstrating the steps taken to restore PVC capability and concludes with recommendations for design for failure analysis (DFA).
Failure Analysis Methodology on Circular Patch Functional Failure Due to Device Parametric Drift
Authors: Quah A.C.T. , Chen C.Q. , Ang G.B , Nagalingam D. , Ng H.P. , Ng P.T. , Moon SeungJe , Teo Angela , Yip K.H. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
This paper describes the debug and analysis process of a challenging case study from wafer foundry which involved a circular patch functional leakage failure that was induced from device parametric drift due to thicker gate oxide with no detection signal from inline monitoring vehicles. It highlights the need for failure analyst to always be inquisitive and to deep dive into the failure symptoms to value-add the fab in discovering the root cause of the failure in challenging situation where information is limited.
Invisible Defect Root Cause Identification with Electrical and Chemical Analyses
Authors: Song Zhigang , Wang Yunyu , Pendyala Sweta 
Published: December 2020

Abstract
As semiconductor technology keeps scaling down, the conventional physical failure analysis processes have faced increasing challenges and encountered low success rate. It is not only because the defect causing a failure becomes tinier and tinier, but also because some of these defects themselves are invisible. Electrical nano-probing with narrowing down a defect to a single transistor has greatly increased the likeliness of finding a tiny defect in subsequent TEM (transmission Electron Microscope) analysis. However, there is still an increasing trend of encountering an invisible defect at most advanced technology nodes. This paper will present how to identify the root causes of three such invisible defects with the combination of electrical nano-probing and TEM chemical analysis.
Unusual Defects Generated by Wafer Sawing—An Update—Including Pick and Place Processing
Authors: Jacob Peter 
Published: December 2020

Abstract
At ESREF 2008, the paper “Unusual defects, generated by wafer sawing: Diagnosis, mechanisms and how to distinguish from related failures” had won the Best Paper Award. In the meantime, new experiences were collected, related to new methods as laser sawing and its specific ESD risks and additional failure mechanisms as backside damage, charging of foils, pad corrosion and sawing residue damages. This paper explains in detail these failure sources, including detailed explanations on root causes and physical mechanisms as well as important hints for failure analysts how to distinguish related failure signatures from those, which look similar but are of other origin.
Study of 1340 nm Continuous Laser Invasiveness on 28 nm Advanced Technologies
Authors: Penzes Maxime , Dudit Sylvain , Parrassin Thierry , Vallet Michel , Lewis Dean , Perdu Philippe 
Published: December 2020

Abstract
This paper presents a study about the invasiveness of 1340 nm continuous wave laser used for electrical failure analysis on 28 nm advanced technologies. It underlines the potential laser-induced degradation for deep submicron technologies that could jeopardize analysis results by modifying physical and chemical properties at substructure level. The impact of laser power on transistor morphology and electrical behavior is studied and the results of this study enable us to setup safe experimental conditions.
Innovative Laser Process for Gel Removal
Authors: Anderson Gregory Burt , Fordham Lance 
Published: December 2020

Abstract
High-power modules incorporating insulated gate bipolar transistors (IGBT) include a thick layer of dielectric insulating gel to prevent arcing. Chemical methods currently used to remove the gel are slow, taking up to 24 hours, while generating as much as a half-gallon of waste. High-pressure wet jets have also been used, but they cause significant damage to wire bonds. In this paper, we present a fast and efficient process for removing insulating gel from high-power modules. The method uses a CO2 laser to selectively open windows in the gel that are then filled with a few drops of solvent followed by a DI water rinse. The entire process takes less than an hour to prepare samples for inspection and analysis, while generating just 200ml of waste.
An Analysis of Random Telegraph Signal Noise in a Precise Analog Circuit
Authors: Wang Yuguo , Chatterjee Tathagata , Tian Weidong , Aggarwal Raj , Balster Scott , Cestra Gregory , Howard Steven , Barr Chris , Reyes Alexander 
Published: December 2020

Abstract
We analyzed the gain error issue and non-linearity issue of a precise Analog-to-Digital Converter (ADC) and found the root cause to be Random Telegraph Signal (RTS) noise in bipolar devices. The RTS noise produced nearly 1mV abrupt changes in a band-gap reference voltage, and affected ADC and other circuits where the reference voltage was used. We developed a new measurement method enabling us to detect RTS noise in bipolar with higher signal-to-noise ratio than traditional methods. We also developed an algorithm to extract RTS occurrence frequency and average magnitude. The RTS characterization capability has helped us invent a new bipolar structure and develop new processes to minimize RTS noise.
Development of Small Spot Thickness Capability on a Conventional Energy Dispersive X-Ray Fluorescence Spectrometer
Authors: Bogani Federica , Dobriyal Priyanka 
Published: December 2020

Abstract
The metal thickness of surface finish is an important consideration when plating on microelectronics. Metal finish thickness should comply with specification requirements to prevent serious reliability concerns. The thickness of metallic coatings is routinely determined by X-ray fluorescence (XRF) spectrometry. For conventional XRF instrumentation, typical focal spot sizes at the sample surface range in diameter from several hundred micrometers up to several millimeters. Micro- XRF focuses or collimates the X-ray beam to significantly smaller spot sizes, ranging from ~30 µm to 2 mm, thus obtaining a representative average of layer properties both at the surface and in-depth layers. This is a critical property for application in semiconductor industry where feature size is becoming progressively smaller. This work describes how a mid-range cost conventional XRF tool can be utilized for small spot size thickness measurement with the addition of a 0.25 mm diameter collimator.
Electrical Failures Due to Particle Induced Copper Wire Bond Corrosion
Authors: Kho W.F. , Chan Gary H.G. 
Published: December 2020

Abstract
Contamination by particles is one of the major causes of failures in integrated circuits. In some cases, particles may absorb moisture leading to electrochemical migration, dendrite growth, and electrical leakage and short failures. This work presents two case studies of particle induced corrosion of copper wire bond that resulted in an electrical failure. In the first case, adjacent pin resistive short failures were found to fail due to corrosion and electrochemical migration at wires that were in contact with calcium chloride particles. Analysis showed that the highly hygroscopic calcium chloride particles absorbed moisture and resulted in corrosion and electrochemical migration of the copper wires. For the second case, an electrical open failure after temperature cycle reliability test was found to be due to an organophosphorus particle being in contact with the wire.
Mechanism to Improve the Reliability of Cu Wire Bonding by Pd-Coating of the Wire
Authors: Qin Wentao , Anderson Tom , Chang George , Anderson Harold , Barrientos Denise 
Published: December 2020

Abstract
Coating of the Cu bond wire with Pd has been a rather widely accepted method in semiconductor packaging to improve the wire bonding reliability. Based on comparison of a Cu bond wire and a Pd-coated Cu bond wire on AlCu pads that had passed HAST, new insight into the mechanism of the reliability improvement is gained. Our analysis showed the dominant Cu-rich intermetallics (IMC) were Cu3Al2 for the Cu wire, and (CuPdx)Al for the Pd-coated wire. The results have verified the Cu-rich IMC being suppressed by the Pd-coating, which has been extensively reported in literature. Binary phase diagrams of Al, Cu, and Pd indicate that the addition of Pd elevates the melting point and bond strength of (CuPdx)Al compared with CuAl that formed with the bare Cu wire. The improvements are expected to decrease the kinetics of phase transformation toward the more Cu-rich IMC. With the suppression of the Cu-rich IMC, the corrosion resistance of the wire bonding is enhanced and the wire bonding reliability improved. We find that Ni behaves thermodynamically quite similar to Pd in the ternary system of Cu wire bonding, and therefore possesses the potential to improve the corrosion resistance.
Single Event Transient Acquisition and Mapping for Space Device Characterization
Authors: Pilia Roberta , Bascoul Guillaume , Sanchez Kevin , Mura Giovanna , Infante Fulvio 
Published: December 2020

Abstract
It is necessary for space applications to evaluate the sensitivity of electronic devices to radiations. It was demonstrated that radiations can cause different types of effects to the devices and possibly damage them [1][2]. The interest in the effect of Single Event Transient (SET) has recently risen because of the increased ability of parasitic signals to propagate through advanced circuit with gate lengths shorter than 0.65 nm and to reach memory elements (in this case they become Single Event Upset (SEUs)). Analog devices are especially susceptible to perturbations by such events which can induce severe consequences, from simple artifacts up to the permanent fail of the device. This kinds of phenomena are very difficult to detect and to acquire, because they are not periodical. Furthermore, they can vary a lot depending on different parameters such as device technology and biasing. The main obstacle for the analysis is due to the maximum frequency of these signals, which is unknown. It is consequently difficult to set a correct sample frequency for the acquisition system. In this document a methodology to evaluate SETs in analog devices is presented. This method allows to acquire automatically these events and to easily study the sensitivity of the device by analyzing a “SETs cartography”. The advantages are different: it allows to easily acquire and analyze the SETs in an automatic way; the obtained results allow the user to accurately characterize the device under test; and, finally, the costs due to the implementation of the tests are lower than a classical analysis performed by a particle accelerator.
Case Study—Lock-in Thermography Application in Failure Analysis of a System Level DC-DC μModule Regulator
Authors: Kumar Vikash , Karthikeyan Devraj 
Published: December 2020

Abstract
Fault localization is a common failure analysis process that is used to detect the anomaly on a faulty device. The Infrared Lock-In Thermography (LIT) is one of the localization techniques which can be used on the packaged chips for identifying the heat source which is a result of active damage. This paper extends the idea that the LIT analysis for fault localization is not only limited to the devices within the silicon die but it also highlights thermal failure indications of other components on the PCB (like capacitors, FETs etc on a system level DC-DC μmodule). The case studies presented demonstrate the effectiveness of using LIT in the Failure analysis process of a system level DC-DC μmodule regulator.
SRAM PFET and NFET Super FIN Characterization
Authors: Wei Yong , Baumann Frieder , Lucarini Stephen , Barth Karl , Song Zhigang , Katnani Ahmad 
Published: December 2020

Abstract
The State-of-the-Art FinFET technology has been widely adopted in the industry, typically at 14 nm and below technology nodes. As fin dimensions are pushed into the nanometer scale, process complexity is highly escalated, posing great challenges for physical failure analysis. Meanwhile, the accelerated cycles of learning for new technology nodes demand high accuracy and fast turnaround time to solve the material and interface issues pertaining to semiconductor processing or device failure. In this paper, we report a case study of fin related defect that caused device failure. Several analytical techniques, namely, Scanning Electron Microscopy (SEM), plan-view and cross-section Transmission Electron Microscopy (TEM) with Energy Dispersive X-ray spectroscopy (EDX), Electron Energy Loss Spectroscopy (EELS) and Z-contrast tomography were employed to characterize the defect and identify root-cause, leading to the resolution of this issue.
Further Inquiry into Xe Primary Ion Species for Circuit Edit Application
Authors: Ray Valery , Hadjikhani Ali , Favata Joseph , Ahmadi Seyedeh , Shahbazmohamadi Sina 
Published: December 2020

Abstract
Widespread adoption and significant developments in Focused Ion Beam technology has made FIB/SEM instrumentation a commonplace sample preparation tool. Fundamental limitations inherent to Ga ion species complicate usage of Ga+ FIB instruments for the modification of semiconductor devices on advanced technology nodes. Said limitations are fueling interest in exploring alternative primary species and ion beam technologies for circuit edit applications. Exploratory tests of etching typical semiconductor materials with Xe ion beams generated from two plasma ion sources confirmed advantages of Xe+ as a potential ion species for gas-assisted etching of semiconductor materials, but also revealed potential complications including, swelling of metal and Xe+ retention within the material arising from excessive Xe ion beam current density.
A Study on Error Corrected Code Failure-Induced Latent Defect in between High-k MIM Capacitors
Authors: Kim Jinseon , Kim Minsoo , Shin Minju , Nam Incheol , Kim Daesun , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jang Seongjin 
Published: December 2020

Abstract
For fault management, various types of error-correcting codes (ECC) have been widely used for most computers and memory. From a memory perspective, the ECC technique is generally adopted for DRAM modules to correct data corruption among multiple chips, not in-chip level. Recently, increased soft single-bit failures have accelerated introduction of the ECC technique into DRAM components. For reliability, fault generation technique by high voltage at high temperature, also known as burn-in stress, has been widely used in the IC manufacturing process. In DRAM, burn-in stress is also useful to screen latent defects or to predict device lifetime. In this paper, we studied un-correctable errors which occurred due to various types of storage node bridge defects in ECC DRAM. 12 faulty cells among 1,000 cells are observed after burn-in stress. Retention time of each cell is measured with automatic test equipment under the various temperature conditions, and activation energy were extracted from measurement results. Results of activation energy show that there were two types of faults, one was metal-metal hard bridge (0.14eV) and the other was dielectric-dielectric soft bridge (0.35eV), in comparison with normal cells (0.53eV). Moreover, soft bridge was carefully analyzed with TEM and nanoprobing showing that activation energy analysis was well-matched.
Application of AFP Nanoprobing Light-Induced Photovoltaic Current in the Failure Analysis
Authors: Chen C.Q. , Ng P.T. , Ang G.B. , Rivai Francis , Ting S.L. , Teo Angela , Ng H.P. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically. But sometimes the EFA spot coverage is too big to do nanoprobing analysis. Then further narrow-down is quite critical to identify the suspected structure before nanoprobing is employed. That means there is a gap between global fault isolation and localized device analysis. Under these kinds of situation, PVC and AFP current image are offen options to identify the suspected structure, but they still have their limitation for many soft defect or marginal fails. As in this case, PVC and AFP current image failed to identify the defect in the spot range. To overcome the shortage of PVC and AFP current image analysis, laser was innovatively applied in our current image analysis in this paper. As is known to all, proper wavelength laser can induce the photovoltaic effect in the device. The photovoltaic effect induced photo current can bring with it some information of the device. If this kind of information was properly interpreted, it can give us some clue of the device performance.
Predictive Failure Analysis of Solder Joints with Simultaneous High Speed EBSD and EDS
Authors: Lindsay J. , Trimby P. , Goulden J. , McCracken S. , Andrews R. 
Published: December 2020

Abstract
The results presented here show how high-speed simultaneous EBSD and EDS can be used to characterize the essential microstructural parameters in SnPb solder joints with high resolution and precision. Analyses of both intact and failed solder joints have been carried out. Regions of strain localization that are not apparent from the Sn and Pb phase distribution are identified in the intact bond, providing key insights into the mechanism of potential bond failure. In addition, EBSD provides a wealth of quantitative detail such as the relationship between parent Sn grain orientations and Pb coarsening, the morphology and distribution of IMCs on a sub-micron scale and accurate grain size information for all phases within the joint. Such analyses enable a better understanding of the microstructural developments leading up to failure, opening up the possibility of improved accelerated thermal cycling (ATC) testing and better quality control.
Investigating Root Cause of a Bubble Formation in Spin on Hardmask
Authors: Dar Rebecca , Behnke Jason , Baumann Frieder , Shepherd Tim , Teo Kok Hin (Rick) , Zhao Wayne , Moore Joshua , Dumas Laurent 
Published: December 2020

Abstract
Through inline processing of a prospective Spin on Hardmask (SOH) material, bubble defects were observed randomly across a wafer. Several complementary FA techniques were utilized to characterize the bubble defects including SEM, TEM, and chemical analysis techniques. The root cause of defect formation was identified as a raw material imperfection in SOH, which led to excessive outgassing. Imperfections within the substrate formed nucleation sites for outgassing of SOH material forming bubbles, which allowed voids to propagate. These findings led to implementation of greater quality control methods by the raw material manufacturer.
A Case Study of High SRAM Low Power Mode Current
Authors: Asquith John , Biyer Frank , Erington Kent , Gomez Nelson , Heineke Stephen , Wu Carey , Ybarra Juan 
Published: December 2020

Abstract
Low power mode current is a very important parameter of most microcontrollers. A non-production prototype microcontroller had high current issues with certain SRAM modules which were produced using a new memory compiler. All devices were measuring 100’s μA of low power mode current which was an order of magnitude higher than the requirement. Many failure analysis (FA) techniques had to be used to determine the root cause: Optical Beam Induced Resistance Change (OBIRCh), photo emission microscopy (PEM), microprobing, and nanoprobe device characterization. Transistor models and measurements of probe structures from the effected lots both predicted that the device low power mode current would meet expectations; however, all first silicon samples had elevated low power mode current. A knowledge of low power design methodology was needed to ensure all issues were discovered.
Correction of Stress Release During Sample Preparation for TEM CBED Measurements
Authors: Gluch Jürgen , Gall Martin , Zschech Ehrenfried , Mühle Uwe , Narendraraj Chandran , Hrabovský Miloš , Morávek Tomáš 
Published: December 2020

Abstract
In the vicinity of a through silicon via (TSV) used in 3D chip integration, the effect of dedicated strain engineering to enhance the carrier mobility in the channel of metal oxide semiconductor field effect transistors (MOSFETs) is superposed by a strain caused by cooling down from high process temperatures to room temperature. This additional strain influences the transistor characteristics, and consequently the product performance. The measurement of strain with high spatial resolution requires TEM-based methods. In this paper, convergent beam electron diffraction (CBED) is used for strain measurement. The strain state is significantly changed during the preparation of the TEM lamellae. The exact sample geometry and accurate materials parameters were used in FE modelling and strain simulation based on a physical model. The strain in silicon at several distances from the TSV were determined experimentally using TEM-CBED and compared with numerical simulations. High-quality sample preparation is crucial for reliable and reproducible TEM-based strain data, i.e., it is a necessary precondition for strain release correction based on FE modelling and simulation.