Sn Doping Effects in Solid-Phase Crystallized Ge Thin-Film Transistors
Authors: Moto Kenta , Yamamoto Keisuke , Imajo Toshifumi , Suemasu Takashi , Nakashima Hiroshi , Toko Kaoru 
Published: December 2020

Introduction

Low-temperature synthesis of high carrier mobility thin films on insulating substrates is actively being conducted to dramatically improve the device performance of thin-film transistors (TFTs). Ge is one of the candidates for next-generation TFTs because of its high carrier mobility and good compatibility with Si. We recently reported that the densification of amorphous (a-) Ge precursor in solid-phase crystallization (SPC) significantly enlarged the grain size of polycrystalline (poly-) Ge and improved Hall effect hole mobility μ
Hall [1]. The TFT using this Ge layer exhibited both high field effect mobility μ
FE (170 cm2/Vs) and on/off current ratio I
on/I
off (~102) without minimizing the channel region (< 1 μm) [2]. The key technology was thinning the 100 nm thick Ge film with a large grain size (3.7 μm) enough to fully deplete the channel. Very recently, we further improved μ
Hall by combining the precursor densification method with Sn incorporation in SPC [3,4]. In this study, we fabricate TFT using SPC-GeSn and further improve its performance.

Experimental Procedure

The a-Ge1−x
Sn
x
(0 ≤ x ≤ 4.5%) precursors were deposited on SiO2 glass substrates using the Knudsen cell of a molecular beam deposition system (base pressure of 5 × 10−7 Pa). The deposition rate of Ge was fixed at 1.0 nm/min at room temperature, whereas that of Sn was adjusted to obtain the targeted GeSn composition. The deposition time was 100 min. The precursors were densified by heating the substrate at 125 °C during deposition [1,3,4]. The samples were then loaded into a conventional tube furnace in an N2 atmosphere annealed at 450 °C for 5 h to induce SPC. The grown layers were analyzed by the electron backscattering diffraction (EBSD) measurement and Hall effect measurement (van der Pauw method).
We fabricated accumulation-mode metal source/drain (S/D) p-channel TFTs using SPC-GeSn. Pt and TiN were sequentially formed as a metal S/D and a capping layer, respectively. The PtGe/Ge contacts have low hole barrier height and are suitable for p-channel Ge-TFTs. We used Al/SiO2/Al2O3/SiO2/GeO2 for the gate stack with the equivalent oxide thickness of 17.7 nm. The channel width and length (W/L) were 55 and 5–10 μm, respectively. Here, all process including SPC were conducted below 450 °C.

Results and Discussion

First, we discuss the crystalline quality and electrical properties of the SPC-GeSn layer. Figure 1(a) shows that the crystal grain size dramatically varies with initial Sn concentration x and maximized at x = 1.6%. These results are roughly consistent with the solid solubility of Sn in Ge of approximately 1%–2%. We thinned x = 1.6% sample with the maximum grain size using chemical-mechanical polishing (CMP) to fabricate TFT for full depletion in poly-GeSn layer. As a reference, we also thinned x = 0% sample. Figure 1(b) shows that hole concentration p is constant in-depth direction although hole mobility μ
Hall decreases by thinning. The Sn doping in Ge provides lower p.
Finally, we discuss the TFT characteristics fabricated on the thinned SPC samples (55 nm for Ge and 50 nm for GeSn). Figure 2(a) shows that the typical p-channel transistor operation, i.e., drain current I
D increases with increasing gate voltage V
G. Figure 2(b) shows Sn doping reduces the off current I
off significantly under keeping the on current I
on. This reflects the electrical properties of the GeSn film obtained by the Hall effect measurement (Fig.1 (b)). Figure 3 summarizes the relationship between μ
FE and I
on/I
off for different channel length (L = 5, 10, and 15 μm) in the same substrate. The experimental data show a clear increase in variability as the channel length decreases, which is in good agreement with the trends of poly-Si-TFTs. This is the first result showing such variability reflecting grain boundary at poly-Ge and GeSn. Furthermore, Sn doping improves I
on/I
off by roughly an order of magnitude although μ
FE is almost identical. These results thus demonstrate the usefulness of Sn doping of polycrystalline Ge in TFT application. The current TFT performance will be further improved by the optimization of Sn concentration, film thickness, and channel dimensions (W/L).

Reference

[1] K. Toko, K. Moto et al., Sci. Rep. 7, 16981 (2017).
[2] K. Moto et al., Appl. Phys. Lett. 114, 212107 (2019).
[3] K. Moto et al., Sci. Rep. 8, 14832 (2018).
[4] K. Moto et al., Appl. Phys. Lett. 114, 112110 (2019).

Figure 1