(Invited) Metallic Contamination Control in Advanced ULSI Processing
Authors: Saga Koichiro 
Published: February 2020

As semiconductor devices continue to shrink, metallic contamination on silicon surfaces become to have a detrimental impact on ULSI device performance and yield. Surface metal impurities degrade gate oxide integrity [1] and cause the whisker growth in film deposition [2] and the crystal defect growth on a photomask for 193nm exposure [3], while metal impurities dissolved in silicon cause recombination centers and result in junction leakage [4] and cause dark current in image sensors [5]. In this article, we have extensively reviewed metallic contamination control including the analysis, prevention, removal, and gettering in advanced ULSI manufacturing.
Trace metal contamination on the silicon surfaces can be detected with VPD- or LPD TXRF, AAS, and ICP-MS and these methods have been widely used. These analyses provide average concentration on the whole wafer surface and even direct TXRF provide average concentration on the 10 mm diameter area. However, metal impurities accidentally deposited in wafer processing such as reactive ion etching are localized [6]. Therefore, the methods to easily detect localized metal atoms are required. When III-V compound semiconductor materials are introduced for high mobility channels, the detection sensitivity on the III-V semiconductor surface by TXRF and the metal collection efficiency become critical issues [7]. Changing chemistry for the cleaning of the III-V surface will be inevitable [8].
As wafer diameter becomes larger and gate dielectric thickness become smaller, single-wafer cleaning have become popular. The single-wafer cleaning can prevent re-deposition of metals and use ozone-based liquid or dilute chemistries.
In order to control metal impurities in silicon, understanding of the penetration and diffusion behaviors and efficient gettering are necessary. Surface metals penetrate silicon even through SiO2 or Si3N4 films by the collision of the surface metals and dopant atoms during ion implantation and subsequent annealing [9]. The amount of metals penetrating the silicon substrate depends on metal species and the oxide thickness. W is more difficult to penetrate the SiO2 film than Fe, Cr, Ni and Cu. The penetration of metals with a low diffusion coefficient in SiO2 such as W can be controlled by varying the SiO2 thickness. On the other hand, fast diffusers such as Fe and Cu cannot be always reduced by an increase in the SiO2 thickness. It is remarkable that Cr and W metals penetrate the silicon substrate through the Si3N4 film more easily than through the thermally-grown SiO2 [9]. This phenomenon can be explained by the ab-initio calculations of the diffusion barriers of metals in high temperature cristobalite SiO2 and β-Si3N4. These metals on Si3N4 films must be strictly controlled before ion implantation.
Metals penetrating silicon generate deep levels in silicon. The depth profiles of the metal-induced deep level depend on metal species. We have demonstrated the deep level, capture cross-section, and the depth profile of thermally-diffused W in silicon [10].
In-wafer distribution of recombination centers can be detected with high sensitivity and visualized with μ-PCD and photoluminescence. The distributions of surface metal concentration measured with TXRF before ion implantation are in good agreement with that of recombination lifetime after ion implantation followed by annealing. The low level surface Fe and Ni contamination as little as 2 × 1011 atoms/cm2 can generate recombination centers even when dopants were implanted through even 20-nm-thick SiO2 [9].

Gettering is effective to mitigate the influence of metal impurities on device characteristics. Transition metals are trapped at the high-dose boron or phosphorous implanted region and the dislocation loops in low-energy ion implanted silicon [11]. The oxygen-containing dislocation loops generated by phosphorous ion implantation can be gettering sites for Fe and Cr, while high concentration of phosphorous and/or vacancies will chemically bond with Cu and Ni. Gettering design based on physical properties of metal species must be necessary.
Reference
[1] P. S. D. Lin, J. Electrochem. Soc., 131, 1878 (1983).
[2] G. M. Choi, ECS transactions, vol. 11, no. 2, p.133.
[3] K. Saga, et.al, Proc. of SPIE, 6730-44 (2007).
[4] T. Kuroi, et. al, Tech. Digest of SSDM ’92 (1992).
[5] W. C. McColgin, et.al, Mat. Res. Soc. Symp., Proc. Vol. 262, 1992 Material Research Society.
[6] T. Tomita, et. al, ECS proceeding volume, PV 98-13.
[7] H .Fontaine, T. Lardin, ECS transactions,58 (6) 327-335 (2013).
[8] D. H. van Dorp, et. al, Solid State Phenomena Vol. 219 (2015) pp 56-58

[9] K. Saga, et.al, ECS Journal of Solid State Science and Technology, 4 (5) P131-P136 (2015).
[10] E. Simoen, K. Saga, J. Lauwaerta, and H. Vrielincka, ECS Transactions, 64 (11) 219-228 (2014).
[11] K. Saga, Solid State Phenomena Vol. 187 (2012) 283-286