bluuebunny/crossref_metadata_2025_split huggingface dataset:
Effectiveness of Non Destructive Physical Analysis Method Using X-ray CT Imaging
Authors: Mizoguchi Akira , Takeuchi Koichiro 
Published: December 2020

Abstract
Now we are attempting to apply non destructive analysis from evaluation tests or failure analysis to acceptance tests or production tests. Needless to say non destructive analysis has an advantage of conserving the state of samples and the reducing the time of analysis as compared to conventional methods with destructive physical analysis. Moreover, we are paying attention to the following reasons for nondestructive physical analysis. It is difficult to keep the reproducibility of the analysis because of the high skill level required for destructive physical analysis. On the other hand, high reproducibility can be easily achieved by fixing the condition or parameters of the device during nondestructive analysis when performed by tools like X-ray. Moreover, we expect that neither the analytical result nor the quality of the nondestructive analysis depends upon the worker's capability. In this paper we will discuss the following two items from the viewpoint of quality assurance. 1. The method of the screening for fake parts (1) The procedure flow for the production discontinued parts (2) The comparison and examination between the diagnostic using X-ray computed tomography (X-ray CT) images and various examinations (3) Other observation cases using X-ray CT images 2. Effectiveness and consideration in reliability evaluation test using X-ray CT image (1) Comparison of observation cases with a variety of jointing points in parts (2) Consideration of application of nondestructive observation technique in reliability test Use of X-ray CT images is effective in diagnosing the quality of the product or the process. Moreover, we find that use of X-ray CT images is effective for the improvement of the reproducibility of the evaluation examination. Then we find that use of X-ray CT images can reduce the time of evaluation examination too.
Failure Analysis of Stacked-Die Devices by Combining Non-Destructive Localization and Target Preparation Methods
Authors: Schmidt Christian , Simon Michél , Altmann Frank , Nowodzinski Antoine 
Published: December 2020

Abstract
The paper will present an approach for non-destructive localization of thermal active defects at multi chip devices combining the Lock-in Thermography and following local X-Ray inspection. In combination of both methods inner defects in inter chip connections of complex device built ups can be found in a non-destructive way before opening the device. The methods were demonstrated at defective flip chip devices with a high ohmic daisy chain with lots of chip to chip contacts. Subsequently, cross section analysis at located high ohmic contacts was performed in order to find the root cause of the failure.
Damage Induced Field Failures of Electrical Contacts
Authors: Munukutla Aravind , Rahn Randy , Lewis J.S. 
Published: December 2020

Abstract
Degradation of contact mating surfaces can produce a wide range of problems including intermittent failures and also full functional failures in all computer systems. This paper discusses the complexity involved with investigating the failure mechanism and root cause for intermittent memory failures on a product from end customers. Also discussed in detail is the approach of fault isolation followed by hypothesis development & physical analysis to arrive at root cause of failure. Fault isolation was achieved through register probing. Three major hypotheses were put forth namely plastic debris, misalignment and contact area issues. The physical analysis data collected through optical inspection, 2D x-ray, cross section and SEM analysis coupled with EDX to prove or disprove the hypotheses, revealed contact area corrosion in the form of nickel oxide. Contributors like gold plating thickness and plating porosity of the mating surfaces was verified to be not an issue in this case. Further analysis on the connector pins, memory modules and the contact area indicated damage to the connector pins leading to nickel exposure. The root cause for damage to the pins was analyzed to be a result of memory modules being inserted at an angle. Further studies are planned to look into design issues of connectors and memory modules to minimize damage to the contact area.
Two-Photon X-Variation Mapping Based on a Diode-Pumped Femtosecond Laser
Authors: Serrels K. A. , Reid D. T. , Lundquist T. R. , Vedagarbha P. 
Published: December 2020

Abstract
By inducing two-photon absorption within the device layer of a proprietary silicon test chip, the first nonlinear variant of X-variation mapping is reported by demonstrating frequency mapping of a ring oscillator circuit at 1.55µm.
Quantitative, Nanoscale Free-Carrier Concentration Mapping Using Terahertz Nearfield Nanoscopy
Authors: Wittborn J. , Weiland R. , Huber A. J. , Keilmann F. , Hillenbrand R. 
Published: December 2020

Abstract
We use ultra-resolving terahertz (THz) near-field microscopy based on THz scattering at atomic force microscope tips to analyze 65-nm technology node transistors. Nanoscale resolution is achieved by THz field confinement at the very tip apex to within 30 nm. Images of semiconductor transistors provide evidence of 40 nm (λ/3000) spatial resolution at 2.54 THz (wavelength λ = 118µm) and demonstrate the simultaneous THz recognition of materials and mobile carriers in a single nanodevice. The mobile carrier contrast can be clearly related to near-field excitation of THz-plasmons in the semiconductor regions. The extraordinary high sensitivity of our microscope provides THz near-field contrasts from less then 100 mobile electrons in the probed volume.
Quality Evaluation Techniques of Solar Cell Module
Authors: Murahara Daisuke , Shimizu Wataru , Kubota Hidehisa , Oda Tamiko , Yabe Kazuhiro 
Published: December 2020

Abstract
We have developed a process diagnostics system for photovoltaic energy modules based on standard methods and practices already developed for LSI and MEMS technologies. This paper provides a description of methods used to ensure the conformation of solar cell modules to the rigors of high-quality manufacturing necessary for reliable photovoltaic energy production when exposed to long-term environmental use. We have verified the possibility of inspecting each solar cell and the module assembly in detail for several photovoltaic technologies, specifically monocrystalline Si, polycrystalline Si, and CuInxGa1-xSe2 An objective set of criteria for the quality of each module can be provided by this method for use in module selection by consumers. Moreover, the quality of conformance and reliability data can be used as feedback to the manufacturer to minimize the number of defects created during manufacturing process and ameliorate their effects.
System Level FA on Transmission Line Issues
Authors: Konkol Nicholas 
Published: December 2020

Abstract
One issue that faces failure analysis at the system level is impedance mismatched transmission lines resulting from developers pushing the edge of trace layout recommendations. When transmission lines on printed circuit boards are routed in such a way as to allow for impedance mismatches, the effects can be unwanted on the signal that the line carries. Techniques can be used for discovering if capacitance, resistance, or split planes are creating the impedance mismatches that are resulting in the system level failure seen by the customer.
Failure Analysis Power Cycling Tool – FAPCT
Authors: Chua Yi Yun 
Published: December 2020

Abstract
One of the problems for failure analysis (FA) is to perform power cycling to stress the motherboard in order to duplicate the failure. The other problem is the timing is not synchronizing correctly. For this purpose, a user-friendly with extra feature program called Failure Analysis Power Cycling Tool (FAPCT) was developed to resolve problems associated with power cycling and enhance the AC cycling tools, which is more suitable for FA purpose. With this hardware and software, the FAE is provided one more option to duplicate intermittent or other issues that need to do power cycling to capture the failure. The hardware cost is only about 600 USD, which is consider at the lower cost hardware for a FA tools to do power cycling although there is some limitation compare to some hardware available in the market.
Fast Turn-around Failure Analysis of Metal Interconnection Using FIB and LA ICP-MS
Authors: Pan Zixiao , Wei Wei , Li Fuhe 
Published: December 2020

Abstract
This paper introduces our effort in failure analysis of a 200 nm thick metal interconnection on a glass substrate and covered with a passivation layer. Structural damage in localized areas of the metal interconnections was observed with the aid of focused ion beam (FIB) cross-sectioning. Laser ablation inductively coupled plasma mass spectroscopy (LA ICP-MS) was then applied to the problematic areas on the interconnection for chemical survey. LA ICP-MS showed direct evidence of localized chemical contamination, which has likely led to corrosion (or over-etching) of the metal interconnection and the assembly failure. Due to the high detection sensitivity of LA ICP-MS and its compatibility with insulating material analysis, minimal sample preparation is required. As a result, the combination of FIB and LA ICP-MS enabled successful meso-scale failure analysis with fast turnaround and reasonable cost.
Innovative Methodologies of Circuit Edit on Wafer-Level Chip Scale Package (WLCSP) Devices
Authors: Liu Shih-Ting , Liu Tao-Chi , Chang Ming-Lun , Lin Jandel 
Published: December 2020

Abstract
Contrary to traditional packages, packaging and testing of wafer-level chip scale package (WLCSP) are done before wafer dicing. The package can’t be rebuilt on a single chip; therefore, the failure analysis and debug performed by Circuit Edit (CE) on ICs with WLCSP face challenges. In addition, there are route designs on the package level of WLCSP devices, which are unique compared with traditional packages. CE is required on both chip and package level of WLCSP devices. This package technology offers the smallest possible package size; consequently, it has seen wider use lately. Developing the approaches of FIB edits on a fully-packaged WLCSP device is indeed essential. Thus, methodologies for CE and debug on WLCSP devices will be explored in this study.
Application of Lock-in Thermography for Backside Failure Localization Using Solid Immersion Lenses
Authors: Schmidt Christian , Große Christian , Altmann Frank , Schulz Jürgen , Seibt Alexander 
Published: December 2020

Abstract
In this paper the application of solid immersion lenses (SIL) in combination with Lock-in Thermography will be demonstrated for backside defect localization. The paper will give an introduction into Lock-in Thermography technique and presents a new developed easy-to-use holding system to adapt SIL for high resolution thermal imaging. It will be shown that defect localization can be applied from the backside of the chip up to a silicon thickness of 250µm using the same SIL. The relationship between the bulk silicon thickness and the resulting optical parameters was investigated.
Fast Mixed Field Material Removal Using New Dielectric Etch Solution
Authors: Makarov Vladimir V. , Krasnobayev Leo , Hahn James 
Published: December 2020

Abstract
A new application of the Novel Dielectric Etch solution for FIB Circuit Edit is reported to allow smooth and fast removal of copper dummies/dielectric layers for exposure of the circuitry underneath. Experimental data on the selectivity of the removal of dummies as a function of the ion beam current density is provided. Examples of de-processing several layers to expose a line of interest as well as the exposure of fine copper lines beneath the copper dummies/dielectric layer are presented.
Resolving the Failure Analysis Challenges on Stacked Die Structure in Lead Frame Chip Scale Package
Authors: Mendaros Raymond G. , Salimbangon Jon Carlo P. 
Published: December 2020

Abstract
Access to critical die and package structures for failure analysis purposes is complicated in stacked die devices in small packages, such as thin plastic Lead Frame Chips Scale Packages also known as Quad Flat No Leads Packages. This paper discusses the failure analysis solutions developed to effectively access the areas of interest. It illustrates two different ways of analyzing the bottom die: a repackaging technique and a technique for accessing from the backside of the bottom die. One of the major concerns during the evaluations that had been addressed was the difficulty of removing the nonconductive die attach material in between the top and bottom die. This was resolved by a novel method of thermal decomposition of the material. Observations suggested that the die extraction process did not introduce surface oxidation or contamination that may have led to a bonding failure.
Device Selection for Failure Analysis of Chain Fails Using Diagnosis Driven Yield Analysis
Authors: Schuermyer Chris , Benware Brady , Rhodes Graham , Appello Davide , Tancorre Vincenzo , Riewer Olivia 
Published: December 2020

Abstract
This work presents the first application of a diagnosis driven approach for identifying systematic chain fail defects in order to reduce the time spent in failure analysis. The zonal analysis methodology that is applied separates devices into systematic and random populations of chain fails in order to prevent submitting random defects for failure analysis. Two silicon case studies are presented to validate the production worthiness of diagnosis driven yield analysis for chain fails. The defects uncovered in these case studies are very subtle and would be difficult to identify with any other methodology.
Practical Implementation of Soft Defect Localization (SDL) in Mixed Signal and Analog ICs
Authors: Barbian Eric , Crow Gretchen , Swe Win Thandar , Phillips Mark C. 
Published: December 2020

Abstract
Dynamic Laser Stimulation (DLS) techniques for Soft Defect Localization (SDL) have been well documented for logic devices [1][2]. More recent literature has broadened the traditional SDL pass/fail mapping by employing multiple device parameters including power analysis [3], spectrum response [4], and other analog variations [5]. A practical and efficient implementation of SDL without the use of synchronization or traditional Automatic Test Equipment (ATE) hardware is presented. A dynamic way of analyzing many parameters of mixed signal and analog ICs can be obtained through the use of a high waveform rate oscilloscope, feedback loop, or discrete comparator. Multiple case studies are shown to illustrate the methodology.
A Systematic Failure Analysis to Reveal the Mystery of Lower N-Well Resistance
Authors: Zhu David , Neo Soh Ping , Quah Alfred , Ang Ghim Boon , Zhu Lei , Huang Yanhua , Koo Hong Tak , Yau Moi Kian , Hninhnin Ma , Dayanand Nagalingam 
Published: December 2020

Abstract
In this paper, we will describe a low yield case which revealed itself as leakage failures near the wafer edge. A systematic problem solving approach was used based on the application of a variety of FA techniques such as electrical curve tracing, Spreading Resistance Probing (SRP), Secondary Ion Mass Spectrometry (SIMS), and Chemical Analysis coupled with extensive Fab investigations. These techniques transformed an invisible defect into a visible one, leading to a full resolution of the issue with good understanding of the failure mechanism and the root cause. We will show that the wafer edge leakage was the result of N-type contamination of the substrate due to Phosphorus outgassing from the V-ring during the high temperature Argon anneal process.
From the Store Shelf to Device-Level Atom Probe Analysis: An Exercise in Feasibility
Authors: Larson D. J. , Lawrence D. , Olson D. , Prosa T. J. , Ulfig R. M. , Reinhard D. A. , Clifton P. H. , Kelly T. F. , Lefebvre W. 
Published: December 2020

Abstract
There are many opportunities in semiconductor processing where atom probe tomography (APT) analysis of a finished product is desirable; competitive analysis and failure analysis are two good examples, and only recently have APT results been obtained from fully processed "off-the-shelf" transistor structures that are part of a finished product. This paper explores the feasibility of APT analysis for fully packaged integrated-circuit microelectronic devices by detailing the various options available in specimen preparation and the resulting analyses. The goal of this work is to take an off-the-shelf microelectronics product and perform APT analysis on various device-level components. This work demonstrates that a wealth of high quality information may be obtained from site-specific APT analysis of post-production microelectronic devices. The yield of useful results from such analyses has not yet been determined, but the small number of specimens analyses (four) yielded quality results in the first attempt.
Nano Probe Analysis of Device Characteristics Affected by Ring Type Crystalline Defect
Authors: Lee Jong Hak , Lee Yu Jun , Kim Jung Sam , Jeong Seo Kyung , Kim Min Su , Oh Seok Hoon , Jung Kyoung Wook , Son Soo Yong , Kim Chang Reol 
Published: December 2020

Abstract
In this work, crystalline defects (dislocations) occurred in the silicon substrate during annealing SOD (Spin On Dielectric) which is an easy choice for its superior STI gap-fill ability. The reversal of address data that share same SIO (Signal Input Out) line in a DQ arises from crystalline defects. The failure analysis of physical methods has difficulty finding minute defects within the active because it is scarcely detectable from the top view. Situation can be well understood by electrical analysis using the nano probe. Due to its ability to probing contact nodes around the fail area, a ring type crystalline defect which is hardly detected from the top view was effectively analyzed by 3D TEM with the assistance of nano probe. This work shows that hybrid analysis of electrical method by nano probe and physical method by 3D TEM is useful and effective in failure analysis in semiconductor.
Closer to the Theoretical Limit: Spherical Corrections to Aplanatic Solid Immersion Imaging with Adaptive Optics
Authors: Lu Y. , Ramsay E. , Stockbridge C.R. , Yurt A. , Köklü F. H. , Bifano T. G. , Ünlü M. S. , Goldberg B. B. 
Published: December 2020

Abstract
Aplanatic solid immersion lens (SIL) microscopy is required to achieve the highest possible resolution for next generation silicon IC backside inspection and failure analysis. However, aplanatic SILs are susceptible to spherical aberration introduced by substrate thickness mismatch. We have developed a wavefront precompensation technique using a MEMS deformable mirror and demonstrated an increase in substrate thickness tolerance in aplanatic SIL imaging. Good agreement between theory and experiment is achieved and spot intensity increases by at least a factor of two to three are demonstrated for thicknesses deviating several percent from ideal. This technique is also capable of fixing aberrations due to SIL fabrication, off-axis imaging and refractive index mismatch.
A Silicon Debugging Methodology on Customer Prototype for Wafer Foundries
Authors: Zhihong Mai , Hau Ng Tsu , Khalid Dawood M. , Kee Tan Pik , Lam Jeffrey 
Published: December 2020

Abstract
IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the failure location by InGaAs microscopy, upon which the failure was identified to be caused by a latch-up issue. In the second case, due to confidentiality considerations from the customer, full information could not be provided to the foundry for silicon debugging. The paper illustrates the ability to effectively debug a failure despite being constrained by limited information from the customer.
Counterfeit IC’s Overview – From a Test Lab’s Perspective
Authors: Loaney Dave 
Published: December 2020

Abstract
Counterfeiting of electronic components continues to be an evolving issue that greatly impacts many companies around the globe. And with so many initiatives that have either been enacted or are in the works, there is a significant amount of confusion and even fear in our industry. The financial impact and potential loss of life related to counterfeit components has become so great that an enormous amount of attention is now being devoted to identifying and mitigating this risk by both private industry and governments agencies around the world. Many companies are reaching out to test labs for both the testing of their components and direction on how to address some of these issues. This paper addresses a few of the questions that our lab is getting from some of our customers regarding counterfeit IC’s and how we have answered those questions. The goal is to provide some additional insight to allow others to address this issue proactively and without fear.
Logic Yield Learning Vehicle Failure Analysis in Technology Development
Authors: Song Zhigang , Beaudoin Felix , Lucarini Stephen , Wu Stephen , Wang Yunyu , Arie Lior , Steiner Kobi 
Published: December 2020

Abstract
With the microelectronic technology progresses in nanometer realm, like SRAM, logic circuits and structures are also becoming dense and more sensitive to process variation. Logic failures may have different root causes from SRAM failure. If these technology weak points for logic circuits are not detected and resolved during the technology development stage, they will greatly affect the product manufacturing yield ramp, leading to longer time of design to market. In this paper, we present a logic yield learning methodology based on an inline logic vehicle, which includes several scan chains of different latch types representative of product logic. Failure analysis for the low yield wafers had revealed several killer defects associated with logic circuits. A few examples of the systematic failures unique to logic circuits will be presented. In combination with SRAM yield learning, logic yield learning makes the technology development more robust thus improving manufacturability.
Image and Information Enhancement by Combining Brightfield and Darkfield Optical Images
Authors: Rosales Sonny Benson P. , Badillo Andrew C. , Oblefias Wilma R. 
Published: December 2020

Abstract
Image enhancement algorithm by combining brightfield and darkfield images is presented on this paper. The result combines the unique features of each illumination plus the power of differential interference contrast (DIC) even in the absence of DIC hardware and sophisticated software. The effectivity of the method is illustrated on actual samples with height variation.
Low Temperature Fault Isolation Using Soft Defect Localization
Authors: Staller Kristopher D. 
Published: December 2020

Abstract
Cold temperature failures are often difficult to resolve, especially those at extreme low levels (&lt; -40°C). Momentary application of chill spray can confirm the failure mode, but is impractical during photoemission microscopy (PEM), laser scanning microscopy (LSM), and multiple point microprobing. This paper will examine relatively low-cost cold temperature systems that can hold samples at steady state extreme low temperatures and describe a case study where a cold temperature stage was combined with LSM soft defect localization (SDL) to rapidly identify the cause of a complex cold temperature failure mechanism.