bluuebunny/crossref_metadata_2025_split huggingface dataset:
Towards Sustainable Innovations - essay in memoriam of Andries Nentjes
Authors: Krozer Yoram 
Published: December 2020

Aim: This paper assesses theoretically and empirically three key factors for sustainable development within context of debates about economy and environment: autonomous technological change, induced technological change and barriers of entry to innovations.

Design/research methods: The paper covers a literature review on strong versus weak sustainability, followed by an explanation of autonomous technological change. Statistical analysis with literature review on induced technological change due to consumers’ and policy demands for sustainable innovations, as well as literature review on policy support for the incumbent interests that rival sustainable innovations is provided. The information used is largely based on two chapters in the book on sustainable innovations (Krozer 2015), and presented in the context of long scientific cooperation with the late Andries Nentjes.

Conclusion/findings: The economic theoretical debates are hardly relevant for policies on sustainable innovations, because political views are inconsistent with observations and change during fluctuations in economic outcomes. The main conclusion is that autonomous technological change is the driver of sustainable innovations. Present policies pose barriers of entry to sustainable innovations, where the global value of support for vested interest exceeds the market potential for induced technological change due to demands of policies and consumers put together.

Originality/value of the paper: The study contribution to understanding of autonomous and induced technological change, showing that shifting policy support away from the incumbent interests towards sustainable innovations is key for sustainable development.
Hegyi Ádám: HUNGARICA IN DER DISSERATIONSSAMMLUNG DES NÜRNBERGER NATURFORSCHERS CHRISTOPH JACOB TREW (1695‒1769) KATALOG 1582‒1765
Authors: P.Szabó Béla 
Published: December 2020

P.Szabó Béla könyvismertetése Hegyi Ádám által feltárt: HUNGARICA IN DER DISSERATIONSSAMMLUNG DES NÜRNBERGER NATURFORSCHERS
CHRISTOPH JACOB TREW (1695‒1769) KATALOG 1582‒1765 című művéről.
TENK ANTAL: DICSŐ MÚLTUNK III. A MAGYARÓVÁRI GAZDASÁGI AKADÉMIA SZEREPE MEZŐGAZDASÁGUNK 200 ÉVES FEJLŐDÉSÉBEN (1818-2018).
Authors: Surányi Béla 
Published: December 2020

Surányi Béla könyvismertetése Tenk Antal :" Dicső múltunk III. A Magyaróvári Gazdasági Akadémia szerepeMezőgazdaságunk 200 éves fejlődésében (1818-2018)
Determinant Factor of Food Farming Vulnerability in Banten Province To Support Climate Change Adaptation
Authors: Suciantini  , Estiningtyas Woro , Rahman Adi 
Published: December 2020

Food crop is one of the most impacted agricultural sectors by climate related disaster. The negative impacts of climate related disaster could be assessed by its vulnerability level that depends on various indicators including exposure, sensitivity, and adaptive capacity. This paper aims to identify the determinant factors that influence the vulnerability of food farming based on the characteristics of land resources, climate and water, and socio-economic factors at the district level in Banten Province, and to develop recommendations on climate adaptation. Identification of the dominant factors, which most contribute to the level of vulnerability, is one of the main considerations to determine the strategy of adaptation. Our results showed that the main determinant factors varied among districts. The most important factors were Oldeman’s climate type (SEI12), the ratio of the number of extension agents to rice field area (ACI3), and the ratio of the number of farmer groups to rice field area (ACI4). SEI12 deals with the climate, whereas ACI3 and ACI4 are related human resources and institutions. Further, although urban area had high exposure and sensitivity as in rural area, but the adaptive capacity for the urban area was still high. Therefore, the level of vulnerability was reduced in urban, but still high in rural area. More efforts are expected to adapt climate related disaster in rural area.
A Noise Generator for Embedded Circuits Testing
Authors: Flores Maria da Glória , Negreiros Marcelo , Carro Luigi , Susin Altamiro 
Published: December 2020

This paper describes the implementation of a white noise generator to be used as the input signal of a new method for testing analog-to-digital converters (ADCs) and linear filters. The main goal of this method is to avoid the comparison of the output signal with a known and very precise reference input. The proposed white noise generator is easily implemented, with less complexity than others excitation signals. The use of noise as the input signal avoids concerns about the inherent noise present in all electronic systems. The testing technique is based on the analysis of the spectral response of the CUT output. This paper covers the generation of the excitation signal, as well as simulation and practical results are presented to prove the efficiency of the test method.
A Cryptography Core Tolerant to DFA Fault Attacks
Authors: Moratelli Carlos R. , Cota Érika , Lubaszewski Marcelo S. 
Published: December 2020

This work describes a hardware approach for the concurrent fault detection and error correction in a cryptographic core. It has been shown in the literature that transient faults injected in a cryptographic core can lead to the revelation of the encryption key using quite inexpensive equipments. This kind of attack is a real threat to tamper resistant devices like Smart Cards. To tackle such attacks, the cryptographic core must be immune to transient faults. In this work the DES algorithm is taken as a vulnerable cryptosystem case study.We show how an attack against DES is performed through a fault injection campaign. Then, a countermeasure based on partial hardware replication is proposed and applied to DES. Experimental results show the efficiency of the proposed scheme to protect DES against DFA fault attacks. Furthermore, the proposed solution is independent of implementation, and can be applied to other cryptographic algorithms, such as AES.
Impact of the Nitrogen Concentration of Sub-1.3 nm Gate Oxides on 65 nm Technology Transistor Parameters
Authors: Rotondaro A. L. Pacheco , Laaksonen R. T. , Singh S. P. 
Published: December 2020

The nitrogen concentration of ultrathin gate oxides (sub-1.3 nm) was varied in a wide range (from 13 % to 23 %). The threshold voltage and the channel carrier mobility of advanced 65 nm technology CMOSFET transistors fabricated with these oxides were analyzed. It was observed that increasing the nitrogen concentration in the gate oxide results in a negative shift of the threshold voltage for both NMOS and PMOS devices and a degradation of the hole mobility. It was also observed that pchannel transistors are more sensitive to the nitrogen concentration of the gate oxide than n-channel transistors.
Table of Contents and Foreword
Authors: Martino João Antonio , Carro Luigi 
Published: December 2020

This issue of Journal of Integrated Circuits and Systems (JICS) includes 6 papers on design, test and CAD. Some of them have been selected from the presentations given at SBCCI2007 (21st Symposium on Integrated Circuits and Systems Design), which has been held in Rio de Janeiro, Brazil in 2007. Among the contributions presented at SBCCI2007 conference, only a few best rated by the reviewers were selected by the JICS Editorial Board and have been invited to submit an extended version. These papers have been submitted to usual reviewing process with the help of external experts. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection, which guarantees the scientific level of this issue.We sincerely hope that JICS readers will enjoy these contributions, as we have enjoyed listening to them at the SBCCI2007 conference. This year the JICS journal will restart the spontaneous submission of papers additionally to the invitation of best papers of Symposium on Microelectronics Technology and Devices and Symposium on Integrated Circuits and Systems Design. We hope the community will support our decision submitting high quality papers that will contribute to the excellence of JICS Journal.João Antonio Martino Luigi CarroJICS Editor-in-chief JICS Co-Editor
New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAMs
Authors: Dilillo L. , Girard P. , Pravossoudovitch S. , Virazel A. , Borri S. , Bastian M. 
Published: December 2020

This paper presents a complete analysis of the ability of March tests to detect ADOFs (Address Decoder Open Faults) and resistive-ADOFs in address decoders of embedded-SRAMs. Such faults are the primary target of this study because they are notoriously hard-to-detect. With this study, we show that standard March tests without modifications are not able to detect them and we propose to translate the algorithm presented in [1, 2] into March elements. These new March elements involve a particular address sequence and data to be written. For this purpose, we have exploited some Degrees of Freedom of the March tests (DOF I and IV) in order to generate these new March elements for ADOFs detection. Compared to the previous March solutions, these new March elements ensure the fault observation.
Fabrication of Silicon Microtips with Integrated Electrodes
Authors: Mielli Murilo Z. , Barros Alex L. , Lopes Alexandre T. , Carreño Marcelo 
Published: December 2020

This paper describes a simple method to fabricate silicon microtips with integrated self-aligned polarization electrodes for development of MEMS and electron field emission devices. The method is based on the wet bulk micromachining of the silicon substrate in KOH solutions and utilizes low stress PECVD SiOxNy films obtained at low temperatures (320°C) as structural material for both mechanical support and electrical insulation of the electrodes. For the electrodes sputtered Cr films were utilized. The microtip formation process was studied by optical and electronic microscopy to analyze tip geometry and the characteristic etch rate of the different stages during the tips formation. The fabricated devices were matrixes with different numbers of microtips, each with a typical height of 52 μm and with diameter at the apex below 1 μm. In the best case, the distance between the apex of the tips and the metallic electrode was lower than 5 μm. The results also show that the low stress SiOxNy film is essential to attain the necessary flatness required by the process.
A Novel AES Cryptographic Core Highly Resistant to Differential Power Analysis Attacks
Authors: Ghellar Felipe , Lubaszewski Marcelo 
Published: December 2020

In this work, we present a novel core implementation of the Advanced Encryption Standard with an integrated countermeasure against side channel attacks, which can theoretically increase the complexity of a DPA attack by a factor of 240. This countermeasure is based on mathematical properties of the Rijndael algorithm, and retains compatibility with the published Standard. The entire system was designed from the ground up to allow the reutilization of the building blocks in many different combinations, thus providing for design space exploration. Synthesis results show that the protected core can perfectly meet the performance constraints of currently used smart cards.
Flow-injection Analysis Technique Used to Electrochemically Measure Nitrite through a Gold Working Electrode Modified with 1-2 Diaminobenzene (DAB)
Authors: Almeida F. L. , Dos Santos Filho S. G. , Fontes M. B. A. 
Published: December 2020

In this paper, it is presented nitrite analysis, electrochemically measured, using a Flow-injection Analysis (FIA) system. The importance of determining nitrite from water, food and blood is based on its toxicity for human health, even at low concentrations (<4mM). The presented electrochemical planar sensor uses silk-screen technology and has a working electrode covered with 1-2 Diaminobenzene (DAB) that allowed good selectivity, reproductively, stability and sensitivity at 0.75 VAg/AgCl Nafion® 117, 0.5 VAg/AgCl Nafion® 117 and 0.3 VAg/AgCl Nafion® 117. It was noteworthy that nitrite response adds to the response of the studied interfering elements (paracetamol, ascorbic acid and uric acid) and it is predominant for concentrations lower than 175 μmol L-1. Finally, the nitrite sensitivity was 11.2 mA mol-1 L mm-2 using the working electrode recovered with DAB at 0.5 VAg/AgCl Nafion®117.
Framework for Generating Configurable SAT Solvers
Authors: Vieira Bernardo C. , Andrade Fabrício V. , Fernandes Antônio O. 
Published: December 2020

The state-of-the-art SAT solvers usually share the same core techniques, for instance: the watched literals structure, conflict clause recording and non-chronological backtracking. Nevertheless, they might differ in the elimination of learnt clauses, as well as in the decision heuristic. This article presents a framework for generating configurable SAT solvers. The proposed framework is composed of the following components: a Base SAT Solver, a Perl Preprocessor, XML files (Solver Description and Heuristics Description files) to describe each heuristic as well as the set of heuristics that the generated solver uses. This solvers may use several techniques and heuristics such as those implemented in BerkMin, and in Equivalence Checking of Dissimilar Circuits, and also in Minisat. In order to demonstrate the effectiveness of the proposed framework, this article also presents three distinct SAT solver instances generated by the framework to address a complex and challenging industry problem: the Combinational Equivalence Checking problem (CEC).The first instance is a SAT solver that uses BerkMin and Dissimilar Circuits core techniques except the learnt clause elimination heuristic that has been adapted from Minisat; the second is another solver that combines BerkMin and Minisat decision heuristics at run-time; and the third is yet another SAT solver that changes the database reducing heuristic at run-time. The experiments demonstrate that the first SAT solver generated is a faster solver than state-of-the-art SAT solver BerkMin for several instances as well as for Minisat in almost every instance.
Multi-Objective Design of Analog Integrated Circuits Using Simulated Annealing with Crossover Operator and Weight Adjusting
Authors: Weber T. O. , Noije Wilhelmus A. M. V. 
Published: December 2020

This paper approaches the problem of analog circuit synthesis through the use of a Simulated Annealing algorithm with capability of performing crossovers with past anchor solutions (solutions better than all the others in one of the specifications) and modifying the weight of the Aggregate Objective Function specifications in order to escape local minimums. Search for the global optimum is followed by search for the Pareto front, which represents the trade-offs involved in the design and it is performed using the proposed algorithm together with Particle Swarm Optimization. In order to check the performance of the algorithm, the synthesis of a Miller Amplifier was accomplished in two different situations. The first was the comparison of 40 syntheses for Adaptive Simulated Annealing (ASA), Simulate Annealing/Quenching (SA/SQ) and the proposed SA/SQ algorithm with crossovers using a 20-minute bounded optimization with the aim of comparing the solutions of each method. Results were compared using Wilcoxon-Mann-Whitney test with a significance of 0.05 and showed that simulated annealing with crossovers have higher change of returning a good solution than the other algorithms used in this test. The second situation was the synthesis not bounded by time aiming to achieve the best circuit in order to test the use of crossovers in SA/SQ. The final amplifier using the proposed algorithm had 15.6 MHz of UGF, 82.6 dBV, 61º phase margin, 26 MV/s slew rate, area of 980 μm² and current supply of 297 μA in a 0.35 μm technology and was performed in 84 minutes.
Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores
Authors: Livramento Vinícius dos S. , Moraes Bruno G. , Machado Brunno A. , Boabaid Eduardo , Güntzel José Luiz 
Published: December 2020

The development of mobile multimedia devices follows the platform-based design methodology in which IP cores are the building blocks. In the context of mobile devices there is a concern of battery lifetime which leads to the need of energy-efficient IP cores. This paper presents four energy-efficient FDCT/IDCT configurable IP cores. These architectures are based on Massimino’s algorithm, which was chosen due to its high accuracy and parallelism. The four architectures were built by combining fully-combinational or pipelined datapaths, using either a single or two 1-D DCT blocks with a transpose buffer that assures the optimal minimum latency of eight cycles. Synthesis results for 90nm showed that our most efficient architecture, which uses two pipelined 1-D blocks, achieved 250 MHz as maximum frequency at a total power of 14.03 mW. Such frequency was enough to process 16x 1080p@30fps videos in real time (nearly 2 GigaPixels/s). Comparisons with related work, in terms of energy efficiency (μJ/MPixels), revealed that our most energy-efficient architecture is at least 2 times as efficient as other DCT architectures. Moreover, the four designed architectures were also synthesized by using common low-power techniques. These results showed that pipelined versions at high throughput tend to take more benefit from using Low-Vdd and High-Vt combined than the combinational ones, thus becoming the most energy efficient.
Design, Analysis and Measurement Results of a Fully-Integrated Low-power LNA Presenting Faults
Authors: Moreira e Silva Paulo M. , Rangel de Sousa Fernando 
Published: December 2020

We present in this paper the analysis, design and measurement results of a low noise amplifier (LNA) operating in the ISM band at 2.45 GHz. The circuit topology adopted was based on a current reuse technique to minimize the power consumption. A prototype was fabricated in a 0.18-μm standard CMOS technology and the measured power consumption was 1.1 mW. The measured input reflection coefficient was below -10 dB and the reverse isolation was higher than 20 dB. The measured insertion gain and noise figure were 5.6 dB and 4.8 dB respectively, with divergences from the simulated values of 5 dB and 2 dB, respectively. To explain these discrepancies, we devised an analysis on the circuit, including sources of uncertainties. Moreover, we characterized a transistor included in the LNA die, that helped to explain part of the disagreements. After including the uncertainty sources, we wereaable to explain a deviation of 3.9 dB in the insertion gain with respect to the simulated result.
Gray Encoded Harmonics Power Line Interference Cancelling Structure Using LMS and NLMS Adaptive Algorithms
Authors: Costa Eduardo A. , Almeida Sérgio J. , Matzenauer Mônica L. , Fonseca Mateus B. 
Published: December 2020

This paper proposes the implementation of a Gray encoded structure for harmonics power line interference cancelling. The structure uses dedicated hardware architecture for the Least Mean Square (LMS) adaptive filtering algorithm, as well as its normalized version (NLMS). In the used scheme, from a 60Hz reference signal, the algorithms are able to estimate the superior harmonics, using after these results for the cancelling of interferences related to the signal of interest. In this work, the proposed adaptive filtering architectures and the harmonics generator block use a Hybrid encoding in its data buses, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching characteristic of the Gray encoding. For the Hybrid structures, new Hybrid multipliers were proposed, and the results showed that those multipliers are more efficient than the Binary ones, by presenting less power consumption in some cases. The implemented harmonic cancelling structure with the LMS and NLMS adaptive filtering architectures were validated and compared by using both Binary and Hybrid encoding. The efficiency of the implemented Hybrid structure for the cancelling of interferences was proved by reducing more power than the Binary one. By the results, we conclude that it could be practicable to implement a harmonic cancelling structure, based on LMS and NLMS adaptive filtering, operating on Hybrid encoding.
Analysis of Pel Decimation and Technology Choices to Reduce Energy on SAD Calculation
Authors: Seidel Ismael , Bräscher André Beims , De Moraes Bruno George , Monteiro Marcio , Güntzel José Luis 
Published: December 2020

As the number of pixels per frame tends to increase in new high definition video coding standards such as HEVC and VP9, pel decimation appears as a viable means of increasing the energy efficiency of Sum of Absolute Differences (SAD) calculation. First, we analyze the quality costs of pel decimation using a video coding software. Then we present and evaluate two VLSI architectures to compute the SAD of 4x4 pixel blocks: one that can be configured with 1:1, 2:1 or 4:1 sampling ratios and a non-configurable one, to serve as baseline in comparisons. The architectures were synthesized for 90nm, 65nm and 45nm standard cell libraries assuming both nominal and Low-Vdd/High-Vt (LH) cases for maximum and for a given target throughput. The impacts of both subsampling and LH on delay, power and energy efficiency are analyzed. In a total of 24 syntheses, the 45nm/LH configurable SAD architecture synthesis achieved the highest energy efficiency for target throughput when operating in pel decimation 4:1, spending only 2.05pJ for each 4×4 block. This corresponds to about 13.65 times less energy than the 90nm/nominal configurable architecture operating in full sampling mode and maximum throughput and about 14.77 times less than the 90nm/nominal non-configurable synthesis for target throughput. Aside the improvements achieved by using LH, pel decimation solely was responsible for energy reductions of 40% and 60% when choosing 2:1 and 4:1 subsampling ratios, respectively, in the configurable architecture. Finally, it is shown that the configurable architecture is more energy-efficient than the non-configurable one.
Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results
Authors: Nissimoff Albert , Sasaki Katia R. A. , Aoulaiche Marc , Martino João Antonio , Simoen Eddy , Claeys Cor 
Published: December 2020

This paper presents the concept and implementation of a complete 1T-DRAM memory characterization setup and analyzes the read windows of decananometer UTBOX SOI 1T-DRAM memory devices focusing on the mechanisms involved as a function of the applied gate voltage during the read operation. It will be demonstrated both experimentally and by simulation that a novel two-sided read window is possible where the two main effects present, GIDL and parasitic BJT, can be effectively accounted for in two different zones.