bluuebunny/crossref_metadata_2025_split huggingface dataset:
Morphology of Oxygen Precipitates in RTA Pre-Treated Czochralski Silicon Wafers Investigated by FTIR Spectroscopy and STEM
Authors: Kot Dawid , Kissinger Gudrun , Schubert Markus Andreas , Sattler Andreas 
Published: February 2020

Rapid thermal annealing (RTA) is a commonly used technique to control precipitation of oxygen in Czochralski silicon wafers (1,2). RTA pre-treatment leads to the formation of intrinsic point defects, mainly vacancies, which are responsible for the enhanced precipitation of oxygen. Oxygen precipitates are widely known as getter sites for metal impurities in the silicon microelectronic technology (3). The getter efficiency of oxygen precipitates depends on their density and morphology (4,5). The density of the precipitates can be controlled by the temperature of RTA and it can be easily determined by preferential etching. The morphology of oxygen precipitates depends on the type and the concentration of dopants, the thermal history, and the annealing temperature and time (6-8). Recently, it was shown that the supersaturation of vacancies impacts the morphology of oxygen precipitates (9). Since RTA pre-treatments introduce vacancy supersaturation in silicon wafers its usage before nucleation annealing could modify the morphology of precipitates compared to wafers without RTA. The morphology of oxygen precipitates can be determined by transmission electron microscopy, however the preparation of samples is demanding. An alternative is the Fourier transform infrared (FTIR) spectroscopy at liquid helium temperature, which also allows distinguishing different types of oxygen precipitates. The oxygen precipitates give rise to absorption bands in the range between 1000 and 1300 cm-1. There are two characteristic broad bands at 1095 cm-1 and at 1225 cm-1 which belong to spherical and plate-like precipitates, respectively (10-12). The sharp bands (1136 cm-1 and satellites and 1205 cm-1) are attributed to interstitial oxygen.
In this work, we investigate the morphology of oxygen precipitates by FTIR spectroscopy at liquid helium temperature and by scanning transmission electron microscopy (STEM) in silicon samples pre-treated by RTA at 1250°C for 30s in O2 containing Ar atmosphere subsequently annealed in the temperature range between 800°C and 1000°C in N2. The results show that the morphology of the oxygen precipitates in RTA pre-treated samples depends on the nucleation temperature. Fig. 1 presents absorption spectra of silicon samples pre-treated by RTA at 1250°C and annealed at 800°C (a), 900°C (b) and 1000°C (c) for 64h. As can be seen from the deconvolution of the spectra, the number and position of the bands is different for each annealing temperature. Based on the effective medium theory (EMT) (13) and STEM investigations the absorption bands can be matched to relevant morphologies.
Plasma Etch in the Era of Atomic Scale Fidelity
Authors: Lill Thorsten , Singh Harmeet , Kamarthy Gowri , Kanarik Keren J. , Cohen Andy , Eppler Aaron , Holland John , Fischer Andreas , Shen Meihua , Marks Jeff , Gottscho Richard A. , Vahedi Vahid 
Published: February 2020

In IC manufacturing, the ultimate goal is to produce the structures that are conceived and modeled by design engineers in the real world with high fidelity. The term “fidelity”is chosen deliberately to express that what is needed in the end is the highest possible degree to which a material structure matches the design intent. It includes but is not limited to statistical criteria such as accuracy and precision.
Plasma etch plays a key role in obtaining structural fidelityin all three dimensions. Accuracy is obtained by control of proximity and 3D effects such as critical dimension (CD) loading, profile loading, aspect ratio dependent etching (ARDE), and selectivity. Precision, on the other hand, is obtained by means of wafer-to-wafer, chamber-to-chamber, and tool-to-tool matching.
Atomic scale fidelity is required as we approach devices with a half pitch of 10 nm and below because the device dimensions and their allowed tolerances are of the same order of magnitude as the inter-atomic distances in the crystal lattice. This type of performance can be obtained when the material is removed layer by layer. Each step in the etch process uses the simplest possible chemistry to surgically target specific reactions at the wafer surface such as activation, removal, and passivation. We call this layer-by-layer etch with atomic fidelity atomic layer etch /1/.
We will introduce the framework of high productivity, production-worthy atomic layer etch and discuss the implications for hardware and process development.
References:
Kanarik, et al., Solid State Technology, 56 (2013) 14-17.
Etch Challenges for 3D NAND Flash Technology
Authors: Khan Anisul Haque , Srinivasan Sunil , Choi Jinhan , Athayde Amulya , Achutharaman Raman 
Published: February 2020

Current 2D NAND scaling is approaching technology limitation in both lithography and device performance arena. To address the lithography challenges at the 1x nodes and the well-known scaling issues associated with planar NAND, 3D flash technology is being developed and is expected to greatly reduce the lithography burden albeit shifting it to deposition and etch. The emerging 3D flash architecture requires depositing alternating layer stacks and then etching those stacked layers with extreme precision. Staircase etch for contact landing, hard mask etch, gate trench etch, channel hole etch and staircase contact etch are the main critical etches required to manufacture 3D flash device (Figure 1).
Plasma etching processes involved in the fabrication of 3D flash devices are becoming increasingly challenging. The staircase etch, which requires lateral resist mask etch followed by vertical stacked layer etch, repeated in multiple the lateral/vertical etch cycles, to form staircase shaped contact landing pads, offers unique challenges in lateral to vertical etch rate control of resist mask, resist mask shape control, selectivity control of the stacked layer etch, staircase step width control and step width uniformity control. Hardmask open, gate trench etch, channel hole etch, and staircase contact etch create significant challenges for etching, especially of high aspect ratio (HAR) features ranging in aspect ratio from 30:1 to >80:1. Furthermore, etching through the HAR alternating layer stacks intensifies the demands on the etch process, which must be capable of etching distortion free, vertical profiles free of bending, faceting and feature clogging. Additionally, smooth sidewall transitions in the alternating stack, and very high selectivity to the tiny pad are required, especially for the staircase contact etch application, which combines extreme simultaneous multi-level etch at aspect ratios ranging from 30:1 to >80:1 along with extremely high selectivity for negligible loss of the underlying contacted material.
In this paper we will present etch hardware and process development solutions provided to overcome these difficult etch challenges for staircase etch, hard mask open, gate trench etch, channel hole etch, and staircase contact etch applications to enable 3D NAND flash technology.
SiC Power Devices in a Soft Switching Converter, Including Aspects on Packaging
Authors: Ranstad Per , Bakowski Mietek , Tolstoy Georg , Lim Jang-Kwon , Giezendanner Florian , Ranstad Anton 
Published: February 2020

In many applications of power electronic converters efficiency and size are important figures of merit. Low losses in the power semiconductors and high frequency operation are important factors. The converters considered in this paper are off-line powered and in the power range of 50 – 150 kW with a high-voltage dc-output. The switching frequency is 20-40 kHz. With modern IGBTs an efficient operation (n> 95%) can be obtained when using soft-switching topologies. Fig 1(a) shows the schematic diagram of an SLR, series loaded resonant converter [1]. In Fig 1(b) typical waveforms of transformer current and voltage are depicted.
In a recent paper, [2], frequency dependent IGBT losses are evaluated. Fig 2 shows the on-state voltage of an IGBT when conducting a sinusoidal current at different frequencies. At the higher frequency (30 kHz, Tr4) the increase of conduction losses is evident.
Power switches made from SIC show excellent properties enabling; low conduction losses, high frequency operation and an ability to operate at high die temperatures [3]. Fig 3 (a) shows the on-state voltage of an unipolar SIC switch while Fig 3(b) shows the on-state voltage of a bipolar switch. Measurements have been performed up to 200 kHz without showing any high-frequency effects.
High voltage SiC PiN diodes can replace several series connected Si diodes due to the higher critical field strength in SiC. This enables substantially reduced conduction losses in the output rectifier. In Fig 4 on-state voltages of 10 kV SiC and Si-diodes are shown, indicating a 50% reduction of losses.
References
[1] V. Vlatkovic, M. J. Schutten, and R. L. Steigerwald, “Auxiliary Series Resonant Converter: a New Converter for High-Voltage, High-Power Applications,” in Proc. of PESC -96, 1996.
[2] P. Ranstad, and H-P. Nee, “On dynamic effects influencing IGBT losses in soft switching converters,” IEEE Transactions on Power Electronics, vol. 26, No. 6, December 2010.
[3] P. Ranstad, H-P. Nee, J. Linner, and D. Peftitsis “An experimental evaluation of SiC switches in soft-switching converter,” IEEE Transactions on Power Electronics, 2014
Reliability of Commercially Available SiC Power Mosfets
Authors: Lelis Aivars , Green Ron , El Mooro , Habersat Dan 
Published: February 2020

With the introduction of SiC power MOSFETs into the commercial market place, it is critically important to determine the reliability of these devices. A number of potential issues need to be addressed, including the stability of the device threshold voltage, and the reliability of both the body diode and the gate oxide.
An ideal switch has minimal leakage current in the OFF state and very low resistance in the ON state. But an excess negative shift of the threshold voltage under high-temperature reverse-bias (HTRB) conditions can lead to a critical increase in OFF-state leakage current and potential device failure [1]. In a similar fashion, a large positive shift of the threshold voltage may occur under high-temperature gate-bias (HTGB) conditions, wherein a positive bias-temperature stress is applied. This can lead to a significant increase in the ON-state resistance.
This work focuses on the stability of the device threshold voltage when subject to bias-temperature stressing, although the reliability of the body diode will also be discussed in the full paper. The primary defects that contribute to shifts in the threshold voltage are near-interfacial oxide traps [2, 3]. A certain number of defect states become activated during device processing. This can vary depending on the details of the processing steps, or may be a function of device design. Typical instabilities of the threshold voltage at room temperature are about 0.25 V. Much larger threshold-voltage instabilities are observed following bias-temperature gate-bias stressing. This is very likely due to the activation of additional oxide traps, which can then participate in the oxide-trap charging process [3]. Since this activation is a function of time at temperature (and bias), more stressful processing conditions can quicken the onset of significant shifts in the threshold voltage during bias-temperature stressing. (Similarly, stressing at higher temperatures also leads to an earlier onset of significant increases in threshold-voltage instability.)
As a result, we have observed a marked difference in the onset of significant increases in threshold-voltage instability between different commercial vendors. This difference in bias-temperature stress time can vary in some cases by two orders of magnitude. Detailed results will be provided in the full paper.

References

1. Lelis, et al., Mater. Sci. Forum, vols. 679-680, p. 599 (2011).
2. Lelis, et al., IEEE Trans. Elec. Dev., 55:8, 1835 (2008).
3. Lelis, et al., ECS Transactions, Vols. 41(8), p. 203 (2011).
Towards Highly Transparent and Flexible Field Emission Displays Based on Low-Dimensional Nanocarbon
Authors: Tanemura Masaki 
Published: February 2020

Transparency and flexibility are key words required for the devices of next generation. This is also the case for displays, for example, highly intelligent information displays for the upcoming ubiquitous world. To realize the transparent and flexible devices, nanocarbon, such as carbon nanotubes (CNTs), carbon nanofibers (CNFs) and graphene, are promising. In the present talk, nanocarbon-based highly transparent and flexible displays will be dealt with.
Field emission displays (FEDs) offer promising advantages such as high brightness, low power consumption, wider viewing angle, etc. Recently some groups have demonstrated the fabrication of nanocarbon based flexible (opaque) FEDs [1, 2]. The next step is the realization of transparency. To achieve this, we are tackling several approaches based on single-walled CNTs, ion-induced conical nanocarbons and their hybrid structures formed on transparent and flexible polymer substrates [3-8]. In addition, in situ transmission electron microscope (TEM) observation of graphene and CNT formation from amorphous carbon-based nanofibers by solid phase reaction during field emission process will be demonstrated [9].
1. H. S. Sim, et al., Appl. Phys. Lett., 90 (2007) 143103-143105.
2. B-J. Yoon, et al., J. Am. Chem. Soc., 127 (2005) 8234-8235.
3. P. Ghosh, et al., J. Am. Chem. Soc., 132 (2010) 4034-4035.
4. D. Ghosh, et al., Chem. Commun., 47 (2011) 4980-4982.
5. M. Tanemura and S. P. Lau: "Flexible Field Emitters: Carbon Nanofibers" in "Carbon Nanotube and Related Field Emitters: Fundamentals and Applications" Edited by Y. Saitoh, Wiley-VCH (Weinheim) (2010), Chapt. 15.
6. D. Ghosh, et al., Phys. Status Solidi RRL 6 (2012) 303–305.
7. D. Ghosh, et al., Phys. Status Solidi RRL 7 (2013) 1080–1083.
8. P. Ghosh, et al., J. Nanoscience and Nanotechnology, 13 (2013) 5767-5772.
9. M. Zamri, M. Tanemura, et al., ASC Nano, 6 (2012) 9567-9573.
Study on Oxide Thickness Dependence of Current-Voltage Characteristics for HfOx Based ReRAM Device
Authors: Hamada Yoshifumi , Otsuka Shintaro , Shimizu Tomohiro , Shingubara Shoso 
Published: February 2020

A resistance random access memory (ReRAM) is expected to be a next-generation nonvolatile memory because of its fast switching speed, and low power consumption. The device structure is composed of an oxide layer sandwiched with two metal electrodes. ReRAM exhibits repetitive transition between high resistance state (HRS) and low resistance state (LRS). It is considered that resistive switching phenomenon is caused by the formation and rupture of the conductive filament formed in the oxide layer. In this study, we investigated HfOx thickness dependence of current-voltage characteristics for Ni/HfOx/Pt ReRAM device. We fabricated Ni/HfOx/Pt devices with a simple crossbar structure. HfOx layer was deposited on the Pt bottom electrode by DC reactive sputtering. The I-Vcharacteristics were measured by two-probe method at room temperature.
Red line in Figure 1 shows I-V characteristics of the Ni/ HfOx/Pt device with oxide thickness of 5.6 nm. Initial state of resistance is HRS. SET process (from HRS to LRS) took place at 2.4 V with a current compliance of 0.1 mA. RESET process (from LRS to HRS) occurred at -1.6 V. The resistance ratio of HRS to LRS is about 107 with 0.1 V readout bias. On the other hand, blue line shows the I-V characteristics of the Ni/ HfO2/Pt device with oxide thickness of 4.0 nm. Initial state of resistance is LRS. Forming process was not observed in this device. SET process took place at 1.0 V. RESET process was observed at -0.6 V. Switching voltage of this device is smaller than the former device with the thicker oxide layer. The resistance ratio of HRS/LRS is about 101 with 0.1 V readout bias. There was a significant difference in switching properties between these devices whose oxide thicknesses differ only 1.6 nm.
It is suggested that leakage current increases when the oxide thickness decreases, thereby the on-state occurred initially for the device with 4.0 nm oxide. It should be noted that I-V characteristic is symmetrical for the device with 4.0 nm oxide, while it is asymmetrical for the device with 5.6 nm oxide. This suggests the mechanism of conductive filament formation and rupture is completely different between these devices. Further discussions and analysis will be presented in the symposium.
Single-Grain Si Tfts Fabricated on a Precursor from Doctor-Blade Coated Liquid-Si
Authors: Zhang Jin , Trifunovic Miki , van der Zwan Michiel , Takagishi Hideyuki , Shimoda Tatsuya , Ishihara Ryoichi 
Published: February 2020

In the application of display, Si TFTs is superior than organic TFTs and metal oxide TFTs in the sense of carrier mobility, reliability and traditional IC process compatibility. However, the difficulty of achieving single crystalline Si limits the application of Si TFTs. In this paper, we would like to present a low-temperature approach for manufacturing single-grain Si TFTs on a precursor from doctor-blade coated liquid-Si on flexible polyimide substrate, with the carrier mobility of 460 cm2/Vs and 121 cm2/Vs, for electrons and holes respectively.
Pure cyclopentasilane is used as liquid-Si, and it was coated using doctor-blade method, and polymerized under the UV lamp. According to [1], polysilane was formed after polymerizing the solution of cyclopentasilane and toluene. After an annealing process at 350 °C, an a-Si precursor was formed (see Fig. 1). A XeCl laser with the wavelength of 308 nm was used for the crystallization of the a-Si precursor, and thanks to the special cavity structures called the grain-filters, which are 110 nm width by 700 nm depth, underneath the a-Si layer, Si single grains were formed[2] (see Fig.2). A top-gated transistor was fabricated using the IC-compatible process of ICP gate oxide growth (250 °C), PECVD TEOS oxide (350 °C), Al gate and contact pads formation, self-aligned source-drain dopant ion-implantation and laser activation of the dopants (room temperature). The process temperature was so low that the devices were fabricated on top of flexible polyimide substrate. At the end of the process, all the devices were peeled off from the supporting Si wafer to a PEN foil and become flexible (Fig. 5).
The devices show transfer characteristics with high on-off ratio and high carrier mobility, 420 cm2/Vs for electrons and 121 cm2/Vs for the holes (Fig. 3). After peeling off from the Si wafer, the devices could function until a bending diameter of 6 mm (Fig.4). To restrain the mobility degradation during the bending, a double-sided polyimide structure was investigated.
[1] T. Shimoda, Y. Matsuki, M. Furusawa, T. Aoki, I, Yudasaka, H. Tanaka, H. Iwasawa, D. Wang, M. Miyasaka and Y. Takeuchi, Nature 440, 6, 2006, 783-786
[2] R. Ishihara, P.C. van der Wilt , B.D. van Dijk , A. Burtsev , J.W. Metselaar and C.I.M. Beenakker, Thin Solid Film 427, 2003, 77-85
Interpretation of Defect States in Sputtered IGZO Devices Using I-V and C-V Analysis
Authors: Mudgal Tarun , Walsh Nathaniel , Edwards Nicholas , Manley Robert G. , Hirschman Karl D 
Published: February 2020

There has been significant progress in advancing the performance of IGZO TFTs; however device stability still remains a challenge. While traditional materials and techniques used for silicon-based TFTs may not be applicable, the influence of defect states can be reduced by annealing. The interpretation of non-ideal current-voltage (I-V) characteristics is not always unambiguous due to issues that may be related to carrier injection. Capacitance-voltage (C-V) analysis provides complementary information that is valuable in separating the influence of material and interface defects from other factors that influence transistor operation.
In this work, bottom-gate, top-contact TFT structures and interdigitated capacitors fabricated using sputtered IGZO have been investigated. Interdigitated capacitors, unlike one-dimensional capacitors, are much more representative of the actual TFT structure; specifically the channel region. Annealing was performed at 300 - 400 °C in O2, N2and air ambient conditions. Silicon dioxide, aluminum oxide, and B-staged bisbenzocyclobutene-based (BCB) resins were applied as materials for back-channel passivation. Analytical measurements and both I-V and C-V results were used to refine a material model developed for TCAD device simulation [1]. The correlation between I-V and C-V characteristics will be presented.
[1] T. C. Fung, C. S. Chuang, C. Chen, K. Abe, R. Cottle, M. Townsend, et al., "Two-dimensional numerical simulation of radio frequency sputter amorphous In-Ga-Zn-O thin-film transistors," Journal of Applied Physics, vol. 106, p. 084511, 2009.
Improvement of Electrical Properties and Bias Stability of InGaZnO Thin-Film Transistors by Fluorinated Silicon Nitride Passivation
Authors: Jiang Jingxin , Tatsuya Toda , Tatsuoka Gengo , Wang Dapeng , Furuta Mamoru 
Published: February 2020

Recently, oxide-based thin-film transistors (TFTs) have attracted considerable attention for applications such as active-matrix flat panel displays. Among oxide semiconductors, amorphous InGaZnO (a-IGZO) is widely accepted as a promising channel material for TFT application [1]. However, the bias induced instability is a remained issue to be solved. Ambient atmosphere includes oxygen and water, which easily absorb on the exposed a-IGZO surface and influence TFT properties; therefore, a suitable passivation layer is an essential to improve the reliability of the oxide TFTs. In this study, electrical properties of the IGZO TFTs with SiOx, fluorinated SiNx (SiNX:F) passivation were investigated.
Bottom-gate IGZO TFT with SiOX etch-stopper was used for this experiment, and a SiOX or SiNX:F was deposited on the TFT as a passivation [2]. The experimental transfer characteristics (IDS-VGS) of the IGZO TFTs with SiOX and SiNX:F passivation are shown in Fig. 1(a) and 1(b), respectively. The IGZO TFT with SiNX:F passivation showed steep subthrehold swing, low threshold voltage (Vth), and small hysteresis as compared with the SiOX passivation. Fig. 2 shows the comparison of positive bias temperature stress (PBTS) reliability of the IGZO TFTs with SiOX and SiNX:F passivation. It was found that positive threshold voltage shift is significantly suppressed by SiNX:F passivation. Influence of SiNX:F passivation on reliability of the IGZO TFT will be presented at the conference.
Authors would like to thank Tokyo Electron Co., Ltd. for their experimental supports on SiNx:F film.
[1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, Nature. 432, 488 (2004).
[2] M. Furuta, M. P. Hung, and J. Jiang, D. Wang, S. Tomai, H. Hayasaka, and K. Yano, ECS Trans., 54 (2013).