(Invited) 3D Monolithic Integration
Authors: Brunet Laurent , Batude Perrine , Fenouillet-Beranger Claire , Andrieu François , Vinet Maud 
Published: February 2020

3D monolithic integration, also named 3D sequential integration, consists in stacking active device layers on top of each other in a sequential manner. It differs from 3D Packaging where the tiers are fabricated in parallel and then stacked together using a bonding step bonding step (copper to copper or hybrid bonding for example). The monolithic flow offers unique 3D connectivity opportunities: indeed, as the top active patterning is defined by lithography and can be aligned with respect to bottom tiers (alignment marks being seen by transparency), the alignment accuracy and feature size of stacked tiers and inter-tier interconnections are only limited by stepper resolution and not by bonding alignment accuracy like 3D packaging. This allows ultra-high density of 3D vias: state-of-the-art 3D packaging achieves a maximum density of 105 vias/mm2 while 3DSI demonstration using conservative 65nm design rules already achieves a maximum density of 2.107 via/mm2 [1]. However it comes at the cost of thermal budget constraints for top layer processing, as it will be necessary to realize the top tiers without degrading electrical and morphological performances of bottom tiers. In this paper we will review the different fields of application of 3D monolithic integration and describe the related processing options.
Furthering Moore’s law for high-performance applications was the original driver for 3D sequential integration. It can be seen at the gate granularity scale, meaning optimizing NMOSfets and PMOSfets independently in two separate layers. This case would offer very fine tuning options on each level (e.g: channel material, strain boosters, substrate orientation, etc.) and avoid costly and complex co-integration steps [2,3]. It can also be seen at the circuit granularity scale by stacking CMOS over CMOS to boost IC speed performance. It can be obtained by reducing the wire length and then the interconnection delay. Performance Power Area (PPA) evaluations have been carried out with various outcomes depending on the application case study, technology node and place and route methodologies [4]. For FPGA (field programmable gate arrays) applications for example, it has been evidenced that 3D sequential integration enables one to reach the PPA of nodes n+1 by stacking 2 n tiers, enabling one to keep following Moore’s law without resorting to straight device scaling [5-7]. Is also important to note that new approaches for “big data” processing such as in-memory and neuromorphic computing require large amounts of on-chip memory with a high density of interconnects between core and memory and 3D Monolithic appears to be an adequate candidate [8]. Maximum thermal budget and technology solutions to realize such integration will be presented.
3D Monolithic can also be very interesting in a Moore than Moore scheme like 3D smart sensors. Lower parasitic capacitance in 3D vias obtained with a monolithic configuration compared to 3D packaging with TSVs could increase data transfer bandwidth. For these sensing applications, analog devices will be needed and depending on their positioning in the 3D stack, may have to be realized with a limited thermal budget. If another tier is realized above they will also need to be resistant to additional thermal budgets. This stability as well as their feasibility with a limited thermal budget must be evaluated. For this latter, technological knowledge on silicides which is usually the first limiting element in thermal budget stability will be presented [9,10].
References : [1] L. Brunet et al., VLSI 2016, [2] P. Batude et al., IEDM 09, [3] P. Batude et al, VLSI 09, [4] M. Jung et al., TCPMT 2015, S. Panth et al., Journal of Information and Communication Convergence Engineering 2014, , [5] O. Turkyilmaz et al., DATE 2014, [6] ITRS 2013, “System driver summary”. http://public.itrs.net, [7] ITRS 2013, “ORTC”. http://public.itrs.net, [8] M. M. Sabry Aly et al., Computer, vol. 48, no. 12 2015, [9] C. Fenouillet-Beranger et al., ESSDERC 2014, [10] C. Fenouillet-Beranger et al., IEDM 2014