Ultra-Thin, High Quality HfO2 on Strained-Ge MOS Capacitors with Low Leakage Current
Authors: Teherani James T. , Chern Winston , Antoniadis Dimitri A. , Hoyt Judy L. 
Published: February 2020

Strained-Ge is a promising channel material for future CMOS nodes due to its very high hole mobility [1] and compatibility with existing processes. In comparison to Si, high quality dielectric interfaces for Ge are challenging due to the lack of an ideal native oxide. In this work, for the first time, we show an extremely-scaled (EOT < 5 Å), high quality dielectric on s-Ge. CV measurements of a MOS capacitor structure show areal capacitance scaling, little hysteresis, and low gate leakage current (< 0.2 A/cm2).
The epitaxial structure (shown in Fig. 1(a)) was grown by low-pressure CVD, and the s-Ge layer is compressively strained (2.3% biaxial) due to the lattice mismatch with the relaxed Si0.55Ge0.45 virtual substrate. The epitaxial wafer was cleaved into pieces, and a 5-minute 1:10 (HCl:H2O) clean was performed prior to atomic layer deposition (ALD) of 1 minute O3/~3 nm HfO2 (both at 250 °C), followed by ~10 nm of TiN at 300 °C. After ALD, Al contacts were sputtered and patterned followed by a 30-minute forming gas anneal at 450 °C. The final MOS capacitor structure (Fig. 1(a)) reflects the loss in the s-Ge due to the HCl clean and O3 oxidation.
CV measurements of a 100×100 µm MOS capacitor show a CET of 8.6 Å (Fig. 2). Large frequency dispersion exists for frequencies > 50 kHz due to large series resistance likely caused by a 500 meV valence band offset [2] between s-Ge and Si0.55Ge0.45 (Fig. 1(b)). The IV measurements (Fig. 3) show small gate leakage current (< 0.2 A/cm2), which translates to IG
< 20 pA/µm for LG
= 10 nm, well below ITRS requirements [3].
Quasistatic one-dimensional self-consistent coupled Poisson-Schrödinger electrostatic simulations were performed in order to extract EOT. A strain-dependent 6×6 k∙p Hamiltonian (with deformation potentials from [2]) was used to calculate hole quantization in the s-Ge layer. In accordance with [4], a 2.1 eV valence band offset between Ge and GeOx was used in the simulations (Fig. 1(b)). The 500 meV valence band offset between between s-Ge and Si0.55Ge0.45creates a deep quantum well confining most of the holes in the s-Ge layer.
Fig. 5 shows the 10 kHz experimental CV in addition to simulated quasistatic CV curves for structures with varying EOT. The mismatch of the simulated and experimental curves in strong hole accumulation is due to both a large series resistance (Rs
~ 0.1 Ω∙cm2) and gate leakage, which causes a sizable error when transforming the measured impedance to a two-element parallel capacitance CP
, parallel conductance GP
circuit model [5]. A circuit model (inset Fig. 6) incorporating parasitic gate tunneling conductance Gt
and series resistance Rs
is applied to an ideal simulated CV in order to recover the measured CV result, yielding an extracted EOT of 4.9 Å (Fig. 6). This is the smallest known EOT for a high quality dielectric on s-Ge published to date. Other recent results include a 7-Å EOT on s-Ge [6], and an 8-Å CET on unstrained Ge [7].

References

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[3] ITRS Front End Processes, 2012 update.
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[6] R. Zhang et al., IEEE IEDM, p. 26.1.1, 2013.
[7] B. Duriez et al., IEEE IEDM, p. 20.1.1, 2013.