bluuebunny/crossref_metadata_2025_split huggingface dataset:
New Method for Decapsulation of Copper Wire Devices Using LASER and Subambient Temperature Chemical Etch
Authors: Lefevre Matthew J. , Beauquis Frédéric , Obein Michael , Gounet Pascal , Barberan Sandrine 
Published: December 2020

Abstract
IC packages have been greatly improved over the past several years. With the adoption of Cu wires and new green EMC (Epoxy Molding Compound), the suppression of lead, the use of Cu pillars and the increased number of dies, the verification of the quality of the assembly and failure analysis becomes critical. Starting twelve years ago, LASER ablation was introduced as a means to facilitate the pre-decapsulation of packages aiming at a completion by wet chemistry (acids) or dry chemistry (plasma). The decapsulation process with acid at medium temperature (75°C) does not permit to keep the Cu wires intact. Our studies and work in the past several years has consisted in lowering the temperature of acid use in order to minimize the effect of acid attack on the Al pads and Cu wires. Currently the thinnest wires used are 0.6 mil in diameter (approximately 15 μm). In this article we will demonstrate that decapsulations at sub-ambient temperatures are now possible and give expected results. Moreover, openings at near ambient temperature reduce the component deformation and also the deformation of its constituents compared to decapsulations at medium or high temperature.
A Novel Low Cost Technique to Perform Concurrent Topside and Backside Analysis of a Bare Die
Authors: Kabadi Raj , Swe Win Thandar 
Published: December 2020

Abstract
A novel low cost technique to facilitate concurrent topside and backside imaging of a bare die for optical fault localization purposes is presented. The technique overcomes the restrictions posed by unavailability of a suitable package or limited choices that may be present at a small scale packaging lab. The difficulties imposed on backside preparation of commonly used ceramic packages are overcome by providing an alternative that is relatively less expensive and easier to implement. This is accomplished by mounting the bare die on a glass cover slip using a suitable adhesive and wire bonding the bond pads to a specially designed printed circuit board. This method is being successfully utilized on multiple failure analysis requests received in our lab.
Systematic EFA Approach in Locating Floating Nodes in Analog Mixed Signal Devices
Authors: Karki Sagar 
Published: December 2020

Abstract
With advancements in technology, it is nearly impossible to find the defects in integrated circuits without applying appropriate failure isolation techniques. Failure isolation is a critical step in identifying the physical defect on integrated circuits. This paper addresses the challenges imposed by floating node conditions on both analog and digital circuitry, and a case study for each circuit type is presented. Different approaches along with the challenges involved in isolating each case in a very timely manner are addressed. Finally, the usefulness of global isolation tools, such as PEM (Photon Emission Microscopy), FIB (Focused Ion Beam), and micro-probing, is also discussed.
Activity Analysis at Low Power Supply on 45nm Technology
Authors: Bascoul Guillaume , Perdu Philippe , Sanchez Kevin , Lewis Dean , Dudit Sylvain , Celi Guillaume 
Published: December 2020

Abstract
VLSI internal testing through silicon substrate has been widely studied and techniques like Time Resolved Emission has given impressive results. Nevertheless, Integrated Circuits (IC) are still evolving with more and more complex functions and various kinds of signals that could be split into two main categories: data and control. Controls activate specific block and according to the wide range of different blocks and device complexity, the first analysis task is to check block activity related to control line status. In this paper, we show how Time Resolved Imaging can precisely answer this challenge even in up-to-date technologies at low power supply.
Enhanced Comparison of Lock-In Thermography and Magnetic Microscopy for 3D Defect Localization of System in Packages
Authors: Schmidt Christian , Altmann Frank , Vallett David P. 
Published: December 2020

Abstract
Lock-in thermography and magnetic current imaging are emerging as the two image-based fault isolation methods most capable of meeting the challenges of short and open defect localization in thick, opaque assemblies. Such devices are rapidly becoming prevalent as 3D integration begins to ramp up production. This paper expands on previously published work with a qualitative comparison of the techniques on single chip and stacked die packages with known designed-in or FIB created defects.
DRAM Cell Fault Localization Using Passive Voltage Contrast
Authors: Liew San Lin , Wei Yu Pei , Chen Bi Jen , Chen Hua Sheng , Luo Jian Shing 
Published: December 2020

Abstract
This paper presents the memory cell level passive voltage contrast (PVC) involving diode, capacitor and transistor devices in a (dynamic random access) DRAM chip. More particularly, we show that the voltage contrast sensitivity can be improved significantly by the adjustment of scan location and scan location sequence. Both leaky and resistive fault localizations by PVC imaging are presented to illustrate our point.
Lock-in Phase Mapping of Modulated Reflectance in Dynamically Operating Mixed-Signal IC Devices
Authors: Qian Zhongling , Brillert Christof , Burmer Christian 
Published: December 2020

Abstract
The lock-in phase mapping technique with modulated reflectance is introduced for the first time. With its help, the modulated reflectance mechanisms using thermal laser in operating FETs, particularly in the pinch off region, are clarified. The free carrier absorption mechanism dominates at a high modulation frequency, while thermo-reflectance mechanisms at a low modulation frequency. In the pinch-off region, thermo-reflectance mechanism cannot be neglected due to extremely low free carrier concentration. The modulated reflectance signal was unexpectedly observed at passive poly/oxide/poly capacitance. The advantages of lockin phase mapping in dynamically operating mixed-signal IC devices are shown in several case studies.
From EBT to LVP, from 130nm to 28nm Node, Internal Timing Characterization Evolution
Authors: Parrassin Thierry , Larre Philippe , Dudit Sylvain , Vallet Michel , Reverdy Antoine 
Published: December 2020

Abstract
In semiconductor industries, development of new technologies and new products generally follows a phase of yield improvement where Failure Analysis expertise is used to locate and fix killer defects and for design debug. When process and design reach a certain level of maturity, a second phase of optimization, qualification and reliability is executed in which Failure Analysis expertise is used for internal timing characterization of integrated circuit and results are compared with design/process simulations. In order to reduce the cost of testing during manufacturing, circuits embed Built in Self Timing Characterizer (BISC) for timing measurements inside critical functional blocks. Thanks to advanced integration, the last CMOS technologies allow high performance in terms of speed. Arithmetic and Logical Units (ALU) are able to work at frequencies greater than few GHz and some memories’ access time is lower than hundreds picoseconds. In the CMOS 40nm analysis case study presented in this paper, a BISC measurement of memories’ access times gives different results than what was expected from simulation. Internal probing becomes mandatory to understand this critical timing issue. A complete comparison is done between the 3 contactless probing techniques available in our laboratory which are the E-Beam Testing (EBT), Time Resolved Emission (TRE) and the recent Laser Voltage Probing (LVP) to highlight strength and weakness of each probing techniques in front of this timing related defect. We demonstrate that the LVP is an inevitable technique to address the nanometer-scale technologies in terms of spatial resolution, low voltage measurements and timing performance.
Improved Parasitic Fault Modeling for Automatic Analog Fault Simulation
Authors: Borgmann Gerhard , Burmer Christian , Mézière Sébastien 
Published: December 2020

Abstract
Analog simulation combined with Time Resolved Light Emission (TRE) can be used to evaluate different fault possibilities and to isolate the most likely fault candidate. In this paper we will describe an improved fault model derived from parasitic layout extraction.
Focused Ion Beam Circuit Edit on Copper Redistribution Layer
Authors: Motta Lorenzo , Veneto Paolo , Antolik Mark , Di Donato Donato 
Published: December 2020

Abstract
Focused ion beam (FIB) circuit edit (CE) is an integral part of IC debug, fault-isolation, and low yield analysis. Regarding FIB microsurgery, complexity is growing with the shrinking of dimensions of lower level metallization while the redistribution layer (RDL) structures can increase in all three dimensions. This requires continuous development of CE processes to address these opposite dimension trends and material variations. There are two venues to address CE, accessing from the front side (FS) or from the back side (BS) of an IC. This paper describes the FS techniques and methodologies developed to edit the RDL technology. The goal of this work is to demonstrate on a Cu GND/power plane the performance of the halogen-based contamination process. Results shows that the benefit of reduced time to remove thick Cu metallization is surely advantageous for CE throughput as well as for improving edit success rates.
Multi-Site Full Thickness Backside Focused Ion Beam (FIB) Editing for eDRAM Array Address Descramble Verification
Authors: Herschbein Steven B. , Scrudato Carmelo F. , Worth George K. , Hermann Edward S. 
Published: December 2020

Abstract
Focused Ion Beam (FIB) modification for chip repair, layout verification, and internal signal probing has become an integral part of the process for bringing advanced products to market. As devices become more complex, with more levels of dense, thick upper power planes and tighter lower point-to-point wiring and device geometries, primary FIB access through the backside of the chip has become the only viable approach. And the pervasive switch to flip-chip solder bump mounting of chips to modules and chip to chip stacked die has made the backside editing approach ever more sensible by placing the unobstructed backside of the die within easy reach. Sample preparation for backside edit, however, has become a growing problem. Mechanical thinning of the silicon to speed trenching time can be problematic on highly stressed chips as there is a high risk of silicon cracking. Plus there are situations in which die strength must be preserved to enable the transfer of an edited die to a new substrate. While single point full thickness silicon editing has been demonstrated, the need to make multiple trenches for repetitive edits can be extremely time consuming when using conventional FIB bulk removal recipes. A single logic error often gets repeated in each core of a multi-core chip, and may need to be fixed at each location. Verification of existing SRAM and the introduction of embedded DRAM (eDRAM) for large blocks of L3 cache on high end microprocessors meant that the FIB lab would be called upon to provide layout checking services on a number of designs. Clearly, a better method for rapid mass silicon removal needed to be developed to keep multi-point backside editing viable. Through an extensive set of experiments we were able to develop a process that can sustain a removal rate of 10 million cubic microns of silicon per minute, enabling full thickness trenches in as little as 25 minutes. As will be shown, this preparation technique was successfully used to ensure the bit map descramble accuracy of multiple eDRAM array blocks in several cores, and to help evaluate test coverage.
Image Reconstruction Techniques for High Numerical Aperture Integrated Circuit Imaging
Authors: Berkin Cilingiroglu T. , Hakan Koklu F. , Ramsay Euan , Lu Yang , Yurt Abdulkadir , Clem Karl W. , Konrad Janusz , Goldberg Bennett B. , Selim Unlu M. 
Published: December 2020

Abstract
As feature sizes in integrated circuits (ICs) become smaller, higher-resolution defect detection and failure analysis techniques are required. The introduction of solid immersion lenses (SIL) has been an enabling technology for highresolution backside IC imaging. High Numerical Aperture (NA) SIL imaging introduces properties of focused light which cannot be predicted by scalar beam optics. For example, spatial resolution can be manipulated in selected directions by modification of the polarization direction in linearly polarized light. In this work, we propose a unified framework combining multiple SIL microscopy images collected using polarizations at different directions in order to improve image reconstruction performance and ultimately resolution and defect localization. We show improvement in reconstruction quality by combining data taken using light with multiple polarizations. We demonstrate the effectiveness of our framework on experimental data.
Comparison of Beam-Based Failure Analysis Techniques for Microsystems-Enabled Photovoltaics
Authors: Yang Benjamin B. , Cruz-Campa Jose L. , Haase Gaddi S. , Cole Edward I. , Tangyunyong Paiboon , Okandan Murat , Nielson Gregory N. 
Published: December 2020

Abstract
Microsystems-enabled photovoltaics (MEPVs) are microfabricated arrays of thin and efficient solar cells. The scaling effects enabled by this technique results in great potential to meet increasing demands for light-weight photovoltaic solutions with high power density. This paper covers failure analysis techniques used to support the development of MEPVs with a focus on the laser beam-based methods of LIVA, TIVA, OBIC, and SEI. Each FA technique is useful in different situations, and the examples in this paper show the relative advantages of each method for the failure analysis of MEPVs.
Novel Defect Detection Using Laser-Based Imaging and TIVA with a Visible Laser
Authors: Miller Mary A. , Tangyunyong Paiboon , Cole Edward I. , Pimentel Alejandro , Udoni Darlene M. 
Published: December 2020

Abstract
This paper presents two different case studies that highlight the use of reflected light imaging in laser scanning microscopy. In the first case study, the exact location of defects in metal comb test structures were much easier to detect with reflected light imaging than with thermally-induced voltage alteration (TIVA). This case study also shows visible-wavelength TIVA defect localization using a 532-nm laser. A comparison between 532-nm TIVA and conventional 1320-nm TIVA is made to show the resolution improvement with the visible laser. In the second case study, the cause of a linear string of bit failures was localized easily with backside reflected light imaging. It is observed that the indicated sites matched the light-induced voltage alteration signals and the failing cells in the bit map. In both of the case studies, the reflected light images have proved very helpful in the localization and characterization of failing devices or test structures.
Advanced CMOS Device Fault Isolation Using Frequency Mapping on Passive Structures
Authors: Goh S.H. , Yeoh B.L. , You G.F. , Hung W.H. , Lam Jeffrey , Ruttkowski E. , Kamaludeen R. , Zhang Henry 
Published: December 2020

Abstract
Backside frequency mapping on modulating active in transistors is well established for defect localization on broken scan chains. Recent experiments have proven the existence of frequency signals from passive structures modulations. In this paper, we demonstrate the effectiveness of this technique on a 65 nm technology node device failure. A resistive leaky path leading to a functional failure which, otherwise cannot be isolated using dynamic emission microscopy, is localized in this work to guide follow on failure analysis.
Simple and Effective Technique of Backside Deprocessing of Thin Flip Chip Package
Authors: Lee Suk Ho , Park Chan Hee , Cha Seung Joon , Lee Eun Cheol , Hong Kyu Shik 
Published: December 2020

Abstract
This paper introduces a simple and effective technique of backside de-processing procedure. This technique reduces time and steps by simple wet etching. The front-side deprocessing requires many steps, such as wet and dry etching and parallel lapping, and also backside de-processing requires mechanical grinding to thin down the silicon thickness before wet etching. This paper introduces an effective way by skipping mechanical grinding and by etching at high temperature in case of thin flip chip. The backside silicon images are presented and compared after de-processing with TMAH and KOH which commonly have been used for bulk silicon etchant. The results show uniform backside images without any damage or residue. This backside de-processing technique was applied in two case studies to facilitate failure analysis.
A New Deprocess Flow of Failure Analysis for MEMS Motion Sensor
Authors: Huang Chun-An , Long Han-Yun , Chiang King-Ting , Chuang Li , Tsui Kevin 
Published: December 2020

Abstract
This paper demonstrates a new de-process flow for MEMS motion sensor failure analysis, using layer by layer deprocessing to locate defect points. Analysis tools used in this new process flow include IR optical microscopy, thermal system, SEM and a cutting system to de-process of MEMS motion sensor and successful observation defect points.
Top-Down Delayering with Planar Slicing Focus Ion Beam (TD-PS-XFIB)
Authors: Low G.R. , Tan P.K. , Ng T.H. , Yap H.H. , Feng H. , He R. , Tan H. , Dawood M.K. , Huang Y.M. , Wang D.D. , Zhao Y.Z. , Zhou Y. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
Top-down, layer-by-layer de-layering inspection with a mechanical polisher and serial cross-sectional Focused Ion Beam (XFIB) slicing are two common approaches for physical failure analysis (PFA). This paper uses XFIB to perform top-down, layer-by-layer de-layering followed by Scanning Electron Microscope (SEM) inspection. The advantage of the FIB-SEM de-layering technique over mechanical de-layering is better control of the de-layering process. Combining the precise milling capability of the FIB with the real-time imaging capability of the SEM enables the operator to observe the de-layering as it progresses, minimizing the likelihood of removing either too much or too little material. Furthermore, real time SEM view during top-down XFIB de-layering is able to provide a better understanding of how the defects are formed and these findings could then be feedback to the production line for process improvement.
Improving Failure Analysis for Cell-Internal Defects through Cell-Aware Technology
Authors: Hapke F. , Keim M. , Herrmann T. , Heidel T. , Reese M. , Schloeffel J. , Rivers J. , Redemund W. , Over A. , Glowatz A. , Fast A. , Benware B. , Rajski J. 
Published: December 2020

Abstract
This paper describes a new approach for quickly ramping up the yield for new CMOS technologies by performing a cell-internal (CI) diagnosis based on the cell-aware (CA) methodology. We present results from carrying out this new method on a test chip of a 28-nm technology. After creating defect-oriented CA test patterns for this test chip, we tested various wafers with those CA patterns, selected fail data, conducted a normal electrical failure analysis, and used the new CI diagnosis method to guide the physical failure analysis (PFA) process to look specifically for hot-spot areas within standard library cells. This new approach can reduce the yield ramp-up time significantly.
Improved Lock-in Phase Mapping of Modulated Reflectance with SIL
Authors: Qian Zhongling , Brillert Christof , Burmer Christian 
Published: December 2020

Abstract
The application of lockin phase mapping of modulated reflectance with SIL is discussed in detail, particularly the socalled ghost mapping signal in STI neighboring to active regions. The different lockin phase between active regions and ghost regions showed clearly that both of them have different physical origins. The phase transition between active regions provides an enhancement of spatial resolution for defect localization in scan cell and sub blocks.c
A Comprehensive Investigation of the Galvanic Corrosion Induced Ag-Al Bond Degradation in Microelectronic Packaging Using Argon Ion Milling, SEM, Dual Beam FIB-SEM, STEM-EDS, and TOF-SIMS
Authors: Chen Yixin , Simon Emmanuel , Khoo Bing Sheng , Lee Esther , Chooi Meailing , Hao Meng , Shao Jingjing , Hua Younan , Li Xiaomin 
Published: December 2020

Abstract
In this study, a comprehensive investigation of the Ag-Al bond degradation mechanism in an electrically failed module using the argon ion milling, scanning electron microscopy (SEM), dual beam focused ion beam-SEM, scanning transmission electron microscopy energy dispersive x-ray spectroscopy, and time-of-flight secondary ion mass spectrometry is reported. It is found that the bond degradation is due to the galvanic corrosion in the Ag-Al bonding area. Specific attention is given to the information of microstructures, elements, and corrosive ions in the degraded bond. In this study, it is believed that the Ag-Al bond degradation is highly related to the packaging designs.
Feature Based Nondestructive Fault Isolation in Advanced IC Packages
Authors: Lee K.C. , Alton J. , Igarashi M. , Barbeau S. 
Published: December 2020

Abstract
Traditional time domain reflectometry (TDR) techniques employ time-based information to locate faults within packages with minimal references to internal structures. Here, we combine a novel and innovative technique, electro optical terahertz pulse reflectometry (EOTPR) [1], with full 3D device-under-test (DUT) modelling to quickly and nondestructively perform feature-based analysis. We demonstrate fault isolation to an accuracy of 10 ìm or better with respect to device features in an advanced integrated circuit (IC) package.
Identification of Subtle Defect by Means of High Kev SEM Passive Voltage Contrast
Authors: Xie Sujing , Chen Chaoying , Wang Nathan , Komrowski Andrew , Wu Qindi , Shah Saunil 
Published: December 2020

Abstract
This paper presents two cases utilizing high KeV Passive Voltage Contrast (PVC) for defect localization that is impossible with other techniques. The first case is thin layer resistor of CrSi. De-processing or polishing to expose the defective layer may damage it. High KeV PVC combined with FIB etch allows for a clear top view and x-section image. The second case involves a beam sensitive via chain. In order to avoid ion-beam-caused-damage, carbon paste was used to ground the sample. A high KeV electron beam was used to localize the defective via. This paper also discusses the way to avoid beam caused sample damage and how to apply it for further grounding and FIB cross sectioning to reveal the defect.
In-Line Defects Overlaying with Functional Failures and Characterization for Fast Defect Learning and Fast Yield Improvement
Authors: Song Zhigang , Patterson Oliver D. , Xu Qian 
Published: December 2020

Abstract
Process defects, either random or systematic, are often the top killers of any semiconductor device. Process defect learning and reduction are the main focuses in both technology development stage and product manufacturing yield ramp stage. In order to achieve fast defect learning, in-line defect inspection is implemented in critical layers during wafer manufacturing. In-line defect inspection is able to detect defects. However, in-line defect inspection alone cannot predict the impact of defects on device functional yield. Failure analysis is an effective method of finding the defects which really cause device functional failures. However, often, the defects found by failure analysis are very different from the original defects, making it difficult to understand the root cause. This paper will describe a methodology how to combine in-line defect inspection and failure analysis together to found the top killer defects and accelerate their root cause identification for fast defect learning and yield improvement.