bluuebunny/crossref_metadata_2025_split huggingface dataset:
Analysis of Defects Generated by the Reflow Soldering in SMT (Surface Mount Technology) Assembly Applying the Six Sigma Method
Authors: Bueno Ana C. , Shiki Maíra P. , De Lima Valdemir R. , Brandão Luis G. , Oka Maurício M. 
Published: December 2020

The Six Sigma method using the DMAIC methodology is being applied for analyzing the reflow soldering process in an SMT assembly line. The Define phase (D) and Measure phase (M) were concluded, the Analysis (A) phase is being implemented, and the Improve (I) and Control (C) phases will be the next ones. Defects generated during the reflow process were classified and measured both on assembled memory modules and on virgin laminates that were passed through the oven during the reflow of these modules. Spots of solder and flux were found on the edge connector of the modules and also on the surface of the virgin laminates. It was found that these defects are generated inside the reflow oven, indicating that the oven is contaminated. Two solder pastes were analyzed and consequently, two temperature profiles were used. The amount of defects generated by the oven was found to be independent on the temperature profile. On the other hand the amount of defects depends on the solder paste that is used. The FMEA (Failure Mode and Effect Analysis) was also accomplished. As a result, the main failure modes of the reflow process were determined, namely, the heating rate, the soak temperature, the conveyor velocity, the reflow temperature, the reflow time, and the cooling rate.
Study of the Drain Leakage Current Behavior in Graded-Channel SOI nMOSFETs Operating at High Temperatures
Authors: Bellodi Marcello , Martino João Antonio 
Published: December 2020

The theoretical and experimental study of drain leakage current behavior in Graded-Channel ( GC ) SOI nMOSFETs operating at high-temperatures ( up to 300oC ) is analyzed and discussed here. Through the studies it was noticed that drain leakage current depends strongly on the ratio between the length of the lowly doped region and the mask channel length. Also, it was observed that the drain leakage behavior is similar to the conventional SOI nMOSFETs which effective channel length being equal in both structures when the GC SOI nMOSFETs has the same channel doping level in the higher doped region. Numerical bidimensional simulations and experimental data were used in order to compare and discuss all the results.
Table of contents and Foreword
Authors: Martino João Antonio , Carro Luigi 
Published: December 2020

This issue of Journal of Integrated Circuits and Systems (JICS) includes 6 papers on design, test and CAD. These papers have been selected from the presentations given at SBCCI2006 (Symposium on Integrated Circuits and Systems Design), which was organized in Ouro Preto, Brazil in 2006. Among the contributions presented at SBCCI2006 conference, only a few were selected by the Technical Committee for this issue. These papers have been submitted to usual reviewing process with the help of external experts. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection which guarantees the scientic level of this issue.We sincerely hope that JICS readers will enjoy these contributions, as we have enjoyed listening to them at the SBCCI2006 conference.
The Editors.
Table of contents and Foreword
Authors: Martino João Antonio , Carro Luigi 
Published: December 2020

This issue of Journal of Integrated Circuits and Systems (JICS) includes 8 papers on process, materials, devices, and modeling. These papers have been selected from the presentations given at SBMicro2006 (Symposium on Microelectronics Technology and Devices), which was organized in Ouro Preto, Brazil in 2006. Among the contributions presented at SBMicro2006 conference, only a few were selected by the Technical Committee for this issue. These papers have been submitted to usual reviewing process with the help of external experts. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection which guarantees the scientic level of this issue.We sincerely hope that JICS readers will enjoy these contributions, as we have enjoyed listening to them at the SBMicro2006 conference.The Editors.
Effect of Nucleation Parameters of Ge Quantum Dots Grown over Silicon Oxide by LPCVD
Authors: Mestanza S. N. M. , Doi I. , Frateschi N. C. 
Published: December 2020

Germanium quantum dots (Ge-QD) were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on Si nucleus previously grown on 3 nm thick SiO2 ultra thin film. Samples were analyzed by atomic force microscopy (AFM) and high resolution transmission electron microscopy (HRTEM). We report the analysis of the influence of the nucleation parameters on size and spatial distribution of Ge-QD. AFM images show a Ge-QD density of around 3.6x1010 cm-2, with an 11 nm mean size and 2.9 nm height. Finally, HRTEM investigation shows that the Ge-QD have a crystalline structure, i.e., they are nanocrystals.
Fabrication of Ti-Si-Ti Metal-Semiconductor-Metal Photodetectors Using Low Temperature Rapid Thermal Annealing
Authors: Ohta Ricardo L. , Viana Carlos E. , Morimoto Nilton I. , Borges Ben-Hur V. 
Published: December 2020

The electrical properties of Ti-Si-Ti Metal-Semiconductor-Metal (MSM) photodetector were studied as a function of annealing temperature, using Rapid Thermal Annealing (RTA) process. Low temperatures were used at the RTA (200-350°C) in order to avoid the formation of silicides.We observed a decrease in the dark current on samples annealed between 200 and 300°C. The lowest dark current was obtained in the sample annealed at 250°C (4.8 nA), which is one order of magnitude lower than as-deposited sample (53.5 nA). The sample annealed at 350°C had an increase in dark current (82.9 nA). This behavior of the dark current can be explained by the increase in the barrier height at 200-300°C annealing temperature range, due to increase of the thickness of the amorphous interdiffused Ti-Si interfacial layer, and decrease in the barrier value at sample annealed at 350°C, due to pre formation of C49 TiSi2.
Charge-Based Continuous Equations for the Transconductance and Output Conductance of Graded-Channel SOI MOSFET’s
Authors: De Souza Michelly , Pavanello Marcelo A. 
Published: December 2020

This paper presents charge-based continuous equations for the transconductance and output conductance of submicrometer Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. The effects of carrier velocity saturation, channel length modulation and drain-induced barrier lowering were taken into account in the proposed equations. Experimental results were used to test the validity of the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement in a wide range of bias.
Model Driven Engineering for MPSoC Design Space Exploration
Authors: Oliveira Marcio F. da S. , Brião Eduardo W. , Nascimento Francisco A. , Wagner Flávio R. 
Published: December 2020

This paper presents a Model Driven Engineering approach for MPSoC Design Space Exploration (DSE) to deal with the ever-growing challenge of designing complex embedded systems. This approach allows the designer to automatically select the most adequate modeling solution for application, platform, and mapping between application and platform, in an integrated and simultaneous way and at a very early design stage, before system synthesis and code generation have been performed. The exploration is based on high-level estimates of physical characteristics of each candidate solution. In an experimental setting, the DSE tool automatically performs four design activities: it selects the number of processors, maps tasks to processors, allocates processors to bus segments, and sets the voltage of each processor. Experimental results, extracted from a DSE scenario for a real application, show that the proposed estimation and exploration approach may find a suitable solution regarding the design requirements and constraints in a very short time, with an acceptable accuracy, without relying on costly synthesis-and-simulation cycles.
A New Router Architecture for High-Performance Intrachip Networks
Authors: Carara Everton , Calazans Ney , Moraes Fernando 
Published: December 2020

For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality of Service (QoS) achievement and/or power consumption reduction. On the other hand, the use of NoCs brings about the solution of new design problems, such to the choice of synchronization method to employ between NoC routers and application modules mapping. Although the availability of NoC structures is already rather ample, some design choices are at base of many, if not most, NoC proposals. These include the use of wormhole packet switching and virtual channels. This work pledges against this practice. It discusses trade-offs of using circuit or packet switching, arguing in favor the use of the former with fixed size packets (cells). Quantitative data supports the argumentation. Also, the work proposes and justifies replacing the use of virtual channels by replicated channels, based on the abundance of wires in current and expected deep sub-micron technologies. Finally, the work proposes a transmission method coupling the use of session layer structures to circuit switching to better support application implementation. The main reported result is the availability of a router with reduced latency and area, a communication architecture adapted for high-performance applications.
Design Space Exploration of High-Performance Parallel Architectures
Authors: Musoll Enric , Nemirovsky Mario 
Published: December 2020

High-performance single-threaded processors achieve their performance goal partly by relying, among other architectural techniques, on speculation and large on-chip caches. The hardware to support these techniques is usually a large portion of the overall processor real state area, and therefore it consumes a significant amount of power that sometimes is not optimally used toward doing useful work. In this work, we study the intuitive fact that architectures with hardware support for threads are more power efficient than a more traditional single-threaded superscalar architecture. Toward this goal, we have created a model of the power, performance and area of several parallel architectures. This model shows that a parallel architecture can be designed so that (a) it requires less area and power (to reach the same performance), or (b) it achieves better power efficiency and less area (for the same power budget), or (c) it has higher performance and better power efficiency (for the same area constraint), when compared to a single-threaded superscalar architecture.
Parallelized Radix-4 Scalable Montgomery Multipliers
Authors: Pinckney Nathaniel , Harris David M. 
Published: December 2020

This paper describes a parallelized radix-4 scalable Montgomery multiplier implementation. The design does not require hardware multipliers, and uses parallelized multiplication to shorten the critical path. By left-shifting the sources rather than right-shifting the result, the latency between processing elements is shortened from two cycles to nearly one. Multiplexers are used to select precomputed products. Carry-save adders propagate carry bits before words are discarded. The new design can perform 1024-bit modular exponentiation in 9.4 ms and 256-bit exponentiation in 0.38 ms using 4997 Virtex2 4-input lookup tables, while consuming 30% fewer LUTs than a previous parallelized radix-4 design. This is comparable to radix-2 for long multiplies and nearly twice as fast for short ones.
Table of Contents and Foreword
Authors: Martino João Antonio , Lubaszewski Marcelo 
Published: December 2020

This issue of the Journal of Integrated Circuits and Systems (JICS) includes papers on analog design, design for yield, design for security and dynamically reconfigurable architectures. These papers have been selected from the presentations given at SBCCI2008 (21st Symposium on Integrated Circuits and Systems Design), which has been held in Gramado, Brazil in 2008. Among the contributions presented at SBCCI2008, only a few best rated by the reviewers were selected by the JICS Editorial Board and have been invited to submit an extended version. These papers have been submitted to the usual reviewing process with the help of external experts. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection, which guarantees the scientific level of this issue.We sincerely hope that JICS readers will enjoy these contributions.João Antonio Martino - JICS Editor-in-chief Marcelo Lubaszewski - JICS Co-Editor
Mobility Modeling in Advanced MOSFETs with Ultra-Thin Silicon Body under Stress
Authors: Sverdlov Viktor A. , Windbacher Thomas , Schanovsky Franz , Selberherr Siegfried 
Published: December 2020

We use a two-band k·p model to describe the subband structure in strained silicon thin films. The model provides the dependence of the conductivity effective mass on strain and film thickness. The conductivity mass decreases along tensile stress in [110] direction applied to a (001) film. This conductivity mass decrease ensures the mobility enhancement in MOSFETs even with extremely thin silicon films. The two-band k·p model also describes the dependence of the non-parabolicity parameter on film thickness and strain. The influence of the subband structure modification on the mobility in advanced MOSFETs with strained ultra-thin silicon body is investigated. It is shown that an increase of subband non-parabolicity in thin films with strain reduces the mobility enhancement due to the conductivity mass modification, especially at higher strain values.
Waferlevel Vacuum Packaged Microscanners: A High Yield Fabrication Process for Mobile Applications
Authors: Oldsen Marten , Hofmann Ulrich , Janes Joachim , Quenzer Hans-Joachim , Wagner Bernd 
Published: December 2020

Packaging of MEMS is an important expense factor within the production costs and, to ensure mass producibility, the packaging has to be performed on a waferlevel. While for inertial MEMS this is state of the art, it has not yet been reported for scanning micromirrors. Therefore, Fraunhofer ISIT has developed a process technology based on two 30 μm thick epitaxially deposited polysilicon layers for the manufacturing of waferlevel vacuum packaged MEMS scanning mirrors. It allows the fabrication of vertically stacked combdrives for out-of-plane mirror operation and a low damping environment for the reduction of needed driving signals. An anodically bonded structured glass wafer seals the devices at the front side, while an Au-Si eutectically bonded silicon wafer with an integrated 400 nm thick Ti getter layer is used to seal the devices from the backside. The measurement of the quality factor allows the estimation of the internal cavity pressure of sealed devices, which is in the range of 10-3 mbar.Waferlevel measurements showed that the fabrication process reaches a high mechanical yield of Ym = 95%. Vacuum packaged devices needed 6V driving voltage to reach a total optical scan angle of above 50°.
Preparation and Characterization of Electrodeposited Co/p-Si Schottky Diodes
Authors: Zandonay R. , Delatorre R. G. , Pasa A. A. 
Published: December 2020

Schottky diodes were prepared by photoinduced electrodeposition of Co on p-Si, probing the influence of different concentrations of CoSO4 (26 and 104 mM) in the electrolyte on the electrical properties of the metal-semiconductor interface. Current density versus voltage (JxV) and capacitance versus voltage (CxV) measurements were performed in diodes with different Co thicknesses to obtain the barrier heights and ideality factors. Atomic force microscopy (AFM) and vibrating sample magnetometry (VSM) were additional techniques used to determine the surface morphology and the magnetic response. Devices with improved electrical properties were observed by increasing the thickness of the metal, i. e., saturation currents with values of about 0.1 mA.cm-2, ideality factors close to 1.19 and barrier heights of about 0.65 eV were determined.
Time-of-Flight Flow Microsensor using Free-Standing Microfilaments
Authors: Rodrigues Roberto Jacobe , Furlan Rogério 
Published: December 2020

In this work we present the processing conditions and the characterization results of a time-of-flight (TOF) flow microsensor implemented using polysilicon microfilaments. Numerical simulation (ANSYS®/FLOTRAN®) and experimental results for analysis with air flow and nitrogen are compared considering different heater to sensor distances and flows. A good agreement was observed between experimental and simulated results. However, experimental TOF values resulted ever consistently higher than the simulated ones due to delays introduced by the circuitry and the data acquisition system and also in the thermal response of the microfilament. Analysis of the heater microfilament reveal that temperatures of the order of 100 °C (that is low enough to not affect the gas flow) can be obtained with a power dissipation of tens of mW. The time-of-flight measurements show that the proposed structure is suitable for the detection of low volumetric flows (tens of SCCM) and presents a response time of the order of milliseconds.
An Integrated Switch in a HV-SOI Wafer Technology, With a Novel Self-Protection Mechanism
Authors: Miguez Matías , Gak Joel , Arnaud Alfredo 
Published: December 2020

An integrated switch to control electrical stimuli in implantable medical devices is presented. First a self-biased protection mechanism to avoid VGS reaching maximum rated value is presented. Then, using a HV-CMOS technology this technique is incorporated in a fully integrated switch, to control 0 to 16V, and 0 to 30 mA, pulses for implantable stimulators. Because of the low supply voltage VDD between 2 to 5V, and safety considerations in implantable devices, special level shifters, drivers, and a voltage multiplier, that drive a large 40000μm/3μm dual-in-series PMOS switch, were necessary for the circuit. The circuit was fabricated in a HV 0.6μm CMOS technology in SOI wafer for transistor isolation, and tested. Measurement results that closely fit the expected performance of the circuit are presented.
A Compact Low-Distortion Low-Power Instrumentation Amplifier
Authors: De Lima Jader A. 
Published: December 2020

A CMOS instrumentation amplifier based on a simple topology that comprises a double-input Gm-stage and a low-distortion class-AB output stage is presented. Sub-threshold design techniques are applied to attain high figures of differential-gain and rejection parameters. Analyses of input-referred noise and CMRR are comprehensively carried out and their dependence on design parameters determined. The prototype was fabricated in standard n-well CMOS process. For 5V-rail-to-rail supply and bias current of 100nA, stand-by consumption is only 16μW. Low-frequency parameters are ADM=86dB, CMRR=89.3dB, PSRR+=87dB, PSRR-=74dB. For a 6.5pF-damping capacitor, ΦM=73º and GBW=47KHz. The amplifier exhibits a THD of –64.5dB @100Hz for a 1Vpp-output swing. Input-noise spectral density is 5.2μV/ Hz @1Hz and 1.9μV/ Hz @10Hz, which gives an equivalent input-noise of 37.6μV, over 1Hz-200Hz bandwidth. This circuit may be employed for low-frequency, low-distortion signal processing, advantageously replacing the conventional 3-opamp approach for instrumentation amplifiers.
PECVD Silicon Oxynitride as Insulator for MDMO-PPV Thin-Film Transistors
Authors: Cavallari Marco R. , Albertin Katia F. , Dos Santos Gerson , Ramos Carlos A. S. , Pereyra Inés , Fonseca Fernando J. , De Andrade Adnei M. 
Published: December 2020

We demonstrate that PECVD SiOxNy with good dielectric properties can replace thermally grown SiO2 in Organic Thin-Film Transistors (OTFT) applications. It can be used on ITO-covered glass or even flexible substrates. Poly [2-methoxy-5-(3’,7’-dimethyloctyloxy)-1,4-phenylenevinylene] (MDMO-PPV) is used as the active layer, due to its wide range of applications such as bulk heterojunction solar cells, light-emitting diodes and light-emitting transistors.We show that charge carrier mobility can be at least two times higher for MDMO-PPV on silicon oxynitride than silicon dioxide, μh 1.1x10-4 cm2/Vs. MDMO-PPV spun from solvents such as chloroform and toluene provide comparable TFT performance on SiOxNy. Preliminary studies of devices with hexamethyldisilazane-treated SiO2 demonstrate that performance can be further improved by the choice of a proper surface treatment.
A Study of the Geometrical Correction Factor and the Membrane Thickness on the Sensitivity of the Transversal Piezoresistive Pressure Sensor
Authors: Coraucci G. O. , De Oliveira R. V. D. , Garcia V. , Fruett F. 
Published: December 2020

The sensitivity of four-terminal devices like Hall and piezoresistive sensors is very dependent on its geometric parameters. This dependence is modeled by the Geometrical Correction Factor (G). The majority of these studies take very time-consumption analytical calculations for the analysis of G. In order to simplify this analysis, we present numerical analyses using FEM (Finite Element Method) for the most common geometrical forms of four-terminal devices. This result is general for any fourterminal-shaped sensors and can be used to optimize the sensor aspect ratio leading the maximization of G. In addition, FEM was also used to evaluate the membrane´s thickness influence over the sensor sensitivity by analyzing the in-plane mechanical stress behavior on the sensor active area. Experimental result of a new topology of pressure sensor is also presented, which maximizes G in comparison with conventional four-terminal devices and also improves its sensitivity. A special designed anisotropic wet etching system was used to post-process the sensor membrane. This anisotropic wet etching system allows the fabrication of well-defined membranes with thickness of 20 μm ± 3 μm and roughness as low as 90 nm rms.
Performance of Source Follower Buffers Implemented with Standard and Strained Triple-Gate nFinFETs
Authors: Pavanello Marcelo Antonio , Martino João Antonio , Simoen Eddy , Rooyackers Rita , Collaert Nadine , Claeys Cor 
Published: December 2020

In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion.