Deep Level Assessment of n-Type Si/SiO2 Metal-Oxide-Semiconductor Capacitors with Embedded Ge Quantum Dots
Authors: Aouassa Mansour , Vrielinck Henk , Simoen Eddy 
Published: February 2020

Device structures with silicon or germanium nanodots embedded in an oxide matrix may find application in the field of Non-Volatile Memories (NVMs) [1,2] or photonics [3,4]. In the former case, the nanodots can become charged by tunneling of electrons or holes from the silicon substrate through a tunnel oxide. Successful operation requires that the charge does not leak away by the assistance of traps or defects in the material stack. The latter can be probed by techniques like Admittance Spectroscopy [5] or Deep-Level Transient Spectroscopy (DLTS) [2,5]. In the present work we report on a systematic investigation of Metal-Oxide-Semiconductor (MOS) capacitors fabricated on n-type Czochralski silicon substrates and containing Ge nanodots with different size.
Ge nanodots with average diameter of 1, 2 or 3 nm have been deposited by Molecular Beam Epitaxy (MBE) on a 5 nm tunnel oxide, thermally grown on n-type Czochralski silicon wafers. An Atomic Force Microscopy (AFM) picture is shown in Fig. 1. Next, 50 nm of SiO2 is deposited. MOS capacitors are prepared by thermal evaporation of 2 mm diameter Al gate contacts, while InGa+In foil ohmic contacts are prepared on the silicon substrate side. The device structure is schematically shown in Fig. 2. Capacitance-Voltage (C-V) characterization is performed at a fixed frequency f=1 MHz, using both a forward and reverse gate voltage sweep. As can be seen in Fig. 3, the presence of the Ge nanodots has a pronounced impact on the C-V characteristics: there is a shift towards positive flat-band voltage, compared with the zero dot reference, a strong increase of the accumulation capacitance and, for the nanodot samples, the hysteresis increases with the increase in nanodot size.
For temperature (T-) scan DLTS, the capacitors are mounted in a helium contact gas cryostat cooled with liquid nitrogen. Measurements at different bias pulses from reverse bias (VR) to the pulse bias (VP) are performed in parallel in order to probe the electron traps in different parts of the structure. An example is given in Fig. 4, for the 1 nm nanodots sample. It shows that in deep depletion, there is a broad peak between 150-250 K which could stem from the response of filled interface traps. The increase found at room temperature may originate from minority carrier generation in the depletion region [2,5,6]. When probing closer to the interface, for more positive VR, a pronounced but broad peak around 200 K dominates the spectra. From the Arrhenius plot shown in Fig. 5, it is concluded that it corresponds to the dangling bond (Pb) acceptor level at about 0.31 eV from the conduction band [2,5,6]. Maximum densities are estimated in the range of 5x1011 cm-2eV-1. A comparison of the spectra near the interface for the different samples studied is provided in Fig. 6 and will be discussed in more detail in the conference paper.

References

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Figure 1