bluuebunny/crossref_metadata_2025_split huggingface dataset:
Frequency Domain Imaging: Acoustic Microscopy Technique for Die Stacking Application
Authors: Aspera France B. , Flores Christopher , Salvador Ma. Cristina 
Published: December 2020

Abstract
Die stacking package technology continues to become the trend of manufacturing integrated circuits (IC) today. This primary design offers smaller and thinner packages that would optimize board space and assembly cost. Consequently, this packaging technology has posed challenges in conducting failure analysis. Nondestructive techniques like acoustic microscopy are bound for advancement to make them feasible for use in this packaging technology. This paper will present frequency domain imaging in the field of acoustic microscopy as applied in the detection of delamination defect on a stacked die package. Fast Fourier Transform (FFT) was used as an algorithm to reconstruct and reveal the delamination defect which was not clearly detected in time domain imaging of the package. Frequency domain imaging was found to offer a better image contrast of delamination. This gives the failure analyst another approach to characterize the location and extent of delamination defect, a set of information that is substantial in the root cause analysis of adhesion related failures in stacked die packages.
Defect Snap Shot: Quick Isolation and Mapping of Interconnect Defects for Backend Yield Improvement
Authors: Fan Jenny , Mark Dave 
Published: December 2020

Abstract
Metal interconnect defects have become a more serious yield detractor as backend process complexity has increased from a single layer to about 10 layers. This paper introduces a test methodology to monitor and localize the metal defects based on FPGA products. The test patterns are generated for each metal layer. The results not only indicate the severity of defects for each metal layer, but also accurately isolate open/short defects.
Material and Doping Contrast in Semiconductor Devices at Nanoscale Resolution Using Scattering-Type Scanning Near-Field Optical Microscopy
Authors: Wittborn J. , Weiland R. , Kazantsev D. , Huber A. , Hillenbrand R. , Keilmann F. 
Published: December 2020

Abstract
The usefulness of scattering-type near-field optical microscopy for mapping the material and doping in microelectronic devices at nanoscale resolution is demonstrated. Both amplitude and phase of infrared (λ = 10.7 μm) laser light scattered by a metallised, vibrating AFM tip scanned a few nanometers above the sample are detected and transformed into images showing contrast of materials, as well as of doping concentration. Cross-sections through layers as thin as 20 nm have been clearly imaged.
A System for Electromechanical Reliability Testing of MEMS Devices
Authors: Spinner Stefan , Doelle Michael , Ruther Patrick , Paul Oliver , Polian Ilia , Becker Bernd 
Published: December 2020

Abstract
This paper reports on a setup and a method that enables automated analysis of mechanical stress impact on microelectromechanical systems (MEMS). In this setup both electrical and optical inspection are available. Reliability testing is possible on a single chip as well as on the wafer level. Mechanical stress is applied to the tested structure with programmable static forces up to 3.6 N and dynamic loads at frequencies up to 20 Hz. The applications of the presented system include the postmanufacturing test, characterization and stress screens as well as reliability studies. We report preliminary results of long-term reliability testing obtained for a CMOS-based stress sensor.
Mixed-Signal Test Software Generation Process—Open Environment, Software Engineering Methods and Tools for Improving Quality and Productivity
Authors: Vock Stefan , von Staudt Hans Martin 
Published: December 2020

Abstract
Typical mixed-signal ICs are approaching 1000 or even more parametric tests. These tests are usually coded in a procedural or a semi-object oriented language. The huge code base of the programs is a significant challenge for maintaining code quality which inherently translates into outgoing quality. The paper will present software metrics of typical mixedsignal power management and audio devices with regard to the number of tests conducted. It will be shown that classical ways to handle test programs are error prone and tend to systematically repeat known mistakes. The adoption of selected software engineering methods can avoid such mistakes and improves the productivity of the mixed-signal test generation. Results of a pilot project show significant productivity improvement. Open-source based software is employed to provide the necessary tool support. They establish a potential roadmap to become independent of proprietary tester specific tool sets.
Image Intensity Analysis for Defect Localization Utilizing SEM BSE Imaging
Authors: Demarest J. , Chanda K. , Klepeis S. , Redder B. , Shore A. , Wang Y. , Christiansen C. , Rue C. 
Published: December 2020

Abstract
Failure analysts occasionally find themselves faced with the problem of having one of the various defect isolation techniques indicating a defect location, and yet no defect is readily visible through the various imaging methods available. Many common conventional imaging tools, such as scanning electron microscopes (SEM), display images in shades of gray. The human eye is inherently more sensitive to changes in color rather than changes in grayscale. As a result, subtle variations in grayscale which could indicate the defect location can go unobserved unless a careful examination of the image intensities is performed. One useful way to highlight these variations is through intensity profiling where a line scan is drawn through the region under investigation and compared to an identical reference location contained within the same image. Subtle variations in the intensity profiles can then be identified and defect locations can be pinpointed to specific locations for later cross sectioning and final root cause determination. This paper discusses the application of this methodology to two case studies: a resistive short and a resistive open.
Applications of Soft Defect Localization (SDL) on AMD Advanced SOI Microprocessors
Authors: Seah Yi-Xuan , Palaniappan M. , Chin J.M. 
Published: December 2020

Abstract
In this paper, we present application of the SDL technique towards full root cause analysis of functional and structural failures from BIST, SCAN etc. on AMD’s advanced Silicon-on-Insulator (SOI) microprocessors based on a 90 nm process technology node. The devices were exercised at speed using production testers. SDL is used on these microprocessors with failure modes which pass at a lower temperature/voltage but fail at higher temperature/voltage or vice versa to isolate the failing logic/node. The SDL sites are examined for a full root cause analysis and possible process improvements.
Back Side Die Preparation for Check of Backend Related Problems
Authors: Huettinger Michael , Papenberg Uwe , Touzel Jerome , Janeiro Abel , Guedes Ricardo , Caldeira Conceicao , Ribeiro Carla 
Published: December 2020

Abstract
Damage on the top metal layer caused by backend packaging processes often results in unlocalizable electrical failures like column select fails in DRAM products. Consequently, crosssections through an exact address are unhelpful. Decapping from the front side of the die by removing the package (Top- Down preparation), only uncovers the damaged die area. The root cause is removed with the package. A preparation method that preserves the package at the failure (Bottom-Up preparation) is necessary. This paper presents a preparation method for investigations and assessment of backend related problems by removal of the Si-die from the back side, leaving the package and connections layers free for a quick and reliable review. Typical applications described here are the localization of imprint-originated fails or monitoring of the bonding processes.
Indirect Electrostatic Discharge Stressing Mechanism in VLSI Chips with Multiple Power Supply Domains
Authors: Sofer Sergey , Fefer Yefim , Shapira Yoram 
Published: December 2020

Abstract
Indirect electrostatic discharge stressing of a chip with multiple isolated power domains was analyzed. The stress penetrates to the victim domain via common nets having nonnegligible complex impedance and via coupling of the interdomain parasitic capacitors and in some cases may cause chip damage.
An Advanced Integrated Circuit Analysis System
Authors: Keyes Edward , Abt Jason 
Published: December 2020

Abstract
Historically, the extraction of circuitry from an integrated circuit was normally within the abilities of the average FA laboratory and could be accomplished with little more than an optical microscope and film camera. Dramatic increases in the level of integration and number of metal interconnect levels coupled with shrinking feature sizes have rendered these techniques obsolete. This paper describes techniques and methods for the fast, semi-automated extraction of detailed circuit schematics from modern, nanometer scale integrated circuits.
Yield Learning with Layout-aware Advanced Scan Diagnosis
Authors: Mekkoth Jayanth , Krishna Murali , Qian Jun , Hsu Will , Chen Chien-Hui , Chen Yuan-Shih , Tamarapalli Nagesh , Cheng Wu-Tung , Tofte Jan , Keim Martin 
Published: December 2020

Abstract
Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.
NBTI Reliability of Strained SOI MOSFETs
Authors: Thareja Gaurav , Lee Jack , Thean Aaron Voon-Yew , Vartanian Victor , Nguyen Bich-Yen 
Published: December 2020

Abstract
We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET on Strained Silicon on Insulator (S-SOI) substrates for the first time. The degradation has been found to be significantly higher for the S-SOI devices in comparison to SOI counterparts. Subsequent to a Constant Voltage Stress (CVS) during NBTI measurements, a negligible change in the subthreshold swing values was observed. Thus it is believed that generation of fixed charge is responsible for the observed BTI shift in threshold voltage (VTH) and transconductance (GM). Also higher BTI degradation was recorded for short channel devices.
Atomic Force Probe Analysis of Nonvisible Defects in Sub-100nm CMOS Technologies
Authors: Mulder Randal , Subramanian Sam , Chrastecky Tony 
Published: December 2020

Abstract
Traditional micro-probing and electrical characterization at the transistor level for sub-100nm technologies has become very difficult if not virtually impossible. Scanning probe microscopy technology specifically atomic force probing was developed in response to these issues with traditional micro-probing. The case studies presented in this paper demonstrate how atomic force probing was used to characterize failing sub-100nm transistors, identify possible failure mechanisms, and allow device/process engineers to make adjustments to the wafer fabrication process to correct the problem even though physical analysis with scanning election microscope/transmission electron microscope was not able to image and identify a failure mechanism. The probable causes for the transistor level failures are being identified through test methods, computer simulations, and electrical analysis by means of the atomic force probe after the failure has been sufficiently localized to a minimum number of transistors.
90nm Technology SRAM Soft Fail Analysis Using Nanoprobing and Junction Stain TEM
Authors: Zimmermann Gunnar , Mueller Stefan 
Published: December 2020

Abstract
This article describes a 90nm technology SRAM soft fail analysis. The bitmaps of affected wafers show a large number of wafer edge dies failing with single cell cluster fails at supply voltages below 1.0V. The fails appear in characteristic areas within a 256k dualport SRAM memory block. Nanoprobing was used for electrical localization at the cell level by means of a Multiprobe atomic force probe (AFP) system. Fail areas exhibit very weak PFET drain currents several orders of magnitude below the target values, while the drain currents of NFET cell transistors are in the expected range. For fail visualization a junction stain was applied to TEM samples to delineate areas with different doping levels. Due to differences in etch behavior between failed and reference areas, missing LDD extensions and a partially blocked source/drain (S/D) implantation were identified as the root cause of the fails.
Integrated Raman – IR Thermography for Reliability and Performance Optimization and Failure Analysis of Electronic Devices
Authors: Kuball Martin , Sarua Andrei , Pomeroy James W. , Falk Aaron , Albright Grant , Uren Michael J. , Martin Trevor 
Published: December 2020

Abstract
We report on the development of a novel thermography technique, integrated Raman – IR thermography, illustrated here on AlGaN/GaN electronic devices. As it is a generic technique future application to Si, GaAs and other devices is anticipated. While IR thermography can provide fast temperature overviews, its current use for many of today’s technologies is complicated by the fact that it does not provide the spatial resolution needed to probe sub-micron/micron size active device areas. Integrating IR with micro-Raman thermography, providing temperature information with ~0.5 µm spatial resolution, enables unique thermal analysis of semiconductor devices to a level not possible before. This opens new opportunities for device performance and reliability optimization, and failure analysis of modern semiconductor technology, in research, development, and quality control / manufacturing environments.
Re-Thin a TEM Lamella by Using a Novel TEM Sample Preparation
Authors: Chen C. R. 
Published: December 2020

Abstract
Conventional FIB ex-situ lift-out is the most common technique for precise TEM sample preparation. But this method has some limitations and so in-situ lift-out technique was developed to overcome these drawbacks. The in-situ lift-out technique lifts-out the sample and then attaches the sample to a half-cut copper grid inside the FIB chamber by mini-probing system. This paper introduces a novel and simple technique that can overcome the above problems and a wide application of TEM samples preparation. The examples highlighted here demonstrate the novel method of low cost and high image quality TEM sample preparation. The method can reduce the amorphous phenomenon on the sidewall of specimen; no shield effect was found during the reprocess of thinning by ion-miller; and no contamination induced by the ion-miller sputtering was formed.
Detection and Verification of Silicide Pipe Defects on SOI Technology Using Voltage Contrast Inspection
Authors: Patterson Oliver D. , Kang Hyoung H. , Strane Jay , Lavoie Christian , Barth Karl , Ouyang Xu , Wu Kevin 
Published: December 2020

Abstract
A methodology for detecting silicide pipes on SOI technology in-line soon after their formation is described. Techniques currently exist to detect pipes in-line, but only much later in the process. This methodology, which is based on voltage contrast inspection of test structures, allows experiments to be completed more quickly providing much faster cycles of learning. Two different test structures are described. The first one was designed for other purposes but was adopted for silicide pipe detection at M1. The second was specially designed and allows pipe detection at silicide anneal, W CMP and M1. A procedure for determining the cause of buried shorts detected by the eS32 is also described. Experimental results are presented to demonstrate the benefit of this technique.
Concepts for In Situ Diagnostics in Analog Microelectronic Circuits
Authors: Kolasa Ted , Mendoza Alfredo 
Published: December 2020

Abstract
Comprehensive in situ (designed-in) diagnostic capabilities have been incorporated into digital microelectronic systems for years, yet similar capabilities are not commonly incorporated into the design of analog microelectronics. And as feature sizes shrink and back end interconnect metallization becomes more complex, the need for effective diagnostics for analog circuits becomes ever more critical. This paper presents concepts for incorporating in situ diagnostic capability into analog circuit designs. Aspects of analog diagnostic system architecture are discussed as well as nodal measurement scenarios for common signal types. As microelectronic feature sizes continue to shrink, diagnostic capabilities such as those presented here will become essential to the process of fault localization in analog circuits.
An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages
Authors: Hertl Michael , Weidmann Diane , Ngai Alex 
Published: December 2020

Abstract
A new approach to reliability improvement and failure analysis on ICs is introduced, involving a specifically developed tool for Topography and Deformation Measurement (TDM) under thermal stress conditions. Applications are presented including delamination risk or bad solderability assessment on BGAs during JEDEC type reflow cycles.
Laser Timing Probe with Frequency Mapping for Locating Signal Maxima
Authors: Koh L.S. , Marks H. , Ross L.K. , Chua C.M. , Phang J.C.H. 
Published: December 2020

Abstract
A Laser Timing Probe (LTP) system which uses a noninvasive 1.3 µm continuous wave (CW) laser with frequency mapping and single point measurement capabilities is described. The frequency mapping modes facilitate the localization of signal maxima for subsequent single point measurements. Measurements of waveforms with long delays and 50 ps response time from NMOS and PMOS transistors are also shown.
Electrical Signature Verification of a Lightly Doped Drain Profile Abnormality in a 65nm Device via Nano-Probing and Junction Stain TEM
Authors: Su Jie , Liang Sanan , Wen Yoyo , Yang May , Wu Linfeng , Niou Chorng , Chen Xianfeng , Zhao Gary 
Published: December 2020

Abstract
Failures caused by threshold voltage (Vt) shifts in sub-100nm technology transistors have become very difficult to both analyze and determine the failure mechanism. The failure mechanisms for Vt shifts are typically non-visible for traditional physical analysis methods such as SEM inspection or traditional TEM analysis. This paper demonstrates how nano-probing was used to carefully and fully characterize the Vt shift failure to determine a specific electrical signature for a specific failure mechanism and then with junction stain Transmission Electronic Microscopy (TEM) verify the subtle doping defect affecting the Static Random Access Memory function in the 65nm generation node. Device failure due to a lack of Lightly Dope Drain (LDD) implant induced by an inconspicuous spacer defect was determined to be the root cause of the failure.
Non-Destructive Failure Analysis in Organic Thin-Film Transistors
Authors: Liu Shih-Ting , Liu Tao-Chi , Chang Ming-Lun , Chiang King-Ting , Chiu Su-Ping , Lin Jandel , Lo Po-Yuan , Li Pei-Wen 
Published: December 2020

Abstract
Contrary to conventional Si-based device, organic thin-film transistors (OTFTs) constituting organic semiconductors are easily destroyed. Investigating failures using traditional FA techniques like electron microscopy or cross section is hard to procure. Therefore, the purpose of this paper attempts to develop approaches for failure analysis of OTFTs. We successfully demonstrate a non-destructive technique for defect inspection and localization, exactly specifying the failure of OTFT with a void existing in the organic dielectric. Application of optical beam induced resistance change (OBIRCH) in current leakage localization is shown. Non-distorted cross-section sample preparation and analysis of internal structure by electron microscopy are also developed. Moreover, the failure of OTFT induced by high driving voltage punch-through is analyzed using techniques established in the article. Particular elongation of the gate metal was found to be the failure mode.
Approaches to Photovoltaic Systems Reliability
Authors: Granata Jennifer E , Collins Elmer , Mundt Mike , Robert Sorensen N. , Quintana Michael A. 
Published: December 2020

Abstract
Although crystalline silicon PV technology has been in use for more than 30 years, PV has remained a "cottage industry" until the recent expansion. This paper provides an introduction to the issues of reliability in the photovoltaic (PV) field, and the work the Department of Energy's Solar Energy Technologies Program is focused on to address these issues. In particular, the works of the Reliability Programs at both Sandia National Laboratories and the National Renewable Energy Laboratory are reviewed with several examples of results included and sited. Expanding reliability assessment and failure analysis techniques for components and systems can enhance the reliability of PV systems, which is necessary for large-scale deployment of PV as a power generation source.
Doping Profile Inspected by SEM Dopant Contrast, Wet Stain and SCM
Authors: Chou Po Fu , Chen Chun Yen 
Published: December 2020

Abstract
The techniques of doping profile inspection, such as SEM (Scanning Electron Microscope) dopant contrast, SEM wet stain and SCM (Scanning Capacitance Microscope) have been widely used in failure analysis for implant root causes identification. The applications of real FA (Failure analysis) cases and advantages/disadvantages will be discussed and demonstrated in this paper. To sum up, SEM dopant contrast is the most convenient method for doping profile inspection, and SCM is the best method for low doping profile observation.
A Novel Technique of Device Measurement after Cross-Sectional FIB in Failure Analysis
Authors: Chang Chih-Chung , Lin Jian-Chang , Wu Wen-Sheng , Tasi Chih-Ying , Chang Ching-Lin 
Published: December 2020

Abstract
A dual beam FIB (Focused Ion Beam) system which provides the ion beam (i-beam) and electron beam (e-beam) function are widely used in semiconductor manufacture for construction analysis and failure cause identification. Although FIB is useful for defect or structure inspection, sometimes, it is still difficult to diagnose the root cause via FIB e-beam image due to resolution limitation especially in products using nano meter scale processes. This restriction will deeply impact the FA analysts for worst site or real failure site judgment. The insufficient e-beam resolution can be overcome by advanced TEM (Transmission Electron Microscope) technology, but how can we know if this suspected failure site is a real killer or not when looking at the insufficient e-beam images inside a dual beam tool? Therefore, a novel technique of device measurement by using C-AFM (Conductive Atomic Force Microscope) or Nano-Probing system after cross-sectional (X-S) FIB inspection has been developed based on this requirement. This newly developed technology provides a good chance for the FA analysts to have a device characteristic study before TEM sample preparation. If there is any device characteristic shift by electrical measurement, the following TEM image should show a solid process abnormality with very high confidence. Oppositely, if no device characteristic shift can be measured, FIB milling is suggested to find the real fail site instead of trying TEM inspection directly.