bluuebunny/crossref_metadata_2025_split huggingface dataset:
Fault Diagnosis on the TMS320C80 (MVP) Using FastScan™
Authors: Platt J. , Butler K.M. , Venkataraman S. , Hetherington G. , Lorig G. 
Published: December 2020

Abstract
With the ever decreasing trend in accessibility to hardware tools, the need for software tools is becoming greater than ever for IC fault diagnosis. In this paper, we present a process of studying the limitations and capabilities of fault diagnosis using automated Diagnosis tools, such as FastScan™, as applied to a programmable, parallel processing DSP, The Multimedia Video Processor (TMS320C80). Starting with a brief description of the MVP, we describe how FastScan™ is integrated for supporting fault diagnosis. For establishing the effectiveness of FactScan™ as a diagnostic tool, both the simulation and manufacturing modes of evaluation were done. In simulation mode, both the fault model and the heuristics used by the fault diagnosis software are tested by inserting known defects using a focused ion beam (FIB), machine. This process is then repeated with unknown defects in unknown locations. Experiments on several chips demonstrate the value of the tool and its limitations in relation to detection of classic stuck-at faults and some realistic faults, such as bridging defects.
A Signature Analysis Method for IC Failure Analysis
Authors: Henderson C.L. , Soden J.M. 
Published: December 2020

Abstract
A new method of signature analysis is presented and explained. This method of signature analysis can be based on either experiential knowledge of failure analysis, observed data, or a combination of both. The method can also be used on low numbers of failures or even single failures. It uses the Dempster-Shafer theory to calculate failure mechanism confidence. The model is developed in the paper and an example is given for its use.
The Study of ESD Destructive Mechanism for PN-Junction
Authors: Wakai N. , TsuTsumi M. , Setoya T. 
Published: December 2020

Abstract
Mechanism of destruction caused by electrostatic discharge of PN junction was examined from two viewpoints; classification of destruction mode with consideration to destructive energy density, and comparison of destruction shape. Destructive energy density of PN junction was calculated based on Speakman model, and destruction mode was classified by Wunsch-Bell plot. As a result of Wunsch-Bell plot, electric discharge which occur at low resistance, for example machine model (MM: C∙R = 200pF ∙ 0Ω), resulted in adiabatic destruction that does not involve thermal diffusion. With electric discharge at high resistance, for example human body model (HBM: C∙R = 100pF ∙ 1500Ω), excessive destruction in intermediate region that involves thermal diffusion, and depending on the device, destruction at equilibrium region were proven to be reproducible. In case of MM, (adiabatic region destruction) destruction was confirmed in a wide extent of the joint part, but in case of HBM (intermediate region destruction) destruction was confirmed near the center of the joint part. From this fact, it was found that by verifying the places of destruction and their shapes, although in special cases, it is possible to know the destruction mode when destruction occurs.
Dielectric Breakdown in Printed Circuit Boards at Elevated Temperatures
Authors: Singh P. , Galyon G.T. , Obrzut J. , Alpaugh W.A. 
Published: December 2020

Abstract
A time delayed dielectric breakdown in printed circuit boards, operating at temperatures below the epoxy resin insulation thermo-electrical limits, is reported. The safe temperature-voltage operating regime was estimated and related to the glass-rubber transition (To) of printed circuit board dielectric. The TG was measured using DSC and compared with that determined from electrical conductivity of the laminate in the glassy and rubbery state. A failure model was developed and fitted to the experimental data matching a localized thermal degradation of the dielectric and time dependency. The model is based on localized heating of an insulation resistance defect that under certain voltage bias can exceed the TG, thus, initiating thermal degradation of the resin. The model agrees well with the experimental data and indicates that the failure rate and truncation time beyond which the probability of failure becomes insignificant, decreases with increasing glass-rubber transition temperature.
TPLY for Yield Improvement
Authors: Matusiewicz G. 
Published: December 2020

Abstract
A strategy for improving yield lately is this: wafers are electrically tested to determine which chips are defective. Defects are located and classified by the failure analyst who establishes a root cause for each type of defect. This information is delivered to the process engineers who then eliminate the root causes of the most frequently occurring defects. This process is known as TPLY. for Tested Product Limited Yield. This method gives the physical failure analyst the job of finding statistical numbers of defects. Defects are located by deprocessing chips and examining them with an optical or electron microscope, usually in an area of the chip identified by a bit fail map or some other technique, such as liquid crystal hot spot detection. This presentation offers practical suggestions for improving the efficiency of the TPLY process. It includes general considerations for TPLY, methods for delayering chips and finding defects quickly, and statistical methods for identifying the cause of low yield with minimum sample sizes. A simple yield model is developed for relating test site yield to product chip final test yield, and explains why test sites do not always adequately predict yield of the product. Case studies and other examples are discussed to demonstrate the application of these techniques.
An Investigation into Moisture-Induced Cracking in Plastic Packages Using Thermal Analysis Techniques
Authors: Chew S. 
Published: December 2020

Abstract
Pop-corn package cracking in thin quad flatpack packages (TQFP) during surface mount solder reflow can be minimized by adopting precautionary measures such as design changes, selection of new grades of epoxy mold compound (EMC) with lower affinity for moisture and lower expansivity, shipment and storage of epoxy mold compound under dry pack, as well as drying of plastic package prior to solder reflow. This paper investigates, using thermal analysis techniques, the cause of pop-corning phenomenon from pad-plastic interface in a particular batch of TQFPs despite the precautionary measures adopted. By comparing the difference in EMC properties between a control and reject batch of TQFP, this study suggest that ensuring optimum degree of polymerization or cure of the epoxy encapsulant can also assist in minimizing package delamination and pop-corn cracking.
Focused Ion Beam Irradiation Induced Damages on CMOS and Bipolar Technologies
Authors: Benbrik J. , Rolland G. , Perdu P. , Benteo B. , Casari M. , Desplats R. , Labat N. , Touboul A. , Danto Y. 
Published: December 2020

Abstract
Focused Ion Beam is commonly used for IC repairs and modifications. However, FIB operation may also induce a damaging impact which can takes place far from the working area due to the charge-up phenomenon. A complete characterization joined to an in-depth understanding of the physical phenomena arising from FIB irradiation is therefore necessary to take into account spurious FIB induced effects and to enhance the success of FIB modifications. In this paper, we present the effects of FIB irradiation on the electrical DC performances of different electronic devices such as nMOS and pMOS transistors, CMOS inverters, PN junctions and bipolar transistors. From the observed behavior of the DC characteristics evolution of the devices, some suggestions about physical mechanisms inducing the electrical degradation are proposed.
Performing Circuit Modification and Debugging Using Focused-Ion-Beam on Multi-Layered C4 Flip-Chip Devices
Authors: Li Susan X. 
Published: December 2020

Abstract
The task of circuit repairing and debugging using a Focused-Ion-Beam system on multi-layered IC devices is often difficult and tedious, especially when desired or target metal nodes or layers are buried under other higher level or nontarget metal nodes or layers. As a result, not only are target nodes difficult to access, but also, undesired shorts are difficult to prevent. To further complicate the situation, as the number of metal layers increases, the lower level metal nodes become increasingly thinner, and the node population becomes increasingly denser. These conditions result in a decreased success rate utilizing the FIB and an increased turn-around time for design debugging. Besides significant improvement of the FIB equipment and tools, new techniques that can be used to overcome the difficulties encountered during FIB operations on multi-layered IC devices need to be utilized. In this paper, we will focus on discussion of some new techniques that can be used for FIB device modification work and device debugging on multi-layered IC devices, including C4 (controlled-collapse chip connection) flip-chip devices. Some recommendations and tips for using these techniques on complicated fib modification work will also be shared based on the author’s experience.
Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM
Authors: Perungulam Srikanth , Wills Scott , Mekras Greg 
Published: December 2020

Abstract
This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.
ESD Effects on Electromigration Performance of Aluminum Metallization Systems
Authors: Vinson J. E. , Dion M. J. 
Published: December 2020

Abstract
The semiconductor industry continues to challenge designer’s ability to provide adequate protection for ESD by scaling to ever-smaller geometries. The metal lines used to connect these circuit elements are also scaled. The effect of non-destructive ESD events on aluminum metal lines is investigated showing a reduction in electromigration lifetime for ESD events close to the failure threshold of the metal. The mechanism contributing to the reduction is a change in the microstructure of the metal resulting in void formation similar to traditional electromigration damage rather than melting and crystallization into smaller grains.
Guidelines for Two-Dimensional Dopant Profiling Using Scanning Capacitance Microscopy
Authors: Born Axel , Wiesendanger R. 
Published: December 2020

Abstract
This paper provides guidance and insights on the use of scanning capacitance microscopy (SCM) in semiconductor failure analysis. It explains why SCM systems are constrained by rigid performance tradeoffs and how CV measurements are affected by large stray capacitance and as well as edge effects associated with the 3D geometry of the sample and probe. It also explains how samples should be prepared and how proper sample preparation techniques combined with optimally selected voltages make it possible to accurately determine doping concentrations, even in p-n junctions.
Magnetic Current Imaging Techniques: Comparative Case Studies
Authors: Crépel Olivier , Descamps Philippe , Poirier Patrick , Desplats Romain , Perdu Philippe , Firiti Abdelhatif 
Published: December 2020

Abstract
Magnetic field based techniques have shown great capabilities for investigation of current flows in integrated circuits (ICs). After reviewing the performances of SQUID, GMR (hard disk head technologies) and MTJ existing sensors, we will present results obtained on various case studies. This comparison will show the benefit of each approach according to each case study (packaged devices, flip-chip circuits, …). Finally we will discuss on the obtained results to classify current techniques, optimal domain of applications and advantages.
Electrical Characterization of Sub-30nm Gatelength SOI MOSFETs
Authors: Kane Terence , Tenney Michael P. 
Published: December 2020

Abstract
Atomic Force Probe (AFP) techniques are well suited for the electrical characterization of sub-65nm node SOI devices with multiple metal interconnect levels and low-k interlevel dielectric films. This paper discusses the use of these techniques on sub-30nm gatelength SOI MOSFETs.
IC Specification Improvement Through Direct Passive Component Modification in the FIB
Authors: Domengès B. , Feron B. , Ledain S. , Tiphaigne B. 
Published: December 2020

Abstract
It is shown in this study that it is possible to modify under a controlled way the resistance of a passive component either through the milling of part of the volume of a polysilicon resistor or on the contrary through the deposition of a Pt strap parallely connected to the involved device polysilicon resistor. In the latter case, each modification step being followed by an electrical characterization, the evolution of device VCO phase noise versus equivalent resistor value could be drawn and the optimum value quantified.
Photon Emission Microscopy in 90 nm CMOS Technologies
Authors: Kruseman Bram , Goossens Martijn , Zieren Victor 
Published: December 2020

Abstract
The capabilities of photon emission microscopy with CCD and MCT camera systems for the 90 nm CMOS technology node were investigated. This was done with a dedicated test circuit with selectable shorts with resistance between 0 to 40 kΩ. Our investigations showed that conventional PEM with CCD systems is not possible anymore due to the reduction in photon emission intensity in the visible range. However, photon emission can be enhanced by using elevated supply voltages. For these overdrive conditions PEM with a CCD system is still feasible. We furthermore show that PEM is in principle capable of determining the state of a circuit and that PEM in combination with defect simulations can determine defect characteristics. In this manner, for example, the resistance of a short can be estimated by localising the PMOST emission spot.
Quantifying the Work of Adhesion Between an AFM Cantilever Tip and MEMS Test Structures After Packaging
Authors: Thoreson E. J. , Burnham N. A. , Martin J. 
Published: December 2020

Abstract
Adhesion is important to the yield and performance of MEMS (Micro-Electro-Mechanical Systems) and NEMS (Nano- Electro-Mechanical Systems). Measuring the work of adhesion, with an AFM (Atomic-Force Microscope), allows one to study surface interactions from an energy perspective as opposed to an adhesion (force) perspective. The works of adhesion were measured with different AFM tip radii on multiple types of samples. Two sample variables were examined: four die attach conditions (no attachment, silicone, polyimide silicone, and silver glass), and two surface conditions (native oxide with and without a few angstroms of vapor-deposited diphenyl siloxane). For a normal silicon cantilever, the work of adhesion seems to be slightly less for the treated surfaces than the untreated, except for the silverglass die attach material. There were at least three orders of magnitude difference in the works of adhesion for the different AFM tip radii. Presumably, the trend is due to some combination of material properties, interfacial roughness, and torque on the AFM cantilever.
Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint
Authors: Armendariz Norman J. , Paulraj Prawin 
Published: December 2020

Abstract
The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.
A Methodology for Characterizing System-Level ESD Sensitivity
Authors: Chagny Marie-Pascale , Naoum John A. 
Published: December 2020

Abstract
Over the years, failures induced by an electrostatic discharge (ESD) have become a major concern for semiconductor manufacturers and electronic equipment makers. The ESD events that cause destructive failures have been studied extensively [1, 2]. However, not all ESD events cause permanent damage. Some events lead to recoverable failures that disrupt system functionality only temporarily (e.g. reboot, lockup, and loss of data). These recoverable failures are not as well understood as the ones causing permanent damage and tend to be ignored in the ESD literature [3, 4]. This paper analyzes and characterizes how these recoverable failures affect computer systems. An experimental methodology is developed to characterize the sensitivity of motherboards to ESD by simulating the systemlevel ESD events induced by computer users. The manuscript presents a case study where this methodology was used to evaluate the robustness of desktop computers to ESD. The method helped isolate several weak nets contributing to the failures and identified a design improvement. The result was that the robustness of the systems improved by a factor of 2.
A Study of Power Plane Shapes, Their Contribution to Inter-Planar Electric Field Intensities, and Pre-Preg Breakdown
Authors: Kuriakose Eldho V. , Birdsley Jeff , Naoum John A. 
Published: December 2020

Abstract
The presence of sharp, “pointed” features on Printed Circuit Board (PCB) power planes and their contribution to increased plane-to-plane electric fields is studied as a potential root cause for PCB level dielectric breakdown. The results of this study are used to gauge the propensity for heat generation due to current leakage through pre-preg. A first order approximation for the E-field between a power and ground plane is Ê = V/d (1) where Ê is the electric field, V is the potential across the planes, and d is the separation between the planes. While this first order approximation is correct for infinite parallel planes, simulations show that second and third order effects that exist on real boards can multiply the effective Ê by more than 100x. The second order effects are primarily dependent on the local sharpness of planar shapes, and plane-to-plane separation. This amplified Efield could potentially breakdown pre-preg locally and initiate current leakage. Leakage through prepreg can grow over time as a leakage path becomes established and can wreak havoc with power rails or create a local ohmic conduction path that can lead to board level failures. A test platform and a series of experiments were developed to understand and quantify the various parameters that contribute to these failures. Tests revealed that given an ambient temperature of 70C, the presence of pointed features in planes reduces the breakdown voltage by at least 75%. It is suspected that under the right conditions, a breakdown will occur on a sharp shape if given sufficient duration of exposure to even low voltages.
In-Situ Sample Preparation and High-Resolution SEM-STEM Analysis
Authors: Young Richard J. , Bernas Michael P. , Moore Mary V. , Wang Young-Chung , Jordan Jay P. , Schampers Ruud , van Hees Ian 
Published: December 2020

Abstract
The dual-beam system, which combines a high-resolution scanning electron microscope (SEM) with a focused ion beam (FIB), allows sample preparation, imaging, and analysis to be accomplished in a single tool. This paper discusses how scanning transmission electron microscopy (STEM) with the electron beam enhances the analysis capabilities of the dualbeam. In particular, it shows how, using the combination of in-situ sample preparation and integrated SEM-STEM imaging, more failure analysis and characterization problems can be solved in the dual-beam without needing to use the Ångstrom-level capabilities of the transmission electron microscope (TEM).
Characterization of Interconnect Defects Using Scanning Thermal Conductivity Microscopy
Authors: Ho H.W. , Phang J.C.H. , Altes A. , Balk L.J. 
Published: December 2020

Abstract
In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.