bluuebunny/crossref_metadata_2025_split huggingface dataset:
(Invited) Etching of Advanced Semiconductor Devices
Authors: Lill Thorsten 
Published: February 2020

Plasma etching or Reactive Ion Etching (RIE) is the workhorse for patterning of semiconductor devices since the early 1980-ies when it replaced wet etching in manufacturing. Today, RIE is reaching levels of performance which were unimaginable back then. At the same time, etching technologies such as Atomic Layer Etching (ALE), radical, dry vapor and Ion Beam Etching are finding their way into manufacturing for certain applications.
We will present an overview of dry etching technologies used in semiconductor manufacturing. The emphasis is on the elementary surface processes and how they impact the performance on the wafer. We will start from less complex etching technologies which use just one kind of etching species, such as neutrals, radicals or ions. Then we combine these techniques into cycling processes which leads to the discussion of ALE. The highest level of complexity is reached in RIE with simultaneous species fluxes. Reactor designs for the various etching technologies and process control will be covered. Finally, and an outlook into the future of semiconductor device etching will be given.
New Process Concepts Towards Area-Selective Atomic Layer Deposition and Atomic Layer Etching of Zinc Oxide
Authors: Mameli Alfredo , Verheijen Marcel A. , Karasulu Bora , Mackus Adriaan J.M. , Kessels W.M.M. , Roozeboom Fred 
Published: February 2020

Area-Selective Atomic Layer Deposition, AS-ALD, can be initiated by local area-activation1,2 or -deactivation.3 We studied the maskless growth of ZnO from diethyl zinc and water. The method is based on the different nucleation delays that arise from precursor adsorption on OH-terminated versus that on H-terminated Si-substrate.
TEOS (tetraethyl orthosilicate) and H2O were used to deposit a SiO2 seed layer by EBID (e-beam-induced deposition) in a pattern of 500x500 nm2 dots on H-terminated a-Si:H substrate. After this local activation the substrate was coated with a ZnO film in a conventional ALD reactor using 80 cycles of diethyl zinc and water vapor. In situ spectroscopic ellipsometry (Fig. 1), SEM, cross-sectional TEM and energy dispersive X-ray spectroscopy (EDX) showed good areal selectivity with ZnO growth only occurring on the SiO2 dots. This observation was corroborated by Density functional theory calculations suggesting a kinetically hindered surface reaction between diethyl zinc and H-terminated Si.
Atomic Layer Etching, ALE, was also tested on a ZnO case. Current ALE technology is emerging in both thermal, isotropic and plasma-based, anisotropic approaches.4 In this presentation we will demonstrate a plasma-assisted ALE-process driven by radicals, and therefore being isotropic.
The ALE-process was tested at temperatures between 150 and 250 °C. We used alternating doses of acetylacetone (Hacac) and O2-plasma intermitted by Ar-purging. The ZnO-layer thickness as measured by spectroscopic ellipsometry decreased linearly with the number of cycles. In a synergy test, we proved that only the alternated dosing of Hacac and O2-plasma caused ZnO etching, whereas Hacac and O2-plasma alone did not (Fig. 2). Preliminary infrared studies suggest that Hacac forms volatile complexes by metal oxide surface chelation (e.g. Zn(acac)2), whereas the O2-plasma step removes non-reactive Hacac fragments to refresh the surface for the next etching cycle.5

TEM- and XPS-inspection indicated no damage of the ZnO surface, good preservation of the ZnO-stoichiometry throughout the etching process, and no distinct contamination. Furthermore, we demonstrated this ALE-process to be selective over SiO2. We believe that this novel plasma-assisted ALE-concept can be extended to several other materials.
[1] A. J. M. Mackus et al., Nanoscale, 4, 4477 (2012).
[2] R. Chen et al.,
Adv. Mater., 18, 1086 (2006).
[3] A. Mameli et al., Chem. Mater.
29, 921 (2017).
[4] D. R. Zywotko, et al., Chem. Mater.
29, 1183 (2017).
[5] M. A. George, et al.,
J. Electrochem.
Soc.,
143, 3257 (1996).

Figure 1
(Invited) Strain-Engineered Low-Threshold Group IV Lasers for Photonic-Integrated Circuits
Authors: Jung Yongduck , Luo Manlin , Qi Zhipeng , Sun Hao , Nam Donguk 
Published: February 2020

Photonic-integrated circuits (PICs) are a key enabler for the ultimate miniaturization of next-generation optical computers that can fit in the palm of your hand. However, the realization of fully functional PICs is currently limited by the absence of an efficient light source on silicon (Si), thus making a practical Si-compatible light source the Holy Grail. Especially, it has been thus far considered close to impossible to create a practical on-chip laser using Si-compatible group IV semiconductor materials (e.g. germanium (Ge)) owing to their indirect bandgap nature. Strain-engineered Ge material has recently garnered much attention for the dramatic reduction of the lasing threshold of group IV lasers because large tensile strain fundamentally alters the Ge’s bandstructure.
Here, we present our recent research works on highly strained group IV materials on a Si chip for the realization of low-threshold on-chip lasers. In the first part, we will introduce our innovative strain engineering platforms that can create direct bandgap Ge nanowires by inducing >5% elastic tensile strain. In the second part, we will present the first experimental observation of low-threshold optically pumped lasing in highly strained Ge nanowires. The strain engineering of direct bandgap germanium-tin will also be described for the ultimate reduction of the lasing threshold.
(Invited) The Scaling-Down and Performance Optimization of InAs Nanowire Field Effect Transistors
Authors: Chen Qing , Yang Wenyuan 
Published: February 2020

The excess OFF-state current caused by band to band tunneling (BTBT) is a serious issue for short channel nanowire (NW) field-effect transistors (FETs), especially for semiconductors with narrow bandgap such as InAs. To suppress the OFF-state current and find way to improve the properties of short channel NW FETs based on semiconductors with narrow bandgap, we for the first time fabricate and study InAs NW FETs with nanoscale partial-gate (PG).
While compared with full-gate (FG) FET fabricated on the same NW, PGFET shows better OFF-state characteristics. Through studying the devices with different length of PG, different measurement conditions and fabrication processes, we find the excess OFF-state leakage current is mainly induced by the BTBT caused by the high-field at the drain-end of the channel, which can be obviously suppressed by the ungated region of PGFET. Through statistic study, we find BTBT effect can be more serious in the devices with better gate-control.
(Invited) Development of Si-Based Sigesn Technique Towards Short-Wave and Mid-Infrared Applications
Authors: Yu Shui-Qing , Du Wei , Ghetmiri Seyed Amir , Mosleh Aboozer , Margetis Joe , Tolle John , Liu Jifeng , Mortazavi Mansour , Sun Greg , Soref Richard , Li Baohua 
Published: February 2020

Silicon-based emitters and detectors have long been desired owing to the possibility of monolithic integration of photonics with high-speed Si electronics and the aspiration of broadening the reach of Si technology by expanding its functionalities well beyond electronics. To overcome the intrinsic problem of bandgap indirectness in the group-IV semiconductors of Si, Ge, and SiGe alloys, a new group-IV material platform Silicon-Germanium-tin alloy (SiGeSn) has been investigated, which features: 1) the industry scalable growth; 2) compatible with current Si complementary metal-oxide semiconductor (CMOS) process; 3) capability of monolithic integration on Si; 4) the identified group-IV based direct bandgap materials; and 5) the tunable bandgap allowing the optoelectronic devices operation covers broad wavelength in near- and mid-infrared ranges. For the past decade, plenty of promising results have been reported, such as GeSn lasers based on direct bandgap GeSn alloys, GeSn light emitting diodes (LEDs) and detectors operating in 2~3 µm. With tremendous novel electrical, optical, and mechanical properties, the newly developed GeSn devices could dramatically change the landscape of future microelectronics and photonics.
In this work, the following aspects have been reported: 1) The material growth of SiGeSn by commercially available reduced pressure chemical vapor deposition (CVD) system. The maximum Sn composition of 22% was achieved; 2) The demonstration of GeSn optically pumped laser. The lasing coverage from 2 to 3 μm was achieved at Sn composition ranging from 8.0 to 22%; 3) The investigation of GeSn-based PIN photodiodes, based on which the light emitting diodes (LEDs) and photodetectors were characterized. The specific detectivity (D*) of GeSn detector is only one order of magnitude lower than current market dominating detectors that are made from III-V materials.
Fabrication of Homogeneous Ultra-Thin Sige-on-Insulator Layer for Thermoelectric Applications
Authors: Goyal Chandra Prakash , Omprakash M. , Mutoh K. , Nishino S. , Matsuki T. , Navaneethan M. , Watanabe Takanobu , Shimura Y. , Takeuchi T. , Ponnusamy S. , Hayakawa Y. , Ikeda H. 
Published: February 2020

SiGe nanostructures has attracted much attention in recent years in order to realize high-efficient thermoelectric devices due to carrier confinement effect and alloying effect [1,2]. For this purpose, in the present study, we fabricated a compositionally-homogeneous thin SGOI (SiGe on insulator) substrate by simple sputtering and physical evaporation techniques and characterized its crystallographic properties and thermal conductivity. A 30-nm-thick Si layer was sputtered on a thermally-oxidized Si wafer (SiO2 thickness: 103 nm), followed by the deposition of a thin Ge film with a thickness of 30 nm, at room temperature. Afterwards, Si-Ge diffusion was carried out by a rapid thermal annealing process at 880oC for 10 and 120 min. The prepared SGOI substrates were characterized by means of XRD, SEM, EPMA, Raman spectroscopy, XPS, and AFM, which showed the formation of a compositionally-homogeneous poly-crystalline Si1-xGex layer with x=0.45 (thickness: 60 nm). The thermal conductivity was determined by a picosecond time-domain thermoreflectance (TDTR) method at room temperature and shown in the figure, as a function of annealing time. For a reference, the measured values of our as-deposited Ge/Si layer and a commercial single-crystalline SGOI substrate (x=0.5) are also plotted. It is found that our poly-crystalline SGOI layer has lower thermal conductivity of 0.87 W/mK, compared with that of a single-crystalline SGOI 1.43 W/mK.
[1] H. Kim, I. Kim, H.-J. Choi, and W. Kim, Appl. Phys. Lett., 96 (2010) 233106.
[2] R. Basu, S. Bhattacharya, R. Bhatt, M. Roy, S. Ahmad, A. Singh, M. Navaneethan, Y. Hayakawa, D. K. Aswal, and S. K. Gupta, J. Mater. Chem. A, 2 (2014) 6922.

Figure 1
In-Plane Solid-Liquid-Solid Growth and Engineering of Si and Si/Ge Nanowires for Integratable High Performance Fin-like Thin Film Transistors
Authors: Yu Linwei 
Published: February 2020

Self-assembly growth of quasi-1D nanowires (NWs) has been a popular, high yield and low cost technology to fabricate ideal semiconducting channels for fin-like field effect transistors or thin film transistors (TFTs). However, a technical challenge to implementing this approach for large scale electronic applications arises from the fundamental difficulty in collecting and positioning these tiny 1D building blocks into precise locations for convenient electric connection and integration. This is particularly true when the SiNWs were grown with gas-feeding vapor-liquid-solid (VLS) approach, where the as-produced SiNWs are typically standing ones on substrate, and thus require further delicate manipulations to arrange them on planar architecture. Fortunately, this challenge can be addressed by adopting a self-assembly in-plane solid-liquid-solid (IPSLS) growth of Si nanowires (SiNWs), where a thin film of amorphous Si (a-Si) is fed as precursor layer to drive the indium (In) or tin (Sn) nano-droplets to move and produce well-defined crystalline SiNWs behind.[1] Remarkably, a precise control of the location, the growth routine and the geometry of the SiNW channels can be accomplished via a simple low temperature (<350 oC) process in conventional plasma enhanced chemical vapor deposition (PECVD) system. We will first demonstrate a reliable batch-manufacturing of parallel SiNW arrays upon glass substrates, which can serve as high mobility channels in fin-like thin film transistors (Fin-TFTs) for large area display application. Specifically, the SiNWs Fin-FETs achieve a high hole mobility of >150 cm2V–1s–1, on/off ratio >106 and excellent subthreshold swing of 120 mV/dec. In addition, the tiny SiNWs, of ~60 nm in diameter and 2 μm apart grown on glass substrate, are transparent to visible light.[2] Furthermore, we will show that the geometry degree of freedom can also be programmed during the in-plane growth of SiNWs.[3,4,5] Finally, an alloy mixture or amorphous bilayer feeding control will be presented, which can help to achieve a self-automated phase-separation and diameter modulation in a unique Si/Ge superlattice nanowire structure. There results could indicate a promising strategy to tailor the Si or SiGe nanowires for high perfomance large area electronics.

References

[1] L. Yu, et al., Phys. Rev. Lett. 102, 125501 (2009).
[2] M. Xu et al., Nanoscale 9, 10350 (2017).
[3] Z. Xue et al., Adv. Func. Mater. 26, 5352 (2016).
[4] Z. Xue et al., Nature commun. 7, 12836 (2016).
[5] Z. Xue et al., Nano Lett. 17, 7638 (2017)
HfO2/Al2O3 Nanolaminate on Si0.7Ge0.3(100) Surface by Thermal Atomic Layer Deposition
Authors: Kwak Iljo , Kavrik Mahmut , Thomson Emily , Liang Yu-Chia , Ueda Scott T , Tang Kechao , Hou Vincent , Lee Chung-Yang , Aoki Toshihiro , Kim Moon , Fruhberger Bernd , Taur Yuan , McIntyre Paul C. , Kummel Andrew C 
Published: February 2020

Silicon germanium (SiGe) channels for CMOS are favorable due to high intrinsic carrier mobility and band gap tunability[1] To utilize the superior properties of SiGe, low interface defect density (Dit) must be obtained at the SiGe-high k interface. Germanium oxide (GeOx) is the primary source of interface defects[2]. In comparison with GeOx, SiOx has a higher heat of formation. Using this difference, it is possible to reduce interface defects with selective reduction or diffusion of GeOx by employing an oxygen-scavenging metal as a gate material[4,5] such as aluminum. ALD was performed with TDMAH and H2O to grow 50 cycles (5nm) of HfO2 at 250C. 50 nm thick, 150 um diameter Ni or Al gate metal was deposited by thermal evaporation. C-V measurement were employed to characterized the electronic defects. The interface trap density (Dit) integrated across the band gap was more than an order of magnitude lower for Al vs Ni gated MOSCAPs. From TEM-EELS-EDS measurement, Al gated MOSCAPs were observed to have a very thin interfacial oxide layer (<0.5 nm) with high-k oxide atoms almost directly bonded with the SiGe surface atoms with just a thin SiOx interlyer. Selective scavenging of Ge-O vs Si-O bonds is consistent with a DFT model showing HfO2/SiOx/SiGe interfaces can be defect-free. DFT models also show that two 3- and 5-fold coordinated interfacial Si atoms do not create any mid-gap or band-edge states. These results indicate the need to form a SiOx interface between HfO2 and SiGe, but the same interface may be created with other techniques. The alternative techniques include a selective oxidation of SiGe form SIOx using remote O3 oxidation and ALD of an Si rich layer on SiGe. The key issue is which of the three techniques is manufacturable and can produce both a scale oxide and scaled interlayer.
[1] Liu, C. et. al, MRS Bull. 39, 658–662 (2014).
[2] Zhang, L. et al, ACS Appl. Mater. Interfaces 8, 19110–19118 (2016).
[3] Zhang, L. et al, ACS Appl. Mater. Interfaces 7, 20499–20506 (2015).
[4] Kim, H. et al, J. Appl. Phys. 96, 3467–3472 (2004).
[5] Frank, M. et al, ECS Solid State Lett. 2, N8–N10 (2012).
[6] Sardashti, K. et al. Appl. Surf. Sci. 366, 455–463 (2016)
(Invited) Heterogeneous Liquid Metal Particle Composites for Thermal Interface Materials
Authors: Wang Robert Y. 
Published: February 2020

Thermal interface materials (TIMs) improve thermal transport away from computer chips by filling micro air gaps between the rough surfaces of adjacent components (e.g., between the computer chip and heat spreader). TIMs typically consist of a polymer or grease with solid particle additives that have high thermal conductivity such as diamond, silver, aluminum nitride, etc. Despite these efforts, TIM conductivities are still usually below 2 W m-1 K-1 because the small point-like contacts between solid filler particles lead to large thermal contact resistances that bottleneck thermal transport.
I present my group’s ongoing work to use heterogeneous liquid metal (LM) particles to overcome thermal transport bottlenecks in polymer composites. The central premise behind this effort is that LM-coated particles will have enlarged particle-particle contact regions relative to the point-like contacts between non-coated particles. In effect, the LM functions as a thermally conductive “solder” between particles.
I first present our work on Cu particles coated in LM (eutectic Ga-In-Sn). Using these particles, we achieve effective thermal conductivities up to ~ 10 W m-1 K-1 under certain circumstances. This Cu-LM system also benefits from a room-temperature reaction between the Cu and LM. Cu-LM mixtures initially start as a slurry and can be processed accordingly. However, this slurry transforms into a conductive solid within a practical time frame (e.g., tens of minutes). During this process, Ga leaches out of the LM and reacts with the Cu to form CuGa2. This also shifts the LM away from its eutectic Ga-In-Sn composition and the LM itself solidifies. In this sense, the LM can be viewed as a solder that is molten at room temperature, but then solidifies via chemical reaction (as opposed to freezing). Another important byproduct of this reaction is that it sequesters the Ga and prevents Ga-induced corrosion of neighboring components.
I next present our ongoing efforts to develop LM-coated Al and LM-coated W particles. These metals have low reduction potentials, which creates opportunities to transform their surface for LM-coatings via galvanic replacement reactions. Additionally, I present our modeling concepts for LM-coated heterogenous nanowires that can enable TIMs that are simultaneously thermally conductive and electrically insulating.
Impact of Ni Content on the Thermoelectric Properties of Half-Heusler Thermoelectrics
Authors: Tang Yinglu , Landmann Daniel , Battaglia Corsin 
Published: February 2020

Motivated by high peak zT values reported 13 years ago for the (Ti,Zr,Hf)NiSn Half-Heusler system, Half-Heusler materials are identified as a promising materials class for thermoelectric applications. We investigate the TiNiSn sub-system, which does not rely on expensive Hf. From phase boundary mapping, we find that the thermoelectric TiNiSn Half-Heusler phase shows a narrow solubility range on the Ti-Ni-Sn phase diagram primarily in the range of excess Ni that can be approximated as TiNi1+xSn, where x is temperature dependent with 0 ≤ x ≤ 0.06 at 1223 K. Four phase boundary compositions with different Ni contents associated with four three-phase regions are identified. We characterize the thermoelectric properties of these stable compositions and find significant difference between Ni-rich and Ni-poor phase boundary compositions of TiNiSn, which amounts up to 41%, 58%, and 25% difference in Seebeck coefficient, lattice thermal conductivity, and thermoelectric figure of merit respectively. This explains the large discrepancy of literature data on the thermoelectric properties of TiNiSn within a unified phase diagram framework. We demonstrate that Ni-rich TiNiSn results in a narrower band gap using the Goldsmid formula, which we interpret to be due to the formation of an impurity band from interstitial Ni in the forbidden gap as previously suggested. Interstitial Ni atoms scatter both electrons and phonons, with the latter effect being much stronger, thus a lower lattice thermal conductivity compensates the decrease in electron mobility leading to a high zT value of 0.6 at 850 K for intrinsic Ni-rich TiNiSn. With Sb doping, the carrier concentration in these stable boundary compositions can be tuned but the distinct features in their transport properties remain unchanged. A maximum zT value of 0.6 was also achieved at 850 K for intrinsic Ni-poor TiNiSn upon Sb doping. We further present results on the integration of n-type TiNiSn Half-Heusler material into 36-legs modules in conjunction with p-type FeTiNb Half-Heusler material including their multi-physics modelling-assisted matching and integration into a heat exchanger mounted and tested in the exhaust gas system of a compact van.
Y. Tang, X. Li, L.H.J. Martin, E. Cuervo Reyes, T. Ivas, C. Leinenbach, S. Anand, M. Peters, G.J. Snyder, C. Battaglia, Energy & Environmental Science, 2018, 11, 311
D. Landmann, Y. Tang, D. Widner, R. Huber, P. Rickhaus, R. Widmer, C. Battaglia, in preparation
Electrodeposition in Supercritical Fluids
Authors: Black Alex , Bartlett Philip N. , Cook David Andrew , Reid Gill , Zhang Wenjian , Smith David Christopher , Alibouri Mehrdad 
Published: February 2020

Supercritical fluids possess several characteristics which make them interesting for electrodeposition. Supercritical fluids have low viscosity, allowing fast mass transport and therefore rapid deposition. Additionally, adjusting the pressure and temperature influences the density and viscosity of the solvent, therefore allowing tuning of the solvent properties1 2. Low surface tension and phase separation also allows penetration of electrolyte into porous templates, meaning high aspect ratio nanowires can be deposited, with reported diameters as low as 3 nm3. This is a capability pertinent to the manufacture of the next generation of p-block based electronic devices, such as thermoelectric or phase change memory materials. As the current fabrication methods begin to reach their limits of size and control capabilities, extracting the maximum potential from these materials requires a new approach.
Where possible, aqueous conditions remain the most popular for electrodeposition, however its small cathodic limit can put refractory metals out of reach. Supercritical difluoromethane (scR32) is a promising solvent for supercritical electrodeposition. It has a large cathodic limit (-2 V), and a high enough dielectric constant to provide reasonable conductivity, and coordinates poorly with reagents1. Electrodeposition from scR32 has yielded films and nanowires of several p-block metals, including Te, Bi, Sb and Ge4-6. Extending this capability to alloys and compounds is the next challenge.
We present an introduction into the practical aspects of electrochemistry in supercritical fluids, often a non-trivial task. We will also present preliminary results concerning electrodeposition from a bismuth and tellurium electrolyte. The films produced were of varying, controlled composition. Bismuth telluride is a thermoelectric material, with the highest known room temperature thermoelectric figure of merit7, and is currently the subject of significant research efforts. The combination of supercritical fluids and electrodeposition holds significant promise for the fabrication of nanostructured materials.
This work has been supported by the EPSRC Programme Grant, Advanced Devices by Electroplating (EP/N0354371/1). Work from the EPSRC Programme Grant EP/I013394/1 also contributed.

1 Abbott A. P., Eardley C. A., Tooth R., J. Chem. Eng. Data, 1999, 44, 112

2 Abbott A. P., Hope E. G., Palmer D. J., Anal. Chem., 2005, 77, 6702

3 Ke J. et al., Phys. Chem. Chem. Phys., 2012, 14, 1517

4 Bartlett P. N. et al., Phys. Chem. Chem. Phys., 2014, 16, 9202

5 Bartlett P. N. et al., Chem. Eur. J, 2016, 22, 309

6 Bartlett P. N. et al., RSC Adv., 2017, 7, 40720

7 Rosi F., Abeles B., Jensen R., J. Phys. Chem. Solids, 1959, 10, 191

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