bluuebunny/crossref_metadata_2025_split huggingface dataset:
Sample Preparation and Preservation for TEM Analysis of Copper Interconnect Integrated Circuit
Authors: Gao Qiang , Zhang Mark , Li Ming , Niou Chorng , Kary Chien W.T. 
Published: December 2020

Abstract
This paper examines copper-interconnect integrated circuit transmission electron microscope (TEM) sample contamination. It investigates the deterioration of the sample during ion milling and storage and introduces prevention techniques. The paper discusses copper grain agglomeration issues barrier/seed step coverage checking. The high temperature needed for epoxy solidifying was found to be harmful to sidewall coverage checking of seed. Single beam modulation using a glass dummy can efficiently prevent contamination of the area of interest in a TEM sample during ion milling. Adoption of special low-temperature cure epoxy resin can greatly reduce thermal exposure of the sample and prevent severe agglomeration of copper seed on via sidewall. TEM samples containing copper will deteriorate when stored in ordinary driers and sulphur contamination was found at the deteriorated point on the sample. Isolation of the sample from the ambient atmosphere has been verified to be very effective in protecting the TEM sample from deterioration.
Analysis and Identification of Off-Odor Compounds in Electronic Systems
Authors: Nailos Mary Ann , Stein Dan , Nielsen Lawrence T. , Iwasinska Anna 
Published: December 2020

Abstract
The detection and identification of substances that give rise to aromas and off-odors is often a difficult task. Perception of odors is very subjective and odor detection thresholds vary from person to person. The identification of trace levels of compounds responsible for perceived odors is difficult using conventional analytical tools. This paper will focus on a novel method for sampling and analyzing aromatic volatile compounds using an analytical system specifically designed for odor analysis.
Using a Unified Data Stream to Drive Failure Analysis for Product Improvement in the Personal Computer (PC) Environment
Authors: Horley Shirleen , Rascon Joseph 
Published: December 2020

Abstract
The longer defective units are in the manufacturing pipeline before they are detected, the more expensive it becomes. Economic pressures drive the requirement to capture failures and perform root cause analysis further upstream in the product manufacturing cycle. This places greater emphasis on the ability to identify failures and perform value add analysis to drive product improvements as early as possible. This paper describes the method used to develop a reliable Unified Data Stream (UDS) that feeds the failure analysis process which in turn provides actionable information to product development teams in the Personal Computer (PC) environment. This manuscript describes the development and implementation of the Unified Data Stream designed to replace ambiguity and uncertainty with a defect trend and symptom pareto that drives action upstream. Focus will be on the output of UDS enabling the prioritization of product defects that feed the failure analysis system. Additionally, this paper will touch on the application of the UDS system for different types of pc components. The future of UDS is without bounds as it can also be applied to a wide range of products.
Fundamental Considerations for CDM Failure in 90nm Products
Authors: Wakai Nobuyuki , Kobira Yuji , Egawa Hidemitsu , Tsutsumi Masayoshi 
Published: December 2020

Abstract
Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.
Surface Defect Analysis by Using a Novel Backside XTEM Sample Preparation Method
Authors: Luo Jian-Shing , Huang Lang-Yu , Gu Wen-Lon , Russell Jeremy D. 
Published: December 2020

Abstract
This paper demonstrates a novel method of XTEM sample preparation for site-specific surface defect analysis using backside polishing. Analysis of three different types of site-specific surface defects was demonstrated using a novel backside XTEM sample preparation method. The details of the backside XTEM sample preparation method and some examples are reported in this paper. Comparing to Auger electron spectrometry (AES) results on similar defects, more detailed and precise information is observed using TEM analysis with this method. It is therefore a complementary technique to traditional AES analysis on surface defects for contamination with atomic level concentration. From the results, the sample preparation method can produce a clean, pristine surface that is well characterized and could be reproduced, successfully.
Deformation Study of Low K Dielectric after E-beam Exposure
Authors: Chen Xianfeng , Gao Qiang , Li Ming , Niou Chorng , Kary Chien W.T. 
Published: December 2020

Abstract
In this paper, the deformation mechanism of low K dielectric film under electron beams (E-beams) is discussed, and the effect of film deformation on the development of a low K dielectric film etching recipe is investigated. To provide meaningful data for process development, numerical analysis was used in the failure analysis procedure. A correction factor is formulated to calculate the change in thickness of the low K dielectric film after E-beam exposure. In addition, scanning electron microscope (SEM) settings for imaging low K dielectric films are optimized to minimize deformation.
New Approach—Sample Preparation Techniques for Plastic Small Outline Package (Frontside and Backside)
Authors: Marquez Erwin , Nguyen Dat 
Published: December 2020

Abstract
As device packages become smaller, the job of failure analysts becomes more difficult. Other complex configurations such as Small Outline Packages (SOP) pose unique problems. The difficulty of removing the encapsulant while preserving the integrity of the die, bond pads, bond wires and lead frame interconnects on a small outline package pose a serious problem. A new sample preparation technique is offered in order to expose the front side and backside of the die. This technique dramatically reduced the risk of damage and ensures the functionality of the device after decapsulation.
Fault Identification by Use of a Simulated Passive Voltage Contrast Reference CAD Display
Authors: Fredrickson R. 
Published: December 2020

Abstract
Passive voltage contrast (PVC) is a phenomenon seen while inspecting a semiconductor device where imaged circuit features have a different value of contrast depending on whether that feature has an electrical path to ground, another circuit element, or has an open connection. A common method of fault isolation during failure analysis is to use these contrast values to determine if a feature is incorrectly connected indicating a defect is present. This paper discusses a fault identification method by creating a simulated PVC reference that can be displayed next to the scanning electron microscope PVC image for a comparison of the expected PVC. The procedure of how to create the PVC reference is discussed using functions found in tools typically used to run a Design Rules Check in commonly available software. Three examples are given of how this methodology could be used to provide further analysis capabilities during fault isolation.
Functional IC Analysis Through Chip Backside with Nano Scale Resolution—E-Beam Probing in FIB Trenches to STI Level
Authors: Schlangen R. , Leihkauf R. , Kerst U. , Boit C. , Krüger B. 
Published: December 2020

Abstract
One method of dynamic probing in modern integrated circuits (ICs) is performed through the backside of the device. The established techniques are limited in lateral resolution because they use infrared (IR) light. This paper demonstrates how state of the art FIB circuit edit (CE) processes enable the application of E-Beam probing through chip backside on current and future IC technologies with low risk of device performance degradation.
Use of a Solid Immersion Lens for Thermal IR Imaging
Authors: Breitenstein O. , Altmann F. , Riediger T. , Karg D. , Gottschalk V. 
Published: December 2020

Abstract
A hemispherical silicon solid immersion lens (SIL) was used to improve the spatial resolution of front-side thermal IR imaging in lock-in mode. The bottom of the SIL was coneshaped to reduce the footprint of the SIL to the size of the imaged region. Caused by the lock-in operation mode, the detection limit improves by 2-3 orders of magnitude, and scattered light does not limit the image contrast. By using this SIL in combination with an IR camera working in the 3-5 μm wavelength range, a spatial resolution of 1.4 μm was obtained for thermal IR imaging. An automatic SIL positioning facility was constructed to place the SIL exactly in the center of the imaged region and to easily remove it after the detailed investigation.
Planar Deprocessing of Advanced VLSI Devices
Authors: Wills Kendall Scott 
Published: December 2020

Abstract
Modern day VLSI Semiconductor devices are manufactured using a chemical mechanical polish (CMP) process. The resultant layers are planar with respect to one another and should be easy to remove. All that needs to be done is to lap the layer until the region of interest is exposed. In practice this has been difficult. This article describes the combination of processes that are required to take full advantage of the strength of deprocessing techniques (lapping, plasma and gel controlled wet chemical deprocessing) to deliver a perfectly planar sample for inspection. A discussion on the thought process required to adequately select the proper chemicals for the gel controlled etch is given. Finally, a typical deprocessing flow is described. It is concluded that this combined solution enables planarity to be maintained across 100% of the device surface. There is less chance the failure site is damaged by the deprocessing.
Marginal Deviation of Thermal Budget Brings Shallow Junction Formation Failure Forth Study
Authors: Chuang Tsan-Cheng , Shen C.M. , Chou J.H. 
Published: December 2020

Abstract
Shallow junction formation in silicon chips is a hot topic in the semiconductor industry. Reduction of power consumption of integrated circuits and an increase of the device performance would drastically reduce the sizes of circuits and, therefore, would necessitate a similar reduction for the depth of the p-n junctions. This paper performed the flash lamp annealing process application, applied to the CMOS as alternative method to attain the goal of shallow junction in the case. A marginal thermal budget mismatch related failure mode was revealed and explained.
Metal Slice Defect Induced Package Level Reliability Failure
Authors: Zhang Mark , Liao Scott , Liang Sanan , Lou Ricky , Chen Rock , Niou Chorng , Kary Chien W.T. 
Published: December 2020

Abstract
In this paper, a case of package level reliability test failure was studied. A model of “Slice Defect”, which was identified as the root cause by failure analysis, is introduced. Experiment results are presented to approve that such model is in fact correct and the corrective actions are effective.
Effects of Backside Circuit Edit on Transistor Characteristics
Authors: Jain R.K. , Malik T. , Lundquist T.R. , Wang Q.S. , Schlangen R. , Kerst U. , Boit C. 
Published: December 2020

Abstract
Backside circuit edit techniques on integrated circuits (ICs) are becoming common due to increase number of metal layers and flip chip type packaging. However, a thorough study of the effects of these modifications has not been published. This in spite of the fact that the IC engineers have sometimes wondered about the effects of backside circuit edit on IC behavior. The IC industry was well aware that modifications can lead to an alteration of the intrinsic behavior of a circuit after a FIB edit [1]. However, because alterations can be controlled [2], they have not stopped the IC industry from using the FIB to successfully reconfigure ICs to produce working “silicon” to prove design and mask changes. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after various steps of modification.
Measuring Static Noise Margin of 65 nm Node SRAMs Using a 7-Point SEM Nanoprobing Technique
Authors: Stallcup Richard E. , Cross Zachary , James William , Ngo Phuc 
Published: December 2020

Abstract
Non-visual fails have become an ever present complication in the IC industry. Nano probing SRAM bit cells at the inverter level allows the cell to be tested and static noise margin (SNM) to be measured. This paper explains how nano probing of a 65nm technology 6 transistor bit cell was performed and SNM dependence on supply voltage was measured for both hold and read modes. Connection to the bit cell was made at the Metal 1 layer with 7 nano probes to collect the voltage transfer curves (VTCs) of the two inverters of the cell. In this experiment, each inverter was tested by varying Vdd voltage from 1.5, 1.2, 1.0, 0.8, 0.6, 0.4 and 0.2V while collecting the VTC. The two VTCs of the cell are plotted to produce the cell’s butterfly curve from which the SNM is found graphically for each setting of Vdd.
Comparison of Active and Passive Voltage Contrast for Failure Localization
Authors: Rosenkranz R. , Werner W. 
Published: December 2020

Abstract
In many cases of failure localization, passive voltage contrast (PVC) localization method does not work, because it is not possible to charge up conducting structures which supposed to be dark in the SEM and FIB images. The reason for this is leakage currents. In this article, the authors show how they succeeded in overcoming these difficulties by the application of the active voltage contrast (AVC) method as it was described as biased voltage contrast by Campbell and Soden. They identified three main cases where the PVC didn't work but where they succeeded in failure localization with the AVC method. This is illustrated with the use of two case studies. Compared to the optical beam based methods the resolution is much better so a single failing contact of e.g. 70 nm technology can clearly be identified which cannot be done by TIVA or OBIRCH.
Annular Illumination and Collection in Solid Immersion
Authors: Ippolito Stephen Bradley , Terada Hirotoshi 
Published: December 2020

Abstract
Tailoring the angular spectrum with annular illumination and collection can significantly improve integrated circuit analysis with an optical microscope, when combined with solid immersion. We present the development, testing, and optimization of a simple and compact apparatus to implement annular illumination and collection in a Hamamatsu iPHEMOS system. We demonstrated improved imaging of an IBM 45nm silicon-oninsulator circuit, with annular illumination and collection in confocal scanning optical microscopy and widefield microscopy with an InGaAs camera.
Backside IR Raman Temperature Measurements
Authors: Aaron Falk R. , Pham Tram , Albright Grant 
Published: December 2020

Abstract
Spatial resolution limitations of IR thermal microscopy also limit the temperature accuracy for small thermal sources. Use of Raman temperature measurements significantly improves spatial resolution and thereby temperature accuracy. Previous, visible-wavelength, Raman temperature measurements are limited to top side measurements in silicon. This paper describes the first ever IR Raman measurements in silicon and demonstrates its use for backside temperature measurements.
Methodologies for Quantifying FIB “Milling Acuity”
Authors: Rue Chad 
Published: December 2020

Abstract
FIB column performance can be difficult to evaluate, and the traditional metrics of imaging resolution and minimum spot size give little indication of how a FIB system will perform its intended daily tasks. A series of supplemental FIB performance tests is proposed to quantify “milling acuity” under real-world conditions. A quantitative measuring scheme for evaluating the quality of High Aspect Ratio (HAR) vias is proposed, and an example is shown in which the HAR measuring scheme can be used for process development.
Production Yield Enhancement through Failure Analysis Investigation
Authors: Medikonduri Rajesh 
Published: December 2020

Abstract
Production yield verification for a complex device, such as the flash memory, is a problem of primary importance due to high design density and current testing capabilities of such design. In this paper, the flow byte issue in the one time programmable block is investigated through physical failure analysis (PFA). The customer reported fail for this unit was flow byte error with flipped data loss in one of the bit. Various experiments were done on numerous units to identify the yield related issue and prevent shipment of such units to customers. The case study from this paper is beneficial to the FA community by showing the exact methodology in identifying the problem, its containment, and implementation of corrective actions on the ATE to prevent shipment of low yield units to customer. The yield was enhanced by implementing the containment and corrective actions on the ATE.
Case Study in Fault Isolation of a Metal Short for Yield Enhancement
Authors: Ipek Sarven , Grosjean David 
Published: December 2020

Abstract
The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.
Backside Infrared Imaging Using Improved Refraction-Assisted Illumination Methods
Authors: Yeoh Terence , LaLumondiere Stephen , Ives Neil , Leung Martin 
Published: December 2020

Abstract
Infrared backside imaging using refraction assisted illumination (RAIL) allows for imaging microelectronic devices at high contrast and resolution through 700 microns of silicon without the need for specialized optics or coatings. However, due to the angle of illumination, not all of the metal features are equally illuminated. In this paper we present improvements on this method through image composition of a series of RAIL images taken at various illumination directions. The resultant composited image provides more uniform illumination and better approximates the features seen in scanning laser confocal microscopy.
Counterfeit Parts Recognition and Detection for Failure Analysts
Authors: Whittington Katherine V. 
Published: December 2020

Abstract
The electronics supply chain is being increasingly infiltrated by non-authentic, counterfeit electronic parts, whose use poses a great risk to the integrity and quality of critical hardware. There is a wide range of counterfeit parts such as leads and body molds. The failure analyst has many tools that can be used to investigate counterfeit parts. The key is to follow an investigative path that makes sense for each scenario. External visual inspection is called for whenever the source of supply is questionable. Other methods include use of solvents, 3D measurement, X-ray fluorescence, C-mode scanning acoustic microscopy, thermal cycle testing, burn-in technique, and electrical testing. Awareness, vigilance, and effective investigations are the best defense against the threat of counterfeit parts.
Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology
Authors: Dickson K. , Lange G. , Erington K. , Ybarra J. 
Published: December 2020

Abstract
This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.
A Position-Sensitive, Single-Photon Detector with Enhanced NIR Response
Authors: Stellari Franco , Song Peilin , Weger Alan J. , Nakamura Tomonori , Kim Stanley , Roche Robert 
Published: December 2020

Abstract
In this paper, we evaluate a novel, position-sensitive, singlephoton detector with enhanced Near InfraRed (NIR) sensitivity [1-3] for taking 2D Time Resolved Emission (TRE), also known as Picosecond Imaging for Circuit Analysis (PICA), in future low voltage SOI technologies. In particular, we will investigate and quantify the sensitivity of two generations (Gen. I and Gen. II) of PICA cameras by Hamamatsu Photonics as a function of the power supply voltage on an IBM 45 nm SOI test chip. Additionally, we will compare the results to the performance obtained with an InGaAs Single Photon Avalanche Diode (SPAD) from DCG Systems [4]. Finally we will show a case study and an advanced analysis and localization technique that takes advantage of the 2D capability of the camera.
Transmission Electron Microscopy Characterization of FinFET – Understanding the 3D Structure by 2D Imaging Technique
Authors: Zhu Yu , Gonsalves Jemima 
Published: December 2020

Abstract
For 22nm technology node and beyond, fully depleted devices such as FinFET and ETSOI are leading candidates. Certain critical dimensions of such devices are well below 10nm, and only transmission electron microscopy (TEM) has the resolution to provide measurement with sub-nanometer accuracy. Due to the projection effect of TEM technique, comprehensive understanding of the 3D structure from 2D images is needed for process development of FinFET. This paper will address sample preparations and TEM imaging techniques for FinFET device at sub-100nm pitch.
A Sample Preparation Technique to Localize Gate Oxide Defects in Memory Arrays Using Conducting Atomic Force Microscopy
Authors: Lakshmanan Lakshminarayanan , Herlinger Lowell , Miller Kathryn 
Published: December 2020

Abstract
Shrinking gate lengths have led to increased challenges in isolating defects using conventional physical failure analysis methods. Conducting atomic force microscopy (CAFM) has been proven to be a powerful tool to isolate gate oxide defects in silicon-on-insulator devices. Some sample preparation techniques of exposing polysilicon and gate oxide, which were critical to perform CAFM scan, are discussed in this paper.