bluuebunny/crossref_metadata_2025_split huggingface dataset:
Using Electrical Fault Isolation and Characterization to Improve the Effectiveness of Physical Fault Isolation Techniques for Analog Circuits
Authors: Douglass Jim , Pourmand Sohrab 
Published: December 2020

Abstract
This paper shows that by combining electrical fault isolation and characterization by microprobing with physical fault isolation techniques both what is wrong with the circuit and where the defect is located can be determined with less microprobing and more safety from electrical recovery. In the first example, the unit was powered up using the optical beam induced resistance change (OBIRCH) supply, and OBIRCH was performed to determine if there were OBIRCH site differences between the good part and the return. The second example uses a combination of electrical fault isolation and characterization with microprobing and the physical fault isolation tool of lock in thermography (LIT). With these two examples, it has been shown that the use of electrical fault isolation and microprobing can be used to enhance the physical fault isolation tools of OBIRCH and LIT.
Design for Failure Analysis in a 24 GHz Low-Noise Amplifier for Short Range Radar Applications Created in Silicon CMOS Technology
Authors: Scholz Philipp , Vehring Soenke , Kerst Uwe , Berger Dirk , Boit Christian , Boeck Georg , Gerfers Friedel 
Published: December 2020

Abstract
As the Internet of Things, smart factories and autonomous driving increase the demand for low-price radar sensors, the authors address this need by developing a 24 GHz short range radar in standard bulk silicon CMOS technology for mass market production. CMOS technology enables cost reduction and efficient system integration compared to former GaAs and current SiGe solutions. Design for failure analysis (DFFA) is implemented in the low-noise amplifier (LNA) of the radar to identify and compensate process deviations. It consists of scalable capacitor structures and is executed using focused ion beam circuit edit. By doing so, the design specifications of high gain and low noise of the LNA are reliably met at high yield for the desired operating frequency. The presented DFFA method enables a shift in peak gain by 2.5 GHz. It thereby improves gain and noise figure at 24 GHz by 2 dB and -0.2 dB respectively. The resulting optimized LNA achieves a gain of 20 dB and a noise figure of 3.7 dB matching and surpassing other state-of-the-art works in a single prototyping run.
High-Resolution Ultrasonic Inspection Images of Semiconductor Packages by Advanced High-Frequency Transducers
Authors: Kikukawa Koutaro , Sumikawa Kenta , Takahashi Takuya , Ohno Shigeru 
Published: December 2020

Abstract
This paper describes a method for obtaining high-resolution ultrasonic inspection images of semiconductor packages. We evaluated the effect of the incident ultrasonic frequency on the resolution and defect detection. When the incident frequency of the ultrasonic transducers is changed from 300 MHz to 400 MHz, the capability to detect package defect improves from 2.5 µm to 1.0 µm. The observed images of semiconductor packages proves that a 400 MHz transducer can be applied to inspect sophisticated LSIs.
An Advanced Diagnosis Flow for SRAMs
Authors: Ho Tien-Phu , Faehn Eric , Virazel Arnaud , Bosio Alberto , Girard Patrick 
Published: December 2020

Abstract
In modern electronic designs, more and more memories are embedded in a single chip. With the latest technologies, defects due to the manufacturing process are more prone to occur in the periphery of the memory. Obtaining a fast and accurate localization of such defects has become much more difficult with traditional diagnosis approaches that do not allow a fast-enough yield learning and improvement. This paper describes a new and automated diagnosis flow for SRAMs to determine the localization of any given defect and thus, to precisely guide the Failure Analysis phase. Based on the electrical and topological fault signatures obtained through traditional methods, each potential fault on the identified active nets is automatically simulated to retrieve the best defect candidates. This paper also presents preliminary results on a representative case study.
Application of Laser Deprocessing Techniques to Improve the Job Efficiency and Throughput on Logic Device
Authors: Yap H.H. , Yu J. , Nedeau D. , Sheridan Lucile C. Teague , Oh C.K. 
Published: December 2020

Abstract
There are several methods commonly used to locate the area of interest (AOI), such as using layout landmarks, applying laser marks, focus ion beam marks, etc. This paper discusses another method which can improve the job efficiency and cost-effectiveness by introducing the combination of laser marking and laser deprocessing technique (LDT) as a quick way to deprocess the AOI. It further explores LDT to improve the job efficiency and throughput in logic devices to achieve cost-saving targets. An experiment was performed on a 14nm technology node prototype chip that integrated logic and SRAM. The proposed LDT has demonstrated itself to be a useful method to increase the job efficiency by performing in batch and easy to locate the AOI upon loading the sample for SEM inspection. It is also a simple and cost-effective way to delayer comparing to other methodologies.
Nanoscale Strain Mapping via Photo-Induced Force Microscopy
Authors: Park Sung , Park Katie , Nowak Derek , Albrecht Tom , Wood Erin Leigh , Walker Angela Hight 
Published: December 2020

Abstract
Carrier mobility enhancement through local strain in silicon is a means of improving transistor performance. Among the scanning probe microscopy based techniques, tip-enhanced Raman spectroscopy (TERS) has shown some promising results in measuring strain. However, TERS is known to depend critically on the quality of the plasmonic tip, which is difficult to control. In this study, a test structure is used to demonstrate the capability of photo-induced force microscopy with infrared excitation (IR PiFM) in direct measurement of strain with approximately 10 nm spatial resolution. For SiGe pitch less than about 800 nm, the region between the SiGe lines should maintain residual strain. For a region with SiGe pitch of 1000 nm, it is verified that the strain between the SiGe lines is fully relaxed. PiFM promises to be a powerful tool for studying nanoscale strain in diverse material.
Case Study Failure Analysis of an Ultra-High Vacuum Enclosure Made of a Silicon Chip and Borosilicate Glass for the Cold Atom Laboratory
Authors: Garteiz Gil , Verdugo Javeck , Aveline David , Williams Eric , Croonquist Arvid , Blank Richard 
Published: December 2020

Abstract
In this paper, a failure analysis case study on a custom-built vacuum enclosure is presented. The enclosure’s unique construction and project requirement to preserve the maximum number of units for potential future use in space necessitated a fluorocarbon liquid bath for fault isolation and meticulous sample preparation to preserve the failure mechanism during failure analysis.
VLSI for Space Applications—Single Event Effect Investigation and Optical Analysis on an Integrated Laser Platform
Authors: Chef Samuel , Chua Chung Tah , Siah Yu Wen , Perdu Philippe , Gan Chee Lip , Tan Soon Huat , Koh Lian Ser 
Published: December 2020

Abstract
Today’s VLSI devices are neither designed nor manufactured for space applications in which single event effects (SEE) issues are common. In addition, very little information about the internal schematic and usually nothing about the layout or netlist is available. Thus, they are practically black boxes for satellite manufacturers. On the other hand, such devices are crucial in driving the performance of spacecraft, especially smaller satellites. The only way to efficiently manage SEE in VLSI devices is to localize sensitive areas of the die, analyze the regions of interest, study potential mitigation techniques, and evaluate their efficiency. For the first time, all these activities can be performed using the same tool with a single test setup that enables a very efficient iterative process that reduce the evaluation time from months to days. In this paper, we will present the integration of a pulsed laser for SEE study into a laser probing, laser stimulation, and emission microscope system. Use of this system will be demonstrated on a commercial 8 bit microcontroller.
Failure Analysis Case Study of a 1.5 Meter Space Flex Harness
Authors: Kim Erick , Mansour Kamjou , Garteiz Gil , Verdugo Javeck , Ross Ryan , D’Agostino Saverio , Blank Richard 
Published: December 2020

Abstract
This paper presents the failure analysis on a 1.5m flex harness for a space flight instrument that exhibited two failure modes: global isolation resistances between all adjacent traces measured tens of milliohm and lower resistance on the order of 1 kiloohm was observed on several pins. It shows a novel method using a temperature controlled air stream while monitoring isolation resistance to identify a general area of interest of a low isolation resistance failure. The paper explains how isolation resistance measurements were taken and details the steps taken in both destructive and non-destructive analyses. In theory, infrared hotspot could have been completed along the length of the flex harness to locate the failure site. However, with a field of view of approximately 5 x 5 cm, this technique would have been time prohibitive.
An Overview of Risk-Based EEE Counterfeit Part Detection Based on SAE AS6171
Authors: Azarian Michael H. 
Published: December 2020

Abstract
As counterfeiting techniques and processes grow in sophistication, the methods needed to detect these parts must keep pace. This has the unfortunate effect of raising the costs associated with managing this risk. In order to ensure that the resources devoted to counterfeit detection are commensurate with the potential effects and likelihood of counterfeit part usage in a particular application, a risk based methodology has been adopted for testing of electrical, electronic, and electromechanical (EEE) parts by the SAE AS6171 set of standards. This paper provides an overview of the risk assessment methodology employed within AS6171 to determine the testing that should be utilized to manage the risk associated with the use of a part. A scenario is constructed as a case study to illustrate how multiple solutions exist to address the risk for a particular situation, and the choice of any specific test plan can be made on the basis of practical considerations, such as cost, time, or the availability of particular test equipment.
Use of Analog Simulation in Failure Analysis: Application to Emission Microscopy and Laser Voltage Probing Techniques
Authors: Auvray Etienne , Saury Luc , Armagnat Paul , Melis Tommaso , Reverdy Antoine 
Published: December 2020

Abstract
This paper describes a novel flow using analog simulations for the failure analysis of digital, analog, and mixed signal devices. Although cell level diagnosis tools are available in the industry, it presents a solution through analog intra-cell simulation particularly advantageous when multiple defects give the same fault result at cell level. Details of case studies such as the one analog intracell simulation on digital device and the analog laser voltage probing are covered. The aim of the simulation solution proposed is to support the failure analyst to interpret emission images on analog devices. The presented analog simulation flow consists of computing the current (or current density) in MOS and bipolar transistors and simulating the internal waveforms in digital or analog cells. It enables failure analysts to interpret light emission and laser voltage probing results obtained on a physical device in a fast and efficient way.
Transmission Electron Microscopy Sample Preparation By Design-Based Recipe Writing in a DBFIB
Authors: Demarest J. , Austin B. , Arjavac J. , Breton M. , Bergendahl M. , Biedrzycki M. , Boye C. , Gaudiello J. , Hager J. , Matham S. , Nguyen K. , Persala M. , Teehan S. 
Published: December 2020

Abstract
Transmission electron microscopy (TEM) sample can be routinely made at a sub 30nm thickness and specific features in semiconductor device design are on the order of 30nm and smaller. As a result, small changes in pattern match registration can significantly influence the success or failure of proper TEM sample placement as an approximately 15nm shift in lamella placement can easily cause the sample to be off the feature of interest. To address this issue, design based recipe writing is being developed on a dual beam focused ion beam platform. The intent is to have the tool read a GDS file and pattern match the design information to physical wafer images in a similar fashion to state-of-the-art critical dimension scanning electron microscopy operation. While the results are very encouraging, more work needs to be done to ensure a TEM sample of approximately 30nm thickness is placed at the desired location.
Time Domain Nanoprobe Analysis of RTS Popcorn Noise in Analog Circuits
Authors: Mulder Randal 
Published: December 2020

Abstract
Random Telegraph Signal (RTS), also described as popcorn noise in semiconductor analog circuits occurs when there is a sudden step in threshold voltage for a MOSFET or sudden step in base current for a bipolar transistor. The causes of popcorn noise can be process-related in semiconductor manufacturing. This paper presents a nanoprobe analysis methodology that was able to detect popcorn noise issues in discrete transistors causing analog circuit failure. The results presented for two different devices obtained similar results proving that the analysis methodology is viable for detecting popcorn noise issues in semiconductor MOSFET transistors. From a failure analysis perspective, the purpose of this paper is to provide the ability and a methodology to detect a signal that differentiates a failing transistor (popcorn noise) from a non-failing transistor (no popcorn noise). In this regard, the ability to obtain these results was not only unexpected but also very successful.
Spectroscopy-Based Mapping with Scanning Microwave Impedance Microscopy
Authors: De Wolf Peter , Huang Zhuangqun , Pittenger Bede 
Published: December 2020

Abstract
Methods are available to measure conductivity, charge, surface potential, carrier density, piezo-electric and other electrical properties with nanometer scale resolution. One of these methods, scanning microwave impedance microscopy (sMIM), has gained interest due to its capability to measure the full impedance (capacitance and resistive part) with high sensitivity and high spatial resolution. This paper introduces a novel data-cube approach that combines sMIM imaging and sMIM point spectroscopy, producing an integrated and complete 3D data set. This approach replaces the subjective approach of guessing locations of interest (for single point spectroscopy) with a big data approach resulting in higher dimensional data that can be sliced along any axis or plane and is conducive to principal component analysis or other machine learning approaches to data reduction. The data-cube approach is also applicable to other AFM-based electrical characterization modes.
SEM/EDS Characterization of Uncommon Metal Whiskers and Determination of Underlying Growth Mechanisms
Authors: Basak D. , Ponce L. H. 
Published: December 2020

Abstract
Two case-studies on uncommon metals whiskers, performed at the Reliability Analysis Laboratory (RAL) of Northrop Grumman Innovation Systems, are presented. The components analyzed are an Oven Controlled Crystal Oscillator (OCXO) and an Electromechanical Relay. Investigative techniques were used to determine the chemical and physical makeup of the metal whiskers and develop an understanding of the underlying effects and mechanisms that caused the conditions conducive to whisker growth.
Non-Destructive Short Fault Localization in Advanced IC Packages Using Electro Optical Terahertz Pulse Reflectometry
Authors: Zee B. , Qiu W. , Alton J. , White T. , Igarashi M. , Sullivan D. 
Published: December 2020

Abstract
We demonstrate how electro optical terahertz pulse reflectometry (EOTPR) can be used in conjunction with a new one-dimensional lump circuit simulation software to quickly and non-destructively isolate faults in advanced IC packages. In the case studies presented, short failures are accurately located in a series of advanced IC package.
Integrated Diffractive Lenses for Ultrathin Silicon
Authors: van Veenhuizen Marc , van der Cruijsen Peter , Serrels Keith A. , Zachariasse Frank 
Published: December 2020

Abstract
High numerical aperture (NA) laser scanning for fault localization requires the use of special lenses aimed at creating a tightly focused laser spot within an integrated circuit. Typically, extrinsic solid immersion lenses are employed that optimize the refraction at the air-silicon surface. In this feasibility study we investigate with both simulations and experiments the use of integrated diffraction lenses for high-NA imaging. We take the limit to ultrathin silicon and discuss the implications for the lens design and performance.
A Novel Approach on Fractography Through Infrared Microscopy
Authors: Norico Allan , Estores Rommel 
Published: December 2020

Abstract
Some of the most challenging task in analyzing fractures is a die that has not been fully cracked apart and a cracked die with electrical overstress damage. Traditional tools such as simple magnifying lens, optical microscope and up to the advance Scanning Electron Microscope are not enough to study the internal fractures or markings that could lead back to the origin of the crack. In order to study these internal fractures, the analyst tends to break the sample into pieces. However, this method creates additional mechanical stress and leads to a secondary crack where the point of origin will be difficult to analyze.
This paper aims to introduce infrared microscopy in fractography (mainly on silicon) using cases and techniques to minimize the occurrence of secondary crack in analyzing internal fractures.
Optimisation of Large Chunk Lift-Out Method and Lamella Preparation for CBED mEasurements Using Xenon Plasma FIB
Authors: Hrabovský Miloš , Morávek Tomáš , Narendraraj Chandran , Gluch Jürgen , Gall Martin , Zschech Ehrenfried , Mühle Uwe 
Published: December 2020

Abstract
As the new generation of microelectronics is pushed into smaller spaces and the yield production is pushing to lower the unoccupied spaces on chips, the local variation of stress has an influence on the component’s performance. This stress comes mainly from different thermal and mechanical properties of the materials used especially in 3D integrations like through silicon via (TSV) technology [1]. Through finite element simulation [2] the internal strain profile was modelled and based on these findings we devised a simulation model for a large area chunk lift out, to preserve the stress inside the material.
Standard preparation method for strain measurement is to use a wafer dicing saw and subsequently focused ion beam (FIB) milling, to create lamellae with a defined geometry, close to the desired TSV. This method requires different equipment and knowledge base to achieve a lamella which is still contaminated by Gallium. Therefor we developed our own method based on an FE model of a large chunk lift out, where only a Xenon Plasma FIB is utilized until the local stress measurement using convergent beam electron diffraction (CBED) is measured in a transmission electron microscope (TEM).
3D-Printed Samples For EXLO/INLO Practice and Training
Authors: Giannuzzi Zachary A. , Giannuzzi Lucille A. , Gehoski Kathleen A. , Mahoney William J. 
Published: December 2020

Abstract
Practice and training samples have been manufactured using 3D-printing methods. These 3D-printed samples mimic the exact geometry of focused ion beam (FIB) prepared specimens and can be used to help master ex situ and in situ lift out micromanipulation methods. An additively manufactured array of samples yields numerous samples needed for repetition and deliberate practice necessary to master the lift out and micromanipulation steps. The 3D-printed samples are cost effective and negates expensive FIB time needed to prepare FIB specimens.
High Throughput and Multiple Length Scale Sample Preparation for Characterization and Failure Analysis of Advanced Semiconductor Devices
Authors: Bonifacio C. S. , Nowakowski P. , Ray M. L. , Fischione P. E. , Downing C. 
Published: December 2020

Abstract
Failure analysis of advanced semiconductor devices demands fast and accurate examination from the bulk to the specific area of the defect. Consequently, nanometer resolution and below is critical for finding defects. This work presents the use of argon ion milling methods for multiple length scale sample preparation, micrometer to sub-ångström, without sample preparation- induced artifacts for correlative SEM and TEM failure analysis. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 20 nm are obtained.
Second Order Effect Monitoring During Backside Milling for Functional End Point Detection
Authors: George Anthony , Goldthwaite Isaac , Liszewski Katie , Schley Jeremiah , Kent Thomas 
Published: December 2020

Abstract
Backside silicon removal provides an avenue for a number of modern non-destructive and circuit edit techniques. Visible light microscopy, electron beam microscopy, and focused ion beam circuit edit benefit from a removal of back side silicon from the integrated circuit being examined. Backside milling provides a potential path for rapid sample preparation when thinned or ultrathinned samples are required. However, backside milling is an inherently destructive process and can damage the device function, rendering it no longer useful for further nondestructive analysis. Recent methods of backside milling do not guarantee device functionality at a detected end point without a priori knowledge. This work presents a methodology for functional end point detection during backside milling of integrated circuit packaging. This is achieved by monitoring second order effects in response to applied device strain, which guide the milling procedure, avoiding destructive force as the backside material is removed. Experimental data suggest a correlation between device power consumption waveforms and second order effects which inform an in situ functional end point.
Keywords: functional end point, side-channel analysis, backside thinning, milling, machine learning, second order effects
A Novel Method of Fabrication of Metal Probes for Scanning Probe Microscopy
Authors: Milczarek Michał , Jarząbek Dariusz M. 
Published: December 2020

Abstract
A novel method of fabrication of all-metal probes for scanning probe microscopy was developed. The motivation for this work was to develop probes and a method of fabricating them, which can be applied to measure friction of pairs of many different materials at the nanoscale. The main process of the presented manufacturing technique is nickel electrodeposition. The other steps are similarly simple and cheap. Moreover, the technique can be easily modified to manufacture probes of different materials and with different tip shapes.
Introduction of a Novel Sample Preparation Technique for the Failure Analysis of Silicon Integrated Photonics Modules
Authors: Pichumani Pradip Sairam , Khatkhatay Fauzia 
Published: December 2020

Abstract
Silicon photonics is a disruptive technology that aims for monolithic integration of photonic devices onto the complementary metal-oxide-semiconductor (CMOS) technology platform to enable low-cost high-volume manufacturing. Since the technology is still in the research and development phase, failure analysis plays an important role in determining the root cause of failures seen in test vehicle silicon photonics modules. The fragile nature of the test vehicle modules warrants the development of new sample preparation methods to facilitate subsequent non-destructive and destructive analysis methods. This work provides an example of a single step sample preparation technique that will reduce the turnaround time while simultaneously increasing the scope of analysis techniques.