bluuebunny/crossref_metadata_2025_split huggingface dataset:
Mechanical/Structural Properties of the Key Thin Film Materials Ag, Cu, & Ni for Electronics Applications
Authors: Mohammed Yousuf , Josell Daniel , Baumgart Helmut , Elmustafa A A 
Published: February 2020

Thin metallic films and coatings of Ag, Cu, and Ni for interconnect and contact in next generation nanoelectronic are expected to have high conductivity, high temperature stability, good ohmic contacts to both p- and n- type semiconductors, and also superb mechanical properties. These metallic thin film are used in a variety of electronic applications due to their low cost of production, non-toxicity and excellent electrical conductivity. However, their applications in nanoelectronics are still limited due to diffusion into the commonly used silicon substrates and the tendency of developing oxides under atmospheric conditions. Thin oxide layers form immediately on metallic films surfaces’ upon contact with air even at room temperature. Thin metallic oxide films `tend to exhibit brittle behavior with a sharp jump in the mechanical properties such as hardness and modulus and results in high resistivity. Although the formation of oxides is still perceived as the primary impediment in using thin metallic films in nanoelectronics, thin metallic films exhibit promising applications in large-area electronics such as memories, MEMS, and microprocerssors.
Metallic films of Ag, Cu, and Ni each of 150, 300, 600 and 1000 nm thick were deposited on Si using E-beam evaporation and deposition technique. A shutter was used to successively cover increments of 1² of the wafer at a time, starting with the wafer fully uncovered. A thin titanium layer of 10 nm is first deposited over the entire Si wafers followed by 150, 300, 600, and 1000 nm of the 2² target. Vacuum conditions at the start were ~1x10-7 torr and reached as high as 2x10-6 torr during the copper deposition due to outgassing. Similar vacuum conditions were maintained for the other films.
The Ag, Cu, and Ni films thickness were verified using field emission scanning electron microscopy. A sample cross sectional FE-SEM of the 150 nm thick Ag film is shown in Figure1. Nanocrstalline grain structure formation is observed to dominate the crystal film growth. The nanomechanical properties were measured using nanoindentation to determine the modulus and hardness of the Ag, Cu, and Ni films. Indentations of 1/3 and 2/3 of the film thickness in addition to 2 µm deep indents were performed on each film to study the film properties irrespective of the Si substrate influence as well as the substrate influence on the mechanical properties. Figures 2 and 3 depict hardness versus normalized depth of indentation to film thickness for Ag and Cu. The hardness increases as the film thickness decreases and remains nearly flat (no size effects) for the same film with depth of indentation except for the very thin films as they suffer what is known as tapping effect [1].

References:

[1] David E. Stegal, Md. Abdullah Mamun, Bryan Crawford, and Abdelmageed Elmustafa, J. Mater. Res., Vol. 27, No. 12, Jun 28, 2012.

Figure 1
(Invited) Mechanism of Low Temperature ALD of Al2O3 on Graphene Terraces
Authors: Kwak Iljo , Park Jun Hong , Grissom Larry , Fruhberger Bernd , Kummel Andrew 
Published: February 2020

2-D materials are single or trilayer networks of atoms, such as carbon, hBN, and MoS2. 2D materials are attractive for future electronic devices because they provide ballistic transport of charge carriers as well as carrier confinement. These novel devices require ultrathin and defect-free dielectric layers as gate or channel insulators. However 2D semiconductors such as graphene, boron nitride, and metal dichalcogenides (MDCs) are un-reactive; thus, the dielectric layer selectively nucleates on defect sites or step edges. In the conventional atomic layer deposition (ALD) process on graphene or other 2D semiconductors, such non-uniformly grown oxides can create large leakage currents. In the present report, polar metal phthalocyanine molecules have been employed as an ALD template for high nucleation density deposition of dielectric layers. By combining in-situ scanning tunneling microscopy (STM) and fabrication graphene devices, the insulating property and growth mechanism of the dielectric layer have been elucidated. Metal Ptholocyanines have been used to deposit gate oxides on graphene, MoS2, and WSe2. To deposit an ultrathin dielectric onto WSe2, monolayer titanyl phthalocyanine (TiOPc) is deposited by molecular beam epitaxy (MBE) as a seed layer for atomic layer deposition (ALD) of Al2O3 on WSe2. TiOPc molecules are arranged in a flat monolayer with four-fold symmetry as measured by scanning tunneling microscopy (STM). ALD pulses of trimethyl aluminum and H2O nucleate on the TiOPc, resulting in a uniform deposition of Al2O3, as confirmed by atomic force microscopy and cross-sectional transmission electron microscopy. The field-effect transistor (FETs) formed using this process have a leakage current of 0.046 pA/µm2 at 1 V gate bias with 3.0 nm EOT, which is lower leakage current than prior reports. The n-branch of the FET yielded a subthreshold swing of 80 mV/decade.
(Invited) Reliability Study on Layered 2D Insulator
Authors: Nagashio Kosuke 
Published: February 2020

Hexagonal boron nitride (h-BN), an insulating layered material with a wide band gap, is widely utilized as the substrate and gate insulator to achieve high carrier mobility in layered channel materials, especially graphene. However little study has been conducted on the statistical analysis of the breakdown voltages and the breakdown mechanism. Generally the dielectric breakdown of SiO2, conventional three-dimensional (3D) amorphous oxides is simply explained by a percolation model. It has not been determined whether the dielectric breakdowns of 2D layered materials follow the general breakdown phenomena for 3D amorphous oxides. In this study, the anisotropic dielectric breakdown of h-BN is studied.
We have found that the dielectric breakdown in c axis direction using a conductive atomic force microscope proceeded in the layer-by-layer manner [1]. The obtained dielectric field strength was ~12 MV/cm, which is comparable to the conventional SiO2. On the other hand, to estimate the dielectric field strength in a direction perpendicular to c axis, voltage is applied to a relatively thick h-BN (5-60 nm) through Cr/Au electrodes fabricated on the h-BN by EB lithography. We realized that the absorbed water on h-BN significantly affect the IV characters and the breakdown voltage. After the adsorbed water was removed by the heating in vacuum, the dielectric field strength was determined to be ~ 3 MV/cm, which is the same order as that in c axis direction. This value could be increased to be ~5 MV/cm when we consider the effect of electric field concentration around the metal electrode. This difference in dielectric filed strength for two directions is due to the highly-anisotropic nature of dielectric constant[2].
Ref. [1] Y. Hattori, et al., ACS nano
2015, 9, 916. [2] Y. Hattori, et al., in preparation.
Development of High Performance p-Type Bisbte Based Alloys By Powder Metallurgy
Authors: Madavali Babu , Lee Chul-Hee , Shin Dong-Won , Olu Emmanuel Femi , Hong Soon Jik 
Published: February 2020

Due to the rapidly increasing global demands for alternative energy sources, thermoelectric materials are receiving great attention compare to other renewable energy sources due to the exhibiting excellent characteristic features such as no moving parts, silent, reliable, environment freely and minimum maintenance. TE devices are the semiconductor systems that can either directly convert thermal energy into electricity for power generation, or perform cooling or heating with electric power.
So far, single (unidirectional) crystal growth techniques such as zone melting and czochralski were used to produce TE material in which the maximum ZT of TE materials almost unity ( ZT= 1) was obtained. However, these crystals having cleavages along the basal plane and got easily fractured. Nevertheless, improving mechanical properties was elusive so far due to exhibiting coarse grain size and gets easily fractured during the manufacturing. Recent studied showed that the powder metallurgy methods (PM) have been attaining best TE properties as well as mechanical properties. TE alloys by gas atomization is one of the well adopted processes, can easily make powders in large scale.
In this research, we have fabricated thermoelectric alloys by gas atomization then subsequently consolidated by SPS. The phase analysis, and microstructure of powders and bulks were characterized by X-ray diffraction and scanning electron microscopy respectively. The temperature dependence of electrical resistivity and Seebeck coefficient were systematically investigated from room temperature to 500 K. The figure of merit, ZT is calculated from the measured Seebeck coefficient, electrical conductivity, and thermal conductivity values.
Plasma-Enhanced Atmospheric-Pressure Spatial ALD of Al2O3 and ZrO2
Authors: Creyghton Yves , Illiberi A. , Mione A. , van Boekel W. , Debernardi N. , Seitz M , van den Bruele Fieke , Poodt P. , Roozeboom Fred 
Published: February 2020

Spatial Atomic Layer Deposition is emerging as an industrial thin-film manufacturing technology [1]. The technique is becoming so popular since it combines all advantages of conventional ALD (ultimate control of layer thickness and conformality over 3D-topologies, superior film material properties) with far higher deposition rates and processing at atmospheric pressure by means of spatial separation of the reactive gases. The integration of non-thermal plasma in spatial ALD reactors is expected to widen the thermal ALD process window towards lower operation temperatures and to enable to growth of specific materials requiring radicals (O, N, H, OH, NH, etc.). To this end, novel plasma sources with exceptional dimensional and chemical stability are required which provide the flow geometries optimized for efficient radical transport.
This paper reports on our preliminary efforts to provide and examine the required linear scalable plasma sources. The effectiveness of close-proximity direct and remote plasma sources [2] are demonstrated using the deposition of thin dielectric films of Al2O3 and ZrO2 at temperatures ranging from room temperature to 100 oC. Both direct and remote plasma sources of the so-called surface DBD-type (Dielectric Barrier Discharge) can be applied for spatial ALD using the usual metal precursors and O2/N2 plasma. The advantage of the remote plasma option is avoidance of electrical source-substrate interaction which is often the cause of layer or substrate damage as a result of filamentary plasma discharges impacting the substrate.

P. Poodt, et al., J. Vac. Sc. Technol. A, 30 010802-1 (2012).

Y. Creyghton et al., Patent publication WO2015199539, Dec. 30 (2015).
Tuning the Performance of Pt/HfO2/Ti/Pt ReRAM Devices Obtained from Plasma-Enhanced Atomic Layer Deposition for HfO2 Thin Films
Authors: Hardtdegen Alexander , Zhang Hehe , Hoffmann-Eifert Susanne 
Published: February 2020

The market of portable electronics and Green IT solutions demands for non-volatile memory circuits with high speed data access, high reliability, and low power consumption. Resistive switching random access memories (ReRAM) based on the valence change mechanism (VCM) represent a promising concept. VCM-type memristive devices are generally based on transition metal oxide thin films sandwiched between metal electrodes that differ in respect of work function and oxidation enthalpy. ReRAM cells built from insulating metal oxides with a high band gap, like e.g. TiO2, HfO2, Al2O3, typically require an electroforming step to enable resistive switching. Decisive for a stable device operation are a homogeneous microstructure and a controlled defect density in the oxide films of a few nm in thickness. Atomic layer deposition (ALD) can fulfill these requirements by its unique surface-reaction controlled self-limiting growth enabling a control of the film defect structure even for thicknesses in the nm-regime and for low growth temperatures.
During the electroforming process, an electronically conducting filament is formed a significantly increased density of oxygen vacancies. The stable VCM-type resistive switching is related to drift/diffusion processes of oxygen vacancies (or oxygen ions, respectively) which depend on the oxidation/reduction enthalpies of the materials involved in the switching event.
In this presentation we are going to discuss possibilities to tune the resistive switching performance of nanostructured ReRAM devices by means of a variation of metal oxide bilayer structures with respect to the layer thickness and the stack sequence. This study was performed on various bilayers based on combinations of TiO2/Al2O3 [1] and TiO2/HfO2 [2] with a total thickness < 10 nm integrated into nano-crossbar structures with a size of 100 x 100 nm2. Addressing the ReRAM device performance we discuss effects on the electroforming voltage, necessary SET- and RESET-voltages, achievable resistance ratios, switching stability and variability. In addition, changes in the resistive switching polarity, i.e. from bipolar to complementary-type, which have been observed for certain stacks, are discussed.
This work was supported in part by the Deutsche Forschungsgemeinschaft (SFB917).
References:
[1] H. Zhang, N. Aslam, M. Reiners, R. Waser, S. Hoffmann-Eifert, “Atomic Layer Deposition of TiOx/Al2O3 Bilayer Structures for Resistive Switching Memory Applications”, Chemical Vapor Deposition, vol. 20, pp. 282-290, 2014.
[2] A. Hardtdegen, C. La Torre, H. Zhang, C. Funck, S. Menzel, R. Waser, S. Hoffmann-Eifert, “Internal Cell Resistance as the Origin of Abrupt Reset Behavior in HfO2-based Devices determined from Current Compliance Series”, Memory Workshop (IMW), 2016 8th IEEE International, accepted, 2016.
A High Mobility of p-Type Sno Thin Films Grown By Atomic Layer Deposition for Thin Film Transistors
Authors: Kim Soo Hyun , Pyeon Jung Joon , Kim Seong Keun 
Published: February 2020

Oxide semiconductors have attracted great interest as channel materials for use in various emerging electronic applications including transparent and flexible displays, sensors, logic devices, and so on. Great progress has been made in n-type oxide semiconductors for thin film transistors (TFTs), which show superior properties such as high electron mobility and Ion/off ratio. Despite rapid development of n-type oxides, progress in the development of p-type oxides has been delayed. Only a few oxides including SnO, CuO, and NiO have been reported for p-type TFTs, and not yet sufficient for applications. Furthermore, most of the p-type oxides have been fabricated by a reactive sputtering technique, which is not applicable in industry.
In this study, we propose atomic layer deposition (ALD) of stable and high quality p-type SnO thin films for p-type TFTs. The SnO films were deposited with dimethylamino-2-methyl-2-propoxy-tin(II) and H2O as Sn and O sources, respectively. The growth of the SnO films was performed in a growth temperature range from 150 to 210 oC. From the XPS analysis, the ALD-grown SnO films are mainly composed of Sn2+ ions and O2- ions, and a peak from Sn4+ ions in the XPS spectra is not observed. As increasing the growth temperature, the Hall mobility increased from 1.26 to 3.8 cm2/Vs and Sn/O atomic ratio of the films approached the stoichiometric value from less unity (O-rich phase). We also fabricated TFTs with the ALD-grown SnO layer to characterize the properties of the p-channel layer in the TFTs. To exclude the influence of environment, we deposited a 15 nm-thick Al2O3 passivation layer on the TFTs by ALD. The field effect mobility increased with increasing the growth temperature, consistent with the change in the Hall mobility. A high field effect mobility of 1.5 cm2/Vs was achieved at a growth temperature of 210 oC. A high Ion/off ratio of ~ 106 was also achieved in the SnO film grown at 210 oC. This is attributed to the formation of dense and stoichiometric SnO films at 210 oC.
Bottom-up Cu Filling of through-Silicon-Via(TSV) with Single Additive
Authors: Jin Sanghyun , Seo Sungho , Park Sangwoo , Yoo Bongyoung 
Published: February 2020

Downscaling of the Cu interconnection was one of core technologies to enhance the performance of semiconductor devices. However, the shrinkage of Cu interconnection will face the limitation due to the physical limitation of Si based semiconductor device. In order to maintain the development in semiconductor device, the 3D interconnection is emerged, and the through-Si-via(TSV) interconnection is noticed. Large integration, high efficiency and high performance could be realized by composing the 3D integrated circuit with TSV. Furthermore, hetero interconnection between the logic and memory was possible by accepting the TSV technology.
The TSV filling process which plating the Cu in the TSV by electrodeposition was one of core process in TSV process due to high cost and difficulty. During the TSV filling process, bottom-up Cu filling which the Cu filled from the bottom of via to the top, should be occurred for avoiding the void formation and decreasing the processing time. In other to achieve the bottom-up filling, various additives were added in the electrolyte. The suppressor inhibited the deposition rate of Cu at the top surface and the sidewall of TSV. The accelerator promoted deposition rate of Cu at the undermost bottom of TSV.
Theoretically, the bottom-up filling of TSV was initiated by suppression breakdown at the bottom of TSV.1-3 Simultaneous detachment of suppressor by high potential due to ion depletion at TSV bottom leads focus of current at bottom of TSV. Therefore, bottom-up TSV filling could be achieved by only using the suppressor. Moreover, it was reported that accelerator substitute the suppressor at the sidewall and disturbed the bottom-up filling.3

In this research, the characteristics of suppressor were systematically investigated to achieve the bottom-up Cu filling of TSV with only using the suppressor. The influence of suppressor concentration on the Cu electrodeposition was investigated by observing the CV curves and morphology of Cu deposit. The influence of suppressor concentration and current density on the bottom-up TSV filling had also been observed. Interesting changes in bottom-up TSV filling by changing experimental conditions were delicately analyzed. Finally, the bottom-up TSV filling was achieved with only using the suppressor. This leaded the perfect and fast void free filling of 60 μm deep TSV within 1000 seconds.

References

1.T. P. Moffat and D. Josell, J. Electrochem. Soc., 159, D208 (2012).
2.D. Josell, D. Wheeler, and T. P. Moffat, J. Electrochem. Soc., 159, D570 (2012).
3.L. Yang, A. Radisic, J. Deconinck, and P. M. Vereeckena, J. Electrochem. soc., 160, D3051 (2013).
Damascene Copper Plating Recipe Engineering for Defectivity, Health of Line (HOL) and Reliability Improvement
Authors: Ahmed Shafaat , Huang Qiang , Cheng Tien Jen , Findeis Paul , Koli Dinesh R , Troung Connie Nga , Grunow Stephan 
Published: February 2020

A typical damascene copper plating is a multi-step process, including wafer entry, Cu nucleation, trench filling and thick overburden plating. During these steps, the most important parameters are found to be the entry bias voltage (Evolv), nucleation pulse current (MWE) and the first plating step. It has been observed that a higher bias voltage helps to protect the seed dissolution and therefore improves the slit voids. In addition, an optimized MWE coupled with the first filling current was found to be beneficial to achieve embedded void free plating. This benefit is believed to relate to a thin but uniform Cu nucleation, which provides good conductivity but still leaves enough space in the narrow trenches for Cu to be filled during the first plating step. Fig.1a shows hollow metals signature at 12:00 and 3:00 O’clock position on the post CMP polished wafer surface which were acquired from a defined coordinate of a test macro. However, 1b shows the hollow metals at these locations significantly improved due to the graded plating fill current density in the first few fill steps followed by a potentiostatic entry. In this paper, we will describe how plating recipe could be engineered to minimize plating related defects and improve the overall HOL and reliability for BEOL interconnects.
Fig.1(a) API images from the post CMP wafer surface shows hollow metal signature at 12:00 and 3:00 O’clock position. 1(b) shows the hollow metals at these exact same locations significantly improved due to the graded fill current plating.

Figure 1
Bridging the Gap Between Supercapacitors and Batteries By a New Material Based on Renewable Resource
Authors: Fichtner Maximilian , Gao Ping , Chen Zhi , Zhao-Karger Zhirong , Ruben Mario 
Published: February 2020

A new material is presented, which is based on a porphyrin material and which delivers good specific capacities in the order of 180 mAh/g at an average voltage of approx. 3 V. The material can be charged and discharged at rates around 50 C which is in the range of supercapacitors.
By a simple chemical modification of the material, the typical issue of organic batteries, the degradation upon cycling, was greatly improved and 80% of the capacity was retained after 6,000 cycles. The material can be used as cathode or anode, or both. Charge and discharge can be done based on Li or other ionic shuttles such as Mg.

Figure 1
Morphological and Chemical Control of Oxide Cathode Materials Based on Mn
Authors: Hu Linhua , Cabana Jordi 
Published: February 2020

Oxides based on Mn redox couples continue to attract wide attention in lithium battery due to consideration of cost and safety. To bypass issues of capacity and durability associated with John-Teller distortions, substituents such as Ni and Co are introduced in the Mn or Li sites. Ni-Co-Mn ternary materials, e.g. LiNixMnyCozO2, are usually synthesized through methods that involve steps at high temperature, whether to react binary oxides or precursors such as hydroxides made by co-precipitation and other low temperature methods. High temperature calcination results in complex morphologies that hard to control, especially if refined nanoscale features are desired. Further, they inherently under thermodynamic driving forces and, thus, may miss possible intermediate or metastable phases.
Here, we report a one-step hydrothermal process to synthesize well-defined nanocrystals of binary Ni-Mn and ternary Ni-Mn-Co cathode materials. TEM showed their morphology varies between rod and octahedron depending on conditions. XRD and EDX revealed that nanorods are composed of layered Li[NixLi(1/3-2x/3)Mn(2/3-3/x)]O2, whereas the octahedra correspond to spinel-type LiMnxNixCo(2-2x)O4.

Their electrochemical property showed high voltage range 2-4.9v and large capacity at 150~200mAh/g. The uniform morphology provide the further potential for their surface functionalization with alumina and the quest for faster Li diffusion channels in the near future.