(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions
Authors: Tomioka Katsuhiro , Fukui Takashi 
Published: February 2020

Primary purpose in future integrated circuits is to decrease the power consumption while enhancing their performance. In this regard, the reduction of supply voltage of the field-effect transistors (FETs) using high-mobility channels such as III-Vs is effective approach to achieve the power scaling because the power consumption of integrated circuits is to proportional to the square of the supply voltage. With this matter, reduction of off-state leakage current and subthreshold slope (SS, < 60 mV/decade) in FETs is required for decreasing the supply voltage. The use of multi-gate architecture and steep SS transistors such as tunnel FET has been proposed as a way of reducing these parameters.
Conventional FETs have a physical limit on SS due to carrier thermal diffusion. Further power scaling of FET will be stopped by the physical limitation even though the mulltigate FETs using III-Vs are used. Thus, steep SS transistors specifically TFET are expected as a promising candidate switch in future energy efficient circuits. The use of the TFETs with an SS of 10 mV/decade with keeping device performance as conventional FETs would reduce the required supply voltage to as low as 0.3 V. Although Si-based TFETs are attractive device for mature Si-CMOS, the Si has low band-to-band tunneling probability, which decreases ON-state current. One of promising materials for increasing the ON-state current of TFETs is a combination of narrow band-gap III-V with a Si, that is, III-V/Si heterojunctions.
Our main goal is to replace mature Si-MOSFET by III-V nanowire (NW)-channel and TFET structure using the III-V NW/Si heterojunctions. However, the changes in technology from the mature Si-CMOS to the TFETs using III-V/Si heterojunction present significant challenges in terms of heteroepitaxy, devices processes and so on. Here we report on recent advances in heteroepitaxy of III-V NWs on Si substrate and recent achievements of steep-SS transistor using vertical III-V NW/Si heterojunctions.
As for formation of III-V NW-channels on Si, we used selective-area epitaxy with catalyst-free method. Recent progresses in the selective-area growth have enabled integration of vertical III-V NWs on Si substrates with precise positioning [1-3]. These heteroepitaxy provide unique phenomenon at the III-V NW/Si interface in terms of crystallography and electronic property. First, a number of misfit dislocations are decreased with decreasing diameter of the heterojunction [1,4]. Second, the III-V NW/Si with less misfit dislocation inherently forms specific band discontinuity, which is feasible for the utilization of TFETs [5,6]. For example, n-type InAs NWs grown on p-Si substrate has staggered type-II band discontinuity at the InAs/Si interface [6]. And both band-to-band (Esaki) tunneling and Zener tunneling current can be controlled by changing the carrier concentration of p-Si substrate [4]. This is because the position of the Fermi level in p-Si varies the tunneling transport under forward/reverse bias, and means that these III-V NW/Si heterojunctions are feasible as a new junction for TFETs. Thus, we have proposed vertical- and lateral-type TFETs based on III-V NWs/Si heterojunctions [6].
As a first step to demonstrate vertical TFET using III-V NW/Si heterojunction with steep SS, high performance gate stacking technologies are required for the III-V NW-channels. We have, therefore, developed device fabrication processes of vertical surrounding-gate architecture using InAs NW [7, 8] and InGaAs NW [9, 10], and achieved very low SS (~ 68 mV/dec.) for InGaAs NW-channel surrounding-gate transistors with EOT = 0.70 nm [11]. Moreover, we proposed high-electron mobility transistor using the InGaAs NW-channel [10] and demonstrate high performance vertical MOSFET using InGaAs NW-channel with transconductance of 1.45 mS/μm at VDS = 0.50 V [11]. The interface state density of the III-V NW/gate-oxide is ranged 2 - 4 ×1012 cm-2eV-1[12], which indicates these device processes and their gate-stacking technologies have good property to elicit steeper SS of vertical TFETs.
As for vertical TFET using InAs NW/Si heterojucntion, we have demonstrated much steeper SS ~ 21 mV/dec at room temperature [6]. This was resulted from the increment of heterojunction resistance with decreasing nanowire-diameter and the number of misfit dislocations. And next, we improved the channel resistance for InAs NW-channel by using specific pulse-doping method and revealed that formation of intrinsic InAs NW channel resulted in shifting of turn-on voltage while maintaining steep SS [4]. Other III-V NW/Si heterojunction, such as InGaAs NW/Si junction, has also shown steep turn-on properties under lower VDS[13].

Acknowledgments

The authors would like to thank Professors Junichi Motohisa and Tamotsu Hashizume, and Mr. Masatoshi Yoshimura, Eiji Nakai, and Fumiya Ishizaka for the fruitful discussions and the experimental supporting of MOVPE. This work was financially supported by a Grant-in-Aid for Scientific Research from the Ministry of Education, Culture, Sports, Science and Technology (MEXT) and the Japan Science and Technology Agency (JST) PRESTO program.

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