bluuebunny/crossref_metadata_2025_split huggingface dataset:
Analysis of Al-over-Cu Bond Pad Hillock and Pit Hole Defects
Authors: Cavasin Daniel , Yassine Abdullah 
Published: December 2020

Abstract
Bond pad metal corrosion was observed during assembly process characterization of a 0.13um Cu microprocessor device. The bond pad consisted of 12kÅ of Al-0.5%Cu atop 9kÅ of Cu, separated by a thin Ta diffusion barrier. The corrosion was first noted after the wafer dicing process. Analysis of the pad surface revealed pitting-type corrosion, consistent with published reports of classic galvanic cell reactions between Al2Cu (theta phase) particles and the surrounding Al pad metal. Analysis of the bond pads on samelot wafers which had not been diced showed higher-thanexpected incidence of hillock and pit hole defects on the Al surface. Statistically designed experiments were formulated to investigate the possibility that the observed pre-saw pad metal defects act as nucleation sites for galvanic corrosion during the sawing process. Analyses of the experimental samples were conducted using optical and scanning electron microscopy, along with focused ion beam deprocessing and energy dispersive X-ray. This paper explores the relationship between the presence of these pre-existing defects and the propensity for the bond pads to corrode during the dicing process, and reviews the conditions under which pit hole defects are formed during the final stages of the Cu-metallized wafer fabrication process. Indications are that strict control of wafer fab backend processes can reduce or eliminate the incidence of such defects, resulting in elimination of bond pad corrosion in the wafer dicing process.
Die Edge Thin Film Delamination on the Bottom Die of a Stacked Chip Scale Package (SCSP)
Authors: De la Rama Lito P. , Nuarin Dante G. , Nery Marilin H. 
Published: December 2020

Abstract
The increasing demand for high end electronic devices incorporating multiple functions in a small form factor leads to the widespread use of Stacked Chip Scale Packaging (SCSP) in the semiconductor industry. Multiple die stacking in various combinations have been achieved. However, new failure mechanisms are being observed due to new package stress characteristics. This paper will present a unique failure mechanism observed on the bottom die of a multiple die stack package. A detailed discussion of the failure mechanism showing the interaction between the presence of a high die attach adhesive fillet and the die singulation damage initiating a thin film delamination from the die edge towards the active circuit area causing electrical failures will be presented.
Multi-Point Probing on 65nm Silicon Technology using Static IREM-based Methodology
Authors: Bockelman Daniel R. , Rahman Asifur , Wan Ifar , Chen Steven Y. C. , Ettinger Scott M. 
Published: December 2020

Abstract
As silicon manufacturing processes move to smaller feature sizes, new silicon fault isolation and debug challenges arise. This paper presents a methodology for silicon fault isolation/debug that allows for simultaneous probing of multiple locations on the die using static infrared emission logic state imaging. Recent tool enhancements leading to more efficient fault isolation and debug are reviewed. Cases are presented from debug of 65nm products showing how this methodology was used to achieve very low throughput times on a variety of complex new failure mechanisms.
Novel and Practical Method of Through Silicon FIB Editing of SOI Devices
Authors: Jain R.K. , Lundquist T.R. , Antolik M.E. , Thompson M.A. 
Published: December 2020

Abstract
Circuit edit techniques have been developed for silicon-on-insulator (SOI) devices using a coaxial photon-ion column. Novel trenching, navigation and milling methods, utilizing sub pico-Amp beam currents provide enhanced capability for editing devices with decreased geometries including buried (Box) thickness. Flat trenches 200x200µm were obtained using real time optical fringe monitoring with 125nm accuracy with 950nm λ and FIB bit map milling to adjust for parallelism to the ILD0. This bit map milling technique controlled the etch rate to maintain trench flatness by correlating the optical fringes to the bit map grayscales to vary the dwell time of the ion beam across the trench floor. Through highly accurate, CAD directed beam deflection control, beam placement accuracy in the sub 20nm regime can readily be accomplished, sub pA beam currents provide ultracontrolled etch rates and high aspect ratio (HAR) capability. Complete process definitions, techniques and results are reported. These techniques have proven successful in circuit edit below 90nm, and are expected to meet future technology circuit edit requirements down to 45nm.
Dynamic Laser Delay Variation Mapping (DVM) Implementations and Applications
Authors: Sanchez Kevin , Desplats Romain , Perdu Philippe , Beaudoin Felix , Dudit Sylvain , Woods Gary , Lewis Dean 
Published: December 2020

Abstract
In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.
Soft Defect Localization Techniques without a Synchronization Signal to the Laser Scanning Module
Authors: Mitro Diana M. , Glaeser Dawn , Howard Clifford 
Published: December 2020

Abstract
Soft Defect Localization (SDL) is an analysis technique where changes in the pass/fail condition of a test are monitored while a laser is scanned across a die.[1,2,3,4] The technique has proven its usefulness for quickly locating failing nodes for functional fails that are temperature, frequency, and/or voltage dependant. The localized heating from the laser can toggle the pass/fail condition as it sweeps over failing nodes with the aforementioned sensitivity. The technique is instrumental in identifying latent defect locations on conditional fails even though they seldom produce light emissions or liquid crystal hot spots. These fails often manifest themselves after reliability stress or at the customer. The technique can also be applied to support design groups with first silicon analysis of timing race conditions and identification of signals that are speed path limiters. The main challenges associated with the technique are in synchronizing the tester with the Laser Scanning Module (LSM) and ensuring the laser can heat the device enough to overcome the pass/fail threshold temperature of the failing node.
Analysis Methods for Characterizing Drop Test Robustness of Lead-Free FBGAs
Authors: Walter J. , Fischer R. , Birzer C. 
Published: December 2020

Abstract
During the last few years the drop test has become more and more important for electronic handheld components. Drop test reliability for lead-free solder interconnects is an extreme challenge today. Thus, the need for improved micro structural diagnostics of new material combinations and crack detection methods has increased. The target of this paper is to summarize detection and analysis methods for solder joint cracks, material characterization [1] and preparation methods of assembled printed circuit boards (PCB) after a drop test to completely understand lead-free solder interconnect reliability in fine pitch ball grid array packages (FBGA). In particular, we will introduce the outstanding advantages of embedded cross-sections combined with ion beam polishing (IBP), dye- or rather resin-penetration, selective tin etch and micro-hardness measurements.
Analysis of a Microcircuit Failure using SQUID and MR Current Imaging
Authors: Felt Frederick S. 
Published: December 2020

Abstract
SQUID and MR magnetic sensors have separately been used for fault isolation of shorts and resistive opens in integrated circuits and packages. These two technologies were once considered to be mutually exclusive, although recent studies [1] rather pointed to their complementary character. This paper shows, for the first time, the use of these two sensors together to isolate a low resistance short in a Quad-NAND gate microcircuit. Electrical test confirmed low resistance shorts between three of the device pins. However, internal optical inspection found no evidence of failure. The low resistance of the shorts was deemed insufficient for liquid crystal analysis. Magnetic current imaging with a SQUID sensor confirmed current flow through the package lead frame and isolated the defect to the microcircuit. Due to package design and the resulting distance of the scan plane, the SQUID was unable to resolve the current path on the microcircuit. In parallel with the SQUID, a magnetoresistive (MR) probe was employed to fit inside the device cavity, make direct contact with the microcircuit, and map high-resolution current images. Two sites with high-current density were accurately identified by MCI in input transistors. Subsequent deprocessing revealed that the defects were located under a broad sheet of aluminum metallization which blocked optical detection, and rendered detection by thermal emission difficult.
Single Device Characterization by Nano-probing to Identify Failure Root Cause
Authors: Wu Chao-Chi , Lee Jon C. , Chuang Jung-Hsiang , Li Tsung-Te 
Published: December 2020

Abstract
In general failure analysis cases, a less invasive fault isolation approach can be utilized to resolve a visual root cause defect. In the case of nano technology, visual defects are not readily resolved, due to an increase in nonvisible defects. The nonvisible defects result in a lower success rate since conventional FA methods/tools are not efficient in identifying the failure root cause. For the advanced nanometer process, this phenomenon is becoming more common; therefore the utilization of advanced techniques are required to get more evidence to resolve the failure mechanism. The use of nanoprobe technology enables advanced device characterization in order to obtain more clues to the possible failure mechanism before utilizing the traditional physical failure analysis techniques.
Analysis of DRAM Standby Current Failure due to Hot Electron Induced Punch-through (HEIP) of PMOS transistor
Authors: Cho M. H. , Kim Y. I. , Choi J. , Woo D. S. , Lee K. P. , Park Y. J. , Lee W. S. , Ryu B. I. 
Published: December 2020

Abstract
A standby current failure of the 80nm design-ruled Dynamic Random Access Memory (DRAM) during burn-in stress was investigated. In our case, hot electron induced punch-through (HEIP) of a PMOS transistor was a leakage current source. The bake test is a useful method to identify the mechanism of a standby current failure due to hot carrier degradation.
Method of Failure Site Isolation for Flash Memory Device Using FIB, Passive Voltage Contrast Techniques
Authors: Yuan Caiwen , Li Susan , Gray Andy 
Published: December 2020

Abstract
Current VLSI devices have very complicated circuit designs and very small feature size. As a result, fault isolation on failing devices becomes a more and more challenging task. Although backside photoemission technique is commonly used to detect the failure site covered with multiple metal layers, it has the disadvantages of more time consumption and less success rate. Without a localized failure site, it will be very difficult, sometime even impossible, to find the physical evidence for the failures. This article describes a method that has been successfully used for isolating the wordline leakage on a memory FLASH device using FIB cutting and passive voltage contrast on the leaky wordline. The concept of this article is not just limited to this application; rather it can be used for all similar types of fault isolation work for other applications.
Increasing Planarity for Failure Analysis Using Blocked Reactive Ion Etching Combined with Planar Polish
Authors: Weldy Mary Elizabeth , Serrano Leslie 
Published: December 2020

Abstract
Challenges in sample preparation for semiconductor failure analysis are always increasing as more complex material and smaller dimensions are required to meet the needs of the semiconductor industry. These changes require the constant need for more refined procedures in all areas of sample preparation, including mechanical polish. This paper presents a newly modified technique which increases the planarity at the critical edge of the sample and results in a larger planar region of interest. The novel method combines both a blocked reactive ion etching and a standard planar polish. It has proven to be a successful delayering technique and helpful in facilitating further analysis. This method has been verified on dies, wafer pieces, and dies thinned and attached to blank silicon for support. It is useful for increasing overall planarity and particularly helpful for the extreme edge.
Automated Sample Preparation of Low-k Dielectrics for FESEM
Authors: Cerchiara R. R. , Cook H. A. , Fischione P. E. , Gronsky J. J. , Matesa J. M. , Robins A. C. , Smith D. W. , Beach E. R. , Wood C. J. , Rozeveld S.J. , Waeterloos J. 
Published: December 2020

Abstract
The SiLK resins, composed of aromatic hydrocarbons, are a family of highly cross-linked thermoset polymers with isotropic dielectric properties. Patterning of SiLK for high aspect ratio copper interconnects has depended on reactive ion etching with oxygen/nitrogen gas mixtures. Reactive ion etching is therefore also accomplished with reducing plasmas such as nitrogen/hydrogen. An additional plasma cleaning step can be inserted after the reactive ion etching (RIE) step, so that any residual contamination is removed prior to imaging or final sputter coating. Automated sample preparation of microelectronic materials containing high and low-k dielectrics for FESEM is accomplished in this article by combining these techniques: plasma cleaning, ion beam etching, and reactive ion etching. A single RIE chemistry was effective in etching both dielectrics as well as delineating the other phases present.
A Novel Method to Observe the Silicide in TEM
Authors: Liu Pan 
Published: December 2020

Abstract
In modern IC fabrication technology, metal silicide technology in microelectronics has been a standard process to reduce contact resistance. The thickness of metal silicide is an important parameter in reducing the contact resistance, especially, the 130nm, 90nm, and beyond technology. The traditional method to measure the thickness of silicide, however, has a dilemma as to whether to obtain the clear interface or to get the true thickness. This paper reports a novel method to improve the interface contrast and get a true thickness by changing the substrate single crystal contrast. Polishing and ion milling method were used to get thin transmission electron microscopy samples. In this paper, the substrate scattering probability is changed by tilting the samples. Using the method, a clear interface can be developed between the silicide and substrate single crystal silicon can be obtained without affecting the accuracy of the measured silicide thickness.
Thermal Imaging Product Power-up: Metrology for Capturing Thermal Defects on Live Units Not Visible on Any Other Technique
Authors: Zamora Nova T. , Chong Kam Meng , Gupta Ashish 
Published: December 2020

Abstract
This paper presented the recent application of die powerup in Thermal Imaging as applied to the detection of defects causing thermal failure on revenue products or units not being captured using other available techniques. Simulating the condition on an actual computer setup, the infrared (IR) camera should capture images simultaneously as the entire bootup process is being executed by the processor, thus revealing a series of images and thermal information on each and every step of the startup process. This metrology gives the failure analyst a better approach to acquire a set of information that substantiate in the conduct of rootcause analysis of thermal-related failure in revenue units, especially on customer returns. Defective units were intentionally engineered in order to collect the thermal response data and eventually come up with a plot of all known thermal-related defects.
Strategies for the Analysis of Single Unit Failures in Low Failure Rate Applications
Authors: Kolasa Ted , Kopycinski Jay , Mendoza Alfredo 
Published: December 2020

Abstract
Many manufacturers in the microelectronics industry supply customers who increasingly demand ultra-low product failure rates. However, one of the least desirable scenarios for the microelectronic failure analyst is when analysis is required on a single failed unit. In these cases, the analyst loses the luxury of having “disposable” failing units in the analysis process. In the following discussion we present strategies to help the analyst more effectively find the failure mechanism for single unit failures.
Improvement of Electrical Contacts in the Failure Analysis for in-depth Characterization of Structures and Products
Authors: Huettinger Michael , Touzel Jérôme 
Published: December 2020

Abstract
The electrical interface, in terms of a reliable, low ohmic and defined connection with the device or die is the most relevant aspect in the characterization of products. Bad or undefined contacts inhibit an exact assessment of the functionality. This paper describes different contact related failures analyzed in our lab and gives the solutions we used to solve the problems. Especially an electroless (nickel)-gold plating method has been optimized and is described in details. Low ohmic and reliable contacts can be produced; the paper shows several applications to improve the contact quality in different domains of the failure analysis business
Failure Analysis of Electronic and Microelectronic Components with a New Automatic Target Preparation System
Authors: Reiter Katja , Bundgaard Hans 
Published: December 2020

Abstract
Based on the requirements regarding target, reproducibility, and specimen surface quality, an automatic system for controlled material removal and target preparation has been developed. The tool is for metallographic failure analysis of electric and microelectronic components, and provides an accuracy of 5 micrometer. This article presents details of sample preparation and device evaluation methods. The images presented show typical objects of examination in the analysis of microstructures and materials in the electronics packaging industry with brief comments. For automatically controlled material removal and preparation, the tool offers alignment and measuring of the sample prior to the preparation. The desired preparation layers were achieved precisely and reproducibly with several specimens of the same kind. The automatic preparation system allowed the preparation of critical samples within a short time, with high precision and with excellent reproducibility.
An Atlas of ESD Failure Signatures in Vertical Cavity Surface Emitting Lasers
Authors: Mathes D.T. , Guenter J. , Hawkins B. , Hawthorne B. , Johnson C. 
Published: December 2020

Abstract
AOC herein describes a collection of material degradation features observed in Vertical Cavity Surface Emitting Lasers (VCSELs) that have been intentionally degraded with a range of electrostatic discharge (ESD) stress conditions. Failure analysis techniques employed include emission microscopy, Focused Ion Beam (FIB) microscopy and Transmission Electron Microscopy (TEM). The results have enabled higher confidence in root-cause determination for failed VCSEL devices.
3D Observation of Elemental Distribution of Si-Device using a Dedicated FIB/STEM System
Authors: Yaguchi T. , Konno M. , Kamino T. , Ogasawara M. , Kaji K. , Ohnishi T. , Watanabe M. 
Published: December 2020

Abstract
A technique for preparation of a pillar shaped sample and its multi-directional observation of the sample using a focused ion beam (FIB) / scanning transmission electron microscopy (STEM) system has been developed. The system employs an FIB/STEM compatible sample rotation holder with a specially designed rotation mechanism, which allows the sample to be rotated 360 degrees [1-3]. This technique was used for the three dimensional (3D) elemental mapping of a contact plug of a Si device in 90 nm technology. A specimen containing a contact plug was shaped to a pillar sample with a cross section of 200 nm x 200 nm and a 5 um length. Elemental analysis was performed with a 200 kV HD-2300 STEM equipped with the EDAX genesis Energy dispersive X-ray spectroscopy (EDX) system. Spectrum imaging combined with multivariate statistical analysis (MSA) [4, 5] was used to enhance the weak X-ray signals of the doped area, which contain a low concentration of As-K. The distributions of elements, especially the dopant As, were successfully enhanced by MSA. The elemental maps were reconstructed from the maps.
Burn-In Acceleration Considerations in 130nm and 90nm Products
Authors: Wakai Nobuyuki , Kobira Yuji , Setoya Takashi , Oishi Tamotsu , Yamasaki Shinichi 
Published: December 2020

Abstract
An effective procedure to determine the Burn-In acceleration factors for 130nm and 90 nm processes are discussed in this paper. The relationship among yield, defect density, and reliability, is well known and well documented for defect mechanisms. In particular, it is important to determine the suitable acceleration factors for temperature and voltage to estimate the exact Burn- In conditions needed to screen these defects. The approach in this paper is found to be useful for recent Cu-processes which are difficult to control from a defectivity standpoint. Performing an evaluation with test vehicles of 130nm and 90nm technology, the following acceleration factors were obtained, Ea&gt;0.9ev and β (Beta)&gt;-5.85. In addition, it was determined that a lower defect density gave a lower Weibull shape parameter. As a result of failure analysis, it is found that the main failures in these technologies were caused by particles, and their Weibull shape parameter “m” was changed depending of the related defect density. These factors can be applied for an immature time period where the process and products have failure mechanisms dominated by defects. Thus, an effective Burn-In is possible with classification from the standpoint of defect density, even from a period of technology immaturity.
Impact of Metal Pad Etch-Induced Plasma Damage on Dynamic Retention Time Degradation during High Temperature Stress in High Density DRAM Technology
Authors: Kim D-J , Kim I-G , Noh J-Y , Lee H-J , Park S-H , Lee J-H , Lee S-W , Yang K-H , Park Joosung , Shin Dongho , Oh Kyungseok 
Published: December 2020

Abstract
As DRAM technology extends into 12-inch diameter wafer processing, plasma-induced wafer charging is a serious problem in DRAM volume manufacture. There are currently no comprehensive reports on the potential impact of plasma damage on high density DRAM reliability. In this paper, the possible effects of floating potential at the source/drain junction of cell transistor during high-field charge injection are reported, and regarded as high-priority issues to further understand charging damage during the metal pad etching. The degradation of block edge dynamic retention time during high temperature stress, not consistent with typical reliability degradation model, is analyzed. Additionally, in order to meet the satisfactory reliability level in volume manufacture of high density DRAM technology, the paper provides the guidelines with respect to plasma damage. Unlike conventional model as gate antenna effect, the cell junction damage by the exposure of dummy BL pad to plasma, was revealed as root cause.