(Invited) Challenges of Graphene Process Integration in CMOS Technology
Authors: Lisker Marco , Lukosius Mindaugas , Lukose Rasuole , Wenger Christian , Mai Andreas 
Published: February 2020

Compatibility of graphene device fabrication process with Si integrated circuit (IC) manufacturing platforms can enhance the implementation of graphene in electronic and optoelectronic applications and their commercialization. Recent demonstrations of hybrid graphene-Si devices on a wafer scale [1, 2] clearly indicate increasing maturity of the graphene technology. However, there are remaining questions about the manufacturability, as well as the integration and compatibility with Si technology which are seen as prerequisites to the commercialization of graphene (opto-) electronic devices [3, 4]. Despite the remarkable progress in recent years, protocols used for the fabrication of graphene devices often lack the required stability and compatibility which in turn hinders access to the large-scale semiconductor device manufacturing infrastructure. From this point of view, it is of utmost importance to investigate preparation of graphene devices in conditions resembling as close as possible to the Si-based IC production environment. Although this approach may pose inherent risks to the fabrication toolsets, it provides a rare opportunity to explore the engineering aspects of graphene device preparation in a relevant production environment.
In this paper we focus on engineering aspects of graphene device fabrication under constraints of manufacturability. We demonstrate some of the key stepping stones which can form a pathway to the fabrication of graphene-based components using tools and processes applied in the IC manufacturing in a 200 mm wafer Si technology environment. As a case study, we present insights into processes of cleaning, patterning, encapsulation, and contacting graphene in a 200 mm wafer pilot line routinely used for the fabrication of ICs in 0.13/0.25um SiGe BiCMOS (bipolar-complementary metal-oxide-semiconductor) technologies. Following the presentation of key process steps and selected electrical characterization results, we point out to the challenges and roadblocks which need to be overcome to enable integration of this material with Si devices.
Although Cu substrates offer graphene an outstanding quality, layer transfer from Cu is associated with a significant risk of metallic contaminations which pose limitations on handling of graphene in CMOS processing lines. For this reason, our experiments rely on graphene grown on Ge surfaces which has been proven to be front-end-of-line compatible in terms of purity. Chip-size patches of graphene are transferred from the epi-Ge/Si growth wafer by electrochemical delamination to various sorts of patterned 200 mm wafers on which the further process development takes place. This method of graphene transfer is not yet fully compatible with the Si technology; however, it offers convenient prototyping opportunities as an intermediate solution until full 200mm wafer transfer processes as for example the wafer bonding is developed.
Encapsulation of deposited graphene is essential to protect its properties from the environment and the destructive influences of subsequent processing. The key element of the encapsulation in our fabrication scheme is a thin (20 nm-50 nm) SiN layer deposited by low power plasma-enhanced chemical vapor deposition (PECVD). It has been demonstrated that layers of SiN can be grown by PECVD directly on the graphene with excellent uniformity and electrical performance while preserving its crystalline quality and transport properties. The added value of PECVD technique is that it is widely used in the Si IC manufacturing. We adapted this approach to form closed and smooth (rq = 0.47 nm) encapsulating layers of SiN (refractive index n = 2.02 at l = 633 nm) directly on transferred graphene. The second element of the encapsulation is realized by the deposition of a SiO2 layer on the SiN film by using CVD.
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