Vertical and Lateral GaN Power Devices Enabled By Engineered GaN Substrates
Authors: Luna Lunet E , Anderson Travis J. , Koehler Andrew D , Tadjer Marko J , Aktas Ozgur , Hobart Karl D. , Kub Fritz J 
Published: February 2020

GaN has accrued significant research interest as a material platform for next-generation high power devices. This focused research thrust in GaN, fueled by its wide bandgap and high electric field strength, is expected to enable power devices with superior performance compared to the readily available Si power devices. However, the lack of uniform, high quality commercially available GaN substrates has bottlenecked the research progress of GaN high power devices. These substrate issues can be avoided by straying away from native GaN substrates and moving towards cost-effective engineered substrates designated QST™ (Qromis Substrate Technology) [1]. The QST™ substrate is comprised of a core that is thermally matched to GaN, a series of thin films encapsulating the core, and an epi-ready Si (111) surface for GaN epitaxy. Through its coefficient of thermal expansion (CTE) match to GaN, the QST™ substrate enables a material platform for thick, low dislocation density epitaxial layers suitable for high voltage devices.
In this work, we present two fabrication processes enabled by QST™ substrates. First, true vertical GaN Schottky barrier diodes (SBDs) were designed from epitaxial GaN layers grown on large area (150 mm) QST™ substrates. The fabrication process is initiated with metal-organic chemical vapor deposition (MOCVD) of epitaxial GaN layers (2 μm GaN nucleation layer, 1.3 μm n+ GaN:Si contact layer with Nd = 5x1018 cm-3, and a 12.3 μm n- GaN drift layer Nd < 1x1016 cm-3) on the engineered QST™ substrate, followed by the deposition of Ni/Au (200 Å/2000 Å) Schottky contacts via a conventional lift-off procedure. The metal contacts and epitaxial GaN were then protected from the remaining etch steps with black wax and loaded metal face down onto a carrier substrate. A backside wet etch was used to selectively remove the QST™ substrate and transition layers. The backside contact was formed with 30 μm of electroplated Cu seeded by Ti/Au (100 Å/1000 Å). Lastly, the black wax was dissolved in xylene, releasing the freestanding vertical GaN device from the carrier substrate. Preliminary current-voltage experiments on true vertical GaN diodes fabricated without the 1.3 μm n+ GaN:Si contact layer (Nd = 5x1018 cm-3), edge termination, or surface passivation show a reverse breakdown voltage of 658 V, corresponding to a 0.58 MV/cm breakdown field.
Second, lateral junction field effect transistors (LJFETs) were designed from the following epitaxial GaN layers grown on large area (150 mm) QST™ substrates: 7 μm semi-insulating layer, 1-2 μm n-GaN channel, 0.2 μm p- and 0.2 μm p+ GaN layers, and a 0.2 μm p++ GaN contact cap. To etch the source/drain regions, patterned photoresist on the p++ layer was used as a hard mask for etching approximately 750 nm GaN. An ohmic contact to the n-GaN was formed with Ti/Al/Ni/Au (200 Å/ 1200 Å/ 400 Å/ 800 Å), followed by a 30-second rapid thermal anneal at 850 °C in nitrogen gas. The Pd/Au (200 Å/ 1000 Å) gate metal was deposited on the p-GaN. Preliminary results demonstrate FET modulation. Improvement in the quality of the p layers is expected to improve performance. Moreover, the QST™ substrates provide an economical platform for optimizing epitaxial growth conditions to reach peak device performance. The feasible fabrication processes and promising preliminary results described in this work underline the potential of engineered GaN substrates for producing low cost vertical and lateral power devices.
Reference: [1] Travis J. Anderson et al 2017 Appl. Phys. Express
10 126501.