Study on Influence of O2 Concentration in Wafer Cleaning Ambient for Smoothness of Silicon (110) Surface Appearing at Sidewall of Three-Dimensional Transistors
Authors: Suwa Tomoyuki , Teramoto Akinobu , Shirai Yasuyuki , Matsuo Takenobu , Mizutani Nobutaka , Sugawa Shigetoshi 
Published: May 2020

The Si(110) surface appears at the sidewall of 3D transistors such as FinFET [1,2]. The surface micro-roughness of Si(110) strongly affects to the device characteristics because the Si(110) sidewall surface have a higher proportion of channel region width the miniaturization of width of fin structure [1,2]. In this work, we investigated the ambient in the wafer cleaning process to keep the smoothness of Si(110) surface.
The wafers used in this study were Cz p-type Si(110) substrates having nearly 10 Ωcm. The wet oxidation of these substrates was performed at 1000 °C to form 300nm-thick silicon oxide films. Just after this oxide films were removed by HF solution, the average surface microroughness (Ra) of Si(110) measured by atomic force microscopy (AFM) was about 0.073 nm. We evaluated the influence of O2 concentration during the immersion in ultra pure water (UPW) by using N2 sealed glove box. The N2 sealed glove box can be controlled O2 concentration from 20% to 30 ppm. After the removing the chemical oxide with a diluted HF (0.5wt %) solution in this glove box with O2 concentration of 100 ppm, the wafers were immersed in UPW. We also evaluated for SOI wafer (20nm-thick Si(110) layer / 400nm-thick BOX layer / 725μm-thick Si(110) substrate) in a similar way.
Figure 1 shows AFM images of Si(110) surface (a) before and after immersion in UPW for 24 hour in (b) 20% O2 (atmosphere) and (c) N2 ambient with O2 concertation less than 100ppm by using glove box. Ra drastically increase in the case of 20% O2 concentration. On the other hand, the increase of Ra is suppressed in N2 ambient with O2 concertation less than 100ppm. This indicates that the controlling of O2 concertation of ambient during the immersion in UPW is very effective to suppress the increase of Ra of Si(110) surface. It has been reported that the increase of Ra is caused by Si dissolving in UPW and Si dissolving in UPW is caused by the local oxidation just on Si surface [3,4].
Figure 2 shows AFM images of Si(110) surface after immersion in UPW for 1, 3 and 24 hour in N2 ambient with O2 concertation of 100ppm. During the immersion in UPW, the O2 concentration was held 100 ppm. Figure 3 shows Ra as a function of immersion time for Si(110) surface in N2 ambient with O2 concertation of 100ppm. As increasing immersion time, the Ra is increasing. In addition, the line-formed roughness to <110> direction and the local bumps are appeared on the Si(110) surface. However, the Ra of immersion for 1 hour is not almost change from the initial Ra. Moreover, Si atoms eluted in UPW for 24 hours calculated from the decrease of SOI thickness was less than 4.0×1014/cm2 per 1hour. This means that the amount of elution of Si atoms in UPW within 1 hour is less than 1 atomic layer because the areal density of Si(110) orientation substrate is 9.6×1014/cm2 [5]. In the actual wafer cleaning process, the time of UPW attaching to wafer surface is far shorter than 1 hour. Therefore, when the O2 concentration is controlled less than 100ppm in the wafer cleaning process, it can be expected that Si(110) surface of sidewall of 3D transistor is not roughened and the shape of Si fin structure is kept. Furthermore, we evaluate the O2 concentration by using the prototype 200mm single wafer cleaning chamber. We demonstrated that the O2 concentration in this chamber can be decreased less than 100ppm within 1 minute by N2 purge of 200 L/min.
Acknowledgements
This work is based on results obtained from a project commissioned by the New Energy and Industrial Technology Development Organization (NEDO) and was carried out at the Fluctuation Free Facility (FFF) of New Industry Creation Hatchery Center, Tohoku University.
Reference
[1] D. James, 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), pp. 324-329, May 2016.
[2] A. Teramoto et al., IEEE Trans. Electron Devices, vol 54, No 6, pp. 1438-1443, 2007.
[3] H. Morinaga, et al., Solid State Phenomena, Vol.134, pp.45-48, 2007.
[4] K. Nii, et al., 206th Meeting of The Electrochemical Society, 2004.
[5] M. Higuchi, et al., Appl. Phys. Lett. 90 Number 12, pp. 123114-1-123114-3, 2007.

Figure 1