bluuebunny/crossref_metadata_2025_split huggingface dataset:
Why you should care about quantile regression
Authors: de Oliveira Augusto Born , Fischmeister Sebastian , Diwan Amer , Hauswirth Matthias , Sweeney Peter F. 
Published: April 2020

Research has shown that correctly conducting and analysing computer performance experiments is difficult. This paper investigates what is necessary to conduct successful computer performance evaluation by attempting to repeat a prior experiment: the comparison between two Linux schedulers.
In our efforts, we found that exploring an experimental space through a series of incremental experiments can be inconclusive, and there may be no indication of how much experimentation will be enough. Analysis of variance (ANOVA), a traditional analysis method, is able to partly solve the problems with the previous approach, but we demonstrate that ANOVA can be insufficient for proper analysis due to the requirements it imposes on the data.
Finally, we demonstrate the successful application of quantile regression, a recent development in statistics, to computer performance experiments. Quantile regression can provide more insight into the experiment than ANOVA, with the additional benefit of being applicable to data from any distribution. This property makes it especially useful in our field, since non-normally distributed data is common in computer experiments.
Verifying systems rules using rule-directed symbolic execution
Authors: Cui Heming , Hu Gang , Wu Jingyue , Yang Junfeng 
Published: April 2020

Systems code must obey many rules, such as "opened files must be closed." One approach to verifying rules is static analysis, but this technique cannot infer precise runtime effects of code, often emitting many false positives. An alternative is symbolic execution, a technique that verifies program paths over all inputs up to a bounded size. However, when applied to verify rules, existing symbolic execution systems often blindly explore many redundant program paths while missing relevant ones that may contain bugs.
Our key insight is that only a small portion of paths are relevant to rules, and the rest (majority) of paths are irrelevant and do not need to be verified. Based on this insight, we create WOODPECKER, a new symbolic execution system for effectively checking rules on systems programs. It provides a set of builtin checkers for common rules, and an interface for users to easily check new rules. It directs symbolic execution toward the program paths relevant to a checked rule, and soundly prunes redundant paths, exponentially speeding up symbolic execution. It is designed to be heuristic-agnostic, enabling users to leverage existing powerful search heuristics.

Evaluation on 136 systems programs totaling 545K lines of code, including some of the most widely used programs, shows that, with a time limit of typically just one hour for each verification run, WOODPECKER effectively verifies 28.7% of the program and rule combinations over bounded input, whereas an existing symbolic execution system KLEE verifies only 8.5%. For the remaining combinations, WOODPECKER verifies 4.6 times as many relevant paths as KLEE. With a longer time limit, WOODPECKER verifies much more paths than KLEE,
e.g.,
17 times as many with a fourhour limit. WOODPECKER detects 113 rule violations, including 10 serious data loss errors with 2 most serious ones already confirmed by the corresponding developers.
Demand-based coordinated scheduling for SMP VMs
Authors: Kim Hwanju , Kim Sangwook , Jeong Jinkyu , Lee Joonwon , Maeng Seungryoul 
Published: April 2020

As processor architectures have been enhancing their computing capacity by increasing core counts, independent workloads can be consolidated on a single node for the sake of high resource efficiency in data centers. With the prevalence of virtualization technology, each individual workload can be hosted on a virtual machine for strong isolation between co-located workloads. Along with this trend, hosted applications have increasingly been multithreaded to take advantage of improved hardware parallelism. Although the performance of many multithreaded applications highly depends on communication (or synchronization) latency, existing schemes of virtual machine scheduling do not explicitly coordinate virtual CPUs based on their communication behaviors.
This paper presents a demand-based coordinated scheduling scheme for consolidated virtual machines that host multithreaded workloads. To this end, we propose communication-driven scheduling that controls time-sharing in response to inter-processor interrupts (IPIs) between virtual CPUs. On the basis of in-depth analysis on the relationship between IPI communications and coordination demands, we devise IPI-driven coscheduling and delayed preemption schemes, which effectively reduce synchronization latency and unnecessary CPU consumption. In addition, we introduce a load-conscious CPU allocation policy in order to address load imbalance in heterogeneously consolidated environments. The proposed schemes are evaluated with respect to various scenarios of mixed workloads using the PARSEC multithreaded applications. In the evaluation, our scheme improves the overall performance of consolidated workloads, especially communication-intensive applications, by reducing inefficient synchronization latency.
Examining a Large Keystroke Biometrics Dataset for Statistical-Attack Openings
Authors: Serwadda Abdul , Phoha Vir V. 
Published: April 2020

Research on keystroke-based authentication has traditionally assumed human impostors who generate forgeries by physically typing on the keyboard. With bots now well understood to have the capacity to originate precisely timed keystroke sequences, this model of attack is likely to underestimate the threat facing a keystroke-based system in practice. In this work, we investigate how a keystroke-based authentication system would perform if it were subjected to synthetic attacks designed to mimic the typical user. To implement the attacks, we perform a rigorous statistical analysis on keystroke biometrics data collected over a 2-year period from more than 3000 users, and then use the observed statistical traits to design and launch algorithmic attacks against three state-of-the-art password-based keystroke verification systems.
Relative to the zero-effort attacks typically used to test the performance of keystroke biometric systems, we show that our algorithmic attack increases the mean Equal Error Rates (EERs) of three high performance keystroke verifiers by between 28.6% and 84.4%. We also find that the impact of the attack is more pronounced when the keystroke profiles subjected to the attack are based on shorter strings, and that some users see considerably greater performance degradation under the attack than others. This article calls for a shift from the traditional zero-effort approach of testing the performance of password-based keystroke verifiers, to a more rigorous algorithmic approach that captures the threat posed by today’s bots.
Ubik
Authors: Kasture Harshad , Sanchez Daniel 
Published: April 2020

Chip-multiprocessors (CMPs) must often execute workload mixes with different performance requirements. On one hand, user-facing, latency-critical applications (e.g., web search) need low tail (i.e., worst-case) latencies, often in the millisecond range, and have inherently low utilization. On the other hand, compute-intensive batch applications (e.g., MapReduce) only need high long-term average performance. In current CMPs, latency-critical and batch applications cannot run concurrently due to interference on shared resources. Unfortunately, prior work on quality of service (QoS) in CMPs has focused on guaranteeing average performance, not tail latency.
In this work, we analyze several latency-critical workloads, and show that guaranteeing average performance is insufficient to maintain low tail latency, because microarchitectural resources with state, such as caches or cores, exert inertia on instantaneous workload performance. Last-level caches impart the highest inertia, as workloads take tens of milliseconds to warm them up. When left unmanaged, or when managed with conventional QoS frameworks, shared last-level caches degrade tail latency significantly. Instead, we propose Ubik, a dynamic partitioning technique that predicts and exploits the transient behavior of latency-critical workloads to maintain their tail latency while maximizing the cache space available to batch applications. Using extensive simulations, we show that, while conventional QoS frameworks degrade tail latency by up to 2.3x, Ubik simultaneously maintains the tail latency of latency-critical workloads and significantly improves the performance of batch applications.
Deterministic galois
Authors: Nguyen Donald , Lenharth Andrew , Pingali Keshav 
Published: April 2020

Non-determinism in program execution can make program development and debugging difficult. In this paper, we argue that solutions to this problem should be on-demand, portable and parameterless. On-demand means that the programming model should permit the writing of non-deterministic programs since these programs often perform better than deterministic ones for the same problem. Portable means that the program should produce the same answer even if it is run on different machines. Parameterless means that if there are machine-dependent scheduling parameters that must be tuned for good performance, they must not affect the output.
Although many solutions for deterministic program execution have been proposed in the literature, they fall short along one or more of these dimensions. To remedy this, we propose a new approach, based on the Galois programming model, in which (i) the programming model permits the writing of non-deterministic programs and (ii) the runtime system executes these programs deterministically if needed. Evaluation of this approach on a collection of benchmarks from the PARSEC, PBBS, and Lonestar suites shows that it delivers deterministic execution with substantially less overhead than other systems in the literature.
VSwapper
Authors: Amit Nadav , Tsafrir Dan , Schuster Assaf 
Published: April 2020

The number of guest virtual machines that can be consolidated on one physical host is typically limited by the memory size, motivating memory overcommitment. Guests are given a choice to either install a "balloon" driver to coordinate the overcommitment activity, or to experience degraded performance due to uncooperative swapping. Ballooning, however, is not a complete solution, as hosts must still fall back on uncooperative swapping in various circumstances. Additionally, ballooning takes time to accommodate change, and so guests might experience degraded performance under changing conditions.
Our goal is to improve the performance of hosts when they fall back on uncooperative swapping and/or operate under changing load conditions. We carefully isolate and characterize the causes for the associated poor performance, which include various types of superfluous swap operations, decayed swap file sequentiality, and ineffective prefetch decisions upon page faults. We address these problems by implementing VSwapper, a guest-agnostic memory swapper for virtual environments that allows efficient, uncooperative overcommitment. With inactive ballooning, VSwapper yields up to an order of magnitude performance improvement. Combined with ballooning, VSwapper can achieve up to double the performance under changing load conditions.
Cross-Kernel Control-Flow--Graph Analysis for Event-Driven Real-Time Systems
Authors: Dietrich Christian , Hoffmann Martin , Lohmann Daniel 
Published: April 2020

Embedded real-time control systems generally have a dedicated purpose and fixed set of functionalities. This manifests in a large amount of implicit and explicit static knowledge, available already at compile time. Modern compilers can extract and exploit this information to perform extensive whole-program analyses and interprocedural optimizations. However, these analyses typically end at the application--kernel boundary, thus control-flow transitions between different threads are not covered, yet. This restriction stems from the pessimistic assumption of a probabilistic scheduling policy of the underlying operating system, impeding detailed predictions of the overall system behavior. Real-time operating systems, however, do provide deterministic and exactly specified scheduling decisions, as embedded control systems rely on a timely and precise behavior.
In this paper, we present an approach that incorporates the RTOS semantics into the control-flow analysis, to cross the application--kernel boundary. By combining operating system semantics, the static system configuration and the application logic, we determine a cross-kernel control-flow--graph, that provides a global view on all possible execution paths of a real-time system. Having this knowledge at hand, enables us to tailor the operating system kernel more closely to the particular application scenario. On the example of a real-world safety-critical control system, we present two possible use cases: Run-time optimizations, by means of specialized system calls for each call site, allow to speed up the kernel execution path by 33 percent in our benchmark scenario. An automated generation of OS state assertions on the expected system behavior, targeting transient hardware fault tolerance, leverages significant robustness improvements.
Conference reports
Authors: Pérez Jorge A. 
Published: April 2020

This installment of the conference report column includes two nice personal recollections on two recent (and closely related) events on programming language research:
---Fritz Henglein (University of Copenhagen, Denmark) offers some personal impressions on POPL 2016: the 43rd ACM Symposium on Principles of Programming Languages, which took place in St. Petersburg, Florida, during January 20-22, 2016.
POPSTAR
Authors: Delaune Stéphanie 
Published: April 2020

The shrinking size of microprocessors as well as the ubiquity of wireless communication have led to the proliferation of portable computing devices with novel security requirements. Whereas traditional security protocols achieve their security goals relying solely on cryptographic primitives like encryptions and hash functions, the protocols employed to secure these devices establish and rely in addition on properties of the physical world. For instance, they may use, as basic building blocks, protocols for ensuring physical proximity, secure localisation, or secure neighbourhood discovery.
The aim of the POPSTAR ERC project is to develop techniques and tools to analyse protocols that establish and rely on properties of the physical world. We foresee that, at the end of the project, appropriate verification tools will be available to analyse the security and privacy of these "physical protocols". The research community in logics, program verification, and security has already a long tradition in developing techniques and tools to analyse key establishment and authentication protocols. Distance bounding protocols which are used to provide secure proximity control, raise new research challenges, and can not be analysed today using off-the-shelf verification tools.
Session details: Selected extended papers from SBESC 2012 Brazilian symposium on computing system engineering
Authors: de Faria Corrêa Edgard , Kreutz Marcio Eduardo 
Published: April 2020

The Brazilian Symposium on Computing System Engineering (SBESC) is an initiative of the research community originally associated with three events: the Brazilian Workshop on Real-Time Systems, created in 1998; the Brazilian Workshop on Operating Systems, created in 2004; and the Brazilian Workshop on Embedded Systems, created in 2010. The identification of a strong synergy among these research areas added to the fact that designing computing systems is an increasingly multidisciplinary task has motivated the workshops to move from their native conferences to form an independent symposium. The broad term "Computing System Engineering" emerged in the context of contemporary Cyber-Physical Systems, which challenge Engineers and Scientist as they shape a new reality for modern societies.
This year, the symposium was hosted by the Federal University of Rio Grande do Norte (UFRN) in the beautiful coastal city of Natal in Northeast Brazil. The program spanned a whole week, from November 5 to 9, and was organized in two big blocks: peer-reviewed paper sessions and tutorials. The event was organized by UFRN's Computer Science Department (DIMAP), sponsored by the Brazilian Computing Society (SBC), and financed by CAPES, CNPq, and FAPERN.
SBESC's Technical Program Committee also selected two papers from those presented at the symposium addressing operating systems issues to appear in the Operating Systems Review and thus offer ACM fellows a glimpse of the event. Authors were invited to extend and improve their manuscripts with recent research results. The first paper, On the Formal Verification of Component-based Embedded Operating Systems, by M. Ludwich and A. Frohlich, introduces an approach to formally verify the functional correctness and safety properties of embedded operating system components described at system-level. The convergence between software and hardware in the domain of embedded systems is pressing operating systems in the filed to deliver their services both as software and as hardware. In such a scenario, it is desirable to verify system properties regardless of whether components are instantiated as software or hardware. The approach combines software model checking and programming by contract concepts to address such issues. The second, Adaptive Request Batching for Byzantine Replication, by A. de Sa, A. Freitas, and R. Macedo, proposes an adaptation of the Practical Byzantine Fault Tolerance algorithm proposed by Liskov and Castro to increase its performance. The original PBFT algorithm uses a batch to store client requests on the primary replica. Requests in a batch are handled together, aiming at decreasing the time spent with message authentication. The adaptation strategy dynamically varies the batch size and the batch time-out according with application activity.
Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays
Authors: Jamal Al-Shahna , Cahill Eli , Goeders Jeffrey , Wilton Steven J. E. 
Published: April 2020

High-level synthesis (HLS) has gained considerable traction over recent years, as it allows for faster development and verification of hardware accelerators than traditional RTL design. While HLS allows for most bugs to be caught during software verification, certain non-deterministic or data-dependent bugs still require debugging the actual hardware system during execution. Recent work has focused on techniques to allow designers to perform in-system debug of HLS circuits in the context of the original software code; however, like RTL debug, the user must still determine the root cause of a bug using small execution traces, with lengthy debug turns.
In this work, we demonstrate techniques aimed at reducing the time HLS designers spend performing in-system debug. Our approaches consist of performing data dependency analysis to guide the user in selecting which variables are observed by the debug instrumentation, as well as an associated debug overlay that allows for rapid reconfiguration of the debug logic, enabling rapid switching of variable observation between debug iterations. In addition, our overlay provides additional debug capability, such as selective function tracing and conditional buffer freeze points. We explore the area overhead of these different overlay features, showing a basic overlay with only a 1.7% increase in area overhead from the baseline debug instrumentation, while a deluxe variant offers 2×--7× improvement in trace buffer memory utilization with conditional buffer freeze support.
Targeted Inhibition of the E3 Ligase SCFSkp2/Cks1 Has Antitumor Activity in RB1-Deficient Human and Mouse Small-Cell Lung Cancer
Authors: Zhao Hongling , Iqbal Niloy J. , Sukrithan Vineeth , Nicholas Cari , Xue Yingjiao , Yu Cindy , Locker Joseph , Zou Juntao , Schwartz Edward L. , Zhu Liang 
Published: April 2020

Abstract

The RB1 tumor suppressor gene is mutated in highly aggressive tumors including small-cell lung cancer (SCLC), where its loss, along with TP53, is required and sufficient for tumorigenesis. While RB1-mutant cells fail to arrest at G1–S in response to cell-cycle restriction point signals, this information has not led to effective strategies to treat RB1-deficient tumors, as it is challenging to develop targeted drugs for tumors that are driven by the loss of gene function. Our group previously identified Skp2, a substrate recruiting subunit of the SCF-Skp2 E3 ubiquitin ligase, as an early repression target of pRb whose knockout blocked tumorigenesis in Rb1-deficient prostate and pituitary tumors. Here we used genetic mouse models to demonstrate that deletion of Skp2 completely blocked the formation of SCLC in Rb1/Trp53-knockout mice (RP mice). Skp2 KO caused an increased accumulation of the Skp2-degradation target p27, a cyclin-dependent kinase inhibitor, which was confirmed as the mechanism of protection by using knock-in of a mutant p27 that was unable to bind to Skp2. Building on the observed synthetic lethality between Rb1 and Skp2, we found that small molecules that bind/inhibit Skp2 have in vivo antitumor activity in mouse tumors and human patient-derived xenograft models of SCLC. Using genetic and pharmacologic approaches, antitumor activity was seen with Skp2 loss or inhibition in established SCLC primary lung tumors, in liver metastases, and in chemotherapy-resistant tumors. Our data highlight a downstream actionable target in RB1-deficient cancers, for which there are currently no targeted therapies available.

Significance:
There are no effective therapies for SCLC. The identification of an actionable target downstream of RB1, inactivated in SCLC and other advanced tumors, could have a broad impact on its treatment.
CD226hiCD8+ T Cells Are a Prerequisite for Anti-TIGIT Immunotherapy
Authors: Jin Hyung-seung , Ko Minkyung , Choi Da-som , Kim June Hyuck , Lee Dong-hee , Kang Seong-Ho , Kim Inki , Lee Hee Jin , Choi Eun Kyung , Kim Kyu-pyo , Yoo Changhoon , Park Yoon 
Published: April 2020

Abstract
Clinical trials are evaluating the efficacy of anti-TIGIT for use as single-agent therapy or in combination with programmed death 1 (PD-1)/programmed death-ligand 1 blockade. How and whether a TIGIT blockade will synergize with immunotherapies is not clear. Here, we show that CD226loCD8+ T cells accumulate at the tumor site and have an exhausted phenotype with impaired functionality. In contrast, CD226hiCD8+ tumor-infiltrating T cells possess greater self-renewal capacity and responsiveness. Anti-TIGIT treatment selectively affects CD226hiCD8+ T cells by promoting CD226 phosphorylation at tyrosine 322. CD226 agonist antibody-mediated activation of CD226 augments the effect of TIGIT blockade on CD8+ T-cell responses. Finally, mFOLFIRINOX treatment, which increases CD226hiCD8+ T cells in patients with pancreatic ductal adenocarcinoma, potentiates the effects of TIGIT or PD-1 blockade. Our results implicate CD226 as a predictive biomarker for cancer immunotherapy and suggest that increasing numbers of CD226hiCD8+ T cells may improve responses to anti-TIGIT therapy.