bluuebunny/crossref_metadata_2025_split huggingface dataset:
(Invited) Towards Topological Antiferromagnetic Spintronics
Authors: He Qinglin , Pan Lei , Murata Koichi , Wang Kang L. 
Published: February 2020

Magnetic topological insulators in the tetradymite family, such as Cr/V doped Bi2Se3, Bi2Te3, Sb2Te3, and their ternary compounds, provide a new route for realizing the novel time-reversal symmetry-breaking physics [1, 2]. To effectively manipulate these versatile quantum states, various heterostructures are demonstrated by utilizing the unique Néel order in an antiferromagnet CrSb and the topological order in a magnetic topological insulator Cr-doped (Bi,Sb)2Te3 [3-5] grown by molecular beam epitaxy. It is shown that emergent interfacial magnetic interactions can be tailored through deliberate artificial structural engineering. By investigating bilayers, trilayers, and superlattices made of these two components, interfacial exchange coupling and antiferromagnetic exchange coupling were shown to affect the topological magnetism as mediated by the massive Dirac fermions. The relationship of magnetic spin textures of the antiferromagnet to that of the magnetic topological insulator was further explored through polarized neutron reflectometry/diffraction, magneto-electrical transport measurements as well as the control of the mass of Dirac fermions by using different Cr doping concentrations. From these studies, the antiferromagnet is shown to be an efficient interfacial- and interlayer- exchange coupling layer for the massive Dirac fermions of the magnetic topological insulator, which additionally gives rise to a giant enhancement in magnetic ordering. This work provides a new framework for new topological antiferromagnetic spintronics.
*The work was in part supported by the SHINES Center, an Energy Frontier Research Center funded by the U.S. Department of Energy, Office of Science, Basic Energy Sciences under Award # S000686, National Science Foundation, Army Research Office program under contract 15-1-10561, TANMS, FAME Center, and a Semiconductor Research Corporation program sponsored by MARCO and DARPA. References:
[1] Y. L. Chen et al., Science
329, 659 (2010).
[2] X.-L. Qi, T. L. Hughes, and S.-C. Zhang, Physical Review B
78, 195424 (2008).
[3] X. Kou et al., Nature Communications
6, 8474 (2015).
[4] X. Kou et al., Physical Review Letters
113, 137201 (2014).
[5] Y. Fan et al., Nature Materials
13, 699 (2014).
(Invited) Monolithic Integration of n-In0.53Ga0.47As and p-Ge FinFETs on Si
Authors: Chang Shih-Pang , Lin Kun-Lin , Wu Chien-Ting , Chen Cheng-Yu , Chen Mon-Yang , Lee Rong-Ren , Hsu Wen-Da , Chen Shih-Hong , Su Chun-Jung , Luo Guang-Li , Lee Shih-Chang , Hsu Ta-Cheng , Yeh Wen-Kuan , Chyi Jen-Inn 
Published: February 2020

With continuous increase in transistor count and clock frequency, the power density of current Si integrated circuits has reached a level that calls for a revolutionary change in transistor technology. High hole mobility Ge and high electron mobility InGaAs have been considered to be the most promising channel materials for p-channel and n-channel MOSFETs, respectively. Selective-area growth (SAG) on nano-trenches has been quite popular in integrating III-V materials with Si substrates. Since there exists a high lattice mismatch between III-V materials and Si, obtaining defect-free epilayer is still a great challenge. In this work, we demonstrate selective area growth of InGaAs on Ge trenches aiming at integrating n-channel InGaAs FinFETs and p-channel Ge FinFETs side by side on a Si substrate for CMOS applications.
The Ge templates, which were grown on Si by chemical vapor deposition, were prepared by etching through an oxide mask using a dilute H2O2 solution to create Ge linear trench structures with embedded {111} facets at the bottom of the trenches for facilitating the regrowth of III-V materials. The III-V materials were selectively grown on the patterned Ge templates by metal-organic vapor phase epitaxy. An InGaP buffer layer, which has a wide bandgap and is beneficial for electrical isolation between the channel and substrate, was grown onto the Ge trenches. Undoped InGaAs was grown on InGaP as the n-channel material.
High resolution transmission microscopy investigations show that very few dislocations are present near the Ge/InGaP interface in the trenches. It is found that In content of InGaP increases from 50 % to about 70 % with growth as evidenced by energy-dispersive x-ray spectroscopy (EDX). Interestingly, composition grading is also observed on the subsequently grown InGaAs. It begins from an In0.21Ga0.79As layer, which has good lattice match to the In0.7Ga0.3P layer beneath, then changes to the nominal In0.71Ga0.29As layer near the top of the fin. The strain in InGaAs is partially released through the generation of dislocations near the InGaAs/InGaP interface, leading to a nearly defect-free region at the top of the fin. A growth mechanism is proposed to account for the correlation between strain accommodation, composition grading, and defects generation.
Behaviors of GaSb and InSb III-V Semiconductor Surfaces in the Wet Chemical Solutions
Authors: Lim Sangwoo , Seo Dongwan , Na Jihoon , Oh Eunseok 
Published: February 2020

III–V compound semiconductors can be used as new channel materials because of their high carrier mobilities and low power consumption. Among various III–V compound semiconductor materials, Sb-based III-V semiconductors such as gallium antimonide (GaSb) and indium antimonide (InSb) are also gaining attention as a channel material, because they have extremely high carrier mobilities and an excellent lattice matches with various III–V ternary and quaternary compounds. However, Sb-based III-V semiconductors are easily oxidized by atmospheric oxygen and forms native oxide layers. Therefore, effective surface preparation with an understanding of its surface chemistry is required. However, the reaction kinetics in the cleaning / surface preparation process and the mechanisms of etching and oxidation in the overall process have not yet been elucidated. In the current study, the effect of representative wet treatments in acidic and basic solutions on the GaSb and InSb surface behavior is studied.
When GaSb and InSb were treated in acidic hydrochloric acid - hydrogen peroxide mixture (HPM) solutions, the etching rates and oxide layer thicknesses of both GaSb and InSb surfaces decreased, and the contact angles increased as the H2O2 concentration was decreased by dilution. In addition, the results of the XPS measurements confirmed that the XPS Ga3d and In3d5
/2 peak area ratios of Ga2O3/GaSb and In2O3/InSb decreased with decreasing H2O2 concentration in HPM. Based on the observed results, it is suggested that H2O2 serves as a strong oxidant in acidic HPM solutions and the overall surface reaction of GaSb and InSb in HPM solution depends on the surface oxidation by H2O2. In addition, the Sb 3d3/2 peak area ratios of Sb2O3/GaSb (or Sb2O3/InSb) were not significantly changed with H2O2 concentration in HPM. Therefore, it is thought that the surface oxidation behavior of Sb-based materials is determined by the group III elements, Ga and In, rather than the group V element, Sb. On the other hand, in basic ammonium hydroxide - hydrogen peroxide mixture (APM) solutions, H2O2 tends to decompose into OH-, etching species, so that Ga atoms on the GaSb surface or in the Ga oxide can be etched by OH- to form aqueous H2GaO3
- ions. Therefore, H2O2 cannot contribute to the oxidation of GaSb in basic APM solutions, but the surface oxidation of GaSb is accelerated as the solution is diluted by H2O. In APM solution, H2O works as an oxidant on the GaSb and InSb surfaces.
Characterization of Aggregated Carbon Compounds at SiO2/SiC Interface after Plasma Oxidation at Near Room Temperature
Authors: Arima Kenta , Hosoo Kohei , Ito Ryota , Saito Naoki , Kawai Kentaro , Sano Yasuhisa , Morita Mizuho 
Published: February 2020

Si sublimation from a silicon carbide (SiC) surface at elevated temperatures is a convenient and simple method of forming graphene [1]. The increase in carbon concentration at the monolayer scale on SiC prior to graphene growth is the key to obtaining graphene with reduced pit density. There have been some attempts to achieve this, one example of which is the use of vacuum evaporation from a solid carbon source [2, 3]. We have proposed a novel chemical route to enrich the carbon concentration on SiC. Namely, we have found that aggregated carbon compounds with a few monolayers are formed when an initial hexagonal SiC surface is treated by plasma oxidation at near room temperature and then the oxide layer (SiO2) with a thickness of ~10 nm is stripped off by HF etching [4, 5]. No additional carbon clusters were formed in the conventional thermal oxidation of SiC at 1000°C. Neither the composition of the aggregated compounds nor the mechanism of the generation of such carbon species by the plasma-assisted procedure is clear, however.

In this study, we reveal that, after the plasma oxidation followed by wet etching, the SiC surface is more hydrophobic than the initial SiC surface terminated by hydroxyls. Taking the electronegativities of Si, C and O atoms into account, this result indicates the formation of C-O and C-C, which is confirmed by the chemical-shift analyses of O1s and C1s spectra taken by X-ray photoelectron spectroscopy.

In thermal oxidation, it is widely accepted that the reaction (2SiC+3O2 -> 2SiO2+2CO) forms a SiO2 layer whereas CO molecules diffuse into the oxide and are finally emitted in the gas phase. However, it has also been reported that CO molecules can diffuse a high-quality SiO2 film at temperatures higher than 900°C [6]. It is reasonable to suppose that, in the case of plasma oxidation at near room temperature, CO molecules reside at the SiO2/SiC interface and form carbon compounds. In addition, a consideration based on thermodynamics implies the direct formation of solid carbon clusters during oxidation at low temperatures by the reaction SiC+O2 -> SiO2+C(s) [7]. These growth kinetics of SiO2 on SiC well explain the obtained results described in the previous paragraph.

Such a carbon residue at the SiO2/SiC interface can degrade the performance of metal-oxide-semiconductor (SiC) devices. But it may serve as an additional carbon source for epitaxial graphene growth on SiC.

[1] C. Berger et al., J. Phys. Chem. B, 108, 19912 (2004).

[2] A. Al-Temimy et al., Appl. Phys. Lett., 95, 231907 (2009).

[3] J. Park et al., Adv. Mater., 22, 4140 (2010).

[4] N. Saito, K. Arima et al., Carbon, 80, 440-445 (2014).

[5] N. Saito, K. Arima et al., ECS Transactions, 64, 17, 23 (2014).

[6] O.H. Krafcsik et al., Jpn. J. Appl. Phys. 40, 2197 (2001).

[7] K. Kita et al., ECS Transactions, 64, 8, 23 (2014).
The Roles of Band Bending, Surface Misorientation, and Passivation on Electrical Transport Across III-V Bonded Structures
Authors: Yee Matthew , Liao Michael , Seal Mark , Goorsky Mark S. 
Published: February 2020

The electrical conductivity across a variety of III-V semiconductor wafer pairs can be assessed through an understanding of the surface band bending expected prior to bonding as well as the role that interfacial defects play. With results from bonding of several different materials combinations, surface orientations, and passivation treatments, as well as an assessment of barrier heights reported in the literature for transport in polycrystalline III-V materials as well as for other III-V bonded materials combinations, a general model has emerged. Lattice mismatch does not play a major role in limiting conductivity across an interface; however, misalignment (through twist or tilt) produces interfaces with increased resistance. Passivation techniques are most important for systems with significant surface band-bending; for III-V surfaces that do not exhibit signifncant band-bending there is only a slight improvement associated with a sulfur-based pre-bonding passivation step. The electrical characteristics of a grain boundary, whether in polcrystalline material or at a bonded interface, are determined by the presence of defect states and interfacial charge which creates band bending and Fermi level pinning. The barrier heights and widths from zero bias conductance vs bias measurements over a wide range of temperatures and for different materials can be matched to band structure simulations of bonded semiconductor heterojunctions with resultant I-V curves showing good agreement between experiment and theory. Based on this study which combines experimental results and transport modelling, it is expected that narrow bandgap III-V semiconductors such as GaSb, InAs, and InSb would be ideal candidates for direct wafer bonding, even when bonded to materials with significant surface band bending, such as GaAs.
(Invited) Thermomechanical Finite Element Modeling of Cu-SiO2 Direct Hybrid Bonding with a Dishing Effect on Cu Surfaces
Authors: Estevez Rafael , Beilliard Y. , Parrr G. , McGarry P. , Coudrain P. , Di Cioccio L. 
Published: February 2020

Copper direct bonding technology is considered to be one of the most promising approaches for matching the miniaturization needs in future tridimensional integrated high performance circuits (3D-IC). However, the bonding mechanisms of copper surfaces with an initial dishing effect, induced by the polishing step, must be investigated in order to optimize the adhesion process and prevent further reliability issues. In this study, we present thermo-mechanical finite element simulations of Cu-SiO2 hybrid bonding with account for the annealing step and various amplitudes of the initial dishing. A cohesive interaction model that mimics nonlinear interactions between Cu/Cu and SiO2/SiO2 interfaces with related bonding mechanism is implemented within a nonlinear contact strategy. The overall bonding process along with the influence of the annealing conditions and the copper plastic response on the closure of the Cu/Cu interface are investigated.

Figure 1
Impact of Water Edge Absorption on Silicon Oxide Direct Bonding Energy
Authors: Fournel Frank , Tedjini Marwan , Larrey Vincent , Rieutord François , Morales Christophe , Bridoux Claudine , Moriceau Hubert 
Published: February 2020

Direct bonding of silicon and silicon dioxide thin films is now widely used in industry for SOI (Silicon on Insulator) elaboration for instance or in some backside imager manufacturing processes which are now at a stage of mass production processes. Silicon oxide capping layer is very often used as a convenient bonding layer allowing efficient topography planarization with classical CMP (Chemical Mechanical Planarization) process. Thus silicon oxide//silicon oxide direct bonding has been very developed when bonding interface behaviour deserves to be deeply studied. The bonding energy evolution is one of the key parameters and has been widely studied for many years [1,2,3]. Notably, water edge penetration at the bonding interface after the direct bonding was reported recently [4,5]. This work is then focused on the impact of water edge penetration on silicon oxide direct bonding energy values.
200 mm <001> silicon wafers are thermally oxidized at 950 °C under steam atmosphere in order to growth 145 nm of silicon dioxide thin film. After classical RCA cleaning, these wafers are bonded at room temperature and ambient pressure. Just after the bonding, they are diced into 2 cm wide beams and annealed at 300 °C for bonding energy measurement under anhydrous atmosphere [3]. But after the dicing, the atmospheric water can start to penetrate the direct bonding interface. Two times are then considered: t1 is the time between the dicing and the annealing steps and t2 is the time between the annealing and the energy measurement. The bonding energy dependence regarding t1 and t2 is studied.
It will be shown that increasing t1 is beneficial for the oxide/oxide bonding energy in contrary to t2 increase. A mechanism for bonding evolution will be proposed to explain these results mainly based on water stress corrosion influence. The annealing atmosphere will also be pointed out to explain some behaviours.
Recommendations for storage time and atmosphere as well as for annealing conditions could then be formulated to make bonding energy values at the wafer edge suitable for subsequent device elaborations.

REFERENCES

[1] G. Kräuter, A. Schumacher, U. Gösele, Sensors and Actuators A: Physical, Vol. 70 (3), 271–275 (1998).
[2] F. Fournel, C. Martin-Cocher, V. Larrey, H. Moriceau, F. Rieutord, WaferBond International Conference Brunswick Germany (2015)
[3] F. Fournel, L. Continni, C. Morales, J. Da Fonseca, H. Moriceau, F. Rieutord, A. Barthelemy, I. Radu, J. Appl. Phys., 111, 104907 (2012)
[4] M. Tedjini, F. Fournel, V. Larrey, F. Rieutord, WaferBond International Conference, Brunswick Germany (2015)
[5] M. Tedjini, F. Fournel, H. Moriceau, V. Larrey, D. Landru, O. Kononchuk, S. Tardif, F. Rieutord, Submitted to Journal of Applied Physics.
(Invited) Locally Measuring the Adhesion of InP Membranes Directly Bonded on Silicon
Authors: Patriarche Gilles , Pantzas Konstantinos , Le Bourhis Eric , Beaudoin Gregoire , Talneau Anne 
Published: February 2020

Direct bonding of III-V semiconductors on silicon has recently become a promising technology for the fabrication of hybrid photonic integrated circuits (PICs). In such hybrid PICs, active optical functions (amplification, emission) are ensured by the direct-gap III-V semiconductor and passive functions (guiding, switching) by the Si guiding layer. One particularly attractive feature of hybrid III-V/Si platforms is the possibility to densely integrate a variety of advanced optical functions in the guiding layer using sub-100 nm patterns in the silicon. Nano-patterning the silicon surface may, however, weaken the adhesion of the III-V semiconductor to silicon, potentially making the hybrid bonded stack subject to debonding in subsequent processing steps, such as cleaving. In this context, quantitatively assessing the adhesion of the III-V to Si in a patterned area and comparing it against the adhesion in a nearby unpatterned area can provide one with feedback useful for improving the patterning , post-patterning surface preparation, or bonding processes. Ultimately, such measurements can allow one to propose optimal designs for advanced embedded optical functions in hybrid III-V/Si PICs. Instrumented nanoindentation, Atomic Force Microscopy and Scanning Transmission Electron Microscopy have been combined ex situ to study the adhesion of thin InP membranes to bulk (100) silicon substrates but also to sub-100nm patterned (100) silicon substrates. Three distinct regimes are identified in the deformation of the InP/Si stacks during these experiments: the first is plastic flow of InP at low loads; the second is elastic debonding of the InP membrane, far from the indented zone at medium loads; lastly, the local amorphisation of the underlying Si substrate at high loads. The regime of intermediate loads is shown to be particularly useful in the evaluation of the surface bonding energy of InP to Si [1,2].
[1] K. Pantzas, E. Le Bourhis, G. Patriarche, A. Itawi, G. Beaudoin, I. Sagnes and A. Talneau Eur. Phys. J. Appl. Phys. 65 (2014) 20702
[2] K. Pantzas, E. Le Bourhis, G. Patriarche, D. Troadec, G. Beaudoin, A. Itawi, I. Sagnes and A. Talneau Nanotechnology 27 (2016) 115707
High Efficiency Cleaning Processes for Direct Wafer Bonding
Authors: Dussault Donald , Rothballer Jan , Kurz Florian , Reichardt Make , Dragoi Viorel 
Published: February 2020

Permanent direct wafer bonding has been an enabling technology for many years, especially in the areas of engineered substrates such as SOI, and in various MEMS or backside illuminated CMOS image sensors (BSI) process flows. With the emergence of new and more challenging bonding requirements and materials, precision and surface condition becomes more critical.
One key requirement for a void free and reliable bond is a particle free surface. Residual particulate remaining in the bonding interface can lead to post-bond voids, bond defects and loss of yield. The optimal post cleaning condition is zero particles, and in fact, one of the basic requirements of pre-bond cleaning methods is to be particle neutral, leaving no additional particles after the cleaning process. Historically the critical particle sizes were in the 1um range, but due to continuous feature size reduction, this critical size is today in the area of 90 nm with a strong pressure to reduce below 20 nm.
In prior work (reference 1) we have demonstrated a particle neutral cleaning process on 200 mm wafers in a laboratory environment. The cleaning method and MegPie® megasonic apparatus used in prior work is comparable to that used in the current experiments. In the prior experiments, the wafers were intentionally contaminated with large numbers of silicon nitride particles so that particle removal efficiency could be measured and compared to industry standards.
In this current work we have moved from laboratory generated artificial contamination to real word production conditions, including the unknown type and quantity of particulate that would be typical to incoming pre bond substrates. The results demonstrate the suitability and repeatability of this non contact cleaning method in real world production consitions.
The cleaning tests were performed on an EVG Gemini®FB fully automated fusion bonding system using for cleaning a large area megasonic transducer MegPie®

Particle measurement was performed using the KLA-Tencor SP1 Particle Counter and post bond performance was performed using the SAM450 from PVA Tepla Analytical Systems.
Reference
1. F. Fournel, L. Bally, D. Dussault, and V. Dragoi, Innovative megasonic cleaning technology evaluated through direct wafer bonding. (ECS 2010)