(Invited) Design and Reliability of GaN Power HEMT Technology
Authors: Shankar Bhawani , Soni Ankit , Dutta Gupta Sayak , Sengupta Rudrarup , Khand Heena , Mohan Nagboopathy , Raghavan Srinivasan , Bhat Navakanta , Shrivastava Mayank 
Published: February 2020

Gallium nitride (GaN) based high electron mobility transistors (HEMTs) are extensively being considered for power and RF applications by virtue of their unique properties. AlGaN/GaN HEMTs are depletion mode devices due to presence of high density 2DEG at the interface. However, enhancement mode devices prove beneficial for simpler and reliable power systems. F implant, p-GaN gate and AlGaN recess are some of the widely accepted processes to achieve the same. In spite of extensive research already being carried out in the domain, the search for a reliable technique for e-mode GaN with superior performance metric is still continued. A novel technique incorporating a p-type metal oxide in conjunction with partial recess of AlGaN has been established to demonstrate a high performing e-mode GaN/AlGaN HEMT. The p-type metal oxide helped in positive shift of the VTH which allowed the device to be e-mode even with partial recessing. This helped circumventing the challenges introduced by plasma damage in recess-based e-mode GaN HEMTs. Besides HEMTs, GaN based Schottky diodes have started gaining prominence for power applications. Schottky diodes with high ON current (1A/mm), 0.5 V cut in voltage and reduced reverse leakage were demonstrated by carrying out surface treatment post AlGaN recess. The high temperature anneals, and acid treatments helped reduce the surface damage induced due to plasma.
Technology CAD (TCAD) based design approach goes a long way in designing improved and reliable devices. Hence a consistent and reliable TCAD strategy that can be employed for HEMT analysis and design of high performance HEMTs is the need of the hour. The presence of unique polarization effects combined with traps, hot electrons and self-heating make reproducing accurate device behavior for HEMTs a challenging task. A well-defined Technology CAD strategy is developed for the first time for GaN HEMT, incorporating all the physical aspects pertaining to HEMT. The simulation setup was well calibrated with the experimental data. TCAD based Co-Design guidelines were proposed, which can be effectively utilized to optimize the design parameters for maximum RF and breakdown performance. Further novel designs- RESURF, Superjunction and Stepgate were proposed having high breakdown voltages. Comprehensive study was done to study the physical effect of surface traps and buffer traps on the breakdown performance.
GaN based HEMTs despite of its attractive performance/cost ratio, suffers from poor reliability which limits its penetration in the ever-growing power device market. Therefore, reliability of AlGaN/GaN HEMT is now a topic of intense research. The present understanding of underlying degradation physics needs to be improved further. Many aspects like ability of GaN HEMT to handle high power under extreme conditions and related SOA concerns are yet to be investigated. Characterization of HEMT can be done under dc and pulse stress. In pulse characterization, one can emulate real stress conditions present in power electronic circuits. On the fly dc I-V and C-V gives information about the device degradation whereas sub-bandgap UV is used to capture trapping effects. Besides, on the fly Raman captures evolution of piezoelectric/ thermal stress in HEMT. It has been observed that carrier trapping has significant impact on SOA of GaN HEMTs. High trap density causes electric field shift and peaking towards drain edge. The field enhancement at drain accelerates impact ionization and carrier injection into buffer leading to early filament formation. Non-uniform trapping along width triggers avalanche instability. The SOA boundary is found to deteriorate in OFF-state, due to compressive stress at drain-gate edge. ON-state SOA is also limited by tensile stress in the gate-to-drain region. The electric field profile in channel and buffer can be tuned by controlling the recess depth, which directly affects device degradation and SOA.

Figure 1