bluuebunny/crossref_metadata_2025_split huggingface dataset:
(Invited) Photocurrents in Topological Insulators Based on Hgte
Authors: Dantscher Kathrin-Maria , Ganichev Sergey D. 
Published: February 2020

The paper overviews experimental and theoretical studies of photocurrents induced in various Dirac fermions systems by polarized electromagnetic radiation. We consider second order opto-electronic phenomena [1,2] excited by terahertz radiation in topological insulators (TIs). In focus of our discussion are two- (2D) and three- (3D) dimensional HgTe-based topological TIs [3,4]. We present the state-of-the-art of the experiments, discuss the phenomenological and microscopic theory, and show that nonlinear transport excited by laser radiation opens up new opportunities for the probing of Dirac electrons. A particular attention is paid to the helicity sensitive edge photogalvanic currents in 2D TIs [5] and cyclotron resonance assisted spin polarized currents in 3D TIs [6] and HgTe/HgCdTe quantum wells of a critical thickness [7,8]. We demonstrate that cyclotron resonance induced photocurrents in the surface states of 3D TIs provides a sensitive method to probe the cyclotron masses of Dirac fermions, which can be applied even for micrometer sized structures, to measure Fermi velocity, and to study tiny details of the spin orientation in TIs, in particular, to explore the role of bulk and structure inversion asymmetry in the band structure.
[1] S.D. Ganichev and W. Prettl, Intense Terahertz Excitation of Semiconductors, Oxford University Press (2006)
[2] M.M. Glazov and S.D. Ganichev, Physics Reports 535 101-138 (2014)
[3] B.A. Bernevig, et al., Science 314, 1757 (2006)
[4] M.S. König, et al., Science 318, 766 (2007)
[5] Z.D. Kvon, et al., JETP Letters 99, 290-294 (2014)
[6] K.-M. Dantscher, et al., Phys. Rev. B 92, 165314 (2015)
[7] P. Olbrich, et al., Phys. Rev. B 87, 235439 (2013)
[8] C. Zoth, et al., Phys. Rev. B 90, 205415 (2014)
(Invited) Control of Thermally-Grown SiO2/4H-SiC Mos Interface Properties and Its Impact on Mosfet Performances
Authors: Kita Koji , Hirai Hirohisa , Fujino Yuki , Kajifusa Hiroyuki 
Published: February 2020

4H-SiC MOSFETs is extensively studied for high-voltage power device applications, however, the control of MOS interface properties have been one of the most challenging issues to meet the requirements of low on-resistivity and high-reliability. It is a challenging issue to reduce interface defect density at thermally oxidized SiO2/SiC interfaces since the thermal oxidation is inevitably accompanied with by a carbon-related product generation. We recently demonstrated that selective use of a high-temperature oxidation on 4H-SiC (0001) resulted in a significant improvement of MOS properties by a formation of a MOS capacitor with nearly-ideal CV characteristics and less interface state density (Dit) [1], even without introduction of nitrogen by NO annealing process. We consider high-temperature oxidation works to reduce the remaining carbon byproduct significantly [2].
We also investigated the impact of the post-deposition annealing (POA) conditions on interface state density. It was found that the POA at a relatively low temperature in O2 is quite effective to reduce Dit, probably due to the reduction of oxygen-deficiency induced defects. Employing sufficiently low temperature is so important to suppress further oxidation of the interface during POA. Thus appropriate selection of both POA time and temperature is inevitable to optimize the POA effects. We also found a significant decrease of near-interface oxide traps (NITs), which are the most possible origin of the slow responses of the electrical characteristics to the applied bias. After an optimization of the post-oxidation annealing processes in oxygen ambient at low temperature, the estimated density of NITs decreased by several times.
Finally, a lateral-MOSFET on 4H-SiC (0001) was fabricated based on those process techniques. A relatively high effective mobility ~30 cm2/Vs, as a SiC MOSFET without nitridation of the interface, was obtained with the gate stack prepared simply by the combination of high-temperature thermal oxidation and post-oxidation annealing processes, while we can expecte a further improvement by applying the additional passivation techniques. The process design of thermal oxidation of SiC would be one of the promising ways to improve the MOSFET performance from the viewpoint of both the reduction of channel resistance and the improvement of device reliability.
This work was partly supported by CSTI Cros-ministerial Strategic Innovation Promotion Program"Nex-generation power electrnonics" (funding agency: NEDO) and JSPS KAKENHI.
[1] R. H. Kikuchi and K. Kita, Appl. Phys. Lett. 105, 032106 (2014).
[2] H. Hirai and K. Kita, Appl. Phys. Express 8, 021401 (2015).
Non-Prestonian Behavior Study and Development of Advanced Oxide Polish Slurry for Stop-In-Film Applications
Authors: Zhou Hongjun , Murella Krishna , Hughes John , O'Neill Mark 
Published: February 2020

Non-Prestonian behavior is defined as a non-linear correlation between the removal rate and the polishing pressure. It is believed to be related to dishing, erosion and self-stopping behavior that is observed on pattern wafers.
Nojo et al. has reported that “self-stopping polishing” can be achieved when the non-Prestonian behavior was observed. Significant research effort has been made in this field, following this initial report. For example, the effect of chemical additive concentrations and molecule weight of additives, along with abrasive concentration and size on non-Prestonian behavior have been studied. Primarily, blanket wafer performance data has been presented in the majority of published work. Although some researchers had conducted modelling to calculate the effect of non-Prestonian behavior on pattern performance, a comparison between pattern and blanket wafer performance in not available. This is needed to enable a more clear understanding of non-Prestonian behavior.
In this presentation, Prestonian behavior was modulated by adjusting chemical concentrations and / or formulation pH. Pattern performance, including oxide removal rate and step height reduction rate, were collected and evaluated. It was determined that non-Prestonian behavior does not necessarily lead to good pattern performance. From the learnings of this systematic study, a high-performance, oxide-polish slurry for stop-in-film applications was successfully developed.
Probing the Role of Slurry Chemistry on Nanoparticle-Media Adsorption Relevant to Cu CMP Filtration Applications
Authors: Wienck Richard A , Mlynarski Amy , Connor Patrick , Levy Patrick , Keleher Jason J 
Published: February 2020

As the complexity of nanoparticle dispersions used in next-generation CMP slurries increases to meet stringent performance demands, it is necessary to develop polymeric filtration media that capture rouge particles in order to reduce overall surface defectivity without sacrificing planarization efficiency. Therefore, it is essential to probe the molecular level interactions at the nanoparticle/slurry chemistry/polymer filtration media interface and in turn correlate this to the key performance metrics such as substrate removal rate, post CMP defects, planarization efficiency. More specifically, simulated Cu CMP slurries with a wide range of film formation chemistries for performance control were evaluated with respect to the filterability through various polymeric filtration media. It was determined that a synergy exists between the structure of the additive (small organic molecule vs. surfactant-like additive) and the filter medias ability to regulate the dynamic adsorption processes of the slurry nanoparticles. Utilizing atomic force microscopy (AFM), electrochemical quartz crystal nanobalance (EQCN), modified ATR-IR spectroscopy, and in-situ rotating disk electrode corrosion measurements the static and dynamic nanoparticle binding mechanisms can be determined and correlated to the filterability studies. Furthermore, monitoring the pre/post filtration zeta potential and particle size distributions, bulk copper removal rate, and corrosion current as a function of filtration pressure, the role of filtration media slurry chemistry health can be surveyed on CMP performance based scale.
(Invited) Critical Review of CMP Requirements in the Future
Authors: Banerjee Gautam 
Published: February 2020

With the introduction of tri-gate at 22nm technology node by Intel, other logic chip manufacturing technology developers have steadily migrated from planar to 3 dimensional FinFET technology at the fron-end-of-line. Historically, at 0.8μm technology node, there was no CMP although 2-3 metal levels were used. At 0.35μm technology node, a CMP step was introduced. CMP became mainstream with multiple steps requiring CMP at 90nm technology node which continued until 2x nm technology node. However, at 1x (e.g. 14nm) technology node, CMP began to transition from a ‘process simplifier’ to a ‘process enabler’ step. Expanding applications of CMP have made possible the integration of FinFET, RMG (Replacement Metal Gate) and TSV (Through-Silicon-Via)[1].
In sub 1x logic fabrication, the total number of CMP steps may reach 20 or more. Use of FinFET technology in 1x and sub 1x provides much better performance at the same power budget or equal performance at a much lower power budget compared to planar mode[2]. Further, III-V compounds are expected to be integrated at 5nm technology node. III-V materials enable Vdd scaling to address power without sacrificing performance due to the very high electron injection velocity at virtual source compared to Si[3]. These III-V films will require CMP with special care due to the probability of toxic gas release (AsH3/PH3).
Beyond 5nm, it is widely assumed that FinFET technology will not be able to provide the small scale features and therefore, gate-all-around technology will be used. To implement gate-all-around, one potential pathway may be to use 2D TMD (2 dimensional transition metal dichalogenide) films. 2D TMD gate-all-around film allows for increasing direct S/D (source/drain) tunneling[4].
With new types of films getting integrated in smaller features, it is necessary therefore to understand the type and nature of various films being used to fabricate devices using sub 1x nm features. In this paper, various US patent applications by leading device manufacturers within the past year will be reviewed to explore the most important CMP steps needed to fabricate new devices. Further, new slurry formulation efforts to enable new CMP requirements for the sub 1x nm devices will be reviewed for the same timeline.
References:
1) Y. Moon et al, CMPUG, July 2014, San Francisco, CA.
2) C. Surisetty et al, CAMP 2013, Lake Placid, NY.
3) T.W. Kim, IEDM 2012.
4) K. Majumdar et al, EDL, 35, p.402, 2014.
Planarization of GaN Using a FeIII-Ligand Based Catalyst in H2O2 Solution to Improve Its Removal Rate
Authors: Xu Li , Pan Guoshun 
Published: February 2020

A large amount of attention has been given recently to gallium nitride (GaN) substrates which are considered to be a promising candidate for opto-, high power and high frequency electronic devices due to their wide bandgaps, high carrier mobility, high saturated electron drift velocity and high breakdown field . It is essential to provide a complete damage-free surface to realize the full potential of GaN devices. Chemical mechanism planarization (CMP) is applied to the surface as a final treatment to produce atomic level surface flatness by removing the damage on the surface. However, the removal rate of GaN in CMP with colloidal silica-abrasive-based slurry under acidic slurry pH condition presents a range of ten to a hundred nanometers per hour because of their high mechanical hardness, thermal stability and strong chemical inertness. Thus, improving the CMP removal rate for GaN will lead to an acceleration in the realization of next generation optoelectronics devices on GaN.
In this work, a method for facilitating the removal rate as well as obtaining atomically smooth surface of GaN with a novel FeIII-Ligand-based catalyst in hydrogen peroxide (H2O2) solution is presented. Effect of process parameters, such as concentration of H2O2, the mass of FeIII-Ligand-based catalyst in slurry, pH of the slurry and concentration of abrasive particles on the material removal rate (MRR) as well as the surface quality have been studied in details.
(Invited) Plasma Modification of Graphene Based Materials and Its Applications in Water Treatment
Authors: Yang Hui Ying 
Published: February 2020

The ion and other impurities in the seawater is a naturally distributed element in the environment. The seawater aqueous solution plays an important role in many application fields with proper ion removing and desalination process, e. g. in a middle-scale semiconductor factory, different manufacture process. Therefore, it is necessary to control different ion concentrations within the limit. In the desalination field, reverse osmotic membrane, capacitive desalination, and electro-dialysis desalination are the most popular technologies. However, none of them can efficiently remove smalll ions from seawater due to its small size and uncharged species at pH 8.4. In this presentation, we will discuss different plasma treatment methods and their applications in the treatment of carbon based nanomaterials for water treatment and desalination. We synthesize different carbon based nanomaterials graphene oxide, by simple two-step process in the aqueous solution and have extremly high efficiency as media for water treatment and desalination.
Improvement of Electron Injection by a Ramp-Shape N-Doped Architecture for High-Efficiency Organic Light Emitting Diodes
Authors: Tsai Chi-Ting , Chu Sheng-Yuan 
Published: February 2020

Over the past decades, organic light-emitting diodes (OLEDs) have drawn a lot of attention due to its numerous advantages over light-emitting diodes (LEDs) and liquid crystal display (LCDs). These characteristics make OLED become one of the most promising candidates for commercial applications such as solid state lighting and active matrix organic light-emitting diode (AMOLED) display. However, device properties such as lifetime, efficiency, power consumption are still the main issues needed to overcome for their practical uses. In order to fulfill a highly power-efficient light source or display with OLEDs, the device energy loss during electron–photon conversion should be low. Recent years, there are plenty of approaches proposed to improve the electron or hole injection from the electrodes and reduce the ohmic losses. The most typical way is inserting a chemically p- or n-doped layer between the hole transporting layer (HTL) and anodes or between the electron transporting layer (ETL) and the cathodes, respectively.
In our work, we report OLED with a novel n-doped ramp-shape electron injection structure composed of rubidium carbonate (Rb2CO3) doped 2-methyl-9,10-di(2-naphthyl) anthracene (MADN) which is prepared by thermal co-evaporation. We increase the doping concentration from 17.5 mol% to 84 mol% while depositing the electron injection materials approaching the cathode. By increasing the doping concentration, the activation energy of the material decreases as the Fermi level shifting toward the lowest unoccupied molecular orbital (LUMO). Under thermal equilibrium conditions, a ramp-shape architecture is formed and gradually distribute the energy barrier from cathode to electron transport layer in the device therefore achieve significant electron injection improvement.
As a result, a OLED with the ramp-shape electron injection structure ITO/NPB (40nm)/Alq3 (40nm)/Rb2CO3:MADN (14nm, 17.5~84 mol%)/LiF (1nm)/Al (140nm) accomplished maximum luminance of 33370 cd/m2 and current efficiency of 5.292 cd/A. By contrast, the device without the ramp-shape architecture (the normal device) ITO/NPB (40nm)/Alq3 (40nm)/LiF (1nm)/Al (140nm) only achieved a maximum luminance of 17030 cd/m2 and current efficiency of 3.41 cd/A. The total improvement (55% by current efficiency and 95% by luminance) made by adding ramp-shape structure to device indicated a remarkable electron injection facilitation and its performance is much more efficient than the device with typical electron injection layer ITO/NPB (40nm)/Alq3 (40nm)/Rb2CO3:MADN (5nm, 64 mol%)/LiF (1nm)/Al (140nm).

Figure 1
Process-Structure-Properties Relationship of Electrodeposited Au Thin Film Used in Thermoelectric Power Generation Device
Authors: Banga Dhego 
Published: February 2020

An effective thermoelectric (TE) power source consists of TE modules and thermal management device. The TE modules must be connected electrically in series on both the top and bottom surface with bridging metal interconnects that must maintain low contact resistance with high mechanical strength while operating at high current densities and temperature gradients. Due to its low emissivity, excellent electronic, and mechanical properties, Au coatings can be used for interconnect metallization and heat mitigation in TE modules and thermal management devices respectively.
In this study, we report on the successful synthesis of perfectly coherent and atomically sharp nanoscale growth twin boundaries (figure 1(e&f)) and the introduction of highly crystalline atomic structure (figure 1(f)) in the interior of each grain of Au electrodeposits using pulsed electrodeposition from an additive stable cyanide gold bath. The increase in sharpness of nanoscale twin boundaries resulted in improved mechanical and electronic properties in Au electrodeposits1. During the study of nucleation and growth mechanism of Au electrodeposition process, we established that both instantaneous and progressive nucleation modes could be achieved depending on the overpotential used during deposition. Instantaneous nucleation was observed at lower overpotentials (≥ -0.75 V vs Ag/AgCl) while progressive nucleation occurred at larger overpotentials (< -0.75 V vs Ag/AgCl). We then compared direct (DC) and pulse current (PC) electrodeposition modes and their effects on mechanical and electronic properties of the electrodeposits. We determined that the use of large overpotentials (≤ -0.9 V vs Ag/AgCl) successfully produced films with enhanced properties. Compared to films generated using DC electrodeposition, pulsed Au coatings had improved physical and electronic properties with emissivity as low as 0.006, contact resistance five times less, hardness and electrical conductivity twice as much. We also found that long pulse on-times (≥ 2ms) and a small duty cycle (10%) were needed to produce smooth, porous free(figure 1(b&c)), highly crystalline, strongly textured, low emissivity, reduced contact resistance, enhanced electrical conductivity, and mechanically strong Au electrodeposits.

Reference

1. L. Lu, Y. F. Shen, X. H. Chen, L. H. Qian, and K. Lu, Science,
304 (5669), 422-426 (2004).

Figure 1
High Rate Li-S Batteries: Hollow TiO2 Webbed Carbon Nanotubes with Dual Functional Porous Carbon-Paper
Authors: Hwang Jang-Yeon , Abouimrane Ali , Khaleel Mohammad Ahmed , Belharouak Ilias , Manthiram Arumugam , Sun Yang-Kook 
Published: February 2020

The Li–S batteries are becoming attractive due to the abundance of elemental sulfur and its environmental compatibility. In addition, sulfur undergoes a two-electron redox reaction with lithium and offers an extremely high theoretical speciﬁc capacity of 1675 mAh g−1 and a high energy density of 2600 Wh kg−1.1 Despite these advantages, several issues have hampered the practical use of Li–S batteries. For example, the insulating character of sulfur and lithium sulﬁde impede the full electrochemical utilization of sulfur. Moreover, the dissolution of lithium polysulﬁde inter-mediates in the electrolyte triggers undesirable shuttle reactions. Other issues such as low Coulombic efﬁciency, high self-discharge, and huge volume change remain unsolved. To overcome these drawbacks, several mitigation strategies have been explored by various research groups. One of the most followed routes deals with the mixing/impregnation/conﬁnement of sulfur within highly conducting carbons. carbon nanotube-based composites have been used for high sulfur loading amount. Another approach is the use of metal oxides. In particular, TiO2 is a promising host for sulfur containment owing to its high absorption ability2. Further enhancement in the capacity and cycle life of Li–S batteries has been realized by Manthiram’s group by employing a free-standing interlayer (between the sulfur cathode and the separator) that plays the bifunctional role as a trap for mobile polysulﬁdes and as an upper current collector for fast electron transport3.
Herein, we synthesized and characterized (i) a S-HMT@CNT sulfur cathode comprised of hollow, spherical, nanostructured TiO2 and carbon nanotubes and (ii) DF-PCW interlayer comprised of highly porous carbon spheres and carbon nanotubes. The pores of TiO2 allowed for high sulfur loadings and accommodation of the volume expansion at the electrode level. The CNT component provided an overlap-ping network that improved both the electronic conductivity and mechanical strength of the S-HMT@CNT and DF-PCW. The pores in the carbon interlayer played the role of a medium that scavenged the dissolved lithium polysulﬁdes, while improving Li-ion and electron transports. Owing to our cathode characteristics and cell design, the lithium–sulfur cell fabricated demonstrated good cycle life, high efﬁciency, and high rate capability. Of signiﬁcance, the excellent cycling realized at the 2C and 5C rates is appealing for utilizing the lithium–sulfur batteries in high power applications
In Situ Measurements of Solid Electrolyte Interphase Evolution on Silicon Electrodes
Authors: Yoon Insun , Abraham Daniel P , Lucht Brett L , Bower Allan F , Guduru Pradeep 
Published: February 2020

We report in situ measurements of initial solid electrolyte interphase (SEI) evolution on silicon negative electrode and also the lithiation-induced silicon volume changes in lithium ion half-cells. Thin film amorphous silicon (a-Si) electrodes are designed to enable unambiguous measurement of SEI thickness evolution and silicon thickness evolution. The thin film electrode samples are assembled into a custom-designed electrochemical cell integrated with an atomic force microscope (AFM) to facilitate real time measurements. The films are subjected to two potentiostatic lithiation and delithiation cycles by applying a series of constant potential values against lithium metal, which serves as the counter and reference electrode. The thickness changes are measured after a state of equilibrium is reached at each potential value. Experiments are carried out with two electrolytes – 1.2M lithium hexafluoro-phosphate (LiPF6) in ethylene carbonate (EC) and 1.2M LiPF6 in propylene carbonate (PC) – to investigate the influence of electrolyte compositions on SEI formation and electrochemical performance. The results reveal that the predominant SEI thickness evolution occurs during the first cycle, and reaches steady values of approximately 17nm with EC electrolyte and 10nm with PC electrolyte. Despite the thinner SEI layer, capacity loss due to SEI formation is larger with PC electrolyte compared to that of EC electrolyte. Si volume change shows approximately 21% of irreversible volume expansion during the first cycle and no appreciable irreversible volume expansion was observed in the subsequent cycle. In addition, silicon volume expansion shows an approximate linear relationship with the state of charge. Volume change and capacity of silicon films show hysteresis as functions of equilibrium potential. We seek to explain such hysteretic behavior in terms of the stress-potential coupling in silicon, which shows both qualitative and quantitative agreement. Beyond the specific materials systems considered here, the in situ AFM based experimental technique developed in this work has broader applications to investigate the role of electrolyte composition in the SEI formation kinetics.

Figure 1