(Invited) Integration of an Epitaxial-Base-Link HBT Device with fT = 300GHz, fmax 480GHz in 90nm CMOS
Authors: Manger Dirk , Boeck Josef , Aufinger Klaus , Boguth Sabine , Gruenberger Robert , Popp Thomas , Binder Boris , Hengst Claudia , Majied Soran , Markert Matthias , Pribil Andreas , Rothenhaeusser Steffen , Tschumakow Dmitri Alex , Dahl Claus , Bever Thomas 
Published: December 2020

SiGe HBT based BiCMOS technologies have found widespread use in millimeter-Wave (mmW) applications such as high-speed communication and automotive radar, but are also receiving increased attention for operating frequencies above 100GHz. The drive for higher operating frequencies while reducing power consumption continues to fuel the development of new BiCMOS technologies with HBTs featuring higher switching speeds (fmax) integrated with smaller, more power efficient and cost effective CMOS nodes. There is strong evidence however, that in volume production double poly self-aligned (DPSA) HBT architectures may be limited to fmax of 400GHz[i],[ii],[iii],[iv],[v],[vi]. Alternative HBT architectures to overcome this limitation have been proposed[vii],[viii],[ix].
In this paper we report the successful integration of a SiGe HBT module with fT = 300GHz, fmax = 480GHz in a 90nm BiCMOS technology platform. Building on previous studies by IHP[x] and Infineon[xi] the Epitaxial-Base-Link process flow was further adapted for compatibility to the 90nm CMOS base technology. The new technology platform features seven Cu metal layers high quality passives including a TaN resistor and a MiM capacitor positioned between metal levels 6 and 7 for low parasitic substrate coupling. One metal layer was added compared to the 130nm platform to facilitate the transition from thin wire to RF metallization.
Figure 1 shows a TEM cross section of one of the first successful 90nm BiCMOS runs. Key challenges of the integration into the new CMOS node will be summarized in the presentation. The same device showed nearly ideal Gummel characteristics. CML ring oscillators with a design width EW of 190nm and 2.8 µm length achieved a wafer mean gate delay of 1.86ps with a standard deviation of 1.9%.
Acknowledgment: This work was supported by the European Commission and the German Federal Ministry of Education and Research (BMBF) under project ref# 16ESE0202S ECSEL-TARANTO.

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Figure 1