bluuebunny/crossref_metadata_2025_split huggingface dataset:
Metallurgical Examination of a Galled PH 13-8 Mo Stainless Steel Main Rotor Sub-Assembly
Authors: Grendahl Scott M. , Pepi Marc S. 
Published: December 2020

Abstract
The Aviation and Missile Command requested the US Army Research Laboratory to perform a metallurgical examination of a main rotor sub-assembly from an attack helicopter as vibration was noticed during a test flight after replacement of the main rotor head. This article presents the details of the metallurgical examination, the mechanical properties of and chemical analysis on the failed component, and the techniques adopted for the examination such as scanning electron microscopy, X-ray mapping, energy dispersive spectroscopy, and residual stress analysis. The discussion includes the details of crack origin, fatigue progression, and the circumstances which caused the point contact between a MP35N pin and a PH 13-8 Mo component. The failure of the main rotor strap pack outboard pitch cone bolt was attributable to galling. Several of the cracks may have propagated by fatigue and converged beneath the bolt inner diameter or adhesive wear may have induced a sub-surface crack origin.
ESD Induced Failure of an Internal MOSFET in a Mixed Signal IC due to Two Different Power Supplies
Authors: Bundhoo Fayik , Vedula Lakshmi , Khandekar Shekhar 
Published: December 2020

Abstract
During the ESD testing of a Dual T1/E1 line interface unit (LIU) at Level One, the circuitry in every pad cell was found to be robust to Electro-Static Discharge (ESD) threshold of up to 2000 Volts. Device failure was however observed on devices when functional tests were performed. These failures were observed on devices which were only subjected for 1250 Volts of ESD stress. The failure analysis revealed ESD induced damage at the Gate - Drain region of a MOSFET in the core of the die. A weak power supply clamp in the supply circuit caused this failure. The step by step analysis process and the redesign of this device with confirmation on new design revision is explained.
Evaluation of Pt/PZT/Pt Capacitors Using SIMS
Authors: Tomotani Miki , Ashida Hiroshi , Goto Yasuyuki , Otani Seigen 
Published: December 2020

Abstract
This paper presents the results of a study on the effects of N2-H2 annealing on Pt/PZT/Pt capacitors. By measuring the electrical properties of test capacitors before and after annealing and comparing the data with composition profiles obtained via secondary ion mass spectrometry (SIMS), the authors found that annealing causes an increase in hydrogen in the PZT layer (accompanied by a reduction in nonvolatile polarization) and a decrease in oxygen in the upper Pt film, which is associated with poor adhesion. The authors also found that oxygen annealing, after N2-H2 annealing, can restore electrical properties as well as adhesion states back to their original levels.
ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement
Authors: Patrick D.S. , Wagner L.C. , Nguyen P.T. 
Published: December 2020

Abstract
Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.
Faster Defect Localization with a New Development of IDDQ
Authors: Desplats Romain , Perdu Philippe , Benbrik Jamel , Dupire Michel 
Published: December 2020

Abstract
Recent progress with IDDQ testing has demonstrated the ability to identify a majority of defects in logic ICs. IDDQ testing has also been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms to further extend defect coverage. However, this progress has not eliminated the complex task of defect localization on the silicon level of ICs. To deal with the challenge of faster and more accurate defect localization with greater sensitivity, we have developed a new method based on voltage contrast capabilities for internal localization of IDDQ defects. This method covers an extended range of cases: functional or non functional devices, with or without CAD information, etc... Using only the same test pattern as that used to identify a faulty circuit, the equipotential line of the failure can be located. This approach can also be extended to coupling with netlist information. For example, the equipotential line previously found on the faulty circuit can be compared with the fault simulator output. Then, the site of the simulated defect corresponding to the physical failure can be extracted and local deprocessing with a FIB can be used on the failed circuit to physically reveal the defect with an improved turn around time.
Comparison of Failure for HBM ESD Testers Meeting ANSI/ESD S-5.1 or the New ESDA Standard Test Method and JEDEC Standard
Authors: Khosropour Fred , Hatchard Colin , Morgan Ian , Henry Leo G. 
Published: December 2020

Abstract
The ESD Association standard ANSI/ESDA S-5.1 1993 for testing sensitivity to the Human Body Model (HBM) 1 forms the basis around which the majority of automated HBM ESD simulators have been constructed. As device pin counts increase it is unlikely that new larger simulators for &gt; 512 pins will be capable of meeting this standard 2, since increased parasitics will increase the effective socket (stray) capacitance. However, such larger HBM simulators are expected to meet both the JEDEC Standard JESD-22-114A, 1997 3 and the newly issued ESDA Standard Test Method, ESD STM 5.1, 19984. This paper begins to evaluate the several questions regarding the correlation of HBM Withstand Voltage when used to characterize state-of-the-art semiconductor IC's, between simulators meeting the (NEW) standards JESD 22, ESD STM- 5.1 and those existing simulators presently in daily use, which typically meet the (OLD) ESDA S-5.1. This paper for the first time investigates the impact of "effective" socket capacitance in the same tester; i.e., with the same discharge model and the same pin selection mechanism. The experimental investigation was based on stressing three different sub-micron CMOS technology products; firstly on a simulator meeting the OLD standard and then on a modified version of this simulator meeting the NEW standards. Electrical properties of damaged pins and physical analysis was used to establish common Failure Signatures5 for the two mother boards.
Selective Wet-Etch of Silicon Nitride Passivation Layers
Authors: Malberti P. , Ciappa M. 
Published: December 2020

Abstract
Selective removal of silicon nitride passivation layers is of major importance in failure analysis of semiconductor devices. Typical applications are: cleaning of the die surface for optical microsccjpy and for removal of superficial contamination, electron microscopy, liquid crystals, voltage contrast, electron beam testing, mechanical microprobing, and . selective layer-by-layer strip. A new wet-etch for silicon nitride passivation layers has been developed, which is fully selective! over aluminum metallization and which preserves full device functionality after passivation removal. For the first time in the failure analysis literature, the chemical recipe and the etching procedure are given in details. This etchant has been experimented for more than two years in many failure analysis laboratories on a wide spectrum of discrete and integrated semiconductor devices, always with excellent results. Its capability and efficiency are illustrated by two failure analysis case histories.
Infrared Scanning Using Radiance vs. Temperature Calibration Techniques to Determine Actual Temperature of an Electronic Component
Authors: Dickey David 
Published: December 2020

Abstract
It is necessary to understand the limitations of an automated InfraRed (IR) system when using it for temperature measurements. These systems correct for emissivity of the test sample by heating the unpowered sample and taking radiance measurements at two temperatures. For the specific sample that was analyzed, the temperature of the area of interest of the powered sample was higher than the two temperatures used for emissivity correction. This resulted in a significant error in the temperature calculated by the system. The use of direct radiance measurements provided an accurate measurement of the sample temperature.
A Novel Fault Isolation Technique Using Noise Detection and Characterization of Light Emitted From Integrated Circuits
Authors: Zheng Hong , Patterson Joe , Li G. P. 
Published: December 2020

Abstract
This paper describes a new technique for identifying defects on integrated circuit. This technique detects the noise content in light emitted from defect sites. The purpose of this technique is to determine which of many light emission sites represent a defect and which represent normal devices. It reports the first phase of studies to evaluate the feasibility and potential effectiveness of this technique. The feasibility of this technique has been demonstrated by simultaneously monitoring electrical noise and the noise in the light emitted from a gallium arsenide light emission diode (LED) and a bipolar transistor. The paper will present the methodology and apparatus used to detect and analyze the noise in light emission.
Optical Probing of VLSI ICs from the Silicon Backside
Authors: Eiles Travis M. , Woods Gary L. , Rao Valluri 
Published: December 2020

Abstract
With the advent of C4 packaging technology, Intel has developed, in conjunction with a technology partner, an integrated, laser-based optical backside probing system. This article begins with a description of the basic system operation. This is followed by a discussion on the electro-optic effect in CMOS, which is used for the signal acquisition. The question of invasiveness of the photo-injected carriers is then discussed. Information on the entire probing environment is also provided. The article also discusses results and presents a comparison with other waveform acquisition techniques. It ends with a brief discussion on the developments needed to scale the technique to future processes.
Electrical Probing and Surface Imaging of Deep Sub-Micron Integrated Circuits
Authors: Krieg Kenneth , Qi Richard , Thomson Douglas , Bridges Greg 
Published: December 2020

Abstract
A contact probing system for surface imaging and real-time signal measurement of deep sub-micron integrated circuits is discussed. The probe fits on a standard probe-station and utilizes a conductive atomic force microscope tip to rapidly measure the surface topography and acquire real-time highfrequency signals from features as small as 0.18 micron. The micromachined probe structure minimizes parasitic coupling and the probe achieves a bandwidth greater than 3 GHz, with a capacitive loading of less than 120 fF. High-resolution images of submicron structures and waveforms acquired from high-speed devices are presented.
Light Emission Spectral Analysis: The Connection Between the Electric Field and the Spectrum
Authors: Barton Daniel L. , Tangyunyong Paiboon , Soden Jerry M. , Henderson Christopher L. , Cole Edward I. , Danz Rainer , Steiner Reinhard , Iwinski Zbigniew 
Published: December 2020

Abstract
The device physics necessary to gain theoretical insight into the relationship between the bias conditions and the associated electric field for semiconductor structures in various failure conditions such as forward and reverse biased junctions, MOSFET saturation, latchup, and gate oxide breakdown are examined. The relationships are verified by light emission spectra collected from test samples under various bias conditions. Several examples are included that demonstrate the utility and limitations of spectral analysis techniques for defect identification and the associated, non-electric field related information contained in the spectra.
Short High Voltage Stress for Design-to-Process Characterization
Authors: Lisenker Boris , Veinger Dmitry , Mitnick Yuri 
Published: December 2020

Abstract
This paper discusses the use of failure analysis techniques, including high-voltage stress testing, to determine the product margin for a microprocessor manufactured on a 0.25-μm CMOS process. The first part of the approach is to define the parametric baseline of the product and differentiate normal from failure-prone behavior. The next step is to measure the margin on each unit (i.e., transistor gate) by temporarily increasing the supply voltage (Vcc) and observing its effect on leakage current. As the authors explain, the new approach facilitates the detection of potential design and manufacturing problems in a much shorter time than the hundreds of hours normally required.
Latch-Up Induced Slit Voiding in Aluminum Metal Lines
Authors: Zhang Chunyu , Vedula Lakshmi , Khandekar Shekhar 
Published: December 2020

Abstract
Latch-up induced during High Temperature Operating Life (HTOL) test of a mixed signal device fabricated with 1.0 μm CMOS, double poly, double metal process caused failures due to an open in aluminum metal line. Metal lines revealed wedge voids of about 50% of the line width. Triggering of latch up mechanism during the HTOL test resulted in a several fold increase of current flowing through the ground metal line. This increase in current resulted in the growth of the wedge voids leading to failures due to open metal lines.
Nondestructive Detection of Cracks in Ceramics Using Vicinal Illumination
Authors: Hull Scott M. 
Published: December 2020

Abstract
Cracks and other defects in ceramic materials can be difficult or impossible to examine and photograph due to the extreme lack of contrast. A method for inspecting translucent ceramics using scattered light, also known as vicinal illumination, will be described. This method has been known in the ceramics industry for quite some time, but is not well known in the testing and failure analysis community. Electronics applications include substrates, packages, multilayer capacitors, and thin film resistors. Ceramic materials are used in electronic applications as microcircuit packages and substrates which carry signals and power between microcircuits. Fine cracks in ceramic materials can result in mechanical failures, electrical failures, and loss of hermeticity. Often, fine cracks are difficult or impossible to detect using standard nondestructive inspection techniques such as visual inspection, ultrasonic inspection, or vapor crack detection. Dye penetrant inspection is usually effective, but contaminates the part, which is unacceptable for space flight hardware. One effective nondestructive inspection method of detecting cracks involves examining the way in which light scatters through the ceramic material when viewed with a standard bright field reflected light microscope. This method, termed vicinal illumination, has been used for detecting cracks during failure analyses of several part types, and screening of space flight hardware. The technique has proven effective on several different types of ceramic materials as well. A related method for use with dark field equipment has also been used to successfully locate otherwise invisible cracks.
An Application of Passive Voltage Contrast (PVC) to Failure Analysis of CMOS LSIs Using Secondary Electron Collection
Authors: Nishikawa Akira , Kato Naoko I. , Kohno Yoshiteru , Miura Nobuhito , Shimizu Masao 
Published: December 2020

Abstract
This paper describes a method for applying passive voltage contrast (PVC) in the failure analysis of CMOS LSIs using a conventional scanning electron microscope (SEM), and demonstrates the effectiveness of this method. It was confirmed by measurement of the stage absorption current that the combined emission efficiency of secondary and backscattered electrons from aluminum is larger than 1 at acceleration voltages lower than about 2.5 kV. This means that local positive charges should be generated on a conductor in association with its irradiation with an electron beam at a relatively low acceleration voltage. However, a pn junction connected to the conductor would change the potential. The potential is still positive if the conductor is connected to a reverse-biased diode but becomes lower if such a diode is forward-biased. The PVC signal observed on the conductor should be defined according to the bias state of any diode connected to the conductor. Therefore, for failure analysis applications, if the bias state of a diode connected to a suspicious conductor is known, the PVC observation is useful for determining whether there is an open defect or a short-circuit defect. Some case studies are presented to demonstrate the effectiveness of the method. Cross-sectional TEM observations of defects localized in this way are also included.
Electrostatic Discharge (ESD) Failures in Thin Film Resistors
Authors: Hull Scott M. 
Published: December 2020

Abstract
Field failures of nichrome thin-film resistors have been investigated recently for several pieces of spaceflight hardware. These failures have involved resistance shifts ranging from a few percent to complete open circuits. Failure analysis and duplication of these failures have revealed that the failures were caused by electrostatic discharge. The failure characteristics and the circuit conditions necessary for failure have been studied for several types of thin-film resistors, including nichrome and tantalum nitride resistive elements. The effects of latent damage and resistive pattern design will also be discussed.
Electromigration and Electrochemical Reaction Mixed Failure Mechanism in Gold Interconnection System
Authors: Murayama Hide , Yamazaki Makoto , Nakajima Shigeru 
Published: December 2020

Abstract
Power bipolar devices with gold metallization experience high failure rates. The failures are characterized as shorts, detected during LSI testing at burn-in. Many of these shorted locations are the same for the failed devices. From a statistical lot analysis, it is found that the short failure rate is higher for devices with thinner interlayer dielectric films. Based upon these results, a new electromigration and electrochemical reaction mixed failure mechanism is proposed for the failure.
From IDDQ Fault Detection to Defect Localization in Logic CMOS Integrated Circuits: Key Issues
Authors: Perdu Philippe , Desplats Romain 
Published: December 2020

Abstract
IDDQ testing detects a majority of faults in logic ICs. To improve defect coverage with very short test patterns, IDDQ testing has been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms. Nevertheless, for failure analysis purposes, this progress has not eliminated the complex task of fault isolation at the silicon level of ICs. Defect localization is facilitated with IDDQ testing because the defect is detected as soon as it is activated inside the device. At the failed vector, abnormal IDDQ current is measured and accurate localization of the corresponding defect inside the chip can be performed. Thermally related techniques or emission microscopy can be used for this localization process. Very powerful tools like electron beam testers can also be used to deeply analyze faulty devices by internal contactless testing. In this paper, we will present an application of IDDQ testing for fault detection and some key issues regarding localization of the corresponding defect: • Appropriate techniques, • Switching from electrical testing to fault localization, • Modifying the test pattern to shorten the localization process, • Constructing a localization method based on an IDDQ diagnostic.
Scanning Electron Acoustic Microscopy: A Novel Tool for Failure Analysis and Microcharacterization
Authors: Wong W-K , Thong J.T.L. , Phang J.C.H. , Yin Q.R. , Fang J.W. 
Published: December 2020

Abstract
This paper describes Scanning Electron Acoustic Microscopy (SEAM) applications, particularly to samples that are of interest to the microelectronics industry. Several applications of SEAM involving semiconductor and ferroelectric samples are discussed in this paper. The expanding scope of applications for SEAM presents exciting possibilities. The challenge ahead lies in understanding the contrast mechanisms in SEAM signal formation as well as correlating results to the physical properties of samples.
Data Analysis Tools and Methodologies for Quick Yield Learning in a High Volume Manufacturing Environment
Authors: Andrade L. , Taylor T. 
Published: December 2020

Abstract
High volume products in manufacturing require fast yield learning, root cause identification, and verification that process or tool problems are fixed. Yield losses of 1% correspond to very large dollar losses. Therefore, it is important to have sophisticated data analysis tools that handle large volumes of data to drive higher yields. This paper will present our methodology for defining yields, assessing wafer yield signatures, and using data analysis tools to determine tools or processes which drive yield loss. A SAS based data analysis tool will be shown which can identify tool or process related problems causing abnormalities in parametrics and impacting yield. Case studies illustrating the usefulness of the tool are shown for a Synchronous Dynamic Random Access Memory (SDRAM) product from our wafer fab. In the final analysis, it is clear that an efficient data analysis approach utilizes resources most effectively and pinpoints yield problems with minimal cycle time.
A Novel Method to Analyze the Deep Trench Capacitors in DRAM
Authors: Lee Jack , Huang Kuo-Hui , Lue Jen-Lang 
Published: December 2020

Abstract
A novel method has been developed to reveal the entire three dimensional (3D) deep trench (DT) capacitors for inspection in DRAM, especially NO capacitor dielectrics, ASG residues at corners, morphology etc., for process evaluation and failure analysis. It offers an alternative to conventional cross-section polishing, top down polishing or FIB milling methods. A DRAM chip was ground and polished down to a certain level from the chip backside. An etching solution was then applied to enhance the DTs appearance. 3D DTs can be inspected in scanning electron microscopy (SEM). The entire DTs or specific DT also can be lifted out for detailed investigation in transmission electron microscopy (TEM). The innovation of this technique is to provide a quick 3D observation in SEM, and much more flexibility to an entire DT inspection in TEM, which were not presented before.