(Invited) Ultra-Low Power III-V-Based Mosfets and Tunneling FETs
Authors: Takagi Shinichi , Ahn Dae-Hwan , Gotow Takahiro , Takenaka Mitsuru 
Published: February 2020

CMOS and tunneling FETs (TFETs) utilizing low effective mass III-V channels on Si substrates is expected to be one of the promising device options for low power integrated systems, because of the enhanced carrier transport and tunneling properties. In this paper, we present viable device and process technologies of III-V MOSFETs and TFETs on the Si CMOS platform. Heterogeneous integration to form these new materials on Si is a common key issue. The wafer bonding technologies are utilized for this purpose. We demonstrate the operation and the electrical characteristics of a variety of III-V MOSFETs and TFETs including the hetero-structures.
One strategy to reduce Vdd is to increase Ion of MOSFETs by employing low effective mass (high velocity) channels. From this viewpoint, III-V/Ge materials are promising. One of the most critical problems for III-V MOSFETs on Si platform is high quality III-V channel formation on Si substrates. As a technology of the III-V channel formation, we are focusing on III-V wafer bonding to Si substrates. We have developed a bonding technology extendable to 300-mm Si wafers, where III-V channels are grown on Si with thick buffers and transferred to Si wafers [1]. The high channel quality with a low defect density has been confirmed from the tight leakage current distribution. By using InGaAs-OI substrates fabricated by wafer bonding, we have demonstrated tri-gate In0.3Ga0.7As (3nm)/InAs (3nm)/In0.3Ga0.7As (3nm)-on-insulator quantum well (QW) MOSFETs [2]. High Ion and suppressed short channel effects have been obtained by the narrow width tri-gate structure and the optimized ultrathin quantum-well channels [2, 3].
Also, the other strategy to reduce Vdd is to realize steep slope devices with low sub-threshold swing (S.S.). Here, TFETs are one of the most promising steep slope devices, which have been regarded as mandatory for future scaled LSIs for ultra-low power and IoT applications [4]. There can be two critical issues to realize high performance TFETs. One issue is the choice of the source/channel materials enabling to increase tunneling current. Thus, semiconductors such as Ge and III-V are expected as suitable materials with small and/or direct band gap for enhancing Ion of TFETs. In addition, source/channel junctions composed of type-II hetero-structures are effective in boosting the TFET performance without increase in the junction leakage current. Also, the second critical issue is the defect-less source tunnel junction formation with the optimum source concentration and the steep source impurity profile, which leads to sufficiently thin tunneling width and resulting high tunneling current with minimized leakage currents. From this viewpoint, the technologies to form the source tunnel junctions are of paramount importance.
The source regions of n-InGaAs TFETs were formed by selective diffusion from Z-doped SOG [5], which can automatically realize the steep Zn profile, thanks to the concentration-dependent diffusion constant of Zn in InGaAs. We have combined this source with InGaAs quantum well (QW) channels, resulting in enhanced Ion and suppressed Ioff of n-TFETs [6, 7]. The minimum S.S. of 54 mV/dec. has been obtained at room temperature for the In0.53Ga0.47As /In0.67Ga0.33As/In0.53Ga0.47As QW n-TFETs having W/HfO2/Al2O3 gate stacks with CET of 1.4 nm. Type-II hetero-structure GaAsSb/InGaAs TFETs are also regarding as one of the most promising material systems for TFETs. We experimentally observed the operation of vertical n-TFETs with InGaAs channels and GaAsSb sources doped in an in-situ manner during the epitaxial growth, which also realized the steep impurity profiles [8]. While high leakage current in the source junctions degrades the performance at 300 K, TFETs with the high GaAsSb source doping concentration of 1x1020 cm-3 have exhibited the Ion/Ioff ratio of 109, the minimum SS of ~30 mV/dec. and Ion of ~4 mA/mm at 20 K. We have also confirmed the operation of GaAsSb/InGaAs n-TFETs on a Si wafer, which was fabricated by direct wafer bonding [4].
This work was supported by JST-CREST Grant Number JPMJCR1332, Japan, and a Grant-in-Aid for Scientific Research (17H06148) from MEXT. The authors would like to thank Drs. M. Yokoyama, O. Ichikawa, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, Drs. M. Mitsuhara, H. Sugiyama, Hoshi and H. Yokoyama in NTT for their collaborations.
References [1] S.-H. Kim et al., APL 105, 043504 (2014) [2] S.-H. Kim et al., IEEE TED 61, 1354 (2014) [3] S.-H. Kim et al., APL 104, 263507 (2014) [4] S. Takagi et al., IEDM, 516 (2016) [5] M. Noguchi et al., JAP 118, 045712 (2015) [6] D.-H. Ahn et al., APEX 10, 084201 (2017) [7] D.-H. Ahn et al., JAP 122, 135704 (2017) [8] T. Gotow et al., JAP 122, 174503 (2017)