Advantages of Faceted P-Raised Source/Drain in Fully Depleted Silicon on Insulator Technology
Authors: Aydin Ömür Işıl , Holt Judson Robert , Vanamurthy Laks , Feudel Thomas , Le Royer Cyrille , Heyne Tobias , Gerber Ralf , Lenski Markus , Mulfinger George Robert , McArdle Timothy J , Jansen Sören , Utess Dirk , Klein Christoph , Peeva Anita , Barge David , Divay Alexis , Lehmann Steffen , Smith Elliot , Peters Carsten , Sachse Jens-Uwe 
Published: February 2020

Recently, a 22nm fully depleted gate-first SOI technology (FDSOI) has shown significant promise as a low-cost alternative to FinFETs with devices that are tunable between low-leakage and high-performance regimes. [1] The 22nm FDSOI PFET utilizes a SiGe channel with epitaxial grown raised source/drain (RSD) to define the junction profile, strain the channel, and facilitate contact formation. The pRSD epitaxial growth is typically a two-layer process with a main layer of SiGe:B followed by a capping layer of Si. Because the RSD epitaxy grows along the spacer dielectric, it results in a parasitic capacitance to the Gate electrode which then contributes to the total MOSFET capacitance and degrades AC device performance. Since the thickness of the main layer as well as the cap layer has a strong influence on this parasitic capacitance (Cgd), the RSD thickness should, in theory, be kept as low as possible. This is necessary to achieve the maximum AC and RF device performance. However, decreasing the RSD thickness below a certain level has the undesirable effect of DC performance drop. Therefore, another approach is needed to decrease Cgd further without degrading the drive current.
In this paper we present one of the strongest methods to increase FDSOI technology AC/RF device performance, namely faceted raised source/drain epitaxial growth. Faceted pRSD epitaxy effectively decouples the RSD height and Cgd, lowering the parasitic capacitance not by reduced total RSD height, but rather by eliminating the shared wall between the Gate and the RSD. This simple approach has two desirable outcomes: 1) low Cgd & AC performance gain, and 2) low electrical variability via suppressing the influence of RSD height variation. The primary electrical response from faceted pRSD is the lowering of Cgd up to 25% at matched DC performance at zero gate bias; and this resulted in approximately 5% ring oscillator performance and ca. 20GHz RF p-Ft improvement.
Other advantages of faceted pRSD are the selectivity in epitaxial growth and electrical variability. As mentioned previously, in a typical FDX device, RSD height needs to be controlled very tightly to achieve low device variability in DC transistor parameters (Ieff, Vtsat, Ioff) and Cgd. With faceted pRSD, however, this “shared wall” between Gate and RSD is liminated. We observed that the Cgd did not respond over a range of +/- 13% in main layer thickness, which led to a tight distribution of transistor parameters. Put another way, with faceted RSD, the primary need of a tight control over the pRSD thickness is eliminated.
References
[1] R. Carter and et al., "22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications," in IEDM16, San Fransisco, 2016.