bluuebunny/crossref_metadata_2025_split huggingface dataset:
Application of Scanning Probe Microscopy Techniques with Electrical Modules in Via Related Defects
Authors: Wang Xiang-Dong , David Theodore N. , Garteiz Gil , Sanders Paul 
Published: December 2020

Abstract
Identifying defects in marginally failed vias has long been a challenge for failure analysis (FA) of state-of-the-art semiconductor integrated circuits. This paper presents two cases where a conventional FA approach is found to not be effective. The first case involves high resistance or marginally open vias. The second case involves early breakdown of large capacitors. The large size of the capacitor and the lack of ways to track electrical flow during diagnosis made it difficult to isolate the defect. The paper shows that conducting atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) are effective techniques for isolation of via-related defects. The SCM technique could be applied to samples without a direct conducting path to the substrate, such as SOI samples. On the other hand, C-AFM allows current imaging as well as I-V characterization whenever a direct conductive path is available.
Open Failure Diagnosis Candidate Selection Based on Passive Voltage Contrast Potential and Processing Cost
Authors: Pan Yan , Khiam Oh Chong , Ohnmar Nyi , Zhang Chuan , Kannan Sekar , Chittora Atul , Huat Goh Szu , Yinzhe Ma , Nedeau Don , Keat Lim Seng , Lam Jeffrey 
Published: December 2020

Abstract
With a focus on open failure candidates, an extra effort in defining the ease of physical failure analysis (PFA) processing is taken in this paper by closely modeling the PFA processing flow and detailed estimation of the processing cost involved in every step is made. The paper begins with a discussion on the general PFA procedure to process open failure candidates in logic circuits. This is followed by a section that reviews common practice in PFA candidate selection, before proposing the comprehensive selection flow that aims to filter out the easiest candidate in terms of processing cost. This methodology is then evaluated by several case studies and is followed by a discussion on the potential future work. Case studies show that the cost model closely matches with real-world PFA turnaround time and the authors are working toward automating the full flow in software to further improve the efficiency.
Challenges of Small Defect Analysis in Large Analog Power FET Arrays
Authors: Cattey Eric 
Published: December 2020

Abstract
The proverbial needle in the haystack – locating a minute process defect or subtle ESD strike in a large sea of analog output power FETs can be just that. The premise of this paper is to discuss failure analysis techniques used to identify these elusive “needles”, specifically in large array power FET structures. Two case studies will be explored in detail – both of which are 250nm technology devices.
Thermal Laser Stimulation Technique for AlGaN/GaN HEMT Technologies Improvement
Authors: Carisetti Dominique , Sarazin Nicolas , Labat Nathalie , Malbert Nathalie , Curutchet Arnaud , Lambert Benoit , Brunel Laurent , Rousseau Karine , Latu Eddy Romain , Frank Thomas 
Published: December 2020

Abstract
To improve the long-term stability of AlGaN/GaN HEMTs, the reduction of gate and drain leakage currents and electrical anomalies at pinch-off is required. As electron transport in these devices is both coupled with traps or surface states interactions and with polarization effects, the identification and localization of the preeminent leakage path is still challenging. This paper demonstrates that thermal laser stimulation (TLS) analysis (OBIRCh, TIVA, XIVA) performed on the die surface are efficient to localize leakage paths in GaN based HEMTs. The first part details specific parameters, such as laser scan speed, scan direction, wavelength, and laser power applied for leakage gate current paths identification. It compares results obtained with Visible_NIR electroluminescence analysis with the ones obtained by the TLS techniques on GaN HEMT structures. The second part describes some failure analysis case studies of AlGaN/GaN HEMT with field plate structure which were successful, thanks to the OBIRCh technique.
Arsenic Segregation Induced Gate Leakage by TEM Failure Analysis
Authors: Liu Binghai , Zhao Si Ping , Er Eddie , Chen Changqing , Ang Ghim Boon , Mo Zhiqiang 
Published: December 2020

Abstract
High gate to source/drain (S/D) leakage was observed at both failed pins and ET structures with random failure signatures. Detailed TEM failure analysis revealed an abnormal thin Nitrogen-rich nitride layer along the poly gate which extended to the S/D regions. Along the abnormal nitride layer, appreciable Arsenic (As) segregation occurred. The segregated As dopants at these interfaces may form a continuous conducting path, accounting for the gate to S/D leakage mechanism. The preferable As segregation at the Silicon nitride interface may be related to a vacancy-assisted As diffusion process.
Direct Plan View FIB Liftout for Near-Surface Defect Analysis in TEM
Authors: Lifson Max L. , Chapman Carla M. , Pokrinchak D. Philip , Campbell Phyllis J. , Chrisman Greg S. , Boren Steven J. , Camillo-Castillo Renata A. 
Published: December 2020

Abstract
Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.
Automated Mapping of Very Large Areas of VLSI Circuit Using SIL
Authors: Lin Chung-Ching , Stellari Franco 
Published: December 2020

Abstract
In this paper, we present a novel system and method for the automated mapping of pattern and spontaneous photon emission from very large areas of VLSI circuit using Solid Immersion Lens (SIL). To the best of our knowledge, this is the first time that such a technique has been developed and demonstrated on a real chip. The system being presented includes an automation software Application Programming Interface (API) to control the microscope used to acquire the images, an acquisition software that allows to automatically navigate the chip, move (hop) the SIL to the desired location, focus the image after the SIL landing, register the acquired images, and stitch them together to create a high resolution mosaic. In this paper, we will present, for the first time, a real life example involving thousands of images acquired from a 90 nm bulk technology test chip that were used to create a mosaic of more than 25 x 25 images covering a total area of approximately 400 x 400 μm2.
Evaluation of TEM-Lamella Oxidation
Authors: Haber Thomas , Gspan Christian 
Published: December 2020

Abstract
This study investigated the origin of detrimental high ohmic behavior of contacts by means of analytical electron microscopy. The root cause for the high resistivity could be identified as delamination of the contact bottom in the nanometer range. Based on the results, we were able to establish a method to identify thin oxide layers using analytical methods without being able to spatially resolve them in a combined focused ion beam instrument and scanning electron microscope.
Effective and Efficient FEOL Defects Localization/Inspection by Selective Mechanical/Chemical Deprocessing
Authors: Peng Ng Hui , Angela Teo , Boon Ang Ghim , Hong Yip Kim , Chen Chang Qing , Quah Alfred , Seng Tam Yong , Lam Jeffrey , Mai Zhi Hong 
Published: December 2020

Abstract
With the rapid development of semiconductor manufacturing technologies, IC devices evolve to smaller feature sizes and higher densities, and thus the task of performing successful failure analysis (FA) is becoming increasingly difficult. Device miniaturization often requires high spatial resolution fault isolation and physical analysis [1]. To cater to the shrinking of devices, extensive process improvements have been conducted at the front-end-of-line (FEOL) structures. As a result, among the numerous types of defects leading to chip failure, FEOL defects are becoming more common for devices of advanced tech nodes [2]. Therefore, it becomes more complexity and difficulty on searching the physical defect. Sample preparation is a key activity in material and failure analysis. In order to image small structures or defects it is often necessary to remove excess material or layers hiding the feature of interest. Removing selected layers to isolate a structure is called delayering. It can be accomplished by chemical etching using liquid or plasma chemistry, or by mechanical means, by polishing off each unwanted layer.
Methods to Reconstruct SEM and Optical Probe Tips Using a FIB Tool
Authors: Lepuschenko Walter , Goulet David 
Published: December 2020

Abstract
Various electrical probing and nano probing solutions are offered for semiconductor or failure analysis labs. Using a focused ion beam (FIB) instrument, it is possible to make modifications to probe tips used in optical and SEM probe stations for improved ohmic contact and probe tip durability. The other added benefit is cost reduction by being able to reconstruct damaged tips. This paper shows various FIB techniques and compares reconstructed tip performance with new probe tips.
Al-Cu Alloy Films Characterization and Studies Using TOF-SIMS, XPS, AFM, EBSD and TEM
Authors: Shao J.J. , Shen Y.Q. , Shen Y. , Zhou Y.K. , Li K. , Chou S.Y. , Liu Y.F. , Hao M. , An W.W. , Hua Y.N. , Xing Z.X. , Li X.M. 
Published: December 2020

Abstract
Aluminum-copper alloys are popular for many applications that take advantage of the combination of properties in the alloys. This paper describes the use of multiple advanced failure analysis tools to analyze the physical and chemical properties of Al-Cu alloy thin films.
Foil Capacitor Characterization and Failure Analysis with Special Respect to Noise Filter Applications
Authors: Jacob Peter 
Published: December 2020

Abstract
An increasing number of foil capacitors (metallized thin film capacitors, MTFC) are used as filters in power converters. Thus, they are constantly connected between power lines (different phases) or between power lines and ground. However, after some years of operation, severe damage cases were observed, where filter capacitors became extremely hot and started a slow process of outgasing which sometimes is even ended by catastrophic burning. Failure analysis of surviving capacitors of the same kind in neighbor phases identified air inclusions as the cause, which led to internal corona discharge. Useful corona discharge measurements, based on a modification of the well-known partial-discharge (PD) tests, made it possible to assess capacitors on their potential risk of such failures. It turned out that many, even new foil capacitors, started internal corona discharge already underneath their official AC voltage specification.
Unique Approaches to Isolate Nanoscale Defect in Snake-Comb Test Structure
Authors: Xie Sujing , Wang Nathan , Chen Chaoying , Wu Qindi 
Published: December 2020

Abstract
Multiple techniques including electrical resistance measurement plus calculation, cross-sectional view of passive voltage contrast (XPVC) sequential searching, planar and cross-section STEM are successfully used to isolate a nanoscale defect, single metallic stringer in a snakecomb test structure. The defect could not be found by traditional failure analysis methods or procedures. The unique approach presented here, expands failure analysis capabilities to the detection of nanometer-scale defects and the identification of their root causes. With continuous shrinking feature sizes, the need of such techniques becomes more vital to failure analysis and root cause identification, and therefore yield enhancement in fabrication.
Magneto-Optical Frequency Mapping System for Very Low Resistance Short Circuit Failure Imaging
Authors: Nakamura Tomonori 
Published: December 2020

Abstract
Magnetic field imaging (MFI) has been an excellent tool for a low resistance failure localization in LSI devices. A Superconducting Quantum Interference Device (SQUID) and a Giant Magneto Resistive (GMR) sensor are well known in this field. A SQUID has extremely high magnetic sensitivity (500 nA, &lt;40 pT/ √Hz)[1], but the spatial resolution is somewhat problematic due to the clearance that is needed for cooling and vacuuming mechanism. A GMR sensor has higher resolution but lower sensitivity (50 uA, &lt;10 nT/√Hz)[1] and, they have less flexibility because the sensor/stage has to be scanned during operation. In this paper, we present a new current imaging method called Magneto-Optical (MO) Frequency Mapping (MOFM). The imaging is based on a laser beam scanning, which allows flexibility and ease of use. The MO signal intensity is inversely proportional to the distance between the sensor and the current path to be detected. Since it can be 10 um or less, i.e., one half of the MO crystal thickness, it practically makes the MOFM’s system sensitivity is 10 uA, it only 20 times lower than a SQUID method, even though the intrinsic sensitivity may be about 250 times or so lower. It can also achieve high special resolution as with the GMR sensor because of the short distance or clearance needed to sense the current. These characteristics are verified with a TEG sample and we present a case in which it is applied for the short circuit failure localization.
Analysis of Write Recovery Time Degradation Caused by Adjacent Storage Node Data in DRAM
Authors: Lee Kwangwon , Nam Incheol , Kim Daesun , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung 
Published: December 2020

Abstract
As microelectronic feature sizes are scaled down, the characteristics and distribution of DRAM data retention time and write recovery time are getting worse. This degradation is due to the increases in the leakage current and resistance of the cell node and the decrease of cell capacitance in DRAM devices. As the physical distance between storage nodes decreases, node potential is increasingly affected by small potential changes in adjacent storage nodes. In this paper, we will show that the one of the most dominant contributors to failure is the adjacent storage node level, and we will demonstrate how node level affects write time delay. The effect of the adjacent storage node level can be correlated with a change in threshold voltage, much like the MOSFET body effect. We define this phenomenon as the lateral body effect, and propose a model for adjacent potential effect using the Buried Cell Array Transistor (BCAT) structure in sub 20nm DRAM.
Implementation of a Visual System to Manage and Improve Failure Analysis Work Flow
Authors: Benz Jason M , Distelhurst Kevin A , Hunt Douglas B , Kontra Rick 
Published: December 2020

Abstract
Many articles and books have been written that discuss and study the techniques of lean thinking and methodologies. The applications of these methodologies have included such industries as manufacturing, health care, and information technology. Application to analytical laboratories has been rare or non-existent due to the inability to apply lean methodologies to a process with ‘unique’ analytical work flows as well as a lack of a direct connection to the manufacturing value stream. The following paper describes the work done in a semiconductor failure analysis laboratory to visualize work flow, design a forecasting model, and create a management system. The result of which has been sustained and improved quality, resource utilization, and delivery of actionable root cause failure analysis.
Symptom or Cause? A Case Study
Authors: Swaminathan Anuradha , Liao Joy , Marks Howard 
Published: December 2020

Abstract
Although there are many advanced technologies and techniques for silicon diagnostics, effective failure analysis to root cause is getting increasingly challenging, as very often the electrical failure analysis data would point to a symptom that is the result of the defect rather than the actual location of the defect. Therefore, a combination of multiple techniques is often employed so that sensitivity of "the cause of the problem" can be observed. This work compiles a successful analysis with the aid of continuous wave laser voltage probing and soft defect localization techniques and presents three cases that are voltage-sensitive fails. The first case is a 28 nm device which failed at-speed scan. The second case is a 28 nm device failing RAM register BIST with high Vmin and the third case is a scan shift failure in a less than 28nm device.
Non-Visible Defect Analysis by the Nanoprobing Methodology
Authors: Chen C.Q. , Ang G.B. , Ng P.T. , Quah A.C.T. , Ng H.P. , Teo A. , Lam J. , Mai Z.H. 
Published: December 2020

Abstract
This paper explains how the authors used nanoprobing techniques and electrical characterization to trace a die failure to a problem with the photoresist used to mask the wafer for ion implantation. Nanoprobing and leakage current measurements revealed significant differences between the inner and outer fingers of a multi-finger native transistor. Based on simulations, the differences can be attributed to severe scattering at the active edge of the Pwell due to problems with the photoresist, resulting in nonuniform doping profiles and die failure.
LASER Combined with Plasma—Will It Be the Future’s Green and Safe IC Decapsulation Method
Authors: Poirier Patrick , Obein Michael 
Published: December 2020

Abstract
LASER techniques are widely used for pre-opening in combination with a final manual or automated wet chemistry decapsulation. Even if most of the ICs may be opened today, and if opening the recently introduced Ag wires packages have been solved with novel chemical recipes, the need for a greener and safer solution is still there. Plasma techniques combined with LASER can be a promising solution to these challenges. In this paper, after a presentation of the state of the art of the different techniques available in laboratories nowadays, the latest solution combining LASER and acid or plasma etching is presented. The paper compares the results obtained with these solutions on Cu an Ag wires devices with pros and cons for each solution. The results presented show the benefits, the constraints and the limitations of each technique regarding the different types of wires used in industry.
Failure Analysis of ILD Delamination—Uncovering Multiple Root Causes
Authors: Castignolles Marie , Zirilli Thomas , Cattey Eric , Lewenstein Justin , Schauer Steve , Liu Wei , Chen Jeff , Hammett Jake , Subramanian Sam 
Published: December 2020

Abstract
FA cannot consist of simply jumping to conclusions. The FA process is validated through correlation with the initial failure and through interpretation of the obtained results, subjective by definition. This paper illustrates the difficulty of analyzing complex failures caused by multiple factors, including wafer fabrication, assembly, and application conditions. Inter-Layer Dielectric (ILD) delamination was experienced on various ICs from the same 250nm technology. A complete set of techniques (C-SAM, laser and optical microscopy, SEM, FIB cross-sections, TEM, EFTEM, SIMS, Auger, delineation) was used as different pieces of the same puzzle to reveal the multiple factors contributing to the ILD delamination failures. Due to the subtle nature of some of the underlying causes, defining an accurate FA approach with appropriate sample preparation and accurate device traceability was critical to understanding this complex, multivariate issue.
Extending the Resolution of Emission Images beyond Diffraction Limits Using Deconvolution
Authors: Lan Fei , Stellari Franco , Shehata Andrea Bahgat , Song Peilin 
Published: December 2020

Abstract
In this work, we demonstrate the effectiveness of deconvolution algorithms in improving the spatial resolution of time-integrated emission images from integrated circuits. A mathematical model of the Point Spread Function (PSF) encompassing both the optical system and the imaging detector properties is used for the deconvolution process. Tuning of the PSF parameters is achieved through the minimization of dedicated cost functions that optimize image resolution while suppressing artifacts in the deconvoluted images. The optimized PSF is then used in both the Lucy-Richardson (L-R) and blind deconvolution algorithms. Results from 32 nm and 14 nm SOI devices show that the deconvolution process significantly improves spatial resolution of time-integrated emission images, pushing their resolution beyond the diffraction limit of Solid Immersion Lenses (SILs).
A Study on a Low Cost Thin Film Antireflection Coating Solution for Failure Analysis Applications
Authors: Awitan Fritz Christian , Garcia Camille Joyce , Doyle Dirk Andrew , Benedict Lawrence 
Published: December 2020

Abstract
An ARC solution that can be used to improve backside imaging for backside photoemission microscopy applications is presented in this paper. Zinc Oxide (ZnO) -based thin films used as ARCs are deposited at the backside of the failing units through a simple and low cost spray pyrolysis technique. An improvised set-up, composed of an atomizer and a hot plate, is used in the experiment. The paper provides evidence of acceptable process repeatability and demonstrates that the technique and the material have important applications in the field of failure analysis. Furthermore, it shows that the application of ARC resulted in better defect localization. The location of the defect is easily been determined upon doing frontside inspection - to - backside image comparison on the deposited unit. By using high kV ion beam passive voltage contrast (PVC) and angled cut focused ion beam (FIB) cross section, we are able to isolate further and show the nature of the defect at the failing block.
Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture
Authors: Schlangen Rudolf , Colburn Jon , Sarmiento Joe , Nelapatla Bala Tarun , Gupta Puneet 
Published: December 2020

Abstract
Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.
Analysis of Retention Time Degradation Caused by Electrostatic Potential Variation between Adjacent Bit-Line and Adjacent Contact Node in DRAM
Authors: Mok Jungil , Kang Byungki , Kim Daesun , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung 
Published: December 2020

Abstract
Systematic retention failure related on the adjacent electrostatic potential is studied with sub 20nm DRAM. Unlike traditional retention failures which are caused by gate induced drain leakage or junction leakage, this failure is influenced by the combination of adjacent signal line and adjacent contact node voltage. As the critical dimension between adjacent active and the adjacent signal line and contact node is scaled down, the effect of electric field caused by adjacent node on storage node is increased gradually. In this paper, we will show that the relationship between the combination electric field of adjacent nodes and the data retention characteristics and we will demonstrate the mechanism based on the electrical analysis and 3D TCAD simulation simultaneously.