bluuebunny/crossref_metadata_2025_split huggingface dataset:
Miniaturization and Biocompatible Encapsulation for Implantable Biomedical Silicon Devices
Authors: Souriau Jean-Charles , Herrera Morales Jorge Mario , Castagné Laetitia , Simon Gilles , Amara Karima , Boutaud Bertrand 
Published: February 2020

Facing demographic aging and surging demand for advanced healthcare, the global market for active medical devices has greatly expanded these last years. Furthermore, microsystem improvement in term of miniaturization offers new perspectives for medical applications. Gradually the electronic devices that were previously external invade the human body in order to improve therapy or physiological parameter measurements. However, biological medium is a new environment for such devices and the packaging has to be reconsidered taking into account new constraints. First of all it is essential to preserve the human body from toxic elements exposure that are usually present on silicon devices such as Cu or Al. Moreover, for functionality and reliability aspect it is also crucial to preserve electronics parts from corrosive substances which constitute the major part of the body.
The objective of this paper is to present new strategy of packaging developed in the CEA-LETI for medical applications which include a Micro Electro-Mechanical Systems (MEMS) accelerometer and an Application-Specific Integrated Circuit (ASIC) inside a hermetic silicon box that could be embedded in a cardiac lead in order to monitor the endocardial acceleration (fig1).
The electronic components are bonded on a wafer silicon interposer and covered by an additional silicon wafer which contain cavities. The wafer bonding is performed at the wafer level using eutectic AuSi solder. The gas content and hermeticity of the package were analyzed using Residual Gas Analysis (RGA) and the standard leak rate, which is assessed based on the formation of water droplet condensation in our package after 20 years, was estimated to ~6 10-13 atm.cc/s which guarantees a life time much more than 20 years.
The final silicon box is encapsulated with biocompatible materials that have high conformality deposition and act as good bi-directional barrier. Materials that had been reported in literature as biocompatible and compatible with fabrication in standard clean rooms were studied. These include Al2O3, BN, SiC, DLC(a-CH), HfO2, SiN, SiO2, SiOC, TiO2 and ZnO. Biodegradation tests were performed in phosphate buffer saline at different temperature. Changes in thickness and chemical composition were monitored by variable angle spectroscopic ellipsometry and x-ray photon electron spectroscopy. Non-cytotoxic test according to in-vitro tests outlined by the norm ISO10993-5 were carried out. Finally, Helium gas permeability measurements of selected packaging layers are also provided.

Figure 1
Microvia Filling in an Acidic Copper Planting Bath with Insoluble Anodes
Authors: Liu Chu-Chi , Dow Wei-Ping 
Published: February 2020

Microvia filling of a printed circuit board (PCB) by acidic copper electroplating has been widely used in electronic industry. The filling mode of copper electrodeposition in microvia must be bottom-up form. Moreover, bottom-up filling phenomenon is believed to be related to the properties and interaction of plating additives. Especially, the interaction of three (accelerator, suppressor, leveler) components have significantly effect on copper filling performance.
It was confirmed that soluble anodes (i.e., P-doped Cu anode) have disadvantage when they were used in the acidic copper plating bath. For instance, the shape of the soluble anodes are changeable with operating time, which may causes non-uniform current distribution to form unequal copper thickness on substrate. Therefore, a special functional insoluble anode was used to replace the soluble anode and conventional dimensionally stable anode (DSA) to maintain better bath stability. The disadvantage of soluble anode can be improved by using the novel DSA.
In this work, a planting formula which was composed of chloride ions, suppressor (polyethylene glycol), leveler (quaternary ammonium species) and a novel accelerator instead of bis(3-sulfopropyl) disulfide (SPS). SPS is not appropriate for DSA system because of easy breakdown; therefore, we develop a novel accelerator, ACC, which has a longer lifetime and better performance for acceleration on copper deposition than SPS. Using DSA instead of P-doped Cu anode has another important contribution, that is, SPS reacts with the copper anode to produce Cu(I)-thiolate. The Cu(I)-thiolate is a strong accelerator in the presence of chloride ion. Cu(I)-thiolate will be accumulated in the copper plating bath to destroy the synergy between the suppressor and accelerator. DSA has no this issue because DSA has no copper. Herein, we will show that ACC combining with DSA can perform excellent copper fill in microvia.
Reduction of Thermal Expansion Coefficient of Electrodeposited Copper
Authors: Kondo Kazuo , Mukahara Shingo , Onuki Jin , Yokoi Masayuki 
Published: February 2020

Introduction

Thermal expansion coefficient(TEC) mismatch between the chip and copper causes serious problems in 3D and PCB interconnections. However no one even ever tried to reduce the TEC of the copper wiring formed by electrodeposition. We are the pioneer to succeed in the TEC reduction of electrodeposited copper.
Results

1.Figure 1 shows the thermal expansion results with and without the additive A. Without the additive A the sample is basically electrodeposited conventional copper and the thermal expansion is linear with the temperature(red line). This linearity holds with multiple numbers of annealing. With the additive A, this copper shrinks with raising the temperature for the first time anneal(green curve). Most materials expands with raising the temperature, and this copper shrinks. For the second time anneal, this copper shows about half of the TEC of conventional copper(blue curve) at 400°C.
2.There are no voids or seams and a perfect filling has been achieved of 4μm width and 25μm depth TSV. In-situ SEM observation of pumping with annealing will be presented at the meeting.
3.Next, let’s discuss the grain size distribution by EBSD. The electron back scattering diffraction(EBSD) observes the back scattering diffraction by irradiating electrons in the crystal sample.
The average grain size is 348nm. With the additive A at 400°C, the average grain size is 360nm and the grain size only grows 12nm. Without the additive A, with annealing, 45 nm growth have been observed(1).
The deference in grain size between room temperature and 400°C is only 12nm with the additive A. Additive A inhibits the grain growth at 400°C.
4.Symbols(⊥) indicate the dislocation(Fig.2). The impurity from the additive A segregates at the grain boundaries. This impurity which segregates at the grain boundary prevents the slipping transformation of piled up dislocations. However, without additive A, this impurity does not segregate at the grain boundaries and the slipping transformation of piled up dislocation is large. So the grain growth occurs without the additive A.
1 Kazuo Kondo, Shingo Mukahara, Taro Hayashi, Minoru,Takeuchi,Takeyasu Saito, Naoki Okamoto, ,ECS, San Fransisco, USA, October(2013)

Figure 1
Superconformal Filling of High Aspect Ratio through Glass Vias for Interposer Applications Using Tnbt and Ntbc Additives
Authors: Dimitrov Nikolay , Ogutu Paul , Fey Edmond 
Published: February 2020

The drive toward higher circuit density and higher operating frequencies in electronic packaging has led to the employment of interposers between the Si chip and the underlying package. Currently Si or glass, both are considered materials feasible for the fabrication of interposers. Through-holes are needed to make connections between the top and bottom surfaces of the interposer. This can be done with conformal Cu plating, but especially in the case of glass it is also desirable to fill the through glass vias (TGVs) with Cu to compensate for its poorer thermal conductivity compared to Si. Filling also enables formation of a flat surface for subsequent layers or for component attachment. Techniques have already been developed for filling “blind” holes/vias by Cu electroplating using combinations of suppressors and accelerators. In the case of Si, through-vias have been generated by first filling holes as blind ones. Then thinning the back side of the wafer by CMP is applied until the bottoms of the filled vias are intersected, thereby producing filled through-holes. Alternatively, sealing one end of the through vias could be made and then one could fill them as blind vias. In the case of glass, TGVs may be formed directly into the glass without the need for mechanical thinning, but this leaves the problem of filling the holes as through-holes, open on both ends. The aforementioned plating methods for filling of blind vias do not work well when directly applied to filling of TGVs, and a different approach is needed.
In this report, Cu superconformal filling of through glass vias (TGV) of aspect ratios (AR) 6:1 and 10:1 for glass interposer applications is achieved by DC electroplating in the presence of the additives tetranitroblue tetrazolium Cl- (TNBT) and nitroblue tetrazolium Cl- (NTBC) in acidic CuSO4/ Cl- formulations. Filling takes place by the so-called ‘butterfly’ mechanism that nucleates Cu plug in the TGV’s center and keeps low surface coverage. Holes of AR 6:1 are filled in 3 hours at 2.5 mA.cm-2, using a bath composed of 40 ppm TNBT, 80 ppm Cl-, 0.88M CuSO4, and 0.3M CH3COOH under stagnant conditions. Increasing [TNBT] to 80 ppm and [Cl-] to 120 ppm in the presence of 0.3 M CH3COOH allows filling of 10:1 AR holes in 12.5 hours at 1.0 mA.cm-2 while maintaining thin surface coverage. In the case of NTBC, 6:1 holes are filled in 4-5 h at 2.5 – 4.0 mA.cm-2, and 10:1 holes are filled in 12-13 h at 1.0 to 1.5 mA.cm-2 in a slowly stirred bath containing 0.88 M CuSO4, 80 ppm Cl-, 0.6 M H2SO4, and 45-50 ppm NTBC. Bath composition is necessary to avoid void-formation in the holes. Effects of composition on overvoltage and Cu surface topography are discussed. Finally, a critical discussion on some mechanistic aspects of the supeconformal filling process, taking place according to the Figure, is also presented.

Figure 1
Novel Si Etching and Dielectric Liner Film Processing Technologies for Low-Cost TSV Packaging
Authors: Morikawa Yasuhiro 
Published: February 2020

In recent years, "2.5D silicon interposers" and "Full 3D stacked" technology for high-performance LSI circuits has attracted much attention since this technology can solve interconnection problems by using TSVs (Through Silicon Vias) to electrically connect stacked LSI circuits. 2.5D and 3D Si integration has great advantages over conventional 2D devices such as a high packaging density, small wire length, high-speed operation, low power consumption, and a high feasibility for parallel processing. Yet, the problem of cost-effective TSV production is still to be solved. In particular, the demand for a new plating bath technology to shorten the Cu plating time is pressing. In addition, TSV isolation liner materials will be necessary with lower cost for the production of future high-frequency devices.
A new etch process has been developed for scallop-free and taper-shaped TSV fabrication [1]. By using a direct etch process instead of cycled etching, TSVs were obtained with smooth-sidewalls and tapered profiles. The absence of scallops has a positive effect on signal transmission speed. Also, the direct etch process allows for shorter TSV fill process times and thus provides lower cost of deposition processes like PE-CVD, PVD and Cu-ECP (electrochemical plating) [2,3]. A cost correlation of taper-shape etching and Cu-ECP (electro-chemical plating) will be included.
For the TSV isolation, polyurea dielectric liners were successfully deposited using a vapor deposition polymerization technology (which is Ulvac’s FPF/PV large panel technology). This process allows for isolation liners in next-generation high-frequency devices and for the film formation into a TSV pattern.
In summary, a novel low-cost TSV fabrication flow can be provided for 2.5 / 3D Si integration in high-frequency applications. The process flow yields scallop-free and taper TSVs, which can be filled effectively with electroplated copper and polyurea dielectric liners.

References

[1] Y. Morikawa, et al., “Scallop Free TSV Etching Method for 3-D LSI Integration”, Proc. Int. Symp. on AVS 57th, Albuquerque, New Mexico, Nov. 1, 2010, p 121.
[2] Y. Morikawa, et al., “A Novel Scallop Free TSV Etching Method in Magnetic Neutral Loop Discharge Plasma”, in Proc. IEEE Electronic Components and Technol. Conf. (ECTC 2012), San Diego, CA, May 29 – June 1, 2012, pp. 794–795.
[3] Y. Morikawa, T. Murayama, Y. Nakamuta, T. Sakuishi, A. Suzuki, and K. Suu, “Total Cost Effective Scallop Free Si Etching for 2.5D & 3D TSV Fabrication Technologies in 300mm Wafer”, Proc. IEEE Electronic Components and Technol. Conf. (ECTC 2013), Las Vegas, NV, USA, May 28 – 31, 2013, pp. 605–607.
Lithium Plating and Stripping in the Framework of a 3D Electrochemical Model
Authors: Hein Simon , Latz Arnulf 
Published: February 2020

The range of application of lithium-ion-batteries (LIB) is vast. It ranges from consumer electronics, like smartphones, to battery packs inside of electric vehicles. While cell size and geometry may differ, the electrodes are subject to the same degradation mechanisms. One of these processes is known as “lithium plating”. While charging a lithium-ion-battery with high currents or during operation at low ambient temperatures ( T < 0 °C), lithium ions can deposit on the surface of the negative electrode. The resulting metallic film can lead to increased solid electrolyte interphase growth, and may even create an electrical short-circuit, potentially causing a thermal runaway of the whole battery. Therefore it is desirable to hinder or, if possible, prevent the deposition of metallic lithium on the electrode surface.
To pursue this objective, a better understanding of which operating conditions, at which spatial locations inside the electrode microstructure and which material most parameters influence the deposition is vital. Since it is not convenient to measure the exact electrochemical situation at the electrode surface during operation, theoretical modeling and simulation is the tool of choice.
We present a model describing the initialization, growth and dissolution of a metallic lithium phase. This model is incorporated into the framework of a 3D microstructure resolved model [1, 2]. This is achieved by extending the mathematical description of the interfaces to consider the governing differential equations of surface species. These surface modifications allow for the simulation of the electrode surfaces, on which metallic lithium nucleates and grows. In the presented model, a complete coverage of the surface with a metallic lithium film results in the blockage of the direct intercalation pathway.
The influence of the geometry of the negative electrode and operating conditions on the cell performance and electrochemical conditions is investigated. The cell voltage plateau during discharge of a LIB, which contains plated lithium, [3, 4] can be attributed to chemical intercalation of metallic lithium into the supporting active material, as well to electrochemical dissolution.
[1] Battery and Electrochemical Simulation Tool, http://www.itwm.fraunhofer.de/best
[2] A. Latz and J. Zausch, J. Power Sources, 196 (2011), pp. 3296–3302.
[3] M. Petzl and M. A. Danzer, J. Power Sources, 254 (2014), pp. 80-87.
[4] B.V. Ratnakumar, M.C. Smart, J. Electrochem. Soc. Trans. 25 (2010), pp. 241-252.
Analyzing Capacitive Characteristics of Lithium-Ion Batteries Using a Distribution Function of the Differential Capacity
Authors: Schoenleber Michael , Ivers-Tiffée Ellen 
Published: February 2020

By analyzing the Distribution Function of Relaxation Times (DRT) of a measured impedance spectrum one can separate different loss processes and thereby study which physical mechanisms contribute how strongly to the overall polarization resistance. The method is based on the idea that certain parts of an impedance spectrum can be represented by a serial connection of parallel RC-Elements [1].
The DRT has been successfully used for analyzing the polarization processes taking place in Solid Oxide Fuel Cells (SOFC) as well as in Li-Ion batteries [2][3]. For the latter however, the analysis had to be limited: Due to the structure of the underlying modelling approach using parallel RC-elements, only the non-capacitive region of the impedance could be analyzed using the DRT. Accordingly, information contained within the capacitive region could not be utilized optimally so far.
For analyzing capacitive characteristics we therefore propose to adapt the concept of DRT to capacitive systems yielding a Distribution Function of Differential Capacities (DDC).
By physical means this function states how much load is intercalated how fast into an electrode after applying a voltage step. Figure 1 further exemplifies the concept by showing
(i) a simple model system consisting of three intercalation pathways.
(ii) the non-measurable intercalation currents over time exhibiting the different time constants with which the partial capacity of different-sized particles can be utilized.
(iii) the according shape of the DDC, which allows to quantify time-constants and capacity contributions of different-sized particles from simple impedance measurements.
Hence, using the proposed DDC allows to easily obtain information regarding an electrodes capacitive characteristics and can therefore serve as a supporting tool for custom-tailoring modern electrode microstructures.
A detailed motivation and derivation of the new method will be given and first results will be shown.
REFERENCES
[1] H. Schichlein, A.C. Müller, M. Voigts, A. Krügel, E. Ivers-Tiffée, “Deconvolution of electrochemical impedance spectra for the identification of electrode reaction mechanisms in solid oxide fuel cells”, J. Appl. Electrochem. 32, p. 875-882 (2002).
[2] A. Leonide, V. Sonn, A. Weber and E. Ivers-Tiffée, “Evaluation and Modeling of the Cell Resistance in Anode-Supported Solid Oxide Fuel Cells”, J. Electrochem. Soc., 155 (1), p. B36-B41 (2008).
[3] J. Illig, M. Ender, T. Chrobak, J. P. Schmidt, D. Klotz and E. Ivers-Tiffée, "Separation of Charge Transfer and Contact Resistance in LiFePO4-Cathodes by Impedance Modeling", J. Electrochem. Soc. 159, p. A952-A960 (2012).

Figure 1
Discovery of New Anode SEI Forming Additives Using an in silico Evolutionary Approach
Authors: Murdock Stuart E. , Hughes Thomas F. , Kwak Shaun H. , Goldberg Alexander , Giesen David J , Cao Yixiang , Sanders Jeffrey , Gavartin Jacob , Dathar G. K. Phani , Halls Mathew D. 
Published: February 2020

To reduce the capacity fade and improve the performance associated with lithium-ion batteries functional additives are used to reduce damage to the electrolyte by forming SEI layers when the cell is charged. Two major factors defining a successful anode SEI former are a high reduction potential and a high reactivity.
High throughput quantum chemistry screening of large libraries of structures is an approach that is becoming more popular with the ever decreasing cost of CPU cycles, however this can be a time consuming and highly curated procedure. The automated evolution of a set of input structures and defining the direction in which chemical properties should be automatically adjusted requires less user management and enables knowledge creation rather than knowledge implementation. As the expense of computing resources decreases a monitored genetic algorithm to improve the chemistry of an initial set of structures can be a faster method requiring less user intervention than traditional high throughput chemistry.
In this presentation we show how we reduce the chemical hardness and increase the reduction potential of a set of potential SEI additives or structures having potential SEI additive traits automatically while additionally suggesting optional structural characteristics that the molecules should have. An improvement of these characteristics of a set of input structures is shown using our genetic optimization through supervised learning.
Computational Modelling Study on Electrochemical Activity of Nanoporous and Bulk Beta MnO2
Authors: Ngoepe Phuti Esrom , Sayle Thi X T , Sayle Dean C 
Published: February 2020

Nanostructured manganese dioxides (MnO2) are among the promising materials for high-capacity lithium-ion batteries [1], lithium air batteries [2] and supercapacitors [3], that can be used in electric vehicles and other consumer electronics. They further have several advantages owing to their high specific energy capacity, low fabrication cost, abundance of the materials in the earth, and environmentally friendly nature [4]. Various experimental methods have been employed for the synthesis of MnO2 with various nano-architectures such as the spheres, sheets, porous, wires, rods [5,6] etc.
Simulated amorphisation recrystallisation method has been successfully used to nucleate and crystallise bulk and nanoporous β-MnO2 [7]. In the current study molecular dynamics simulation reveals that the reason nanoporous β-MnO2 is electrochemically active, in contrast to the parent bulk material, is because strain imposed upon nanoporous β-MnO2 during lithium intercalation does not influence the structure or dimensions of the 1D tunnels in which the lithium ions intercalate and reside. Conversely, the parent bulk material suffers structural collapse of the 1D tunnels under strain.
[1] B.X. Li, G.X. Rong, Y. Xie, L.F. Huang and C.Q. Feng, Inorg. Chem. 2006, 45, 6404.
[2] A. Débart, A.J. Paterson, J. Bao and P.G. Bruce, Angew. Chem., Int. Ed. 2008, 47, 4521.
[3] W. Wei, X. Cui, W. Chen and D.G. Ivey, Chem. Soc. Rev. 2011, 40, 1697.
[4] S. Devaraj and N. Munichandraiah, J. Phys. Chem. C 2008, 112, 4406.
[5] J.H. Cheng, G.A. Shao, H.J. Yu and J.J. Xu, J. Alloys Compd. 2010, 505, 163.
[6] X. Wang and Y. Li, Chem. Eur. J. 2003, 9, 300.
[7] P.E.Ngoepe, R.R. Maphanga and D.C. Sayle, (2013), “Towards the Nanoscale”, Chapter 9 in Computational Approaches to Energy Materials, pp 261-290, edited by C.R.A. Catlow, A. Sokol and A. Welsch, John Wiley and Sons Ltd.