(Keynote) Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices
Authors: Loo Roger , Akula Anjani , Shimura Yosuke , Porret Clement , Rosseel Erik , Dursap Thomas , Hikavyy Andriy Yakovitch , Beggiato Matteo , Bogdanowicz Janusz , Merkulov Alex , Ayyad Mustafa , Han Han , Richard Olivier , Impagnatiello Andrea , Wang Dong , Yamamoto Keisuke , Sipőcz Tamás , Kerekes Árpád , Mertens Hans , Horiguchi Naoto , Langer Robert 
Published: December 2024

The scaling evolution from stacked nano-sheet devices to fork-sheet devices and CFET architectures went together with increased complexities of the epitaxial growth schemes. This is valid for both the Si/SiGe multi-layers which define the thickness of the nano-sheet channels as well as the vertical distance between individual nano-sheets and also for the epitaxially grown source/drain (SD) layers which require a continuous increase in active doping concentration and a reduction in thermal budget without compromising material quality.
Fork-sheet transistors are lateral nano-sheet devices with a forked gate structure [1,2]. The physical separation of n- and p-devices by a dielectric wall enables device scaling and, consequently, sheet width maximization within the limited footprint of low-track-height standard cells. Bottom dielectric isolation has been proposed to circumvent the junction isolation trade-off between punch-through suppression on the one hand and junction leakage and capacitance on the other hand [3]. A typical fabrication scheme includes the challenging epitaxial growth of fully strained Si/Si1-yGey/multi-{Si1-xGex/Si} epi stacks (y>x) where the bottom Ge-rich Si1-yGey layer is later replaced by a SiN/SiCO isolation [4,5].
In the CFET architecture, n- and p-MOS devices are placed on top of each other, thus completely removing the area consumption by the n-p spacing. This allows for further maximizing the effective channel width and, hence, the drive current [6-9]. The architecture can be fabricated following either a monolithic or a sequential approach. In the first option, n- and p-MOS transistors are built on the same wafer, while the sequential fabrication flow is based on wafer-to-wafer bonding techniques. The strengths and challenges of both approaches are discussed in [9]. In the monolithic approach, device fabrication starts with the epitaxial growth of an even more complicated Si/SiGe multi-stack with two different Ge concentrations (Fig. 1) [10], and where Ge-rich Si1-yGey layers are later replaced by isolating dielectrics [9]. Owing to the very small dimensions (e.g., sub-10 nm nano-sheet channel width), high etching selectivity of the Si1-yGey layers towards both Si1-xGex and Si, and excellent process controls are mandatory. This sets stringent requirements on the epitaxial layer stacks (thicknesses and composition control, sharpness of interfaces, and absence of strain relaxation) [4,5,10,11] as well as on the Si1-yGey etch process (high selectivity, limited consumption of Si1-xGex and Si) [11-14].
To alleviate scaling-related contact issues in these devices, high performance metal / SD junctions are key [15]. Selective epitaxial growth (SEG) processes yielding heavy active doping are therefore required (Fig. 2), in addition to introducing innovative contact materials and designs [16-18]. The resulting electrical performance is, however, restricted by doping solubility limits and loading effects (impact of substrate patterning) inherent to scaling. Those must be circumvented to enable the upcoming generations of components. Moreover, novel device architectures add stringent constraints regarding pre-epi cleaning strategies, thermal budgets, and stability [19].
This work describes the material requirements of the different layers and the progress made on the associated epitaxial growth techniques.

Acknowledgements

This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 101007254. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Netherlands, Germany, France, Czech Republic, Austria, Spain, Belgium, Israel. Parts of this work were supported by a JSPS-FWO Bilateral Joint Research Project (file number: VS01522N). The imec core CMOS program members, local authorities and the imec pilot line are acknowledged for their support.

References

P. Weckx et al., IEDM 2017, 20.5.

H. Mertens et al., VLSI 2021, T 2.1.

J. Zhang et al., IEDM 2019, 11.6.

A. Hikavyy et al., ECS Trans.104 (4), p. 139 (2021).

H. Mertens et al., IEDM 2022, 23.1.

P. Schuddinck et al., VLSI 2022, p. 365.

S. Subramanian et al., VLSI 2020, TH3.1.

A. Vandooren et al., VLSI 2022, p. 330.

N. Horiguchi et al., IEDM 2023, 29.1.

R. Loo et al., SSDM 2023, p. 291.

R. Loo et al., ECS Trans. 109 (4), 135 (2022).

Y. Muraki et al., Advanced Etch Technology and Process Integration for Nanopatterning XI, p. 12056-6 (2022).

Y. Oniki et al., Surface Preparation and Cleaning Conference (SPCC), (2020).

J. M. Hartmann et al., Semicond. Sci. and Technol. 25 (10), 105009 (2010).

P. Raghavan et al., 2015 Proc. Cust. Integr. Circ. Conf. 1-5 (2015).

C. Porret et al., IEDM 2022, 34.1.

C. Porret et al., SSDM 2023, p. 287.

F. Panciera et al., Microelectron. Eng. 120, 34 (2014).

E. Rosseel et al., PRIME 2024, Symposium G03: SiGe, Ge & Related Compounds: Materials, Processing and Devices 11 (submitted).

Figure 1