bluuebunny/crossref_metadata_2025_split huggingface dataset:
Failure Mechanism and Root Cause Analysis of UBGA Solder Ball Contamination
Authors: Martinez Vanessa Grace , Almero Alden , Gador Gerard 
Published: December 2020

Abstract
A comparison of the electrical performance and effect of different types of flux to Micro Ball Grid Array (ìBGATM) solder ball quality was conducted. The units using no clean flux were found to exhibit opens failures during off-board testing and programming. Initial analysis conducted showed that the failures were due to contact problems between the solder balls and the test/programming sockets resulting from the presence of a transparent residue on the solder balls. In-depth failure analysis, in parallel with experiments conducted in the assembly line, was performed to determine the root cause of the solder ball contamination. Three failure analysis techniques were employed, namely: Scanning Electron Microscopy (SEM), Energy Dispersive Xray Analysis (EDX), and Fourier Transform Infrared (FTIR) Spectroscopy. An initial experiment was conducted to isolate the cause of the contamination by examining the different modules in the ìBGATM assembly. Failure analysis and experimental data proved that the opens failures were due to the no clean flux residue that was deposited on the surface of the solder ball after the reflow process.
Methodologies for Isolating Faults in Multi Chip Fiber Optic Transceivers That Use GHz Mixed Signal ICs
Authors: Seo Kuhn , Wahl Brent , Mayonte Myrna , Kim Young Gon 
Published: December 2020

Abstract
This paper outlines a methodology which accurately identifies fault locations in Mixed Signal Integrated Circuits (ICs). The architecture of Mixed Signal ICs demands more attention during failure analysis because of the complexity of measuring both the analog and digital signals in a compact circuit. In this paper, the GHz range of data signal or radio frequency (RF) signal from an internal IC circuit will be extracted by a high-impedance active single probe in order to find the internal IC circuit failure locations. The advantages of using a single probe is that it can maneuver to extract data almost anywhere in the circuit, providing ranges of bandwidth in GHz with no loading effect on the circuits during measurement. The process of preparing a sample and extracting a signal will be described.
Missing Metal Pillar Failure Analysis-A Plug Technology Issue
Authors: Nguyen Dat , Campbell Tim , Whitlock Steven , Velaga Ankineedu 
Published: December 2020

Abstract
Smaller technologies and increasing chip functionality has resulted in tightly packed devices and more stacked metal layers. For technologies between 0.25µm and 0.14 µm, stacking packed metal layers required the combination of Tungsten plugs as interconnection and the utilization of Chemical Mechanical Polishing (CMP). “Pillar”, however, is a small metal line, which allows interlevel connections between Tungsten plugs. The size and shape of the pillar can be a yield limiting issue. The process of identification and resolution of the missing metal pillar included yield analysis, electrical and physical failure analysis, root cause analysis and the engineering coordination of photo engineering, etch process engineering, CMP engineering, integration engineering, and inline inspection. Resolving the missing pillar issue has proven to have significant contribution to yield.
Reliability and Failure Analysis of RF MEMS Switches
Authors: De Wolf Ingrid , Jourdain Anne , Witvrouw Ann , Fiorini Paolo , Tilmans Harrie A. C. , van Spengen W. Merlijn , Modlinski Robert 
Published: December 2020

Abstract
In this paper we discuss reliability and failure analysis issues of RF-MEMS capacitive switches. We describe specific instrumentation and methods that can be used for testing and examination of these switches. These include SEM, AFM, SAM, static and dynamic optical investigation and electrical lifetime testing. Processing as well as testing and packaging issues are discussed.
Failure Analysis of the Digital Micromirror Device
Authors: Davis Cary , Mahin Wes , Holdford Becky 
Published: December 2020

Abstract
The Digital Micromirror Device (DMD) is a spatial light modulation Micro-Optical Electro-Mechanical Systems (MOEMS) device used in tabletop projectors, televisions and cinema projection systems. This device creates high resolution, high quality images by deflecting/modulating light with microscopic mirrors. Failure analysis of these devices requires superstructure, package, optics, and substructure approaches. Particles within the active array of a DMD are often killer defects, but those are the subjects of an entire discussion of their own. This paper will show evidence of failures associated with: windows in the package lids, failures of the superstructure area, and failures within the substructure. Methods for removal of the mirrors, as well as other structures, will be covered in greater detail. We will conclude with examples of analysis areas in DMD devices that show how they differ from other types of devices.
Wavefront Coded Imaging Systems for MEMS Analysis
Authors: Barton Daniel L. , Walraven Jeremy A. , Dowski Edward R. , Danz Rainer , Faulstich Andreas , Faltermeier Bernd 
Published: December 2020

Abstract
A new imaging technique called Wavefront Coding allows real-time imaging of three-dimensional structures over a very large depth. Wavefront Coding systems combine aspheric optics and signal processing to achieve depth of fields ten or more times greater than that possible with traditional imaging systems. Understanding the relationships between traditional and modern imaging system design through Wavefront Coding is very challenging. In high performance imaging systems nearly all aspects of the system that could reduce image quality are carefully controlled. Modifying the optics and using signal processing can increase the amount of image information that can be recorded by microscopes. For a number of applications this increase in information can allow a single image to be used where a number of images taken at different object planes had been used before. Having very large depth of field and real-time imaging capability means that very deep structures such as surface micromachined MEMS can be clearly imaged with one image, greatly simplifying defect and failure analysis.
Investigation of Choline Hydroxide for Selective Silicon Etch from a Gate Oxide Failure Analysis Standpoint
Authors: Korchnoy Valentina 
Published: December 2020

Abstract
A robust procedure for poly-silicon wet etch selective to SiO2 is presented. The procedure is applicable for CMOS devices and maintains the integrity of the gate oxide film. The technique uses a 50% wt. choline hydroxide aqueous solution. The optimum etching conditions, which allow exposure of gate oxide to enable its further inspection using SEM or AFM were determined. An investigation of general silicon etching characteristics of choline hydroxide, as etch rate, selectivity and surface quality, has been carried out as well.
In situ Decapsulation of Plastic Encapsulated Devices Mounted to a Printed Circuit Board
Authors: Hylton Ronald R. 
Published: December 2020

Abstract
In situ decapsulation of plastic devices can be used to avoid the removal or alteration of failure mechanisms caused by exposure to desoldering temperatures. This paper describes techniques to decapsulate devices mounted to a printed circuit board using materials that are readily available and easily customized to specific applications. The techniques are extended to the decapsulation of other packaging technologies, such as SBGA packages and chip-on-board assemblies. Finally, post decapsulation cleaning techniques that will not harm the printed circuit board material are presented.
Probeless FA Approach: A Breakthrough Simulation Based Failure Analysis Method
Authors: Lock ChoonHou , Wong YikChoong , Siek KahHee 
Published: December 2020

Abstract
A breakthrough approach was developed in which failure analysis (FA) of advanced microprocessor was carried out without the use of defect localization equipment. This technique enables the reading of internal signal value without the use of any physical probing method. This method demonstrates the same FA capability with higher success rate and shorter analysis time.
Electrical Faults Captured by In-line E-beam Inspection and Failure Analysis
Authors: Song Z.G. , Ang G.B. , Li H.Y. , Sane V. , Indahwan J. , Ansari S. , Tee S.F. , Richter W. , Oh C.K. , Redkar S. 
Published: December 2020

Abstract
Fault isolation is a critical step of failure analysis, which is most important for yield improvement for any new microelectronic device manufacturing. Conventionally, electrical faults are isolated by emission microscopy, liquid crystal, LIVA/TIVA and ORBIRCH etc. techniques after final test. As microelectronic devices are becoming more complicated and with multiple metal layers, failure analysis faces more challenges than before. These challenges are even tougher in wafer foundries because little device information is available. This makes yield ramp-up take longer time. Utilizing inline E-beam inspection equipment, the electrical faults can be captured at the source layer rather than after final test. E-beam inspection can be incorporated in the manufacturing line at any critical layer of front end and back-end. This paper describes the in-line E-beam inspection and presents three cases: (1) Gate-oxide issue, (2) Contact issue, and (3) Interconnect issue to demonstrate its application.
Effect of Corner Underfill Voids on Chip Scale Package (CSP) Performance Under Mechanical Loading
Authors: Canumalla Sridhar , Shetty Santosh , Hannan Nael 
Published: December 2020

Abstract
The critical impact of corner voids on the anticipated reliability of CSP subjected to mechanical stresses is demonstrated in this paper. Experimental and numerical simulation results indicate that the presence of a corner underfill void subjects the solder joint to stress values approaching that of a non-underfilled CSP. In the absence of underfill voids, the reliability in drop testing improved when the CSP was underfilled, and the improvement was inversely proportional to the modulus of the underfill in the range studied. Results indicate that underfill quality could potentially play a critical role in determining reliability in the field for products subjected to mechanical loading.
Method for Measuring Package to Board Interconnection Shear Strength for Area Array, Fine Pitch Packages
Authors: Yee Sridhar , Yang Hee Dong , Viswanadham Puligandla 
Published: December 2020

Abstract
The package to board interconnection shear strength (PBISS) test method yields an amalgamated measure of pad peel strength, solder/pad interfacial strength and bulk solder shear strength. This measure mirrors the reliability of the actual product better than any single component strength value. Using a novel fixture that ensures pure shear stresses on the package, the shear strengths of two different ball grid array packages with Sn62PbAg2 solder balls are characterized as a function of pad finish and board build-up layer type. The tests can be performed relatively quickly (&lt; 15 minutes for an entire package on board) with good repeatability. Results indicate that the component shear test is sensitive to the variables studied and attractive as a candidate technique for quantifying solder joint quality and integrity on actual production samples for a variety of package types and sizes. Potential applications of this method are for materials/process/vendor evaluation during product development phase and as a production/supplier quality assessment tool in the factory. Key words: interconnection strength, shear test, area array package, solder joint, pad surface finish
Scanning SQUID Microscopy for Die Level Fault Isolation
Authors: Vallett David P. 
Published: December 2020

Abstract
This paper presents detailed results of scanning SQUID microscopy (SSM) analyses performed on the frontside and backside of both loose and packaged die. Optical and SEM images of localized defects are shown. Comparisons with alternative physical fault isolation (PFI) techniques like liquid crystal (LC), Schlieren thermal mapping (STM), temperature induced voltage alteration (TIVA), and photon emission microscopy (PEM) are included. Finally, limitations with and potential improvements for die level SSM are also discussed.
A Successful Failure Localization Approach for Defect Identification on High Resistance Interconnects
Authors: Lin Yu-Ting , Huang Y.S. , Lee C.S. , Cheng C.M. , Hsu Will 
Published: December 2020

Abstract
The emission microscopy effectiveness has been proven in detecting a variety of IC process leakage defects over the years. However this technique shows limitation on high resistance backend process defects localization, especially on function failures with frequency dependent but without leakage current. This paper introduces three trigger algorithms to enable precisely and directly defects localization of high resistance interconnects.
Backside FIB Device Modifications Through the BOX Layer of an SOI Device
Authors: Huynh Jeffery P. , Shannon Joseph P. , Johnson Richard W. , Santana Mike , Chu Thomas Y. , Gonzalez Manuel 
Published: December 2020

Abstract
Modifications directly to a transistor’s source/drain and polysilicon gate through the backside of a SOI device were made. Contact resistance data was obtained by creating contacts through the buried oxide layer of a manufactured test structure. A ring oscillator circuit was modified and the shift in oscillator frequency was measured. Finally, cross section images of the FIB created contacts were presented in the paper to illustrate the entire process.
Coaxial, Photon-Ion Technology Enables Direct Navigation to Buried Nodes on Planarized Surfaces, Including Silicon
Authors: Thompsona M. A. , Le Roya E. , Lundquista T. , Thompsona W. B. , Richardsonb C. 
Published: December 2020

Abstract
The limitation of Focused Ion Beam (FIB) and all charged beam technologies are their insensitivity to the internal composition of materials relative to surface composition. For the most part, charged particle technology cannot provide the resolution at a depth necessary for locating traces either buried under passivation or through silicon. Before CMP planarization was utilized in the industry, it was possible to correlate passivation topography with buried metal traces and manually navigate to the correct x-y coordinates necessary for edit placement. There was still a level of difficulty and CAD navigation helped immensely. With the advent of CMP-planarized metallization, CAD navigation became a necessity, yet still required passivation topography for precise alignment. Current manufacturing processes now planarize all layers, including the passivation, increasing the overall difficulty of navigation. Techniques of drilling “seeker” holes or surface demarcation using FIB and lasers to establish reference fiducials are used extensively [1,2]. Seeker holes and optical-to-FIB image correlation have been useful workarounds for the navigation-related problems presented by advanced ICs. In this paper we will discuss the advantages of Real-Time Optical Imaging coaxially integrated into the FIB, providing non-invasive navigation to nodes for front side and backside applications.
Electron Beam Induced Luminescence
Authors: Miller N.C. , Rispoli K.P. 
Published: December 2020

Abstract
A method to detect defects affecting laser diode radiation has been devised by imaging the induced luminescence resulting from a scanning electron beam. Electron Beam Induced Luminescence (EBIL) involves imaging the current from a sensor diode as the SEM electron beam scans across the laser diode surface. Defects preventing laser diode radiation will be shown as contrast variations in the EBIL image. This technique is similar to electron beam induced current (EBIC), reference 1, in which the electron beam provides the capability for measuring subsurface electrical and physical parameters that effect device electrical performance. However in the case of EBIL, laser diode radiation is utilized as the imaging parameter providing direct correlation between the semiconductor active layer and the resultant diode luminescence output. Alternative techniques such as Cathode Luminescence (CL), reference 2 and 5, in the scanning electron microscope (SEM) have been used for examination of semiconductor laser diodes for defects preventing radiation. However CL SEM analysis requires costly accessories, including at least an ellipsoidal mirror and a cooled photomultiplier tube sensitive to the particular laser diode output frequency. In addition the laser diode must be at the focal point of an ellipsoidal mirror, making CL SEM examination of a packaged laser diode difficult or impossible. This paper will describe the EBIL technique using several test diodes to demonstrate the ability of EBIL to image diode luminescence and defects affecting luminescent output. Deprocessing of the laser diode top electrode and EBIL operating parameters will be discussed.
What Can a Failure Analyst Do With an AFM?
Authors: Erickson Andrew N. 
Published: December 2020

Abstract
Atomic Force Microscopy (AFM) is gaining acceptance as a mainline failure analysis tool. Acceptance has come as the number of applications has multiplied. The serious analyst will find at his disposal a means of mapping minute changes in properties such as temperature, current, electric field, capacitance, resistance, voltage, and doping concentration. Each of these properties can be viewed in an image with resolution from microns to angstroms. Furthering its application the AFM is being used to probe sub-quarter micron nodes. The AFM’s intrinsic imaging and force control lend itself well to this job. However, traditional microscopes and probes are not well suited to the application. This paper describes the requirements and solutions to allow for nanometer probing applications.
Conducting Atomic-Force Microscopy Investigations on Thin Silicon Gate Oxides: Influence of Tip Shape and Humidity
Authors: Kremmer S. , Peissl S. , Teichert C. , Kuchar F. 
Published: December 2020

Abstract
Conducting Atomic-Force Microscopy (C-AFM) has a strong potential for the characterization of thin silicon oxides on the nanometer scale. Here we consider difficulties and possible errors that may arise during C-AFM experiments. Using electrostatic simulations it is shown that very sharp tips can cause an inhomogeneous electric field distribution leading to an error in the measured Fowler-Nordheim (FN) current. Further, it is found that a water film, which is ever present under ambient conditions, on the one hand homogenizes the electric field distribution but on the other hand decreases the resolution of the measurements. For increased oxide thickness this water film leads to a ring formation in the electric field maximum and therefore makes an interpretation of FN current maps difficult. The occurrence of protrusions after the applying of voltage pulses and voltage ramps to the sample is investigated by comparing experiments under ambient conditions with measurements in ultra high vacuum (UHV). From this comparison we can conclude that the observed protrusions are real topographic effects, when a water film is present on the surface. However, for UHV experiments on a baked sample it is not yet clear if the protrusions are due to charging effects or due to a reaction with a residual amount of water.
A Study on Non-Stick Aluminium Bondpads Due to Fluorine Contamination Using SEM, EDX, TEM, IC, AUGER, XPS and TOF-SIMS Techniques
Authors: Hua Y. N. , Redkar S. , Lau C. K. , Mo Z. Q. 
Published: December 2020

Abstract
Fluorine contamination on Al bondpads will result in corrosion, affect quality of bondpads and pose problem such as non-stick on pad (NSOP) during wire bonding at assembly process. In this paper, a fluorine contamination case in wafer fabrication will be studied. Some wafers were reported to have bondpad discoloration and bonding problem at the assembly house. SEM, EDX, TEM, AES and IC techniques were employed to identify the root cause of the failure. Failure analysis results showed that fluorine contamination had caused bondpad corrosion and thicker native aluminium oxide, which had resulted in discolored bondpads and NSOP. It was concluded that fluorine contamination was not due to wafer fab process, but was due to the wafer packaging foam material. XPS/ESCA and TOF-SIMS advanced tools were used to study the chemical and physical failure mechanism of fluorine-induced defects. An unknown Al compound was found using XPS technique and identified it as [AlF6]3- using electrochemical theories and TOF-SIMS technique. This finding was very significance, as it helped developing a theoretical electrochemical model for fluorine-induced corrosion and helped understanding of the mechanism of fluorine-induced corrosion on aluminium bondpads. It was found that fluorine contamination had formed [AlF6]3-on the affected bondpads and it had caused further electrochemical reactions and formed some new products of (NH4)+ and OH-. Then [AlF6]3- and (NH4)+ ions combined and formed a corrosive complex compound, (NH4)3(AlF6), while the OH- reacted with Al and caused further corrosion.
Hot Disk: A Transient Plane Source Technique for Rapid Thermal Conductivity Measurement
Authors: He Yi , Ng Grace S. 
Published: December 2020

Abstract
Hot disk metrology represents a transient plane source measurement technique for characterizing thermal conductivity and thermal diffusivity of a wide range of materials. In this technique, the hot disk sensor serves as a heat source and a thermometer. During the measurement, the sensor is sandwiched between two halves of a sample and a constant current is supplied to the sensor. The temperature increase at the sensor surface is strongly dependent on the thermal transport properties of the surrounding material. By monitoring the temperature increase as a function of time, one can determine the thermal conductivity and thermal diffusivity of the surrounding material. The main advantages of the hot disk technique include: wide thermal conductivity range, from 0.005 W/m·K to 500 W/m·K; wide range of materials, from liquid to solid; easy sample preparation; non-destructive; and more importantly, high accuracy (within 2% or better). In this paper, the basic theory of the hot disk technique will be discussed based on first principles. This technique has been successfully used to characterize a variety of thermal interface materials (TIMs) used in electronic packaging. The experimental results are in good agreement with the results obtained by another method.
Infrared Emission-based Static Logic State Imaging on Advanced Silicon Technologies
Authors: Bockelman Daniel R. , Chen Steven , Obradovic Borna 
Published: December 2020

Abstract
A technique is presented for mapping the logic states of CMOS integrated circuits by observing their static infrared emission. Application of the technique is shown in two case studies. The technique has the advantages of being non-invasive, having high observability and reduced complexity compared with dynamic probing techniques.
N-Channel Sub-Threshold Leakage “Pipes” Generated From Micro-Twinning Near Shallow Trench Isolation Interface
Authors: Spory Erick M. 
Published: December 2020

Abstract
The pursuit of shorter and narrower channel transistor processes, especially those employing Shallow Trench Isolation (STI), can readily produce devices that are increasingly susceptible to the formation of sub-threshold, leakage-generating defects. Specifically, STI N-channel devices exhibiting lengths at or below 0.35 um and with widths below 1 um, are at a heightened risk of developing a channel micro-twin defect “pipe” due to the very high compressive stress within the silicon lattice. Wider, sub-0.35 um devices can also exhibit the problem if their channels are in extremely close proximity to an active/STI corner region. Modification of the relevant process parameters can significantly alleviate this stress and reduce the frequency of “pipe” formation.