bluuebunny/crossref_metadata_2025_split huggingface dataset:
Identification of Wet Chemical Deprocessing Induced Artifacts—A Common Problem Affecting All MOS and CMOS Technologies
Authors: Mendaros Raymond G. , Marquez Christian Renan B. , Mazon Bernardino D. 
Published: December 2020

Abstract
Wet Chemical Deprocessing is one of the techniques in exposing embedded structures in an integrated circuit (IC). Layers of the die from the passivation to silicon substrate can be selectively etched using this technique. From series of evaluations conducted, it was discovered that there are silicon damage sites that are induced during wet chemical deprocessing. Their physical attributes are almost identical to the attributes of electro-static discharge (ESD) defects. It only differs in the locations where they occur. ESD defects are expected near the edges of the transistors’ gate channel where high electric fields are present while deprocessing artifacts are observed at the center of the gate channel. Deprocessing artifacts are represented by mechanically induced damage sites in the silicon substrate. These mechanical damage sites manifest in the form of silicon pits, voids, slits and fractures as a result of tensional or shearing stresses in the silicon substrate when the polysilicons separate from the silicon substrate. If deprocessing artifacts are not well understood by the analysts then these can be mistakenly reported as ESD or fabrication defects.
Process Flow Employed for Parametric Test Structure Chain Opens Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries
Authors: Kodali Satish , Ma Yinzhe , Oh Chong Khiam , Zhao Wayne , Beaudoin Felix 
Published: December 2020

Abstract
With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of a line. This work provides a process flow sheet for root cause identification on chain opens on advanced 20 nm and sub-20 nm technologies setting a standard guideline for a specific category fail type. It provides a consistent way of attack in a much more streamlined fashion. Further, dependability on TEM rather than convention FIB cross-sections provides shortest time to root cause identification. Three typical cases encountered are discussed to demonstrate the idea: embedded chain opens by electron beam absorbed current (EBAC) isolation, chains opens at level by EBAC isolation, and chains opens at level by passive voltage contrast isolation.
Direct Charge Measurement in Floating Gate Transistors of Flash EEPROM Using Scanning Electron Microscopy
Authors: Courbon Franck , Skorobogatov Sergei , Woods Christopher 
Published: December 2020

Abstract
We present a characterization methodology for fast direct measurement of the charge accumulated on Floating Gate (FG) transistors of Flash EEPROM cells. Using a Scanning Electron Microscope (SEM) in Passive Voltage Contrast (PVC) mode we were able to distinguish between '0' and '1' bit values stored in each memory cell. Moreover, it was possible to characterize the remaining charge on the FG; thus making this technique valuable for Failure Analysis applications for data retention measurements in Flash EEPROM. The technique is at least two orders of magnitude faster than state-of-the-art Scanning Probe Microscopy (SPM) methods. Only a relatively simple backside sample preparation is necessary for accessing the FG of memory transistors. The technique presented was successfully implemented on a 0.35 μm technology node microcontroller and a 0.21 μm smart card integrated circuit. We also show the ease of such technique to cover all cells of a memory (using intrinsic features of SEM) and to automate memory cells characterization using standard image processing technique.
Optimizing Gas-Assisted Processes for Ga and Xe FIB Circuit Edit Application
Authors: Ray Valery , Oboňa Josef V. , Sharang Sharang , Rotkina Lolita , Chang Eddie , Tolua Kevin 
Published: December 2020

Abstract
Despite commercial availability of a number of gas-enhanced chemical etches for faster removal of the material, there is still lack of understanding about how to take into account ion implantation and the structural damage by the primary ion beam during focused ion beam gas-assisted etching (FIB GAE). This paper describes the attempt to apply simplified beam reconstruction technique to characterize FIB GAE within single beam width and to evaluate the parameters critical for editing features with the dimensions close to the effective ion beam diameter. The approach is based on reverse-simulation methodology of ion beam current profile reconstruction. Enhancement of silicon dioxide etching with xenon difluoride precursor in xenon FIB with inductively coupled plasma ion source appears to be high and relatively uniform over the cross-section of the xenon beam, making xenon FIB potentially suitable platform for selective removal of materials in circuit edit application.
Nonwetting Effects of Si Contamination on Cu Bumps of a Flip Chip Package—A Case Study
Authors: Salamania Janella Mae R. 
Published: December 2020

Abstract
Presence of foreign materials (i.e, contamination) can affect the reliability of copper (Cu) bumps when it affects the wettability of the solder and consequently weakens the joint formation of the copper to the substrate. This paper looks at a case of non-wetting of Cu bumps due to silicon contamination induced during assembly processing. In this case study, surface roughness is the main factor being altered when foreign materials contaminate the metal substrate. Sample devices were tested in a resistive open unit and a direct current failing unit, respectively. It was found that the silicon dust present on the substrate in effect "roughens" the surface, thereby decreasing the wettability between the molten solder to the metal substrate. For future studies, it is recommended that the effect of reliability stress activities on the Cu bumps with silicon contaminations be examined to evaluate the risks for possible field failures of this defect.
Application of Electro Optical Terahertz Pulse Reflectometry for Fault Localization and Defect Analysis
Authors: Lin Yi-Sheng , Hsiao Yu-Hsiang , Lee Shu-Hua 
Published: December 2020

Abstract
Electro Optical Terahertz Pulse Reflectometry (EOTPR) is an E-FA (Electrical Failure Analysis) technique in the semiconductor industry for non-destructive electrical fault isolation for shorts, leakages and opens. This paper introduces the capability and presents several case studies identifying the physical location of defects where EOTPR is useful as a non-destructive analysis technique. In this paper, the methodology and application of EOTPR on open and short failure isolations in advanced 2.5D IC and wafer level packages (WLP) have been presented. The experimental results of P-FA (Physical Failure Analysis) verify the accuracy of the EOTPR system in determining the distance to defect.
A Study on the Cause and Improvement Method of Aluminum PAD Disappearance Defect in TSV Package Process
Authors: Kim Boem-Su , Park Su Hyeon , Kim Hyoung Ryeun , Hwang Sung Min 
Published: December 2020

Abstract
Through Silicon Via (TSV) Package (PKG) technology that forms a 3D stack with chip to chip or wafer to wafer contact, uses a variety of wet chemicals unlike conventional package technology. Therefore, new kinds of defects related to the wet chemical occur. In this a new failure mode of disappeared Al pad will be presented, a problem came up to disappear Al pad, which served as the fiducial key during the metal residue removal process after forming the TSV PKG front bump, the mechanism of disappearance of Al pad was investigated. Through chemical analysis of process and equipment, we found that Cu etchant (including H3PO4) can damage for Al pad. The process simulation demonstrated that Al pad actually disappeared. Therefore, it confirmed that it needs to be removed through sufficient rinsing time after applying the wet chemical applied to the TSV PKG process. As a result we solved problem through modified equipment and increased rinsing time.
Device Channel Temperature Measurement Using NIR Emission
Authors: Weger Alan J. , Stellari Franco , Song Peilin 
Published: December 2020

Abstract
In this paper, we present a technique for device temperature measurement using spontaneous near infrared (NIR) emission from an Integrated Circuit (IC). By leveraging modeling and data analysis, time-integrated emission measurements are used to estimate the temperature increase due to switching activity inside the channel of CMOS transistors. The non-invasive nature of the technique allows one to reliably monitor the temperature of any device on-chip without the need for circuit modifications or dedicated on-chip sensors and with a higher spatial resolution than thermal cameras. This method has important applications for modeling heat dissipation during early process development, localizing hot spots, calibrating on-chip sensors, etc. In this paper, temperature is estimated by fitting empirical emission data to an emission model that can be solved for device channel temperature.
Picosecond Time-Resolved LADA Integrated with a Solid Immersion Lens on a Laser Scanning Microscope
Authors: Dickson Kris , Erington Kent , Bodoh Dan , Serrels Keith , Petri Charles , Ybarra Juan , Ly Khiem 
Published: December 2020

Abstract
We present an upgraded time-resolved LADA system, with a 25ps pulsed laser, integrated into a commercial laser scanning microscope used in failure analysis. We demonstrate the use of this system on 14nm/16nm finfet devices.
Ion Milling of Ex-Situ Lift-Out FIB Specimens
Authors: Campin M.J. , Bonifacio C.S. , Boccabella M. , Fischione P.E. , Kang H.H. 
Published: December 2020

Abstract
The semiconductor industry is constantly investigating new methods that can improve both the quality of TEM lamella and the speed at which they can be created. To improve throughput, a combination of FIB-based preparation and ex situ lift-out (EXLO) techniques have been used. Unfortunately, the carbon support on the EXLO grid presents problems if the lamella needs to be thinned once it is on the grid. In this paper, we present low-energy (&lt;1 keV), narrow-beam (&lt;1 μm diameter), Ar+ ion milling as a method of preparing electron-transparent and gallium-free EXLO FIB specimens.
Increasing FA Throughput in Challenging Samples Utilizing TRUE X-Sectioning and the Rocking Stage
Authors: Šikula Marek , Hrnčíř Tomáš , Gounet Pascal 
Published: December 2020

Abstract
An advanced sample preparation protocol using Xe+ Plasma FIB for increasing FA throughput is proposed. We prepared cross-sections of 400 μm and wider in challenging samples such as a BGA (CSP), bond wires in mold compound or a TSV array. These often suffer from FIB milling artifacts. The unsatisfactory quality of the cross-section face is mainly due to extremely different milling rates of the various materials (polyimide, tin, copper, mold compound, platinum), ion beam induced ripples [1] or due to significant surface topography. We explored the usability of the protocol for standard cross-sections and also tested the preparation of TEM lamellae. The process parameters of the proposed approach were compared with the standard methods of Xe+ Plasma FIB FA with respect to preparation time and cross-section quality. Aiming for ultimate results, we incorporated the Rocking stage technique which also greatly improves cross-section quality.
Fin Level Defect Isolation Inside a FinFET Using Electron Beam Alteration of Current Flow
Authors: Ryu H.J. , Shah A.B. , Wang Y. , Chuang W.-H. , Tong T. 
Published: December 2020

Abstract
When failure analysis is performed on a circuit composed of FinFETs, the degree of defect isolation, in some cases, requires isolation to the fin level inside the problematic FinFET for complete understanding of root cause. This work shows successful application of electron beam alteration of current flow combined with nanoprobing for precise isolation of a defect down to fin level. To understand the mechanism of the leakage, transmission electron microscopy (TEM) slice was made along the leaky drain contact (perpendicular to fin direction) by focused ion beam thinning and lift-out. TEM image shows contact and fin. Stacking fault was found in the body of the silicon fin highlighted by the technique described in this paper.
Advanced In Situ X-ray Metrology for Thermal Interface Materials Package Failure Analysis
Authors: Li Peng , Mar Alfred La , Liu Yongmei , Goyal Deepak 
Published: December 2020

Abstract
Innovative in situ X-ray metrologies for package failure analysis (FA) were developed to understand solder thermal interface materials (STIM) package process and failure mechanisms through elevated temperature. Dynamic STIM void formation mechanism and STIM bleeding-out dependency on reflow were observed. It was found that long sit time before STIM liquidus temperature helps to minimize the STIM void formation and fast cooling mitigates the STIM bleed-out risk. Our studies demonstrate that in situ metrologies offer direct guidance to packaging process optimization and accelerate root-cause identification for temperature induced package failures; therefore, it improves throughput-time for packaging technology development.
Sample Preparation Techniques for Reduced Lateral Heat Distribution and Implications for Non-IR Probing on Integrated Circuits
Authors: Mulholland Matthew M. , Vlasyuk Vladimir V. , Wadell Robert P. , Khan Imran , Bakken Nathan J. 
Published: December 2020

Abstract
Validation techniques on packaged integrated circuit (IC) samples positively impact time to market (TTM) by saving considerable fabrication modification turnaround time and costs. The validation techniques are typically done by working through the backside of the chip. These validation and debug techniques, such as optical probing, use the Solid Immersion Lens (SIL) for imaging and data collection. Solid Immersion Lens based near infrared (NIR) optical probing systems have been an integral function in the product life cycle enabling a fast, reliable, and low defect product to market. For the SIL configuration, the remaining silicon thickness (RST) target is specified to be 50 +/- 5um. The sample preparation tools and techniques to accomplish this have been fully developed and matured enough to provide this specification for all segment form factors. This silicon thickness is also within a sustainable thermal envelope at certain power densities during debug electrical testing and validation. As we move into the next generation of optical probing debug in the visible range, increasing resolution further, new sample preparation methods need to be developed. There are a number of different strategies and techniques to prepare the sample, while also enabling efficient heat transfer. This paper will detail some of the sample preparation techniques as a function of silicon thickness and aspect ratio. These final geometries will then be characterized thermally by investigating lateral heat distribution and junction temperature within the silicon Region of Interest (ROI). Finally, based on this sample preparation and thermal study, implications around debug techniques for optical probing will be discussed.
Measurement of Dielectric Constant and Doping Concentration of a Cross-Sectioned Device by Quantitative Scanning Microwave Impedance Microscopy
Authors: Iyer D. , Messinger A. , Crowder R. , Zhang Y. , Amster O. , Friedman S. , Yang Y. , Stanke F. 
Published: December 2020

Abstract
Scanning microwave impedance microscopy (sMIM) is an emerging technique that can provide detailed information beyond that of conventional scanning capacitance microscopy (SCM), and other electrical scanning probe microscopy (SPM) techniques, for the investigation and failure analysis (FA) of semiconductor devices. Integration of new dielectric materials at lower levels of the device structure with the need for quantification of dielectric and dopants in semiconductor devices with sub-micron spatial resolution pushes the practical boundaries of typical atomic force microscopy (AFM) electrical modes. sMIM can measure both linear and non-linear materials (insulators and doped semiconductors, respectively) simultaneously. sMIM has a linear response to log k (dielectric number) and log N (doping concentration) making it an ideal method for providing quantitative measurements of semiconductor devices over a large range of values. This work demonstrates an example of a practical application of sMIM for quantitative measurement of the dopant concentration profile in production semiconductor devices. A planar dopant calibration sample is used to calibrate the sMIM prior to performing the measurements on an “unknown” production device. We utilize nanoscale C-V data to establish a calibration curve for both n- and p-type carriers and apply the calibration curve to an “unknown” device, presenting the measurements in units of doping concentration.
Advanced T-LSIM System Detections using Amplified External Isolated Source-Sense Unit
Authors: Lau Zhi Jie , Philips Chris 
Published: December 2020

Abstract
Thermal-Laser Signal Injection Microscopy (T-LSIM) is a widely used fault isolation technique. Although there are several T-LSIM systems on the market, each is limited in terms of the voltage and current it can produce. In this paper, the authors explain how they incorporated an Amplified External Isolated Source-Sense (AxISS) unit into their T-LSIM platform, increasing its current sourcing capability and voltage biasing range. They also provide examples highlighting the types of faults and failures that the modified system can detect.
FIB-Based Sample Preparation for Localized SCM and SSRM
Authors: Lorut Frédéric , Valéry Alexia , Chevalier Nicolas , Mariolle Denis 
Published: December 2020

Abstract
Dopants imaging using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy are used for identifying doped areas within a device, the latter being analyzed either in a top view or in a side view. This paper presents a sample preparation workflow based on focused ion beam (FIB) use. A discussion is then conducted to assess advantages of the method and factors to monitor vigilantly. Dealing with FIB machining, any sample preparation geometry can be achieved, as it is for transmission electron microscopy (TEM) sample preparation: cross-section, planar, or inverted TEM preparation. This may pave the way to novel SCM imaging opportunities. As FIB milling generates a parasitic gallium implanted layer, a mechanical polishing step is needed to clean the specimen prior to SCM imaging. Efforts can be conducted to reduce the thickness of this layer, by reducing the acceleration voltage of the incident gallium ions, to ease sample cleaning.
OBIRCH for Isolating High and Low Resistance Test Structure Failures During Sub-14nm Technology Development
Authors: Masnik John , Saujauddin Noor Jehan , Davidson Kevin , Chen Esther P.Y. , Beaudoin Felix 
Published: December 2020

Abstract
OBIRCH is a static technique for isolating both high and low resistance failures in test structures that continues to be relevant to sub 14nm technologies. While limited resolution is a factor as devices get smaller, an approximate location is adequate for finding obvious defects on sub 14nm technology structures. Its speed is what makes this technique appealing. If the approximate location isn’t good enough, a more time-consuming, higher-resolution technique can be employed. But the use of OBIRCH as a first isolation technique saves considerable time for a high volume FA lab if obvious defects cause the majority of failures. The seven case studies on sub 14nm technology are examples of obvious defects where OBIRCH had adequate resolution for isolation. The OBIRCH results for the first example are compared to the PVC (Passive Voltage Contrast) and EBAC (Electron-Beam Absorbed Current Imaging) findings to illustrate each technique’s strength and weakness.
Mitigation of Dielectric Charging in MEMS Capacitive Switches with Stacked TiO2/Y2O3 Insulator Film
Authors: Birmpiliotis D. , Koutsoureli M. , Buhagier L. , Papaioannou G. , Ziaei A. 
Published: December 2020

Abstract
Metal-insulator-metal (MIM) capacitors with single TiO2 and a TiO2/Y2O3 stack are used as insulator films in MIM and MEMS, respectively, are explored. It is found that, under electron injection from bottom electrode, the TiO2 MIM capacitors demonstrate resistive switching with a magnitude of leakage currents not usable for MEMS application. The deposition of a stacked TiO2/Y2O3 dielectric film improves the MEMS performance without compromising the low dielectric charging of TiO2 single layer.
Identifying the Root Cause of Source-Drain Leakage Caused Soft Fail in Advanced Bulk FinFET Devices
Authors: Chen Liangshan , Wei Yuting , Schaeffer Tanya , Oh Chongkhiam 
Published: December 2020

Abstract
The paper reports the investigation on the root cause of source-drain leakage in bulk FinFET devices. While the failing device was readily isolated by nanoprobing technique and the electrical analysis pinpointed the potential defect location inside the Fin channel, the identification of physical root cause went through extreme challenges imposed by the tiny-sized device and the unique FinFET 3D architecture. The initial TEM analysis was misled by the projection of a species in the lamella surface and thus could not explain the electrical data. Careful analysis on the device structure was able to identify the origin of the species and led to the discovery of the actual root cause. This paper will provide the analysis details leading to the findings, and highlight the role of electrical understanding in not only providing guidance for physical analysis but also revealing the true root cause of failure in FinFET devices.
Nanoprobing and EBAC for Improving Failure Analysis Success Rates on Sub-14nm Logic and SRAM
Authors: Masnik John , Saujauddin Noor Jehan , Davidson Kevin , Chen Esther P.Y. 
Published: December 2020

Abstract
Nanoprobing, electrical probing (DC electrical measurement of semiconductors using nanoscale probes) on an electron microscopic scale, and EBAC, a high-resolution, static technique, can be used for isolating defects and improving failure analysis success rates on both logic and SRAM devices. This paper presents three case studies of subtle defects on a technology beyond 14nm that required nanoprobing.