Silicon Nanowire Arrays for High Capacitance Electrodes in Room Temperature Ionic Liquid Electrolyte
Authors: Shougee Abdurrahman , Konstantinou Foivia , Albrecht Tim , Fobelets Kristel 
Published: February 2020

Si has not been much considered as electrode material for capacitors due to a low specific capacitance and high reactivity with electrolytes, despite the benefits a μ-Si-based electrolytic capacitor can offer in integrated circuits. Recent investigations however, have shown that nanostructured Si electrodes with and without a protective coating demonstrate good capacitive ability [1]. In our work, we protect the Si nanowires (NWs) with a thin (<2nm) NAOS oxide (nitric acid oxidation) [2] and use a non-aqueous ionic liquid electrolyte, [Bmim][NTf2] in order to extend the operating voltage window of SiNW electrodes.
In addition to the capacitor value, the effective series resistance is also important for efficient electrolytic capacitors. To reduce the electrode’s resistance, spin-on-doping (SOD) is used [2]. In this work, we investigate the influence of three different doping atoms: B, Ga and Al on the characteristics. All 3 are p-type doping in Si. The diffusion constant, D is DAl > DGa > DB. The starting wafer has a B doping of the order of ~5 1017 cm-3.
Silicon Nanowire Arrays (SiNWAs) are fabricated by metal-assisted chemical etching (a solution-based process that produces Ag nanoparticles on the surface, forming the catalyst for local oxidation and etch of the Si), followed by SOD and anneal in an RTA (rapid thermal annealer); a buffered HF dip and NAOS at 120 °C for 10 min in 76% HNO3. Annealing of the SOD has been done in Ar for Ga and Al doping, but O2 for B to avoid the growth of a boron rich layer. The length of the NWs in the arrays is ~ 15 μm. Samples are characterised in a three-electrode setup by cyclic voltammetry (CV) at different scan rates (0.05 – 0.5 V/s) and electrical impedance spectroscopy (EIS). The results of the SOD samples were compared with a non-SOD sample.
For large scan windows (2 – 2.5V) a redox reaction was observed for all samples except the Ga SOD sample. The redox peaks show very similar characteristics and are quasi-irreversibility. The B SOD sample has the smallest voltage window (~ 2V). The Ga doped sample did not show any redox reactions within a 3.5 V scan window. The maximum voltage window of [Bmim][NTf2] is 4V [2]. The maximum capacitance derived from the minimum currents in the CV with a large voltage window are: 0.3 mF·cm-2, 0.9 mF·cm-2, 1.0 mF·cm-2 and 2.3 mF·cm-2 for B, non-SOD, Al and Ga doped samples, respectively. These values are confirmed by the EIS measurements. The Ga doped SiNWA capacitance is found to be the best amongst those reported in literature. It remains to be investigated whether the introduction of Ga leads to an increase in corrosion resistance of the NWs. The resistance value derived from the EIS measurements is: 110 Ω, 60 Ω and 16 Ω for the B, Ga and Al SOD samples, respectively. The difference in resistance is in accordance with the diffusion constants of the doping atoms into Si. These resistance values however are still large and can be further reduced via multiple SOD implementations. Multiple SOD was tested for bulk Si with B which has shown a reduction of the resistance from 54 Ω in the 1st SOD step to 7 Ω in the 3rd step. Applying multiple SOD on the SiNWAs will decrease their resistance further. XPS might give an insight of the presence of any of the SOD related doping atoms on the SiO2 surface that might cause or limit redox reactions. The figures in the attachment show a cross section of a SiNWA, the CV for Ga doped SiNWAs for different scan rates and the extracted capacitance versus frequency plot from EIS measurements for the same electrode.

References

[1] N. Berton, M. Brachet, F. Thissandier, J. Le Bideau, P. Gentile, G. Bidan, T. Brousse, S. Sadki, "Wide-voltage-window silicon nanowire electrodes for micro-supercapacitors via electrochemical surface oxidation in ionic liquid electrolyte." Electrochemistry Communications 41 (2014): 31-34.
[2] A. Shougee, L. Qiao, T. Albrecht, and K. Fobelets, “Improving the double layer capacitance in silicon nanowire arrays with room temperature ionic liquids”, MNE 2015, Den Haag, The Netherlands (2015).

Figure 1