Fabrication of 3-Layer Stacked Pixel for Pixel-Parallel CMOS Image Sensors by Au/SiO2 Hybrid Bonding of SOI Wafers
Authors: Goto Masahide , Nakatani Naoki , Honda Yuki , Watabe Toshihisa , Nanba Masakazu , Iguchi Yoshinori , Saraya Takuya , Kobayashi Masaharu , Higurashi Eiji , Toshiyoshi Hiroshi , Hiramoto Toshiro 
Published: December 2020

CMOS image sensors have improved their performances including pixel counts, frame rate, and dynamic range to meet the rising demands for high-quality video systems such as 8K/4K television [1] and three-dimensional (3D) imaging. In recent days, 3D integration technologies have been utilized in CMOS image sensor fabrication by using mainly through-silicon vias (TSVs) [2-3]. However, TSVs are shared by plural pixels, thereby preventing fully parallel signal processing to limit sensor performance in conventional stacked sensors. This is because the TSV penetrates the pixel area and it is difficult to be integrated within pixel.
To overcome this problem, we have proposed a 3D integration technology without using TSVs but Au/SiO2 hybrid bonding of silicon-on-insulator (SOI) wafers. Stacked layers are electrically connected with Au electrodes integrated in every pixel, which gives pixel-parallel signal processing to image sensor as illustrated in Fig. 1, where Au electrodes are embedded in the SiO2 intermediate layer by the damascene process with chemical mechanical polishing (CMP). The electrode size can be reduced to 1 μm or less in diameter. We previously developed 2-layer stacked pixel-parallel image sensor and showed its wide dynamic range with the ability to capture video images [4-6]. In this paper, we report 3-layer stacked image sensor pixel by extending the 3D integration technology, aiming to shrink the pixel size and to enhance functionality of the pixel-parallel image sensor.
Figure 2 shows the fabrication process for the 3-layer stacked CMOS image sensor. The top layer is assigned for photo-detectors and pulse generation circuits, where number of generated pulses are designed to correspond to input illuminance. The middle and bottom layers are for the lower and upper 8-bit pulse counters, respectively. The 3-layer configuration gives every pixel a 16-bit A/D conversion function. The fabrication process flow is as follows: (1) The intermediate SiO2 layers of the top and middle layer equipped with photo detectors or integrated circuits are patterned and etched to form via holes, and the Au electrodes are embedded by electroplating and CMP. (2) The two layers are directly bonded at room temperature mediated with Si thin layer [7]. (3) The handle layer of the middle layer is removed by grinding and XeF2 vapor phase etching, and the backside Au electrodes are formed in the same process as (1). (4) The bottom layer equipped with integrated circuits is then bonded by the same manner as the first bonding, and finally the handle layer of the top layer is removed. By repeating the bonding, electrode forming, and handle layer removing processes, we could obtain multi-layer devices more than three.
The cross-sectional SEM image for the developed 3-layer stacked 8-inch wafer is shown in Fig. 3, where no void or separation was observed at the bonded interfaces. The electrode size was 5 μm in diameter with alignment accuracy of as good as 1 μm. Figure 4 shows the measured input-output characteristics of the developed 3-layer stacked pixel. We confirmed linear response of 16-bit digital signal output from pulse counters in middle and bottom layers, which indicates the developed sensor pixel has high bit depth and wide dynamic range with excellent linearity.
In summary, a 3-layer stacked pixel for pixel-parallel CMOS image sensor was developed by using hybrid bonding of SOI wafers and embedded Au electrodes. The developed pixel confirmed its pixel-parallel 16-bit A/D conversion operation. Our multi-layer stacked process is promising not only for image sensors with ultimate performances but also various More-than-Moore type devices with multi functions.

References

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Figure 1