Defect-Free SiGe/Si Multistacks for Next-Generation CFET Architectures
Authors: Rengo Gianluca , Casey Daniel , Marozas Brendan , Claessens Niels , Khazaka Rami 
Published: December 2024

The complementary FET (CFET) is the leading architecture choice for upcoming logic applications. Leveraging a stacked pMOS and nMOS design, this architecture is expected to enhance device performance with a reduced footprint [1,2]. The fabrication of the channels in these devices requires the deposition of SiGe/Si multistacks. The difference in etching rate of Si and SiGe is exploited, allowing for the selective removal of the SiGe layers and the resulting formation of free-standing Si channels.
In this contribution, we present fully strained pseudomorphic SiGe/Si epitaxial multistacks for the use as channel regions in CFET devices. All layers were grown in a 300 mm ASM reduced-pressure chemical vapor deposition (RPCVD) reactor on Si(001) substrates.
A targeted multistack structure for 1x1 nanosheet channel is displayed in Fig. 1(a). Two types of SiGe layers are present in the stack, having Ge concentration of 22% and 38%, respectively. Fig. 1(b) shows the X-ray diffraction (XRD) Omega-2Theta scan acquired for the deposited stack at the Si(004) Bragg reflection. The experimental spectrum is accurately simulated using a model closely resembling the nominal structure, thereby confirming that the thicknesses and germanium concentrations of the stack’s constituent layers are well within the targeted specifications. The X-ray reflectivity (XRR) spectrum acquired on the same sample and shown in Fig. 1(c) exhibits a high signal-to-noise ratio even at high incidence angles, suggesting a low surface roughness of the sample. Fig. 1(d) displays the asymmetric reciprocal space map (RSM) acquired around the Si(113) reflection. The stack's diffraction peaks are very narrow and horizontally aligned, indicating the absence of strain-relaxation in the sample. The within-wafer non-uniformity (WWNU) of thickness and Ge concentration was first minimized for single SiGe/Si bilayers. The optimized growth parameters were then successfully applied to the growth of multi-layered structures.

Fig.2 depicts the haze map measured via deep-UV (DUV) laser scattering for the same multistack considering a 3 mm wafer edge-exclusion. The measured intensity ranges between 0.59 and 0.69 ppm, indicating a highly smooth surface morphology.
AFM inspections, as shown in Fig. 3(a), confirm that the stack is fully strained, as evidenced by the absence of cross-hatch pattern in the examined areas with dimension 20x20 μm2. The RMS roughness (Rq) of the sample surface is found to be as low as 0.1 nm, which reduces to 0.07 nm on a 2x2 μm2 inspection area (Fig. 3(b)).
The cross-sectional TEM analysis of a 3x3 nanosheet channel stack, as shown in Fig. 4(a), indicates that the layer thicknesses are highly consistent and in good agreement with the targeted nominal values. The energy-dispersive X-ray spectroscopy (EDS) elemental mapping of the same cross-section also reveals a close match between the measured Ge concentration and the expected value. Furthermore, the high-resolution HAADF-TEM image presented in Fig. 4(b) demonstrates the excellent crystalline quality of the epitaxial stack and indicates the presence of sharp compositional transitions between the layers.
Finally, Fig. 5 displays the Omega-2Theta spectra measured for the first and last 1x1 nano-sheet channel stacks fabricated in a batch processing of 25 wafers. Notably, the two spectra exhibit perfect overlapping, with identical peak positions and intensities, showcasing ideal run-to-run repeatability of the process.
In this work, we have demonstrated the fabrication of complex SiGe/Si multistacks that exhibit excellent agreement with the targeted specifications, are free of relaxation-defects and have extremely low surface haze values. These results highlight the effectiveness of our growth process in overcoming typical challenges associated with the development of advanced CFET devices.
[1] P. Schuddinck et al., 2022 IEEE Symposium on VLSI, pp. 365-366.
[2] E. Park et al., IEEE Transactions on VLSI Systems, 31(2), , 2022, pp.177-187.

Figure 1