(Invited) Layer-Controlled, Wafer-Scale Fabrication of 2D Semiconductor Materials
Authors: Chiappe Daniele , Afanasiev Valeri , Tomczak Yoann , Sutar Surajit , Leonhardt Alessandra , Ludwig Jonathan , Celano U. , Brems Steven , Dabral Ashish , Pourtois Geoffrey , Caymax Matty , Schram Tom , Huyghebaert Cedric , Asselberghs Inge , De Gendt Stefan , Radu Iuliana 
Published: February 2020

The rapid cadence of MOSFET scaling is stimulating the development of new technologies and accelerating the introduction of new semiconducting materials as silicon alternative.
In this context, transition metal dichalcogenides (TMDs) with a unique layered structure have attracted tremendous interest in recent years mainly motivated by the characteristic 2D nature together with distinctive and tunable optoelectronic properties which make them appealing for a wide variety of applications. Their ultra-thin body nature, in particular, is expected to provide superior immunity to short channel effects therefore extending the potential to scale transistors down to the few-nanometer-scale. [1-4] Another key feature of 2D materials is the absence of surface dangling bonds. The latter property has the potential to eliminate lattice mismatch constraints thus paving the way for hybrid integration of TMDs into artificial heterostructures with sharp interfaces and designed band alignment. These ingredients, as recently demonstrated, make TMDs ideal building blocks for the fabrication of tunnel field effect transistors with very steep sub-threshold slope which is mandatory for low voltage device operation. [5] Based on these premises, there are some practical issues that need to tackled in order to enable a TMD-based technology. Given their 2D nature, the electronic properties of TMDs critically depend on the physico-chemical characteristics of the interfaces. Therefore, interface/surface engineering represents a logical route to control the electrical performance of TMD-based devices. Surface quality control is mainly a material growth-related issue. From that standpoint, the development of scalable synthesis techniques is obviously a fundamental step towards the development of a manufacturable technology. However, another important step still needs to be achieved: the ability to precisely control the number of layers and surface uniformity at the nano-to micro-length scale over the entire wafer surface to obtain TMD films with atomically flat, self-passivated surfaces. This challenge is further complicated by the fact that powder vaporization techniques and CVD processes used to grow TMD films do not exhibit a self-limiting character. Because of that, local thickness fluctuations and layer discontinuities are commonly observed in synthetic TMD films.
In this work, we will discuss fundamental aspects of film formation and provide a pathway towards layer-controlled, wafer-scale synthesis of TMD films. The high temperatures involved in the synthesis process as well as the use of growth templates require the development of a reliable wafer-scale transfer technology. Such a heterogeneous integration, on the one hand, is useful to overcome the incompatibility of the growth process with processing requirements for the BEOL interconnect structures. On the other hand, it reduces the level of control over the interface between the 2D layer and the dielectric substrate. It is not surprising that electronic transport in transferred TMD films is strongly affected by hydrocarbon residues, non-homogeneities (e.g. uncontrolled strain and contaminated regions), dipole formation, and charge transfer effects. Monitoring environmental effects in ultra-thin TMD films and minimizing the impact of layer transfer on the electrostatic potential distribution across the interface is of utmost importance. A wafer-scale transfer process and related experimental challenges and opportunities will be also presented.

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