(Invited) Light Emission from Highly-Strained Germanium for On-Chip Optical Interconnects
Authors: Nam D. , Sukhdeo D. S. , Dutt B. R. , Saraswat K. C. 
Published: February 2020

The relentless device scaling paradigm is being threatened by the limits of Cu-based interconnects including excessive power dissipation, insufficient communication bandwidth, and signal latency. Many of these limitations are caused by the increase in Cu resistivity as wire dimensions are scaled down [1]. To alleviate this performance bottleneck in integrated circuits (ICs), optical interconnects, which have already revolutionized long-haul communications, have recently gained much attention for on-chip applications.
Ge has emerged as a viable candidate to augment Si for CMOS and optoelectronics. First, the lower effective mass and lower valley degeneracy of Ge could alleviate the problem by providing a higher source injection velocity, rendering higher drive current and smaller gate delay in MOSFETs [2]. Second, Ge has a larger absorption coefficient than Si in the telecommunications wavelength range (1.3-1.55 µm), which makes it attractive for integration of monolithic optical components for the use in optical interconnects. Third, lower processing temperatures allow 3-D integration of Ge on Si.
Over the past decade many of the key Ge-based constituents of an on-chip optical interconnect system, such as high-performance photodetectors and modulators, have been demonstrated on a silicon-compatible platform. We have demonstrated p-i-n [3] and metal–semiconductor–metal (MSM) photodetectors [4] in Ge grown on Si with excellent quantum efficiency and responsivities at a wavelength of 1.55 µm. Dark current, a concern for Ge photodetectors due to its small bandgap, has been mitigated by using electrodes with asymmetric work functions in MSM detectors [4]. Researchers have also observed quantum-confined Stark effect electro-absorption in Ge quantum wells with SiGe barriers grown on Si substrates, and a Ge modulator based on this effect has been demonstrated on a Si substrate [5]. This effect is very promising for high-speed, low-power modulators fabricated compatibly with mainstream Si ICs [5].
An efficient light source, on the other hand, remains particularly challenging: Si and Si-compatible materials such as Ge are not readily suitable for light emission because their band gaps are indirect. In Ge, however, the energy difference between the direct Γ valley and the indirect L valley is only 136 meV and this difference can be reduced further by introducing tensile strain [6]. It has been proposed to use tensile strain to make Ge’s band gap direct and thus suitable for light emission [7,8], however highly-strained Ge experimental device realization has thus far been limited to LEDs [9] rather than lasers.
In this presentation, we focus on developing an efficient Si-compatible light emitter based on highly-strained Ge technology. Starting from theoretical calculations showing how tensile strain can improve the light emission efficiency of Ge [7,8], we present several approaches for enhancing light emission from highly strained Ge on a CMOS-compatible platform. We have developed methods to grow single crystal Ge films with low defect densities on Si [10]. First, we describe a thin film membrane technique in which a large residual stress in a tungsten layer as a stressor is used to induce a biaxial tensile strain in a Ge membrane, upon which we have fabricated optoelectronic devices [11]. Second, we introduce an approach to induce sufficiently large uniaxial strain to create a direct band gap in Ge wire using geometrical amplification of a small pre-existing strain induced during the heteroepitaxial growth of Ge on Si [12]. Lastly, we present a novel way to mimic double-heterostructure behavior within a single material, further enhancing light emission from Ge by capturing photo-generated carriers within a strain-induced potential well [13]. In summary we have demonstrated integration of Ge on Si for optoelectronic applications. This should alleviate a critical performance bottleneck in the continued scaling of integrated circuits to future technology nodes.

References

1. K. H. Koo et al., IEEE Trans. Electron Dev., 54, 3206 (2007).
2. K. Saraswat et al.,
Mat. Sci. and Eng.: B, 135(3), 242 (2006).
3.H.-Y. Yu et al., IEEE Electron Dev.
Lett.,
30, 1161 (2009).
4. A. K. Okyay et al., Optics Lett.,
31, 2565 (2006).
5. Y.-H. Kuo et al., IEEE JSTQE., 12, 1503 (2006).
6. M. V. Fischetti et al., J. Appl. Phys.
80(4), 2234 (1996).
7. B. Dutt et al., IEEE Photon. J.,
4(5), 2002 (2012).
8. D. Sukhdeo et al., CLEO, JTh2A.109 (2013).
9. D. Nam et al., Appl. Phys. Lett., 100(13), 131112 (2012).
10. A. Nayfeh et al., Appl.
Phys. Lett.,
85(14), 2815 (2004).
11. D. Nam et al., Opt. Express
19 (27), 25866 (2011).
12. D.S. Sukhdeo et al., Photon. Research J. (in press).
13. D. Nam et al., Nano Lett.,
13, 3118-3123 (2013).