bluuebunny/crossref_metadata_2025_split huggingface dataset:
(Invited) Key Challenges in Area Selective Deposition: From R&D Scale to High Volume Manufacturing
Authors: Saly Mark , Bhuyan Bhaskar 
Published: December 2024

The semiconductor industry has enjoyed unprecedented growth over the last two decades fueled by the PC/internet era (2000s) and the Mobile/Social Media era (2010s). We are now entering the Artificial Intelligence/Big Data era which is predicted to push the industry towards $1T in revenue by the early 2030s1. AI applications require massive amounts of computational power and power consumption. To keep pace with expected computational demands and ensure that the industry does not put strain on the global power supply, device makers are looking at ways to increase compute while driving lower operational power consumption. The image below showcases TSMC’s device architecture roadmap on new transistor architectures and gives insight into a path on new integrated materials2. After gate-all-around nanosheets (entering trial production today), TSMC will enter the 3D regime with transistor stacking called CFETs (complementary field-effect transistors). 3D integration of devices is a common strategy across the industry from logic to memory to continue scaling trends. Stacking the devices is shown to increase performance, decrease area cost, and decrease power consumption. Realization of these complex architectures requires very stringent and rigorous fabrication steps with various patterning techniques and new processes. Selective deposition has been identified as one primary method to simplify integration schemes to lower complexity and cost. For example, selective deposition can mitigate issues encountered in fine pitch lithography such as edge placement error that can lead to reliability and performance issues like BEOL contact shorts. Applied Materials is the current leader in selective deposition processing, and we have fielded multiple products that are being used to fabricate cutting-edge devices at leading edge customers. This discussion will focus on the trials and tribulations of ASD, and how it is enabling our customers to reduce power consumption while increasing performance all at a lower area cost, which will be crucial to the future sustainability of this industry.
1. https://www.semi.org/en/blogs/semi-news/global-semiconductor-industry-driving-%241-trillion-and-beyond-together
2. TSMC 2023 North America Technology Symposium (April 26th, 2023)

Figure 1
Ultra-Low Loaded Platinum Via Plasma-Enhanced Atomic Layer Deposition for the Fuel Electrode Active Layer in Steam Reversible Solid Oxide Cells
Authors: Kim Hyong June , Li Haoyu , Kim Deahyun , Park Geonwoo , Jo Sung Eun , Ju Kyoungjae , Park Haesun , Lee Min Hwan , An Jihwan 
Published: December 2024

Reversible solid oxide cells (rSOCs) are crucial energy devices in sustainable energy systems, offering efficient energy conversion and storage solutions through hydrogen. Conventional SOFC/SOEC operating temperatures are above 700°C; at these temperatures, the cells benefit from high energy conversion efficiencies due to facilitated electrochemical reactions and effective waste heat utilization. Despite their advantages, commercial rSOCs face hurdles including suboptimal performance in the intermediate temperature range of 500-700°C, limited lifespan, and elevated operational costs. Addressing these issues, significant progress has been made in electrode fabrication, particularly through advanced semiconductor fabrication methods such as atomic layer deposition (ALD).
In this study, we explore the application of plasma-enhanced ALD (PEALD) for depositing exceptionally low loadings of platinum on Ni-yttria stabilized zirconia (Ni-YSZ) fuel electrodes, aiming to enhance both performance and stability. Employing this novel approach, we achieved precise control over the Pt nanoparticle deposition process, resulting in a catalyst loading of only 0.2 µg/cm2.
Experimental results demonstrated that rSOC samples with 10 cycles of PEALD Pt exhibited a 20% increase in maximum power density (548 vs. 479 mW/cm2 at 700°C) and an 18% increase in current density (1260 vs. 1070 mA/cm2 at 1.5 V) compared to the bare samples. Notably, these improvements were achieved without any observable performance degradation over 50 hours of operation at 700°C with 50% humidified hydrogen. Density functional theory (DFT) simulations were employed to elucidate the mechanisms contributing to the enhanced activity, revealing that the nano-scale Pt deposition promotes efficient hydrogen oxidation and evolution reactions.
These findings highlight the potential of PEALD for rSOC manufacturing, enabling the creation of highly active and stable electrodes with minimal precious metal loading. The outcomes of this study suggest that such advancements could lead to more economically viable and sustainable hydrogen energy solutions, aligning with broader goals of energy security and environmental sustainability. This work provides a compelling case for the wider application of nano-engineered catalysts in high-performance electrochemical systems at intermediate temperature ranges.
ALD-Imparted Stability on High-Voltage Cathode Materials for Increased Cycle Life and Energy Density in Lithium-Ion Batteries
Authors: Pach Gregory F. , Martinez Madison , DuMont Jaime W , Herbert-Walters Meghan , Dameron Arrelaine A , Hughes Barbara K 
Published: December 2024

High-voltage cathode materials such as lithium cobalt oxide (LCO) and nickel manganese cobalt oxide (NMC) are critical for obtaining high energy densities in lithium-ion batteries (LIBs). Although both materials have been implemented in commercially available consumer electronics, the demand for exceedingly higher cell energy densities requires cathodic stability at increased cell potentials. Cycling LIBs to high potentials (≥ 4.4 V) can accelerate degradation modes at the cathode such electrolyte consumption, material phase transitions, transition metal ion dissolution, and oxygen loss. Material engineering strategies such as transition metal doping/alloying or surface coating are often employed to mitigate these failure pathways, however, many of the methods used to realize these solutions are not feasible at industrial scales while also being time, energy, and cost prohibitive.
In this work, we demonstrate how atomic layer deposition (ALD) can be used to stabilize both LCO and single-crystalline NMC materials at high cell potentials in LIBs. Using Forge Nano’s ALD technology, we show how we can deposit thin, homogenous coatings on these cathode materials at industrially relevant scales. Electrochemical testing and differential capacity analysis of cathode half cells at progressively wider voltage windows illustrate that ALD protects and stabilizes the cathode against detrimental side reactions that cause capacity fade and increased internal resistance. Post-cycling SEM-EDX characterization from full cells shows that Co dissolution can be significantly reduced when an ALD coating is deposited on the cathode and that this effect becomes more pronounced at elevated cut off voltages. EIS analysis results demonstrate that ALD protects LCO surfaces from detrimental phase transitions above a 4.5 V upper cut off voltage, suppressing the formation of a spinel layer and shielding the surface from harmful reactions with the electrolyte. Together, these enhancements lead to cycling performances that rival the best performing commercial material investigated in this work, showing that ALD can be a viable and affordable technology for cathode materials enhancement.
Low-Temperature Selective Si:As Epitaxy
Authors: Abdula Daner , Chiu YuJen , Marozas Brendan , Khazaka Rami , Miskin Caleb K , Lee Jung Soo , Demos Alexandros T 
Published: December 2024

A selective low-temperature Si:As (LT-SiAs) process is presented which utilizes cyclic deposition-etch (CDE) at <450oC. Selectivity against SiN and SiOx dielectrics and crystallinity are confirmed on gate-all-around (GAA) patterned structures. Hall measurements on blanket wafers show a resistivity minimum of 0.42 mΩ-cm at ~1.7% As for selective LT-SiAs. SIMS profiles of P and As diffusion into intrinsic Si (i-Si) for LT-SiP/LT-SiAs/i-Si and LT-SiP/i-Si stacks show >2× benefit of using LT-SiAs spacers to minimize dopant diffusion for as-deposited, soak-annealed and spike-annealed samples. Improvement is attributed to relatively limited diffusivity of As in Si versus P and the lower As concentration needed for LT-SiAs layer to achieve minimum resistivity relative to LT-SiP (~3%). Lastly, a comparison of LT-SiAs and high-temperature Si:As (HT-SiAs) shows a ~2× reduction of As diffusion into i-Si for LT-SiAs at length scales of >10nm.
[1]: E. Rosseel et al. ECS Trans.
98, 37 (2020).

Figure 1
(Invited) Interface Control Process of Rare-Earth Oxides on Si for Gate Dielectric Application
Authors: Kakushima Kuniyuki 
Published: December 2024

High-k gate dielectrics are indispensable to overcome the shot-channel effect in scaled CMOS devices [1]. Besides the enhanced electrostatic control of the gate electrode, high-k/Si interface properties, including interface state density, fixed charges, dipoles, carrier mobility, reliability, and so on, need to meet the requirement levels. Rare earth oxides have been intensively studied for gate dielectric applications as these oxides react with Si to form a silicate layer, whereas, for the HfO2 case, a SiO2-based low-k interface layer is formed. One of the issues for rare earth oxide gate dielectrics is controlling the reaction amount while obtaining a good interface property. In this presentation, the interface reaction of rare-earth oxides and Si is modeled and controlled by the thermal treatment process. Furthermore, the influence of the metal gate electrode on the interface is assessed.
A la-silicate interface layer is formed between the La2O3 film and Si interface. Although the La atom content in the reactively formed silicate layer generally depends on the annealing environment, a silicate/Si interface can be easily formed, which is advantageous for gate dielectric scaling. However, even under the same process, the La atom content in the silicate increases with the thinning of the initial La2O3 thickness, and the interface state density, flat-band voltage, and mobility degrade [2]. The reaction between La2O3 and Si can be modeled by oxygen atom supply from the environment, and the influence of the metal gate can explain the degradation of electrical properties. A La-rich silicate can be formed with nice interface properties by controlling the supplied oxygen atoms by selecting a proper metal gate stack [3]. The crystal grain size in the metal gate also affects the interface state density. A low interface state density can be obtained by adopting a metal gate material with nano-sized grains [4].
In conclusion, an interface control process of La2O3 film on Si is presented by limiting the oxygen atom supply during the interface reaction. La-rich silicate, a high-k film, can be obtained by adopting a proper stacked gate structure. Also, nano-sized grains in the metal electrodes can exhibit a decent interface property.
[1] J. Robertson, et al., Materials Science and Engineering R, 88, 1 (2015).
[2] K. Kakushima, et al., Solid-State Electron., 54, 715 (2010).
[3] T. Kawanago, et al., IEEE Trans. on ED, 59, 269 (2011).
[4] K. Tuokedaerhan, et al., Appl. Phys. Lett., 104, 021601 (2014).
(Invited) How Reliable Is Our Ranking of Coulombic Efficiency for Li Metal Anodes?
Authors: Gallant Betar M. 
Published: December 2024

The performance of Li metal anodes is benchmarked by Coulombic efficiency.1 However, despite the singular importance of this parameter in interpreting and understanding advances in electrolyte design, there is no agreed-upon standard protocol for measuring and reporting CE. The lack of such standardization imperils attempts to rank electrolyte performance and even to understand what performance metrics have truly been achieved.
In this talk, I will share our recent efforts dedicated to understanding how cell assembly parameters affect the resulting CE that is measured in coin cells. Specifically, we examine how selection of cell parts, crimping pressure, cell assembly order, and other parameters lead to different conclusions about CE as a function of electrolyte and why. By further examining a rank order analysis of electrolyte performance subject to such common experimental variations, such as those that might be occurring between different laboratories or even different researchers within the same lab, we demonstrate the ease of drawing erroneous conclusions regarding which electrolytes are field-leading. I will discuss the implications for data-driven research approaches like machine learning, while rely crucially on having accurate metrics and ranking of performance, and make recommendations to improve standardization to bolster data quality.

M. Hobold, J. Lopez, R. Guo, et al., Nature Energy 2021, 6, 951-960.
Super Wide Area Exploration of High Conductive Oxide Solid Electrolytes Using Data-Driven Feature Value Map
Authors: Kita Yuki , Yamada Tetsuya , Shishino Kazuyuki , Hayashi Fumitaka , Teshima Katsuya 
Published: December 2024

Currently, over 100,000 data on inorganic compounds was reported in the Inorganic Crystal Structure Database (ICSD). Until now, exploration of functional materials has been experimentally carried out using intuition and experience from such huge amount of materials. This approach needs several trials and errors, resulting in consuming times. Moreover, experimental space is small and only local optimization is possible. Thus, drastic improvement of material performance is difficult. To overcome this issue, we propose super wide area exploration of chemical composition using huge experimental space. In detail, we introduce data-driven exploration map that consists of intrinsic material properties, such as crystal structure, composition, and their physicochemical properties. We call the map as "feature value map", afterwards. Since functional performances are strongly dependent of material's properties, this approach should potentially lead to novel discoveries beyond the subjective perception of the researcher.
In this study, we attempted to expand this feature value map to lithium-ion conductive oxide solid electrolytes. Conventional Lithium-Ion Batteries use flammable organic compounds as electrolytes, which can burn in the worst case if the temperature of the battery rises due to a large load on the battery in some way. All-solid-state batteries use a solid electrolyte, which reduces the risk of ignition. Especially oxide solid electrolytes are known as safe and chemically stable. Although safer, oxide solid electrolytes have lower ionic conductivity and plasticity, resulting in lower battery performance. So far, several exploration approach, including elemental doping, has been carried out. But, still difficulty to satisfy 10-1 S/cm at room temperature, which is a target value for actual use. In this presentation, development of ionic conductivity correlated feature value map and super wide space exploration of materials using this map will be reported.
Acknowledgement
This work was partly supported by Priority Project in Aichi Knowledge Hub Aichi, JST Green Technologies of Excellence, the Strategic Innovation Program (SIP) of the Cabinet Office, and joint research with a company.
Estimating State of Charge and State of Health of Lithium-Ion Batteries in Japanese Satellite Reimei
Authors: Bolay Linda , Shironita Sayoko , Umeda Minoru , Hosono Eiji , Asakura Daisuke , Sone Yoshitsugu , Latz Arnulf , Horstmann Birger 
Published: December 2024

In-orbit satellite REIMEI, developed by the Japan Aerospace Exploration Agency (JAXA), has been relying on off-the-shelf Li-ion batteries since its launch in 2005 [1]. The data from the batteries have been recorded and analyzed ever since. These comprise current and voltage measurements of several thousand cycles [2,3].
The performance and durability of Li-ion batteries is impacted by various degradation mechanisms, one of which is the growth of the solid-electrolyte interphase (SEI). Long-term SEI growth is the greatest contributor to capacity fade in lithium-ion batteries. Physics-based models for long-term SEI growth have been developed [4,5]. To show the inhomogeneous growth of the SEI in 3D, we performed microstructure-resolved simulations [6].
In this contribution, we will address several aspects of the analysis and simulation of the batteries of satellite REIMEI. We simulate long-term degradation under the generic LEO satellite cycling conditions in a P2D framework. The simulations are validated with terrestrial experiments and in-flight data provided by JAXA [1,6].
These studies are the foundation for analyzing the states of the batteries, which cannot be measured directly. To estimate the state of charge and state of health, we make use of filter techniques and the in-flight data of the satellite batteries. Kalman filters are particularly suitable for the noisy data. Since the states change on different timescales, a multi-time-scale algorithm is developed, where two filters are combined to estimate the states simultaneously. With this approach, we aim to reliably predict the lifetime of satellite batteries in orbit [3].

References

[1] M. Uno, et al., J. Power Sources, 196(20) (2011) 8755–8763.
[2] O. Mendoza-Hernandez, et al., Electrochemistry
88
(
4
) (2020) 300-304.
[3] L. Bolay, PhD thesis Ulm University, (2024), https://doi.org/10.18725/OPARU-52298
[4] F. Single, et al., ChemSusChem, 11(12) (2018) 1950–1955.
[5] L. von Kolzenberg, et al., ChemSusChem, 13(15) (2020) 3901–3910.
[6] L. Bolay, et al., J. Power Sources Advances, 14 (2022) 100083.
Early Prediction of the Failure Probabilitydistribution for Energy Storage Technologiesdriven By Domain-Knowledge-Informed Machinelearning
Authors: Alghalayini Maher , Noack Marcus , Harris Stephen J 
Published: December 2024

There is a growing focus on sustainable energy sources and storage systems. The
challenge with such emerging systems is their need to be warrantied for around
15 years with just a year of early testing. This requires accurate data extrapolation
and estimation of the failure distribution. Physics-based approaches can be
overwhelmed by the complexity of degradation, and pure data-driven approaches
are inherently unable to extrapolate beyond the testing data. Here, we propose
a framework for a hybrid approach for technology-agnostic customizations of a
Gaussian process for stochastic and domain-knowledge-informed failure distribution
predictions. We equip the Gaussian process with customized non-stationary
kernels, heteroscedastic noise models, and prior-mean functions to allow for accurate
extrapolation with high accuracy. Furthermore, we minimize testing time
with a novel experiment-stopping criterion, which can significantly reduce the
required data. Our framework could revolutionize energy-storage testing, enabling
the rapid development of new technologies.
(Invited) Amorphous Indium-Gallium-Tin Oxide Thin-Film Transistor with High Mobility of 40 cm2 V−1 s−1 and Excellent Stability
Authors: Lim Taebin , Sun Jiwon , Lee Solbee , Jang Jin 
Published: December 2024

Metal oxide semiconductor (MOS) has been studied extensively for use in the backplane of the display due to its extremely low leakage current, low temperature and large area process. Among them, InGaZnO (IGZO) thin-film transistor (TFT) is the most popular due to its relatively high mobility and good stability. MOS TFT has a challenge to replace Low-Temperature Poly-Si (LTPS) TFT which is high cost TFT process. However, the electron mobility of IGZO is typically ~10 cm2 V−1 s−1, which is very low compared to LTPS, making it unsuitable for use in high resolution backplane of active-matrix organic light-emitting diode (AM-OLED) display. There are limitations to increasing the mobility of a-IGZO. Therefore, research on high mobility MOS such as In2O3 and InGaO (IGO) to replace LTPS is attracting attention recently. Note that Ga effectively suppresses carrier concentration and lowers the Fermi level (EF), resulting in stable on/off characteristics with excellent stability. The tin cation (Sn4+) increases the carrier concentration by having an electron orbital similar to In (In3+) and increase the overlap of the 5s orbitals. Therefore, a-InGaSnO (IGTO) TFT can have high mobility and thus a good candidate for low-cost AM-OLED TFT backplane. In our previous study, we developed back channel etched (BCE) structured dual-gate a-IGTO TFT exhibiting high mobility (39.1 cm2 V−1 s−1). When compared with a-IGZO TFT, a-IGTO TFT exhibits high mobility, excellent stability, and steep subthreshold swing (SS). We confirmed low density of state in band gap of a-IGTO. But BCE structure has an unintended parasitic capacitor between gate and source/drain electrode that can deteriorate operating characteristics. This can be improved by introducing coplanar structure TFT. It is important to secure thermal stability characteristics at high temperatures. Tin has a higher bond dissociation energy with oxygen (548 kJ/mol) than indium (360 kJ/mol). Therefore, the thermal stability can be improved in a-IGTO TFT.
In this work, we present the high-performance, coplanar structured a-IGTO TFTs fabricated on the glass substrate. The a-IGTO TFT exhibits the field-effect mobility (µFE) of 40.0 cm2 V−1 s−1, SS of 0.16 V dec−1, and on/off current ratio of > 107 at low drain voltage (VDS) of 0.1 V. Even with the short channel length of 2 μm, it shows a threshold voltage (VTH) close to 0 V (−0.3 V) and hysteresis-free characteristics. We confirmed good ohmic contact between Mo electrode with a-IGTO. At gate voltage (VGS) of +20 V, the channel resistance and contact resistance of the a-IGTO TFT are found to be 27.47 kΩ/μm and 16.77 kΩ, respectively. Additionally, we confirmed excellent thermal stability of the a-IGTO TFT, demonstrating unaffected electrical characteristics even after air annealing. The coplanar structured a-IGTO TFT can be a promising candidate for low-cost AMOLED backplane.

Figure 1
(Invited) Advancements in High-Performance Metal-Oxide TFTs Via Atomic-Layer Deposition: A Path Towards Next-Gen Display and Memory Technology
Authors: Yoon Seong Hun , Hur Jae Seok , Jeong Jae Kyeong 
Published: December 2024

This paper delves into the recent advancements in crafting high-performance metal-oxide thin-film transistors (TFTs) via the atomic-layer deposition (ALD) process. As metal-oxide TFTs emerge as pivotal backplane technology for cutting-edge display products like organic light-emitting diode (OLED) televisions and selectors for 3D-DRAM, relentless efforts are underway to push the boundaries of performance through diverse methodologies. Among these, two prominent avenues, namely, adjusting cation composition ratios and innovating novel structural designs, are spotlighted. Both pathways leverage the myriad advantages offered by the ALD process over conventional sputtering methods. The paper elucidates the state-of-the-art characteristics of ALD-deposited oxide semiconductors, revealing promising prospects for ALD-derived metal oxide TFTs to emerge as prime contenders for the next generation of high-end active-matrix displays and 3D DRAM devices.
This work was supported by Institute of Information & communications Technology Planning & Evaluation (IITP) under the artificial intelligence semiconductor support program to nurture the best talents (IITP-2024-RS-2023-00253914) grant funded by the Korea government.