bluuebunny/crossref_metadata_2025_split huggingface dataset:
Diamond Probe Applications for Nanoprobing
Authors: Pendyala Sweta , Dalton Andrew , Zumwalt Sean , Miller John 
Published: December 2020

Abstract
As technology continues to scale down, semiconductor devices and circuitry have become more complex. The layouts are more integrated and the devices do not isolate at contact level like they used to. Due to this, nanoprobing cannot always localize the defect to one gate finger and as a result the follow-on physical analysis gets more complicated and time consuming. In this paper, we will explore an approach to simplify a given circuit and localize the failing finger in that circuit by cutting metal lines using diamond nano-probes [1] on the FEI Hyperion Atomic Force Probe (AFP) Platform. We will also describe some of the other applications of diamond nano-probes in facilitating semiconductor failure analysis.
Failure Analysis Case Study of Inductively Coupled Cross-Chip Signals
Authors: Loveless Steven , You Zhihong , Chatterjee Tathagata , Subbannavar Badarish 
Published: December 2020

Abstract
This paper discusses a failure analysis case study in a highly integrated mixed signal device caused by inductive coupling of on-chip signals. The techniques utilized and the approach to root cause analysis are discussed in depth. The interactions between the device design and failure mechanism are identified in detail. Focus is placed on drawing conclusions from the sum of individual data points, and the discussion provides an analytical path by which similar failures can be isolated and specific device sensitivities can be identified.
The Use of a Fresnel Lens on an Actual Failure
Authors: van Veenhuizen Marc , Kerver Harry , Peters-Wu Lei , Lee Sukho , Zachariasse Frank 
Published: December 2020

Abstract
We report on the use of Fresnel lenses in the failure analysis (FA) of actual failures. The design parameters affecting the performance of Fresnel lenses in terms of resolution, magnification, and field of view have been analyzed. It is demonstrated that the magnification depends linearly on the change in focus distance caused by the lens, normalized by the silicon thickness. The focus distance shift that can be obtained with the Fresnel lens is observed to saturate, whose root-cause remains to be investigated. The field of view is shown to increase with the silicon thickness and, to a lesser extent, with the number of lens rings. It has also been shown that these lenses are robust against patterning distortions. The OBIRCh responses of actual device failures before and after lens placement have been compared, demonstrating clearly the increase in magnification, resolution, and the ability to focus light which all translate into a better electrical fault isolation. All in all, this study proves the usefulness of Fresnel lenses for FA purposes and offers clear guidelines that will facilitate proper lens design.
Wire-Wound Resistor Investigation—A Case Study
Authors: Wheeler Jason , Wolfgong John 
Published: December 2020

Abstract
The focus of this paper is to present an interesting case study involving Vishay wire-wound (WSC model) resistor failures, which affected a significant number of production and fielded assemblies. The failures were considered “mission critical”, which was the primary driver necessitating root cause analysis. A disciplined approach to the failure analysis effort was established, which resulted in root cause determination and the generation of appropriate corrective actions. This paper will highlight a non-conventional decapsulation method used to preserve the integrity of the fragile resistive element and a “lucky break” that was instrumental in linking the supplier’s actions to the failures.
Two-Dimensional Local Deep-Level Transient Spectroscopy Imaging Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy
Authors: Chinone N. , Cho Y. , Kosugi R. , Tanaka Y. , Harada S. , Okumura H. 
Published: December 2020

Abstract
A new technique for local deep level transient spectroscopy (DLTS) imaging using super-higher-order scanning nonlinear dielectric microscopy is proposed. Using this technique. SiCVSiC structure samples with different post oxidation annealing conditions were measured. We observed that the local DLTS signal decreases with post oxidation annealing (POA), which agrees with the well-known phenomena that POA reduces trap density. Furthermore, obtained local DLTS images had dark and bright areas, which is considered to show the trap distribution at/near SiCVSiC interface.
Investigation of Phase Change Memory Confined Cell Endurance Using Transmission Electron Microscopy
Authors: Zhu Yu , Kim S. , Gonsalves J. , Brightsky M. , Sosa N. , Lam C. , Chen J. , Shen J. , Gong N. , Cha J. , Ma T.P. 
Published: December 2020

Abstract
The endurance performance of a novel confined phase change memory cell with metallic nitride liner is investigated using a transmission electron microscope (TEM). Write endurance has been shown to be substantially improved by this new structure [1]. Memory cells that had been cycled up to 109 were cross-sectioned and studied using the TEM. A majority of the electrically observed endurance failure mechanisms were stuck-SET. Physical failure analysis showed the failed cell is always associated with large void formation and material segregation. In-situ TEM analysis was used to study the void formation, accumulation and movement, where the memory cell was simultaneously operated and imaged in the TEM. Also, an interesting self-healing process of the void was recorded during the set/reset operation.
Elemental Characterization of Sub 20 nm Structures in Devices Using Low Energy SEM-EDS
Authors: Sagar James T. , Holland James , Burgess Simon R. , McCarthy Connor , Xiaobing Li 
Published: December 2020

Abstract
Here we investigate a new energy dispersive X-ray detector, which for the first time is optimized to work at the conditions typically used for high resolution imaging in a scanning electron microscope (SEM). To achieve this, significant developments have been made with regard to detector geometry and electronics. Using this new detector we are able to analyze structures in bulk semiconductor devices as well as thin sections at sub 20nm length scales in SEM. Here we outline the conditions required to carry out this analysis. Based on these results we propose workflows to accelerate failure analysis by obtaining the analysis result directly in the SEM without the need for analysis using transmission electron microscopy (TEM).
TEM Sample Prep Tool Matching—DualBeam FIB Cut Look and Measure Monitoring for Process Control and Development in a 300 mm IC Fab
Authors: Jeon Jangbae 
Published: December 2020

Abstract
This work presents a novel method of continuous improvement for faster, better and cheaper TEM sample preparation using Cut Look and Measure (CLM). The improvement of the process is executed by operational monitoring of daily beam conditions, end products, bulk thickness control, recipe usage and tool running time. This process produces a consequent decrease in rework rate and process time. In addition, it also increases throughput with better quality TEM samples.
Scanning Surface Photovoltage Microscopy for Stress Analysis in Nanoscale CMOS Devices
Authors: Dahanayaka Daminda , Kaszuba Phil , Moszkowicz Leon , Wells Randall , Slinkman James , Bumm Lloyd A. 
Published: December 2020

Abstract
Mechanical stress is a critical parameter in the design and manufacture of devices in very large scale integrated (VLSI) circuits. Whether intentionally introduced or parasitic, mechanical stress in nanoscale silicon technologies can alter carrier mobility as by as much as 25%, which can significantly affect device performance. Currently stress metrology for in-line production is conducted only at a wafer monitor level. For design purposes, the stress state in active device regions is usually inferred from electrical data. In this paper an instrument which we have developed is described for measuring mechanical stress in nanoscale silicon devices with high spatial resolution using scanning surface photovoltage microscopy (SSPVM). Other existing techniques are generally not suitable for making such measurements on production silicon nano-device structures in situ.
Fast Root Cause Identification Using Combination of Failure Analysis and In-Line Inspection
Authors: Song Zhigang , Weng Weihao , Engel Brett 
Published: December 2020

Abstract
Failure analysis plays an important role in yield improvement during semiconductor process development and device manufacturing. It includes two main steps. The first step is to find the defect and the second step is to identify the root cause. In the past, failure analysis mainly focused on the first step, namely how to find the defect for a failure; because in the previous generations of technology, once the defect was found, its root cause was relatively easy to be understood. As the current advanced semiconductor technology has become tremendously complicated, especially 3D devices, like FinFET, a defect found by failure analysis can be substantially transformed from its original defect by subsequent processes and can be totally different from its origin in size and shape. Thus, sometimes, the second step, identifying the root cause for a defect becomes more challenging and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more quickly, leading to fast root cause identification. In this paper, the methodology was validated by fast identification of the root causes for three case studies in the latest FinFET technology.
Failure Analysis and Process Verification of High-Density Copper ICs Used in Multichip Modules
Authors: Walraven Jeremy A. , Jenkins Mark W. , Simmons Tuyet N. , Levy James E. , Jensen Sara E. , Jones Adam , Edwards Eric E. , Bartz James A. , Cole Edward I. , Soirez Lovelace , Norbert John 
Published: December 2020

Abstract
Manufacturing of integrated circuits (ICs) using a split foundry process expands design space in IC fabrication by employing unique capabilities of multiple foundries and provides added security for IC designers [1]. Defect localization and root cause analysis is critical to failure identification and implementation of corrective actions. In addition to split-foundry fabrication, the device addressed in this publication is comprised of 8 metal layers, aluminum test pads, and tungsten thru-silicon vias (TSVs) making the circuit area &gt; 68% metal. This manuscript addresses the failure analysis efforts involved in root cause analysis, failure analysis findings, and the corrective actions implemented to eliminate these failure mechanisms from occurring in future product.
Characterization of Dynamic Laser Stimulation Approach to Locate Memory Fails Using EeLADA
Authors: Goh S.H. , Yeoh B.L. , Ngow Y.T. , Hao Hu , Tan Alan , Chan Y.H. , Zhao Lin , Lam Jeffrey , Tay C.C. 
Published: December 2020

Abstract
Most modern system on-chip incorporates a significant amount of embedded memories to achieve a reduced power consumption, higher speed and lower cost. In general, such memories are evaluated using built-in self-testing methods and in the event of a failure, bitmapping is heavily relied on for fault localization to guide subsequent failure analysis. However, a fast yield ramp can be impeded when bitmapping is not enabled in time or is inaccurate. This work studies the feasibility of employing electrically-enhanced LADA as an alternative method to debug embedded memory failures. Results are presented to demonstrate that the resolution of localization depends on the precision of diagnostic test pattern used and the laser spot size.
High Throughput Phase Mapping for Metrology Using Low-Loss EELS
Authors: Fu Lianfeng , Chen Lifan , Wang Haifeng 
Published: December 2020

Abstract
The plasmon-loss region of the low-loss electron energy loss spectroscopy (EELS) contains chemical information similar to core-loss EELS; therefore it can be utilized as finger-printing elements. A high throughput phase mapping technique based on plasmon energy (Ep) is proposed. We have successfully applied this phase mapping technique into two case studies in our magnetic head manufacturer processes. This Ep phase mapping can be applied to not only the data storage but also semiconductor industries.
Trends in Discrete Power MOSFET and Power System In-Package Fault Isolation
Authors: Kearney Ian , Dipsey Mark 
Published: December 2020

Abstract
Photoluminescence, defect-band emission, and Lock-in Infrared Thermography (LIT) generally enable the correlation of multi-crystalline silicon defect types. Long Wavelength Infrared (LWIR) thermal imaging has traditionally seen limited application in failure analysis. LWIR cameras are typically uncooled systems using a microbolometer Focal Plane Arrays (FPA) commonly used in industrial IR applications, although cooled LWIR cameras using Mercury Cadmium Tellurium (MCT) detectors exists as well. On the contrary, the majority of the MWIR cameras require cooling, using either liquid nitrogen or a Stirling cycle cooler. Cooling to approximately −196 °C (77 K), offers excellent thermal resolution, but it may restrict the span of applications to controlled environments. Recent developments in LWIR uncooled and unstabilized micro-bolometer technology combined with microscopic IR lens design advancements are presented as an alternative solution for viable low-level leakage (LLL) defect localization and circuit characterization. The 30 micron pitch amorphous silicon type detector used in these analyses, rather than vanadium oxide (VOx), has sensitivity less than 50mK at 25C. Case studies reported demonstrate LWIR enhanced package-level and die-level defect localization contrasted with other quantum and thermal detectors in localization systems.
To Reveal Invisible Doping Defect by Nanoprobing Analysis, Scanning Capacitance Microscopy, and Simulation
Authors: Lai LiLung , Yang Li , Wang Chunhui , Wu Yong 
Published: December 2020

Abstract
Modern techniques of semiconductor physical failure analysis are effective at revealing physical defects and device material composition, however, dopant profiles/ concentrations are not easily determined since these materials are in trace concentrations. Therefore, defects related to dopants are often referred to as invisible defects. New techniques have been incorporated into failure analysis to reveal the invisible defects resulting from electrical carriers (via SCM/SSRM) and physical doping profile (via STEM/EDS) in nm-scale dimension. Using nanoprobing analysis, simulation for electrical modeling, along with EDS and SCM for physical profiling, we have a great opportunity to uncover abnormal doping issues allowing completion of the failure analysis and the execution of corrective actions.
Characterization of Gate Oxide Pinhole Defect in NMOS FinFET Devices
Authors: Chen Liangshan , Bousquet Arnaud , Schaeffer Tanya , Sheridan Lucile C. Teague , Hodgkins Lowell , Fu Bianzhu , Oh Chongkhiam 
Published: December 2020

Abstract
This paper highlights the application of nanoprobing technique and electron tomography analysis to characterize the tiny gate oxide pinhole defect in NMOS FinFET devices. Nanoprobing technique was utilized to achieve a better understanding on the failure mechanism by characterizing the device electrical behaviors, and electron tomography, capable of mitigating the common projection issue encountered by general TEM analysis, was applied for physical analysis. It has been demonstrated through two cases, one logic fail and the other memory fail, that these two techniques together can effectively identify the root cause of pinhole defect. This type of pinhole defect, characterized by a tiny spot of oxide discontinuity and without excessive materials inter-diffusion, has been extremely challenging in FA analysis. This paper will provide the analysis details leading to the successful characterization of such type of oxide pinhole defect.
Targeted Memory Test for Enhanced Diagnostic Fault Localization
Authors: Safran Laura , Hodge Christopher , Sylvestri John 
Published: December 2020

Abstract
A customized test resource has been created on Linux based automated test system to enhance and accelerate diagnostics and fault localization on random access memory. The resource, Targeted Memory Test, allows creation of a user defined sub-array which targets a specific area of a memory array. The resource includes a customized pattern set which can then be used with the unique Advanced Characterization shmoo plot routine to fully characterize any given failure mode. The sub-array patterns and characterization data can provide a clear understanding of the failure and reduce the time needed for both fault localization and physical failure analysis.
Pattern Search Automation for Combinational Logic Analysis
Authors: Venkat Krishnan Ravikumar , Xuan Seah Yi , Gabriel Lim , Abel Tan , Winson Lua , Ranganathan Gopinath , Angeline Phoa , Meng Chua Choon 
Published: December 2020

Abstract
Combinational logic analysis (CLA) using laser voltage probing allows studying standard cells such as NOR or NAND gates as a whole, instead of individual transistors. The process involves building a reference library of laser probing (LP) waveforms and comparing them to signals from the real device. While CLA has greatly increased the success rate and turn-around time for LP, there are difficulties in signal interpretation. This is partly due to the lack of precise understanding of the laser interaction area and probe placement and partly due to difficulties identifying the correct logic states in the waveform. In this work, we have significantly improved the CLA process by first predicting the shape of the waveform based on laser interaction with the target circuitry and second, implementing an automated pattern search algorithm to further increase the speed and reliability of CLA using LP.
Electron Channeling Contrast Imaging for Beyond Silicon Materials Characterization
Authors: Strakos Libor , Machek Ondrej , Vystavel Tomas , Schulze Andreas , Han Han , Caymax Matty , Young Richard 
Published: December 2020

Abstract
As semiconductor devices continue to shrink, novel materials (e.g. (Si)Ge, III/V) are being tested and incorporated to boost device performance. Such materials are difficult to grow on Si wafers without forming crystalline defects due to lattice mismatch. Such defects can decrease or compromise device performance. For this reason, non-destructive, high throughput and reliable analytical techniques are required. In this paper Electron Channeling Contrast Imaging (ECCI), large area mapping and defect detection using deep learning are combined in an analytical workflow for the characterization of the defectivity of “beyond Silicon” materials. Such a workflow addresses the requirements for large areas 10-4 cm2 with defect density down to 104 cm-2.
Investigation of Die Tilting of Packages with Single and Multi-chips
Authors: Wee Lo Chea , Yee Tan Sze , Yin Gan Sue , Sheng Goh Cin 
Published: December 2020

Abstract
Advanced package technology often includes multi-chips in one package to accommodate the technology demand on size & functionality. Die tilting leads to poor device performance for all kinds of multi-chip packages such as chip by chip (CbC), chip on chip (CoC), and the package with both CbC and CoC. Traditional die tilting measured by optical microscopy and scanning electron microscopy has capability issue due to wave or electron beam blocking at area of interest by electronic components nearby. In this paper, the feasibility of using profilemeter to investigate die tilting in single and multi-chips is demonstrated. Our results validate that the profilemeter is the most profound metrology for die tilting analysis especially on multi-chip packages, and can achieve an accuracy of &lt;2μm comparable to SEM.
Electromigration Response of Microjoints in 3DIC Packaging Systems
Authors: Attari Vahid , Duong Thien , Arroyave Raymundo 
Published: December 2020

Abstract
In multilevel 3D integrated packaging, three major microstructures are viable due to the application of low volume of solders in different sizes, and/or processing conditions. Thermodynamics and kinetics of binary compounds in Cu/Sn/Cu low volume interconnection is taken into account. We show that current crowding effects can induce a driving force to cause excess vacancies saturate and ultimately cluster in the form of microvoids. A kinetic analysis is performed for electromigration mediated intermetallic growth using multiphase- field approach. Faster growth of intermetallic compounds (IMCs) in anode layer in the expense of shrinkage of cathode IMC layer in shown. This work paves the road for computationally study the ductile failure due to formation of microvoids in low volume solder interconnects in 3DICs.
Asymmetric Data-Frequency Mapping and Multi Trigger-Probing for Improved Scan Debug
Authors: Swaminathan  , Anuradha  , Abuayob  , Eli  , Gitelmkher Konstantine , Nathan Bakken 
Published: December 2020

Abstract
Integrated-circuit device dimensions continue to shrink, enabling higher density of devices and smaller node size. A number of strategies to improve the resolution of failure analysis and fault isolation tools exist, but some of these techniques are reaching fundamental limits so that engineers are also challenged to innovative methods to increase the useful life of existing toolsets. Laser Scanning Microscopy including Laser Voltage Probing and frequency mapping struggle to maintain resolution commensurate with shrinking feature size. Here we present two methods to improve efficiency and capability of this toolset using existing optical hardware and configuration. The first method applies a frequency mapping technique using scan chain data patterns that allow for data manipulation. This enables an effective resolution increase through deconvolution of data collected in a sequence of scans completed on varied device states. A second method using multiple triggers per loop to evaluate a deterministic continuous wave signal is shown to reduce probe acquisition time, improve job throughput time, and enable, better signal-to-noise ratio for common scan chain debug workflow.
Reproducing the Fail from a Production Memory ATE on a Logic FA Tester
Authors: Rai Nivesh , Link Hans 
Published: December 2020

Abstract
We present a case study where an APG (Algorithmic Pattern Generator) based pattern from a memory tester is being converted to run on a logic FA tester. Due to the regular structure of memory patterns, the APG patterns are written in a high-level based language and converted on a real-time basis to be executed on the hardware. A logic analyzer is used to capture the test pattern that is seen by the Device Under Test (DUT). The captured test pattern is then converted to the Standard Test Interface Language (STIL) based pattern format with the help of a scripting language. An existing test program is modified to include the Timing, Levels, Specs and the pin configuration to adapt to the DUT. The failing condition for FA could be exactly reproduced after running the pattern on the FA tester and can be made as a generic solution for similar exercises.