Low Temperature Effect on Strained and Relaxed Ge pFinFETs STI Last Processes
Authors: Oliveira Alberto Vinícius de , Simoen Eddy , Agopian Paula Ghedini Der , Martino Joao Antonio , Mitard Jerome , Witters Liesbeth , Langer Robert , Collaert Nadine , Thean Aaron , Claeys Cor 
Published: February 2020

The lower effective mass of germanium compared to silicon makes its quite attractive for future high-performance applications, since high hole mobility material is required for p-type channel devices [1]. In combination with FinFET structures, which present a strong electrostatic coupling [2], it give rises to a promising future device, Ge pFinFET.
This work analyses the influence of low temperature effects on static parameters such as threshold voltage (VT), transcondunctance (gm) and subthreshold swing (SS) of strained and relaxed Ge pFinFET devices. The gate stack layer is composed of a paritally oxidized Si passivation layer, hafnium oxide (HfO2) and TiN. The temperature impact is analyzed from 200 K down to 77 K. The devices used in this work have been fabricated on a p-type silicon substrate at Imec/Belgium. There are two diffent STI last processes under evaluation. The first one is the strained channel, whereby a thin Ge layer has been grown on top of a thicker layer of SiGe relaxed buffer (SRB) on a silicon wafer. The other is a relaxed channel, where a thicker Ge layer has been grown on top of the silicon substrate. The planar device dimensions are fin width (Wfin) of 20 nm and geometric channel length (LG) of 1 µm and 4 fins in parallel. All measurements were carried out in linear operation.
As the temperature is varied from 200 K down to 77 K one clearly observes that the drain current (IDS) is increased and the curves shift to more negative values, as shown in Fig. 1. The temperature reduction causes the Ge intrinsic concentration to drop, which in turns results in a lower Fermi level value and consequently a threshold voltage (VT) value shift towards positive values [3]. On the other hand, as presented in Fig. 2 the temperature effect is not strong for both relaxed and strained devices, since the VT over temperature ratio values are quite low and similar, 3.25x10-4 V/K and 3.7x10-4 V/K, respectively. The IDS improvement is associated to the carrier mobility increase with the low temperature [4]. Furthermore, the difference between the IDS levels (ΔIDS) for a strained device and relaxed one (Fig. 1) is due to the impact of the strain that boosts the hole mobility and the effect remains for different temperatures. This means that the mobility scattering mechanism is the same, as confirmed in Fig. 3, since both devices present a similar slope. In contrast, the ΔIDS cannot be observed as the strained device presents a higher capacitance equivalent thickness. Moreover, while the IDS in the ON-region raises with the temperature fall, the leakage current reduces due to the thermal activation of the carrier generation in the subthreshold region, as depicted in Fig. 4. On the other hand, the slope for both strained and relaxed devices is different, pointing out that an additional effect also plays a role on the subthreshold swing.[1] S. Takagi et al., ECS Trans.,
35(3), 279 (2011).
[2] T. Chiarella et al., Solid-State Electron, 54, 855 (2010).
[3] A. A. Osman at el, Proc. the 4th Int. High Temp. Electron. Conf., 1998 Fourth International, p. 301 (1998).
[4] J. Mitard et al., Tech. Dig., IEEE VLSI (2009), p. 82.

Figure 1