(Invited) Nanostructures and Crystal Defects in Thick GaN and SiC Epitaxial Layers for Power Electronic Switches
Authors: Christou Aristos 
Published: February 2020

The state-of-the-art power switching devices made from SiC and GaN semiconductors contain a high density of crystal defects. Most of these defects are present in starting wafers and some are generated during device processing. There is little conclusive evidence so far on the exact role that the crystal defects play on device performance, manufacturing yield, and more importantly, long-term field-reliability especially when devices are operating under extreme stressful environments. This paper provides a review of the current state-of-the-art of SiC and GaN power semiconductor material technology, and the potential impact crystal defects may have on high-density power switching electronics.
Group III-Nitride materials suffer from both extended and point defects, each of which will challenge the material’s application in both vertical and lateral power devices. The extended defects include vertical threading dislocations of both edge and screw type. The latter defects have been shown to be correlated to leakage in vertical two terminal device structures while the influence of the former is still undetermined and remains a critical research issue. Channel surfaces in vertical three terminal devices will also degrade due to vertical threading dislocations. These extended defects occur in all epitaxial layers grown on c-plane substrates (the predominant and largest area substrate type) and are the result of the lack of a high quality substrate bulk material as well as substrate surface. The present substrate technology after multiple efforts (either GaN, SiC or Si) still have a high defect density indicating that low-defect seeds may be non-existing. Point defects influence the background carrier concentration in low-doped layers and various recombination processes.
The intrinsic nature of III-N materials makes nitrogen-vacancies a predominant point defect that automatically dopes the crystal n-type, but there are impurities (oxygen and carbon) from most growth environments that also contribute to conductivity. These defects are not well understood and not well controlled. Such defects must be minimized in order to realize thick epitaxial layers with drift regions that will support both high blocking voltages and low on-state resistances. A wide range of materials characterization methods have been applied to further understand these impurities.
The semiconductor and dielectric materials used in the construction of power electronics switching devices employed for energy efficiency applications experience extreme electrical and thermal stresses during the on-state as well as when switching high voltages and high currents. For example, in a bipolar type power semiconductor switching device in order to achieve significant conductivity modulation and reduce the drift-region resistance, high-level injection of minority carriers is typical. If the semiconductor contains a high density of crystal defects, as is the case with WBG semiconductors, minority carrier recombination phenomenon can be adversely affected. For example, it has been shown more than a decade ago [3, 4] that basal plane dislocations (BPDs) present in SiC are excited by the energy released from minority carrier recombination process; the result is excess BPD generation and its glide within the semiconductor material that leads to an increase in the drift-region resistance and thermal run-away in a forward biased bipolar junction diode
The reported experimental data for high-voltage SiC semiconductor strongly suggests that material defects have profound impact on its characteristics under extreme environments. Since GaN semiconductor has even higher density of material defects, this problem is further exacerbated especially in thick epitaxial GaN layers which are required for power switches beyond 5kV.
The integration of the pillar junction scheme with the trench-gate GaN MOSFET processes developed at the University of Maryland will be reported. The thick pillar junction epitaxial layers have been grown by a commercial vendor, using a windowed GaN growth process and/or selective deep etching, followed by GaN regrowth to fabricate columns with opposite carrier polarities. The doping density of the n--pillars under the gate has been specified with background carrier concentration n ≤ 1x1016 cm-3, while the p-pillars will have a higher doping density (p ≥ 1x1018 cm-3) to maximize depletion in the n--pillar. The p-body and n+-source layers are grown by subsequent epitaxial growth across the whole structure. Our current research into optimized trench gate fabrication and gate dielectric processing has been used to fabricate gate trenches into the structure. These devices can be compared to traditional trench MOSFETs with extremely thick blocking layers of comparable thickness to the pillar junction layer in order to determine the role of defects in thick GaN epi layers in terms of limiting device performance and reliability.