bluuebunny/crossref_metadata_2025_split huggingface dataset:
Flip Chip Joining with Quaternary Low Melting Temperature Solder Bump Fabricated with Injection Molded Solder
Authors: Hisada Takashi , Aoki Toyohiro , Nakamura Eiji , Kohara Sayuri , Mori Hiroyuki 
Published: December 2019

Abstract
IBM has developed and has been enhancing the injection molded solder (IMS) technology as an advanced solder bumping technology with flexible solder alloy composition applicable even to fine pitch and small diameter systems. IMS is a simple bumping technology that can form solder bumps by injection of molten solder into via holes patterned in a photoresist layer. IMS is applicable to formation of solder caps for Cu pillar bumping which is a technology widely used for fine pitch applications. One of the advantages of IMS is the capability of using ternary, quaternary, or more compositions solder alloys for bumping, which is not achievable by current plating technology. In this study, the feasibility of IMS bumping and flip chip joining with quaternary solder alloys is demonstrated through assembling of 2.5D package test vehicles using low melting temperature (135°C) SnBi based quaternary alloy solder and associated reliability test. The test vehicles passed the 2250 cycles criteria of thermal cycling test and the observation of microstructures showed that there is no significant crack at the solder joints after flip chip joining or after the 2250 cycles of thermal cycling test. In addition, the tensile test on SnBi based quaternary alloy solder, Sn-58wt%Bi-2.0wt%In with small amount of Pd (less than 1wt%) was conducted using fine diameter specimens. From the SS curve obtained from the test, Young's modulus of the solder was determined as 7.3 GPa and 0.2% proof stress was obtained as 73 MPa both at 25°C. The creep property of the solder was evaluated and the constants for Norton's creep law for the solder were determined at 25, 80 and 110°C. The microstructure observation and Energy Dispersive X-ray (EDX) analysis of the flip chip joints revealed the formation of a thick bismuth (Bi) layer between CuSn intermetallic compound (IMC) layers within a joint. The mechanical simulation of the 2.5D test vehicles showed that the thermomechanical stress of a flip chip joint with Bi/CuSn IMCs at thermal cycling condition is comparable to those of CuSn IMC or Sn-3.0Ag-0.5Cu (SAC305) solder joints consistent with the thermal cycling test result. The advantage of using low temperature quaternary solder materials in flip chip packages is confirmed by mechanical simulation of 2D packages at reflow condition which showed lower stress on low-k dielectric layers for the packages with quaternary solder joints than for the packages with SAC305 solder joints.
Optimal Lid Design Parameters for Reducing Warpage of Flip-chip Package
Authors: Shah Priyal , Bhagavat Milind 
Published: December 2019

Abstract
Flip-chip packages are usually integrated with a stiffener ring (SR) or lid to reduce the warpage which usually consumes considerable substrate space and hence, reduce the effective area available for placement of dies and passive components. With chip module size growing in modern semiconductor devices (e.g., to enable heterogeneous integration of different functional dies), there is a need to reduce the substrate area occupied by the lid while also reducing the package warpage to an allowable value. This requires an accurate understanding of how different parameters of the lid affect the warpage of the package. Here, for a large package, effects of the lid design variables, including (i) SR versus lid, (ii) lid foot width, (iii) lid plate thickness to foot width ratio, (iv) lid material, and (v) thickness of thermal interface material (TIM) connecting the die and the lid, on the warpage have been analyzed using the 3-D elasticity theory and the finite element method. It is found that for a given value of the lid plate thickness to foot width ratio, the warpage of the package is a non-monotonic function of the foot width and is not necessarily minimum for the maximum value of the foot width. The effects of lid material and TIM thickness are found to depend upon the foot width. Various results presented here should provide packaging engineers with guidelines to obtain optimal lid designs that minimize the package warpage while offering noticeable saving in the effective substrate area.
FLUXES WITH DECREASED VISCOSITY AFTER REFLOW FOR FLIP-CHIP AND SIP ASSEMBLY
Authors: Mao Runsheng , Chen Fen , Lee Ning-Cheng 
Published: December 2019

Abstract
A series of flux systems have been developed which would result in a reduced viscosity after reflow. This enables a high viscosity, high tack flux to be used to secure components at the component placement and reflow stage, but ends up with a low viscosity flux residue after reflow, thus facilitating the flux residue to be cleaned. A technique for forming such special fluxes is to establish a temporary association force within the materials themselves, such as an acid-base association. This kind of association force can increase the apparent molecular weight and cause material viscosity to increase. After a heating process, one of the critical ingredients was evaporated, thus eliminating the association force, causing a decrease in the apparent molecular weight, and consequently a decrease in viscosity or an increase in mobility. The evaporation of one ingredient can be the result of one ingredient having a lower boiling point, or the decomposition of one ingredient during heating. A strong association force is desired to allow this acid-base combination approach to work. In this work, the volatile ingredient approach was less effective than a decomposable ingredient approach, presumably due to the formation of a bigger association cluster from the decomposable ingredient. Accordingly, the decomposable ingredient was the best approach to lower flux viscosity after reflow.
Package Qualification Envelope for 22FDX® Technology
Authors: Klewer Christian , Kuechenmeister Frank , Paul Jens , Breuer Dirk , Boehme Bjoern , Cho Jae Kyu , Capecchi Simone , Thiele Michael 
Published: December 2019

Abstract
This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV.
Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.
Thermal Decoupling in Power Electronics Modules Using Thermal Pyrolytic Graphite
Authors: Paul Riya , Deshpande Amol , Luo Fang 
Published: December 2019

Abstract
The device within a power electronics module package will fail if the maximum junction temperature is not within the device's permissible maximum temperature rating specified by the manufacturer. Modern electronic miniaturization demands multi-chip module (MCM) packaging providing different semiconductor technology integration, reduced number of component interconnects, and lower power supply. But the huge amount of heat generated by each chip produces thermal coupling among devices, leading to an increase in the junction temperature. The power device specifications in the datasheet assume the devices being mounted on a suitable heatsink. Wide bandgap (WBG) devices like silicon carbide (SiC) devices can generally sustain a maximum junction temperature of about 175 °C – 200 °C. The junction temperature of the WBG devices becomes severe in a high-density high-power module. This highlights the need for a thermal management system to limit the maximum junction temperature within the device's permissible range. As a result, the power module needs to be connected to a heatsink to effectively increase the surface area of the heat dissipation junctions. A high conductivity material based heatsink extracts heat effectively from the module as the thermal resistance value remains low. In this paper, preliminary thermal analysis is done for a high density high-power module where the high in-plane thermal conductivity of thermal pyrolytic graphite (TPG) is exploited in substrate as well as heatsink designs. TPG brings down the junction temperature to a considerably lower level, leading to a safer power module functioning. This paper focuses on the design and proper alignment of the substrate and heatsink with respect to the module layout so that maximum junction temperature is reduced by proper heat extraction far below the operating temperature of the devices and also extent of reduction of the thermal coupling among the power devices placed next to each other on the same plane within the power module.
Innovative Panel Plating for Heterogeneous Integration
Authors: Boulanger Richard , Hander Jon , Moon Robert 
Published: December 2019

Abstract
Panel plating requirements are much more demanding as more applications migrate from silicon to panel assembly such as Panel Level Fan Out (PLFO) to leverage the large sizes of the panels. More recently, Heterogeneous Integration (HI) like Intel's Embedded Bridge (EMIB) or various other embedded die concepts are also pushing the boundary for typical panel structures. Line widths and spaces less than 10 Microns, thickness uniformity better than 10%, via topology free of voids and the same height as the redistribution lines are critical.
Traditional Panel plating tools are mostly for bulk processing and are not designed to handle these additional requirements. A new tool was required to overcome these challenges. An electroplating process with a single panel per reservoir approach is used. An overhead transporter brings the individual panels that have been pre-loaded in a rigid panel holder designed to handle large currents as well as reduce the warpage to a series of plating reservoirs as well as pre and post processing steps with the tool.
The first process is to reduce voiding by removing all air in a vacuum chamber and then inserting degassed water in the same chamber to “prewet” the panel. Panels are then typically immersed in an acid bath known as an activation step before processing in the plating cells. The plating cells are customized for each metal layer but often include a fine alignment feature, a current uniformity optimizing shield, multiple anode channels for dynamic uniformity along with an agitation mechanism to produce a uniform thin boundary layer at the panel surface. This whole mechanism needs to be very close to the panel, yet still allow some warpage typically associated with panel manufacturing.
This paper will demonstrate that it is possible to achieve better line density, bump thickness uniformity and void free vias to allow semiconductor like assembly for Heterogeneous Integration on a standard Printed Circuit Board (PCB) instead of more expensive semi additive processes or silicon interposers
Evaluation of die to organic laminate to PCB interconnects up to 50GHz
Authors: Bulumulla Selaka , Ramachandran Koushik 
Published: December 2019

Abstract
Ceramic substrates have traditionally been used in RF and microwave packaging applications because of the electrical properties at high frequencies. However, there is significant interest in using organic laminates due to its tighter wiring ground rules for high density packaging and lower cost of fabrication. The high frequency performance of interconnection from die to PCB using an organic packaging substrate has not yet been studied in detail. In this work, the interconnect performance of die to organic laminate to PCB up to 50 GHz was modeled and characterized using a test vehicle assembly. The test vehicle was specifically designed with test pads to characterize the interconnect performance at multiple levels of interconnection. A comparison study using a ceramic package substrate was also carried out. The modeling and hardware testing results from this study showed −3dB bandwidth of more than 50GHz for printed circuit board (PCB) to organic laminate and a bandwidth of 40GHz for the die to organic laminate to PCB interconnection. The results from this study showed that the organic laminate demonstrated a high frequency performance comparable to that of the ceramic substrate, which makes it suitable as a packaging substrate material for high frequency applications.
A Flexible Down-Converter for Satellite Communication in the Ka-Band
Authors: Uhlig Peter , Kulke Reinhard , Günner Carsten , Kassner Jürgen , Möllenbeck Gregor 
Published: December 2019

Abstract
Conventional communications satellites operate with fixed frequency, polarisation and coverage plans that are drawn up years before their launch during the payload definition phase. The satellite will typically be designed for a lifetime of more than fifteen years. During this operating period, changes in bandwidth requirements and the distribution of the service across its geographic coverage are more than likely. A new generation of communication satellites is expected to respond flexibly to these regional and temporal fluctuations in demand. The concept of cellular division of the coverage area and the coverage of these cells with spot beams in connection with the reuse of frequency bands enables this flexibility. The satellite's frequency plan has to be redefined throughout the mission lifetime via commands from the ground. The Flexible Down-Converter DOCON is one of the new components that allow satellite signals to be redistributed between service areas to flexibly reallocate the most critical spectrum resources as needed. DOCON is a flexible Ka-band down-converter from RF = 27.5 ... 30.0 GHz to IF = 17.7 ... 20.2 GHz designed for GEO communication satellites. The device includes the housing, DC-, RF-, and telemetry / tele-command interfaces. An Engineering Model (EM) in form, fit and function was successfully built and tested. The next stage, the Engineering Qualification Model (EQM), is currently in fabrication and will be qualified until end of 2019. The modular concept comprises hermetically sealed LTCC microwave modules as key building blocks. There are three of these LTCC-modules: the Local Oscillator Module (LOM), the Mixer Module (MXM), and the Variable Gain Module (VGM). Their function and realization shall be discussed in this paper.
Development of Backside Buried Metal Layer Technology for 3D-ICs
Authors: Watanabe Naoya , Araga Yuuki , Shimamoto Haruo , Kikuchi Katsuya , Nagata Makoto 
Published: December 2019

Abstract
In this study, we developed backside buried metal (BBM) layer technology for three-dimensional integrated circuits (3D-ICs). In this technology, a BBM layer for global power routing is introduced in the large vacant area on the backside of each chip and is parallelly connected with the frontside routing of the chip. The resistances of the power supply (VDD) and ground (VSS) lines consequently decrease. In addition, the BBM structure acts as a decoupling capacitor because it is buried in the Si substrate and has metal–insulator–silicon structure. Therefore, the impedance of power delivery network can be reduced by introducing the BBM layer.
The fabrication process of the BBM layer for 3D-ICs was simple and compatible with the via-last through-silicon via (TSV) process. With this process, it was possible to fabricate the BBM layer consisting of electroplated Cu (thickness: approximately 10 μm) buried in the backside of the CMOS chip (thickness: 43 μm), which was connected with the frontside routing of the chip using 9 μm-diameter TSVs.
Control of Void Formation in Adhesively Bonded Joints
Authors: Dytiuk Nina S. , Marinis Thomas F. , Soucy Joseph W. 
Published: December 2019

Abstract
Adhesively bonded joints are ubiquitous in electronic assemblies that are used in a wide range of applications, which include automotive, medical, military, space and communications. The steady drive to reduce the size of assemblies in all of these applications, while providing increased functionality, generates a need for adhesive joints of higher strength, improved thermal and electrical conductivity and better dielectric isolation. All of these attributes of adhesive joints are degraded by the presence of voids in them. The quest to minimize voids in bonded structures motivated this study of their formation in a solvent cast, die bond epoxy film, which undergoes a liquid phase transition during cure. Void formation is influenced by a number factors, which include wettability of the bonded surfaces, adsorbed water, amount of solvent retained in the film, volume of entrapped air, thermal profile of the cure schedule, and clamping pressure during cure. We have been exploring the interaction of these parameters and their impact on void retention in bonded joints with the aid of a moving boundary, finite difference model that tracks the movement of volatile species into and out of the void under diffusion control. The position of the void interface is updated at each discrete time step by integrating the product of the time step and flux of diffusing species over the area of the interface. The internal pressure of the void is determined by application of the Young-Laplace equation, while Henry's law is used to estimate the concentration of diffusing species adjacent to the void interface. The calculation proceeds for a time equivalent to the integral of the time temperature product required to achieve a 70% cure state of the adhesive, at which point the void interface is immobile. The adhesive we have chosen for this study is transparent in both the pre and post-cured states, so by sandwiching the material between glass slides we are able to observe void formation and evolution during cure. This allows us to directly observe the effects of various parameters for comparison with our predicted behavior.
Advanced Die Saw Technology for WLCSP Reliability Enhancement
Authors: Chen Ching Chia , Wang Yu-Po , Tsai Jensen , Chen Hsin Long 
Published: December 2019

Abstract
As consumer and portable devices get thinner and more functionality. Chips which are made by less than 28 nm node wafer with extreme Low-k (ELK) inter metal dielectric material is a trend in order to contain more transistors and to lower power consumption. However, side wall crack (SWC) for WLCSP is one of the major challenges since ELK layer getting brittle.
Laser grooving is applied to remove metal before blade saw, but the high temperature during laser grooving usually easily generates HAZ (heat-affected zone) which can induce stress concentration and lower chip strength. The laser ablation also leaves metal-silicon residue (or recast) from the re-deposition of silicon to the groove and surrounding areas. Therefore, SWC (sidewall crack) is a huge potential risk waiting to happen after pick and place, during shipment and during SMT process. In the industry, HAZ size and SWC rate could be reduced by adjusting process parameters, or by exploring new alternatives to eliminate HAZ and silicon recast is one of driving factors of this paper.
In this study, plasma etching was applied as surface treatment on the scribe line after laser grooving process with ELK wafer. Plasma could etch HAZ and recast area and expected to increase chip strength and reduce SWC rate. Plasma applied with various process time and power, and different types of mask coating materials were studied. Different plasma gases and effectiveness will be discussed.
Conventional blade dicing process will be compared to different plasma etching conditions for mechanical properties of die using 3-point bending test to check die strength, and SEM and OM to verify quality of sidewall of the die. Finally drop test was performed to confirm the reliability enhancement.
The Case of Failure Analysis of the PCBA Wire Corrosion under High Reliability Requirements
Authors: Zheng Jie , Zou Yabing , Yang Ying , Shen Jianghua , Zhang Yingjie 
Published: December 2019

Abstract
The wire breakage of a no-cleaning process PCBA occurs at the beginning of the application. Through visual inspection, cross-section, SEM & EDS, and ion chromatography analysis, it was found that the high content of ions (bromide ion) on the surface of the solder source side caused corrosion and fracture of the conductors of wave soldering surface, this article also analyzes the source of bromide ion and conclude the main factors involved in this type of failure.
Dust and Water Resistance Testing Methodology for Environmental Sensors
Authors: Kummerl S. , Mantle D. , Patel N. , Munje R. , Chen P. 
Published: December 2019

Abstract
This paper explores the “IEC standard 60529 International Protection Marking” also sometimes referenced as Ingress Protection Marking and how it applies to mobile and wearable electronics on a component level. The testing methodology used for an OCQFN (Open Cavity Quad Flatpack No-lead) humidity sensor will be evaluated including pass/fail criteria. The applicability of this standard has been developed to verify the robustness of finished mechanical assemblies intended to be put in static mounted applications but in this case has been adopted to verify the robustness of a semiconductor based sensor at a packaging level with accelerated pre-conditioning to predict the end of life performance.
A Study of Defects in High Reliability Die Sort Applications
Authors: Parrish Sarah 
Published: December 2019

Abstract
For high-reliability microelectronics with uses in aerospace, defense, automotive, and medical applications, in-line visual inspection during the die sort process allows for a higher quality and more robust process for generating known-good-die. The visual inspection serves three primary functions: verifying unique device characteristics (such as bumps, MEMS structures, waveguides, etc.), verifying the device is free from singulation defects, and verifying the die sort process induces no device damage. Performing a visual inspection of the die top surface and one edge during the pick and place process allowed qualification of a non-surface contact edge grip approach for sensitive surface MEMS and optoelectronic parts. Die 100 microns thick or less were also inspected to ensure no cracking during the die pick process. For continual process reliability improvement and optimization, the inspection results must be captured and logged along with incoming product details including the wafer ID, electrical test results, and chip ID. This logged information is then traceable to the die position in the output medium. As new device manufacturing technology is implemented, this screening for process-induced defects is required for a robust manufacturing process.
Impact of multi-dimensional vibration trajectories on quality and failure modes in ultrasonic bonding
Authors: Schemmel Reinhard , Eacock Florian , Dymel Collin , Hemsel Tobias , Hunstig Matthias , Brökelmann Michael , Sextro Walter 
Published: December 2019

Abstract
Ultrasonic joining is a common industrial process. To build electrical connections in the electronics industry, uni-axial and torsional ultrasonic vibration have been used to join different types of workpieces for decades. Many influencing factors like ultrasonic power, bond normal force, bond duration and frequency are known to have a high impact on bond quality and reliability. Multi-dimensional bonding has been investigated in the past to increase ultrasonic power and consequently bond strength. This contribution is focused on the comparison of circular, multi-frequency planar and uniaxial vibration trajectories used for ultrasonic bonding of copper pins on copper substrate. Bond quality was analyzed by shear tests, scanning acoustic microscopy and interface cross-sections.