Strain Relaxed Silicon Germanium Buffer Layers: From Growth to Integration Challenges
Authors: Dube Abhishek , Huang Yi-Chiau , Cherian Benjamin , Nafisi Kourosh , Chung Hua , Chu Schubert 
Published: February 2020

Silicon germanium (SiGe) strain relaxed buffers (SRB) have been an active area of investigation both in academia as well as the semiconductor industry for a number of years [1, 2]. These relaxed epitaxial layers act as virtual substrates or templates for subsequent growth of tensile or compressively strained layers that can serve as N and PMOS channels for continued scaling of Si CMOS technology. The most well established methodology, proposed by Fitzgerald et al. [1], for growing SiGe SRB’s is by grading the Ge concentration throughout the layer, typically 2-3 µm thick, which leads to the creation of a series of low lattice mismatched interfaces. By managing the lattice mismatch using this grading method the threading dislocation density (TDD) can be reduced significantly. In the work reported here, we have studied thick graded SRB layers from a holistic perspective that involves growth, defect density optimization followed by the growth of strained Si/SiGe layers on these virtual substrates.
The focus during this study was on the high temperature growth regime (> 900 oC) which helps reduce TDD due to the higher dislocation velocity resulting in a higher number of dislocation annihilation events. Depicted in Fig. 1 is one such example, where a 2 µm graded layer (0-20 % Ge grading) was grown followed by a 1 µm layer at 20 % Ge analyzed using SIMS. The growth for this sample was carried out using Dichlorosilane (SiH2Cl2 or DCS) and Germane (GeH4) at 900 oC and 80 Torr under H2 ambient in an Applied Materials CenturaTM RP Epi reactor. From a morphology perspective these films are extremely rough after growth due to the well-known cross hatch pattern formation as shown in the AFM scan in Fig. 2 (a). In order to enable growth of strained and atomically smooth channel layers on top of this SRB, a chemical-mechanical planarization (CMP) step is required to remove the cross-hatch and leave behind a much smoother template. As shown in Fig. 2(b), Applied Materials ReflexionTM LK CMP tool was able to polish these substrates down to an RMS roughness of ~ 1.3 Å, compared to a starting RMS roughness of ~ 66 Å, after ~ 0.2 µm removal of the 20 % Ge constant composition layer. To characterize the TDD for this layer, plan view transmission electron microscopy (PV-TEM) was performed and the results are shown in Fig. 3. As seen in this case, 2 threading dislocations are visible in a 100 µm2 area which translates to a TDD of ~ 2 x 10 6 /cm2. PV-TEM however, has limited resolution and led us to explore large area defect etching utilizing vapor phase hydrochloric acid (HCl) in the epi reactor itself [3]. HCl based defect etching was done on SRB samples grown at various temperatures in the 900 – 1100 oC range after they had gone through CMP. The resulting etch pits, which in essence are highlighted threading dislocations, were inspected optically on a 300 µm2 area as shown in Table 1 where 1100 oC growth resulted in the lowest TDD ~ 5 x 10 4 /cm2. For temperatures greater than 1000 oC, GeCl4 was used instead of GeH4 in order to keep the process chamber walls clean.
Another critical aspect of SRB integration is the growth of strained Si or SiGe layers on top of this relaxed layer. These strained layers serve as the channel material for N or PMOS transistors. Figure 4 represents one such illustration in the form of a cross-section TEM where we have grown a Si layer under tensile strain, 436 Å in thickness, on a 30 % Ge graded SRB layer post CMP. This Si layer appears to be defect free, and based on the (224) reciprocal space map (RSM: In Fig. 5) acquired using X-ray diffraction techniques, it is < 5 % relaxed with respect to the underlying SRB. A systematic optimization of epi pre-clean and H2 pre-bake had to be performed to achieve defect free Si or SiGe (~ 60-70 % Ge) growth on SRB templates.
In summary, we have explored the growth and integration of SiGe SRB layers in order to enable scaling for future generation CMOS technology beyond 7 nm. Higher growth temperatures (> 1000 oC) were effective in improving the TDD by almost two orders of magnitude. Pseudomorphically strained N and P channel growth on SiGe SRB has also been achieved by optimizing the pre-clean and prebake conditions.
References:

Fitzgerald et al., Appl. Phys. Lett., 59(7), 1991

Liu et al., IEEE- ISTDM meeting, 2012

Hartmann et al., Thin Solid Films, 557, 2014

Figure 1