bluuebunny/crossref_metadata_2025_split huggingface dataset:
Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic Analyses
Authors: Lomné V. , Dehbaoui A. , Ordas T. , Maurine P. , Torres L. , Robert M. , Soares R. , Calazans N. , Moraes F. 
Published: December 2020

Side channel attacks (SCA) are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of secure triple track logic (STTL) against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind STTL are valid in general and particularly for FPGAs. Also, the paper shows that this new logic may provide interesting design guidelines to get circuits that are resistant to differential power analysis (DPA) attacks which and also more robust against differential electromagnetic attacks (DEMA).
Investigation of the Gate Length and Drain Bias Dependence of the ZTC Biasing Point Instability of N- and P-Channel PD SOI MOSFETs
Authors: Camillo Luciano Mendes , Martino João Antonio , Simoen Eddy , Claeys Cor 
Published: December 2020

This paper presents an analysis of the instability of the Zero Temperature Coefficient (ZTC) as a function of the gate length and drain bias for partially depleted SOI MOSFETs operating at high temperatures (from room temperature up to 573K). The study takes into account temperature dependent model parameters such as threshold voltage and channel mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplifications used for the VZTC model as a function of temperature in the linear and the saturation regime.
A Fast-Response Charge-Pump Gate Driver Applied to Linear Regulation
Authors: Mansano André L. R. , De Lima Jader A. , Swart Jacobus W. 
Published: December 2020

This paper presents a compact charge-pump gate driver (CPGD) that dynamically adjusts the driving voltage VGS_SW of power switches, following stringent load transients in amplitude and duration. Owing to its simple topology, the CPGD responsively sustains regulation of the charge-pump (CP) output voltage VOUT within the range [2.4V, 3.0V] during transient load, while consuming only tens of μA. Contrary to driving techniques that depend on the settling of VOUT before adjusting VGS_SW, the CPGD instantaneously compares VOUT to a reference VREF and optimally sets VGS_SW. The circuit shows low sensitivity with switching frequency fsw across a broad range [50KHz fsw 1MHz]. Simulations with PSPICE and Bsim3v3 models attest the CPGD performance at extreme scenarios of a light and heavy load current ILOAD. For a 20μs-step of ILOAD from 0 to 20mA, the CPGD takes only 20μs to raise VGS_SW from 1.0V to 4.75V. The entire CP regulator was prototyped on a standard 0.35μm CMOS fabrication process, with the CPGD occupying an area of 0.014μm2. Experimental results match closely both DC and transient the expectations for CPGD. The driver features consumption below 475μW and complies with a low-voltage supply, such as1.5V-batteries.
Design Validation of Multithreaded Processors Using Threads Evolution
Authors: Ravotto D. , Sanchez E. , Sonza Reorda M. , Squillero G. 
Published: December 2020

Within the design arena of modern devices based on cutting-edge processor cores, the availability of effective verification, validation and test methodologies able to work on high-level descriptions of processor cores represents an interesting advantage, since it can dramatically reduce the overall time for design and manufacturing, while improving yield and quality. In this paper we propose a semi-automatic test program generation technique able to target modules in modern computer architectures that implement the multithreading paradigm. The methodology starts from high level descriptions of processor cores and using an incremental multi-run approach produces, with very limited manual intervention, a test set able to maximize verification metrics. Experimental results gathered on a couple of real complex designs (the OpenSPARC™ T1 and T2) show the effectiveness of the proposed methodology.
Motion Estimation Architecture Using Efficient Adder-Compressors for HDTV Video Coding
Authors: Porto Marcelo , Silva André , Almeida Sergo , Da Costa Eduardo , Bampi Sergio 
Published: December 2020

This paper presents real time HDTV (High Definition Television) architecture for Motion Estimation (ME) using efficient adder compressors. The architecture is based on the Quarter Sub-sampled Diamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC) algorithm. The main characteristic of the proposed architecture is the large amount of Processing Units (PUs) that are used to calculate the SAD (Sum of Absolute Difference) metric. The internal structures of the PUs are composed by a large number of addition operations to calculate the SADs. In this paper, efficient 4-2 and 8-2 adder compressors are used in the PUs architecture to achieve the performance to work with HDTV (High Definition Television) videos in real time at 30 frames per second. These adder compressors enable the simultaneous addition of 4 and 8 operands respectively. The PUs, using adder compressors, were applied to the ME architecture. The implemented architecture was described in VHDL and synthesized to FPGA and, with Leonardo Spectrum tool, to the TSMC 0.18μm CMOS standard cell technology. Synthesis results indicate that the new QSDS-DIC architecture reach the best performance result and enable gains of 12% in terms of processing rate. The architecture can reach real time for full HDTV (1920x1080 pixels) in the worst case processing 65 frames per second, and it can process 269 HDTV frames per second in the average case.
Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors
Authors: Contreras E. , Cerdeira A. , Alvarado J. , Pavanello M. A. 
Published: December 2020

The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.
PDMS (Polydimethylsiloxane) Microfluidic Chip Molding for Love Wave Biosensor
Authors: Tarbague H. , Lachaud J.-L. , Destor S. , Vellutini L. , Pillot J.-P. , Bennetau B. , Pascal E. , Moynet D. , Mossalayi D. , Rebière D. , Dejous C. 
Published: December 2020

We present the development of new Polydimethylsiloxane (PDMS) chips, which are coupled with Love acoustic wave sensors to realize a detection cell of bio-organisms in liquid media. Three generations of biocompatible PDMS chips have been developed. Built-in thermistors allow a thermal control (±0.05°C). Unlike the usual assemblies, this chip is maintained by pressure on the sensor and not sticked on its surface. This technique makes it entirely removable and cleanable. Therefore, the surface of the sensor can be functionalized or regenerated. The realization of these chips is quick and inexpensive.We here outline the development of these different cells and present characteristics of the resulting microsensors, depending on the chip configuration. Real-time responses during antibodies immobilization are presented and analyzed. Antibodies at typical concentration of 45μg/ml are successfully fast detected, with response times from 350s for static down to 90s for dynamic detection setup, with similar sensitivity. Discussions on the mechanical fluid behaviour at the near sensor surface allow to better understand these results and to investigate further developments aiming at improving the quality of the fluid stream in order to even increase future sensor characteristics.
Thin-Film Lateral SOI PIN Diodes for Thermal Sensing Reaching the Cryogenic Regime
Authors: De Souza Michelly , Rue Bertrand , Flandre Denis , Pavanello Marcelo Antonio 
Published: December 2020

This paper presents the performance of lateral SOI PIN diodes for temperature sensing in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen for calibration. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend the analysis, verifying the accuracy of the existing model.
Table of Contents and Foreword
Authors: Lubaszewski Marcelo , Pavanello Marcelo Antonio 
Published: December 2020

This issue of the Journal of Integrated Circuits and Systems (JICS) features a very broad content, including papers on RF, AMS and digital design, presenting low voltage, low power and low noise solutions, improving the circuit robustness against attacks, proposing new approaches for video compression and dealing with reconfigurability, SAT solvers and energy harvesting. Six of these papers have been selected from the presentations given at SBCCI2010 (23rd Symposium on Integrated Circuits and Systems Design), which has been held in São Paulo, Brazil in 2010. Among the contributions presented at the Symposium, only a few best rated were selected by the JICS Editorial Board and have been invited to submit an extended version to the Journal. These papers have been reviewed by external experts and have been accepted for the special section on best SBCCI2010 papers. In addition to the best papers presented at the conference, three spontaneous submissions passed through the usual reviewing process and have been accepted as regular papers. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection, which guarantees the scientific level of this issue.We sincerely hope that JICS readers will enjoy these contributions.
Marcelo Lubaszewski - JICS Editor-in-chief
Marcelo Pavanello - JICS Co-Editor
A Cellular Automata Based Multi-Process Microfabrication Simulator
Authors: Colombo Fábio B. , Carreño Marcelo N. P. 
Published: December 2020

We describe a 3D simulator for several fabrication techniques utilized to create MEMS. The software is based on a cellular automata model and allows the user to simulate several processes, such as anisotropic wet etching in alkaline solutions and deep reactive-ion etching (DRIE) on (100) oriented Si substrates. The simulator allows for arbitrarily shaped masking materials and several processes can be applied in sequence to the same substrate. This enables the software to simulate the fabrication of complex MEMS devices which require more than one etching step. So, we show examples of fabrication processes involving different combinations of substrate wet and plasma DRI etching. Although relatively simple automata were utilized for the simulations, the results are in excellent accordance with reported experimental results. At this moment the simulations do not consider physical parameters affecting the fabrication process, the results shown here are important from an engineering point of view for qualitative analyses. At this moment more sophisticated automata are in development to simulate other processes, like film deposition (with different degrees of anisotropy) on previously etched substrates.
Temperature and Silicon Film Thickness Influence on the Operation of Lateral SOI PIN Photodiodes for Detection of Short Wavelengths
Authors: De Souza Michelly , Bulteel Olivier , Flandre Denis , Pavanello Marcelo Antonio 
Published: December 2020

This work presents an analysis of the temperature influence on the performance of a lateral thin-film SOI PIN photodiodes when illuminated by low wavelengths, in the range of blue and ultra-violet (UV). Experimental measurements performed from 100K to 400K showed that the optical responsitivity of SOI PIN photodetectors is affected by temperature change, being reduced at low and moderately high temperatures. Two-dimensional numerical simulations showed the same trends as in the experimental results, and were used both to investigate the physical phenomena responsible for the observed behavior as a function of the temperature as well as to predict the influence of silicon film thickness downscaling on the photodetector performance.
Table of Contents and Foreword
Authors: Lubaszewski Marcelo , Pavanello Marcelo Antonio 
Published: December 2020

This issue of the Journal of Integrated Circuits and Systems (JICS) features a very broad content, including papers on analog and digital design, presenting novel solutions for circuit synthesis, energy efficiency, memory architectures and processor modeling and also proposing new approaches for wireless communication, motion estimation and neural networks applications. Six of these papers have been selected from the presentations given at SBCCI2011 (24th Symposium on Integrated Circuits and Systems Design), which has been held in João Pessoa, Brazil in 2011. Among the contributions presented at the Symposium, only a few best rated were selected by the JICS Editorial Board and have been invited to submit an extended version to the Journal. These papers have been reviewed by external experts and have been accepted for the special section on best SBCCI2011 papers. In addition to the best papers presented at the conference, one spontaneous submission passed through the usual reviewing process and has been accepted as a regular paper. We would like to thank the authors for their effort in preparing these high quality papers, as well as the reviewers for their help on paper selection, which guarantees the scientific level of this issue.We sincerely hope that JICS readers will enjoy these contributions.Marcelo Lubaszewski - JICS Editor-in-chief Marcelo Antonio Pavanello - JICS Co-Editor
Induced Optical Losses in Optoelectronic Devices due Focused Ion Beam Damages
Authors: Vallini F. , Barea L. A. M. , Dos Reis E. F. , Von Zuben A. A. , Frateschi N. C. 
Published: December 2020

A study of damages caused by gallium focused ion beam (FIB) into III-V compounds is presented. Potential damages caused by local heating, ion implantation, and selective sputtering are presented. Preliminary analyzes shows that local heating is negligible. Gallium implantation is shown to occur over areas tens of nanometers thick. Gallium accumulation as well as selective sputtering during III-V compounds milling is expected. Particularly, for GaAs, this effect leads to gallium segregation and formation of metallic clusters. Microdisks resonators are fabricated using FIB milling with different emission currents to analyze these effects on a device. It is shown that for higher emission current, thus higher implantation doses, the cavity quality factor rapidly decreases due optical scattering losses induced by implanted gallium atoms.
A 65nm CMOS 60 GHz Class F-E Power Amplifier for WPAN Applications
Authors: Deltimple N. , Dréan S. , Kerhervé E. , Martineau B. , Belot D. 
Published: December 2020

This work presents a two-stage 60 GHz Power Amplifier designed in a 65nm CMOS technology dedicated to low cost Wireless Personal Area Network (WPAN) applications. In order to provide a high efficiency operation, the PA is based on a Class E power stage. A Class F driver stage is also designed to provide a square waveform signal to the Class-E power stage. To realize the output networks of both driver and power stage at 60 GHz, distributed elements are used instead of lumped elements. The post-layout simulation results show a saturated output power of 15 dBm with a peak PAE of 26% at 60 GHz. It achieves a gain of 15dB at 60 GHz.
CMOS Image Sensor Featuring Current-Mode Focal-Plane Image Compression
Authors: Oliveira Fernanda D. V. R. , Haas Hugo L. , Gomes José Gabriel R. C. , Petraglia Antonio 
Published: December 2020

The interest in focal-plane processing techniques, by which image processing is carried out at the pixel level, has increased since the advent of active pixel sensors in the middle 90’s. By sharing processing circuitry by a group of neighboring pixels such techniques enable high-speed imaging operation and massive parallel computation. Focal-plane image compression is particularly interesting, because it allows for further reduction in data rates. The proposed approach also benefits from processing currents rather than voltages, which not only suits current-mode APS imagers, but also enables the circuits to operate at low voltage supply levels and achieve high speed. Moreover, arithmetic computations such as additions and scaling are easily implemented in current mode. Whereas current-mode imaging architectures produce higher fixed pattern noise (FPN) figures than their voltage-mode counterparts, low FPN can be achieved by applying correlated double sampling (CDS) and gain correction techniques. This work presents a 32 × 32 gray-level imaging integrated circuit featuring focal plane image compression, such that for each 4 × 4 pixel block, analog circuits implement differential pulse-code modulation, linear transform, and vector quantization. Other processing functions implemented in the chip are CDS and A/D conversion. Theoretical details are described, as well as the test setup of the chip fabricated in a 0.35 μm CMOS process. To validate the proposed technique, experimental results and captured photographs are shown. The CMOS imager compresses captured images at 0.94 bits/pixel for an overall power consumption below 40 mW (white image), which is equivalent to approximately 36 μW per pixel. Using photographs taken from bar-target pattern inputs, it is shown that details up to 2 cycles/c mare preserved in the decoded images.
Fully Reliable Dynamic Routing Logic for a Fault-Tolerant NoC Architecture
Authors: Alhussien Abdulaziz , Verbeek Freek , Van Gastel Bernard , Bagherzadeh Nader , Schmaltz Julien 
Published: December 2020

A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The novelty of this routing logic is that it is capable of using runtime information on availability of links to dynamically bypass faulty channels. When faults occur, no offline reconfiguration or dropping of packets is necessary. Instead, dynamic routes are suggested on-the-fly. Routing decisions are based only on local knowledge, which allows for fast switching. Our approach does not use any costly virtual channels. As we do not prohibit cyclic dependencies, the routing function provides minimal routing from source to destination even in the presence of faults. We have implemented the architecture design using synthesizable HDL. Using simulations, we have assessed the overhead of our approach in terms of latency, power and area. On average, even with 40% of the links faulty our routing logic is capable performing correctly. Using formal verification, we have proven 100% reliability up to three faults, i.e., for any combination of three faults our routing logic remains connected, deadlock-free and livelock-free.
On the Variability of the Low-Frequency Noise in UTBOX SOI nMOS-FETs
Authors: Simoen Eddy , Andrade Maria G. C. , Almeida Luciano M. , Aoulaiche M. , Caillat C. , Jurczak M. , Claeys Cor 
Published: December 2020

The variability of the low-frequency (LF) noise in n-channel MOSFETs fabricated on an Ultra-Thin Buried Oxide (UTBOX) Silicon-on-Insulator (SOI) substrate has been studied and compared with the variability in the threshold voltage and low-field mobility of the same devices. No correlation has been found between the noise magnitude and the DC parameters, suggesting that the traps responsible for the current fluctuations do not affect the latter. A possible explanation is that the LF noise is dominated by Generation-Recombination (GR) centers in the silicon film, which have less impact on the drain current.
An RF-Powered Temperature Sensor Designed for Biomedical Applications
Authors: Martins Gustavo Campos , Rangel de Sousa Fernando 
Published: December 2020

Continuous patient monitoring enables early detection and treatment of diseases. Small and wireless devices are more comfortable to the patient and simplify the implantation procedure. This paper presents the design and partial testing of an integrated RF-powered temperature sensor suitable for the human body temperature range, from 35 to 42oC. The device was designed using a 130-nm standard CMOS technology and it receives energy from a 900-MHz signal that has power as low as −10 dBm. A calibration method was designed to obtain conversion errors smaller than 0.2oC.
The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime
Authors: Doria Rodrigo T. , Trevisoli Renan D. , De Souza Michelly , Estrada Magali , Cerdeira Antonio , Pavanello Marcelo Antonio 
Published: December 2020

The linearity of Junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature, the doping concentration and the geometry on the overall linearity have been evaluated. The increase of the series resistance associated both to the variation of the physical parameters and the incomplete ionization effect has shown to improve the second order distortion and degrade the third order one.
Ibn-Rushd (Averroes).The Incoherence of the Incoherence. Part Two
Authors: Ibrahim T. , Efremova N. V. 
Published: December 2020

(Translation from Arabic into Russian, intoduction and comments)This series of publications is a translation of selected sections from the book «The Incoherence of the Incoherence» (Tahafut at-Tahafut) of a peripatetic philosopher Ibn Rushd (Averroes, d. 1198), written in response to the book of asharite mutakallim al-Ghazali (d. 1111)«The Incoherence of the Philosophers» (Tahafut al-Falasifa). The first of these sections and the longest one is devoted to the question of the world’s eternity.In this part Ibn Rushd continues examining the first of the two objections raised by al-Ghazali as the main proof for the pre-eternity of God’s creation – «from the complete cause», or, in Ghazaliane wording, «It is impossible that the temporal should proceed from the absolutely eternal». According to this objection, it is the God’s eternal will that predetermined the specific moment when the world came into being.