(Invited) UTBB FDSOI PMOSFETs Including Strained SiGe Channels at the 14nm Technology Node and Beyond
Authors: Andrieu François , Berthelon Remy , Morvan Simeon , Gourhant Olivier , Baylac Elise , Le Royer Cyrille , Dutartre Didier , Josse Emmanuel , Haond Michel 
Published: February 2020

The 28 nm Ultra-Thin Body and Buried Oxide (UTBB) Fully Depleted Silicon-On-Insulator (FDSOI) technology is in production [4]. This technology addresses both high performance and low power / low voltage applications. Indeed, a 28 nm FDSOI Processor (CPU) has been demonstrated to run at 3 GHz for a 1.3 V supply voltage (Vdd), 1 GHz for 0.6 V, still 300 MHz at 0.5 V [1]. This latter result evidences the high potential of FDSOI for Low Voltage operation, required for the next handheld, mobile or Internet-of-Things markets. The 14nm FDSOI technology extends this offer to even more performance (+50% frequency at a given dissipated power), with a 100mV supply voltage reduction [5].
For the 14nm FDSOI, we have integrated SiGe channel, which enables to achieve high biaxial compressive stress due to the lattice mismatch between Silicon and Germanium. The compressive stress enhance the hole mobility, and in turn pMOSFETs performance. In such an approach, one of the main challenges is to conserve the strain during the CMOS integration. Especially, it is well known that the patterning of SiGe leads to partial relaxation close to the active edges. This relaxation affects especially the level of stress in the channel when the dimensions of the active are small. The stress configuration becomes thus strongly layout-dependent.
We have physically and electrically characterized the strain-induced layout effects in SiGe pMOSFETs built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). This layout effect is reproduced by an accurate physics-based electrical model, which enable us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading to +21% effective current increase in short transistor at Lg=20nm gate length and in turn -15% delay reduction for ring-oscillator of 1-gate finger inverters. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Especially, a continuous-RX design, which consists in a long active line configuration, optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage [10]. This demonstrates the interest of process/design co-optimization of strain-induced layout effects.
For next UTBB-FDSOI nodes below 14nm, both the electrostatics and the carrier mobility must be improved. For the hole mobility, one may think about changing the crystalline orientation of the channel and using (110)-oriented substrates. However, in terms of electronic transport, the long channel carrier mobility is no longer the most relevant electrical parameter. One should pay a great attention to i) the strain compatibility and ii) the evolution of the apparent mobility with the gate length and width. Taking them into account, for pMOSFETs, SiGe channel + SiGeB source/drain + compressive contact etch stop layers in the (100) <110> direction is the best combination. For nMOSFETs, different technological solutions have been assessed, especially based on strain memorization techniques [6-7]. Strain-SOI substrates (sSOI) is another option, which brings enough performance boost to ensure a one-node scaling (+20-30% performance increase for nMOSFETs due to tensile strain, even for narrow active regions) [8]. Finally, the gate-last integration on planar FDSOI could be another strain booster because it leverages not only a low thermal budget for EOT and a threshold voltage optimization, but also a strain improvement during the final gate formation [9].
References
[1] D. Jacquet et al., VLSI Technology and Circuit, p. 44, 2013. [2] R. Wilson et al., ISSCC, p. 452-3, 2014. [3] H. Makiyama et al., IEDM, p.822, 2013. [4] N. Planes et al., VLSI Technology, p. 133, 2012. [5] O. Weber et al., VLSI Technology, p. 168-9, 2015. [6] A Bonnevialle et al., SNW, 2015. [7] S. Morvan et al., ULIS, p. 219-22, 2012. [8] F. Andrieu et al., ESSDERC, p.106-9, 2014. [9] S. Morvan et al., IEDM, p. 530-33, 2013. [10] R. Berthelon et al., VLSI Technology, 2016.