High Performance CMOS RF Switch Based on Highly Carbon Doped Raised Source/Drain Regions
Authors: Chollet Antonin , Berbezier Isabelle , Favre Luc , Labrot Maxime , Dura Julien , Melhem Kassem , Duru Romain , Figarols François , Abel Mathieu , Bodnar Sylvie , Bartolotti B. 
Published: December 2024

The demand for high-performance Radio Frequency (RF) switches has rapidly increased in recent years due to the ever-growing demand for wireless communication. Complementary Metal Oxide Semiconductor (CMOS) RF switches are favored for their affordability, energy efficiency, and CMOS process compatibility. However, their performance is compromised by factors like insertion loss, isolation, linearity, and power handling. Enhancing CMOS RF switch performance is vital for advancing high-speed wireless communication and supporting emerging technologies like 5G, IoT, and smart homes [1]. The Figure of Merit (FoM) of a RF switch is a metric used to evaluate the overall performance, combining on-resistance (Ron) and off-capacitance (Coff), with lower values indicating better performance (fig 1). One of the methods used to reduce the Ron of switches is strain engineering of the channel. By growing a material with a different lattice constant than the silicon substrate, we can directly modify the strain of the channel, increase the mobility of the charge carriers (µ) and thus reduce Ron. The strain can be either compressive or tensile, depending on the material chosen. Materials investigated for strain engineering, include silicon-germanium (Si1-xGex), silicon-carbon (Si1-yCy), and silicon-nitride (SiN) [2].
In this paper we will give new insights on a promising strain engineering method based on incorporation of 1% carbon on the Source/Drain regions, induced tensile strained Si channel (fig 2). The process involves Raised Source/Drain (RSD), where a layer of with a high concentration of substitutional carbon (Csub) is selectively grown on top of the silicon. This creates a tensile strained Si channel, improving the mobility of electron carriers and reducing Ron for N-type switch device [3,4]. We decided to selectively grow RSD, resulting in a theoretical 16% gain in current. The thickness of the layer was limited to 40 nm for 1 % Csub, to avoid its relaxation due to the critical thickness [5]. This approach was implemented in a 200 mm Reduced Pressure Chemical Vapor Deposition (RP-CVD) equipment from Applied Materials, using silane (SiH4) and methylsilane (MS) gases. The carbon concentration was determined by SIMS analysis for quantifying the total carbon concentration (Ctot) and XRD to measure the Csub within the layers.
Growth parameters were carefully optimized to increase Csub. First, a compromise between the growth temperature and the growth rate was found around 600°C where 0.82% of Csub was reached (for 1.44% Ctot) while 0.58% of Csub was obtained at 625°C (for 1.26% Ctot). Further increase of Csub up to 1.22% were obtained thanks to the reduction of the H2 carrier gas/total pressure ratio, leading to a rise in the partial pressures of MS and SiH4 (fig 3). We indeed found that reducing the carrier gas debit and increasing the total pressure have a positive impact on the carbon concentration, thanks to the increased growth rate. However, two limitations were shown: (i) the growth rate should not be too fast to avoid the nucleation of extended defects preventing strain engineering; (ii) the thickness range should be reduced to not alter the uniformity of the grown layer (fig 4).
Subsequent steps of the process will involve the RSD selective epitaxy of only on the S/D areas, thanks to the dielectric masking materials around the S/D with Cyclic Deposition Etch process (CDE). The final assessment of this based strain engineering process will be made through electrical and radio frequency characterizations of the CMOS RF SOI (Silicon on Insulator) switch devices.
[1] STMicroelectronics RF-SOI
[2] Maiti C K and Maiti T K 2012 Strain-Engineered MOSFETs (CRC press)
[3] Ang K-W, Balasubramanian N, Samudra G S and Yeo Y-C 2007 Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon–Carbon Source/Drain Regions IEEE Trans. ELECTRON DEVICES 54
[4] Bauer M, Machkaoutsan V, Zhang Y, Weeks D, Spear J, Thomas S G, Verheyen P, Kerner C, Clemente F, Bender H, Shamiryan D, Loo R, Hikavyy I, Hoffmann T, Absil P and Biesemans S 2008 SiCP Selective Epitaxial Growth in Recessed Source/Drain Regions yielding to Drive Current Enhancement in n-channel MOSFET ECS Trans.

[5] Cherkashin N, Hÿtch M, Houdellier F, Hüe F, Paillard V, Claverie A, Gouyé A, Kermarrec O, Rouchon D, Burdin M and Holliger P 2018 On the influence of elastic strain on the accommodation of carbon atoms into substitutional sites in strained Si:C layers grown on Si substrates Appl Phys Lett

Figure 1