Copper Metallization of Nano-through Silicon Vias for Backside Power Delivery Networks
Authors: Tran Anh Van Nhat , Venkataraman Nandini , Tseng Ya-Ching , Varghese Binni , Singh Navab 
Published: December 2024

I. Introduction

Backside power delivery networks (BS-PDNs) represents an exciting technological concept that has been steadily advancing over the past few years, particularly in the integration of leading-edge nodes. With BS-PDN approaches, the entire power network is migrated to the backside of the wafer, eliminating interference, and allowing more area for signal routing on the frontside. In addition, the route for power delivery to transistor is shorter and more direct, resulting in reduction by 30% in IR drop1.
Nano-Through Silicon Vias (n-TSVs) is one of the key enabling processes for BS-PDN integration1-4. The application of n-TSVs enhances the interconnect packing density, potentially increase the efficiency of power delivery up to 7 times compared to frontside power delivery, based on the simulation studies conducted by Arm and Imec5. The scaling down of TSV diameter to 200 nm brings challenges in fabrication process steps such as wafer thinning and metallization. To maintain the aspect ratio between 3 and 5 for reliable n-TSVs etch and filling processes, Si substrate must be thinned down to below 1µm6. Cu is one of the options for the filling of n-TSVs. However, significant challenges exist in Cu metallization of high aspect ratio n-TSVs (diameter <200 nm, aspect ratio 3-5). These include poor Cu seed sidewall coverage and overhang at via entrance with conventional physical vapor deposition (PVD) setups, as well as fill voids during electroplating (ECP) in structures with aspect ratio >3 due to limited additive diffusion into the nano features. In this paper, we will co-optimize PVD and ECP processes to achieve robust void-free Cu metallization of n-TSVs.

II. Experimental

250x760 nm n-TSVs with pattern density approximately 1% were fabricated on 300mm silicon wafers. Immersion lithography was employed for pattern definition, followed by plasma dry etching on 760nm oxide/silicon/oxide stack, to mimic typical n-TSVs film structure. Subsequently, Al2O3 passivating dielectric and Ta barrier/Cu seed deposition by atomic layer deposition (ALD) and PVD, respectively. To enhance the Cu seed coverage, bias conditions during PVD process were investigated.
Copper electroplating was conducted in AMAT-Nokota platform using a commercially available acidic copper electrolyte. To gain insights into copper filling mechanism of n-TSVs, ECP process was conducted at different conditions with varying current densities, agitation, and pulse current waveforms. The n-TSVs copper filling was characterized using cross-sectional focused ion beam transmission electron microscopy (FIB-TEM).

III. Results

Fig. 1 shows a cross-sectional TEM image illustrating n-TSVs filling under baseline condition. There are systematic voids at the center, throughout the top-half of the n-TSVs. These seam voids might be due to the poor diffusion of additives to nano scale features, leading to sub-conformal plating configuration, resulting in pinch off voids near the top of n-TSVs. To facilitate the diffusion and adsorption of appropriate additives towards n-TSVs, periodic pulse current waveforms are applied. Besides the enhancement of additive diffusion during pulse off-time, high peak current pulsing results in higher overpotential deposition which promotes copper nucleation. In addition, the average current density is reduced by 20% to allow sufficient replenishment of copper ions inside the n-TSVs.
Apart from the center voids at the top region of the vias, there are voids along the sidewalls around the Si layer due to poor Cu seed coverage. To improve the Cu seed coverage, the wafer bias during PVD process is modulated. The increase in bias condition is beneficial not only for the continuous Cu seed at sidewalls, but also to reduce overhang at the top of the vias. With the approach of high bias PVD, via opening CD is larger, allowing better additive and copper ion diffusion during electroplating.
Fig. 2 shows a cross-sectional TEM image representing n-TSVs filling under optimized condition. Void-free filling is achieved with the co-optimization of PVD and ECP processes. The details will be discussed in the full paper.

IV. Novelty

This work demonstrates a robust void-free Cu metallization for n-TSVs which is important for the integration and fabrication of backside power delivery networks.

V. References

Hafez et al., 2023 IEEE Symposium on VLSI Technology and Circuits, p. 1-2 (2023).

Veloso et al., 2021 Symposium on VLSI Technology, p. 1-2 (2021).

Veloso et al., IEEE Transactions on Electron Devices,
69, p. 7173–7179, (2022).

Anne Jourdain et al., IEEE Electronic Components and Technology Conf., p. 1531-1538 (2022).

Cline, D. Presaderic, E. Beyne, O. Zografos, “Next-Gen Chips Will Be Powered from Below,” IEEE Spectrum, (2021).

Anne Jourdain et al., Proc. IEEE Electronic Components and Technology Conf., p. 42-48 (2020).

Figure 1