bluuebunny/crossref_metadata_2025_split huggingface dataset:
The Human Longevity Record May Hold for Decades: Jeanne Calment’s Extraordinary Record Is Not Evidence for an Upper Limit to Human Lifespan
Authors: Lenart Adam , Aburto José Manuel , Stockmarr Anders , Vaupel James W. 
Published: December 2020

AbstractSince 1990 Jeanne Louise Calment has held the record for human longevity. She was born on 21 February 1875, became the longest-lived human on 12 May 1990 when she was 115.21 and died on 4 August 1997 at age 122.45 years. In this chapter, we use data available on 25 September 2017 on people who reached age 110, supercentenarians, to address the following questions:

How likely is it that a person has reached age 122.45?

How unlikely is it that Calment’s record has not yet been broken?

How soon might it be broken?

Assuming a constant annual probability of death of 50% after age 110, we found that the probability that a person who survived to age 110 would have lived to 122.45 by 25 September 2017 is 17.1%. Furthermore, we calculated that there was only a 20.3% chance that Calment’s record would have been broken after 1997 but before 2017. Finally, we estimated that there is less than a 50% chance that someone will surpass Calment’s lifespan before 2045. Jeanne Louise Calment’s record is exceptional but not impossible. It does not provide evidence that her lifespan is an upper limit to human lifespans.
RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience
Authors: Herkersdorf Andreas , Engel Michael , Glaß Michael , Henkel Jörg , Kleeberger Veit B. , Kühn Johannes M. , Marwedel Peter , Mueller-Gritschneder Daniel , Nassif Sani R. , Rehman Semeen , Rosenstiel Wolfgang , Schlichtmann Ulf , Shafique Muhammad , Teich Jürgen , Wehn Norbert , Weis Christian 
Published: December 2020

AbstractThe Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron CMOS technologies at the semiconductor material or device levels. RAP assumes that each of such physical faults will eventually manifest as a single- or multi-bit binary signal inversion or out-of-specification delay in a signal transition between bit values. When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, finite state machine (FSM) states, IP macro-interfaces, or software variables. Thus, design concerns can be investigated at higher abstraction layers without the necessity to further consider the full details of lower levels of design. This chapter introduces the ideas of RAP based on examples of particle strike, noise and voltage drop induced bit errors in SRAM cells. Furthermore, we show by different examples how probabilistic bit flips are systematically abstracted and propagated towards instruction and data vulnerability at MPSoC architecture level, and how RAP can be applied for dynamic testing and application-level optimizations in an autonomous robot scenario.
Resource Management for Improving Overall Reliability of Multi-Processor Systems-on-Chip
Authors: Ma Yue , Zhou Junlong , Chantem Thidapat , Dick Robert P. , Hu X. Sharon 
Published: December 2020

AbstractMulti-processor systems on a chip (MPSoCs) are widely deployed in real-time embedded systems. In such systems, soft-error reliability (caused by transient faults) and lifetime reliability (caused by permanent faults) are both imperative design concerns. Most existing work considers only one of the two classes of faults. Unfortunately, techniques that increase one may adversely impact the other. Achieving high overall reliability requires a trade-off of soft-error reliability and lifetime reliability. In this chapter, we first introduce concepts and models associated with the two reliability metrics, then present two techniques that optimize them separately. Finally, we show how to make appropriate trade-offs using two case studies involving “big–little” type MPSoCs and CPU–GPU integrated MPSoCs.
Cross-Layer Resilience Against Soft Errors: Key Insights
Authors: Mueller-Gritschneder Daniel , Cheng Eric , Sharif Uzair , Kleeberger Veit , Bose Pradip , Mitra Subhasish , Schlichtmann Ulf 
Published: December 2020

AbstractDriven by technology scaling, integrated systems become more susceptible to various causes of random hardware faults such as radiation-induced soft errors. Such soft errors may cause malfunction of the system due to corruption of data or control flow, which may lead to unacceptable risks for life or property in safety-critical applications. Hence, safety-critical systems deploy protection techniques such as hardening and redundancy at different layers of the system stack (circuit, logic, architecture, OS/schedule, compiler, software, algorithm) to improve resiliency against soft errors. Here, cross-layer resilience techniques aim at finding lower cost solutions by providing accurate estimation of soft error resilience combined with a systematic exploration of protection techniques that work collaboratively across the system stack. This chapter demonstrates how to apply the cross-layer resilience principle on custom processors, fixed-hardware processors, accelerators, and SRAM memories (with a focus on soft errors) and presents key insights obtained.
Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures
Authors: Bauer Lars , Zhang Hongyan , Kochte Michael A. , Schneider Eric , Wunderlich Hans-Joachim , Henkel Jörg 
Published: December 2020

AbstractRuntime/reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are a promising augment to conventional processor architectures such as Central Processing Units (CPUs) and Graphic Processing Units (GPUs). Since the reconfigurable parts are typically manufactured in the latest technology, they may suffer from aging and environmentally induced dependability threats. In this chapter, strategic online test methods for dependable runtime-reconfigurable architectures as well as cross-layer optimizations for high reliability and lifetime are developed. Firstly, two orthogonal online tests are proposed that ensure reliable configuration of the reconfigurable fabric and aid fault detection. Secondly, a novel design method called module diversification is presented that enables self-repair of the system in case of faults caused by degradation effects as well as single-event upsets in the configuration. Thirdly, a novel stress-aware placement method is proposed that aims for slowing down system degradation by aging effects. The combined methods ensure reliable operation across architectural and gate level and allow to prolong the lifetime of dependable runtime-reconfigurable architectures.
Uncertainty-Aware Compositional System-Level Reliability Analysis
Authors: Aliee Hananeh , Glaß Michael , Khosravi Faramarz , Teich Jürgen 
Published: December 2020

AbstractContinuous technology scaling has increased the susceptibility of today’s electronic devices to manufacturing tolerances and environmental changes. The resulting uncertainty in component reliability can be only approximated or estimated at design time and might propagate to system level. Therefore, uncertainty must be considered to enable the design of robust systems. In this chapter, we propose a methodology for cross-level reliability analysis to tame the ever increasing analysis complexity of contemporary systems under the influence of uncertainties. The presented methodology combines various reliability analysis techniques across different levels of abstraction while providing an explicit modeling of uncertainties. It introduces mechanisms for (a) the composition and decomposition of the system during analysis and (b) converting analysis data between different levels of abstraction through adapters. The developed analysis techniques are integrated in an automatic electronic system-level reliability analysis tool to allow for the evaluation of reliability-increasing techniques and for DSE!. The tool thereby uses meta-heuristic algorithms for optimization and enables the comparison of system implementation candidates with objectives represented by uncertainty distributions.
Soft Error Handling for Embedded Systems using Compiler-OS Interaction
Authors: Engel Michael , Marwedel Peter 
Published: December 2020

AbstractAdvancing semiconductor technologies increasingly fail to provide expected gains in cost and energy reductions due to reaching the physical limits of Moore’s Law and Dennard scaling. Instead, shrinking semiconductor feature sizes increase a circuit’s susceptibility to soft errors. In order to ensure reliable operation, a significant hardware overhead would be required.The FEHLER project (Flexible Error Handling for Embedded Real-Time Systems) introduces error semantics into the software development process which provide a system with information about the criticality of a given data object to soft errors. Using this information, the overhead required for error correction can be reduced significantly for many applications, since only errors affecting critical data have to be corrected.In this chapter, the fundamental components of FEHLER that cooperate at design and runtime of an embedded system are presented. These include static compiler analyses and transformations as well as a fault-aware microkernel. Using examples of typical embedded applications, the efficiency of the approach is demonstrated, along with an extension towards approximate computing systems.
Robust Computing for Machine Learning-Based Systems
Authors: Hanif Muhammad Abdullah , Khalid Faiq , Putra Rachmad Vidya Wicaksana , Teimoori Mohammad Taghi , Kriebel Florian , Zhang Jeff (Jun) , Liu Kang , Rehman Semeen , Theocharides Theocharis , Artusi Alessandro , Garg Siddharth , Shafique Muhammad 
Published: December 2020

AbstractThe drive for automation and constant monitoring has led to rapid development in the field of Machine Learning (ML). The high accuracy offered by the state-of-the-art ML algorithms like Deep Neural Networks (DNNs) has paved the way for these algorithms to being used even in the emerging safety-critical applications, e.g., autonomous driving and smart healthcare. However, these applications require assurance about the functionality of the underlying systems/algorithms. Therefore, the robustness of these ML algorithms to different reliability and security threats has to be thoroughly studied and mechanisms/methodologies have to be designed which result in increased inherent resilience of these ML algorithms. Since traditional reliability measures like spatial and temporal redundancy are costly, they may not be feasible for DNN-based ML systems which are already super computer and memory intensive. Hence, new robustness methods for ML systems are required. Towards this, in this chapter, we present our analyses illustrating the impact of different reliability and security vulnerabilities on the accuracy of DNNs. We also discuss techniques that can be employed to design ML algorithms such that they are inherently resilient to reliability and security threats. Towards the end, the chapter provides open research challenges and further research opportunities.
Hardware/Software Codesign for Energy Efficiency and Robustness: From Error-Tolerant Computing to Approximate Computing
Authors: Rahimi Abbas , Gupta Rajesh K. 
Published: December 2020

AbstractVoltage scaling, as the most important knob for energy efficiency, is limited by leakage and variability. Variability is arisen from various sources including static manufacturing process, dynamic voltage and temperature fluctuations, and temporal changes over time. To address these variations, designers resort to excessive margins. These margins are increasing rapidly and eventually obliterating any gains due to device scaling. As a consequence, reduction of margins in design has become an important research challenge. We demonstrate how to recover part of these margins through hardware/software codesign with examples in many-core GPUs and FPGAs. This naturally leads to a departure from traditional error-tolerant computing to approximate computing.
Reliable CPS Design for Unreliable Hardware Platforms
Authors: Chang Wanli , Narayanaswamy Swaminathan , Pröbstl Alma , Chakraborty Samarjit 
Published: December 2020

AbstractToday, many battery-operated cyber-physical systems (CPS) ranging from domestic robots, to drones, and electric vehicles are highly software-intensive. The software in such systems involves multiple feedback control loops that implement different functionality. How these control loops are designed is closely related to both the semiconductor aging of the processors on which the software is run and also the aging of the batteries in these systems. For example, sudden acceleration in an electric vehicle can negatively impact the health of the vehicle’s battery. On the other hand, processors age over time and stress, impacting the execution of control algorithms and thus the control performance. With increasing semiconductor scaling, and our increasing reliance on battery-operated devices, these aging effects are of concern for the lifetime of these devices. Traditionally, the design of the control loops focused only on control-theoretic metrics, related to stability and performance (such as peak overshoot or settling time). In this chapter we show that such controller design techniques that are oblivious of the characteristics of the hardware implementation platform dramatically worsen the battery behaviour and violate the safety requirement with processor aging. However, with proper controller design these effects can be mitigated—thereby improving the lifetime of the devices.
Our Perspectives
Authors: Chen Jian-Jia , Henkel Joerg 
Published: December 2020

AbstractResearch and development in the last decades have led to a silicon process that has been expected to become inherently undependable in the near future when migrating towards new technologies. The special priority program (SPP) 1500 funded by the German Research Foundation (Deutsche Forschungsgemeinschaft, DFG) in 2010–2016 and the Variability Expedition funded by the National Science Foundation (NSF) in 2010–2015 made a joint effort to explore design challenges of Power Consumption, Reliability, Interference, and Manufacturability under such a design requirement.
ASTEROID and the Replica-Aware Co-scheduling for Mixed-Criticality
Authors: Rambo Eberle A. , Ernst Rolf 
Published: December 2020

AbstractThe ASTEROID project developed a cross-layer fault-tolerance solution to provide reliable software execution on unreliable hardware under soft errors. The approach is based on replicated software execution with hardware support for error detection that exploits future many-core platforms to increase reliability without resorting to redundancy in hardware. This chapter gives an overview of ASTEROID and then focuses on the performance of replicated execution and the proposed replica-aware co-scheduling for mixed-criticality. The performance of systems with replicated execution strongly depends on the scheduling. Standard schedulers, such as Partitioned Strict Priority Preemptive (SPP) and Time-Division Multiplexing (TDM)-based ones, although widely employed, provide poor performance in face of replicated execution. By exploiting co-scheduling, the replica-aware co-scheduling is able to achieve superior performance.
Dependability Aspects in Configurable Embedded Operating Systems
Authors: Schirmeier Horst , Borchert Christoph , Hoffmann Martin , Dietrich Christian , Martens Arthur , Kapitza Rüdiger , Lohmann Daniel , Spinczyk Olaf 
Published: December 2020

AbstractAs all conceptual layers in the software stack depend on the operating system (OS) to reliably provide resource-management services and isolation, it can be considered the “reliable computing base” that must be hardened for correct operation under fault models such as transient hardware faults in the memory hierarchy. In this chapter, we approach the problem of system-software hardening in three complementary scenarios. (1) We address the following research question: Where do the general reliability limits of static system-software stacks lie, if designed from scratch with reliability as a first-class design goal? In order to reduce the proverbial “attack surface” as far as possible, we harness static application knowledge from an AUTOSAR-compliant task set, and protect the whole OS kernel with AN-encoding. This static approach yields an extremely reliable software system, but is constrained to specific application domains. (2) We investigate how reliable a dynamic COTS embedded OS can become if hardened with programming-language and compiler-based fault-tolerance techniques. We show that aspect-oriented programming is an appropriate means to encapsulate generic software-implemented hardware fault tolerance mechanisms that can be application-specifically applied to a selection of OS components. (3) We examine how system-software stacks can survive even more adverse fault models like whole-system outages, using emerging persistent memory (PM) technology as a vehicle for state conservation. Our findings include that software transactional memory facilitates maintaining consistent state within PM and allows fast recovery.
Fault-Tolerant Computing with Heterogeneous Hardening Modes
Authors: Kriebel Florian , Khalid Faiq , Prabakaran Bharath Srinivas , Rehman Semeen , Shafique Muhammad 
Published: December 2020

AbstractFault-tolerance using (full-scale) redundancy-based techniques has been employed to detect and correct reliability errors (i.e., soft errors), but they pose significant area and power overhead. On the other hand, due to the masking and the error tolerance properties at different system layers and of different applications, respectively, reliable heterogeneous architectures have been emerged as an attractive design choice for power-efficient dependable computing platforms. This chapter discusses the building blocks of such computing systems, based on both embedded and superscalar processors, with different reliability (fault-tolerant) modes at the architecture layer to memories like caches, for heterogeneous in-order and out-of-order processors. We provide a comprehensive reliability, i.e., soft error, vulnerability analysis of different components in in-order and out-of-order processors, e.g., caches. We also discuss different methodologies to improve the performance and power of such a system by analyzing these vulnerabilities. Moreover, we show how such heterogeneous hardware-level hardening modes can further be complemented by software-level techniques that can be realized using a reliability-driven compiler (as introduced in Chapter “Dependable Software Generation and Execution on Embedded Systems”).
Thermal Management and Communication Virtualization for Reliability Optimization in MPSoCs
Authors: van Santen Victor M. , Amrouch Hussam , Wild Thomas , Henkel Jörg , Herkersdorf Andreas 
Published: December 2020

AbstractThis chapter covers the interdependencies of temperature and the reliable operation of multiprocessor systems on chip (MPSoC). Starting with the assessment of temperature values for the different cores either through measurement or estimation, it is shown which methods on system level can be applied to balance the thermal stress in the system and thus to come to an evenly distributed probability of errors. Special focus is given to task migration as a system-level means, which is supported by an on-chip interconnect virtualization technique that eases fast and transparent switch-over of communication channels. Overall, it is shown how mechanisms on different levels of the system stack can be combined to cooperate across layers for improving system reliability.
Lightweight Software-Defined Error Correction for Memories
Authors: Alam Irina , Dolecek Lara , Gupta Puneet 
Published: December 2020

AbstractReliability of the memory subsystem is a growing concern in computer architecture and system design. From on-chip embedded memories in Internet-of-Things (IoT) devices and on-chip caches to off-chip main memories, the memory subsystems have become the limiting factor in the overall reliability of computing systems. This is because they are primarily designed to maximize bit storage density; this makes memories particularly sensitive to manufacturing process variation, environmental operating conditions, and aging-induced wearout. This chapter of the book focuses on software managed techniques and novel error correction codes to opportunistically cope with memory errors whenever they occur for improved reliability at minimal cost.
Introduction
Authors: Vankova Zvezda 
Published: December 2020

AbstractThe policy idea of facilitating circular migration entered the European Union’s agenda more than a decade ago as part of a worldwide buzz among international organisations that it could provide a ‘triple win solution’ that would benefit all: the countries of origin and destination as well as the migrant workers themselves. According to the European Commission’s vision, this type of migration was to be facilitated in such a way as to allow some degree of legal mobility for migrants between two countries. Chapter 1 aims to introduce the understanding of this concept in the EU context and to set the scene for the book to unfold.
The Formulation of the EU’s Approach to Circular Migration
Authors: Vankova Zvezda 
Published: December 2020

AbstractThis chapter presents the process of the formulation of the circular migration approach at the European level. It examines the genesis of the circular migration concept in the EU’s migration policy by discussing the main policy developments and legal acts adopted since the Tampere programme as well as by analysing the interviews concluded with EU and international actors that have had a bearing on the topic. In doing so it outlines the formulation of a two-fold approach towards the facilitation of circular migration at the EU level, incorporating legal migration directives and policy initiatives developed under the auspices of the Global Approach to Migration and Development (GAMM).
The Implementation of the EU’s Approach to Circular Migration Through Legal and Policy Routes
Authors: Vankova Zvezda 
Published: December 2020

AbstractThis chapter brings together the legal and policy instruments developed as part of the EU’s circular migration approach in order to assess its implementation and establish whether it provides rights-based outcomes for migrant workers. In order to do so, it employs a benchmark framework for analysis based on universal and regional international standards and soft law principles as well as policy measures that have been identified as conducive to circular migration (presented in Chap.1). The benchmark framework covers six policy areas considered inherent to this type of labour migration and which at the same time could help distinguish circular migration from the guest-worker model and other time-bound migration policies: entry and re-entry conditions, work authorisation, residence status, social security coordination, entry and residence conditions for family members, and recognition of qualifications. To be beneficial for migrant workers, policies need to allow for a certain degree of migrant-led trajectory of movement and provide adequate protection of the rights of migrant workers.