Atomistic Structure of Low-Resistance Si/GaAs Heterointerfaces Fabricated By Surface-Activated Bonding at Room Temperature
Authors: Ohno Yutaka , Yoshida Hideto , Takeda Seiji , Liang Jianbo , Shigekawa Naoteru 
Published: February 2020

Tandem solar cells consisting of silicon (Si) and III-V compounds are one of the promising candidates for next-generation terrestrial photovoltaic systems, that can surpass the efficiency milestone of 30% for non-concentrating solar cells without using expensive Ge or GaAs substrates. Recently, the surface-activated bonding (SAB) at room temperature (RT), in which surfaces of substrates are activated before bonding by creating dangling bonds via the removal of contaminants under an energetic particle bombardment in high vacuum, is applied to form Si/GaAs heterointerfaces for hybrid triple-junction cells with a high conversion efficiency above 26% [1]. Even though the interface resistance (~100 Wcm2) is low enough for solar cells, it is still higher than the ideal one at defect-free heterointerfaces (~10-4 Wcm2). Accordingly, a comprehensive knowledge of the electrical property at the heterointerfaces depending on their atomistic structure is indispensable to establish the fabrication processes of high-efficiency tandem cells by optimizing the interface structure.
In the present work, p-Si/n-GaAs heterointerfaces were fabricated at RT under a SAB condition [1], with the substrates of B-doped (100) p-Si (with a carrier concentration of 2x1014 cm-3) and Si-doped (100) n-GaAs (2x1016 cm-3) which was 5o off from (100) toward [011]. A part of them were then annealed at 673 K for 1 min. Their structural properties were determined by plane-view transmission electron microscopy (TEM) (Fig. 1), as well as cross-sectional scanning TEM (STEM). As-bonded heterointerfaces included an As-deficient crystalline GaAs layer less than about 1 nm thick and an amorphous Si layer about 3 nm thick [2]. Dimples were introduced on the whole GaAs surface at the bonding heterointerface (Fig. 1d), presumably via the introduction of As vacancies during the surface activation process, and they disappeared after 673 K annealing. The density in the amorphous Si layer was slightly lower than in the conventional amorphous Si, presumably due to the introduction of Si vacancies during the surface activation process, and it was increased by 673 K annealing. Those structural changes would result in the reduction of the resistance at the bonded Si/GaAs heterointerfaces [3]. On the other hand, dislocations in GaAs cropping out the heterointerfaces induce large strains at the interfaces (indicated with the arrows in Figs. 1a and 1b), and they would increase the interface resistance even after annealing. Therefore, the resistance should be reduced by suppressing those interface defects, via the optimization of SAB conditions with a defect-free GaAs substrate. In order to confirm the hypothesis, the electronic property of the defects was examined by cathodoluminescence (CL) spectroscopy in a transmission electron microscope. The relationship of the defects and the interface resistance will be discussed in the conference.
References: [1] N. Shigekawa, et al., Jpn. J. Appl. Phys. 54 (2015) 08KE03; [2] Y. Ohno, et al., Jpn. J. Appl. Phys. 57 (2018) 02BA01; [3] J. Liang, et al., Jpn. J. Appl. Phys. 54 (2015) 030211.
Acknowledgments: This work was supported by the "Research and development of ultra-high efficiency and low-cost III–V compound semiconductor solar cell modules (High efficiency and low-cost III–V/Si tandem)" project of NEDO and by JSPS KAKENHI Grant Number 15H03535 (2015–2018). Cross-sectional STEM was performed at ISIR under the Cooperative Research Program of "Network Joint Research Center for Materials and Devices: Dynamic Alliance for Open Innovation Bridging Human, Environment and Materials".
Figure caption: Plane-view dark-field images of crystalline (a) GaAs and (b) Si at a Si/GaAs heterointerface taken with the (220) reflection for GaAs and Si, respectively. The inset in (a) shows transmission electron diffraction obtained with the incident direction nearly normal to the interface. (c and d) Plane-view bright-field images of the interface taken with both the (2-20) reflections for Si and GaAs; due to (c) a dislocation in GaAs cropping out the interface and (d) dimples on the GaAs surface. The inset in (c) indicates the calculated hydrostatic stress field for dislocations in GaAs.

Figure 1