bluuebunny/crossref_metadata_2025_split huggingface dataset:
Annealing Effects on the Electrical Activation of Si Dopants in InGaAs
Authors: Lind Aaron Gregg , Aldridge Henry Lee , Bomberger Cory Carl , Hatem Chris , Zide Joshua M. O. , Jones Kevin Scott 
Published: February 2020

There is a renewed interest in integrating high mobility III-V channel materials into sub 10 nm nMOS devices but the continued scaling of devices has resulted in the need to create contacts and source/drains with ultra low contact resistivities in order to reduce current losses. This study investigates thermal stability of Si dopants incorporated via MBE growth and ion implantation as potential methods to create heavily-doped, low resistance source/drain regions in III-V channel devices. For this study, the electrical activation and diffusion of Si active layers in In0.53Ga0.47As formed by a 10 keV, 5×1014 cm-2 Si implant and MBE growth doping with a peak Si concentration of 7×1019 cm-3 were investigated as a function of post growth and post-implant isochronal annealing. While most previous studies conclude that MBE doping can achieve higher active Si concentrations than ion implantation, the results of this study show conclusively that electrically active Si concentrations above 1.4×1019 cm-3 formed by MBE doping are prone to deactivation upon thermal treatment after growth whereas ion-implantation shows no metastable activation behavior. Significant Si deactivation in MBE doped substrates is shown to occur before the onset of Si diffusion whereas saturated activation in ion implanted substrates does not occur until diffusion is observed. Upon annealing at sufficiently high temperatures to cause Si diffusion, the electrical activation of Si in MBE doped substrates and ion implanted Si are shown to converge to a stable activation limit of 1.4×1019 cm-3. The common activation limit upon Si profile motion for both Ion implanted and growth doped Si active layers after thermal annealing at 750°C suggests that the maximum stable electrical activation of Si is an intrinsic property of In0.53Ga0.47As. Si diffusivity has also been calculated from SIMS results in both ion-implanted substrates and growth-doped substrate and Si diffusion in MBE doped substrates was observed to be nearly three times as fast as ion implanted substrates presumably due to the observed concentration dependent diffusion effects. The mechanism of Si diffusion and its relation to the observed concentration dependent diffusion and electrical activation behavior in both materials are also discussed.

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Invited: Approaches to the Formation and Integration of Large Lattice Mismatched Materials: Metamorphic and Non-Conventional 'buffer' Layers
Authors: Kuech Thomas F , Babcock Susan E , Mawst Luke J , Wood Adam , Kim Tae Won , Rajeev Ayushi , Schulte Kevin , Guan Yingxin 
Published: February 2020

The growth of large lattice mismatched materials has been studied for many years in order to understand mismatch-derived defects, their mode of introduction, and their mitigation. Traditional approaches focused on the formation of ‘buffer’ layers. ‘Buffer’ layers are intermediate layers within a growing structure which allow a chemical or structural transition between two epitaxial materials. The choice and design of these layers depend critically on the nature of the material transition. Controllably varying the composition across the buffer layer has been the approach most often used in this context. As the composition is graded from the substrate or a lattice matched compound to the substrate to a material which has the desired lattice parameter, the structurally required mismatch dislocations are introduced with a minimum of residual threading dislocations.
The approach of transitional or graded layers has undergone continual development with new effects being realized which can reduce the buffer layer thickness and achieve the dislocation density desired for growth of device layers. Composition grading in compound semiconductors can be accomplished by the change in the cation composition, as in the grading of InxGa1-xAs to transition from GaAs to InAs, or on the anion sublattice using InAsyP1-y to transition from InP to InAs. Often these graded layers are too rough to use in device applications due to the presence of a surface cross-hatch derived from the introduction of mismatch dislocations. Chemical-mechanical polishing has offered a means to recover the required planar surface. There are alternative approaches to graded buffer layers which are beginning to be studied and utilized. The intent of all these approaches is to generate the required misfit dislocations, have them reside at an appropriate interface and, finally, leave no threading dislocation line segments residing within the device layer. A self-assembled block co-polymer approach to nanoscale patterning, which offers rapid and cost-effective full wafer patterning at the 20-nm length scale, was used to achieve improvements in heteroepitaxial growth of large lattice mismatched materials. The x-ray spectra taken from a 600-nm or less thickness GaSb film grown on a patterned GaAs substrate show a sharp reduction in the full width at half maximum (FWHM). The FWHM of the GaSb peak in this initial study was reduced by at least a factor of two as compared to the film grown to the same thickness on a non-patterned wafer. A reduction of this magnitude is extremely significant for films of this thickness. This improvement in materials properties through nano-patterned growth should be applicable to a wide range of materials and lattice mismatch situations. Views on the strengths, challenges, similarities and applicability of these various approaches will be presented.
Continuum Modelling of Silicon Diffusion and Activation in in0.53Ga0.47As
Authors: Aldridge Henry Lee , Lind Aaron Gregg , Law Mark E , Hatem Chris , Jones Kevin Scott 
Published: February 2020

There is significant research interest in the behavior of silicon as a dopant in InGaAs during processing conditions for possible integration into future CMOS devices. A major objective is obtaining low resistances for source and drain regions, which require very high doping concentrations near the limits of solid solubility (>1×1020cm-3). Understanding dopant behavior and activation near these limits are of paramount importance in order to fully integrate InGaAs and related III-V materials into systems previously dominated by silicon.
In this work, a Si diffusion and activation model in In0.53Ga0.47As using the Florida Object Oriented Process and Device Simulator (FLOOXS) will be presented. Similar to previous studies in GaAs, the group-III vacancy-Si pair is implemented as the principle mechanism for silicon diffusion in InGaAs. Fermi level considerations concerning concentration-dependent diffusion are also taken into account in the presented model, building upon simpler previous models.
Experimental studies that provided the data include Si-implanted InGaAs samples and MBE-grown delta-doped layers of Si in InGaAs. Both sets of samples were capped with Al2O3 and annealed at temperatures ranging from 550 to 750°C. As indicated through SIMS data, post annealed profiles for silicon exhibit very sharp shoulders characteristic of concentration dependent diffusion. The extracted power of concentration dependence from the SIMS results are relatively high (greater than n=4). This sharp dependence differs from prior continuum-based modelling procedures, where power dependence is believed to closely correspond to the charge state of defects responsible for diffusion. Ultimately the connection between diffusion and activation will be explored, along with developments in prediction and modelling.

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(Invited) Fabrication and Applications of High-Efficiency, Lightweight, Multi-Junction Solar Cells by Epitaxial Liftoff
Authors: Elarde Victor Christopher , Miyamoto Haruki , Chan Ray , Stender Chris , Youtsey Chris , Adams Jessica G J , Wibowo Andree , Tatavarti Rao , Osowski Mark , Pan Noren 
Published: February 2020

MicroLink Devices has developed an epitaxial liftoff (ELO) technology for removing thin device layers from the surface of a semiconductor wafer using a flexible metallic sheet to provide structural support. The wafer is left intact and available for use in a subsequent growth cycle. This technology has been applied to high-efficiency, multi-junction solar cells. Removal of the substrate allows the devices to achieve very high specific power of approximately 1000W/kg. For large area devices, the cost of the substrate can be a significant component of the overall device manufacturing cost. By utilizing ELO technology to reuse the substrate for multiple growth cycles, the manufacturing cost of the device can be dramatically reduced. A flexible solar cell fabricated using ELO is shown in Figure 1.
Lightweight, flexible, high-efficiency solar cells have a broad range of applications in both space and terrestrial markets. MicroLink has demonstrated the use of these devices to extend the flight time of electric unmanned aerial vehicles (UAVs). The lightweight and flexible solar cells can be embedded in the wings of the vehicle, adding only minimal weight and conforming to the flight surfaces to avoid introducing addition drag. Figure 2 contains an image of a Raven UAV with MicroLink’s lightweight flexible solar cells integrated into the surface of the wings. The solar array contributes an additional 40W of power to the aircraft under typical operating conditions leading to a 62% increase in flight time.
MicroLink has also demonstrated a Mobile Solar Power (MSP) panel designed for use by soldiers in the field which is capable of recharging a standard issue BB-2590 battery. This panel is shown in Figure 3 lying on top of a conventional CIGS panel. MicroLink’s MSP panel dramatically reduces the size of the panel, allowing it to be used on-the-go. This panel has demonstrated a specific power of 117W/kg, more than double the specific power of CIGS based panels (typically 43W/kg).
By reducing the weight and cost of high-efficiency photovoltaic devices, MicroLink’s novel approach to device fabrication allows for a wide array of previously impractical applications of solar power.

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(Invited) InAs/InAs1-XSbx Type-II Superlattices for High-Performance Long-Wavelength Infrared Medical Thermography
Authors: Razeghi Manijeh , Haddadi Abbas , Chen Guanxi , Chevallier Romain , Hoang Ahn Minh 
Published: February 2020

After being proposed by Sai-Halasz et al. in 1977, type-II superlattices (T2SLs) have demonstrated themselves as a very important material system in various fields such as lasers, photodetectors and transistors. In the field of infrared detection and imaging, InAs/GaSb T2SLs have become a viable candidate to compete with the state-of-the-art mercury-cadmium-telluride (MCT) compounds material system. By spatially separating electrons and holes into different quantum wells, the type-II band alignment enables the full control of the electronic bandstructure and thus, allows for great flexibility in hetero-structure device designs. Beside InAs/GaSb type-II superlattices, InAs/InAs1-xSbxT2SLs have been proved to have a longer carrier lifetime than InAs/GaSb T2SLs and have been proposed as an alternative for infrared photodetectors.
We report demonstration of a high performance long-wavelength infrared nBn photodetectors based on InAs/InAs1-xSbx type-II superlattices on GaSb substrate. The photodetector’s 50% cut-off wavelength was ~10 mm at 77K. The photodetector with a 6 mm-thick absorption region exhibited a peak responsivity of 4.47 A/W at 7.9 mm, corresponding to a quantum efficiency of 54% at -90 mV bias voltage under front-side illumination and without any anti-reflection coating. With an R×A of 119 Ω·cm2 and a dark current density of 4.4×10-4 A/cm2 under -90 mV applied bias at 77 K, the photodetector exhibited a specific detectivity of 2.8×1011 cm./W.
(Invited) Synchrotron White-Beam X-Ray Topography Analysis of the Defect Structure of HVPE-GaN Substrates
Authors: Kirste Lutz , Danilewsky Andreas N. , Sochacki Tomasz , Köhler Klaus , Zajac Marcin , Kucharski Robert , Boćkowski Michal , McNally Patrick J. 
Published: February 2020

For demanding GaN-based applications like laser diodes or high mobility transistors there is a need for substrate material with low defect densities, since threading dislocations act as centers of non-radiative recombination, increasing the leakage current, reducing the room temperature mobility and thereby limiting the efficiency, performance and lifetime of devices. Hydride vapor-phase epitaxy (HVPE) is the most common technique for the growth of large area freestanding GaN wafers with diameters up to 50 mm and a threading dislocation density below 107 cm−2. An alternative technique with great potential for the growth of GaN bulk crystals is the ammonothermal growth method. For this method GaN threading dislocation densities as low as 5 × 103 cm−2were reported [1]. We are interested examining significant differences in the defect structure of the GaN substrates which can be observed in samples obtained from different manufacturers or as a function of the growth technique.
In this work we present a detailed analysis of defect structures of freestanding GaN (0001) crystals grown by HVPE and the ammonothermal method from different vendors. Synchrotron white-beam X-ray topography (SWXRT), high resolution X-ray diffraction (HRXRD) and microphotoluminescence (µPL) were used for this combined study. SWXRT in two principal X-ray topography geometries was used in the course of this analysis, namely the large-area back-reflection mode and section transmission mode. HRXRD reciprocal space mappings and in-plane measurements were used for mosaicity analyses. The combination of these methods allows a detailed statement of the nature, density and distribution of typical defects in GaN bulk crystals with a large field of view. As an example, Fig. 1 shows a large-area back-reflection topograph (0006 reflection) of a HVPE GaN substrate. The topograph shows dislocation free areas, surrounded by rather sharp lines, indicating good material quality with low defect density. These features are interpreted as dislocation cell walls, suggesting the formation of a cellular defect network within this GaN sample, analogous to what was commonly observed in LEC GaAs [2].
With the combination of the results from SWXRT, HRXRD and µPL a consistent model for different defect structures of the freestanding GaN samples grown by HVPE and the ammonothermal method is discussed.

References

P.J. R. Doradzinski, R. Dwilinski, J. Garczynski, L.P. Sierzputowski, Y. Kanbara, in Technology of Gallium Nitride Crystal Growth, edited by D.Ehrentraut, E. Meissner, and M. Bockowski, (Springer-Verlag, Heidelberg, ISBN 978-3-642-04828-9), 137-158, (2010).

P.J. McNally, P.A.F. Herbert, T. Tuomi, M. Karilahti, and J.A. Higgins, J. Appl. Phys. (1996) 79, 8294.

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(Invited) High Efficiency Green-Yellow Emission from InGaN/GaN Quantum Well Structures Grown on Overgrown Semi-Polar (11-22) GaN on Regularly Arrayed Micro-Rod Templates
Authors: Gong Y , Xing K , Xu B , Yu X , Li Z , Bai J , Wang Tao 
Published: February 2020

Last two decades have seen major developments in the field of III-nitride materials and optoelectronics, which is mainly based on polar GaN on sapphire. So far, the growth of c-plane GaN on sapphire has almost approached its theoretical limits and the major limit to the performance of GaN-based LEDs is due to the growth on c-plane. Consequently, this polar orientation leads to a number of fundamental issues, such as efficiency droop, and green and yellow gaps in wavelength coverage. One clear way forward, meeting the fundamental challenges, is to grow along semi-polar/non-polar direction. Semi-polar orientations, in particular, (11-22), offer another major advantage, namely, it can also significantly enhance indium incorporation into GaN, which cannot be achieved using c-plan GaN and thus is extremely important for growth of long wavelength emitters, such as green and even better for yellow. However, the current challenge is due to the crystal quality of semi-/non-polar GaN, which is far from satisfactory. So far, the best performing semi-polar emitters are grown on semi-polar GaN substrates which are typically ~ 10x10 mm in size. Therefore, it is necessary to develop a cost-effective approach to developing large size semi-polar GaN templates with major improvement in crystal quality but still based on sapphire substrates.
The Sheffield team has developed an overgrowth approach for 2" (11-22) semi-polar GaN with significantly enhanced crystal quality on nanorod templates fabricated by self-organised nickel nano-mask approach. Very recently, a new overgrowth approach based on optical lithography mask pattern technique has been developed, where regularly arrayed micro rod templates can be cost-effectively fabricated and the size of the micro rods can be well controlled. The new approach has led to further improvement in both crystalline quality and surface morphology. This has been confirmed by high resolution transmission microscopy (TEM) studies, demonstrating further significant reduction in both dislocation density and basal stacking fault density.
InGaN/GaN multiple quantum well structures with high In compositions have been grown on such semi-polar GaN templates, and we have achieved strong emission at long wavelengths, even down to ~600 nm. For the green-yellow emission at 555 nm, we have obtained an internal quantum efficiency (IQE) of up to 14%, and 7-10% for the pure yellow emission at ~570 nm. Con-focal photoluminescence (PL), micro-PL, time-resolved PL (TRPL), and micro-TRPL have been performed
(Invited) Power Loss Reduction in Perforated-Channel HFET Switches
Authors: Shur Michael , Gaevski Mikhail , Gaska Remis , Simin Grigory , Wong Hugh Yung , Braga Nelson , Mickevicius Rimvydas 
Published: February 2020

The key factors affecting the efficiency of power electronic systems are the conduction and switching losses in semiconductor power switches. For field-effect transistor switches, the conduction power loss is proportional to the product of the squared current, ION
, flowing through the switch in the on-state and the switching loss is proportional to the squared maximum switch voltage, VMAX,
the effective device output capacitance, COUT
, and the switching frequency, fSW
. Therefore, the RONCOUT

product is an important figure of merit of a FET-type switch determining the overall power efficiency. Our proposed and implemented Perforated Channel (PC) FET design 1 allowed us to significantly reduce RON
,
but not COUT. We now propose and demonstrate the improved PC-HFET design that allows us to reduce both RON and COUT
. This design reduces the power losses and significantly improves the efficiency of power electronics systems. In the PC-HFET, the portions of the channel under the gate are removed and the remaining channel forms a dash-line of islands WG1
wide with WGG spacing between them. The channel “filling factor” in PC-HFET is kF = WG1/(WG1+WGG
). Compared to conventional HFET with the same total width W, the total channel width and, hence, the device gate capacitance, of the PC-HFET is kF
times smaller. However, our analytical estimates, numerical simulations (using the 3D simulation in Synopsys Sentaurus device simulator), and experimental data all show the on-resistance of the PC-HFET can be only 10-15% higher than that of the conventional HFET of the same width. This is achieved due to a strong current spreading effect in the source-to-gate and, especially, in a larger gate-to-drain spacing. The gate capacitance of PC-HFET reduces proportionally to the kF
factor as proven by our simulations and experimental data presented in [1]. However our 3D simulations show that the CGD
scaling in PC-HFET at high drain voltage is nearly the same as that for conventional HFET. To reduce this capacitance, we proposed the PC-HFET device design with the holes extending into the gate-drain spacing. Our simulations show that the hole extension allows for nearly the same CGD
reduction as the gate metal removal over the holes. We used the obtained RON
and CGD
data to calculate the power loss in AlGaN/GaN PC-HFET and showed that the PC-HFET design filling factor kF
= 0.25 reduces the total conversion loss in the power switch by more than a factor of 2.
[1] G. Simin, M. Islam, M. Gaevski, J. Deng, R. Gaska, and M. Shur, “Low RC-constant Perforated-Channel HFET”, IEEE El. Dev. Letters, V. 35, pp.449-451, 2014

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In-Situ Characterization of Defect Dynamics in 4H-SiC Power Diodes under High-Voltage Stressing
Authors: Shenai Krishna , Raghothamachar Balaji , Dudley Michael , Christou Aris 
Published: February 2020

Wide bandgap (WBG) semiconductor power switching devices, especially those made on silicon carbide (SiC) and gallium nitride (GaN), promise transformative advances in electrical power switching systems because of superior electrical and thermal properties of these materials compared to the semiconductor silicon [1]. However, the progress has been slow despite intense scientific and industrial development. Both SiC and GaN semiconductors contain a high density of crystal defects and the role of defects on the performance and reliability of electrical power switching devices under extreme operating environment is not clear. Using synchrotron white beam X-ray topography (SWBXT), it is shown that the breakdown mechanism in 4H-SiC is initiated at the threading screw dislocations present in the high field regions of a power diode. To avoid this phenomenon from occurring, commercial 4H-SiC high-voltage diodes are rated for punch-through leakage currents rather than for avalanche breakdown condition. Thus, crystal defects in 4H-SiC present a major roadblock for performance and reliability optimization of power switching devices.
[1] K. Shenai et al, “Current status and emerging trends in wide bandgap (WBG) semiconductor power devices,” ECS J. Solid State Sci. and Tech.
2(8), N3055-N3063, Jul. 2013.