bluuebunny/crossref_metadata_2025_split huggingface dataset:
Surface Cleaning of SiGe(100) and Passivation of Ge(100) with Aqeuous Ammonium Sulfide
Authors: Heslop Stacy Lynn , Engesser Philipp , Okorn-Schmidt Harald F. , Muscat Anthony J. 
Published: February 2020

As scaling of microelectronic devices continues, germanium and silicon-germanium are promising materials for integration into silicon-based technology. Germanium and silicon-germanium based field-effect transistors can reduce leakage current and consume less power by means of improved carrier mobility and a narrower band gap, as opposed to traditional electronics. However, silicon-germanium surfaces are more challenging to work with because the topmost surface layer is comprised of germanium oxides that complicate cleaning and passivation processes. Here we seek to obtain a smooth, oxide free SiGe surface and hope to garner an understanding of the best conditions to effectively remove surface oxides. Additionally, we hope to further our understanding of aqueous ammonium sulfide passivation processes on Ge surfaces that will prevent re-oxidation of the surface for applications towards modern field-effect transistors (FETs).
The first portion of this work focuses on the removal of oxides from the SiGe surface with 50 and 75% Ge molar ratios using a variety of aqueous processes. These processes include SC-1, HCl, HF, and HCl/HF mixtures. The SiGe surface was characterized using X-ray photoelectron Spectroscopy (XPS) after each chemical treatment. Film thicknesses were measured using spectroscopic ellipsometry. Immersion in HCl showed similar results to as shipped samples and was ineffective in removing surface oxides. Aqueous HF, however, removed both surface oxides and carbon contamination. SC-1 treatments selectively reduced the Ge in the SiGe film and left the surface enriched in Si, which oxidized as confirmed by XPS. If the Ge could be completely removed from the top-most layer, the SiO2 layer that forms could be used to passivate the SiGe surface and avoid problematic Ge oxides. Ellipsometry results showed that SC-1 solutions (NH4OH:H2O2:H2O, 1:1:100 v/v) etched 1 nm of the SiGe film, which was then oxidized. Ge 2p to Si 2p XPS peak ratios confirmed that increasing concentrations of SC-1 depleted the Ge content on the surface from 0.8 to 0.4, confirming the enrichment of the surface in Si. Ge to Si peak area ratios as a function of the SC-1 dilution factor showed a non-linear trend for SiGe 50% surfaces.
Passivation of Ge with aqueous (NH4)2S was also studied. Because Ge oxides are unstable and water soluble, it is advantageous to remove them and deposit a sulfur layer to prevent further oxidation when exposed to air. Surface passivation was studied as a function of deposition time, solution concentration and the addition of H2O2. Passivation of the surface was ineffective at times below 20 min. Changing the concentration of (NH4)2S also had no noticeable effect on the surface based on XPS. Furthermore, at high ammonium sulfide concentrations the addition of H2O2 did not affect the passivation process. The addition of H2O2 to dilute (NH4)2S showed poor passivation due to oxidation of the surface by H2O2.
Effect of Pre-Wet Cleaning Conditions on the Pad Oxide Thickness
Authors: Bhattacharyya Dhiman , Sampathkumar Sathya Priya , Prasad Jagdish 
Published: February 2020

The thickness of the furnace grown pad oxide is limited by the balance between the bird’s beak effect and the stress induced crack of the silicon nitride. Absence of pad oxide can completely eliminate the bird’s beak effect; however it also introduces stress generated cracks at the Si and silicon nitride interface which ultimately degrades the transistors. Additionally, the silicon wafers are also cleaned by wet processes to remove any incoming contamination, surface particles and other defects before the growth of this pad oxide. Since this wet cleaning process directly affects the pad oxide thickness, it is important to understand how the pre-clean chemistries and process conditions control the oxide growth.
In this study, effects of temperature, process time and concentration of SC1 and SC2 cleaning chemistries are investigated. Furthermore, effect of removing native SiO2 by initial dHF treatment is also evaluated as one of the variables. A set of experiments were designed to evaluate the effects and interactions between these variables within wide windows. A difference of >2A in pad oxide thickness and >1nm in mean roughness of the silicon surface after the pre-wet clean were observed. For example, SC1 process at higher temperature always showed thicker oxide growth compared to room temperature SC1 when the SC1 process time was identical. This article provides a detailed understanding of how the growth of pad oxide can be affected by the pre cleaning process parameters.
Real-Time pH Monitoring of Ultra-Diluted Chemistry with a Micro-Sampling pH Monitor
Authors: Nakai Yoko , Miyamura Kazuhiro , Takagi So , Mori Yoshihiro 
Published: February 2020

At wet cleaning and etching process in semiconductor manufacturing, several ppm of ultra-dilute ammonia is sometimes used. When CO2 dissolves into the ammonia solution, it changes to carbonic acid, and neutralizes ammonia solution. It means, CO2 dissolution leads to pH change and impact to process performance. In order to know the chemical condition, pH is one of the key parameters. From its principle, however, internal solution (KCl) of pH probe dissolves into sample solution and lead to contamination, so the sample needs to be drained after measurement. Schematic system of pH probe is shown in Fig.1. Measurement using pH probe requires several tens to hundreds mL sample, so waste chemical amount and cost impact is significant.
In order to solve such problems, we developed a real time, in-situ use pH monitor. This monitor equips micro flow pH sensor, which samples 0.5 mL per one monitoring, minimum interval is 1 min, i.e. sample consumption is maximum 30 mL per hour, and it enables to obtain real time pH data.
Using this monitor, ca. 1ppm ammonia solution was continuously monitored at every 1 minute. Test system is shown in Fig.2. From 0 to 0.9 h, sample solution was bubbled with N2, from 0.9 to 1.9 h bubbled with air, then from 1.8 to 4 h bubbled with N2. Monitor result is shown in Fig.3.
[0 to 0.9 h] bubbled with N2 gas, CO2 does not dissolve to the solution, and pH is kept stable.
[0.9 to 1.9 h] bubbled with air, pH drops from 9.3 to 7.0 approximately in 10 minutes, which is caused by CO2 dissolution from the air.
[1.9 to 4 h] bubbled with N2 gas again, pH value recovered because CO2 is put out.
In conclusion, micro-sampling pH monitoring system, it enabled to detect clear pH change of ultra-diluted ammonia solution caused by CO2 dissolution with real-time bases.

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(Invited) Optimizations of p and n-Type Bi2Te3-Based Ternary Compounds By Ms-Pulsed Plating and Annealing Under Telluride Atmospheres
Authors: Nielsch Kornelius 
Published: February 2020

In this work, a comprehensive study of thermoelectric chalcogenide materials is presented and the systematic optimization of n-type Bi2Te3, p-type Sb2Te3 and their ternary compounds is performed. Thermoelectric materials are synthesized by potentiostatic electrodeposition on Au/Pt and stainless steel substrates. The influence of the preparative parameters such as the composition of the electrolyte bath and the deposition potential is investigated in a nitric acid solution.
As a post-deposition step, the influence of annealing of the films is investigated. The use of a potential-controlled millisecond-pulsed deposition method improves both the morphology and the composition of the films.
For n-doped films, approximately -100 µV K−1 (Bi2Te3) and -130 µV K−1 (Bi2(TexSe1−x)3) are achieved. Power factors and ZT values for p-type and n-type ternary alloys of up to 1325 µW m−1K−2 (ZT=0.4) and 825 µW m−1K−2 (ZT=0.3) are realized, respectively. In conclusions, the thermoelectric perform have been improved by one to two orders of magnitude in comparison to previously electrochemical synthesized thermoelectric layers. Based on the electrochemical synthesis and subsequent balancing of the stoichiometry by annealing under Te atmosphere, have resulted in bulk-like power-factors.
Millisecond pulsed electrochemical deposition is also a quite flexible approach for achieving nanowires of ternary chalcogenide compounds, which are grown in nanoscale confined spaces. After the annealing in Te enhanced the transport properties, on single Bi2(Te1-xSex)3 and (Bix-1Sbx)2Te3 nanowires power factors of 3100 mW K-2 m-1 and of 1600 mW K-2 m-1 with nearly bulk-like properties are achieved, respectively. Furthermore, we present magneto-resistance measurements on the Bi2Te3 and Sb2Te3 nanowires, which show clear evidences of topological surface states.
The financial support by the German Ministry of Science and Educations (BMBF) and by the German Priority Program DFG-SPP 1386 on Thermoelectric Nanostructures is gratefully acknowledged: www.spp1386thermoelectrics.de
(Keynote) Silicon Photonics Technology for Optical Communications with High Bandwidth Density Requirements (1Tbit/s and 1,000 Gbit/s/cm²)
Authors: Menezo Sylvie , Pares Gabriel , Bernabe Stephane , Castany Olivier , Sciancalepore Corrado , Hassan Karim , Blampey Benjamin , Charbonnier Benoit , Harduin Julie , Messaoudene Sonia , Saeedi Saman , Emami Azita , Ben Bakir Badhise 
Published: February 2020

As many applications emerge with the need for providing System-In-Package with optical I/Os, Silicon photonics technology shows great assets over other optical technologies:
- The integrations of all the optical functions required to establish an optical transmission link have been demonstrated (silicon based modulators and (de)multiplexers, integration of Ge/Si photodetectors and heterogeneous integration of III-V/Si lasers). The fabrication is achieved in CMOS fabs on 200 and 300mm-wafers.
- Besides the Si-Photonics technology enables the use of 3D assembling techniques for interconnecting the Silicon-Photonic Integrated Circuit (PIC) with its required driving Electronics (Electronic IC). Micro pillars can be used with ultra-low parasitics between the PIC and its companion EIC.
The talk will review how the Silicon photonics technology toolbox developed at CEA-Leti (including the photonic devices library and the 3D assembling techniques for interconnecting PICs and EICs) scales with transmission applications having denser integration requirements (Tbit/s-class transceiver with bandwidth density > 1,000 Gbit/cm²). The performances of several demonstrators will be presented (25Gb/s receiver and 16-QAM transmitter) made from hybridation of Si-PICs and CMOS Electronic ICs).
(Invited) Negative Capacitance Using Ferroelectrics for Future Steep-Slope MOSFETS
Authors: O'Neill Anthony 
Published: February 2020

Effective negative capacitance has been postulated in ferroelectrics because there is hysteresis in plots of polarization-electric field. In future integrated circuits, the incorporation of negative capacitance into MOSFET gate stacks would reduce the sub-threshold slope, enabling low power operation and reduced self-heating. As a step towards meeting this challenge, effective negative capacitance is demonstrated at room temperature in metal-insulator-metal capacitors, where it is stabilized by the presence of a paraelectric material.
Steep slope MOSFETs are a priority research area, driven by the need for low energy CMOS. Gate capacitance places a lower limit on the sub-threshold slope. The consequence is that transistors need a larger applied voltage to be on and/or will leak current and so can never be fully switched off. This leads to increased power loss and heating as more transistors are crammed onto the same area of silicon, which limits component density. The concept of ferroelectrics displaying effective negative permittivity has led to the speculation that their inclusion in the gate stack of a MOSFET will reduce the sub-threshold swing, S, of CMOS devices below 60 mV/dec. For a gate stack comprising a thin ferroelectric layer on top of a thin SiO2 layer, the channel potential ψs can change more than the gate voltage Vg, thus providing a step-up voltage transformer and S < 60 mV/dec. If this can be engineered, it heralds a transformation of future integrated circuits (ICs), reducing the off-state current (Ioff) and/or supply voltage (VDD) which otherwise limits Moore’s Law as heat generated during switching cannot be removed. The idea has led to the search for unambiguous experimental evidence of negative capacitance in candidate ferroelectrics at room temperature as a step towards this ambition.
In this study, experimental evidence is presented to demonstrate effective negative capacitance at room temperature in thin films of the ferroelectric BaTiO3. The BaTiO3 is fabricated in a bi-layer stack in series with SrTiO3, which is paraelectric at room temperature. The Metal-Insulator-Metal (MIM) stack is formed on a SrTiO3 substrate and using SrRuO3 as the bottom conducting electrode, which is lattice matched to the substrate. As the BaTiO3 layer thickness increases then the total capacitance is seen to increase, which is consistent with the ferroelectric capacitance being negative. In each case the bi-layer capacitance exceeds the SrTiO3 capacitance alone. Any hysteresis behavior is absent from the capacitance measurements in these bi-layer devices. The present work demonstrates the feasibility of negative capacitance at room temperature using a lead-free perovskite ferroelectric of varying thickness. The robust material can be integrated into CMOS or included as a performance booster within innovative devices such as tunnel field effect transistors in order to realize a future low power technology.
(Invited) Silicene As a 2D Material Candidate
Authors: Vogt Patrick , Le Lay Guy , De Padova Paola 
Published: February 2020

Silicene, a new Si-based 2D material with a graphene-like honeycomb structure, has attracted considerable interest, because its topology confers to it the same remarkable electronic properties as those of graphene [1]. Contrary to graphene, silicene does not exist in nature and had to be synthesized on a substrate material, such as Ag(111) [2]. In comparison to graphene, such silicene layers might have a potential advantage of being easily integrated in current Si-based nano/micro-electronics offering novel technological applications. Only very recently the first silicene transistor was reported, based on silicene layers grown on a Ag(111) substrate [3].
In this talk the recent development in epitaxial formation of single layer silicene will be reviewed, including structural and electronic properties for different silicene and 2D-Si layers. Furthermore, the formation of silicene double-layer and multi-layer structures will be discussed [4]. Different structure models will be compared to experimental results in order to unveil the nature of these layered materials. Such a detailed understanding of single/multi-layer silicene structures and their formation is crucial in order to optimize the performance of future devices which are based on such layers.
We will also discuss the stability of single/multi-layer silicene upon heating and oxidation and look a possible modifications of silicene by adsorbates. It is expected that silicene can be functionalized this way, which could open a new way for the application of Si in electronic devices.
1) G. G. Guzmán-Verri and L. C. Lew Yan Voon, Phys. Rev. B 76, 075131 (2007); S. Lebègue and O. Eriksson, Phys. Rev. B, 79 115409 (2009); S. Cahangirov et al., Phys. Rev. Lett. 102, 236804 (2009).
2) P. Vogt et al., Phys. Rev. Lett. 108, 55501 (2012); C.-L. Lin et al., Appl. Phys. Exp.
5, 045802 (2012); B. Feng et al., Nano Lett. 11, 3507 (2012).
3) Li Tao et al., Nature Nanotechnology (2015).
4) P. Vogt et al., Appl. Phys. Lett. 104, 021602(2014), P. De Padova et al., Appl. Phys. Lett. 102, 163106 (2013)
(Invited) Innovative Embedded Non-Volatile Memories: Flexibility and Reliability
Authors: Navarro Gabriele , Vianello Elisa , Molas Gabriel , Sousa Véronique , Perniola Luca 
Published: February 2020

Conventional memory technologies are facing nowadays many challenges such as miniaturization limits and reliability issues. In the last years, 3D integration strategies showed how Flash memory can still dominate the stand-alone market in the near future, mainly driven by the increasing demand of data storage in portable applications. However, in a technology context in rapid evolution and differentiation, where the microcontrollers market is growing fast becoming more and more price sensitive, the embedded non-volatile memories (eNVM) represent a key element for rapid product customization. Moreover, if the parallel and fast computing is pushing the CMOS platform towards aggressive technology nodes, back-end-of-line (BEOL) memory solutions can represent a real compromise between performances and cost saving.
Innovative NVMs such as resistive ram solutions (e.g. Phase-Change Memory), recently showed how they can represent a real breakthrough in terms of increasing performances, power consumption lowering and cost reduction. This is also due to their CMOS-compatible fabrication, and easy BEOL integration. Material engineering and architecture optimization demonstrated how these technologies can even target extreme specifications required in such applications as industrial or automotive.
In this talk we present the main features of emerging resistive NVM solutions, and how target specifications can be satisfied by material tuning, architectures engineering and specific programming techniques.
Reduction of Dendrite Formation in Zn Electrodes By Controlled Pulse Electrodeposition
Authors: Garcia Grecia , Ventosa Edgar , Schuhmann Wolfgang 
Published: February 2020

Great efforts have been devoted to extending the use of Zinc for secondary batteries due to its high energy density, abundance and environmental sustainability. Nevertheless, there are several drawbacks preventing the implementation of Zn electrode in rechargeable batteries. One of the major limitations of a reversible Zn electrode is the formation of dendrites upon cycling. The morphology of the electrode undergoes significant changes leading to the formation of metallic Zinc needles. In a battery, these dendrites can penetrate through the separators, resulting in short-circuit and reducing significantly the lifetime of the battery.
Several strategies have been proposed to address this issue, ranging from incorporating certain additives in the electrolyte, to the use of special separators as a physical barrier between electrodes. Here, we present a strategy to suppress dendrite formation based on controlling the electrodeposition using designed charge pulse profiles. Understanding and designing a suitable pulse profile requires a large number of experiments. In order to make this possible in a reasonable amount of time, high throughput evaluation of the influence of a chosen electrochemical pulse deposition profile on the morphology was carried out using a specifically designed Scanning Droplet Cell (SDC). The SDC offers the advantage of performing automatically many experiments in a short timeframe enabling the evaluation of a wide vari­ety of parameters that may affect electrodeposition of Zinc. The electroreduction of ZnO proceed via a two-step process. Zincates dissolved in the pores of the paste electrode are reduced to metallic zinc. Due to the consumption of zincates, ZnO dissolves in the solution. Therefore, controlling the very early stage of the formation and growth of Zn nuclei from the reduction of zincates allows the redistribution of the material during charge. In addition, diffusion limitation of zincates was considered as a key factor for controlling the electrodeposition of Zn. Finally, our study envisions the application of these pulse profiles in a three electrode prototype cell.

Figure 1
Alkaline Earth Metals As Anode for High Energy Rechargeable Fluoride Ion Batteries
Authors: Tho Thieu Duc , Fichtner Maximilian 
Published: February 2020

With increasing demand on energy supply together with reducing fossil sources, many efforts have been put into the research and development of environmentally benign, high energy density and low-cost rechargeable battery systems as an alternative. Fluoride Ion Battery (FIB), which is based on fluoride ion electrochemistry rather than lithium ion (in case of lithium ion battery), has emerged as a potential alternative. The element fluorine possesses an outstanding potential compared to Li owing to its high electronegativity and, thus, electrochemical stability, relatively low weight, more natural abundance and comparably low cost. By choosing an appropriate pair of electrodes comprising metal fluoride and metal together with a suitable fluoride-containing electrolyte, a high voltage electrochemical FIB cells can be built [1, 2]. Recently the first proof of concept for rechargeable fluoride ion batteries based on all-solid-state setup has been demonstrated [2].
Alkaline earth metals have recently attracted much attention for their employment in energy storage technologies due to potentially high energy density, low cost and environmental friendliness. Hence, in this study Ca and Ba pure metals were chosen and tested as anode in rechargeable FIB system. CaxBa1-xF2 (x ~ 0.5), a highly ion conducting metastable fluoride compound, was selected and synthesized via high energy mechanical milling route as fluoride ion conducting electrolyte. Powder X-ray diffraction confirms the formation of solid solution and electrochemical impedance measurement of CaxBa1-xF2 shows ionic conductivity in the order of 10-4 S.cm-1 at elevated temperature around 200 0C, which is in agreement with earlier report [3]. The assembly of all-solid-state electrochemical FIB cells was carried out with Ca or Ba as anode, selected metal fluorides (BiF3, CoF3, and CuF2) as high voltage cathode, and CaxBa1-xF2 (x ~ 0.5) as electrolyte. The cells were assembled in the charged state and electrochemically tested at ~ 200 0C. Initial results showed that the specific capacities of Ca/BiF3 and Ca/CuF2 cells for the first discharge are about 260 mAh/g and 350 mAh/g, respectively. These capacities are about 86% (in case of BiF3) and 66% (in case of CuF2) of their theoretical specific capacities and higher than those of Ce/BiF3 and Ce/CuF2 systems reported previously [2]. Electrode analysis together with cycling behaviour reveal the fluoride ion transfer between anode and cathode, as well as the cyclability of alkaline earth metal based FIB system. Further structural and electrochemical characterization will be presented and discussed.

References

1. N. I. Sorokin and B. P. Sobolev, Crystallography Reports, 52, 2007, 842-863.
2. M. A. Reddy and M. Fichtner, J. Mater. Chem., 21, 2011, 17059-17062.
3. A. Duvel, B. Ruprecht, P. Heitjans and M. Wilkening, J. Phys. Chem. C, 115, 2011, 23784-23789.