Optimized Novel Indium Antimonide Quantum Well Field Effect Transistor for High-Speed and Low Power Logic Applications
Authors: Islam Rabiul , Uddin Md. Mohi , Matin Mahmud Abdul 
Published: February 2020

The physical gate length L
G of the Si transistors are shrinking day by day to meet Moore’s law that states the number of transistors per integrated circuit doubles in every 24 months. It is projected that L
G may be down to ~20 nm. Therefore, it is urgent need to be “energy efficient” which operates with the lowest switching power. Much effort has been paid to incorporate III-V nanoelectronics on the silicon platform due to highest intrinsic electron mobility. The InSb quantum well field effect transistor (QWFET) is a promising candidate for future high performance and low power logic applications [1,2]. In addition, recent success in depositing high-quality Al2O3 gate dielectrics by atomic layer deposition (ALD) on the InSb quantum wells (QWs) and completely depletion of the two-dimensional electron gas (2DEG) confined in InSb QW opens the prospects to fabricate high-quality InSb QW field effect transistor (FET) [3,4].
An InSb QWFET with a 10 nm thick Al2O3 top gate insulator has been simulated by using quantum corrected Schrödinger-Poisson (QCSP) solution as shown in Fig. 1 (a). Gate voltage (V
g) dependent electron density (ns
) and mobility (µ) is shown in Fig. 1 (b). A very high electron mobility 4.42 m2V-1s-1
at V
g= 0V is achieved which is at least ~180 times greater than that of Si NMOS. The confined 2DEG in InSb QW is completely depleted with a very small V
g= -0.25V (is called as the pinch–off voltage, V
p). The slope of the ns-Vg
yields a giant gate controllability ratio of dn
s/dV
g = ~ 5.2 × 1015
m
-2
V
-1 (estimated in the range of V
g=-0.2V to 0V). The room temperature conduction band (CB) and valance band (VB) profile of the proposed structure at V
g= 0 and -0.25V are calculated by QCSP as shown in Fig. 2. The QW is lifted above the Fermi level (E
F) at V
g = -0.25V which is confirmed complete depletion (V
p) as shown in Fig. 1. Moreover, the hole accumulation prevents as the VB doesn’t touch the E
F.
The interface trap density (D
it) has been calculated using the equation D
it= -(dQ
it / (e × d(E
F - E
V))) where Q
it is the net charge (difference between oxide and semiconductor charge) [4]. Energy dependent D
it and corresponding applied gate voltage (V
g) is shown in Fig. 3. Very low D
it is found to be 7.8 × 1014 – 3.7 × 1016
m-2eV-

1 at the interface between Al2O3 and Al0.1In0.9Sb top layer of the InSb QWFET, results a giant dn
s/dV
g (Fig. 1b). It indicates that the E
F is smoothly tuned by the V
g due to a very low D
it of the InSb QWFET. The capacitance-voltage (C-V) calculation has also been confirmed the low D
it and V
p of the proposed QWFET. The standard transistor characteristics with I
D versus V
DS at different V
g, transconductance (g
m) have also been calculated and explained by the established theory and experimental explanation.
[1] T. Ashley et al. Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology (SSICT), 2253 (2004).
[2] S. Datta, Microelectronic Engineering84, 2133 (2007).
[3] M. M. Uddin et al., Appl. Phys. Lett.101, 233503 (2012).
[4] M. M. Uddin et al., Appl. Phys. Lett.103, 123502 (2013).

Fig. 1: (a) Cross section of InSb optimized QWFET layer structure with LG
=100 nm and δ-doping (dashed line). (b) Electron density (n
s) and mobility (μ) of the InSb QWFET as a function of gate bias (V
g) at 300 K. The dashed line points to the pinch-off voltage V
p.

Fig. 2: Band profile (CB and VB) of the proposed InSb QWFET at 300 K. The Fermi level is shown at 0eV.

Fig. 3: The interface trap density (D
it) as a function of E
F-E
V obtained from the QCSP solution with corresponding applied V
g (V).

Figure 1