bluuebunny/crossref_metadata_2025_split huggingface dataset:
Package Reliability and Integrity Improvements for a Thermally Enhance Non-Conductive Die Attach Adhesive for ASIC Devices on Exposed Pad Packages
Authors: Denoyo Alvin , De Lazo Darwin , Costa Ivan , Menor Allen 
Published: December 2019

Abstract
Polymers being used in a plastic-encapsulated integrated circuit (IC) package exposed to a humid environment absorbed moisture and expand resulting to a so called delamination failure. Weak or imperfect adhesions between the interfaces of the mold compound and adhesive unto the leadframe surface are often the main sources of these failures. In response to automotive requirements and to ensure excellent package reliability and integrity, delamination in all interfaces should then be eliminated. Thus the primary objective of this work is to fulfill the no delamination criteria in all interfaces after moisture soak for an exposed pad package. To satisfy these requirements, activities includes leadframe design improvements, surface enhancement and bill-of-material changes. With the design improvements implemented, still the material compatibility plays an important role in achieving improved package reliability.
Flip-Chip Flux Evolution
Authors: Mackie Andy , Jo Hyoryoon , Lim Sze Pei 
Published: December 2019

Abstract
Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage.
This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.
Low thermal resistance packaging for high power electronics
Authors: Shashidhar Nagaraja , Rao Abhijit 
Published: December 2019

Abstract
Alumina and aluminum nitride substrates are routinely used in micro-electronic packaging where large quantity of heat needs to be dissipated, such as in LED packaging, high power electronics and laser packaging. Heat management in high power electronics or LED's is crucial for their lifespan and reliability. The ever-increasing need for higher power keeps challenging the packaging engineers to become more sophisticated in their packaging.
With the availability of a 40 μm thick, high thermal conductivity ribbon alumina from Corning, the options available for packaging engineers has widened. This product has very high dielectric breakdown (~10kV at 40 μm thick), high thermal conductivity (&gt;36 W/mK) and is rugged enough to be handled (with components attached) during packaging. These characteristics make ribbon alumina a cost-effective alternative to incumbent materials such as thick aluminum nitride, for use in high power microelectronics packaging.
In this paper, high power LED and IGBT modules are modeled using commercially available code from ANSYS®. A geometry representative of typical LED packaging and IGBT packaging is constructed with Ansys Design Modeler platform and the allied meshing is done employing in-built Meshing tool in ANSYS Workbench®. We show that packaging with ~40 μm ribbon alumina delivers performance on par with or better than packaging with thicker aluminum nitride substrates.
Reliability of screen-printed conductors and resistors during fatigue cycling on flexible substrate
Authors: Garakani Behnam , Sandakelum Somarathna K Udara , Weerawarne Darshana L , Poliks Mark D , Alizadeh Azar 
Published: December 2019

Abstract
Scalable printing of conductor and resistor components has revolutionized the field of flexible electronics by enabling a myriad of low cost highly conformable devices. Flexible electronic devices need to exhibit reliable performance under strenuous mechanical deformations to be adopted in applications such as human and asset monitoring. The reliability of the devices is in turn affected by the microstructure of the materials, manufacturing processes, and conditions of use.
In this research, the mechanical behavior and microstructural properties of stretchable silver conductor and stretchable carbon conductor inks on flexible substrate are studied. The test vehicles (such as 4- point probe structures are screen printed on thermoplastic polyurethane (TPU) and cured in a convection oven. The quality of the printed traces including the resolution and thickness profile are measured by Confocal Laser Scanning microscope. The microstructure of the sample including particle/nanoparticles morphology is studied by Scanning Electron Microscopy (SEM). The electrical resistance is measured by 4-point probes method and the sheet resistance of the printed samples is calculated. The mechanical and electrical reliability of the samples are investigated by fatigue-cycling and in-situ measuring of the electrical resistance. In terms of electrical conductivity, the silver printed traces show different behavior compared to the carbon printed samples when exposed to fatigue cycling. The electrical resistance of the printed silver trace increases during the fatigue cycling. Higher extension rate along with higher strain magnitude accelerate the rate of increase in the electrical resistance. The relative electrical resistance of the carbon trace initially drops to 0.7 after 40 cycles and remains constant for the rest of the cycles. The extension rate does not considerably change the electrical resistance of carbon trace. The stability in electrical resistance is crucial in applications where electrical shielding is concerned.
Ultra-Thin Wafer-Level Chip Scale Packaging
Authors: Hackler Douglas , Wilson Dale , Prack Edward 
Published: December 2019

Abstract
IC packages are getting thinner to facilitate thinner electronics products. Labels and tags are getting smarter. Electronics are starting to bend, and reliability is in question. Semiconductor-on-Polymer™ (SoP) Chip Scale Packaging (CSP) is enabling ultra-thin flexible hybrid electronics and sensors today. This presentation shares the development, of SoP application to flexible hybrid electronics (FHE), and where SoP fits in IC packaging technologies. SoP CSP facilitates more functionality for hybrid approaches with printed electronics by allowing seamless integration of thin die into flexible/printed electronics with high reliability. Reliable thin die are an enabler for thinner conventional IC packages and potentially for thinner embedded packages (both FO and substrate based). The presentation also shows the technology roadmap for SoP application to IC packaging.
Development of EDA Techniques for Power Module EMI Modeling and Layout Optimization
Authors: Evans Tristan M. , Le Quang , Narayanasamy Balaji , Peng Yarui , Luo Fang , Mantooth H. Alan 
Published: December 2019

Abstract
The design of power electronics modules is undergoing renewed interest as new challenges and technologies emerge in the realm of wide bandgap (WBG) power device packaging. In order to meet the demands of these high-speed transistors, novel techniques are required to produce modules with reduced parasitics and noise generation without exceeding the operating temperature of the devices or their packaging materials. Traditionally, power module design has been a highly iterative process—repeatedly reworking and simulating designs using finite element analysis (FEA) tools that require considerable time in terms of both labor and computation. To overcome these issues, an electronic design automation tool (EDA) known as PowerSynth is ongoing in its development toward power module layout synthesis and optimization based on electrical and thermal criteria. In this paper, work to extend the capabilities of PowerSynth to optimize layouts with reduced electromagnetic interference (EMI) is presented. Optimization strategies based on the transfer functions of noise propagation paths are introduced and results showing layouts with reduced noise generation are compared with FEA simulations.
Study Photo Imagable dielectric (PID) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection
Authors: Chien Chun-Hsien , Chen Chien-Chou , Yeh Wen-Liang , Lin Wei-Ti , Wu Cheng-Hui , Chen Fu-Yang , Lin Yi-Cheng , Wang Po-Chiang , Li Jeng-Ting , Lin Bo Cheng , Chen Yu-Hua , Tseng Tzyy-Jang 
Published: December 2019

Abstract
In 1965, Gordon E. Moore, the co-founder of Intel stated that numbers of transistors on a chip will double every 18 months and his theory called the Moore's Law. The law had been the guiding principle of chip design over 50 years. The technology dimension is scaling very aggressively in IC foundry. For example, TSMC announced their 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second half of 2019.[1] To overview the semiconductor supply chain included IC foundry, wafer bumping, IC carrier, PCB (Printed circuit board) and OSAT (oversea assembly and testing)… etc., the IC carrier and PCB technology dimension scaling are far behind than the IC foundry since many reasons for the traditional industry. The industry needs different kinds of breakthrough approaches for the scaling of via and strip line in next generation interconnection. Traditional organic substrates faces many challenges of warpage, surface roughness and material dimension stability issues for manufacturing and high density I/Os with very fine line interconnections. To breakthrough these challenges, the materials of glass carrier, new photo-imagable dielectric (PID) and advanced equipment were evaluated for the fine line and fine via interconnection. In the papers, there are many PID and non-PID materials were surveyed and compared for fine via (&lt; 10μm) interconnection or low loss of high frequency application. The first candidate was chosen for redistribution layers (RDL) fabrication by using 370mm × 470mm glass panels. Semi additive process (SAP) was used for direct metallization on glass panel with different build-up dielectric materials to form daisy chain test vehicles. The process, fabrication integration and electrical measurement results of daisy chain showed good continuity and electric resistance in the glass panel substrate. The reliability of the thermal cycling test (TCT) and highly accelerated stress test (HAST) were evaluated as well in this study.
LTCC slot array antenna for 5G application
Authors: Takahashi Hiroyuki , Hirano Satoshi , Yamashita Daisuke 
Published: December 2019

Abstract
We develop the antenna module substrate which is broadband and large gain using an LTCC technology in a 28GHz band in this study. We used LTCC materials (dielectric constant 5.8, Dielectric loss 0.002@28GHz) which we developed for materials originally. First of all, we confirmed ability of slot array antenna made by LTCC for 5G application to get broadband property. The structure of designed array antenna became 40mm × 3.2mm × t1.6mm. We confirmed that this antenna has wider bandwidth (2.2GHz) and higher gain (6dBi). But this antenna size is too large for applying mobile device. Therefore we redesigned to reduce antenna size without specification degradation. The structure of redesigned antenna element becomes basically 4.8mm × 6.7mm × t1.0mm. This antenna has wider bandwidth (2.7GHz). The gains are more than 5dBi for the characteristic of this element in a band. Assume this antenna a fabric; 2 × 2 (4 elements: for mobile device) and 4 × 4 (16 elements: for small cell base station) we make an array antenna for Small cell base station and for mobile device. We will evaluate a beam steering examination with emission properties (gain, beam angle).
Non-destructive In-line IMC Thickness Measurement Using Acoustic Metrology for 3D Stacking
Authors: Mehendale M. , Hou L. , Mair R. , Kotelyanskii M. , Liebens M. , Derakhshandeh J. , Mukundhan P. , Miller A. , Beyne E. , Kryman T. 
Published: December 2019

Abstract
The constant demand for small-feature-size, high performance and dense I/O applications have necessitated the development of fine-pitch vertical interconnects for 3-D integration. Microbumps and through silicon vias enable the high-density vertical interconnects. As microbumps scale, intermetallic compound formation during thermocompression bonding and its impact on reliability is a concern. In this paper, we describe the application of picosecond acoustic metrology technology as a viable option for non-destructive characterization of the intermetallic compounds. The small spot size technology allows measurement on small bumps, with very good accuracy and repeatability.
Contact Electroplating Technology (CET)
Authors: Kadija Igor V. 
Published: December 2019

Abstract
Whenever possible electroplating is the most preferred method of metallizing interconnects and devices in electronics. It delivers metals and alloys with their physical and chemical properties closest to the ideally attainable level. To do so the-state-of-the-art electroplating processes in electronics rely entirely on making direct contact of the power supply to the electroplated part. This is done either by having a heavier gauge clamp attached to one end of the object to be plated or with a, sometime intricate, conductive path or seed layer capable of delivering adequate electroplating polarization to the electroplated parts of the pattern. In most instances that type of direct link to the power supply presents a nuisance, forcing the designer of electronics to cope with the introduction of non-functional patterns, such as seed layers, taking space from the precious real-estate of the electronic substrate. Therefore, it is desirable to have an efficient way to enable metallization of isolated electronic patterns by electroplating, without sacrificing the substrate real-estate for establishing direct contact to the power supply. More recently a novel and potentially practical approach was introduced by ECSI Fibrotools. This process is the subject of this article. By applying the Contact Electroplating Technology (CET), US Patent #10,184,189, with up to several million electrical contacts per square inch, each isolated structure is simultaneously contacted and charged by the main power supply via the CET's working electrode. CET technique has been demonstrated with actual patterned structures of various substrates such as PWB surface finishing, flexible electronics, and various small electronic devices. CET technology enables completing or upgrading the electronic structures by electroplating of pure metal or alloy of desired thickness up to 10 microns or thicker if needed. Electroplating occurs directly on thin seed layer, laser ablated, or toner drawn patterns enabling well-defined metal plating. Completely isolated electronic interconnects were uniformly electroplated for surface finishing with Cu, Ni, Ag and Au.
Low Profile and Large Size WLCSP in IoT Applications
Authors: Tang Tom , Kuo Kuei Hsiao , Lin Victor , Chen Kelly , Chen J.Y. , Ma B.H. , Wang Yu-Po 
Published: December 2019

Abstract
Recently, Wafer Level Chip Scale Package (WLCSP) Package is being rapidly adopted in Internet of Things (IoT) and consumer mobile electronics due to its low profile, small form factor and relatively easy assembly process. WLCSP with large die size becomes the trend in fulfilling high performance product demands. However, the solder joint reliability performances of WLCSP is the key challenge and becomes critical as increasing die size, especially the size is larger than 6 × 6 mm2.
There is also growing interest in low profile WLCSP packages to less than 300 microns, especially when they are placed in a limited space inside IoT devices. Thin wafers are fragile and must be supported over their full dimensions to prevent cracking and breakage. An increasingly popular approach to thin wafer handling involves grinding and taping thin wafers with in-line machines. A specific carry tape have been also developed for transferring thin wafers after thinning.
In this paper, WLCSP board level reliability for both large die size and low profile was studied, a test vehicle used for the large WLCSP package testing has 350um ball pitch and fully populated array. In addition to board level reliability test simulation and data collection, processing challenges were discussed, as well as processing solutions for thin wafer handling.
A Novel Dicing tape for WLCSP Using Stealth Dicing Through Dicing tape and Back Side Protection-Film
Authors: Furuno Kenta , Yamashita Shigeyuki , Wakayama Yoji , Saiki Naoya , Takyu Shinya 
Published: December 2019

Abstract
Market demand of information terminals for Internet of Things (IoT) is increasing. So market situation requires various semiconductor packages. Wafer Level Chip Size Package (WLCSP) is one of the most important technology among them. We selected stealth dicing (SD) as a manufacturing method for WLCSP because the cutting speed is higher than blade dicing and the yield of semiconductor chip is higher than blade dicing. But, SD process still has some technical issues. In some cases, when the laser is irradiated from circuit side (from surface side of Si wafer), the metal pattern in circuit might prevent the laser focusing. In this case, the laser should be irradiated from backside of Si wafer through dicing tape. We have already developed a transparency suitable dicing tape for the SD process, but the base film material of the dicing tape is poly vinyl chloride (PVC) which is not becoming to conform with some of recent environmental standard. Market situation requires poly olefin (PO) dicing tape because of global environmental consideration. We developed PO dicing tape for SD process through dicing tape by conducting various evaluations. In this study, we report details of the development process of novel PO base film dicing tape with the same performance as PVC base film dicing tape and successfully separated a 12 inch silicon mirror wafer into 1 mm die squares and 12 inch silicon mirror wafer with the back side protection-film into 6 mm die squares.
How to secure the fabrication of Gallium Nitride on Si wafers
Authors: Alliata D. , Anderson N. , de Gevigney M. Durand , Bergoend I. , Gastaldo P. 
Published: December 2019

Abstract
Process control solutions to secure the High-Volume Manufacturing of Gallium Nitride (GaN) devices for power applications are a must today. Unity recently developed and introduced on the market a total control solution that address both defectivity and metrology needs of GaN industry. Proprietary technologies like Phase Shift Deflectometry, darkfield inspection, confocal chromatic imaging and infrared interferometry are here explored to detect killer defects potentially affecting the gallium nitride wafer. More in detail, we characterized Gallium nitride on Silicon substrate before and after the fabrication of the final device and demonstrated how the fabrication process can be optimized.
Optimizing the Within Wafer Non-Uniformity at the Chemical Mechanical Planarization step in Interposers and RDL fabrication process for 3D IC stacking
Authors: Kumar Amit , Chacon Jose , Gelzinis Peter , Velaga Ankineedu 
Published: December 2019

Abstract
Chemical Mechanical Planarization (CMP) is an integral step in fabrication processes of through silicon via based Interposer and Redistribution layer for routing. The key motivation in the CMP process is to achieve planarization with minimum recess and dishing on the metal routing sites. In this work we established the metrics for Within-wafer non-uniformity (WIWNU) and optimized the CMP parameters. Currently, there is no standard guideline for reporting the WIWNU during CMP and thus a better understanding and practice is needed to enhance post CMP uniformity across the wafer. The work reported in this article were conducted on 200 mm silicon wafers with either Copper or Tungsten to optimize the uniformity of removal rate with respect to polishing parameters, such as slurry flow, slurry composition, down force, relative velocity of wafer surface with pad, etc. With optimized CMP parameters for blank wafer, the WIWNU in patterned wafer were evaluated and analyzed for additional optimization in non-uniformity.
Bumping Co-planarity Collocation for Different UBM Size by Geometry Integration
Authors: Liu Wei-Wei (Xenia) , Weng Berdy , Lai Lu-Ming , Chen Kuang-Hsiung 
Published: December 2019

Abstract
Bumping co-planarity is a Cu pillar bump characteristic, that can impact to the joint quality of subsequent flip chip bonding process. The plated bump height variation correlates with lesser co-planarity values. Co-planarity can be minimized by bumping process, however the bumping process window is not adequate for some design features. For example, dummy bump or structure drawback features. This paper provides a methodology to improve co-planarity by collocating oval and circular bump which integrates the solder volume of different bump shapes. The final solder formation is different due to the geometry variation from the oval shape and circular shape. The final solder height can be calculated by mathematical integral from as-plated solder volume. Hence, better co-planarity can be achieved by the proposed method to collocate different bump shapes. The Cu pillar bump collocation design rules can be optimized to minimize co-planarity during initial design realization to minimize quality risks during fabrication..
Nanovoid Formation at Cu/Cu/Cu Interconnections of Blind Microvias: A Field Study
Authors: Bernhard T. , Gregoriades L. , Branagan S. , Stamp L. , Steinhäuser E. , Schulz R. , Brüning F. 
Published: December 2019

Abstract
A key factor for a high electrical reliability of multilayer High Density Interconnection Printed Circuit Boards (HDI PCBs) is the thermomechanical stability of stacked microvia interconnections. With decreasing via sizes and higher numbers of interconnected layers, the structural integrity of these interconnections becomes a critical factor and is a topic of high interest in current research. The formation of nanovoids and inhibited Cu recrystallization across the interfaces are the two main indications of a weak link from the target pad to the filled via. Based on TEM/EDX measurements on a statistically relevant number of stacked and blind microvias produced in the industrial field, different types of nanovoid phenomena are revealed at the Cu/Cu/Cu junction. The types of nanovoids were categorized relating to the time of appearance (before or after thermal treatment), the affected interfaces or layers and the impact on the Cu recrystallization. The main root causes for each void type are identified and the expected impact on the thermomechanical stability of the via junction is discussed.