bluuebunny/crossref_metadata_2025_split huggingface dataset:
Effects of Temperature on the Corrosion Potential of Stainless Steel Under Gamma-Ray Irradiation
Authors: Satoh Tomonori , Kato Chiaki , Ueno Fumiyoshi 
Published: February 2020

The structural materials of the instruments used in Fukushima Daiichi nuclear power station are exposed to the corrosive condition under the gamma-ray irradiation. In order to determine the effects of the temperature of water under gamma-ray irradiation on the corrosion potential of stainless steel, the measurements of the corrosion potential under gamma-ray irradiation condition was performed. The dissolved oxygen concentration was aerated condition in each temperature in this study. And the corrosive condition under the irradiation was evaluated by the water radiolysis calculation and the measurements of the included hydrogen peroxide in the water after the irradiation. As parameters, the temperature of water and the gamma-ray dose rate were changed. The major results are listed as follows;
(1) The corrosion potentials rose about 400 mV by the gamma-ray irradiation in all temperature conditions.
(2) The potential was low with higher temperature under irradiation with the aerated condition. It was assumed that the lower dissolved oxygen concentration with higher temperature will cause the dependency of the corrosion potential on the temperature under irradiation.
(3) The generation of some ppm of hydrogen peroxide was confirmed by the measurements of hydrogen peroxide concentration. It was indicated that the increase of the corrosion potential by the irradiation was caused by the generation of the high concentration of hydrogen peroxide.
(4) It was confirmed that the generation of hydrogen peroxide was lower in higher temperature condition due to the lower dissolved oxygen concentration in high temperature. It was indicated that lower potential in high temperature water was caused by not only lower dissolved oxygen but also lower generation of hydrogen peroxide.
(Invited) Silicon Nanowires/Metal Nanoparticles Composites with Specific Properties
Authors: Boukherroub Rabah 
Published: February 2020

In the past few years, there have been considerable advances in the synthesis and bio-applications of silicon nanowires (SiNWs). Because of their high surface area, electronic properties, biocompatibility, surface tailorability, multifunctionality and their compatibility with conventional silicon technology, SiNWs have been the focus of intense interest due to their potential applications in various fields including nanophotonics, biological/chemical sensors, microfluidics, and matrix-free laser desorption/ionization mass spectrometry substrates. Interfacing SiNWs with living cells and bacteria have been investigated in several reports with the aim to gain a better understanding on how these nanostructured substrates influence cell functions such as cell differentiation, adhesion and spreading.
In this presentation, I will focus on the deposition of metal nanoparticles (Ag, Au, Ni, Cu) on SiNWs and their use for various applications ranging from SERS to anti-bacterial substrates. Moreover, given the high catalytic activity of noble metal nanocatalysts owing to their relatively high chemical activity and specificity of interaction, the resulting SiNWs/metal NPs have been successfully applied for various catalytic and photocatalytic transformations. Finally, the deposition of Cu NPs on SiNWs allowed the fabrication of affinity surfaces for specific capture of His-tag peptides and their subsequent analysis by matrix-free mass spectrometry.
Porosity Control and Transfer in Silicon Nanostructures through Electrochemical & Chemical Etching
Authors: Defforge Thomas , Vijayakumar Sanahan , Loni Armando , Chaix Arnaud , Sauldubois Audrey , Andreazza-Vignolle Caroline , Cunin Frederique , Di Renzo Francesco , Canham Leigh T , Gautier Gael 
Published: February 2020

Porous silicon particles and nanostructures are receiving growing interest from the scientific community. Two important parameters usually used to define a porous material are porosity and pore size. However, internal surface area and pore morphology are also of high importance, as they determine the material performances in many applicative domains such as Li-ion batteries (1), catalysis, separation, drug delivery (2) etc.
High surface area porous silicon structures were prepared through silicon anodization in acidic HF electrolyte under galvanostatic control. The layers were then either taken off mechanically, forming powders, or subjected to a metal-assisted chemical etching (MaCE) post-treatment to produce high aspect ratio silicon nanowires through the depth of the porous film.
In the first scenario, careful attention was paid to the electrolyte composition in order to increase the internal surface area of the powders. In acidic solutions (i.e. HF mixed with strong acids such as HCl or H2SO4), powders with surface area exceeding 850 m²/g were achieved by lowering the average pore size to around 3 nm, whilst maintaining moderate porosity (~ 65%) (3).
In the latter scenario, MaCE (4) on porous silicon thin films facilitated the transfer of the parameters defining the mesoporous framework (porosity, pore diameter, surface area, pore orientation) from the thin film to high aspect ratio nanowires. This consisted of periodic modulation of the porosity with depth and applying MaCE post-treatment as illustrated by electron microscopy images, below, the nanowires clearly displayed the porosity gradient of the original porous silicon thin film.
The control of both anodization conditions, through an accurate choice of the silicon wafer doping type and level and electrolyte composition, to achieve ultra-high surface area porous powder, and porous layer post-treatment such as MaCE, to convert the porous framework from thin film to nanowires, provide new and promising opportunities in many application fields.

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Z.Huang, N.Geyer, P.Werner, J.de Boor, U.Gosele. Adv.Mater23 : 285 (2011)

Figure 1
(Invited) Electrochemical Preparation and Processing of Porous Silicon Nanoparticles for Targeted, Self-Reporting Drug Delivery
Authors: Sailor M. J. 
Published: February 2020

The electronic and optical properties that make the semiconductor silicon so useful for solid-state devices such as solar cells and microelectronics can also be harnessed for biological applications—in particular in vivo imaging and drug delivery. This presentation will discuss the chemistry and photochemistry of nanostructured porous silicon. The intrinsic photoluminescence that derives from quantum confinement and surface defect states provides a non-toxic and biodegradable luminescent probe for in vivo and in vitro imaging. The luminescence properties are intimately tied to the surface chemistry of the material, and the relatively long (microseconds) excited state lifetime of this material can be harnessed for time-gated imaging or chemical sensing. Applications in sensing, drug delivery, and targeted therapies will be discussed.
(Invited) Current Filamentation in Rram As Measured By High Speed Electrical Thermometry
Authors: Bain James A. , Sharma Abhishek , Skowronski Marek 
Published: February 2020

In this paper, we review our method of measuring the local device temperature in oxide RRAM cells by taking high speed pulsed electrical measurements of the device I-V characteristics. These measurements are taken sufficiently fast (< 5 ns) as to avoid local joule heating of the device, revealing the device’s “true” room temperature I-V characteristics. Repeating these measurements as a function of stage temperature allows the construction of a unique I-V-T map, where T is the device temperature. This calibrated map can then be used under more general I-V interrogation where self-heating is present to extract the actual device temperature from I-V measurements. This method has been applied to a variety of RRAM-type oxide switches, including TiO2, Ta2O5 and HfO2 devices. Both pristine devices (prior to the initial filament forming breakdown step) as well as devices that have a filament present and can be repeatedly switched between high and low resistance states have been examined. The measurements show that internal device temperatures can range from 50ºC to 400ºC at the onset of the electroforming event, with temperatures above 600ºC when the event is completed. During switching, temperatures within the filaments peak at 300ºC-400ºC during each switching event. Temperature dependent resistivity measurements reveal that the filament has a metallic nature in materials like TiO2 (resistivity increases with increasing temperature) with a resistivity value of approximately 6000 nΩ-m. The surrounding matrix is semiconducting (resistivity decreases strongly with increasing temperature) and displays highly non-linear I-V curves. By combining the above thermometry technique with modeling of the thermal transport in the filament and its surrounding region, it is possible to get an estimate of the filament radius. Specifically, a unique filament radius is determined that self-consistently explains both the filament I-V behavior and slope of filament temperature vs dissipated power (the filament thermal resistance, Rth
). This analysis reveals that the filaments in oxide RRAM memory devices are typically 1 nm in diameter and have a hot zone around them that grows to several nm during the switching event. We are also able to apply this same analysis to the transient (i.e. non-permanent) current filaments that form prior to the permanent filament, during so-called threshold switching events. These measurements confirm for oxides the same picture reported in the literature for chalcogenide phase change materials many years ago - that a transient electrical current filament precedes the permanent structural one in these devices. Moreover, it is most likely that the heating within this transient filament that allows for the microstructural arrangement of the oxide atoms that results in a permanent conducting filament able to participate in the memory switching event.
(Invited) Integration Challenges of Ferroelectric Hafnium Oxide Based Embedded Memory
Authors: Müller Johannes , Polakowski Patrick , Paul Jan , Riedel Stefan , Hoffmann Raik , Drescher Maximilian , Slesazeck Stefan , Müller Stefan , Mulaosmanovic Halid , Schröder Uwe , Mikolajick Thomas , Flachowsky Stefan , Erben Elke , Smith Elliot , Binder Robert , Triyoso Dina , Metzger Joachim , Kolodinski Sabine 
Published: February 2020

System on chip (SoC) embedded memory solutions promise small form factors and high operating speed, as well as a high energy and cost efficiency. Single cell scalability and basic memory parameters such as data retention, cycling endurance and disturb characteristics on array level are important aspects in stand-alone memory development and can serve as a guideline for embedded solutions. However, one of the key aspects in embedded memory development is compatibility of the memory technology to its underlying complementary metal oxide semiconductor (CMOS) platform. This includes the voltage requirements for logic and memory operation, the need for additional lithographic steps and minimally CMOS invasive integration efforts, as well as the introduction of new materials and related contamination concerns. Especially in state of the art high-k metal gate (HKMG) CMOS technologies at minimum feature size (F) these aspects proof rather challenging when searching for a suitable embedded memory solution. As a consequence most approaches result in large memory cells of multiple F2 or leave a BEoL integration of the memory cell as the only viable option.
With the introduction of ferroelectric hafnium oxide, however, a scalable one-transistor (1T) memory solution derived from the conventional HKMG transistor was presented for the 2X nm node. The therewith close resemblance of the memory and logic transistor appears ideally suited for combining nonvolatile data storage and logic circuitry on the same chip. Nevertheless, in order to fulfill these expectations and to ease manufacturing issues this resemblance has to be as close as possible. In the context of a minimally invasive memory integration strategy this means that ideally the ferroelectric hafnium oxide based memory transistor has to adapt to the HKMG transistor in terms of thermal budget and post treatments, vertical and lateral dimensions, the use of stress engineering, as well as metal gate and work function engineering. Based on experimental gate first transistor and metal insulator metal (MIM) capacitor data these aspects together with embedded memory requirements will be analyzed and critically discussed.
(Keynote) Status and Challenges in Spin-Transfer Torque MRAM Technology
Authors: Krounbi Mohamad , Nikitin Vladimir , Apalkov Dmytro , Lee Jangeun , Tang Xueti , Beach Robert , Erickson Dustin , Chen Eugene 
Published: February 2020

Spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising candidate for next generation non-volatile memory due to a combination of fast speed, high endurance, excellent scalability, and ease of integration with the standard CMOS processes. While feasibility demonstrations used magnetic tunnel junction (MTJ) devices with an in-plane magnetization, significant advances in materials allowed implementation of the perpendicular MTJ design, which provides the best long-term scalability for STT-MRAM beyond 20 nm. Despite significant progress, there are many remaining hurdles in the productization of STT-MRAM. They are stemming from a set of requirements imposed on the MTJ performance: simultaneously low writing current/voltage and high thermal stability, high magneto-resistance at low RA (resistance and area product) value, low error rates and high endurance cycles. We will discuss the inter-dependencies of these parameters, and show how they are affected by varying magnetic properties of the MTJ stack layers. In particular, we study impact of the free layer anisotropy, magnetic moment, thickness, and Gilbert damping on writing current and thermal stability. In this presentation, we report our progress in meeting these requirements and our development approaches for future challenges.
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Mohamad Krounbi has over 25 years of experience in magnetic recording technology and recording head process and design innovations. While at IBM from 1978 to 1997, he played a leading role in the development and production of the magneto resistive heads from MR to GMR and TMR generations of products. Mohamad contributed to major breakthroughs in design, process, and integration of heads and media in the HDD industry. He held executive positions at IBM, Western Digital, and Hitachi Global Storage Technology (HGST). Mohamad holds over 50 US patents and co-authored numerous scientific publications in magnetic recording and fundamental materials and polymer research. He received numerous outstanding innovation and contribution awards while at IBM and was elected to the IBM academy of technology in 1995. At HGST he was awarded the President’s technology award for the development and launch of the first perpendicular magnetic recording product. In 2010, Mohamad joined Grandis, Inc. as the CTO and Senior Vice President of technology development and operations. Mohamad is currently the CTO and Senior Vice President of Samsung’s New Memory Technology Laboratory in the US ( NMT Lab). Mohamad has a BS in Physics from Hagazian College in Beirut Lebanon and a MS in Physics from San Jose State University.
(Invited) Resistive Random Access Memory for Storage Class Applications
Authors: Jo Sung Hyun , Kumar Tanmay 
Published: February 2020

Resistive RAM (RRAM) is one of the most promising emerging nonvolatile memory technologies thanks to fast operation, superior scalability, low power consumption and potential for 3D stacking. From an architectural point of view, 1T1R architecture is suitable for embedded memory applications while 1S1R based cross-point architecture is suited to high density memory applications. In the 1S1R based cross-point integration, however, the suppression of sneak current paths has been the major technical barrier for the high density RRAM.
We show that the sneak path challenge has been overcome by utilizing a Field Assisted Superlinear Threshold (FAST) selector [1]. The FAST selector device uses an insulating amorphous material which provides volatile switching at critical electric field. Excellent selector performance is presented, including high selectivity of > 107, sharp switching slope of < 5mV/dec., and large endurance of > 1011. The low fabrication temperature (≤300°C) of the FAST selector allows 3D stacking of 1S1R memory layers. It is also demonstrated that a volatile switch based selector has inherent benefits such as low voltage overhead for 1S1R integration and high read voltage margin.
For the 1S1R demonstration, electrochemical metallization RRAM with a sub-5nm filament is utilized. The RRAM device offers a self-current-limiting feature during the program operation [2]. The self-limited program obviates the need for external current compliance, which can increase the number of concurrent programs in the 1S1R cross-point architecture with reduced power consumption and increased reliability benefits. Furthermore, the hold voltage property (snap-back behavior) of a FAST selector allows novel sensing techniques such as Resistance Ratio Amplification (RRA) which amplifies the intrinsic ON/OFF ratio of RRAM by a factor of > 104 [2]. Besides the direct advantage of increased memory ON/OFF ratio, the RRA technique also reduces BER and increases read bandwidth of the RRAM array. The integrated self-current-limited RRAM with FAST selector enables the high density and high performance 1S1R RRAM technology.
References
[1] S. H. Jo, T. Kumar, S. Narayanan, W. D. Lu and H. Nazarian, “3D-stackable crossbar resistive memory based on field assisted superlinear threshold (FAST) selector,” IEDM, 2014.
[2] S. H. Jo, T. Kumar, C. Zitlaw and H. Nazarian, “Self-limited RRAM with ON/OFF resistance ratio amplification,” VLSI Tech. Symp. 2015.

Figure 1
High Performing Semitransparent Graphene/BiFe0.95Si0.05O3/ITO Ferroelectric Photovoltaic Device
Authors: Gupta Surbhi , Katiyar Rajesh K. , Medwal Rohit , Pavunny Shojan P. , Limbu Tej B. , Tomar Monika , Morell G , Gupta Vinay , Katiyar Ram S. 
Published: February 2020

Enriched and versatile room temperature multiferroic, BiFeO3 has been widely appreciated for future generation optoelectronic devices including light detectors, terahertz emitters, tunable solar cells, micro-sensors, and thin-film transistors with additional degree of magnetic and electric control. Moreover, literature also highlights its adjustable electrical, optical, and ferroelectric properties by doping with selected elements. We hereby report substantial photovoltaic response of semitransparent graphene/semiconductor Si doped BiFeO3 hetero-structure fabricated on In2O3 doped SnO2 coated glass substrates using bottom up spin coating technique considering the commercial aspect. The short circuit current density Jsc and open circuit voltage VOC were measured as 75 mA/cm2 and 0.45 V, respectively, with approximately 3 orders of increase in current density under standard AM1.5 (100 mW/cm2) illumination at room temperature. For the first time crystal structure, optical band gap, leakage behavior, ferroelectric and magnetic characteristics of 5 mol% Si doped BiFeO3 polycrystalline thin films is investigated and reported. Quick and reproducible transient response of JSC and VOC with (ton,toff <100 ms) for more than 50 consecutive cycles establishes high scale of endurance and retentivity. Further, high stability (95%) of photo-response of chemically derived photovoltaic cell over a period of 16 weeks was achieved in ambient condition. This work establishes BiFe0.95Si0.05O3 as a high performing multiferroic material with complementary graphene and ITO as electrodes for self-powered oxide electronics.
Perovskite Based Solar Cells with Multi-Walled Carbon Nanotubes (MWCNTs)/Carbon Back Contact
Authors: Abdel-Fattah Tarek M , Ebrahim Shaker , Ramadan Wegdan , Nofal Mohammed , Soliman Moataz 
Published: February 2020

The search for alternative energy solutions is currently a leading research area and will remain so for the foreseeable future, and photovoltaics (PV) are a key technology for a sustainable energy supply. The impressive properties of perovskites solar cells could ultimately boost efficiencies as close as commercial costly single-crystal silicon. That could make solar electricity as cheap as electricity produced from coal or natural gas. Solution base process of highly crystalline organic–inorganic hybrid perovskite CH3NH3PbI3-xClx pigment with promising visible-to-near-infrared absorptivity and electrical properties has attracted great attention to be used as a sensitizer for mesosuper structured solar cells.
In this work we fabricated cell structure of FTO/TiO2/ CH3NH3PbI3-xClx/ MWCNTs-carbon as shown below in the schematic diagram (Figure 1). TiO2 compact layer improved adhesion between the meso-TiO2 layer and FTO surface to facilitate electron transfer and enhanced the efficiency of the photoelectrical conversion. Multi-walled carbon nanotubes/carbon paste back contact was used with polymeric binder. The output cell parameters achieved from current-voltage curve (Figure 2) were open circuit voltage of 0.72 V, short circuit current density of 11.62 mA/cm2, fill factor of 0.27 and power conversion efficiency of 2.3%.

Figure 1