Study on the Effects of Post-Deposition Annealing on SiO2/β-Ga2O3 MOS Characteristics
Authors: Kita Koji , Suzuki Eiki , Mao Qin 
Published: February 2020

MOSFETs on β-Ga2O3 is a new candidate of high-efficient and cost-effective alternative option for high-voltage power devices. In various studies, ALD-deposited Al2O3 films have been often employed as the gate dielectrics, however, it would be reasonable to replace with SiO2 if one considers the conduction-band offset against β-Ga2O3, which is limited to 1.5−1.6 eV [1] for Al2O3 but can be beyond 2 eV for the case of SiO2. In this study we investigated the effects of post-deposition-annealing (PDA) on the characteristics of SiO2/β-Ga2O3 MOS interface, especially focusing of the impact of the annealing temperature and ambient.
β-Ga2O3 (001) wafers with ~2×1016 cm-3 n-type doped epitaxial layers were cleaned in diluted HF solution. Then SiO2 films were deposited by electron-beam evaporation of Si in O2 ambient of ~1×10-2 Pa, followed by PDA in 1 atm-O2 at various temperatures from 600 to 1000℃. Au was evaporated as gate electrode to form MOS capacitors. For some samples an additional annealing at 400℃ was conducted in various ambient (O2, N2, and diluted H2).
Nearly-ideal C-V characteristics with negligible hysteresis were obtained for the MOS capacitor fabricated with O2-PDA at 1000℃. The suppressed frequency dispersion indicates a successful formation of MOS interface with low interface defect densty. The energy profiles of interface state density (Dit) were determined by conductance method for the samples with different PDA conditions. Lower Dit was achieved for higher PDA temperatures, down to ~1010 cm-3 at the energy level of EC−0.2 eV. These values are significantly lower than typically reported ones so far on β-Ga2O3 [2, 3]. When we see the hysteresis width (ΔVhys) of C-V curves, defined by the difference between the voltages to observe the flatband-capacitance, the smaller ΔVhys was observed for the samples annealed at higher temperatures. The additional annealing at low temperature at 400℃ works for further reduction of ΔVhys to less than 1 mV/nm, irrespective of the annealing ambient, O2, N2, or diluted H2. After such low-temperature annealing at 400℃, I-V characteristics clarifed that these stacks resulted in the dielectric breakdown fields around 7−8 MV/cm, even though the process has not been optimized for the suppression of the leakage current.
Next the flatband voltage (VFB) shift was compared for the samples annealed in different conditions. As we expected, O2-PDA resulted in VFB close to the ideal value estimated from the physical properties of Au and Ga2O3, probably because the fixed charge density at the interface would be minimized. However, PDA in N2 at 1000℃ resulted in a negative shift of VFB, which shows the introduction of positive fixed charges in the stack. The additional annealing in diluted H2 at 400℃ was also induced a negative VFB shift, whereas such additional annealing at the same temperature in O2 or N2 does not cause a significant shift. From these results it was suggested that oxygen deficiency introduction near the interface will induce positive fixed charges.
Acknowledgement: This work was partly done in collaboration with JST, Center for Low Carbon Society Strategy.
References:
(1) T. Kamimura et al., Appl. Phys. Lett. 104, 192104 (2014).
(2) K. Zeng et al., IEEE Electron Device Lett., 37, 906, (2016).
(3) T. Kamimura et al., Jpn. J. Appl. Phys., 55, 1202B5 (2016).