num_pages: 179
description: Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
language: English
title: Formal Semantics and Proof Techniques for Optimizing VHDL Models
titlecomplete: Formal Semantics and Proof Techniques for Optimizing VHDL Models
publisher: Springer