# RTL Implementation Task: AES Cipher Control

## Environment

You are working in `/home/dev/workspace/code/`. Implement these 4 tightly-coupled modules:
- `rtl/aes_cipher_control.sv`
- `rtl/aes_cipher_control_fsm.sv`
- `rtl/aes_cipher_control_fsm_p.sv`
- `rtl/aes_cipher_control_fsm_n.sv`

All other modules are pre-implemented. Read `spec/aes_standard.pdf` and `pkg/aes_pkg.sv` for reference.

## Redundant FSM Pattern

OpenTitan uses redundant positive/negative rail FSMs for fault tolerance:

- **`_fsm_p.sv`**: The positive rail — contains the actual state machine logic
- **`_fsm_n.sv`**: The negative rail — instantiates `_fsm_p` but inverts specific control signals (those using `sp2v_e` encoding) through `prim_buf` barriers. Ports use `_ni`/`_no` suffixes for inverted signals.
- **`_fsm.sv`**: The wrapper — instantiates both `_p` and `_n`, compares their outputs, and raises `alert_o` on mismatch. Also buffers inputs/outputs through `prim_buf`.
- **`aes_cipher_control.sv`**: Top-level cipher control that instantiates the FSM wrapper and provides the register/signal mapping.

## Key Behaviours

- Sequences AES cipher rounds based on key length (10/12/14 rounds)
- Triggers SubBytes, ShiftRows, MixColumns, and KeyExpand each round
- Tracks the round counter and signals when the final round is complete
- Supports decryption key generation mode (`dec_key_gen`)
- Handles PRNG reseed requests and key/data clearing between operations
- Compares positive and negative rail outputs to detect faults

### Critical: Required Internal Signals (SVA bind references)

The testbench binds SVA assertions that reference these internal signals by hierarchical path. They **must exist** or elaboration will fail:

- In `aes_cipher_control.sv`: expose a `rnd_ctr` output or wire (4-bit round counter) — the parent `aes_cipher_core` SVAs reference it as `u_aes_cipher_control.rnd_ctr`
- In `aes_cipher_control_fsm_p.sv`: the round counter register should be named `rnd_ctr` or `rnd_ctr_q`

Read `rtl/aes_cipher_core.sv` to see how `aes_cipher_control` is instantiated.

## Time Budget

You have **20 minutes**. Prioritize:
1. Get a compiling implementation first (`make compile` must pass with zero errors)
2. Drive all outputs to valid values (no X)
3. Then iterate on correctness

## Build Commands

```bash
cd /home/dev/workspace/code/run
make compile
```