# RTL Implementation Task: ADC Controller Full IP

## Environment

You are working in `/home/dev/workspace/code/`.

```
rtl/          -- Implement the 3 core ADC controller RTL modules here
prim/         -- OpenTitan primitive library (read-only)
tlul/         -- TileLink-UL bus modules (read-only)
pkg/          -- ADC / AST / LC / top package files (read-only)
spec/         -- ADC controller specification documents
run/          -- Makefile + filelist for elaboration feedback
```

## Task

Implement these three behavioural modules with the provided exact port lists:

1. `rtl/adc_ctrl_core.sv` — filter evaluation, wakeup generation, and integration in the AON clock domain
2. `rtl/adc_ctrl_fsm.sv` — oneshot / LP / NP sampling FSM
3. `rtl/adc_ctrl_intr.sv` — AON-to-core interrupt CDC and interrupt-status logic

The following files are provided and must not be modified: `rtl/adc_ctrl.sv`, `rtl/adc_ctrl_reg_top.sv`.

## Specs

- `spec/theory_of_operation.md`
- `spec/registers.md`
- `spec/interfaces.md`
- `spec/programmers_guide.md`
- `spec/adc_overview.svg`
- `spec/adc_ctrl_testplan.hjson`
- `pkg/adc_ctrl_pkg.sv`
- `pkg/adc_ctrl_reg_pkg.sv`
- `pkg/ast_pkg.sv`

## Hierarchy

Preserve these DV-visible instance names:
- `u_reg`
- `u_adc_ctrl_core`
- `u_adc_ctrl_core.u_adc_ctrl_fsm`
- `u_adc_ctrl_core.u_adc_ctrl_intr`
- `u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync`

## Build

```bash
cd /home/dev/workspace/code/run
make compile
```