# RTL Implementation Task: ADC Controller Interrupt Module

## Environment

You are working in `/home/dev/workspace/code/`:

```
rtl/          -- adc_ctrl_intr.sv is a stub; all other RTL is provided and must not be modified
prim/         -- OpenTitan primitive library (read-only)
tlul/         -- TileLink-UL bus modules (read-only)
pkg/          -- Packages: adc_ctrl_reg_pkg.sv, adc_ctrl_pkg.sv, ast_pkg.sv, lc/top (read-only)
spec/         -- ADC controller specification documents
run/          -- Makefile + filelist for elaboration feedback
```

## Your Task

Implement `rtl/adc_ctrl_intr.sv` — the interrupt aggregation and AON→core-clock CDC module for OpenTitan's ADC controller.

The module collects filter-match and FSM-transition events from the `clk_aon_i` domain, hands them across to `clk_i` via `prim_sync_reqack`, updates `adc_intr_status` appropriately (including the non-AON `oneshot` source), and drives the Status-type `match_pending` interrupt through `prim_intr_hw`.

## Specs

Read these before writing RTL:

- `spec/theory_of_operation.md` — interrupt semantics, debounce/match pipeline.
- `spec/registers.md` — `intr_state`/`intr_enable`/`intr_test`, `adc_intr_status`, `adc_intr_ctl`.
- `spec/programmers_guide.md` — software interrupt handling.
- `spec/adc_ctrl_testplan.hjson` — verification intent.
- `pkg/adc_ctrl_reg_pkg.sv` — register struct typedefs; `NumAdcFilter`.
- `prim/prim_sync_reqack.sv` and `prim/prim_intr_hw.sv` — primitives to use.

## Hierarchy Constraint

The verification environment binds coverage to fixed hierarchical paths. Preserve the module name `adc_ctrl_intr` and its oracle port list, and name the `prim_sync_reqack` instance `u_match_sync`.

## Build

```bash
cd /home/dev/workspace/code/run
make compile
```

Inspect `compile_log/compile.log` and fix elaboration errors before submission.