# RTL Implementation Task: ADC Controller Sampling FSM

## Environment

You are working in `/home/dev/workspace/code/`:

```
rtl/          -- adc_ctrl_fsm.sv is a stub; all other RTL is provided and must not be modified
prim/         -- OpenTitan primitive library (read-only)
tlul/         -- TileLink-UL bus modules (read-only)
pkg/          -- Packages: adc_ctrl_reg_pkg.sv, adc_ctrl_pkg.sv (fsm_state_e), ast_pkg.sv, lc/top (read-only)
spec/         -- ADC controller specification documents
run/          -- Makefile + filelist for elaboration feedback
```

## Your Task

Implement `rtl/adc_ctrl_fsm.sv` — the sampling state machine for OpenTitan's ADC controller.

The FSM sequences ADC channel sampling across three operating modes (oneshot, low-power periodic, normal-power continuous), drives `adc_o.pd` and `adc_o.channel_sel`, and produces the `adc_ctrl_done` / `oneshot_done` / `aon_fsm_trans` event pulses consumed by `adc_ctrl_core`. All logic runs in `clk_aon_i`.

## Specs

Read these before writing RTL:

- `spec/theory_of_operation.md` — FSM behaviour, sampling flows, filter/debounce pipeline.
- `spec/registers.md` — register fields controlling the FSM (`adc_pd_ctl`, `adc_en_ctl`, `adc_sample_ctl`, `adc_lp_sample_ctl`, `adc_fsm_rst`).
- `spec/interfaces.md` — `adc_ast_req_t`/`adc_ast_rsp_t` handshake with the AST ADC.
- `spec/programmers_guide.md` — intended software use.
- `spec/adc_overview.svg` — block diagram.
- `spec/adc_ctrl_testplan.hjson` — verification intent.
- `pkg/adc_ctrl_pkg.sv` — the `fsm_state_e` enum you must use.
- `pkg/adc_ctrl_reg_pkg.sv` — register struct typedefs.

## Hierarchy Constraint

The verification environment binds coverage to fixed hierarchical paths. Keep the module name `adc_ctrl_fsm` and its oracle port list unchanged — do not rename ports or combine this module into another.

## Build

```bash
cd /home/dev/workspace/code/run
make compile
```

Inspect `compile_log/compile.log` and fix elaboration errors before submission.