# RTL Implementation Task: ADC Controller Core

## Environment

You are working in `/home/dev/workspace/code/`:

```
rtl/          -- adc_ctrl_core.sv is a stub; all other RTL is provided and must not be modified
prim/         -- OpenTitan primitive library (read-only)
tlul/         -- TileLink-UL bus modules (read-only)
pkg/          -- Packages: adc_ctrl_reg_pkg.sv, adc_ctrl_pkg.sv, ast_pkg.sv, lc/top (read-only)
spec/         -- ADC controller specification documents
run/          -- Makefile + filelist for elaboration feedback
```

## Your Task

Implement `rtl/adc_ctrl_core.sv` — the integrating core of OpenTitan's ADC controller.

The core evaluates the 8 filter pairs against the two channel samples, writes `filter_status` and `adc_chn_val[*]`, generates `wkup_req_o` from filter + wakeup-enable state, and instantiates the sampling FSM and interrupt submodule. All filter evaluation runs in `clk_aon_i`.

## Specs

Read these before writing RTL:

- `spec/theory_of_operation.md` — filter/debounce semantics, wakeup generation, LP/NP pipeline.
- `spec/registers.md` — filter registers (`adc_chn0_filter_ctl[]`, `adc_chn1_filter_ctl[]`), `filter_status`, `adc_wakeup_ctl`, `adc_chn_val[*]`.
- `spec/interfaces.md` — AST ADC handshake.
- `spec/programmers_guide.md` — intended software use.
- `spec/adc_overview.svg` — block diagram.
- `spec/adc_ctrl_testplan.hjson` — verification intent.
- `pkg/adc_ctrl_reg_pkg.sv` — register struct typedefs; `NumAdcFilter`, `NumAdcChannel`.
- `pkg/adc_ctrl_pkg.sv` — `fsm_state_e`.

## Hierarchy Constraint

The verification environment binds coverage to fixed hierarchical paths. Preserve the module name `adc_ctrl_core` and its oracle port list, and instantiate the FSM and interrupt submodules as `u_adc_ctrl_fsm` and `u_adc_ctrl_intr` respectively.

## Build

```bash
cd /home/dev/workspace/code/run
make compile
```

Inspect `compile_log/compile.log` and fix elaboration errors before submission.