{"size":1811,"ext":"bsv","lang":"Bluespec","max_stars_count":46.0,"content":"\/\/ Copyright (c) 2016 Cornell University.\n\n\/\/ Permission is hereby granted, free of charge, to any person\n\/\/ obtaining a copy of this software and associated documentation\n\/\/ files (the \"Software\"), to deal in the Software without\n\/\/ restriction, including without limitation the rights to use, copy,\n\/\/ modify, merge, publish, distribute, sublicense, and\/or sell copies\n\/\/ of the Software, and to permit persons to whom the Software is\n\/\/ furnished to do so, subject to the following conditions:\n\n\/\/ The above copyright notice and this permission notice shall be\n\/\/ included in all copies or substantial portions of the Software.\n\n\/\/ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\/\/ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\/\/ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n\/\/ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n\/\/ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n\/\/ ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n\/\/ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n\/\/ SOFTWARE.\n\nimport Stream::*;\nimport GetPut::*;\nimport Pipe::*;\nimport StructDefines::*;\n\ntypeclass GetMacTx#(type a);\n function Get#(ByteStream#(8)) getMacTx(a t);\nendtypeclass\n\ntypeclass GetMacRx#(type a);\n function Put#(ByteStream#(8)) getMacRx(a t);\nendtypeclass\n\ntypeclass GetWriteClient#(type a);\n function Get#(ByteStream#(16)) getWriteClient(a t);\nendtypeclass\n\ntypeclass GetWriteServer#(type a);\n function Put#(ByteStream#(16)) getWriteServer(a t);\nendtypeclass\n\ntypeclass GetMetaIn#(type a);\n function PipeIn#(MetadataRequest) getMetaIn(a t);\nendtypeclass\n\ntypeclass SetVerbosity#(type a);\n function Action set_verbosity(a t, int verbosity);\nendtypeclass\n\ntypedef 128 ChannelWidth;\n\n","avg_line_length":33.537037037,"max_line_length":70,"alphanum_fraction":0.7598012148} {"size":1124,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"\/\/ For Verilog:\n\/\/ We expect the rules to schedule with methods first,\n\/\/ in interface definition order, then with user rules\n\/\/ in the order they are elaborated (m2, m1, m3, done).\n\/\/\n\/\/ For Bluesim:\n\/\/ We expct the methods to be ordered by the order of\n\/\/ actions in the calling rule (m3, m2, m1, done).\n\nimport Clocks::*;\n\ninterface Ifc;\n method Action m2();\n method Action m1();\n method Action m3();\nendinterface\n\n(* synthesize *)\nmodule sysMethodOrder2();\n Ifc sub <- mkSub();\n\n rule foo;\n sub.m3();\n sub.m2();\n sub.m1();\n endrule\n\nendmodule\n\n(* synthesize *)\nmodule mkSub(Ifc);\n Reg#(Bool) rg1 <- mkReg(True);\n Reg#(Bool) rg2 <- mkReg(True);\n Reg#(Bool) rg3 <- mkReg(True);\n\n ReadOnly#(Bool) in_reset <- isResetAssertedDirect();\n\n rule done if (!in_reset);\n $display(\"Exiting...\");\n $finish(0);\n endrule\n\n method Action m3();\n rg3 <= !rg3;\n $display(\"Changing r3\");\n endmethod\n\n method Action m1();\n rg1 <= !rg1;\n $display(\"Changing r1\");\n endmethod\n\n method Action m2();\n rg2 <= !rg2;\n $display(\"Changing r2\");\n endmethod\nendmodule\n","avg_line_length":19.3793103448,"max_line_length":55,"alphanum_fraction":0.6120996441} {"size":928,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"import GetPut::*;\nimport RandGlobal::*;\nimport RandGen::*;\n\n\/\/(* synthesize *)\nmodule mkRUser1(UserIfc);\n Reg#(Int#(8)) gap_counter();\n mkRegA#(0) the_gap_counter(gap_counter);\n Reg#(Nat) running_counter();\n mkRegA#(0) the_running_counter(running_counter);\n\n\/\/ GetCPut#(4,Bit#(6)) inFifo();\n\/\/ mkGetCPut the_inFifo(inFifo);\n GetPut#(Bit#(6)) inFifo();\n mkGetPut the_inFifo(inFifo);\n Get#(Bit#(6)) supply = inFifo.fst;\n\n Reg#(Bit#(6)) x();\n mkRegA#(0) the_x(x);\n\n Component2 cmp2;\n cmp2 =\n (interface Component2;\n method value;\n return x;\n endmethod\n endinterface);\n\n \n\n rule consume;\n running_counter <= running_counter + 1;\n gap_counter <= (gap_counter==0 ? 2 : gap_counter - 1);\n if (gap_counter == 0)\n\taction\n\t Bit#(6) xx <- supply.get();\n\t x <= xx;\n\t $display(\"%d: 1 gets %h\", running_counter, xx);\n\tendaction\n endrule\n \n return tuple2(inFifo.snd, cmp2);\nendmodule\n\n \n","avg_line_length":20.1739130435,"max_line_length":59,"alphanum_fraction":0.6293103448} {"size":488,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"interface ModIfc;\n method Action foo();\n method Action bar();\nendinterface\n\n(* synthesize *)\nmodule sysWrongArgType2 #((* port=\"INC\" *) parameter UInt#(4) n)\n (Clock clk2, ModIfc ifc);\n\n Reg#(UInt#(4)) r1 <- mkReg(0);\n Reg#(UInt#(4)) r2 <- mkReg(1, clocked_by clk2, reset_by noReset);\n\n method Action foo();\n $display(\"Foo: %h\", r1);\n r1 <= r1 + n;\n endmethod\n\n method Action bar();\n $display(\"Bar: %h\", r2);\n r2 <= r2 + n;\n endmethod\n\nendmodule","avg_line_length":21.2173913043,"max_line_length":67,"alphanum_fraction":0.5799180328} {"size":4217,"ext":"bsv","lang":"Bluespec","max_stars_count":9.0,"content":"\/\/ Copyright (c) HPC Lab, Department of Electrical Engineering, IIT Bombay\n\/\/\n\/\/ Permission is hereby granted, free of charge, to any person obtaining a copy\n\/\/ of this software and associated documentation files (the \"Software\"), to deal\n\/\/ in the Software without restriction, including without limitation the rights\n\/\/ to use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\n\/\/ copies of the Software, and to permit persons to whom the Software is\n\/\/ furnished to do so, subject to the following conditions:\n\n\/\/ The above copyright notice and this permission notice shall be included in\n\/\/ all copies or substantial portions of the Software.\n\n\/\/ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n\/\/ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n\/\/ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n\/\/ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n\/\/ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n\/\/ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n\/\/ THE SOFTWARE.\n\n\/\/ouput of adder is QUireWidth.. that is directly connected to output\npackage FDA_PNE_Quire;\n\n\/\/ -----------------------------------------------------------------\n\/\/ This package defines:\n\/\/\n\/\/ The different artefacts your package defines. One per line\n\/\/ with a small description per line, please.\n\/\/\n\/\/ -----------------------------------------------------------------\n\n\nimport FIFOF :: *;\nimport FIFO :: *;\nimport GetPut :: *;\nimport ClientServer :: *;\n\nimport Posit_Numeric_Types :: *;\nimport Posit_User_Types :: *;\nimport Extracter_Types\t:: *;\nimport Extracter\t:: *;\nimport Normalizer_Types\t:: *;\nimport Normalizer\t:: *;\nimport Adder_Types_fused_op \t:: *;\nimport Adder_fused_op\t\t:: *;\nimport Divider_Types_fda\t:: *;\nimport Divider_fda\t:: *;\nimport Common_Fused_Op :: *;\n\ninterface FDA_PNE_Quire ;\n interface Server #(InputQuireTwoPosit,Bit#(QuireWidth)) compute;\nendinterface\n\nmodule mkFDA_PNE_Quire(FDA_PNE_Quire);\n\nFIFO #(Bit#(QuireWidth)) ffO <- mkFIFO;\nFIFO #(Bit#(QuireWidth)) fftemp <- mkFIFO;\nExtracter_IFC extracter1 <- mkExtracter;\nExtracter_IFC extracter2 <- mkExtracter;\nDivider_IFC divider <- mkDivider;\nAdder_IFC adder <- mkAdder;\n\/\/get their extracted value and semd to divide\nrule rl_connect0;\n \tlet extOut1 <- extracter1.inoutifc.response.get();\n \tlet extOut2 <- extracter2.inoutifc.response.get();\n\tdivider.inoutifc.request.put (Inputs_md {\n\tsign1: extOut1.sign,\n\tnanflag1: 1'b0,\n \tzero_infinity_flag1: extOut1.zero_infinity_flag ,\n\tscale1 : extOut1.scale,\n\tfrac1 : extOut1.frac,\n\tsign2: extOut2.sign,\n\tnanflag2: 1'b0,\n \tzero_infinity_flag2: extOut2.zero_infinity_flag ,\n\tscale2 : extOut2.scale,\n\tfrac2 : extOut2.frac});\n\t\/\/ the fraction and scale are extended since operation is on quire\n\t\/\/using signed extension for scale value\n\t\/\/fraction value is normally extended but also shifted to maked the MSB the highest valued fraction bit\nendrule\n\/\/get the divide pipeline output and send to adder pipeline\nrule rl_connect1;\n \tlet divOut <- divider.inoutifc.response.get();\n \tlet in_quire = fftemp.first;\n\n\tadder.inoutifc.request.put(Inputs_a{q1 : Quire{sign : msb(in_quire),\n\t\t\t\t\t\t zero_infinity_flag : REGULAR,\n\t\t\t\t\t\t nan_flag : 1'b0,\n\t\t\t\t\t\t carry_int_frac : in_quire[valueOf(QuireWidthMinus2):0]} , q2 : divOut}); \n\tfftemp.deq;\nendrule\n\/\/get output from adder pipeline and send to Testbench\nrule rl_out;\n\tlet addOut <- adder.inoutifc.response.get ();\n\t\tffO.enq(addOut);\nendrule\ninterface Server compute;\n interface Put request;\n method Action put (InputQuireTwoPosit p);\n\t\tlet in_quire = p.quire_inp;\n\t\tlet in_posit1 = Input_posit {posit_inp : p.posit_inp1};\n\t \textracter1.inoutifc.request.put (in_posit1);\n\t \tlet in_posit2 = Input_posit {posit_inp : p.posit_inp2};\n\t \textracter2.inoutifc.request.put (in_posit2);\n\t\tfftemp.enq(in_quire);\n endmethod\n endinterface\n interface Get response = toGet (ffO);\nendinterface\n\nendmodule\n\n(* synthesize *)\nmodule mkPNE_test (FDA_PNE_Quire);\n let _ifc <- mkFDA_PNE_Quire;\n return (_ifc);\nendmodule\nendpackage: FDA_PNE_Quire\n","avg_line_length":35.4369747899,"max_line_length":104,"alphanum_fraction":0.7147261086} {"size":5348,"ext":"bsv","lang":"Bluespec","max_stars_count":1.0,"content":"\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/ (c) Copyright 2004, Bluespec Incorporated and Donald G. Baltus.\n\/\/\/\n\/\/\/ Time-stamp: <2004-06-22 11:13:58 baltus>\n\/\/\/\n\/\/\/ $Id$\n\/\/\/ $Source: $\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\n`ifdef BSV_NO_Z\n `define BSV_GENC True\n`else\n `define BSV_GENC genC\n`endif\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\npackage ZBusUtil;\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nexport ZBit;\nexport mkZBit;\nexport zBitGetWord;\nexport ConvertToZ(..);\nexport mkConvertToZ;\nexport ConvertFromZ(..);\nexport mkConvertFromZ;\nexport ResolveZ(..);\nexport mkResolveZ;\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nimport List::*;\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ntypedef struct {\n\t\tt word;\n\t\t} ZBit #(type t) deriving (Eq, Bits);\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nfunction ZBit#(t) mkZBit(t w);\n return ((ZBit { word : w}));\nendfunction\n\nfunction t zBitGetWord(ZBit#(t) wz);\n return (wz.word);\nendfunction\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ninterface ConvertToZ #(type i);\n method ZBit#(i) convert(i x1, Bool x2);\nendinterface\n\nimport \"BVI\" ConvertToZ = module vMkConvertToZ (ConvertToZ#(i))\n\t\t\t provisos (Bits#(i,si));\n default_clock clk();\n\t\t\t parameter width = valueOf(si); \n\t\t\t no_reset;\n\t\t\t method OUT convert(IN, CTL);\n schedule convert CF convert ;\n\t\t\t endmodule\n\nmodule mkConvertToZ(ConvertToZ#(i))\n provisos (Eq#(i), Bits#(i, si), Bits#(ZBit#(i), sz));\n ConvertToZ#(i) ifc;\n if (`BSV_GENC)\n ifc = interface ConvertToZ\n\t method convert(word, enable) ; \n\t\t return (bitToZBit(word, enable));\n\t endmethod\n\t endinterface;\n else begin\n ConvertToZ#(i) _a();\n vMkConvertToZ inst__a(_a);\n ifc = _a;\n end\n return (ifc);\nendmodule\n\nfunction ZBit#(i) bitToZBit(i word, Bool enable)\n provisos (Eq#(i), Bits#(i, si));\n return ((enable ? mkZBit(word) : mkZBit(unpack(0))));\nendfunction\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ninterface ConvertFromZ #(type i);\n method i convert(ZBit#(i) x1);\nendinterface\n\nimport \"BVI\" ConvertFromZ = module vMkConvertFromZ (ConvertFromZ#(i))\n\t\t\t provisos (Bits#(i,si));\n default_clock clk();\n\t\t\t parameter width = valueOf(si); \n\t\t\t no_reset;\n\t\t\t method OUT convert(IN);\n\t\t\t schedule convert CF convert;\n\t\t\t endmodule\n\nmodule mkConvertFromZ(ConvertFromZ#(i))\n provisos (Eq#(i), Bits#(ZBit#(i), sz), Bits#(i, si1));\n ConvertFromZ#(i) ifc;\n if (`BSV_GENC)\n ifc = interface ConvertFromZ\n\t method convert(k) ; \n\t\t return (zBitToBit(k));\n\t endmethod\n\t endinterface;\n else begin\n ConvertFromZ#(i) _a();\n vMkConvertFromZ inst__a(_a);\n ifc = _a;\n end\n return (ifc);\nendmodule\n\nfunction i zBitToBit(ZBit#(i) wz)\n provisos (Eq#(i));\n return (zBitGetWord(wz));\nendfunction\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ninterface ResolveZ #(type i);\n method ZBit#(i) resolve(ZBit#(i) x1, ZBit#(i) x2);\nendinterface: ResolveZ\n\nimport \"BVI\" ResolveZ = module vMkResolveZ (ResolveZ#(i))\n\t\t\tprovisos (Bits#(i,si));\n default_clock clk();\n\t\t\t parameter width = valueOf(si);\n\t\t\t no_reset;\n\t\t\t method OUT resolve(IN_0, IN_1);\n schedule resolve CF resolve;\n\t\t\tendmodule\n\nmodule mkResolveZ(ResolveZ#(i))\n provisos (Eq#(i), Bits#(i, si), Bits#(ZBit#(i), sz));\n ResolveZ#(i) ifc;\n if (`BSV_GENC)\n ifc = interface ResolveZ\n\t method resolve(in_0, in_1) ; \n\t\t return (resolveZ(in_0, in_1));\n\t endmethod\n\t endinterface;\n else begin\n ResolveZ#(i) _a();\n vMkResolveZ inst__a(_a);\n ifc = _a;\n end\n return (ifc);\nendmodule\n\nfunction ZBit#(i) resolveZ(ZBit#(i) wz_0, ZBit#(i) wz_1)\n provisos (Eq#(i), Bits#(i, si));\n return (mkZBit(unpack(pack(zBitGetWord(wz_0)) | pack(zBitGetWord(wz_1)))));\nendfunction\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nendpackage\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\n","avg_line_length":28.0,"max_line_length":80,"alphanum_fraction":0.4016454749} {"size":273,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"typedef struct {\n Bit#(32) a;\n Int#(32) b;\n Maybe#(UInt#(32)) c;\n} MyStruct deriving(Bits);\n \n(* synthesize *)\nmodule mkStructUninitErr4();\n\n MyStruct foo;\n if (False)\n foo.a = 0;\n\n rule test;\n $display(foo);\n $finish(0);\n endrule\n \nendmodule\n\n","avg_line_length":13.0,"max_line_length":28,"alphanum_fraction":0.5677655678} {"size":125,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"interface Ifc;\n method Bool r;\nendinterface\n\n(* synthesize *)\nmodule mkModparamResult #(parameter int r) (Ifc);\nendmodule\n\n","avg_line_length":13.8888888889,"max_line_length":49,"alphanum_fraction":0.736} {"size":204,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"\/\/ Valid attribute is wrong place\n\ninterface Foo ;\n method Action start () ;\n (* result = \"x1\" *)\n interface Reg#(int) rint ;\n method Action stop () ;\nendinterface\n\nmodule sysT2();\nendmodule\n\n","avg_line_length":15.6923076923,"max_line_length":33,"alphanum_fraction":0.637254902} {"size":156,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"typedef struct {\n function Action f(Bool x) _write;\n} MyStruct;\n\nfunction Action doWrite(MyStruct s, Bool b);\n action\n s <= b;\n endaction\nendfunction\n\n","avg_line_length":14.1818181818,"max_line_length":44,"alphanum_fraction":0.7051282051} {"size":49,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"typedef Foo Bar;\ntypedef Bar Foo;\n\nFoo x = 0;\n\n\n\n","avg_line_length":6.125,"max_line_length":16,"alphanum_fraction":0.6326530612} {"size":22503,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"import Real::*;\nimport FloatingPoint::*;\nimport StmtFSM::*;\nimport FShow::*;\nimport DefaultValue::*;\nimport Vector::*;\n\n \n \/\/ 0\n \/\/ -0\n \/\/ epsilon (normalized)\n \/\/ -epsilon (normalized)\n \/\/ epsilon (denormalized)\n \/\/ -epsilon (denormalized)\n \/\/ 2\n \/\/ 3\n \/\/ 2.3\n \/\/ -2.3\n \/\/ infinity\n \/\/ -infinity\n \/\/ qnan\n \/\/ snan\n \/\/ large number\n \/\/ -large number\n \/\/ max normalized\n \/\/ min normalized\n \/\/ max denormalized\n \/\/ min denormalized\n\n(* synthesize *)\nmodule sysArith();\n Reg#(FP16) zero <- mkReg(fromInteger(0));\n \n Vector#(7, FP16) boundaryvals;\n boundaryvals[0] = infinity(True);\n boundaryvals[1] = fromInteger(-1);\n boundaryvals[2] = -fromInteger(0);\n boundaryvals[3] = fromInteger(0);\n boundaryvals[4] = fromInteger(1);\n boundaryvals[5] = infinity(False);\n boundaryvals[6] = snan();\n\n Stmt test = \n seq\n delay(10);\n \/\/ verify addition\n action\n\t FP16 a, b;\n\t \n\t \/\/ verify carry out bit set\n\t \/\/ 2 + 2 = 4\n\t a = fromInteger(2);\n\t b = fromInteger(2);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"2 + 2 = \", fshow(a+b));\n\n\t \/\/ 2 + -2 = 0\n\t a = fromInteger(2);\n\t b = fromInteger(-2);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"2 + -2 = \", fshow(a+b));\n\n\t \/\/ -2 + 2 = 0\n\t a = fromInteger(-2);\n\t b = fromInteger(2);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"-2 + 2 = \", fshow(a+b));\n\n\t \/\/ -2 + -2 = -4\n\t a = fromInteger(-2);\n\t b = fromInteger(-2);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"-2 + -2 = \", fshow(a+b));\n\t \n\t \/\/ 100 + 103\n\t a = fromInteger(100);\n\t b = fromInteger(103);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"100 + 103 = \", fshow(a+b));\n\n\t \/\/ 65504 + 32768 (overflow)\n\t a = fromInteger(65504);\n\t b = fromInteger(32768);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"65504 + 32768 = \", fshow(a+b));\n\n\t \/\/ -65504 + -32768 (overflow)\n\t a = fromInteger(-65504);\n\t b = fromInteger(-32768);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"-65504 + -32768 = \", fshow(a+b));\n\t \n\t \/\/ \/\/ verify subnormal addition\n\n\t \/\/ 5.960464478e-8 + 5.960464478e-8\n\t a = fromReal(5.960464478e-8);\n\t b = fromReal(5.960464478e-8);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"5.96e-8 + 5.96e-8 = \", fshow(a+b));\n\t \t \n\t \/\/ -5.960464478e-8 + -5.960464478e-8\n\t a = fromReal(-5.960464478e-8);\n\t b = fromReal(-5.960464478e-8);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"-5.96e-8 + -5.96e-8 = \", fshow(a+b));\n\t \n\t \/\/ 5.960464478e-8 + -5.960464478e-8\n\t a = fromReal(5.960464478e-8);\n\t b = fromReal(-5.960464478e-8);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"5.96e-8 + -5.96e-8 = \", fshow(a+b));\n\t \n\t \/\/ -5.960464478e-8 + 5.960464478e-8\n\t a = fromReal(-5.960464478e-8);\n\t b = fromReal(5.960464478e-8);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"-5.96e-8 + 5.96e-8 = \", fshow(a+b));\n\t \n\t \/\/ verify case where normalization is necessary\n\t \n\t \/\/ 100 + -103\n\t a = fromInteger(100);\n\t b = fromInteger(-103);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"100 + -103 = \", fshow(a+b));\n\n\t \/\/ -100 + 103\n\t a = fromInteger(-100);\n\t b = fromInteger(103);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"-100 + 103 = \", fshow(a+b));\n\n\t \/\/ 1e-7 + 2e-6\n\t a = fromReal(1e-7);\n\t b = fromReal(2e-6);\n\t FP16 c = fromReal(2.1e-6);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"1e-7 + 2e-6 = \", fshow(a+b));\n\t $display(\"c=\", fshow(c));\n\t \t \n\t \/\/ 100 + .25 = 100.25\n\t a = fromReal(0.25);\n\t b = fromInteger(100);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t $display(\"100 + .25 = \", fshow(a+b));\n\t \n\t \/\/ 3.25x10^3 + 2.63*10^-1\n\t a = fromReal(3.25e3);\n\t b = fromReal(2.63e-1);\n\t $display(\"a= \", fshow(a));\n\t $display(\"b= \", fshow(b));\n\t $display(\"3.25*10^3 + 2.63*10^-1 = \", fshow(a+b));\n\t \n\t \/\/ verify subnormal rollover to normal\n\t a = unpack('b0_00000_1111111111_11_1);\n\t b = unpack('b0_00000_0000000000_00_1);\n\t $display(\"a= \", fshow(a));\n\t $display(\"b= \", fshow(b));\n\t $display(\"a+b= \", fshow(a+b));\n\t \n\t a = unpack('b0_00000_1111111111_00_0);\n\t b = unpack('b0_00000_0000000001_00_0);\n\t $display(\"a= \", fshow(a));\n\t $display(\"b= \", fshow(b));\n\t $display(\"a+b= \", fshow(a+b));\n\t \n endaction\n \/\/ verify subtraction\n action\n \t FP16 a, b;\n\t \n \t \/\/ verify carry out bit set\n \t \/\/ 2 - 2 = 0\n \t a = fromInteger(2);\n \t b = fromInteger(2);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"2 - 2 = \", fshow(a-b));\n\n \t \/\/ 2 - -2 = 4\n \t a = fromInteger(2);\n \t b = fromInteger(-2);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"2 - -2 = \", fshow(a-b));\n\n \t \/\/ -2 - 2 = -4\n \t a = fromInteger(-2);\n \t b = fromInteger(2);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"-2 - 2 = \", fshow(a-b));\n\n \t \/\/ -2 - -2 = 0\n \t a = fromInteger(-2);\n \t b = fromInteger(-2);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"-2 - -2 = \", fshow(a-b));\n\t \n \t \/\/ 100 - 103\n \t a = fromInteger(100);\n \t b = fromInteger(103);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"100 - 103 = \", fshow(a-b));\n\n \t \/\/ 65504 - 32768\n \t a = fromInteger(65504);\n \t b = fromInteger(32768);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"65504 - 32768 = \", fshow(a-b));\n\n \t \/\/ -65504 - -32768\n \t a = fromInteger(-65504);\n \t b = fromInteger(-32768);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"-65504 - -32768 = \", fshow(a-b));\n\n \t \/\/ -65504 - 32768 (overflow)\n \t a = fromInteger(-65504);\n \t b = fromInteger(32768);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"-65504 - 32768 = \", fshow(a-b));\n\n \t \/\/ 65504 - -32768 (overflow)\n \t a = fromInteger(65504);\n \t b = fromInteger(-32768);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"65504 - -32768 = \", fshow(a-b));\n\t \n \t \/\/ verify subnormal addition\n\n \t \/\/ 5.960464478e-8 - 5.960464478e-8\n \t a = fromReal(5.960464478e-8);\n \t b = fromReal(5.960464478e-8);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"5.96e-8 - 5.96e-8 = \", fshow(a-b));\n\t \t \n \t \/\/ -5.960464478e-8 - -5.960464478e-8\n \t a = fromReal(-5.960464478e-8);\n \t b = fromReal(-5.960464478e-8);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"-5.96e-8 - -5.96e-8 = \", fshow(a-b));\n\t \n \t \/\/ 5.960464478e-8 - -5.960464478e-8\n \t a = fromReal(5.960464478e-8);\n \t b = fromReal(-5.960464478e-8);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"5.96e-8 - -5.96e-8 = \", fshow(a-b));\n\t \n \t \/\/ -5.960464478e-8 - 5.960464478e-8\n \t a = fromReal(-5.960464478e-8);\n \t b = fromReal(5.960464478e-8);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"-5.96e-8 - 5.96e-8 = \", fshow(a-b));\n\t \n \t \/\/ verify case where normalization is necessary\n\t \n \t \/\/ 100 - -103\n \t a = fromInteger(100);\n \t b = fromInteger(-103);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"100 - -103 = \", fshow(a-b));\n\n \t \/\/ -100 - 103\n \t a = fromInteger(-100);\n \t b = fromInteger(103);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"-100 - 103 = \", fshow(a-b));\n\n \t \/\/ 1e-7 - 2e-6\n \t a = fromReal(1e-7);\n \t b = fromReal(2e-6);\n \t FP16 c = fromReal(-1.9e-6);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"1e-7 - 2e-6 = \", fshow(a-b));\n \t $display(\"c=\", fshow(c));\n\t \t \n \t \/\/ 100 - .25 = 99.75\n \t a = fromReal(0.25);\n \t b = fromInteger(100);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"100 - .25 = \", fshow(a-b));\n\t \n \t \/\/ 3.25x10^3 - 2.63*10^-1\n \t a = fromReal(3.25e3);\n \t b = fromReal(2.63e-1);\n \t $display(\"a= \", fshow(a));\n \t $display(\"b= \", fshow(b));\n \t $display(\"3.25*10^3 - 2.63*10^-1 = \", fshow(a-b));\n\t \n\t \/\/ verify normal rollover to subnormal\n\t a = unpack('b0_00001_0000000000_00_0);\n\t b = unpack('b0_00000_1000000000_00_0);\n\t $display(\"a= \", fshow(a));\n\t $display(\"b= \", fshow(b));\n\t $display(\"a-b= \", fshow(a-b));\n\t \n\t a = unpack('b0_00001_0000000000_00_0);\n\t b = unpack('b0_00000_0000000001_11_1);\n\t $display(\"a= \", fshow(a));\n\t $display(\"b= \", fshow(b));\n\t $display(\"a-b= \", fshow(a-b));\n endaction\n \/\/ verify multiply\n action\n \t FP16 a; FP16 b;\n\t \n \t a = fromInteger(2);\n \t b = fromInteger(2);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"2 * 2 = \", fshow(a*b));\n\t \n \t a = fromInteger(3);\n \t b = fromInteger(3);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"3 * 3 = \", fshow(a*b));\n\n \t a = fromInteger(3);\n \t b = fromInteger(5);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"3 * 5 = \", fshow(a*b));\n\t \n \t a = fromReal(1.75);\n \t b = fromInteger(-5);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"1.75 * -5 = \", fshow(a*b));\n\n \t a = fromReal(5.960464478e-8);\n \t b = fromReal(5.960464478e-8);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"5.96e-8 * 5.96e-8 = \", fshow(a*b));\n\n \t a = fromReal(5.960464478e-8);\n \t b = fromReal(2.0);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"5.96e-8 * 2 = \", fshow(a*b));\n \t FP16 c = fromReal(11.920928956e-8);\n \t $display(\"c=\", fshow(c));\n\t \n \t a = fromInteger(32768);\n \t b = fromInteger(2);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"32768 * 2 = \", fshow(a*b));\n endaction\n \/\/ verify divide\n action\n \t FP16 a, b, c;\n\t \n \t a = fromReal(4.0);\n \t b = fromReal(2.0);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"4\/2 = \", fshow(a\/b));\n\n \t a = fromReal(-4.0);\n \t b = fromReal(2.0);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"-4\/2 = \", fshow(a\/b));\n\n \t a = fromReal(-4.0);\n \t b = fromReal(-2.0);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"-4\/-2 = \", fshow(a\/b));\n\n \t a = fromReal(4.0);\n \t b = fromReal(-2.0);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"4\/-2 = \", fshow(a\/b));\n\t \n \t a = fromInteger(5);\n \t b = fromInteger(4);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"5\/4 = \", fshow(a\/b));\n\t \n \t a = fromInteger(1);\n \t b = fromReal(2.5);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"1\/2.5 = \", fshow(a\/b));\n \t c = fromReal(0.4);\n \t $display(\"c=\", fshow(c));\n\t \n \t a = fromReal(11.920928956e-8);\n \t b = fromInteger(2);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"11.92e-8\/2 = \", fshow(a\/b));\n \t c = fromReal(5.960464478e-8);\n \t $display(\"c=\", fshow(c));\n\n \t a = fromReal(11.920928956e-8);\n \t b = fromReal(11.920928956e-8);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"11.92e-8\/11.92e-8 = \", fshow(a\/b));\n \t c = fromInteger(1);\n \t $display(\"c=\", fshow(c));\n\t \n \t a = fromInteger(65504);\n \t b = fromInteger(7);\n \t $display(\"a=\", fshow(a));\n \t $display(\"b=\", fshow(b));\n \t $display(\"65504\/7 = \", fshow(a\/b));\n \t c = fromReal(9357.714285714);\n \t $display(\"c=\", fshow(c));\n endaction\n \/\/ verify boundary addition\n action\n \t FP16 a, b, c;\n\t \t \n \t Vector#(7, Vector#(7, FP16)) adds = newVector;\n \t \/\/ -inf\n \t adds[0][0] = infinity(True);\n \t adds[0][1] = infinity(True);\n \t adds[0][2] = infinity(True);\n \t adds[0][3] = infinity(True);\n \t adds[0][4] = infinity(True);\n \t adds[0][5] = snan();\n \t adds[0][6] = snan();\n \t \/\/ -1\n \t adds[1][0] = infinity(True);\n \t adds[1][1] = fromInteger(-2);\n \t adds[1][2] = fromInteger(-1);\n \t adds[1][3] = fromInteger(-1);\n \t adds[1][4] = fromInteger(0);\n \t adds[1][5] = infinity(False);\n \t adds[1][6] = snan();\n \t \/\/ -0\n \t adds[2][0] = infinity(True);\n \t adds[2][1] = fromInteger(-1);\n \t adds[2][2] = -fromInteger(0);\n \t adds[2][3] = fromInteger(0);\n \t adds[2][4] = fromInteger(1);\n \t adds[2][5] = infinity(False);\n \t adds[2][6] = snan();\n \t \/\/ 0\n \t adds[3][0] = infinity(True);\n \t adds[3][1] = fromInteger(-1);\n \t adds[3][2] = fromInteger(0);\n \t adds[3][3] = fromInteger(0);\n \t adds[3][4] = fromInteger(1);\n \t adds[3][5] = infinity(False);\n \t adds[3][6] = snan();\n \t \/\/ 1\n \t adds[4][0] = infinity(True);\n \t adds[4][1] = fromInteger(0);\n \t adds[4][2] = fromInteger(1);\n \t adds[4][3] = fromInteger(1);\n \t adds[4][4] = fromInteger(2);\n \t adds[4][5] = infinity(False);\n \t adds[4][6] = snan();\n \t \/\/ inf\n \t adds[5][0] = snan();\n \t adds[5][1] = infinity(False);\n \t adds[5][2] = infinity(False);\n \t adds[5][3] = infinity(False);\n \t adds[5][4] = infinity(False);\n \t adds[5][5] = infinity(False);\n \t adds[5][6] = snan();\n \t \/\/ nan\n \t adds[6][0] = snan();\n \t adds[6][1] = snan();\n \t adds[6][2] = snan();\n \t adds[6][3] = snan();\n \t adds[6][4] = snan();\n \t adds[6][5] = snan();\n \t adds[6][6] = snan();\n\t \n \t $display(\"Addition\");\n \t for(Integer j = 0; j < 7; j = j + 1) begin\n \t for(Integer i = 0; i < 7; i = i + 1) begin\n \t a = boundaryvals[j];\n \t b = boundaryvals[i];\n \t $display(\"i=%d j=%d\", i, j);\n \t $display(\"a=\",fshow(a));\n \t $display(\"b=\",fshow(b));\n \t c = a + b;\n \t $display(\"ans=\",fshow(c));\n \t $display(\"c =\",fshow(adds[j][i]));\n \t if (c != adds[j][i]) $display(\"ERROR: MISMATCH!\");\n \t end\n \t end\n endaction\n \/\/ verify boundary subtraction\n action\n \t FP16 a, b, c;\n\t \t \n \t Vector#(7, Vector#(7, FP16)) subs = newVector;\n \t \/\/ -inf\n \t subs[0][0] = snan();\n \t subs[0][1] = infinity(True);\n \t subs[0][2] = infinity(True);\n \t subs[0][3] = infinity(True);\n \t subs[0][4] = infinity(True);\n \t subs[0][5] = infinity(True);\n \t subs[0][6] = snan();\n \t \/\/ -1\n \t subs[1][0] = infinity(False);\n \t subs[1][1] = fromInteger(0);\n \t subs[1][2] = fromInteger(-1);\n \t subs[1][3] = fromInteger(-1);\n \t subs[1][4] = fromInteger(-2);\n \t subs[1][5] = infinity(True);\n \t subs[1][6] = snan();\n \t \/\/ -0\n \t subs[2][0] = infinity(False);\n \t subs[2][1] = fromInteger(1);\n \t subs[2][2] = fromInteger(0);\n \t subs[2][3] = -fromInteger(0);\n \t subs[2][4] = fromInteger(-1);\n \t subs[2][5] = infinity(True);\n \t subs[2][6] = snan();\n \t \/\/ 0\n \t subs[3][0] = infinity(False);\n \t subs[3][1] = fromInteger(1);\n \t subs[3][2] = fromInteger(0);\n \t subs[3][3] = fromInteger(0);\n \t subs[3][4] = fromInteger(-1);\n \t subs[3][5] = infinity(True);\n \t subs[3][6] = snan();\n \t \/\/ 1\n \t subs[4][0] = infinity(False);\n \t subs[4][1] = fromInteger(2);\n \t subs[4][2] = fromInteger(1);\n \t subs[4][3] = fromInteger(1);\n \t subs[4][4] = fromInteger(0);\n \t subs[4][5] = infinity(True);\n \t subs[4][6] = snan();\n \t \/\/ inf\n \t subs[5][0] = infinity(False);\n \t subs[5][1] = infinity(False);\n \t subs[5][2] = infinity(False);\n \t subs[5][3] = infinity(False);\n \t subs[5][4] = infinity(False);\n \t subs[5][5] = snan();\n \t subs[5][6] = snan();\n \t \/\/ nan\n \t subs[6][0] = snan();\n \t subs[6][1] = snan();\n \t subs[6][2] = snan();\n \t subs[6][3] = snan();\n \t subs[6][4] = snan();\n \t subs[6][5] = snan();\n \t subs[6][6] = snan();\n\t \n \t $display(\"Subtraction\");\n \t for(Integer j = 0; j < 7; j = j + 1) begin\n \t for(Integer i = 0; i < 7; i = i + 1) begin\n \t a = boundaryvals[j];\n \t b = boundaryvals[i];\n \t $display(\"i=%d j=%d\", i, j);\n \t $display(\"a=\",fshow(a));\n \t $display(\"b=\",fshow(b));\n \t c = a - b;\n \t $display(\"ans=\",fshow(c));\n \t $display(\"c =\",fshow(subs[j][i]));\n \t if (c != subs[j][i]) $display(\"ERROR: MISMATCH!\");\n \t end\n \t end\n endaction\n \/\/ verify boundary multiplication\n action\n \t FP16 a, b, c;\n\t \t \n \t Vector#(7, Vector#(7, FP16)) subs = newVector;\n \t \/\/ -inf\n \t subs[0][0] = infinity(False);\n \t subs[0][1] = infinity(False);\n \t subs[0][2] = snan();\n \t subs[0][3] = snan();\n \t subs[0][4] = infinity(True);\n \t subs[0][5] = infinity(True);\n \t subs[0][6] = snan();\n \t \/\/ -1\n \t subs[1][0] = infinity(False);\n \t subs[1][1] = fromInteger(1);\n \t subs[1][2] = fromInteger(0);\n \t subs[1][3] = -fromInteger(-0);\n \t subs[1][4] = fromInteger(-1);\n \t subs[1][5] = infinity(True);\n \t subs[1][6] = snan();\n \t \/\/ -0\n \t subs[2][0] = snan();\n \t subs[2][1] = fromInteger(0);\n \t subs[2][2] = fromInteger(0);\n \t subs[2][3] = -fromInteger(0);\n \t subs[2][4] = -fromInteger(0);\n \t subs[2][5] = snan();\n \t subs[2][6] = snan();\n \t \/\/ 0\n \t subs[3][0] = snan();\n \t subs[3][1] = -fromInteger(0);\n \t subs[3][2] = -fromInteger(0);\n \t subs[3][3] = fromInteger(0);\n \t subs[3][4] = fromInteger(0);\n \t subs[3][5] = snan();\n \t subs[3][6] = snan();\n \t \/\/ 1\n \t subs[4][0] = infinity(True);\n \t subs[4][1] = fromInteger(-1);\n \t subs[4][2] = -fromInteger(0);\n \t subs[4][3] = fromInteger(0);\n \t subs[4][4] = fromInteger(1);\n \t subs[4][5] = infinity(False);\n \t subs[4][6] = snan();\n \t \/\/ inf\n \t subs[5][0] = infinity(True);\n \t subs[5][1] = infinity(True);\n \t subs[5][2] = snan();\n \t subs[5][3] = snan();\n \t subs[5][4] = infinity(False);\n \t subs[5][5] = infinity(False);\n \t subs[5][6] = snan();\n \t \/\/ nan\n \t subs[6][0] = snan();\n \t subs[6][1] = snan();\n \t subs[6][2] = snan();\n \t subs[6][3] = snan();\n \t subs[6][4] = snan();\n \t subs[6][5] = snan();\n \t subs[6][6] = snan();\n\t \n \t $display(\"Multiplication\");\n \t for(Integer j = 0; j < 7; j = j + 1) begin\n \t for(Integer i = 0; i < 7; i = i + 1) begin\n \t a = boundaryvals[j];\n \t b = boundaryvals[i];\n \t $display(\"i=%d j=%d\", i, j);\n \t $display(\"a=\",fshow(a));\n \t $display(\"b=\",fshow(b));\n \t c = a * b;\n \t $display(\"ans=\",fshow(c));\n \t $display(\"c =\",fshow(subs[j][i]));\n \t if (c != subs[j][i]) $display(\"ERROR: MISMATCH!\");\n \t end\n \t end\n endaction\n \/\/ verify boundary division\n action\n \t FP16 a, b, c;\n\t \t \n \t Vector#(7, Vector#(7, FP16)) subs = newVector;\n \t \/\/ -inf\n \t subs[0][0] = snan();\n \t subs[0][1] = infinity(False);\n \t subs[0][2] = infinity(False);\n \t subs[0][3] = infinity(True);\n \t subs[0][4] = infinity(True);\n \t subs[0][5] = snan();\n \t subs[0][6] = snan();\n \t \/\/ -1\n \t subs[1][0] = fromInteger(0);\n \t subs[1][1] = fromInteger(1);\n \t subs[1][2] = infinity(False);\n \t subs[1][3] = infinity(True);\n \t subs[1][4] = fromInteger(-1);\n \t subs[1][5] = -fromInteger(0);\n \t subs[1][6] = snan();\n \t \/\/ -0\n \t subs[2][0] = fromInteger(0);\n \t subs[2][1] = fromInteger(0);\n \t subs[2][2] = snan();\n \t subs[2][3] = snan();\n \t subs[2][4] = -fromInteger(0);\n \t subs[2][5] = -fromInteger(0);\n \t subs[2][6] = snan();\n \t \/\/ 0\n \t subs[3][0] = -fromInteger(0);\n \t subs[3][1] = -fromInteger(0);\n \t subs[3][2] = snan();\n \t subs[3][3] = snan();\n \t subs[3][4] = fromInteger(0);\n \t subs[3][5] = fromInteger(0);\n \t subs[3][6] = snan();\n \t \/\/ 1\n \t subs[4][0] = -fromInteger(0);\n \t subs[4][1] = fromInteger(-1);\n \t subs[4][2] = infinity(True);\n \t subs[4][3] = infinity(False);\n \t subs[4][4] = fromInteger(1);\n \t subs[4][5] = fromInteger(0);\n \t subs[4][6] = snan();\n \t \/\/ inf\n \t subs[5][0] = snan();\n \t subs[5][1] = infinity(True);\n \t subs[5][2] = infinity(True);\n \t subs[5][3] = infinity(False);\n \t subs[5][4] = infinity(False);\n \t subs[5][5] = snan();\n \t subs[5][6] = snan();\n \t \/\/ nan\n \t subs[6][0] = snan();\n \t subs[6][1] = snan();\n \t subs[6][2] = snan();\n \t subs[6][3] = snan();\n \t subs[6][4] = snan();\n \t subs[6][5] = snan();\n \t subs[6][6] = snan();\n\t \n \t $display(\"Division\");\n \t for(Integer j = 0; j < 7; j = j + 1) begin\n \t for(Integer i = 0; i < 7; i = i + 1) begin\n \t a = boundaryvals[j];\n \t b = boundaryvals[i];\n \t $display(\"i=%d j=%d\", i, j);\n \t $display(\"a=\",fshow(a));\n \t $display(\"b=\",fshow(b));\n \t c = a \/ b;\n \t $display(\"ans=\",fshow(c));\n \t $display(\"c =\",fshow(subs[j][i]));\n \t if (c != subs[j][i]) $display(\"ERROR: MISMATCH!\");\n \t end\n \t end\n endaction\n\n action\n\t FP64 a, b, c;\n\t Double da, db, dc;\n\t da = unpack(64'hBBE0_0000_0000_0000);\n\t db = da;\n\t $display(\"da=%0X\", da);\n\t $display(\"db=%0X\", db);\n\t a = toFP(da);\n\t b = toFP(db);\n\t $display(\"a=\", fshow(a));\n\t $display(\"b=\", fshow(b));\n\t c = a + b;\n\t $display(\"a+b=\", fshow(c));\n\t dc = fromFP(c);\n\t $display(\"dc=%08X\", pack(dc));\n endaction\n \n delay(10);\n endseq;\n \n mkAutoFSM(test);\n \nendmodule\n\n","avg_line_length":28.85,"max_line_length":64,"alphanum_fraction":0.4562947163} {"size":615,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"\ninterface IFC#(type anyType);\n (*prefix = \"\" *)\n method Action start(anyType a, anyType b);\n method anyType result(anyType c);\n (*prefix = \"\", result = \"result\" *)\n method ActionValue#(anyType) check(anyType d);\nendinterface\n\ntypedef Bit#(5) Type;\n\n(* synthesize *) \nmodule mkDesign_12 (IFC#(Type));\n\n Reg#(Type) val <- mkReg(0);\n Reg#(Type) res <- mkReg(0);\n\n\n method Action start(a,b);\n val <= a;\n res <= b;\n endmethod\t\n \n method Type result(c);\n return res+c;\n endmethod\t\n \t \n method ActionValue#(Type) check(d);\n val <= val + 1;\n res <= res + 2;\n\treturn res+d;\n endmethod\t\n\t\nendmodule\n","avg_line_length":17.5714285714,"max_line_length":47,"alphanum_fraction":0.6146341463} {"size":14969,"ext":"bsv","lang":"Bluespec","max_stars_count":7.0,"content":"\/\/ Copyright (c) 2013-2019 Bluespec, Inc. All Rights Reserved\n\n\/\/ ================================================================\n\/\/ WARNING: this is an 'include' file, not a separate BSV package!\n\/\/\n\/\/ Contains RISC-V Supervisor-Level ISA defs, based on:\n\/\/ The RISC-V Instruction Set Manual\"\n\/\/ Volume II: Privileged Architecture\n\/\/ Privileged Architecture Version 1.10\n\/\/ Document Version 1.10\n\/\/ May 7, 2017\n\/\/\n\/\/ ================================================================\n\n\/\/ Invariants on ifdefs:\n\/\/ - If RV32 is defined, we assume Sv32 for the VM system\n\/\/ - If RV64 is defined, one of SV39 or SV48 must also be defined for the VM system\n\n\/\/ ================================================================\n\/\/ Supervisor-level CSRs\n\nCSR_Addr csr_addr_sstatus = 12'h100; \/\/ Supervisor status\nCSR_Addr csr_addr_sedeleg = 12'h102; \/\/ Supervisor exception delegation\nCSR_Addr csr_addr_sideleg = 12'h103; \/\/ Supervisor interrupt delegation\nCSR_Addr csr_addr_sie = 12'h104; \/\/ Supervisor interrupt enable\nCSR_Addr csr_addr_stvec = 12'h105; \/\/ Supervisor trap handler base address\nCSR_Addr csr_addr_scounteren = 12'h106; \/\/ Supervisor counter enable\n\nCSR_Addr csr_addr_sscratch = 12'h140; \/\/ Scratch reg for supervisor trap handlers\nCSR_Addr csr_addr_sepc = 12'h141; \/\/ Supervisor exception program counter\nCSR_Addr csr_addr_scause = 12'h142; \/\/ Supervisor trap cause\nCSR_Addr csr_addr_stval = 12'h143; \/\/ Supervisor bad address or instruction\nCSR_Addr csr_addr_sip = 12'h144; \/\/ Supervisor interrupt pending\n\nCSR_Addr csr_addr_satp = 12'h180; \/\/ Supervisor address translation and protection\n\n`ifdef ISA_CHERI\nCSR_Addr csr_addr_sccsr = 12'h9c0; \/\/ Supervisor capability control and status register\n`endif\n\n\/\/ ================================================================\n\/\/ SSTATUS\n\nfunction Bit #(1) fn_sstatus_sd (WordXL sstatus_val); return sstatus_val [xlen-1]; endfunction\n\n`ifdef RV64\nfunction Bit #(2) fn_sstatus_UXL (WordXL sstatus_val); return sstatus_val [33:32]; endfunction\n`endif\n\nfunction Bit #(1) fn_sstatus_SUM (WordXL sstatus_val); return sstatus_val [19]; endfunction\nfunction Bit #(1) fn_sstatus_MXR (WordXL sstatus_val); return sstatus_val [18]; endfunction\n\nfunction Bit #(2) fn_sstatus_xs (WordXL sstatus_val); return sstatus_val [16:15]; endfunction\nfunction Bit #(2) fn_sstatus_fs (WordXL sstatus_val); return sstatus_val [14:13]; endfunction\n\nfunction Bit #(1) fn_sstatus_spp (WordXL sstatus_val); return sstatus_val [8]; endfunction\n\nfunction Bit #(1) fn_sstatus_spie (WordXL sstatus_val); return sstatus_val [5]; endfunction\nfunction Bit #(1) fn_sstatus_upie (WordXL sstatus_val); return sstatus_val [4]; endfunction\n\nfunction Bit #(1) fn_sstatus_sie (WordXL sstatus_val); return sstatus_val [1]; endfunction\nfunction Bit #(1) fn_sstatus_uie (WordXL sstatus_val); return sstatus_val [0]; endfunction\n\n\/\/ ----------------\n\/\/ SCAUSE (reason for exception)\n\nfunction Bit #(1) scause_interrupt (WordXL scause_val); return scause_val [xlen-1]; endfunction\nfunction Bit #(TSub #(XLEN,1)) scause_exception_code (WordXL scause_val); return scause_val [xlen-2:0]; endfunction\n\n\/\/ ================================================================\n\n`ifdef ISA_PRIV_S\n\/\/ ================================================================\n\/\/ SATP (supervisor address translation and protection)\n\n\/\/ ----------------\n`ifdef RV32\n\ntypedef Bit #(1) VM_Mode;\ntypedef Bit #(9) ASID;\n\nfunction WordXL fn_mk_satp_val (VM_Mode mode, ASID asid, PA pa) = { mode, asid, pa [33:12] };\nfunction VM_Mode fn_satp_to_VM_Mode (Bit #(32) satp_val); return satp_val [31]; endfunction\nfunction ASID fn_satp_to_ASID (Bit #(32) satp_val); return satp_val [30:22]; endfunction\nfunction PPN fn_satp_to_PPN (Bit #(32) satp_val); return satp_val [21: 0]; endfunction\n\nBit #(1) satp_mode_RV32_bare = 1'h_0;\nBit #(1) satp_mode_RV32_sv32 = 1'h_1;\n\n`elsif RV64\n\ntypedef Bit #(4) VM_Mode;\ntypedef Bit #(16) ASID;\n\nfunction WordXL fn_mk_satp_val (VM_Mode mode, ASID asid, PA pa) = { mode, asid, pa [55:12] };\nfunction VM_Mode fn_satp_to_VM_Mode (Bit #(64) satp_val); return satp_val [63:60]; endfunction\nfunction ASID fn_satp_to_ASID (Bit #(64) satp_val); return satp_val [59:44]; endfunction\nfunction PPN fn_satp_to_PPN (Bit #(64) satp_val); return satp_val [43: 0]; endfunction\n\nBit #(4) satp_mode_RV64_bare = 4'd__0;\nBit #(4) satp_mode_RV64_sv39 = 4'd__8;\nBit #(4) satp_mode_RV64_sv48 = 4'd__9;\nBit #(4) satp_mode_RV64_sv57 = 4'd_10;\nBit #(4) satp_mode_RV64_sv64 = 4'd_11;\n\n`endif\n\n\/\/ ----------------------------------------------------------------\n\/\/ Virtual and Physical addresses, page numbers, offsets\n\/\/ Page table (PT) fields and entries (PTEs)\n\/\/ For Sv32 and Sv39\n\n\n\/\/ ----------------\n\/\/ RV32.Sv32\n\n`ifdef RV32\n\n\/\/ Virtual addrs\ntypedef 32 VA_sz;\ntypedef 20 VPN_sz;\ntypedef 10 VPN_J_sz;\n\n\/\/ Physical addrs\ntypedef 34 PA_sz;\ntypedef 22 PPN_sz;\ntypedef 12 PPN_1_sz;\ntypedef 10 PPN_0_sz;\n\n\/\/ Offsets within a page\ntypedef 12 Offset_sz;\n\n\/\/ PTNodes (nodes in the page-table tree)\ntypedef 1024 PTNode_sz; \/\/ # of PTEs in a PTNode\n\n\/\/ VAs, VPN selectors\nfunction VA fn_mkVA (VPN_J vpn1, VPN_J vpn0, Bit #(Offset_sz) offset) = { vpn1, vpn0, offset };\nfunction VPN fn_Addr_to_VPN (Bit #(n) addr) = addr [31:12];\nfunction VPN_J fn_Addr_to_VPN_1 (Bit #(n) addr) = addr [31:22];\nfunction VPN_J fn_Addr_to_VPN_0 (Bit #(n) addr) = addr [21:12];\n\n\/\/ ----------------\n\/\/ RV64.Sv39\n\n\/\/ ifdef RV32\n`elsif RV64\n\n\/\/ ----------------\n\/\/ RV64.Sv39\n\n\/\/ ifdef RV32 .. elsif RV64\n`ifdef SV39\n\n\/\/ Virtual addrs\ntypedef 39 VA_sz;\ntypedef 27 VPN_sz;\ntypedef 9 VPN_J_sz;\n\n\/\/ Physical addrs\ntypedef 64 PA_sz; \/\/ need 56b in Sv39 mode and 64b in Bare mode\ntypedef 44 PPN_sz;\ntypedef 26 PPN_2_sz;\ntypedef 9 PPN_1_sz;\ntypedef 9 PPN_0_sz;\n\n\/\/ Offsets within a page\ntypedef 12 Offset_sz;\n\n\/\/ PTNodes (nodes in the page-table tree)\ntypedef 512 PTNode_sz; \/\/ # of PTEs in a PTNode\n\n\/\/ VAs, VPN selectors\nfunction VA fn_mkVA (VPN_J vpn2, VPN_J vpn1, VPN_J vpn0, Bit #(Offset_sz) offset) = { vpn2, vpn1, vpn0, offset };\nfunction VPN fn_Addr_to_VPN (Bit #(n) addr) = addr [38:12];\nfunction VPN_J fn_Addr_to_VPN_2 (Bit #(n) addr) = addr [38:30];\nfunction VPN_J fn_Addr_to_VPN_1 (Bit #(n) addr) = addr [29:21];\nfunction VPN_J fn_Addr_to_VPN_0 (Bit #(n) addr) = addr [20:12];\n\n\/\/ ifdef RV32 .. elsif RV64 \/ ifdef SV39\n`else\n\n\/\/ TODO: RV64.SV48 definitions\n\n\/\/ ifdef RV32 .. elsif RV64 \/ ifdef SV39 .. else\n`endif\n\n\/\/ ifdef RV32 .. elsif RV64\n`endif\n\n\/\/ ----------------\n\/\/ Derived types and values\n\n\/\/ Physical addrs\nInteger pa_sz = valueOf (PA_sz); typedef Bit #(PA_sz) PA;\n\nfunction PA fn_WordXL_to_PA (WordXL eaddr);\n`ifdef RV32\n return extend (eaddr);\n`elsif RV64\n return truncate (eaddr);\n`endif\nendfunction\n\n\/\/ Virtual addrs -- derived types and values\nInteger va_sz = valueOf (VA_sz); typedef Bit #(VA_sz) VA;\n\nfunction VA fn_WordXL_to_VA (WordXL eaddr);\n`ifdef RV32\n return eaddr;\n`elsif RV64\n return truncate (eaddr);\n`endif\nendfunction\n\n\/\/ Page offsets\nfunction Offset fn_Addr_to_Offset (Bit #(n) addr);\n return addr [offset_sz - 1: 0];\nendfunction\n\n\/\/ VPNs\nInteger vpn_sz = valueOf (VPN_sz); typedef Bit #(VPN_sz) VPN;\nInteger vpn_j_sz = valueOf (VPN_J_sz); typedef Bit #(VPN_J_sz) VPN_J;\nInteger offset_sz = valueOf (Offset_sz); typedef Bit #(Offset_sz) Offset;\n\n\/\/ PPNs\nInteger ppn_sz = valueOf (PPN_sz); typedef Bit #(PPN_sz) PPN;\n`ifdef RV64\nInteger ppn_2_sz = valueOf (PPN_2_sz); typedef Bit #(PPN_2_sz) PPN_2;\n`endif\nInteger ppn_1_sz = valueOf (PPN_1_sz); typedef Bit #(PPN_1_sz) PPN_1;\nInteger ppn_0_sz = valueOf (PPN_0_sz); typedef Bit #(PPN_0_sz) PPN_0;\n\n`ifdef RV32\ntypedef Bit #(PPN_1_sz) PPN_MEGA;\n`elsif RV64\ntypedef Bit #(TAdd #(PPN_2_sz, PPN_1_sz)) PPN_MEGA;\ntypedef Bit #(PPN_2_sz) PPN_GIGA;\n`endif\n\nfunction PPN fn_PA_to_PPN (PA pa);\n return pa [ppn_sz + offset_sz - 1: offset_sz];\nendfunction\n\nfunction PA fn_PPN_and_Offset_to_PA (PPN ppn, Offset offset);\n`ifdef RV32\n return {ppn, offset};\n`elsif RV64\n return zeroExtend ({ppn, offset});\n`endif\nendfunction\n\n\/\/ ----------------\n\/\/ PTNodes (nodes in the page-table tree)\n\nInteger ptnode_sz = valueOf (PTNode_sz); \/\/ # of PTEs in a PTNode\ntypedef TLog #(PTNode_sz) PTNode_Index_sz;\ntypedef Bit #(PTNode_Index_sz) PTNode_Index;\nInteger ptnode_index_sz = valueOf (PTNode_Index_sz);\n\n\/\/ ----------------\n\/\/ PTEs (Page Table Entries in PTNodes)\n\ntypedef WordXL PTE;\n\nInteger pte_V_offset = 0; \/\/ Valid\nInteger pte_R_offset = 1; \/\/ Read permission\nInteger pte_W_offset = 2; \/\/ Write permission\nInteger pte_X_offset = 3; \/\/ Execute permission\nInteger pte_U_offset = 4; \/\/ Accessible-to-user-mode\nInteger pte_G_offset = 5; \/\/ Global mapping\nInteger pte_A_offset = 6; \/\/ Accessed\nInteger pte_D_offset = 7; \/\/ Dirty\nInteger pte_RSW_offset = 8; \/\/ Reserved for supervisor SW\n\n`ifdef RV32\nInteger pte_PPN_0_offset = 10;\nInteger pte_PPN_1_offset = 20;\n`elsif RV64\nInteger pte_PPN_0_offset = 10;\nInteger pte_PPN_1_offset = 19;\nInteger pte_PPN_2_offset = 28;\n`endif\n\n`ifdef RV64\nInteger pte_StoreCap_offset = 63;\nInteger pte_LoadCap_offset = 62;\nInteger pte_CapDirty_offset = 61;\n`endif\n\nfunction Bit #(1) fn_PTE_to_V (PTE pte);\n return pte [pte_V_offset];\nendfunction\n\nfunction Bit #(1) fn_PTE_to_R (PTE pte);\n return pte [pte_R_offset];\nendfunction\n\nfunction Bit #(1) fn_PTE_to_W (PTE pte);\n return pte [pte_W_offset];\nendfunction\n\nfunction Bit #(1) fn_PTE_to_X (PTE pte);\n return pte [pte_X_offset];\nendfunction\n\nfunction Bit #(1) fn_PTE_to_U (PTE pte);\n return pte [pte_U_offset];\nendfunction\n\nfunction Bit #(1) fn_PTE_to_G (PTE pte);\n return pte [pte_G_offset];\nendfunction\n\nfunction Bit #(1) fn_PTE_to_A (PTE pte);\n return pte [pte_A_offset];\nendfunction\n\nfunction Bit #(1) fn_PTE_to_D (PTE pte);\n return pte [pte_D_offset];\nendfunction\n\nfunction PPN fn_PTE_to_PPN (PTE pte);\n return pte [ppn_sz + pte_PPN_0_offset - 1 : pte_PPN_0_offset];\nendfunction\n\nfunction PPN_MEGA fn_PTE_to_PPN_mega (PTE pte);\n return pte [ppn_sz + pte_PPN_0_offset - 1 : pte_PPN_1_offset];\nendfunction\n\n`ifdef RV64\nfunction PPN_GIGA fn_PTE_to_PPN_giga (PTE pte);\n return pte [ppn_sz + pte_PPN_0_offset - 1 : pte_PPN_2_offset];\nendfunction\n`endif\n\nfunction PPN_0 fn_PTE_to_PPN_0 (PTE pte);\n return pte [pte_PPN_1_offset - 1 : pte_PPN_0_offset];\nendfunction\n\nfunction PPN_1 fn_PTE_to_PPN_1 (PTE pte);\n return pte [ppn_1_sz + pte_PPN_1_offset - 1 : pte_PPN_1_offset];\nendfunction\n\n`ifdef RV64\nfunction PPN_2 fn_PTE_to_PPN_2 (PTE pte);\n return pte [ppn_2_sz + pte_PPN_2_offset - 1 : pte_PPN_2_offset];\nendfunction\n`endif\n\n`ifdef RV64\nfunction Bit #(1) fn_PTE_to_StoreCap (PTE pte);\n return pte [pte_StoreCap_offset];\nendfunction\n\nfunction Bit #(1) fn_PTE_to_LoadCap (PTE pte);\n return pte [pte_LoadCap_offset];\nendfunction\n\nfunction Bit #(1) fn_PTE_to_CapDirty (PTE pte);\n return pte [pte_CapDirty_offset];\nendfunction\n`else\nfunction Bit #(1) fn_PTE_to_StoreCap (PTE pte);\n return 1'b1;\nendfunction\n\nfunction Bit #(1) fn_PTE_to_LoadCap (PTE pte);\n return 1'b1;\nendfunction\n\nfunction Bit #(1) fn_PTE_to_CapDirty (PTE pte);\n return 1'b1;\nendfunction\n`endif\n\n\/\/ ----------------\n\/\/ Check if a PTE is invalid (V bit clear, or improper R\/W bits)\n\nfunction Bool is_invalid_pte (PTE pte);\n return ( (fn_PTE_to_V (pte) == 0)\n\t || ( (fn_PTE_to_R (pte) == 0)\n\t && (fn_PTE_to_W (pte) == 1)));\nendfunction\n\n\/\/ ----------------\n\/\/ Check if PTE bits deny a virtual-mem access\n\nfunction Tuple2#(Bool,Exc_Code) is_pte_fault\n\t\t\t (Bool dmem_not_imem, \/\/ load-store or fetch?\n\t\t\t Bool read_not_write,\n\t\t\t Bool capability,\n\t\t\t Priv_Mode priv,\n\t\t\t Bit #(1) sstatus_SUM,\n\t\t\t Bit #(1) mstatus_MXR,\n\t\t\t PTE pte);\n\n let pte_u = fn_PTE_to_U (pte);\n let pte_x = fn_PTE_to_X (pte);\n let pte_w = fn_PTE_to_W (pte);\n let pte_r = fn_PTE_to_R (pte);\n\n let pte_StoreCap = fn_PTE_to_StoreCap (pte);\n \/\/ pte_LoadCap would not cause a denial\n\n Bool priv_deny = ( ((priv == u_Priv_Mode) && (pte_u == 1'b0))\n\t\t || ((priv == s_Priv_Mode) && (pte_u == 1'b1) && (sstatus_SUM == 1'b0)));\n\n Bool access_fetch = ((! dmem_not_imem) && read_not_write);\n Bool access_load = (dmem_not_imem && read_not_write);\n Bool access_store = (dmem_not_imem && (! read_not_write));\n\n let pte_r_mxr = (pte_r | (mstatus_MXR & pte_x));\n\n Bool access_ok = ( (access_fetch && (pte_x == 1'b1))\n\t\t || (access_load && (pte_r_mxr == 1'b1))\n\t\t || (access_store && (pte_w == 1'b1)));\n\n Bool access_cap_ok = ( (! capability)\n\t\t\t || access_load\n\t\t\t || (access_store && (pte_StoreCap == 1'b1)));\n\n Bool pte_a_d_fault = ( (fn_PTE_to_A (pte) == 0)\n\t\t\t || ((! read_not_write) && (fn_PTE_to_D (pte) == 0)));\n\n Bool pte_cd_fault = ( capability\n\t\t\t&& (! read_not_write)\n\t\t\t&& (fn_PTE_to_CapDirty (pte) == 0));\n\n Exc_Code exc_code = ?;\n\n if (priv_deny || (! access_ok) || (access_cap_ok && pte_a_d_fault)) begin\n exc_code = fn_page_fault_default_exc_code (dmem_not_imem, read_not_write);\n end\n else if ((! access_cap_ok) || pte_cd_fault) begin\n \/\/ Note that we cannot trap on loads for this reason.\n \/\/ However, with additional revocation PTE modes, we may trap here, and\n \/\/ will need separate read and write signals to behave correctly for\n \/\/ AMOs.\n exc_code = exc_code_STORE_AMO_CAP_PAGE_FAULT;\n end\n\n return tuple2 ((priv_deny || (! access_ok) || (! access_cap_ok) || pte_a_d_fault),\n\t\t exc_code);\nendfunction\n\n\/\/ Exception code to give in case of invalid PTEs etc only depends on access type\nfunction Exc_Code fn_page_fault_default_exc_code (Bool dmem_not_imem, Bool read_not_write);\n return ((! dmem_not_imem) ? exc_code_INSTR_PAGE_FAULT\n\t :(read_not_write ? exc_code_LOAD_PAGE_FAULT\n\t : exc_code_STORE_AMO_PAGE_FAULT));\nendfunction\n\n`else \/\/ ifdef ISA_PRIV_S\n\/\/ The below definitions are valid for cases where there is no VM\n\/\/ Physical addrs -- without VM, PA is same as WordXL\ntypedef XLEN PA_sz;\n\n\/\/ Physical addrs\nInteger pa_sz = valueOf (PA_sz); typedef Bit #(PA_sz) PA;\n\nfunction PA fn_WordXL_to_PA (WordXL eaddr);\n return eaddr;\nendfunction\n\n`endif \/\/ else-ifdef ISA_PRIV_S\n\n\/\/ ----------------\n\/\/ Choose particular kind of access fault\n\nfunction Exc_Code fn_access_exc_code (Bool dmem_not_imem, Bool read_not_write);\n return ((! dmem_not_imem) ? exc_code_INSTR_ACCESS_FAULT\n\t :(read_not_write ? exc_code_LOAD_ACCESS_FAULT\n\t : exc_code_STORE_AMO_ACCESS_FAULT));\nendfunction\n\n\/\/ ================================================================\n","avg_line_length":31.3815513627,"max_line_length":116,"alphanum_fraction":0.6639054045} {"size":819,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"\/\/ This RWire's wget and whas output ports are only used in one place.\n\/\/ When the RWire is inlined, the signals for those ports should remain\n\/\/ in the output Verilog (as inlining will not expose any optimization).\n\n(* synthesize *)\nmodule sysRWireOneUse (Empty);\n\n Reg#(Bit#(8)) x <- mkRegU;\n Reg#(Bit#(8)) y <- mkRegU;\n\n RWire#(Bit#(8)) rw <- mkRWire;\n\n \/\/ Give a condition to the setting of the RWire, so that we\n \/\/ can see the rw$whas signal in the output Verilog.\n \/\/ The condition can't be the rule predicate, though, because\n \/\/ then the rwire port disappears as it is just an alias for\n \/\/ CAN_FIRE_rule1 (and optimization removed aliases).\n rule rule1;\n if (x > 64)\n\t rw.wset(x + y);\n endrule\n\n rule rule2 (isValid(rw.wget));\n y <= validValue(rw.wget);\n endrule\n\nendmodule\n\n","avg_line_length":28.2413793103,"max_line_length":72,"alphanum_fraction":0.6703296703} {"size":309,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"(* synthesize *)\nmodule sysTest();\n\n Reg#(UInt#(8)) r <- mkReg(0);\n Reg#(UInt#(8)) m <- mkReg(0);\n\n rule rl1;\n r <= r \/ 16;\n m <= r % 16;\n endrule\n\n Reg#(Int#(8)) sr <- mkReg(0);\n Reg#(Int#(8)) sm <- mkReg(0);\n\n rule rl2;\n sr <= sr \/ 16;\n sm <= sr % 16;\n endrule\n\nendmodule","avg_line_length":15.45,"max_line_length":32,"alphanum_fraction":0.4530744337} {"size":1588,"ext":"bsv","lang":"Bluespec","max_stars_count":134.0,"content":"\/\/ Copyright (c) 2016 Accelerated Tech, Inc.\n\n\/\/ Permission is hereby granted, free of charge, to any person\n\/\/ obtaining a copy of this software and associated documentation\n\/\/ files (the \"Software\"), to deal in the Software without\n\/\/ restriction, including without limitation the rights to use, copy,\n\/\/ modify, merge, publish, distribute, sublicense, and\/or sell copies\n\/\/ of the Software, and to permit persons to whom the Software is\n\/\/ furnished to do so, subject to the following conditions:\n\n\/\/ The above copyright notice and this permission notice shall be\n\/\/ included in all copies or substantial portions of the Software.\n\n\/\/ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\/\/ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\/\/ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n\/\/ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n\/\/ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n\/\/ ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n\/\/ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n\/\/ SOFTWARE.\n\nimport Strstr::*;\nimport Vector::*;\nimport BuildVector::*;\n\nimport ConnectalMemTypes::*;\n\ninterface StrstrExample;\n interface StrstrRequest request;\n interface Vector#(2, MemReadClient#(64)) readClients;\nendinterface\n\nmodule mkStrstrExample#(StrstrIndication ind)(StrstrExample);\n Strstr#(64,64) strstr <- mkStrstr(ind);\n interface request = strstr.request;\n interface readClients = append(strstr.config_read_client, strstr.haystack_read_client);\nendmodule\n","avg_line_length":40.7179487179,"max_line_length":90,"alphanum_fraction":0.7688916877} {"size":15164,"ext":"bsv","lang":"Bluespec","max_stars_count":271.0,"content":"\/\/ Copyright (c) 2018-2021 Bluespec, Inc. All Rights Reserved.\n\npackage Core;\n\n\/\/ ================================================================\n\/\/ This package defines:\n\/\/ Core_IFC\n\/\/ mkCore #(Core_IFC)\n\/\/\n\/\/ mkCore instantiates:\n\/\/ - mkCPU (the RISC-V CPU)\n\/\/ - mkFabric_2x3\n\/\/ - mkNear_Mem_IO_AXI4\n\/\/ - mkPLIC_16_2_7\n\/\/ - mkTV_Encode (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF)\n\/\/ - mkDebug_Module (RISC-V Debug Module, optional: INCLUDE_GDB_CONTROL)\n\/\/ and connects them all up.\n\n\/\/ ================================================================\n\/\/ BSV library imports\n\nimport Vector :: *;\nimport FIFOF :: *;\nimport GetPut :: *;\nimport ClientServer :: *;\nimport Connectable :: *;\n\n\/\/ ----------------\n\/\/ BSV additional libs\n\nimport Cur_Cycle :: *;\nimport GetPut_Aux :: *;\n\n\/\/ ================================================================\n\/\/ Project imports\n\n\/\/ Main fabric\nimport AXI4_Types :: *;\nimport AXI4_Fabric :: *;\nimport Fabric_Defs :: *; \/\/ for Wd_Id, Wd_Addr, Wd_Data, Wd_User\nimport SoC_Map :: *;\n\n`ifdef INCLUDE_DMEM_SLAVE\nimport AXI4_Lite_Types :: *;\n`endif\n\n`ifdef INCLUDE_GDB_CONTROL\nimport Debug_Module :: *;\n`endif\n\nimport Core_IFC :: *;\nimport CPU_IFC :: *;\nimport CPU :: *;\n\nimport Fabric_2x3 :: *;\n\nimport Near_Mem_IFC :: *; \/\/ For Wd_{Id,Addr,Data,User}_Dma\nimport Near_Mem_IO_AXI4 :: *;\nimport PLIC :: *;\nimport PLIC_16_2_7 :: *;\n\n`ifdef INCLUDE_TANDEM_VERIF\nimport TV_Info :: *;\nimport TV_Encode :: *;\n`endif\n\n\/\/ TV_Taps needed when both GDB_CONTROL and TANDEM_VERIF are present\n`ifdef INCLUDE_GDB_CONTROL\n`ifdef INCLUDE_TANDEM_VERIF\nimport TV_Taps :: *;\n`endif\n`endif\n\n\/\/ ================================================================\n\/\/ The Core module\n\n(* synthesize *)\nmodule mkCore\n #(Reset dm_power_on_reset) \/\/ for future use\n (Core_IFC #(N_External_Interrupt_Sources));\n\n \/\/ ================================================================\n \/\/ STATE\n\n \/\/ System address map\n SoC_Map_IFC soc_map <- mkSoC_Map;\n\n \/\/ The CPU\n CPU_IFC cpu <- mkCPU;\n\n \/\/ A 2x3 fabric for connecting {CPU, Debug_Module} to {Fabric, Near_Mem_IO, PLIC}\n Fabric_2x3_IFC fabric_2x3 <- mkFabric_2x3;\n\n \/\/ Near_Mem_IO\n Near_Mem_IO_AXI4_IFC near_mem_io <- mkNear_Mem_IO_AXI4;\n\n \/\/ PLIC (Platform-Level Interrupt Controller)\n PLIC_IFC_16_2_7 plic <- mkPLIC_16_2_7;\n\n \/\/ Reset requests from SoC and responses to SoC\n \/\/ 'Bool' is 'running' state\n FIFOF #(Bool) f_reset_reqs <- mkFIFOF;\n FIFOF #(Bool) f_reset_rsps <- mkFIFOF;\n\n`ifdef INCLUDE_TANDEM_VERIF\n \/\/ The TV encoder transforms Trace_Data structures produced by the CPU and DM\n \/\/ into encoded byte vectors for transmission to the Tandem Verifier\n TV_Encode_IFC tv_encode <- mkTV_Encode;\n`endif\n\n`ifdef INCLUDE_GDB_CONTROL\n \/\/ Debug Module\n Debug_Module_IFC debug_module <- mkDebug_Module;\n`endif\n\n \/\/ ================================================================\n \/\/ RESET\n \/\/ There are two sources of reset requests to the CPU: externally\n \/\/ from the SoC and, optionally, the DM. When both requestors are\n \/\/ present (i.e., DM is present), we merge the reset requests into\n \/\/ the CPU, and we remember which one was the requestor in\n \/\/ f_reset_requestor, so that we know whome to respond to.\n\n Bit #(1) reset_requestor_dm = 0;\n Bit #(1) reset_requestor_soc = 1;\n`ifdef INCLUDE_GDB_CONTROL\n FIFOF #(Bit #(1)) f_reset_requestor <- mkFIFOF;\n`endif\n\n \/\/ Reset-hart0 request from SoC\n rule rl_cpu_hart0_reset_from_soc_start;\n let running <- pop (f_reset_reqs);\n\n cpu.hart0_server_reset.request.put (running); \/\/ CPU\n near_mem_io.server_reset.request.put (?); \/\/ Near_Mem_IO\n plic.server_reset.request.put (?); \/\/ PLIC\n fabric_2x3.reset; \/\/ Local 2x3 Fabric\n\n`ifdef INCLUDE_GDB_CONTROL\n \/\/ Remember the requestor, so we can respond to it\n f_reset_requestor.enq (reset_requestor_soc);\n`endif\n $display (\"%0d: Core.rl_cpu_hart0_reset_from_soc_start\", cur_cycle);\n endrule\n\n`ifdef INCLUDE_GDB_CONTROL\n \/\/ Reset-hart0 from Debug Module\n rule rl_cpu_hart0_reset_from_dm_start;\n let running <- debug_module.hart0_reset_client.request.get;\n\n cpu.hart0_server_reset.request.put (running); \/\/ CPU\n near_mem_io.server_reset.request.put (?); \/\/ Near_Mem_IO\n plic.server_reset.request.put (?); \/\/ PLIC\n fabric_2x3.reset; \/\/ Local 2x3 fabric\n\n \/\/ Remember the requestor, so we can respond to it\n f_reset_requestor.enq (reset_requestor_dm);\n $display (\"%0d: Core.rl_cpu_hart0_reset_from_dm_start\", cur_cycle);\n endrule\n`endif\n\n rule rl_cpu_hart0_reset_complete;\n let running <- cpu.hart0_server_reset.response.get; \/\/ CPU\n let rsp2 <- near_mem_io.server_reset.response.get; \/\/ Near_Mem_IO\n let rsp3 <- plic.server_reset.response.get; \/\/ PLIC\n\n near_mem_io.set_addr_map (zeroExtend (soc_map.m_near_mem_io_addr_base),\n\t\t\t\tzeroExtend (soc_map.m_near_mem_io_addr_lim));\n\n plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_base),\n\t\t\t zeroExtend (soc_map.m_plic_addr_lim));\n\n Bit #(1) requestor = reset_requestor_soc;\n`ifdef INCLUDE_GDB_CONTROL\n requestor <- pop (f_reset_requestor);\n if (requestor == reset_requestor_dm)\n\t debug_module.hart0_reset_client.response.put (running);\n`endif\n if (requestor == reset_requestor_soc)\n\t f_reset_rsps.enq (running);\n\n $display (\"%0d: Core.rl_cpu_hart0_reset_complete\", cur_cycle);\n endrule\n\n \/\/ ================================================================\n \/\/ Direct DM-to-CPU connections\n\n`ifdef INCLUDE_GDB_CONTROL\n \/\/ DM to CPU connections for run-control and other misc requests\n mkConnection (debug_module.hart0_client_run_halt, cpu.hart0_server_run_halt);\n mkConnection (debug_module.hart0_get_other_req, cpu.hart0_put_other_req);\n`endif\n\n \/\/ ================================================================\n \/\/ Other CPU\/DM\/TV connections\n \/\/ (depends on whether DM, TV or both are present)\n\n`ifdef INCLUDE_GDB_CONTROL\n`ifdef INCLUDE_TANDEM_VERIF\n \/\/ BEGIN SECTION: GDB and TV\n \/\/ ----------------------------------------------------------------\n \/\/ DM and TV both present. We instantiate 'taps' into connections\n \/\/ where the DM writes CPU GPRs, CPU FPRs, CPU CSRs, and main memory,\n \/\/ in order to produce corresponding writes for the Tandem Verifier.\n \/\/ Then, we merge the Trace_Data from these three taps with the\n \/\/ Trace_Data produced by the CPU.\n\n FIFOF #(Trace_Data) f_trace_data_merged <- mkFIFOF;\n\n \/\/ Connect merged trace data to trace encoder\n mkConnection (toGet (f_trace_data_merged), tv_encode.trace_data_in);\n\n \/\/ Merge-in CPU's trace data.\n \/\/ This is equivalent to: mkConnection (cpu.trace_data_out, toPut (f_trace_data_merged))\n \/\/ but using a rule allows us to name it in scheduling attributes.\n rule merge_cpu_trace_data;\n let tmp <- cpu.trace_data_out.get;\n f_trace_data_merged.enq (tmp);\n endrule\n\n \/\/ Create a tap for DM's memory-writes to the bus, and merge-in the trace data.\n DM_Mem_Tap_IFC dm_mem_tap <- mkDM_Mem_Tap;\n mkConnection (debug_module.master, dm_mem_tap.slave);\n let dm_master_local = dm_mem_tap.master;\n\n rule merge_dm_mem_trace_data;\n let tmp <- dm_mem_tap.trace_data_out.get;\n f_trace_data_merged.enq (tmp);\n endrule\n\n \/\/ Create a tap for DM's GPR writes to the CPU, and merge-in the trace data.\n DM_GPR_Tap_IFC dm_gpr_tap_ifc <- mkDM_GPR_Tap;\n mkConnection (debug_module.hart0_gpr_mem_client, dm_gpr_tap_ifc.server);\n mkConnection (dm_gpr_tap_ifc.client, cpu.hart0_gpr_mem_server);\n\n rule merge_dm_gpr_trace_data;\n let tmp <- dm_gpr_tap_ifc.trace_data_out.get;\n f_trace_data_merged.enq (tmp);\n endrule\n\n`ifdef ISA_F\n \/\/ Create a tap for DM's FPR writes to the CPU, and merge-in the trace data.\n DM_FPR_Tap_IFC dm_fpr_tap_ifc <- mkDM_FPR_Tap;\n mkConnection (debug_module.hart0_fpr_mem_client, dm_fpr_tap_ifc.server);\n mkConnection (dm_fpr_tap_ifc.client, cpu.hart0_fpr_mem_server);\n\n rule merge_dm_fpr_trace_data;\n let tmp <- dm_fpr_tap_ifc.trace_data_out.get;\n f_trace_data_merged.enq (tmp);\n endrule\n`endif\n\n \/\/ Create a tap for DM's CSR writes, and merge-in the trace data.\n DM_CSR_Tap_IFC dm_csr_tap <- mkDM_CSR_Tap;\n mkConnection(debug_module.hart0_csr_mem_client, dm_csr_tap.server);\n mkConnection(dm_csr_tap.client, cpu.hart0_csr_mem_server);\n\n`ifdef ISA_F\n (* descending_urgency = \"merge_dm_fpr_trace_data, merge_dm_gpr_trace_data\" *)\n`endif\n (* descending_urgency = \"merge_dm_gpr_trace_data, merge_dm_csr_trace_data\" *)\n (* descending_urgency = \"merge_dm_csr_trace_data, merge_dm_mem_trace_data\" *)\n (* descending_urgency = \"merge_dm_mem_trace_data, merge_cpu_trace_data\" *)\n rule merge_dm_csr_trace_data;\n let tmp <- dm_csr_tap.trace_data_out.get;\n f_trace_data_merged.enq(tmp);\n endrule\n\n \/\/ END SECTION: GDB and TV\n`else\n \/\/ for ifdef INCLUDE_TANDEM_VERIF\n \/\/ ----------------------------------------------------------------\n \/\/ BEGIN SECTION: GDB and no TV\n\n \/\/ Connect DM's GPR interface directly to CPU\n mkConnection (debug_module.hart0_gpr_mem_client, cpu.hart0_gpr_mem_server);\n\n`ifdef ISA_F\n \/\/ Connect DM's FPR interface directly to CPU\n mkConnection (debug_module.hart0_fpr_mem_client, cpu.hart0_fpr_mem_server);\n`endif\n\n \/\/ Connect DM's CSR interface directly to CPU\n mkConnection (debug_module.hart0_csr_mem_client, cpu.hart0_csr_mem_server);\n\n \/\/ DM's bus master is directly the bus master\n let dm_master_local = debug_module.master;\n\n \/\/ END SECTION: GDB and no TV\n`endif\n \/\/ for ifdef INCLUDE_TANDEM_VERIF\n\n`else\n \/\/ for ifdef INCLUDE_GDB_CONTROL\n \/\/ BEGIN SECTION: no GDB\n\n \/\/ No DM, so 'DM bus master' is dummy\n AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User)\n dm_master_local = dummy_AXI4_Master_ifc;\n\n`ifdef INCLUDE_TANDEM_VERIF\n \/\/ ----------------------------------------------------------------\n \/\/ BEGIN SECTION: no GDB, TV\n\n \/\/ Connect CPU's TV out directly to TV encoder\n mkConnection (cpu.trace_data_out, tv_encode.trace_data_in);\n \/\/ END SECTION: no GDB, TV\n`endif\n`endif\n \/\/ for ifdef INCLUDE_GDB_CONTROL\n\n \/\/ ================================================================\n \/\/ Connect the local 2x3 fabric\n\n \/\/ Masters on the local 2x3 fabric\n mkConnection (cpu.mem_master, fabric_2x3.v_from_masters [cpu_dmem_master_num]);\n mkConnection (dm_master_local, fabric_2x3.v_from_masters [debug_module_sba_master_num]);\n\n \/\/ Slaves on the local 2x3 fabric\n \/\/ default slave is taken out directly to the Core interface\n mkConnection (fabric_2x3.v_to_slaves [near_mem_io_slave_num], near_mem_io.axi4_slave);\n mkConnection (fabric_2x3.v_to_slaves [plic_slave_num], plic.axi4_slave);\n\n \/\/ ================================================================\n \/\/ Connect interrupt lines from near_mem_io and PLIC to CPU\n\n rule rl_relay_sw_interrupts; \/\/ from Near_Mem_IO (CLINT)\n Bool x <- near_mem_io.get_sw_interrupt_req.get;\n cpu.software_interrupt_req (x);\n \/\/ $display (\"%0d: Core.rl_relay_sw_interrupts: relaying: %d\", cur_cycle, pack (x));\n endrule\n\n rule rl_relay_timer_interrupts; \/\/ from Near_Mem_IO (CLINT)\n Bool x <- near_mem_io.get_timer_interrupt_req.get;\n cpu.timer_interrupt_req (x);\n\n \/\/ $display (\"%0d: Core.rl_relay_timer_interrupts: relaying: %d\", cur_cycle, pack (x));\n endrule\n\n rule rl_relay_external_interrupts; \/\/ from PLIC\n Bool meip = plic.v_targets [0].m_eip;\n cpu.m_external_interrupt_req (meip);\n\n Bool seip = plic.v_targets [1].m_eip;\n cpu.s_external_interrupt_req (seip);\n\n \/\/ $display (\"%0d: Core.rl_relay_external_interrupts: relaying: %d\", cur_cycle, pack (x));\n endrule\n\n \/\/ ================================================================\n \/\/ INTERFACE\n\n \/\/ ----------------------------------------------------------------\n \/\/ Soft reset\n\n interface Server cpu_reset_server = toGPServer (f_reset_reqs, f_reset_rsps);\n\n \/\/ ----------------------------------------------------------------\n \/\/ AXI4 Fabric interfaces\n\n \/\/ IMem to Fabric master interface\n interface AXI4_Master_IFC cpu_imem_master = cpu.imem_master;\n\n \/\/ DMem to Fabric master interface\n interface AXI4_Master_IFC core_mem_master = fabric_2x3.v_to_slaves [default_slave_num];\n\n \/\/ ----------------------------------------------------------------\n \/\/ Optional AXI4-Lite D-cache slave interface\n\n`ifdef INCLUDE_DMEM_SLAVE\n interface AXI4_Lite_Slave_IFC cpu_dmem_slave = cpu.dmem_slave;\n`endif\n\n \/\/ ----------------------------------------------------------------\n \/\/ Interface to 'coherent DMA' port of optional L2 cache\n\n interface AXI4_Slave_IFC dma_server = cpu.dma_server;\n\n \/\/ ----------------------------------------------------------------\n \/\/ External interrupt sources\n\n interface core_external_interrupt_sources = plic.v_sources;\n\n \/\/ ----------------------------------------------------------------\n \/\/ Non-maskable interrupt request\n\n method Action nmi_req (Bool set_not_clear);\n cpu.nmi_req (set_not_clear);\n endmethod\n\n \/\/ ----------------------------------------------------------------\n \/\/ Optional TV interface\n\n`ifdef INCLUDE_TANDEM_VERIF\n interface Get tv_verifier_info_get;\n method ActionValue #(Info_CPU_to_Verifier) get();\n match { .n, .v } <- tv_encode.tv_vb_out.get;\n return (Info_CPU_to_Verifier { num_bytes: n, vec_bytes: v });\n endmethod\n endinterface\n`endif\n\n \/\/ ----------------------------------------------------------------\n \/\/ Optional DM interfaces\n\n`ifdef INCLUDE_GDB_CONTROL\n \/\/ ----------------\n \/\/ DMI (Debug Module Interface) facing remote debugger\n\n interface DMI dm_dmi = debug_module.dmi;\n\n \/\/ ----------------\n \/\/ Facing Platform\n\n \/\/ Non-Debug-Module Reset (reset all except DM)\n interface Client ndm_reset_client = debug_module.ndm_reset_client;\n`endif\n\n \/\/ ----------------------------------------------------------------\n \/\/ Misc. control and status\n\n \/\/ ----------------\n \/\/ Debugging: set core's verbosity\n\n method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay);\n cpu.set_verbosity (verbosity, logdelay);\n endmethod\n\n \/\/ ----------------\n \/\/ For ISA tests: watch memory writes to addr\n\n`ifdef WATCH_TOHOST\n method Action set_watch_tohost (Bool watch_tohost, Fabric_Addr tohost_addr);\n cpu.set_watch_tohost (watch_tohost, tohost_addr);\n endmethod\n\n method Fabric_Data mv_tohost_value = cpu.mv_tohost_value;\n`endif\n\n \/\/ Inform core that DDR4 has been initialized and is ready to accept requests\n method Action ma_ddr4_ready;\n cpu.ma_ddr4_ready;\n endmethod\n\n \/\/ Misc. status; 0 = running, no error\n method Bit #(8) mv_status;\n return cpu.mv_status;\n endmethod\nendmodule: mkCore\n\nendpackage\n","avg_line_length":33.5486725664,"max_line_length":96,"alphanum_fraction":0.6294513321} {"size":6110,"ext":"bsv","lang":"Bluespec","max_stars_count":134.0,"content":"\/\/ Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n\/\/ Permission is hereby granted, free of charge, to any person\n\/\/ obtaining a copy of this software and associated documentation\n\/\/ files (the \"Software\"), to deal in the Software without\n\/\/ restriction, including without limitation the rights to use, copy,\n\/\/ modify, merge, publish, distribute, sublicense, and\/or sell copies\n\/\/ of the Software, and to permit persons to whom the Software is\n\/\/ furnished to do so, subject to the following conditions:\n\n\/\/ The above copyright notice and this permission notice shall be\n\/\/ included in all copies or substantial portions of the Software.\n\n\/\/ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\/\/ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\/\/ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n\/\/ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n\/\/ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n\/\/ ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n\/\/ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n\/\/ SOFTWARE.\n\n\/\/ Idea:\n\/\/ BlueScopeEventPIO allows one to record values only when they change,\n\/\/ along with timestamps of the time of change.\n\/\/ The input is some collection of bits, in some clock domain\n\/\/ A trigger signal is generated when the input, anded with a trigger\n\/\/ mask, changes from clock to clock\n\/\/ Whenever the trigger happens, the new value and a timestamp are saved\n\/\/ into a SyncBRAMFiFo. The output of the FiFo is in the system clock\n\/\/ domain, as is a counter value that says how many events have happened.\n\/\/ When enabled, the events in the fifo are reported by indication\n\n\/\/ A very similar module is BlueScopeEventPIO.bsv, which reports by DMA.\n\/\/ It supports a much higher data rate, but is more trouble to set up and use\n\nimport Clocks::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport BRAMFIFO::*;\n\n\/\/ This version records timestamped events\ninterface BlueScopeEventPIORequest;\n \/\/ emtpy fifo and reset event counter\n method Action doReset();\n \/\/ changes in bits selected by the mask will trigger events\n method Action setTriggerMask(Bit#(32) mask);\n \/\/ generate a report pointer indication\n method Action getCounterValue();\n \/\/ copy from fifo to memory\n method Action enableIndications(Bit#(32) en);\nendinterface\n\ninterface BlueScopeEventPIOIndication;\n \/\/ report number of events since last reset,\n method Action counterValue(Bit#(32) v);\n \/\/ report an event\n method Action reportEvent(Bit#(32) value, Bit#(32) timestamp);\nendinterface\n\n\/\/ This interface is used by the device under test to report events\n\/\/ Reported events are actually recorded only if they meet the trigger\n\/\/ conditions\ninterface BlueScopeEventPIO#(numeric type dataWidth);\n method Action dataIn(Bit#(dataWidth) d);\nendinterface\n \ninterface BlueScopeEventPIOControl#(numeric type dataWidth);\n interface BlueScopeEventPIO#(dataWidth) bse;\n interface BlueScopeEventPIORequest requestIfc;\nendinterface\n\nmodule mkBlueScopeEventPIO#(Integer samples, BlueScopeEventPIOIndication indication)(BlueScopeEventPIOControl#(dataWidth))\n provisos(Add#(0,dataWidth,32));\n \n let clk <- exposeCurrentClock;\n let rst <- exposeCurrentReset;\n let rv <- mkSyncBlueScopeEventPIO(samples, indication, clk, rst, clk,rst);\n return rv;\nendmodule\n\n\/\/ sClk is the source? sample? side, input samples come here\n\/\/ dClk is the destination? dma? side, this will generally be the system clock\n\nmodule mkSyncBlueScopeEventPIO#(Integer samples, BlueScopeEventPIOIndication indication, Clock sClk, Reset sRst, Clock dClk, Reset dRst)(BlueScopeEventPIOControl#(dataWidth))\n provisos(Add#(0, dataWidth, 32));\n\n \/\/ the idea here is that we let events pour into the Bram continually,\n \/\/ then reset them before starting an acquisition interval\n \/\/ we reset both halves of the fifo, not clear that is needed\n MakeResetIfc sFifoReset <- mkReset(2, True, sClk);\n MakeResetIfc dFifoReset <- mkReset(2, True, dClk);\n SyncFIFOIfc#(Bit#(64)) dfifo <- mkSyncBRAMFIFO(samples, sClk, sFifoReset.new_rst, dClk, dFifoReset.new_rst);\n \/\/ mask reg is set from a request in the dClk domain but used in the\n \/\/ sClk domain to determine triggering\n Reg#(Bit#(dataWidth)) maskReg <- mkSyncReg(0, dClk, dRst, sClk);\n \/\/ freeClockReg counts cycles to timestamp events\n Reg#(Bit#(32)) freeClockReg <- mkReg(0, clocked_by sClk, reset_by sRst);\n \/\/ countReg counts accumulated samples\n Reg#(Bit#(32)) countReg <- mkReg(0, clocked_by sClk, reset_by sRst);\n \/\/ countSyncReg repeats that value into the dClk domain\n Reg#(Bit#(32)) countSyncReg <- mkSyncReg(0, sClk, sFifoReset.new_rst, dClk);\n \/\/ oldData is used in the sample domain, to save the previous value\n Reg#(Bit#(dataWidth)) olddata <- mkReg(0, clocked_by sClk, reset_by sRst);\n Reg#(Bit#(1)) enableIndicationReg <- mkReg(0);\n \n rule doIndication (enableIndicationReg == 1);\n let v = dfifo.first();\n indication.reportEvent(v[63:32], v[31:0]);\n dfifo.deq();\n endrule\n \n rule freeClock;\n freeClockReg <= freeClockReg + 1;\n endrule\n \n interface BlueScopeEventPIO bse;\n \n method Action dataIn(Bit#(dataWidth) data);\/\/ if (stateReg != Idle);\n\t let c = countReg;\n\t if ((maskReg & (data ^ olddata)) != 0)\n begin\n\t if (dfifo.notFull())\n\t\t begin\n\t\t dfifo.enq({data, freeClockReg});\n\t\t countReg <= c + 1;\n\t\t countSyncReg <= c + 1;\n\t\t end\n\t else\n\t\t $display(\"bluescope.stall c=%d\", c);\n\t end\n\t olddata <= data;\n endmethod\n\n endinterface\n \n interface BlueScopeEventPIORequest requestIfc;\n\n method Action doReset();\n\t sFifoReset.assertReset();\n\t dFifoReset.assertReset();\n endmethod\n \n method Action setTriggerMask(Bit#(32) mask);\n\t maskReg <= truncate(mask);\n endmethod\n\n method Action getCounterValue();\n indication.counterValue(countSyncReg);\n endmethod\n\n method Action enableIndications(Bit#(32) en);\n\t enableIndicationReg <= en[0];\n endmethod\n\n endinterface\nendmodule\n\n","avg_line_length":38.427672956,"max_line_length":174,"alphanum_fraction":0.7237315876} {"size":952,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"package Take;\n\nimport Vector :: *;\n\nfunction Action displayabc (a abc) provisos (Bits #(a, sa));\n action\n $display (\"%d\", abc);\n endaction\nendfunction\n\n\n\nfunction Action display_list (Vector #(n,a) my_list) provisos (Bits # (a,sa));\n action\n joinActions ( map (displayabc, my_list));\n endaction\nendfunction\n\n\n\nmodule mkTestbench_Take();\n Vector #(5,Int #(4)) my_list1 = cons (0, cons (1, cons (2, cons (3, cons (4, nil)))));\n Vector #(2,Int #(4)) my_list2 = cons (0, cons(1, nil));\n Vector #(2,Int #(4)) my_list3 = take (my_list1);\n\n\n\n rule fire_once (True);\n $display (\"Original Vector:\");\n display_list (my_list1);\n $display (\"Taking two elements. New Vector:\");\n display_list (my_list3);\n if (my_list3 != my_list2 )\n $display (\"Simulation Fails\");\n else\n $display (\"Simulation Passes\");\n\t $finish(2'b00);\n endrule \n \nendmodule : mkTestbench_Take\nendpackage : Take\n","avg_line_length":22.6666666667,"max_line_length":89,"alphanum_fraction":0.6113445378} {"size":185,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"import Vector::*;\n\n\/\/ Div#(x,32,n) should imply Add#(x,_,TMul#(32,n))\n\nfunction Vector#(n, Bit#(32)) fn(Bit#(x) v)\n provisos(Div#(x,32,n));\n return unpack(zeroExtend(v));\nendfunction\n","avg_line_length":20.5555555556,"max_line_length":50,"alphanum_fraction":0.6378378378} {"size":70,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"module mkFoo();\n rule bogus;\n Bool x = True;\n endrule\nendmodule\n\n","avg_line_length":10.0,"max_line_length":18,"alphanum_fraction":0.6428571429} {"size":1394,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"\/\/Signal from Argument to Return value of the same method, \n\/\/The combinational loop is completed at the top level\n\/\/Should report an error with -verilog flag\n\npackage Argument2ReturnValue2;\n\nimport FIFO :: *;\n\ninterface Argument2ReturnValue2Interv;\n method Action start (Bit #(8) inp);\n method Bit #(8) result();\nendinterface\n\nimport \"BVI\" Imported_Verilog =\n module mkArgument2ReturnValue2v (Argument2ReturnValue2Interv);\n method start (Input) enable(En_Input);\n method Result result();\n path (Input, Result);\n schedule start SB result;\n endmodule\n\ninterface Argument2ReturnValue2Inter;\n method ActionValue #(Bit #(8)) start (Bit #(8) inp);\nendinterface\n\n(* synthesize *)\n\nmodule [Module] mksubArgument2ReturnValue2(Argument2ReturnValue2Inter);\n \n Argument2ReturnValue2Interv dut();\n mkArgument2ReturnValue2v the_dut (dut);\n\n method ActionValue #(Bit #(8)) start (inp);\n dut.start (inp);\n return (dut.result);\n endmethod\n \nendmodule\n\n(* synthesize *)\nmodule [Module] mkArgument2ReturnValue2 ();\n \n Argument2ReturnValue2Inter dut();\n mksubArgument2ReturnValue2 the_dut(dut);\n \n RWire #(Bit #(8)) inwire();\n mkRWire the_inwire (inwire);\n \n rule always_fire;\n Bit #(8) temp <- (dut.start(unJust (inwire.wget))); \n inwire.wset (temp);\n endrule\n\n \nendmodule\n \n\nendpackage\n","avg_line_length":23.6271186441,"max_line_length":71,"alphanum_fraction":0.6822094692} {"size":8992,"ext":"bsv","lang":"Bluespec","max_stars_count":2.0,"content":"\n\/\/ Copyright (c) 2017 Massachusetts Institute of Technology\n\/\/ \n\/\/ Permission is hereby granted, free of charge, to any person\n\/\/ obtaining a copy of this software and associated documentation\n\/\/ files (the \"Software\"), to deal in the Software without\n\/\/ restriction, including without limitation the rights to use, copy,\n\/\/ modify, merge, publish, distribute, sublicense, and\/or sell copies\n\/\/ of the Software, and to permit persons to whom the Software is\n\/\/ furnished to do so, subject to the following conditions:\n\/\/ \n\/\/ The above copyright notice and this permission notice shall be\n\/\/ included in all copies or substantial portions of the Software.\n\/\/ \n\/\/ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\/\/ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\/\/ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n\/\/ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n\/\/ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n\/\/ ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n\/\/ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n\/\/ SOFTWARE.\n\n`include \"ProcConfig.bsv\"\n\nimport Types::*;\nimport ProcTypes::*;\nimport Vector::*;\n\n(* noinline *)\nfunction Data alu(Data a, Data b, AluFunc func);\n Data res = (case(func)\n Add : (a + b);\n Addw : signExtend((a + b)[31:0]);\n Sub : (a - b);\n Subw : signExtend((a[31:0] - b[31:0])[31:0]);\n And : (a & b);\n Or : (a | b);\n Xor : (a ^ b);\n Slt : zeroExtend( pack( signedLT(a, b) ) );\n Sltu : zeroExtend( pack( a < b ) );\n Sll : (a << b[5:0]);\n Sllw : signExtend((a[31:0] << b[4:0])[31:0]);\n Srl : (a >> b[5:0]);\n Sra : signedShiftRight(a, b[5:0]);\n Srlw : signExtend((a[31:0] >> b[4:0])[31:0]);\n Sraw : signExtend(signedShiftRight(a[31:0], b[4:0])[31:0]);\n Csrw : b;\n Csrs : (a | b); \/\/ same as Or\n Csrc : (a & ~b);\n default : 0;\n endcase);\n return res;\nendfunction\n\n(* noinline *)\nfunction Bool aluBr(Data a, Data b, BrFunc brFunc);\n Bool brTaken = (case(brFunc)\n Eq : (a == b);\n Neq : (a != b);\n Lt : signedLT(a, b);\n Ltu : (a < b);\n Ge : signedGE(a, b);\n Geu : (a >= b);\n AT : True;\n NT : False;\n default : False;\n endcase);\n return brTaken;\nendfunction\n\n(* noinline *)\nfunction Addr brAddrCalc(Addr pc, Data val, IType iType, Data imm, Bool taken, Bit #(32) orig_inst);\n Addr fallthrough_incr = ((orig_inst [1:0] == 2'b11) ? 4 : 2);\n Addr pcPlusN = pc + fallthrough_incr;\n Addr targetAddr = (case (iType)\n J : (pc + imm);\n Jr : {(val + imm)[valueOf(AddrSz)-1:1], 1'b0};\n Br : (taken? pc + imm : pcPlusN);\n default : pcPlusN;\n endcase);\n return targetAddr;\nendfunction\n\n(* noinline *)\nfunction ControlFlow getControlFlow(DecodedInst dInst, Data rVal1, Data rVal2, Addr pc, Addr ppc, Bit #(32) orig_inst);\n ControlFlow cf = unpack(0);\n\n Bool taken = dInst.execFunc matches tagged Br .br_f ? aluBr(rVal1, rVal2, br_f) : False;\n Addr nextPc = brAddrCalc(pc, rVal1, dInst.iType, validValue(getDInstImm(dInst)), taken, orig_inst);\n Bool mispredict = nextPc != ppc;\n\n cf.pc = pc;\n cf.nextPc = nextPc;\n cf.taken = taken;\n cf.mispredict = mispredict;\n\n return cf;\nendfunction\n\n(* noinline *)\nfunction ExecResult basicExec(DecodedInst dInst, Data rVal1, Data rVal2, Addr pc, Addr ppc, Bit #(32) orig_inst);\n \/\/ just data, addr, and control flow\n Data data = 0;\n Data csr_data = 0;\n Addr addr = 0;\n ControlFlow cf = ControlFlow{pc: pc, nextPc: 0, taken: False, mispredict: False};\n\n Data aluVal2 = fromMaybe(rVal2, getDInstImm(dInst)); \/\/isValid(dInst.imm) ? fromMaybe(?, dInst.imm) : rVal2;\n \/\/ Get the alu function. By default, it adds. This is used by memory instructions\n AluFunc alu_f = dInst.execFunc matches tagged Alu .alu_f ? alu_f : Add;\n Data alu_result = alu(rVal1, aluVal2, alu_f);\n\n \/\/ Default branch function is not taken\n BrFunc br_f = dInst.execFunc matches tagged Br .br_f ? br_f : NT;\n cf.taken = aluBr(rVal1, rVal2, br_f);\n cf.nextPc = brAddrCalc(pc, rVal1, dInst.iType, validValue(getDInstImm(dInst)), cf.taken, orig_inst);\n cf.mispredict = cf.nextPc != ppc;\n\n Addr fallthrough_incr = ((orig_inst [1:0] == 2'b11) ? 4 : 2);\n\n data = (case (dInst.iType)\n St, Sc, Amo : rVal2;\n J, Jr : (pc + fallthrough_incr); \/\/ could be computed with alu\n Auipc : (pc + fromMaybe(?, getDInstImm(dInst))); \/\/ could be computed with alu\n Csr : rVal1;\n default : alu_result;\n endcase);\n csr_data = alu_result;\n addr = (case (dInst.iType)\n Ld, St, Lr, Sc, Amo : alu_result;\n default : cf.nextPc;\n endcase);\n\n return ExecResult{data: data, csrData: csr_data, addr: addr, controlFlow: cf};\nendfunction\n\n(* noinline *)\nfunction Maybe#(Exception) checkForException(\n DecodedInst dInst,\n ArchRegs regs,\n CsrDecodeInfo csrState\n); \/\/ regs needed to check if x0 is a src\n Maybe#(Exception) exception = Invalid;\n let prv = csrState.prv;\n\n if(dInst.iType == Ecall) begin\n exception = Valid (case(prv)\n prvU: EnvCallU;\n prvS: EnvCallS;\n prvM: EnvCallM;\n default: IllegalInst;\n endcase);\n end\n else if(dInst.iType == Ebreak) begin\n exception = Valid (Breakpoint);\n end\n else if(dInst.iType == Mret) begin\n if(prv < prvM) begin\n exception = Valid (IllegalInst);\n end\n end\n else if(dInst.iType == Sret) begin\n if(prv < prvS) begin\n exception = Valid (IllegalInst);\n end\n else if(prv == prvS && csrState.trapSret) begin\n exception = Valid (IllegalInst);\n end\n end\n else if(dInst.iType == SFence) begin\n if(prv == prvS && csrState.trapVM) begin\n exception = Valid (IllegalInst);\n end\n end\n else if(dInst.iType == Csr) begin\n let csr = pack(fromMaybe(?, dInst.csr));\n Bool csr_has_priv = (prv >= csr[9:8]);\n if(!csr_has_priv) begin\n exception = Valid (IllegalInst);\n end\n else if(prv == prvS && csrState.trapVM &&\n validValue(dInst.csr) == CSRsatp) begin\n exception = Valid (IllegalInst);\n end\n \/\/ TODO check permission for accessing cycle\/inst\/time, and check\n \/\/ read-only CSRs being written\n end\n else if(dInst.iType == Fpu) begin\n if(dInst.execFunc matches tagged Fpu .fpu_f) begin\n \/\/ Get rounding mode\n let rm = (fpu_f.rm == RDyn) ? unpack(csrState.frm) : fpu_f.rm;\n case(rm)\n RNE, RTZ, RDN, RUP, RMM: exception = exception; \/\/ legal modes\n default : exception = Valid (IllegalInst);\n endcase\n end\n else begin\n \/\/ Fpu instruction without FPU execFunc\n exception = Valid (IllegalInst);\n end\n end\n\n return exception;\nendfunction\n\n\/\/ check mem access misaligned: byteEn is unshifted (just from Decode)\nfunction Bool memAddrMisaligned(Addr addr, ByteEn byteEn);\n if(byteEn[7]) begin\n return addr[2:0] != 0;\n end\n else if(byteEn[3]) begin\n return addr[1:0] != 0;\n end\n else if(byteEn[1]) begin\n return addr[0] != 0;\n end\n else begin\n return False;\n end\nendfunction\n\nfunction Data gatherLoad(Addr addr, ByteEn byteEn, Bool unsignedLd, Data data);\n function extend = unsignedLd ? zeroExtend : signExtend;\n Bit#(IndxShamt) offset = truncate(addr);\n\n if(byteEn[7]) begin\n return extend(data);\n end else if(byteEn[3]) begin\n Vector#(2, Bit#(32)) dataVec = unpack(data);\n return extend(dataVec[offset[2]]);\n end else if(byteEn[1]) begin\n Vector#(4, Bit#(16)) dataVec = unpack(data);\n return extend(dataVec[offset[2:1]]);\n end else begin\n Vector#(8, Bit#(8)) dataVec = unpack(data);\n return extend(dataVec[offset]);\n end\nendfunction\n\nfunction Tuple2#(ByteEn, Data) scatterStore(Addr addr, ByteEn byteEn, Data data);\n Bit#(IndxShamt) offset = truncate(addr);\n if(byteEn[7]) begin\n return tuple2(byteEn, data);\n end else if(byteEn[3]) begin\n return tuple2(unpack(pack(byteEn) << (offset)), data << {(offset), 3'b0});\n end else if(byteEn[1]) begin\n return tuple2(unpack(pack(byteEn) << (offset)), data << {(offset), 3'b0});\n end else begin\n return tuple2(unpack(pack(byteEn) << (offset)), data << {(offset), 3'b0});\n end\nendfunction\n\n","avg_line_length":35.4015748031,"max_line_length":119,"alphanum_fraction":0.5859653025} {"size":945,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"package VectorBug;\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nimport Vector::*;\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ninterface Test;\n interface Vector#(3, Reg#(Bit#(8))) zaz;\nendinterface\n\n\n(* synthesize *)\nmodule mkTest0 (Test);\n\n Vector#(3, Reg#(Bit#(8))) reg_vector = newVector;\n \n for (Integer i = 0; i < 3; i = i + 1)\n begin\n\t reg_vector[i] <- mkReg(0);\n end\n \n interface Vector zaz = reg_vector;\n \nendmodule\n\n(* synthesize *)\nmodule mkTest1 (Test);\n\n Vector#(3, Reg#(Bit#(8))) reg_vector = ?;\n \n for (Integer i = 0; i < 3; i = i + 1)\n begin\n\t reg_vector[i] <- mkReg(0);\n end\n \n interface Vector zaz = reg_vector;\n \nendmodule\n\n\nendpackage","avg_line_length":20.1063829787,"max_line_length":80,"alphanum_fraction":0.3788359788} {"size":10430,"ext":"bsv","lang":"Bluespec","max_stars_count":7.0,"content":"\/\/ Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved.\n\n\/\/-\n\/\/ AXI (user fields) modifications:\n\/\/ Copyright (c) 2019 Alexandre Joannou\n\/\/ Copyright (c) 2019 Peter Rugg\n\/\/ Copyright (c) 2019 Jonathan Woodruff\n\/\/ All rights reserved.\n\/\/\n\/\/ This software was developed by SRI International and the University of\n\/\/ Cambridge Computer Laboratory (Department of Computer Science and\n\/\/ Technology) under DARPA contract HR0011-18-C-0016 (\"ECATS\"), as part of the\n\/\/ DARPA SSITH research programme.\n\/\/-\n\npackage P1_Core;\n\n\/\/ ================================================================\n\/\/ This package defines the interface and implementation of the 'P1 Core'\n\/\/ for the DARPA SSITH project.\n\/\/ This P1 core contains:\n\/\/ - Piccolo CPU, including\n\/\/ - Near_Mem (ICache and DCache)\n\/\/ - Near_Mem_IO (Timer, Software-interrupt, and other mem-mapped-locations)\n\/\/ - External interrupt request lines\n\/\/ - 2 x AXI4 Master interfaces (from DM and ICache, and from DCache)\n\/\/ - RISC-V Debug Module (DM)\n\/\/ - JTAG TAP interface for DM\n\/\/ - Optional Tandem Verification trace stream output interface\n\n\/\/ ================================================================\n\/\/ BSV library imports\n\nimport Vector :: *;\nimport FIFO :: *;\nimport GetPut :: *;\nimport ClientServer :: *;\nimport Connectable :: *;\nimport Bus :: *;\n\n\/\/ ----------------\n\/\/ BSV additional libs\n\nimport GetPut_Aux :: *;\nimport Semi_FIFOF :: *;\n\n\/\/ ================================================================\n\/\/ Project imports\n\nimport SoC_Map :: *;\n\n\/\/ The basic core\nimport Core_IFC :: *;\nimport Core :: *;\n\n\/\/ External interrupt request interface\nimport PLIC :: *; \/\/ for PLIC_Source_IFC type which is exposed at P2_Core interface\n\n\/\/ Main Fabric\nimport AXI4 :: *;\nimport Fabric_Defs :: *;\n\n`ifdef INCLUDE_DMEM_SLAVE\nimport AXI4_Lite_Types :: *;\n`endif\n\n`ifdef INCLUDE_TANDEM_VERIF\nimport TV_Info :: *;\nimport AXI4_Stream ::*;\n`endif\n\n`ifdef INCLUDE_GDB_CONTROL\nimport Debug_Module :: *;\nimport JtagTap :: *;\nimport Giraffe_IFC :: *;\n`endif\n\n\/\/ ================================================================\n\/\/ The P1_Core interface\n\ninterface P1_Core_IFC;\n\n \/\/ ----------------------------------------------------------------\n \/\/ Core CPU interfaces\n\n \/\/ CPU IMem to Fabric master interface\n interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data,\n 0, 0, 0, 0, 0) master0;\n\n \/\/ CPU DMem (incl. I\/O) to Fabric master interface\n interface AXI4_Master_Synth #( Wd_MId_ext, Wd_Addr, Wd_Data\n , Wd_AW_User_ext, Wd_W_User_ext, Wd_B_User_ext\n , Wd_AR_User_ext, Wd_R_User_ext) master1;\n\n \/\/ External interrupt sources\n (* always_ready, always_enabled, prefix=\"\" *)\n method Action interrupt_reqs ((* port=\"cpu_external_interrupt_req\" *) Bit #(N_External_Interrupt_Sources) reqs);\n\n`ifdef INCLUDE_DMEM_SLAVE\n \/\/ ----------------------------------------------------------------\n \/\/ Optional AXI4-Lite D-cache slave interface\n\n interface AXI4_Lite_Slave_IFC #(Wd_Addr, Wd_Data, Wd_User) slave0;\n`endif\n\n`ifdef INCLUDE_TANDEM_VERIF\n \/\/ ----------------------------------------------------------------\n \/\/ Optional Tandem Verifier interface. The data signal is\n \/\/ packed output tuples (n,vb),\/ where 'vb' is a vector of\n \/\/ bytes with relevant bytes in locations [0]..[n-1]\n\n interface AXI4_Stream_Master_IFC #(Wd_SId, Wd_SDest, Wd_SData, Wd_SUser) tv_verifier_info_tx;\n`endif\n\n`ifdef INCLUDE_GDB_CONTROL\n \/\/ ----------------\n \/\/ JTAG interface\n\n`ifdef JTAG_TAP\n interface JTAG_IFC jtag;\n`endif\n`endif\nendinterface\n\n\/\/ ================================================================\n\n(* synthesize *)\nmodule mkP1_Core (P1_Core_IFC);\n\n \/\/ Core: CPU + Near_Mem_IO (CLINT) + PLIC + Debug module (optional) + TV (optional)\n Core_IFC::Core_IFC_Synth #(N_External_Interrupt_Sources) core <- mkCore_Synth;\n\n \/\/ ================================================================\n \/\/ Tie-offs (not used in SSITH GFE)\n\n \/\/ Set core's verbosity\n rule rl_never (False);\n core.set_verbosity (?, ?);\n endrule\n\n \/\/ Tie-offs\n rule rl_always (True);\n \/\/ Non-maskable interrupt request.\n core.nmi_req (False);\n endrule\n\n \/\/ ================================================================\n \/\/ Reset on startup, and also on NDM reset from Debug Module\n \/\/ (NDM reset from Debug Module = \"non-debug-module-reset\" = reset all except Debug Module)\n\n Reg #(Bool) rg_once <- mkReg (False);\n Reg #(Maybe #(Bool)) rg_ndm_reset <- mkReg (tagged Invalid);\n\n rule rl_once (! rg_once);\n Bool running = True;\n if (rg_ndm_reset matches tagged Valid False)\n\t running = False;\n core.cpu_reset_server.request.put (running);\n rg_once <= True;\n endrule\n\n rule rl_reset_response;\n let running <- core.cpu_reset_server.response.get;\n\n`ifdef INCLUDE_GDB_CONTROL\n \/\/ Respond to Debug module if this is an ndm-reset\n if (rg_ndm_reset matches tagged Valid .x) begin\n\t core.ndm_reset_client.response.put (running);\n end\n rg_ndm_reset <= tagged Invalid;\n`endif\n endrule\n\n \/\/ ----------------\n \/\/ Also do a reset if requested from Debug Module (NDM = Non-Debug-Module reset)\n\n rule rl_ndmreset (rg_once);\n`ifdef INCLUDE_GDB_CONTROL\n let running <- core.ndm_reset_client.request.get;\n rg_ndm_reset <= tagged Valid running;\n`endif\n\n rg_once <= False;\n endrule\n\n \/\/ ================================================================\n`ifdef INCLUDE_GDB_CONTROL\n\n \/\/ Instantiate JTAG TAP controller,\n \/\/ connect to core.dm_dmi;\n \/\/ and export its JTAG interface\n\n Wire#(Bit#(7)) w_dmi_req_addr <- mkDWire(0);\n Wire#(Bit#(32)) w_dmi_req_data <- mkDWire(0);\n Wire#(Bit#(2)) w_dmi_req_op <- mkDWire(0);\n\n Wire#(Bit#(32)) w_dmi_rsp_data <- mkDWire(0);\n Wire#(Bit#(2)) w_dmi_rsp_response <- mkDWire(0);\n\n BusReceiver#(Tuple3#(Bit#(7),Bit#(32),Bit#(2))) bus_dmi_req <- mkBusReceiver;\n BusSender#(Tuple2#(Bit#(32),Bit#(2))) bus_dmi_rsp <- mkBusSender(unpack(0));\n\n`ifdef JTAG_TAP\n let jtagtap <- mkJtagTap;\n\n mkConnection(jtagtap.dmi.req_ready, pack(bus_dmi_req.in.ready));\n mkConnection(jtagtap.dmi.req_valid, compose(bus_dmi_req.in.valid, unpack));\n mkConnection(jtagtap.dmi.req_addr, w_dmi_req_addr._write);\n mkConnection(jtagtap.dmi.req_data, w_dmi_req_data._write);\n mkConnection(jtagtap.dmi.req_op, w_dmi_req_op._write);\n mkConnection(jtagtap.dmi.rsp_valid, pack(bus_dmi_rsp.out.valid));\n mkConnection(jtagtap.dmi.rsp_ready, compose(bus_dmi_rsp.out.ready, unpack));\n mkConnection(jtagtap.dmi.rsp_data, w_dmi_rsp_data);\n mkConnection(jtagtap.dmi.rsp_response, w_dmi_rsp_response);\n`endif\n\n rule rl_dmi_req;\n bus_dmi_req.in.data(tuple3(w_dmi_req_addr, w_dmi_req_data, w_dmi_req_op));\n endrule\n\n rule rl_dmi_rsp;\n match {.data, .response} = bus_dmi_rsp.out.data;\n w_dmi_rsp_data <= data;\n w_dmi_rsp_response <= response;\n endrule\n\n (* preempts = \"rl_dmi_req_cpu, rl_dmi_rsp_cpu\" *)\n rule rl_dmi_req_cpu;\n match {.addr, .data, .op} = bus_dmi_req.out.first;\n bus_dmi_req.out.deq;\n case (op)\n\t 1: core.dm_dmi.read_addr(addr);\n\t 2: begin\n\t core.dm_dmi.write(addr, data);\n\t bus_dmi_rsp.in.enq(tuple2(?, 0));\n\t end\n\t default: bus_dmi_rsp.in.enq(tuple2(?, 2));\n endcase\n endrule\n\n rule rl_dmi_rsp_cpu;\n let data <- core.dm_dmi.read_data;\n bus_dmi_rsp.in.enq(tuple2(data, 0));\n endrule\n\n`endif\n\n`ifdef INCLUDE_TANDEM_VERIF\n let tv_xactor <- mkTV_Xactor;\n mkConnection (core.tv_verifier_info_get, tv_xactor.tv_in);\n`endif\n\n \/\/ ================================================================\n \/\/ INTERFACE\n\n \/\/ CPU IMem to Fabric master interface\n interface master0 = core.cpu_imem_master;\n\n \/\/ CPU DMem to Fabric master interface\n interface master1 = core.cpu_dmem_master;\n\n \/\/ External interrupts\n method Action interrupt_reqs (Bit #(N_External_Interrupt_Sources) reqs);\n for (Integer j = 0; j < valueOf (N_External_Interrupt_Sources); j = j + 1) begin\n\t Bool req_j = unpack (reqs [j]);\n\t core.core_external_interrupt_sources [j].m_interrupt_req (req_j);\n end\n endmethod\n\n`ifdef INCLUDE_DMEM_SLAVE\n \/\/ ----------------------------------------------------------------\n \/\/ Optional AXI4-Lite D-cache slave interface\n\n interface AXI4_Lite_Slave_IFC slave0 = core.cpu_dmem_slave;\n`endif\n\n`ifdef INCLUDE_TANDEM_VERIF\n \/\/ ----------------------------------------------------------------\n \/\/ Optional Tandem Verifier interface. The data signal is\n \/\/ packed output tuples (n,vb),\/ where 'vb' is a vector of\n \/\/ bytes with relevant bytes in locations [0]..[n-1]\n\n interface tv_verifier_info_tx = tv_xactor.axi_out;\n`endif\n\n`ifdef INCLUDE_GDB_CONTROL\n \/\/ ----------------------------------------------------------------\n \/\/ Optional Debug Module interfaces\n\n`ifdef JTAG_TAP\n interface JTAG_IFC jtag = jtagtap.jtag;\n`endif\n\n`endif\nendmodule\n\n\/\/ ================================================================\n\/\/ The TV to AXI4 Stream transactor\n\n`ifdef INCLUDE_TANDEM_VERIF\n\n\/\/ ================================================================\n\/\/ TV AXI4 Stream Parameters\n\ntypedef SizeOf #(Info_CPU_to_Verifier)Wd_SData;\ntypedef 0 Wd_SDest;\ntypedef 0 Wd_SUser;\ntypedef 0 Wd_SId;\n\n\/\/ ================================================================\n\ninterface TV_Xactor;\n interface Put #(Info_CPU_to_Verifier) tv_in;\n interface AXI4_Stream_Master_IFC #(Wd_SId, Wd_SDest, Wd_SData, Wd_SUser) axi_out;\nendinterface\n\nfunction AXI4_Stream #(Wd_SId, Wd_SDest, Wd_SData, Wd_SUser) fn_TVToAxiS (Info_CPU_to_Verifier x);\n return AXI4_Stream {tid: ?,\n\t\t tdata: pack(x),\n\t\t tstrb: '1,\n\t\t tkeep: '1,\n\t\t tlast: True,\n\t\t tdest: ?,\n\t\t tuser: ? };\nendfunction\n\n(*synthesize*)\nmodule mkTV_Xactor (TV_Xactor);\n AXI4_Stream_Master_Xactor_IFC #(Wd_SId, Wd_SDest, Wd_SData, Wd_SUser)\n tv_xactor <- mkAXI4_Stream_Master_Xactor;\n\n interface Put tv_in;\n method Action put(x);\n\t toPut(tv_xactor.i_stream).put(fn_TVToAxiS(x));\n endmethod\n endinterface\n\n interface axi_out = tv_xactor.axi_side;\nendmodule\n`endif\n\n\/\/ ================================================================\n\nendpackage\n","avg_line_length":30.231884058,"max_line_length":117,"alphanum_fraction":0.5980824545} {"size":3740,"ext":"bsv","lang":"Bluespec","max_stars_count":1.0,"content":"\/\/ Copyright (c) 2008- 2009 Bluespec, Inc. All rights reserved.\n\/\/ $Revision$\n\/\/ $Date$\n\npackage SceMiDiniPCIE;\n\n\/\/ This is an implementation of SceMi over PCI-Express using the\n\/\/ BlueNoC connection through FPGA Q.\n\nimport Clocks :: *;\nimport Connectable :: *;\nimport TieOff :: *;\nimport DefaultValue :: *;\nimport AlteraCells :: *;\nimport BlueNoC :: *;\nimport NoCUtils :: *;\n\nimport SceMiDefines :: *;\nimport SceMiInternals :: *;\nimport SceMiNoC :: *;\n\n\/\/ Interface wrapper for PCIE\ninterface SceMiDiniPCIEIfc#(type i);\n interface i orig_ifc;\n interface TrainingSignals training;\n interface FPGASource#(BPB) source;\n interface FPGASink#(BPB) sink;\n interface MsgPort#(BPB) noc_cont;\n (* always_ready *)\n method Bool isLinkUp();\n (* always_ready *)\n method Bool isOutOfReset();\n (* always_ready *)\n method Bool isClockAdvancing();\nendinterface\n\n\/\/ Argument structure used for passing in clocks and resets\ntypedef struct {\n Clock fpga_clk;\n Reset fpga_rst;\n Clock noc_q_clk;\n Clock noc_a_clk;\n Reset noc_reset_n;\n SceMiLinkType link_type;\n} SceMiDiniPCIEArgs;\n\n\/\/ This module builds the transactor hierarchy, the clock\n\/\/ generation logic and the PCIE-to-port logic.\n(* no_default_clock, no_default_reset *)\nmodule [Module] buildSceMiPCIEDini#( SceMiModule#(i) mod\n , Clock fpga_clk\n , Reset fpga_rst\n , Clock noc_q_clk\n\t\t\t\t , Clock noc_a_clk\n\t\t\t\t , Reset noc_reset_n\n , SceMiLinkType link_type\n )\n (SceMiDiniPCIEIfc#(i));\n\n \/\/ Create a reset to use with the NoC Q clock domain\n Reset noc_q_rst <- mkAsyncReset(4,noc_reset_n,noc_q_clk);\n Reset noc_a_rst <- mkAsyncReset(4,noc_reset_n,noc_a_clk);\n \n \/\/ Instantiate the NoC connection to FPGA Q\n FPGAMsgPort#(BPB) to_fpga_q <- mkFPGAMsgPort(noc_q_clk, clocked_by noc_a_clk, reset_by noc_a_rst);\n\n \/\/ The fpga clock (G0) is the base SCE-MI clock, but we want to\n \/\/ propagate loss-of-partner as a reset to the SCE-MI system\n MakeResetIfc network_status <- mkReset(0, True, fpga_clk, clocked_by noc_a_clk, reset_by noc_a_rst);\n\n (* fire_when_enabled, no_implicit_conditions *)\n rule reset_scemi_if_fpga_q_is_not_present if (!to_fpga_q.status.partner_detected());\n network_status.assertReset();\n endrule\n\n Clock scemiClock = fpga_clk;\n Reset scemiReset <- mkResetEither(fpga_rst, network_status.new_rst, clocked_by fpga_clk);\n\n \/\/ Build the design with a NoC connection\n SceMiNoCIfc#(i) _dut <- buildSceMiNoC( mod\n , noc_a_clk\n , noc_a_rst\n , to_fpga_q.status.partner_detected()\n , link_type\n , clocked_by scemiClock\n , reset_by scemiReset\n );\n mkConnection(_dut.noc_src,to_fpga_q.noc);\n\n \/\/ Pass along the required interface elements\n interface orig_ifc = _dut.orig_ifc;\n interface training = to_fpga_q.pins.training;\n interface source = to_fpga_q.pins.source;\n interface sink = to_fpga_q.pins.sink;\n interface noc_cont = _dut.noc_cont;\n method Bool isLinkUp = to_fpga_q.status.partner_detected();\n method Bool isOutOfReset = _dut.isOutOfReset();\n method Bool isClockAdvancing = _dut.isClockAdvancing();\n\nendmodule: buildSceMiPCIEDini\n\nendpackage: SceMiDiniPCIE\n","avg_line_length":36.3106796117,"max_line_length":103,"alphanum_fraction":0.6106951872} {"size":459,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"(* synthesize *)\nmodule sysPortArg_ImplCond ();\n \/\/ This has an implicit conditions\n Wire#(Bool) w <- mkWire;\n\n \/\/ The instantiation with an illegal argument expression\n Empty s <- mkPortArg_ImplCond_Sub(w);\n\n \/\/ driver for the wire\n Reg#(Bool) b <- mkReg(True);\n rule r (b);\n w <= True;\n b <= False;\n endrule\nendmodule\n\n(* synthesize *)\nmodule mkPortArg_ImplCond_Sub #(Bool b) ();\n rule r;\n $display(b);\n endrule\nendmodule\n","avg_line_length":19.9565217391,"max_line_length":59,"alphanum_fraction":0.6339869281} {"size":1227,"ext":"bsv","lang":"Bluespec","max_stars_count":12.0,"content":"\/\/ Copyright (c) 2016 Cornell University.\n\n\/\/ Permission is hereby granted, free of charge, to any person\n\/\/ obtaining a copy of this software and associated documentation\n\/\/ files (the \"Software\"), to deal in the Software without\n\/\/ restriction, including without limitation the rights to use, copy,\n\/\/ modify, merge, publish, distribute, sublicense, and\/or sell copies\n\/\/ of the Software, and to permit persons to whom the Software is\n\/\/ furnished to do so, subject to the following conditions:\n\n\/\/ The above copyright notice and this permission notice shall be\n\/\/ included in all copies or substantial portions of the Software.\n\n\/\/ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\/\/ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\/\/ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n\/\/ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n\/\/ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n\/\/ ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n\/\/ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n\/\/ SOFTWARE.\n\ntypedef enum {\n INSTANCE,\n ROLE,\n ROUND,\n VROUND,\n VALUE\n} ExternReg deriving (Bits, Eq, FShow);\n\n\n","avg_line_length":38.34375,"max_line_length":70,"alphanum_fraction":0.7530562347} {"size":222,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"import StmtFSM::*;\n\nmodule sysCaseStmt();\n Reg#(int) rg <- mkReg(0);\n mkAutoFSM\n (seq\n case (mreg)\n 0 : noAction;\n default : noAction;\n endcase\n endseq);\nendmodule\n\n","avg_line_length":15.8571428571,"max_line_length":32,"alphanum_fraction":0.4954954955} {"size":619,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"package All;\n\nimport ListN :: *;\nfunction Bool f (Int #(32) a);\n if (a < 0)\n return False;\n else\n return True;\nendfunction\n\n\nmodule mkTestbench_All();\n ListN #(5,Int #(32)) my_list1 = cons (4, cons (-3, cons (-2, cons (1,cons (0,nil)))));\n ListN #(5,Int #(32)) my_list2 = cons (4, cons (3, cons (2, cons (1,cons (0,nil)))));\n\n\n\n rule fire_once (True);\n if (all(f, my_list1) != False || any(f, my_list2) != True) \n $display (\"Simulation Fails\");\n else\n $display (\"Simulation Passes\");\n\t $finish(2'b00);\n endrule \n \nendmodule : mkTestbench_All\nendpackage : All\n","avg_line_length":22.1071428571,"max_line_length":89,"alphanum_fraction":0.5654281099} {"size":44910,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"\/\/ Copyright (c) 2020 Bluespec, Inc. All rights reserved.\n\/\/\n\/\/ SPDX-License-Identifier: BSD-3-Clause\n\npackage TLM3Defines;\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nimport BRAM::*;\nimport BUtils::*;\nimport CBus :: *;\nimport Connectable::*;\nimport DefaultValue::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport FShow::*;\nimport GetPut::*;\nimport Randomizable::*;\nimport Vector::*;\n\n`include \"TLM.defines\"\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ntypedef enum {DEFAULT, APB, AHB, AXI, AXI4} TLMFamily deriving(Bounded, Bits, Eq);\n\ntypedef TLMRequest#(`TLM_PRM_STD) TLMRequestStd;\ntypedef TLMResponse#(`TLM_PRM_STD) TLMResponseStd;\n\ntypedef enum {READ, WRITE, UNKNOWN} \t TLMCommand deriving(Bounded, Bits, Eq);\ntypedef enum {REGULAR, DEBUG, CONTROL, UNKNOWN} TLMMode deriving(Bounded, Bits, Eq);\ntypedef enum {INCR, WRAP, CNST, UNKNOWN} \t TLMBurstMode deriving(Bounded, Bits, Eq);\n\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\n\/\/ typedef enum {SUCCESS, ERROR, NO_RESPONSE, UNKNOWN} TLMStatus deriving(Bounded, Bits, Eq);\ntypedef enum {SUCCESS, ERROR, EXOKAY, UNKNOWN} TLMStatus deriving(Bounded, Bits, Eq);\n\ntypedef enum {NONE, \/\/ 0\n\t SPLIT_CONTINUE, \/\/ 1 (Ahb)\n\t RETRY, \/\/ 2 (Ahb)\n\t SPLIT, \/\/ 3 (Ahb)\n\t RW_ONLY, \/\/ 4\n\t UNMAPPED, \/\/ 5\n\t SLVERR, \/\/ 6 (Axi)\n\t DECERR \/\/ 7 (Axi)\n\t } TLMErrorCode deriving(Bounded, Bits, Eq, FShow);\n\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ntypedef enum {NORMAL, EXCLUSIVE, LOCKED, RESERVED} TLMLock deriving(Bounded, Bits, Eq);\n\n\/\/typedef UInt#(8) TLMBurstLength;\ntypedef UInt#(15) TLMBurstLong;\ntypedef Bit#(4) TLMQos;\n\ntypedef Bit#(id_size) TLMId#(`TLM_PRM_DCL);\ntypedef Bit#(addr_size) TLMAddr#(`TLM_PRM_DCL);\ntypedef Bit#(data_size) TLMData#(`TLM_PRM_DCL);\ntypedef Bit#(TDiv#(data_size, 8)) TLMByteEn#(`TLM_PRM_DCL);\ntypedef UInt#(length_size) TLMBLength#(`TLM_PRM_DCL);\ntypedef Bit#(user_size) TLMUser#(`TLM_PRM_DCL);\n\/\/ TLMUserPort is obsolete, but left as an alias, for backwards compatibility\ntypedef TLMUser#(`TLM_PRM) TLMUserPort#(`TLM_PRM_DCL);\n\ntypedef enum { BITS8, BITS16, BITS32, BITS64, BITS128, BITS256, BITS512, BITS1024} TLMBSize deriving(Bounded, Bits, Eq, FShow);\n\ntypedef enum {NO_CACHE, CACHE} TLMCache deriving(Bounded, Bits, Eq);\n\/\/typedef enum {NO_CACHE_MOD, CACHE_MOD} TLMCacheMod deriving(Bounded, Bits, Eq);\ntypedef enum {NO_MODIFY, MODIFY} TLMModify deriving(Bounded, Bits, Eq);\ntypedef enum {NO_BUFFER, BUFFER} TLMBuffer deriving(Bounded, Bits, Eq);\ntypedef enum {NO_ALLOCATE, ALLOCATE} TLMAllocate deriving(Bounded, Bits, Eq);\n\ntypedef enum {NORMAL, PRIVILEGED} TLMPrivilege deriving(Bounded, Bits, Eq);\ntypedef enum {SECURE, NON_SECURE} TLMSecurity deriving(Bounded, Bits, Eq);\ntypedef enum {DATA, INST} TLMAccess deriving(Bounded, Bits, Eq);\ntypedef enum {LAST, NOT_LAST, OPEN} TLMMark deriving(Bounded, Bits, Eq);\n\ntypedef Bit#(4) TLMRegion;\n\ntypedef struct {TLMCommand command;\n TLMMode mode;\n\t\tTLMAddr#(`TLM_PRM) addr;\n\t\tTLMUser#(`TLM_PRM) user_addr;\n\t\tTLMRegion region;\n\t\tTLMData#(`TLM_PRM) data;\n TLMBLength#(`TLM_PRM) b_length;\n\t\tTLMUser#(`TLM_PRM) user;\n\t\tTLMBEKind#(`TLM_PRM) byte_enable;\n TLMBurstMode burst_mode;\n TLMBSize b_size;\n TLMQos prty;\n\t\tTLMLock lock;\n\t\tTLMId#(`TLM_PRM) transaction_id;\n\t\t\/\/ protection parameters\n\t\tTLMPrivilege privilege;\n\t\tTLMSecurity security;\n TLMAccess access;\n\t\t\/\/ cache parameters\n\t\tTLMCache cache;\n\t\tTLMBuffer buffer;\n\t\tTLMAllocate read_allocate;\n\t\tTLMAllocate write_allocate;\n\t\tTLMMark mark;\n\t\tBool cntrl_flow;\n } RequestDescriptor#(`TLM_PRM_DCL) deriving (Eq, Bits, Bounded);\n\ntypedef struct {TLMData#(`TLM_PRM) data;\n\t\tTLMUser#(`TLM_PRM) user;\n\t\tTLMBEKind#(`TLM_PRM) byte_enable;\n\t\tTLMId#(`TLM_PRM) transaction_id;\n\t\tBool is_last;\n } RequestData#(`TLM_PRM_DCL) deriving (Eq, Bits, Bounded);\n\n\ntypedef union tagged {RequestDescriptor#(`TLM_PRM) Descriptor;\n RequestData#(`TLM_PRM) Data;\n } TLMRequest#(`TLM_PRM_DCL) deriving(Eq, Bits, Bounded);\n\ntypedef struct {TLMCommand command;\n\t\tTLMData#(`TLM_PRM) data;\n TLMStatus status;\n\t\tTLMUser#(`TLM_PRM) user;\n TLMQos prty;\n TLMId#(`TLM_PRM) transaction_id;\n\t\tBool is_last;\n\/\/\t\tBool cntrl_flow;\n } TLMResponse#(`TLM_PRM_DCL) deriving (Eq, Bits, Bounded);\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ninstance DefaultValue #(RequestDescriptor#(`TLM_PRM));\n function defaultValue ();\n RequestDescriptor#(`TLM_PRM) request;\n request.command = READ;\n request.mode = REGULAR;\n request.addr = 0;\n request.user_addr = 0;\n request.region = 0;\n request.data = 0;\n request.user = 0;\n request.b_length = 0;\n request.byte_enable = tagged Calculate;\n request.burst_mode = INCR;\n request.b_size = BITS32; \/\/ assume 32 bits for now.\n\/\/ request.b_size = getMaxBSize(valueOf(data_size));\n request.prty = 0;\n request.lock = NORMAL;\n request.transaction_id = 0;\n request.privilege = NORMAL;\n request.security = SECURE;\n request.access = DATA;\n request.cache = NO_CACHE;\n request.buffer = NO_BUFFER;\n request.read_allocate = NO_ALLOCATE;\n request.write_allocate = NO_ALLOCATE;\n request.mark = OPEN;\n request.cntrl_flow = False;\n return request;\n endfunction\nendinstance\n\ninstance DefaultValue #(RequestData#(`TLM_PRM));\n function defaultValue ();\n RequestData#(`TLM_PRM) request;\n request.data = 0;\n request.user = 0;\n request.byte_enable = tagged Calculate;\n request.transaction_id = 0;\n request.is_last = False;\n return request;\n endfunction\nendinstance\n\ninstance DefaultValue #(TLMResponse#(`TLM_PRM));\n function defaultValue ();\n TLMResponse#(`TLM_PRM) response;\n response.command = READ;\n response.data = 0;\n response.user = 0;\n response.status = SUCCESS;\n response.prty = 0;\n response.transaction_id = 0;\n\/\/ response.cntrl_flow = False;\n response.is_last = False;\n return response;\n endfunction\nendinstance\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ntypeclass TLMRequestTC#(type a, `TLM_PRM_DCL)\n dependencies (a determines (`TLM_PRM));\n function TLMRequest#(`TLM_PRM) toTLMRequest(a value);\n function a fromTLMRequest(TLMRequest#(`TLM_PRM) value);\nendtypeclass\n\ntypeclass TLMResponseTC#(type a, `TLM_PRM_DCL)\n dependencies (a determines (`TLM_PRM));\n function TLMResponse#(`TLM_PRM) toTLMResponse(a value);\n function a fromTLMResponse(TLMResponse#(`TLM_PRM) value);\nendtypeclass\n\ninstance TLMRequestTC#(TLMRequest#(`TLM_PRM), `TLM_PRM);\n function toTLMRequest = id;\n function fromTLMRequest = id;\nendinstance\n\ninstance TLMResponseTC#(TLMResponse#(`TLM_PRM), `TLM_PRM);\n function toTLMResponse = id;\n function fromTLMResponse = id;\nendinstance\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nmodule mkTLMRandomizer#(Maybe#(TLMCommand) m_command) (Randomize#(a))\n provisos(TLMRequestTC#(a, `TLM_PRM),\n Bits#(RequestDescriptor#(`TLM_PRM), s0),\n Bounded#(RequestDescriptor#(`TLM_PRM)),\n Bits#(RequestData#(`TLM_PRM), s1),\n Bounded#(RequestData#(`TLM_PRM))\n );\n\n Reg#(TLMBLength#(`TLM_PRM)) count <- mkReg(0);\n Randomize#(RequestDescriptor#(`TLM_PRM)) descriptor_gen <- mkGenericRandomizer;\n Randomize#(TLMCommand) command_gen <- mkConstrainedRandomizer(READ, WRITE); \/\/ Avoid UNKNOWN\n Randomize#(TLMBurstMode) burst_mode_gen <- mkConstrainedRandomizer(INCR, WRAP); \/\/ Avoid UNKNOWN\n Randomize#(TLMBLength#(`TLM_PRM)) burst_length_gen <- mkConstrainedRandomizer(0,15); \/\/ legal sizes between 1 and 16\n Randomize#(Bit#(2)) log_wrap_gen <- mkConstrainedRandomizer(1,3);\n Randomize#(RequestData#(`TLM_PRM)) data_gen <- mkGenericRandomizer;\n Reg#(TLMId#(`TLM_PRM)) id <- mkReg(0);\n\n\/\/ Randomize#(Bit#(TLog#(SizeOf#(TLMBurstSize#(`TLM_PRM))))) log_size_gen <- mkGenericRandomizer;\n TLMBSize max_size = unpack(fromInteger(valueOf(TLog#(TDiv#(data_size, 8)))));\n Randomize#(TLMBSize) b_size_gen <- mkConstrainedRandomizer(BITS8, max_size);\n\n interface Control cntrl;\n method Action init();\n \/\/ srand(0);\n descriptor_gen.cntrl.init();\n command_gen.cntrl.init();\n burst_mode_gen.cntrl.init();\n burst_length_gen.cntrl.init();\n log_wrap_gen.cntrl.init();\n data_gen.cntrl.init();\n b_size_gen.cntrl.init();\n endmethod\n endinterface\n\n method ActionValue#(a) next ();\n\n if (count == 0)\n begin\n let descriptor <- descriptor_gen.next;\n let burst_mode <- burst_mode_gen.next;\n\n descriptor.command <- command_gen.next;\n\n let b_size <- b_size_gen.next;\n\n descriptor.b_size = b_size;\n\n \/\/ align address to burst_size\n let addr = descriptor.addr;\n addr = addr >> pack(b_size);\n addr = addr << pack(b_size);\n descriptor.addr = addr;\n\n if (burst_mode == WRAP)\n begin\n let shift <- log_wrap_gen.next;\n let burst_length = 2 << shift; \/\/ wrap legal lengths are 2, 4, 8, 16\n descriptor.b_length = (burst_length - 1);\n descriptor.addr = addr;\n end\n else\n begin\n let burst_length <- burst_length_gen.next;\n descriptor.b_length = burst_length;\n end\n\n descriptor.command = case (m_command) matches\n tagged Just .x: x;\n default : descriptor.command;\n endcase;\n\n descriptor.mode = REGULAR;\n\/\/ descriptor.byte_enable = getTLMByteEnL(descriptor);\n\t if (descriptor.b_length == 0 && descriptor.command == WRITE)\n\t descriptor.byte_enable = tagged Specify getTLMByteEnL(descriptor);\n\t else\n\t descriptor.byte_enable = tagged Calculate;\n\n descriptor.burst_mode = burst_mode;\n\n\/\/ descriptor.thread_id = 0;\n descriptor.transaction_id = id;\n\/\/ descriptor.export_id = 0;\n\n if (descriptor.command == READ)\n begin\n descriptor.data = 0;\n\/\/ descriptor.byte_enable = '1;\n end\n\t a r = fromTLMRequest(tagged Descriptor descriptor);\n let request = toTLMRequest(r);\n let remaining = getTLMCycleCount(descriptor);\n count <= remaining;\n id <= (remaining == 0) ? id + 1 : id;\n return fromTLMRequest(request);\n end\n else\n begin\n let data <- data_gen.next();\n data.transaction_id = unpack({0, id});\n\t TLMRequest#(`TLM_PRM) request = tagged Data data;\n let remaining = count - 1;\n count <= remaining;\n id <= (remaining == 0) ? id + 1 : id;\n return fromTLMRequest(request);\n end\n\n endmethod\n\nendmodule\n\ninstance Randomizable#(TLMRequest#(`TLM_PRM))\n provisos(Bits#(RequestDescriptor#(`TLM_PRM), s0),\n Bounded#(RequestDescriptor#(`TLM_PRM)),\n Bits#(RequestData#(`TLM_PRM), s1),\n Bounded#(RequestData#(`TLM_PRM))\n );\n\n module mkRandomizer (Randomize#(TLMRequest#(`TLM_PRM)));\n let ifc <- mkTLMRandomizer(Invalid);\n return ifc;\n endmodule\n\nendinstance\n\n\nmodule mkTLMSource#(Maybe#(TLMCommand) m_command, Bool verbose) (TLMSendIFC#(`TLM_RR))\n provisos(TLMRequestTC#(req_t, `TLM_PRM),\n\t TLMResponseTC#(resp_t, `TLM_PRM),\n\t Bits#(resp_t, s0));\n\n Reg#(Bool) initialized <- mkReg(False);\n\n FIFO#(resp_t) response_fifo <- mkFIFO;\n Randomize#(req_t) gen <- mkTLMRandomizer(m_command);\n\n rule start (!initialized);\n gen.cntrl.init;\n initialized <= True;\n endrule\n\n rule grab_responses;\n let value = toTLMResponse(response_fifo.first);\n response_fifo.deq;\n if (verbose) $display(\"(%0d) Response is: \", $time, fshow(value));\n endrule\n\n interface Get tx;\n method ActionValue#(req_t) get;\n let value <- gen.next;\n if (toTLMRequest(value) matches tagged Descriptor .d)\n if (verbose) $display(\"(%0d) Request is: \", $time, fshow(d));\n return value;\n endmethod\n endinterface\n\n interface Put rx = toPut(response_fifo);\n\nendmodule\n\n\n\nmodule mkTLMSourceStd#(Maybe#(TLMCommand) m_command, Bool verbose) (TLMSendIFC#(TLMRequestStd, TLMResponseStd));\n\n Reg#(Bool) initialized <- mkReg(False);\n FIFO#(TLMResponseStd) response_fifo <- mkFIFO;\n Randomize#(TLMRequestStd) gen <- mkTLMRandomizer(m_command);\n\n rule start (!initialized);\n gen.cntrl.init;\n initialized <= True;\n endrule\n\n rule grab_responses;\n let value = response_fifo.first;\n response_fifo.deq;\n if (verbose) $display(\"(%0d) Response is: \", $time, fshow(value));\n endrule\n\n interface Get tx;\n method ActionValue#(TLMRequestStd) get;\n let value <- gen.next;\n if (value matches tagged Descriptor .d)\n if (verbose) $display(\"(%0d) Request is: \", $time, fshow(d));\n return value;\n endmethod\n endinterface\n\n interface Put rx = toPut(response_fifo);\n\nendmodule\n\n(* synthesize *)\nmodule mkTLM2Source#(Maybe#(TLMCommand) m_command, Bool verbose) (TLMSendIFC#(TLMRequestStd, TLMResponseStd));\n\n Reg#(Bool) initialized <- mkReg(False);\n FIFO#(TLMResponseStd) response_fifo <- mkFIFO;\n Randomize#(TLMRequestStd) gen <- mkTLMRandomizer(m_command);\n\n rule start (!initialized);\n gen.cntrl.init;\n initialized <= True;\n endrule\n\n rule grab_responses;\n let value = response_fifo.first;\n response_fifo.deq;\n if (verbose) $display(\"(%0d) Response is: \", $time, fshow(value));\n endrule\n\n interface Get tx;\n method ActionValue#(TLMRequestStd) get;\n let value <- gen.next;\n if (value matches tagged Descriptor .d)\n if (verbose) $display(\"(%0d) Request is: \", $time, fshow(d));\n return value;\n endmethod\n endinterface\n\n interface Put rx = toPut(response_fifo);\n\nendmodule\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nfunction TLMBLength#(`TLM_PRM) getTLMCycleCount (RequestDescriptor#(`TLM_PRM) desc);\n if (desc.command == READ)\n return 0;\n else\n return desc.b_length;\nendfunction\n\nfunction Bit#(n) getTLMIncr (RequestDescriptor#(`TLM_PRM) desc)\n provisos(Add#(TLog#(TDiv#(data_size, 8)), 1, n));\n Bit#(n) one = 1;\n if (desc.burst_mode == CNST)\n return 0;\n else\n return one << pack(desc.b_size);\nendfunction\n\nfunction TLMByteEn#(`TLM_PRM) getTLMByteEn (Bool big_endian, RequestDescriptor#(`TLM_PRM) tlm_descriptor);\n let be = getTLMByteEnL(tlm_descriptor);\n return ((big_endian) ? reverseBits(be) : be);\nendfunction\n\nfunction TLMByteEn#(`TLM_PRM) getTLMByteEnU (Bool big_endian, RequestDescriptor#(`TLM_PRM) tlm_descriptor);\n let be = getTLMByteEnUL(tlm_descriptor);\n return ((big_endian) ? reverseBits(be) : be);\nendfunction\n\nfunction TLMByteEn#(`TLM_PRM) getTLMByteEnL (RequestDescriptor#(`TLM_PRM) tlm_descriptor);\n\n if (valueOf(SizeOf#(TLMByteEn#(`TLM_PRM))) == 1)\n return 1;\n else\n begin\n\t Bit#(TLog#(SizeOf#(TLMByteEn#(`TLM_PRM)))) addr = ?;\n\t if (valueOf(TLog#(SizeOf#(TLMByteEn#(`TLM_PRM)))) <= valueOf(addr_size))\n\t addr = truncateNP(tlm_descriptor.addr);\n\t else\n\t addr = extendNP(tlm_descriptor.addr);\n\n\t TLMByteEn#(`TLM_PRM) all_ones = unpack('1);\n\t let shift = 1 << pack(tlm_descriptor.b_size);\n\t let mask = ~(all_ones << shift);\n\t return (mask << addr);\n end\nendfunction\n\nfunction TLMByteEn#(`TLM_PRM) getTLMByteEnUL (RequestDescriptor#(`TLM_PRM) tlm_descriptor);\n\n if (valueOf(SizeOf#(TLMByteEn#(`TLM_PRM))) == 1)\n return 1;\n else\n begin\n\t TLMAddr#(`TLM_PRM) ones = '1;\n\t let size_shft = pack(tlm_descriptor.b_size);\n\t let msk = ones << size_shft;\n\t let offset = ~msk & tlm_descriptor.addr;\n\n\n\t Bit#(TLog#(SizeOf#(TLMByteEn#(`TLM_PRM)))) addr = ?;\n\t if (valueOf(TLog#(SizeOf#(TLMByteEn#(`TLM_PRM)))) <= valueOf(addr_size))\n\t addr = truncateNP(tlm_descriptor.addr);\n\t else\n\t addr = extendNP(tlm_descriptor.addr);\n\n\t \/\/ align the address\n\t addr = addr >> size_shft;\n\t addr = addr << size_shft;\n\t TLMByteEn#(`TLM_PRM) all_ones = unpack('1);\n\t let shift = 1 << size_shft;\n\t let mask = ~(all_ones << shift);\n\t mask = mask >> offset;\n\t mask = mask << offset;\n\t return (mask << addr);\n end\nendfunction\n\n\nfunction RequestDescriptor#(`TLM_PRM) incrTLMAddr(RequestDescriptor#(`TLM_PRM) desc);\n let incr = getTLMIncr(desc);\n let addr = desc.addr + cExtend(incr);\n if (desc.burst_mode == WRAP)\n begin\n\t \/\/ This code assumes a valid wrap burst_length\n\t \/\/ therefore b_length will be of the form: 00000111 (i.e 0,\n\t \/\/ 1, 3, 7 etc)\n\t Vector#(TAdd#(length_size, 1), Bit#(1)) bit_vector = unpack(extendNP(pack(desc.b_length)));\n\t Bit#(4) offset = foldr1(\\+ , map(extend, bit_vector));\n\t Bit#(4) total = offset + extendNP(pack(desc.b_size));\n\t TLMAddr#(`TLM_PRM) mask_bar = '1 << total;\n\t addr = (addr & ~mask_bar) | (desc.addr & mask_bar);\n end\n desc.addr = addr;\n return desc;\nendfunction\n\nfunction Bit#(n) countLSBZeros (Bit#(n) value);\n Vector#(n, Bool) vector_value = unpack(value);\n let pos = findIndex(id, vector_value);\n case (pos) matches\n tagged Valid .p: return zExtend(pack(p));\n tagged Invalid: return fromInteger(valueOf(n));\n endcase\nendfunction\n\n\nfunction TLMData#(`TLM_PRM) getTLMData(TLMRequest#(`TLM_PRM) request);\n case (request) matches\n (tagged Descriptor .d): return d.data;\n (tagged Data .d) : return d.data;\n endcase\nendfunction\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nfunction RequestDescriptor#(`TLM_PRM) incrTLMAddrN(Integer log_n, RequestDescriptor#(`TLM_PRM) desc);\n Bit#(addr_size) incr = cExtend(getTLMIncr(desc));\n let addr = desc.addr + (incr << log_n);\n desc.addr = addr;\n return desc;\n \/\/ return ((desc.burst_mode == INCR || desc.burst_mode == CNST) ? desc : error(\"incrTLMAddrN cannot be applied to WRAP descriptors.\"));\nendfunction\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ninstance FShow#(TLMCommand);\n function Fmt fshow (TLMCommand label);\n case (label)\n READ: return fshow(\"READ \");\n WRITE: return fshow(\"WRITE\");\n UNKNOWN: return fshow(\"UNKNOWN\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMMode);\n function Fmt fshow (TLMMode label);\n case (label)\n REGULAR: return fshow(\"REG\");\n DEBUG: return fshow(\"DBG\");\n CONTROL: return fshow(\"CTL\");\n\t UNKNOWN: return fshow(\"UNK\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMBurstMode);\n function Fmt fshow (TLMBurstMode label);\n case (label)\n INCR: return fshow(\"INCR\");\n CNST: return fshow(\"CNST\");\n WRAP: return fshow(\"WRAP\");\n endcase\n endfunction\nendinstance\n\nfunction Fmt fshowBurstMode (RequestDescriptor#(`TLM_PRM) op);\n case (op.burst_mode)\n INCR: return ($format(\"INCR \") + fshow(op.b_size));\n CNST: return ($format(\"CNST \") + fshow(op.b_size));\n WRAP: return ($format(\"WRAP \") + fshow(op.b_size));\n endcase\nendfunction\n\ninstance FShow#(TLMStatus);\n function Fmt fshow (TLMStatus label);\n case (label)\n SUCCESS: return fshow(\"SUCCESS\");\n ERROR: return fshow(\"ERROR \");\n \t EXOKAY: return fshow(\"EXOKAY \");\n\t UNKNOWN: return fshow(\"UNKNOWN\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMLock);\n function Fmt fshow (TLMLock label);\n case (label)\n NORMAL: return fshow(\"NORMAL \");\n EXCLUSIVE: return fshow(\"EXCLUSIVE\");\n\t LOCKED: return fshow(\"LOCKED \");\n\t RESERVED: return fshow(\"RESERVED \");\n endcase\n endfunction\nendinstance\n\n\ninstance FShow#(TLMPrivilege);\n function Fmt fshow (TLMPrivilege label);\n case (label)\n NORMAL: return fshow(\"NORMAL \");\n PRIVILEGED: return fshow(\"PRIVILEGED\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMSecurity);\n function Fmt fshow (TLMSecurity label);\n case (label)\n SECURE: return fshow(\"SECURE \");\n NON_SECURE: return fshow(\"NON_SECURE\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMAccess);\n function Fmt fshow (TLMAccess label);\n case (label)\n DATA: return fshow(\"DATA\");\n INST: return fshow(\"INST\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMCache);\n function Fmt fshow (TLMCache label);\n case (label)\n NO_CACHE: return fshow(\"NO_CACHE\");\n CACHE: return fshow(\"CACHE\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMModify);\n function Fmt fshow (TLMModify label);\n case (label)\n NO_MODIFY: return fshow(\"NO_MODIFY\");\n MODIFY: return fshow(\"MODIFY\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMBuffer);\n function Fmt fshow (TLMBuffer label);\n case (label)\n NO_BUFFER: return fshow(\"NO_BUFFER\");\n BUFFER: return fshow(\"BUFFER\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMAllocate);\n function Fmt fshow (TLMAllocate label);\n case (label)\n NO_ALLOCATE: return fshow(\"NO_ALLOCATE\");\n ALLOCATE: return fshow(\"ALLOCATE\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMMark);\n function Fmt fshow (TLMMark label);\n case (label)\n LAST: return fshow(\"LAST\");\n NOT_LAST: return fshow(\"NOT_LAST\");\n\t OPEN: return fshow(\"OPEN\");\n endcase\n endfunction\nendinstance\n\ninstance FShow#(RequestData#(`TLM_PRM));\n\n function Fmt fshow (RequestData#(`TLM_PRM) data);\n return ($format(\"\") : fshow(\">\")));\n endfunction\nendinstance\n\ninstance FShow#(RequestDescriptor#(`TLM_PRM));\n\n function Fmt fshow (RequestDescriptor#(`TLM_PRM) op);\n return ($format(\"\", op.data));\n endfunction\nendinstance\n\ninstance FShow#(TLMRequest#(`TLM_PRM))\n provisos(FShow#(RequestData#(`TLM_PRM)),\n FShow#(RequestDescriptor#(`TLM_PRM)));\n\n function Fmt fshow (TLMRequest#(`TLM_PRM) request);\n case (request) matches\n tagged Descriptor .a:\n return fshow(a);\n tagged Data .a:\n return fshow(a);\n endcase\n endfunction\nendinstance\n\ninstance FShow#(TLMResponse#(`TLM_PRM));\n function Fmt fshow (TLMResponse#(`TLM_PRM) response);\n TLMErrorCode code = unpack(truncateNP(response.data));\n let code_or_data = (response.status == ERROR) ? fshow(code) : $format(\" %h\", response.data);\n let f = $format(\"\") : fshow(\">\"));\n return f;\n endfunction\nendinstance\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ninterface TLMSendIFC#(type req, type resp);\n interface Get#(req) tx;\n interface Put#(resp) rx;\nendinterface\n\ninterface TLMRecvIFC#(type req, type resp);\n interface Get#(resp) tx;\n interface Put#(req) rx;\nendinterface\n\ninterface TLMReadWriteSendIFC#(type req, type resp);\n interface TLMSendIFC#(req, resp) read;\n interface TLMSendIFC#(req, resp) write;\nendinterface\n\ninterface TLMReadWriteRecvIFC#(type req, type resp);\n interface TLMRecvIFC#(req, resp) read;\n interface TLMRecvIFC#(req, resp) write;\nendinterface\n\ninterface TLMTransformIFC#(type req, type resp);\n interface TLMRecvIFC#(req, resp) in;\n interface TLMSendIFC#(req, resp) out;\nendinterface\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ninstance Connectable#(TLMSendIFC#(req, resp), TLMRecvIFC#(req, resp));\n module mkConnection#(TLMSendIFC#(req, resp) request, TLMRecvIFC#(req, resp) response) (Empty);\n mkConnection(request.tx, response.rx);\n mkConnection(request.rx, response.tx);\n endmodule\nendinstance\n\ninstance Connectable#(TLMRecvIFC#(req, resp), TLMSendIFC#(req, resp));\n module mkConnection#(TLMRecvIFC#(req, resp) response, TLMSendIFC#(req, resp) request) (Empty);\n mkConnection(request.tx, response.rx);\n mkConnection(request.rx, response.tx);\n endmodule\nendinstance\n\ninstance Connectable#(TLMReadWriteSendIFC#(req, resp), TLMReadWriteRecvIFC#(req, resp));\n module mkConnection#(TLMReadWriteSendIFC#(req, resp) request, TLMReadWriteRecvIFC#(req, resp) response) (Empty);\n let read_con <- mkConnection(request.read, response.read);\n let write_con <- mkConnection(request.write, response.write);\n endmodule\nendinstance\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ntypeclass AddrMatch#(type addr_t, type ifc_t);\n function ifc_t addAddrMatch(function Bool addrMatch(addr_t value), ifc_t value);\nendtypeclass\n\nfunction Bool alwaysAddrMatch(a value);\n return True;\nendfunction\n\nfunction RequestDescriptor#(`TLM_PRM) addByteEnable (Bool big_endian, RequestDescriptor#(`TLM_PRM) request);\n let request_new = request;\n TLMByteEn#(`TLM_PRM) be = getTLMByteEn(big_endian, request);\n request_new.byte_enable = tagged Specify be;\n return request_new;\nendfunction\n\nfunction RequestDescriptor#(`TLM_PRM) addByteEnableU (Bool big_endian, RequestDescriptor#(`TLM_PRM) request);\n let request_new = request;\n TLMByteEn#(`TLM_PRM) be = getTLMByteEnU(big_endian, request);\n request_new.byte_enable = tagged Specify be;\n return request_new;\nendfunction\n\nfunction RequestDescriptor#(`TLM_PRM) alignAddress (RequestDescriptor#(`TLM_PRM) request);\n let addr = request.addr;\n addr = addr >> pack(request.b_size);\n addr = addr << pack(request.b_size);\n let d = request;\n d.addr = addr;\n return d;\nendfunction\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ninstance TLMRequestTC#(BRAMRequest#(Bit#(addr_size), Bit#(data_size)), `TLM_PRM)\n provisos (DefaultValue #(BRAMRequest#(Bit#(addr_size), Bit#(data_size)))\n ,DefaultValue #( RequestDescriptor#(`TLM_PRM) ));\n\n function TLMRequest#(`TLM_PRM) toTLMRequest(BRAMRequest#(Bit#(addr_size), Bit#(data_size)) value);\n RequestDescriptor#(`TLM_PRM) request = defaultValue;\n request.command = value.write ? WRITE : READ;\n request.data = value.datain;\n request.addr = value.address;\n \/\/ responseOnWrite must be true as TLM always generates a response\n return tagged Descriptor request;\n endfunction\n\n function BRAMRequest#(Bit#(addr_size), Bit#(data_size)) fromTLMRequest(TLMRequest#(`TLM_PRM) value);\n BRAMRequest#(Bit#(addr_size), Bit#(data_size)) brequest = defaultValue ;\n case (value) matches\n tagged Descriptor .desc:\n begin\n brequest.write = desc.command == WRITE ;\n brequest.datain = desc.data;\n brequest.address = desc.addr;\n return brequest;\n end\n tagged Data .data:\n begin\n \/\/ XXXX should never occur\n return brequest;\n end\n endcase\n endfunction\nendinstance\n\ninstance TLMResponseTC#(Bit#(data_size), `TLM_PRM)\n provisos (DefaultValue# (TLMResponse#(`TLM_PRM))\n );\n function TLMResponse#(`TLM_PRM) toTLMResponse (Bit#(data_size) value );\n TLMResponse#(`TLM_PRM) response = defaultValue ;\n response.data = value ;\n return response ;\n endfunction\n function Bit#(data_size) fromTLMResponse (TLMResponse#(`TLM_PRM) value);\n return value.data;\n endfunction\nendinstance\n\ninstance TLMRequestTC#(BRAMRequestBE#(Bit#(addr_size), Bit#(data_size), n), `TLM_PRM)\n provisos (DefaultValue #(BRAMRequest#(Bit#(addr_size), Bit#(data_size)))\n ,DefaultValue #( RequestDescriptor#(`TLM_PRM) )\n ,Div#(data_size,8,n)\n ,Div#(data_size,8,TDiv#(data_size,8))\n );\n\n function TLMRequest#(`TLM_PRM) toTLMRequest(BRAMRequestBE#(Bit#(addr_size), Bit#(data_size), n) value);\n RequestDescriptor#(`TLM_PRM) request = defaultValue;\n request.command = value.writeen != 0 ? WRITE : READ;\n request.data = value.datain;\n request.addr = value.address;\n\/\/ request.byte_enable = value.writeen != 0 ? value.writeen : '1 ;\n request.byte_enable = tagged Calculate;\n \/\/ responseOnWrite must be true as TLM always generates a response\n return tagged Descriptor request;\n endfunction\n\n function BRAMRequestBE#(Bit#(addr_size), Bit#(data_size), n) fromTLMRequest(TLMRequest#(`TLM_PRM) value);\n BRAMRequestBE#(Bit#(addr_size), Bit#(data_size),n) brequest = defaultValue ;\n case (value) matches\n tagged Descriptor .desc:\n begin\n\/\/ brequest.writeen = desc.command == WRITE ? desc.byte_enable : 0 ;\n brequest.datain = desc.data;\n brequest.address = desc.addr;\n return brequest;\n end\n tagged Data .data:\n begin\n \/\/ XXXX should never occur\n return brequest;\n end\n endcase\n endfunction\nendinstance\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nfunction Bool isValidRequest(TLMRequest#(`TLM_PRM) request, TLMFamily family);\n return True;\nendfunction\n\nfunction Bool isValidResponse(TLMResponse#(`TLM_PRM) request, TLMFamily family);\n return True;\nendfunction\n\nmodule wrapFIFO#(FIFO#(a) fifo) (FIFO#(a));\n\n PulseWire do_enq <- mkPulseWire;\n PulseWire do_deq <- mkPulseWire;\n\n Reg#(Bit#(8)) count <- mkReg(0);\n Reg#(Bit#(8)) max_count <- mkReg(0);\n\n rule incr (do_enq && !do_deq);\n count <= count + 1;\n max_count <= max(max_count, count + 1);\n if ((count + 1) > max_count)\n\t $display(\"(%0d) %m MAX is: %0d\", $time, count + 1);\n endrule\n\n rule decr (!do_enq && do_deq);\n count <= count - 1;\n endrule\n\n method Action enq (a value);\n do_enq.send;\n fifo.enq(value);\n endmethod\n method Action deq ();\n do_deq.send;\n fifo.deq;\n endmethod\n method first = fifo.first;\n method clear = fifo.clear;\n\nendmodule\n\nmodule wrapFIFOF#(FIFOF#(a) fifo) (FIFOF#(a));\n\n PulseWire do_enq <- mkPulseWire;\n PulseWire do_deq <- mkPulseWire;\n\n Reg#(Bit#(8)) count <- mkReg(0);\n Reg#(Bit#(8)) max_count <- mkReg(0);\n\n rule incr (do_enq && !do_deq);\n count <= count + 1;\n max_count <= max(max_count, count + 1);\n if ((count + 1) > max_count)\n\t $display(\"(%0d) %m MAX is: %0d\", $time, count + 1);\n endrule\n\n rule decr (!do_enq && do_deq);\n count <= count - 1;\n endrule\n\n method Action enq (a value);\n do_enq.send;\n fifo.enq(value);\n endmethod\n method Action deq ();\n do_deq.send;\n fifo.deq;\n endmethod\n method first = fifo.first;\n method clear = fifo.clear;\n method notEmpty = fifo.notEmpty;\n method notFull = fifo.notFull;\n\nendmodule\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ntypedef union tagged {void Calculate;\n TLMByteEn#(`TLM_PRM) Specify;\n } TLMBEKind#(`TLM_PRM_DCL) deriving(Eq, Bits, Bounded);\n\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nfunction TLMBSize getMaxBSize (Integer data_width);\n case (data_width)\n 8: return BITS8;\n 16: return BITS16;\n 32: return BITS32;\n 64: return BITS64;\n 128: return BITS128;\n 256: return BITS256;\n 512: return BITS512;\n 1024: return BITS1024;\n endcase\nendfunction\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nmodule mkSafeDepthParamFIFO#(parameter UInt#(32) depth) (FIFO#(a))\n provisos(Bits#(a, sa));\n (* hide *)\n let _ifc <- mkDepthParamFIFO(max(2,depth));\n return _ifc;\nendmodule\n\nmodule mkSafeDepthParamFIFOF#(parameter UInt#(32) depth) (FIFOF#(a))\n provisos(Bits#(a, sa));\n (* hide *)\n let _ifc <- mkDepthParamFIFOF(max(2,depth));\n return _ifc;\nendmodule\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\ninterface SFIFO#(type a, type b);\n method Action enq (a value);\n method Action deq;\n method a first;\n method Action clear;\nendinterface\n\nmodule mkSizedSFIFO#(Integer n) (SFIFO#(a, b))\n provisos (Bits#(a,sa), Bits#(b, sb), Arith#(b), Eq#(b));\n\n \/\/ If the queue contains n elements, they are in q[0]..q[n-1]. The head of\n \/\/ the queue (the \"first\" element) is in q[0], the tail in q[n-1].\n\n Tuple2#(b, a) dflt = tuple2(0, ?);\n\n Reg#(Tuple2#(b, a)) q[n];\n for (Integer i=0; i 1)\n\t $display (\"%0d: Near_Mem.rl_reset\", cur_cycle);\n endrule\n\n rule rl_reset_complete (rg_state == STATE_RESETTING);\n let _dummy1 <- icache.server_reset.response.get;\n let _dummy2 <- dcache.server_reset.response.get;\n\n f_reset_rsps.enq (?);\n rg_state <= STATE_READY;\n\n if (cfg_verbosity > 1)\n\t $display (\"%0d: Near_Mem.rl_reset_complete\", cur_cycle);\n endrule\n\n \/\/ ----------------------------------------------------------------\n \/\/ INTERFACE\n\n \/\/ Reset\n interface Server server_reset;\n interface Put request;\n\t method Action put (Token t) if (rg_state == STATE_READY);\n\t rg_state <= STATE_RESET;\n\t endmethod\n endinterface\n\n interface Get response;\n\t method ActionValue #(Token) get ();\n\t let rsp <- pop (f_reset_rsps);\n\t return rsp;\n\t endmethod\n endinterface\n endinterface\n\n \/\/ ----------------\n \/\/ IMem\n\n \/\/ CPU side\n interface IMem_IFC imem;\n \/\/ CPU side: IMem request\n method Action req (Bit #(3) f3,\n\t\t\t WordXL addr,\n\t\t\t \/\/ The following args for VM\n\t\t\t Priv_Mode priv,\n\t\t\t Bit #(1) sstatus_SUM,\n\t\t\t Bit #(1) mstatus_MXR,\n\t\t\t WordXL satp, \/\/ { VM_Mode, ASID, PPN_for_page_table }\n\t\t\t WordXL parbase,\n\t\t\t WordXL parmask,\n\t\t\t WordXL mrbm);\n\t Bit #(7) amo_funct7 = ?;\n\t Bit #(64) store_value = ?;\n\t icache.req (CACHE_LD, f3,\n`ifdef ISA_A\n\t\t amo_funct7,\n`endif\n\t\t addr, store_value, priv, sstatus_SUM, mstatus_MXR, satp, parbase, parmask, mrbm);\n endmethod\n\n \/\/ CPU side: IMem response\n method Bool valid = icache.valid;\n method Bool is_i32_not_i16 = True;\n method WordXL pc = icache.addr;\n method Instr instr = truncate (icache.word64);\n method Bool exc = icache.exc;\n method Exc_Code exc_code = icache.exc_code;\n method WordXL tval = icache.addr;\n endinterface\n\n \/\/ Fabric side\n interface imem_master = icache.mem_master;\n\n \/\/ ----------------\n \/\/ DMem\n\n \/\/ CPU side\n interface DMem_IFC dmem;\n \/\/ CPU side: DMem request\n method Action req (CacheOp op,\n\t\t\t Bit #(3) f3,\n`ifdef ISA_A\n\t\t\t Bit #(7) amo_funct7,\n`endif\n\t\t\t WordXL addr,\n\t\t\t Bit #(64) store_value,\n\t\t\t \/\/ The following args for VM\n\t\t\t Priv_Mode priv,\n\t\t\t Bit #(1) sstatus_SUM,\n\t\t\t Bit #(1) mstatus_MXR,\n\t\t\t WordXL satp, \/\/ { VM_Mode, ASID, PPN_for_page_table }\n\t\t\t WordXL parbase,\n\t\t\t WordXL parmask,\n\t\t\t WordXL mrbm);\n\t dcache.req (op, f3,\n`ifdef ISA_A\n\t\t amo_funct7,\n`endif\n\t\t addr, store_value, priv, sstatus_SUM, mstatus_MXR, satp, parbase, parmask, mrbm);\n endmethod\n\n \/\/ CPU side: DMem response\n method Bool valid = dcache.valid;\n method Bit #(64) word64 = dcache.word64;\n`ifdef ISA_A\n method Bit #(64) st_amo_val = dcache.st_amo_val;\n`endif\n method Bool exc = dcache.exc;\n method Exc_Code exc_code = dcache.exc_code;\n endinterface\n\n \/\/ Fabric side\n interface dmem_master = dcache.mem_master;\n\n \/\/ ----------------\n \/\/ FENCE.I: flush both ICache and DCache\n\n interface Server server_fence_i;\n interface Put request;\n\t method Action put (Token t);\n\t icache.server_flush.request.put (?);\n\t dcache.server_flush.request.put (?);\n\t endmethod\n endinterface\n interface Get response;\n\t method ActionValue #(Token) get;\n\t let ti <- icache.server_flush.response.get;\n\t let td <- dcache.server_flush.response.get;\n\t return ?;\n\t endmethod\n endinterface\n endinterface\n\n \/\/ ----------------\n \/\/ FENCE: flush DCache\n\n interface Server server_fence;\n interface Put request;\n\t method Action put (Fence_Ordering t);\n\t dcache.server_flush.request.put (?);\n\t endmethod\n endinterface\n interface Get response;\n\t method ActionValue #(Token) get;\n\t let td <- dcache.server_flush.response.get;\n\t return ?;\n\t endmethod\n endinterface\n endinterface\n\n \/\/ ----------------\n \/\/ SFENCE_VMA: flush TLBs\n\n method Action sfence_vma;\n icache.tlb_flush;\n dcache.tlb_flush;\n endmethod\nendmodule\n\n\/\/ ================================================================\n\nendpackage: Near_Mem_Caches\n","avg_line_length":27.32,"max_line_length":88,"alphanum_fraction":0.5875549048} {"size":438,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"import FIFO::*;\nimport Vector::*;\n\n\/\/ Hierarchy test for virtual class\ntypedef UInt#(14) I;\ntypedef UInt#(14) O;\ntypedef 3 SIZE;\ntypedef 5 OSIZE;\n\n(*synthesize, options =\"-elab\"*)\nmodule sysTest2F ();\n Vector#(OSIZE,Vector#(SIZE,Reg#(I))) rsssss ;\n for (Integer i = 0; i < valueOf(OSIZE) ; i = i + 1) begin\n for (Integer j = 0; j < valueOf(SIZE) ; j = j + 1) begin\n rsssss[i][j] <- mkRegU;\n end\n end\nendmodule\n","avg_line_length":23.0526315789,"max_line_length":62,"alphanum_fraction":0.602739726} {"size":22121,"ext":"bsv","lang":"Bluespec","max_stars_count":1.0,"content":"\n\/\/ Copyright (c) 2017 Massachusetts Institute of Technology\n\/\/ \n\/\/ Permission is hereby granted, free of charge, to any person\n\/\/ obtaining a copy of this software and associated documentation\n\/\/ files (the \"Software\"), to deal in the Software without\n\/\/ restriction, including without limitation the rights to use, copy,\n\/\/ modify, merge, publish, distribute, sublicense, and\/or sell copies\n\/\/ of the Software, and to permit persons to whom the Software is\n\/\/ furnished to do so, subject to the following conditions:\n\/\/ \n\/\/ The above copyright notice and this permission notice shall be\n\/\/ included in all copies or substantial portions of the Software.\n\/\/ \n\/\/ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\/\/ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\/\/ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n\/\/ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n\/\/ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n\/\/ ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n\/\/ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n\/\/ SOFTWARE.\n\n`include \"ProcConfig.bsv\"\nimport ClientServer::*;\nimport DefaultValue::*;\nimport GetPut::*;\nimport Types::*;\nimport ProcTypes::*;\nimport TlbTypes::*;\nimport Performance::*;\nimport FullAssocTlb::*;\nimport ConfigReg::*;\nimport Fifos::*;\nimport Cntrs::*;\nimport SafeCounter::*;\nimport CacheUtils::*;\nimport LatencyTimer::*;\nimport HasSpecBits::*;\nimport Vector::*;\nimport Ehr::*;\n\nexport DTlbReq(..);\nexport DTlbResp(..);\nexport DTlbRqToP(..);\nexport DTlbTransRsFromP(..);\nexport DTlbToParent(..);\nexport DTlb(..);\nexport mkDTlb;\n\ntypedef `L1_TLB_SIZE DTlbSize;\n\n\/\/ req & resp with core\n\/\/ D TLB also keeps the information of the requesting inst, so we don't need\n\/\/ extra bookkeeping outside D TLB.\ntypedef struct {\n instT inst;\n SpecBits specBits;\n} DTlbReq#(type instT) deriving(Bits, Eq, FShow);\n\ntypedef struct {\n TlbResp resp;\n instT inst;\n SpecBits specBits;\n} DTlbResp#(type instT) deriving(Bits, Eq, FShow);\n\n\/\/ req & resp with L2 TLB\ntypedef struct {\n Vpn vpn;\n DTlbReqIdx id;\n} DTlbRqToP deriving(Bits, Eq, FShow);\n\ntypedef struct {\n \/\/ may get page fault: i.e. hit invalid page or\n \/\/ get non-leaf page at last-level page table\n Maybe#(TlbEntry) entry; \n DTlbReqIdx id;\n} DTlbTransRsFromP deriving(Bits, Eq, FShow);\n\ninterface DTlbToParent;\n interface FifoDeq#(DTlbRqToP) rqToP;\n interface FifoEnq#(DTlbTransRsFromP) ldTransRsFromP;\n \/\/ after DTLB flush itself, it notifies L2, and wait L2 to flush\n interface Client#(void, void) flush;\nendinterface\n\ninterface DTlb#(type instT);\n \/\/ system consistency related\n method Bool flush_done;\n method Action flush;\n method Action updateVMInfo(VMInfo vm);\n method Bool noPendingReq;\n\n \/\/ req\/resp with core\n method Action procReq(DTlbReq#(instT) req);\n method DTlbResp#(instT) procResp;\n method Action deqProcResp;\n\n \/\/ req\/resp with L2 TLB\n interface DTlbToParent toParent;\n\n \/\/ speculation\n interface SpeculationUpdate specUpdate;\n\n \/\/ performance\n interface Perf#(L1TlbPerfType) perf;\nendinterface\n\ntypedef FullAssocTlb#(DTlbSize) DTlbArray;\nmodule mkDTlbArray(DTlbArray);\n let m <- mkFullAssocTlb(True); \/\/ randomness in replacement\n return m;\nendmodule\n\n\/\/ a pending tlb req may be in following states\ntypedef union tagged {\n void None;\n void WaitParent;\n DTlbReqIdx WaitPeer;\n} DTlbWait deriving(Bits, Eq, FShow);\n\nmodule mkDTlb#(\n function TlbReq getTlbReq(instT inst)\n)(DTlb::DTlb#(instT)) provisos(Bits#(instT, a__));\n Bool verbose = False;\n\n \/\/ TLB array\n DTlbArray tlb <- mkDTlbArray;\n\n \/\/ processor init flushing by setting this flag\n Reg#(Bool) needFlush <- mkReg(False);\n \/\/ after flushing ITLB itself, we want parent TLB to flush\n Reg#(Bool) waitFlushP <- mkReg(False);\n\n \/\/ current processor VM information\n Reg#(VMInfo) vm_info <- mkReg(defaultValue);\n\n \/\/ pending reqs\n \/\/ pendWait should be meaningful even when entry is invalid. pendWait =\n \/\/ WaitParent True means this entry is waiting for parent TLB resp;\n \/\/ pendWait = WaitPeer means this entry is waiting for a resp initiated by\n \/\/ another req. Thus, pendWait must be None when entry is invalid.\n Vector#(DTlbReqNum, Ehr#(2, Bool)) pendValid <- replicateM(mkEhr(False));\n Vector#(DTlbReqNum, Reg#(DTlbWait)) pendWait <- replicateM(mkReg(None));\n Vector#(DTlbReqNum, Reg#(Bool)) pendPoisoned <- replicateM(mkRegU);\n Vector#(DTlbReqNum, Reg#(instT)) pendInst <- replicateM(mkRegU);\n Vector#(DTlbReqNum, Reg#(TlbResp)) pendResp <- replicateM(mkRegU);\n Vector#(DTlbReqNum, Ehr#(2, SpecBits)) pendSpecBits <- replicateM(mkEhr(?));\n\n \/\/ ordering of methods\/rules that access pend reqs\n \/\/ procReq mutually exclusive with doPRs (no procReq when pRs ready)\n \/\/ procResp < {doPRs, procReq}\n \/\/ wrongSpec C {procReq, doPRs, procResp}\n \/\/ correctSpec C wrongSpec\n \/\/ correctSpec CF doPRs\n \/\/ {procReq, procResp} < correctSpec (correctSpec is always at end)\n\n RWire#(void) wrongSpec_procResp_conflict <- mkRWire;\n RWire#(void) wrongSpec_doPRs_conflict <- mkRWire;\n RWire#(void) wrongSpec_procReq_conflict <- mkRWire;\n\n let pendValid_noMiss = getVEhrPort(pendValid, 0);\n let pendValid_wrongSpec = getVEhrPort(pendValid, 0);\n let pendValid_procResp = getVEhrPort(pendValid, 0); \/\/ write\n let pendValid_doPRs = getVEhrPort(pendValid, 1); \/\/ assert\n let pendValid_procReq = getVEhrPort(pendValid, 1); \/\/ write\n\n let pendSpecBits_wrongSpec = getVEhrPort(pendSpecBits, 0);\n let pendSpecBits_procResp = getVEhrPort(pendSpecBits, 0);\n let pendSpecBits_procReq = getVEhrPort(pendSpecBits, 0); \/\/ write\n let pendSpecBits_correctSpec = getVEhrPort(pendSpecBits, 1);\n\n \/\/ free list of pend entries, to cut off path from procResp to procReq\n Fifo#(DTlbReqNum, DTlbReqIdx) freeQ <- mkCFFifo;\n Reg#(Bool) freeQInited <- mkReg(False);\n Reg#(DTlbReqIdx) freeQInitIdx <- mkReg(0);\n\n \/\/ req & resp with parent TLB\n Fifo#(DTlbReqNum, DTlbRqToP) rqToPQ <- mkCFFifo; \/\/ large enough so won't block on enq\n Fifo#(2, DTlbTransRsFromP) ldTransRsFromPQ <- mkCFFifo;\n \/\/ When a resp comes, we first process for the initiating req, then process\n \/\/ other reqs that in WaitPeer.\n Reg#(Maybe#(DTlbReqIdx)) respForOtherReq <- mkReg(Invalid);\n \/\/ flush req\/resp with parent TLB\n Fifo#(1, void) flushRqToPQ <- mkCFFifo;\n Fifo#(1, void) flushRsFromPQ <- mkCFFifo;\n\n \/\/ perf counters\n Fifo#(1, L1TlbPerfType) perfReqQ <- mkCFFifo;\n`ifdef PERF_COUNT\n Fifo#(1, PerfResp#(L1TlbPerfType)) perfRespQ <- mkCFFifo;\n Reg#(Bool) doStats <- mkConfigReg(False);\n Count#(Data) accessCnt <- mkCount(0);\n Count#(Data) missParentCnt <- mkCount(0);\n Count#(Data) missParentLat <- mkCount(0);\n Count#(Data) missPeerCnt <- mkCount(0);\n Count#(Data) missPeerLat <- mkCount(0);\n Count#(Data) hitUnderMissCnt <- mkCount(0);\n Count#(Data) allMissCycles <- mkCount(0);\n\n LatencyTimer#(DTlbReqNum, 12) latTimer <- mkLatencyTimer; \/\/ max latency: 4K cycles\n\n rule doPerf;\n let t <- toGet(perfReqQ).get;\n Data d = (case(t)\n L1TlbAccessCnt: (accessCnt);\n L1TlbMissParentCnt: (missParentCnt);\n L1TlbMissParentLat: (missParentLat);\n L1TlbMissPeerCnt: (missPeerCnt);\n L1TlbMissPeerLat: (missPeerLat);\n L1TlbHitUnderMissCnt: (hitUnderMissCnt);\n L1TlbAllMissCycles: (allMissCycles);\n default: (0);\n endcase);\n perfRespQ.enq(PerfResp {\n pType: t,\n data: d\n });\n endrule\n\n rule incrAllMissCycles(doStats);\n function Bool isMiss(DTlbWait x) = x != None;\n when(all(isMiss, readVReg(pendWait)), allMissCycles.incr(1));\n endrule\n`endif\n\n \/\/ do flush: start when all misses resolve\n Bool noMiss = all(\\== (False) , readVReg(pendValid_noMiss));\n\n rule doStartFlush(needFlush && !waitFlushP && noMiss);\n tlb.flush;\n \/\/ request parent TLB to flush\n flushRqToPQ.enq(?);\n waitFlushP <= True;\n if(verbose) $display(\"[DTLB] flush begin\");\n endrule\n\n rule doFinishFlush(needFlush && waitFlushP);\n flushRsFromPQ.deq;\n needFlush <= False;\n waitFlushP <= False;\n if(verbose) $display(\"[DTLB] flush done\");\n endrule\n\n \/\/ get resp from parent TLB\n \/\/ At high level, this rule is always exclusive with doStartFlush, though\n \/\/ we don't bother to make compiler understand this...\n rule doPRs(ldTransRsFromPQ.notEmpty);\n let pRs = ldTransRsFromPQ.first;\n \/\/ the current req being served is either the initiating req or other\n \/\/ req pending on the same resp\n let idx = fromMaybe(pRs.id, respForOtherReq);\n TlbReq r = getTlbReq(pendInst[idx]);\n\n if(pendPoisoned[idx]) begin\n \/\/ poisoned inst, do nothing\n if(verbose) $display(\"[DTLB] refill poisoned: idx %d; \", idx, fshow(r));\n end\n else if(pRs.entry matches tagged Valid .en) begin\n \/\/ check permission\n if(hasVMPermission(vm_info,\n en.pteType,\n en.ppn,\n en.level,\n r.write ? DataStore : DataLoad)) begin\n \/\/ fill TLB, and record resp\n tlb.addEntry(en);\n let trans_addr = translate(r.addr, en.ppn, en.level);\n pendResp[idx] <= tuple2(trans_addr, Invalid);\n if(verbose) begin\n $display(\"[DTLB] refill: idx %d; \", idx, fshow(r),\n \"; \", fshow(trans_addr));\n end\n end\n else begin\n \/\/ page fault\n Exception fault = r.write ? StorePageFault : LoadPageFault;\n pendResp[idx] <= tuple2(?, Valid (fault));\n if(verbose) begin\n $display(\"[DTLB] refill no permission: idx %d; \", idx, fshow(r));\n end\n end\n end\n else begin\n \/\/ page fault\n Exception fault = r.write ? StorePageFault : LoadPageFault;\n pendResp[idx] <= tuple2(?, Valid (fault));\n if(verbose) $display(\"[DTLB] refill page fault: idx %d; \", idx, fshow(r));\n end\n\n \/\/ get parent resp, miss resolved, reset wait bit\n pendWait[idx] <= None;\n\n doAssert(pendValid_doPRs[idx], \"entry must be valid\");\n if(isValid(respForOtherReq)) begin\n doAssert(pendWait[idx] == WaitPeer (pRs.id), \"entry must be waiting for resp\");\n end\n else begin\n doAssert(pendWait[idx] == WaitParent, \"entry must be waiting for resp\");\n end\n\n \/\/ find another req waiting for this resp\n function Bool waitForResp(DTlbReqIdx i);\n \/\/ we can ignore pendValid here, because not-None pendWait implies\n \/\/ pendValid is true\n return pendWait[i] == WaitPeer (pRs.id) && i != idx;\n endfunction\n Vector#(DTlbReqNum, DTlbReqIdx) idxVec = genWith(fromInteger);\n if(find(waitForResp, idxVec) matches tagged Valid .i) begin\n \/\/ still have req waiting for this resp, keep processing\n respForOtherReq <= Valid (i);\n doAssert(pendValid_doPRs[i], \"waiting entry must be valid\");\n end\n else begin\n \/\/ all req done, deq the pRs\n respForOtherReq <= Invalid;\n ldTransRsFromPQ.deq;\n end\n\n`ifdef PERF_COUNT\n \/\/ perf: miss\n let lat <- latTimer.done(idx);\n if(doStats) begin\n if(isValid(respForOtherReq)) begin\n missPeerLat.incr(zeroExtend(lat));\n missPeerCnt.incr(1);\n end\n else begin\n missParentLat.incr(zeroExtend(lat));\n missParentCnt.incr(1);\n end\n end\n`endif\n\n \/\/ conflict with wrong spec\n wrongSpec_doPRs_conflict.wset(?);\n endrule\n\n \/\/ init freeQ\n rule doInitFreeQ(!freeQInited);\n freeQ.enq(freeQInitIdx);\n freeQInitIdx <= freeQInitIdx + 1;\n if(freeQInitIdx == fromInteger(valueof(DTlbReqNum) - 1)) begin\n freeQInited <= True;\n end\n endrule\n\n \/\/ idx of entries that are ready to resp to proc\n function Maybe#(DTlbReqIdx) validProcRespIdx;\n function Bool validResp(DTlbReqIdx i);\n return pendValid_procResp[i] && pendWait[i] == None && !pendPoisoned[i];\n endfunction\n Vector#(DTlbReqNum, DTlbReqIdx) idxVec = genWith(fromInteger);\n return find(validResp, idxVec);\n endfunction\n\n function Maybe#(DTlbReqIdx) poisonedProcRespIdx;\n function Bool poisonedResp(DTlbReqIdx i);\n return pendValid_procResp[i] && pendWait[i] == None && pendPoisoned[i];\n endfunction\n Vector#(DTlbReqNum, DTlbReqIdx) idxVec = genWith(fromInteger);\n return find(poisonedResp, idxVec);\n endfunction\n\n \/\/ drop poisoned resp\n rule doPoisonedProcResp(poisonedProcRespIdx matches tagged Valid .idx &&& freeQInited);\n pendValid_procResp[idx] <= False;\n freeQ.enq(idx);\n \/\/ conflict with wrong spec\n wrongSpec_procResp_conflict.wset(?);\n endrule\n\n method Action flush if(!needFlush);\n needFlush <= True;\n waitFlushP <= False;\n \/\/ this won't interrupt current processing, since\n \/\/ (1) miss process will continue even if needFlush=True\n \/\/ (2) flush truly starts when there is no pending req\n endmethod\n\n method Bool flush_done = !needFlush;\n\n method Action updateVMInfo(VMInfo vm);\n vm_info <= vm;\n endmethod\n\n \/\/ Since this method is called at commit stage to determine no in-flight\n \/\/ TLB req, even poisoned req should be considered as pending, because it\n \/\/ may be in L2 TLB.\n method Bool noPendingReq = noMiss;\n\n \/\/ We do not accept new req when flushing flag is set. We also do not\n \/\/ accept new req when parent resp is ready. This avoids bypass in TLB. We\n \/\/ also check rqToPQ not full. This simplifies the guard, i.e., it does not\n \/\/ depend on whether we hit in TLB or not.\n method Action procReq(DTlbReq#(instT) req) if(\n !needFlush && !ldTransRsFromPQ.notEmpty && rqToPQ.notFull && freeQInited\n );\n \/\/ allocate MSHR entry\n freeQ.deq;\n DTlbReqIdx idx = freeQ.first;\n doAssert(!pendValid_procReq[idx], \"free entry cannot be valid\");\n doAssert(pendWait[idx] == None, \"entry cannot wait for parent resp\");\n\n pendValid_procReq[idx] <= True;\n pendPoisoned[idx] <= False;\n pendInst[idx] <= req.inst;\n pendSpecBits_procReq[idx] <= req.specBits;\n \/\/ pendWait and pendResp are set later in this method\n\n \/\/ try to translate\n TlbReq r = getTlbReq(req.inst);\n\n`ifdef SECURITY\n \/\/ Security check\n \/\/ Forbid any data load shared outside of the protection domain\n \/\/ if shared load are not allowed\n \/\/ No need to special case M mode with special vm_info value because we\n \/\/ assume that we allow shared load all the time when in M mode.\n \/\/ (Because we are always non speculative in M mode)\n if (!vm_info.sanctum_authShared && outOfProtectionDomain(vm_info, r.addr))begin\n pendWait[idx] <= None;\n pendResp[idx] <= tuple2(?, Valid (LoadAccessFault));\n end\n`else\n \/\/ No security check\n if (False) begin\n noAction;\n end\n`endif\n else if (vm_info.sv39) begin\n let vpn = getVpn(r.addr);\n let trans_result = tlb.translate(vpn, vm_info.asid);\n if (trans_result.hit) begin\n \/\/ TLB hit\n let entry = trans_result.entry;\n \/\/ check permission\n if (hasVMPermission(vm_info,\n entry.pteType,\n entry.ppn,\n entry.level,\n r.write ? DataStore : DataLoad)) begin\n \/\/ update TLB replacement info\n tlb.updateRepByHit(trans_result.index);\n \/\/ translate addr\n Addr trans_addr = translate(r.addr, entry.ppn, entry.level);\n pendWait[idx] <= None;\n pendResp[idx] <= tuple2(trans_addr, Invalid);\n if(verbose) begin\n $display(\"[DTLB] req (hit): idx %d; \", idx, fshow(r),\n \"; \", fshow(trans_result));\n end\n`ifdef PERF_COUNT\n \/\/ perf: hit under miss\n if(doStats && readVReg(pendWait) != replicate(None)) begin\n hitUnderMissCnt.incr(1);\n end\n`endif\n end\n else begin\n \/\/ page fault\n Exception fault = r.write ? StorePageFault : LoadPageFault;\n pendWait[idx] <= None;\n pendResp[idx] <= tuple2(?, Valid (fault));\n if(verbose) $display(\"[DTLB] req no permission: idx %d; \", idx, fshow(r));\n end\n end\n else begin\n \/\/ TLB miss, req to parent TLB only if there is no existing req\n \/\/ for the same VPN already waiting for parent TLB resp\n function Bool reqSamePage(DTlbReqIdx i);\n \/\/ we can ignore pendValid here, because not-None pendWait implies\n \/\/ pendValid is true\n let r_i = getTlbReq(pendInst[i]);\n return pendWait[i] == WaitParent && getVpn(r.addr) == getVpn(r_i.addr);\n endfunction\n Vector#(DTlbReqNum, DTlbReqIdx) idxVec = genWith(fromInteger);\n if(find(reqSamePage, idxVec) matches tagged Valid .i) begin\n \/\/ peer entry has already requested, so don't send duplicate req\n pendWait[idx] <= WaitPeer (i);\n doAssert(pendValid_procReq[i], \"peer entry must be valid\");\n if(verbose) begin\n $display(\"[DTLB] req miss, pend on peer: idx %d, \",\n idx, \"; \", fshow(r), \"; \", fshow(i));\n end\n end\n else begin\n \/\/ this is the first req for this VPN\n pendWait[idx] <= WaitParent;\n rqToPQ.enq(DTlbRqToP {\n vpn: vpn,\n id: idx\n });\n if(verbose) begin\n $display(\"[DTLB] req miss, send to parent: idx %d, \",\n idx, fshow(r));\n end\n end\n`ifdef PERF_COUNT\n \/\/ perf: miss\n latTimer.start(idx);\n`endif\n end\n end\n else begin\n \/\/ bare mode\n pendWait[idx] <= None;\n pendResp[idx] <= tuple2(r.addr, Invalid);\n if(verbose) $display(\"DTLB %m req (bare): \", fshow(r));\n end\n\n`ifdef PERF_COUNT\n \/\/ perf: access\n if(doStats) begin\n accessCnt.incr(1);\n end\n`endif\n \/\/ conflict with wrong spec\n wrongSpec_procReq_conflict.wset(?);\n endmethod\n\n method Action deqProcResp if(\n validProcRespIdx matches tagged Valid .idx &&& freeQInited\n );\n pendValid_procResp[idx] <= False;\n freeQ.enq(idx);\n \/\/ conflict with wrong spec\n wrongSpec_procResp_conflict.wset(?);\n endmethod\n\n method DTlbResp#(instT) procResp if(\n validProcRespIdx matches tagged Valid .idx &&& freeQInited\n );\n return DTlbResp {\n inst: pendInst[idx],\n resp: pendResp[idx],\n specBits: pendSpecBits_procResp[idx]\n };\n endmethod\n\n interface DTlbToParent toParent;\n interface rqToP = toFifoDeq(rqToPQ);\n interface ldTransRsFromP = toFifoEnq(ldTransRsFromPQ);\n interface Client flush;\n interface request = toGet(flushRqToPQ);\n interface response = toPut(flushRsFromPQ);\n endinterface\n endinterface\n\n interface SpeculationUpdate specUpdate;\n method Action incorrectSpeculation(Bool kill_all, SpecTag x);\n \/\/ poison entries\n for(Integer i = 0 ; i < valueOf(DTlbReqNum) ; i = i+1) begin\n if(kill_all || pendSpecBits_wrongSpec[i][x] == 1'b1) begin\n pendPoisoned[i] <= True;\n end\n end\n \/\/ make conflicts with procReq, doPRs, procResp\n wrongSpec_procReq_conflict.wset(?);\n wrongSpec_doPRs_conflict.wset(?);\n wrongSpec_procResp_conflict.wset(?);\n endmethod\n method Action correctSpeculation(SpecBits mask);\n \/\/ clear spec bits for all entries\n for(Integer i = 0 ; i < valueOf(DTlbReqNum) ; i = i+1) begin\n let new_spec_bits = pendSpecBits_correctSpec[i] & mask;\n pendSpecBits_correctSpec[i] <= new_spec_bits;\n end\n endmethod\n endinterface\n\n interface Perf perf;\n method Action setStatus(Bool stats);\n`ifdef PERF_COUNT\n doStats <= stats;\n`else\n noAction;\n`endif\n endmethod\n\n method Action req(L1TlbPerfType r);\n perfReqQ.enq(r);\n endmethod\n\n method ActionValue#(PerfResp#(L1TlbPerfType)) resp;\n`ifdef PERF_COUNT\n perfRespQ.deq;\n return perfRespQ.first;\n`else\n perfReqQ.deq;\n return PerfResp {\n pType: perfReqQ.first,\n data: 0\n };\n`endif\n endmethod\n\n method Bool respValid;\n`ifdef PERF_COUNT\n return perfRespQ.notEmpty;\n`else\n return perfReqQ.notEmpty;\n`endif\n endmethod\n endinterface\nendmodule\n","avg_line_length":36.4431630972,"max_line_length":94,"alphanum_fraction":0.6013742598} {"size":651,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"(* synthesize *)\nmodule sysLog2Test();\n\n rule test;\n Bool pass = True;\n Integer power = 1;\n for(Integer i = 0; primSeq(pass, primSeq(power,i <= 65536)); i = i + 1)\n begin\n if(log2(power) != i) begin\n pass = False; \n $display(\"Fail %0d\", i);\n end\n if(i > 2 && log2(power - 1) != i) begin\n pass = False;\n $display(\"Fail -1 %0d\", i);\n end\n if(log2(power + 1) != i + 1) begin\n pass = False;\n $display(\"Fail +1 %0d\", i);\n end\n messageM(integerToString(i));\n power = power * 2;\n end\n if (pass) $display(\"Test passed\");\n $finish(0);\n endrule\n\nendmodule\n","avg_line_length":22.4482758621,"max_line_length":75,"alphanum_fraction":0.5053763441} {"size":1738,"ext":"bsv","lang":"Bluespec","max_stars_count":134.0,"content":"\/\/ Copyright (c) 2013 Nokia, Inc.\n\/\/ Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n\/\/ Permission is hereby granted, free of charge, to any person\n\/\/ obtaining a copy of this software and associated documentation\n\/\/ files (the \"Software\"), to deal in the Software without\n\/\/ restriction, including without limitation the rights to use, copy,\n\/\/ modify, merge, publish, distribute, sublicense, and\/or sell copies\n\/\/ of the Software, and to permit persons to whom the Software is\n\/\/ furnished to do so, subject to the following conditions:\n\n\/\/ The above copyright notice and this permission notice shall be\n\/\/ included in all copies or substantial portions of the Software.\n\n\/\/ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\/\/ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\/\/ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n\/\/ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n\/\/ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n\/\/ ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n\/\/ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n\/\/ SOFTWARE.\nimport Adapter::*;\n\ninterface TestIndication;\n method Action done();\nendinterface\n\ninterface TestRequest;\n method Action start();\nendinterface\n\ninterface Test;\n interface TestRequest request;\nendinterface\n\nmodule mkTest#(TestIndication indication)(Test);\n let dummy <- mkAdapterTb(interface AdapterIndication;\n method Action done = indication.done;\n endinterface);\n interface TestRequest request;\n method Action start();\n dummy.start();\n endmethod\n endinterface\nendmodule\n","avg_line_length":36.9787234043,"max_line_length":70,"alphanum_fraction":0.7272727273} {"size":1263,"ext":"bsv","lang":"Bluespec","max_stars_count":185.0,"content":"package ModuleCollect;\n\/*\nexport ModuleCollect;\nexport addToCollection;\nexport mapCollection;\nexport getCollection;\nexport IWithCollection(..);\nexport exposeCollection;\n*\/\nimport ModuleContext::*;\nimport UnitAppendList::*;\nimport HList::*;\n\ntypedef ModuleContext#(HList1#(UAList#(a))) ModuleCollect#(type a);\n\nmodule [mc] addToCollection#(a r)(Empty)\n provisos (IsModule#(mc, _1), Context#(mc, UAList#(a)));\n UAList#(a) s <- getContext();\n putContext(tagged Append tuple2(s, tagged One r));\nendmodule\n\nmodule [mc] mapCollection#(function a f(a x), mc#(i) m)(i)\n provisos (IsModule#(mc, _1), Context#(mc, UAList#(a)));\n let i <- m;\n UAList#(a) c <- getContext();\n putContext(uaMap(f, c));\n return i;\nendmodule\n\n\nmodule [Module] getCollection#(ModuleCollect#(a, i) x1)(Tuple2#(i, List#(a)));\n let {c,i} <- runWithCompleteContext(hList1(NoItems), x1);\n return (tuple2(i, flatten(hHead(c))));\nendmodule\n\ninterface IWithCollection #(type a, type i);\n method i device();\n method List#(a) collection();\nendinterface: IWithCollection\n\nmodule [Module] exposeCollection#(ModuleCollect#(a, i) _m)(IWithCollection#(a, i));\n let {_d,_xs} <- getCollection(_m);\n method device = _d;\n method collection = _xs;\nendmodule: exposeCollection\n\nendpackage\n","avg_line_length":26.3125,"max_line_length":83,"alphanum_fraction":0.6991290578} {"size":373,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"interface I;\n \/\/ value method\n method Bool vm();\n \/\/ action method\n method Action am();\n \/\/ actionvalue method\n method ActionValue#(Bool) avm();\nendinterface\n\nimport \"BVI\" VMod =\nmodule mkI (I);\n default_clock clk();\n default_reset rst();\n \/\/ missing enable\n method M avm();\n \/\/ for completeness\n method A vm();\n method am() enable(B);\nendmodule\n\n","avg_line_length":17.7619047619,"max_line_length":35,"alphanum_fraction":0.6380697051} {"size":489,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"(* synthesize *)\nmodule sysLiteralEqOrd();\n Real w = 1.2;\n Real x = 1.1;\n Real y = 1.2;\n Real z = 1.3;\n Real v = 1;\n\n function m(s) = $display(message(s,s));\n\n rule r;\n if (w == y)\n\tm(\"w == y\");\n if (w != y)\n\tm(\"ERROR: w != y\");\n\n if (w < x)\n\tm(\"ERROR: w < x\");\n if (w > x)\n\tm(\"w > x\");\n\n if (w <= z)\n\tm(\"w <= z\");\n if (w >= z)\n\tm(\"ERROR: w >= z\");\n\n if (w < v)\n\tm(\"ERROR: w < v\");\n if (w > v)\n\tm(\"w > v\");\n endrule\nendmodule","avg_line_length":15.28125,"max_line_length":43,"alphanum_fraction":0.3844580777} {"size":926,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/Integrated IDCT Module\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\npackage MkIDCT_top;\n\nimport MkIDCT_1D :: *;\nimport MkIDCT_col :: *;\nimport MkIDCT_row :: *;\nimport TBuffer :: *;\n\n\n(*synthesize,\n CLK = \"clk\",\n RST_N = \"reset\"\n*)\n\nmodule mkIDCT_top (IDCT_1D_IFC#(12,9));\n \n IDCT_1D_IFC#(12,16) row();\n mkIDCT_row the_row(row);\n IDCT_1D_IFC#(16, 9) col();\n mkIDCT_col the_col(col);\n TBuffer_IFC#(16) tbuffer();\n mkTBuffer the_buffer(tbuffer);\n \n rule always_fire (True);\n tbuffer.start (row.result);\n col.start (tpl_1(tbuffer.result), tpl_2(tbuffer.result));\n endrule\n \n method start (a, b);\n action\n row.start (a,b);\n endaction\n endmethod : start\n \n method result ();\n return (col.result); \n endmethod : result\n\nendmodule : mkIDCT_top\n\n\nendpackage : MkIDCT_top\n","avg_line_length":20.5777777778,"max_line_length":76,"alphanum_fraction":0.5377969762} {"size":1318,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"\/*\nCopyright (c) 2017\n\tHyoukjun Kwon (hyoukjun@gatech.edu)\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n*\/\n\n\n\ntypedef 16 FixedPointSz;\ntypedef Bit#(FixedPointSz) FixedPoint;\n\ninterface FixedALU;\n method Action putArgA(FixedPoint newArg);\n method Action putArgB(FixedPoint newArg);\n method ActionValue#(FixedPoint) getRes;\nendinterface\n\n","avg_line_length":37.6571428571,"max_line_length":78,"alphanum_fraction":0.7996965099} {"size":39812,"ext":"bsv","lang":"Bluespec","max_stars_count":1.0,"content":"\/\/ Copyright (c) 2013-2020 Bluespec, Inc. All Rights Reserved\n\n\/\/ ================================================================\n\/\/ ISA defs for UC Berkeley RISC V\n\/\/\n\/\/ References (from riscv.org):\n\/\/ The RISC-V Instruction Set Manual\n\/\/ Volume I: Unprivileged ISA\n\/\/ Document Version 20181106-Base-Ratification\n\/\/ November 6, 2018\n\/\/\n\/\/ The RISC-V Instruction Set Manual\n\/\/ Volume II: Privileged Architecture\n\/\/ Document Version 20181203-Base-Ratification\n\/\/ December 3, 2018\n\/\/\n\/\/ ================================================================\n\npackage ISA_Decls;\n\n\/\/ ================================================================\n\/\/ BSV library imports\n\nimport DefaultValue :: *;\nimport Vector :: *;\nimport BuildVector :: *;\n\n\/\/ ================================================================\n\/\/ BSV project imports\n\n\/\/ None\n\n\/\/ ================================================================\n\ntypedef 3 NO_OF_PRIVMODES;\n\n\/\/ RV32ACIMU\n`define RV32\n`define ISA_PRIV_M\n`define ISA_PRIV_U\n`define ISA_I\n`define ISA_M\n`define ISA_A\n`define ISA_C\n`define SHIFT_BARREL\n`define MULT_SYNTH\n`define Near_Mem_Caches\n`define FABRIC64\n\n\/\/ ================================================================\n\/\/ XLEN and related constants\n\n`ifdef RV32\n\ntypedef 32 XLEN;\n\n`elsif RV64\n\ntypedef 64 XLEN;\n\n`endif\n\ntypedef TMul #(2, XLEN) XLEN_2; \/\/ Double-width for multiplications\ntypedef TSub #(XLEN, 2) XLEN_MINUS_2;\/\/ XLEN-2 for MTVEC base width\n\nInteger xlen = valueOf (XLEN);\n\ntypedef enum { RV32, RV64 } RV_Version deriving (Eq, Bits);\n\nRV_Version rv_version = ( (valueOf (XLEN) == 32) ? RV32 : RV64 );\n\n\/\/ ----------------\n\/\/ We're evolving the code to use WordXL\/IntXL instead of Word\/Word_S\n\/\/ because of the widespread and inconsistent use of 'word' in the field.\n\/\/ All existing uses of 'Word\/Word_S' should migrate towards WordXL\/IntXL.\n\/\/ All new code should only use WordXL\/IntXL\n\/\/ Eventually, we should remove Word and Word_S\n\ntypedef Bit #(XLEN) WordXL; \/\/ Raw (unsigned) register data\ntypedef Int #(XLEN) IntXL; \/\/ Signed register data\n\ntypedef Bit #(XLEN) Word; \/\/ Raw (unsigned) register data \/\/ OLD: migrate to WordXL\ntypedef Int #(XLEN) Word_S; \/\/ Signed register data \/\/ OLD: migrate to IntXL\n\ntypedef WordXL Addr; \/\/ addresses\/pointers\n\n\/\/ ----------------\n\ntypedef 8 Bits_per_Byte;\ntypedef Bit #(Bits_per_Byte) Byte;\n\ntypedef XLEN Bits_per_Word; \/\/ REDUNDANT to XLEN\n\ntypedef TDiv #(Bits_per_Word, Bits_per_Byte) Bytes_per_Word; \/\/ OLD ('WordXL')\ntypedef TLog #(Bytes_per_Word) Bits_per_Byte_in_Word; \/\/ OLD ('WordXL')\ntypedef Bit #(Bits_per_Byte_in_Word) Byte_in_Word; \/\/ OLD ('WordXL')\ntypedef Vector #(Bytes_per_Word, Byte) Word_B; \/\/ OLD ('WordXL')\n\ntypedef TDiv #(XLEN, Bits_per_Byte) Bytes_per_WordXL;\ntypedef TLog #(Bytes_per_WordXL) Bits_per_Byte_in_WordXL;\ntypedef Bit #(Bits_per_Byte_in_WordXL) Byte_in_WordXL;\ntypedef Vector #(Bytes_per_WordXL, Byte) WordXL_B;\n\ntypedef XLEN Bits_per_Addr;\ntypedef TDiv #(Bits_per_Addr, Bits_per_Byte) Bytes_per_Addr;\n\nInteger bits_per_byte = valueOf (Bits_per_Byte);\n\nInteger bytes_per_wordxl = valueOf (Bytes_per_WordXL);\nInteger bits_per_byte_in_wordxl = valueOf (Bits_per_Byte_in_WordXL);\n\nInteger addr_lo_byte_in_wordxl = 0;\nInteger addr_hi_byte_in_wordxl = addr_lo_byte_in_wordxl + bits_per_byte_in_wordxl - 1;\n\nfunction Byte_in_Word fn_addr_to_byte_in_wordxl (Addr a);\n return a [addr_hi_byte_in_wordxl : addr_lo_byte_in_wordxl ];\nendfunction\n\n\/\/ ================================================================\n\/\/ FLEN and related constants, for floating point data\n\/\/ Can have one or two fpu sizes (should they be merged sooner than later ?).\n\n\/\/ ISA_D => ISA_F (ISA_D implies ISA_F)\n\/\/ The combination ISA_D and !ISA_F is not permitted\n\n\/\/ ISA_F - 32 bit FPU\n\/\/ ISA_D - 64 bit FPU\n\n`ifdef ISA_F\n\n`ifdef ISA_D\ntypedef 64 FLEN;\nBool hasFpu32 = False;\nBool hasFpu64 = True;\n`else\ntypedef 32 FLEN;\nBool hasFpu32 = True;\nBool hasFpu64 = False;\n`endif\n\ntypedef Bit #(FLEN) FP_Value;\ntypedef Bit #(FLEN) WordFL; \/\/ Floating point data\n\ntypedef TDiv #(FLEN, Bits_per_Byte) Bytes_per_WordFL;\ntypedef TLog #(Bytes_per_WordFL) Bits_per_Byte_in_WordFL;\ntypedef Bit #(Bits_per_Byte_in_WordFL) Byte_in_WordFL;\ntypedef Vector #(Bytes_per_WordFL, Byte) WordFL_B;\n\n`endif\n\n\/\/ ================================================================\n\/\/ Tokens are used for signalling\/synchronization, and have no payload\n\ntypedef Bit #(0) Token;\n\n\/\/ ================================================================\n\/\/ Instruction fields\n\n\/\/ This is used for encoding Tandem Verifier traces\ntypedef enum { ISIZE16BIT, ISIZE32BIT\n } ISize deriving (Bits, Eq, FShow);\n\ntypedef Bit #(32) Instr;\ntypedef Bit #(7) Opcode;\ntypedef Bit #(5) RegName; \/\/ 32 registers, 0..31\ntypedef 32 NumRegs;\nInteger numRegs = valueOf (NumRegs);\n\nInstr illegal_instr = 32'h0000_0000;\n\nfunction Opcode instr_opcode (Instr x); return x [6:0]; endfunction\n\nfunction Bit #(2) instr_funct2 (Instr x); return x [26:25]; endfunction\nfunction Bit #(3) instr_funct3 (Instr x); return x [14:12]; endfunction\nfunction Bit #(5) instr_funct5 (Instr x); return x [31:27]; endfunction\nfunction Bit #(7) instr_funct7 (Instr x); return x [31:25]; endfunction\nfunction Bit #(10) instr_funct10 (Instr x); return { x [31:25], x [14:12] }; endfunction\nfunction Bit #(2) instr_fmt (Instr x); return x [26:25]; endfunction\n\nfunction RegName instr_rd (Instr x); return x [11:7]; endfunction\nfunction RegName instr_rs1 (Instr x); return x [19:15]; endfunction\nfunction RegName instr_rs2 (Instr x); return x [24:20]; endfunction\nfunction RegName instr_rs3 (Instr x); return x [31:27]; endfunction\nfunction CSR_Addr instr_csr (Instr x); return unpack(x [31:20]); endfunction\n\nfunction Bit #(12) instr_I_imm12 (Instr x);\n return x [31:20];\nendfunction\n\nfunction Bit #(12) instr_S_imm12 (Instr x);\n return { x [31:25], x [11:7] };\nendfunction\n\nfunction Bit #(13) instr_SB_imm13 (Instr x);\n return { x [31], x [7], x [30:25], x [11:8], 1'b0 };\nendfunction\n\nfunction Bit #(20) instr_U_imm20 (Instr x);\n return x [31:12];\nendfunction\n\nfunction Bit #(21) instr_UJ_imm21 (Instr x);\n return { x [31], x [19:12], x [20], x [30:21], 1'b0 };\nendfunction\n\n\/\/ For FENCE decode\nfunction Bit #(4) instr_pred (Instr x); return x [27:24]; endfunction\nfunction Bit #(4) instr_succ (Instr x); return x [23:20]; endfunction\n\n\/\/ For AMO decode\nfunction Bit #(2) instr_aqrl (Instr x); return x [26:25]; endfunction\n\n\/\/ ----------------\n\/\/ Decoded instructions\n\ntypedef struct {\n Opcode opcode;\n\n RegName rd;\n RegName rs1;\n RegName rs2;\n RegName rs3;\n CSR_Addr csr;\n\n Bit #(3) funct3;\n Bit #(5) funct5;\n Bit #(7) funct7;\n Bit #(10) funct10;\n\n Bit #(12) imm12_I;\n Bit #(12) imm12_S;\n Bit #(13) imm13_SB;\n Bit #(20) imm20_U;\n Bit #(21) imm21_UJ;\n\n Bit #(4) pred;\n Bit #(4) succ;\n\n Bit #(2) aqrl;\n } Decoded_Instr\nderiving (FShow, Bits);\n\nfunction Decoded_Instr fv_decode (Instr instr);\n return Decoded_Instr {opcode: instr_opcode (instr),\n\n\t\t\t rd: instr_rd (instr),\n\t\t\t rs1: instr_rs1 (instr),\n\t\t\t rs2: instr_rs2 (instr),\n\t\t\t rs3: instr_rs3 (instr),\n\t\t\t csr: instr_csr (instr),\n\n\t\t\t funct3: instr_funct3 (instr),\n\t\t\t funct5: instr_funct5 (instr),\n\t\t\t funct7: instr_funct7 (instr),\n\t\t\t funct10: instr_funct10 (instr),\n\n\t\t\t imm12_I: instr_I_imm12 (instr),\n\t\t\t imm12_S: instr_S_imm12 (instr),\n\t\t\t imm13_SB: instr_SB_imm13 (instr),\n\t\t\t imm20_U: instr_U_imm20 (instr),\n\t\t\t imm21_UJ: instr_UJ_imm21 (instr),\n\n\t\t\t pred: instr_pred (instr),\n\t\t\t succ: instr_succ (instr),\n\n\t\t\t aqrl: instr_aqrl (instr)\n\t\t\t };\nendfunction\n\n\/\/ Decodes if we need to read the GPR register file. This step becomes necessary\n\/\/ on integrating the FPU as certain instruction now do not require the GPR\n\/\/ anymore\n\/\/ IsFP, GPRRd\n\/\/ function Tuple2# (Bool, Bool) fv_decode_gpr_read (Decoded_Instr di);\n\/\/ `ifdef ISA_F\n\/\/ \/\/ FP_LD and FP_ST are treated as non-FP operation as far as GPR reads\n\/\/ \/\/ are concerned\n\/\/ if (di.opcode != op_FP) begin\n\/\/ return (tuple2 (False, True)); \/\/ Regular op with GPR read\n\/\/ end\n\/\/ \n\/\/ \/\/ This is an FP operation. The following f5 values would work for F and\n\/\/ \/\/ D subsets\n\/\/ else begin\n\/\/ if ( (di.funct5 == f5_FCVT_F_X)\n\/\/ || (di.funct5 == f5_FMV_W_X))\n\/\/ return (tuple2 (True, True)); \/\/ FP op with GPR read\n\/\/ else\n\/\/ return (tuple2 (True, False));\/\/ FP op with no GPR read\n\/\/ end\n\/\/ `else\n\/\/ return (tuple2 (False, True)); \/\/ Regular op with GPR read\n\/\/ `endif\n\/\/ endfunction\n\n\/\/ ================================================================\n\/\/ Instruction constructors\n\/\/ Used in 'C' decode to construct equivalent 32-bit instructions\n\n\/\/ R-type\nfunction Instr mkInstr_R_type (Bit #(7) funct7, RegName rs2, RegName rs1, Bit #(3) funct3, RegName rd, Bit #(7) opcode);\n let instr = { funct7, rs2, rs1, funct3, rd, opcode };\n return instr;\nendfunction\n\n\/\/ I-type\nfunction Instr mkInstr_I_type (Bit #(12) imm12, RegName rs1, Bit #(3) funct3, RegName rd, Bit #(7) opcode);\n let instr = { imm12, rs1, funct3, rd, opcode };\n return instr;\nendfunction\n\n\/\/ S-type\n\nfunction Instr mkInstr_S_type (Bit #(12) imm12, RegName rs2, RegName rs1, Bit #(3) funct3, Bit #(7) opcode);\n let instr = { imm12 [11:5], rs2, rs1, funct3, imm12 [4:0], opcode };\n return instr;\nendfunction\n\n\/\/ B-type\nfunction Instr mkInstr_B_type (Bit #(13) imm13, RegName rs2, RegName rs1, Bit #(3) funct3, Bit #(7) opcode);\n let instr = { imm13 [12], imm13 [10:5], rs2, rs1, funct3, imm13 [4:1], imm13 [11], opcode };\n return instr;\nendfunction\n\n\/\/ U-type\nfunction Instr mkInstr_U_type (Bit #(20) imm20, RegName rd, Bit #(7) opcode);\n let instr = { imm20, rd, opcode };\n return instr;\nendfunction\n\n\/\/ J-type\nfunction Instr mkInstr_J_type (Bit #(21) imm21, RegName rd, Bit #(7) opcode);\n let instr = { imm21 [20], imm21 [10:1], imm21 [11], imm21 [19:12], rd, opcode };\n return instr;\nendfunction\n\n\/\/ ================================================================\n\/\/ Symbolic register names\n\nRegName x0 = 0; RegName x1 = 1; RegName x2 = 2; RegName x3 = 3;\nRegName x4 = 4; RegName x5 = 5; RegName x6 = 6; RegName x7 = 7;\nRegName x8 = 8; RegName x9 = 9; RegName x10 = 10; RegName x11 = 11;\nRegName x12 = 12; RegName x13 = 13; RegName x14 = 14; RegName x15 = 15;\nRegName x16 = 16; RegName x17 = 17; RegName x18 = 18; RegName x19 = 19;\nRegName x20 = 20; RegName x21 = 21; RegName x22 = 22; RegName x23 = 23;\nRegName x24 = 24; RegName x25 = 25; RegName x26 = 26; RegName x27 = 27;\nRegName x28 = 28; RegName x29 = 29; RegName x30 = 30; RegName x31 = 31;\n\n\/\/ Register names used in calling convention\n\nRegName reg_zero = 0;\nRegName reg_ra = 1;\nRegName reg_sp = 2;\nRegName reg_gp = 3;\nRegName reg_tp = 4;\n\nRegName reg_t0 = 5; RegName reg_t1 = 6; RegName reg_t2 = 7;\nRegName reg_fp = 8;\nRegName reg_s0 = 8; RegName reg_s1 = 9;\n\nRegName reg_a0 = 10; RegName reg_a1 = 11;\nRegName reg_v0 = 10; RegName reg_v1 = 11;\n\nRegName reg_a2 = 12; RegName reg_a3 = 13; RegName reg_a4 = 14; RegName reg_a5 = 15;\nRegName reg_a6 = 16; RegName reg_a7 = 17;\n\nRegName reg_s2 = 18; RegName reg_s3 = 19; RegName reg_s4 = 20; RegName reg_s5 = 21;\nRegName reg_s6 = 22; RegName reg_s7 = 23; RegName reg_s8 = 24; RegName reg_s9 = 25;\nRegName reg_s10 = 26; RegName reg_s11 = 27;\n\nRegName reg_t3 = 28; RegName reg_t4 = 29; RegName reg_t5 = 30; RegName reg_t6 = 31;\n\n\/\/ ----------------\n\/\/ Is 'r' a standard register for PC save\/restore on call\/return?\n\/\/ This function is used in branch-predictors for managing the return-address stack.\n\nfunction Bool fn_reg_is_link (RegName r);\n return ((r == x1) || (r == x5));\nendfunction\n\n\/\/ ================================================================\n\/\/ Kinds of memory access (excluding AMOs)\n\ntypedef enum { Access_RWX_R, Access_RWX_W, Access_RWX_X } Access_RWX\nderiving (Eq, Bits, FShow);\n\n\/\/ ================================================================\n\/\/ Data sizes for LOAD\/STORE\n\ntypedef enum {BITS8,\n\t BITS16,\n\t BITS32,\n\t BITS64 \/\/ Even in RV32, to allow for Double (floating point)\n } Mem_Data_Size\nderiving (Eq, Bits, FShow);\n\n\/\/ ================================================================\n\/\/ LOAD\/STORE instructions\n\ntypedef Bit #(2) MemReqSize;\n\nMemReqSize f3_SIZE_B = 2'b00;\nMemReqSize f3_SIZE_H = 2'b01;\nMemReqSize f3_SIZE_W = 2'b10;\nMemReqSize f3_SIZE_D = 2'b11;\n\n\/\/ ----------------\n\/\/ Load instructions\n\nOpcode op_LOAD = 7'b00_000_11;\n\nBit #(3) f3_LB = 3'b000;\nBit #(3) f3_LH = 3'b001;\nBit #(3) f3_LW = 3'b010;\nBit #(3) f3_LD = 3'b011;\nBit #(3) f3_LBU = 3'b100;\nBit #(3) f3_LHU = 3'b101;\nBit #(3) f3_LWU = 3'b110;\n\n\/\/ ----------------\n\/\/ Store instructions\n\nOpcode op_STORE = 7'b01_000_11;\n\nBit #(3) f3_SB = 3'b000;\nBit #(3) f3_SH = 3'b001;\nBit #(3) f3_SW = 3'b010;\nBit #(3) f3_SD = 3'b011;\n\n\/\/ ================================================================\n\/\/ Memory Model\n\nOpcode op_MISC_MEM = 7'b00_011_11;\n\nBit #(3) f3_FENCE = 3'b000;\nBit #(3) f3_FENCE_I = 3'b001;\n\ntypedef struct {\n \/\/ Predecessors\n Bool pi; \/\/ IO reads\n Bool po; \/\/ IO writes\n Bool pr; \/\/ Mem reads\n Bool pw; \/\/ Mem writes\n \/\/ Successors\n Bool si;\n Bool so;\n Bool sr;\n Bool sw;\n } Fence_Ordering\nderiving (FShow);\n\ninstance Bits #(Fence_Ordering, 8);\n function Bit #(8) pack (Fence_Ordering fo);\n return {pack (fo.pi),\n\t pack (fo.po),\n\t pack (fo.pr),\n\t pack (fo.pw),\n\t pack (fo.si),\n\t pack (fo.so),\n\t pack (fo.sr),\n\t pack (fo.sw) };\n endfunction\n function Fence_Ordering unpack (Bit #(8) b8);\n return Fence_Ordering {pi: unpack (b8 [7]),\n\t\t\t po: unpack (b8 [6]),\n\t\t\t pr: unpack (b8 [5]),\n\t\t\t pw: unpack (b8 [4]),\n\t\t\t si: unpack (b8 [3]),\n\t\t\t so: unpack (b8 [2]),\n\t\t\t sr: unpack (b8 [1]),\n\t\t\t sw: unpack (b8 [0]) };\n endfunction\nendinstance\n\n\/\/ ================================================================\n\/\/ Atomic Memory Operation Instructions\n\nOpcode op_AMO = 7'b01_011_11;\n\n\/\/ NOTE: bit [4] for aq, and [3] for rl, are here set to zero\n\nBit #(3) f3_AMO_W = 3'b010;\nBit #(3) f3_AMO_D = 3'b011;\n\nBit #(5) f5_AMO_LR = 5'b00010;\nBit #(5) f5_AMO_SC = 5'b00011;\nBit #(5) f5_AMO_ADD = 5'b00000;\nBit #(5) f5_AMO_SWAP = 5'b00001;\nBit #(5) f5_AMO_XOR = 5'b00100;\nBit #(5) f5_AMO_AND = 5'b01100;\nBit #(5) f5_AMO_OR = 5'b01000;\nBit #(5) f5_AMO_MIN = 5'b10000;\nBit #(5) f5_AMO_MAX = 5'b10100;\nBit #(5) f5_AMO_MINU = 5'b11000;\nBit #(5) f5_AMO_MAXU = 5'b11100;\n\nBit #(10) f10_LR_W = 10'b00010_00_010;\nBit #(10) f10_SC_W = 10'b00011_00_010;\nBit #(10) f10_AMOADD_W = 10'b00000_00_010;\nBit #(10) f10_AMOSWAP_W = 10'b00001_00_010;\nBit #(10) f10_AMOXOR_W = 10'b00100_00_010;\nBit #(10) f10_AMOAND_W = 10'b01100_00_010;\nBit #(10) f10_AMOOR_W = 10'b01000_00_010;\nBit #(10) f10_AMOMIN_W = 10'b10000_00_010;\nBit #(10) f10_AMOMAX_W = 10'b10100_00_010;\nBit #(10) f10_AMOMINU_W = 10'b11000_00_010;\nBit #(10) f10_AMOMAXU_W = 10'b11100_00_010;\n\nBit #(10) f10_LR_D = 10'b00010_00_011;\nBit #(10) f10_SC_D = 10'b00011_00_011;\nBit #(10) f10_AMOADD_D = 10'b00000_00_011;\nBit #(10) f10_AMOSWAP_D = 10'b00001_00_011;\nBit #(10) f10_AMOXOR_D = 10'b00100_00_011;\nBit #(10) f10_AMOAND_D = 10'b01100_00_011;\nBit #(10) f10_AMOOR_D = 10'b01000_00_011;\nBit #(10) f10_AMOMIN_D = 10'b10000_00_011;\nBit #(10) f10_AMOMAX_D = 10'b10100_00_011;\nBit #(10) f10_AMOMINU_D = 10'b11000_00_011;\nBit #(10) f10_AMOMAXU_D = 10'b11100_00_011;\n\n\/\/ ================================================================\n\/\/ Integer Register-Immediate Instructions\n\nOpcode op_OP_IMM = 7'b00_100_11;\n\nBit #(3) f3_ADDI = 3'b000;\nBit #(3) f3_SLLI = 3'b001;\nBit #(3) f3_SLTI = 3'b010;\nBit #(3) f3_SLTIU = 3'b011;\nBit #(3) f3_XORI = 3'b100;\nBit #(3) f3_SRxI = 3'b101; Bit #(3) f3_SRLI = 3'b101; Bit #(3) f3_SRAI = 3'b101;\nBit #(3) f3_ORI = 3'b110;\nBit #(3) f3_ANDI = 3'b111;\n\n\/\/ ================================================================\n\/\/ Integer Register-Immediate 32b Instructions for RV64\n\nOpcode op_OP_IMM_32 = 7'b00_110_11;\n\nBit #(3) f3_ADDIW = 3'b000;\nBit #(3) f3_SLLIW = 3'b001;\nBit #(3) f3_SRxIW = 3'b101; Bit #(3) f3_SRLIW = 3'b101; Bit #(3) f3_SRAIW = 3'b101;\n\n\/\/ OP_IMM.SLLI\/SRLI\/SRAI for RV32\nBit #(7) msbs7_SLLI = 7'b_000_0000;\nBit #(7) msbs7_SRLI = 7'b_000_0000;\nBit #(7) msbs7_SRAI = 7'b_010_0000;\n\n\/\/ OP_IMM.SLLI\/SRLI\/SRAI for RV64\nBit #(6) msbs6_SLLI = 6'b_00_0000;\nBit #(6) msbs6_SRLI = 6'b_00_0000;\nBit #(6) msbs6_SRAI = 6'b_01_0000;\n\n\/\/ ================================================================\n\/\/ Integer Register-Register Instructions\n\nOpcode op_OP = 7'b01_100_11;\n\nBit #(10) f10_ADD = 10'b000_0000_000;\nBit #(10) f10_SUB = 10'b010_0000_000;\nBit #(10) f10_SLL = 10'b000_0000_001;\nBit #(10) f10_SLT = 10'b000_0000_010;\nBit #(10) f10_SLTU = 10'b000_0000_011;\nBit #(10) f10_XOR = 10'b000_0000_100;\nBit #(10) f10_SRL = 10'b000_0000_101;\nBit #(10) f10_SRA = 10'b010_0000_101;\nBit #(10) f10_OR = 10'b000_0000_110;\nBit #(10) f10_AND = 10'b000_0000_111;\n\nBit #(7) funct7_ADD = 7'b_000_0000; Bit #(3) funct3_ADD = 3'b_000;\nBit #(7) funct7_SUB = 7'b_010_0000; Bit #(3) funct3_SUB = 3'b_000;\nBit #(7) funct7_XOR = 7'b_000_0000; Bit #(3) funct3_XOR = 3'b_100;\nBit #(7) funct7_OR = 7'b_000_0000; Bit #(3) funct3_OR = 3'b_110;\nBit #(7) funct7_AND = 7'b_000_0000; Bit #(3) funct3_AND = 3'b_111;\n\n\/\/ ----------------\n\/\/ MUL\/DIV\/REM family\n\nBit #(7) f7_MUL_DIV_REM = 7'b000_0001;\n\nfunction Bool f7_is_OP_MUL_DIV_REM (Bit #(7) f7);\n return (f7 == f7_MUL_DIV_REM);\nendfunction\n\nBit #(3) f3_MUL = 3'b000;\nBit #(3) f3_MULH = 3'b001;\nBit #(3) f3_MULHSU = 3'b010;\nBit #(3) f3_MULHU = 3'b011;\nBit #(3) f3_DIV = 3'b100;\nBit #(3) f3_DIVU = 3'b101;\nBit #(3) f3_REM = 3'b110;\nBit #(3) f3_REMU = 3'b111;\n\nBit #(10) f10_MUL = 10'b000_0001_000;\nBit #(10) f10_MULH = 10'b000_0001_001;\nBit #(10) f10_MULHSU = 10'b000_0001_010;\nBit #(10) f10_MULHU = 10'b000_0001_011;\nBit #(10) f10_DIV = 10'b000_0001_100;\nBit #(10) f10_DIVU = 10'b000_0001_101;\nBit #(10) f10_REM = 10'b000_0001_110;\nBit #(10) f10_REMU = 10'b000_0001_111;\n\n\/\/ ================================================================\n\/\/ Integer Register-Register 32b Instructions for RV64\n\nOpcode op_OP_32 = 7'b01_110_11;\n\nBit #(10) f10_ADDW = 10'b000_0000_000;\nBit #(10) f10_SUBW = 10'b010_0000_000;\nBit #(10) f10_SLLW = 10'b000_0000_001;\nBit #(10) f10_SRLW = 10'b000_0000_101;\nBit #(10) f10_SRAW = 10'b010_0000_101;\n\nBit #(7) funct7_ADDW = 7'b_000_0000; Bit #(3) funct3_ADDW = 3'b_000;\nBit #(7) funct7_SUBW = 7'b_010_0000; Bit #(3) funct3_SUBW = 3'b_000;\n\nBit #(10) f10_MULW = 10'b000_0001_000;\nBit #(10) f10_DIVW = 10'b000_0001_100;\nBit #(10) f10_DIVUW = 10'b000_0001_101;\nBit #(10) f10_REMW = 10'b000_0001_110;\nBit #(10) f10_REMUW = 10'b000_0001_111;\n\nfunction Bool is_OP_32_MUL_DIV_REM (Bit #(10) f10);\n return ( (f10 == f10_MULW)\n\t || (f10 == f10_DIVW)\n\t || (f10 == f10_DIVUW)\n\t || (f10 == f10_REMW)\n\t || (f10 == f10_REMUW));\nendfunction\n\n\/\/ ================================================================\n\/\/ LUI, AUIPC\n\nOpcode op_LUI = 7'b01_101_11;\nOpcode op_AUIPC = 7'b00_101_11;\n\n\/\/ ================================================================\n\/\/ Control transfer\n\nOpcode op_BRANCH = 7'b11_000_11;\n\nBit #(3) f3_BEQ = 3'b000;\nBit #(3) f3_BNE = 3'b001;\nBit #(3) f3_BLT = 3'b100;\nBit #(3) f3_BGE = 3'b101;\nBit #(3) f3_BLTU = 3'b110;\nBit #(3) f3_BGEU = 3'b111;\n\nOpcode op_JAL = 7'b11_011_11;\n\nOpcode op_JALR = 7'b11_001_11;\nBit #(3) funct3_JALR = 3'b000;\n\n`ifdef ISA_F\n\/\/ ================================================================\n\/\/ Floating Point Instructions\n\/\/ TODO: these are implementation choices; should not be in ISA_Decls\n\/\/ Enumeration of floating point opcodes for decode within the FPU\ntypedef enum {\n FPAdd\n , FPSub\n , FPMul\n , FPDiv\n , FPSqrt\n , FPMAdd\n , FPMSub\n , FPNMAdd\n , FPNMSub } FpuOp deriving (Bits, Eq, FShow);\n\n\/\/ Enumeration of rounding modes\ntypedef enum {\n Rnd_Nearest_Even\n , Rnd_Zero\n , Rnd_Minus_Inf\n , Rnd_Plus_Inf\n , Rnd_Nearest_Max_Mag\n} RoundMode deriving (Bits, Eq, FShow);\n\n\/\/ Funct2 encoding\nBit #(2) f2_S = 2'b00;\nBit #(2) f2_D = 2'b01;\nBit #(2) f2_Q = 2'b11;\n\n\/\/ Floating point Load-Store\nOpcode op_LOAD_FP = 7'b_00_001_11;\nOpcode op_STORE_FP = 7'b_01_001_11;\nBit #(3) f3_FSW = 3'b010;\nBit #(3) f3_FSD = 3'b011;\nBit #(3) f3_FLW = 3'b010;\nBit #(3) f3_FLD = 3'b011;\n\n\/\/ Fused FP Multiply Add\/Sub instructions\nOpcode op_FMADD = 7'b10_00_011;\nOpcode op_FMSUB = 7'b10_00_111;\nOpcode op_FNMSUB = 7'b10_01_011;\nOpcode op_FNMADD = 7'b10_01_111;\n\n\/\/ All other FP intructions\nOpcode op_FP = 7'b10_10_011;\n\nBit #(7) f7_FADD_D = 7'h1 ;\nBit #(7) f7_FSUB_D = 7'h5 ;\nBit #(7) f7_FMUL_D = 7'h9 ;\nBit #(7) f7_FDIV_D = 7'hD ;\nBit #(7) f7_FSQRT_D = 7'h2D;\nBit #(7) f7_FCMP_D = 7'h51;\nBit #(7) f7_FMIN_D = 7'h15;\nBit #(7) f7_FMAX_D = 7'h15;\nBit #(7) f7_FSGNJ_D = 7'h11;\n\nBit #(7) f7_FADD_S = 7'h0 ;\nBit #(7) f7_FSUB_S = 7'h4 ;\nBit #(7) f7_FMUL_S = 7'h8 ;\nBit #(7) f7_FDIV_S = 7'hC ;\nBit #(7) f7_FSQRT_S = 7'h2C;\nBit #(7) f7_FCMP_S = 7'h50;\nBit #(7) f7_FMIN_S = 7'h14;\nBit #(7) f7_FMAX_S = 7'h14;\nBit #(7) f7_FSGNJ_S = 7'h10;\n\nBit #(7) f7_FCVT_W_S = 7'h60;\nBit #(7) f7_FCVT_WU_S = 7'h60;\nBit #(7) f7_FCVT_S_W = 7'h68;\nBit #(7) f7_FCVT_S_WU = 7'h68;\n\nBit #(7) f7_FCVT_L_S = 7'h60;\nBit #(7) f7_FCVT_LU_S = 7'h60;\nBit #(7) f7_FCVT_S_L = 7'h68;\nBit #(7) f7_FCVT_S_LU = 7'h68;\n\nBit #(7) f7_FCVT_S_D = 7'h20;\nBit #(7) f7_FCVT_D_S = 7'h21;\nBit #(7) f7_FCVT_W_D = 7'h61;\nBit #(7) f7_FCVT_WU_D = 7'h61;\nBit #(7) f7_FCVT_D_W = 7'h69;\nBit #(7) f7_FCVT_D_WU = 7'h69;\n\nBit #(7) f7_FCVT_L_D = 7'h61;\nBit #(7) f7_FCVT_LU_D = 7'h61;\nBit #(7) f7_FCVT_D_L = 7'h69;\nBit #(7) f7_FCVT_D_LU = 7'h69;\n\nBit #(7) f7_FMV_X_D = 7'h71;\nBit #(7) f7_FMV_D_X = 7'h79;\nBit #(7) f7_FCLASS_D = 7'h71;\nBit #(7) f7_FMV_X_W = 7'h70;\nBit #(7) f7_FMV_W_X = 7'h78;\nBit #(7) f7_FCLASS_S = 7'h70;\n\n\/\/ fv_is_rd_in_GPR: Checks if the request generates a result which\n\/\/ should be written into the GPR\nfunction Bool fv_is_rd_in_GPR (Bit #(7) funct7, RegName rs2);\n\n`ifdef ISA_D\n let is_FCVT_W_D = (funct7 == f7_FCVT_W_D)\n && (rs2 == 0);\n let is_FCVT_WU_D = (funct7 == f7_FCVT_WU_D)\n && (rs2 == 1);\n`ifdef RV64\n let is_FCVT_L_D = (funct7 == f7_FCVT_L_D)\n && (rs2 == 2);\n let is_FCVT_LU_D = (funct7 == f7_FCVT_LU_D)\n && (rs2 == 3);\n\n`endif\n \/\/ FCLASS.D also maps to this -- both write to GPR\n let is_FMV_X_D = (funct7 == f7_FMV_X_D);\n \/\/ FEQ.D, FLE.D, FLT.D map to this\n let is_FCMP_D = (funct7 == f7_FCMP_D);\n`endif\n\n let is_FCVT_W_S = (funct7 == f7_FCVT_W_S)\n && (rs2 == 0);\n let is_FCVT_WU_S = (funct7 == f7_FCVT_WU_S)\n && (rs2 == 1);\n`ifdef RV64\n let is_FCVT_L_S = (funct7 == f7_FCVT_L_S)\n && (rs2 == 2);\n let is_FCVT_LU_S = (funct7 == f7_FCVT_LU_S)\n && (rs2 == 3);\n`endif\n\n \/\/ FCLASS.S also maps to this -- both write to GPR\n let is_FMV_X_W = (funct7 == f7_FMV_X_W);\n\n \/\/ FEQ.S, FLE.S, FLT.S map to this\n let is_FCMP_S = (funct7 == f7_FCMP_S);\n\n return (\n False\n`ifdef ISA_D\n || is_FCVT_W_D\n || is_FCVT_WU_D\n`ifdef RV64\n || is_FCVT_L_D\n || is_FCVT_LU_D\n`endif\n || is_FMV_X_D\n || is_FCMP_D\n`endif\n`ifdef RV64\n || is_FCVT_L_S\n || is_FCVT_LU_S\n`endif\n || is_FCVT_W_S\n || is_FCVT_WU_S\n || is_FMV_X_W\n || is_FCMP_S\n );\nendfunction\n\n\/\/ Check if a rounding mode value in the FCSR.FRM is valid\nfunction Bool fv_fcsr_frm_valid (Bit #(3) frm);\n return ( (frm != 3'b101) \n && (frm != 3'b110)\n && (frm != 3'b111)\n );\nendfunction \n\n\/\/ Check if a rounding mode value in the instr is valid\nfunction Bool fv_inst_frm_valid (Bit #(3) frm);\n return ( (frm != 3'b101) \n && (frm != 3'b110)\n );\nendfunction\n\n\/\/ fv_rounding_mode_check\n\/\/ Returns the correct rounding mode considering the values in the\n\/\/ FCSR and the instruction and checks legality\nfunction Tuple2# (Bit #(3), Bool) fv_rmode_check (\n Bit #(3) inst_frm, Bit #(3) fcsr_frm);\n let rm = (inst_frm == 3'h7) ? fcsr_frm : inst_frm;\n let rm_is_legal = (inst_frm == 3'h7) ? fv_fcsr_frm_valid (fcsr_frm)\n : fv_inst_frm_valid (inst_frm);\n return (tuple2 (rm, rm_is_legal));\nendfunction\n\n\/\/ A D instruction requires misa.f to be set as well as misa.d\nfunction Bool fv_is_fp_instr_legal (\n Bit #(7) f7, Bit #(3) rm, RegName rs2, Opcode fopc);\n Bit #(2) f2 = f7[1:0];\n Bool is_legal = True;\n if ( (fopc == op_FMADD )\n || (fopc == op_FMSUB )\n || (fopc == op_FNMADD)\n || (fopc == op_FNMSUB))\n`ifdef ISA_D\n return ((f2 == f2_S) || (f2 == f2_D)); \/\/ Both SP and DP are legal\n`else\n return (f2 == f2_S); \/\/ Only SP is legal\n`endif\n else\n if ( (f7 == f7_FADD_S) \n || (f7 == f7_FSUB_S) \n || (f7 == f7_FMUL_S) \n`ifdef INCLUDE_FDIV\n || (f7 == f7_FDIV_S) \n`endif\n`ifdef INCLUDE_FSQRT\n || (f7 == f7_FSQRT_S) \n`endif\n || ((f7 == f7_FSGNJ_S) && ( rm == 0))\n || ((f7 == f7_FSGNJ_S) && ( rm == 1))\n || ((f7 == f7_FSGNJ_S) && ( rm == 2))\n || ((f7 == f7_FCVT_W_S) && (rs2 == 0))\n || ((f7 == f7_FCVT_WU_S)&& (rs2 == 1))\n`ifdef RV64\n || ((f7 == f7_FCVT_L_S) && (rs2 == 2))\n || ((f7 == f7_FCVT_LU_S)&& (rs2 == 3))\n`endif \n || ((f7 == f7_FCVT_S_W) && (rs2 == 0))\n || ((f7 == f7_FCVT_S_WU)&& (rs2 == 1)) \n`ifdef RV64 \n || ((f7 == f7_FCVT_S_L) && (rs2 == 2))\n || ((f7 == f7_FCVT_S_LU)&& (rs2 == 3))\n`endif\n || ((f7 == f7_FMIN_S) && ( rm == 0))\n || ((f7 == f7_FMAX_S) && ( rm == 1))\n || ((f7 == f7_FCMP_S) && ( rm == 0))\n || ((f7 == f7_FCMP_S) && ( rm == 1))\n || ((f7 == f7_FCMP_S) && ( rm == 2))\n || ((f7 == f7_FMV_X_W) && ( rm == 0))\n || ((f7 == f7_FMV_W_X) && ( rm == 0))\n || ((f7 == f7_FCLASS_S) && ( rm == 1))\n`ifdef ISA_D\n || (f7 == f7_FADD_D) \n || (f7 == f7_FSUB_D) \n || (f7 == f7_FMUL_D) \n`ifdef INCLUDE_FDIV\n || (f7 == f7_FDIV_D) \n`endif\n`ifdef INCLUDE_FSQRT\n || (f7 == f7_FSQRT_D) \n`endif\n || ((f7 == f7_FSGNJ_D) && ( rm == 0))\n || ((f7 == f7_FSGNJ_D) && ( rm == 1))\n || ((f7 == f7_FSGNJ_D) && ( rm == 2))\n || ((f7 == f7_FCVT_W_D) && (rs2 == 0))\n || ((f7 == f7_FCVT_WU_D)&& (rs2 == 1))\n`ifdef RV64\n || ((f7 == f7_FCVT_L_D) && (rs2 == 2))\n || ((f7 == f7_FCVT_LU_D)&& (rs2 == 3))\n`endif \n || ((f7 == f7_FCVT_D_W) && (rs2 == 0))\n || ((f7 == f7_FCVT_D_WU)&& (rs2 == 1)) \n`ifdef RV64 \n || ((f7 == f7_FCVT_D_L) && (rs2 == 2))\n || ((f7 == f7_FCVT_D_LU)&& (rs2 == 3))\n`endif\n || ((f7 == f7_FCVT_D_S) && (rs2 == 0))\n || ((f7 == f7_FCVT_S_D) && (rs2 == 1))\n || ((f7 == f7_FMIN_D) && ( rm == 0))\n || ((f7 == f7_FMAX_D) && ( rm == 1))\n || ((f7 == f7_FCMP_D) && ( rm == 0))\n || ((f7 == f7_FCMP_D) && ( rm == 1))\n || ((f7 == f7_FCMP_D) && ( rm == 2))\n || ((f7 == f7_FMV_X_D) && ( rm == 0))\n || ((f7 == f7_FMV_D_X) && ( rm == 0))\n || ((f7 == f7_FCLASS_D) && ( rm == 1))\n`endif\n ) return True;\n else return False;\nendfunction\n\n\/\/ Returns True if the first operand (val1) should be taken from the GPR\n\/\/ instead of the FPR for a FP opcode\nfunction Bool fv_fp_val1_from_gpr (Opcode opcode, Bit#(7) f7, RegName rs2);\n return (\n (opcode == op_FP)\n && ( False\n`ifdef ISA_D\n || ((f7 == f7_FCVT_D_W) && (rs2 == 0))\n || ((f7 == f7_FCVT_D_WU) && (rs2 == 1))\n`ifdef RV64\n || ((f7 == f7_FCVT_D_L) && (rs2 == 2))\n || ((f7 == f7_FCVT_D_LU) && (rs2 == 3))\n`endif\n || ((f7 == f7_FMV_D_X))\n`endif\n || ((f7 == f7_FCVT_S_W) && (rs2 == 0))\n || ((f7 == f7_FCVT_S_WU) && (rs2 == 1))\n`ifdef RV64\n || ((f7 == f7_FCVT_S_L) && (rs2 == 2))\n || ((f7 == f7_FCVT_S_LU) && (rs2 == 3))\n`endif\n || ((f7 == f7_FMV_W_X))\n )\n );\nendfunction\n`endif\n\n\/\/ ================================================================\n\/\/ System Instructions\nOpcode op_SYSTEM = 7'b11_100_11;\n\n\/\/ sub-opcodes: (in funct3 field)\nBit #(3) f3_PRIV = 3'b000;\nBit #(3) f3_CSRRW = 3'b001;\nBit #(3) f3_CSRRS = 3'b010;\nBit #(3) f3_CSRRC = 3'b011;\nBit #(3) f3_SYSTEM_ILLEGAL = 3'b100;\nBit #(3) f3_CSRRWI = 3'b101;\nBit #(3) f3_CSRRSI = 3'b110;\nBit #(3) f3_CSRRCI = 3'b111;\n\n\/\/ sub-sub-opcodes for f3_PRIV\n\nBit #(12) f12_ECALL = 12'b_0000_0000_0000;\nBit #(12) f12_EBREAK = 12'b_0000_0000_0001;\n\nBit #(12) f12_URET = 12'b_0000_0000_0010;\nBit #(12) f12_SRET = 12'b_0001_0000_0010;\nBit #(12) f12_HRET = 12'b_0010_0000_0010;\nBit #(12) f12_MRET = 12'b_0011_0000_0010;\nBit #(12) f12_WFI = 12'b_0001_0000_0101;\n\n\/\/ v1.10 sub-sub-opcode for SFENCE_VMA\nBit #(7) f7_SFENCE_VMA = 7'b_0001_001;\n\nInstr break_instr = { f12_EBREAK, 5'b00000, 3'b000, 5'b00000, op_SYSTEM };\n\nfunction Bool fn_instr_is_csrrx (Instr instr);\n let decoded_instr = fv_decode (instr);\n let opcode = decoded_instr.opcode;\n let funct3 = decoded_instr.funct3;\n let csr = decoded_instr.csr;\n return ((opcode == op_SYSTEM) && f3_is_CSRR_any (funct3));\nendfunction\n\nfunction Bool f3_is_CSRR_any (Bit #(3) f3);\n return (f3_is_CSRR_W (f3) || f3_is_CSRR_S_or_C (f3));\nendfunction\n\nfunction Bool f3_is_CSRR_W (Bit #(3) f3);\n return ((f3 == f3_CSRRW) || (f3 == f3_CSRRWI));\nendfunction\n\nfunction Bool f3_is_CSRR_S_or_C (Bit #(3) f3);\n return ((f3 == f3_CSRRS) || (f3 == f3_CSRRSI) ||\n\t (f3 == f3_CSRRC) || (f3 == f3_CSRRCI));\nendfunction\n\n\/\/ ================================================================\n\/\/ Privilege Modes\n\ntypedef 4 Num_Priv_Modes;\n\ntypedef Bit #(2) Priv_Mode;\n\nPriv_Mode u_Priv_Mode = 2'b00;\nPriv_Mode s_Priv_Mode = 2'b01;\nPriv_Mode reserved_Priv_Mode = 2'b10;\nPriv_Mode m_Priv_Mode = 2'b11;\n\nfunction Fmt fshow_Priv_Mode (Priv_Mode pm);\n return case (pm)\n\t u_Priv_Mode: $format (\"U\");\n\t s_Priv_Mode: $format (\"S\");\n\t m_Priv_Mode: $format (\"M\");\n\t default: $format (\"RESERVED\");\n\t endcase;\nendfunction\n\n\/\/ ================================================================\n\/\/ Control\/Status registers\n\ntypedef Bit #(12) CSR_Addr;\n\nfunction Bool fn_csr_addr_can_write (CSR_Addr csr_addr);\n return (csr_addr [11:10] != 2'b11);\nendfunction\n\nfunction Bool fn_csr_addr_priv_ok (CSR_Addr csr_addr, Priv_Mode priv_mode);\n return (priv_mode >= csr_addr [9:8]);\nendfunction\n\n\/\/ ----------------\n\/\/ User-level CSR addresses\n\nCSR_Addr csr_addr_ustatus = 12'h000; \/\/ User status\nCSR_Addr csr_addr_uie = 12'h004; \/\/ User interrupt-enable\nCSR_Addr csr_addr_utvec = 12'h005; \/\/ User trap handler base address\n\nCSR_Addr csr_addr_uscratch = 12'h040; \/\/ Scratch register for trap handlers\nCSR_Addr csr_addr_uepc = 12'h041; \/\/ User exception program counter\nCSR_Addr csr_addr_ucause = 12'h042; \/\/ User trap cause\nCSR_Addr csr_addr_utval = 12'h043; \/\/ User bad address or instruction\nCSR_Addr csr_addr_uip = 12'h044; \/\/ User interrupt pending\n\nCSR_Addr csr_addr_fflags = 12'h001; \/\/ Floating-point accrued exceptions\nCSR_Addr csr_addr_frm = 12'h002; \/\/ Floating-point Dynamic Rounding Mode\nCSR_Addr csr_addr_fcsr = 12'h003; \/\/ Floating-point Control and Status Register (frm + fflags)\n\nCSR_Addr csr_addr_cycle = 12'hC00; \/\/ Cycle counter for RDCYCLE\nCSR_Addr csr_addr_time = 12'hC01; \/\/ Timer for RDTIME\nCSR_Addr csr_addr_instret = 12'hC02; \/\/ Instructions retired counter for RDINSTRET\n\nCSR_Addr csr_addr_hpmcounter3 = 12'hC03; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter4 = 12'hC04; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter5 = 12'hC05; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter6 = 12'hC06; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter7 = 12'hC07; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter8 = 12'hC08; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter9 = 12'hC09; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter10 = 12'hC0A; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter11 = 12'hC0B; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter12 = 12'hC0C; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter13 = 12'hC0D; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter14 = 12'hC0E; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter15 = 12'hC0F; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter16 = 12'hC10; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter17 = 12'hC11; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter18 = 12'hC12; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter19 = 12'hC13; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter20 = 12'hC14; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter21 = 12'hC15; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter22 = 12'hC16; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter23 = 12'hC17; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter24 = 12'hC18; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter25 = 12'hC19; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter26 = 12'hC1A; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter27 = 12'hC1B; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter28 = 12'hC1C; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter29 = 12'hC1D; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter30 = 12'hC1E; \/\/ Performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter31 = 12'hC1F; \/\/ Performance-monitoring counter\n\nCSR_Addr csr_addr_cycleh = 12'hC80; \/\/ Upper 32 bits of csr_cycle (RV32I only)\nCSR_Addr csr_addr_timeh = 12'hC81; \/\/ Upper 32 bits of csr_time (RV32I only)\nCSR_Addr csr_addr_instreth = 12'hC82; \/\/ Upper 32 bits of csr_instret (RV32I only)\n\nCSR_Addr csr_addr_hpmcounter3h = 12'hC83; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter4h = 12'hC84; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter5h = 12'hC85; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter6h = 12'hC86; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter7h = 12'hC87; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter8h = 12'hC88; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter9h = 12'hC89; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter10h = 12'hC8A; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter11h = 12'hC8B; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter12h = 12'hC8C; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter13h = 12'hC8D; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter14h = 12'hC8E; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter15h = 12'hC8F; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter16h = 12'hC90; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter17h = 12'hC91; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter18h = 12'hC92; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter19h = 12'hC93; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter20h = 12'hC94; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter21h = 12'hC95; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter22h = 12'hC96; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter23h = 12'hC97; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter24h = 12'hC98; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter25h = 12'hC99; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter26h = 12'hC9A; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter27h = 12'hC9B; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter28h = 12'hC9C; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter29h = 12'hC9D; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter30h = 12'hC9E; \/\/ Upper 32 bits of performance-monitoring counter\nCSR_Addr csr_addr_hpmcounter31h = 12'hC9F; \/\/ Upper 32 bits of performance-monitoring counter\n\n\/\/ Information from the CSR on a new trap. \ntypedef struct {\n Addr pc;\n WordXL mstatus;\n WordXL mcause;\n Priv_Mode priv;\n} Trap_Info deriving (Bits, Eq, FShow);\n\n\/\/ ================================================================\n\/\/ 'C' Extension (\"compressed\" instructions)\n\n`include \"ISA_Decls_C.bsv\"\n\n\/\/ ================================================================\n\/\/ Supervisor-Level ISA defs\n\n`include \"ISA_Decls_Priv_S.bsv\"\n\n\/\/ ================================================================\n\/\/ Hypervisor-Level ISA defs\n\n\/\/ `include \"ISA_Decls_Priv_H.bsv\"\n\n\/\/ ================================================================\n\/\/ Machine-Level ISA defs\n\n`include \"ISA_Decls_Priv_M.bsv\"\n\n\/\/ ================================================================\n\nendpackage\n","avg_line_length":34.5290546401,"max_line_length":121,"alphanum_fraction":0.5907515322} {"size":430,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"typedef Bit#(5) Type;\n\ninterface IFC#(type mType);\n (* prefix = \"g\" *)\n method Action one(mType a, mType b);\n (* prefix = \"\" *)\n method mType two(mType g_a);\nendinterface\n\n(* synthesize *)\nmodule mkDesign_01 (IFC#(Type));\n\n Reg#(Type) val <- mkReg(0);\n Reg#(Type) res <- mkReg(0);\n\n\n method Action one(a,b);\n val <= a;\n res <= b;\n endmethod\t\n\n method Type two(g_a);\n return res+g_a;\n endmethod\t\n \t \n\t\nendmodule\n","avg_line_length":15.3571428571,"max_line_length":37,"alphanum_fraction":0.5953488372} {"size":2783,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"package MkWrapSTRAM;\n\nimport Vector::*;\nimport Precedence::*;\nimport RegFile::*;\nimport SyncSRAM::*;\nimport STRAM::*;\nimport SPSRAM::*;\nimport TRAM::*;\nimport RAM::*;\nimport ClientServer::*;\nimport GetPut::*;\n\nmodule mkDesign_MkWrapSTRAM (TRAM#(Bit#(1),Bit#(16),Bit#(16)));\n \n TRAM#(Bit#(1),Bit#(16),Bit#(16)) tx <- mkWrapSTRAM(mkSPSRAM(65536));\n\n return(tx);\n\nendmodule: mkDesign_MkWrapSTRAM \n\nmodule mkTestbench_MkWrapSTRAM ();\n\n TRAM#(Bit#(1),Bit#(16),Bit#(16)) tx <- mkWrapSTRAM(mkSPSRAM(65536));\n Reg#(Bit#(16)) in_data <- mkReg(16'h5555);\n Reg#(Bit#(16)) in_address <- mkReg(16'h0000);\n Reg#(Bit#(16)) in_offset <- mkReg(0);\n Reg#(Bit#(16)) out_offset <- mkReg(0);\n Reg#(Bit#(16)) out_address <- mkReg(16'h0000);\n Reg#(Bit#(16)) out_data <- mkReg(16'h5555);\n Reg#(Bit#(8)) counter <- mkReg(0);\n Reg#(Bool) request <- mkReg(True);\n Reg#(Bool) fail <- mkReg(False);\n\n \/\/RAMreq#(Bit#(16),Bit#(16)) x = (RAMreqWrite(in_data,in_address));\n\n Rules r1 = rules \n rule always_fire (True);\n \t counter <= counter + 1;\n endrule\n endrules;\n \n Rules r2 = rules \n rule data_write (counter < 16 );\n Tuple2#(Bit#(16),Bit#(16)) x = tuple2(in_address,in_data) ;\n TRAMreq#(Bit#(1),Bit#(16),Bit#(16)) y = Write(x);\n \t tx.request.put(y);\n in_data <= in_data + 25;\n in_offset <= in_offset + 5;\n in_address <= in_address + in_offset + 1;\n $display(\"Cycle Number: %d, Writing Data: %h address %h offset %h\", counter, in_data,in_address,in_offset);\n endrule\n endrules;\n \n Rules r3 = rules \n rule request_value ((counter >= 16) && (counter <32));\n\t Tuple2#(Bit#(1),Bit#(16)) z = tuple2(1, out_address) ;\n TRAMreq#(Bit#(1),Bit#(16),Bit#(16)) req = Read(z);\n \t tx.request.put(req);\n out_offset <= out_offset + 5;\n out_address <= out_address + out_offset +1;\n \t \/\/request <= False;\n endrule\n endrules;\n \n Rules r4 = rules \n rule read_value ((counter >= 18) && (counter < 34));\n TRAMresp#(Bit#(1),Bit #(16)) first <- tx.response.get;\n out_data <= out_data + 25;\n \t $display(\"Cycle Number = %d, Value read %h address %h offset %h\",counter, tpl_2(first),out_address,out_offset);\n if (out_data != tpl_2(first))\n fail <= True;\n \t \/\/request <= True;\n endrule\n endrules;\n \n Rules r5 = rules \n rule endofsim (counter == 35);\n \tif (fail)\n \t $display(\"Simulation Fails\");\n \telse\n \t $display(\"Simulation Passes\");\n \t$finish(2'b00);\n endrule\n endrules;\n\n Vector #(4, Rules) my_list = cons(r1, cons(r2, cons(r3, cons(r5,nil))));\n \n addRules (precede (r4, joinRules (my_list)));\n\nendmodule: mkTestbench_MkWrapSTRAM\n\nendpackage: MkWrapSTRAM\n","avg_line_length":29.6063829787,"max_line_length":117,"alphanum_fraction":0.5874955084} {"size":324,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"\ninterface Foo;\n method Action bar;\n method Action baz;\nendinterface\n\nmodule sysIfcIfcWarning(Foo);\n Reg#(Bit#(8)) r();\n mkReg#(0) the_r(r);\n\n method bar;\n action\n r <= r + 1;\n endaction\n endmethod\n\n method baz;\n action\n r <= r + 2;\n endaction\n endmethod\nendmodule\n\n","avg_line_length":13.5,"max_line_length":29,"alphanum_fraction":0.5555555556} {"size":5936,"ext":"bsv","lang":"Bluespec","max_stars_count":40.0,"content":"\/*\n--------------------------------------------------------------------------------------------------------------------------------------------------------\n-- \n-- Copyright (c) 2013,2014 Indian Institute of Technology Madras (IIT Madras)\n-- All rights reserved.\n--\n-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:\n--\n-- 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.\n-- 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and \n-- the following disclaimer in the documentation and\/or other materials provided with the distribution.\n-- 3. Neither the name of IIT Madras nor the names of its contributors may be used to endorse or \n-- promote products derived from this software without specific prior written permission.\n--\n-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. \n-- IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, \n-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; \n-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, \n-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-- \n-------------------------------------------------------------------------------------------------------------------------------------------------------- \n*\/\n\n\npackage TestCaseCommands ;\n\n\nfunction Bit#(512) get_command ( Bit#(64) address_in) ;\n\n\t Bit#(8) opcode \t\t ;\n\t Bit#(2) fuse \t\t\t ;\n\t Bit#(16) command_id \t ;\n\t Bit#(6) reserved0 ;\n\t Bit#(32) nsid\t \t\t ;\n\t Bit#(32)\t reserved1\t\t\t\t;\n\t Bit#(32)\t reserved2\t\t\t;\n\t Bit#(64) mptr \t\t\t ;\n\t Bit#(64) prp1 \t\t\t ;\n\t Bit#(64) prp2 \t\t\t ;\n\t Bit#(32) cdw10 \t\t ;\n\t Bit#(32) cdw11 \t\t ;\n\t Bit#(32) cdw12 \t\t ;\n\t Bit#(32) cdw13 \t\t ;\n\t Bit#(32) cdw14 \t\t ;\n\t Bit#(32) cdw15 \t\t ;\n\n\tcase(address_in) matches\n\t\t0 : begin\t\t\t\t\t\t \/\/ Base Address of SQ 0 \t\t\t\t\t\t\n\t\t\t\t opcode \t= 8'h01\t\t; \/\/ Create I\/O Submission Queue\n\t\t\t\t fuse \t\t= 0\t\t \t; \/\/ No Fuse \n\t\t\t\t command_id = 0 \t\t;\n\t\t\t\t reserved0 \t= 0\t\t\t;\n\t\t\t\t nsid\t \t= 0 \t\t;\n\t\t\t\t reserved1\t= 0\t\t\t;\n\t\t\t\t reserved2\t= 0\t\t\t;\n\t\t\t\t mptr \t\t= 0\t \t\t;\n\t\t\t\t prp1 \t\t= 64'd200\t \t\t;\/\/ Base address of the Q to be created is 200 \n\t\t\t\t prp2 \t\t= 0\t \t\t;\n\t\t\t\t cdw10 \t\t= 32'h0005_0002 ; \/\/ qID is \"2\" .. sizeof Q is 5 ..\n\t\t\t\t cdw11 \t\t= 32'h0001_0000 \t;\/\/ qID of CQ to be used is 1 \n\t\t\t\t cdw12 \t\t= 0 \t\t;\n\t\t\t\t cdw13 \t\t= 0 \t\t;\n\t\t\t\t cdw14 \t\t= 0 \t\t;\n\t\t\t\t cdw15 \t\t= 0 \t\t;\n\t\t\tend\t\n\t\t64 : begin\t\t\n\t\t\t\t opcode = 8'h05\t\t ; \/\/ Create I\/O completion Q command\n\t\t\t\t fuse \t= 0\t\t ;\n\t\t\t\t command_id = 0 ;\n\t\t\t\t reserved0 = 0\t\t;\n\t\t\t\t nsid\t \t= 0 ;\n\t\t\t\t reserved1\t= 0\t\t\t;\n\t\t\t\t reserved2\t= 0\t\t;\n\t\t\t\t mptr \t\t= 0\t ;\n\t\t\t\t prp1 \t\t= 64'd400\t ; \/\/ Base Address of Q to be created\n\t\t\t\t prp2 \t\t= 0\t ;\n\t\t\t\t cdw10 \t\t= 32'h0005_0001 ;\/\/ qID is \"1\" .. sizeof Q is 5 ..\n\t\t\t\t cdw11 \t\t= 5 ; \/\/ Interrupt Vector Number for the CQ is 5 \t\n\t\t\t\t cdw12 \t\t= 0 ;\n\t\t\t\t cdw13 \t\t= 0 ;\n\t\t\t\t cdw14 \t\t= 0 ;\n\t\t\t\t cdw15 \t\t= 0 ;\n\t\t\tend\n\t\t128 : begin\n\t\t\t\t opcode = 8'h08\t\t ; \/\/ ABORT Command \n\t\t\t\t fuse \t= 0\t\t ;\n\t\t\t\t command_id = 0 ;\n\t\t\t\t reserved0 = 0\t\t;\n\t\t\t\t nsid\t \t= 0 ;\n\t\t\t\t reserved1\t= 0\t\t\t;\n\t\t\t\t reserved2\t= 0\t\t;\n\t\t\t\t mptr \t\t= 0\t ;\n\t\t\t\t prp1 \t\t= 0\t ; \n\t\t\t\t prp2 \t\t= 0\t ;\n\t\t\t\t cdw10 \t\t= 32'h0014_0002 ; \/\/ Abort the Command with CQID = 20 and SQID = 2 ... \n\t\t\t\t cdw11 \t\t= 0 ; \t\n\t\t\t\t cdw12 \t\t= 0 ;\n\t\t\t\t cdw13 \t\t= 0 ;\n\t\t\t\t cdw14 \t\t= 0 ;\n\t\t\t\t cdw15 \t\t= 0 ;\n\t\t\tend\n\t\t200 : begin\t\t\t\t\t\t\t\/\/ Base Address of I\/O SQ 2 \n\t\t\t\t opcode = 8'h01\t\t ; \t\/\/ Write Comand \n\t\t\t\t fuse \t= 0\t\t ;\n\t\t\t\t command_id = 'd20 ;\t\t\/\/ Command ID is 20 \n\t\t\t\t reserved0 = 0\t\t;\n\t\t\t\t nsid\t \t= 0 ;\n\t\t\t\t reserved1\t= 0\t\t\t;\n\t\t\t\t reserved2\t= 0\t\t;\n\t\t\t\t mptr \t\t= 0\t ;\n\t\t\t\t prp1 \t\t= 64'd1008\t ; \/\/ Data to be written is in location 1008 in Main Memory \n\t\t\t\t prp2 \t\t= 0\t ;\n\t\t\t\t cdw10 \t\t= 32'd0 ; \/\/ The Logical Block Address is given combinedly by cdw10 and cdw11 .. its 100 here \n\t\t\t\t cdw11 \t\t= 0 ; \t\n\t\t\t\t cdw12 \t\t= 0 ;\n\t\t\t\t cdw13 \t\t= 0 ;\n\t\t\t\t cdw14 \t\t= 0 ;\n\t\t\t\t cdw15 \t\t= 0 ;\n\t\t\tend\n\t\t 264 : begin\t\t\t\t\t\t\/\/ Command in SQ 2 \n\t\t\t\t opcode = 'h02\t\t ;\t\/\/ READ Command\n\t\t\t\t fuse \t= 0\t\t ;\n\t\t\t\t command_id = 'd21 ;\t\t\/\/ Command ID is 21\n\t\t\t\t reserved0 = 0\t\t;\n\t\t\t\t nsid\t \t= 0 ;\n\t\t\t\t reserved1\t = 0\t\t\t;\n\t\t\t\t reserved2\t= 0\t\t;\n\t\t\t\t mptr \t\t= 0\t ;\n\t\t\t\t prp1 \t\t= 'd2008\t ; \/\/ Data read from NAND is to be transfered to memory Location 2008 \n\t\t\t\t prp2 \t\t= 0\t ;\n\t\t\t\t cdw10 \t\t= 32'd0 ;\t\/\/ The Logical Block Address is given Combinedly by cdw10 and cdw11 .. its 100 here \n\t\t\t\t cdw11 \t\t= 0 ;\n\t\t\t\t cdw12 \t\t= 0 ;\n\t\t\t\t cdw13 \t\t= 0 ;\n\t\t\t\t cdw14 \t\t= 0 ;\n\t\t\t\t cdw15 \t\t= 0 ;\n\t\t\tend\n\t\tdefault : begin\n\t\t\t\t opcode = 0\t\t ;\n\t\t\t\t fuse \t= 0\t\t ;\n\t\t\t\t command_id = 0 ;\n\t\t\t\t reserved0 = 0\t\t;\n\t\t\t\t nsid\t \t= 0 ;\n\t\t\t\t reserved1\t = 0\t\t\t;\n\t\t\t\t reserved2\t= 0\t\t;\n\t\t\t\t mptr \t\t= 0\t ;\n\t\t\t\t prp1 \t\t= 0\t ;\n\t\t\t\t prp2 \t\t= 0\t ;\n\t\t\t\t cdw10 \t\t= 0 ;\n\t\t\t\t cdw11 \t\t= 0 ;\n\t\t\t\t cdw12 \t\t= 0 ;\n\t\t\t\t cdw13 \t\t= 0 ;\n\t\t\t\t cdw14 \t\t= 0 ;\n\t\t\t\t cdw15 \t\t= 0 ;\n\t\t\tend\n\tendcase\n\t\n\treturn( { cdw15,cdw14 ,cdw13,cdw12 ,cdw11,cdw10,prp2,prp1,mptr,reserved2 , reserved1,nsid ,command_id,reserved0,fuse ,opcode } ) ;\n\nendfunction\n\nendpackage\n","avg_line_length":36.1951219512,"max_line_length":241,"alphanum_fraction":0.5028638814} {"size":32576,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"\/\/ Copyright (c) 2017 Massachusetts Institute of Technology\n\/\/\n\/\/-\n\/\/ RVFI_DII + CHERI modifications:\n\/\/ Copyright (c) 2020 Jonathan Woodruff\n\/\/ All rights reserved.\n\/\/\n\/\/ This software was developed by SRI International and the University of\n\/\/ Cambridge Computer Laboratory (Department of Computer Science and\n\/\/ Technology) under DARPA contract HR0011-18-C-0016 (\"ECATS\"), as part of the\n\/\/ DARPA SSITH research programme.\n\/\/\n\/\/ This work was supported by NCSC programme grant 4212611\/RFA 15971 (\"SafeBet\").\n\/\/-\n\/\/\n\/\/ Permission is hereby granted, free of charge, to any person\n\/\/ obtaining a copy of this software and associated documentation\n\/\/ files (the \"Software\"), to deal in the Software without\n\/\/ restriction, including without limitation the rights to use, copy,\n\/\/ modify, merge, publish, distribute, sublicense, and\/or sell copies\n\/\/ of the Software, and to permit persons to whom the Software is\n\/\/ furnished to do so, subject to the following conditions:\n\/\/\n\/\/ The above copyright notice and this permission notice shall be\n\/\/ included in all copies or substantial portions of the Software.\n\/\/\n\/\/ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\/\/ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\/\/ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n\/\/ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n\/\/ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n\/\/ ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n\/\/ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n\/\/ SOFTWARE.\n\n`include \"ProcConfig.bsv\"\n\nimport Types::*;\nimport MemoryTypes::*;\nimport Amo::*;\n\nimport Cntrs::*;\nimport Vector::*;\nimport ConfigReg::*;\nimport FIFO::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport CCTypes::*;\nimport ICRqMshr::*;\nimport IPRqMshr::*;\nimport CCPipe::*;\nimport L1Pipe ::*;\nimport FShow::*;\nimport DefaultValue::*;\nimport Fifos::*;\nimport CacheUtils::*;\nimport Performance::*;\nimport LatencyTimer::*;\nimport RandomReplace::*;\n`ifdef PERFORMANCE_MONITORING\nimport PerformanceMonitor::*;\nimport BlueUtils::*;\n`endif\n\nexport ICRqStuck(..);\nexport IPRqStuck(..);\nexport IBank(..);\nexport mkIBank;\n\n\/\/ L1 I$\n\n\/\/ although pRq never appears in dependency chain\n\/\/ we still need pRq MSHR to limit the number of pRq\n\/\/ and thus limit the size of rsToPIndexQ\n\ntypedef struct {\n Addr addr;\n ICRqState state;\n Bool waitP;\n} ICRqStuck deriving(Bits, Eq, FShow);\n\ntypedef IPRqMshrStuck IPRqStuck;\n\ninterface IBank#(\n numeric type supSz, \/\/ superscalar size\n numeric type lgBankNum,\n numeric type wayNum,\n numeric type indexSz,\n numeric type tagSz,\n numeric type cRqNum,\n numeric type pRqNum\n);\n interface ChildCacheToParent#(Bit#(TLog#(wayNum)), void) to_parent;\n interface InstServer#(supSz) to_proc; \/\/ to child, i.e. processor\n \/\/ detect deadlock: only in use when macro CHECK_DEADLOCK is defined\n interface Get#(ICRqStuck) cRqStuck;\n interface Get#(IPRqStuck) pRqStuck;\n \/\/ security: flush\n method Action flush;\n method Bool flush_done;\n \/\/ performance\n method Action setPerfStatus(Bool stats);\n method Data getPerfData(L1IPerfType t);\n`ifdef PERFORMANCE_MONITORING\n method EventsCache events;\n`endif\nendinterface\n\nmodule mkIBank#(\n Bit#(lgBankNum) bankId,\n module#(ICRqMshr#(cRqNum, wayT, tagT, procRqT, resultT)) mkICRqMshrLocal,\n module#(IPRqMshr#(pRqNum)) mkIPRqMshrLocal,\n module#(L1Pipe#(lgBankNum, wayNum, indexT, tagT, cRqIdxT, pRqIdxT)) mkL1Pipeline\n)(\n IBank#(supSz, lgBankNum, wayNum, indexSz, tagSz, cRqNum, pRqNum)\n) provisos(\n Alias#(wayT, Bit#(TLog#(wayNum))),\n Alias#(indexT, Bit#(indexSz)),\n Alias#(tagT, Bit#(tagSz)),\n Alias#(cRqIdxT, Bit#(TLog#(cRqNum))),\n Alias#(pRqIdxT, Bit#(TLog#(pRqNum))),\n Alias#(cacheOwnerT, Maybe#(cRqIdxT)), \/\/ owner cannot be pRq\n Alias#(cacheInfoT, CacheInfo#(tagT, Msi, void, cacheOwnerT, void)),\n Alias#(ramDataT, RamData#(tagT, Msi, void, cacheOwnerT, void, Line)),\n Alias#(procRqT, ProcRqToI),\n Alias#(cRqToPT, CRqMsg#(wayT, void)),\n Alias#(cRsToPT, CRsMsg#(void)),\n Alias#(pRqFromPT, PRqMsg#(void)),\n Alias#(pRsFromPT, PRsMsg#(wayT, void)),\n Alias#(pRqRsFromPT, PRqRsMsg#(wayT, void)),\n Alias#(cRqSlotT, ICRqSlot#(wayT, tagT)), \/\/ cRq MSHR slot\n Alias#(l1CmdT, L1Cmd#(indexT, cRqIdxT, pRqIdxT)),\n Alias#(pipeOutT, PipeOut#(wayT, tagT, Msi, void, cacheOwnerT, void, RandRepInfo, Line, l1CmdT)),\n Mul#(2, supSz, supSzX2),\n Alias#(resultT, Vector#(supSzX2, Maybe#(Instruction16))),\n \/\/ requirements\n FShow#(pipeOutT),\n Add#(tagSz, a__, AddrSz),\n \/\/ make sure: cRqNum <= wayNum\n Add#(cRqNum, b__, wayNum),\n Add#(TAdd#(tagSz, indexSz), TAdd#(lgBankNum, LgLineSzBytes), AddrSz)\n);\n\n Bool verbose = False;\n\n ICRqMshr#(cRqNum, wayT, tagT, procRqT, resultT) cRqMshr <- mkICRqMshrLocal;\n\n IPRqMshr#(pRqNum) pRqMshr <- mkIPRqMshrLocal;\n\n L1Pipe#(lgBankNum, wayNum, indexT, tagT, cRqIdxT, pRqIdxT) pipeline <- mkL1Pipeline;\n\n Fifo#(1, Addr) rqFromCQ <- mkBypassFifo;\n\n Fifo#(2, cRsToPT) rsToPQ <- mkCFFifo;\n Fifo#(2, cRqToPT) rqToPQ <- mkCFFifo;\n Fifo#(2, pRqRsFromPT) fromPQ <- mkCFFifo;\n\n FIFO#(MshrIndex#(cRqIdxT, pRqIdxT)) rsToPIndexQ <- mkSizedFIFO(valueOf(TAdd#(cRqNum, pRqNum)));\n\n FIFO#(cRqIdxT) rqToPIndexQ <- mkSizedFIFO(valueOf(cRqNum));\n \/\/ temp fifo for pipelineResp & sendRsToP (reduce conflict)\n FIFO#(cRqIdxT) rqToPIndexQ_pipelineResp <- mkFIFO;\n FIFO#(cRqIdxT) rqToPIndexQ_sendRsToP <- mkFIFO;\n\n \/\/ index Q to order all in flight cRq for in-order resp\n FIFO#(cRqIdxT) cRqIndexQ <- mkSizedFIFO(valueof(cRqNum));\n\n`ifdef DEBUG_ICACHE\n \/\/ id for each cRq, incremented when each new req comes\n Reg#(Bit#(64)) cRqId <- mkReg(0);\n \/\/ FIFO to signal the id of cRq that is performed\n \/\/ FIFO has 0 cycle latency to match L1 D$ resp latency\n Fifo#(1, DebugICacheResp) cRqDoneQ <- mkBypassFifo;\n`endif\n\n \/\/ security flush\n`ifdef SECURITY\n Reg#(Bool) flushDone <- mkReg(True);\n Reg#(Bool) flushReqStart <- mkReg(False);\n Reg#(Bool) flushReqDone <- mkReg(False);\n Reg#(Bool) flushRespDone <- mkReg(False);\n Reg#(indexT) flushIndex <- mkReg(0);\n Reg#(wayT) flushWay <- mkReg(0);\n`else\n Bool flushDone = True;\n`endif\n\n LatencyTimer#(cRqNum, 10) latTimer <- mkLatencyTimer;\n`ifdef PERF_COUNT\n Reg#(Bool) doStats <- mkConfigReg(False);\n Count#(Data) ldCnt <- mkCount(0);\n Count#(Data) ldMissCnt <- mkCount(0);\n Count#(Data) ldMissLat <- mkCount(0);\n`endif\n`ifdef PERFORMANCE_MONITORING\n Array #(Reg #(EventsCache)) perf_events <- mkDRegOR (2, unpack (0));\n`endif\n function Action incrReqCnt;\n action\n`ifdef PERF_COUNT\n if(doStats) begin\n ldCnt.incr(1);\n end\n`endif\n`ifdef PERFORMANCE_MONITORING\n EventsCache events = unpack (0);\n events.evt_LD = 1;\n perf_events[0] <= events;\n`endif\n noAction;\n endaction\n endfunction\n\n function Action incrMissCnt(cRqIdxT idx);\n action\n let lat <- latTimer.done(idx);\n`ifdef PERF_COUNT\n if(doStats) begin\n ldMissLat.incr(zeroExtend(lat));\n ldMissCnt.incr(1);\n end\n`endif\n`ifdef PERFORMANCE_MONITORING\n EventsCache events = unpack (0);\n events.evt_LD_MISS_LAT = saturating_truncate(lat);\n events.evt_LD_MISS = 1;\n perf_events[1] <= events;\n`endif\n noAction;\n endaction\n endfunction\n\n function tagT getTag(Addr a) = truncateLSB(a);\n\n \/\/ XXX since I$ may be requested by processor constantly\n \/\/ cRq may come at every cycle, so we must make cRq has lower priority than pRq\/pRs\n \/\/ otherwise the whole system may deadlock\/livelock\n \/\/ we stop accepting cRq when we need to flush for security\n rule cRqTransfer(flushDone);\n Addr addr <- toGet(rqFromCQ).get;\n`ifdef DEBUG_ICACHE\n procRqT r = ProcRqToI {addr: addr, id: cRqId};\n cRqId <= cRqId + 1;\n`else\n procRqT r = ProcRqToI {addr: addr};\n`endif\n cRqIdxT n <- cRqMshr.getEmptyEntryInit(r);\n \/\/ send to pipeline\n pipeline.send(CRq (L1PipeRqIn {\n addr: r.addr,\n mshrIdx: n\n }));\n \/\/ enq to indexQ for in order resp\n cRqIndexQ.enq(n);\n \/\/ performance counter: cRq type\n incrReqCnt;\n if (verbose)\n $display(\"%t I %m cRqTransfer: \", $time,\n fshow(n), \" ; \",\n fshow(r)\n );\n endrule\n\n \/\/ this descending urgency is necessary to avoid deadlock\/livelock\n (* descending_urgency = \"pRqTransfer, cRqTransfer\" *)\n rule pRqTransfer(fromPQ.first matches tagged PRq .req);\n fromPQ.deq;\n pRqIdxT n <- pRqMshr.getEmptyEntryInit(req);\n \/\/ send to pipeline\n pipeline.send(PRq (L1PipeRqIn {\n addr: req.addr,\n mshrIdx: n\n }));\n if (verbose)\n $display(\"%t I %m pRqTransfer: \", $time,\n fshow(n), \" ; \",\n fshow(req)\n );\n endrule\n\n \/\/ this descending urgency is necessary to avoid deadlock\/livelock\n (* descending_urgency = \"pRsTransfer, cRqTransfer\" *)\n rule pRsTransfer(fromPQ.first matches tagged PRs .resp);\n fromPQ.deq;\n pipeline.send(PRs (L1PipePRsIn {\n addr: resp.addr,\n toState: S,\n data: resp.data,\n way: resp.id\n }));\n if (verbose)\n $display(\"%t I %m pRsTransfer: \", $time, fshow(resp));\n doAssert(resp.toState == S && isValid(resp.data), \"I$ must upgrade to S with data\");\n endrule\n\n`ifdef SECURITY\n \/\/ start flush when cRq MSHR is empty\n rule startFlushReq(!flushDone && !flushReqStart && cRqMshr.emptyForFlush);\n flushReqStart <= True;\n endrule\n\n (* descending_urgency = \"pRsTransfer, flushTransfer\" *)\n (* descending_urgency = \"pRqTransfer, flushTransfer\" *)\n rule flushTransfer(!flushDone && flushReqStart && !flushReqDone);\n \/\/ We allocate a pRq MSHR entry for 2 reasons:\n \/\/ (1) reuse the pRq logic to send resp to parent\n \/\/ (2) control the number of downgrade resp to avoid stalling the cache\n \/\/ pipeline\n pRqIdxT n <- pRqMshr.getEmptyEntryInit(PRqMsg {\n addr: ?,\n toState: I,\n child: ?\n });\n pipeline.send(Flush (L1PipeFlushIn {\n index: flushIndex,\n way: flushWay,\n mshrIdx: n\n }));\n \/\/ increment flush index\/way\n if (flushWay < fromInteger(valueof(wayNum) - 1)) begin\n flushWay <= flushWay + 1;\n end\n else begin\n flushWay <= 0;\n flushIndex <= flushIndex + 1; \/\/ index num should be power of 2\n if (flushIndex == maxBound) begin\n flushReqDone <= True;\n end\n end\n if (verbose)\n $display(\"%t I %m flushTransfer: \", $time, fshow(n), \" ; \",\n fshow(flushIndex), \" ; \", fshow(flushWay));\n endrule\n`endif\n\n rule sendRsToP_cRq(rsToPIndexQ.first matches tagged CRq .n);\n rsToPIndexQ.deq;\n \/\/ get cRq replacement info\n procRqT req = cRqMshr.sendRsToP_cRq.getRq(n);\n cRqSlotT slot = cRqMshr.sendRsToP_cRq.getSlot(n);\n \/\/ send resp to parent\n cRsToPT resp = CRsMsg {\n addr: {slot.repTag, truncate(req.addr)}, \/\/ get bank id & index from req\n toState: I,\n data: Invalid, \/\/ I$ never downgrade with data to writeback\n child: ?\n };\n rsToPQ.enq(resp);\n \/\/ req parent for upgrade now\n \/\/ (prevent parent resp from coming to release MSHR entry before replace resp is sent)\n rqToPIndexQ_sendRsToP.enq(n);\n if (verbose)\n $display(\"%t I %m sendRsToP: \", $time,\n fshow(rsToPIndexQ.first),\" ; \",\n fshow(req), \" ; \",\n fshow(slot), \" ; \",\n fshow(resp)\n );\n endrule\n\n rule sendRsToP_pRq(rsToPIndexQ.first matches tagged PRq .n);\n rsToPIndexQ.deq;\n \/\/ get pRq info & send resp & release MSHR entry\n pRqFromPT req = pRqMshr.sendRsToP_pRq.getRq(n);\n cRsToPT resp = CRsMsg {\n addr: req.addr,\n toState: I, \/\/ I$ must downgrade to I\n data: Invalid, \/\/ I$ never downgrade with data to writeback\n child: ?\n };\n rsToPQ.enq(resp);\n pRqMshr.sendRsToP_pRq.releaseEntry(n); \/\/ mshr entry released\n if (verbose)\n $display(\"%t I %m sendRsToP: \", $time,\n fshow(rsToPIndexQ.first), \" ; \",\n fshow(req), \" ; \",\n fshow(resp)\n );\n doAssert(req.toState == I, \"I$ only has downgrade req to I\");\n endrule\n\n rule sendRqToP;\n rqToPIndexQ.deq;\n cRqIdxT n = rqToPIndexQ.first;\n procRqT req = cRqMshr.sendRqToP.getRq(n);\n cRqSlotT slot = cRqMshr.sendRqToP.getSlot(n);\n cRqToPT cRqToP = CRqMsg {\n addr: req.addr,\n fromState: I, \/\/ I$ upgrade from I\n toState: S, \/\/ I$ upgrade to S\n canUpToE: False,\n id: slot.way,\n child: ?\n };\n rqToPQ.enq(cRqToP);\n if (verbose)\n $display(\"%t I %m sendRqToP: \", $time,\n fshow(n), \" ; \",\n fshow(req), \" ; \",\n fshow(slot), \" ; \",\n fshow(cRqToP)\n );\n \/\/ performance counter: start miss timer\n latTimer.start(n);\n endrule\n\n \/\/ last stage of pipeline: process req\n\n \/\/ XXX: in L1, pRq cannot exist in dependency chain\n \/\/ because there are only two ways to include pRq into chain\n \/\/ (1) append to a cRq that could finish, but such cRq must have been directly reponded\n \/\/ (2) overtake cRq (S->M), but such downgrade can be done instaneously without the need of chaining\n \/\/ (this cannot happen in I$)\n \/\/ Thus, dependency chain in L1 only contains cRq\n\n \/\/ pipeline outputs\n pipeOutT pipeOut = pipeline.first;\n ramDataT ram = pipeOut.ram;\n \/\/ get proc req to select from cRqMshr\n procRqT pipeOutCRq = cRqMshr.pipelineResp.getRq(\n case(pipeOut.cmd) matches\n tagged L1CRq .n: (n);\n default: (fromMaybe(0, ram.info.owner)); \/\/ L1PRs\n endcase\n );\n\n \/\/ function to get superscaler inst read result\n function resultT readInst(Line line, Addr addr);\n Vector#(LineSzInst, Instruction16) instVec = unpack(pack(line.data));\n \/\/ the start offset for reading inst\n LineInstOffset startSel = getLineInstOffset(addr);\n \/\/ calculate the maximum inst count that could be read from line\n LineInstOffset maxCntMinusOne = maxBound - startSel;\n \/\/ read inst superscalaer\n resultT val = ?;\n for(Integer i = 0; i < valueof(supSzX2); i = i+1) begin\n if(fromInteger(i) <= maxCntMinusOne) begin\n LineInstOffset sel = startSel + fromInteger(i);\n val[i] = Valid (instVec[sel]);\n end\n else begin\n val[i] = Invalid;\n end\n end\n return val;\n endfunction\n\n \/\/ function to process cRq hit (MSHR slot may have garbage)\n function Action cRqHit(cRqIdxT n, procRqT req);\n action\n if (verbose)\n $display(\"%t I %m pipelineResp: Hit func: \", $time,\n fshow(n), \" ; \",\n fshow(req)\n );\n \/\/ check tag & cs: even this function is called by pRs, tag should match,\n \/\/ because tag is written into cache before sending req to parent\n doAssert(ram.info.tag == getTag(req.addr) && ram.info.cs == S,\n \"cRqHit but tag or cs incorrect\"\n );\n \/\/ deq pipeline or swap in successor\n Maybe#(cRqIdxT) succ = cRqMshr.pipelineResp.getSucc(n);\n pipeline.deqWrite(succ, RamData {\n info: CacheInfo {\n tag: getTag(req.addr), \/\/ should be the same as original tag\n cs: ram.info.cs, \/\/ use cs in ram\n dir: ?,\n owner: succ,\n other: ?\n },\n line: ram.line\n }, True); \/\/ hit, so update rep info\n \/\/ process req to get superscalar inst read results\n \/\/ set MSHR entry as Done & save inst results\n let instResult = readInst(ram.line, req.addr);\n cRqMshr.pipelineResp.setResult(n, instResult);\n cRqMshr.pipelineResp.setStateSlot(n, Done, ?);\n if (verbose)\n $display(\"%t I %m pipelineResp: Hit func: update ram: \", $time,\n fshow(succ), \" ; \", fshow(instResult)\n );\n`ifdef DEBUG_ICACHE\n \/\/ signal that this req is performed\n cRqDoneQ.enq(DebugICacheResp {\n id: req.id,\n line: ram.line\n });\n`endif\n endaction\n endfunction\n\n rule pipelineResp_cRq(pipeOut.cmd matches tagged L1CRq .n);\n if (verbose)\n $display(\"%t I %m pipelineResp: \", $time, fshow(pipeOut));\n\n procRqT procRq = pipeOutCRq;\n if (verbose)\n $display(\"%t I %m pipelineResp: cRq: \", $time, fshow(n), \" ; \", fshow(procRq));\n\n \/\/ find end of dependency chain\n Maybe#(cRqIdxT) cRqEOC = cRqMshr.pipelineResp.searchEndOfChain(procRq.addr);\n\n \/\/ function to process cRq miss without replacement (MSHR slot may have garbage)\n function Action cRqMissNoReplacement;\n action\n cRqSlotT cSlot = cRqMshr.pipelineResp.getSlot(n);\n \/\/ it is impossible in L1 to have slot.waitP == True in this function\n \/\/ because cRq is not set to Depend when pRq invalidates it (pRq just directly resp)\n \/\/ and this func is only called when cs < S (otherwise will hit)\n \/\/ because L1 has no children to wait for\n doAssert(!cSlot.waitP && ram.info.cs == I, \"waitP must be false and cs must be I\");\n \/\/ Thus we must send req to parent\n \/\/ XXX first send to a temp indexQ to avoid conflict, then merge to rqToPIndexQ later\n rqToPIndexQ_pipelineResp.enq(n);\n \/\/ update mshr\n cRqMshr.pipelineResp.setStateSlot(n, WaitSt, ICRqSlot {\n way: pipeOut.way, \/\/ use way from pipeline\n repTag: ?, \/\/ no replacement\n waitP: True \/\/ must fetch from parent\n });\n \/\/ deq pipeline & set owner, tag\n pipeline.deqWrite(Invalid, RamData {\n info: CacheInfo {\n tag: getTag(procRq.addr), \/\/ tag may be garbage if cs == I\n cs: ram.info.cs,\n dir: ?,\n owner: Valid (n), \/\/ owner is req itself\n other: ?\n },\n line: ram.line\n }, False);\n endaction\n endfunction\n\n \/\/ function to do replacement for cRq\n function Action cRqReplacement;\n action\n \/\/ deq pipeline\n pipeline.deqWrite(Invalid, RamData {\n info: CacheInfo {\n tag: getTag(procRq.addr), \/\/ set to req tag (old tag is replaced right now)\n cs: I,\n dir: ?,\n owner: Valid (n), \/\/ owner is req itself\n other: ?\n },\n line: ? \/\/ data is no longer used\n }, False);\n doAssert(ram.info.cs == S, \"I$ replacement only replace S line\");\n \/\/ update MSHR to save replaced tag\n \/\/ although we send req to parent later (when resp to parent is sent)\n \/\/ we set state to WaitSt now, since the req to parent is already on schedule\n cRqMshr.pipelineResp.setStateSlot(n, WaitSt, ICRqSlot {\n way: pipeOut.way, \/\/ use way from pipeline\n repTag: ram.info.tag, \/\/ tag being replaced for sending rs to parent\n waitP: True\n });\n \/\/ send replacement resp to parent\n rsToPIndexQ.enq(CRq (n));\n endaction\n endfunction\n\n \/\/ function to set cRq to Depend, and make no further change to cache\n function Action cRqSetDepNoCacheChange;\n action\n cRqMshr.pipelineResp.setStateSlot(n, Depend, defaultValue);\n pipeline.deqWrite(Invalid, pipeOut.ram, False);\n endaction\n endfunction\n\n if(ram.info.owner matches tagged Valid .cOwner) begin\n if(cOwner != n) begin\n \/\/ owner is another cRq, so must just go through tag match\n \/\/ tag match must be hit (because replacement algo won't give a way with owner)\n doAssert(ram.info.cs == S && ram.info.tag == getTag(procRq.addr),\n \"cRq should hit in tag match\"\n );\n \/\/ should be added to a cRq in dependency chain & deq from pipeline\n doAssert(isValid(cRqEOC), \"cRq hit on another cRq, cRqEOC must be true\");\n cRqMshr.pipelineResp.setSucc(fromMaybe(?, cRqEOC), Valid (n));\n cRqSetDepNoCacheChange;\n if (verbose)\n $display(\"%t I %m pipelineResp: cRq: own by other cRq \", $time,\n fshow(cOwner), \", depend on cRq \", fshow(cRqEOC)\n );\n end\n else begin\n \/\/ owner is myself, so must be swapped in\n \/\/ tag should match, since always swapped in by cRq, cs = S\n doAssert(ram.info.tag == getTag(procRq.addr) && ram.info.cs == S,\n \"cRq swapped in by previous cRq, tag must match & cs = S\"\n );\n \/\/ Hit\n if (verbose)\n $display(\"%t I %m pipelineResp: cRq: own by itself, hit\", $time);\n cRqHit(n, procRq);\n end\n end\n else begin\n \/\/ cache has no owner, cRq must just go through tag match\n \/\/ check for cRqEOC to append to dependency chain\n if(cRqEOC matches tagged Valid .k) begin\n if (verbose)\n $display(\"%t I %m pipelineResp: cRq: no owner, depend on cRq \", $time, fshow(k));\n cRqMshr.pipelineResp.setSucc(k, Valid (n));\n cRqSetDepNoCacheChange;\n end\n else if(ram.info.cs == I || ram.info.tag == getTag(procRq.addr)) begin\n \/\/ No Replacement necessary\n if(ram.info.cs > I) begin\n if (verbose)\n $display(\"%t I %m pipelineResp: cRq: no owner, hit\", $time);\n cRqHit(n, procRq);\n end\n else begin\n if (verbose)\n $display(\"%t I %m pipelineResp: cRq: no owner, miss no replace\", $time);\n cRqMissNoReplacement;\n end\n end\n else begin\n if (verbose)\n $display(\"%t I %m pipelineResp: cRq: no owner, replace\", $time);\n cRqReplacement;\n end\n end\n endrule\n\n rule pipelineResp_pRs(pipeOut.cmd == L1PRs);\n if (verbose) begin\n $display(\"%t I %m pipelineResp: \", $time, fshow(pipeOut));\n $display(\"%t I %m pipelineResp: pRs: \", $time);\n end\n\n if(ram.info.owner matches tagged Valid .cOwner) begin\n procRqT procRq = pipeOutCRq;\n doAssert(ram.info.cs == S && ram.info.tag == getTag(procRq.addr),\n \"pRs must be a hit\"\n );\n cRqHit(cOwner, procRq);\n \/\/ performance counter: miss cRq\n incrMissCnt(cOwner);\n end\n else begin\n doAssert(False, (\"pRs owner must match some cRq\"));\n end\n endrule\n\n rule pipelineResp_pRq(pipeOut.cmd matches tagged L1PRq .n);\n pRqFromPT pRq = pRqMshr.pipelineResp.getRq(n);\n if (verbose)\n $display(\"%t I %m pipelineResp: pRq: \", $time, fshow(n), \" ; \", fshow(pRq));\n\n doAssert(pRq.toState == I, \"I$ pRq only downgrade to I\");\n\n \/\/ pRq is never in dependency chain, so it is never swapped in\n \/\/ pRq must go through tag match, which either returns a tag matched way or asserts pRqMiss\n \/\/ In I$ a tag matched way should always be processed since pRq always downgrades to I\n \/\/ pRq is always directly handled: either dropped or Done\n\n if(pipeOut.pRqMiss) begin\n if (verbose)\n $display(\"%t I %m pipelineResp: pRq: drop\", $time);\n \/\/ pRq can be directly dropped, no successor (since just go through pipeline)\n pRqMshr.pipelineResp.releaseEntry(n);\n pipeline.deqWrite(Invalid, pipeOut.ram, False);\n end\n else begin\n if (verbose)\n $display(\"%t I %m pipelineResp: pRq: valid process\", $time);\n \/\/ should process pRq\n doAssert(ram.info.cs == S && pRq.toState == I && ram.info.tag == getTag(pRq.addr),\n \"pRq should be processed\"\n );\n \/\/ line cannot be owned, because\n \/\/ (1) pRq never own cache line\n \/\/ (2) if owned by cRq, cRq would have hit and released ownership\n doAssert(ram.info.owner == Invalid, \"pRq cannot hit on line owned by anyone\");\n \/\/ write ram: set cs to I\n pipeline.deqWrite(Invalid, RamData {\n info: CacheInfo {\n tag: ram.info.tag,\n cs: I, \/\/ I$ is always downgraded by pRq to I\n dir: ?,\n owner: Invalid, \/\/ no successor\n other: ?\n },\n line: ? \/\/ line is not useful\n }, False);\n \/\/ pRq is done\n pRqMshr.pipelineResp.setDone(n);\n \/\/ send resp to parent\n rsToPIndexQ.enq(PRq (n));\n end\n endrule\n\n`ifdef SECURITY\n rule pipelineResp_flush(\n !flushDone &&& !flushRespDone &&&\n pipeOut.cmd matches tagged L1Flush .flush\n );\n pRqIdxT n = flush.mshrIdx;\n if (verbose)\n $display(\"%t I %m pipelineResp: flush: \", $time, fshow(flush));\n\n \/\/ During flush, cRq MSHR is empty, so cache line cannot have owner\n doAssert(ram.info.owner == Invalid, \"flushing line cannot have owner\");\n\n \/\/ flush always goes through cache pipeline, and is directly handled\n \/\/ here: either dropped or Done\n if(ram.info.cs == I) begin\n if (verbose)\n $display(\"%t I %m pipelineResp: flush: drop\", $time);\n \/\/ flush can be directly dropped\n pRqMshr.pipelineResp.releaseEntry(n);\n end\n else begin\n if (verbose)\n $display(\"%t I %m pipelineResp: flush: valid process\", $time);\n pRqMshr.pipelineResp.setDone(n);\n rsToPIndexQ.enq(PRq (n));\n \/\/ record the flushed addr in MSHR so that sendRsToP rule knows\n \/\/ which addr is invalidated\n Bit#(LgLineSzBytes) offset = 0;\n Addr addr = {ram.info.tag, flush.index, bankId, offset};\n pRqMshr.pipelineResp.setFlushAddr(n, addr);\n end\n\n \/\/ always clear the cache line\n pipeline.deqWrite(Invalid, RamData {\n info: CacheInfo {\n tag: ?,\n cs: I, \/\/ downgraded to I\n dir: ?,\n owner: Invalid, \/\/ no successor\n other: ?\n },\n line: ?\n }, False);\n\n \/\/ check if we have finished all flush\n if (flush.index == maxBound &&\n pipeOut.way == fromInteger(valueof(wayNum) - 1)) begin\n flushRespDone <= True;\n end\n endrule\n\n rule completeFlush(!flushDone && flushReqStart && flushReqDone && flushRespDone);\n flushDone <= True;\n flushReqStart <= False;\n flushReqDone <= False;\n flushRespDone <= False;\n endrule\n`endif\n\n \/\/ merge rq to parent index into indexQ\n rule rqIndexFromPipelineResp;\n let n <- toGet(rqToPIndexQ_pipelineResp).get;\n rqToPIndexQ.enq(n);\n endrule\n\n (* descending_urgency = \"rqIndexFromPipelineResp, rqIndexFromSendRsToP\" *)\n rule rqIndexFromSendRsToP;\n let n <- toGet(rqToPIndexQ_sendRsToP).get;\n rqToPIndexQ.enq(n);\n endrule\n\n interface ChildCacheToParent to_parent;\n interface rsToP = toFifoDeq(rsToPQ);\n interface rqToP = toFifoDeq(rqToPQ);\n interface fromP = toFifoEnq(fromPQ);\n endinterface\n\n interface InstServer to_proc;\n interface Put req;\n method Action put(Addr addr);\n rqFromCQ.enq(addr);\n endmethod\n endinterface\n interface Get resp;\n method ActionValue#(resultT) get if(\n cRqMshr.sendRsToC.getResult(cRqIndexQ.first) matches tagged Valid .inst\n );\n cRqIndexQ.deq;\n cRqMshr.sendRsToC.releaseEntry(cRqIndexQ.first); \/\/ release MSHR entry\n if (verbose)\n $display(\"%t I %m sendRsToC: \", $time,\n fshow(cRqIndexQ.first), \" ; \",\n fshow(inst)\n );\n return inst;\n endmethod\n endinterface\n`ifdef DEBUG_ICACHE\n interface done = toGet(cRqDoneQ);\n`endif\n endinterface\n\n interface Get cRqStuck;\n method ActionValue#(ICRqStuck) get;\n let s <- cRqMshr.stuck.get;\n return ICRqStuck {\n addr: s.req.addr,\n state: s.state,\n waitP: s.waitP\n };\n endmethod\n endinterface\n\n interface pRqStuck = pRqMshr.stuck;\n\n`ifdef SECURITY\n method Action flush if(flushDone);\n flushDone <= False;\n endmethod\n method flush_done = flushDone._read;\n`else\n method flush = noAction;\n method flush_done = True;\n`endif\n\n method Action setPerfStatus(Bool stats);\n`ifdef PERF_COUNT\n doStats <= stats;\n`else\n noAction;\n`endif\n endmethod\n\n method Data getPerfData(L1IPerfType t);\n return (case(t)\n`ifdef PERF_COUNT\n L1ILdCnt: ldCnt;\n L1ILdMissCnt: ldMissCnt;\n L1ILdMissLat: ldMissLat;\n`endif\n default: 0;\n endcase);\n endmethod\n`ifdef PERFORMANCE_MONITORING\n method EventsCache events = perf_events[0];\n`endif\nendmodule\n\n\n\/\/ Scheduling note\n\n\/\/ cRqTransfer (toC.req.put): write new cRq MSHR entry, cRqMshr.getEmptyEntry\n\n\/\/ pRqTransfer: write new pRq MSHR entry, pRqMshr.getEmptyEntry\n\n\/\/ pRsTransfer: -\n\n\/\/ sendRsToC (toC.resp.get): read cRq MSHR result, releaseEntry\n\n\/\/ sendRsToP_cRq: read cRq MSHR req\/slot that is replacing\n\n\/\/ sendRsToP_pRq: read pRq MSHR entry that is responding, pRqMshr.releaseEntry\n\n\/\/ sendRqToP: read cRq MSHR req\/slot that is requesting parent\n\n\/\/ pipelineResp_cRq:\n\/\/ -- read cRq MSHR req\/state\/slot currently processed\n\/\/ -- write cRq MSHR state\/slot\/result currently processed\n\/\/ -- write succ of some existing cRq MSHR entry (in WaitNewTag or WaitSt)\n\/\/ -- read all state\/req\/succ in cRq MSHR entry (searchEOC)\n\/\/ -- not affected by write in cRqTransfer (state change is Empty->Init)\n\/\/ -- not affected by write in sendRsC (state change is Done->Empty)\n\n\/\/ pipelineResp_pRs:\n\/\/ -- read cRq MSHR req\/succ, write cRq MSHR state\/slot\/result\n\n\/\/ pipelineResp_pRq:\n\/\/ -- r\/w pRq MSHR entry, pRqMshr.releaseEntry\n\n\/\/ ---- conflict analysis ----\n\n\/\/ XXXTransfer is conflict with each other\n\/\/ Impl of getEmptyEntry and releaseEntry ensures that they are not on the same entry (e.g. cRqTransfer v.s. sendRsToC)\n\/\/ XXXTransfer should operate on different cRq\/pRq from other rules\n\n\/\/ sendRsToC is ordered after pipelineResp to save 1 cycle in I$ latency\n\n\/\/ sendRqToP and sendRsToP_cRq are read only\n\n\/\/ sendRsToP_pRq is operating on different pRq from pipelineResp_pRq (since we use CF index FIFO)\n\n\/\/ ---- conclusion ----\n\n\/\/ rules\/methods are operating on different MSHR entries, except pipelineResp v.s. sendRsToC\n\n\/\/ we have 5 ports from cRq MSHR\n\/\/ 1. cRqTransfer\n\/\/ 2. sendRsToC\n\/\/ 3. sendRsToP_cRq\n\/\/ 4. sendRqToP\n\/\/ 5. pipelineResp\n\n\/\/ we have 3 ports from pRq MSHR\n\/\/ 1. pRqTransfer\n\/\/ 2. sendRsToP_pRq\n\/\/ 3. pipelineResp\n\n\/\/ safe version: use EHR ports\n\/\/ sendRsToP_cRq\/sendRqToP\/pipelineResp < sendRsToC < cRqTransfer\n\/\/ pipelineResp < sendRsToP_pRq < pRqTransfer\n\/\/ (note there is no bypass path from pipelineResp to sendRsToP_pRq since sendRsToP_pRq only reads pRq)\n\n\/\/ unsafe version: all reads read the original reg value, except sendRsToC, which should bypass from pipelineResp\n\/\/ all writes are cononicalized. NOTE: writes of sendRsToC should be after pipelineResp\n\/\/ we maintain the logical ordering in safe version\n","avg_line_length":35.7192982456,"max_line_length":119,"alphanum_fraction":0.5963285855} {"size":7982,"ext":"bsv","lang":"Bluespec","max_stars_count":1.0,"content":"\/\/ Copyright 2009-2010 Bluespec, Inc. All rights reserved.\n\/\/ $Revision$\n\/\/ $Date$\n\npackage ModuleContext;\n\nimport ModuleContextCore::*;\nimport HList::*;\nimport Vector::*;\n\nexport ModuleContextCore::*;\nexport ModuleContext::*;\n\n\/\/typedef 4 CLOCKCONTEXTSIZE;\ntypedef 9 CLOCKCONTEXTSIZE;\n\ntypeclass Context#(type mc1, type c2);\n module [mc1] getContext(c2) provisos (IsModule#(mc1, a));\n module [mc1] putContext#(c2 s)(Empty) provisos (IsModule#(mc1, a));\nendtypeclass\n\ninstance Context#(Module, void);\n module [Module] getContext(st1);\n return ?;\n endmodule\n module [Module] putContext#(void c)(Empty);\n endmodule\nendinstance\n\ninstance Context#(ModuleContext#(st1), st1);\n module [ModuleContext#(st1)] getContext(st1);\n let c <- getCompleteContext();\n return c;\n endmodule\n module [ModuleContext#(st1)] putContext#(st1 c1)(Empty);\n putCompleteContext(c1);\n endmodule\nendinstance\n\ninstance Context#(ModuleContext#(st1), st2)\n provisos (Gettable#(st1, st2));\n module [ModuleContext#(st1)] getContext(st2);\n let c <- getCompleteContext();\n return getIt(c);\n endmodule\n module [ModuleContext#(st1)] putContext#(st2 c2)(Empty);\n let c <- getCompleteContext();\n putCompleteContext(putIt(c, c2));\n endmodule\nendinstance\n\n\/\/ ---\n\nmodule [mc1] applyToContext#(function c2 f(c2 c))(Empty)\n provisos (IsModule#(mc1, a), Context#(mc1, c2));\n\n c2 x <- getContext();\n putContext(f(x));\nendmodule\n\nmodule [mc1] applyToContextM#(function module#(c2) m(c2 c))(Empty)\n provisos (IsModule#(mc1, a), Context#(mc1, c2));\n\n c2 x <- getContext();\n c2 y <- m(x);\n putContext(y);\nendmodule\n\n\/\/ ======\n\ntypedef struct {\n Vector#(n, Clock) clks;\n Vector#(n, Reset) rsts;\n\t\t} ClockContextP#(numeric type n);\n\nClockContextP#(n) initClockContext = ClockContextP {\n clks: replicate(noClock), rsts: replicate(noReset) };\n\ntypedef ClockContextP#(CLOCKCONTEXTSIZE) ClockContext;\ntypedef Empty ClockContextIfc;\ntypedef ModuleContext#(HList1#(ClockContext)) ClockModule;\n\nmodule mkInitialClockContextWithClocks#(Vector#(CLOCKCONTEXTSIZE, Clock) cs,\n\t\t\t\t\tVector#(CLOCKCONTEXTSIZE, Reset) rs)(ClockContext);\n return ClockContextP {clks: cs, rsts: rs };\nendmodule\n\n\/\/ ======\n\ntypeclass Expose#(type c, type ifc, numeric type n)\n dependencies (c determines (ifc, n));\n module unburyContext#(c x)(ifc);\n return error(\"unburyContext not defined for some typeclass\");\n endmodule\n module unburyContextWithClocks#(c x, ClockContextP#(n) cc)(ifc);\n (*hide*)\n let _ifc <- unburyContext(x);\n return _ifc;\n endmodule\nendtypeclass\n\ninstance Expose#(HList1#(ct1), ifc1, n)\n provisos (Expose#(ct1,ifc1,n));\n\n module unburyContext#(HList1#(ct1) c1)(ifc1);\n (*hide_all*) ifc1 _i1 <- unburyContext(hHead(c1));\n return _i1;\n endmodule\n module unburyContextWithClocks#(HList1#(ct1) c1, ClockContextP#(n) cc)(ifc1);\n (*hide_all*) ifc1 _i1 <- unburyContextWithClocks(hHead(c1), cc);\n return _i1;\n endmodule\nendinstance\n\ninstance Expose#(HCons#(c1,c2), Tuple2#(ifc1,ifc2), n)\n provisos (Expose#(c1,ifc1,n), Expose#(c2,ifc2,n));\n\n module unburyContext#(HCons#(c1,c2) c12)(Tuple2#(ifc1,ifc2));\n (*hide_all*) ifc1 _i1 <- unburyContext(hHead(c12));\n (*hide_all*) ifc2 _i2 <- unburyContext(hTail(c12));\n return tuple2(_i1, _i2);\n endmodule\n module unburyContextWithClocks#(HCons#(c1,c2) c12, ClockContextP#(n) cc)(Tuple2#(ifc1,ifc2));\n (*hide_all*) ifc1 _i1 <- unburyContextWithClocks(hHead(c12), cc);\n (*hide_all*) ifc2 _i2 <- unburyContextWithClocks(hTail(c12), cc);\n return tuple2(_i1, _i2);\n endmodule\nendinstance\n\ninstance Expose#(ClockContextP#(n), Empty, n);\n module unburyContext#(ClockContextP#(n) x)();\n endmodule\n module unburyContextWithClocks#(ClockContextP#(n) x, ClockContextP#(m) cc)();\n endmodule\nendinstance\n\n\/\/ ====\n\ntypeclass Hide#(type mc, type ifc);\n module [mc] reburyContext#(ifc i)(Empty);\nendtypeclass\n\ninstance Hide#(mc, Empty)\n provisos (IsModule#(mc, a));\n module [mc] reburyContext#(Empty i)(Empty);\n endmodule\nendinstance\n\ninstance Hide#(mc, Tuple2#(ifc1,ifc2))\n provisos (IsModule#(mc, a),\n\t Hide#(mc,ifc1), Hide#(mc,ifc2));\n\n module [mc] reburyContext#(Tuple2#(ifc1,ifc2) i12)(Empty);\n match {.x1, .x2} = i12;\n reburyContext(x1);\n reburyContext(x2);\n endmodule\nendinstance\n\n\/\/ ====\n\ntypeclass ContextRun#(type m, type c1, type ctx2)\n dependencies ((m, c1) determines ctx2);\n module [m] runWithContext #(c1 initState, ModuleContext#(ctx2, ifcType) mkI)\n (Tuple2#(c1, ifcType));\nendtypeclass\n\ntypeclass ContextsRun#(type m, type c1, type ctx2)\n dependencies ((m, c1) determines ctx2);\n module [m] runWithContexts#(c1 initState, ModuleContext#(ctx2, ifcType) mkI)\n\t(Tuple2#(c1, ifcType));\nendtypeclass\n\ninstance ContextRun#(ModuleContext#(ctx), c1, HCons#(c1,ctx));\n module [ModuleContext#(ctx)] runWithContext#(c1 initState,\n\t\t\t\t\t ModuleContext#(HCons#(c1, ctx), ifcType) mkI)\n (Tuple2#(c1, ifcType));\n\n ctx c0 <- getContext();\n (*hide*)\n Tuple2#(HCons#(c1, ctx), ifcType) _res <-\n liftModule(runWithCompleteContext(hCons(initState, c0), mkI));\n match {.ctx_fin, .ifc} = _res;\n putContext(hTail(ctx_fin));\n return tuple2(hHead(ctx_fin), ifc);\n endmodule\nendinstance\n\ninstance ContextsRun#(ModuleContext#(ctx), c1, ctx2)\n provisos (HAppend#(c1, ctx, ctx2),\n\t HSplit# (ctx2, c1, ctx));\n module [ModuleContext#(ctx)] runWithContexts#(c1 initState,\n\t\t\t\t\t\t ModuleContext#(ctx2, ifcType) mkI)\n (Tuple2#(c1, ifcType));\n\n ctx c0 <- getContext();\n (*hide*)\n Tuple2#(ctx2, ifcType) _res <-\n liftModule(runWithCompleteContext(hAppend(initState, c0), mkI));\n match {.c1ctx_fin, .ifc} = _res;\n Tuple2#(c1, ctx) c1ctx= hSplit(c1ctx_fin);\n match {.c1_fin, .ctx_fin} = c1ctx;\n putContext(ctx_fin);\n return tuple2(c1_fin, ifc);\n endmodule\nendinstance\n\ninstance ContextRun#(Module, c1, c1);\n module [Module] runWithContext#(c1 initState,\n\t\t\t\t ModuleContext#(c1, ifcType) mkI)\n (Tuple2#(c1, ifcType));\n\n (*hide*)\n Tuple2#(c1, ifcType) _res <-\n liftModule(runWithCompleteContext(initState, mkI));\n return _res;\n endmodule\nendinstance\n\n\ninstance ContextsRun#(Module, c1, c1);\n module [Module] runWithContexts#(c1 initState,\n\t\t\t\t ModuleContext#(c1, ifcType) mkI)\n (Tuple2#(c1, ifcType));\n\n (*hide*)\n Tuple2#(c1, ifcType) _res <-\n liftModule(runWithCompleteContext(initState, mkI));\n return _res;\n endmodule\nendinstance\n\n\n\/\/ ====\n\nmodule [Module] unbury#(c1 initState,\n\t\t\tModuleContext#(c1, ifcType) mkM)(Tuple2#(ifc, ifcType))\n provisos (Expose#(c1,ifc,n));\n\n (*hide*)\n Tuple2#(c1, ifcType) ci <- runWithCompleteContext(initState, mkM);\n match {.c, .i} = ci;\n (*hide*)\n ifc i2 <- unburyContext(c);\n return tuple2(i2, i);\nendmodule\n\nmodule [Module] unburyWithClocks#(c1 initState, ModuleContext#(c1, ifcType) mkM)(Tuple2#(ifc, ifcType))\n provisos (Expose#(c1,ifc,n), Context#(ModuleContext#(c1), ClockContextP#(n)),\n\t Gettable#(c1, ClockContextP#(n)));\n\n (*hide*)\n Tuple2#(c1, ifcType) ci <- runWithCompleteContext(initState, mkM);\n match {.c, .i} = ci;\n ClockContextP#(n) cc = getIt(c);\n (*hide*)\n ifc i2 <- unburyContextWithClocks(c, cc);\n return tuple2(i2, i);\nendmodule\n\nmodule [c1] rebury#(Module#(Tuple2#(ifc, ifcType)) mkI)(ifcType)\n provisos (IsModule#(c1, a), Hide#(c1, ifc));\n match {.c, .i} <- liftModule(mkI);\n reburyContext(c);\n return i;\nendmodule\n\nmodule [c1] reburyWithClocks#(function Module#(Tuple2#(ifc, ifcType)) mkI\n\t\t\t\t (Vector#(n, Clock) cks, Vector#(n, Reset) rs))(ifcType)\n provisos (IsModule#(c1, a), Hide#(c1, ifc), Context#(c1, ClockContextP#(n)));\n ClockContextP#(n) clks <- getContext;\n match {.c, .i} <- liftModule(mkI(clks.clks, clks.rsts));\n (*hide_all*) let rbc <- reburyContext(c);\n return i;\nendmodule\n\nendpackage\n","avg_line_length":28.7122302158,"max_line_length":103,"alphanum_fraction":0.6648709597} {"size":2445,"ext":"bsv","lang":"Bluespec","max_stars_count":1.0,"content":"\/\/ Copyright (c) 2007--2009 Bluespec, Inc. All rights reserved.\n\/\/ $Revision$\n\/\/ $Date$\n\npackage TLMUtils;\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nimport TLMDefines::*;\nimport Vector::*;\nimport BUtils::*;\n\n`include \"TLM.defines\"\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\nfunction RequestDescriptor#(`TLM_TYPES) createBasicRequestDescriptor()\n provisos(Bits#(RequestDescriptor#(`TLM_TYPES), s0));\n RequestDescriptor#(`TLM_TYPES) request = unpack(0);\n request.command = READ;\n request.transaction_id = 0;\n request.burst_length = 1;\n request.burst_size = 3; \/\/ assume 32 bits for now.\n request.burst_mode = INCR;\n request.byte_enable = '1;\n return request;\nendfunction\n\n\/* -----\\\/----- EXCLUDED -----\\\/-----\nfunction TLMResponse#(`TLM_TYPES) createTLMResponse(TLMId#(`TLM_TYPES) id, TLMStatus status)\n provisos(Bits#(TLMResponse#(`TLM_TYPES), s0));\n TLMResponse#(`TLM_TYPES) response = unpack(0);\n response.status = status;\n response.transaction_id = id;\n return response;\nendfunction\n -----\/\\----- EXCLUDED -----\/\\----- *\/\n\nfunction TLMResponse#(`TLM_TYPES) createBasicTLMResponse()\n provisos(Bits#(TLMResponse#(`TLM_TYPES), s0));\n TLMResponse#(`TLM_TYPES) response = unpack(0);\n return response;\nendfunction\n\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/\/\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\n\nfunction TLMData#(`TLM_TYPES) createTLMBitMask (TLMByteEn#(`TLM_TYPES) enable_bits);\n\n \n Vector#(TDiv#(data_size, 8),Bit#(1)) enable = unpack(enable_bits);\n Vector#(TDiv#(data_size, 8),Bit#(8)) mask = map(signExtend, enable);\n \n return cExtend(mask);\n\nendfunction\n\nfunction TLMData#(`TLM_TYPES) maskTLMData(TLMByteEn#(`TLM_TYPES) byte_enable, TLMData#(`TLM_TYPES) data);\n \n TLMData#(`TLM_TYPES) mask = createTLMBitMask(byte_enable);\n \n return mask & data;\n \nendfunction\n\nfunction TLMData#(`TLM_TYPES) overwriteTLMData(TLMByteEn#(`TLM_TYPES) byte_enable, TLMData#(`TLM_TYPES) data_orig, TLMData#(`TLM_TYPES) data);\n \n TLMData#(`TLM_TYPES) mask = createTLMBitMask(byte_enable);\n \n return (~mask & data_orig) | (mask & data);\n \nendfunction\n\nendpackage\n","avg_line_length":30.1851851852,"max_line_length":142,"alphanum_fraction":0.5570552147} {"size":252,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"package Design4;\n\n\ninterface DESIGN_IFC;\n \n method Bit#(11) out4();\nendinterface: DESIGN_IFC\n\n\n\n\nmodule mkDesign (DESIGN_IFC);\n\n method Bit#(11) out4();\n int x = -1;\n out4 = 1<< x;\n \n endmethod\n\nendmodule: mkDesign\n \nendpackage\n","avg_line_length":10.9565217391,"max_line_length":29,"alphanum_fraction":0.619047619} {"size":767,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"package Derive1;\n\n\/\/ we use different identifiers everywhere to prevent from\n\/\/ confusing two different things with the same name (in different scopes)\n\/\/ in dump and debugging output\n\ntypedef union tagged {\n void Nilx;\n struct {\n dtype c1ar;\n Kens1List#(dtype) c1dr;\n } Cons1x;\n} Kens1List#(type dtype)\nderiving(Eq)\n;\n\n\n(* synthesize *)\nmodule sysDerive1();\n rule foo;\n Kens1List#(int) a=Nilx;\n Kens1List#(int) b=Nilx;\n Kens1List#(int) c=tagged Cons1x { c1ar:10, c1dr: Nilx};\n Kens1List#(int) d=tagged Cons1x { c1ar:10, c1dr: Nilx};\n Kens1List#(int) e=tagged Cons1x { c1ar:20, c1dr: Nilx};\n $display(a==b);\n $display(a==c);\n $display(c==d);\n $display(c==e);\n\n $finish(0);\n endrule\n \nendmodule\n\nendpackage\n","avg_line_length":20.7297297297,"max_line_length":74,"alphanum_fraction":0.6401564537} {"size":840,"ext":"bsv","lang":"Bluespec","max_stars_count":null,"content":"import RandTop3A::*;\nimport Clocks::*;\n\n(* synthesize *)\nmodule mkTop(Empty);\n Reg#(Nat) ctr <- mkReg(0);\n\n Clock defclock <- exposeCurrentClock;\n MakeResetIfc rifc0 <- mkReset(2, True, defclock);\n Reset r0 = rifc0.new_rst;\n\n Reg#(Bool) greg0 <- mkReg(True);\n Reg#(Bool) greg1 <- mkReg(True);\n Reg#(Bool) greg2 <- mkReg(True);\n Reg#(UInt#(4)) fr1 <- mkReg(3);\n\n rule steer;\n if (ctr<20) rifc0.assertReset;\n if (ctr==50) greg1 <= False;\n if (ctr==100) greg1 <= True;\n if (ctr==150) greg2 <= False;\n if (ctr==200) greg2 <= True;\n if (ctr==250) greg0 <= False;\n if (ctr==300) greg0 <= True;\n if (ctr==320) fr1 <= 7;\n if (ctr==400) $finish(0);\n \n ctr <= ctr+1;\n endrule\n\n ExtIfc randifc();\n mkRandTop dut(fr1, greg0, greg1, greg2, randifc, reset_by r0);\nendmodule\n\n","avg_line_length":24.0,"max_line_length":65,"alphanum_fraction":0.5726190476} {"size":24124,"ext":"bsv","lang":"Bluespec","max_stars_count":12.0,"content":"import Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport Vector::*;\n\n(* always_ready, always_enabled *)\ninterface MacwrapJtag;\n method Reset reset_reset();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP0_link_fault;\n method Bit#(2) status_data();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP0_rx;\n method Bit#(64) fifo_out_data();\n method Bit#(3) fifo_out_empty();\n method Bit#(1) fifo_out_endofpacket();\n method Bit#(6) fifo_out_error();\n method Action fifo_out_ready(Bit#(1) v);\n method Bit#(1) fifo_out_startofpacket();\n method Bit#(1) fifo_out_valid();\n method Bit#(40) status_data();\n method Bit#(7) status_error();\n method Bit#(1) status_valid();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP0_tx;\n method Action fifo_in_data(Bit#(64) v);\n method Action fifo_in_empty(Bit#(3) v);\n method Action fifo_in_endofpacket(Bit#(1) v);\n method Action fifo_in_error(Bit#(1) v);\n method Bit#(1) fifo_in_ready();\n method Action fifo_in_startofpacket(Bit#(1) v);\n method Action fifo_in_valid(Bit#(1) v);\n method Bit#(40) status_data();\n method Bit#(7) status_error();\n method Bit#(1) status_valid();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP0_xgmii;\n method Action rx_data(Bit#(72) v);\n method Bit#(72) tx_data();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP1_link_fault;\n method Bit#(2) status_data();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP1_rx;\n method Bit#(64) fifo_out_data();\n method Bit#(3) fifo_out_empty();\n method Bit#(1) fifo_out_endofpacket();\n method Bit#(6) fifo_out_error();\n method Action fifo_out_ready(Bit#(1) v);\n method Bit#(1) fifo_out_startofpacket();\n method Bit#(1) fifo_out_valid();\n method Bit#(40) status_data();\n method Bit#(7) status_error();\n method Bit#(1) status_valid();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP1_tx;\n method Action fifo_in_data(Bit#(64) v);\n method Action fifo_in_empty(Bit#(3) v);\n method Action fifo_in_endofpacket(Bit#(1) v);\n method Action fifo_in_error(Bit#(1) v);\n method Bit#(1) fifo_in_ready();\n method Action fifo_in_startofpacket(Bit#(1) v);\n method Action fifo_in_valid(Bit#(1) v);\n method Bit#(40) status_data();\n method Bit#(7) status_error();\n method Bit#(1) status_valid();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP1_xgmii;\n method Action rx_data(Bit#(72) v);\n method Bit#(72) tx_data();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP2_link_fault;\n method Bit#(2) status_data();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP2_rx;\n method Bit#(64) fifo_out_data();\n method Bit#(3) fifo_out_empty();\n method Bit#(1) fifo_out_endofpacket();\n method Bit#(6) fifo_out_error();\n method Action fifo_out_ready(Bit#(1) v);\n method Bit#(1) fifo_out_startofpacket();\n method Bit#(1) fifo_out_valid();\n method Bit#(40) status_data();\n method Bit#(7) status_error();\n method Bit#(1) status_valid();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP2_tx;\n method Action fifo_in_data(Bit#(64) v);\n method Action fifo_in_empty(Bit#(3) v);\n method Action fifo_in_endofpacket(Bit#(1) v);\n method Action fifo_in_error(Bit#(1) v);\n method Bit#(1) fifo_in_ready();\n method Action fifo_in_startofpacket(Bit#(1) v);\n method Action fifo_in_valid(Bit#(1) v);\n method Bit#(40) status_data();\n method Bit#(7) status_error();\n method Bit#(1) status_valid();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP2_xgmii;\n method Action rx_data(Bit#(72) v);\n method Bit#(72) tx_data();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP3_link_fault;\n method Bit#(2) status_data();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP3_rx;\n method Bit#(64) fifo_out_data();\n method Bit#(3) fifo_out_empty();\n method Bit#(1) fifo_out_endofpacket();\n method Bit#(6) fifo_out_error();\n method Action fifo_out_ready(Bit#(1) v);\n method Bit#(1) fifo_out_startofpacket();\n method Bit#(1) fifo_out_valid();\n method Bit#(40) status_data();\n method Bit#(7) status_error();\n method Bit#(1) status_valid();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP3_tx;\n method Action fifo_in_data(Bit#(64) v);\n method Action fifo_in_empty(Bit#(3) v);\n method Action fifo_in_endofpacket(Bit#(1) v);\n method Action fifo_in_error(Bit#(1) v);\n method Bit#(1) fifo_in_ready();\n method Action fifo_in_startofpacket(Bit#(1) v);\n method Action fifo_in_valid(Bit#(1) v);\n method Bit#(40) status_data();\n method Bit#(7) status_error();\n method Bit#(1) status_valid();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacwrapP3_xgmii;\n method Action rx_data(Bit#(72) v);\n method Bit#(72) tx_data();\nendinterface\n(* always_ready, always_enabled *)\ninterface MacWrap;\n interface MacwrapJtag jtag;\n interface MacwrapP0_link_fault p0_link_fault;\n interface MacwrapP0_rx p0_rx;\n interface MacwrapP0_tx p0_tx;\n interface MacwrapP0_xgmii p0_xgmii;\n interface MacwrapP1_link_fault p1_link_fault;\n interface MacwrapP1_rx p1_rx;\n interface MacwrapP1_tx p1_tx;\n interface MacwrapP1_xgmii p1_xgmii;\n interface MacwrapP2_link_fault p2_link_fault;\n interface MacwrapP2_rx p2_rx;\n interface MacwrapP2_tx p2_tx;\n interface MacwrapP2_xgmii p2_xgmii;\n interface MacwrapP3_link_fault p3_link_fault;\n interface MacwrapP3_rx p3_rx;\n interface MacwrapP3_tx p3_tx;\n interface MacwrapP3_xgmii p3_xgmii;\nendinterface\nimport \"BVI\" altera_mac =\nmodule mkMacWrap#(Clock mgmt_clk_clk, Clock clk_156_25, Vector#(4, Clock) rx_clk, Vector#(4, Reset) rx_rst, Reset mgmt_reset_reset_n, Reset rst_156_25)(MacWrap);\n default_clock clk();\n default_reset rst();\n input_clock mgmt_clk_clk(mgmt_clk_clk) = mgmt_clk_clk;\n input_reset mgmt_reset_reset_n(mgmt_reset_reset_n) = rst_156_25;\n input_clock p0_rx_clk_clk(p0_rx_clk_clk) = rx_clk[0];\n input_reset p0_rx_reset_reset_n(p0_rx_reset_reset_n) clocked_by(p0_rx_clk_clk) = rx_rst[0];\n input_clock p0_tx_clk_clk(p0_tx_clk_clk) = clk_156_25;\n input_reset p0_tx_reset_reset_n(p0_tx_reset_reset_n) = rst_156_25;\n input_clock p1_rx_clk_clk(p1_rx_clk_clk) = rx_clk[1];\n input_reset p1_rx_reset_reset_n(p1_rx_reset_reset_n) clocked_by(p1_rx_clk_clk) = rx_rst[1];\n input_clock p1_tx_clk_clk(p1_tx_clk_clk) = clk_156_25;\n input_reset p1_tx_reset_reset_n(p1_tx_reset_reset_n) = rst_156_25;\n input_clock p2_rx_clk_clk(p2_rx_clk_clk) = rx_clk[2];\n input_reset p2_rx_reset_reset_n(p2_rx_reset_reset_n) clocked_by(p2_rx_clk_clk) = rx_rst[2];\n input_clock p2_tx_clk_clk(p2_tx_clk_clk) = clk_156_25;\n input_reset p2_tx_reset_reset_n(p2_tx_reset_reset_n) = rst_156_25;\n input_clock p3_rx_clk_clk(p3_rx_clk_clk) = rx_clk[3];\n input_reset p3_rx_reset_reset_n(p3_rx_reset_reset_n) clocked_by(p3_rx_clk_clk) = rx_rst[3];\n input_clock p3_tx_clk_clk(p3_tx_clk_clk) = clk_156_25;\n input_reset p3_tx_reset_reset_n(p3_tx_reset_reset_n) = rst_156_25;\n interface MacwrapJtag jtag;\n output_reset reset_reset(jtag_reset_reset);\n endinterface\n interface MacwrapP0_link_fault p0_link_fault;\n method p0_link_fault_status_data status_data();\n endinterface\n interface MacwrapP0_rx p0_rx;\n method p0_rx_fifo_out_data fifo_out_data() clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n);\n method p0_rx_fifo_out_empty fifo_out_empty() clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n);\n method p0_rx_fifo_out_endofpacket fifo_out_endofpacket() clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n);\n method p0_rx_fifo_out_error fifo_out_error() clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n);\n method fifo_out_ready(p0_rx_fifo_out_ready) clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n) enable((*inhigh*) EN_p0_rx_fifo_out_ready);\n method p0_rx_fifo_out_startofpacket fifo_out_startofpacket() clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n);\n method p0_rx_fifo_out_valid fifo_out_valid() clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n);\n method p0_rx_status_data status_data() clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n);\n method p0_rx_status_error status_error() clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n);\n method p0_rx_status_valid status_valid() clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n);\n endinterface\n interface MacwrapP0_tx p0_tx;\n method fifo_in_data(p0_tx_fifo_in_data) clocked_by (p0_tx_clk_clk) reset_by (p0_tx_reset_reset_n) enable((*inhigh*) EN_p0_tx_fifo_in_data);\n method fifo_in_empty(p0_tx_fifo_in_empty) clocked_by (p0_tx_clk_clk) reset_by (p0_tx_reset_reset_n) enable((*inhigh*) EN_p0_tx_fifo_in_empty);\n method fifo_in_endofpacket(p0_tx_fifo_in_endofpacket) clocked_by (p0_tx_clk_clk) reset_by (p0_tx_reset_reset_n) enable((*inhigh*) EN_p0_tx_fifo_in_endofpacket);\n method fifo_in_error(p0_tx_fifo_in_error) clocked_by (p0_tx_clk_clk) reset_by (p0_tx_reset_reset_n) enable((*inhigh*) EN_p0_tx_fifo_in_error);\n method p0_tx_fifo_in_ready fifo_in_ready() clocked_by (p0_tx_clk_clk) reset_by (p0_tx_reset_reset_n);\n method fifo_in_startofpacket(p0_tx_fifo_in_startofpacket) clocked_by (p0_tx_clk_clk) reset_by (p0_tx_reset_reset_n) enable((*inhigh*) EN_p0_tx_fifo_in_startofpacket);\n method fifo_in_valid(p0_tx_fifo_in_valid) clocked_by (p0_tx_clk_clk) reset_by (p0_tx_reset_reset_n) enable((*inhigh*) EN_p0_tx_fifo_in_valid);\n method p0_tx_status_data status_data() clocked_by (p0_tx_clk_clk) reset_by (p0_tx_reset_reset_n);\n method p0_tx_status_error status_error() clocked_by (p0_tx_clk_clk) reset_by (p0_tx_reset_reset_n);\n method p0_tx_status_valid status_valid() clocked_by (p0_tx_clk_clk) reset_by (p0_tx_reset_reset_n);\n endinterface\n interface MacwrapP0_xgmii p0_xgmii;\n method rx_data(p0_xgmii_rx_data) clocked_by (p0_rx_clk_clk) reset_by (p0_rx_reset_reset_n) enable((*inhigh*) EN_p0_xgmii_rx_data);\n method p0_xgmii_tx_data tx_data() clocked_by (clk);\n endinterface\n interface MacwrapP1_link_fault p1_link_fault;\n method p1_link_fault_status_data status_data();\n endinterface\n interface MacwrapP1_rx p1_rx;\n method p1_rx_fifo_out_data fifo_out_data() clocked_by (p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n);\n method p1_rx_fifo_out_empty fifo_out_empty() clocked_by (p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n);\n method p1_rx_fifo_out_endofpacket fifo_out_endofpacket() clocked_by (p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n);\n method p1_rx_fifo_out_error fifo_out_error() clocked_by (p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n);\n method fifo_out_ready(p1_rx_fifo_out_ready) clocked_by (p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n) enable((*inhigh*) EN_p1_rx_fifo_out_ready);\n method p1_rx_fifo_out_startofpacket fifo_out_startofpacket() clocked_by (p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n);\n method p1_rx_fifo_out_valid fifo_out_valid() clocked_by (p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n);\n method p1_rx_status_data status_data() clocked_by (p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n);\n method p1_rx_status_error status_error() clocked_by (p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n);\n method p1_rx_status_valid status_valid() clocked_by (p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n);\n endinterface\n interface MacwrapP1_tx p1_tx;\n method fifo_in_data(p1_tx_fifo_in_data) clocked_by (p1_tx_clk_clk) reset_by (p1_tx_reset_reset_n) enable((*inhigh*) EN_p1_tx_fifo_in_data);\n method fifo_in_empty(p1_tx_fifo_in_empty) clocked_by (p1_tx_clk_clk) reset_by (p1_tx_reset_reset_n) enable((*inhigh*) EN_p1_tx_fifo_in_empty);\n method fifo_in_endofpacket(p1_tx_fifo_in_endofpacket) clocked_by (p1_tx_clk_clk) reset_by (p1_tx_reset_reset_n) enable((*inhigh*) EN_p1_tx_fifo_in_endofpacket);\n method fifo_in_error(p1_tx_fifo_in_error) clocked_by (p1_tx_clk_clk) reset_by (p1_tx_reset_reset_n) enable((*inhigh*) EN_p1_tx_fifo_in_error);\n method p1_tx_fifo_in_ready fifo_in_ready() clocked_by (p1_tx_clk_clk) reset_by (p1_tx_reset_reset_n);\n method fifo_in_startofpacket(p1_tx_fifo_in_startofpacket) clocked_by (p1_tx_clk_clk) reset_by (p1_tx_reset_reset_n) enable((*inhigh*) EN_p1_tx_fifo_in_startofpacket);\n method fifo_in_valid(p1_tx_fifo_in_valid) clocked_by (p1_tx_clk_clk) reset_by (p1_tx_reset_reset_n) enable((*inhigh*) EN_p1_tx_fifo_in_valid);\n method p1_tx_status_data status_data() clocked_by (p1_tx_clk_clk) reset_by (p1_tx_reset_reset_n);\n method p1_tx_status_error status_error() clocked_by (p1_tx_clk_clk) reset_by (p1_tx_reset_reset_n);\n method p1_tx_status_valid status_valid() clocked_by (p1_tx_clk_clk) reset_by (p1_tx_reset_reset_n);\n endinterface\n interface MacwrapP1_xgmii p1_xgmii;\n method rx_data(p1_xgmii_rx_data) clocked_by(p1_rx_clk_clk) reset_by (p1_rx_reset_reset_n) enable((*inhigh*) EN_p1_xgmii_rx_data);\n method p1_xgmii_tx_data tx_data() clocked_by(clk);\n endinterface\n interface MacwrapP2_link_fault p2_link_fault;\n method p2_link_fault_status_data status_data();\n endinterface\n interface MacwrapP2_rx p2_rx;\n method p2_rx_fifo_out_data fifo_out_data() clocked_by (p2_rx_clk_clk) reset_by (p2_rx_reset_reset_n);\n method p2_rx_fifo_out_empty fifo_out_empty() clocked_by (p2_rx_clk_clk) reset_by (p2_rx_reset_reset_n);\n method p2_rx_fifo_out_endofpacket fifo_out_endofpacket() clocked_by (p2_rx_clk_clk) reset_by (p2_rx_reset_reset_n);\n method p2_rx_fifo_out_error fifo_out_error() clocked_by (p2_rx_clk_clk) reset_by (p2_rx_reset_reset_n);\n method fifo_out_ready(p2_rx_fifo_out_ready) clocked_by (p2_rx_clk_clk) reset_by (p2_rx_reset_reset_n) enable((*inhigh*) EN_p2_rx_fifo_out_ready);\n method p2_rx_fifo_out_startofpacket fifo_out_startofpacket() clocked_by (p2_rx_clk_clk) reset_by (p2_rx_reset_reset_n);\n method p2_rx_fifo_out_valid fifo_out_valid() clocked_by (p2_rx_clk_clk) reset_by (p2_rx_reset_reset_n);\n method p2_rx_status_data status_data() clocked_by (p2_rx_clk_clk) reset_by (p2_rx_reset_reset_n);\n method p2_rx_status_error status_error() clocked_by (p2_rx_clk_clk) reset_by (p2_rx_reset_reset_n);\n method p2_rx_status_valid status_valid() clocked_by (p2_rx_clk_clk) reset_by (p2_rx_reset_reset_n);\n endinterface\n interface MacwrapP2_tx p2_tx;\n method fifo_in_data(p2_tx_fifo_in_data) clocked_by (p2_tx_clk_clk) reset_by (p2_tx_reset_reset_n) enable((*inhigh*) EN_p2_tx_fifo_in_data);\n method fifo_in_empty(p2_tx_fifo_in_empty) clocked_by (p2_tx_clk_clk) reset_by (p2_tx_reset_reset_n) enable((*inhigh*) EN_p2_tx_fifo_in_empty);\n method fifo_in_endofpacket(p2_tx_fifo_in_endofpacket) clocked_by (p2_tx_clk_clk) reset_by (p2_tx_reset_reset_n) enable((*inhigh*) EN_p2_tx_fifo_in_endofpacket);\n method fifo_in_error(p2_tx_fifo_in_error) clocked_by (p2_tx_clk_clk) reset_by (p2_tx_reset_reset_n) enable((*inhigh*) EN_p2_tx_fifo_in_error);\n method p2_tx_fifo_in_ready fifo_in_ready() clocked_by (p2_tx_clk_clk) reset_by (p2_tx_reset_reset_n);\n method fifo_in_startofpacket(p2_tx_fifo_in_startofpacket) clocked_by (p2_tx_clk_clk) reset_by (p2_tx_reset_reset_n) enable((*inhigh*) EN_p2_tx_fifo_in_startofpacket);\n method fifo_in_valid(p2_tx_fifo_in_valid) clocked_by (p2_tx_clk_clk) reset_by (p2_tx_reset_reset_n) enable((*inhigh*) EN_p2_tx_fifo_in_valid);\n method p2_tx_status_data status_data() clocked_by (p2_tx_clk_clk) reset_by (p2_tx_reset_reset_n);\n method p2_tx_status_error status_error() clocked_by (p2_tx_clk_clk) reset_by (p2_tx_reset_reset_n);\n method p2_tx_status_valid status_valid() clocked_by (p2_tx_clk_clk) reset_by (p2_tx_reset_reset_n);\n endinterface\n interface MacwrapP2_xgmii p2_xgmii;\n method rx_data(p2_xgmii_rx_data) clocked_by(p2_rx_clk_clk) reset_by(p2_rx_reset_reset_n) enable((*inhigh*) EN_p2_xgmii_rx_data);\n method p2_xgmii_tx_data tx_data() clocked_by(clk);\n endinterface\n interface MacwrapP3_link_fault p3_link_fault;\n method p3_link_fault_status_data status_data();\n endinterface\n interface MacwrapP3_rx p3_rx;\n method p3_rx_fifo_out_data fifo_out_data() clocked_by (p3_rx_clk_clk) reset_by (p3_rx_reset_reset_n);\n method p3_rx_fifo_out_empty fifo_out_empty() clocked_by (p3_rx_clk_clk) reset_by (p3_rx_reset_reset_n);\n method p3_rx_fifo_out_endofpacket fifo_out_endofpacket() clocked_by (p3_rx_clk_clk) reset_by (p3_rx_reset_reset_n);\n method p3_rx_fifo_out_error fifo_out_error() clocked_by (p3_rx_clk_clk) reset_by (p3_rx_reset_reset_n);\n method fifo_out_ready(p3_rx_fifo_out_ready) clocked_by (p3_rx_clk_clk) reset_by (p3_rx_reset_reset_n) enable((*inhigh*) EN_p3_rx_fifo_out_ready);\n method p3_rx_fifo_out_startofpacket fifo_out_startofpacket() clocked_by (p3_rx_clk_clk) reset_by (p3_rx_reset_reset_n);\n method p3_rx_fifo_out_valid fifo_out_valid() clocked_by (p3_rx_clk_clk) reset_by (p3_rx_reset_reset_n);\n method p3_rx_status_data status_data() clocked_by (p3_rx_clk_clk) reset_by (p3_rx_reset_reset_n);\n method p3_rx_status_error status_error() clocked_by (p3_rx_clk_clk) reset_by (p3_rx_reset_reset_n);\n method p3_rx_status_valid status_valid() clocked_by (p3_rx_clk_clk) reset_by (p3_rx_reset_reset_n);\n endinterface\n interface MacwrapP3_tx p3_tx;\n method fifo_in_data(p3_tx_fifo_in_data) clocked_by (p3_tx_clk_clk) reset_by (p3_tx_reset_reset_n) enable((*inhigh*) EN_p3_tx_fifo_in_data);\n method fifo_in_empty(p3_tx_fifo_in_empty) clocked_by (p3_tx_clk_clk) reset_by (p3_tx_reset_reset_n) enable((*inhigh*) EN_p3_tx_fifo_in_empty);\n method fifo_in_endofpacket(p3_tx_fifo_in_endofpacket) clocked_by (p3_tx_clk_clk) reset_by (p3_tx_reset_reset_n) enable((*inhigh*) EN_p3_tx_fifo_in_endofpacket);\n method fifo_in_error(p3_tx_fifo_in_error) clocked_by (p3_tx_clk_clk) reset_by (p3_tx_reset_reset_n) enable((*inhigh*) EN_p3_tx_fifo_in_error);\n method p3_tx_fifo_in_ready fifo_in_ready() clocked_by (p3_tx_clk_clk) reset_by (p3_tx_reset_reset_n);\n method fifo_in_startofpacket(p3_tx_fifo_in_startofpacket) clocked_by (p3_tx_clk_clk) reset_by (p3_tx_reset_reset_n) enable((*inhigh*) EN_p3_tx_fifo_in_startofpacket);\n method fifo_in_valid(p3_tx_fifo_in_valid) clocked_by (p3_tx_clk_clk) reset_by (p3_tx_reset_reset_n) enable((*inhigh*) EN_p3_tx_fifo_in_valid);\n method p3_tx_status_data status_data() clocked_by (p3_tx_clk_clk) reset_by (p3_tx_reset_reset_n);\n method p3_tx_status_error status_error() clocked_by (p3_tx_clk_clk) reset_by (p3_tx_reset_reset_n);\n method p3_tx_status_valid status_valid() clocked_by (p3_tx_clk_clk) reset_by (p3_tx_reset_reset_n);\n endinterface\n interface MacwrapP3_xgmii p3_xgmii;\n method rx_data(p3_xgmii_rx_data) clocked_by(p3_rx_clk_clk) reset_by(p3_rx_reset_reset_n) enable((*inhigh*) EN_p3_xgmii_rx_data);\n method p3_xgmii_tx_data tx_data() clocked_by(clk);\n endinterface\n schedule (p0_link_fault.status_data, p0_rx.fifo_out_data, p0_rx.fifo_out_empty, p0_rx.fifo_out_endofpacket, p0_rx.fifo_out_error, p0_rx.fifo_out_ready, p0_rx.fifo_out_startofpacket, p0_rx.fifo_out_valid, p0_rx.status_data, p0_rx.status_error, p0_rx.status_valid, p0_tx.fifo_in_data, p0_tx.fifo_in_empty, p0_tx.fifo_in_endofpacket, p0_tx.fifo_in_error, p0_tx.fifo_in_ready, p0_tx.fifo_in_startofpacket, p0_tx.fifo_in_valid, p0_tx.status_data, p0_tx.status_error, p0_tx.status_valid, p0_xgmii.rx_data, p0_xgmii.tx_data, p1_link_fault.status_data, p1_rx.fifo_out_data, p1_rx.fifo_out_empty, p1_rx.fifo_out_endofpacket, p1_rx.fifo_out_error, p1_rx.fifo_out_ready, p1_rx.fifo_out_startofpacket, p1_rx.fifo_out_valid, p1_rx.status_data, p1_rx.status_error, p1_rx.status_valid, p1_tx.fifo_in_data, p1_tx.fifo_in_empty, p1_tx.fifo_in_endofpacket, p1_tx.fifo_in_error, p1_tx.fifo_in_ready, p1_tx.fifo_in_startofpacket, p1_tx.fifo_in_valid, p1_tx.status_data, p1_tx.status_error, p1_tx.status_valid, p1_xgmii.rx_data, p1_xgmii.tx_data, p2_link_fault.status_data, p2_rx.fifo_out_data, p2_rx.fifo_out_empty, p2_rx.fifo_out_endofpacket, p2_rx.fifo_out_error, p2_rx.fifo_out_ready, p2_rx.fifo_out_startofpacket, p2_rx.fifo_out_valid, p2_rx.status_data, p2_rx.status_error, p2_rx.status_valid, p2_tx.fifo_in_data, p2_tx.fifo_in_empty, p2_tx.fifo_in_endofpacket, p2_tx.fifo_in_error, p2_tx.fifo_in_ready, p2_tx.fifo_in_startofpacket, p2_tx.fifo_in_valid, p2_tx.status_data, p2_tx.status_error, p2_tx.status_valid, p2_xgmii.rx_data, p2_xgmii.tx_data, p3_link_fault.status_data, p3_rx.fifo_out_data, p3_rx.fifo_out_empty, p3_rx.fifo_out_endofpacket, p3_rx.fifo_out_error, p3_rx.fifo_out_ready, p3_rx.fifo_out_startofpacket, p3_rx.fifo_out_valid, p3_rx.status_data, p3_rx.status_error, p3_rx.status_valid, p3_tx.fifo_in_data, p3_tx.fifo_in_empty, p3_tx.fifo_in_endofpacket, p3_tx.fifo_in_error, p3_tx.fifo_in_ready, p3_tx.fifo_in_startofpacket, p3_tx.fifo_in_valid, p3_tx.status_data, p3_tx.status_error, p3_tx.status_valid, p3_xgmii.rx_data, p3_xgmii.tx_data) CF (p0_link_fault.status_data, p0_rx.fifo_out_data, p0_rx.fifo_out_empty, p0_rx.fifo_out_endofpacket, p0_rx.fifo_out_error, p0_rx.fifo_out_ready, p0_rx.fifo_out_startofpacket, p0_rx.fifo_out_valid, p0_rx.status_data, p0_rx.status_error, p0_rx.status_valid, p0_tx.fifo_in_data, p0_tx.fifo_in_empty, p0_tx.fifo_in_endofpacket, p0_tx.fifo_in_error, p0_tx.fifo_in_ready, p0_tx.fifo_in_startofpacket, p0_tx.fifo_in_valid, p0_tx.status_data, p0_tx.status_error, p0_tx.status_valid, p0_xgmii.rx_data, p0_xgmii.tx_data, p1_link_fault.status_data, p1_rx.fifo_out_data, p1_rx.fifo_out_empty, p1_rx.fifo_out_endofpacket, p1_rx.fifo_out_error, p1_rx.fifo_out_ready, p1_rx.fifo_out_startofpacket, p1_rx.fifo_out_valid, p1_rx.status_data, p1_rx.status_error, p1_rx.status_valid, p1_tx.fifo_in_data, p1_tx.fifo_in_empty, p1_tx.fifo_in_endofpacket, p1_tx.fifo_in_error, p1_tx.fifo_in_ready, p1_tx.fifo_in_startofpacket, p1_tx.fifo_in_valid, p1_tx.status_data, p1_tx.status_error, p1_tx.status_valid, p1_xgmii.rx_data, p1_xgmii.tx_data, p2_link_fault.status_data, p2_rx.fifo_out_data, p2_rx.fifo_out_empty, p2_rx.fifo_out_endofpacket, p2_rx.fifo_out_error, p2_rx.fifo_out_ready, p2_rx.fifo_out_startofpacket, p2_rx.fifo_out_valid, p2_rx.status_data, p2_rx.status_error, p2_rx.status_valid, p2_tx.fifo_in_data, p2_tx.fifo_in_empty, p2_tx.fifo_in_endofpacket, p2_tx.fifo_in_error, p2_tx.fifo_in_ready, p2_tx.fifo_in_startofpacket, p2_tx.fifo_in_valid, p2_tx.status_data, p2_tx.status_error, p2_tx.status_valid, p2_xgmii.rx_data, p2_xgmii.tx_data, p3_link_fault.status_data, p3_rx.fifo_out_data, p3_rx.fifo_out_empty, p3_rx.fifo_out_endofpacket, p3_rx.fifo_out_error, p3_rx.fifo_out_ready, p3_rx.fifo_out_startofpacket, p3_rx.fifo_out_valid, p3_rx.status_data, p3_rx.status_error, p3_rx.status_valid, p3_tx.fifo_in_data, p3_tx.fifo_in_empty, p3_tx.fifo_in_endofpacket, p3_tx.fifo_in_error, p3_tx.fifo_in_ready, p3_tx.fifo_in_startofpacket, p3_tx.fifo_in_valid, p3_tx.status_data, p3_tx.status_error, p3_tx.status_valid, p3_xgmii.rx_data, p3_xgmii.tx_data);\nendmodule\n","avg_line_length":74.9192546584,"max_line_length":4082,"alphanum_fraction":0.7732548499} {"size":29274,"ext":"bsv","lang":"Bluespec","max_stars_count":36.0,"content":"\/*-\n * Copyright (c) 2013 Jonathan Woodruff\n * Copyright (c) 2013 Alan A. Mujumdar\n * Copyright (c) 2013 Alex Horsman\n * Copyright (c) 2014 Alexandre Joannou\n * All rights reserved.\n *\n * This software was developed by SRI International and the University of\n * Cambridge Computer Laboratory under DARPA\/AFRL contract FA8750-10-C-0237\n * (\"CTSRD\"), as part of the DARPA CRASH research programme.\n *\n * This software was developed by SRI International and the University of\n * Cambridge Computer Laboratory under DARPA\/AFRL contract FA8750-11-C-0249\n * (\"MRC2\"), as part of the DARPA MRC research programme.\n *\n * @BERI_LICENSE_HEADER_START@\n *\n * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor\n * license agreements. See the NOTICE file distributed with this work for\n * additional information regarding copyright ownership. BERI licenses this\n * file to you under the BERI Hardware-Software License, Version 1.0 (the\n * \"License\"); you may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n *\n * http:\/\/www.beri-open-systems.org\/legal\/license-1-0.txt\n *\n * Unless required by applicable law or agreed to in writing, Work distributed\n * under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR\n * CONDITIONS OF ANY KIND, either express or implied. See the License for the\n * specific language governing permissions and limitations under the License.\n *\n * @BERI_LICENSE_HEADER_END@\n *\/\n\nimport MIPS::*;\nimport MemTypes::*;\nimport DefaultValue::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport MEM::*;\nimport ConfigReg::*;\nimport Assert::*;\nimport Debug::*;\nimport MasterSlave::*;\nimport GetPut::*;\n\ntypedef struct {\n Bit#(tag_size) tag;\n Bit#(index_size) index;\n Bit#(offset_size) offset;\n} PAddrT#( numeric type tag_size,\n numeric type index_size,\n numeric type offset_size) deriving (Bits, Eq);\n\ntypedef struct {\n Bit#(tag_size) tag;\n `ifdef CAP\n Bool capability;\n `endif\n Bool valid;\n} TagT#(numeric type tag_size) deriving (Bits, Eq);\n\ntypedef union tagged {\n UInt#(nb_ways_size) CachedMiss;\n void UncachedMiss;\n} MissReqT#(numeric type nb_ways_size) deriving (Bits);\n\ntypedef enum {Init, Serving, Miss\n `ifdef MULTI\n , StoreConditional\n `endif\n} CacheState deriving (Bits, Eq);\n\nmodule mkGenericDCache#(Bit#(16) coreId) (CacheDataIfc#(nb_ways, sets_per_way, bytes_per_line))\n provisos (\n Bits#(PhyAddress, paddr_size),\n Log#(nb_ways, nb_ways_size),\n Log#(bytes_per_line, offset_size),\n Log#(sets_per_way, index_size),\n Add#(TAdd#(tag_size, index_size), offset_size, paddr_size),\n Mul#(bytes_per_line, 8, line_size),\n Add#(line_size, 0, 256)\n );\n\n`define TagMEM MEM#(Bit#(index_size),TagT#(tag_size))\n`define DataMEM MEM#(Bit#(index_size), Bit#(line_size))\n\n \/\/ requests fifo\n FIFO#(CacheRequestDataT) req_fifo <- mkLFIFO;\n \/\/ response fifo\n FIFO#(CacheResponseDataT) rsp_fifo <- mkBypassFIFO;\n \/\/ commit fifo\n FIFOF#(Bool) commit_fifo <- mkSizedBypassFIFOF(4);\n \/\/ miss fifo\n FIFO#(MissReqT#(nb_ways_size)) miss_req_fifo <- mkFIFO;\n \/\/ invalidate requests fifo\n FIFOF#(PAddrT#(tag_size, index_size, offset_size))\n inval_fifo <- mkSizedFIFOF(20);\n \/\/ memory interface request fifo\n FIFOF#(CheriMemRequest) mem_req_fifo <- mkFIFOF;\n \/\/ memory interface response fifo\n FIFOF#(CheriMemResponse) mem_rsp_fifo <- mkFIFOF;\n \/\/ counter used to initialize the icache\n Reg#(Bit#(index_size)) initCount <- mkReg(0);\n \/\/ icache state register\n Reg#(CacheState) cacheState <- mkConfigReg(Init);\n\n \/\/ MEMs\n \/\/ Tag MEMs\n Vector#(nb_ways, `TagMEM)\n tags <- replicateM(mkMEM);\n Vector#(nb_ways, Vector#(sets_per_way, Reg#(TagT#(tag_size))))\n tagsDebug <- replicateM(replicateM(mkReg(TagT{\n valid : False,\n `ifdef CAP\n capability: ?,\n `endif\n tag : ?\n })));\n \/\/ Data MEMs\n Vector#(nb_ways, `DataMEM)\n data <- replicateM(mkMEM);\n\n \/\/ invalid tag\n TagT#(tag_size) tagInvalid = TagT {\n `ifdef CAP\n capability: ?,\n `endif\n tag: ?,\n valid: False\n };\n\n \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n \/\/ utils function to easily access the MEMs \/\/\n \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n \/\/ sends a write request to the tag MEM for a single way\n function Action writeTag ( Bit#(index_size) windex,\n TagT#(tag_size) wdata,\n `TagMEM wayTagMEM);\n action\n wayTagMEM.write(windex, wdata);\n endaction\n endfunction\n \/\/ writes to the tag debug vector for a single way\n \/\/ \/!\\ this is instantaneous whereas the actual write of\n \/\/ the MEM takes one cycle\n function Action writeDebugTag ( Bit#(index_size) windex,\n TagT#(tag_size) wdata,\n Vector#(sets_per_way, Reg#(TagT#(tag_size))) wayTagDebug);\n action\n wayTagDebug[windex] <= wdata;\n endaction\n endfunction\n \/\/ sends a read request to the tag MEM for a single way\n function Action lookupTag ( Bit#(index_size) rindex,\n `TagMEM wayTagMEM);\n action\n wayTagMEM.read.put(rindex);\n endaction\n endfunction\n \/\/ sends a read request to the data MEM for a single way\n function Action lookupData ( Bit#(index_size) rindex,\n `DataMEM wayDataMEM);\n action\n wayDataMEM.read.put(rindex);\n endaction\n endfunction\n\n \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n \/\/ Eviction policy \/\/\n \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\n \/\/ TODO implement better replacement policy\n \/\/ select a victim way by returning a way number\n Reg#(UInt#(nb_ways_size)) nextVictimWay <- mkReg(0);\n function ActionValue#(UInt#(nb_ways_size)) selectVictimWay\n (Vector#(nb_ways, TagT#(tag_size)) tags_vector);\n function Bool isTagInvalid(TagT#(tag_size) tag) = !tag.valid;\n return actionvalue\n case (findIndex(isTagInvalid, tags_vector)) matches\n tagged Valid .x: begin\n return x;\n end\n tagged Invalid: begin\n nextVictimWay <= nextVictimWay + 1;\n return nextVictimWay;\n end\n endcase\n endactionvalue;\n endfunction\n\n \/\/ Sets every valid bit to False in the tags MEM\n rule do_initialize (cacheState == Init);\n mapM_(writeTag(pack(initCount), tagInvalid), tags);\n mapM_(writeDebugTag(pack(initCount), tagInvalid), tagsDebug);\n initCount <= initCount + 1;\n debug2(\"dcache\", $display(\"