Patent claim: A computer program for controlling a clock signal generator the computer program comprising computer executable instructions for controlling a programmable processor to form a control quantity on the basis of reception moments of timing messages the reception moments being expressed as time values based on a first clock signal and the timing messages being transmitted in accordance with a second clock signal characterized in that the computer program further comprises computer executable instructions for controlling the programmable processor toform at least one additional control quantity on the basis of the reception moments of the timing messagescalculate a weighted sum of the control quantity and the at least one additional control quantity andcontrol the clock signal generator with the weighted sum of the control quantities so as to achieve synchronization between the first clock signal and the second clock signal.

Related passage: Fig.1 shows in the form of block diagram an example of a communications network comprising an arrangement according to an embodiment of the invention for adjusting a clock signal.A communications network comprises a first network element 101 and second network elements 102 103 104 and 105.Other parts of the communications network are represented by the crosshatched area 199.Network element 101 is arranged to receive synchronisation messages from network elements 102 103 104 and 105 via the communications network 199.Synchronisation messages S1 sent by network element 102 are marked with referencenumber 106 in Fig.1 synchronisation messages S2 sent by network element 103 are marked with reference number 107 synchronisation messages S3 sent by network element 104 are marked with reference number 108 and synchronisation messages S4 sent by network element 105 are marked with reference number 109.Each of the network elements 102 to 105 is arranged to send the synchronisation messages 106 107 108 or 109 timed by a clock signal 125 126 127 or 128 of the network element in question.The clock signals 125 to 128 may originate from a single source or from several different sources.Network element 101 has an adjustable clock signal source 110 arranged to produce an adjustable clock signal 115.The adjustable clock signal source may be a voltage controlled oscillator VCO or numerically controlled oscillator NCO for instance.The arrangement for adjusting the clock signal 115 comprises a processor device consisting of functional blocks 111 to 114 which processor device is adapted to produce a control variable 116 containing information about synchronisation messages 106 to 109 received from more than one network element 102 to 105.The processor device is further adapted to adjust the clock signal 115 on the basis of the difference 118 between the control variable 116 and its reference value 117.A situation in which a network element 101 stops receiving good enough synchronisation messages from a sending network element 102 103 104 or 105 will not unreasonably disturb the frequency andor phase of the clock signal 115 to be adjusted because only a certain portion of the control variable 116 used for the adjustment of the clock signal depends on synchronisation messages sent by an individual network element 102 103 104 or 105.The functional blocks 111 to 114 in the processor device can be implemented by software using one or more programmable processors for example.The functional blocks may also be implemented using one or more application specific integrated circuits or a hybrid solution including one or more programmable processors the software required and one or more application specific integrated circuits.