Patent SG-11201901324Q-A (SG)
Title: Separate read and write address decoding in a memory system to support simultaneous memory read and write operations
Inventor: GARG MANISH
IPC: G11C11/419
Filed: 2017-09-05
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property C.--.` 11111111110111010101111101 110 1 0101101100111110111100HRHOE111 Organization International Bureau (10) International Publication Number 03 (43) International Publication Date ......•' WO 2018/067254 Al 12 April 2018 (12.04.2018) WIP0 1 PCT (51) International Patent Classification: (71) Applicant: QUALCOMM INCORPORATED [US/US]; Gl1C 7/10 (2006.01) Gl1C 11/418 (2006.01) ATTN: International IP Administration, 5775 Morehouse Gl1C 8/10 (2006.01) Gl1C 8/08 (2006.01) Drive, San Diego, California 92121-1714 (US). G11C 11/419 (2006.01) (72) Inventor: GARG, Manish; 5775 Morehouse Drive, San (21) International Application Number: Diego, California 92121 (US). PCT/US2017/050040 (74) Agent: TERRANOVA, Steven, N.; WITHROW & TER- (22) International Filing Date: RANOVA, PLLC, 106 Pinedale Springs Way, Cary, North 05 September 2017 (05.09.2017) Carolina 27511 (US). (25) Filing Language: English (81) Designated States (unless otherwise indicated, for every (26) Publication Language: English kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (30) Priority Data: CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, 62/403,740 04 October 2016 (04.10.2016) US DZ, EC, EE, EG, ES, GB, GD, GE, GH, GM, FI, GT, HN, 15/429,842 10 February 2017 (10.02.2017) US HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, (54) Title: SEPARATE READ AND WRITE ADDRESS DECODING IN A MEMORY SYSTEM TO SUPPORT SIMULTANEOUS MEMORY READ AND WRITE OPERATIONS MEMORY SYSTEM (400) 522(0) C(0) T rttrow_seke> 42610) 432(0) wrice)440 524(0) WIA> 1 r * f ht ,.--410(060X0) x 410(40)(X) wi maxop w 4c-53° — bib V — •• •• • bib bl —1 N •• • • 4110(MX0XX) b bl 1 ' 1 'AILAcik WI_ ck5220 : rd row sekNA WL ) 426(P 4., Uwr ra, se14 524(N) a _t...._ mom ) a 41ow)(4x) M go(MXNo) ---s WI_ VA N — bibh - bib N — bt bl • •• b til ) 528 --41.,1, 410KNYX) Allid_idr MIL wr A O -•-, r504(0) m as- 526 rot obi ben> 5 ) W' mw r6.4091410A wr_atseto co/ seRM 0> xl_wr ck WR COLUMN DRIVER (K U aRcun- r 506)0- WR MLUMN DRIVER CIRCUIT (MIR I w Sala wr Gat 438 id elk 430 RD!WR 5141) (422) c 514114) (422) 'ird CLOCX C ENERAT ICH CIRCUIT rdDol_sel. cd r° *015) RD COLLMN SELECT CIRCUIT (518(0)) coliell) Goljt rik 1516i RD COLUMN SELECT CRCLU (51860)) (503) rd (418) Y rd dais (4T6) Si_prat (SO) 31. PRE-CHARGER CIRCUIT POD RI.CHARGER CIRCUIT (512(M)) MEMORY BIT CELL MEMORY SUB-ARRAY (500) SaECTICN mug (502) FIG. 5 1-1 7r (57) : Memory systems that provide separate read and write address decoding to support simultaneous memory read and write p,a iln operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory read and jr.: write operation even if employing single port memory bit cells. The read and write addresses of respective read and write operations are ,IZ separately decoded into read and write row and column selects driven to a memory array so that simultaneous read and write operations 0 ...... are not affected by each other. To avoid a circuit conflict for a simultaneous read and write operation, the memory system is configured GC to prioritize a write row select over a read row select to drive a row of memory bit cells in the memory array. In this manner, that write 1-1 c:, operation will always be successful regardless of whether the read and write row select are to the same row. ei C [Continued on next page] WO 2018/067254 Al 11111111111111111110111111111110111110100111011001111111111111111111111110111111111111 OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))