baber/WOPTO huggingface dataset:
Patent JP-H0469784-A (JP)
Title: Storage embedding method, storage retrieving method and storage retrieving device
Inventor: NARA SHIGETOSHI
IPC: G06N3/00
Filed: 1990-07-10
Abstract: PURPOSE:To decrease the ratio of being led into a pseudo-storage at the time of storage recollection by making a synapse coupling matrix by taking mutually a direct product so that plural ignition patterns to be stored become cyclic, and furthermore adding up plural pieces of independent ones thereof. CONSTITUTION:An input device 1 is connected to a neural network 2, the neural network 2 is connected to an output device 3, and on the other hand, the output device 3 is connected to a feature extracting device 5 operated by inputting an ignition pattern by synchronizing with time development of a system, and the feature extracting device 5 is connected to a parameter controller 4 for controlling a parameter of the neural network 2 under a prescribed function relation with an output signal of the feature extracting device 5. In such a state, when an assembly of ignition patterns to be stored is determined, the ignition patterns are divided into groups in a lump, and with respect to the ignition patterns, a synapse matrix is constituted so that a chain of its direct product becomes cyclic. In such a way, the ratio of being led into a pseudo- storage at the time of storage recollection is decreased.
Patent JP-H0629404-A (JP)
Title: Manufacture of semiconductor device
Inventor: YAGI HARUYOSHI
IPC: H01L21/3205
Filed: 1992-07-13
Abstract: PURPOSE:To fabricate a semiconductor device so that the resistivity of alumi num wiring can be suppressed and so that the step coverage of the aluminum wiring in a contact hole can be enhanced. CONSTITUTION:A conductive layer 3 is formed on the surface of the substrate of a semiconductor device or on the substrate, an insulating film 6 is formed to cover the surface of the conductive layer 3, a contact hole 7 is formed so that the surface of the conductive layer can be exposed to the insulating film. Next, a barrier layer 9 containing high-melting-point metal is formed on a conductive layer so as to be exposed at least to the inside of the contact hole 7, and on the surface of the barrier layer 9 an amorphous silicon film 10 or amorphous germanium film is formed. Next, on the surface of the amorphous silicon film 10 or amorphous germanium film an aluminum-containing film 11 is formed, and amorphous silicon film or amorphous germanium film is made to be dissolved in the aluminum-containing film.
Patent JP-H0741626-A (JP)
Title: Poly(vinyl chloride) resin composition and packing material
Inventor: YAMAGUCHI MASAYUKI
IPC: C08L75/00
Filed: 1993-07-27
Abstract: PURPOSE:To obtain the title resin composition which comprises a poly(vinyl chloride) resin as a matrix and a polyurethane as a dispersion phase and is useful as a packing material because of its excellent compression set. CONSTITUTION:The objective composition has a phase-separation structure comprising (A) a poly(vinyl chloride) resin as a matrix and (B) a polyurethane as a dispersion phase where the tensile modulus of the component A is 9X10<5> to 8X10<7>dyne/cm<2> at 20 to 70 deg.C in the measurement of dynamic viscoelasticity and the ratio of compression modulus of the matrix phase to that of the dispersion phase is 0.4 to 1.8 at 70 deg.C.
Patent JP-2000021602-A (JP)
Title: Chip resistor
Inventor: MASATOKI TAMIJI
IPC: H01C7/00
Filed: 1998-06-30
Abstract: PROBLEM TO BE SOLVED: To easily distinction the upper or lower face of a resistor, and determinate whether a resistor exists or not in bulkily mounting by providing the resistor on a ceramic substrate with a body color which is formed by mixing ceramic raw material powder with a coloring pigment and firing it. SOLUTION: A ceramic substrate 1 is provided by mixing ceramic raw material powder with a coloring pigment and firing it. In general, the substrate is preferably an alumina substrate using alumina raw material powder, for example Al2O3 powder, at 94 to 96% of purity. Inorganic pigment of a metal oxide capable of hanging a ground color of the ceramic is used as the coloring pigment. A resistor layer 3 is provided on the ceramic substrate 1, a pair of electrodes are provided on both ends of the substrate 1 and an intermediate electrode 4 and an outer electrode 5 are formed on the surface of the electrodes 2 by a plating method. A protective layer 6 is also formed on the surface of the resistor layer 3.  Thereby, distinction between the upper end the lower faces of the resistor, and determination whether the resistor exists or not in mounting it can be facilitated without increasing the production cost including part and mounting costs.
Patent JP-S6245842-A (JP)
Inventor: SUEMATSU DAIKICHI
IPC: E03F3/04
Filed: 1985-08-23
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S5888200-A (JP)
Title: Preparation of single crystal of cu-zn-al alloy having shape memory
Inventor: KAYANE MIHARU
IPC: C30B29/52
Filed: 1981-11-20
Abstract: PURPOSE:To obtain a single crystal of the titled alloy having a large amount of shape memory, causing no intergranular cracking, by providing a Cu-Zn-Al alloy material having shape memory with a given strain, passing it through a furnace in the atmosphere of air at a fixed speed. CONSTITUTION:A Cu-Zn-Al alloy having shape memory is melted, forged, rolled, so that the casting texture is destroyed. The alloy is annealed at about 700- 750 deg.C to remove the strain, to give a uniform alpha+beta texture free from internal strain. The alloy material is provided with about 1-3% strain again, and it is removed. The alloy material is drawn up from the low-temperature side to the high-temperature side through an electric furnace having a temperature gradient in the atmosphere of air so that it is heat-treated gradually. A crystal grain starts to grow with the rise in temperature, the phase of the crystal grain is changed into the phase of the crystal simultaneously with the enlargement of the crystal grain and it becomes a single beta grain shortly. The pulling is stopped at this stage, it is kept for about 30-60min as it is, the subgrain is removed, it is made into a solution, to give a single crystal material of alloy having shape memory.
Patent JP-S6166583-A (JP)
Title: Controller of brushless motor
Inventor: TANAKA TADASHI
IPC: H02P6/06
Filed: 1984-09-06
Abstract: PURPOSE:To efficiently control to drive a brushless motor by advancing the phase angle between the induced electromotive force and the armature current of a motor to become zero. CONSTITUTION:An exciter 4 applies sinusoidal signals ex, ey to the stator windings of a resolver 2, and outputs a pulse train signal EQ1 having a period of T0/2 for the period T0 of the signals. A phase locked loop circuit 5 outputs a digital signal DS3 indicating the phase state of the detection signal e0 of the resolver 2. A pulse phase converter 6 increases or decreases the phase of the signal EP1 in response to a speed signal ETG or a torque command signal ET to output a pulse train signal EP5. A latch circuit 7 latches a digital signal DS3 by the signal EP5 to output a digital signal DS5. A memory 8 applies sinusoidal digital signals Du-Dw on the basis of the signal DS5 to sinusoidal digital signals Du-Dw to current command signal forming circuits 9-1-9-3.
Patent JP-2001008612-A (JP)
Title: Pizza crust having rice cake-like texture, and pizza
Inventor: MIYAZAWA HITOSHI
IPC: A23L35/00
Filed: 1999-06-30
Abstract: PROBLEM TO BE SOLVED: To provide a pizza crust having a rice cake-like texture while keeping a shortened crispy feeling at the outside, and a bread-like texture in the inside caused by the formed grains. SOLUTION: This pizza crust having a rice cake-like texture with 3,000-8,000 mm.g value corresponding to the energy for breakage in a tensile test by using a texture analyzer is obtained by including a modified starch and gluten. The raw material powder of the pizza crust preferably comprises 30-67 wt.% modified starch and 3-20 wt.% gluten. A pizza is obtained by baking the pizza crust.
Patent JP-S6432073-A (JP)
Title: Surge pump
Inventor: KAWAGUCHI KATSUYUKI
IPC: F03B13/12
Filed: 1987-07-27
Abstract: PURPOSE:To increase pump supply water quantity and head by taking a surge into each dissimilar piston installed in each cylinder of stepped cylinders free of slide motion. CONSTITUTION:A pumping plant 1 installed in a surge inlet part 3 of a caisson 2 has stepped cylinders 5, 5', dissimilar pistons 7, 7' a seawater suction port 10 and a seawater discharge port 11. These pistons 7, 7' are moved by energy of the surge, and they feed water with pressure via a discharge pipe 11, and when the surge goes back, these pistons 7, 7' move in the reverse direction by dint of suction action of the surge inlet ports 9, 9', whereby an inlet valve 12 is opened, thus water is attracted into the cylinder 5. Accordingly, utilizing wave energy, pump supply water quantity and head are increasable.
Patent JP-2000027015-A (JP)
Title: Shoulder pad
Inventor: HARA FUMIO
IPC: A41D27/26
Filed: 1998-07-01
Abstract: PROBLEM TO BE SOLVED: To obtain a shoulder pad capable of allowing an outer material to be readily produced in an accurate size, and improving the productivity. SOLUTION: This shoulder pad 10 having inner cotton 40 present between an outer material 20 and a lining cloth 30 is obtained by forming the outer material 20 out of right and left fragments 21, 22 symmetrical to each facing edge parts, overlapping the fragments 21, 22 so as to agree at the edge parts, welding the edge parts by ultrasonic welding, turning back the right and left fragments 21, 22 by centering the connecting line, and arranging the connecting line along the shoulder line of a pad.
Patent JP-H10341571-A (JP)
Title: Switching power supply device with power factor improvement function
Inventor: SATO MORIO
IPC: H02M7/12
Filed: 1997-06-06
Abstract: PROBLEM TO BE SOLVED: To simplify the circuit of a switching power supply with a power factor improvement function and, further, prevent a voltage applied to a switching device from being higher than a voltage applied to the switching device of a general switching power supply. SOLUTION: A reactor 5 is connected in series to the primary winding of a transformer and a diode 2 and a capacitor 1 which charge a voltage applied to a switching device 13 in the off-period of the switching device 13 are added to it. Further, an auxiliary winding 4 is added to the transformer so as to have charge stored in the capacitor 1 discharged through the auxiliary winding 4 in the on-period of the switching device 13. Moreover, a diode 3 which prevents a flyback current from being applied to the off-period of the switching device 13 is added.
Patent JP-H0527196-A (JP)
Title: Solid state image pickup element
Inventor: IIJIMA TAKASHI
IPC: H04N5/359
Filed: 1991-07-25
Abstract: PURPOSE:To converge incident light with efficiency and improve the sensitivity by forming a groove as a concave lens between adjacent convex lenses which have a larger refractive index than air. CONSTITUTION:The convex lenses 8 which converge the incident light are formed at positions facing photodetection parts 2 provided on a semiconductor substrate 1. Here, n0>=n1 holds for the refractive index n1 of a flattened layer 7 and the refractive index n0 of the convex lenses 8, so light which is made incident from the convex lens 8 having width (a) at the border between the both is converged on the photodetection part 2 like an optical path 11 without having its optical path changed. Further, the groove is provided between the adjacent convex lenses 8 to form the concave lens 9 in the flattened layer 7. The concave lens 9 has the same refractive index with the flattened layer 7 and light which is made incident on the concave lens 9 from the air above it is converged on the photodetection part 2 like an optical path 10 while the numerical aperture of a solid state image pickup element is increased equivalently almost to a unit picture element pitch C.
Patent JP-S6247243-A (JP)
Title: Transmission repeating installation
Inventor: FUKUDA MINORU
IPC: H04L69/14
Filed: 1985-08-24
Abstract: PURPOSE:To improve operability by providing a transmission box which can hold a handy-type terminal equipment, scanning each terminal equipment, building in a repeater circuit and a charging circuit, providing one connector to perform a transmission and a charging at every terminal equipment and modeling an installation in a plug-in type. CONSTITUTION:A transmission repeating installation 4 is connected between the handy-type terminal equipment (HT) and a data processor 2 and a communication adapter 3. The transmission repeating installation 4 is equipped with a signal multiplexer 41, a charger 42 and plural channels of connecting terminals 43 including both signal and a charging circuits, and is formed to be plug-in- connected simultaneously to plural HT1s through a connector 11. Also, a holder 21 and a connecting terminal 43 to plug-in the HT1 are provided on the installation 4. The multiplexer 41 builds in a microprocessor and a program and scans automatically each channel and when it detects the HT1 in which a transmission request is generated, it relays a transmission with the data processor 2 and progresses the scanning of the next channel after the transmission.
Patent JP-H0523341-A (JP)
Title: Ultrasonic probe
Inventor: KOISHIHARA YASUSHI
IPC: A61B8/00
Filed: 1991-07-25
Abstract: PURPOSE:To facilitate the obtaining of a clear ultrasonic tomographic image while eliminating fear of inflicting a pain on a patient by reducing the width of an ultrasonic probe to lessen the width of a contact part with a human body. CONSTITUTION:A negative electrode 11 is provided on the front and one side face of an ultrasonic vibrator 1 and a conductor 12 is formed on the one side end face as divided equally in terms of the thickness of the ultrasonic vibrator 1. Moreover, a conductor 13 is connected to the side of the conductor 12 and a conductor 7 is connected to a positive electrode 3 on the rear thereof. Thus, a dead space where no ultrasonic wave of the ultrasonic vibrator 1 is generated is curtailed to reduce the width of a tip as ultrasonic probe.
Patent JP-S57116981-A (JP)
Title: Combination faucet device
Inventor: MIYAZAKI SADAMITSU
IPC: F24J2/46
Filed: 1980-12-25
Abstract: PURPOSE: To simplify the piping of connection in a device, by selectively feeding hot water to the device from either a solar heat water heater or a hot water supplier source through the handling of a hot water supply handle.  
     CONSTITUTION: A valve part 25 is advanced to separate a valve seat part 31' from an O-ring 32' in a valve part 25 by handling a hot water supply handle 24, then a hot water source to a faucet A is switched to a water heater B, thus hot water stored in the water heater B passes through an inflow pipe line 27 of a return hot water inflow pipe part 26 via an outflow piping 34 and is guided to a faucet main unit 1. In the winter season or cloudy weather, the hot water source, supplying hot water to the faucet main unit 1 from a hot water supply line 22, is switched to an oil hot water supplier device C by handling the hot water supply handle 24, then hot water can be supplied, thus the piping of connection is simplified. 
     COPYRIGHT: (C)1982,JPO&Japio
Patent JP-H0349453-A (JP)
Title: Telephone set
Inventor: IZUMI MICHIHIRO
IPC: H04M1/02
Filed: 1989-07-18
Abstract: PURPOSE:To enter a data in a convenient time and to improve the job efficiency by utilizing an electronic notebook separately from a main body device to set the data. CONSTITUTION:The telephone set is provided with a connection means 2 connecting an electronic notebook 3 to a telephone set main body 1, a reception means receiving a data from the electronic notebook 3, a main body memory storing the received data and a mode setting means setting the operating mode corresponding to a data stored in the main body memory. Then the electronic notebook 3 being a separate device from the main body device 1 is connected to the telephone set, a data is received from the electronic notebook 3 and the telephone set is set in the relevant operating mode. Thus, many various data are set easily at any time by utilizing the electronic notebook.
Patent JP-S6246550-A (JP)
Title: Leadframe for semiconductor device
Inventor: IGARASHI TADASHI
IPC: H01L23/48
Filed: 1985-08-23
Abstract: PURPOSE:To realize an inexpensive lead frame capable of excellent adherence to low-meting glass by a method wherein a special aluminum coating is formed on the surface of the lead frame to be subjected to sealing by glass. CONSTITUTION:Distortion-free pure aluminum with a lattice constant d0 is caused to experience a thermal history same as that a package experiences during a thermal sealing process, whereby the lattice constant develops into (d). An aluminum coating layer wherein d/d0 is not more than 1.000 is applied to at least one side of the package sealing region. The diameter of a crystal grain in such an aluminum coating layer should be not more than 1mum and the degree of orientation 111 of the crystals in the aluminum coating layer not lower than 80%. Under these conditions, an aluminum coating layer 13 is formed on one side of a region corresponding to a glass seal region 12 of an aluminum lead frame 11. The aluminum coating layer 13 adheres strongly to low-melting glass and ensures excellent airtightness.
Patent JP-H0631759-A (JP)
Title: Manufacture of integrally molded product with skin
Inventor: SABUROMARU AKIRA
IPC: B29C43/18
Filed: 1992-07-14
Abstract: PURPOSE:To prevent effectively the surface of the skin from generating a blister. CONSTITUTION:A plurality of very fine vent holes 12a are formed into a skin material 12 molded into a fixed form. The molded skin material 12 in which the vent holes 12a are formed is set up within a press bottom force 34, on which a press molding resin material 36 softened by heating is put. Then the molded skin material 12 and resin material 36 are press-molded integrally and an integrally molded product 40 with the skin is manufactured.
Patent JP-H01150100-A (JP)
Title: Method of preventing storage of pressure of gas body
Inventor: IAN SUUIFUTO
IPC: F16K17/40
Filed: 1988-07-26
Abstract: PURPOSE: To realize staged pressure relief for protection against buildup fluid pressure by a pressure relief assembly having at least two frangible panel portions which burst at different pressures. CONSTITUTION: A first panel 26 has a somewhat U-shaped perforated line of weakness 38 defining a first frangible panel portion 40. A second panel 30 has a U-shaped weakness line 42 defining a second frangible panel portion 44. A substantially rectangular orifice 46 formed in the second frangible panel portion 44 has a first cross-section area. A third panel 32 has a substantially U-shaped weakness line 48 defining a third frangible panel portion 50. A substantially rectangular orifice 52 having a predetermined second cross-section area is arranged in the third frangible panel portion 50.
Patent JP-H0350737-A (JP)
Title: Manufacture of semiconductor device
Inventor: YAMAMOTO YUICHI
IPC: H01L21/322
Filed: 1989-07-18
Abstract: PURPOSE:To improve intrinsic gettering effect by performing heat treatment at a specified temperature range after heat treatment, in a manufacturing method, of a semiconductor device, having a process wherein a silicon semiconductor substrate is subjected to heat treatment at a temperature higher than or equal to 1200 deg.C. CONSTITUTION:A P-type silicon substrate 1 whose oxygen concentration in lattice is (1.3-1.7)X10<18>/cm<3> and whose specific resistance is 1-5CHI.cm is subjected to heat treatment at 1170 deg.C for 7 hours, at 600 deg.C for 20 hours, and at 100 deg.C for 7 hours, thereby obtaining a silicon substrate having a non-defective layer 2 and an inner defective layer 3 due to oxygen deposit. A silicon oxide film 4 is formed on the silicon substrate 1;. A window for diffusing impurity is bored in the silicon oxide film 4;. A diffusion source 5 containing antimony is spread. By performing heat treatment at 125 deg.C for 10 hours, an antimony diffusion layer 6 is obtained. By performing heat treatment at a temperature range of 900-1150 deg.C, deposition nuclei 7 are grown, and an inner defective layer 3A due to oxygen deposit is formed. Thereby IG effect can be obtained in any process of element manufacture, and the yield of an element can be improved.
Patent JP-S6342203-A (JP)
Inventor: JIEREMII EI RANDO
IPC: H01Q5/357
Filed: 1987-07-28
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-2001015697-A (JP)
Title: Semiconductor device and manufacture thereof
Inventor: SAITO TOMOHIRO
IPC: H01L21/822
Filed: 1999-06-30
Abstract: PROBLEM TO BE SOLVED: To suppress damage when machining a ferroelectrics film. SOLUTION: A TiO2 film 14 on an inter-layer insulating film 11 is processed with RIE to form a channel 15. After an SrRuO3 film is formed 70 nm, CMP is performed with the TiO2 film 14 as a stopper to remove an excessive SrRuO3 film on the TiO2 film 14, forming a lower part electrode 16 comprising the SrRuO3 film in the channel 15. A Pb (Zr, Ti)O3 film 17 is deposited 100 nm and then an SrRuO3 film 18 which is to be an upper part electrode is deposited 100 nm. After deposition an patterning of an SiO2 film for forming an upper part electrode formed in a region comprising a plurality of lower part electrodes 16, etching of the SrRuO3 film 18 in O3 water as well as dry-etching of the Pb (Zr, Ti)O3 film 17 in HCL solution or Ar and Cl2 are performed to form the upper part electrode 18, and then the SiO2 film is removed to form a capacitor.
Patent JP-S57112035-A (JP)
Title: Position sensing system
Inventor: NAKASHIMA MASAHITO
IPC: H01L21/60
Filed: 1980-12-29
Abstract: PURPOSE:To realize a reliable method for sensing an address by a method wherein video signals perceived by video pick up means concerning the externals and pattern position of a chip undergoing pattern formation are converted into binary signals and memorized for a proper travelling of an X-Y stage in a process of wiring a semiconductor chip by an automatic wire bonder. CONSTITUTION:A semiconductor chip 2 is placed on an X-Y stage 1 provided with a manual stage operating unit 4 and an X-Y stage driver 3. The externals of the chip 2 and the wiring pattern position are perceived by a TV camera 6 provided with a camera driver 7 and a monitor TV13. Video signals collected by the TV camera 6 are supplied to a binary circuit 8 for conversion into binary signals that are put into a pattern data memory 9 whose output is transmitted via an externals sensing circuit 10, a pattern position address arithmetic processing system 11, and a system controlling unit 5, to be stored in a memory 12. Data stored in the memory 12 are used to activate the operating unit 4 and the controlling unit 5 for the purpose of moving the stage 1 to a desired position.
Patent JP-S6165493-A (JP)
Inventor: MIYA YOSHIHIRO
IPC: H05K3/12
Filed: 1984-09-06
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6079829-A (JP)
Title: Code converting circuit
Inventor: KAWASAKI HIROTAKA
IPC: H03M7/16
Filed: 1983-10-06
Abstract: PURPOSE:To output a data having a content of correct binary code in response to a logical state change by providing a circuit latching the data of binary code according to the logical state change of the least significant bit of the binary code. CONSTITUTION:Although output data B0-B3 of a logical circuit 1 are changed when the content of output data G0-G3 of an absolute encoder of gray code output type is changed, the least significant bit B0 of the output data of the circuit 1 is changed last. Thus, when the output of the circuit 1 is changed completely into a code corresponding to the change in the gray code, one pulse is outputted from an exclusive OR circuit 4a of a pulse generating circuit 4 with a slight time delay. When a signal CS' is at H level in this case, an output of an AND gate 5 goes to H level and a latch circuit 3 latches the data B0-B3 at that time. When the signal CS' changes to L level, a latch data is outputted from output terminals O0-O3.