Patent GB-877768-A (GB)
Title: Improvements in or relating to electrical counting circuits incorporating junction transistors
Inventor: PEDDLE EDWARD ARTHUR RICHARD
IPC: H03K23/00
Filed: 1958-09-19
Abstract: 877,768. Transistor multi-stable state circuits. GENERAL ELECTRIC CO. Ltd. Sept. 3, 1959 [Sept. 19, 1958], No. 30092/58. Class 40(6) [Also in Group XIX] A counting circuit comprises a chain of at least three stages, each stage including a single junction transistor having a voltage from its collector-emitter circuit applied to the base circuit of every other transistor via a rectifier such that when any one stage is in a first conduction condition all the others are in a second conduction condition, means being provided for operating each stage in turn into the first conduction condition in response to successive input pulses. Fig. 1 shows a chain of four junction transistors arranged so that at any time only one is conducting. Assuming that 2a is the conducting transistor, its collector electrode is substantially at earth potential so that rectifiers 8b, 8c and 8d connected to the bases of transistors 2b, 2c and 2d respectively, maintain the other transistors non-conducting. A positive pulse applied to input terminal 15 will pass through capacitor 14a to render the first transistor 2a non-conducting. The collector electrode potential accordingly goes negative and this voltage change is applied through a capacitor 3b to the base electrode of transistor 2b to render the transistor conductive. The resulting earth potential at the collector electrode of this transistor is applied through rectifiers 8a, 9c and 9d to maintain the remaining. transistor non-conducting. The time constant of the input circuit including the capacitors 14 is sufficiently long to prevent the next stage being also triggered by the same input pulse. The counter may be reset to the state. in which transistor 2a is conductive by applying a pulse to the base of transistor 2a through a terminal 20. In an alternative circuit (Fig. 2, not shown). the input pulses are applied to the emitter electrodes instead of to the base electrodes and a rectifier is connected in series with each emitter electrode to maintain a high impedance for the input pulses. In addition the capacitors 3 are replaced by rectifier connections. Some saving in the number of rectifiers may be effected by arranging the transistors in groups. Thus in a six stage counter (Fig. 3, not shown) the base circuits of the first three stages are connected through individual rectifiers to a common point which is connected through individual rectifiers to the collector stages of the second three stages. The second three stages are similarly connected to the first three. In a further embodiment (Fig. 4, not shown) one input-terminal is connected to the odd number stages and another to the even number stages and the input pulses are applied to the input terminals in succession. This prevents false triggering and permits the time constant capacitors 14 to be dispensed with. It is also stated that the circuit may be arranged so that only one stage is non-conducting, or so as to be operated by negative input pulses and that the interconnection between the stages can be between emitter and base rather instead of collector and base.