Patent GB-981421-A (GB)
Title: Superconductive circuits
Inventor: ANDERSON JOHN LEANDER
IPC: G11C11/44
Filed: 1961-12-19
Abstract: 981,421. Superconductive circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 19, 1961, No. 45548/61. Heading H3B. A superconductor circuit comprises first and second paths each of material capable of exhibiting superconductivity and connected in parallel across a source and means for applying input pulses to the first path to divert current in discrete increments from the first path to the second. The circuits described form " learning " circuits, and may be used in computers which may be " taught " to solve problems, instead of being programmed. In Fig. 1, cryotron gates 20, 30 lie in parallel paths between current input terminal 14 and earth point 16. Gate 30 is in series with inductance 38, winding 22 on gate 20, and winding 52 on gate 50. The output circuit consists of cryotron gates 50, 54 connected to current source 58, gate 54 being connected to further cryotron gates 60, 64. Winding 62 on gate 60 is normally energized and winding 66 on gate 64 is unenergized. The output from gate 60 may be applied as an input to a further stage 80. Circuit 10 is set for operation by pulsing windings 32, 28 and 56 so that current flows only through gates 20 and 50 from the respective sources 14 and 58. If input pulses are now applied to in puts 42, 44, 46 to produce a current I x  sufficient to make gate 20 resistive, current I B  is transferred to gate 30. Inductance 38 is provided to lengthen the current transfer time constant so that only a portion of the total current can be transferred during the pulse. The circuit then settles to a new state with current I B  in gate 30, and in winding 22, and current I A  in gate 20. While gate 20 is resistive gate 50 is also resistive and current flows through gates 54, 64. If the output is to be applied to the next stage 80 winding 62 is de-energized and winding 66 is energized. The presence of current I B  means that an output can be obtained with a current smaller than I X , i.e. with smaller or fewer input pulses. Next time gate 20 becomes resistive I B  is further increased so that the circuit effectively learns to respond to successively fewer inputs. Current Ib may be arbitrarily increased, to increase the level of learning, by pulsing learn winding 24, or I B  may be reduced by pulsing forget winding 34. The rate of learning also depends on the magnitude or frequency of the inputs. Use of the device as an accumulator or adder is referred to. The circuit may be used as an AND circuit initially operating for n inputs, and subsequently for (n-1), (n-2) &c. A learning computer may consist of a number of such circuits, a set of input being applied to the input terminals. The response is observed by interrogating the output terminals, a change of response possibly occurring eachtime the inputs are applied. If successive responses show a desired trend certain of the learn windings may be energized to speed up attainment of the desired response. If an undesired response persists individual forget windings may be energized, possibly randomly, until the desired output is obtained. In Fig. 3 the diverted current increments are standardized. The circuit is set for operation by pulsing windings 266 and 232, and energizing bias input 260. Current from source 200 thus flows only through gate 210. When an input pulse is applied to winding 240 current I B  flows through gate 264 and opposes the bias current in winding 254 to allow gate 250 to conduct. Current is also diverted from gate 210 to gate 220, and flows through inductance 222, gate 250, winding 252 and winding 226. Inductance 224 is sufficiently large relative to the inductance of winding 252 to prevent current being established in 224 while the input pulse is applied. The current I T  through winding 252 increases to a valve just below I c , which would drive gate 220 resistive. When the input pulse ceases, current I B  stops flowing, gate 250 becomes resistive due to the bias current, and current I T  is transferred to inductance 224 as a standardised increment Is. Further input pulses add further increments I s  until the total current I 2  in winding 226 is sufficient to drive cryotron 230 resistive. The circuit is insensitive to input pulse width or height, above a certain minimum. The circuit may be used as a decimal counter if the increment I s  is one-tenth of the critical current of gate 230. The cryotrons in both embodiments are preferably of film-type.