Patent GB-1264023-A (GB)
Title: Frame synchronisation system
IPC: H04J3/06
Filed: 1969-11-25
Abstract: 1,264,023. Multiplex pulse code signalling. INTERNATIONAL STANDARD ELECTRIC CORP. 25 Nov., 1969 [4 Dec., 1968], No. 57627/69. Heading H4L. The time division multiplex P.C.M. frame synchronizing system disclosed in Specification 1,264,024 is modified to reduce the search time by the addition of a shift-register storing the cumulative function of previous signal samples to provide a control signal for the adustment of the locally generated timing signals. In the system described, Fig. 2, the frame rate is 8 kc./s. and the synchronizing code is of the distributed type consisting of binary 1 and binary 0 in adjacent frames. Bit rate pulses from clock 3 are supplied via an INHIBIT gate 5 to a timing signal generator 6 including binary counters. Circuit 6 produces a 4 kc./s. reference squarewave REF which is supplied to an EXCLUSIVE OR gate 7 together with the input signal, the output MMF of gate 7 being binary 1 only if the two inputs do not coincide. A synchronization bit signal ST having a constant width of one clock period and a halt time signal HT having a variable width equal to the width of the HALT pulse from a gate 22 plus the width of one clock period are also produced as in the previous arrangement and an additional shift register timing signal SH is produced having a variable width of N clock periods plus the width of the HALT pulse. The signal MMF is supplied directly and via an inverter 10 to a bi-stable 8 which is triggered by a signal MT from an AND gate 9 supplied with the clock signals from 3 and the signal ST. The output of bi-stable 8 is supplied to a decision circuit 11 comprising a Miller integrator whose output is compared with a reference voltage and co-operating with AND gate 22 and INHIBIT gate 5 as in the previous arrangement. The output of gate 7 is also supplied via an OR gate 12 to the "1" input of the first stage B N  of the N + stage shift register 18 and via an inverter 15 to the "0" input, the register 18 being triggered by pulses SHC from an AND gate 13. Signals SH and ST are supplied to an OR gate 14 whose output is supplied to the AND gate 13 together with the clock signals from 3. The output of register stage B N  is supplied to an AND gate 16 whose output is coupled to stage B N-1  of the register directly and via inverter 17, the other output of gate 16 being supplied by AND gate 22 via an inverter 21. The output of register 18 is supplied to an AND gate 19 which is enabled via an inverter 20 only when the signal ST is in the binary 0 condition. This enables all but the first of the N + 1 previous samples of signal MMF to be shifted through AND gate 19 and supplied via OR gate 12 to provide a cumulative function of the signal MMF of each frame which is stored in turn in the register 18 under the control of signal SHC which includes N+1+H consecutive clock pulses per frame where H is the number of clock pulses blocked by the HALT signal from gate 22. The output of AND gate 22 is supplied via inverter 21 to the AND gate 16 so that in the absence of a HALT signal the information is shifted normally through the register 18, the bits of information returning to their original position each frame period, and normal counting proceeds at 6. The information bit, originating from stage B 0 , however, will be inhibited by AND gate 19 since signal ST will be in its "1" condition when the counters at 6 are at 0. When a HALT signal occurs at the output of AND gate 22, gate 16 is disabled and a zero condition is shifted into stage B N-1  which after it is shifted out of stage B 0  is OR gated at 12 with new information MMF, the H additional pulses of signal SHC causing the information to be shifted H additional positions in the register. This is repeated until the H right-hand positions of the register contain H new bits of signal MMF. Figs. 10A to 10C show the operation of shift register 18 assuming that N=8, a mismatch being stored as "1" and a match as "0" as indicated by the output of OR gate 12. As shown in Fig. 10A, in the stored information labelled "previous frame", the first "0" indicates a match so that AND gate 22 is not activated and there is no halt signal. One frame period later these stored signals are supplied via OR gate 12 together with the signal MMF labelled present frame from gate 7, the output of the OR gate 12 being shown as OR function. As the OR function is generated it is used to control through stage B N , and gates 22 and 5 the counters of circuit 6. Provided that the other signals ST, SHC, HT &c. are in the "1" state the first two "1's" (reading from left to right) of the OR function will halt the circuit 6 for two bit periods as shown in Fig. 10B. This causes two bits circulating in the register to be reset to zero and two additional samples (01) from gate 7 to be shifted into the register. The correct phase is now assumed to be the third column because of the HALT pulse of two bit periods and one frame later the OR function is generated as indicated in the bottom three lines of Fig. 10C. This causes a halt for five bit periods, five bits are reset and five new samples are stored. In this example, the first halt was caused by mismatch samples from the present frame, but the second halt was caused by a mismatch from a sample stored two frames previously, thus considerably speeding the synchronization search. The system may be adapted for lumped type code or a combined lumped and distributed code in the manner disclosed in Specification 1,264,024.