Patent GB-1072379-A (GB)
Title: Apparatus for reversibly reducing trains of data signals
IPC: G06F3/00
Filed: 1965-10-15
Abstract: 1,072,379. Electric selective signalling; data processors. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 15, 1965 [Oct. 26, 1964], No. 43920/65. Headings G4A and G4H. Control code bits are derived from an input signal train and assembly with selected portions of the input train to constitute an output train which is reversibly reduced equivalent of the input train. Words of 24 parallel bits each are passed in turn from a computer into and out of 26-stage buffer registers (142, Fig. 7B) selected in turn by read-in and read-out counters. The other two bit-positions of each register receive ND (no data) and LD (lost data) bits to indicate whether or not adjacent words have not been supplied by the computer and been lost due to the reduction system being unable to operate quickly enough, respectively. Encoding means (3) receives data words from the buffer registers and compares the six 4-bit bytes of each with the corresponding bytes respectively of the preceding word, producing a PC (primary code) bit for each byte pair which is 1 if they are equal and 0 if unequal. The six PC bits for each word are considered to form two 3-bit PC bytes, and the two such bytes relating to a given word are compared with the corresponding such bytes, respectively, for the preceding word, to produce an SC (secondary code) bit in each case which is 1 if the two PC bytes are equal and 0 if unequal. For each word, 4-bit bytes are constituted as follows in assembly means (4): (a) the ND, LD and SC bits, (b) the first three PC bits and a " don't care " bit, (c) the other three PC bits and a " don't care " bit, (d)-(i) the 24 data bits of the original word in 4-bit bytes. Byte (a), those if any of bytes (b) and (c) not indicated as redundant by the corresponding SC bit being 1, and those of bytes (d)-(i) not indicated as redundant by the corresponding PC bit being 1, are passed in turn into respective consecutive 4-bit segments of an assembly register (50, Figs. 4, 5 and 6) by a counter. Concurrently a format register (52) receives bits to mark those 4-bit bytes which comprise a " don't care " bit or have an LD bit equal to 0. The contents of the assembly register (50) are passed under control of counters to a tape buffer register (114, Fig. 6) without gaps, one of the counters being controlled by the format register (52) to delete the first bit from each 4-bit byte marked by the format register (see above). The contents of the tape buffer register are gated in 6-bit bytes by a counter to a magnetic tape store, a parity bit being appended to each byte. A block of words thus recorded in reduced form on the tape is preceded and followed by several blank bytes (without parity) and followed by count bytes indicating the number of words in the original unreduced block. The input data from the computer may represent programmed instructions, output for debugging purposes. A computer programme algorithm is described for reconstituting the original data, and incorporates a check on the number of words (utilizing the count bytes), and a recognition of any erroneous 4-bit byte consisting of LD and ND bits 1 together with SC bits not both 1. The two-level scheme above (using primary and secondary codes) may be extended to further levels. Punched tape for input to and output from the system is mentioned as an alternative.