Patent GB-1050591-A (GB)
IPC: G11C19/06
Abstract: 1,050,591. Circuits employing magnetic storage devices. WESTERN ELECTRIC CO. Inc. May 14, 1963 [May 21, 1962], No.18992/63. Heading H3B. [Also in Division G4] Each stage of a magnetic shift register consists of a bridge lattice network with input and output terminals coupled to the respective diagonals, the bridge lattice consisting either of electrical conductor arms with a separate magnetic storage core coupled to each arm, or an equivalent magnetic circuit constituted by the various limbs of one or two multiapertured storage cores with associated windings. The cores or limbs are switched in pairs by an input signal consisting of two pulses of alternate polarity, the first pulse switching two cores or the flux in two core limbs, while the second pulse switches the two remaining cores or limbs. An output signal in the same form as the input signal is obtained by the use of two successive pulses, the first pulse resetting one core or limb of each pair and the second pulse resetting the remaining cores or limbs. First embodiment, as shown in Figs. 1 and 2 in which Fig. 1 shows only the transfer current paths and Fig. 2 the complete circuit, input terminals 12, 13 and output terminals 16, 17 of the shift register are linked by bridge lattice networks each of which includes a magnetic storage core a-d, two adjacent lattices such as section 1 and section 2 forming a single register stage. The cores a and b are substantially smaller than cores c and d, the ratio of the respective path lengths being in the order of 1 : 4. Alternative bias arrangements are shown and comprise either continuous bias B applied to the larger cores c and d of each section, continuous bias B<SP>1</SP> applied to all cores, or pulsed bias applied sequentially in the order B1-B4 to various groups of cores. In each case the cores are biased to the threshold of the ' 1 ' switching state. Fig. 1 shows a ' 1 ' value stored in the first stage (clockwise arrows in first section cores) and an '0' value stored in the second stage (anticlockwise arrows). Shifting of data through the register is effected by cycles of 4 pulses applied in turn to windings S1-S4. With data stored in the first section of the register as shown, the first shift pulse in windings S1 switches cores a 1  and b 1  to the ' 0 ' state, the induced currents in conductors 10 and 18 returning through the lattice conductors 18 and 19 of section 2 and switching cores a 2  and c 2  to state ' 1 '. The second shift pulse in windings S2 switches the remaining cores c 1  and d 1  of the first section to state ' 0 ', and in this case the induced currents circulate through the lattice conductors of section 2 in such a direction as to switch cores b 2  and d 2  to the ' 1 ' state, the switched cores a 2  and C 2  being prevented from resetting by the bias. Similarly the third and fourth shift pulses applied to windings S3 and S4 transfer the state ' 1 ' registered in section 2 to section 3. In a modification, Fig. 4 (not shown), a separate information write-in winding passes through the cores C 1  and d 1  of the first section. Second embodiment. Multiaperture cores 27, 28 are used in Fig. 5, a single core being provided for each section. The cores are biased towards the ' 1 ' threshold as in the previous embodiment. The input conductors 10<SP>1</SP>, 11<SP>1</SP> form a winding which magnetises the core branches A 1 , B 1  of section 1, and the coupling winding to the next section is formed by conductors 1011, 11<SP>11</SP> coupled to fluxes passing between core branches C 1  and D 1 . Information write-in to the section is applied from terminals 20, 21 to core branches C 1  and D 1 . The directions of the arrows in the various core branches denotes the flux distribution when an ' 0 ' is stored. The arrow directions are all in the clockwise sense when a ' 1 is stored, i.e. when the information write in winding is pulsed the direction of flux in all the core branches reversed. When a ' 1 ' is written into a core the flux reversals are parallel to the coupling winding and no output is induced in this circuit. Data is transferred by sequentially energizing windings S1 to S4. No-flux reversals occur if an 0 ' is stored. If a ' 1 ' is stored in section 1, the first shift pulse S1 reverses the direction of flux in core branches A1 and B1, thus inducing an output pulse which reverses the flux in branches B2 and D2 of section 2. The next shift pulse S2 reverses the direction of flux in core branches C 1  and D 1  and so restores section 1 to the ' 0 ' state. An output pulse is again produced which switches the flux in branches A2 and C2 of section 2, the second output pulse being of reverse polarity to the first. Due to the bias the other core branches remain in the ' 1 ' state. In the second section as the flux changes take place firstly in the loop formed by branches B2, D2, and secondly in the loop formed by branches A2, C2, no flux changes occur which would induce an output in the next coupling winding. Subsequently the stored data is transferred from section 2 by pulses S3 and S4. Third embodiment. Separate multiaperture cores 29-32, Fig. 6 are used, two cores being provided for each section. The direction of the core fluxes for a stored ' 0' is shown by arrows in the figure. The cores are biased towards the ' 1 ' threshold as in the other embodiments. A ' 1 ' is written in by a pulse on conductors 20, 21 which reverses the innermost flux of the section 1 cores, i.e. the flux through core branches a<SP>1</SP> 1  and b<SP>1</SP> 1  is reversed. As the coupling windings 33, 36 are linked with saturated core branches e 1 , f 1  in which the flux directions are unchanged no output is produced. Shift pulses S1 to S4 are applied sequentially. Pulse S1 reverses the fluxes in core branches a<SP>1</SP> 1 , e 1  and b<SP>1</SP> 1 , f 1  if a ' 1 ' is stored in the section, and induced outputs are obtained in windings 33, 36 which switch the innermost flux in core 31, i.e. the flux in core branch a<SP>1</SP> 2  is reversed. The next shift pulse S2 resets the cores 29, 30 to the ' 0 ' state and induces an output of opposite polarity which sets core 32 to the ' 1 ' state without changing the ' 1 ' state previously established in core 31. Subsequent shift pulses S3 and S4 transfer the stored data to the next sections. Modifications. In Fig. 7 (not shown) several loads are connected to the output of the register through a transformer. Fig. 8 shows a modification of Fig. 1 in which the storage cores a 1 -d 1  serve additionally as transformer cores to produce gain. An alternative is shown in Fig. 9.