Patent SE-326467-B (SE)
Inventor: LUCKY R
IPC: H04L25/03
Filed: 1966-04-14
Abstract: 1,134,058. Transversal equalizers. WESTERN ELECTRIC CO. Inc. 14 April, 1966 [14 April, 1965], No. 16359/66. Heading H4R. The multipliers in a transversal equalizer, used in a system which gives distortion such that the sum of the time spaced samples of the components other than the main component is greater than the main component itself, are adjusted by apparatus using a test signal transmitted over the system in which odd pulses of the test signal are fed through the equalizer, consisting of a tapped delay line with multipliers adjustable from - 1 to + 1 connected to its taps, time spaced samples are taken, and, if the samples are of greater than a predetermined value and of a given polarity, then a polarity inverter is inserted in the respective tap to oppose the distortion of the sample. The multipliers of the equalizer, other than at the reference or central tap, are then shunted out and the succeeding even pulse is fed through the equalizer, and such inverters as were inserted in the previous step, and the polarities of time spaced samples are determined and used to adjust the corresponding multipliers, by discrete steps in a direction in opposition to the detected polarity. The process is repeated for successive pairs of pulses to reduce the distortion components to an acceptable value, the inverters being shunted out on odd numbered test pulses and the multipliers shunted out on even numbered test pulses. Fig. 1 shows the system including a transversal equalizer comprising a delay line 14 with multipliers C-1, C0, and C+ 1 connected to taps- 1, 0, and + 1 with additional taps - 2 and + 2 and inverters I - 2, I-1, I+1, and I+2 which are used only during the setting up operation. Under data transmission conditions test relay 22 is unoperated so that all the inverters are out of circuit and the effective circuit is the normal transversal equalizer circuit, Fig. 4 (not shown). When the line is first taken into use it is set up using test pulses from source 10, with switch 23 closed to operate relay 22, the detached contacts of which are shown as crosses for make contacts and bars for break contacts. The first test pulse to arrive at the receiver operates bi-stable 20 to its " 1 " state to operate relay 21 and also operates bi-stable 27 to allow pulses from clock 26 to step on counter 29 at a rate equal to the normal digital data transmission rate which has a period equal to the delay T of the equalizer line elements. Operation of relays 21 and 22 put the equipment into condition for receiving "odd" test pulses, Fig. 2 (not shown), i.e. the transversal equalizer is connected as for normal reception but its output is connected to a slicer 18 which gives an output dependent of the polarity of its input, and this signal is fed in to the first stage of shift register 30. As the principal value of the test pulse progresses down the line 14 so the corresponding polarity samples are fed down the stages of the shift register 30 until the principal value of the test pulse reaches + 2 in line 14, the shift register is full, and the count of counter 29 is completed. Completion of the count of counter 29 produces a signal on line 33 to operate gate assembly 19 so that relays R - 2, R - 1, R+1, and R+2 are operated in accordance with the pattern stored in the shift register 30 so that the corresponding inverters can be inserted in the appropriate equalizer stages to tend to oppose the distortion products at those stages. The system then awaits the succeeding " even " test pulse which, when it arrives, sets bi-stable 27 once again, to allow the count to begin, and triggers bi-stable 20 to release relay 21 and put the equalizer into the condition for receiving " even " test pulses, Fig. 3 (not shown), where the multipliers are taken out of circuit leaving inverters in those places where they were inserted on the previous step. The " even " pulse then proceeds down the equalizer line and time spaced samples appearing on the summing bus are applied to the slicer 18 and corresponding signals are fed from the slicer into shift register 31. When the test pulse reaches the end of the line 14 and the count of counter 29 is complete an output on line 33 resets bi-stable 27 and enables gate 19 which allows the signals in shift register 31 to adjust the corresponding multipliers on the delay line taps to be adjusted one incremental step in the direction to reduce distortion components. The multiplier on the central, reference, tap is not adjusted in this fashion but may be adjusted, as described in Specification 39326/65 to standardize the principal component of the test pulse. The process of inserting inverters and adjusting multipliers on respective successive test pulses continues until the residual distortion is within one half step of the incremental adjustment provided on the multipliers, when switch 23 is opened, allowing relay 22 to release and put the system back into its normal reception condition, Fig. 4 (not shown), and switch 12 is operated to allow data transmission to commence. Switch 23 may be operated manually or automatically in response to a predetermined signal transmitted to the receiver. During adjustment of the multipliers on the " even " pulse cycle a multi level slicer may be used at 18, and the shift register expanded to accommodate more levels, so that the multipliers may be adjusted by multiples of the incremental step.