Patent GB-1270596-A (GB)
Title: Range finder circuit
Inventor: FRAZEE JEROME A
IPC: G02B7/32
Filed: 1969-07-03
Abstract: 1,270,596. Automatic focusing; transistor zero-crossing detector; synchronous detector. EASTMAN KODAK CO. 3 July, 1969 [9 July, 1968], No. 33567/69. Headings H3A, H3T and H4D. Specification describes a rangefinder circuit particularly for use with an automatic rangefinder and focusing apparatus of the type described in Specification 1,270,597, and comprising first and second photo-sensitive transducer means 32, 34, Figs. 2 and 3, arranged in spaced relationship and adapted to receive reflected amplitude modulated light from the subject 5 at the unknown distance the range distance being determined by triangulation when the setting of the rangefinder causes the transducer means to be equally illuminated; differential amplifier means 50 receiving the transducer outputs to produce an amplified A.C. difference signal, Fig. 4A, devoid of ambiant light interference; split phase amplifier means, 76, Fig. 4, producing antiphase versions, Figs. 4A and 4B, of said difference signal; means (e.g. modulated light source 36, Fig. 2, apertured mirror 42, photo-transistor H 3  and push-pull limiter amplifier 52) to produce two reference signals S 1 , Fig. 4C, and S 2 , Fig. 4D, in antiphase and synchronous with the modulation signal; full wave synchronous detector means 96, receiving the signals of Fig. 4A and Fig. 4B and the reference signals of Figs. 4C and 4D to produce the full wave rectified derivative Fig. 4E, of said difference signal; detector means 120 to derive the D.C. component A, Fig. 6, of said signal 4E said D.C. component having positive and negative polarities when transducers 34 and 32 are respectively illuminated and exhibiting the sought after cross-over point of time to when the two transducers are equally illuminated; and logic circuit means 56 and Fig. 5 to produce a pulse D, Fig. 6, on detection of said cross-over. The full wave synchronous detector means 96 comprises two field effect transistors 98/100 each having a source 106/112, a gate 104/110, and a drain 102/108 the respective sources being connected to receive the antiphase signals Figs. 4A, 4B, the respective gates being connected to receive the synchronous pulse signals 51, 52 and the drains being connected in common to provide the full wave signal, Fig. 4E. The logic circuit means comprises first 168, second 170, third 148, fourth 164 transistors, a resistor 174, a capacitor 154, Zener diode means 174, a silicon controlled rectifier means 178 having a gate electrode, the capacitor 154 being connected to receive the D.C. component signal A and being coupled to the base of the first transistor 168 through said resistor 174 to provide an RC time delay for the first transistor 168, the first and second transistors 168, 170 having their emitters in common, the base of the second transistor 170 being connected to the collector of the first transistor 168, the collector of the second transistor 170 being connected both to the collector of said third transistor 148 and to the base of the fourth transistor 164, the base of the third transistor 148 being coupled to said D.C. component signal so as to reverse bias its base/emitter junction when said signal passes through zero, the fourth transistor 164 having its base connected to the collector of the third transistor 148 and its emitter connected to the cathode of the Zener diode means 176, the anode of the Zener diode means being connected to the said gate electrode, whereupon when said component signal goes positive, the capacitor 154 charges to a higher potential, turning on the first transistor 168 (the second transistor 170 turning off) whereby when said component signal passes through zero, the third transistor 148 turns off, the base of the fourth transistor 164 following the potential of the collector of the third transistor 148, and an output control signal D is applied to the said gate electrode to enable rectifier means 178 whereby current can pass through relay coil 58 to activate focus indicating means.