Patent GB-1537504-A (GB)
Title: Network computer system
IPC: G06F17/13
Filed: 1976-01-22
Abstract: 1537504 Solving difference equations PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 22 Jan 1976 [25 Jan 1975 16 June 1975] 02483/76 Heading G4A A computer system for solving difference . equations involving N unknown quantities includes N processors 2 (Fig. 1) arranged in a matrix 1 in two groups S and W such that each is connected only to neighbouring processor of the other group, each group being connected by a common instruction bus 4, 5 and a common data bus 8, 9 to a control computer 7. As described the computer 7 is connected to the matrix by a control unit 3 and shift register type buffer 6 which is of sufficient capacity to supply data to and accept data from all the processors of the first row of the matrix in parallel. A second buffer may be provided to feed that data directly from the last row of processes to the computer 7 (Fig. 8, not shown). The matrix may be a 1 x m, n x 1, or three-dimensional matrix and in the latter case the buffer store may be two-dimensional.  Control unit (Fig. 2, not shown).-This includes a program store (21) to which the program for solving an equation is transferred by the computer 7, three instruction decoders (22; 23; 24); for decoding instructions for buses 4, 5, 8 and 9 and a switching matrix (25). Processor (Fig. 3, not shown).-Each processor includes an instruction register (34) connected to a store (32), arithmetic and logic units (33) and an accumulator (31), the accumulator having an input to and an output from other processors.  Instruction Decoder (Fig. 4, not shown).-Two of the decoders (22, 23) include an address register (41) for the programme store with an incrementer connected between its output and input, a command register (42) receiving the addressed instruction and a decoder (43), outputs of which are connected to the address register (41) and registers (44, 45, 46) applying data to the switching matrix (25) to establish a data path from the switching matrix (25) and conduct information to the third decoder (24) respectively. The third decoder (24, Fig. 5, not shown) includes registers (57, 55) connected to the other two decoders (22, 23) and a register (56) connected to a convergence logic unit (26, Fig. 2, not shown). The convergence logic comprises two bistables (71, 72, Fig. 7, not shown) controlled by the lines 8, 9 connected at inputs to an AND gate (73) also receiving an interrogation input from the third decoder (24). Solution of a differential equation.-To solve a differential equation of the form it is converted into a system of difference equations of the form such an equation existing for each grid point ij. The computer 7 calculates the coefficients L ij , R ij , T ij , B ij , G ij  for all grid points and these are fed to their associated processor via a buffer store 6 by transferring the contents to the accumulators of a row i of cell to the accumulators of the next row i=1, all the coefficients L ij  being followed by all the coefficients R ij , &c. Relaxation parameters #, there being a pair for each iteration step, are then fed to the buffer store. Each iteration step comprises two half steps, in the first of which each processor of group S calculates a new status on the basis of its old status and the status of its neighbouring processors of group W and each processor in group W tests for convergence and in the second of which of these operations are interchanged. When the convergence logic unit indicates that convergence has occurred in two successive halfsteps, the status values stored in the processors are transferred to the control computer and iteration is complete.