Patent GB-1157126-A (GB)
Title: Process for obtaining a Monitoring Quantity for Automatically Removing Pulse-Distortion
IPC: H04J3/10
Filed: 1966-10-06
Abstract: 1,157,126. Transversal equalizer adjustment system. PATELHOLD PATENTVERWERTUNGS- & ELEKTRO HOLDING A.G. 6 Oct., 1966 [8 Oct., 1965], No. 44625/66. Heading H4R. In an arrangement for automatically adjusting the multipliers of a transversal equalizer an estimate of the distortion present in the equalized signal is derived by multiplying the instantaneous values of the output signal of the equalizer by the sign of the instantaneous values of the output signal shifted in time by a predetermined amount. Fig. 3 shows an equalizer including a tapped delay line L1 whose multipliers V-2 to V2 are set in accordance with the distortion measurements obtained by multiplying the signal at the taps of a second delay line L2 with the signal En derived from the centre tap of L2, after that signal has been amplitude dichotomized, or zero clipped, in B. The multiplied signal is integrated to produce a signal Vk which is dependent on the distortion present at a time relative the main pulse equal to the time spacing between the two signals multiplied together. The effects of genuine signal pulses occurring at the time for which the distortion is being measured are eliminated by the integration since, provided the signal pulses are uncorrelated, the integral of the signal pulses at that time will be zero. The distortion signal is applied via switch S2 to the appropriate level control circuit P-2 to P2, the switch S2 being ganged with the delay tap switch S1. A number of modifications of the basic circuit are described in which; Fig. 4 (not shown), the line section used for post pulse interference cancellation is also used for delaying the signal in distortion assessment, or, Fig. 5 (not shown), the whole of the line used for compensation is used for distortion assessment, while in Fig. 6, a two section line L1 is used for both pre-pulse and post-pulse distortion cancellation with the line L2 used for distortion assessment, and modifications of this arrangement are described in which the limiter B is provided in the common line to the multipliers U, Fig. 6a (not shown), or the same line is used for distortion assessment as is used for distortion cancellation. Fig. 6b and 6c (not shown). Assessment of cross-talk occurring between two transmission channels may be made by equipment as shown in Fig. 7, in which the output of each channel is fed through a respective line L<SP>1</SP>2 or L<SP>11</SP>2 and delay distortion in each channel is determined in the manner described above to obtain the values V<SP>1</SP>-2, V<SP>1</SP>-1, V<SP>1</SP>1 and V<SP>1</SP>2 &c., while cross-talk between the channels is determined by multiplying together amplitude dichotomized signals from one channel with signals from the other channel, some of which are time displaced, to give the assessments W<SP>1</SP>0, W<SP>1</SP>1, W<SP>1</SP>2, &c. Again a modification is described, Fig. 8 (not shown), in which the same lines are used for compensation as are used for distortion assessment. If the transmission system introduces low frequency distortion, e.g. loses the D.C. level, the 1.f. distortion may be corrected before the time delay distortion is assessed and the assessment used to adjust a transversal equalizer provided before the 1.f. distortion correction, Fig. 9 (not shown). Alternatively as shown in Fig. 10, the multipliers B may be fed with mixed signals X2, X1 &c., on one input in order to compensate for the correlation introduced into the signal by the 1.f. distortion. Adjustment of transversal equalizers may be accomplished using apparatus as shown in Fig. 13, in which the signal V from the distortion assessment multiplier U controls the frequency of a generator G which feeds a counter Z whose direction of counting is controlled by the polarity of the signal V. The counter stage outputs are arranged to control the switching in of the resistors R1 to R5 whose values are arranged in binary progression on one input of a differential transformer T to the other input of which a resistor R o  is connected. The common point of the resistors is connected to a tapping Dn + K of the transversal equalizer delay line while the differential transformer output is connected to the summing line of the transversal equalizer. It is suggested that the signal feed to the equalizer system might be put into digital binary coded form so that pulse stores might be used instead of delay lines and logical digital circuits used instead of analogue circuits.