Patent GB-1231570-A (GB)
IPC: G06F12/08
Filed: 1969-10-22
Abstract: 1,231,570. Data storage: data processing. INTERNATIONAL BUSINESS MACHINES CORP. 22 Oct., 1969 [14 Nov., 1968], No. 51663/69. Headings G4A and G4C. A data processing system includes a processor, a random access slow speed main memory (e.g. cores) comprising a plurality of interleaved memory modules including a plurality of sets of blocks of word locations, the word locations within a block being resident in different successively addressable memory modules, a random access high-speed buffer memory including a plurality of sets of blocks of word locations, the sets of the two memories corresponding whereby a given word from a given set in the main memory can reside in any one of the blocks of the corresponding set in the buffer memory, and a processor fetch request supplying to the processor the required word from the buffer memory if it is there and causing the word to be transferred to the buffer memory from the main memory if it is not. In the latter case the word is supplied to the processor direct, as well as being inserted into the buffer memory, and is followed into the buffer memory by the other words of its main memory block, serially by word. The block is placed into one of the blocks in the buffer memory set corresponding to the main memory set and a data directory (random access high-speed store) location corresponding to the buffer memory block and set location receives the block portion of the original address. When a fetch request arrives, whether the required word is in the buffer memory is discovered by comparing the block portion of the required address with the block address portions stored in the part of the data directory corresponding to the set portion of the required address, equality causing the appropriation location in the buffer memory to be accessed (the original address supplying the set and word portions of the address for this and the block portion depending on which of the comparisons gave equality). However this accessing only occurs if a valid bit associated with the data directory entry giving equality is set. In this case a location in a random access store called the chronology array, addressed by the set portion of the address is updated to reflect the order of fetching from block locations of the buffer memory. When a particular set of the buffer memory is full and another block is to be transferred into it, the fourth most-recently fetched-from block is replaced (there are four blocks per set in the buffer memory). Processor store (i.e. write) requests are dealt with similarly to fetch requests. I/O channel store and fetch requests, which go to the main memory, cause resetting of the appropriate valid bit if the required word position is also in the buffer memory, so that a subsequent processor request relating to this block will have to go to the main memory. When a block is transferred from main to buffer memory there is a delay due to the relatively slow speed of the main memory and this can be used to permit further store or fetch requests to access the buffer memory. If one of these requires a further block to be transferred, signals to access the main memory modules involved in this way may be sent as soon as those for the first block have been sent and this can be done without conflicting requests to the same module. A transfer address register stack, a storage data buffer stack, a storage address register stack and a timer control push-down stack are provided. As described, the main memory has 32 modules arranged in two banks and interleaved 16 ways, providing 64 sets of 1024 blocks of 8 words, successive words of a given block being in successive modules (and having successive addresses, hence the " interleaving "). The buffer memory has 64 sets of 4 blocks of 8 words.