Patent GB-770616-A (GB)
Title: Improvements in or relating to electronic switching circuits
Inventor: HARRIS LIONEL ROY FRANK
IPC: H03K5/15
Filed: 1950-12-21
Abstract: 770,616. Electric digital-data-storage apparatus. POSTMASTER GENERAL. Sept. 4, 1952 [Dec. 21, 1950; Dec. 21, 1950], No. 31138/50 and 31139/50. Class 106 (1). [Also in Group XXXIX] A two-position trigger circuit comprises a pulse source feeding a D.C. operated gate whose output pulses after power amplification are rectified to provide the D.C. operating potential for the gate, such triggers may find use in digit storage devices. As shown, Fig. 8, a recurring series of pulses on lead I are applied to the gate circuit C1 whose output passes through the (optional) gate circuit C3 and the amplifier A to the coincidence circuit C2. Coincidence between the amplified pulse and the pulse on lead I causes C2 to emit a pulse to the rectifier or pulse lengthener circuit PL whose D.C. output maintains the gate C1 open. The gate is triggered to its operative state by the injection at any suitable point such as T1, T2 or T3 of a pulse coincident with the pulse 1. An inhibiting gate, not shown, may be included in the circulation path or the lead I to which an inhibiting pulse coincident with the pulse on lead I may be applied to restore the trigger to normal. Indication as to the condition of the trigger may be obtained either by a D.C. output over lead V or by the presence or absence of a pulse train on lead 01. It may be required that the output over 01 shall consist only of pulses coincident with pulses of a second series. The gating circuit whose lead I<SP>11</SP> is fed with the second series of pulses is included for this purpose. In a modification, Fig. 9, the gates C1 and C2 are fed with different sources of pulses, the pulses on the lead 1<SP>1</SP> feeding gate C2 being delayed by a time t relative to the pulses on lead I. In this case a delay line D introducing a. delay t is introduced to delay the pulses from I so that they may coincide with those of I<SP>1</SP>. The occurrence frequency of the pulses on I<SP>1</SP> may be less than that of I so that not all I pulses when delayed effect coincidence with an P pulse. Triggering may be effected by the injection at point T1 of a pulse which when delayed by a time t coincides with an I<SP>1</SP> pulse or alternatively by the injection at point T2 of a pulse coincident with an I<SP>1</SP> pulse. N trigger circuits each operated over its I (and maybe I<SP>1</SP>) lead by a different one of a set of N time-spaced pulse trains may be combined, common triggering, output and normalizing leads being provided, over which pulses to or from the trigger circuits are sent or received in appropriate time positions. Such a combination would have 2N stable states. If circuits of the type shown in Fig. 9 are used and the spacings of adjacent pulse trains are equal, then the pulses for an I lead of one trigger circuit may be applied to the I<SP>1</SP> lead of another trigger circuit (e.g., the adjacent trigger circuit if the interval between the I and I<SP>1</SP> pulses is equal to the spacing of adjacent pulse trains). When such a combination is used, the trigger circuits may have a common amplifier A, Fig. 12. M such combinations of N trigger circuits may be further combined to provide a circuit having 2NM stable states so that the pulse positions used occupy a cycle of NM positions. In Fig. 6 each of the symbols X<SP>1</SP>01 ... X<SP>1</SP>0M represents a combination of N circuits of the type shown in Fig. 12. The common output, triggering and normalizing leads O, T, N are fed to each of the combinations XI01 ... X<SP>1</SP>0M via individual gates C pulsed over leads I<SP>11</SP>1 ... I<SP>11</SP>M and are arranged so that a pulse on T, for example, can only enter one of the combinations X<SP>1</SP>01 ... X<SP>1</SP>0M wherein it can trigger only one trigger circuit. This may be arranged for example by feeding the leads I1 ... IN with a pulse series P1 ... PN and the leads I<SP>11</SP>1 ... I<SP>11</SP>M with a pulse series P1 ... PM which are arranged so that each p pulse coincides with a P pulse, the pulse recurrence period of the p and P series being Nt and Mt respectively where M and N are prime to one another. Alternatively, one series, e.g. the P-series, could consist of long pulses having a pulse recurrence period of NMt and the other series, e.g. the p-series, might consist of short pulses having a pulse recurrence period of Mt so that each P-pulse may be coincident with M successive p-pulses. Similar arrangements, Fig. 9 (not shown), may be provided using trigger circuits of the type shown in Fig. 9. Detailed circuits, Figs. 14, 15. In the case in which the triggering pulse has the same tine position as those required to be emitted, leads I and I<SP>1</SP> are strapped and terminals A, B are strapped. A negative triggering pulse applied to terminal T is amplified by valves V1, V2 and appears at point A as a positive-going pulse of voltage V. Since this coincides with the negative pulse of voltage V received from lead I<SP>1</SP>, condenser C2 is charged to voltage - 2 v., which charges the small capacity condenser C1 to substantially the same voltage during the subsequent pulse interval and then maintains this voltage as long as pulses are received from point A in this time position. With C<SP>1</SP> thus charged, pulses over I forward bias the rectifier W2 to pass a pulse.via condenser C3 to the grid of V1 thus maintaining the circulation. The circulation is stopped by the application of a positive potential to lead N, thereby preventing the negative pulse received over C3 from affecting the valve VI. Alternatively, the trigger pulse may be positive and applied at point T1. In this case a rectifier is inserted between A and B to prevent transmission of the trigger pulse to the output lead O. In an alternative embodiment, a delay line is inserted at AB and the leads I and I<SP>1</SP> are fed by pulses separated by the delay time of the delay line. This unit may be triggered by a pulse coincident with one of those on lead I<SP>1</SP> provided it is applied at point T1. Specification 770,617, [Group XXXIX], is referred to.