Patent GB-1003924-A (GB)
Title: Indirect addressing system
IPC: G06F9/30
Filed: 1962-07-30
Abstract: 1,003,924. Digital computers. SPERRY RAND CORPORATION. July 30, 1962 [Aug. 17, 1961], No. 29150/62. Heading G4A. An indirect addressing system includes a keyword register, the successive keyword digits being effective to select a particular address from a register storing a plurality of addresses, or to terminate the selection process. Each keyword digit corresponds to one level of indirect addressing in a multi-level indirect addressing system. The indirect addressing system described can be applied to the data processing system described in Specifications 1,003,921 and 1,003,923. Word format.-Computer words consist of twelve decimal digits, each digit being represented in binary-coded form, a fifth, checking bit, being appended. An instruction word takes the form T II AA BB M<SP>1</SP>M<SP>1</SP>M<SP>1</SP>M<SP>1</SP>M<SP>1</SP> where T which normally indicates whether the machine is to go into a tracing mode, can have a special value to indicate that an indirect addressing operation is required. The II digits are an operation code and the AA and BB digits designate addressable registers among the 100 such registers 121, Fig. 1a these registers providing certain operands or being used in address modification. The five M<SP>1</SP> digits denote an address in the memory 111. The first " keyword " takes the form KKKKK BB MMMMM there being five " key digits K," the BB digits denoting an addressable register 121, whose contents may be employed to modify the M digits which are the address of the first " M word " of memory words containing two addresses, the M words constituting the indirect addressing series. Subsequent keywords contain twelve key digits. Each key digit K equals 0, 1, 4, 5, 6 or 9. If K=5, 6 or 9, modification of the M word address by the contents of the designated addressable register 121 is called for. If K = 0 or 5 it indicates that the left-hand portion of an M word is required; if K = 1 or 6, the right-hand portion is indicated; and if K = 4 or 9, the indirect addressing is terminated, the word addressed by the current address being the required operand. The M words take the form MMMMM BB MMMMM, representing two memory addresses (only one of which is selected) and an addressable register address BB. Operation.-In an indirect addressing operation, the address in the control counter 104 causes the first instruction T II AA BB M<SP>1</SP>M<SP>1</SP>M<SP>1</SP>M<SP>1</SP>M<SP>1</SP> to be read out from the core memory 111 into the instruction register 101, the T symbol indicating an indirect addressing operation setting an indirect address control flip-flop (IAFF) 187. The instruction decoder 109 is thereby inhibited from interpreting the instruction until the indirect addressing has been completed. The M<SP>1</SP> digits are then modified in the B-adder 139 by the contents of the addressable register BB, the modified address being employed to extract the first keyword KKKKK BB MMMMM from the memory 111 via the memory read register 150 to both the keyword register 191 and the M word register 193. The successive key digits are shifted from the keyword register 191 and decoded by a decoder 192 (Fig. 6, not shown) to cause the control circuits 130 to control operations dependent on the key digit value. The rightmost five M digits in the M word register 193 are effective, after modification (if this is required by the first key digit) to address the memory 111 to read out the first M word MMMMM BB MMMMM which replaces the first keyword in the M register 193. The second M word is addressed by the left- or right-hand portions of the first M word according to the value of the first key digit. This pattern of operation continues until a key digit is 4 or 9, whereupon the flip-flop 187 is reset to permit the instruction decoder 109 to decode the II digits of the instruction word and effect the corresponding operation on the operand which has been retrieved by the indirect addressing. The Specification describes an example of indirect addressing in the form of an information retrieval operation relating to an electronic circuit. The keyword register 191, digit decoder 192, M word register 193 are described in detail in the Specification (Figs. 5-7, not shown).