Patent GB-1244683-A (GB)
Title: Data storage apparatus
IPC: G11C11/4094
Filed: 1969-09-18
Abstract: 1,244,683. Digital data store. NATIONAL CASH REGISTER CO. 18 Sept., 1969 [8 Oct., 1968], No. 46028/69. Heading G4C. [Also in Division H3] In a data store of the type in which a single memory cell 10 of a matrix of semi-conductor memory cells, each of which capacitively stores a binary digit, may be selected by energizing an appropriate row and column, charge supply means C3 are provided for each column so that after each read or write operation on a selected cell all the cells storing a capacitive charge and lying in the same row as the selected cell are regenerated. Thus it is not necessary to extend the memory cycle to include a period of regeneration. Store construction.-A single storage element is shown in Fig. 1, and the matrix store comprising a matrix array of storage elements 10 is shown in Fig. 6. Each element 10 includes only transistors Q 1 , Q 2 , and Q 3  and capacitor C 1  of Fig. 1, the remaining circuit elements Q 4 -Q 9  and C 2  and C 3  being common to a matrix column. The transistors are M.O.S. field effect transistors formed as integrated circuits., lines # 1 , # 2  and 93 carry timing pulses and elements 61 and 65 are row and column selector circuits, respectively. Write operations.-Write operations are controlled by the sequential clock pulses on lines # 1  # 2  and # 3  Clock pulse 91 renders transistor Q 4  conductive and capacitor C a  charges from the power supply line V. The clock pulse # 2  and a simultaneous pulse on a read line 16 render transistors Q 5  and Q 1  conductive, capacitor C 3  charges from the power line and capacitor C 2  discharges via transistor Q 2  only if a charge is stored on capacitor C 1 . The clock pulse # 3  and simultaneous pulses on the write line 18 corresponding to the selected read line 16 and a column line 22 permit conduction through transitor Q 3  the direction being determined by the signal level at the input 14 and the previous charge on capacitor C 1 . The signal at input 14 passes through "OR" gate 76 and if it is a voltage V corresponding to binary "1" it will regenerate or charge capacitor C 1 . However, if it is a zero potential the capacitor C 1 , if previously charged, will discharge to this zero potential or if capacitor C 1  was previously uncharged, no change will occur. Thus the charge of the capacitor C 1  of the selected cell will correspond to the input signal level on line 14. It will be appreciated that the remaining cells in the selected row which have not received a pulse on their column lines 22 will have the charge on their capacitors C 1  confirmed since the transistor Q 8  of these columns will be non-conductive and the charge on capacitor C 3  will either run to earth through transistor Q 6 , which is biased conducting if a charge is present on the capacitor C 2  indicating that binary "0" is to be stored in the cell, and transistor Q 7 , or will regenerate capacitor C 1  if transistor Q 6  is biased non- conducting by the absence of charge of capacitor C 2  indicating that binary "1" is to be stored in the cell. Read operation.-Read operations are also controlled by a similar series of timing pulses # 1 , # 2  and # 3 , the first causing capacitor C 2  to charge and the second in conjunction with a simultaneous pulse on read line 16 causes capacitor C 3  to charge and capacitor C 2  to discharge or remain charged according to whether transistor Q 2  is biased conducting by a charge on capacitor C 1 , as in a write operation. The third pulse # 3 , and simultaneous pulses on a select line 22 and inhibit line 24, the last pulse switching "off" transistor Q 10 , permit conduction of transistors Q 7 , Q 8  and Q 9 . The signal on line 26 corresponds to the voltage on the capacitor C 2 , and is therefore zero if C 1  holds the charge and positive otherwise. This signal is inverted by the inverter 68, and passes to the input of "AND" gate 69 where it is gated with the inhibit pulse on line 24, the output of gate 69 then passes through OR gate 76 and appears at transistor Q 9  of the selected cell in the same way as an input pulse in a write operation. It will now be appreciated that all the cells in the row in which the selected cell lies will be regenerated in the same way as in a write operation, i.e. capacitor C 3  is selectively discharged to earth or to capacitor C 1  according to whether a charge is or is not present on the capacitor C 2 . Moreover, the selected cell is regenerated by the output of "AND" gate 69 which passes through "OR" gate 76 and functions in exactly the same way as an input pulse on line 14 in a write operation. A three-dimensional memory may be constructed from a number of the storage matrices described above, the control lines associated with similar matrix positions in each matrix being connected together.