Patent GB-1510588-A (GB)
Title: Sequential computing system
IPC: G06F13/12
Filed: 1976-05-28
Abstract: 1510588 Data processing J M POLSKY V P ZAKHAROV N T GOLETS J V TAYAKIN G P LIPOVETSKY V V PROTSENKO A D KHOMENKO V P SIDORENKO A Y SIROTA J V PROKOFIEV and A M KOPYTOV 28 May 1976 [2 June 1975 28 July 1975 15 March 1976 (10)] 22419/76 Heading G4A Data circulating in serially-connected registers 2 1 -2 n  is processed by an adder 6 and gates controlled by a microinstruction matrix 10, timing signals being provided by three counters 33, 34, 35 acting as frequency dividers. To replace a digit by zero gate 24 temporarily disconnects register 2 1  from register 2 n . To move a digit one place to the right gate 26 temporarily connects the input of register 2 1  to the output of register 2 m . To move a digit to the left it is transferred from register 2 n  via gate 4, adder 6, and gate 12 to an accumulator register 11 in which it is circulated via gate 13 until it is replaced in the data circulating in registers 2 1 -2 n  via gate 25 and register 2 1 . The carry output of the adder 6 is stored in a register 19 the contents of which are circulated via a gate 20 and indicate whether a program jump is to take place. The result of the processing is provided via a matrix 80 to outputs 81. An address counter 38, receiving the output of an address register 74 and control signals from a control unit 42, provides an address to a program matrix 27 the output of which contains an address in a matrix 32 which provides addresses to the microinstruction matrix 10, a code which, via a circuit 70, modifies the addresses supplied from matrix 32 to matrix 10, a rear instruction address code, a code which causes a signal at output 87 of a circuit 29 to modify the operations of certain of the gates, and a jump condition code. External information is received from an input 69 and supplied to registers 66 1 -66 p  whose output is selectively connectible via a gate 68 to adder 6 or via gate 67 to an output 65, a flip-flop 89 producing a control signal when external information is received. For operation with binary-coded decimal numbers constants 0110 and 1010 are formed by circuits 53 and 55 respectively. A plurality of such computers may be connected together (Fig. 2, not shown) the output 48 connected to counter 35 of the first computer being connected to the inputs 46 connected to counters 33 of the other computers, the output 65 of all but the first computer being connected to the input 69 of the preceding computer and the output 65 of the first computer being connected via external register to the input 69 of the last computer so that all the registers 66 1 -66 p1  the gates 67 and the external registers are connected in a closed loop. The code of the computer which is to continue calculations and the initial program address in that computer are inserted into this loop by a computer completing a calculation. All the computers are interrupted to determine the computer code in the closed loop. The computer whose code is in the closed loop passes the initial program address to registers 2 1 -2 n  and then from register 2 k  via control unit 42 to address counter 38. One of the computers may control all the other computers.