Patent GB-1490872-A (GB)
Title: Processor equipments
IPC: G06F15/167
Filed: 1974-08-15
Abstract: 1490872 Data processing system MARCONI CO Ltd 3 July 1975 [15 Aug 1974] 35932/74 Heading G4A [Also in Division H4] Interprocessor communication is established over a channel having, at least over that part adjacent the two processors, control and data signals paths so that in the absence of faults both control and data signals are transmitted and received, the control data normally controlling the transfer of data signals, whereas in the presence of a fault in the control signal path the (non faulty) data signals alone are still transmitted and received. As described two way communication is performed over respective unidirectional PCM highways 17, 117, between two processors 1, 101. Transmission occurs in 16 frames each of 32 time slots each of 8-bits. Time slots 1-15, 17-31 are reserved for speech data fed in at 16, 116, multiplexed with the remaining data, and extracted at 18, 118. Alternate time slots O contain "frame alignment" and "not frame alignment" bytes which indicate the frame number and provide data buffer addresses (see below). Alternate ones of the remaining time slots (16) contain data and control signal bytes which are transmitted as follows. Assuming a message is to be sent from processor 1 to processor 101 control data shift registers 4-7 and 104-107 are set to all 1's and data buffers 2, 3, 102, 103, are set to all 0's. Eight 8-bit message bytes are then read into buffer 2 by processor 1 asynchronously. To initiate transmission processor 1 writes all 0's into register 4 indicating that a message is being sent and sets a 100 msecs time out, a period for longer than required in normal circumstances. The first two bits Mo and Bo from shift registers 4, 5 are shifted into encoders 10, 11 which form a control byte Bo Bo Bo Bo Mo Mo Mo Mo which is converted into serial form in converter 14 and transmitted in time slot 16 of the first frame. Registers 4 and 5 (register 5 serving for processor 1 the same purpose as register 105 for processor 101 see below) shift successive bits into the encoders for transmission, control bytes and message bytes from buffer 2 being transmitted alternately in time slot 16 of successive frames. The reverse procedure occurs with serial to parallel converter 115, decoders 112, 113, shift registers 106, 107, and data buffer 103 at the receiving processor 101. A permanent 1-bit is fed into shift register 4 so that when this 1-bit is received a predetermined number of times in register 106 the end of the message is signalled-the bits causing an interrupt via line 120 to processor 101 which examines the contents of the shift registers 106, 107, and writes all 1's in register 106 and all 0's in register 105 thereby to cancel the interrupt and indicate that it is working on the data which has been received in buffer 103 respectively. If the control data path is not functioning correctly processor 101 can still retrieve the data received in buffer 103. In the absence of correct control signals processor 101 examines the data buffer contents periodically, e.g. at every 100 msec time out, to see if the data has changed. Thus data transmission is still possible, albeit at a slower rate. The contents of registers 104, 105 are encoded 110, 111 and transmitted to processor 1 in a manner similar to that described above, the corresponding data received in register 7 at processor 1 from register 105 indicating the busy status of processor 101. The content of register 105 remains at 0 due to a feedback at its most significant bit so that busy status is indicated for as long as processor 101 is working as the data, i.e. until the processor rewrites the contents of the register, see below. Processor 101 then examines the received data in buffer 103 and if it is unsatisfactory rewrites register 106 to all 0's whereupon a requisite number of frames later, determined by the number of 1-bits required in register 106 to interrupt processor 101, a new interrupt occurs. This repetition continues until processor 101 deems the received data satisfactory or until the time out terminates when the whole process must be repeated. Whether or not a message received satisfactorily by processor 101 requires a response the processor rewrites 1's into shift register 105 to signal processor 1 that its message has been received and that it is no longer busy, this being determined by detecting the 1-bits received in register 7. In this case the system is reset and another message can be transmitted. Independent transmission of control data alone is also possible in the event of a data path fault.