Patent GB-1405508-A (GB)
Title: Circuit design apparatus
IPC: G06F17/50
Filed: 1972-12-19
Abstract: 1405508 Data processing INTERNATIONAL BUSINESS MACHINES CORP 19 Dec 1972 [29 Dec 1971] 58461/72 Heading G4A A graphical processor (20, Fig. 1, not shown) generates the topological pattern of a semiconductor integrated circuit from output data provided by a processor (10) receiving at its input electrical, positional and topological data relating to the elements in the circuit. The particular embodiment is directed to generating the pattern for the logic of Fig. 2 (not shown), in which the gates comprise FET's. From a designer circuit for the logic (Fig. 9) in which the devices are positioned relative to a grid of rails 1-6 and channels A-M tables are derived. Table I (Fig. 5, not shown) lists, for each FET, its position in the grid and its width to length ratio. Table II (Fig. 7c, not shown) is an instruction table with an instruction for each sub-group of devices and contains the relative relationship of the devices in the sub group, i.e. series, parallel, the starting and ending rail number of each sub group, the number of devices in the sub group and the net start and end numbers. At the start of the operation field 1 of instruction 1 of Table II is accessed to determine the type of circuit. In the circuit of the particular embodiment FET's 22<SP>1</SP>, 22<SP>11</SP>, 22<SP>111</SP> are in parallel resulting in a parallel sub routine (Fig. 12A, not shown) being followed. Initially X and Y counters are at "1" so that the design data for the first device 22<SP>1</SP> is fetched from Table I. The co-ordinates of segment S11 (Fig. 10) are calculated with this data and stored in a first net start section of a third table (Fig. 8, not shown). The X counter is then incremented and the process repeated until all the FET's in the first sub group have been processed and co-ordinates for the segments S12, S13 stored in the same section of the table. The Y counter is then incremented to initiate the formation of the end segment S21, the co-ordinates for which are established by the lowest and highest X coordinates of the segments S11-S13. These coordinates are stored in the second net end position and Table II is accessed to obtain the next instruction. The second instruction results in a series sub routine being followed to compute the segments associated with device 30<SP>1</SP>, the X counter being incremented to 1 and the Y counter being incremented to 3 since the starting rail number of the second instruction is 3. Table I is then accessed to obtain the data associated with the device 30<SP>1</SP> so that the co-ordinates of segment S31 are computed and stored in the section of Table III associated with the second start net segment. The Y counter is then incremented and the count compared with the end rail number in Table II. At equality the end net number of the instruction in Table II is fetched to determine the co-ordinates of end segment 41 which are then stored in Table III at a section associated with the third net end section. Instructions 3 and 4 result in a parallel and series sub routine respectively being performed to derive the segments for devices 24<SP>1</SP>, 24<SP>11</SP> and 28<SP>1</SP>, 28<SP>11</SP>. After all the instructions in Table II have been effected the terminal routine is performed to connect the common start and end segments as specified by Table III. This is effected by testing, for each net number, for the presence of start and end segments. If only a net end or a net start is present for a number the co-ordinates of link segments such as S11<SP>1</SP>, S12<SP>1</SP> (Fig. 11) are calculated and stored together with the previously calculated co-ordinates of segments S11, S12, S13 in an output table. If both net end and net starts are present the co-ordinates of a segment in the end section are compared with the co-ordinates of the segments in the start section to determine the relative positions of the segments, the co-ordinates of the start segments such as S31-S33 being stored in one of three tables in dependence on whether they are to one side or the other or wholly overlapped by segments in the end section. A combination sub routine is then effected in which the three tables of segments are examined and revised coordinates for, for example, segment 31 are derived linking it to segment 21. Alternatively a link segment 31<SP>1</SP> may be defined. This data is then stored in the output table. When this process has been effected for each node number the output table is fed to the graphical plotter. The thin oxide and metallization patterns are generated by the positional and width to length ratio data of Table I to derive a plot of the required circuit (Fig. 12F, not shown).