Patent GB-943833-A (GB)
Title: Digital communication system
IPC: G06F13/12
Filed: 1962-08-01
Abstract: 943,833. Digital computers. SPERRY RAND CORPORATION. Aug. 1, 1962 [Oct. 6, 1961], No. 29513/62. Heading G4A. A data processing system comprises a central computer and remote data-handling equipment capable of transmitting to the computer an index word indicator effective to extract an index word from the computer store, said index word being effective to energize the storage locations required in a data transfer operation. General arrangement. In the arrangement shown in Fig. 1 a central computer 10 is connected to twelve input data handling devices 12 and twelve output data handling devices 14, data being transmitted in a 30-bit parallel mode on lines 16. When an input device 12 requires access to the computer an "interrupt" line 20 is activated and an interrupt word is transmitted to the computer over lines 16 to cause the computer to initiate a sub-routine to deal with the request. When an output device 14 is to accept data from the computer, an "output data request" signal is applied on a line 24 to cause the computer to transmit an output data word to the device 14. The computer controls the devices 14 by means of "function words" transmitted together with a signal on a line 26 to the controlled devices. The computer, Fig. 2, comprises a control section 30, an input - output section 52, a storage section 72 and an arithmetic unit 92. The control section includes a 30-bit instruction register divided into a 15-bit "upper" register U U  and a 15-bit "lower" register U L  for the operand address; and a program counter 38 whose contents may be incremented by 0,1 or 2 in a modifier 40. A 30-bit instruction word, Fig. 3, contains a 6-bit function designator f, designators j, k, b allowing various modifications, and the 15-bit operand address y. However in an input-output instruction j* and k* designators are effective to identify a particular input-output channel. Addresses may be modified by adding the contents of a selected B-register 42. An instruction is executed in four "sequences": an A-sequence in which an instruction is obtained from the memory, a B-sequence in which data is obtained and transmitted to the arithmetic unit, a C-sequence in which the arithmetic is performed and a D-sequence in which the result is stored. The input-output section 52 contains a plurality of sets of thirty gated amplifiers 54, one set for each input channel; priority and access control circuits 56 arranged to give access to the requesting input channel having the highest priority and including means for testing the channels to determine if they are "busy". The output to the output devices is applied via line drivers 66-70. The storage section 72 includes a magnetic core store 74 having an input-output register 78 divided into "lower" and "upper" parts Z L , Z U . During the restore portion of a memory cycle, the contents of the registers Z L , Z U , may be increased by 0 or 1 at modifiers 86, 88. After a data word has been transmitted, communication is established with other peripheral devices, thus providing a timesharing arrangement between the computer and the peripheral devices. Input-output data transfer. This takes place in any one of three possible modes: (1) the INTERNALLY SPECIFIED INDEX mode in which the address of an index control word is internally specified; (2) the EXTERNALLY SPECIFIED INDEX mode in which the address of the index control word is supplied by the peripheral unit itself- or (3) the EXTERNALLY SPECIFIED ADDRESS mode in which direct storage addresses are supplied by the peripheral unit. An index control word consists of a 30-bit word in two 15-bit sections, the upper half determining the address of the last word to be stored or read out and the lower half determining the address of the first word to be stored or read out. As each data word is transferred, the index control word is incremented by unity before it is returned to the memory until the two halves of the word are equal as detected by a comparator 90 which then issues a signal to terminate the data transfer. Priority. The computer includes a subpriority network to deal with requests of various types (input, output, external interrupt) on a fixed priority basis, and a priority network to establish priority among the various channels that may be presenting simultaneous requests to the computer, the higher numbered channels having priority over the lower. Interrupt facilities. A peripheral unit may send an "external interrupt" control signal to the computer thereby initiating a sub-routine to deal with request (e.g, a break in a magnetic tape). Time-sharing. If several "input" and "output" requests are present simultaneously, the input and output word transfers are interlaced by a time sharing circuit, the output word on the highest numbered channel being taken first. Circuit details. The input-output control circuits (Figs. 12a-12p, not shown) are described in detail in the Specification with reference to the three possible data transfer modes, and other circuits in the input-output section are also described in detail.