Patent GB-1364110-A (GB)
Title: Radar data processor
IPC: G01S13/64
Filed: 1971-12-23
Abstract: 1364110 Pulse radar INTERNATIONAL STANDARD ELECTRIC CORP 23 Dec 1971 [29 Dec 1970] 59928/71 Heading H4D A pulse coherent doppler radar system comprises range gates, means for scanning the gate outputs, means for detecting the timings of the beginning and end of an echo within the range slice of a particular gate, means for storing the rotation angle of the scanning aerial (and hence bearing) corresponding to the echo beginning and means for computing the bearing corresponding to echo maximum from said timings. Range selectors S1 to SN feed limiters A1-AN producing square wave echo pulses applied to circuits C1-CN which are sequentially energized by device 2 producing pulses on lines 29 1 -29 n  and which produce pulses corresponding to echo beginning and end which are fed via OR gates 9, 10 respectively to devices D, F. The gates also control a bi-stable B. When the radar is switched on, B is set by pulse 44 opening gate 22 and allowing clock pulses through to 2. However when echo beginning is detected, bi-stable B is reset via OR gate 11. Gate 11 is therefore closed and device 2 stopped momentarily. As the aerial rotates, circuit 3 supplies binary words corresponding to the rotation angle. When echo beginning is detected, D emits pulses D1, D2, D3 sequentially, D1 opens gate 14, allowing transfer of the contents of counter 28 in 2 (giving the range slice corresponding to the echo) to memory access 6 and opens gate 23, transferring aerial rotation angle or bearing to the access 5, operation of circuit 3 being inhibited by the DT pulse at 27. D2 allows storage of the bearing code in M1. If the echo is detected in range gate S1 the code is stored in the first row of the memory, the second row corresponding to the second gate and so on. D3 sets bi-stable B and opens gate 22 allowing operation of 2. The further range gates are therefore scanned. If no other echoes are detected and assuming that the echo occurs in S1, C1 detects echo end and produces a pulse at OR gate 10 output. This resets bi-stable B via gate 11 and hence 2 is again stopped. Device F is also energized, producing pulses F1-F7 in succession. F1 opens gate 14 and allows transfer of counter 28 contents to access 6. F2 allows read out of the bearing code stored at echo beginning. F3 allows transfer of echo beginning bearing and the present output of circuit 3, corresponding to echo end bearing to arithmetic unit 8. F4 transfers the output of adder 32, giving half the sum of the bearings, into register 33 and transfers the difference of the bearings, from 35, to memory M2. M2 delivers a correction code, corresponding to the bearing difference, to be added to the code held in 33. The correction is primarily due to the assymetrical nature of the echo, the code in 33 therefore not giving the true maximum amplitude bearing. In addition, compensation for processing time is necessary. F5 introduces the code in 33 and the correction code to adder 34. F6 transfers the range slice code from 2 to register 38 and the corrected bearing code to 3 register 39. F7, applied to OR gate 12, sets B and re-energizes 2. Operation of 3 is inhibited during pulses F1, F2, F3, i.e. until after it is addressed by F3. A circuit for use as one of circuits C1-CN is described.