baber/WOPTO huggingface dataset:
Patent TW-466731-B (TW)
Title: Method for eliminating metal contamination between memory device region and logic device region
Inventor: LIANG MONG-SONG
IPC: H01L23/50
Filed: 2000-12-07
Granted: 2001-12-01
Abstract: The present invention provides a method for eliminating a metal contamination between a memory device region and a logic device region, which comprises: forming a plurality of memory devices and a plurality of logic devices isolated by an insulation layer on a semiconductor substrate, in which the source/drain on each device has a contact plug; forming a first trench in the insulation layer and between the memory device regions and the logic device regions, thereby exposing the semiconductor substrate; forming a first isolation layer on the insulation layer to cover the insulation layer and filling up the first trench; forming an inter-metal dielectric layer on the first isolation layer; forming an interconnect trench in the inter-metal dielectric layer and forming a second trench in the memory device regions and the logic device regions; forming a barrier layer in the interconnect trench and the second trench; forming a metal layer in the interconnect trench and the second trench and on the barrier layer; and forming a second isolation layer on the inter-metal dielectric layer.
Patent TW-538270-B (TW)
Title: Semiconductor device, electro-optical device substrate, liquid crystal device substrate and manufacturing method therefor, liquid crystal device, and projection liquid crystal display device and electronic apparatus using the liquid crystal device
Inventor: HIRABAYASHI YUKIYA
IPC: G02F1/136
Filed: 2000-12-27
Granted: 2003-06-21
Abstract: This invention provides a means to securely prevent a crack and peeling of an insulating film in the periphery of a disconnection part at disconnection of a wiring for a short circuit by etching in substrates for various electronic equipment, such as the substrate for liquid crystal device subjected to a countermeasure against the static electricity by the wiring for the short circuit. In the substrate for liquid crystal device, a hole for cutting 37 for cutting the wiring 33 for the short circuit by etching is provided in a first interlayer insulating film 21 and a second interlayer insulating film 22 which cover the wiring 33 for the short circuit as a static electricity countermeasure wiring. An etching stop layer 38 consisting of a single crystal silicon film having resistance to etching of the second interlayer dielectric 22 is formed over a wider region than the hole for cutting 37 between the wiring 33 for the short circuit and an embedded oxidized film 62.
Patent TW-494637-B (TW)
Title: Linear low noise phase locked loop frequency synthesizer using controlled divider pulse widths
Inventor: RILEY THOMAS
IPC: H03L7/197
Filed: 2001-01-15
Granted: 2002-07-11
Abstract: A method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite phase frequency detector (PFD) has both a digital phase frequency detector (digital PFD) and an analog phase detector (analog PD) with the digital PFD compensating for large phase differences and the analog PD compensating for smaller phase differences. The PLL automatically chooses between these two components in the composite PFD by controlling the pulse width of the divider output. This is accomplished by synchronizing the dead zone of the digital PFD with the active pulse width of the divider output and by similarly synchronizing the phase detector window of the analog PD to be within both the dead zone of the digital PFD and the active pulse width of the divider output. Thus, during the active pulse of the divider output, the analog PD is operative while during the inactive pulse the digital PFD is operative. By essentially having only one PD active at any time, problems with analog/digital mixed circuits are avoided.
Patent TW-501364-B (TW)
Title: Camera device and shooting method
Inventor: KAWANISHI ISAO
IPC: H04N5/235
Filed: 2001-02-14
Granted: 2002-09-01
Abstract: The purpose of the present invention is to make a proper determination for performing a proper backlight correcting operation. The solution of the present invention is: in step 1, the location of a dark distribution is determined, and a dark distribution histogram ratio is calculated. Next, in step 2, the location of a bright distribution is determined, and a high-brightness slice set value is set. In step 3, a determination is made as to whether or not a subject is in a backlighted state. Here, backlight determining means determines that the subject is not in a backlighted state when a dark_ratio falls within a range of from 0 dB to less than -6 dB, while it determines that the subject is in a backlighted state when the dark_ratio falls within a range of from -6 dB to -30 dB. Also, when the subject is not in a backlighted state, the high-brightness slice set value is used unchanged in step 4. On the other hand, when the subject is in a backlighted state, the dark_ratio is normalized in step 5, so that, for example, backlight correction is carried out so that a high-brightness component limiter value of an integration signal of a peak-value-detected output is decreased.
Patent TW-522075-B (TW)
Title: Polishing pad with a transparent portion
Inventor: BUDINGER WILLIAM D
IPC: B24B37/26
Filed: 2001-05-02
Granted: 2003-03-01
Abstract: A transparent portion of a polishing pad in the solid phase has an index of refraction matched nearly to the index of refraction of a fluid polishing composition for chemical mechanical polishing, which minimizes scattering of an optical beam at an interface of the transparent portion and the polishing composition. A polishing pad for polishing integrated circuit wafers comprising, a polishing surface and a transparent portion disposed in an opening in the polishing surface, wherein the portion has an index of refraction matched nearly to the index of refraction of a polishing composition for chemical-mechanical polishing.
Patent TW-476151-B (TW)
Title: Semiconductor device and method for assembling the same
Inventor: SHIBATA KAZUTAKA
IPC: H01L21/60
Filed: 2001-03-21
Granted: 2002-02-11
Abstract: The present invention provides a semiconductor device for connecting a plurality of semiconductor chips on a solid surface. The plurality of semiconductor chips are arranged with different heights from the solid surface. The semiconductor device are assembled starting from the semiconductor chip with the lower height to be connected on the solid surface sequentially so as to proceed with the assembling process.
Patent TW-478028-B (TW)
Title: Semiconductor device and method of manufacturing the same
Inventor: SHIMIZU SATOSHI
IPC: H01L29/792
Filed: 2001-03-21
Granted: 2002-03-01
Abstract: A major object is to provide an improved semiconductor device capable of preventing occurrence of a crystal defect in a substrate. A source region is arranged at a surface of a semiconductor substrate and between first and second layered gates. A sidewall spacer is arranged on sidewalls, neighboring to a drain region, of the first and second layered gates. A sidewall spacer is not arranged on sidewalls, neighboring to a source region, of the first and second layered gates.
Patent TW-540133-B (TW)
Title: Method of manufacturing a semiconductor device comprising semiconductor elements formed in a top layer of a silicon wafer situated on a buried insulating layer
Inventor: DEKKER RONALD
IPC: H01L29/732
Filed: 2001-04-12
Granted: 2003-07-01
Abstract: A method of manufacturing a semiconductor device comprising semiconductor elements having semiconductor zones (17, 18, 24, 44, 45) formed in a top layer (4) of a silicon wafer (1) situated on a buried insulating layer (2). In this method, a first series of process steps are carried out, commonly referred to as front-end processing, wherein, inter alia, the silicon wafer is heated to temperatures above 700 DEG C. Subsequently, trenches (25) are formed in the top layer, which extend as far as the buried insulating layer and do not intersect pn-junctions. After said trenches have been filled with insulating material (26, 29), the semiconductor device is completed in a second series of process steps, commonly referred to as back-end processing, wherein the temperature of the wafer does not exceed 400 DEG C. The trenches are filled in a deposition process wherein the wafer is heated to a temperature which does not exceed 500 DEG C. In this manner, a semiconductor device can be made comprising semiconductor elements having very small and shallow semiconductor zones.
Patent TW-521544-B (TW)
Title: Arrangement of many circuit-modules
Inventor: HOEGERL JUERGEN
IPC: H01L25/10
Filed: 2001-05-15
Granted: 2003-02-21
Abstract: In order to reliably and simply connect the overlapped circuit-modules (2), it is suggested in a corresponding arrangement (1) to form an electrical connection of different connection-devices (5) of the overlapped circuit-modules (2) through direct mechanical and electrical contacts between the connection-elements (6) of different connection-devices (5).
Patent TW-490604-B (TW)
Title: Method of determining set temperature trajectory for heat treatment system
Inventor: SAKAMOTO KOICHI
IPC: H01L21/31
Filed: 2001-08-22
Granted: 2002-06-11
Abstract: This invention is a method of determining set temperature trajectories for a heat treatment system that conducts a first heat treatment process and a second heat treatment process to an object to be processed. The method comprises the steps of: conducting the first heat treatment process to a first test object to be processed, by using a temporary first set temperature trajectory; measuring a result of the first heat treatment process produced on the first test object to be processed; and determining a first set temperature trajectory for the first heat treatment process by correcting the temporary first set temperature trajectory on the basis of the measured result of the first heat treatment process. The method also comprises the steps of: conducting the second heat treatment process to a second test object to be processed to which the first heat treatment process has been conducted by using the determined first set temperature trajectory, by using a temporary second set temperature trajectory; measuring a result of the first heat treatment process and the second heat treatment process produced on the second test object to be processed; and determining a second set temperature trajectory for the second heat treatment process by correcting the temporary second set temperature trajectory on the basis of the measured result of the first heat treatment process and the second heat treatment process.
Patent TW-I240222-B (TW)
Title: Method and apparatus for processing graphics perspective transformations
Inventor: FOSSUM GORDON CLYDE
IPC: G06T15/20
Filed: 2001-09-04
Granted: 2005-09-21
Abstract: A method and apparatus in a data processing system for processing perspective transformations. An estimate of a depth coordinate is obtained. A determination is made as to whether the estimate is sufficiently accurate for the perspective transformation. An algebraic operation is performed on the estimate if the estimate is insufficiently accurate for the perspective transformation, wherein the algebraic operation increases the accuracy of the estimate.
Patent TW-507308-B (TW)
Title: Correction of overlay offset between inspection layers in integrated circuits
Inventor: MURADIAN DAVID
IPC: G03F7/20
Filed: 2001-09-19
Granted: 2002-10-21
Abstract: A first method for determining the offset between the origins of the coordinate systems used for inspection of at least two different defect inspections of a wafer with integrated circuits disposed on it, comprises creating a database containing location data for defects disposed on at least two inspection layers of an integrated circuit wafer; defining maximum offsets for interlayer defects; defining minimum spacings for intralayer defects; for all defects having spacings larger than the minimum spacings searching the database for interlayer defect pairs having offsets smaller than the maximum offsets; calculating an actual offset for each interlayer defect pair; determining whether the actual offsets are randomly distributed; identifying dense zones for the actual offsets if they are not randomly distributed; and developing an estimate of the offset between the origins of the at least two layers and a confidence value for the estimate for said actual offsets. A second method comprises identifying from the database at least one die having a number of defects nd wherein 0 ≤ nd ≤ k where k is an integer less than or equal to 5, identifying all interlayer defect pairs on the at least one die, and calculating an actual offset for each interlayer defect pair in place of defining maximum offsets for interlayer defects and defining minimum spacings for intralayer defects.
Patent TW-580411-B (TW)
Title: Method for recovering waste copper foil
Inventor: LIU MING-CHUAN
IPC: B09B3/00
Filed: 2001-10-08
Granted: 2004-03-21
Abstract: A method for recovering waste copper foil (1) comprises: using a chemical replacement reaction including using a copper sulfate solution and a copper foil electroplated with one or more metals having an oxidation potential higher than copper to undergo an oxidation-reduction replacement reaction; the method includes feeding copper foil to a tank containing a copper sulfate solution to perform a chemical replacement reaction; and subjecting the reacted copper foil attached with the solution film to a water washing system for recycling, or alternatively cutting the copper foil into a desired size to recover the copper foil.
Patent TW-508309-B (TW)
Title: Compact printhead and method of delivering ink to the printhead
Inventor: HSU TSUNG-PING
IPC: B41J2/15
Filed: 2001-11-08
Granted: 2002-11-01
Abstract: This present invention provides an ink jet printhead and method of delivering ink to the printhead. The printhead has a substrate, a nozzle layer, and a plurality of bubble generators. A plurality of first chambers and a plurality of second chambers are formed between the nozzle layer and the top of the substrate. A central ink flow channel and a periphery ink flow channel for delivering ink to the chambers are formed in the substrate. The characteristic of the present invention is that positioning the central ink flow channel and the periphery ink flow channel together on the substrate so that the amount of the nozzles per unit area of the printhead is increased.
Patent TW-564507-B (TW)
Title: Methods and systems for positioning substrates using spring force of phase-changeable bumps therebetween
Inventor: RINNE GLENN A
IPC: H01L21/60
Filed: 2001-11-09
Granted: 2003-12-01
Abstract: A second substrate is positioned relative to a first substrate having phase-changeable bumps, such as solder bumps, between them, wherein the second substrate has a first face adjacent the first substrate, a second face remote from the first substrate, and at least one edge wall between the first and second faces. The phase-changeable bumps are liquefied to establish an equilibrium position of the first and second substrates relative to one another. At least a portion of the second face is pushed away from the equilibrium position towards the first substrate, to a new position, without applying external force to the first face other than spring forces of the phase-changeable bumps that are liquefied, and without applying external force to any edge wall. Thus, only spring forces of the phase-changeable bumps that are liquefied oppose the pushing. The phase-changeable bumps that are liquefied then are solidified, to maintain the new position.
Patent TW-I221982-B (TW)
Title: System and method for grating profile classification
Inventor: DODDI SRINIVAS
IPC: G01M11/00
Filed: 2001-12-13
Granted: 2004-10-11
Abstract: Invention teaches a method and system for characterizing grating profile data. One embodiment is a method for characterizing grating profile data by clustering the grating profile data space and associating profile shape data to each cluster. Another aspect of the present invention is a system for classifying grating profile data comprising a cluster generator for generating clusters of grating profiles, for associating profile shape data to each cluster, and for linking the associated profile shape data to the grating profiles belonging to each cluster. The present invention includes a method and a system for evaluating input grating profile by comparing the profile data from the closest matching grating profile library instance with a set of acceptable ranges of profile data for the application; flagging the input grating profile if the profile data is outside the set of acceptable ranges; and presenting the profile data and flags associated with the input grating profile. The system is scalable and may operate in a distributed manner utilizing networks.
Patent TW-500889-B (TW)
Title: Solenoid-operated valve
Inventor: FUKANO YOSHIHIRO
IPC: F16K7/16
Filed: 2001-12-18
Granted: 2002-09-01
Abstract: A solenoid-operated valve comprises first and second elastic ring members (68a, 68b) each of which is made of an elastic material such as rubber, which retain a peripheral edge of a diaphragm (50), and which are flexibly bent in accordance with displacement of the diaphragm (50). A pair of lip sections (70a, 70b) is formed on the first and second elastic ring members (68a, 68b).
Patent TW-520986-B (TW)
Title: An intervertebral implant with a deformable wedge
Inventor: SENEGAS JACQUES
IPC: A61L27/00
Filed: 2001-12-20
Granted: 2003-02-21
Abstract: The invention relates to an intervertebral implant including a wedge which is inserted between two spinous processes and has two opposite grooves in which said spinous processes engage, which grooves have substantially parallel axes, and each of which grooves is defined by two flanges. The wedge (10) has at least one central opening (16) between said two grooves (12, 14) and said central opening (16) passes completely through said wedge (10) along an axis Ac substantially parallel to the axes Ag1 and Ag2 of said grooves, which renders said wedge (10) elastically deformable.
Patent TW-513782-B (TW)
Title: Manufacture method of selective copper film on damascene interconnect
Inventor: HUANG CHAO-YUAN
IPC: H01L21/768
Filed: 2001-12-31
Granted: 2002-12-11
Abstract: This invention discloses a manufacture method of forming selective copper film suitable for copper damascene process. Firstly, a metal layer and a dielectric layer are formed sequentially. Then, a plural number of damascene openings are formed in the dielectric layer. A barrier metal/Cu seed layer is globally formed on the surface of the dielectric layer. A chemical mechanical polishing (CMP) process is performed to remove the barrier metal/Cu seed layer at the place where there are no damascene openings to expose the top surface of the dielectric layer and leave the barrier metal/Cu seed layer only on the sidewall and at the bottom of the damascene openings. A chemical electroplating process is performed to form a Cu metal layer on the surface of the barrier metal/Cu seed layer and fully fill the damascene openings. Finally, another CMP process is carried out.
Patent TW-576991-B (TW)
Title: Data file management method, recording medium recorded with data file management program, and electronic terminal
Inventor: TAKASUGI YASUFUMI
IPC: G06F17/30
Filed: 2002-02-06
Granted: 2004-02-21
Abstract: The present invention is a data file management method, which includes the following steps: following the file operation for recording or reading data files (step 31); sequentially adding records with the file operation history Dh relating to the data file and the data file in independent management files Th (steps 33, 34). Thus, this data file management method is different from the conventional file management method, which only uses the various information relating to the current status of data file for file management, and executes the file searching based on the information relating to the past status of the data file. Therefore, in the situation of unknown status for the data file, it only needs to recall the several information during file operation in the past to easily and certainly find out the desired data file.
Patent TW-I251626-B (TW)
Title: Apparatus and method for making a silicon-based structure
Inventor: SHIMAOKA KEIICHI
IPC: H01L21/00
Filed: 2002-03-28
Granted: 2006-03-21
Abstract: The present invention provides a simplified process for producing a hollow, silicon-based structure. Apparatus are described for producing a hollow, silicon-based structure. The silicon-based structure includes forming a silicon dioxide layer on a silicon substrate, covering the silicon dioxide layer with a silicon layer and then further processing. The apparatus includes first gas supplying parts 20 and 21, second gas supplying parts 30 and 31, etching reaction chamber 10, alternative connecting devices 23 to 26, 34 and 35 and a gas exhaust device 42. The first gas is utilized to etch the silicon. The second gas is utilized to etch the silicon dioxide, but the second gas does not substantially etch the silicon. The alternative connecting devices 23 to 26, 34 and 35 enable the etching reaction chamber 10 to selectively communicate with one of the first gas supplying parts 20 and 21 or the second gas supplying parts 30 and 31. The gas exhaust device 42 discharges the gas from the etching reaction chamber 10.
Patent TW-537946-B (TW)
Title: Apparatus and methods with resolution enhancement feature for improving accuracy of conversion of required chemical mechanical polishing pressure to force to be applied by polishing head to wafer
Inventor: SALDANA MIGUEL A
IPC: B24B37/005
Filed: 2002-03-29
Granted: 2003-06-21
Abstract: CMP systems and methods in which a polishing pad is moved relative to a wafer and a retainer ring implement instructions for applying required pressure to the wafer for CMP operations. Accuracy of computations of the pressures, and of conversion of the pressure to force, is improved without use of high resolution components, such as high resolution digital devices. Such improved accuracy is achieved using both digital and analog operations, and by converting values of required pressure or force from one set of units to a second set of units and then back to the first set of units. A quantization process is performed using data processed by average resolution digital devices. The process transfers both pressure/force scale and pressure/force set point data between separate processors to obtain computed values of pressure and force having acceptable accuracy, such that quantization errors are eliminated or significantly reduced. A method of accurately representing, for computational processing, a desired value among a pressure range of values of pressure to be applied to a wafer in chemical mechanical polishing, comprising the operations of: dividing the pressure range by the value of a component resolution to define scale portions of the pressure range; generating a first output signal to identify one of the scale portions that includes the desired value; and generating a second output signal to identify a set point that defines the requested value in the identified scale portion.
Patent TW-543188-B (TW)
Title: Method of coding a mask ROM
Inventor: XU DANIEL
IPC: H01L27/105
Filed: 2002-05-10
Granted: 2003-07-21
Abstract: The present invention provides a method of coding a mask ROM, which comprises: first providing a semiconductor substrate formed with a mask ROM cell array; next, forming a rugged adhesion layer on the semiconductor substrate; then, forming a coding mask on the surface of the rugged adhesion layer which covers on the memory cells to be protected; and using the coding mask as a shield to implant ions into the semiconductor substrate without being shielded for performing a coding process.