Patent GB-1281428-A (GB)
Title: Data processor interface
Inventor: DARTON KENNETH STANLEY
IPC: H04Q3/545
Filed: 1970-07-02
Abstract: 1281428 Inter-exchange signalling systems STANDARD TELEPHONES & CABLES Ltd 2 July 1970 32215/70 Heading H4K A processor sends and receives data over a transmission channel the data format of which employs words of a bit-length greater than the bit length n of the processor, the send and receive interface between the processor and the transmission channel comprising an m-bit register and an m-bit buffer for each direction of transmission, m being greater than n; the processor, for each word to be sent, delivering two consecutive n-bit words to the send buffer which transfers an m-bit word to the send register from which the m-bits of the data word to be sent are read serially to a line modem; serial bits of a received data word being set up on the receive m-bit register and transferred in parallel to the receive buffer from which the data is transferred in two separate consecutive portions of n-bits each to the processor. The arrangement is specifically intended for interfacing a 16-bit word processor with a 28-bit signal unit format as proposed in the CCITT No. 6 separate channel signalling system. The No. 6 system uses a transmission rate of 2400 bauds with check bits and correction by retransmission. A signal unit is presumed to include 8 check bits and 20 data bits. A sequence of 12 signal units comprise a signal block the last unit of each block being devoted to an aeknowldgement unit indicating which of the preceding units of the last block contained errors and require retransmission. If an acknowledgment unit is faulty the whole block is resent. Some units are devoted to synchronization. The processor/signal channel interface accepts 16-bit words from the processor and adds check bits to the 20-bit data word comprising the message which it supplies in serial bit form to the signal channel modem. The registers and associated buffers for each direction of transmission handle the data bits and are in consequence of 20 bit capacity. Transfer between buffer and processor is in two steps gathering 10 bits from one half of the buffer at one step and the remaining 10 bits from the other half at the next step. Each such half of the data word is carried in a 16 bit word the sixteenth bit of which in the first step indicates if the data has been associated with a check bit error, while in the. second step it indicates if the signal unit is a synchronizing unit. Check registers of 8 bits, and constituted by re-entrant stepping registers, are provided for the send and receive sides of the interface to produce and add, or to extract and evaluate, the check bits. If the check bits received agree with the check bits formulated the receiving cheek bit register will end up empty. Whenever the 20-bit outgoing register is cleared after sending a signal unit a program interrupt is demanded for two consecutive words from the processor comprising new data bits. If the processor has no such bits to send, it instructs the interface to send a synchronizing unit. A synchronizing unit contains a four bit code indicating the position of the unit in the signal block and it is from this that the processor judges block synchronization. A signal unit counter in the interface is reset by the processor at the end of each block of units. The rest of the synchronizing unit is recognized by the receive side of the interface which controls unit synchronization. If the processor so instructs, the received bit stream is continuously shifted until synchronization code is recognized in order to establish correct alignment of the interface with the signal units. Bit synchronism is effected in the modem. The interface may service a number of signalling channels and is controlled from the processor by an instruction having address and function portions to set up interface decoders. Demands for interrupt from the signal channels can be handled on a 10 msec scan or by a masking control for processor interrupts.