Patent UA-90281-U (UA)
Title: Device for monitoring resource of air high-voltage switches
IPC: G07C3/10
Filed: 2013-08-09
Abstract: A device for monitoring resource of air high-voltage switches comprises first, second and third current sensors, which outputs are connected correspondingly through first, second and third comparators to first inputs of first, second and third flip-flops, which outputs are connected correspondingly to first, second and third inputs of second OR gate, and to control inputs of first, second and third electronic switches which outputs are connected to inputs of fourth and fifth comparators. Analog inputs are connected correspondingly to outputs of first, second and third current sensors. First input of encipher is connected to output of second OR gate. Second and third inputs are connected correspondingly to outputs of fourth and fifth flip-flops which first inputs are connected correspondingly to outputs of fourth and fifth comparators, and second inputs together with another inputs of first, second and third flip-flops and first pulse counter are connected to output of first OR gate which first input is connected to output of zero adjustment unit, second input is connected to output of pulse former, and third input is connected to output of signal delay element. Output of switching sensor is connected to input of differentiator and first input of second AND gate, which output is connected to input pulse former and to second input of first AND gate, to which first input the output of first pulse generator is connected, and output is connected to first input of first pulse counter and to first inputs of fourth, sixth and eighth AND gates. Output of differentiator is connected to first inputs of third, fifth and seventh AND gates, which second inputs are connected correspondingly to outputs of first, second and third NOT gates, which inputs are connected correspondingly to outputs of first, second and third flip-flops. Outputs third, fifth and seventh AND gates are connected correspondingly to first inputs of third, fourth and fifth OR gates, which second inputs are connected correspondingly to outputs of fourth, sixth and eighth AND gates, a outputs are connected correspondingly to inputs of second, third and fourth pulse counters. Second inputs of fourth, sixth and eighth AND gates are connected correspondingly to outputs of first, second and third flip-flops. Output of pressure sensor is connected to inputs of sixth and seventh comparators, which outputs are connected to first inputs of sixth and seventh flip-flops, which second inputs are connected to output of first OR gate, outputs of sixth and seventh flip-flops are connected to fourth and fifth inputs of first functional generator, which first, which second and third inputs are connected correspondingly to first, second and third outputs of encipher. Input of signal delay element and second input of second AND gate are connected to output of first digital comparator. First input digital bus is connected to output digital bus of first functional generator. Second input digital bus is connected to output digital bus of digital switch, which first input digital bus is connected to output digital bus of second functional generator, and second input digital bus and input digital bus of second functional generator are connected to output digital bus of first pulse counter. Output of differentiator is connected to input of fifth pulse counter, output of switching sensor through fourth NOT gate is connected to input of first monovibrator, which output is connected to control input of digital switch. The device comprises eighth, ninth and tenth comparators, OR-NOT gate, second monovibrator, sixth OR gate, first, second and third EXCLUSIVE OR gates, second pulse generator, eighth flip-flop, ninth, tenth, eleventh and twelfth AND gates, standard delay setup unit, fifth, sixth and seventh pulse counters, second, third and fourth digital comparators, first, second and third indicators. Outputs of first, second and third current sensors are connected correspondingly to inputs of eighth, ninth and tenth comparators. Output of eighth comparator is connected to first inputs of first EXCLUSIVE OR gate and OR-NOT gate, to second input of third EXCLUSIVE OR gate and to third input of ninth AND gate. Output of ninth comparator is connected to first inputs of second EXCLUSIVE OR gate and ninth AND gate, to second input of first EXCLUSIVE OR gate and to third input of OR-NOT gate. Output of tenth comparator is connected to first input of third EXCLUSIVE OR gate and to second inputs of second EXCLUSIVE OR gate, OR-NOT gate and ninth AND gate. Outputs of first, second and third EXCLUSIVE OR gates are connected correspondingly to first inputs of tenth, eleventh and twelfth AND gates which outputs are connected correspondingly to first inputs of sixth, seventh and eighth pulse counters. Outputs of first, second and third EXCLUSIVE OR gates are connected correspondingly to first inputs of tenth, eleventh and twelfth AND gates, which outputs are connected correspondingly to first inputs of sixth, seventh and eighth pulse counters, which output digital buses are connected correspondingly to first input digital buses of second, third and fourth digital comparators. Output of second pulse generator is connected to third inputs of tenth, eleventh and twelfth AND gates. Output of ninth AND gate is connected to second input of eighth flip-flop, which output is connected to second inputs of tenth, eleventh and twelfth AND gates. Output of OR-NOT gate is connected to input of second monovibrator, which output is connected to second input of sixth OR gate, which first input is connected to output of zero adjustment unit, and output is connected to second inputs of sixth, seventh and eighth pulse counters and to first input of eighth flip-flop, output digital bus of standard delay set unit is connected to second input digital buses of second, third and fourth digital comparators, which outputs are connected correspondingly to first, second and third indicators.