Patent GB-721215-A (GB)
Title: Improvements in electrostatic storage of digital information
Inventor: WILLIAMS FREDERIC CALLAND
IPC: G11C11/23
Filed: 1951-07-30
Abstract: 721,215. Pulse-storing circuits. NATIONAL RESEARCH DEVELOPMENT CORPORATION. July 17, 1952 [July 30, 1951], No. 18026/5. Class 40 (6). [Also in Group XIX] Digital information is stored in the form of two different states of electrostatic charge on a series of adjacent " digit " areas on a chargeretaining surface by directing a cathode-ray beam successively and recurrently upon these areas, the beam being switched on (unless it is already on) at the beginning of each digit interval, thus producing a positive charge on the surface, and being either maintained throughout the interval or switched off before the positive charge has been neutralized by secondary electrons from an adjacent region, and the information is read by extracting the voltage generated at the commencement of each digit interval in a signal plate capacitatively coupled to the surface. The storage system described combines features of the " anticipation method illustrated in Specification 645,691, and in Fig. 1 (e)-(h), and the dot-dash method illustrated in Specification 657,591, and in Fig. 1 (a)-(d). In the present method, Fig. 1 (i)-(m), the beam is switched off near the commencement of a digit interval to represent digit A (or O) and is switched on throughout the interval to represent B (or 1). Thus A is represented by a separate dot or by an extension of the line representing B (see digit intervals 1 and 4) but in either case the charge distribution, Fig. 1 (k), is such that a negative-going voltage pulse, Fig. 1 (L) is produced in the signal pick-up plate at the beginning of a digit interval which is gated by strobe pulses, Fig. 1 (m), while B is represented by no signal or a positivegoing pulse. The signals from the pick-up plate 11, Fig. 4, are applied via an amplifier 12 to an " integrating and clamping " circuit 13 to which a clamping wave also is applied at 14. The output of circuit 13' is applied through amplifier 15 to a gate 16 to control the production of a switching voltage applied to the control grid 17 of the cathode-ray storage tube 10. Integrating and clamping circuits. As shown in Fig. 5, the signal from amplifier 12 is applied to the control grid of a pentode V arranged as a Miller integrator, the coupling from its anode to the integrator condenser 21 being through a cathode follower V2 from which the output is taken at 23. During the later part of each digit interval, a positive clamping voltage is applied at 14 to the control grid of a pentode V3 which then conducts and clamps the anode of V1 and the cathode of V2 to a fixed positive value due to the low-resistance feed-back path provided through diode 22. In an alternative circuit, Fig. 6 (not shown), the integrator condenser is connected across a diagonal of a diode bridge to which clamping waveforms are applied. Gate circuit. The output of amplifier 15, Fig. 4, is inverted in circuit 33, Fig. 7, to produce zero-representing positive pulses, Fig. 8 (a), which are differentiated, Fig. 8 (b), in circuit 34, 35 and passed through diode 36, thus charging condenser 37. The control grid of pentode V4 is thus held at a positive value (see Fig. 8 (d)) until a negative control pulse, Fig. 8 (c), is applied through diode 39. While a positive voltage on the control grid coincides with a positive strobe pulse, Fig. 8 (e), on the suppressor grid, V4 conducts and the resultant negative anode output pulse, Fig. 8 (f), cuts off cathode follower V5 which is rendered conducting at the beginning of each digit interval by a positive control pulse, Fig. 8 (g), applied through diode 45. This produces the required beam-switching output signal, Fig. 8 (h), at 43.