Patent GB-1274960-A (GB)
Title: Improvements in or relating to time-division multiplex telecommunications exchange systems
IPC: H04J3/06
Filed: 1970-09-15
Abstract: 1,274,960. Automatic exchange systems. SIEMENS A.G. 15 Sept., 1970 [16 Sept., 1969], No. 43961/70. Addition to 1,257,214. Heading H4K. In a TDM system having 4-wire highways between exchanges, the time frames on all the incoming pairs to any one exchange are synchronized to each other as also are the frames on all the outgoing pairs, the latter frames being delayed by a period tv relative to the incoming ones. Time slot interchange is effected by pairs of delay circuits, one circuit of a pair delaying a channel in one direction by a time tx and the other circuit delaying the corresponding channel in the other direction by a time ty where tx + ty = 2tv. The wire pairs are connected to the delay circuits via gates which are controlled by only one recirculating type memory per highway. The outputs of the memory are applied to the gates on the incoming pair side of the delay circuits immediately they are produced but are applied to the gates on the outgoing pair side of the delay circuits after a delay equal to tv. As shown, the incoming (PCM) pairs ZMLanI to ZMLanN are connectable via associated sets of gates, Ik0 ... Ik3<SP>1</SP> to Nk0 ... Nk3<SP>1</SP>, to pairs of delay circuits Z0/Z6 ... Z3/Z3<SP>1</SP> to the outputs of which the outgoing pairs ZMLabI to ZMLabN are connectable via sets of gates 6kI ... 3kI to 6kN ... 3kN. The delay pair Z0/Z6 provide delays of tx = 0, ty = 2tv respectively while the pair Z3/Z3<SP>1</SP> provide delays of tx=tv, ty=tv respectively, other combinations of tx and ty being provided by the not shown intervening pairs. The incoming pair ZMLanI and the outgoing pair ZMLabI of a same highway have an associated recirculating memory UI whose output in a particular time slot immediately controls via decoder DanI one of gates Ik0 ... Ik3<SP>1</SP> while its decoded output (DabI) from the same time slot controls one of gates 6kI ... 3kI after a delay (=tv) provided by a delay circuit Vtv. In operation a connection between calling highway ZMLanI/ZMLabI and called highway ZMLanN/ ZMLabN is set-up by allocating a delay pair e.g. Z0/Z6 which will provide the desired time slot matching for the two channels to be used on the highways and by inserting the appropriate gating instructions in UI and UN. In the example, these comprise opening gates Ik0 and OkN simultaneously for the calling to call speech direction and opening Nk6 and 6kI with a time separation equal to tv for the called to calling speech direction, this being affected by inserting the instruction in UN such that it emanates therefrom at a time which leads by tv the corresponding instruction from UI. If the pair Z3/Z3<SP>1</SP> i.e. tx=tt=tv, had been used then the instructions would be inserted simultaneously into the memories UI, UN. In the event that delays longer than 2tv are necessary to effect time slot interchange, additional static memories ZV, ZV<SP>1</SP> are provided. Access to these is obtained via gates vkV ... Vkv which are controlled by memory UV and decoders DanV, DabV in a manner similar to that described above. Only one intermediate line between all the gates Ikv ... Nkv pertaining to the incoming pairs and the gates vkV ... ukV<SP>1</SP> (and similarly for the outgoing pairs) is needed in this case.