baber/WOPTO huggingface dataset:
Patent JP-2000061101-A (JP)
Title: Pachinko machine
Inventor: FUKUSHIMA SEIICHIRO
IPC: A63F7/02
Filed: 1999-09-10
Abstract: PROBLEM TO BE SOLVED: To confirm the paying out of gift balls and the paying out of dispensing balls. SOLUTION: Gift balls discharge from a gift ball discharging device 33 are passed through a gift ball discharging passage 39 which is formed on a mechanism plate 26 and discharged from a gift ball outflow port 15a into an upper tray and because when a player operates any one of lending buttons, on the other hand, the dispensing balls of the number corresponding to the operated dispensing button are passed through a dispensing ball discharging passage 40 which is formed on the mechanism plate 26 and discharged from a dispensing ball outflow port 15b into the upper tray by the gift ball discharging device 33 and since the gift balls and the dispensing balls to be discharged into the upper tray 14 are discharged through the different passages 39 and 40, it can be easily comprehended which kind of balls are discharged.
Patent JP-H04134696-A (JP)
Title: Semiconductor integrated circuit device
Inventor: SHIOMI TORU
IPC: G11C11/413
Filed: 1990-09-25
Abstract: PURPOSE:To obtain a semiconductor integrated circuit device of large capacity and low power consumption stably operating at high speed by making the logical amplitude of a current mode operating circuit in the final stage larger than logical amplitudes of other current mode operating circuits and stably converting into a signal of MOS level at high speed. CONSTITUTION:In the figure, the logical amplitudes of an input master circuit 14 and input slave circuit 15 in an input data holding circuit 8' are made different, i.e., the logical amplitude of circuit 15 is made larger than that of the circuit 14. The circuit 8' is further furnished with a level conversion circuit 200 for converting the output signal received from the circuit 15 to, e.g., the signal of MOS level, and a driver circuit 201 for driving the internal circuit of next stage at high speed in response to the output of this level conversion circuit 200. The output of circuit 201 has the level for MOS transistor and is capable of sufficiently driving at high speed a memory array cell including memory cells in which MOS transistors are made to the constituting elements.
Patent JP-H0198223-A (JP)
Title: Method for diffusing impurity into silicon wafer
Inventor: IWAMOTO KOICHI
IPC: H01L21/22
Filed: 1987-10-12
Abstract: PURPOSE:To keep wafers at a fixed temperature, and to diffuse an impurity economically by preventing the temperature drops of the wafers near both ends of a first vessel made of quartz at the time of heat treatment by thermal diffusion preventive plates and thermal reflection surfaces in second and third vessels made of quartz arranged in a diffusion furnace. CONSTITUTION:Thermal diffusion preventive plates 6a disposed at one end sections of second and third vessels 7, 8 made of quartz are housed so that the thermal reflection surfaces 6b of the plates 6a are exposed to the end face sides of the second and third vessels 7, 8 made of quartz. Each vessel 2, 7, 8 made of quartz is inserted into a diffusion furnace 5 consisting of a tube 3, one end of which is opened, and a heater 4 installed onto the outer circumferential surface of the tube 3 made of quartz so that the surfaces of wafers 1a at both end sections of a first vessel 2 made of quartz and the thermal reflection surfaces 6b of the thermal diffusion preventive plates 6a at the end sections of the second and third vessels 7, 8 made of quartz are faced oppositely. The heater 4 is heated, and a temperature in the diffusion furnace 5 is elevated up to a required diffusion temperature close to 1200 deg.C. The diffusion temperature is continued for a fixed time, the temperature of the heater 4 is lowered, and the temperature in the diffusion furnace 5 is dropped at 900 deg.C, thus completing heat treatment.
Patent JP-H09172614-A (JP)
Title: Method and apparatus for pixel interpolation using correlation of wide-area vector
Inventor: KIN EITAKU
IPC: H04N7/01
Filed: 1996-09-27
Abstract: PROBLEM TO BE SOLVED: To obtain a picture element interpolating method and a device where interpolation is efficiently executed concerning edges with various kinds of inclination by introducing an interpolation method using a wide-range vector when data of the picture element of a line which is omitted through the use of data of the picture element given by means of jump scanning. SOLUTION: Data sample given by jump scanning is inputted to a correlating part 20 and inputted to the correlating part 20 by way of LPF 10. A fist corrector 21 calculates DV from the data sample so as to output it and the second/ third corrector 22/23 obtain 1'/1" and m'/m" with Dn /D as min. from the data sample which is executed low band filtering so as to output them. Wide-range/ narrow-range vector reference filters 30/31 output interpolating values by the wide-range/narrow-range vectors from 1"/1' and m"/m' and the data sample. A longitudinal filter 50 outputs a longitudinal interpolating value from the data sample. A selector 60 selects the interpolating value suitable for a state from respective inputs so as to output it.
Patent JP-S62115842-A (JP)
Title: Gate array having delay cell
Inventor: NAKAYAMA KEIZO
IPC: H01L21/822
Filed: 1985-11-15
Abstract: PURPOSE:To maintain wiring efficiency by shortcircuiting the active element terminal of an unused gate as a delay cell in a gate array by a metal pattern, and using it to delay a signal as a capacitive load to reduce a power consumption. CONSTITUTION:A delay cell is disposed between a gate A and a gate B, an aluminum pattern 3 is formed on the entire region of an unused basic cell region C, and the pattern 3 is interposed between the wirings 1 and 2 of a terminal (a) of the gate A and an input terminal (b) of the gate B. As a result, an equivalent circuit having a delay cell (DEL) is obtained. The pattern 3 is formed on a lower layer, the terminal of the entire active element is shortcircuited, and their parasitic capacities are used. Since a resistor R is connected at its one terminal to a high potential power source Vcc, the Al pattern is punched. The all terminals (emitter, base, collector) of a transistor Tr are shortcircuited to be connected with the pattern 3, and the portion of the resistor R is punched in the pattern. Thus, the wirings of a channel region is not routed around to eliminate the decrease in the yield due to the disconnection of the long wirings and to reduce the rejection rate of the gate array.
Patent JP-H01101012-A (JP)
Title: Light receiving circuit
Inventor: OIMURA KATSUHIKO
IPC: H04B10/293
Filed: 1987-10-14
Abstract: PURPOSE:To improve the high frequency characteristic of a light receiving circuit by making the output current of a first transistor into an input current, providing a current mirror circuit to generate the output current of comparable strength to it, simultaneously, connecting a load resistance to the transistor at the output side, and giving the output voltage to a second transistor. CONSTITUTION:An output current (i) of a transistor(TR) Q1 flows to a TR Q4 of a current mirror, and a current of almost the same intensity as it flows also to a TR Q3. The output current (i) of the TR Q3 is converted to a voltage by a load resistance R1, and impressed to the base of a TR Q2. The TR Q2 outputs the input signal with an emitter flower. The output is negative-fed-back through a feedback resistance Rf to the TR Q1. In such a circuit, the voltage to be impressed to the TR Q2 appears at the corrector (C point) of the TR Q3 of the current mirror. Thus, it is necessary that the load resistance is connected to the corrector of the TR Q1, and since the potential of the corrector (B point) of the TR Q1 is constant at a VCC, a negative feedback through a capacity CBC does not occur. Consequently, the high frequency characteristic can be improved, compared with a conventional one.
Patent JP-H04234458-A (JP)
Title: Decomposable polyamide composition
Inventor: RARUFU DOUYARUDEIN
IPC: C08L77/02
Filed: 1991-09-10
Abstract: PURPOSE: To obtain a decomposable aliphatic polyamide compsn. useful for obtaining a packing material for a food package by adding a specific aliphatic polyester or polycarbonate to a base composed of polycaprolactam or a predetermined polyamide or a copolymer of units of them.  
     CONSTITUTION: Polycaprolactam or a polyamide based on 4-6C aliphatic dicarboxylic acid and aliphatic diamine or a copolymer of units of them (e.g.; polycaprolactam) is used as a base and 5-25 wt.%, pref., 10-20 wt.% of a straight chain or branched oligomeric aliphatic polyester or polycarbonate with a mol.wt. of 800-4,000 (e.g.; polyester obtained from hexane-1,6-diol and adipic acid) is added to the base. 
     COPYRIGHT: (C)1992,JPO
Patent JP-H02104906-A (JP)
Title: Exhaust heat recovering boiler system and its operation
Inventor: HOIZUMI SHINICHI
IPC: F01K7/24
Filed: 1988-10-14
Abstract: PURPOSE:To hold fluctuation of generated evaporation, steam temperature and etc. smallest possible by installing a flow rate control device which adjusts the amount of reheat steam corresponding to exhaust gas supplied into an exhaust heat recovering boiler. CONSTITUTION:Steam flow rate controllers 51, 61 are installed on the way of low-temperature reheat steam pipes 15, 25. Then, the steam flow rate controllers 51, 61 are so adjusted that the amount of reheat steam can be passed through reheaters 13, 23, corresponding to the load of respective exhaust heat recovering boilers 10, 20. Steam flow rate equivalent to heating value held by exhaust gas is fed into the reheaters 13, 23 to control the ratio of heating value held by the reheat steam to heating value held by the exhaust gas equally for each of reheaters 13, 23. It is thus possible to manage almost equally and stably reheat steam conditions.
Patent JP-H03119834-A (JP)
Title: Error correction decoder
Inventor: MATSUMI CHIYOKO
IPC: H03M13/00
Filed: 1989-10-02
Abstract: PURPOSE:To perform error correction for reception words in normal and reverse orders by finding syndromes from the reception words in descending width order and ascending width order, respectively, converting an error position to signals synchronized with delay reception words in descending width order and ascending width order, respectively, and selecting either signal based on a selection signal. CONSTITUTION:The syndrome Si (i-0, 1,..., D-1) is found for the reception word inputted to a normal syndrome generator 11 in the descending width order, and the syndrome Si (i-0, 1,..., D-1) for the reception word inputted to a reverse syndrome generator 12 in the ascending width order. It is decided which syndrome by the normal syndrome generator 11 or the reverse syndrome generator 12 is a correct syndrome based on the above input order. The signal required for computation to find an error at a dissipation position selector 16 is selected based on the selection signal inputted to show that the reception word is the one in the descending width order or the ascending width order. In such a way, a circuit which performs the error correction for the reception words in normal and reverse orders is obtained.
Patent JP-H05102648-A (JP)
Title: Printed board
Inventor: SUZUKI SHINICHI
IPC: H05K3/34
Filed: 1991-10-04
Abstract: PURPOSE:To reduce component mounting density and facilitate wiring by providing shared pads which allow the terminal of a plurality of different size chip components to be connected to the edge of the wiring by solder and providing a solder flow preventing part on the shared pads. CONSTITUTION:Two different size shared pads 6 for capacitor mounting are provided and the pads 3a, 3b, 4a and 4b are arranged almost linearly. The shared pad 6 is provided with a solder flow preventing part 7. The solder flow preventing part 7 is formed by patterning the shared pad 6, is constituted of a L-shaped space and is provided with solder resist. Thus, component mounting density is reduced and wiring is facilitated. When a small chip component is soldered, the solder flow is prevented and the deterioration of the reliability of the soldering is prevented.
Patent JP-H0995986-A (JP)
Title: Foot wash place
Inventor: OKAMOTO SUSUMU
IPC: E03C1/18
Filed: 1995-10-04
Abstract: PROBLEM TO BE SOLVED: To utilize a sink cover as a step to an open veranda at not using it by pivotally fitting the rigid flat plate-like cover made of glass fiber reinforced polyurethane foam covering the whole upper face of a sink provided adjacent to the open veranda to the rear end. SOLUTION: A rigid flat plate-like cover 3 made of FRP, artificial wood, or the like covering the whole upper face of a sink 1 is pivotally fitted to the rear end of the sink 1 provided adjacent to the side of an open veranda 2. In addition, recessed grooves 31 are carvedly provided on the surface of the cover 3 at nearly equal intervals, and the appearance at closing is formed so that narrow tablet-like plates are provided side by side similarly to edge plates 22. At the time, a lawn faucet 4 is standingly provided on the step part 11 arranged on the back side of the sink 1, and a hose 5 connected to the lawn faucet 4 is windingly received in the sink 1. Further, a spraingling fitting 6 fitted to the extreme end of the hose 5 is fitted and fixed to a stud 32 fixedly fitted to the back of the cover 3.  The edge plates 22 are pivotally fitted to the rear end of a cabinet 21, vent holes 24 are provided on right and left both side walls of the cabinet 21, and the whole vent hole 24 is covered with a wire net for preventing invasion of insects and dead leaves into the cabinet 21.
Patent JP-H09102589-A (JP)
Title: Semiconductor device having capacitor and manufacture
Inventor: ONO KEIICHI
IPC: H01L27/108
Filed: 1995-10-04
Abstract: PROBLEM TO BE SOLVED: To further increase an effective surface area per unit projected area than a conventional record node electrode by providing a single or a plurality of fins extending mutually separated in the horizontal direction on the surface of the columnar side of a wall body. SOLUTION: In a semiconductor device 1, an interlayer insulating film and an etch-stopper layer 6 are formed on the surface of a semiconductor substrate 2. A record node 10 is formed on the interlayer insulating film 4 and the etch- stopper layer 6 through a connecting hole 8. This record node 10 has a columnar body 12 set up from a semiconductor substrate 2, and a base body 14 extending from this columnar body 12 in the horizontal direction and a wall body 16 set up from a tip part of this base body 14 constitute a cylindrical body 15 with the bottom and the opened top. Further, a fin 18 extending from the inner wall surface of the wall body 16 inwardly in the horizontal direction is formed in the record node 10. Further, a plurality of stages of fins 18 may be provided by mutual separation in the height direction of the wall body 16.
Patent JP-H03121522-A (JP)
Title: Coordinate input device
Inventor: SEKIYA TOSHIYUKI
IPC: G06F3/03
Filed: 1989-10-04
Abstract: PURPOSE:To eliminate variance in coordinate calculation accuracy among indication points and to enable stable coordinate input by selecting the transmission level of a coordinate indicating tool and/or the sensitivity of a sensor according to which area an indication point is in. CONSTITUTION:The coordinate input device is provided with a storage means 50 which has plural areas corresponding to reception accuracy by indication points for respectively sensors 2a-2c and a selecting means 30 which selects the transmission level of the coordinate indicating tool 1 and/or the sensitivity of the sensors according to which area an indication point is in. Then the transmission level of the coordinate indicating tool and/or the sensitivity of the sensor is selected corresponding to the indication area. Consequently, the variation in coordinate calculation accuracy among the indication points is eliminated and the stable coordinate input becomes possible.
Patent JP-H10116916-A (JP)
Title: Cell for forming integrated circuit and method for producing the same
Inventor: ALEXANDER D ESSBAUM
IPC: H01L21/82
Filed: 1997-09-24
Abstract: PROBLEM TO BE SOLVED: To provide a cell device and method used for forming a complex integrated circuit. SOLUTION: A first region 31 in a cell 36 is dedicated to a first type circuit element. A second region 39 in the cell 36 is dedicated to a second type circuit element. A third region 43 is to be utilized for a number of different applications of an integrated circuit and is dedicated to integrated circuit elements of not less than one different type. The cell 36 is used together with a plurality of cells, thus efficiently forming an image displaying a complex integrated circuit device. The cell 36 includes an upper edge, a lower edge, a plane 42 dedicated to a ground line, a plane 40 dedicated to a clock line, and a plane 38 dedicated to a voltage source line. The first region 37 in the cell may be dedicated to an n-type transistor, and the second region 39 in the cell may be dedicated to a p-type transistor.  A center region provided in the cell separates the first region 37 and the third region 43 from the second region 39.
Patent JP-2000083788-A (JP)
Title: Meal self-supporting equipment
Inventor: NAKAGAWA HIROYUKI
IPC: A61G12/00
Filed: 1998-09-11
Abstract: PROBLEM TO BE SOLVED: To provide an economical meal self-supporting equipment for handicapped persons with fingers and mouths paralyzed who may bite chopstick tips into pieces in error during meal, capable of using chopsticks as they are and easily changing inexpensive throwaway chopstick tips only if the chopstick tips are bitten into pieces in error. SOLUTION: This equipment includes a grip 5 contacting the inner face of a third finger F3, a nipping projection portion 6 to be inserted in a space between the side face of a second finger F2 and the side face of the third finger, finger catch portions 7 on which the lower face of a first finger F1 is placed, hand sections 9 on which the roots of the first and second fingers are placed, and a male guide plate 8a and a female guide plate 8b provided on the hand sections of chopstick bodies 8a, 8b. Cylindrical chopstick insert portions provided with axial cuts are formed at the front ends of the pair of chopstick mainbodies 8a, 8b formed in symmetry and pivotally mounted with both guide plates to be set in and out, the base ends of the chopstick tips 16 are inserted in the chopstick insert portions in a removable manner and fastening caps are applied on the chopstick insert portions.
Patent JP-S63114831-A (JP)
Title: Position tracer
Inventor: UNO MASATO
IPC: B23P19/00
Filed: 1986-10-31
Abstract: PURPOSE:To make any damage to be produced at the time of changing preventable, by supporting a part holding device shiftably in three-dimensional directions in a static pressure manner, while installing a discharge part which discharges a medium, statically holding the part holding device, via a throttle. CONSTITUTION:Pressurized gas is fed to an air pocket 3 of an air chamber 2 from a tube 6 via a nozzle 5. If so, a thrust plate becomes floated so that it is smoothly movable to external force in the horizontal direction. If so, in the case where there is dislocation between an assembling part 13 and an assembled part 14, if reaction between parts at a chamber to be produced by a descent of the assembling part 13 acts thereon even slightly, the assembling part 13 is made traceable so as to fit with the assembled part 14. Here, such force in the horizontal direction as necessary to trace so as to absorb the dislocation is influenced by a flow rate to be discharged out of an air port 7 of a throttle 8.
Patent JP-H09104978-A (JP)
Title: Electron tube and its production
Inventor: GONPEI KATSUHIRO
IPC: C22C27/04
Filed: 1995-10-05
Abstract: PROBLEM TO BE SOLVED: To effectively suppress the generation of secondary electrons in electron beam capture electrodes by composing the electron beam capture electrode in an electron tube of a specified metal and implanting the ions of Ce or Be into the surface. SOLUTION: Collector electrodes 13 and 14 for capturing electron beams in a multistage potential lowering type collector electrode structural body of a traveling wave tube are formed of Cu or the alloy thereof excellent in thermal and electric conductivity or Mo or W or the alloy thereof having a high m.p., and, on the surface, ion implanting layers 13b and 14b having about 1μm depth and <=1.0 secondary electron maximum releasing efficiency are formed by an ion implanting method, and after that, annealing treatment is executed at 350 to 550 deg.C for about 10 to 60min in a vacuum or in an inert gas atmosphere of Ar or the like. The generation of secondary electrons in electron beam capture collector electrodes 13 and 14 is remarkably suppressed, by which the objective electron tube high in reliability can be obtd.
Patent JP-H04137553-A (JP)
Title: Lead frame for semiconductor device
Inventor: HAYASHI KAZUNORI
IPC: H01L23/50
Filed: 1990-09-27
Abstract: PURPOSE:To enable depression woking even in the case where the distance between an outer frame and an island end portion can not be ensured so as to be sufficient to contain a depression end portion in a resin seal region, by extending an island suspension lead toward the side of an island, and ensuring a region for depression on the side of the island. CONSTITUTION:Bent parts 15a, 16a, 17a are formed on island suspension leads 15, 16, 17, respectively, as the result of depression of an island 3, and correspond to depression end portions. The island suspension leads 15, 16, 17 are extended toward the side part of the island 3, and the region for the depression end portions is ensured on the side of the island 3. By using this lead frame, depression working is enabled even in the case where the distances between outer frames 1, 2 and the island 3 end portions can not be ensured so as to be sufficient to contain the depression end portions in a resin seal region, on account of the size of a chip 6.
Patent JP-S63111648-A (JP)
Title: Semiconductor device and manufacture of the same
Inventor: ARAI HAJIME
IPC: H01L21/768
Filed: 1986-10-30
Abstract: PURPOSE:To suppress decrease in reliability within a semiconductor due to generation of detects such as crack of an insulating film by forming an oxide film or a nitride film on the surface of wiring and a SOG (spin on glass) film for flattening the shape of a section such as a stepped portion of wiring of a contact hole to the insulating film surface or to the surface of an oxide film or a nitride film. CONSTITUTION:A contact hole 3 is formed by etching the determined portion of insulating film 2 formed on the surface of silicon substrate 1. Next, an aluminum film 4 is formed to the surface of insulating film 2 and the contact hole 3 and an aluminum wiring 40 is formed by selectively etching the aluminum film 4. Thereafter, when the surface of aluminum wiring 40 is oxidized by the plasma processing under the oxygen gas atmosphere, a dense aluminum oxide film 9 is easily and economically formed in the thickness of 100-1000Angstrom  on the surface of aluminum wiring 40. Next, the SOG film 81 is formed by coating the surface of insulating film 2 and aluminum oxide film 9 with the SOG solution and baking the surface thereof.
Patent JP-2001085280-A (JP)
Title: Electrode in sheet form and its manufacture
Inventor: NAKAMICHI SHOJI
IPC: H01G11/38
Filed: 1999-09-13
Abstract: PROBLEM TO BE SOLVED: To enable to manufacture electrodes in thin sheet form exhibiting homogeneous properties by one rolling operation in a long size and to mass- produce such electrodes in sheet form on industrial scale and efficiently. SOLUTION: In the method for manufacturing the electrode in sheet form, a preliminary formed body, which is composed of carbon fine powder, a polymer resin containing fluorine and a liquid lubricant, and whose maximum length (d) in the direction of compression and maximum length d0 in lateral direction orthogonal to the direction of compression in its section perpendicular to the length are in the relationship satisfying the inequality, 0.1<d<d0<10 is subjected to rolling operation on one axis or plural axes.