Patent GB-797000-A (GB)
Title: Electrical computing engines
Inventor: PETHERICK EDWARD JOHN
IPC: G06F7/491
Filed: 1954-10-01
Abstract: 797,000. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Sept. 15, 1955 [Oct. 1, 1954], No. 28393/54. Class 106 (1). A translator for a digital electric computer derives multiplier factors from a number expressed in a cyclic permuting binarydecimal code as described in Specification 762,284, [Group XXXVIII], in which each decimal digit is represented by a complementary binary digit (W) which indicates whether or not the decimal digit is greater than 4, and by three further binary digits which are the same for the decimal digit and its nines complement, the translation being made by changing the digit W in each decimal-digitrepresenting binary word if the sum of binary digits in words representing decimal digits of greater significance is odd to provide rectified complementing binary digits, detecting dissimilarity between rectified complementing binary digits for adjacent decimal orders, decoding the further binary digits to yield in each case a multiplier factor of value N < 5, or (N + 1) if a dissimilarity is detected between the complementing digits in that word and the word of next lower significance, and indicating that a multiplier factor is negative if the rectified complementing binary digit in the corresponding word indicates a decimal digit greater than four. The translating is effected in a manner similar to that described in Specification 762,284, the derived multiplier factors being used to effect multiplication, e.g. as described in Specifications 745,833 and 745,879. As shown in Fig. 1, three binary words representing a 3-digit decimal number are applied in parallel on lines 11-14, 15-18 and 19, 32-34 (positive for " 1 " zero for " 0 "). The lines 11, 15, 19 receive the complementing digits W, and rectified complementing digits are obtained from the outputs of 4, 8 in a series of not-equivalent gates 1-8, dissimilarity being detected in further notequivalent gates 9, 10. The output of 9, 10, the rectified complementing digits and the further binary digits are applied to coincidence gates arranged in decimal-digit groups as shown having outputs 40a-14a, 40b-44b and 40c-44c each group being rendered effective in turn by a pulse from unit 45. Outputs 40a-40c, when positive, represent a negative multiplier factor; outputs 41a-43c, and 44a-44c, represent the further binary digits and a factor (N + 1) respectively, and are applied to common lines 41-44, Fig. 2, of a decoding network of coincidence and inhibiting gates which energizes one of output lines X0-X5 to represent the value of the derived multiplier factor. Line 11, Fig. 1, is connected also to gates 21, 38 which are pulsed by unit 45 to indicate whether the first multiplier factor is " 1 " or " 0." The translator may be extended to handle larger numbers by repeating the set of gates enclosed by line 61, Fig. 1. In an alternative translator (Fig. 3, not shown), the binary digits are set up on electromagnetic relays which control contact networks selected in turn by a uniselector, the dissimilarity detector comprising a two-winding differential relay (J). Reference is made to operations with information presented in serial, instead of parallel, form. Specification 717,114 also is referred to.