Patent GB-1350753-A (GB)
IPC: G06G7/186
Filed: 1970-04-14
Abstract: 1350753 Transistor amplifier and gating circuits; automatic frequency control INTERNATIONAL ELECTRONICS Ltd 5 July 1971 [10 April 1970] 17164/70 Headings H3T and H3A [Also in Division G4] To correct for current drift in an amplifier 62 in a dual ramp digital voltmeter (see Division G4), a pedetermined voltage from a standard cell is applied via the amplifier to an integrator for a predetermined time. It is then replaced by a reference potential of opposite polarity to discharge the integrator to zero at which time a comparator feeds a signal to a memory in a logic circuit (67, Fig. 5, not shown) which is set to its "1" or "0" state in dependence on whether or not a counter (64) counting clock pulses from an oscillator (65) has reached a predetermined count. The memory output is connected via terminal 134 (Fig. 7) to the gate of a field effect transistor 133 so that a correction signal is applied to the gate of a field effect transistor 122 in a long tailed pair, the input signal also being applied to the gate. To correct for voltage drift the predetermined voltage is again fed to the amplifier via a small impedance. After a predetermined time it is replaced by the reference potential and as in the case of correction for current drift a memory in the logic circuit is set in accordance with the time of arrival of the comparator signal. The memory output is applied via terminal 138 to the gate of a field effect transistor 137 to apply correction to the gate of the other field effect transistor 123 in the long tailed pair. The amplifier output is connected when field effect transistor switches 146, 147 (Fig. 8) are cut off to the gate of one of a pair of field effect transistors 162, 163, the antiphased voltages across the load resistors of these transistors being applied to integrating amplifier 164. When a switch 150 comprising a further pair of field effect transistors is cut off a reference signal is applied to the amplifier. To produce a desired relationship between the frequency of oscillator 65 pulsing counter 64 and the mains frequency at terminal 200 (Fig. 10), after division in a binary divider 201, 202 the mains signal is applied to AND gates 205, 206 receiving at their other inputs mutually inverted signals at the same nominal frequency. Consequently a signal from either capacitor 207, or 208 will be applied to the junction of either diode pair 209, 209a or 210, 210a to vary the potential on a capacitor 211. This potential is applied to the gate of a field effect transistor 212 so that potential taken from potentiometer 214 to the base of transistor 215, the emitter of which is connected to oscillator 65, depends on the potential of the capacitor. In alternative embodiment (Fig. 4, not shown) a voltage to which an oscillator is to be locked is received at a terminal (42) and shaped in a shaping circuit (43) one edge of an output pulse from which resets a counter (44) to count pulses from the oscillator. At a predetermined count the counter delivers a signal to logic circuitry (45) which gives an output of one of two output terminals (46, 47) in dependence on whether the signal precedes or follows a pulse from the shaper, to one of two capacitors (48, 51) to raise or lower the potential on a capacitor (50) and hence adjust the oscillator frequency.