Patent GB-754908-A (GB)
Title: Improvements in or relating to apparatus for the time-displacement of electrical impulses
IPC: H03K5/13
Filed: 1954-09-24
Abstract: 754,908. Pulse delaying circuits. SIEMENS & HALSKE AKT.-GES. Sept. 24, 1954. [Sept 24, 1953], No. 27680/54. Class 40 (6). In a pulse delaying circuit a series of pulses is applied from a pulse generator to a pulse counter circuit from the instant at which a datum pulse is set-up, the output pulsefrom the counter being delayed with respect to the datum pulse by a period which is dependent upon the repetition frequency of the pulses in the series and the counting ratio of the counter. Fig. 1 shows a counter in which a pulse train from generator G is applied via a switch S, which is closed by a datum pulse applied at E2, to a counter comprising a chain of two stable state binary counting stages D1, D2 ... D6. When the 64th pulse from G has been applied an output pulse is produced at stage D6 and is applied via transformer U1 to give a positive output pulse at E4, this pulse is also applied to input E3 of switch S to open it and disconnect the pulse train from G. Each stage D1, D2, &c. may comprise a conventional trigger-pair as shown in Fig. 2 in which the negative triggering pulses are applied at E6 via rectifiers G12, G13 to the grid circuits. The switch may comprise a trigger-pair circuit R3, R4, as shown in Fig. 3, the output from which is applied to a coincidence tube R5 which produces a negative output pulse at E only when a positive pulse at E12 and a positive pulse from generator G are present simultaneously. In order to provide an output pulse after any predetermined period the output pulse from the counter may be applied via a delay line to give the required output pulse. In a modification shown in Fig. 5 a delay line L1 is associated with a 6-stage counter D1, D2 ... D6 to give an output pulse delayed by 100 pulse periods. When an input pulse is applied, switch S is closed and an output pulse is produced at E4 after 64 periods which closes switch S1, which is similar to switch S, thus when the counter has received a further 32 pulses an output is received from stage D5 and passes via switch S1 to line L1 ,which delays it by a further 4 periods so that the output pulse at E9 is delayed by 100 periods. The output from switch S1 opens switch S and a pulse from a tapping A2 on line L1 after phase-reversal in transformer U2 re-sets stage D6 to the normal stand-by condition. Rectifier G12 prevents this pulse from passing via rectifier G11 and switch S1 to line L1. Switch S1 is opened by a pulse from tapping A1 on line L1. In a further modification shown in Fig. 6, a delay of a predetermined number of pulse periods is obtained by pre-setting individual stages of the counter to the off-normal position. Thus stages D1, D3, D4 and D5 are in the off-normal and stages D2, D6 and D7 in the normal or stand-by position so that the counter is already in the condition it would occupy for 29 input pulses thus since the normal count is 128 the 99th impulse applied from generator G will produce an output pulse at E4 and after being delayed in delay line L2 a delay of 100 pulse periods will be obtained. The stages D1, D3, D4 and D5 are re-set by negative pulses applied from tapping A3 on line L2 after an output pulse of 100, pulse period delay has been produced at E4 and switch S is opened by the pulse produced at E4. The counter may be pre-set to a pre-determined count as shown in Fig. 8 by setting the complement of the required number of pulse periods into the pulse storing device comprising binary counting stages M1, M2 ... M7, the individual outputs of these storing stages then setting the stages D1, D2 ... D7 of the counter via switches V1, V2 ... V7. In a further modification, Fig. 9 (not shown), a delay line is included in the output of the main counter. Fig. 10 shows a free-running delay circuit, the output pulse of E4 being applied to open switch S to disconnect the pulses from generator G, the same pulse after being applied via delay line L4 closing switch S to re-start the cycle.