Patent GB-1350781-A (GB)
Title: Multiplexer
Inventor: SANDERS R W
IPC: G06F5/06
Filed: 1971-04-19
Abstract: 1350781 Multiplex system COMPUTER TRANSMISSION CORP 19 April 1971 [17 March 1970] 23252/71 Heading H4L In a time division multiplex system for use with data communication systems, by means of which a number of different data rate sources or utilization devices may be connected into a common transmission channel, a number of data terminal transmission adapters (TTA) which adjust the rate, compensate for delays and combine and interleave data such as to enable its ready separation and utilization at the opposite end of the transmission medium, are used. The system employs a single master clock for the entire system. Two different TTA configurations are used, one designed for use in serial or loop systems, Fig. 7, and one for tree configuration systems (Fig. 1). The tree TTA's include a timing generator which accepts high speed clock and frame pulses and by selection of a data rate conversion factor (alpha) produces clock and frame pulses at the required low speed rate. An encoder receives outgoing low rate data, introduces the required delay for proper time slot multiplexing and combines the data into the high rate of the transmission channel. A decoder performs the inverse operation. The TTA's for use in serial or loop systems (Fig. 8, not shown) employ basically the same operational elements but are arranged to allow the through transmission of data as well as data combining and data selection. The TTA's include controllable delay equalizers capable of being adjusted for normal system transmission delay as well as TTA processing delay. A variable delay compensator and circuitry track framing pulses accompanying transmitted data whereby variations in propagation delay are detected and automatically corrected. A data rate combiner, Fig. 10, combines (or separates) the rate of two incoming streams of data by an amount equal to the ratio of any two integers, a memory module with write and read address counters and clocking circuitry generates two clock signals at each of the two low sweep data rates phase locked to the single high speed data rate. The TTA for a tree configuration comprises a timing generator 20 responsive to incoming high speed clock c and frame signals f to produce submultiple clock C and frame signals F at the required low speed data rate, and an encoder 22 adapted to be connected to a plurality of low speed data sources (B1 ... B2). The timing generator 20 includes counting means 25 driven by the incoming clock pulses &c., a switch means 26 for selecting one of a series of submultiple clock signals, a pulse generator 30 producing the low speed clock pulses C, and a frame counter 33 connected to the source of high speed frame signals f, to produce the low speed frame pulses F. The encoder 22 comprises a parallel to serial converter 42 with a plurality of parallel input terminals for the low speed data sources, and a high speed data output terminal 45, the low speed clock and frame signals from the timing generator 20 being used to define a frame of low speed data, the high speed clock pulses &c. being applied to the encoder to advance frames of data from the low speed sources to the high speed data output terminal. Controllable delay means including a shift register, between the source of low speed clock and frame signals and the parallel to serial converter delay time, compensate the outgoing data for proper time slot transmission. Switching logic means 40 selects the delay compensation. The tree TTA also includes a decoder 21 comprising a serial to parallel converter, fed with a serial high speed data and low speed frame and clock pulses where by to discharge data in parallel to low speed utilization devices A 1  ... Aα and at the low speed frame rate. The TTA for serial configuration (Fig. 8, not shown) is an adaptation of the tree TTA wherein the timing generator includes a multistage counter holding at least one frame of high speed clock pulses and coupled to means for deriving the low speed clock pulses C, the incoming data being stored in storage means via output logic means which selectively pass high speed serial data through the multiplexer or into said storage means, low speed frame and clock pulses discharging data from said storage means at low speed. The data rate changer combiner, Fig. 10 comprises a storage memory 60, a write address counter 61, a read address counter 62, the serial data being introduced into the memory through the write address counter at the incoming frame rate; and means for generating a read drive signal from the incoming data rate, and comprising a phase looked loop circuit including a mixer 71, a low pass filter 72 and a voltage controlled oscillator (VCO) 73 connected in loop configuration, a clock signal derived from incoming data being applied to the mixer; means 74 dividing the output of the VCO 73 by an integer P; means for applying the so divided output to the mixer; means 76 dividing the VCO output by an integer N and applying the so divided output to the read address counter as the read signal to the counter.