Patent GB-1292142-A (GB)
Title: Fault protection devices
IPC: H02H3/093
Filed: 1969-10-07
Abstract: 1292142 Protective arrangements WESTINGHOUSE ELECTRIC CORP 7 Oct 1969 [7 Oct 1968 (3)] 46092/69 Heading H2K An overload protective arrangement comprises a level detecting circuit 260 connected to receive rectified pulses having the same configuration as, and a magnitude directly proportional to, the half wave portions of the current in a protected A.C. circuit and producing an output signal instantaneously when the pulses exceed a predetermined value, a timing circuit to maintain the output signal for a predetermined time when the magnitude of the pulses falls below the predetermined value, and pulse generating means 230 controlling the charging of a timing capacitor C4 when permitted to do so by the output signal. In the arrangement shown, bridge rectifiers 22, 24, 26 are connected to current transforming arrangements of a protected three phase network (not shown) and to current auctioneering circuits 110, 120 to provide output signals V1, V2 proportional to the largestline current. The bridge rectifiers are also connected to a power supply circuit comprising a storage capacitor C13 and diodes D23, Z1, Z2, D25 to provide operating supply potentials P1 ... P3. A control circuit 150 prevents operation of the arrangement until the charge on the capacitor C13 is sufficient. A transistor Q5 provides a signal proportional to the largest current to a pulse generator Q4 to produce a pulse signal having a frequency dependent on the magnitude of the current periodically to render non-conducting a transistor Q7 which shunts the signal from a transistor Q6 away from the timing capacitor C4. Since the signal from the transistor Q6 is proportional to the current, the charging of the capacitor C4 will depend on the square of the largest line current. The level detector 260 comprises transistors Q8, Q9 and its timing circuit is formed by a capacitor C5, the output signal from the detector rendering a shunting transistor Q10 non-conductive so that the capacitor C4 is permitted to charge. After a relatively long time delay the capacitor C4 is charged sufficiently to cause an output circuit 410 to render a controlled rectifier Q17 conductive to energize the trip coil (not shown) of a circuit breaker. An auxiliary pulse generating circuit 240 may be provided to increase the sensitivity by periodically raising the voltage at the capacitor C4. An instantaneous tripping circuit 300 comprises a transistor Q18 which provides an output signal through an isolating diode D40 to the output circuit when a high line current occurs on the closing of the circuit-breaker contacts before the contacts are latched in. When the contacts are latched, auxiliary contacts AC1 close to render the circuit 300 inoperative. A short delay tripping circuit 500 comprises a level detecting circuit, with transistors Q11, Q12 and a capacitor C6, which permits the charging of a capacitor C7 when the line current exceeds a predetermined high value. The capacitor C7 is connected via an isolating diode D37 to the output circuit 410. A circuit 600 responsive to ground faults comprises a bridge rectifier D1 ... D4 connected to a ground current transformer (not shown), the rectifier being connected by a resistor R28 to the conductor P1 to charge the capacitor C13, Fig. 2, to provide the operating potentials, and by a resistor R26 to a level detecting circuit 610. When the ground fault current reaches a predetermined level, the circuit 610 permits a capacitor C10 to charge and after a fixed time delay, the voltage across the capacitor causes the operation of the output circuit 410. The output of the level detecting circuit 610 is also applied through a diode D42 to the transistor Q10 to render it non-conductive so that it does not prevent operation of the output circuit 410.