Patent GB-963831-A (GB)
Title: Improvements in or relating to pulse code modulation signalling systems
Inventor: DAVIS JOHN CHRISTOPHER HAMMOND
IPC: H04B14/04
Filed: 1959-12-08
Abstract: 963,831. Pulse code modulation systems. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. Feb. 24, 1961 [Dec. 8, 1959], No. 41757/59. Heading H4L. In a pulse code modulation system a feedback encoder operating on an electrical comparison basis and employing a plurality of resistors of binarily related values is arranged to convert the information represented by the selection of the resistors into a code having a smaller number of terms than the number of resistors, the conversion being effected by a number of tests equal to the number of terms, each of the tests being adapted to include any desired number of the resistors. This arrangement provides non-linear encoding, e.g. for amplitude compression, similar to that described in Specification 889,370, a six-digit code being used to deal with ten binary stages. As in the prior Specification, the first three digits determine the most significant resistor, i.e. the position of the first " 1 " in the hypothetical ten-digit binary number and the remaining three digits represent the rejection or inclusion of further resistors, the presence or absence of any larger, i.e. less significant resistors being ignored. At the encoder, Figs. 2 and 3, the incoming signal sample at S is applied to the common connection of resistors R, 2R . . . 512R, encoding being effected by toggles M1-M10 controlled by timing waves T1 to T8, the binary coded output of the comparator C being sent to line L via a limiter if necessary. Timing pulses T8 and T1 bring all the toggles to the starting position in which only M4 is operated, but the circuits for this are not shown and waveforms T1, T7, T8 are not shown in Fig. 3. During pulse T2, toggle M4 is reset and either M2 or M6 is set according to whether the output of the comparator is C or C, and during pulse T3 toggles M2 or M6 are reset and one of the toggles M1 M3, M5 or M7 is operated as determined by whether M2 or M6 was set and the output of the comparator was C or C. During pulse T4, if M1 is operated, M2 is operated, and if the output is C, M1 is reset and M3 also operated. If M3 is operated, M4 is set, and if the output is C, M3 is reset and M5 operated. If M5 is operated, then M6 is operated, and if the output is C then M5 is reset and M7 operated. If M7 is operated, then M8 is operated, and if the output is C then M7 is reset. The output C has been sent out on the line L during these periods and the circuits are now set for determining the remaining three digits. If the position of the most significant current, i.e. the lowest value resistor, is position 1 corresponding to the first three digits 111 or no initial 0's, the toggles operated will be M1 and M2, M2 enabling the comparator to be effective during pulses T5. Thus during T5 with M1 set, M3 is operated, and if the output is C, M2 is reset, and during period T6 with M1 set, M4 is operated, and with output C, M3 is reset. Similarly, if the most significant digit is in position 2 corresponding to digits 110 with M2 and M3 set, during pulse T5, M4 is operated and if the output is C, M3 will be reset, and during pulse T6 with M2 and M4 set, M5 is operated, and with output C, M4 is reset. The circuits for the most significant digit in positions 3, 4, 5 and 6 in the hypothetical ten-unit code follow the same principles. During pulse T7 the comparator operates normally and transmits a pulse to line, but there are no further logical operations on the state of the toggles. If there are seven or more initial 0's in the hypothetical code the digits representing the choice of the last three resistors are transmitted unchanged. In this case, at the end of pulse T4 only toggle M8 will be set, during pulse TS, M9 will be set, and if the output is C, M8 will be reset. During pulse T6, with M9 operated, M10 is set, and with output C, M9 will be reset. A decoder operating on similar principles is described, although the decoder described in Specification 889,370 is stated to be suitable. Multiplex system. The apparatus may be included in a time division multiplex system and to reduce cross-talk the signals may be transmitted over a plurality of lines on a time division basis under the control of synchronously operating distributers at opposite ends of the lines, pulse lengtheners being included in each line circuit. In a further arrangement for reducing cross-talk, Fig. 9, in which switches S1 &c. for the various channels are closed sequentially and the signal is supplied via a transformer having a tapped secondary winding, the cross-talk due to the leakage impedance Z2 across the switch S1 is counterbalanced by a voltage derived from an impedance Z3. It is suggested that further cross-talk due to overlap in time of the channel signals in impedance Z1 may be reduced by arranging that alternate channel signals are reversed in polarity prior to decoding.