baber/WOPTO huggingface dataset:
Patent TW-417032-B (TW)
Title: Bistable nematic liquid crystal device
Inventor: BANCROFT MARTIN STUART
IPC: G02F1/139
Filed: 1995-03-16
Granted: 2001-01-01
Abstract: The invention provides a nematic liquid crystal device with two bistable switched states. The device comprises two cell walls carrying electrodes structures and enclosed a layer of a nematic liquid crystal material. The cell walls are treated to provide a bigrating on one or both walls. The bigrating is a shaped surface that permits liquid crystal molecules t a surface to lie in two different angular directions, eg 45 DEG or  90 DEG apart, in contrast with conventional surface alignments which align liquid crystal molecules in a single direction at a surface. For a cell with bigratings on both walls the two alignment direction on both walls are in register. Polarisers are arranged in front and behind the cell with their optical axes orthogonal and with the optical axis of one polariser parallel to one of the switched alignment. In this example, as the material is switched between the two alignment states the polariser transmit or block light. The bigratings may be symmetric or asymmetric, in which later case an amount of surface tilt is obtained. Appropriate surface tilt on both cell walls may give a splayed molecular configuration in both switched states. For splayed configurations, the device may be electrically switched using flexoelectric coupling. For other configurations the device may be switched by use of de pulses in combination with chiral ions in the liquid crystal material. The bigratings may be produced by interferography, photolithography, embossing, ruling, or transferred from a carrier layer. A bigrating on one cell wall may be combined with a conventional monograting or eg rubbing alignment treatment on the other cell wall.  In this case the material is twisted in both its switched states.
Patent TW-257910-B (TW)
Title: Programmable source address locking mechanism for secure networks
Inventor: WILLIAM LO
IPC: H04L12/46
Filed: 1995-03-21
Granted: 1995-09-21
Abstract: In a managed repeater having an address learn capability in which receipt at a particular port of a data packet having a received source address different from a stored source address associated with the particular port replaces the stored source address with the received source address, a source address locking circuit includes an address learn circuit associated with the particular port, for replacing the stored source address with the received source address when the stored source address does not match the received source address, and an address lock register for the particular port, coupled to the address learn circuit, for storing a bit value to disable the address learn circuit from replacing the stored source address with the received source address. This managed repeater provides improved security in a network having source address updating by allowing an administrator to disable the source address update for a particular port in the managed repeater. Each address lock register is externally programmable, and the administrator is able to program time windows to disable source address updating for a particular port. The administrator may program each address lock register independently to prevent the stored source address associated with each port from being updated. The managed repeater allows the administrator to determine on a per port basis whether the managed repeater's address learning capability should be enabled or disabled for a programmable time window.
Patent TW-283775-B (TW)
Title: Linear prediction coefficient based inverse spectrum coefficient generator
Inventor: WANG JIUNN-FA
IPC: G10L19/06
Filed: 1995-10-11
Granted: 1996-08-21
Abstract: A linear prediction coefficient based inverse spectrum coefficient generator, which processes linear prediction coefficient according to one inverse spectrum coefficient equation, comprises: first memory unit for continuously storing the linear prediction coefficient; second memory unit for continuously storing inverse spectrum coefficient which will be generated; third memory unit for continuously storing several constants; one control module electrically connected to the first, second and third memory unit, in which the control module could operate to control the first memory unit to output one of the linear prediction coefficients, and to control the second memory unit to output one of the inverse spectrum coefficient, and control the third memory unit to output one of the constants; one multiplier electrically connected to the first, second and third memory unit, in which the multiplier generates one of the choices in the linear prediction coefficient, one of the choices in the inverse spectrum coefficients and one of the choices in the constants; one adder which has one first data input device for receiving the another one in the linear prediction coefficients, second data input device for receiving product generated from the multiplier, and one output end electrically connected to the second memory unit, in which the adder generates the sum of product from the multiplier and another one in the linear prediction coefficients from the first memory unit on the output end of the adder, and getting the inverse spectrum coefficient form the output end of the adder; the control module controls the second memory unit to continuously store the inverse spectrum coefficient from the adder.
Patent TW-303509-B (TW)
Inventor: RONALD R UTTRECHT
IPC: H01L23/50
Filed: 1995-11-29
Granted: 1997-04-21
Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers (60) to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip (52). Opposite rows of substantially flat cantilevered lead-fingers (60) are attached by double-sided adhesive tape (55) in thermal contact with the active face of a chip (52). The lead-fingers (60) are routed in personalized paths over the face of the chip (52) to cover a large surface area to aid heat dissipation. All wirebond connections (63) between the lead-fingers (60) and the chip (52) are made at a centerline connection strip running down the center of the chip (52). Each of the cantilevered lead-fingers (60) has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.
Patent TW-330834-B (TW)
Title: Method of controlling a hemiptera pest in a paddy field
Inventor: HIRAOKA HIROSHI
IPC: C05G3/60
Filed: 1996-02-24
Granted: 1998-05-01
Abstract: A method of controlling a hemiptera pest in a paddy field which comprises side-dressing a pesticide containing fertilizer composition including a fertilizing component and a nitromethylene-,nitroimino- or cyanoimino-series pesticidal compound in which water solubility is at least 100 ppm in the paddy field at the time of transferring seedings.
Patent TW-400425-B (TW)
Title: Combustion apparatus
Inventor: ANDO ATSUSHI
IPC: F24H3/04
Filed: 1996-04-08
Granted: 2000-08-01
Abstract: To provide a combustion apparatus which has more improvement in safety. The apparatus consists of transistors 14, 15 connected in series between ""out"" terminal of the holding coil 12-regulator 911, a frame rod 800 for detecting the combustion flame and outputting the flame detection signal 801, and combustion detection circuit 81, 82 which output ON signals 811, 821 to transistors 14, 15 while the flame rod 800 outputs flame detection signal 801.
Patent TW-350189-B (TW)
Title: A bus controlled arrangement using a duty cycle modulated control signal
Inventor: WILBER JAMES ALBERT
IPC: H04N9/29
Filed: 1996-07-08
Granted: 1999-01-11
Abstract: A sort of bus controlled arrangement using a duty cycle modulated control signal, having a converter, for generation of a light beam control field in the cathode emission tube; a transistor switch having a controllable work cycle; an amplifier with output coupling to have the wave beam being controlled; a feedback network coupled to the amplifier output and the first input of the amplifier, for controlling the first input voltage; and a primary conductor lead coupled to the transistor switch and the first input raised resistor of the first input voltage, for generation in the resistor a switch current, having a work cycle and a range, being the first controlled by the transistor switch and the latter by the input voltage.
Patent TW-321722-B (TW)
IPC: H04B3/462
Filed: 1996-08-22
Granted: 1997-12-01
Abstract: The duration measurement device measures the transfer duration of a signal in a digital transfer unit (1) with higher (2) and lower (3) ranking terminals. A timing signal (15) is sent via the transfer unit from the higher to the lower terminal using a transmitter (12) and receiver (5). The received timing signal (7,7') is passed either directly to a transmitter (9) for sending back to the higher terminal, or via a synchronisation unit (8). A receiver (16) in the higher-order terminal receives the timing signal. A phase comparator (19) compares the phase of the timing signal emanating directly from the source (14) with that of the received timing signal (18), the output of which is used by a calculation part (20) which computes the signal transfer duration.
Patent TW-343319-B (TW)
Title: Optical scanning apparatus for a multi-layer record carrier, including a focus control circuit
Inventor: ANTONIUS HERMANUS MARIA AKKERM
IPC: G11B7/00
Filed: 1996-08-22
Granted: 1998-10-21
Abstract: Optical scanning apparatus for scanning an optical record carrier having at least first and second superjacent information layers, comprising: an optical system including means for focusing a radiation beam to a focal point, focus actuator means for controlling the focusing means to shift the focal point in a direction perpendicular to the information layers, a focus error detector for deriving a focus error (FE) signal indicative of the direction and distance between the focal point and the information layer to be scanned, a focus control circuit for deriving a focus actuator drive signal in response to the FE signal and supplying the drive signal to the focus actuator means to cause the focus actuator means to maintain the focal point substantially on the information layer to be scanned, a first controller for generating a binary loop-control signal which assumes a first logical value controlling a modification of the functionality of the focus control circuit after receiving a layer-jump command signal for changing the scanning from the first to the second information layer and a second logical value controlling the restoring of the functionality, the optical scanning apparatus being characterized in comprising: a second controller for generating a close signal corresponding to the focus error signal, and an inhibiting device for inhibiting the conversion of the close signal during the period during which the focus error signal circles a zero crossing point in conformance with continuous zero crossing points of the information layer.
Patent TW-318933-B (TW)
Title: Semiconductor IC device having a memory and a logic circuit implemented with a single chip
Inventor: WATANABE TAKAO
IPC: G11C7/02
Filed: 1997-03-04
Granted: 1997-11-01
Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.
Patent TW-531682-B (TW)
Title: Process and materials for imagewise placement of uniform spacers in flat panel displays
Inventor: STARAL JOHN SCOTT
IPC: B41M5/40
Filed: 1997-06-13
Granted: 2003-05-11
Abstract: Process and materials are described for selectively placing uniform spacers on a receptor. Spacer elements are placed on a receptor by selectively irradiating a thermal transfer donor sheet comprising a transferable spacer layer. The transferable spacer layer may include particles or fibers to form a composite. The particles may have a spacing dimension either greater than or less than the thickness of the transferable layer. When the spacing dimension of the particle is greater than the thickness of the transferable layer, then the spacing dimension of the particles control the spacing distance. The process and materials are useful in the manufacture of flat panel displays, particularly, liquid crystal display devices.
Patent TW-413699-B (TW)
Title: Bismuth vanadate pigment powder mixtures
Inventor: ERKENS LEONARDUS J HUBE
IPC: C08K3/22
Filed: 1997-06-16
Granted: 2000-12-01
Abstract: Pigment powder mixtures, consisting of 0.999-0.5 part of C.I. Pigment Yellow 184, and 0.001-0.5 part of an organic pigment selected from the group consisting of C.I. Pigment Orange 13, C.I. Pigment Orange 34, C.I. Pigment Orange 36, C.I. Pigment Orange 73, C.I. Pigment Red 170, C.I. Pigment Red 254, C.I. Pigment Red 255 and C.I. Pigment Red 264, or of 0.99-0.5 part of C.I. Pigment Yellow 184, and 0.01-0.5 part of an organic pigment selected from the group consisting of C.I. Pigment Yellow 83, C.I. Pigment Yellow 110 and C.I. Pigment Yellow 139. These pigment powder mixtures are distinguished, in particular in paints, by very high chroma.
Patent TW-343357-B (TW)
Title: Projection exposure device, projection exposure method, mask pattern for amplitude aberration evaluation, amplitude aberration evaluation method
Inventor: KAMON KAZUYA
IPC: H01L21/027
Filed: 1997-09-19
Granted: 1998-10-21
Abstract: A projection exposure device illuminating a mask by an illuminating light from a light source and projecting a circuit pattern by forming an image on an exposed substrate using the diffraction light from the illuminated mask by a projection optical system; in which the projection optical system comprises: a first semi-reflector, a first concave mirror for reflecting the reflection light or transmission light of the first semi-reflector, a second semi-reflector installed independent of the first semi-reflector, and a second concave mirror for reflecting the reflection light or transmission light of the second semi-reflector.
Patent TW-378262-B (TW)
Title: Control apparatus for hydraulically operated vehicular transmission
Inventor: MIYAMOTO OSAHIDE
IPC: F16H61/00
Filed: 1997-09-22
Granted: 2000-01-01
Abstract: Even if a rotational speed of an engine has already increased due to slipping of a fluid torque converter at the time of start of downshifting, a smooth downshifting is performed. For that purpose, there is obtained a speed change developing degree function K(etrm) of the rotational speed of the engine at the time of start of downshifting, the developing degree being dependent on an increase in the rotational speed of the engine due to slipping in the fluid torque converter. The function K(etrm) is obtained with a speed ratio ""etrm"" of the fluid torque converter at the time of starting of downshifting as a parameter. A boosting correction value QDNOFFZ is computed by multiplying a reference correction value QDNOFFZO by K(etrm) (step S108-5). The hydraulic pressure of the hydraulic engaging element on the disengaging side during downshifting is boosted by the amount of QDNOFFZ (step S108-6).
Patent TW-365097-B (TW)
Title: Despreading of direct sequence spread spectrum communications signals
Inventor: BOTTOMLEY GREGORY E
IPC: H04L27/32
Filed: 1997-10-30
Granted: 1999-07-21
Abstract: The disclosure presents a number of reduced complexity architectures for despreading direct sequence spread spectrum communications signals. In a first despreading architecture for a sequence removal unit, received chip-spaced complex samples are negated in accordance with the processed phase of a complex spreading sequence. Furthermore, the in-phase and quadrature phase sample values are switched for each other in accordance with the processed phase. In a second despreading architecture, in a sequence removal unit, received chip-spaced complex samples are processed in the logarithmic domain, with the phase of the complex spreading sequence added to the detected phase, and the resulting complex signal then converted back to Cartesian coordinates. In a third despreading architecture for a correlator, sequence removal and correlation are performed in the logarithmic domain with the amplitudes and phases for the resulting complex signal arithmetically averaged and then converted back to Cartesian coordinates. In a fourth despreading architecture also for a correlator, sequence removal and correlation are performed in the logarithmic domain using circular averaging. In a fifth despreading architecture also for a correlator, wherein multiple component sequences are combined together to form an overall sequence, and wherein one of the multiple component sequences is shared by all channels, a common sequence removal is provided for removal of the shared sequence from all channels. The resulting signals are then sent to a plurality of individual correlators for removal of channel specific sequences.
Patent TW-382669-B (TW)
Title: Semiconductor integrated circuit and data processing system
Inventor: SASAKI KAZUHIRO
IPC: G06F1/08
Filed: 1997-11-18
Granted: 2000-02-21
Abstract: A MOS transistor constituting a semiconductor integrated circuit (16) has a 1st state in which the MOS transistor is operated with a 1st threshold voltage at a 1st clock frequency and a 2nd state in which the MOS transistor is operated with a 2nd threshold voltage higher than the 1st threshold voltage at a 2nd clock frequency lower than the 1st clock frequency. When the operating state is changed from the 1st state to the 2nd state, the clock frequency is changed from the 1st clock frequency to the 2nd clock frequency and then the threshold voltage of the MOS transistor is changed from the 1st threshold voltage to the 2nd threshold voltage. When the operating state is changed from the 2nd state to the 1st state, the threshold voltage of the MOS transistor is changed from the 2nd threshold voltage to the 1st threshold voltage and then the clock frequency is changed from the 2nd clock frequency to the 1st frequency. The control is performed by a 1st logic circuit (10) through a clock control circuit (14) and a substrate bias control circuit (12). With this constitution, a state in which priority is given to the processing speed and a state in which reduction of a subthreshold leakage current has priority over the processing speed can be changed over from one to the other without error, and further the power consumption of the semiconductor integrated circuit can be reduced.
Patent TW-414883-B (TW)
Title: Improved dithering method and apparatus using ramp probability logic
Inventor: WILDE DANIEL
IPC: G09G5/02
Filed: 1997-12-30
Granted: 2000-12-11
Abstract: An improved method and apparatus for rendering curved surfaces in a graphics system. The appearance of a curved surface is created by varying color shades across an object. The graphics systems represents each primary color with fewer than eight bits. The present invention maintains smooth transaction between color shades despite using fewer than eight bits to represent color. An eight bit color shade value is truncated, with the most significant bits being saved and used as a color value. The least significant bits that are truncated are used to determine which of the adjacent color values to use to render pixels. Thus, if five bits are saved and used to represent a color, the three least significant truncated bits are used to determine the appropriate mix of the closest five bit shades. The three truncated bits are used to select an entry from a ramp table and a control signal from a look-up table selects a bit from the selected ramp table entry. The selected bit is used to determine which of the closest five bit shades to use for rendering a pixel.
Patent TW-349163-B (TW)
Title: A gas cooking stove for cooking the rice and the control method of the same
Inventor: TATEMATSU TETSUO
IPC: F23N5/02
Filed: 1998-01-14
Granted: 1999-01-01
Abstract: A gas cooking stove for cooking the rice comprising a heating device for heating a pot for cooking the rice contained therein, and capable of performing a high temperature dehydration cooking with a high power by the heating device prior to completion of the rice cooking, which is characterized in comprising: means for identifying whether or not there is high temperature dehydration rice cooking which identifies whether there is high temperature dehydration rice cooking according to the time information and the temperature information.
Patent TW-367632-B (TW)
Title: A method of making a trilayer battery separator
Inventor: YU WEI-QING
IPC: B29C55/02
Filed: 1998-04-01
Granted: 1999-08-21
Abstract: A method of making a trilayer, shutdown battery separator has the following steps: extruding a polyethylene precursor, extruding a polypropylene precursor; forming a trilayer precursor, the trilayer precursor having the polyethylene precursor sandwiched between two polypropylene precursors; bonding the trilayer precursor; annealing the trilayer precursor; stretching the trilayer precursor; and forming thereby the battery separator
Patent TW-472347-B (TW)
Title: Trench-isolated bipolar devices and methods of making the same
Inventor: NORSTROEM HANS
IPC: H01L21/331
Filed: 1998-04-02
Granted: 2002-01-11
Abstract: In order to produce an electrical connection to an inner layer such as a bottom diffusion (103), which has a good electrical conductivity and is located inside a bipolar semiconductor device isolated by trenches (119) and which for example forms a subcollector of a NPN-transistor, a hole (157) in a trench is used. The hole is filled with electrically conducting material and extends from the surface of the device to the bottom diffusion (103), so that the electrically conducting material in the hole is in contact therewith. The hole (157) is made aligned with a sidewall of the trench (119) by using selective etching. The hole can be made at the same time as contact holes for metallization are made and then also be filled in the metallization step, to contact the bottom diffusion. For a lateral PNP-transistor the hole can be made as a closed groove constituting the outer confinement of the base area, passing all around the transistor. The outer sidewall of such a closed trench can, as seen from above, be bevelled by 45 DEG, so that no inner corners having too small angles are found in the trench, what facilitates the filling with oxide.
Patent TW-381213-B (TW)
Title: Surge detector for power supply
Inventor: JANG NAI-SHUEN
IPC: G06F1/30
Filed: 1998-07-31
Granted: 2000-02-01
Abstract: The present invention provides a power supply surge detector for monitoring the power used by host processor in the computer whether there exists the surge. When the width or the number of surge could possibly influence the normal operation of host processor, the surge detector will send alarm signal to host processor, such as interrupt signal, or power management signal, to stop the normal operation of host processor. While the host processor can query surge detector by host interface whether the surge keeps happening, the host processor can reset the surge detector and reduce the working frequency of host processor to avoid the period of unstable power supply.