baber/WOPTO huggingface dataset:
Patent TW-511109-B (TW)
Title: Plasma display panel, manufacturing method of the same, and display apparatus of plasma display panel
Inventor: MIYASHITA KANAKO
IPC: H01J17/49
Filed: 2001-08-28
Granted: 2002-11-21
Abstract: A plasma display panel (PDP) for performing more stable discharge than conventional PDPs. When forming a protective layer on a dielectric layer, an intermediate layer is formed so as to enhance orientation of columnar crystals which constitute the protective layer. This gives orientation only to selected ones of the columnar crystals, and increases the diameter of the columnar crystals, compared with those in conventional PDPs. This means that the size of an exposed portion of the entire protective layer becomes smaller, and the amount of impurities absorbed by the protective layer is reduced. Therefore, the amount of the impurities that are absorbed by the columnar crystals and released during discharge is reduced, which improves discharge quality of the PDP.
Patent TW-525045-B (TW)
Title: Servo control method
Inventor: HAGIHARA JUN
IPC: H02P29/00
Filed: 2001-09-19
Granted: 2003-03-21
Abstract: A servo control method is disclosed, wherein during passing soft structures of at least two inertia systems connected with spring elements, the instruction and the load are not compliant; and, in order to conduct the necessary complex computation, it will cause the problem of too much computation. The servo control method using feed forward, it is characterized that: the positions of loading and motor are expressed with higher order differential functions, and the operation conditions 4 and the machine parameters 5 are used to decide the higher order differential functions; and, the defined higher order differential functions are used to calculate the position, speed, and torque instructions for the motor; the calculated position, speed, and torque instructions are used to calculate the torque instruction for the motor; and, inputting the calculated torque instruction to the model of the machine; then, the obtained position, speed and torque instruction of the motor are used as the feed forward instruction.
Patent TW-512464-B (TW)
Title: Method for forming shallow trench isolation region
Inventor: HUANG TZUNG-SHIUN
IPC: H01L21/31
Filed: 2001-10-19
Granted: 2002-12-01
Abstract: A method for forming a shallow trench isolation region comprises: sequentially forming a pad silicon oxide layer and a silicon nitride layer on a semiconductor substrate; removing a portion of the pad silicon oxide layer, the silicon nitride layer and the semiconductor substrate to form a trench in the semiconductor substrate; sequentially filling a first filling material, a second filling material, a third filling material in the trench and on the silicon nitride layer to form an insulative shallow trench isolation region in the semiconductor substrate, in which the first filling material, the second filling material, and the third filling material are filled by separately using a first high density plasma process, a second high density plasma process, and a third high density plasma process, and the deposition/sputtering ratio of the first high density plasma process, the second high density plasma process, and the third high density plasma process are 15 to 20, 3.5 to 4.5, and 4.5 to 6, respectively.
Patent TW-I267111-B (TW)
Title: Method and composition for the removal of residual materials during substrate planarization
Inventor: SUN LIZHONG
IPC: C09G1/02
Filed: 2001-11-30
Granted: 2006-11-21
Abstract: A method, composition, and computer readable medium for planarizing a substrate. In one aspect, the composition includes one or more chelating agents and ions of at least one transition metal, one or more surfactants, one or more oxidizers, one or more corrosion inhibitors, and deionized water. The composition may farther comprise one or more agents to adjust the pH and/or abrasive particles. The method comprises planarizing a substrate using a composition including one or more chelating agents and ions of at least one transition metal. In one aspect, the method comprises processing a substrate disposed on a polishing pad including performing a first polishing process to substantially remove the copper containing material, performing a second polishing process to remove residual copper containing material, the second polishing process comprising delivering a CMP composition to the polishing pad, mixing one or more chelating agents and ions of at least one transition metal in situ with the CMP composition, and removing residual copper containing materials from the substrate surface. The invention also provides a computer readable medium bearing instructions for planarizing a substrate surface, the instructions arranged, when executed by one or more processors, to cause one or more processors to control a system to perform polishing the substrate to substantially remove copper containing material formed thereon and polishing the substrate with a CMP composition comprising one or more chelating agents and ions of at least one transition metal to remove residual copper containing material.
Patent TW-516108-B (TW)
Title: Dual damascene process using oxide liner as dielectric barrier layer
Inventor: LEE SHYH-DAR
IPC: H01L21/316
Filed: 2001-12-18
Granted: 2003-01-01
Abstract: This invention discloses a dual damascene process applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. Firstly, an oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first dielectric layer and the second dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, then the excess conductive layer outside the trench region is removed and the conductive layer left in the dual damascene opening forms the dual damascene structure.
Patent TW-I232526-B (TW)
Title: Capping layer for improved silicide formation in narrow semiconductor structures
Inventor: GIEWONT KENNETH J
IPC: H01L29/423
Filed: 2002-01-04
Granted: 2005-05-11
Abstract: A capping layer for a semiconductor structure is described. The capping layer is deposited over a silicide-forming metal and has a composition such that nitrogen diffusion therefrom is insufficient to cause formation of an oxynitride from an oxide layer on the underlying silicon. The capping layer may be a metal layer from which no N diffusion occurs, or one or more layers including Ti and/or TiN arranged so that N atoms do not reach the oxide layer. A method is also described for forming the Ti and TiN layers. It is advantageous to deposit non-stoichiometric TiN deficient in N, by sputtering from a Ti target in a nitrogen flow insufficient to cause formation of a nitride on the target.
Patent TW-533182-B (TW)
Title: Portable electric appliance with cord holder
Inventor: TSUJI MASAO
IPC: B65H75/36
Filed: 2002-01-21
Granted: 2003-05-21
Abstract: A portable electric appliance (10) has a housing with recesses (20) in which posts (25) are mounted for movement between extended and retracted positions. The appliance power cord is wrapped about the posts for storage in their extended positions and held in a notch (31) of a post flange (30).
Patent TW-550595-B (TW)
Title: Semiconductor memory device having error correction function for data reading during refresh operation
Inventor: OKUDA MASAKI
IPC: G11C11/406
Filed: 2002-03-15
Granted: 2003-09-01
Abstract: A semiconductor memory device includes a plurality if memory blocks, each of which is refreshed independently of one another, m (m > 1) data pins, each of which continuously receives or outputs n (n > 1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, mxn data bus lines on which the n data pieces are expanded in parallel with respect to each if the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks, and a parity data comparison circuit which performs a parity check on m data pieces read from the m respective blocks corresponding to the m respective data pins and a parity bit read from a parity-purpose memory block, the parity check being performed separately with respect to each of the n data pieces.
Patent TW-550640-B (TW)
Title: Structure and method for fabricating semiconductor structures and devices for detecting chemical reactant
Inventor: CHASON MARC
IPC: C30B25/18
Filed: 2002-05-24
Granted: 2003-09-01
Abstract: High quality epitaxial layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.
Patent TW-564558-B (TW)
Title: Semiconductor device
Inventor: TERAUCHI TAKASHI
IPC: H01L21/28
Filed: 2002-06-24
Granted: 2003-12-01
Abstract: A semiconductor device having a structure in which the amount of stress on a semiconductor substrate or a gate wire is low, even in a case when the sidewalls of the gate wire are formed of a nitride film is obtained. A gate conductive layer positioned above a silicon substrate, a stress mitigating film that covers a sidewall of the gate conductive layer and a sidewall external layer spacer that covers the stress mitigating film and that exposes the upper edge of the stress mitigating film and the side edge of the bottom portion of the stress mitigating film are provided and the stress mitigating film has silicon oxide films positioned in the areas ranging inwardly from the upper edge and from the side edge so as to sandwich the silicon oxide film from both ends.
Patent TW-574305-B (TW)
Title: The composition of elastomeric insulating materials for solid propellant rocket motors
Inventor: FAN JUNG-NING
IPC: C08L77/00
Filed: 2002-10-25
Granted: 2004-02-01
Abstract: Non-asbestos elastomeric insulating materials for solid propellant rocket motors are disclosed. The insulating materials are composed of EPDM rubber polyaramide fiber, liquid EPDM rubber, magnesium hydroxide or aluminum hydroxide, silicon dioxide, halogenated flame retardant compound and zinc hydroxystannate. The char forming organic fiber is used to substitute asbestos added in traditionally insulating materials that in believed to cause serious environmental problems. These fillers in the formulation, which when combined, have a synergistic effect that reduces ablation rate significantly. Also, use of zinc hydroxystannate, instead of Sb2O3, may further reduce both density of the insulator and smoke density and smoke toxicity of the rocket motor exhausted gas.
Patent TW-I230200-B (TW)
Title: Metal band and manufacturing method of the same
Inventor: KLOWER JUTTA
IPC: B21B3/00
Filed: 2002-12-16
Granted: 2005-04-01
Abstract: The invention relates to a metallic ribbon used for epitaxial coating, which comprises a laminate of multiple layers. The layered laminate includes at least one biaxial textured base layer made from metals, Ni, Cu, Ag or their alloys, and at least one additional metallic layer. The individual additional metallic layer includes one or more intermetallic phases or a metal in which one or more intermetallic phases are included.
Patent TW-583226-B (TW)
Title: Formulation in preparing solid electrolytic capacitor and process thereof
Inventor: TSAI LI-DUAN
IPC: G03F7/038
Filed: 2002-12-17
Granted: 2004-04-11
Abstract: The present invention relates to a formulation in preparing a solid electrolytic capacitor and a process thereof. An electrically conductive polymer is used in an electrolyte formulation in preparing a solid electrolyte container, and a process uses a capacitor blank immersed with the polymer electrolyte. A high concentration oxidation agent solution is used and added with a 5-membered ring or 6-membered ring compound having -C=N- functional group as a polymerization retardant. A mixture of the oxidation agent solution and the electrically conductive polymer monomer is stable in room temperature and enables a capacitor blank to obtain a polymer electrolyte with a sufficient thickness after very few impregnations and polymerization reactions of the mixture solution, thereby achieving a simplified process and obtaining excellent capacitor properties. The invented formulation comprises an electrically conductive polymer monomer, a dopant, and a high concentration oxidation agent solution consisting of an oxidation agent, a solvent, and a 5-membered ring or 6-membered ring polymerization reaction retardant having -C=N- functional groups. By using the polymerization reaction retardant, the electrically conductive polymer monomer and the oxidation agent, after mixing, will not undergo polymerization immediately in room temperature. After the capacitor blank is fully impregnated with the mixture solution, the electrically conductive polymer monomer undergoes the polymerization reaction at the temperature higher than the impregnation temperature so that the impregnation of the polymer electrolyte on the capacitor blank is achieved.
Patent TW-581842-B (TW)
Title: Internal combustion engine
Inventor: HATTORI KATSUTAKA
IPC: F02B75/22
Filed: 2002-12-20
Granted: 2004-04-01
Abstract: An internal combustion engine includes a crankshaft, a mainshaft, a clutch and a countershaft. The mainshaft is for a transmission and holds a transmission gear train. The clutch is disposed on the extension of the mainshaft. Furthermore, the countershaft for the transmission holds a gear train to mesh with the transmission gear train. Accordingly, power is transmitted in order from the crankshaft to the clutch, the mainshaft, and the countershaft. This arrangement ensures better knee-grip when the internal combustion engine is mounted on a vehicle and improves in-vehicle mountability by reducing the width and the axial length of the internal combustion engine. A mainshaft is disposed about immediately below the crankshaft. At least a part of the mainshaft is provided at the same axial position as the crankshaft.
Patent TW-I272477-B (TW)
Title: Apparatus and method for testing a keyboard
Inventor: ZHANG MICHIEL
Filed: 2002-12-31
Granted: 2007-02-01
Abstract: A kind of testing apparatus, which is used for testing the keypad's endurance, comprises of a testing apparatus, a main controlling apparatus and an installation board. Said testing apparatus comprises of elements driven by the steam, a holding apparatus and a reset apparatus. The main apparatus which is connected with the testing parameters, could set the testing parameters and control the cylinder to press the key. And said installation board is just located on the holding apparatus. The invention also uncovered a method used for said testing apparatus, which is compress of: (1) test the editing keys; (2) test the function of the keyboard; (3) judge the cylinder, then decide going on test or turning to alarm; (4) record the testing data.
Patent TW-I239295-B (TW)
Title: Combination mask
Inventor: KIMURA MIKI
IPC: B41F15/34
Filed: 2003-01-09
Granted: 2005-09-11
Abstract: A combination mask for printing comprises a supporting sheet 21 which is supported inside of a frame member 11 in a stretched state and has a quadrangle shape and a screen 31 which is attached to a central part of the supporting sheet 21 and on which an image for printing is formed. A portion of the supporting sheet 21 which is located inside of an attaching portion 32 of the screen 31 for attaching the supporting sheet 21 is cutout and the screen 31 has a polygonal shape having not less than five sides.
Patent TW-I241700-B (TW)
Title: Packaging assembly with integrated circuits redistribution routing semiconductor die and method for fabrication
Inventor: PU HAN-PING
IPC: H01L23/538
Filed: 2003-01-22
Granted: 2005-10-11
Abstract: A semiconductor packaging assembly and the method for fabricating the same is proposed, wherein integrated circuits are mounted on a substrate and an dielectric layer is then coated over upper surfaces of the integrated circuits with electrode pads of the integrated circuits and fingers of the substrate exposed to the dielectric layer. Then, a metal layer is formed on the dielectric layer and the exposed electrode pads and fingers, followed by patterning the metal layer to form a plurality of conductive traces for electrically connecting the electrode pads to the fingers. With the use of conductive traces for electrically connecting the electrode pads to the fingers, there is no need of wire bonding such that problems such as wire sweeping or short circuit can be avoided. Furthermore, electrical connection of the integrated circuits and the substrate by routing redistribution can also eliminate problems resulting from the density limitation of wire bonding and facilitate minimizing finger pitches.
Patent TW-I260944-B (TW)
Title: Display device with passivation structure
Inventor: SU CHIH-HUNG
IPC: H01J1/62
Filed: 2003-01-29
Granted: 2006-08-21
Abstract: A display device includes a substrate, a display unit disposed on the substrate, and a passivation structure covering the substrate and the display unit. The passivation structure is composed of an organic/inorganic film. A side of the organic/inorganic film, which is closer to the display unit, has a maximum organic/inorganic ratio which is decreasing outward gradually.
Patent TW-I254013-B (TW)
Title: An internal hub transmission for a bicycle
Inventor: ITO MINORU
IPC: B62M11/16
Filed: 2003-03-03
Granted: 2006-05-01
Abstract: An internal hub transmission is provided for a bicycle comprising a driver member 11 rotatably mounted on a hub axle 2. A planetary gear mechanism 5 is coupled for selectively communicating rotational force from the drive member 11 to a hub body 4 through various force transmission paths, the transmission path being selected by means of a movable clutch member 26. A pawl body 22 is arranged between the drive member 11 and the clutch member 26, where the pawl body 22 carries a one-way clutch 20 so as to only transmit forward rotational drive force from the drive member 11 to the pawl body 22. Therefore when back pedaling, substantially no reverse rotational motion is transferred from the drive member 11 to the clutch member 26.
Patent TW-I254939-B (TW)
Title: Semiconductor memory
Inventor: SASAKI JUNICHI
IPC: G11C11/407
Filed: 2003-03-13
Granted: 2006-05-11
Abstract: A pulse generator generates a plurality of column pulses in response to a read command. An address counter outputs addresses subsequent to an external address supplied in association with the read command in succession as internal addresses. A column decoder successively selects column selecting lines in synchronization with the column pulses. A plurality of bits of data read from memory cells in response to a single read command RD is successively transmitted to a common data bus line through column switches. This can reduce the number of data bus lines to a minimum, preventing an increase in chip size. Since a single data bus line can transmit a plurality of bits of data, it is possible to minimize the size of the memory region to be activated in response to a read command. This consequently allows a reduction in power consumption.
Patent TW-583490-B (TW)
Title: Pixel structure and method of repairing the same
Inventor: WANG CHIEN-HUNG
IPC: G02F1/136
Filed: 2003-03-31
Granted: 2004-04-11
Abstract: A pixel structure and method of repairing the same are provided. The pixel structure is driven by a scan line and a data line. The structure comprises a first thin film transistor, a second thin film transistor, and a pixel electrode. The first thin film transistor has a first gate and a first source/drain, wherein the first gate is electrically connected the scan line and one end of the first source/drain is electrically connected the data line. The second thin film transistor has a second gate and a second source/drain, wherein the second gate is electrically floated and one end of the second source/drain is electrically connected the data line. The pixel electrode is electrically connected the other end of the first source/drain and the other end of the second source/drain.
Patent TW-I227975-B (TW)
Title: Communication system, signal pre-processing apparatus and signal receiving apparatus thereof
Inventor: DENG JUINN-HORNG
IPC: H04B7/06
Filed: 2003-04-24
Granted: 2005-02-11
Abstract: The present invention provides a communication system, signal pre-processing apparatus and signal receiving apparatus thereof. The signal pre-processing apparatus is used for pre-processing signals before being transmitted by a plurality of antennas. The apparatus includes a series to parallel transformer, L pre-rake processors and L beam forming processors respectively corresponding to the L pre-rake processors. First of all, the series to parallel transformer divides the signal into N sub-signals. Each of the pre-rake processors pre-compensates the N sub-signals and outputs a compensating signal. Each of the beam forming processors intensifies the compensating signal and outputs an intensified signal. Each of the antennas combines L intensified signals into a specific signal, and meanwhile, changes the specific signal to a RF (radio frequency) signal. The antennas transmit the RF signal.
Patent TW-I226193-B (TW)
Title: Image segmentation method, image segmentation apparatus, image processing method, and image processing apparatus
Inventor: KOIDE TETSUSHI
IPC: G06T1/20
Filed: 2003-05-26
Granted: 2005-01-01
Abstract: Cells i corresponding to pixels are initialized into a non-excitation state, to calculate coupling weights Wik between the eight cells k adjacent to the cells i, thereby determining leader cells pi=1 based on calculation results. Next, one leader cell yet to be excited is selected as a self-excitable cell. The selected cell is put into the excitation state, the excitable cells are selected based on the coupling weights between the adjacent cells, and the selected cells are put into the excitation state. These operations are repeated until no excitable cell is detected any more and, if there no excitable cell is detected any more, inhibition processing is performed, thereby completing image segmentation of one region. These operations are repeated until there is no non-excited and non-inhibited leader cell any more, thereby pinpointing regions belonging to the same category from an input image and identifying them as an image segmentation regions.