Patent GB-1434186-A (GB)
Title: Multiprocessor computer systems
IPC: G06F11/22
Filed: 1972-04-26
Abstract: 1434186 Multiprocessor computer systems GENERAL ELECTRIC CO Ltd 26 April 1973 [26 April 1972] 19364/72 Heading G4A A multiprocessor computer system includes a number of input/output channels 15 (Fig. 1) connected to each of a number of independent data processors 10 and fault channels 22 each connected to a monitoring interface 23 of a first processor and to a data interface of another processor so that when a fault channel is opened by a first processor its operation is monitored by the second processor. Core storage 11 is connected to all the processors 10 via leads 13. The input/output channels 15 which are connected to peripherals such as line circuits, a drum store and senders/receivers, are connected to each of the processors by fifty-four leads 14, of which 18 are reserved for two bytes of address data each with a parity bit, 18 are reserved for two bytes of output data each with a parity bit and 18 are reserved for two bytes of input data each with a parity bit. Fault channel.-The fault channel connected to the monitoring interface of processor 0 and accessible to processor 1 is shown in Fig. 2 (the connections to the data channels of the other two processors, shown in Fig. 1, are optional). Bits 0 to 5 and the parity bit of the upper byte of the address together with bits 6, 7 of the lower byte are fed to a line receiver 201 which recognizes the address allocated to the fault channel and performs a persistence check on it. If this is satisfactory it provides a clock signal on line 206 and an enabling signal on line 207 to gate 243 so that data may be fed to the processor 1. The clock signal enables the second line receiver 202 receiving bits 0 to 5 of the lower byte and the parity bit which are then fed to a fault channel address register 209 controlled by the clock signal and the " open fault channel " signal from processor 0. The register 209 includes a parity checking circuit (507, 508, Fig. 5, not shown). Output data for processor 0 is fed via line receiver 211 and gate 212 (enabled by the " open fault channel" signal) to a fault channel data register 214 controlled by the clock signal and by bit 7 of the lower address byte. When the fault channel is closed operation of the processor 0 may be monitored manually by using console keys connected via one set of AND gates (e.g. 419, Fig. 4, not shown) in data selectors 218, 221 to derive control signals on leads 219, 222. Data is fed via OR gate 225 to the processor. A console rotary switch may be operated to control multiplexer 235 so that the contents of any of the processor registers may be displayed on a console display. When the fault channel is open the signals from register 209, 214 are fed via a second set of AND gates (e.g. 418, Fig. 4, not shown) in the data selectors to the processor together with data on leads 227 from the input-output highway of processor 1 if a " data load " signal derived from bit 5 of the lower address byte exists. Data from a selected register in the processor is fed via the multiplexer 235 and a fault channel multiplexer 239 (which includes parity check circuitry) to the input data leads of processor 1 if an " interrogate " signal derived from bit 4 of the lower address byte is present. The data which is in two byte form, the second byte indicating whether the parity of the first byte is correct, may then be tested by the processor 1. Decoder.-The decoder 205 comprises a 6 input NAND gate (301, Fig. 3, not shown) connected selectively to the six address bits or their inverses. The AND gate is connected to a delay line (308) having 8 tapping points so that when the address persists for the duration of the delay the fault channel clock signal and gate data signal are derived. Software.-Tasks waiting to be examined by a process and tasks generated by a process are placed in core storage in input and output queues respectively. Any process may be run on any processor, each process having core storage assigned to it. The supervisor programme deals inter alia with the transfer of tasks, servicing requests from peripherals and handling fault conditions. Supervisor programme.-Periodically a clock 27 (Fig. 1) applies a clock signal to one of the immediate interrupt inputs of unit 25. This causes the processor running the lowest priority process to be interrupted and its register contents stored. The supervisor is then run on this processor and performs the following: (1) The interrupted process is put into its suspended state and periodic processes due to be commenced are unblocked and put into their suspended state so that they are started when a processor is avaiable. (2) Non-immediate interrupt inputs are serviced. (3) The highest priority suspended process is selected and assigned to the processor running the supervisor. The supervisor may also be initiated by a fault interrupt to run a fault routine or by a process requesting that one or more tasks that it has generated be passed to another process or by a processor requesting the supervisor to decide if it should continue running. Fault interrupt.-When a parity error is detected in a processor it inhibits its interrupt inputs and applies an " immediate fault interrupt " signal to the units 25 simultaneously with the application of an " open fault channel " signal. The interrupt signal normally results in the supervisor programme being run on the processor running the lowest priority process. If after a predetermined period the interrupt signal has not been answered the processor attempts selftesting by running a " maze programme ", a timing device being simultaneously triggered to run for a fixed period. If a fault is present the maze programme will either trap, stop or loop. If the processor traps the programme restarts and trapping will continue until the expiry of the fixed period. Similarly looping will continue until the expiry of the period. If the programme reaches its end a computed word is compared with a wired-in word and if comparison occurs the processor returns to service after generating a print-out. If the processor does not reach the end of its programme or the result is wrong the fault channel is again opened and the above process repeated. When the interrupt is answered the supervising processor enters a fault routine by applying the address of the fault channel to the address lines. It interrogates the faulty processor to see if it were running normally at the time of the fault in which case the fault is assumed to be transient and the faulty processor is put back into service after the supervising processor has taken action to prepare the abandoned process for running again or if it were running the maze programme. In the latter ease the supervisor generates a diagnosis task which is run when a processor becomes available. This processor then feeds predetermined data to the register of the faulty processor so that it executes a second (not necessarily different) maze programme. Each of the instructions of the maze programme are sequentially executed with the register content being examined at each step. When an error is detected each of the microinstructions of the instruction incorrectly performed are again executed, one at a time to find the faulty one. Next, previous faults of the processor held in core storage are compared with this fault and if it is a new fault a print out is generated. If no error is generated all the parity checking circuits of the faulty processor are tested by writing in predetermined parityincorrect data to each register in turn to see if it is detected. Roll back.-If a fault is discovered which is likely to erase information in the core stores relating to, for example, the states of the line circuits 19 (Fig. 1) roll back action is taken. The roll back routine interrogates, by a processor applying the appropriate channel and subchannel address on lines 14. Three interrogate wires Y, S, NS representing the states of particular relays in each line circuit are scanned and their information transmitted back to the processor. If Y = 0 the line is assumed to be idle. If Y = 1 signifying a call is in progress the value of the signal from the wire S is examined. If S = 0 the line is assumed to have an incoming call. If S = 1 the value of the signal from the wire NS is examined and if NS is 0 the line circuit is assumed to be in its incoming speech state. If NS = 1 it is not possible to determine exactly the state of the call from the signals on the three interrogate wires and the call is lost. The information derived from each line circuit is entered in the storage location assigned to it in core storage and the process then continues.