Patent GB-953889-A (GB)
Title: Analogue memory circuit
IPC: G11C8/00
Filed: 1960-09-28
Abstract: 953,889. Controlled non-linear inductors. KOKUSAI DENSHIN DENWA KABUSHIKI KAISHA. Sept. 28, 1960 [Sept. 28, 1959], No. 33339/60. Heading H3B. An analogue memory element comprises two or four magnetic cores or a pair of ferro-electric capacitors which are brought to a representative intermediate stable state by the combination of an A.C. or a D.C. input signal of given amplitude and a first A.C. energization, the stored signal being read-out non-destructively as a second-harmonic signal by subsequent application of a second A.C. energization having an amplitude below that necessary to eliminate the representative stable state, and the stored signal being destroyed by a third A.C. energization of larger amplitude. Basic two-core memory element. As shown in Fig. 1, a pair of cores Ml, M2 with rectangular hysteresis loop properties have an input winding N1, an excitation winding N2 and an output winding N3, the respective coils on each core being in series aiding relationship except for the coils of winding N2. Consequentially, A.C. energization of winding N2 induces a second harmonic output in winding N3, the amplitude of which is determined by the remanent state of the cores. For storage of a D.C. signal Is, the memory element is first cleared by A.C. energization Id, Fig. 4, applied to winding N2. This winding is subsequently energized by A.C. bias energization Iw of smaller amplitude in coincidence with the D.C. signal Is to establish the characteristic stable state. Winding N2 is energized by A.C. energization Ir when non-destructive read-out is required, and a second harmonic output e1 is induced in winding N3 which at this stage is utilized in the output circuit. For storage of an A.C. signal of frequency f1 which is of twice the frequency as the writing and reading energizations, the time positions of the signal and the write energization are so chosen that an asymmetric resultant is produced capable of changing the core magnetizations to the required degree, Fig. 3 (not shown). Shifting register. A series of basic two-core memory elements M11, M21, M12 . . . are connected as shown in Fig. 5, the second and subsequent stages having second harmonic negative feedback windings N4 connected in series with the respective output windings N3 of the antecedent stage. The energization cycle shown in Fig. 4 is used, but odd-numbered and evennumbered stages respectively receive the cycle repeated in different time positions, Fig. 6 (not shown). The first stage has a D.C. input and provides an analogue output as previously described which is applied over an amplifier A1 and a synchronous detector Dl to produce a corresponding D.C. input to the second stage. The synchronous detector is gated open by a pulse Ig1 in coincidence with the reading energization Ir. In the second stage the input pulse is in coincidence with a writing energization in winding N2, and when the reading energization is subsequently appllied an induced second harmonic output induced in winding N3 passes over an amplifier A2 and a gated synchronous detector D2 to the third stage. The negative feed-back is so arranged by suitably choosing the windings N1 and N4 that each stage has a gain closely approaching unity. Variable attenuators may also be included in the output and feed-back paths, Fig. 13 (not shown). In the case of an A.C. signals the second harmonic output is of the same frequency f, and is applied from one stage to the next through gates which are opened only during the reading periods and which replace the synchronous detectors, Fig. 11 (not shown).  Alternative two-core memory element. As shown in Fig. 9, the output winding N3 is also used as an input winding and is connected to a transformer T which is tuned by a capacitor C to the second harmonic frequency, the transformer having two secondary windings al, a2, respectively, providing output and feed-back voltages. Four-core memory element. This arrangement comprises cores M1-M4, Fig. 12, having two excitation windings N2, N2a respectively energized by currents of frequencies f1 and f2. A transformer T connected to the output winding N3 is tuned by a capacitor C to the modulation product (f1 + f2) or (f1 - f2), and separate secondary windings a1, a2 provide output and feed-back voltages at one of those frequencies. Alternative shift register. Basic two-core memory elements as in Fig. 9 are used in the shift register shown in Fig. 10, and each feedback secondary winding being directly connected to the output secondary winding of the preceding stage, and each of the latter windings being connected by way of an amplifier A and a synchronous detector D to the common inputoutput winding on the cores of the next stage. This circuit may alternatively use the basic four-core memory elements shown in Fig. 12. Ferro-electric memory element. Two ferroelectric capacitors Cv1 and Cv2, Fig. 8, are associated with the centre-tapped primary winding of transformer T which may be tuned by coupling capacitors C1, C2, the A.C. energization source being connected to terminals 2, 2a and the input signal to terminals 1, la. Separate output and feed-back secondary windings al, a2 are provided and the arrangement may be applied to the shift register circuit of Fig. 5.