Patent GB-1281467-A (GB)
Title: A multi-register control system for a time division multiplex exchange
Inventor: HARDY DANIEL GHISLAIN
IPC: H04Q11/04
Filed: 1970-03-31
Abstract: 1281467 Automatic exchange systems D G HARDY and D A GOBY 31 March 1970 [31 March 1969] 15174/70 Heading H4K A program-controlled processing system for a time-division-multiplex exchange comprises a circulating store 1A, in which call connection data is stored in serial bit form in a number of register sections, each register section holding data in respect of one particular connection, data being read from the circulating store at three spaced read-out stations 11A, 14A, 17A, so that instruction data read-out of a register from station 11A, addresses a program store 20 to set up a computer unit 4 to select and operate on data extracted from the register when it is available at station 14A, the result of the operation, if any, being used to modify register data selectively when available at station 17A, and with subsequent writing back into the circulating store at circuit 19A. The circulating store 1A comprises an 8 ms magnetostrictive delay line 10A with magnetostrictive delays 13A, 16A of 125 Ásec between the read-out stations. This store has a capacity of 66 register sections of 125 Ásec each, each register section having 32 five bit words marked out by pulses t0 to t31. A second circulating store 1B operates in precisely the same fashion as store 1A and increases the capacity of each register section by another 32 five bit words. The use of two circulating stores in parallel is necessary due to limitation of bandwidth of magnetostrictive delay lines. The contents of the A and B halves of a register section are shown in Figs. 4a and 4b and are available to the computer unit 4 in common from the second and third read-out stations. The A-half of a register governs the program store read-out from the first read-out station in accordance with a directive address while the B-half governs loop state detection in register 50 as coupled to exchange lines over leads 500. The computer unit 4 contains a peripheral unit interface by means of which system data may be collected and distributed. The A-half of a register contains class-of-service data in words 8 to 11, call charge data at 13, the order of digit being received in a digit train at 14, and a pulse count for each digit received in word compartments 16 to 29. The B-half of a register contains loop state last-look records at 28 and 29, calling and called subscriber addresses at 3 to 12, timers # and Q at 16 to 21 for dialled impulse train discrimination, and time out for anomalous situations at compartments 24 to 27. The computer unit contains a processor 40, Fig. 5, that, on instructions presented by the program store read out circuit 23 and microprogram store 3 set up by read-out from a register at the first read-out station, effects selective read out from that register at the second readout stations 14A, 14B, and in the result effects further selective read-out for register updating from the third read-out stations 17A, 17B before re-writing in circuits 19A, 19B. The program read-out store 23 comprises a register 231 holding a 9-bit address which when transferred to processor register 411 determines whether readout is from the A- or B-half of a.register and which 5-bit compartment is to be read and which bit in that compartment is to receive attention. A total of 10 bits from two consecutive compartments may be read-out from the register from second station 14A or 14B, the point at which gates 417A or 417B are operated for this purpose being judged by a comparator 419 which matches the register address from 411 against clock counter output 6. Program store read-out circuit also has an 11-bit parameter register 232 providing criteria for processing decisions as when testing initial digits to establish a request for an international trunk circuit or when testing time counts against standard intervals. Test of register data against the parameters is made in comparator 419<SP>1</SP>. The program also sets up instruction register 233 with 6 bits which, with micro-programs from 3, may result in a 20 bit instruction in processor register 413 which governs comparators 419, 419<SP>1</SP>, and controls what data is passed on from this stage of the processing to the next stage with read-out from the third read-out station, as wellas governing the data flow to and from peripheral circuits by register 423 and path 41. A program instruction register 234 contains a 9-bit program address increment data from which, as conditioned by processing results, the program directive for the next appearance of the register is compiled in the third read-out station phase. At this third read-out phase a register 421 receives 9 bits to identify that section of the register from which data is required for further processing a comparator 429 supplied with clock counter code output making the match in this respect and, by leads not shown, controlling gates 427A or 427B accordingly. An add/subtract circuit 430 operating in instruction from registers 422 to 424 modifies the data so extracted from the register and returns the result to the re-write circuits 19A or 19B over gates 432, 435A, 435B, the gate 432 being required for setting up the new program address data in circulating store 1A. Processor function is described with reference to detection and evaluation of digits received as impulse trains. The # and Q timers are used to gauge the significance of make and break periods to afford an initial period of 16 seconds after which, in the absence of dialling, disconnection tone is connected; to determine inter-digital pauses and effect consequential digit steering in the digit impulse count register words; and to time release.