Patent GB-851371-A (GB)
Title: Improvements in high speed arithmetic units
IPC: G06F7/52
Filed: 1957-09-02
Abstract: 851,371. Digital electric calculating apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 2, 1957 [Aug. 31, 1956], No. 27542/57. Class 106 (1). An arithmetic unit for an electronic digital computer comprises a number generator adapted to transmit selectively pulses from a pulse train delivered by a very high frequency (30 to 300 Mc/s.) pulse source so as to produce cyclically number representing groups of pulses, gating means adapted to transmit or block successive groups of pulses in accordance with timed inputs and including an adder arranged to receive at one of its inputs groups of pulses transmitted by said gating means and having its output connected to a circulating loop feeding its other input, said loop including means connected to said pulse source through a delay device so as to introduce a delay time in said loop in order that pulses appearing at the adder from said loop are substantially in phase with pulses appearing at the adder from said number generator. A serial pure binary multiplier having a clock pulse frequency of 50 Mc/s. is described in Figs. 1A, 1B. In operation a 5- digit multiplicand is repeatedly serialised, Fig. 1A, and entered a number of times, appropriately shifted, by a partial product generator controlled by the staticised multiplier digits, into an accumulator loop comprising a binary adder Fig. 1B and a loop reshaper and retimer. The number circulating in the loop is continuously made visible by a neon lamp indicator register. Multiplicand generator.-The multiplicand is set up on switches B0 to B4, Fig. 4A, and is serialised once for each secondary clock pulse received at a terminal 38D by means of a tapped delay line, the serialised output appearing on a lead 45, as a train of negative pulses, Fig. 4C. These negative pulses are amplified and reshaped, Fig. 4B and re-appear at a terminal 43, Fig. 4B, as positive pulses, Fig. 4C. The delay line, Fig. 4A, is so arranged that the output pulses occur at a frequency of 50 Mc/s. and the time between each secondary clock pulse is equal to the circulation time of the accumulator loop. Partial product generator.-The partial product generator, Figs. 5A, 5B, receives the serialised multiplicand at a terminal 43D and routes it via either 0, 1, 2, 3 or 4 digit delays to an output terminal 100 under the control of the multiplier. Each multiplier digit is used in turn, starting with the lowest order, and causes a corresponding gate 54, 55, 56, 57, 58 to be opened for a secondary period (that is the period between two secondary clock pulses) by lowering the potential of a corresponding terminal S0 to S4. The multiplicand digits then pass through one or more of the delays D1 to D4 via a cathode follower and a mixer to the output terminal 100. Serial adder.-The adder, Figs. 7A, 7B, is a conventional serial adder having two input terminals 101D and 110D, an output terminal 109, and an internal carry loop from a cathode follower 167 via a cathode follower 151, a reshaper and retimer circuit 143 and a limiter 140 to the input end of the adder where gates 153 to 155 determine whether or not there are two or more ones being entered, gate 156 determines where one or more ones are entered and gate 157 determines whether three ones are entered. Specification 826,029 is referred to.