Patent GB-1020244-A (GB)
Title: System for controlling a multistage switching network
IPC: H04Q3/545
Filed: 1962-11-15
Abstract: 1,020,244. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. Nov. 15, 1962 [Nov. 24, 1961], No. 43194/62. Heading H4K. In a system in which connections are established through a multistage switching network, means are provided for detecting a blocking condition for a desired call, and for rearranging the other connections in such a manner as to remove the blocking condition. The problem is discussed in relation to the cross-bar switching arrangement shown in Fig. 1 in which it is shown that if, say, a connection between an input to I1 and an output from On is blocked because no switch S1 . . . Sn has a free link to both I1 and On, then provided one switch say Sn has a free link to I1 and another switch say S1 has a free link to On, then a free path can be obtained by rearranging connections involving S1 and Sn only, and that at the most n - 1 rearrangements are necessary. Figs. 2, 3 illustrate the control network which comprises, inter alia, the following components:-an output network memory 110 which stores the identity of output lines in terms of the switches O1 . . . On and levels thereof, in addresses determined by the input switch identity (passed through access circuit 111) and the intermediate switch identity (passed through access circuit 112). Similarly the input network memory stores incoming lines identity in positions determined by the output switch and intermediate switch involved in a connection. A logic circuit 160 is provided to compare the outputs from memories 110, 120 to give different results according to whether one, other, both or neither produces outputs. A counter 103 is used inter alia to enable sequential testing of intermediate switches. The whole system is governed by a clock generator and gate control 170 whose outputs enable the various circuits, the circuit 170 assuming a series of states which are stepped automatically, but may be modified in accordance with information received from the counter 101, the logic circuit 160 and the comparison circuit 180. As a result of the tests performed by this circuit a series of orders are stored in memory 150 relating to the taking down and putting up of connections, and these are subsequently submitted to the network control circuit 100, Fig. 1. Setting up of ordinary connection.-When a connection request is received on lead 171, the identities of the input and output lines are inserted in position 1 (determined by counter 101) of memories 140, 130 respectively. These identities are then passed to registers 143, 133. The input switch identity is then fed to access circuit 111 and the counter 101 feeds " 1 " (corresponding to S1) to access circuit 112. The memory 110 thus reads out the identity of any outgoing line connected to the input switch in question via switch S1. Similarly memory 120 is made to read out the identity of any incoming line connected to the outgoing switch in question via switch S1. If either memory 120 provides an output this is recognized by logic circuit 160 whereupon the counter 101 being not at the maximum value (n), the counter is stepped to its next position and the process is repeated to test switches S2, S3, . . . in a similar manner until a switch having free links towards both the required input and output switches is found. This is recognized by the logic circuit 160 whereupon counter 101 feeds the intermediate switch identity to register 103 and the state register 105 is set to UP. Operations then proceed in a similar manner to those for putting up connections in the blocked condition case as described below, with the exception that the level checking operations do not occur. Blocked connection.-When the identities of the input and output lines requiring connection have been received in memories 140, 130, respectively, the counter 101 steps, the count at each step representing an intermediate switch. At each step the intermediate switch identity is fed to access circuits 112, 122 and the output and input identities of the switches serving the two lines are fed to access circuits 111, 121. If memory 110 fails to give an output it means that the intermediate switch in question has a free link to the input switch concerned. Likewise if memory 120 fails to give an output the intermediate switch has a free link to the output switch concerned. The output conditions obtained from 110, 120 are analysed by the logic circuit 160 so that the intermediate switch identity is inserted in the first case in register 103 (say S3) and in the second case in register 102 (say 52). All the intermediate switches are tested in succession and as in blocked conditions no switch will be found having suitable free links on both sides, the counter 101 will reach its maximum, and the stores 102, 103 will contain the identities of the last two switches having suitable free links in the output and input sides respectively. It is now necessary to interchange these switches in the connections they are involved in, until an intermediate switch is free on both sides towards the input and output switches required to be connected. These connections have to be ascertained. Counter 101 is reset to 1 and now acts as a means for addressing successive rows of memories 130, 140. In the first position access circuit 112 is fed with S3 and access circuit 111 is fed with input switch identity present in 140 (row 1), to feed the outgoing line identity to register 113. Similarly the identity of incoming line connected via S2 to the outgoing line requiring connection is fed to register 123. Since both 113 and 123 provide outputs logic circuit 160 causes counter 101 to move to its second position and this causes the identities in 113, 123 to be transferred to the second rows of memories 130, 140. Similar tests are again carried out using the new input and output switch identities in the second rows of 130, 140, and so on so that in successive rows of 130, 140 are respectively inserted the output connections of switch S3 and the input connections of S2. This continues until one of the outputs from 110 or 120 (say 120) is a blank. This is recognized by the logic circuit 160. At this stage counter 101 is restored but its count at that time is saved in register 104. Then by an appropriate series of events ordered by the circuit 170, the identities of the connections to be taken down are derived from the information stored in stores 130, 140, 102, 103 and stored in successive rows of order memory 150 (under control of counter 101 which affects access to the successive rows) together with a " DOWN " instruction. This is followed by a further sequence which inserts the identities of the connections to be put up together with the instruction " UP." The arrangements are such that although the switch identities so inserted are accurate, the levels (i.e. the identities of the verticals of the input and output switches) may be erroneous. Counter 154 is set to 1 and the first row of order memory 150 is read out to the output register 155, and the order being DOWN in this case the input output and intermediate switch identities are fed to the appropriate access circuits for 110, 120, to obtain the correct identities of the subscribers lines. These are fed in succession from registers 113, 123 via 140, 151 to the order memory 150 to effect the necessary corrections. Access counter 154 is then stepped and all DOWN connections are similarly connected. When it comes to the UP instructions reference is made to the previously existing connections as already stored in the DOWN instructions. Thus counter 101 is restored and caused to read out the first line of the DOWN instructions which are then fed (as far as the line identities, but not the intermediate switch identities, are concerned) via 155, 151 back to the order memory 150 in the position indicated by counter 154. On each such occasion counter 101 is advanced and save memory 104 has its count reduced until when the latter reaches 1 the order memory is read out line by line to the switching network. Recording connections and disconnections.-As each of these is effected memories 110, 120 must be informed. The network control is instructed thus, by the nature of the signal on lead 171 and the identities of the input and output lines on leads 145, 135 and the intermediate switch identity on lead 173. These identities are used in the case of the " connect " signal to control the access circuits for the memories and the input and output line identities are also inserted in registers 124, 114 for gating into the appropriate sections of the memories 126, 110. Similar operations take place for a " disconnect " with the exception that " erase " signals are fed into 114, 124. Request for release.-This consists of a particular signal on lead 171 together with the identity of one only of the lines in question, say the output line. Thus the output line identity is written into memory 130, whilst memory 140 contains no record. Counter 101 applies an S1 indication to access circuits 132, 142, and the switch identities in registers 130, 140 are applied to access circuits 121, 111. Thus in this case memory 120 is interrogated. If the call in question is not coated through S1 the output will be a blank and counter 101 is stepped to position 2 and a similar test is carried out with respect to S2. If the latter is the switch involved then the input line identity is read out. This is applied to access circuit 111 and S2 is applied to access circuit 112 to read out memory 110. This output line identity is compared with that stored in memory 130, in comparator 180. If this check proves successful the line identities are stored in 130, 140 and the intermediate switch identity stored in 101 is transferred to 102. The writing into the order memory of the instruction to take this connection down then occurs just as in the first taking down operation in the case of a blocked connection. Au