Patent GB-1173607-A (GB)
Title: Methods of Multiplexing Sampled Data and Apparatus Therefor.
Inventor: NORBY HAROLD ARTHUR
IPC: H04L5/26
Filed: 1966-11-24
Abstract: 1,173,607. Multiplex pulse signalling; data transmission systems. H. A. NORBY. 24 Nov., 1966 [24 Nov., 1965], No. 52709/66. Headings H4L, H4P and H4R. In a multiplex transmission system a number of carriers are used which are constituted by phase synchronous series of bipolar pulses. In order that the channels shall be orthogonal, and therefore free from cross-talk, the bipolar pulses must have equal area positive and negative portions and the pulses of each series of periodicity greater than the least must be symmetrical about the mid-points of the periods of the pulses of each series of lesser periodicity. In the described embodiments the carriers may be sine waves each of frequency twice that of the next lower frequency carrier or, as shown in Fig. 11, the highest frequency carrier, in channel A, may be a sine wave, the next highest frequency carrier, in channel B, a waveform consisting of two positive halfcycles followed by two negative half-cycles of the highest frequency carrier, the next highest frequency carrier, channel C, four positive half-cycles followed by four negative half-cycles of the highest frequency carrier, the next highest, channel D, eight positive and eight negative and so on. Information is carried by reversing the polarity of selected ones of the series of bipolar pulses and also by varying the amplitude of the pulses. Information is recovered from the multiplex modulated signals by multiplying the received signal with a square wave having the same period as the carrier to be demodulated and then integrating over the period of that carrier, the resulting signal being of a sign which depends on whether or not that bipolar pulse period was inverted and the amplitude being proportional to the transmitted amplitude of the bipolar pulse. For the transmission of digital information one digit position may be used to control the phase reversal of the bipolar pulse while further digits are converted to analogue form and modulate the amplitude of a bipolar pulse. Transmitter, Fig. 1, comprises an oscillator VCO phase locked to an external clock source and whose output is divided down to provide a series of signals each half the frequency of the previous signal and which, after filtering so that only the fundamental remains, provide the channel carrier frequencies. Channels A and B provide simple information channels and so their outputs are modulated first by phase reversal according to the digit stream d or d/2 and then in amplitude by the outputs of the digital to analogue converters fed with the remaining digits of the digit streams to be transmitted. Channel C may be used for synchronization by removing the digit stream d/4 and applying a quadrature version r<SP>1</SP>/4 of this channels normal carrier r/4 together with the carrier from channel B to the balanced gate. If this channel is to be used for normal data transmission the data is applied to the exclusive " OR " logic together with the r<SP>1</SP>/4 carrier. The resulting modulated carriers are added in adding amplifier A and the resulting signal fed to the line. Receiver, Fig. 2. The incoming signal, after equalization and gain adjustment to compensate transmission losses, is applied to a timing generator in order to extract switching signals r, r/2 and r/4 of the same period as the channel carrier bipolar pulses, which are applied to balanced modulators X together with the input signals. The modulator outputs are fed to the gated integrators which integrate over the period of the appropriate channel carrier to derive the channel modulation, in polarity and amplitude, which is fed to the analogue to digital converters in order to derive the transmitted digital signal, the integrator being reset at the end of each bipolar pulse period. By combining the phase reversals of the demodulated signal with the input signal in logic circuits and balanced modulator signals are derived to effect a g.c. of the input signal and phase locking of the timing generator. A receiver for the signals shown in Fig. 11 is described with reference to Fig. 12 (not shown), and comprises a gated integrator, the charge on which is stored and reset at the end of each half period of the highest frequency carrier. The value of the charge is converted to digital form and fed to a digital computer which combines the integrator outputs appropriately in order to extract the data signals corresponding to each multiplexed channel. In an alternative form of demodulator, Fig. 13, the signal is applied to a number of gated integrators in each channel and the signal input of each integrator is phase reversed by a respective switching waveform so that, in each channel, a maximum value will appear at the output of that integrator corresponding to the particular digit sequence transmitted during that signal period on that channel. In channel A eight orthogonal digit sequences are possible, in channel B four, and in channel C two, with D providing a reference signal. The maximum likelihood detector compares the output of the integrators in the respective channel to decide which digit sequence was transmitted, and connects the appropriate integrator output to the analogue to digital converter corresponding to that channel.