baber/WOPTO huggingface dataset:
Patent TW-436987-B (TW)
Title: Semiconductor device and method of manufacturing the same
Inventor: OKADA NORIO
IPC: H01L21/768
Filed: 1999-09-07
Granted: 2001-05-28
Abstract: In a semiconductor device, adjacent ones of aluminum wirings are electrically isolated from each other through an interlayer insulation film containing a void space portion which is disposed between the adjacent ones of the aluminum wirings in a condition in which the void space portion makes its lower surface substantially flush with a lower surface of each of the aluminum wirings. A trench is formed between the adjacent ones of the aluminum wirings in an upper surface of a semiconductor substrate. Each of the trench and the aluminum wirings has its side surfaces covered with a damage preventing silicon oxide film, i.e., side-wall insulation film which is used to form the trench. The trench is filled with the interlayer insulation film.
Patent TW-457371-B (TW)
Title: Testing device and method of touch-type tablet
Inventor: JAU SHUEN-SHIAN
IPC: G01R1/00
Filed: 1999-09-10
Granted: 2001-10-01
Abstract: The present invention relates to a testing device and a testing method of touch-type tablet, and particularly to an automatic testing device manufactured based on the physical and electrical characteristics of the tablet. In accordance with the technique of the present invention, the disclosed testing device includes a testing machine for being placed with the tablet under test and a three-dimensional moving tool carried with a testing pen and arranged on the testing machine. When the tablet is fixed on a testing position and the starting button is pressed, the three-dimensional moving tool is driven to carry the testing pen on the tablet, and the testing pen is pressed on the tablet to move, thereby automatically completing the testing operation. Accordingly, it is able to avoid the error of testing result due to the fatigue and carelessness of the operator when the testing operation is executed manually.
Patent TW-411298-B (TW)
Title: Wafer polishing machine
Inventor: INABA TAKAO
IPC: B24B37/04
Filed: 1999-10-15
Granted: 2000-11-11
Abstract: A CMP machine includes first and second polishing bases 14 and 15, first and second wafer holding heads 31 and 32, a wafer loading unit 41, a wafer unloading unit 42, a first head rotating mechanism, a second head rotating mechanism, a first transportation mechanism, and a second transportation mechanism. The first and second polishing bases each have a polishing cloth 13 attached to the surface thereof and rotate. The first and second wafer holding heads each rotate while pressing the surfaces of wafers against the polishing cloth. Unpolished wafers are placed on the wafer loading unit 41. Polished wafers are placed on the wafer unloading unit 42. The first head rotating mechanism rotates the first wafer holding head so as to position it above the first polishing base, wafer loading unit, or wafer unloading unit. The second head rotating mechanism rotates the second wafer holding head so as to position it above the second polishing base, wafer loading unit, or wafer unloading unit. The first transportation mechanism transports an unpolished wafer to the wafer loading unit. The second transportation mechanism transports a polished wafer from the wafer unloading unit. In the CMP machine, the first and second polishing bases are located mutually adjacently. The wafer loading unit and wafer unloading unit are located mutually adjacently. The first polishing base and wafer loading unit are located diagonally. The second polishing base and wafer unloading unit are located diagonally. Owing to this structure, transportation of a wafer to the wafer loading unit and transportation of a wafer from the wafer unloading unit are achieved by the different transportation mechanisms. This leads to minimized adhesion of dust to an unpolished wafer.
Patent TW-471154-B (TW)
Title: Robust bonding pad structure for integrated circuit chips
Inventor: HORIGUCHI YOKO
IPC: H01L27/04
Filed: 1999-10-21
Granted: 2002-01-01
Abstract: A bonding pad structure for an integrated circuit is comprised of a semiconductor substrate in which a protection device is formed, a bonding pad for connection of a wire through which a signal is supplied to or delivered from the integrated circuit, an insulating layer formed on the substrate. At least a portion of the insulating layer is covered by the bonding pad. In the insulating layer, a first conductive layer is formed for connection to ground, and a second conductive layer laterally spaced from the first conductive layer, arrays of juxtaposed metallic contacts are used to establish a contact between the second conductive layer and the bonding pad, a contact between a first portion of the protection device and the first conductive layer, and a contact between a second portion of the protection device and the second conductive layer.
Patent TW-483212-B (TW)
Title: Battery state displaying device for electric vehicles
Inventor: YAMAMOTO SATOSHI
IPC: G01R31/36
Filed: 1999-10-26
Granted: 2002-04-11
Abstract: This invention is capable of displaying the absolute residue rate of a chargeable battery and the state of degradation, the memory effect state, and relative residue rates of the ratios of residual amounts to actual amounts for observing individual use environments. This invention further aims to provide a battery state displaying device for electric vehicles, which can, according to the memory effect, display the states of regeneration discharge, battery charging, battery life, battery replacement, etc. In a battery state display device (401) for electric vehicles for displaying the states, such as residual capacity, of a chargeable battery (400), there are provided: a display means (402) for displaying the battery states; an absolute residue rate algorithm means (403) for obtaining the ratio of the residual amount to the initial amount of the chargeable battery (absolute residue rate); a relative residue rate algorithm means (404) for obtaining the ratio of the residual amount to the actual amount of the chargeable battery 400 (relative residue rate); a charging rate algorithm means (405) for obtaining the ratio of the capacity of the chargeable battery 9400) during charging to the initial capacity or actual capacity; and a display control means (406) for switching any one of the absolute residue rate, relative residue rate, and charging rate thus obtained to the display means (402) for display.
Patent TW-451063-B (TW)
Title: Method for inspecting the reliability of testing probe
Inventor: TSAI MENG-JIN
IPC: G01R1/00
Filed: 1999-10-28
Granted: 2001-08-21
Abstract: This invention is about the method for inspecting the reliability of testing probe and is used in the testing apparatus that has plural probes. This method includes the following steps: dividing the probes into groups, in which each group includes plural probes; making these probes float; applying voltage to each group of probes in order to measure the resistance value of each probe, in which the remaining probes are grounded when a voltage is applied to one probe among the group of probes; comparing and checking the resistance value of each probe among each group of probes; preparing a testing wafer, in which the testing wafer is deposited with a thin film; making these probes contact this testing wafer; applying voltage to each group of probes in order to measure the contact resistance value of each probe; and comparing and checking the contact resistance value of each probe among each group of probes.
Patent TW-I261066-B (TW)
Title: Etching solution
Inventor: KEZUKA TAKEHIKO
IPC: C03C15/00
Filed: 1999-11-23
Granted: 2006-09-01
Abstract: An etching solution which contains hydrogen fluoride (HF) and exhibits an etching rate ratio: etching rate for a boron-glass film (BSG) or boron-phosphorus-glass film (BPSG)/etching rate for a thermally oxidized film (THOX) of 10 or more at 25 DEG C.
Patent TW-439189-B (TW)
Title: Method for forming a shallow trench isolation in an integrated circuit
Inventor: YANG FU-LIANG
IPC: H01L21/76
Filed: 1999-11-30
Granted: 2001-06-07
Abstract: The present invention discloses a trench-filling method in an integrated circuit process without using chemical mechanical polishing. First, a pad oxide layer and a silicon nitride served as a hard mask are formed on the surface of a substrate and a plurality of trenches are etched and defined. A HDPCVD oxide layer is deposited to fill the trenches. Said deposition method not only can fill the trench to the required depth, but also can deposit the surface of the silicon nitride hard mask. Thereafter, a little portion of the HDPCVD oxide layer is etched back. A top silicon nitride layer is deposited and patterned to leave a portion of the top silicon nitride layer covering the HDPCVD oxide layer formed in the trenches. Finally, the exposed HDPCVD oxide layer, the top silicon nitride layer, the pad oxide layer and the hard mask silicon nitride layer are removed in sequence and the manufacturing of a shallow trench isolation is finished.
Patent TW-450801-B (TW)
Title: Improved transfer relay for increased access fluff capacity
Inventor: DALEY MICHAEL ALLEN
IPC: A61F13/53
Filed: 1999-12-21
Granted: 2001-08-21
Abstract: A personal care absorbent article having a fluid intake/distribution layer, a fluid transfer delay layer disposed beneath said fluid intake/distribution layer, said fluid transfer layer enabling the transfer of fluid from the fluid intake/distribution layer(s) to a pad layer disposed beneath the fluid transfer delay layer while still allowing fluid distribution by the fluid intake/distribution layer along the machine direction of the article resulting in saturation levels of less than or equal to about 0.86 g/g/in of fluid in the intake/distribution layer(s) and/or essentially equal to or greater than 0.06 g/g/in. of fluid in the pad layer.
Patent TW-454190-B (TW)
Title: Semiconductor memory device having reduced data access time
Inventor: YOON HA-RYONG
IPC: G11C7/10
Filed: 1999-12-30
Granted: 2001-09-11
Abstract: Disclosed is a semiconductor memory device comprising a precharging unit between bit lines within a memory cell region and bit lines within a sense amplifier region, respectively. When performing a column operation on the bit lines within the sense amplifier region upon consecutive read operations, the bit lines within the memory cell region are precharged and a wordline is disabled, and thus the memory cell region comes to the ready to enable a new wordline. Accordingly, the timing of row and column operations can be reduced, thereby reducing a data access time and realizing a high speed operation.
Patent TW-450872-B (TW)
Title: Wafer sensor utilizing hydrodynamic pressure differential
Inventor: GROMKO ROBERT DEAN
IPC: H01L21/00
Filed: 2000-07-15
Granted: 2001-08-21
Abstract: A wafer sensor includes a wafer holder, a liquid distribution system, and a pressure sensor. The wafer holder has a hole and is configured so that a wafer being held by the wafer holder restricts the flow of liquid from the liquid distribution system through the hole. The pressure sensor has a predetermined threshold and is configured to sense the pressure of the fluid at the hole. When no wafer is present in the wafer holder, the fluid flows essentially unrestricted through the hole in the wafer holder, resulting in a relatively low pressure of the liquid in the hole. When the wafer holder holds a wafer, the restricted flow through the hole causes an increase in pressure of the liquid in the hole. This increased pressure triggers the pressure sensor, thereby indicating the presence of the wafer in the wafer holder.
Patent TW-I259204-B (TW)
Title: Method for amplifying nucleic acid sequence by using chimera oligonucleotide primer at isothermal
Inventor: MUKAI HIROYUKI
IPC: C12N15/09
Filed: 2000-03-17
Granted: 2006-08-01
Abstract: To provide an easy and efficient method for the amplification of a nucleic sequence by the DNA synthetic reaction in the presence of an oligonucleotide primer and provide a method for the production of a large amount of amplified DNA fragments for the mass-supply of amplified DNA fragments. The invention relates to an easy and efficient method for the amplification of a nucleic acid sequence by the DNA synthesis reaction in the presence of a chimera oligonucleotide primer, a method for supplying a large amount of amplified DNA fragments, an efficient amplification method for nucleic acid sequence comprising a combination of the nucleic acid sequence amplification method of the present invention with other amplification method, a method for the detection of nucleic acid sequence for the detection and determination of viruses, bacteria, fungi and yeasts and a method for the real-time detection of the amplified DNA fragments obtained by the method of the present invention.
Patent TW-498645-B (TW)
Title: Outer loop/weighted open loop power control in a time division duplex communication system
Inventor: ZEIRA ARIELA
IPC: H04B7/005
Filed: 2000-03-22
Granted: 2002-08-11
Abstract: Outer loop/weighted open loop power control controls transmission power levels in a spread spectrum time division duplex communication station. A first communication station transmits a communication to a second communication station. The second station receives the communication and measures its received power level. Based on in part the received communication's power level and the communication's transmission power level, a path loss estimate is determined. A quality of the path loss estimate is also determined. The transmission power level for a communication from the second station to the first station is based on in part weighting the path loss estimate in response to the estimate's quality.
Patent TW-432199-B (TW)
Title: Inertia navigation system with optimized sensor axial installation
Inventor: CHIANG MING-HUANG
IPC: G01C19/02
Filed: 2000-04-07
Granted: 2001-05-01
Abstract: This invention is about an inertia navigation system with optimized sensor axial installation and is mainly about the design concept of non-orthogonal installation for a kind of gyroscope sensing axis, in which system is composed of two dry-type gyroscopes. Two sensing axes of one double-axis dry-type gyroscope are individually directed to the pitch (Y) axis and the yaw (Z) axis. Two sensing axes of the other double-axis dry-type gyroscope individually are directed to two directions, which have included angles of 45 degrees left and right respectively from the roll (X) axis on the XY plane of missile body coordinates. The former gyroscope is mainly for measuring the angular velocity of the pitch and yaw axes of the carrier coordinates, in which much more accurate angular velocity of the roll and yaw axes can be obtained after the operation processing is performed by matching up with two sensing outputs of the latter gyroscope. By using this design, in addition to the premise of maintaining the original measurement precision for roll and yaw axial directions, dynamic measuring range of roll axis angular velocity can be greatly raised to 1.414 times of the original range and the measuring precision of pitch axis can also be increased by 30%. All the merits for this kind of design are built under the premise of maintaining the system production cost.
Patent TW-I231868-B (TW)
Title: Wavelength compensation in a WSXC using off-voltage control
Inventor: HARRIS J MICHAEL
IPC: G02F1/13
Filed: 2000-04-15
Granted: 2005-05-01
Abstract: A tunable liquid crystal switch is disclosed. An electronic controller provides an electronic drive scheme for achieving low intra-channel crosstalk of less than -40 dB using only electronic compensation. A cross-talk less than -50 dB is provided by combining coarse temperature tuning and electronic compensation. This is achieved by designing the thickness of the liquid crystal device to cause a minimum to occur at a wavelength longer than a longest operating wavelength and at a temperature greater than a maximum operating temperature. This ensures that the liquid crystal device is tunable over all operating wavelengths and temperatures using electronic compensation.
Patent TW-593733-B (TW)
Title: CVD TaN plug formation from tantalum halide precursors
Inventor: HAUTALA JOHN J
IPC: H01L23/52
Filed: 2000-04-26
Granted: 2004-06-21
Abstract: A plasma treated chemical vapor deposition (PTTCVD) method for depositing high quality tantalum nitride (TaNx) films from inorganic tantalum halide (TaX5) precursors and a nitrogen containing gas for filling small contacts having high aspect ratio features with TaNx film and eliminating a copper deposition step. The inorganic tantalum halide precursors are tantalum pentafluoride (TaF5), tantalum pentachloride (TaCl5) and tantalum pentabromide (TaBr5). In a thermal CVD process, a TaX5 vapor is delivered into a heated chamber. The vapor is combined with a process gas containing nitrogen to deposit a TaNx film in feature. In one embodiment, a hydrogen gas is introduced in a radiofrequency generated plasma to plasma treat the TaNx film. The plasma treatment is performed periodically until the feature is filled with the TaNx film. The deposited TaNx film is useful for integrated circuits containing copper. The method produces seamless TaN plug fill in high aspect ratio structures.
Patent TW-493089-B (TW)
Title: An apparatus and method for amplifying an optical signal
Inventor: CEREO RICHARD JAMES
IPC: G02B6/26
Filed: 2000-05-22
Granted: 2002-07-01
Abstract: An apparatus and method for amplifying an optical transmission signal having a wavelength of λ1 in an optical fiber amplifier. The amplification segment of the optical fiber amplifier comprises a rare earth doped optical fiber having an input end and an output end, a first pump laser for generating a first pump light having a wavelength of λ1, a second pump laser for generating a second pump light having a wavelength of λ2 a first multiplexer having a first input port, a second port, and an output, a second multiplexer having a first input port, a second input port, an outport, and a multiplexer/demultiplexer having two input ports and two outports. The optical fiber amplifier utilizes the first pump light and the second pump light, each having substantially different wavelengths to simultaneously co-pump power into the input end of the rare earth doped optical fiber amplifier. Both the first pump light and the second pump light are propagated in the same direction as the optical transmission signal and into the input end of the rare earth doped optical fiber amplifier.
Patent TW-521417-B (TW)
Title: Method for production of interposer for mounting semiconductor element
Inventor: ARIMITSU YOSHIO
IPC: H01L23/12
Filed: 2000-05-29
Granted: 2003-02-21
Abstract: This invention relate to electrically separate mother board connection electrodes from each other through etching, without mechanically boring a hole in a board with a die and to make plating leads as short as possible. An interposer for mounting a semiconductor element is fabricated through the steps of a step A, where a conductor circuit 4 that contains mother board connection electrodes 2 and plating leads 3 is formed on an insulating base film 1, a step B where a patterning resin 5 is formed on the conductor circuit 4, a step C where the patterning resin layer 5 is etched so as to make the mother board connection electrodes 2 and the plating leads 3 exposed, a step D where the plating leads 3 are each coated with an electroplating resist layer 6, a step E where an electroplating metal layer 7 is laminated on the exposed mother board connection electrodes 2 respectively, a step F where the electroplating resist layer 6 is removed, a step G where the exposed plating leads 3 are removed through etching, and a step H where a polyimide precursor layer is turned fully to an imide, when the patterning resin layer 5 is a polyimide precursor layer.
Patent TW-I280965-B (TW)
Title: Organic anti-reflective polymer and preparation thereof
Inventor: HONG SUNG-EUN
IPC: C07C309/73
Filed: 2000-06-03
Granted: 2007-05-11
Abstract: The present invention relates to organic anti-reflective coating polymers suitable for use in a semiconductor device during a photolithograhy process for forming ultrafine patterns using 193 nm ArF beam radiation, and preparation method therefor. Anti-reflective coating polymers of the present invention contain a monomer having a pendant phenyl group having high absorbency at the 193 nm wavelength. When the polymers of the present invention are used in an anti-reflective coating in a photolithography process for forming ultrafine patterns, the polymers eliminate the standing waves caused by changes in the thickness of the overlying photosensitive film, by the spectroscopic property of lower layers on wafer and by changes in CD due to diffractive and reflective light originating from the lower layers. Use of the anti-reflective coating of the present invention results in the stable formation of ultrafine patters suitable for 64M, 256M, 1G, 4G and 16G DRAM semiconductor devices and a great improvement in the production yield. The present invention also relates to anti-reflective coating compositions containing these polymers and to the anti-reflective coatings formed from these compositions, as well as preparation methods therefore.
Patent TW-484277-B (TW)
Title: Communications protocol for packet data particularly in mesh topology wireless networks
Inventor: ARONSON ITAI
IPC: H04L12/56
Filed: 2000-06-08
Granted: 2002-04-21
Abstract: In a wireless mesh topology data communications network, a communications method having a type of handshaking protocol for data exchange. A portion of the protocol is synchronous, using a schedule of control channel sessions held at all mutually communicating nodes of the network and a portion of the protocol is asynchronous, relying upon gaps between control channel sessions for transmission of requested data. Nodes which are in line of sight relation request data from each other using a request to send message and a clear to send message. A requesting node sends an RTS message to a neighbor node with information about gaps specifying the location of requested data. A supplying node transmits a potential schedule for sending requested information and the requesting node sends a CTS message agreeing upon the schedule. The potential schedule includes a number of available gaps between known control channel sessions. Because transmissions are scheduled, rapidly switchable directional antennas at requesting and supplying nodes may be used with good advantage.
Patent TW-493064-B (TW)
Title: Methods and apparatus for calibrating temperature measurements and measuring currents
Inventor: BLAU DAVID
IPC: G01J5/10
Filed: 2000-08-15
Granted: 2002-07-01
Abstract: A calibration current source and methods of calibrating temperature measurements made during, e.g., an RTP process are described. The calibration current source preferably includes a biasing circuit, an output transistor current source, and an offset circuit. The biasing circuit has an input, a reference voltage output and a biasing voltage output. The output transistor current source is coupled to the biasing voltage output and is configured to produce an output current The offset circuit is coupled in a feedback loop between the reference voltage output and the biasing circuit input and is configured to generate from the reference voltage output a variable offset voltage for selectively controlling the biasing voltage applied to the output transistor current source. In a temperature calibrating method a calibration table is generated by applying a plurality of input signals to a calibration current source to produce a plurality of output signals. The calibration table is stored. When an output signal of a photodetector is received the calibration input signal corresponding to the received photodetector output signal is determined based upon the stored calibration table.