Patent GB-1532798-A (GB)
Title: Computer memory systems
IPC: G06F12/08
Filed: 1975-11-10
Abstract: 1532798 Computer memory systems SPERRY RAND CORP 10 Nov 1975 [11 Nov 1974] 46376/75 Heading G4C In a computer memory system comprising a relatively large capacity slow cycle time main memory 36 for storing data blocks at addressable locations therein, a relatively small capacity fast cycle time buffer memory 24, 26 for storing a subset of the data blocks stored in the main memory 36, and a plurality of requestor units (which may be central processing units and/or input/output devices) in communication with the buffer memory 24, 26, when a particular address is requested by a requestor unit a check is made to determine if that address is resident in the buffer memory 24, 26 and if so the corresponding data is available for reading or writing; if not a block in the buffer memory 24, 26 is selected for replacement, e.g. on a least recently accessed basis, and the block in the main memory 36 at the requested address is transferred to the buffer memory 24, 26, the block in buffer memory 24, 26 selected for replacement being meanwhile checked for any modification of any of its constituent words while it was resident in the buffer memory 24, 26 and only if such modification has occurred that block is read out from the buffer memory 24, 26 into a temporary holding register 68, 68 and then rewritten into the main memory 36 to update the corresponding block in the main memory 36. In order to reduce access time, the buffer memory is divided into respective odd and even segments 24, 26, buffer memory access being accomplished in overlapped fashion. As described each buffer memory segment, e.g. 24, is divided into 128 sets each containing four 4-word half-blocks of data and a respective tag word, the half-blocks of data and the tag words being respectively stored in a buffer part 30 and in a tag part 28. The main memory 36 is correspondingly divided into 128 sets each containing 256 8-word blocks. Each tag word includes four block addresses each indicating the main memory address of the first word of the respective block stored in the buffer parts 30, 34, four 2-bit age fields indicating the relative order of previous accesses to the four blocks, and four 1-bit modification fields each of which is set to binary 1 if the corresponding block has been modified whilst resident in the buffer memory. Respective comparators (42, 42) associated with each tag part 28, 32, Fig. 2 (not shown) compare each of the four block addresses of a selected set in the buffer memory with a requested address from a requestor unit and if the comparison is successful for one of the blocks, that block is available to the requestor unit. If none of the four block addresses matches the requested address, a block transfer process between the main memory and the buffer memory takes place as above, the modification fields of the selected set being employed to determine whether a block being displaced from the buffer memory is transferred to the main memory to update the corresponding block in the main memory. Priority networks 14 resolve conflicting access requests from more than one requestor unit. Detailed logic circuitry of a control network 15, which controls the orderly transfer of data blocks between the buffer memory 24, 26 and the main memory 36, is described in some detail with reference to Fig. 6 (not shown).