Patent GB-1144784-A (GB)
Title: Sequential access memory systems
Inventor: GALLAHER LEE EASTMAN
IPC: G06F13/16
Filed: 1966-07-28
Abstract: 1,144,784. Digital electric memory system. WESTERN ELECTRIC CO. Inc. 28 July, 1966 [30 July, 1965], No. 33942/66. Heading G4C. A sequential access memory system comprises a sequential access memory such as a magnetic disc or drum, or a delay line, means operative during a single memory period of the system for directing individual processing of information transfer requests of one of several ordered sequences thereof, and means for ordering successively occurring information transfer requests into said sequences according to address in the order in which the addresses would be accessed during a memory period. In one embodiment data is recorded in tracks TK1-TKp on a magnetic drum the circumference of the drum being divided into segments ST1-STm (each storing for instance four storage blocks and a control block) such that only one block can be recorded into or read from each segment during each memory period or revolution of the drum. Data requests, for readout from the memory or read-in to the memory appear at 140 and include the sequential access memory address, a read/write instruction and the address of a small random access memory 120 at which information is stored to or which the information is to be transferred. The data requests are stored in transfer request register 150 in the order in which they are received, with the first at R31. The location in buffer store 120 to which the information is sent is assigned by the control circuit 110 which then directs the information to the store 120 and the transfer request including the buffer store address to the register 150. The transfer requests are ordered in queue registers 220, 291 each comprises a set of register stages equal in number to the segments on the drum and directly corresponding thereto, QR1 to ST1, QRm to STm etc. The request in stage RS1 of register 150 is read out via RD1 and directed by the control unit to the appropriate stage of queue register 220. Register 150 is shifted so that data in RS2 is now in RS1 and the procedure repeated. When a request is identified that would be stored in stage in the queue register already holding a request the request remains in stage R31 and the request in R32 is read out via RD2. When the register 150 is shifted only stages RS3-RSn are shifted down one leaving the original data in RS1. If RS2 would enter a stage already filled then RS3 is read out &c. The ordering of the queue register is effected during one revolution of the drum. During the next revolution the requests are read out in synchronism with the appropriate segment and the new requests and those that had been left in stages RS1, RS2 ... are read into queue register 291 in a similar manner. In the second embodiment (Fig. 4, not shown) it is assumed that access may be had to each consecutive storage address in the memory. Data as before enters the transfer request register, but then the address of each request is compared with an address selector to pick out, for instance, a request for address 0000. If this request is found it is transferred to one of the queue register, the address selector is incremented by one and the next address is looked for. If it is not found the address selector is incremented when all the stages of the transfer request register have been interrogated. If a request is found it is transferred, the register stage cleared and the data in stages above this stage is shifted down. If a queue register is filled with requests before the end of a memory cycle scanning of the request register is terminated until the beginning of the next cycle. In a third embodiment (Fig. 5, not shown) it is assumed that only one address in each of a plurality of sectors can be accessed during a memory cycle. A plurality of registers 551- 55x is provided each being associated with one of the memory sectors. Input data is steered into the appropriate register 551-55x, each register being able to store y requests. The bottom stages of the registers 551-55x are connected to the queue registers. Once during each memory period the contents of the lowest stage of the registers are read into one of the queue registers. .