Patent GB-1313169-A (GB)
Title: Binary adding and subtracting arithmetic member
IPC: G06F7/50
Filed: 1970-06-04
Abstract: 1313169 Adder/subtractor PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 4 June 1970 [7 June 1969] 27010/70 Heading G4A A binary arithmetic unit comprises an accumulator consisting of a number of flip-flops FF 0 -FF n  in which a first binary number is stored, an input register in which a second binary number is stored, and a control device connected to the input register and accumulator and including a device arranged to sense the position of the least significant binary 1 in the second number and to change the state of the correspondingly ordered accumulator flip-flop and a gating circuit adapted to generate sequentially control signals Ti to control the ith flipflcp in the accumulator commencing with the next higher ordered flip-flop to the one whose state is changed by the sensing device, the accumulator being arranged so that successive flip-flops therein have their state changed in response to corresponding control signals Ti. If the (i-l)th flip-flop changes from 0-1 the gating circuit is operative to produce a signal Ti which changes the state of the next flip-flop in the chain for which the corresponding bit in the second binary number is " 0 " and if the change was from 1-0 for which the corresponding bit in the second binary number is " 1 ". The procedure repeats along the chain and the final contents of the accumulator are equal to the sum of the first and second binary numbers. The complementary outputs Ai and Bi from the flip-flops are passed through differentiating circuits D which produce outputs #Ai and #Bi which represent 1-0 changes in those outputs. The signals #Ai and #Bi are then utilized in the gating circuit 5 together with the bits C 0 -C n  which constitute the second binary number to produce the control signals Ti. Subtraction may be performed by using four NAND gates enabled in pairs by " add " and subtract control lines and which are, in the case of subtraction, effective to replace #Ai by #Bi and vice versa. For subtraction an additional sign flip-flop FF n+1  is provided to enable binary " 1 " to be subtracted from the result in the accumulator if the contents of the accumulator pass through zero by subtraction and to be added to the result at a passage through zero by addition. In a modification a further flip-flop FF N  is provided for registering the state of the sign flip-flop at the start of a series of additions and subtractions, the states of flip-flops FF n+1  and FF N  being compared at the end of the series and the addition or subtraction of a binary " 1 " being made as appropriate if their contents differ. In this way time is saved since only a single compensatory addition or subtraction is required. Subtraction is also possible by adding the complement of the second binary number. For this purpose a gate circuit is provided for complementing the bits Ci. A signalling device is also included for the compensatory addition or subtraction of binary 1 as above. The signalling device may consist of a reversible counter for counting the passages through zero in both directions, the contents of the counter being added to those of the accumulator at the end of the operation. A pulse generator may be provided to initiate a second operation when its predecessor has been completed. The Specification describes the gating circuits and Boolean functions required to produce the above operation in full.