Patent GB-1445010-A (GB)
Title: Memory system incorporating a memory cell and timing means on a single semiconductor substrate
IPC: G11C11/405
Filed: 1973-10-29
Abstract: 1445010 Memory systems INTEL CORP 29 Oct 1973 50132/73 Heading G4C [Also in Division H3]  A memory system (Figs. 3A, 3B) comprises, on a single monolithic semi-conductor substrate, an array of memory cells and a generator to provide time signals on receipt of an external signal. Preferably an address buffer and address decode circuitry are also formed on the same substrate. As described, the cells 12, arranged in rows and columns, each comprise three FET's 14, 16, 18, information being stored on the parasitic capacitance associated with FET 18. A timing cell 75 comprising two FET's 77, 79 is associated with each row of cells to simulate the storage cells and feed a timing signal to timing generator 100 to control the pulse width of signals R, R and YE derived from the external signal CE. Signals R, R<SP>1</SP> are supplied to column amplifiers 55 used for sensing the information read out from the cells, signal R also being fed to an intermediate voltage generator 40 deriving appropriate level signals to read data from and write data into the cells. The YE signal is used in circuitry associated with column lines 22. A timing compensator is also included in for example the row decoders to compensate for fabrication differences between substrates. In operation in response to the external signal CE, timing generator 100 supplies a signal YE to the column and row address decoders so that a cell is selected. An intermediate level voltage is then fed from generator 40 on X line 20 to the gates of FET's 14, 16 in the selected cell to cause FET 14 to partially conduct so that, if a charge is stored on the parasitic capacitance, FET 18 will conduct and previously precharged column line 22 will discharge, the signals R, R being fed to the associated column amplifier 55 to detect the charge level and supply a signal to the data control cell 97. A control bit amplifier 125 stores the read information in complementary form. Writing is effected by placing the information to be stored on the appropriate column line and applying a high level signal from the generator 40 to the appropriate X line to cause FET 14 in the selected cell to fully conduct to charge the capacitance. Timing compensator (Fig. 14, not shown).- With signal CE applied to FET (303) it conducts to charge parasitic capacitance (301) to a level V DD . When an input signal is then applied to inverter (308) NOR gate (309) supplies an output signal which also renders FET (300) conductive so that the capacitance is discharged, the output from an inverter (302) then switching the state of the NOR gate (309) to cut off the output signal which is consequently of a width dependent on the conductance of FET (300) and the capacitance of capacitor (301). Intermediate voltage generator (Fig. 4).-An intermediate level signal is derived at node 330a when signals CED and CE are applied to FET's 339, 337 respectively, the D.C. level established being checked by the feedback provided through FET's 342, 343. The high level signal is initiated by the application of a signal R to node 350. The width of this signal is determined by the capacitance between node 354 and the substrate and the rate of discharge through FET 355. Decoder.-The row decoder (Fig. 7, not shown) comprises a NOR gate in the form of a bank of FET's (372a-372f) to the gates of which row address bits are applied. A node (370) which is preconditioned by a signal CE causing an FET (371) to conduct is pulled to ground potential if one of the bank of FET's conducts. The signal on lines (375a, 375b) from the intermediate voltage generator is coupled to the X lines (376a, 376b) whenever node (370) is charged. The column decoder (Fig. 8, not shown) also comprises a bank of FET's (383a-383f), a preconditioned node (381) being pulled to ground potential if any one of the FET's conduct to prevent conductance between YE (387) and line 386. Column amplifier (Fig. 5, not shown).-During the signal CE the input output line (390) is charged to a potential V CC  and at signal CED, if a charge is stored on a cell coupled to the input/output line, the charge on the line flows through the memory cell causing a node (394) to rise in potential and consequently causing a second node (392) to rise so that the line (390) drops sharply in potential due to feedback through an FET (402). R and R generator (Fig. 10, not shown).-At the beginning of a cycle signal CE preconditions a node (415) to a voltage V DD  to charge a capacitance (423) which forms a bootstrap circuit with FET (422). Node (418) is preconditioned to ground potential and line (410), connected to the timing cells is preconditioned to a level V CC . When signal CE goes high, FET (422) conducts to provide a signal on R line (413). The timing cell then causes the charge on line (410) to decay so that line (412) rises and line (413) drops. When a W signal appears on lead (414), FET (435) conducts to cause line 413 to rise again.