Patent GB-1196347-A (GB)
Title: Improvements in Electronic Computers
IPC: G06F15/00
Filed: 1968-03-29
Abstract: 1,196,347. Digital electric computer. ING. C. OLIVETTI & C. S.p.A. 29 March, 1968 [1 April, 1967], No. 15336/68. Heading G4A. A stored programme electronic digital computer is adapted to perform the following sequence of operations in the execution of a main programme and a sub-programme: (a) during the execution of the main programme enter a re-entry address in a register under the control of a re-entry prearranging instruction recorded in the main programme, (b) subsequently jump to and execute the sub-programme under the control of a jump instruction recorded in the main programme, (c) re-enter the main programme at the re-entry address under the control of an end-of-sub-programme instruction recorded at the end of the sub-programme. As shown in Fig. 6 a main programme is held in an instruction register of the computer. A key AUT on the keyboard is pressed to produce automatic operation and under the action of a counter causing access of the register in sequence the instructions are normally accessed successively. The first place C1 does not contain a significant programme instruction but the remaining places do. When place C5 is reached an instruction F15 (F12. Sn) known as an instruction of the second format, is found. This is a two-character instruction, the first character F15 causing replacement of the contents of the first place C1 with the second character F12 Sn. F12 specifies an unconditional jump to the programme instruction Sn. The next place is accessed and the programme proceeds until instruction F12 Sm is reached in C20. This causes a jump to the place C91 containing insertion code Sm which is the place preceding the first instruction of the sub-programme. At the end of the programme instruction F14 is obtained which is an instruction of the third format and causes a jump to the instruction contained in the first place C1 of the instruction register. This contains F12 Sn as stated above and causes a jump to place C21 containing insertion code Sm, and continuation of the main programme. The computer includes a keyboard allowing manual and automatic operation and entry and storage of a programme from the keyboard or programme cards. The memory consists of a delay line LDR such as a magnetostrictive delay line holding ten registers each holding thirty eight-bit characters, the first ten consecutive binary signals representing the first bit of the first place of each register. The delay line is connected to a serial-to-parallel convertor 42 allowing the signals representing corresponding bits in each register to be presented simultaneously. A parallel-to-serial converter 43 feeds the data back to the delay line. Two registers I. J contain between them up to 60 instructions, those of formats one and three occupying one 8-bit place, those of format two occupying two 8-bit places. Registers A, D, E may contain instructions or numerical data. The first format has four bits representing an operand address and four bits representing 16 operation. The third format has all 8 bits representing a function code. A decimal digit is represented by four bits B5-B8. A decimal point bit B4 is "0" for all digits of the number except for the digit after the decimal point, B3 is a sign bit, B2 is "1" only for the decimal digits of a number being "0" if the decimal place is not occupied by a digit. B1 is a tag bit. B1R in the first place of first register R starts the time pulse generator at the start of each cycle and B1E in the thirtieth place of the final register E stops the generator. B1N in the nth place of the N register indicates that the next instruction is in the nth place of the selected instruction register, the tag bit being updated after each instruction. B1M in the nth place of register M indicates that the next number from the keyboard is entered in the (n-1)th decimal place. Utilization of the tag bits can be used to align numbers. Contents of a register can be passed via a register K which effects an extra delay of a digit period until the decimal point bit in one number matches the position of the decimal point bit in another number or until the decimal point bit is in a predetermined position. During the operation of one instruction a bit B 1 is written into the next instruction, normally the adjacent instruction to continue the programme.