Patent GB-926390-A (GB)
Title: Improvements in or relating to digital summing circuits
Inventor: DAVIE JULIAN ALBERT WALTER
IPC: G06F7/50
Filed: 1959-03-12
Abstract: 926,390. Correcting binary-coded addition. INTERNATIONAL COMPUTERS & TABULATORS Ltd. March 10, 1960 [March 12, 1959], No. 8570/59. Class 106 (1). Groups of pulses representing binary-coded digits are summed serially in a single adder to form an uncorrected sum digit which is then fed back if necessary, to the same adder to be summed with a filler digit to produce the true sum. The need for a filler digit is determined by comparison of the uncorrected sum digit with either the digit radix (e.g. 10 for decimal digits) or the code radix less one (e.g. using 1, 2, 4, 8 code the radix is 16). The algebraic summation of two digits takes a period of time known as a sector, divided into ten subsections SS, each subdivided into clock pulse times to U6. Pulses occurring in subsectors SS1 . . . represent the binary code values 1, 2 . . . Number pulses occur at time in a subsector. For addition, the groups of pulses representing the two digits to be added set flip-flops 3, 4 respectively, U6 pulses unsetting the flip-flops, and the outputs are passed through gates 5 and 11 for application in true and inverted form to coincidence circuits 71 to 78 forming a binary adder which also receives the set and unset outputs of a carry flip-flop 27. Coincidence circuit 71 produces a signal applied to or circuit 78 if the A input is 1 and the B and Carry inputs are 0 ; coincidence circuit 73 produces a signal applied to or circuit 80 if the A and B inputs are both 1 and the Carry input is 0; the other coincidence circuits provide for other combinations of inputs. The output of or circuit 80 in true or inverted form sets or unsets after suitable delay the carry flip-flop 27 at U6 time of each of SS 1 to 5, while the output of or circuit 78 on lines 14, 15 is similarly applied to a flip-flop forming the first stage of shaft register 20 which is shifted by U6 pulses. The addition takes place during SS1 to 5, an SS5 pulse indicating a carry on 16, and during this time the sum output is compared with signals derived from a source 82 which may be a magnetic drum. These signals represent the radix of the input digits less one and are applied to the unset side of a flip-flop 31, the side of which is applied to a pair of coincidence circuits 37, 38 of which circuit 37 receives the inverted sum digit and the inverted unset output and circuit 35 receives the true sum digit and unset output. An additional comparison one bit is inserted into or circuit 34 at SS5 to test for the presence of a carry on 16. The arrangement effectively compares the uncorrected binary sum with the code radix less one leading to the result that if the sum is greater than this amount a flip-flop 40 is set at the end of the comparison. This opens a gate 46 which passes the inverted comparison digit-which is the filler digit-as the A input to the adder as the contents of register 20 are gated as B input during SS6 to 9. Any carry on 16 is suppressed during this operation by unsetting the carry flip-flop 27 at SS10 but if the flip-flop 40 is set indicating a carry on the code radix an SS1 signal through gate 58 sets the carry flip-flop before addition of the next pair of digits. Subtraction follows a similar course. The unset side of flip-flop 3 supplies the inverse or complement of the number to be subtracted from the B input. It is merely necessary to test for absence of endaround carry to determine if correction is necessary and this is done by closing gate 33 to pulses from flip-flop 31, only an SS5 pulse through or circuit 34 being compared with the SS5 sum bit. If end-around carry exists flip-flop 40 is set, otherwise the flip-flop remains unset and the scale digit is added to the contents of register 20, gate 63 being opened, during SS6 to 9. The comparison may be by the apparatus disclosed in Specifications 678,427, 738,314 and 738,605. The operands may be derived from a magnetic drum as in 847,961. Specification 673,759 also is referred to.