Patent GB-1525611-A (GB)
Title: Data processing system in a receiving terminal of a pcm-tdma communications system
IPC: H04B7/155
Filed: 1975-08-19
Abstract: 1525611 Time division multiplex communication systems FUJITSU Ltd 19 Aug 1975 [30 Aug 1974] 34372/75 Heading H4M At the receiving terminal of a PCM-TDMA communication system a burst data signal is received, a burst clock from the burst data signal is regenerated and data and a unique word positioned before the data is recovered from the burst data signal by demodulation and processing. The recovery of the unique word is indicated by generation of a unique word detecting output synchronized with the burst clock. At least part of the processing of the burst data signal is performed by a local clock having a phase which is not synchronized with the burst clock. The processing system in the receiving terminal comprises a buffer register 12-15, Fig. 3a, and a first ring counter 11 initially set by the unique word detecting output, which produces a first output when operated by the burst clock regenerated from the burst signal. A first group of gate circuits is connected to the first ring counter and the buffer register such that the data may be written into the buffer register in order and in synchronization with the burst clock. A retiming circuit 20 receives and retimes, by reference to a local clock, the unique word detecting output so as to synchronize it with the local clock. A second ring counter 21 (Fig. 3b) is connected to the retiming circuit and is initially set by the locally synchronized output of the retiming circuit. It is operated by the local clock to provide a second output. A second group of gate circuits 22-25 connected to the buffer register 12-15 and to the second ring counter 21 reads the content of the buffer in synchronization with the local clock by using the second output of the second ring counter. At the receiving terminal (Fig. 2), received burst signals are passed via a down converter providing signals at IF to a demodulator 2 and thence to a decoder 4 and unique word detector 5, operated in accordance with the received burst clock, within system 3. The decoder output passes via the connecting circuit 1 (which forms the subject of the invention) to a descrambler 7 and demultiplexer 9 operated in accordance with the local clock of the receiving terminal. The local clock also controls an aperture generator 8 controlling the unique word detector and thus the interface circuit 1. In the interface circuit 1 the received burst clock rbc, which is derived from a clock recovery circuit in the demodulator 2 is applied to the retiming circuit 20 (Fig. 3a), ring counter 11 and flip-flops 12-19. The unique word in the received signals is positioned between a sync word and the front of a burst signal, and the phase of the front portion of the burst is determined by detecting the unique word. When detected, a pulse uwdp is generated and supplied to second inputs of the retiming circuit 20 and ring counter 11. A local clock having the same frequency but not synchronized in phase is provided within the receiving terminal. It is supplied to the retiming circuit 20 so as to retime the unique word pulse uwdp to produce a signal uwds synchronized with the local clock. Input data from the decoder 4 is applied either via line p or q (depending on the output phases of the four phase psk demodulator 2) to a series of D type flip-flops 12-15 or 10-19. Binary data is clocked into each flip-flop in turn in accordance with the output from the ring counter 11. The flipflop outputs pass to AND gates 22-25 (Fig. 3b) or 27-30 respectively, where they are passed in accordance with a pulse sequence from ring counter 21 in accordance with the local clock to OR gates 26 or 31 and thence to the descrambler 7.