Patent GB-1278151-A (GB)
Title: Electronic desk top calculator having a dual function keyboard logic means
IPC: G06F15/02
Filed: 1970-04-23
Abstract: 1278151 Desk top calculator keyboard SINGER CO 23 April 1970 [5 May 1969] 19502/70 Heading G4A A desk top electronic calculator has a keyboard which includes a number of digit keys, a number of function keys, and a manually actu. able dual function circuit coupled to one of the keys and which is operative when actuated following actuation of one of the digit keys to indicate completion of the entry of a number into the calculator and following actuation of one of the function keys, including itself, to change the value of an arithmetic sign bit associated with the entered number. Data storage.-The digital data may be stored in the calculator in an acoustic delay line 40. The data is interleaved in the delay line such that like ordered digits from each number follow each other in a group. Each digit is represented by the corresponding number of pulses which occur (or do not occur) at particular designated times within each digit, additional time slots being provided for synchronizing &c. pulses. Each number also has a digit position to indicate the arithmetic sign of the number, zero representing +, and one representing -. Pulses coming off the delay line are used to set a counter A, the contents of which may be transferred to counter C either directly in parallel or via counter D. Counter C is then counted down to zero and the pulses placed back on the delay line. The Specification states that magnetic core, drum, or disc stores may be used in place of the delay line.  Shifting data.-Two data shift modes are described. In the first, SHIFT UP, the data are sequentially passed through counters A, D and C so that a one digit period delay is introduced and the data is effectively shifted one place. In such a snift the last digit is lost as no room exists for it on the delay line; in practice the data path is changed back to one via counters A and C as soon as the final count is loaded in counter D, which is then reset. In the second mode, SHIFT LEFT, every nth digit is passed via counters A, D, C, the remaining digits passing via counters A, C. Since the data stored in counter D is delayed by n digit times, one of the interleaved numbers held in the delay line will all have been shifted one place to the left. Calculating.-Addition of two digits is accomplished by preventing counter A from being reset so that a second digit emerging from the delay line is added to the first already held in the counter. For subtraction the pulses representing the second digit are used to decrement the contents of counter A. Multiplication and division are accomplished by successive addition &c. Data input and Circuit details.-Actuation of one of the digit keys sets flip-flops 53 and 55 and causes a phase counter to step to one (E.P.C.1). Flip-flop 66 is set by the output of flip-flop 55 when the phase counter steps to two (E.P.C.2) and the AND gate 65 is enabled by the simultaneous occurrence of the outputs from flip-flops 55 and 66, E.P.C.2 and the data inputs C1-C15 and R1-R4 causing the data on the delay line to be shifted (see above); C1-C15 represent the pulses forming the digits of the numbers stored in "registers" R1-R4 on the delay line. The signals E.P.C.2 and CD enable AND gate 68 and the keyed digit is placed in counter 45 to await entry on to the delay line into the space vacated by the shift operation. The digit is entered on the occurrence of a phase 3 count (E.P.C.3) which enables AND gate 70. The phase counter then resets to zero. If the next key actuated is another digit key flip-flops 53 and 55 will set as before but flip-flop 66 will be in the reset condition and AND gate 65 will not be enabled. The remaining steps are as above and the digit is entered into the delay line when the first entered digit is shifted left by the output of gate 70. When the last digit has been entered the dual function key 16 is actuated which causes flip-flop 56 to be set via gate 57 and the phase counter steps to one (E.P.C.l). When the phase counter steps to two flip-flop 66 is toggled (E.P.C.2) and resets due to the output from flip-flop 56. A number entry complete signal is thus produced and the number which has been keyed in may be displayed for confirmation. When the phase counter resets to zero flip-flops 53 and 56 are reset. If the dual function key is actuated again flip-flop 56 is set and the phase counter is enabled. A set output from flip-flop 66 is also present at the input of gate 72 along with the output of flip-flop 56 and a "CHANGE SIGN" signal. When the remaining timing signals occur AND gate 74 will be enabled and counter A will be incremented. The contents of counter A are then written into the delay line in the digit position which indicates the sign of the number previously keyed in. Several successive actuations of key 16 cause the sign bit to change from positive to negative and back accordingly. Alternatively in place of the actuation of the key 16 following data input a function key 14 may be actuated. In this case the actuation of a function key 14 also causes a number entry complete signal to be generated. Finally data input may be followed by the actuation of key 16 which in turn may be followed by the actuation of a function key. In this latter case a number entry complete signal is generated and the relevant functional operation is then performed on the entered number.