Patent GB-936695-A (GB)
Title: Stored programme digital computer
IPC: G06F9/40
Filed: 1961-07-25
Abstract: 936,695. Digital computers. SPERRY RAND CORPORATION. July 25, 1961 [July 25, 1960], No. 26980/61. Class 106 (1). A digital computer includes masking means associated with a register and capable of recognizing a tracing digit in an instruction, thereby causing the computer to generate a new instruction. General arrangement.-The invention is applied to a general-purpose parallel-mode computer having a word length of twelve decimal digits, each digit being represented by five bits (four data bits plus one checking bit). The computer comprises a memory 152, control curcuits 148, an arithmetic unit 131, a B-adder 139, a set of addressable registers 121, an instruction register 101, a control counter 104 and a set of addressable flip-flops 162. In normal operation, the contents of the control counter 104 are progressively stepped by unity on passing through the B-adder 139. An instruction called for by the control counter 104 is transmitted from the memory 152 to the instruction register 101. A second control counter, 106, is employed to address the memory 152 during a transfer of control operation. The portion T of an instruction word is transmitted via a decoder 161 to the addressable flip-flops 162. A machine instruction has the form where the T digit has tracing values of 1 to 9, the I digits specify the operation to be performed, the A digits specify an operand address from the addressable registers 121 and, on being passed into selector storage 113, specify the address of one of the addressable flipflops 162. The B digits also specify an address in the addressable registers 121, but in this case the contents thereof are employed to modify the M digits of the instruction, as described in Specification 933,066. The machine operates using minor cycles of eight pulse times 0-7, four minor cycles being employed for the execution of instructions. Setting addressable flip-flop. - An instruction 0 97 AA 00 00000 will set the addressable flip-flop 162 selected by the digits AA. The I and A digits are gated via gates 102, 103 into section 107, 107A of instruction register IR 2. During the third minor cycle, gates 134 are enabled to pass the A digits into the B-adder 139, together with zeros from register 147, the output being gated into selector storage 113. The digits " 97 " when applied to arithmetic unit control 130 to ensure that no results are produced thereby. The A digits are decoded by a decoder 183, the outputs therefrom setting the required flip-flop 162. Unconditional transfer instructions.-There are two of these, the " 90 " and " 91 " instructions. The " 90 " instruction requires that its M address is placed in the first control counter and the sequencing routine proceeds from that address (Fig. 6, not shown). The " 91 " instruction is generated by the computer upon the coincidence of a tracing digit T in instruction register 101 with the set condition of one of a pair of addressable flip-flops in the array 162. The effect of this instruction is to add unity to the M digits forming a part thereof and to proceed with the sequencing in accordance with the thus augmented M digits. As described, there are nine tracing flip-flops corresponding to the digits 1-9. Assuming that a previous " 97 " instruction has set one of the flip-flops, the computer operates in its regular sequence until an instruction containing the corresponding tracing digit occurs. When an instruction having a tracing digit corresponding to the set flip-flop occurs, this instruction is not executed, but signals are applied to insert the digits 9100 in the I and A portions of instruction register IR2. Simultaneously the contents 02600 of a register 178 are supplied to the B-adder 139. The second control counter 106 is now employed to address memory location 02601 for the next instruction and the address plus unity of the instruction having the detected tracing digit is placed in memory location 02600. As described for a diagnostic routine the next instruction may take the form the " 95 " instruction being for conditional transfer, transfer taking place only if the addressable tracing flip-flop designated by the A digits is set. The M digits denote the address of a diagnostic routine involving tests and displays of various registers. An entire series of test or " 95 " instructions may be provided starting at memory location 02600 and each of the nine tracing flip-flops may be tested in turn. In a modification, only one tracing flip-flop may be provided. The automatic generation of the " 91 " instruction may take place upon the detection of machine errors. The tracing routine associated with a " 91 " instruction is terminated with an instruction which returns control to the original routine. Specification 824,968 also is referred to.