baber/WOPTO huggingface dataset:
Patent TW-445302-B (TW)
Title: A vacuum deposition apparatus
Inventor: ONO MASANORI
IPC: C23C14/30
Filed: 1999-02-26
Granted: 2001-07-11
Abstract: The invention provides a vacuum deposition apparatus, which comprises a vacuum chamber, an electron beam source coupled to said vacuum chamber, a holder provided in the vacuum chamber for holding a substrate on which a film is to be deposited, a target of deposition materials being placed opposite to the substrate, said target having at least the same area as the substrate, and magnets provided at the back of the target for generating magnetic fields near a surface of the target. The target opposite to the substrate has at least the same area as the substrate and the magnetic fields are generated near the surface of the target. The electrons emitted from the electron beam source are therefore diffused and uniformly distributed over the surface of the target. The electrons enter into the target, and the materials on the surface of the target are uniformly sputtered.
Patent TW-558910-B (TW)
Title: 3D sound system
Inventor: WEI CHIH-HSIU
IPC: H04R5/02
Filed: 1999-03-19
Granted: 2003-10-21
Abstract: The present invention provides a 3D sound system to enhance the sound effect on the rear side for the listener by using four loud speakers. The 3D sound system comprises two front loud speakers, two rear loud speakers, one sound processor, and a sound distributor. The two front speakers and two rear loud speakers are located on the left, right sides in front of the listener, and on the left, right sides behind the listener respectively, so as to play the sound to the listener. The sound processor is for performing a 3D sound processing to an original sound signal based on the position of sound source, so as to generate the sound signal which should be received by the left, right ears of the listener. The sound distributor is electrically connected to the sound processor and the position between the two front and read loud speakers, which is for distributing the left-right-ear sound signals generated by the sound processor to the two front loud speakers and the rear speakers based on the position of the sound source, so that both ears of the listener can receive the transmitted 3D sound similar to the original sound signal from the position of sound source.
Patent TW-428011-B (TW)
Title: Novel polyimide composition
Inventor: OKADA KOHJI
IPC: C07C63/00
Filed: 1999-03-30
Granted: 2001-04-01
Abstract: The present invention provides a novel polyimide composition which includes a cinnamoyl group or a derived cinnamoyl group and has photo-reactivity and heat-reactivity inherent to the cinnamoyl group, comprising a monomer unit of the general formula (I) in a proportion of not smaller than 1% by weight, wherein X is a tetravalent organic group, and W is a divalent organic group selected from divalent organic groups represented by the formulae (1-a), (1-b), (1-c), (1-d), (1-e), and (1-f). Further, a novel diamine and an acid dianhydride according to the present invention are materials mainly used for preparing a novel polyimide composition having the cinnamoyl group or the derived cinnamoyl group in a main chain or a side chain.
Patent TW-432676-B (TW)
Title: Method for forming cylindrical capacitor
Inventor: WU DE-YUAN
IPC: H01L27/10
Filed: 1999-04-02
Granted: 2001-05-01
Abstract: A kind of method for forming cylindrical capacitor is disclosed in this invention. At first, a substrate is provided, on which a dielectric layer is formed and has a contact hole that leads to the upper surface of substrate from the upper surface of dielectric layer. A conductor layer and an isolation layer are formed, in which the conductor layer fills up the contact hole and the isolation layer is located on top surface of conductor layer. On the upper surface of isolation layer, there is a recess slot of lower electrode for DRAM capacitor. The recess slot pierces through the isolation layer and falls into the conductor layer without piercing through the conductor layer, in which the recess slot is located on the upward extending line of the contact hole. An oxide layer is formed on the whole surface inside the recess slot. Finally, etching method is used to remove the isolation layer, the oxide layer inside the recess slot of lower electrode for DRAM capacitor and part of the conductor layer, such that the original conductor layer leaves only a cylinder shape remained on the dielectric layer and thereby a cylindrical capacitor is formed.
Patent TW-438673-B (TW)
Title: Method of making a breathable, barrier meltblown nonwoven
Inventor: MAUGANS REXFORD A
IPC: D04H1/42
Filed: 1999-04-30
Granted: 2001-06-07
Abstract: The present invention relates to a method of making a breathable nonwoven fabric having enhanced moisture barrier properties. In particular, the invention pertains to a method of making a meltblown fibrous layer having an improved hydrohead performance (for example greater than 40 millibars (16 inches of H2O) and adjacent to at least one spunbond fibrous layer, wherein the method comprises secondary processing of the meltblown layer prior to bonding to spunbond layers. The resultant spunbond/meltblown (SM) nowoven fabric was breathable and characterized as having a cloth-like feel and softness and enhanced hydrohead performance rendering it suitable for use in, for example, personal hygiene, disposable industrial garment and infection control/clean room applications for items such as coverings, incontinence pads and diapers, especially as a diaper backsheet or containment flap.
Patent TW-456147-B (TW)
Title: Information process device, method, providing media, recording media, and amusement systems
Inventor: OHBA AKIO
IPC: H04N5/44
Filed: 1999-05-19
Granted: 2001-09-21
Abstract: The present invention provides the user with conditions of errors found in the distribution of data transmitted in the information process device and the connection of electronic machines for correct connection. The image part (61) uses a display device, e.g. television, to display the correct connection. When any error is found in the electronic machine connection, the data part (62) and the image part (61) will jointly display the error on the screen of the image display device. The option data area (62a) of the data part (62) will notify the user with the error by means of telop. The information process device records various process data in the basic data area (62b). Under such construction, while only the image part (61) is displaying, the information process device processes the data input from the image part (61) and the data part (62) according to the data of the basic data area (62b).
Patent TW-428181-B (TW)
Title: Inductor element
Inventor: OKAMOTO AKIRA
IPC: H01L27/04
Filed: 1999-05-26
Granted: 2001-04-01
Abstract: An object of the present invention is to provide an inductor element 10 that effectively functions even if it is formed on the substrate. The inductor element 10 has two vortex-shaped conductors 1, 2 formed on a surface of a semiconductor substrate 3. The inductor element 10 is formed so that the upper conductor 1 and lower conductor 2 almost overlap each other as seen from the surface of the semiconductor substrate 3. In addition, extension wires 6a, 6b are connected to the outer circumferential end (outer edge) and inner circumferential end (inner edge) of the upper conductor 1, respectively, and the outer circumferential end of the upper conductor 1 is connected to the inner-circumferential end of the lower conductor 2 via a connection wire 6c. The upper conductor 1 functions as an inductor conductor and is connected via the extension wires 6a, 6b connected to both ends thereof, to the circuit formed on the semiconductor substrate 3.
Patent TW-432194-B (TW)
Title: Ring furnace with central tubular flow
Inventor: DREYER CHRISTIAN
IPC: F27B13/06
Filed: 1999-06-01
Granted: 2001-05-01
Abstract: The furnace for baking carbonaceous blocks comprises, along the longitudinal X direction of the furnace, a series of sections, each section comprising, in the transverse Y direction, hollow walls (3) through which a heating gas flow comprising combustion gas or a cooling air flow circulates, alternating with pits containing carbonaceous blocks to be baked, each of the said hollow walls (3) in a section being in communication with a wall in an upstream section and/or a wall in a downstream section, so as to form a conduit through which the said gas flow circulates, each of the said walls of a section comprising two vertical lateral partitions (38) in the X-Z plane, and elements in the transverse Y direction for deflecting the said gas flow passing through the said wall and maintaining a constant spacing between the said lateral partitions (38), and characterized in that each wall (3) comprises a means of maintaining, over at least one third of the length L of said wall, a gas flow of rate D uniformly distributed over the entire normal cross-section S, with a degree of uniformity of the distribution of said flow of rate D defined by the expression ""2yD-0.5yD/yS"", where ""2yD-0.5yD"" denotes the extent of the range of the flow D corresponding to a fraction y of the said normal cross-section S, and in which y is not more than 0.25.
Patent TW-417211-B (TW)
Title: High voltage transistor that combines N typed buried layer and N well to lower the substrate bias effect and the manufacture method thereof
Inventor: LIOU GUO-JOU
IPC: H01L21/335
Filed: 1999-06-11
Granted: 2001-01-01
Abstract: This invention comprises an N+ buried layer formed within the wafer, wherein the epitaxial silicon layer is formed above the above-mentioned N+ buried layer whereas P well and N well are sited among the above-mentioned epitaxial silicon layer respectively, and the above-mentioned N well surrounds the peripheral of P well connects with the N+ buried layer to separate the P well, and the field oxide region is formed above the P well and N well to define the active region, a gate oxide layer is formed on the surfaces of the P well and the N well and is adjacent to the field oxide on the N well, the gate is formed above the gate oxide and the drain contact region is sited within some specific region of N well, the source region is sited within P well, one insulated layer covers the gate and part of P well and N well and exposes the drain contact region and  the source which is used as the film layer of insulation, whereas the channel region of HVNMOS is sited within the P well under the gate oxide. The method of this invention comprises forming the N+ buried layer and growing one epitaxial silicon layer, utilizing ion implantation to manufacture N well and P well to form the field oxide region above the wafer, then forming the gate, the drain contact region as well as the source.
Patent TW-559634-B (TW)
Title: Arundo donax pulp, paper products, and particle board
Inventor: ALTHEIMER ERNETT
IPC: D21C5/00
Filed: 1999-12-14
Granted: 2003-11-01
Abstract: Composite panels and pulp, and paper products of the pulp, are produced from Arundo donax. In the fabrication of the composite panels, Arundo donax is comminuted to a suitable size, combined with a binder, and consolidated into panels that meet standards for construction and/or furniture grade panels. The Arundo donax particulates may be combined with wood particulates to produce a mixed furnish that can be used in the preparation of composite panels. Comminuted Arundo donax is treated, in conventional pulping processes, to produce a high tensile strength pulp that can be used in the production of paper. The pulp has a lighter color than wood pulp, and thereby uses less bleaching chemicals to achieve a desired whiteness. The pulp can be combined with wood pulp to produce a variety of products.
Patent TW-415136-B (TW)
Title: Method of producing electric connector terminal and electric connector product thereof
Inventor: HUANG NAN-TZUNG
IPC: H01R12/72
Filed: 1999-07-22
Granted: 2000-12-11
Abstract: The present invention relates to a method of producing an electric connector terminal and an electric connector product thereof. The method integrates the difference in terminal configuration caused by different distance between the electric connector and the soldering position in order to produce products from the same set of mold. The present invention comprises pressing out semifinished terminal on all assembly position from the metal plate, the semifinished product having a holding part of a primary bending, a opposite joint part and a plurality of tail parts both on the two sides of the holding part, and the bending part of the holding part being connected with a material belt; through the guidance of the material belt, sequentially assembling the semifinished terminal into the insulation part of the electric connector; as required, removing any excessive tail end, bending the remaining tail end toward the circuit board for connection of the circuit board; and joining the baffle and the shielding elements, etc. on the electric connector to obtain a product.
Patent TW-432224-B (TW)
Title: Method and apparatus for processing image data acquired by an optical scanning device
Inventor: MOORE CHARLES E
IPC: G06V10/10
Filed: 1999-07-29
Granted: 2001-05-01
Abstract: A method and apparatus for scanning an original image (14) with an optical scanning device (10) and for constructing a duplication of the original image (14). The apparatus of the present invention comprises an optical scanning device (10) for scanning the original image (14) and for generating an electrical representation of the original image (14). The scanning device (10) comprises an illumination device for projecting light onto an original image (14) being scanned, an optical image sensing device disposed to receive light reflected from the original image (14), and a processing device (54) in communication with the optical image sensing device for receiving electrical signals produced by the optical sensors of the optical image sensing device and for processing the electrical signals. The optical image sensing device comprises a plurality of optical sensors. Each optical sensor has a field of view and at least two of the optical sensors have fields of view which at least partially overlap. Each optical sensor generates electrical signals relating to the portion of the original image (14) within the field of view of the respective optical sensor. The processing device (54) processes the image data obtained by the optical sensors and determines the amount of overlap of the images obtained by adjacent optical sensors. Once the amount of overlap has been determined, the processing device (54) uses the determined amount of overlap to construct a duplicate of the original image (14). Preferably, sub-arrays of data suspected of overlapping are correlated to obtain values of a correlation array. The values of the correlation array are then analyzed to determine which data in the sub-arrays is overlapping image data. The overlap is then eliminated to construct a duplication of the original image (14).
Patent TW-423090-B (TW)
Title: Method of testing wafer film
Inventor: JUANG LUNG-SHIANG
IPC: H01L21/66
Filed: 1999-09-14
Granted: 2001-02-21
Abstract: A method of testing the bonding characteristics of a wafer film by a pull test, uses a standardized test chip and using an epoxy resin as the bonding interface between the test head and the test chip. The method comprises: immersing a test chip in salt water at 100 DEG C to boil for about 3.5 hours, the salt water being prepared by dissolving 15 grams of salt in 200 ml pure water; after this pretreatment step, bonding a test head with an epoxy resin, and baking the test head in an oven at about 150 DEG C for about 3.5 hours to cure the resin; performing a pull test and recording the measured values to complete the present invention. According to the present invention, a potential issue in a wafer can be detected during the production stage so that the issue can be improved accordingly.
Patent TW-I221718-B (TW)
Title: Modem driver for operation in a computer system having a memory, and method for employing said modem driver
Inventor: COLLIN ZEEV
IPC: G06F9/445
Filed: 1999-11-15
Granted: 2004-10-01
Abstract: A multi-task structure for a software modem including a plurality of self-contained executable entities. The executable entities include at least a controller and a data pump with the controller operating as an interface between an operating system driver and the data pump when signals are passed from the operating system driver to the data pump. In addition, the data pump includes at least a scheduler and a hardware driver, the scheduler interacting with additional self-contained executable entities and enabling the data pump to operate using one or more individual ones of the additional self-contained executable entities according to the signals passed from the controller to the data pump.
Patent TW-505708-B (TW)
Title: Gold plating solution and plating method using the same
Inventor: KIDA KATSUTSUGU
IPC: C25D3/48
Filed: 1999-10-12
Granted: 2002-10-11
Abstract: This invention provides a gold plating solution which uses gold compounds such as gold salts or gold complex compounds as gold and contains a buffer agent, an organic gloss agent and a conduction salt; the solution is characterized by containing bis(1,2-ethyldiamine). Through the use of a non-cyanide gold plating solution with above-mentioned characteristics, solution stability in any gold plating bath is excellent without causing any change of physical properties of the deposited gold and without being decomposed during gold plating operation. The gold plating solution includes two aspects, the use of bis(1,2-ethyldiamine) gold complex as an ingredient and the use of a gold salt as an ingredient. When such a gold plating solution is used, hardness, purity, and crystal state of the deposited gold can be controlled; thus, it is an excellent gold plating solution not seen among conventional counterparts.
Patent TW-541860-B (TW)
Title: Method of making a printed board
Inventor: YAMASAKI KOZO
IPC: H05K3/28
Filed: 1999-10-19
Granted: 2003-07-11
Abstract: A method of making a printed board is provided. The printed board has a base provided with a plurality of through via conductors having through holes extending completely between upper and lower surfaces of the base and closed by resin fillings and a plurality of blind via conductors having depressions closed by resin fillings. The method comprises the steps of preparing the base provided with the through via conductors having the through holes and the blind via conductors having the depressions, filling the through holes of the through via conductors and the depressions of the blind via conductors with resin paste by printing, while at the same time forming, on an upper surface of the base and at locations around the through holes of the through via conductors and the depressions of the blind via conductors, a plurality of projections made of the above described resin paste by printing, and curing the resin paste, thereby forming the resin fillings in the through holes of the through via conductors and the depressions of the blind via conductors. By this method, the upper surfaces of the resin fillings in the through holes and the depressions are not caused to recede or sink and become lower in level than the upper surface of the base but can be maintained higher in level than the upper surface of the base, thus making it possible to dispense with a manufacturing step for closing receding spaces and manufacture the printed board at lower cost.
Patent TW-451556-B (TW)
Title: A counter for performing multiple counts and method therefor
Inventor: BARNA PAUL
IPC: H03K23/66
Filed: 1999-11-18
Granted: 2001-08-21
Abstract: A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter for monitoring a number of specified events. A data storage device is coupled to the counter for loading the counter with counter values for each of the contiguous counts. A control logic circuit is coupled to the counter and to the data storage circuit for loading the counter and the data storage device with the counter values.
Patent TW-593191-B (TW)
Title: Silica glass optical material for excimer laser and excimer lamp, and method for producing the same
Inventor: YAMAGATA SHIGERU
IPC: G02B1/00
Filed: 1999-11-01
Granted: 2004-06-21
Abstract: A silica glass optical material for transmitting light with a wavelength of from 155 to 195 nm emitted from an excimer laser or an excimer lamp, which comprises silica glass optical material of ultrahigh purity, containing from 1 to 100 wtppm of OH groups, from 5x10<16> to 5x10<19> molecules/cm<3> of H2, and from 10 to 10,000 wtppm of F, but substantially free from halogens other than F, and having a fluctuation in refractive index, Deltan, of from 3x10<-6> to 3x10<-7>.
Patent TW-434875-B (TW)
Title: Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions
Inventor: ZHU MIN
IPC: H01L27/02
Filed: 1999-11-02
Granted: 2001-05-16
Abstract: The present invention discloses a method for reducing the capacitive coupling of the inductor in the integrated circuit chip. The method can form the inductor on any integrated circuit accumulated insulation layer, and further form two back-to-back reverse P/N junctions on the integrated circuit substrate and under the inductor. The junction is in serial connection along the insulation layer capacitor. In comparison with the conventional method, the present invention may reduce the inductor capacitive coupling factor as about 2 to 20 due to the fact that the capacitance reduction can improve the high frequency characteristic of the inductor such as over 1 GHz. By adding an additional single processing step, it can easily form the junction in the dual-well CMOS circuit. The additional step comprises using the dense phosphorus implantation to form a N-type region between the P-type well and the substrate, wherein the region is under the inductor. The junction does not need external bias for maintaining the continuous depletion area between the inductor and the substrate.
Patent TW-463496-B (TW)
Title: Dark current compensation circuit
Inventor: THOMAS BRENT D
IPC: H04N5/357
Filed: 1999-12-29
Granted: 2001-11-11
Abstract: An imaging device includes a compensation circuit for reducing an effect of dark current generated during operation. The compensation circuit calculates an initial dark current offset value using optically dark regions of a photo sensitive array. The compensation circuit also automatically adjusts the initial dark current offset value as output signals from successive rows of the photo sensitive array are transferred. The compensation circuit can calculate the initial dark current offset value each time an image is captured, thereby compensating for variables such as temperature.
Patent TW-457365-B (TW)
Title: A non-intrusive, on-the-fly (OTF) temperature measurement and monitoring system
Inventor: DAS ASHOK
IPC: B01J3/00
Filed: 2000-02-14
Granted: 2001-10-01
Abstract: The present invention provides an apparatus and method for measuring the temperature of a moving radiant object. A probe, such as a pyrometer, is disposed in an opening of a vacuum chamber adjacent a radiation transparent window. The probe defines an optical path which intercepts the radiant object entering or exiting a processing chamber. The radiant object is moved through the optical path and emits electromagnetic waves. The electromagnetic waves are collected by the probe and transmitted to a signal processing unit where the waves are detected and converted to a temperature reading. If desired, the accumulated data may then be used to generate a cooling curve representing the thermal effects experienced by the radiant object. Extrapolation or correlation methods may be used to extend the cooling curve to points in time prior to or after the data collected by the probe.