Patent GB-1311183-A (GB)
Title: Data process system with priority-dependent programme inter ruption
IPC: G06F13/26
Filed: 1970-04-08
Abstract: 1311183 Data processing HOLLANDSE SIGNAALAPPARATEN NV 8 April 1970 [9 April 1969] 16746/70 Heading G4A A data processing system includes a central processor 01-01, and a memory 01-02 both connected to a multiplexor 01-03 to which several I/O peripherals 01-04 are connected via an I/O control unit 01-05 which is arranged to control data transfers between the peripherals and the memory and the selection and priority dependent interruption of programs in the central processor in response to either instructions from the central processor or completed data transfers. If data transfer from a peripheral is required the request signal and an identification of the peripheral concerned are written in code word address register 01-09. The contents of 01-09 are fed to memory address register 01-28 via effective address register 01-10 and a code word is read from memory into a first code word register 01-06, the code word specifying the memory address into which the data to be transferred should be read. A fixed time after the accessing of the first code word a second code word is read in the same way into a second code and word register 01-07, the code word specifying the end address of a memory block assigned to the incoming data. The first code word is continually updated as transfer proceeds and the transfer is terminated when the contents of 01-06 and 01-07 are the same which is indicated by comparator 01-23. The first control word also specifies the instruction to be executed following the transfer and the priority level of the program required by the transferred data. The priority level of the required program supplied by the first control word is fed to priority circuit 01-22 and there compared with the contents of the priority register 01-12 which indicate the priority of the current program running on the CPU. A program interrupt is then initiated if the central processor indicates that it may be interrupted, if the data transfer is complete, and if the required program has a priority greater than that of the current program. A fixed address (called the key address) in memory indicates how the current program started and contains the address of the code word corresponding to this program. When an interrupt is indicated this code word is accessed and is lodged in first auxiliary memory 01-17 at a location determined by its priority level. The address of the code word associated with the interrupting program is then accessed from memory and loaded into the key address in memory. Interrupt register 01-13, which has one bit per priority level, is then loaded with a bit indicating the priority of the interrupted program. A "save program" is then run to save data relating to the point at which the interrupted program was broken off and to provide the central processor with the address of the first instruction of the interrupting program. The priority of the interrupting program is loaded in 01-12 and the I/O control unit then shuts down. If, after the termination of a data transfer, the central processor indicates that it may not be interrupted or the priority of the "interrupting" program is less than that of the current program then the interruption is postponed and the would-be interrupting program queued. The postponement is indicated in a second auxiliary memory 01-18 at a location depending on the priority of the postponed program. The priority level indicated by the first code word associated with the program to be postponed is fed to waiting list address register 01-11 and the contents of 01-11 access a word from memory which is fed to first code word register 01-06 which then indicates an address in auxiliary memory 01-18 at which a code word specifying the start address in main memory of the postponed program is then stored. Waiting list register 01-14 which includes one bit position for each priority level is then loaded with an indication of the priority level of the postponed program. Subsequently when the central processor indicates that it may be interrupted the I/O control unit may initiate an interruption for its most urgent postponed program. The data relating to the current program is removed from the memory key address and stored in the first auxiliary memory 01-17 as above. The code word associated with the most urgent postponed program is then accessed from the second auxiliary memory 01-18, in accordance with the contents of register 01-11 which specify the code word address of the most urgent program, and loaded into the first code wore register 01-06. The contents of 01-06 specify the address of a code word which is accessed and loaded in the key address in memory. The interrupt registers 01-12 and 01-13 are then loaded according to the priorities of the interrupting and the interrupted programs. Where several programs of the same priority have been postponed the oldest program is selected. The input/output control unit may select the most urgent postponed or interrupted program for running on the central processor when so instructed by the central processor.