Patent GB-1486248-A (GB)
Title: Secondary storage facilities for digital data processing systems
IPC: G06F3/06
Filed: 1974-12-20
Abstract: 1486248 Secondary storage facilities DIGITAL EQUIPMENT CORP 20 Dec 1974 Divided out of 1486247 7017/77 Heading G4A In a digital data processing system, one or more drives, e.g. a disc, drum or tape drive (Fig. 7) is coupled to a controller (Fig. 6) to form a secondary storage facility, the controller transmitting and receiving address signals, asynchronous control signals and control information signals over an asynchronous data path and also transmitting and receiving data and synchronous control signals over a synchronous data path, data being stored in the drive and also control information being stored in the drive in registers 140-142, 144-148, one or more of these registers being selected in response to the asynchronous control signals by means of a decoder 180. The synchronous data path carries synchronizing signals derived from sensing the index marks on the moving drive medium, and includes a store 123 for temporarily storing the data being transferred. The data is preferably transferred in the form of words, a word count register 136 in the controller holding preferably in twos-complement form the number of data words to be transferred between the drive and the controller and overflowing when the transfer is complete. An address register 137 holds the address of the coresponding memory location in a central processor of the data processing system and is successively incremented or otherwise altered as data transfer takes place. Transfer of data is initiated by a first synchronous control signal from the controller, successive data transfers over the synchronous data path taking place in response to second synchronous control signals transmitted from the drive to the controller by a timing unit 181. Transfers of data and control information signals over the respective synchronous and asynchronous data paths are each parity-checked using an accompanying parity bit and checking circuits 274, 183. A device selector control signal DS fed to a device selector decoder 177 is compared with the identifying number of the drive held in a circuit 176; if the comparison is satisfied that drive is selected. If the signal DS fails to select any of the drives, an error condition is set in the register 145 which constitutes one bit position of an attention summary register located in the controller, there being one bit position for each drive, an error signal also being sent to the controller on a wire 94 as an ATTN signal which usually interrupts the central processor. A register selector signal RS fed to the decoder 180 also results in an error condition being set if no register is selected in the selected drive. A signal DEM sent from the controller to the drive initiates the transfer of control information, the drive responding with a signal TRA which indicates receipt of the signal DEM or availability of status information. Signals CTOD and INIT respectively indicate the direction of data transfer and a requirement of resetting the drive. Write-checking of data written into the drive is performed by means of an EXOR circuit (298), Fig. 5 (not shown) which compares the data written into the drive with data stored in the data processing system and generates an error signal if the comparison is not satisfied. The Specification describes the transfers over the synchronous and asynchronous data paths in some detail and includes particular assignments of the control information storage registers. Detailed logic and timing circuitry of the controller is given in Figs. 20A, 20B (not shown). The parent Specification, from which this Specification is divided and Specification 1,486,249, which is also divided from the Parent Specification, respectively claim the drive and the controller, and are referred to.