Patent GB-944923-A (GB)
Title: Improvements in memory elements
IPC: H03K3/35
Filed: 1960-02-24
Abstract: 944,923. Semi-conductor bi-stable circuits. SHOCKLEY TRANSISTOR CORPORATION. Feb. 24, 1960 [March 2, 1959], No. 6536/60. Heading H3T. [Also in Division H1] A memory element comprises a first and second means connected in series, the first means having a high impedance for current therethrough less than a value I 1  and low impedance for currents greater than I 1  and the second means having positive differential resistance for a range of current therethrough larger than I 1  and low resistance (positive or negative) for currents exceeding this range. The result is a voltage-current characteristic as shown in Fig. 9. Fig. 1 shows an array of memory elements, one at each intersection of a set of vertical wires 22 and of horizontal wires 24. Normally each element is biased by a "waiting " voltage " w " and may be in either a high conducting " ON " or low conducting " OFF " state. A voltage of " w + 2S " will switch an element from the OFF to the ON state, and by applying " w + S " to one vertical wire and "- s " to one horizontal wire, one selected element may be subjected to the necessary switching voltage " w + 2S." Similarly switching OFF may be accomplished by subjecting an element to a voltage equal to " w - 2e." Reading out may be accomplished by subjecting elements to a voltage equal to " w + 2r " whereby an ON element will show a large increase in current while an OFF element shows only a small increase. Any number of elements may be ON at the same time. Fig. 9 shows the characteristic of suitable elements and the relative values of the applied switching (w + 25), erasing (w - 2e) and reading (w + 25) voltages which must be above Vs below VH and above Vr but below Vs respectively, the latter referring to the points on the curve. The arrangement also requires that w + r and w + s must each be less than Vr, and that w - e must be greater than VH. The characteristic of Fig. 9 results from the combination (Fig. 6) of a bi-stable 4-layer diode 32 in series with a parallel connection of a resistor 33 and an avalanche diode 34. In the OFF condition diode 32 is in its low conducting state; as the applied voltage increases the arrangement switches to the ON condition where diode 32 breaks down to its high conducting state while current is restrained by resistor 33, diode 34 being in its low conducting state. If the current is further increased (i.e. by application of the reading voltage w + 2r) the voltage drop across resistor 33 causes avalanche diode 34 to break down so that the element passes greatly increased current at the VR level on the characteristic. Excessive current in this condition may be prevented by employing a short reading pulse, or a series resistor or a capacitor in the supply circuit. Fig. 11 shows an equivalent structure in which the 4-layer diode is mounted on a block of P-type material having a thin surface N-layer which provides the avalanche diode while the thin N-layer contacts the same base electrode as the P-body to form the equivalent of resistor 33. A further alternative (Fig. 13, not shown) consists of a 5 layer body, the bottom PN junction having a high density of recombination centres so that it has a high reverse current sufficient to provide the holding current for the upper 4-layer diode portion ; after saturation current of the bottom PN junction is reached its resistance increases until avalanche occurs when its resistance falls to a low value. In another embodiment (Fig. 15, not shown) the avalanche diode and resistor are replaced by an arrangement working on the field effect transistor principle. A slightly different form of characteristic is provided by an arrangement (Fig. 16, not shown) in which the resistor and avalanche diode are replaced by a field effect current limiter and a second 4-layer bi-stable diode or a 3-layer diode. A similar arrangement involves a 6-layer device as shown in Fig. 20, the upper 4 layers constituting a 4-layer bi-stable diode, and the lower 3 layers a 3-layer diode which, by its large area, can provide an OFF condition saturation current sufficient to satisfy the " holding " current of the upper 4-layer diode. Instead of the large area, the effect may be achieved by having a large density of recombination centres produced for example by diffusion or ion bombardment. Fig. 19 shows a further arrangement in which a characteristic having a three voltage maxima (Fig. 20) is provided by having an additional parallel combination of a current limiter L 2  and 4-layer diode 90 ; in this arrangement the limiting current of limiter L 1  is greater than the holding current of 4-layer diode 88 and the normal voltage across L 1  is less than the breakdown voltage of the parallel 4-layer diode 89. Moreover the limiting current of L 2  is larger than the holding current of either of diodes 88, 89 and its voltage less than the breakdown voltage of 4-layer diode 90. The load line 94 is arranged to cut the characteristic to provide 4 stable operating points at 95, 96, 97 and 98. When the current from generator is greater than that corresponding to one of these points the element shifts to the next operating point; battery 91 supplies the holding current for any position.