Patent GB-1027303-A (GB)
Title: Radio-navigation system
IPC: G01S5/14
Filed: 1962-12-03
Abstract: 1,027,303. Radio position finding. SOC. D' ETUDES & D'APPLICATION DES TECHNIQUES NOUVELLES " NEO-TEC." Dec. 3, 1962 [Dec. 9, 1961], No. 45633/62. Heading H4D. A radio position finding system comprises a main transmitting station A, Fig. 1 (not shown), and at least two auxiliary transmitting stations B and C, providing at a receiving station R measurements of the distances between the receiving station R and each of the transmitters. Each transmitting station includes a primary clock in absolute synchronism with each other and each auxiliary transmitting station also includes a secondary clock delayed with respect to its primary clock by the known propagation time between the auxiliary transmitting station and the main transmitting station. The receiving station comprises a secondary clock for each transmitting station synchronized with signals produced by the primary clocks on the respective transmitting stations, and a primary clock, to provide, by reference to the differences between the primary clock and the secondary clocks at least three distance measurements and three resulting receiving positions, differences between the said positions producing a signal correcting the receiver primary clock to bring the said differences to zero. Main transmitting station A.-Fig. 2 and Figs. 3, 4 and 5 (not shown). This comprises a crystal controlled oscillator 2 feeding a signal of frequency f 1  (1,800 kc/s.) to a primary clock 1 which produces phase interlocked signals at frequencies of f 1 , f 2  = f 1  (1+1/6) and f s = f 1  (1 + 1/36) on lines 3, 4 and 5 respectively for feeding to an electronic switch 6. Each transmitting station is assigned to a particular 1/100th of a second of the one-second transmission cycle and each of the three signals f 1 , f 2  and f s  are transmitted for 10-9 seconds at 10-3 second intervals. The 1/100th second assignment at the 10-3 second spacing of the signals is produced in the switch 6, whilst the 10-4 second width is produced in a sampler 7, the whole operation being under the control of signals produced by the primary clock 1 and processed in a programming means 8. Primary clock, Fig. 3 (not shown).-This comprises an oscillator 12 producing the signal f 2  on line 4. Part of the output of oscillator 12 is mixed in mixer 13 with the signal f 1  from oscillator 2 to produce a difference frequency signal f 2 -f 1  = f<SP>1</SP>/ 6  which is then frequency multiplied six times at 14 and compared in phase with the signal from oscillator 2 in discriminators 15, to produce an output voltage which controls the oscillator 12 to bring the signals from the two oscillators 2 and 12 into a phase locked relationship. A phase shift can be applied to the oscillator 12 in steps of one cycle by an adjusting arrangement 16, comprising (Fig. 4, not shown) two capacitors 36 and 37 able to feed their predetermined positive or negative changes to the oscillator 12 at the change-over of switches 38 and 41. An oscillator 17 produces the signal f 3  and is frequency controlled in the same manner as oscillator 12 such that signals f 1 , f 2  and f 3  are phase interlocked. In addition, the difference frequency signal f 3 -f 1  =#1/36 =50 kc/s. is tapped off for use in the programming means 8. A third oscillator 22 produces a 1 kc/s. train of pulses and is phase locked with the rest of the clock system by means of frequency amplitude 23 and phase discriminator 24. The 1 kc/s. pulse train is tapped off directly and is also fed to three series connected decode counters 26, 27 and 28. Counter 26 produces a hundred pulses a second with width of 10<SP>-3</SP> second from each of its ten outputs whilst the corresponding statistics for the outputs of contents 27 and 28 are ten pulses a second, 10<SP>-2</SP> second width, and one pulse per second, 10<SP>-1</SP> second width, respectively. Programming means and electronic switch, Fig. 5 (not shown).-The programming means 8 comprises five AND gates 59, 61, 62, 63 and 64. Signals from selected tapping points on the decade counters 27 and 28 are fed to AND gate 61 to produce a pulse train output comprising one pulse per second of 10<SP>-2</SP> second width in the assigned position of the one transmission cycle. To separate out the transmissions of the three signals f 1 , f 2  and f 3 , three adjacent tapping points on the decode counter 26 are fed to three AND gates 62, 63 and 64, together with the output from gate 61, to produce three pulse train outputs comprising one pulse per second of 10<SP>-2</SP> second width, the pulses of the three outputs being relatively spaced by 10<SP>-3</SP> seconds. The outputs from the gates 62, 63 and 64 are fed respectively AND gates 66, 67 and 68 in the switch 6 together with respective signals f 1 , f 2  and f 3  such that three signals are let out of the switch one after the other in bursts of 10<SP>-3</SP> seconds duration during the particular 1/100th second assigned to the transmitter. The 50 kc/s. signal from mixer 18 (Fig. 3) and the 1 kc/s. pulse train are fed to AND gate 59 to produce a spike output, 10<SP>-4</SP> seconds in width every time a 1 kc/s. pulse coincides with a positive gain zero of the 50 kc/s. signal. The spike output is fed to a sampler 7 together with the output from switch 6 to ensure that the three signals are transmitted as a whole member of cycles starting at a zero point. The resulting signals are amplified at 10 and indicated at 11. Auxiliary transmitter. Fig. 6 (not shown).- The auxiliary transmitter comprises an arrangement singular to the main transmitter comprising f 1  oscillator 70, primary 72, electronic switch 73, programming means 75 and sampler 74, the only difference being in the assigned 1/100th second transmission period. The auxiliary transmitter also comprises a secondary clock 81 and associated switch 82 and programming means 83, fed from oscillator 70 through a phase shifter 80 introducing a delay equal to the propagation time between the main and the auxiliary transmitting station. The assignment period of the secondary clock system is the same as that of the main transmitting station and the three signals f 1 , f 2  and f 3  from the main transmitting station are received at 84 and passed one after the other through filters 89, 90 and 91, and gates 92, 93 and 94, to a phase comparator 87, under the control of pulses on line 33 from programming means 83, where they are compared in phase with the respective signals from switch 82. The comparison is only carried out over the first 10 to 50Á sec. of the received pulse to overcome the influence of sky waves. The average of the phase differences found produces an output voltage which controls the phase shift of a variable phase shifter 71 in the output of the oscillator 70, such as to bring the primary clock 72 into absolute synchronism with that on the main transmitter. By arranging the phase shifter 71 such that the speed of variation of the pulse shift thereby introduced is proportional to the sum of the control voltages from comparator 87 and its time integral, the pulse shifter automatically compensates for drift in the oscillator 70. Receiver, Fig. 7 (not shown).-The receiver comprises three secondary clock arrangements similar to the secondary clock arrangements in the auxiliary transmitters and having assignment periods coincident with that of the primary clock in the respective transmitter. Thus secondary clocks 106, 107 and 108 are synchronized with the signals respectively received from the three transmitters, and are thus delayed with respect to the primary clocks of the respective transmitter by the propagation time from the transmitter to the receiver. The receiver also comprises a primary clock 105 fed with an f 1  oscillator 100 via a variable phase shifter 101, and continuously producing the three signals f 1 , f 2  and f 3  (only one output is shown) for phase comparison at the three frequencies and at frequencies f 2 -f 1  (300 kc/s.), f 5 - f 1  (50 kc/s.) and 1 kc/s. with the output of secondary clock 106 in comparator 130, with the output of secondary clock 107 in comparator 131 and with the output of secondary clock 108 in comparator 132. The three comparators provide unambiguous outputs representative of the three distances between the receiver and the transmitter, which in turn provide three position measurements for the receiver. The comparator outputs are fed to a calculating means 133 which detects any difference in the three positions to produce an output signal to control the phase shifter 101 such that the three positions coincide and are correct and the primary clock 105 is thus in absolute synchronism with the primary clocks in the transmitters. Setting-up procedure.-Before the newly started receiver can be used its primary and secondary clocks must be brought into approximate synchronism. Each transmitter radiates an identification signal at frequency f 4  (different from f 1 , f 2  oÁf 3 ) for the first 1/100th second of the one-second transmission cycle, which signals are received by auxiliary equipment at the receiver, not shown, comprising an oscilloscope. The synchronizing of secondary clock 106 is taken as an example. The oscilloscope commences with a one-second sweep having its start synchronized with the zero time (simultaneous passage through zero of the signals f 1 , f 2 , f 3 ) of the clock 106. The identification signals are fed to the oscilloscope to be displayed thereby and the phase of the secondary clock is adjusted until the three pulses occur at the beginning of the sweep. If it is known that the pulse belongs to the main transmitter this is brought to the beginning of the sweep. The sweep is then changed to 1/100th second and 1/100th second for greater accuracy. The receiver is now switched over to receive f 1  only and the 1/100th second oscilloscope sweep is now started in synchronism with 100 the assignment pulse