Patent GB-1085962-A (GB)
Title: System for reading and writing binary digital data on magnetic cards
IPC: G11B20/18
Filed: 1966-04-28
Abstract: 1,085,962. Reading/recording on magnetic cards. NATIONAL CASH REGISTER CO. April 28, 1966 [May 24, 1965], No. 18618/66. Heading G4M. Each track on the card comprises the following: a preamble made up of a sequence of alternate 1, 0 bits; a pair of like (e.g. 1) sync. bits; a plurality of data words (each having 6 bits and an odd parity bit); an end of data word (all zeros); a sum checkword and a concluding pattern of alternate 1, 0 bits. Write operation.-When the presence of the card at the write head is detected by a photocell (16), Fig. 2 (not shown), a bi-stable circuit (P) is turned on and this causes clock pulses to be supplied to a bi-stable circuit (Q), Fig. 3 (not shown), the output from (Q) providing the 1, 0 sequence for the preamble. A monostable circuit (20) is turned on at the same time as (P), and when it turns off after a preset time, the 1 output of (Q) allows clock pulses to be applied to a counter (42), the latter then interrupting the supply of pulses to (Q) for two clock pulse periods so that the two 1 sync. bits are generated after the preamble. The data words are then fed to the write head via a one word serializing register (40), and when the end of data is indicated by the associated data processor which supplies the data, the output of (40) is blocked for 7 bit periods to record the all zero end of data word. During recording of the data words, each bit is applied to a sum check generator (45) which supplies the check word after the end of data word. Clock pulses are then re-supplied to (Q) to produce the end pattern, the write circuits being reset when the card trailing edge passes the photo-cell (16). Each write operation is accompanied by a read operation detailed below. Read operation.-During reading of the preamble, a capacitor 57 in an AGC circuit 50, Fig. 6, is charged until the output of a full wave rectifier 54 reaches the desired level. Towards the end of the preamble a monostable circuit (19), Fig. 2, turns off and locks the AGC circuit to the attained level of operation. A threshold detector 71 is selected for a read only operation, or a detector 72 having a higher threshold level is selected for a read operation accompanying a write operation, and if the selected threshold is exceeded by the output of 54, gate 63 is enabled to produce a train of clock pulses f r  from the recorded data, the clock pulses being automatically synchronized with the centre of the bit periods. Data pulses are obtained from bi-stable circuit R o , one or other of the complementary outputs of which is selected by U, U<SP>1</SP> according to whether the sync. bits were read as 1 or 0, so as to compensate for different polarities of read/write heads in different apparatus. As a safeguard against errors in reading caused by instability of the card leading edge, the output of R o  is only allowed to pass to the staticizer 91 if 7 1, 0 alternations have been counted following the locking up of AGC circuit 50 during reading of the preamble. Further logic circuits, Fig. 7 (not shown), detect the all zero word, and seven bits after this, i.e. after the sum check word, 28 1, 0 alternations of the concluding pattern are counted before the data processor is informed that the end of data word and the sum check word can be regarded as correctly identified.