Patent GB-892435-A (GB)
Title: Electronic switching system
IPC: H04Q11/04
Filed: 1958-12-01
Abstract: 892,435. Automatic exchange systems. AUTOMATIC ELECTRIC LABORATORIES Inc. Dec. 1, 1958 [Jan. 6, 1958], No. 38687/58. Addition to 840,921. Class 40 (4). [Also in Groups XIX and XL (c)] In a time division multiplex exchange a subscriber's line circuit is connected to a link circuit over a multiplex highway which when gated to the line circuit and to the link circuit reverses a voltage sustained by a Zener diode between its ends until a predetermined reverse voltage is reached after which the voltage remains constant for the remainder of the channel time period, the time in the channel period at which the predetermined reverse voltage is reached being determined by signal modulation. The exchange described is a fully transistorized 10-line exchange in which each subscriber has a fixed position in the multiplex cycle. In setting-up a call a pre-allotted one of three link circuits is seized and controls gates between the link circuit and the multiplex highway in the time positions of the calling and called subscribers. Clock pulse source.-As shown in Fig. 18, a transistor oscillator 1801 controlled by a crystal 1802 has a frequency of 1 megacycle and by virtue of a feed-back path causes transistor 1806 to conduct during alternate half-cycles to produce the pulses CLM shown in Fig. 21, the pulses being of 0.5 Ás duration and occurring every 2 Ás. The pulses CLM are delayed 0.2 Ás in 1807 to produce pulses CLK which are delayed further in 1810 to produce pulses CLP and CLN spaced by further intervals of 0.2 Ás. The pulses CLN pass over phase inverter 1820 and, by causing transistor 1805 to conduct and suffer hole storage, clamp transistor 1806 thereby suppressing alternate half-cycles of oscillator 1801. The pulses CLN also produce pulses CP-1A, CP-1B and CP-1C by switching transistors 1817 and 1820. The pulses CLM and CLK are combined to switch transistor 1808 and produce pulse CP-4, 0.7 Ás long. The pulses CLP over transistors 1815 and 1816 produce the pulses CP-1F and CP-1E of opposite polarity. Pulse-distributer.-The pulses CP-1C drive the ring-of-five counter shown in Fig. 17, each stage of which comprises a surface barrier transistor such as 1706, followed by a slave transistor such as 1701. All the transistors 1706 conduct except one which is marked over a rectifier matrix by all other stages. Application of a CP-1C pulse to this matrix causes the marked non-conducting transistor to conduct and switches-off the next stage. With a transistor 1706 switch-off its slave 1701 is also switched-off to apply marks to an odd and an even numbered one of the output leads 0 to 9 shown in Fig. 16. The pulses CP-1C also trigger the bi-stable pair 1601 and 1602 so as to gate the outputs of the ring-of-five counter alternately to the odd and even numbered leads 0 to 9 which are consequently marked in sequence with 2 Ás pulses DP-0 to DP-9 characterizing the ten subscribers. Subscriber calls and seizes pre-allotted link circuit.-The connection of subscriber A with the time position of pulses DP-1, to subscriber B with the time position of pulses DP-2, is described with reference to Figs. 2, 3, 4A and 4B. The multiplex highway ŒL is connected in common to all subscribers' line circuits and to three link circuits, each of which has a linefinder, Fig. 4A, and a connector, Fig. 4B. When the second link circuit is busy its sequence switch, Fig. 4B, is off normal and marks lead ON-2 so that its associated stage in a three stage transistor ring counter, which comprises the allotter (see Group XIX), does not have a rest position. Should lead ON-2 not have a mark and leads ON-1, ON-3 from the other two links have busy marks, the ring counter will step over the stages with busy marks but come to rest on the second stage which is not marked busy. When at rest, the counter returns a mark over lead AL-2 which over OR gate G-1 primes AND gate IG-1, Fig. 4A, in the line-finder and also primes gate G2. Scanning pulses, from a magneto-strictive delay line circulating pulses with a 22 Ás delay, are applied on lead DY6B to gate G-2 the output of which injects a pulse into magnetostrictive delay line DY-2 with a delay of 20 Ás or one multiplex cycle (see Group XL (c)). The input is synchronized by a pulse CP-4. The output of DY-2, shaped and synchronized by pulses CP-1F, appears at terminal B and over gate G-3 and lead S is applied to gates comprised by diodes 207, 208, 209, in the line circuits, Fig. 2. When the output of DY-2 coincides with a DP-1 pulse, which happens once every ten multiplex cycles, a pulse is gated to the lead C from the line circuits provided the subscriber A is calling and has closed his loop circuit so that a potential appears across resistor 202. The pulse on lead C over transistor 301 passes inhibition gate IG-1, amplifier A1, and triggers bi-stable circuit FF-1 from a 0 to a 1 output. Bi-stable circuit FF-2 is also triggered from 0 to 1 and over gate G-9, held open by the normal output of the sequence switch on lead N, triggers bi-stable circuit FF-3 from 0 to 1. The output of FF-3 activates a sequence switch driver comprising a transistor blocking oscillator (see Group XL (c)), to produce single pulses on terminals B and C. From terminal C the pulse resets FF-3 to 0 to remove activation from the driver, while from B the pulse steps the sequence switch which comprises a five-stage transistor ring counter (see Group XIX). Output from the sequence switch is removed from lead N and switched to ON-2 for the remainder of the call and to lead UA at this point of time. The mark on ON-2 is sent to the allotter which is released from the seized link and steps in search of the next idle one. Gate IG-1 is held open over G-1 as, although the allotter removes output on lead AL-2 to G-1, a mark now appears on ON-2 which also primes gate G-4 so that the output of delay line DY-2 is fed back to its input and circulates in the time position of DP-1. So long as the delay line DY-2 circulates a pulse a potential appears on lead HOLD and is applied to terminals L1 of the bi-stable circuits FF-1 and FF-2 which in consequence remain in their 1 states regardless of set 0 inputs. With FF-1 in its 1 state gate G-5 is opened by pulses from DY-2 to open transmission gate TG-1 in the time position of the subscriber A. Over gate G-6, DP-1 pulses from DY-2 go to lead BYM-2 to inhibit the gates IG-1 in the other link circuits and prevent seizure of this channel time position in these links. Pulses on lead BYM-2 in common with similar pulses from other links on leads BYM-1 and BYM-3 are applied over amplifier 307 to lead BYT, Fig. 3, across 4A to 4B, to gate G-17 for busy testing; but as there is no mark on lead BT from the sequence switch nothing is done at this stage. The output of circuit FF-1 in its 1 state opens gate G-15, Fig. 4B, in response to pulses at time DP-0; G-15 being held open for a period after removal of the mark on lead N by gate G-8. Output from G-15 feeds a pulse at time DP-0 into magneto-strictive delay line DY-5 (Fig. 15, not shown) the pulse being circulated over gate G-13 held open by FF-4 and the mark on lead ON-2. As there is a mark on lead UA from the sequence switch, a gate SG-1, Fig. 4A, is opened to admit dial tone on lead DLT to a negative impedance repeater from which it is gated to subscriber A over gate TG-1. For so long as the subscriber's loop is closed pulses at time DP-1 circulate in DY-2 and over lead S go to the line circuit and are returned over lead C. Subscriber dials.-When the subscriber's loop is broken at the first impulse the pulses on lead C cease and no longer inhibit gate IG-2, Fig. 4A. Bi-stable circuit FF-2 is consequently switched to its 0 state and over gate IG-3 and differentiating circuit DF-1 switches FF-4 to its 1 state. With a 1 output from FF-4 gate G-14 is open to a DP-0 pulse, circulating in delay line DY-5 while the circulating path over gate G-13 is closed. Over gate G-14 the DP-0 pulse is fed back with a 2 Ás delay in circuit DY-4 so that the DP-0 pulse is shifted one channel time period and becomes a DP-1 pulse. The output of DY-4 is applied to FF-4 to switch it back to its 0 state to prevent the circulating pulse being delayed more than once in the circuit DY-4 as it recirculates in DY-5. When the subscriber's loop closes at the end of the first impulse pulses are again returned from the line circuit on lead C and these inhibit gate 1G-2 while resetting FF-2 to its 1 state. In response to the second dialled impulse FF-2 is again set to 0 and the connector circuit, Fig. 4B, responds to delay the pulse circulating in DY-5 by a further channel time period of 2 Ás so that it recirculates as a DP-2 pulse. As subscriber B occupies the time position of DP-2 no further impulses are required. During dialling, whenever FF-2 is switched FF-3 follows suit but the sequence switch driver is slow to respond and remains undisturbed until the end of the digit train when it steps the sequence switch to its third position to mark lead BT. Busy tests.-As explained above pulses in position DP-1 circulate in delay line DY-2 and are applied over lead BYT to gate G-17, Fig. 4B. The mark on lead BT primes the gate G-17 and if subscriber B is busy in his channel time DP-2 over one of the other link circuits pulses in position DP-2 are applied to G-17 over lead BYT from BYM1 or BYM3, Fig. 3, and will coincide with the pulses circulating in delay line DY-5, as set by the dialled digit, producing an output from G-17. This triggers bi-stable circuit FF-5 to its 1 state and puts ground on its 0 output lead to inhibit the sequence switch driver. Over gate G-18, which is primed by lead BT, the delay line DY-5 is inhibited. Gate SG-2, Fig. 4A, is marked from FF-5 and by lead BT so that busy tone on lead BST is admitted to the calling subscriber over gate TG-1. Busy tone only becomes available when the sequence switch steps to mark lead BT. If the called subscriber is idle FF-5 remain