Patent GB-1010631-A (GB)
Title: Improvements in or relating to electrical signalling systems
Inventor: ALDRIDGE EDWARD ERNEST
IPC: H04J3/00
Filed: 1961-06-30
Abstract: 1,010,631. Multiple pulse code signalling. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. July 2, 1962 [June 30, 1961], No. 23761/61. Heading H4L. In an electrical signalling arrangement a plurality of individual systems operating at the same bit speed are converted into a single time division multiplex system operating at a higher bit speed by means of a plurality of stages comprising tapped delay lines, the number of delay lines being different at each stage and the delay lines at the different stages being gated by pulses of the appropriate different widths and harmonically related repetition frequencies. The arrangement avoids the use of long delay lines. As shown in Fig. 4 (Prov.) there are abc incoming digital channels, e.g. pulse code modu-   lation systems, each operating at X/abc bits per second where X is the bit speed over the common output lead and a, b, c are small integers. These channels are divided into ab groups each comprising c channels, one group only being indicated as applied to the respective c channel gates of a multiple gate GIc co-operating with c taps on a delay line DL1. The remainder of the ab groups are similarly coupled via further multiple gates (not shown) to respective taps on similar delay lines. Gate pulses of a duration not greater than ab/X and     repetition frequency X/abc are derived from an   oscillator O via a pulse former PF1 and applied simultaneously to the c individual gates of each multiple gate GIC, each section of the delay lines DL1 producing a delay of ab/X seconds so that   sequential output pulses are obtained from each delay line DL 1 giving ab channels each operating   at X/ab bits per second. The output pulses are regenerated and retimed at R1 controlled by timing pulses derived from the oscillator O, and subdivided into a groups of b channels each. Each of these b channels, each carrying c timespaced channels, is applied via a multiple gate GIb, comprising b channel gates, to a correspondingly tapped delay line DL2 the gates being controlled by a pulse having a duration not greater than a/X and a repetition frequency   X/ab. The output of each delay line DL2 consists of a time division multiplex channel operating at X/a bits per second which is applied via a   respective regenerator R2 to a corresponding gate of a multiple gate GIa. The gates are controlled by pulses of duration not greater than 1 X - and repetition frequency - and co-operate X a with taps on a delay line DL3 to provide a single time division multiplex output signal operating at X bits per second. Digital channels operating at different bit rates may be combined by injecting them at the appropriate multiplexing point. At the receiving end the converse takes place, Fig. 5 (not shown), a timing wave of X c/s. being derived from the received signal and suitable gating pulses obtained by frequency division. Phase shifting networks controlled by logic circuits for correcting loss of synchronism are included. The synchronizing signal may consist of a series of " ones " appearing on a particular channel, each channel being provided with an integrating circuit for detecting its presence by the occurrence of D.C. In an example given where a=2, b=5, c=10, the incoming signals at the receiver are first combined into a groups of bc channels each and if a D.C. appears on any of the groups not containing the synchronizing channel it is used to change the phase of the first frequency divider in steps of 2#/a, i.e. 180 degrees, until an output   appears only in the group containing the synchronizing channel. This group is further subdivided into b sub-groups each containing c channels and D.C. output on any sub-group not containing the synchronizing channel changes the phase of the corresponding frequency divider in steps of 2#/b, i.e. 72 degrees until the correct   sub-group is reached. Finally, a D.C. signal on any of the C - 1 channels which are not the synchronizing channel in this sub-group will alter the phase of the appropriate frequency divider in steps of 2#/c, i.e. 36 degrees, until   synchronism is achieved. Logic circuits for carrying out this process are described, Figs. 9 and 10 (not shown).