Patent SG-11201806395S-A (SG)
Title: Processor with reconfigurable algorithmic pipelined core and algorithmic matching pipelined compiler
Inventor: CATILLER ROBERT
IPC: G06F19/00
Filed: 2017-01-26
Abstract: DigitalSignal Processor (DSP) Logical Decision Processor (LDP) 111 FIG. 6 Matrix Bus Switch (MBS) 112 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (10) International Publication Number (43) International Publication Date WO 2017/132385 Al 3 August 2017 (03.08.2017) WIPO I PCT 111111111111110111011111111111010111110111111110111111110111H1 111111111111110111111 (51) International Patent Classification: GOOF 7/57 (2006.01) GOOF 19/00 (2011.01) GOOF 9 / 4 5 (2006.01) (21) International Application Number: PCT/US2017/015143 (22) International Filing Date: 26 January 2017 (26.01.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/287,265 26 January 2016 (26.01.2016) US (71) Applicant: ICAT LLC [US/US]; 683 Ohio Street, Terre Haute, Indiana 47807-3525 (US). (72) Inventor: CATILLER, Robert; 683 Ohio Street, Terre Haute, Indiana 47807-3525 (US). (74) Agent: PARADIES, Christopher; Paradies Law P.A., P.O. Box 20393, Tampa, Florida 33622 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). [Continued on next page] (54) Title: PROCESSOR WITH RECONFIGURABLE ALGORITHMIC PIPELINED CORE AND ALGORITHMIC MATCHING PIPELINED COMPILER W O 20 17 / 13 2385 Al (57) : An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a sys- tem. The reusable algorithmic pipelined core is a reconfig- urable processing core with a pipelined structure compris- ing a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfig- urable, programmable circuit routes data and results from one core to another core and/or 10 controller and/or inter- rupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm. WO 2017/132385 Al MIDEDIMOMONIIMMEMIIIIMOIllOMMOMOVOIMIE Published: — with international search report (Art. 21(3))