Patent GB-1461601-A (GB)
Title: Electronic regulated dc power supply
IPC: H02M7/525
Filed: 1974-01-02
Abstract: 1461601 Automatic voltage control HONEYWELL INFORMATION SYSTEMS Inc 2 Jan 1974 [2 Jan 1973] 93/74 Heading G3R [Also in Division H2]  A D.C.-D.C. converter, Fig. 2, comprises two thyristors 54, 56 arranged to be fired alternately to produce a substantially sinusoidal voltage from a D.C. supply, rectifiers 76, 77 arranged to produce a D.C. output, a control circuit including a pulse generator for firing the thyristors 54, 56 at a rate dependent on the output voltage so as to regulate the D.C. output, fault detection circuits for detecting faults in the D.C. regulated output comprising over current, over-voltage and under-voltage and inhibiting the firing of the thyristors 54, 56 under these conditions and a delay circuit for preventing operation of the under-voltage protection circuit when starting. The Specification describes two trains each comprising a single or three-phase rectifier 11, the inputs being connected in series or parallel across A.C. mains 10, each rectifier 11 feeding an inverter of the form shown in Fig. 2 and each having a rectified output which is connected to a common load. The output of rectifier 11 is fed via an inrush-current limiter 100 to a storage capacitor 51 feeding the thyristors 54, 56 in a series arrangement of high Q circuits 52, 53, 60, 61. The thyristors 54, 56 are turned on alternately giving a sine wave across transformers 72, 73, the outputs of which are rectified at 76, 77, 81 to provide main D.C. output and auxuliary supply for the control circuit. Automatic voltage control. As shown in Fig. 3 the main D.C. output at F is fed to an amplifier 210 where it is compared with a reference Vr, the resulting error controlling a voltage to frequency converter 230. Monostable 228 provides pulses the frequency of which is indicative of the required D.C. output and which are gated at 234, 235 to the respective thyristors 54, 56 (Fig. 2) and corresponding thyristors in the other train. The gates 234, 235 are enabled by a counter 233, operating on the output of the voltage to frequency converter 230 so that the thyristors are triggered in sequence.  Fault detection. The main D.C. load current conductor is passed through a saturable toroidal core 400 having a winding 403 energized with pulsed D.C. from a self-oscillating circuit 22 and feeding transistor 30. The core is arranged to be saturated at normal low current level but, in the event of overcurrent, pulses are induced in a further winding 402 and a result in a signal being fed via amplifier 23 to junction T33. Amplifiers 20, 21 respectively provide a fault signal at T33 in the event of undervoltage and over-voltage. A thermostat 370 provides an over-temperature fault signal. Monostable M10 provides a further fault signal if oscillator 22 should fail. Any of these faults is indicated by a LED 302 and feeds a signal via amplifier 270, 280 to inhibit gates 234 ... 235 and thus prevent triggering of the thyristors. Starting. A positive pulse T23 initially enables gates 234 .... 235. A circuit 500 temporarily inhibits the under-voltage circuit 20 during starting conditions. The circuit is reset after a fault is cleared by pulsing T25.