baber/WOPTO huggingface dataset:
Patent TW-540029-B (TW)
Title: Energy efficient grey scale driver for electroluminescent displays
Inventor: CHENG CHUN-FAI
IPC: G09G3/20
Filed: 2001-12-28
Granted: 2003-07-01
Abstract: A circuit and method are provided of driving a display panel requiring gray scale control wherein the voltage applied to a row of pixels is equal to the sum of voltages of opposite sign with respect to ground applied respectively to the row electrode and column electrodes whose intersection with the row defines the pixels. The pixels have a capacitance that may be voltage dependent such that energy is stored in the pixels when a voltage is applied across them. The driving circuit incorporates a resonant circuit that is able to efficiently recover capacitive energy stored on the row of pixels and transfer it to another row of pixels as the rows are addressed by the sequential application of a voltage on each row. The resonant circuit comprises a step down transformer, a capacitor across the primary winding, either the rows or columns of the display panel connected across the secondary winding and an input voltage and FET switches to drive the resonant circuit synchronous with the timing pulses governing the addressing of the display. The value of the capacitor connected across the transformer primary winding is chosen commensurate with the turns ratio on the transformer and the anticipated range of panel capacitance values to effectively limit variations in the resonance frequency with respect to the frequency of the timing pulses. Limiting the resonance frequency variation in this way maintains high energy recovery efficiency irrespective of random variations in panel capacitance occurring as a result of changes in the displayed image. The improvement of the present invention is an additional secondary winding on the transformer that is connected to a rectifier and DC storage capacitor that is connected in series with the rows or columns of the panel. The additional circuit facilitates clamping of the driver voltage to a constant level irrespective of variations in the load due to the fluctuations in load impedance.
Patent TW-546807-B (TW)
Title: Packaged integrated circuits and methods of producing thereof
Inventor: BADIHI AVNER
IPC: H01L33/62
Filed: 2001-12-31
Granted: 2003-08-11
Abstract: A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
Patent TW-I238296-B (TW)
Title: Developing solution for a photoresist and a method for developing the photoresist
Inventor: IWATA KEIICHI
IPC: G03F7/32
Filed: 2002-01-10
Granted: 2005-08-21
Abstract: Developing solution for a photoresist comprising an alicyclic amine compound and a non-metallic alkali compound is described. The developing solution exhibits excellent wettability and dissolution selectivity to alicyclic compound-based resists. Also, the developing solution does not produce dissolution residues, and it makes it possible to reliably form ultra fine patterns.
Patent TW-I251003-B (TW)
Title: Process aid for melt processable polymers
Inventor: CHAPMAN GEORGE RICHARD JR
IPC: C08J3/00
Filed: 2002-01-22
Granted: 2006-03-11
Abstract: Extrusion processability of non-fluorinated melt-processable polymers is improved by introducing a fluoropolymer process aid by means whereby the weight average particle size of the fluoropolymer is greater than 2 microns as it reaches the extruder die entrance.
Patent TW-583680-B (TW)
Title: Algorithmically programmable memory tester with history FIFO's that aid in ERROR analysis and recovery
Inventor: KRECH ALAN S JR
IPC: G01R31/28
Filed: 2002-01-24
Granted: 2004-04-11
Abstract: The problem is to branch back to an appropriate location within a memory tester test program, and also restore its state of algorithmic control, when an error associated therewith occurs later in time at the DUT (14). Owing to delays in pipelines (24/31, 40, 45, 52) connecting the program execution environment to the DUT and back again (52, 57, 60, 87). These delays allow the program to arbitrarily advance beyond where the stimulus was given. The arbitrary advance makes it difficult to determine the exact circumstances that were associated with the error. A branch based in the error signal can restart section of the test program, but it is likely only a template needing further test algorithm control tester (6) with History FIFO's (91-98, 124-127) whose depths are adjusted to account for the sum of the delays of the pipelines, relative to the location of that History FIFO. When the error flag (90, 99) is generated the desired program location and state information is present at the bottom of an appropriate History FIFO. This is also readily applicable when the test program uses an ALU to generate its own DUT stimuli, as well as to the case when the test program/ALU addresses an intermediate Buffer Memory whose contents are central to the nature of the testing the DUT is to undergo. The first is an ALU History FIFO (91-98), while the second is a Buffer Memory History FIFO (124-127). There can also be ECR History FIFO's. There is a mechanism (84) to track system re-configuration as it occurs and adjust the depths of the various History FIFO's according to resulting pipeline depth. There is a mechanism (86, 98) to freeze the contents of a History FIFO upon the generation of an error. A History FIFO can be extended to allow a branching instruction in the test program to not prematurely respond to an error flag sooner than the pipeline delay needed for that error flag's value to be determined by a cause located within the test program.
Patent TW-579582-B (TW)
Title: Packaging system for die-up connection of a die-down oriented integrated circuit
Inventor: LIM DAVID CHONG SOOK
IPC: H01L23/498
Filed: 2002-02-26
Granted: 2004-03-11
Abstract: A die attach package for connecting a die or chip of die-down orientation to a printed circuit board in a die-up orientation. The package includes a substrate with leads that may be traces terminating in vias or that may be the leads of a lead frame. The traces or the leads of the lead frame are modified such that they pass under the die when the die is attached. The traces or leads are routed under the die such that proper connections are established from the topside of the die to the appropriate mount locations of the printed circuit board. The die is attached to the substrate using a non-electrically-conductive material. This packaging enables a fabricator to make die of one orientation type, die down, and use that die in a die-up package, thereby saving on fabrication costs.
Patent TW-539840-B (TW)
Title: Process and apparatus for separating a gas mixture with emergency operation
Inventor: ZAPP GERHARD
IPC: F25J3/04
Filed: 2002-03-06
Granted: 2003-07-01
Abstract: The process and the apparatus serve for separating a gas mixture in a separation plant. A feed gas (18) is introduced into a compressor system (6, 16) and then into the separation plant. In the event of loss or partial loss of the compressor system (6, 16) of the first feed gas compressor (6), a first auxiliary stream (91, 92) which has approximately the composition of the first product stream or approximately the composition of the feed gas is compressed (78, 89) to at least approximately the first pressure and is recirculated to the separation plant.
Patent TW-I286792-B (TW)
Title: Semiconductor device and method for fabricating the same
Inventor: LEE HI-DEOK
IPC: H01L21/336
Filed: 2002-03-18
Granted: 2007-09-11
Abstract: A method for fabricating a semiconductor device is disclosed. In a high speed device structure consisting of a salicide, in order to fabricate a device having at least two gate oxide structures in the identical chip, an LDD region of a core device region is formed, and an ion implant process for forming the LDD region of an input/output device region having a thick gate oxide and a process for forming a source/drain region at the rim of a field oxide of the core device region having a thin gate oxide are performed at the same time, thereby increasing a depth of a junction region. Thus, the junction leakage current is decreased in the junction region of the peripheral circuit region, and the process is simplified. As a result, a process yield and reliability of the device are improved.
Patent TW-527255-B (TW)
Title: Positioning multifunctional mechanism for supporting tool-holding devices
Inventor: DE BERNARDI FRANCO
IPC: B23Q16/10
Filed: 2002-04-25
Granted: 2003-04-11
Abstract: Multi-functional mechanism for the positioning of devices to hold cutting and/or rotating tools for drilling and/or milling operations, for machine tools, including a table (6) designed to take on operating positions spaced apart angularly, said table (6) supporting said tool-holding devices, a rotating support column (4) for said table (6), a stationary column (3) fixed to the base (1) of a machine tool, motor means (9, 10) to rotate said rotating support column (4) of the table (6) around a predetermined rotation axis (B-B), connection means (15, 19) movable between a first position in which the respective connection means (11) integral with said rotating column (4) and connection means (14) integral with said stationary column (3) are connected to each other, in predetermined operating positions spaced apart angularly, and a position in which said connection means (15, 19) are axially disengaged from said connection means (11, 14). The mechanism also includes a frictional locking member (20) acting on a part (7) integral with said rotating column (4), said locking member (20) locking said rotating column in various angular operating positions even different from those determined by said connection means (15, 19) and connection means (11, 14) as well as a play take-up member (27) acting on said part (7) integral with the rotating column (4), with the interposition of an axial thrust bearing (29), in the opposite direction to the locking direction exerted by said frictional locking member (20), said play take-up member (27) only operating when said rotating column (4) is free to rotate around the stationary column (3).
Patent TW-I233603-B (TW)
Title: Device and method for recording information
Inventor: WEIJENBERGH PAULUS GIJSBERTUS
IPC: G11B20/12
Filed: 2002-07-15
Granted: 2005-06-01
Abstract: A method and device for recording multiple information volumes on a record carrier, usually called multi-session recording, is described. The device has a mapping unit (31) for opening a session by recording intro data comprising a first buffer zone at the beginning of the start zone of the volume, and a session control block (SDCB) in a remaining blank area of the start zone after the buffer zone. The session control block comprises volume data indicative of the status and the contents of the session. The session is closed by recording session control data indicating that the information volume is closed in the remaining blank area, and closure data after the last user information recorded in the data zone for constituting the end zone of the volume. Further the device has a detecting unit (32) for retrieving the session control block from said start zone.
Patent TW-583086-B (TW)
Title: Molded resin, layered object, and processes for producing these
Inventor: MIYAMORI TSUYOSHI
IPC: B32B5/02
Filed: 2002-08-05
Granted: 2004-04-11
Abstract: A molded resin having improved adhesion; the molded resin (1) comprises a resin molding which has raised fibrils on at least part of the surface. The fibrils have a length of 50 mum or longer and a thickness of 10 mum or larger and are present on the molding surface in a number of 100 per cm<2> or larger.
Patent TW-550741-B (TW)
Title: Method for forming a bottle trench
Inventor: TSAI TZU-CHING
IPC: H01L21/334
Filed: 2002-08-20
Granted: 2003-09-01
Abstract: A method for forming a bottle trench in a substrate having a pad structure and trench, comprising the steps of: forming a first isolating layer in the trench; removing a portion of the first isolating layer to a certain depth of the trench; forming a second isolating layer in the trench; removing portions of the second isolating layer on the pad structure and the sidewalls of the trench; forming a etching stop layer in the trench; removing a bottom portion of the etching stop layer; and using the etching stop layer as a mask to remove the remaining of the second isolating layer and the first isolating layer.
Patent TW-581949-B (TW)
Title: Method for making blade server released from position by remote control
Inventor: LI JIUN-LIANG
IPC: G06F15/00
Filed: 2002-10-24
Granted: 2004-04-01
Abstract: The present invention provides a method for making blade server released from jumping out of position by remote control. The method is to connect a plurality of blade servers installed on at least one rack to a network switch, and the network switch is further connected to a computer system at a master site, so that a maintenance manager can issue the commands from the computer system at the master site, and control any one of the blade servers at the remote site through the network switch to make the latch for the blade server installed and positioned on the rack to be released from the rack. Thus, the maintenance manager can rapidly find out the location for the blade server with the released latch, and rapidly proceed the replacement or maintenance operation. Therefore, the present invention is able to not only greatly reduce the time and human resources required by the conventional searching and checking, but also effectively reduce the operation cost of the operator.
Patent TW-565955-B (TW)
Title: Sub-mount for light emitting diode
Inventor: HUANG TENG-HUEI
IPC: H01L33/00
Filed: 2002-10-25
Granted: 2003-12-11
Abstract: A sub-mount for light emitting diode (LED) is disclosed. The sub-mount is a metal substrate, which is coated with a nickel layer and a gold layer. The metal substrate has a slot to divide the metal substrate into two portions. One portion may have a bowel-like reflector formed therein to support a LED chip. After wire bonding and molding with transparent resin to protect the bonding wires[/or wire]. The exposed portions of the metal substrate can provide an excellent oxidation-resist characteristic without further tin or tin-lead deposited process.
Patent TW-I286515-B (TW)
Title: High bulk composite sheets and method for preparing
Inventor: ZAFIROGLU DIMITRI P
IPC: B32B7/028
Filed: 2002-12-20
Granted: 2007-09-11
Abstract: A multi-layer composite sheet comprising a shrinkable layer intermittently bonded a to a gatherable layer with the bonds separated by a specified distance and wherein the shrinkable layer can shrink and at the same time gather the gatherable layer between the bonds. A process for preparing multi-layer composite sheets by intermittently bonding a shrinkable layer to a gatherable layer with the bonds separated by a specified distance and causing the shrinkable layer to shrink while at the same time gathering the gatherable layer between the bonds. Preferably, the shrinkable layer comprises an array of fibers or nonwoven web comprising fibers having latent spiral crimp.
Patent TW-I242032-B (TW)
Title: CMP slurry for metal and method for manufacturing metal line contact plug of semiconductor device using the same
Inventor: AHN KI-CHEOL
IPC: C09K3/00
Filed: 2002-12-31
Granted: 2005-10-21
Abstract: A chemical mechanical polishing (hereinafter, referred to as 'CMP') slurry for metal is disclosed, more specifically, method for manufacturing metal line contact plug of semiconductor device using an acidic CMP slurry for oxide film further comprising an oxidizer and a complexing agent, which polishes a metal, an oxide film and a nitride film at a similar speed, thereby easily separates a metal line contact plug.
Patent TW-I266420-B (TW)
Title: Manufacturing method of thin film transistor array panel for display device
Inventor: YOON JOO-SUN
IPC: G02F1/1345
Filed: 2003-01-02
Granted: 2006-11-11
Abstract: A gate wire including gate lines, gate electrodes, and gate pads and extending in a transverse direction is formed on a substrate. A gate insulating layer is formed thereafter, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. A conductive material is deposited and patterned to form a data wire including data lines intersecting the gate lines, source electrodes, drain electrodes, and data pads. A protective layer made of silicon nitride is deposited on the substrate, and an organic insulating layer made of a photosensitive organic insulating material is coated on the protective layer. The organic insulating layer is patterned to form an unevenness pattern on its surface and first contact holes exposing the protective layer opposite the drain electrodes. Subsequently, the surface of the organic insulating layer is treated using inactive gas such as Ar, and then the protective layer is patterned together with the gate insulating layer by photo etch using a photoresist pattern to form contact holes respectively exposing the drain electrodes, the gate pads, and the data pads. Next, indium-tin-oxide or indium-zinc-oxide is deposited and patterned to form transparent electrodes, subsidiary gate pads, and subsidiary data pads respectively connected to the drain electrodes, the gate pads and the data pads. Finally, a reflective conductive material is deposited and patterned to form reflecting films having respective apertures in the pixel area on the transparent electrodes.
Patent TW-582100-B (TW)
Title: Semiconductor device having a heat spreader exposed from a seal resin
Inventor: HOSOYAMADA SUMIKAZU
IPC: H01L23/433
Filed: 2003-01-24
Granted: 2004-04-01
Abstract: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.
Patent TW-I287053-B (TW)
Title: A process for making stable polytrimethylene terephthalate packages
Inventor: BROWN HOUSTON SLADE
IPC: D01F6/62
Filed: 2003-02-11
Granted: 2007-09-21
Abstract: A process for the production and for the winding of one polyester yarn, preferably multi-filament yarn, which comprises at least 85 weight%, in relation to the total weight of the polyester yarn, of polytrimethylene terephthalate (PTT) wherein said process is characterized in that filaments of said polyester yarn is heat-treated, before it is wound on a bobbin, at a temperature in the range of 70 DEG C to 180 DEG C. The method of accomplishing this is by heating the godets that are used in the spinning part of the process, preferably the last pair of godets, to relax the yarns so that the yarn package will not shrink significantly during storage and/or transportation.
Patent TW-I228944-B (TW)
Title: Self-oscillating electronic discharge lamp ballast with dimming control
Inventor: TAO FENGFENG
IPC: H05B41/38
Filed: 2003-02-19
Granted: 2005-03-01
Abstract: The present invention provides an electronic ballast circuit comprising: an inverter electrically connected to a DC power source, so as to switch the DC power source for outputting an AC power source; a resonant matching circuit comprising an inductor, a capacitor and a transformer, so as to form a resonant circuit. The current of the resonant circuit is fed back to drive the gate terminal of the inverter, and the inverter is electrically connected to a load through the resonant matching circuit.
Patent TW-I233093-B (TW)
Title: Floating-type clamper mechanism
Inventor: LIN JUI-CHIANG
IPC: G11B17/028
Filed: 2003-05-21
Granted: 2005-05-21
Abstract: The present invention is directed to a floating-type clamper mechanism for use in an optical disk reading device. The present invention is different to the fixed-type clamper mechanism which needs higher altitude or the movable-type clamper mechanism which needs the metal member to supply the adsorption of clamper. So it can reduce the cost and the space effectively.
Patent TW-I311414-B (TW)
Inventor: CHEN CHIH WEI
IPC: H04L29/08
Filed: 2003-05-26
Granted: 2009-06-21
Abstract: A server management method and system is disclosed for allowing a user to control scheduling of a server via a remote terminal device. A management program module is installed in the server to receive and execute management commands. The management program module transmits a management command to an operating and/or control mechanism of the server according to management information sent by the user from the remote terminal device and through a network communication system. Thereby, the operating and/or control mechanism can control and manage the server according to the received management command. By the above server management process and system, the user can remotely manage and use the server, thereby increasing operating efficiency.
Patent TW-591799-B (TW)
Title: High-performance hetero-junction bipolar transistor
Inventor: WANG CHENG-HAU
IPC: H01L29/737
Filed: 2003-05-30
Granted: 2004-06-11
Abstract: The present invention relates to a hetero-junction bipolar transistor, especially a high-performance bipolar transistor having dual hetero-junctions. The main structure of the present invention consists of a gallium arsenide substrate, a collector layer, a base layer, and an emitter layer. The collector layer comprises multiple gallium arsenide (GaAs) sub-layers of different doping concentrations. The base layer contains content-incremental indium gallium arsenide nitrides (InGaAsN) and the emitter layer comprises multiple sub-layers. The base layer allows the content of indium to decrease progressively by way of gradual content from the collector layer towards the emitter layer. Besides, based on a lattice equilibrium value, the base layer not only can tilt the potential curve of the conductive band in the base layer to generate a quasi-electrostatic accelerating carrier, but also can balance the stress generated by the change of content. Thus, the component performance is further improved and the component manufacturing becomes easier.
Patent TW-I233658-B (TW)
Title: Electrostatic absorbing apparatus
Inventor: MIZUNO SHIGERU
IPC: H01L21/306
Filed: 2003-06-17
Granted: 2005-06-01
Abstract: The present invention is related to the electrostatic absorbing apparatus where its surface is processed and patterned to have dielectric plate having plural extruding portions, electrode, and external power source. Each substrate-supporting face of plural extruding portions is covered by the conductor wiring that is then used to connect electrically the substrate support face of plural extruding portions. When processing the substrate, substrate back surface and the conductor wiring have the same electric potential by using the movement of charges as the patterned extruding portion contacts the substrate back surface so as to prevent generation of force between substrate back surface and the contacted conductor wiring, and to prevent the generation of friction. By using the electrostatic absorbing apparatus to reduce the generation of particles, substrates can be easily and stably unloaded and conveyed so as to realize high yield and function efficiency of apparatus.