Patent GB-997706-A (GB)
Title: Inverter
IPC: H02M7/538
Filed: 1962-05-30
Abstract: 997,706. Inverting. WESTINGHOUSE ELECTRIC CORPORATION. May 30, 1962 [June 19, 1961], No. 20828/62. Heading H2F. [Also in Divisions G4 and H3] An inverting system comprises a number of square wave inverters having their outputs connected in series and phase displaced, so that the total output voltage approximates to a sine wave. The Specification derives a formula connecting the peak values of each square wave, the number of generators and their phase angles in terms of the peak value of the sine wave (Fig. 1, not shown) whose graph encloses the same area as the stepped wave form of the inverting system. In the embodiment of Fig. 6a and 6b the voltages appearing at each phase of the outputs LA, LB, LC are the vector sum of the voltages of five of the six inverters M, N, P, P, Q and R which are controlled from the pulse generator 2 through bi-stable circuits FM, FN . . . FR. Control circuit.-Each bi-stable circuit, one of which is shown within the dotted line F in Fig. 7, has two transistors 38, 40 and receives input pulses at the terminal 34 which switch the circuit except when inhibited by a signal through terminal 67 from the previous bi-stable circuit in the sequence. The inhibit signal is removed when the previous circuit switches so that each circuit switches one pulse interval after the previous one. Further switching is prevented by another inhibit signal from the previous circuit through terminal 69 so that this circuit cannot switch back until one pulse interval after the previous one. Each bistable circuit provides the inhibit signals for its neighbours through terminals 74, 76. In operation all the bi-stable circuits are switched in the sequence M, N . . . R and then switched back in the same sequence. The supply voltage which is applied between the centre tap 48 of the transformer and earth is increased by the arrangement 368 when the inverter output current is high. Inverter circuit.-Each inverter shown within the dotted lines D in Fig. 7 comprises transformer T with centre tapped primary windings 74, 75 and transistors 78A, 80A, 78B and 80B connected as shown to form two bi-phase inverters in parallel. The base currents are controlled through controlled rectifiers 96, 114 from the transformer 37 of the bi-stable circuit described above. The secondary voltage of transformer 37 must first saturate one of the transformers 124, 126 before the corresponding controlled rectifier is triggered. The inverter output is therefore controlled by delaying the start of the output pulses by biasing the transformers 124, 126 by the bias windings 131, 132, 133, 150, 151 and 152. The short circuiting network 84 which reduces the impedance of the output transformer T when the inverter has zero output is operated by another secondary winding 73 on the bi-stable circuit transformer and also by windings 130, 135 on the saturable transformer, the windings 130, 153 being energized during the delay period. The bias windings are arranged to compensate for variation in the D.C. source voltage and to limit the inverter output voltage and current. Another embodiment has a different output control system (Figs. 10 and 11, not shown). The arrangement of Fig. 13 (not shown) has one inverter operating at three times the frequency of the others.