Patent GB-983185-A (GB)
Title: Pulse code signalling system
IPC: H04B14/02
Filed: 1961-11-30
Abstract: 983,185. Pulse code modulation systems; telegraphy. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 30, 1961 [Dec. 30, 1960], No. 42909/61. Headings H4L and H4P. In a pulse code signalling system in which a binary 1, a binary 0 and a synchronizing signal are represented by pulses of different amplitudes means are provided for detecting the error rate in the information received at the receiver and for automatically reducing the bit frequency when the error rate increases, and when the error rate exceeds a predetermined frequency, for modifying the widths of the respective pulses to provide an additional identification. As shown, at the coder, Fig. 1, a binary signal to be transmitted from a source such as a multiplexer is supplied to a register 1 and translated into serial form through gates 2 to 4 controlled in sequence by a ring counter 5. When the complete sequence of N bits has been transmitted to the gate 6 a synchronizing pulse from the counter 5 resets the register 1, and also is applied to an AND gate 9, the output of gate 6 being applied to an AND gate 10 and via an inverter 11 to an AND gate 12. A clock generator 7 which controls the counter 5 via a delay 8, also supplies pulses to the gates 9, 10, 12, which thus provide outputs for a sync. pulse, a " 1 " bit and an " 0 " bit respectively. The pulse from gate 9 is transformed at 13 into a pulse of amplitude V 1  and width T and similarly the outputs of gates 10 and 12 are transformed at 14 and 15 into pulses of amplitude V 2  and V 3  respectively and width T. With the switches 16, 17, 18 in the position shown these pulses are supplied via OR gate 22 and the output line to the decoder, Fig. 2. If the switches are in their alternative position the pulses from 13, 14, 15 are converted at 19, 20, 21 to pulses of amplitude V 1 , V 2 , V 3 , of width T + #T 1 , T + #T 2  and T + #T 3  respectively, these pulses being transmitted via OR gate 22 as before. The switches 16, 17, 18 may be adjusted manually or their position may be made dependent upon the rate of bit transmission as determined by the clock pulse generator 7. In the decoder an error checking unit sends back a signal to OR gate 23 which increases as the error rate increases, and is passed via inverter 24 to control the pulse rate from generator 7. Thus a low output from gate 23 causes the rate of bit transmission to be high and a high output reduces the bit rate. Sync. pulses from the counter 5 are integrated at 26 and the resulting output supplied to a circuit 27 having either a fixed bias or a bias supplied from the decoder error checker. Only if the signal from the integrator 26 is greater than the bias will an output signal be provided from circuit 27 which will reset trigger 29 or maintain it reset if already in that position and relay 30 will not be energized. With no output from circuit 27 the inverted signal from 28 will set the trigger 29 and energize the relay 30 to transfer switches 16, 17, 18 to their upper contacts. Thus if the error rate increases the pulse repetition frequency is decreased and when the error rate reaches a predetermined magnitude the sync. pulses and signal pulses have their width increased in the manner described. To reduce hunting a trigger 25 is set when the relay 30 is energized and supplies a relatively high signal via OR gate 23 to override any subsequent lower signal from the error rate checker. At the same time a signal is supplied via delay 31 and AND gate 32 to reset the trigger 25 after a predetermined time interval. At the receiver, Fig. 2, the synchronizing pulses are selected by an amplitude detector 33 and passed via a delay 34 to set a trigger 35. The output from 33 is also passed to a circuit 36 which only generates a pulse if the sync. pulse has a width T + #T 1 , this pulse, if present, setting a trigger 37. Trigger 35 when set supplies inputs to AND gates 39, 41, which also receive all incoming pulses except the sync. pulses. Similarly, trigger 37 when set supplies inputs to AND gates 38, 40, receiving all incoming pulses except the sync. pulses as their second input. The AND gates 38, 39, supply the " 0 " bit width detector 42 and amplitude detector 43 respectively and the AND gates 40, 41 supply the " 1 " bit width detector 50 and amplitude detector 49 respectively. The output of " 0 " bit amplitude detector 43 is supplied to AND gate 44 which also receives the output of " 1 " bit amplitude detector 49 after inversion at 54. Thus an output from detector 49 at the same time as one from detector 43 will inhibit the gate 44 and only valid " 0 " pulses are supplied to AND gate 45. This is necessary because the " 0 " bit amplitude detector 43 detects pulses with an amplitude greater than V 3  and would show an output with a " 1 " bit input. The output of detector 49, which responds to amplitudes greater than V2 is also supplied to AND gate 51. When only the amplitudes of the respective bits in the input signal differ the trigger 37 remains reset and the output from AND gate 45 is passed via OR gate 47, OR gate 48, and delay 57 to the distributer 58. Similarly the output from AND gate 51 is passed via OR gate 53, OR gate 48 and delay 57 to the distributer 58. The distributer 58 which is reset by each sync. pulse feeds a register 62 via AND gates 59 &c. controlled by " 1 " pulses from the gate 53. If the pulse widths of the respective bit signals differ the trigger 37 is set so that gates 45 and 51 are blocked but gates 38, 40 are conditioned to pass signal pulses to the " 0 " bit width detector 42 and " 1 " bit width detector 50 respectively, the outputs of detectors 42, 50 being respectively applied to AND gates 46, 52. The other input to AND gate 46 is supplied from AND gate 44 via delay 56 so that both detectors 42 and 43 must supply an output for OR gate 47 to pass an " 0 " signal to the distributer 58. Similarly the other input of AND gate 52 is supplied from amplitude detector 49 and both detectors 49 and 50 must supply an output to enable a " 1 " signal to pass to the distributer. For error checking it is assumed that an N bit message signal contained in register 1, Fig. 1, consists of m characters each character consisting of n bits, e.g. six information bits and one parity bit, and contains an even number of " 1 " bits including the parity bit, a " 1 " parity bit being generated if it is necessary to bring the total number of bits to an even number. A counter 63 counts the " 1 " bits from the gate 53 to indicate whether the number of " 1 " bits in a character is odd or even. To reset the counter 63 at the beginning of each character a signal from position 1 of the distributer 58 is supplied via OR gate 65 and delay 66. At position 1 + n of the distributer 58 the first character has been placed in the register 62 and the output of counter 63 is sampled by AND gate 64. If an odd number of " 1 " bits has been counted the counter 63 will supply a signal to AND gate 64 thus operating a counter 67 which will count the number of errors in a given time interval. The output from OR gate 65 will also reset the counter 67 to prepare for counting the number of " 1 " bits in the next character. The count from the counter 67 is converted into an analogue signal at 68 which is supplied to an AND gate 69 opened by each sync. pulse from detector 33. The signal from gate 69 is stored at 70 for application to the coder, Fig. 1. The sync. pulse is also applied through a delay 71 to reset the counter 67.