Patent GB-717138-A (GB)
Title: Electrical pulse generating circuits
Inventor: DAVIES DONALD WATTS
IPC: H03K5/00
Filed: 1951-11-26
Abstract: 717,138. Pulse generating and gating circuits. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Nov. 11, 1952 [Nov. 26, 1951], No. 27719/51. Class 40 (6) In a circuit for generating a single pulse occurring with a specified timing relative to a periodically recurring series of pulses, a second series is derived from the first having the timing of selected pulses therein. A wide pulse is derived from a trigger circuit connected to a delay line and so timed that it embraces only the desired pulse in the second series. The circuit is particularly applicable to electronic computing machines such as described in Specification 717,114, [Group XIX]. The invention is described as applied to major cycles each comprising 32 minor cycles of 32 digits. Five trigger circuits 1 ... 5, Fig. 1, comprising a major cycle counter feed through changeover switches 15 ... 19, a gate of diodes 10 ... 14 to pass a pulse, a minor cycle long, to the trigger circuit V1 which reverses its state to generate a positive pulse, Fig. 2 (a), at the right anode, and a similar negative pulse at the left anode. With the setting of the switches 15 ... 19, as shown, this pulse commences at the 16th digit and it is arranged that a wide pulse occurring at the 32nd digit is fed over'a differentiating circuit C1R1 to cause valve V3 to conduct at the trailing edge of the wide pulse to produce currentpulses in the anode circuit, Fig. 2 (b). Since the grid of right valve V2 is biased more positively than the left,even during a pulse, the current pulses from valve V3 pass through the right side of valve V2 to maintain right valve V4 cut off. Valve 5 is biased to a condition where the left side conducts and the negative pulses from valve V1 are ineffective until a switch A is closed to charge a capacitor C negatively: over resistors R2R3. Subsequently a pulse from valve V1 causes the valve V5 to reverse its state. Fig. 2 (c). The fall in anode potential of right valve V5 is fed down delay line DL short-circuited at its far end and' with a rectifier arranged as described in Specification 702,401. After about half a major cycle, a negative pulse appears at rectifier D and is terminated a major cycle later after reflection from the far end, Fig. 2 (d). This wide pulse is fed to the right side of valve V2 and lowers the bias sufficiently that the next pulse from the anode of valve V1 causes the currentpulses from valve V3 to pass through left valve V2 to reverse the state of valve V4, Fig. 2 (e), and thus initiate the leading edge of the output pulse, Fig. 2 (f). The next current pulse through valve V3 occurs after the cessation of the pulse from valve V1 so that it passes through right valve V2 to restore the valve V4 and terminate the output pulse. Continuous selected minor cycle, Fig. 2 (g).-If switch B is closed, the right grid of valve V2 is biased sufficiently negative that each positive pulse from valve V1 causes the current pulse from valve V3 to pass through left valve V2 and thus reverse the state of valve V4 to initiate the output pulse, Fig. 2 (g), which is terminated by the succeeding pulse from valve V3. In a modification to produce a single pulse, the output from the circuit with switch B closed, Fig. 2 (g), is gated by the wide pulse from the delay line, Fig. 2 (d), to give a final pulse as in Fig. 2 (f).