Patent GB-842355-A (GB)
Title: Electronic computer
IPC: G06F7/498
Filed: 1956-08-23
Abstract: 842,355. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 23, 1956 [Aug. 23, 1955], No. 25752/56. Class 106 (1). An electronic computer comprises means for receiving successively presented patterns of binary-form data representing a plural-digit number, the data bits of any given pattern being presented simultaneously and identifying equivalued digits of said number (e.g., as from a record card) and means for generating pulse trains for selectively storing either the number or its complement in a storage device. The computer described performs either the calculation (AB)(CÎD) or (AB)¸C, the numbers A, B, C and D being read simultaneously from a record card and the particular calculation performed being determined by programme holes punched in the record card. The addition or subtraction is performed as the card is being read, after which the multiplication (by series of repeated additions alternated with denominational shifts) or division (by repeated subtractions and adding back), is performed. The result of the calculation is transferred to a relay store for controlling read-out punch magnets. Read-in and addition or subtraction.-As each row of the card is sensed a cam-controlled contact 1-24, Fig. 1, closes, causing a gate 1-12 to be opened and thereby causing a primary counter formed by 6 triggers 1-15, 1-17 to 1-21, to go through one 64-clock pulse cycle, each of which is divided into 4 16-clock-pulse read-in cycles. In the first and third of these read-in cycles an arrangement of gates causes cathode followers 1-49, 1-48 to produce two pulse trains 9s and 10s, respectively, the first being positioned in a cycle, as shown in the upper part of Fig. 2a (and also being shown at L, Fig. 2a) and comprising 9 pulses and the second comprising 10 pulses, starting one pulse time before the 9s pulse train. Also as each row is sensed and in each read-in cycle a gate 2-10, Fig. 2, controlled by cam contacts 2-15 to 2-18 and the primary counter, produces an output 1 at a time which is indicative of the particular row being read (the output of gate 2-10 is shown in curves A to I of Fig. 2a) and this causes a read-in trigger to be set on. The read-in trigger is used in conjunction with the 9s pulse train (L, Fig. 2a) to enter digits read from a card into an accumulator either in true form or in complement form. For example, when row 7 of a card is being read, the read-in trigger 2-21 goes on, as shown at N in Fig. 2a, and can be used to gate either 7 pulses from the 9s pulse train into an accumulator, or 2 pulses (P, Fig. 2a). The accumulator into which these pulses are entered comprises 16 decimal counters BC, Figs. 3a, 3b (Fig. 3b being not shown), linked by carry storage triggers 3-141 to 3-156. Entry into the accumulator takes place twice as each card is being read, from the " A " field during the first read-in cycle and from the " B " field during the second read-in cycle, the sensing brushes for these fields being connected to terminals 3-25A to 3-10A and 3-25B to 3-10B respectively, and interdenominational carry occurs during the second and fourth read-in cycles, during each of which 16 resetting clock pulses are applied via lead 1-510 to the carry storage triggers, thereby permitting through carry. Consider, for example, the reading of card row 7 on the first read-in cycle at the time shown by pulse train N, Fig. 2a, the read-in trigger 2-21, Fig. 2, is set on, thereby opening, via amplifier 2-22, the A field entry gates 3-41A to 3-26A, Fig. 3. This results in the setting on of those of triggers 3-75 to 3-60 that correspond to holes sensed in card row 7 and in turn to the gating of 7 pulses from the 9s pulse train through gates 3-92 to 3-77 into the accumulator. During the second read-in cycle the carry storage triggers are sensed and during the remaining two read-in cycles of row 7 the B field is entered in a similar manner. For negative read-in of either the A or B field either relay 2-35 or 2-39, Fig. 2, respectively, is energized by a programme hole in the card instead of relay 2-31 or 2-32, respectively, for additive read-in, whereupon the 9s pulse train is applied to gates 3-108 to 3-93, Fig. 3, instead of gates 3-92 to 3-77, and as these gates are controlled by the inverse outputs of triggers 3-75 to 3-60, the final result is the entry of the nines complement. In respect of the units denomination only of the accumulator the 10s pulse train is used for negative entry, thereby rendering round carry unnecessary. Multiplication.-As the A and B fields are read into the accumulator the multiplier and multiplicand are registered, in a similar manner, in eight decimal counters BC, Fig. 5 and Fig. 4 (Fig. 4 not being shown), respectively, the multiplier being registered in nines complement form. Multiplication is effected by repeated additions of the multiplicand to the accumulator, via a shifting matrix, Fig. 7, under the control of the multiplier, which is gradually destroyed. The shifting matrix, Fig. 7, is arranged so that when one of triggers 5-45 to 5-52, Fig. 5, is on, the associated row of the matrix will transmit differentially-timed negative pulses applied to it on eight vertical conductors 4-450 to 4-520 (Fig. 4) from the multiplicand register to the accumulator, thereby effecting entry of the multiplicand into the accumulator. Multiplication starts with the highest denomination of the multiplier and proceeds in the following stages. Immediately after card row 9 has been sensed the trigger 5-52, Fig. 5, is set on, and the other triggers in the column being off. This primes the top row of the shifting matrix, Fig. 7, and opens a gate 5-72, Fig. 5, leading to the highest denominational counter of the multiplier register. Next a control unit (Fig. 6, not shown) applies a " test " pulse to gate 5-72, Fig. 5, which advances the decimal counter BC, 5-34, by one unit, which may or may not emit a carry signal depending upon whether or not it was originally registering 9. Assuming that the counter was not registering 9, the control unit then opens a gate 1-11, Fig. 1, causing the primary counter to go through a 32 clock-pulse cycle, a gate 1-22 being closed, preventing the last trigger operating. During the first 16 clock-pulses the multiplicand is " rolled " out of its register, by applying the 10s pulse train to each denominational counter, and routed via the top row of the shifting matrix to the accumulator where it turns on triggers 3-75 to 3-60 at differential times, thereby gating pulses from the 9s pulse train into the denominational counters similarly to entry direct from the A or B sensing brushes. The next 16 clock-pulses are devoted to carry propagation in the accumulator. At the end of the 32 clock-pulse cycle the gate 1-11, Fig. 1, is closed, shutting off the primary counter, and a second test pulse is applied by the control unit to lead 6-240 and thence to the highest denominational counter 5-34, Fig. 5, of the multiplier register. If the counter was not registering 9 at the end of the previous addition cycle a further addition cycle, of 32 clock-pulses, takes place in a similar manner. When eventually the counter does register 9, the next test pulse applied to it causes it to emit a carry which is applied, via an Or gate 5-43, to the first trigger 5-52 of the column of shift control triggers causing the On condition to be advanced by one stage. This advance of the On condition is detected by the control unit (from the commoned cathodes) which thereupon applies a further test pulse to the lead 6-240, instead of initiating a 32 clock-pulse addition cycle. As trigger 5-51 of the shift control triggers is now on this further test pulse passes through a gate 5-71 to enter the next lower denominational counter. Further additions of the multiplicand then occur until this counter produces a carry when the On condition in the column of shift control triggers is again advanced. This process continues until every multiplier counter has been returned to zero when the desired result will be in the accumulator. The operation of the control unit is thus such that if the On condition in the column of shift triggers advances after a test pulse a further test pulse is immediately produced but if the On condition does not advance then a 32 clock-pulse addition cycle is initiated before the next pulse is produced. In this way zeros in the multiplier are quickly passed over. To effect the calculation (AB)-(CÎD), as opposed to (AB)+ (C Î D), a relay 2-41, Fig. 2, is energized, by the sensing of the appropriate card position, and this effectively causes firstly the calculation - (AB)+(CÎD), a relay 2-41, Fig. 2, is energized, by the sensing of the appropriate card position, and this effectively causes firstly the calculation -(AB)+(CÎD) to be performed and secondly, the read-out of the result in nines complement form. Division.-The quotient of the number in the accumulator, Figs. 3a, 3b, and a divisor, registered in the multiplicand register (Fig. 4, not shown) is built up in the multiplier or quotient register, Fig. 5, by repeated subtractions of the divisor until the accumulator goes negative, followed by the addition of the divisor, a shift, and further subtractions. During division (and also multiplication) control of the positive or negative entry gates 2-47, 2-48, Fig. 2, is effected, not by the relays shown but by the electronic control unit. The operating sequence for division is as follows: initially the trigger 5-52, Fig. 5, of the shift control triggers is set on and a subtraction of the divisor from the accumulator is effected in the following 32 clock-pulse cycle. The control unit, having sensed the highest denominational carry storage trigger 3-156, Fig. 3a, of the accumulator, then either applies a pulse to the test-pulse lead 6-240, Fig. 5, thereby entering one into the highest denomination of the quoti