baber/WOPTO huggingface dataset:
Patent TW-393308-B (TW)
Title: Rice cooker
Inventor: HAMADA HIRONORI
IPC: A47J27/62
Filed: 1998-06-03
Granted: 2000-06-11
Abstract: A rice cooker not causing malfunction if the operation unit is touched by mistake when closing the lid, and capable of preventing boiling-over without lowering the rice cooking performance is presented. This rice cooker comprises a main body 31, a lid 36 for covering the top of the main body 31, an inner pan 32 detachably accommodated in the main body 31, heating means 33 for induction heating of the inner pan 32, control means 51 for controlling supply of high frequency power to the heating means 33, operating means 46, lid opening and closing detecting means 50 or rice gruel detecting means 103 disposed in a steam tube 47 of the lid 36. The control means 51 is constituted to inhibit operation signal input of the operating means 46 when detecting open state of the lid 36, to control the power supply to the heating means 33 when detecting rise of rice gruel. Therefore, by preventing wrong input in rice cooking when opening or closing the lid, and boiling-over of rice gruel, tasty rice can be cooked.
Patent TW-366391-B (TW)
Title: Sealing structure of a case
Inventor: UEDA SHUSAKU
IPC: F04C23/00
Filed: 1998-06-30
Granted: 1999-08-11
Abstract: Upper case (2a) is embedded externally into the lower case (2b). Recess (2a2) of the circumferential edge (5a) of the housing (5) is disposed on the inner wall (2a1) of the upper case. The protruding part (2a3), which is used to retain housing (5) deformation while the upper case (2a) is shrink fit or press fit, can be selectively formed on the bottom of the concave part (2a). Gap (14) is formed between the lower case (2b) and the housing (5), to reduce the pressure formed by the box (2) onto the housing (5) when the upper case (2a) and the lower case (2b) are welded together.
Patent TW-401641-B (TW)
Title: The manufacture method of cylindrical stack capacitor
Inventor: TSAI SHING-CHUAN
IPC: H01L21/02
Filed: 1998-08-14
Granted: 2000-08-11
Abstract: This invention discloses a manufacture method of Cylindrical Stack Capacitor in the DRAM of the integrated circuit. First, deposite a dielectric oxide layer and silicon nitrideon layer on the substrate containing electrical device, and form the contact via in the silicon nitride layer and dielectric oxide layer; and deposite the first poly-silicon to fill up such contact via; next, deposite an oxide layer and a silicon nitride oxide layer; and define the photoresist pattern of the bottom electrode of the capacitor; and proceed the etch of the silicon nitride oxide and the oxide; next, proceed the laterial etch of oxide and deposite the second poly-silicon layer, then proceed the etch of the second poly-silicon layer and the first  poly-silicon layer to form the capacitor poly-silicon bottom electrode structure; after removing the above-mentioned layer of  silicon nitride oxide, layer of oxide, and part of the silicon nitride layer, the capacitor dielectrics and the poly-silicon top electrode structure is formed.
Patent TW-385489-B (TW)
Title: Method for processing substrate and device of processing device
Inventor: SADA TETSUYA
IPC: B05D3/00
Filed: 1998-08-21
Granted: 2000-03-21
Abstract: The present invention is a method for processing substrate to remove the coating film from the substrate after the coating film is dissolved by a solvent, which comprises: (a) a process to supply solvent independently to each peripheral part of the face side and rear side of the substrate, and (b) a process to supply solvent to the peripheral part of the rear side which amount of the solvent is less than the amount supplied according to the process (a) to the peripheral part of rear side of the substrate, or to supply solvent to the peripheral part of the face side which amount of the solvent is less than the amount supplied according to the process (b) to the peripheral part of face side of the substrate; or a process to stop supplying solvent within the process (b).
Patent TW-380091-B (TW)
Title: In-plant casting method and the apparatus for mineral and artificial stone material
Inventor: JU JIE-SHENG
IPC: B28B1/08
Filed: 1998-08-26
Granted: 2000-01-21
Abstract: The apparatus and methods are used to make mineral and artificial stone material in plant. Making a special mold box and cutting the required stone material into suitable size and arranging them on the mold box in order. Then, pumping out the air to make the slates can be tightly attached on the foam pad of the mold box. After that, adding the spot welding wire net to reinforce the structure and grouting with plaster to form the prefabricated stone wall plates. The prefabricated wall plate can be applied to each kind of architecture that the installation of wall plates can be greatly simplified and save the technical labor and increase the working efficiency. Between the slate and grouting mortar layer, there are screws installed in order to prevent the ablation between the slate and mortar layer that can effectively reinforce the wall plate structure.
Patent TW-434967-B (TW)
Title: Battery charging apparatus
Inventor: HATANAKA KAORU
IPC: B60L11/18
Filed: 1998-08-27
Granted: 2001-05-16
Abstract: The purpose of this invention is to provide a battery charging apparatus that can suppress power consumption in the daytime. To achieve this, a battery charging apparatus 40 for charging a battery 7 for an electrically-operated vehicle includes accumulation means 45 for storing night power, and the battery charging apparatus 40 charges a battery 7 with the night power stored in the accumulation means 45. The accumulation means 45 can also be constructed such that it stores midnight power and, from midnight to daytime, charges a battery 7 using commercial power supply.
Patent TW-392216-B (TW)
Title: The semiconductor device with anti-type doped region and its manufacturing method
Inventor: KE TZUNG-SHI
IPC: H01L21/336
Filed: 1998-09-01
Granted: 2000-06-01
Abstract: The invention provides a semiconductor device with anti-type doped region and its manufacturing method. A first implantation procedure is applied to the semiconductor substrate where the gate and gate oxide layer is formed to form lightly doped region that is placed at the both sides of gate in the semiconductor substrate. Then, a second implantation procedure is applied to form anti-type doped region, which is the distinct feature of the present invention. The doped region is placed in the lightly doped region and close to the both sides of the gate on the surface of semiconductor substrate. Next, a spacer is formed and located at two sides of the gate. A third implantation procedure is applied, by using the spacer as a mask, to form the heavily doped region that is placed at the both sides of gate and located at the outside edges of the anti-type doped region in the semiconductor substrate. This heavily doped region is overlapped with the most of the lightly doped region and the anti-type doped region.
Patent TW-401519-B (TW)
Title: Distributed flat optical fiber
Inventor: KATO TAKATOSHI
IPC: G02B6/036
Filed: 1998-10-13
Granted: 2000-08-11
Abstract: A dispersion flat optical fiber is provided, which applies for the wavelength multiplex soliton transmission using an optical amplifier and the like and equips with the structure to effectively inhibit the appearance of nonlinear optical phenomena. The dispersion flat optical fiber of this invention is characterized in the following properties at a wavelength of 1550 nm: the absolute value of dispersion is below 5ps/nm/km; the effective cross section area is larger than 45 mu m<2> ; the dispersion slope is below 0.03; and the cutoff wavelength at a length of 2 m is above 1.0 mu m.
Patent TW-476748-B (TW)
Title: Processes for preparing optically active S-Α-aryl propionic acids or esters thereof
Inventor: TSAI SHAU-WEI
IPC: C07C43/168
Filed: 1998-12-04
Granted: 2002-02-21
Abstract: The invention describes a process for preparing optically active S-Α-aryl propionic acids from their racemic thioesters by using lipase-hydrolysis and base-racemization in different aqueous organic solvents. The invention also relates to a process for preparing optically active S-Α-aryl propionic acid esters from racemic Α-aryl propionic acid thioesters by using lipase-transesterification and base-racemization in different organic solvents. The processes according to the invention are novel and practical in view of the high optical purity and conversion higher than 50% of the product.
Patent TW-438689-B (TW)
Title: Fuel gauge unit for a fuel tank
Inventor: NAGASE YUJI
IPC: B60K15/077
Filed: 1999-01-22
Granted: 2001-06-07
Abstract: A fuel gauge unit for a fuel tank which, when the gauge unit is attached to the fuel tank, is fixed in its rotational angle in a simple fashion and at a low cost; and in which the fuel scale is simple, inexpensive, and easy to inspect visually. These goals are achieved in accordance with the invention by an indicator which moves back and forth in a horizontal plane when a bearing connected to a float rotates, the position of the indicator corresponding to a fuel scale, so that the quantity of fuel in the fuel tank can be determined by inspecting the gauge. On the top of the gauge unit is a protruding rectangular portion with a transparent window. This protruding rectangular portion engages in a hole in the cover plate attached to the fuel tank. The protruding rectangular portion and its hole may have a rectangular or oblong surface which serves as a rotational position lock for the gauge unit.
Patent TW-431114-B (TW)
Title: Hardware structure and formation for inverse quantization and multi-channel processing of MPEG-II audio signal decoding
Inventor: CHEN LIANG-JI
IPC: H04R5/00
Filed: 1999-04-09
Granted: 2001-04-21
Abstract: The present invention relates to a hardware structure, consisting of 5 sets of serial FIFO registers, a multiplier, a single register, and two adder-subtractors, suitable for inverse quantization and multi-channel processing of MPEG-II audio signal decoding. The first set of FIFO registers is used to receive outputs of the first adder-subtractor and the second set of FIFO registers is used to receive outputs of either the second adder-subtractor or the first set of FIFO registers. The third set of FIFO registers is used to receive outputs of either the single register or the second set of FIFO registers. The single register is used to receive the calculation result of the multiplier and output the calculation result to a buffer zone, the first adder-subtractor, the second adder-subtractor, or the third set of FIFO registers. Based on the hardware structure, inverse quantization can achieve a high output rate and, through efficient and flexible allocation of the multi-channel data, multi-channel processing allows the hardware structure to have a fixed output volume that will not vary along with various dematrixing models.
Patent TW-411544-B (TW)
Title: High speed, real-time, state interconnect for automatic test equipment
Inventor: CZAMARA ALLEN J
IPC: G01R31/319
Filed: 1999-04-13
Granted: 2000-11-11
Abstract: A tester is disclosed in which state coherency is maintained between functional blocks of the tester by way of a novel state distribution and recombination network. The network includes a plurality of nodes configured to provide point-to-point links between pairs of functional blocks. Further, time delays through the point-to-point links can be adjusted by selecting a suitable node configuration and by programming delay circuitry included in each node. The network therefore maintains state coherence between the functional blocks by ensuring that delays throughout the test system are both deterministic and adjustable. The tester is particularly useful for testing complex, mixed-signal semiconductor devices.
Patent TW-463366-B (TW)
Title: DRAM capacitor having a storage electrode with porous and coarse side wall
Inventor: WU SHIE-LIN
IPC: H01L27/108
Filed: 1999-04-23
Granted: 2001-11-11
Abstract: The capacitor structure of the present invention comprises: a storage electrode, a plurality of semispherical silicon grains, a dielectric layer, and a conductive layer. The storage electrode is located on the semiconductor substrate. The storage electrode is electrically connected to the conductive area on the semiconductor substrate. The storage electrode has a porous structure. The semispherical silicon grains are located on the sidewall of the storage electrode. The dielectric layer covers on the porous structure, the storage electrode, and the plurality of semispherical silicon grains. The conductive layer is located above the dielectric layer.
Patent TW-449963-B (TW)
Title: Surface acoustic wave filter apparatus, duplexer, and communications apparatus
Inventor: KADOTA MICHIO
IPC: H03H9/17
Filed: 1999-05-10
Granted: 2001-08-11
Abstract: A surface acoustic wave filter apparatus includes a plurality of stages of multi-mode filters defined by edge-reflection type surface acoustic wave devices and electrically connected in series with each other. The plurality of stages of multi-mode filters are provided on a common piezoelectric substrate and arranged in a direction which is substantially perpendicular to the propagation direction of surface acoustic waves. Ground electrodes are located between the stages of the plurality of stages of multi-mode filters.
Patent TW-417162-B (TW)
Title: Vacuum processor and method of vacuum processing using the processor
Inventor: WATANABE AKIZO
IPC: H01L21/02
Filed: 1999-05-12
Granted: 2001-01-01
Abstract: The objective of the present invention is to stably operate the surface processing of a substrate to be processed, by preventing glow discharging due to inert gas generated between a susceptor and a vacuum processing container. A bush made of porous ceramic is arranged between a susceptor and a vacuum processing container in the middle of an inert gas supplying path, and a guide bush 11 for guiding an elevation pin for carrying a substrate to be processed is constituted as the inside and outside double structure constituted of an insulator bush 11a for supporting the inside elevation pin and an outside porous ceramic 11b. The distance of a channel between the susceptor of the inert gas and the vacuum processing container is made long so that the glow discharging of the inert gas can be prevented. The guide bush 11 can be constituted so that a spiral groove constituted of an insulator can be formed with a hole for supporting the elevation pin at the central part, and with an inert gas channel at the outside part.
Patent TW-498395-B (TW)
Title: Integrated circuit device, and method for forming an electronic device and electronic device formed thereby
Inventor: FRIEND RICHARD HENRY
IPC: H05B33/26
Filed: 1999-05-27
Granted: 2002-08-11
Abstract: An integrated circuit device comprising: a current drive switching element having an input electrode, an output electrode, a switchable region comprising a semiconductive polymer material electrically coupled between the input electrode and the output electrode, and a control electrode electrically coupled to the swtichable region so as to allow the application of a bias to the control electrode to vary the flow of current through the switchable region between the input electrode and the output electrode; and a second circuit element, integrated with the switching element, and electrically coupled with the output electrode of the switching element for receiving a drive current from the switching element.
Patent TW-436776-B (TW)
Title: Objective lens drive device and its manufacturing method
Inventor: SHINOZUKA KEIJI
IPC: G11B7/09
Filed: 1999-07-07
Granted: 2001-05-28
Abstract: To provide an objective lens drive device capable of realizing high sensitivity, a wide band and a small tilt in a very small space and further improving performance. This objective lens drive device is provided with a lens holder 3 holding an objective lens 2 and being driven, four pieces of wires 6 whose one ends are fixed to the lens holder 3 for controlling the attitude of the lens holder 3 and a wire holder 4 to which the other ends of the wires 6 are fixed; and the lens holder 3 and the wire holder 4 are hung/held by a holder hold frame 35 to be removed after assembling, and are provided for removing the holding hold frame 35 after the wires 6 are fixed to both, and the wires 6 are hung/held by a wire hold frame 38 to be removed after assembling, and reformed for removing the wire hold frame 38 after the wires 6 are fixed to the lens holder 3 and the wire holder 4.
Patent TW-461131-B (TW)
Title: Dry-type chemical battery
Inventor: KASANO HIROYUKI
IPC: H01M14/00
Filed: 1999-08-02
Granted: 2001-10-21
Abstract: The present invention uses n-type semiconductor with carrier concentration 5x10<SP>16</SP> to 2x10<SP>19</SP> cm<SP>-3</SP> as the cathode, a kind of metal having an electron affinity larger than that of the cathode stated above as the anode, and skin of the alive body as the electrolyte so as to form a dry-type chemical battery and realize a dry-type chemical battery that is easy to raise both the safety for human body and the operation efficiency.
Patent TW-451496-B (TW)
Title: Electro-optical device driving circuit, electro-optical device and electronic equipment containing the same
Inventor: OZAWA TOKURO
IPC: H04N5/74
Filed: 1999-10-15
Granted: 2001-08-21
Abstract: The rate of transmission of image data at a point on data lines decreases with a reduction in the distance between the point and a tip end thereon in a conventional liquid crystal drive circuit. This results in a decrease in the data latch timing margin of the clock signal. Consequently, it becomes difficult to input image data thereto at a high speed. The solution of the present invention comprises: a drive circuit for an electro-optical device, which has a plurality of pairs of shift registers for latching and holding signals representing bits of image data, a D/A converter for performing D/A-conversion on image data latched by the shift register n-bits by n-bits for generating voltages corresponding to 2<SP>N</SP> gray scales and for supplying the generated voltages to signal lines, and a switch group for selectively supplying image data latched by one of the shift registers of each of the pairs to the D/A converter. This drive circuit is adapted to repeatedly perform an operation of supplying the D/A converter with image data held by one of the shift registers while image data is latched by the other shift register of said each pair of shift registers.
Patent TW-483888-B (TW)
Title: process for the preparation of 3-pentenoic acid from allylic butenyl alcohols or esters using a nickel catalyst
Inventor: BURKE PATRICK MICHAEL
IPC: C07C51/12
Filed: 1999-10-21
Granted: 2002-04-21
Abstract: Process for making 3-pentenoic acid acid by reacting an allylic butenyl alcohol or its corresponding ester with carbon monoxide in the presence of nickel, and a source of iodide.
Patent TW-440993-B (TW)
Title: Design of embedded capacitors in multi-layer substrate and the manufacturing method thereof
Inventor: TSAI JIN-WEN
IPC: H01L21/70
Filed: 2000-03-22
Granted: 2001-06-16
Abstract: The present invention provides a multi-layer substrate structure with embedded capacitors, which uses the through hole between the voltage layer and the ground layer to fill one or more than one substances with high dielectric constant, and electroplates the upper and lower sides of the through holes to form the capacitor electrode plate. Therefore, it can generate a plurality of embedded capacitors built with different capacitance so as to couple with the noise between the voltage layer and the ground layer caused by high frequency operation.
Patent TW-477979-B (TW)
Title: Semiconductor memory device
Inventor: ITOU TAKASHI
IPC: G11C11/401
Filed: 2000-04-28
Granted: 2002-03-01
Abstract: There is provided a test mode decision circuit which in the first WCBR cycle responds to an address key by activating a test mode entry signal and with the test mode entry signal activated in the second WCBR cycle responds to an address key by selectively activating test mode signals. In addition to a test mode signal having been activated, the test mode decision circuit further activates another test mode signal. Thus the DRAM hardly enter a test mode erroneously and is also capable of entering more than one test mode simultaneously.
Patent TW-444134-B (TW)
Title: Projection lenses having reduced lateral color for use with pixelized panels
Inventor: KREITZER MELVYN H
IPC: G02B13/22
Filed: 2000-05-06
Granted: 2001-07-01
Abstract: Projection lens for use with pixelized panels are provided which consist of a first lens unit (U1) which has negative power and a second lens unit (U2) which has a positive power. The V-values and Q-values of the lens elements of the first and second lens units (U1 and U2) are selected so that the projection lenses can simultaneously have: (1) a high level of lateral color correction, including correction of secondary lateral color; (2) low distortion; (3) a large field of view in the direction of the image (screen); (4) a telecentric entrance pupil; and (5) a relatively long back focal length.
Patent TW-466615-B (TW)
Title: A gate structure for integrated circuit fabrication
Inventor: KIZILYALLI ISIK C
IPC: H01L29/43
Filed: 2000-05-15
Granted: 2001-12-01
Abstract: The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.5 nm or less and includes at least one layer other than silicon dioxide. The dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.
Patent TW-445649-B (TW)
Title: Semiconductor memory and method for operating a semiconductor memory
Inventor: FUJIWARA HIDEAKI
IPC: H01L29/423
Filed: 2000-05-19
Granted: 2001-07-11
Abstract: A semiconductor memory capable of attaining a long life, a low voltage, a high-speed operation, low power consumption and high integration is provided. The semiconductor memory comprises a control gate electrode, a floating gate electrode, a semiconductor region, a first insulator film formed on one surface of the semiconductor region and a second insulator film formed on another surface of the semiconductor region. A prescribed voltage is applied to the control gate electrode or a drain region thereby injecting carriers from the control gate electrode or the drain region into the floating gate electrode through the first insulator film, the semiconductor region and the second insulator film.
Patent TW-440489-B (TW)
Title: Hand operated sanding tool
Inventor: STIPE DANIEL M
IPC: B24D9/08
Filed: 2000-05-22
Granted: 2001-06-16
Abstract: A hand-powered sanding tool utilizes a rigid sanding plate, such as one made of steel. The sanding plate has a plurality of material removal teeth on at least one side for removing material from a workpiece, such as for sanding a board or a wall. The sanding plate is attached to a handle that is preferably ergonomically designed for ease of use. In preferred embodiments, the sanding plate is attached to the handle such that it may be repeatably removed and attached thereto without affecting performance. Further, in some embodiments, the sanding plate is reversible so as to provide an alternate sanding surface for use.