Patent GB-848326-A (GB)
Title: Improvements in or relating to information checking apparatus
Inventor: SHARP JOHN JOSHUA
IPC: G11B20/18
Filed: 1956-02-02
Abstract: 848,326. Electric digital-data-storage apparatus. INTERNATIONAL COMPUTERS & TABULATORS Ltd., Jan. 8, 1957, [Feb. 2, 1956], No. 3321/56. Class 106 (1). Apparatus for checking binarytype signals occurring simultaneously on a plurality of channels includes means responsive to a signal on any channel to produce a first test signal, means responsive only to the occurrence of signals on all channels to produce a blocking signal, and means responsive to the blocking signal to block the first test signal. A parity check is also performed. As described, seven tracks of a magnetic tape 2, Fig. 1, are read by pick-up heads 1, and the resulting signals, each of which is either " 0 " or " 1," are checked to determine (a) that all the heads are functioning (b) that sum of the seven digits is an odd number (the seventh channel contains parity digits). Each signal leaving the reading head comprises approximately a single sine wave as indicated at A, Fig. 3, which represents " 101." The signals are transmitted via a transformer 4, Fig. 1, to amplifiers 5 and 6 which transmit positive pulses in response to the positive and negative halves, respectively, of the pulses at A; B indicates the output of amplifier 5 and C the output of amplifier 6 in response to the input A. Pulses B pass via a differentiating circuit 7 to a mono-stable trigger 8 to give output pulses at 10 as shown at D. These output pulses also serve to open a gate 9 to allow passage of a pulse from amplifier 6 to the output line 11 (see E, Fig. 3), this occurring only when a " 1 " signal has been read. Thus, each of the reading heads 1 supplies signals to an output line 10 (see also Fig. 2) for every signal detected (either " 1'' or " 0 "), and signals to an output line 11 for every " 1 " signal picked up. The signals on lines 10, Fig. 2, are fed to an AND gate 14 and an OR gate 13. An output signal from the latter is fed via cathode-follower 18, differentiating circuits 19, 21 and 23, and trigger circuits 20, 22 and 24 (which provide delays to account for possible skew of the tape and other discrepancies) and emerges as a test signal which is applied to a normally open gate 17. If, as would normally be the case, the AND gate 14 responds to signals on all seven of the lines 10 simultaneously, a pulse is transmitted via a cathode-follower 15 and inverter 16 to block the gate 17 and so prevent the test signal from passing through to set an error trigger circuit 25. For the parity check the lines 11 (Figs. 1 and 2) enter the number into a sevenstage shift register 26. Shift pulses from a source 27A step this information out, in series mode, to a utilization device 39A and also, via a differentiating circuit 40 and gates 41, 42 to a trigger circuit 38 whose outputs are connected back to the gates 41, 42 so as to allow pulses to pass through them alternately respectively to set and reset the trigger. The shift pulses also feed a counter 28, 29, 30 arranged to give an output signal at each count of seven which signal, after being differentiated by a device 33, passes an inverter 34 and a delay element 35 before reaching further delay element 37 and the gate 36. The gate 36 is normally closed at this stage as a result of an odd number of pulses passing through the networks 40, 41, 42, 38, and the delayed pulse through 37 merely serves to reset the trigger 38. If, however, an even number of pulses from the shifting register 26 leaves the gate 36 open, the signal passes through to set the error trigger circuit 25. An alternative arrangement of the network 40, 41, 42, 38 ( Fig. 4, not shown) is described and detailed circuits equivalent to the schematic arrangements shown in Figs. 1 and 2 are given in the Specification.