Patent GB-747606-A (GB)
Title: Electrical circuits employing transistors
Inventor: WILLIAMS FREDERIC CALLAND
IPC: G11C19/28
Filed: 1952-07-16
Abstract: 747,606. Transistor circuits. NATIONAL RESEARCH DEVELOPMENT CORPORATION. July 3, 1953 [July 16, 1952; Feb. 10, 1953], Nos. 17984/52 and 3754/53. Class 40 (6). [Also in Group XIX] At least two of the electrodes of a transistor are connected to power sources over circuits arranged to supply predetermined currents to the electrodes when the transistor is conducting (i.e. " on ") and to maintain the potentials on the electrodes within predetermined limits when the transistor is non-conducting (i.e. " off "). The invention is described as applied to circuits having one, two or more stable states, pulse generating, delaying, counting and frequency dividing circuits and to pulse distributing, storage and gating circuits also sawtooth generating circuits. The arrangements described enable transistors to be used having varying characteristics provided they exceed certain minimum values. Since the algebraic sum of the electrode currents is zero, the current in the third electrode is defined indirectly but may be defined directly in a similar manner to the other electrodes. It is shown that a defined emitter current leads to a stable on condition. Two stable state circuits. Currents Ie, Ic and Ib are supplied through resistors Re, Rc and Rb, Fig. 3 (the first Provisional Specification) and their associated diodes D1, D2 and D4 to maintain the emitter, collector and base at 0, - 10 and + 2 volts so that the transistor is off. When the cathode potential of diode D1 is raised, Fig. 3A, the anode and emitter follow until the base potential is approached when collector current equal to αie flows. This has no effect while it is less than Ic as the current through diode D2 is merely reduced, a similar effect occurring in the diodes D1 and D4. By suitable choice of Ie, Ic and Ib it is arranged that diode D4 cuts off first, the increased cur. rent in Re causing the base potential to fall, the emitter current ie to rise and thus more base current to flow. This cumulative action increases until ie takes all the current Ie, diode D1 ceases to conduct and the action ceases as ie cannot be significantly increased. As the base current is in excess of Ib. the base potential falls, charging the stray capacity Cb negatively until diode D3 conducts at - 2 volts. In a similar manner diode D2 cuts off and as the collector current exceeds Ic the collector potential rises at a rate determined by the stray capacitor Cc. In the on state the emitter and collector are slightly above and below respectively the base potential corresponding to a point below the knee of the collector volts/col. lector current curves, Fig. 1 (not shown). The circuit is reset by raising the anode of diode D3 above earth or lowering the cathode of diode D1  below - 2 volts. In a modification, Fig. 4 (the first Provisional Specification), the emitter current ie is defined indirectly since the collector and base currents are defined in the on condition. In the off state diodes D1, D2 conduct, a triggering potential applied to the emitter or cathode of diode D2 causing the transistor to pass to the on condition. The emitter may be allowed to change its potential from the off to on condition, Fig. 6 (the first Provisional Specification), by employing diodes D1, D4. In another embodiment, Fig. 5 (not shown), the collector is held at constant potential, the emitter and base currents being defined directly in the on condition and the collector current indirectly. The collector may be allowed to vary its potential through a range, Fig. 7 (the first Provisional Specification), diodes Dl and D2 conducting in the off condition and the electrodes falling in potential in the on state until the collector is caught at - 6 volts. Two state circuit triggered into one state by one pulse train and other state by a second pulse train. The circuit, Fig. 8 (the first Provisional Specification), when in the off condition operates with diodes D2, D5 and D3 conducting, a triggering pulse V1 lowering the cathode of D3 so that the transistor passes to the on state as in Fig. 6. A pulse of the resetting train V2 applied to the anode of diode D4 causes the base to rise above the emitter, the collector following, Fig. 8A, until the transistor passes to the off condition, which occurs when diode D2 conducts to hold the emitter at earth. The pulse trains V1, V2 must have amplitudes of at least 2 and 5 volts respectively but it is preferable to exceed 7 volts when the trigger action of the transistor is not then relied on. Excessive amplitude of pulses is absorbed by limiting effect of diodes D3 and D4 also D1 for the triggering pulse. This circuit may be employed as a staticisor in a computor. In an alternative arrangement, positive triggering pulses are applied to the cathode of diode D2 and positive resetting pulses applied to the anode of diode D5, the emitter being tied to earth over a capacitor. The diodes D3, D4 may be replaced by a small resistor returned to + 2 volts. Coincidence counting circuit, Fig. 9. Triggering pulse a and resetting pulses b, Fig. 9A, are effective to trigger or reset the circuit according whether the transistor is off or on respectively. In the off condition diodes D1, D2 conduct, D3 being biased off so that only the triggering pulse is effective. The pulse a carries the base below the emitter so that current flows in all the electrodes and diode D1 cuts off, the cumulative action causing the transistor to pass to the on condition with all the electrodes at nearly the same potential of - 3 volts. Further fall in emitter potential is retarded due to capacitor C charging over R1 and Rc. This continues until the collector is at -9 volts, the base and emitter potentials being slightly greater. At the occurrence of the next reset pulse b, diode D2 is biased off and the triggering pulse is ineffective. The reset pulse carries the base positive, the emitter following until all the current flowing in the emitter resistor is diverted to discharge capacitor C, the emitter potential thereafter rising slowly to earth. When the rise in emitter potential is arrested, the continued rise of the base causes the transistor to pass to the off state. The collector follows the base until the transistor cuts off, whereupon collector current ceases and the potential falls to - 10 volts. The slow recovery of emitter potential is such that the triggering pulse a has ceased before recovery is complete. The pulses fed out at a<SP>1</SP>, b<SP>1</SP> are similar to a, b but occur at half the frequency. Two stable state and counting circuits. The first pulse of a train a, Fig. 10A, causes the transistor, Fig. 10, to pass to the on condition as in Fig. 9, diode D1 then being biased off. The next pulse, fed over capacitor C1, cuts off diode D2, the emitter current being supplied by capacitor C2 charging. When the emitter potential has fallen sufficiently for the current to cease, the transistor changes over to the off condition, the base potential rising rapidly until caught at + 2 volts due to diode D1 conducting, while the emitter rises slowly as capacitor C2 is discharged by the current Ic. An output pulse a<SP>1</SP> is fed out over resistor R1, and this may be increased by omitting the collector resistor. One stable state pulse delaying and frequency dividing circuits. By the use of a reduced. emitter current the circuit of Fig. 11 is arranged to be unstable in the on position. The first of a train of pulses a, Fig. 11A causes the transistor to pass to the on condition, the emitter current being maintained by the charging of capacitor C. When it falls below an initial value, the transistor passes to the off condition and diode D1 conducts but is ineffective. The emitter potential rises slowly as capacitor C charges until diode D2 conducts, the next pulse a retriggering the transistor. The capacitor may be replaced by an open-circuited delay line. A resistor may be arranged in series with capacitor C to give a negative pulse to operate a second frequency divider, the collector resistor Rc being omitted, Fig. 12 (not shown). Where a comparatively high rate of division is required, an isolating diode may be included in the emitter lead so that the back resistance of the emitter cannot affect the charge on the. capacitor during the recovery of the emitter potential, Fig. 17 (not shown). In a modification, Fig. 13, the circuit is made unstable in the off condition by allowing the emitter to rise above the base by omitting the diode clamp to earth. In the on condition the electrodes are all near - 9 volts, a positive triggering pulse applied to the anode of diode D1 cuts off the transistor, the base being caught at + 2 volts by diode D2 conducting while the emitter potential rises slowly as capacitor C is discharged and then charged positively. The collector potential falls slightly to - 10 volts until the transistor is switched to the on condition. When this occurs, the collector is raised to near emitter potential to develop a delayed pulse. The delay may be varied by altering C, or the bias on diode D2. Alternatively resistor Re or supply E 1  may be varied over a limited range. The circuit may be used for frequency division. Two unstable state and pulse generating circuits. By reducing Ic or increasing Ib the circuit may be arranged to operate as a relaxation oscillator, Fig. 14. With the transistor off, capacitor C is discharged and then charged positively by the current Ie, diodes D1 and D2 conducting to hold the base and emitter at constant potential. When the emitter potential exceeds the base, the transistor passes to the on condition, the base resistor ensuring a trigger action. The potentials of all the electrodes rise to about + 2 volts since the emitter is held by capacitor C and all fall slowly as capacitor C is charged negatively until diode D2 is rendered conducting again. The emitter current is no longer augmented by capacitor C chargin