Patent GB-1401560-A (GB)
Title: Forming metallic layers in semiconductor devices
IPC: H01L21/288
Filed: 1973-03-22
Abstract: 1401560 Semi-conductor devices WESTERN ELECTRIC CO Inc 22 March 1973 [22 March 1972] 13841/73 Heading H1K A semi-conductor body, e.g. Si, is covered (Figs. 1, 2) with an insulant layer 23, e.g. by thermal oxidation to SiO 2  or vapour deposition, over which a further different dielectric layer 24, e.g. Al 2 O 3  or Si 3 N 4  is deposited. A third adherent dielectric layer 25 similar to 23 or differing therefrom, e.g. SiO 2 , is deposited thereon. A photo-resist mask (not shown) is deposited on layer 25 and the exposed portions of layer 25 are etched with, e.g. to form apertures 25A, 25B thereon, and after removal of the mask further etching with hot H 6 PO 4  forms corresponding apertures in layer 24. Layer 25 is then completely removed by further etching, and the structure is again etched in, e.g. HF, to attack layer 23 without affecting layer 24 to extend the apertures partially or wholly through the thickness of the layer; in the latter case a further thin layer of insulant is deposited on the surface of the body in all or selected apertures. A further layer 24<SP>1</SP> of insulant, e.g. Al 2 O 3  or Si 3 N 4 , is deposited to extend into the apertures at 26A, 26B, e.g. for the gate insulant layer of an IGFET. Layer 24<SP>1</SP> overhangs the perimeters of the apertures, and evaporative deposition of a conductive layer produces regions 27-29 overlying layer 24<SP>1</SP> and electrically separated localized regions 30, 31 overlying 26A, 26B. (Fig. 3) and aligned with the overlaps. Conductors 28, 30; 27, 31 are interconnected by depositing a photo-resist mask leaving the desired regions of connection exposed and conductive material, e.g. Au, is selectively deposited at 33, 34 (Fig. 5), e.g. by electroless plating on conductors 27 to 31 of composite Pd over Ti, in a bath of KAu (CN) 2 +KCN+ KOH+2KBH4 after which the mask is removed by solvent.  In a modification (Fig. 6, not shown) a layer of e.g. combined Ti and Pd is continuously deposited over regions 24<SP>1</SP>, 26A, 26B and a layer of Au is deposited thereon, and etching through a photo-resist mask leaves composite connecting electrodes extending between the plateaux and indentations (Fig. 7, not shown). Alternatively a thin conductive layer may be deposited over the surface of the device (Figs. 7, 8, not shown) without bridging the overhangs, to form conductive elements common with the composite connecting electrodes which overlie the outermost layer of insulant. Alternatively the outermost continuous composite conductive layer of Au (Fig. 6, not shown) is masked and selectively etched leaving portions overlaying the continuous composite layer of Ti and Pd, with further etching to establish discontinuities at the overhangs of the apertures. The composite layer may be of Al and W. In a further modification the structure is masked and etched to remove selected portions of the insulant overhang of the apertures (Fig. 9, not shown) and to radius the removing angles, and a thin conductive layer discontinuous at the overhangs and continuous at the radiused angles is deposited to produce the electrodes, which may be plated up over photo-resist masks to increased thickness (Fig. 10, not shown) The finished structure may be lightly etched to remove spurious inter-electrode bridging. The process is applicable to 2 phase charge coupled devices and to multilevel metallizations of integrated circuits demanding zero effective lateral spacing between adjacent electrodes.