Patent GB-717122-A (GB)
Title: Improvements in or relating to beat frequency oscillators
Inventor: NOBLE SPENCER WATKINS
IPC: H03L7/183
Filed: 1951-03-30
Abstract: 717,122. Valve generating circuits; pulse frequency dividers. NATIONAL RESEARCH DEVELOPMENT CORPORATION. March 24, 1952 [March 30, 1951; Nov. 2, 1951], Nos. 7493/51 and 25722/51. Class 40 (6). [Also in Group XXXV] An oscillation generator more particularly for producing a very low frequency comprises a master oscillator of frequency f, a subsidiary oscillator of frequency nf, a frequency divider for producing a frequency nf/(bn+a) from the frequency nf and a sampling circuit adapted to sample the ouput t of the master oscillator under the control of the output of the divider to produce an output of frequency Af/(bn+a) where a and b are integers, b being positive and A is the modulus of the difference between (bn+a) and the nearest multiple of n. In Fig. 1 the subsidiary oscillator is a pulse generator with an automatic control circuit 2, 3 (described below) for maintaining its frequency at n times the frequency f of the master oscillator. The subsidiary oscillator is connected to a circuit which divides the input frequency by (n+1) to produce an output frequency and this controls a circuit which samples the output of the sine wave master oscillator on the occurrence of each of the divided frequency pulses and produces a stepped wave output, the amplitude of each step being proportional to the mean operates in the same way as that from the pulse instantaneous amplitude of the master oscillator output during the pulse and the envelope of the steps having a frequency A low pass filter may be connected in the output to remove the harmonics. More generally, the divider may divide by (bn+a) so that the sampler operates on every bth cycle of the master oscillator and the output frequency is then Af(bn+a) where A is as defined above. The ouput frequency is varied by varying the master oscillator frequency and range changing is effected by varying n. The frequency divider (Fig. 2) comprises a series of scale-of-two counters 12 which produces 1 pulse for every n pulse applied to it, the input pulses however being applied through a normally open gate which removes 1 pulse in every n+1 so that one output pulse is produced for every n+1 applied to the divider. Each output pulse operates a 2-stage trigger which in turn opens a gate 15. This gate is fed with the input pulses delayed in a re-align circuit by half the interval between the pulses. The first delayed pulse to pass through gate 15 operates a scale-of-two counter which closes the "open" gate. The second delayed pulse causes the scale-of-two counter to re-open the " open " gate and to reclose the trigger. This re-closes the gate 15 which is not opened again until the next divider output pulse occurs. The open gate thus removed one pulse only. However, modification of the scale-of-two counter may cause any number a of the pulses to be removed and modification of the counter 12 may cause the circuit to divide by bn+a. The sampling circuit is of the type claimed in Specification 717,160 and comprises basically an amplifier, Fig. 4, having a capacitive Miller feedback path of large time constant. The sine wave input is applied via a switch which makes simultaneously with the occurrence of the input pulses and which connects a resistance across the capacitor to reduce the the time constant. The capacitor accordingly charges to the instantaneous value of the sine wave and retains the charge until the next pulse when it takes up a value corresponding to the new amplitude of the sine wave. A stepped output is accordingly produced at 524. The switch takes the form of two diodes V5b and V6b, Fig. 5, which when conducting connect respectively the negative and positive halves of the sine wave derived from the master oscillator via an amplifier 519 and the feedback resistor 526 to the input of a valve V7. Biasing potentials applied via diodes V5a and V5b render the former diodes normally non-conducting but the pulses which are applied at 512 to a paraphase pulse forming circuit render the diodes conducting during the incidence of the pulses. The valve V7 is provided with a capacitive feedback path 525 fed from a cathode follower V8 and the sampled output is obtained from terminal 524.