Patent GB-1088331-A (GB)
Title: Information storage system
Inventor: AULT CYRUS FRANK
IPC: G11C17/02
Filed: 1964-09-17
Abstract: 1,088,331. Data processor; digital electric storage device. WESTERN ELECTRIC CO. Inc. Sept. 17, 1964 [Sept. 25, 1963], No.37965/64. Heading G4A. [Also in Division H3] A semipermanent data store has an access arrangement comprising a matrix array of magnetic cores, the energizing circuit for the rows and columns including normally closed shunt switches connected in parallel with the rows and columns respectively. As described, a semipermanent data store comprises a plurality of storage modules, each module consisting of a plurality of storage planes, each plane, Fig. 2, comprising a double matrix array of magnetic wire memory elements, such as described in Specification 877,731, a column wire such as 13b, Fig. 2, comprising a conductive wire having wound thereon in a helical spiral magnetic tape, and being associated with a return conductor 14. The memory elements are energized by passing a current along an energizing wire such as 11 1 , called a " strip solenoid," each strip solenoid being common to one row of each of the two associated planes A (front) and B (rear) of the matrix. The semi-permanent storage of data is achieved by means of cards 15 carrying permanent magnets 17 at locations corresponding to the cross-points of the matrix, the presence of a magnet corresponding to a " 0 " and its absence to a " 1," the cards 15 being of electrically conductive material such as aluminium to concentrate the flux produced by the solenoids 11 &c., and being replaceable if it is desired to change the stored data. The effect of a magnet 17 is to prevent a flux reversal in the associated helical magnetic element when a read current is passed along the associated strip solenoid such as 11 1 . Instead of having permanent magnets 17, the cards 15 may be provided with magnetizable areas which are magnetized at the locations where it is desired to store a " 0." In addition to the permanent magnets 17, the cards 15 carry further permanent magnets (Fig. 3, not shown) arranged between the storage rows and effective whenever a card is inserted or withdrawn to premagnetize the parts of the helical storage areas of the column wires 13a 11 , 13b 11  &c., which lie between the storage cross-points. The two magnet cards 15, 16 of each storage matrix are retained in position by non-magnetic plates 20, 21 carrying spring clips 22, the complete matrix plane being shielded from interaction with adjacent matrices by shield plates 23, 24 of magnetic material. The column wires 13a 1  and associated return conductors are mounted in a flexible " a tape," Fig. 4, common to all the A matrix planes in a module, there being a similar arrangement comprising a " b tape " for the B planes. The column conductor in each tape is coupled to its return conductor 14 directly at one end and via a transformer primary (Fig. 6, not shown) at the other end. The complete memory comprises 16 modules arranged in a 4 x 4 co-ordinate array (Fig. 5, not shown), the modules being arranged in four groups to assist in noise reduction, the output transformers of corresponding column conductors being connected in parallel to a common output transformer primary (Fig. 6, not shown). Access circuits.-Each strip solenoid such as 11 1  is coupled to a toroidal magnetic core 12 which may be switched by passing current through conductors 44, 45, Fig. 2, threading the core. The cores are threaded by a biasing conductor (Fig. 7, not shown) effective to maintain the cores normally in a state opposite to that to which they are switched by the conductors 44, 45. Each strip solenoid corresponds to an A and a B word each of 44 bits, there being 64 matrix planes as in Fig. 2 in each of the 16 modules constituting the memory which thus stores 131,072 44-bit words. The access switch comprises a 256 x 256 co-ordinate array of cores, each core corresponding to the two words of the associated strip solenoid. The cores of the access switch are selected by enabling one of a set of sixteen selector switches 111-0 to 111-15, Fig. 8, and one of a set of sixteen switches 112-0 to 112-15, the switches 111, 112 being connected at opposite ends to different groups of X energizing windings for the cores 12; by energizing similar switches 131 in the Y direction; and then passing a constant current to the selected core from a source 115 normally connected via a current shunt switch 116 and filter network to earth, the alternative path being via the switches 111, 112, the selected core 12 and a series switch 127, there being corresponding circuitry 131, Fig. 8, for the Y direction. The X and Y selection switches are activated simultaneously during an interrogation operation under the control of timing signals from a timing circuit 132 via timing conductors 133. A voltage pulser 134 also controlled by the timing circuit 132 is effective to reduce noise during an interrogation. The selected core is returned to its original state at the conclusion of the switching pulse by means of a bias winding threading all the cores. A tracking circuit (Fig. 13, not shown) is effective to maintain the bias current at its correct value. Address selection switches (Figs. 8, 9, 10, 11, 21, 23, 25, 30, not shown).-Each address selection switch such as X111-0, Fig. 11, comprises an input AND gate consisting of diodes 152 connected to the outputs of the address register together with a further input via a diode 151 for receiving a timing pulse which is effective to open the enabled AND gate of the selected switch thereby saturating a transistor 157 to enable a switch transistor 164 via transformer windings 161, 163. The transistor 164 will then be effective to provide a path for the pulse input via diode 167. Current shunt and series switches.-The current shunt switch 116, Fig. 9, is normally effective to pass a constant current from a lead 118 via normally conductive transistor 212 and filter network 117, this network being provided to minimize transient currents and to reduce noise in the readout circuits. The shunt switch 116 is opened by applying a positive pulse to a lead 220 thereby switching on a normally non- conducting transistor 224 thereby energizing a transformer 226 which applies a current pulse to saturate a transistor 230 thereby turning off transistors 213, 212 to open the switch 116. The current series switch 127, Fig. 10, is identical to the current shunt switch, the voltage drop across the switch 127 when the switch is opened being limited by a limiter 129, Fig. 10, comprising a voltage regulator and a normally non-conducting transistor 238, the voltage regulator including a capacitor 237 and Zener diode 244. The transistor 238 conducts when the potential difference between conductors 235, 236 exceeds the potential on a capacitor 237. A damper circuit, including a Zener diode 251, Fig. 10, is effective to prevent ringing due to the inductive load presented by the X conductors of the core array. A second limiter circuit 128 (Fig. 14, not shown) is connected across the load presented by the X conductors, the operation being substantially similar to that of the limiter 129, but the voltage regulator differs. A further limiter circuit 119, Fig. 9, is effective only if the limiters 128, 129 fail to operate. Voltage pulser.-To prevent dissipation of the energizing pulse, the stray capacitance presented by the unselected windings of the core array is precharged by a voltage pulser 134, Fig. 8, whose construction (Fig. 14, not shown) is similar to that of the current shunt and series switches described above. Readout circuits-general arrangement.-As stated above, the access cores of the memory are arranged in four module groups, each group consisting of four matrix modules. The output wires from the respective module groups are connected to corresponding selector circuits, Fig. 23; there being 44 selector circuits for each of the four module groups since 44-bit words are stored in the memory. The appropriate selector circuits are energized in accordance with the address of the word to be read from the memory, the selection of the A or B word associated with each address being effected at this stage. The output signals are strobed and amplified for transmission to output circuits. Selector circuit. Fig. 23.-Each selector circuit 350-0 comprises identical sections 360-Oa and 360-0b only one of which is selected in accordance with whether an A word or a B word is required. The group of selector circuits corresponding to the stored word to be read is selected by applying earth potential to leads 393G of each selector circuit in that group, the a or b selection being effected by applying a positive potential to leads 382A or 409B respectively. Assuming that circuit 360-Oa, Fig. 23, is selected, amplification of the input signals at a transformer primary 50a is effected by a class A amplifier comprising transistors 361, 362, the output being through transformer windings 373, 373<SP>1</SP>. There are three feedback paths, resistors 372 and 369 forming a D.C. feedback which determines the operating point of the amplifier. Resistor 363 and capacitor 364 provide D.C. and A.C. feedback to make the input transformer winding 371 see a lower impedance than the base of transistor 361. Resistor 407 provides A.C. feedback from the selected output coupled through resistor 405 and windings 399 and 406 and is effective to raise the impedance seen by winding 371. Frequency response is controlled by the high frequency roll-off due to capacitor 364. The outputs of the selector circuits associated with corresponding bit positions are connected to readout amplifiers 450-0 to 450-43 (Fig. 27, not shown) comprising transistor class A amplifier, the outputs of these amplifiers being connected to sampler circuits 500-0 to 500-43 (Fig. 29, not shown) responsive to strobe inputs from timing circuits to produce from pulses input thereto which represent a " 1 " by positive or negative potential accord