Patent GB-977317-A (GB)
Title: Data processing system
IPC: G06F11/10
Filed: 1961-09-20
Abstract: 977,317. Data transfer apparatus. RADIO CORPORATION OF AMERICA. Sept. 20,1961 [Oct. 14,1960], No. 33733/ 61. Heading G4A. A data transmission arrangement comprises two circuits between which transfer is to be effected, a first bus to which data signals from one of said circuits may be applied, a second bus to which the data received from the first bus by the other circuit may be applied, and a circuit for terminating the application of signals to said first bus in response to equality of bits on said two buses. Thus, when transmitting data between registers, computer speed can be improved by the use of shorter command pulses for registers which are physically close together and longer command pulses'for registers which are further apart from each other. Means for checking that the datatransmitted represents binary information are provided, the data being compared with its complement. Parity checking means are also provided. As described, a data word is transferred from a flipflop register 10 to a flip-flop register 14, Fig. 1, under the control of a control pulse generator 30. The register 14 is initially reset and then output gates (not shown) of the register 10 are enabled to cause the word stored therein to appear via leads 48 on a bus RT2 and in complement form on a bus T1. Circuits in a central control system 31 sense when the input gates to the register 14 are enabled and in response thereto enable the output gates of the register 14 leading to a bus RT1. A parity check circuit 18 checks the parity of the word transmitted from the register 10 by the bus RT2. A comparator 26 compares the words on buses RT1,RT2 and if they are equal, sends a signal via a delay 28 to the control pulse generator 30 to terminate the transfer operation. As described, the registers store words of three data bits plus one parity bit. Information checking circuits, Fig. 3. The circuit 20, comprising three "none" gates 51-53 connected to the data leads of buses RT1,T1,is arranged to provide an output A = 1 in the absence of a binary digit on one of the wires of the RT1 bus. The circuit 22 provides an output B = 1 in the absence of a binary digit on one of the wires of the RT2 bus, and circuits 24, 26 provide respective outputs L = 1, M = 1 in the absence of parity bits. Parity circuits, Figs. 4-11 (not shown). The circuits 16,18,36,38, 40 are shown in detail in Figs. 4-11 and comprise arrangements of "none"  and "and" gates. The circuit 16, Fig. 1,for the RT1 bus, is enabled when A = 0 indicating that the information test circuit, Fig. 3, has detected information, and produces an output C = 1 when an error is present. A circuit 18 performs a similar function for bus RT2. These circuits are connected to further logical circuits, Figs. 5, 7, the output of Fig. 5, E = 1 indicating that parity is correct and that of Fig. 7, F = 1 when parity is incorrect. Circuits 36,38,40 provide outputs α#,γ which when they have the value " 1" act as inhibiting inputs to the comparator circuit. Comparator circuit, Fig, 11. This comprises "and" gates such as 120 and "none" gates such as 122 and four output "none" gates 131-134 connected to a common output line 129 which normally carries a "1" signal. The signals α, # and γ are also applied as shown in the circuit and a "0" output is produced only if all of α,#,γ are "0". Central control system Fig. 12. Instructions are stored in a memory 200 which may comprise magnetic cores. The instructions are read out into a register comprising flip-flops 201-205, the first control pulse CP1 resetting the register and the second pulse CP2 reading out the next instruction into the register. Control pulse CP3 enables "none" gates 211-218 to provide output control signals as determined by the instruction in the instruction register. The signals select the registers and buses involved in the required transmission of data.