Patent GB-753025-A (GB)
Title: Magnetic switching devices
IPC: H03K17/80
Filed: 1954-02-05
Abstract: 753,025. Circuits employing bi-stable magnetic elements. RADIO CORPORATION OF AMERICA. Feb. 5, 1954 [Feb. 20, 1953; April 1, 1953], No. 3497/54. Class 40(4). [Also in Groups XIX and XL (c)] In a magnetic switch of the kind used for setting information in a matrix magnetic memory and comprising a number of saturable cores associated with windings which reverse the magnetic polarity of a single core from " N " to " P " when selectively energized, partial demagnetization of unselected cores which occurs as a result of ineffective " P " magnetizing current in an associated winding is reduced by biasing all the cores in an " N polarizing direction over a common D.C. or pulse-energized winding. The bias may in addition effect automatic restoration of a selected core to an " N " polarity when the selecting currents terminate. Saturable cores are also employed in the magnetic memory which has column and row windings connected to individual output coils of the cores of a pair of magnetic switches. A pulse is induced in an output coil each time a selected core in a switch reverses-its polarity, the coincidence of pulses in a row and column causing the polarity of a single core in the matrix to reverse. Memory arrangements of this kind are described in the publication R.C.A. Review Volume XIII, June 1952. When it is required to reset the memory the two switches are restored simultaneously. This induces coincident pulses in the output coils of the selected cores which restore the appropriate memory core to the normal " N " condition. If information is to be retained in the memory the induced pulses are made non- coincident by restoring one switch after the other. A magnetic switch is shown in Fig. 1 and comprises cores 10 having selecting coils 14, 16 arranged in series to form column and row windings C1-C4, R1-R4. each core also including an individual output coil 18 and a bias coil 28 forming part of a common bias winding 26. To select a particular core the associated column and row windings are energized, the combined effect of the currents being just sufficient to reverse the magnetic polarity of the selected core. The bias reduces the partial excursion of fluxes in certain of the unselected cores which is caused by Current flow in one of the associated row and column windings, as well as causing automatic restoration of the selected core when the energizing currents terminate. Alternatively, restoration may take place only when a pulse is applied to the bias coil. The cores may be re-arranged to'lie in a single plane as shown in Fig. 3. In this arrangement the cores are biased by selecting current passing through winding 26 and two of the windings C1-C4, R1-R4. This current has to be increased to restore the selected core; this takes place when tube 40 is fired by a pulse. A sixty-four core memory 50 controlled by two switches comprising core sets 60, 62 is shown in Fig. 4. The memory is continuously or pulse inhibited at 64. Three out of six inputs to each switch are energized to select a particular core, the selecting windings each comprising combinations of " N " inhibiting and " P " driving coils. When a selected core changes its polarity during the selecting or restoring operation of a switch, a pulse of appropriate polarity induced in the output coil is applied to the associated column or row winding C51-C58, R51-R58 of the memory. When a memory core changes its polarity it induces a pulse in its output coil 66. By continuously energizing the inhibiting winding 64, restoration of the memory takes place independently of the switches. An arrangement in which primary magnetic switches control a secondary magnetic switch is shown in Fig. 5. Each primary switch has four inputs, two of which are energized for the selection of a single core 102, 112. One primary switch is associated with groups of the cores 90 in the secondary switch, while the other is associated with the single cores in each group. All the switches are biased as previously described. The bias arrangement may be applied to a cubic array of cores. Three sets of selecting windings are required in this case, each set of windings coupling all the cores in a different plane. By arranging the bias to have double the influence on a core than that of a selecting coil, only the selected core will receive a " P " magnetization. A further switch arrangement is shown in Fig. 6 in which each core is assigned a binary number. Four selecting windings are provided, each winding comprising a combination of " N " and " P " coils. Binary energization of the selecting windings changes over a single core when a " P " magnetizing winding 128 is simultaneously energized, e.g. for the number 0111 the windings 128, 122, 124 and 126 are energized. Parallel inhibiting windings 140, 142 are used, adjustment of current through 142 enabling the cores to be operated at a point of optimum efficiency. It is suggested in the Specification that the feature of automatic restoration of a selected core by the bias permits the use of core materials having low coercivity, and also that it is not essential to magnetize a core to saturation in the " P " direction. A 100-output switch which provides the X or column inputs to a matrix memory (not shown) is illustrated in Fig. 10. The inputs Xx, Yy to the column and row windings respectively of the X switch are applied over gating tubes VC1- VC10, VR1-VR10. A circuit PC is provided for controlling the X switch and a further switch Y (not shown). An input to PC at 18 is in pulse form and is converted into a rectangular pulse MP of given length by a pulseforming circuit 19. This pulse is applied over cathode followers 20, 22 to the X and the Y switches and opens all the column and row gates for the duration of its reception. A further pulse PP which is longer than pulse MP is produced by a pulse former 24, and after passing through a pulse coincidence gate 25 is associated at tube 30 with the MP pulse circuit to switch Y. The pulses MP, PP commence at the same instant. If gate 25 is closed pulse MP only is applied to X and Y. The inputs to both switches are therefore terminated at the same instant when the pulse MP ends, and the selected core in each switch is automatically restored to " N " by the bias. The selected core in the matrix memory is in turn restored to " N "by the coincident induced output voltages from the switches. When gate 25 is-open the longer pulse PP is applied to switch Y which therefore restores to normal later than X. The selected core in the memory thus remains in a " P " magnetic state. To open gate 25 a register 26 is operated by a tripping pulse from sources 27, 28. If the information set in the memory is to be stored, a " write P " pulse is transmitted from 28 to register 26. To read out the stored information a further pulse MP is generated. As gate 25 is closed in this instance, both switches restore simultaneously and drive the selected memory core to " N ". If the read-out information is to be restored in the memory a further pulse MP is produced and the gate 25 is opened by a " restore P " pulse transmitted from 27, the latter operation being subject to continuation of the original input signals at the X and Y switches or application of the read-out information to the appropriate column and row windings of the memory. A modification of circuit PC in which pulse MP is longer than PP is described with reference to Figs. 10A and 10B (not shown). The pulse PP is of opposite polarity to MP and is produced by way of a delay circuit so that the pulses terminate at approximately the same time. If retention of a " P " condition in the memory is required, the gate 25 is opened so that pulse PP suppresses the latter part of MP applied to the Y switch. In Fig. 11 is shown a memory arrangement for use in a binary system in which a single binary digit is allotted to each of a number of parallel inputs, and as many matrix memories MM1- MM3 are provided as there are binary digits. The memories have individual Y-switches SMY1-SMY3 controlled by a common Y input and a single X-switch SMX, although separate X switches could be used. The same position is selected in each matrix for a given code input. The X and Y inputs are applied to the corresponding switches only when gates VC, VR are opened for the duration of a pulse MP produced by a pulse former 19. Each Y switch has common to all its cores a pulse winding 28P which is in addition to the D.C. bias winding 28D. Alternatively, a single winding may serve for both purposes, Figs. 12B and 12C (not shown). A selected Y-switch core will only change to a " P " polarity if the common pulse winding is energized. This triple coincidence can only arise if gates 3 are opened so that pulse MP passes through tubes 23Y1-23Y3 to the pulse windings of the respective switches. Gates 3 are opened only when the associated gates 1 and 2 are closed, and in this condition permit registration of the X and Y inputs to take place in each of the memories during the operative time of MP. A second pulse shorter than MP and commencing at the same time is produced by a pulse former 24 and applied to all the gates 1 and 2. These gates cannot be opened during the time the second pulse is received. To store a " P " condition in any of the memories the associated Y switch SMY1-SMY3 is restored to normal before the X switch SMX. This is effected by applying a " write P " pulse to the appropriate gate 2 which opens at the termination of the second pulse from 24 and closes gate 3. The remaining memories are restored to normal when gates VC, VR are closed simultaneously at the termination of pulse MP, as the D.C. bias automatically restores all the switch cores to the " N " polarity. Gate 1 is used to restore a selected memory core to the "P" state after reading out the stored information, provided that the input signal and pulse MP are still effective. To read out,