Patent GB-1341252-A (GB)
Title: Digital clocks
IPC: G04G5/02
Filed: 1971-04-19
Abstract: 1341252 Electronic timepieces GENERAL ELECTRIC CO 19 April 1971 [6 April 1970] 26333/71 Heading G3T An electronic clock with digital electroluminescent numeric time-display, during normal operation receives at input 1, Fig. 1, of a rate control logic circuit 3 (detailed Fig. 3, not shown), a clock reference signal at 60 Hz and at a first voltage level of 9 volts. This signal is frequency divided and applied to counters, decoders and transistor switching circuits to activate appropriate time display elements, as described later. Setting In order to set the clock however e.g. if it is slow, a reference signal at a higher voltage and same frequency (60 Hz) is applied at input 1, causing the rate control circuit to produce a "fast set" control signal which is applied to a gate 15. Thereby the gate is caused to pass 60 Hz signal from a line 21 directly to a line 25, instead of via frequency dividers 7, 11, and thereby the clock counters 27, 59, 77 and time display are rapidly advanced. For "slow setting" a clock reference signal at a voltage intermediate the normal condition and fast set values is applied at input 1. The rate control circuit consequently causes the gate 15 to pass signals at 2 Hz from divider 7 via line 23 and line 25 to the counters to advance the time display at a slow rate. Clock Operation In normal "time display" operation minute pulses from divider 11 are passed by gate 15 to counter 27 which applies a pulse every ten minutes to counter 59 which in turn supplies a pulse every hour to counter 77. The outputs of the counters on multicore lines 55, 73, 95 are sequentially switched by a matrix switch 53, in response to switching signals from a strobe decoder 143, to a binary decimal decoder stage 157. The strobe decoder receives from strobe counter 137 a binary count from 0 to 2 at 3À33 KHz. The counter 137 has an input at 10 KHz via line 135 from an oscillator (not shown). In decoder 143 the binary information is decoded to provide decimal outputs from 0 to 12 which are applied to a 7-bar decoder 167 which selects appropriate bars of four parallel connected 7-bar display devices V1 to V4, Fig. 5, thereby to provide a corresponding digital display. The binary output of the strobe counter 137 is also supplied via lines 185, 187, Fig. 1 and Fig. 5, to control transistor switches TR4 to TR6 which cause energization of filaments in the display devices V1 to V4 thereby enabling them. As a result the display devices are activated sequentially and selectively in synchronism with the sequential application of the tens of hours, hours, tens of minutes and minutes outputs from the 7-bar decoder 167. (The outputs of decoder 167 are applied via lines 171, 173 175, 177, 179, 181, 183 to respective electrodes V 1  V 2  V 3 . Since tube V 4  is required to display numeral "1" only, the output line 169 is connected to a pair only of the electrodes of V 4 ). Alarm An alarm compare circuit 43 provides an indication signal in a line 133 when the time appearing at counters 27, 59, 77 becomes the same as a pre-set alarm time appearing at alarm counters 33, 113 and this signal may be used to activate a suitable alarm device e.g. a buzzer. This signal is also passed by gate 15 to strobe decoder 143 which applies sequential switching signals via lines 153 and 155 to matrix switch 53. Thus binary outputs of the alarm counters in lines 131, 109 are switched by matrix 53 sequentially to the decoder stage 157. The counts of the alarm counters are thus displayed on the display device in the same manner as that of the clock counters and is advanced (at slow set) as the desired alarm setting is reached. The clock reference signal applied via line 1 is a square waveform and the three voltage levels are selected from a voltage divider R5 R6 R7 and TR3. The rectified voltage across the divider is regulated by a circuit including TR1, TR2 and the square waveform is produced by switching TR3 at supply frequency by means of R4, C2.