Patent GB-1429379-A (GB)
Title: Lsi programmable processor
IPC: G06F9/26
Filed: 1973-07-24
Abstract: 1429379 Microprogrammed processors BURROUGHS CORP 24 July 1973 [20 Nov 1972] 35171/73 Heading G4A A micropgram memory 14 is addressed by command information received over a serial input bus DATA IN to retrieve selected microinstructions for controlling a logic unit which performs arithmetic and logic operations on data information received over the input bus and provides an output to a serial output bus DATA OUT. The logic unit includes a plurality of A registers A1-A3, a B register, a serial adder and logic circuit 30 and selection gates 36, 38, 40, 42 for routing the adder output to a selected A or B register and for selecting the X and Y inputs of the adder. The B register may also be loaded from the input bus serially by bit or in parallel by a literal value (e.g. data, jump address, shift amount) from a microinstruction via decoder 46. The microprogram memory 14 is addressed by a program counter MPCR which may be incremented by 1 or 2 and which is provided with parallel transfer paths 92 for exchanging its contents with those of an alternative program counter AMPCR which is used to store jump and return addresses and which can also be loaded serially from the adder 30 via gates 36 or in parallel with a literal value from decoder 46. Register AMPCR can be selected to provide the Y input to the adder, the other possibilities being the true and false outputs of the B register. The following types of microinstruction are described. The literal assignment microinstruction causes loading of the B register or AMPCR with a literal field contained in the microinstruction, and a variation of this microinstruction loads the literal value of the microinstruction into AMPCR and then transfers it to MPCR as a jump address. The condition test microinstruction has a condition field specifying one of the following condition registers to be tested (a) MST which is set by the most significant bit of the adder output (b) AOV which is set upon an overflow condition occurring in the adder (c) LST which is set by the least significant bit of the adder output (d) ABT which is set when the adder output is all 1's (e) three local condition registers LC1- LC3 and (f) an external condition register EXT settable by a control signal from another unit in the system of which the processor forms part. The microinstruction also includes a set field for setting one of the local condition registers LC1-LC3 if the specified condition register is set, and true and false successor fields which define the next microinstruction in the sequence, depending on the true or false result of the condition test, by specifying whether MPCR is to be incremented by 1 (STEP) or 2 (SKIP), or incremented by 1 and the result saved in AMPCR (SAVE), or whether MPCR is to receive the contents of AMPCR (JUMP). The logic unit microinstruction specifies one of 16 arithmetic and logic operations, Fig. 6 (not shown), the source registers for the X and Y inputs to the adder (the B register output may be complemented) and the destination register for the result. Some logic unit microinstructions provide for transfer of information to the B register from an external source while the adder output is transferred to a specified register, and if the B register is specified the adder output and externally supplied data are ORed together before entering the B register. The external (or device) microinstruction includes a literal value which is transmitted over the out bus via the memory buffer.