baber/WOPTO huggingface dataset:
Patent TW-232057-B (TW)
Title: A sub-assembly for a spring-regulated pressure regulator and method of making same
Inventor: ALSOBROOKS DANIEL E
IPC: G05D16/04
Filed: 1993-08-31
Granted: 1994-10-11
Abstract: A fluid pressure regulator of compact construction including an improved diaphragm-valve assembly interposed between a flow body (20) and a second body cap element (50). The flow body has an inlet and outlet passage (22, 30) and a valve cavity with a centrally disposed ported valve insert (40) to allow the regulated passage of fluid. Mounted to the flow body, the cap element confines a diaphragm (70) of the diaphragm-valve assembly and houses an adjustable coil-spring (120) biased against the assembly. The diaphragm-valve assembly includes a ring-shaped diaphragm element (70) interlocated between a circular element (75) central to the diaphragm and a diaphragm compression limiting clamp plate ring (90). The circular element has a central recess (78) over the valve insert which houses a spring- backed self-aligning ball valve element (80) having a flat chordal surface (82) adjacent the insert. A convolute (100) in the diaphragm element provides a more consistent effective area in relation to the valve stroke during operation improving pressure regulation and reducing stretching of the diaphragm preventing tearing, rupture or undesirable hysteresis.
Patent TW-262551-B (TW)
Title: Device for the testing of coins or flat articles
Inventor: WEILENMANN YVES
IPC: G07D5/02
Filed: 1994-08-29
Granted: 1995-11-11
Abstract: A device for testing the authenticity of coins, tokens or other flat articles has two light barriers (L1,L2) which are arranged at the same height (h) on a path inclined relative to the horizontal (H) at an angle (theta) and which have a mutual spacing (L). The coin (M) to be tested initiates a time measurement when it starts to mask the first light barrier (L1). From the further measured moments t1 to the end of the masking of the first light barrier (L1), t2 at the start of the masking of the second light barrier (L2) and t3 at the end of the masking of the second light barrier (L2), the chord length (B) of the coin (M) can be determined, on the precondition that the coin (M) undergoes an approximately constant acceleration from the moment to of the start of the masking of the first light barrier (L1) to the moment t3 of the end of the masking of the second light barrier (L2). The initial speed of the coin (M) and its initial angular speed play no part in this.
Patent TW-470734-B (TW)
Title: Method of coating a copper film on a ceramic substrate
Inventor: YOSHIZAWA IZURU
IPC: C23C18/28
Filed: 1995-01-27
Granted: 2002-01-01
Abstract: A method of forming a copper film on a ceramic substrate comprises the steps of forming an undercoat containing copper on the ceramic substrate, heat-treating the undercoated substrate in an oxidation atmosphere to obtain a copper oxide layer in a surface of the undercoat, reducing the copper oxide layer to a metallic copper layer within a bath of a reducing solution, and forming an additional copper layer on the metallic copper layer to obtain the copper film. As the reducing solution, a solution of a boron hydride salt, dimethylamine borane, or the like, can be utilized. In particular, when the reducing solution is of dimethylamine borane, the reducing step can be performed at a temperature between 30 DEG C and 50 DEG C.
Patent TW-251370-B (TW)
Title: Read only memory array
Inventor: WU DER-SHUENN
IPC: G11C5/02
Filed: 1995-02-21
Granted: 1995-07-11
Abstract: A read only memory array installed on a semiconductor substrate includes multiple word lines and multiple buried diffusion bit lines vertical to the word line, and forming a memory cell field effect transistor on the intersection of any on word line and any two neighboring buried diffusion bit lines, which constitutes a array structure, and the neighboring four columns of the memory cell field effect transistor constitue a stacked layer passed through by two metal bit lines. The read only memory includes: - multiple stacked layers select field effect transistor, each stack with a stack select field effect transistor coupled to the buried diffusion bit line between the second column memory cell field effect transistor in the stack and the third column memory cell field effect transistor, and passing the first metal bit line of the stack, controlling its operation through a stack select line coupled to its gate; - multiple the first column select field effect transistor, each stack with two first column select field effect transistor, one's source/drain in parallel connection with the source/drain of second column memory cell field effect transistor. the other's source/drain in parallel connection with the source/drain of third column memory cell field effect transistor, controlling its operation through a first column select line coupled to its gate, used to constitute the path for reading the first column memory cell field transistor and the forth column memory cell field effect transistor; - multiple the second column select field effect transistor, each stack with two first column select field effect transistor, one's source/drain in parallel connection with the source/drain of first column memory cell field effect transistor. the other's source/drain in parallel connection with the source/drain of forth column memory cell field effect transistor, controlling its operation through a first column select line coupled to its gate, used to constitute the path for reading the second column memory cell field transistor and the forth column memory cell field effect transistor; - multiple coupling device, each stack with a coupling device coupled the second metal bit line of the stack and between the stack and the buried diffusion bit line of next stack. By the stack control line and the control of the first column select line and the second column select line, there forms a read-out loop between the first metal bit line and the second metal bit line.
Patent TW-269074-B (TW)
Title: Circuit which includes cells with high fanout requirements which has a reduced RC delay
Inventor: STEVEN CRAIG BARTLING
IPC: G06F17/50
Filed: 1995-07-10
Granted: 1996-01-21
Abstract: A circuit is provided that reduces the RC delay due to the high fanout requirements of a particular cell in the circuit. The reduction is accomplished by providing a copy of a cell which has the high fanout requirements and then utilizing that copy to drive a cell which is part of a faster path in the circuit. In so doing, the fanout required for the various functions of the circuit is greatly reduced. The circuit provides for significant advantages as the size of the circuit, such as an adder or the like increases.
Patent TW-268174-B (TW)
Title: Software protection method and device
Inventor: SHYU SHYH-BIN
IPC: H04L9/14
Filed: 1995-08-18
Granted: 1996-01-11
Abstract: A data transmit protecting method used for preventing transmitted data by broadcasting from being illegal received and used, comprises the steps of: on the transmit end encrypting the data that will be transmitted by one time-related procedure; transmitting the encrypted data via a medium to receive end; and on the receive end decrypting the received data by one time-related procedure, if the decrypting and encrypting time signal of host computer on the receive end is synchronous, then output data of decrypting procedure is correct, otherwise, then output data of decrypting procedure is incorrect.
Patent TW-357147-B (TW)
Title: Process for the preparation of a tetrazole derivative in two crystalline forms and novel crystalline form of said derivative
Inventor: CARON ANTOINE
IPC: A61K31/415
Filed: 1995-10-18
Granted: 1999-05-01
Abstract: Process for the preparation of 2-n.butyl-3-[(2^-(tetrazol-5-yl)biphenyl-4-yl]methyl]-1,3-diazaspiro[4,4]-non-1-en-4-one by reaction of the corresponding nitrile with an alkaline azide and triethylamine hydrochloride, recxovering the 2-n.butyl-3-[(2^-(tetrazol-5-yl)biphenyl-4-yl]methyl]-1,3-diazaspiro[4,4]-non-1-en-4-one in form of one of its alkaline salts in aqueous solution, by neutralization of said alkaline salt and crystallization of the 2-n.butyl-3-[(2^-(tetrazol-5-yl)biphenyl-4-yl]methyl]-1,3-diazaspiro[4,4]-non-1-en-4-one, thus precipitated either in a solvent containing less tha 10% of water or in a solvent containing more than 10% of water, in order to obtain 2 different crystalline forms; furthermore a novel crystalline form of 2-n.butyl-3-[(2^-(tetrazol-5-yl)biphenyl-4-yl]methyl]-1,3-diazaspiro[4,4]-non-1-en-4-one and pharmaceutical compositions containing it are described.
Patent TW-390900-B (TW)
Title: Pigment preparation and its use
Inventor: HEINZ DIETER
IPC: C09D11/037
Filed: 1995-10-20
Granted: 2000-05-21
Abstract: The present invention relates to a pigment preparation consisting essentially of one or more lustre pigments, a phosphate derivative and spherical particles having a particle size of 0.05 -150 <mu>m and to its use, especially in printing inks.
Patent TW-283266-B (TW)
Title: Multi-level ROM structure and fabrication method thereof
Inventor: SHYU JENN-TSONG
IPC: H01L27/112
Filed: 1995-12-21
Granted: 1996-08-11
Abstract: A multi-stage ROM structure comprises: multiple first buried bit lines formed in parallel and spaced way on silicon substrate; thin oxide formed on silicon substrate between the above bit lines; thick oxide formed on those bit lines; and multiple word lines formed on the thin oxide and thick oxide, and crossing those buried bit lines, in which on intersection of those word lines and bit lines there are multiple diode memory cell, multiple bipolar transistor memory cell and multiple memory cell in OFF state.
Patent TW-428401-B (TW)
Title: System for estimating signals received in the form of mixed signals
Inventor: DEVILLE YANNICK
IPC: G10L21/0308
Filed: 1996-02-29
Granted: 2001-04-01
Abstract: Source separation system for processing input signals (Ei(t)) formed by instantaneous linear mixtures of primary signals (Xj(t)) that result from sources (S1-Sn) and for producing at least one estimated primary signal (Xk(t)). The system comprises separation means (10) and characterization means (15) which determine cumulants of the input signals for extracting estimated mixing coefficients (Αij). Said coefficients are transformed into separation coefficients (Cki, dki) in separation means (10). The separation means (10) may have a direct structure or a recursive structure. Application: apparatus for receiving electric signals, sound signals electromagnetic signals (antenna, car radio, telephone).
Patent TW-287973-B (TW)
Title: The plug of pouring disc for continuous casting
Inventor: ANTO MITSURU
IPC: B22D41/00
Filed: 1996-03-21
Granted: 1996-10-11
Abstract: A plug of pouring disc for continuous casting with following features. (a) The plug is made by fire-resist material for adjusting the melting-metal flow inside the pouring disc and supported by a spindle; (b) The nut is made by high grade ceramic and formed with inserted part for the plug & spindle.
Patent TW-406118-B (TW)
Title: A process for making a copper phthalocyanine pigment
Inventor: TAKASHIMA TSUTOMU
IPC: C09B67/20
Filed: 1996-03-27
Granted: 2000-09-21
Abstract: This invention provides a process for producing copper phthalocyanine pigments which comprises reacting either phthalic anhydride or its derivatives with urea and a copper-containing substance, or either phthalonitrile or its derivative with a copper-containing substance in a reaction solvent by heating characterized in that an alkylxylene ingredient having a branched C4 side-chain represented by the following formula (I) is used as the reaction solvent.
Patent TW-360852-B (TW)
Title: Pipeline processor
Inventor: HASEGAWA KATSUYA
IPC: G06F9/32
Filed: 1996-04-06
Granted: 1999-06-11
Abstract: According to the present invention, a pipeline processor is provided for executing a predictive branch instruction defining a number of at least one instruction which is to be executed in succession after the predictive branch instruction is given before a control flow is changed. The pipeline processor includes: a program counter for keeping an address of an instruction to be fetched; an instruction memory for outputting an instruction corresponding to the address held by the program counter; an instruction register for fetching and holding the instruction output from the instruction memory; an instruction decoding section for decoding the instruction held by the instruction register, thereby judging whether or not the instruction is the predictive branch instruction; a counter section for holding a counter value and comparing the counter value with a predetermined threshold value, the counter value being initialized to the number defined by the predictive branch instruction and being decremented in synchronization with an increment of the program counter; an adder for incrementing the address held by the program counter and providing the incremented address as a sequential instruction address; a branch target address register for providing a branch target address of the predictive branch instruction; and a selector for selecting one of the sequential instruction address and the branch target address of the predictive branch instruction in accordance with a comparison result obtained by the counter section.
Patent TW-440594-B (TW)
Title: Elastomeric compounds incorporating partially coated carbon blacks
Inventor: MAHMUD KHALED
IPC: C08K9/00
Filed: 1996-05-21
Granted: 2001-06-16
Abstract: Disclosed are elastomeric compounds including an elastomer, a silica coated carbon black, and optionally including a coupling agent. Elastomeric compounds incorporating an elastomer and an oxidized, partially coated carbon black are also disclosed. Also disclosed are silica coated carbon black/elastomeric formulations using a variety of elastomers useful in a variety of product applications.
Patent TW-368441-B (TW)
Title: Molding apparatus
Inventor: UZAKI NAGATO
IPC: B22C15/00
Filed: 1996-09-09
Granted: 1999-09-01
Abstract: A molding method is disclosed to fill a mold space in a pattern box with molding sand. By this method are carried out at least once the steps of (a) measuring and feeding a first amount of all the molding sand necessary to produce a mold in the mold space, the first amount being one of at least two parts divided from the total molding sand, (b) introducing air flows into the mold space at the air-pressure rising rate of 30 to 500 kg/cm<SP>2</SP>/sec, (c) feeding the remaining parts of the molding sand into the mold space; and (d) introducing air flows into the mold space at the air-pressure rising rate of 30 to 500 kg/cm<SP>2</SP>/sec.
Patent TW-348249-B (TW)
Title: Display device, drive circuit for the display device, and method of driving the display device
Inventor: SEKIDO TETU
IPC: G09G3/36
Filed: 1996-09-16
Granted: 1998-12-21
Abstract: A drive circuit for a display device including a display panel (2) for displaying an image line by line, the circuit comprising: a data register (1) which is used to store optional data (OD) in response to a control signal, to overwrite the stored optional data with display data (DD), and to prepare display data for a given line of the display panel, the data prepared in the data register being transferred to the display panel to display the given line of the display panel.
Patent TW-379391-B (TW)
Title: Electric device package enclosed by pliant medium laterally confined by a plastic rim member
Inventor: DUDDERAR THOMAS DIXON
IPC: H01L23/31
Filed: 1997-03-06
Granted: 2000-01-11
Abstract: The bottom and side surfaces of an electronic device, such as an integrated circuit chip or a multichip assembly, are surrounded by a soft gel medium. The gel medium is laterally confined by means of a rigid plastic rim that is epoxy-bonded in place along its perimeter. A plate, made of plastic or metal, can be attached to the top surface of the rim, in order to provide a cover for the package.
Patent TW-325551-B (TW)
Title: Auto switching memory space method capable of judging if there is updated version stored in memory circuit to automatically select program stored in ROM or memory circuit as execution stating location
Inventor: CHEN KUEN-JUEI
IPC: G06F9/445
Filed: 1997-01-04
Granted: 1998-01-21
Abstract: An auto switching memory space method comprises of the steps: (1) Starting up central processing unit in electric product, and executing basic input/output system boot-up program of ROM; (2) ROM sending one control signal to CPU, making CPU detect if there is updated program stored in memory circuit; (3) When CPU detect that there is updated program stored in memory circuit, CPU controls switching controller and common selector, making chip selection pin automatically switch to connect with memory circuit with updated program, and excuting it, then continuing to excute subsequent program of ROM; (4) When CPU does not detect that there is updated program stored in memory circuit, CPU continues to excute program stored in ROM without doing any switching operation.
Patent TW-375693-B (TW)
Title: Active matrix liquid crystal display device
Inventor: YONEYA MAKOTO
IPC: G02F1/133
Filed: 1997-04-08
Granted: 1999-12-01
Abstract: This invention relates to an active matrix liquid crystal display device that has a parallel electric field added to the liquid crystal outside the electric field roughly parallel to substrate surface, in which the extrapolation length of liquid crystal molecules expressed at liquid crystal/oriented film interface and phase transfer joint strength of oriented film surface is a kind of weak twist union of more than 10% of substrate pitch. To obtain said twist union, organic oriented film containing long-chain olefin and/or fluoro polymer Dan/or low polymer, or inorganic oriented film obtained by tilt steam plating, or photoreactive oriented film obtained by polarized light illumination is employed.
Patent TW-382073-B (TW)
Title: Liquid crystal display device and method for fabricating thereof
Inventor: CHIYOU KOUYUU
IPC: G02F1/1362
Filed: 1997-04-10
Granted: 2000-02-11
Abstract: To provide a technology for fabricating a high image quality liquid crystal display device, a set range of a cell gap for holding a liquid crystal layer is limited in accordance with a distance of a pixel pitch in which specifically, the cell gap is set to be a distance of one tenth of the pixel pitch, whereby the high image quality liquid crystal display device with no occurrence of image display failure caused by disturbances of an electric field such as disclination, can be realized.
Patent TW-355196-B (TW)
Title: Sliding bearing
Inventor: BLASE FRANK
IPC: F16C17/03
Filed: 1997-04-19
Granted: 1999-04-01
Abstract: A sliding bearing for mounting transmission shaft having plastic bearing and casing of support bearing, wherein the sliding bearing receives the contour of the transmission shaft, the support bearing indicating a slit along the length of axis and a flexible area to allow the slit to open, to enable the support bearing diametrically to mount to the transmission shaft and disengage from the transmission shaft, the support bearing having a axis to rotate axially, characterized in that: Support bearing (1) rotates within the holding member (7A, 11) and axial holding member (7) is designed to operate the second holding member (7, 7A, 11) during the first step, and operate another second holding member (7, 7A, 11) during the second step.
Patent TW-373280-B (TW)
Title: Multi-chip module with accessible test pads and test fixture
Inventor: BARDSLEY THOMAS J
IPC: H05K1/11
Filed: 1997-07-30
Granted: 1999-11-01
Abstract: An improved multi-chip module with a substrate having top and bottom surfaces, a plurality of chips on the top surface, a plurality of pins on the bottom surface. Each chip has at least one lead extending through the substrate and conductivity coupled to a corresponding pin. The module has at least one net associated with the chips and completely embedded within the substrate. The improvement comprised of at least one pad attached to the bottom surface of the substrate and a conductive path conductivity coupled between the pad and the net.
Patent TW-434283-B (TW)
Title: Process and apparatus for producing prepreg
Inventor: IKEGAWA NAOTO
IPC: C08J7/04
Filed: 1997-08-08
Granted: 2001-05-16
Abstract: There is provided a process of producing a prepreg in which a sheet-shaped fabric material as a reinforcing substrate is continuously provided, a thermosetting resin as a matrix resin in a molten state is supplied to the substrate, and the resin is heated, which process contains the steps of: (a) a first coating step in which the matrix resin is applied to one surface of the reinforcing substrate using a first die coater, and an amount of the matrix resin to be applied is equal to or larger than an amount of the matrix resin which the reinforcing substrate is able to contain in its total void as much as possible, (b) a first heating step in which the reinforcing substrate having the matrix resin is heated by a first non-contact type heating unit so that the matrix resin is impregnated into the inside of the reinforcing substrate, whereby a laminar composite made of the matrix resin and the reinforcing substrate is obtained, (c) a second coating step in which the matrix resin is further applied to at least one of surfaces of the laminar composite using a second die coater, and (d) a second heating step in which the laminar composite which has an amount of the matrix resin applied in the step (c) is heated by a second non-contact type heating unit so as to semi-harden the matrix resin.
Patent TW-367557-B (TW)
Title: Rinsing method and device by microwave excitation
Inventor: AOKI HIDEMITSU
IPC: H01L21/00
Filed: 1997-11-07
Granted: 1999-08-21
Abstract: A kind of microwave excited rinsing and water-rinsing device which comprises a chamber and a microwave oscillator. In which the chamber comprises the inlet for pure water and rinsing chemical solution and the exit for pure water drainage or rinsing chemical solution; and the microwave oscillator is used to generate the microwave to irradiate the pure water or rinsing chemical solution in the chamber.
Patent TW-466737-B (TW)
Title: Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
Inventor: CHEN LIANG-YUH
IPC: H01L23/538
Filed: 1997-12-30
Granted: 2001-12-01
Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD A1) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD A1 via plugs, and a reduced number of process steps to achieve such integration.