baber/WOPTO huggingface dataset:
Patent TW-507203-B (TW)
Title: Semiconductor memory device and method for reading data
Inventor: YAMASAKI KAZUYUKI
IPC: G11C11/41
Filed: 2000-10-12
Granted: 2002-10-21
Abstract: The provision of a semiconductor memory device for which access times in burst mode can be improved with no increase in the chip surface area and with no increase in power consumption. A latch pulse selection circuit 6 uses a control signal CA0T to output an input control signal SALF and a control signal SALS, to a first latch group within a latch circuit 7 as a latch pulse SAL0A, and to a second latch group within the latch circuit 7 as a latch pulse SAL1A, respectively. Based on a control signal YS0 to YS31 input from a column decoder circuit 11, a Y selector 12 is connected to a sense amplifier circuit 8 via Y switches connected to the corresponding digit lines. The sense amplifier circuit 8 comprises 256 sense amplifiers, and performs data evaluations of the signal YD0 to signal YD127 from the Y selector. A latch circuit 7 latches a data signal DT0 to data signal DT127 from the sense amplifier circuit 8 into a first latch group and a second latch group via latch signals SAL0 and SAL1 respectively.
Patent TW-495798-B (TW)
Title: Discharge lamp with electrode support
Inventor: KLING RAINER
IPC: H01J65/04
Filed: 2000-10-24
Granted: 2002-07-21
Abstract: This invention relates to a discharge lamp, which is designed preferably for dielectric barrier discharge. The invention consists in utilizing the support, so as to ensure the adjustment of the position of the electrode which proceeds in the discharge tube of the discharge lamp at a distance from the wall of the discharge tube.
Patent TW-502558-B (TW)
Title: Plasma focus light source with improved pulse power system
Inventor: PARTLO WILLIAM N
IPC: H05H1/06
Filed: 2001-02-07
Granted: 2002-09-11
Abstract: A high energy photon source. A pair of plasma pinch electrodes are located in a vacuum chamber. The chamber contains a working gas which includes a noble buffer gas and an active gas chosen to provide a desired spectral line. A pulse power source provides electrical pulses at voltages high enough to create electrical discharges between the electrodes to produce very high temperature, high density plasma pinches in the working gas providing radiation at the spectral line of the source or active gas. Preferably the electrodes are configured co-axially with the anode on the axis. The anode is preferably hollow and the active gas is introduced through the anode. This permits an optimization of the spectral line source and a separate optimization of the buffer gas. Preferred embodiments present optimization of capacitance values, anode length and shape and preferred active gas delivery systems are disclosed. Preferred embodiments also include a pulse power system comprising a charging capacitor and a magnetic compression circuit comprising a pulse transformer. A heat pipe cooling system is described for cooling the central anode.
Patent TW-518550-B (TW)
Title: Driving method for electro-optical device, image processing circuit, electro-optical device, and electronic machine
Inventor: AOKI TORU
IPC: G02F1/133
Filed: 2000-11-20
Granted: 2003-01-21
Abstract: The present invention relates to a driving method for electro-optical device, an image processing circuit, an electro-optical device, and an electronic machine. When scanning lines are selected sequentially for each of blocks where a plurality of data lines is grouped to display an image, irregular luminance occurring in portions of the displayed image coincident with the borders of the blocks is suppressed to be indiscernible. The first sample-and-hold circuit 310 samples and holds an input image signal VID so as to output an image signal VIDa1 corresponding to a data line for causing noise. A correction circuit 311 produces a correcting signal VID1' according to the image signal VIDa1 and a pre-charging voltage Vpre. An addition circuit 312 adds up an image signal VID6 corresponding to a data line affected by the noise and the correcting signal VID1' so as to produce a corrected image signal VID'.
Patent TW-554186-B (TW)
Title: Methods and apparatus for packaging fiber gratings to provide temperature compensation
Inventor: CORTRIGHT JEFFREY EARL
IPC: G02B6/02
Filed: 2000-12-13
Granted: 2003-09-21
Abstract: Passive temperature compensated packages for short-period fiber gratings and other optical components and techniques for forming the packages are described. In one aspect, a hollow tube having a negative coefficient of thermal expansion (CTE) with a seal and a plug at each end is employed to form an athermalized hollow tube package. According to another aspect, a hollow tube having a negative CTE with a shelf section at each end surrounds an optical fiber containing a short-period grating. The hollow tube is sealed at each end with a fused frit. According to another aspect, two channel members having a negative CTE are joined together to form an athermalized two-piece package. The channel members include longitudinal channels for containing an optical fiber and include transverse channels for sealing the two-piece package with a frit and epoxy at each end. According to another aspect, a substrate having a longitudinal channel an transverse channels having a negative CTE is employed to form an athermalized open channel package.
Patent TW-I222016-B (TW)
Title: Call gate expansion for 64 bit addressing
Inventor: MCGRATH KEVIN J
IPC: G06F9/355
Filed: 2000-12-18
Granted: 2004-10-11
Abstract: A processor supports a first processing mode in which the address size is greater than 32 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the first processing mode. The first processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state). To call code operating in the first processing mode from the 32 bit or 16 bit code, a call gate descriptor is defined which occupies two entries in a segment descriptor table. By occupying two entries, each of which may otherwise store a segment descriptor, the call gate descriptor may include enough space to store an address in excess of 32 bits. Thus, a calling code segment may reference a call gate descriptor, which may reference the target code segment and may provide an address within the address space of the target code segment, even if the address exceeds the address size in the calling code segment.
Patent TW-473596-B (TW)
Title: Gear and the manufacturing method thereof
Inventor: NISHI TAKASHI
IPC: B81C1/00
Filed: 2001-01-16
Granted: 2002-01-21
Abstract: A manufacturing method for the gear, which relates to a process for rotating the screw 1 to form the gaps on the substrate 3 (forming the area between the bearing and the gap portion of the screw gear); and, a process for forming the model frame 12 in the area of the lower portion of the screw; a process for stacking the material 5 of the screw in the area of the lower portion and to the height of the upper portion of the screw; a process for forming the upper portion of the screw; finally, a process for making the gear rotatable and removing the material 13 in the gap between the substrate 3 and the gear 1.
Patent TW-512590-B (TW)
Title: Buffer circuit
Inventor: TSUJI NOBUAKI
IPC: H03K19/0185
Filed: 2001-02-22
Granted: 2002-12-01
Abstract: A buffer circuit comprises a data input terminal: an enabling terminal inputting an enabling signal: an output terminal: a first power source terminal supplying high potential voltage: a second power source terminal supplying low potential voltage: a first N-channel transistor connected between said output terminal and said second power source terminal: a common bulk P-channel transistors group of a first to fifth transistors formed on a common bulk region: a second N-channel transistor formed between said one node and said second power source terminal and comprising a gate electrode supplied an inverted signal of an enabling signal: and a logic circuit either inputting an inverted signal of said input signal to said gate electrodes of said first P-channel transistor and said first N-channel transistor, or inputting a signal keeping said first P-channel transistor turned off to the gate electrode of said first P-channel according to state of said enabling signal.
Patent TW-515042-B (TW)
Title: Method to produce a conductor-structure for an integrated circuit
Inventor: WEGE STEPHAN
IPC: H01L21/3213
Filed: 2001-03-06
Granted: 2002-12-21
Abstract: This invention is related to a simple method with smaller steps and has a structurized first isolation-layer (2), on which a first passivation-layer (5) is applied. On this is applied a layer of conductive material (6), on which a second passivation-layer (7) is applied. On the passivation-layer (7) is applied a hard-mask (8). The layer of conductive material (6) is removed in the region determined by the hard-mask (8). The first passivation-layer (5) is removed by sputtering in the region determined by the hard-mask (8) and is deposited at least partly again on the side-wall of the layer of the conductive-material (6).
Patent TW-535108-B (TW)
Title: A method and apparatus for equalizing channel characteristics in a computer extension system
Inventor: KIRSHTEIN PHILIP M
IPC: G06F3/038
Filed: 2001-04-09
Granted: 2003-06-01
Abstract: An apparatus and method for equalizing the characteristics of a communication channel in a computer extension system. A time measurement system determines the delay time in a pair of wires connecting a computer at a first site to peripherals at a second site. The value of the delay time serves as control signal to select filters where the filters have inverse channel frequency characteristics.
Patent TW-592665-B (TW)
Title: Method and device for sampling and analyzing interstitial fluid and whole blood samples
Inventor: HODGES ALASTAIR MCINDOE
IPC: G01N33/49
Filed: 2001-04-12
Granted: 2004-06-21
Abstract: The invention disclosed in this application is a method and device (10) for combining the sampling and analyzing of sub-dermal fluid samples, e.g., interstitial fluid or whole blood, in a device suitable for hospital bedside and home use. The device includes a dermal layer penetration probe (12) in fluid communication with an analysis chamber (20). It is applicable to any analyte that exists in a usefully representative concentration in the fluid, and is especially suited to the monitoring of glucose.
Patent TW-517421-B (TW)
Title: Structure of SMT-type recoverable over-current protection device and its manufacturing method
Inventor: LIOU WEN-LUNG
IPC: H01C7/00
Filed: 2001-05-03
Granted: 2003-01-11
Abstract: There are provided a structure of SMT-type recoverable over-current protection device and its manufacturing method. The method comprises providing a raw material board having two faces respectively formed with a patterned conductive metal foil; next, cutting the raw material board based on the design to form a grid-shaped substrate having a plurality of bar structures; then forming an insulating layer for encapsulating the whole grid-shaped substrate and exposing the patterned conductive gold foil layer on the terminal face of the bar structure; then, performing a dicing process to cut the bar structures on the grid-shaped substrate into a plurality of dies, each having two cut terminal face; and finally forming two electrodes on the cut terminal faces at two sides of the die.
Patent TW-581913-B (TW)
Title: Liquid crystal display device
Inventor: KIM TAE-JOON
IPC: G09F9/35
Filed: 2001-05-09
Granted: 2004-04-01
Abstract: Disclosed is a liquid crystal display device capable of preventing a grounding clip, which is combined to an end of a mold frame to ground a printed circuit board to a top chassis, from making electrical contact with a display unit. A guide projection is formed at the end of a mold frame so as to be placed adjacent to a grounding clip. A gap between the guide projection and the liquid crystal display panel is narrower than a gap between the liquid crystal display panel and the grounding clip. Accordingly, even though the mold frame is bent by means of an outer force, it is possible to prevent the grounding clip from deforming and making electrical contact with the liquid crystal display panel.
Patent TW-487958-B (TW)
Title: Manufacturing method of thin film transistor panel
Inventor: DAI YUAN-TUNG
IPC: H01L21/336
Filed: 2001-06-07
Granted: 2002-05-21
Abstract: A kind of method for manufacturing thin film transistor (TFT) panel is disclosed to solve the problems such as poor stability of the conventional laser crystallization process and bad quality of the obtained polysilicon film. A transparent insulation layer is formed on the front surface of a silicon wafer and is followed by forming TFT structure and transparent electrode on the upper surface of the transparent insulation layer. A transparent substrate is bonded to the front surface of the silicon wafer. After that, the silicon wafer is removed by using a polishing or etching means from the backside of the silicon wafer, in which the transparent electrode also can be formed at the lower surface of the transparent insulation layer. In addition, the transparent substrate can be first bonded to the backside of the silicon wafer. Then, a single crystallized silicon thin film is formed by performing a thin film process onto the silicon wafer such that the required TFT structure layer and the transparent electrode for constructing the TFT panel is formed on the single crystallized silicon thin film.
Patent TW-I232252-B (TW)
Title: Sealing device
Inventor: LAU LEE-KEUNG
IPC: F16J15/32
Filed: 2001-06-12
Granted: 2005-05-11
Abstract: A sealing device (200) is disclosed comprising a first body (10, 30) having an aperture operable to receive a member (120) and a second body (50) retained within a cavity (40) of the first body (10, 30), the second body (50) having an aperture operable to receive the member (120). The sealing device (200) also comprises a seal (70) retained in a cavity (60) formed by the first body (10, 30) and the second body (50), the seal (70) having an aperture operable to receive the member (120). The sealing device (200) is arranged such that the first body (10, 30) and the second body (50) are co-operable to compress the seal (70) to provide a fluid-tight seal between the member (120) and at least one of the apertures, thereby reducing leakage of fluid along the outside surface of the member (120).
Patent TW-544684-B (TW)
Title: Semiconductor integrated circuit device
Inventor: ARAI KOJI
IPC: G11C7/02
Filed: 2001-07-06
Granted: 2003-08-01
Abstract: P-type well regions Ap1 and Ap9, on which the first and the second pre-charge circuits are formed, and p-type well regions Ap2, Ap3, Ap7 and ap8, on which the first and the second Y-switch circuits are formed, are formed on both ends of a sense amplifier formation region, respectively. A bit line BLT, which extends from the first memory cell formation region of the first and the second memory cell formation regions arranged in both sides of the sense amplifier formation region, arrives at an n-type well region An1 on which a sense amplifier is formed, via both a p-type well region Ap1 on which the first pre-charge circuit is formed and p-type well regions Ap2, Ap3 on which the Y-switch circuit of the first wiring layer is formed. Therefore, a wiring region for arranging wirings other than bit lines can be secured on the extended bit line BL2T.
Patent TW-510025-B (TW)
Title: Manufacture method of static random access memory
Inventor: REN BO-HAN
IPC: H01L21/425
Filed: 2001-07-24
Granted: 2002-11-11
Abstract: This invention provides a manufacture method of a static random access memory, which consists of: defining a substrate with a gate oxide layer and a first conductor layer formed thereon to a form imbedded contact opening, forming a second conductor layer on the substrate, forming a imbedded contact in the substrate corresponding to the imbedded contact opening, forming a protection layer on the substrate to fill up recess, then, removing part of the protection layer, forming a patterned photoresist layer, using the patterned photoresist layer as a mask to etch and form a gate and an interconnect, removing the patterned photoresist layer, and finally removing the protection layer or retaining the protection layer to perform an implantation process to from source/drain connecting with the imbedded contact.
Patent TW-524857-B (TW)
Title: Surface treatment of magnesium alloy
Inventor: HSU FRED
IPC: C22C23/00
Filed: 2001-08-20
Granted: 2003-03-21
Abstract: A surface treatment of magnesium alloy is characterized in that not only remove the rust, corrosion and smut on the surface of magnesium alloy, but also clean the pinholes over the object surfaces of injection molded or casting molded magnesium alloy workpiece. The treatment method may enhance the adhesion for the subsequent process (electro-plating, electro-coating, spray coating and baked coating). It also completely eliminates the environmental pollution caused by the traditional chemical process, because the sandblasted objects can be used directly for electro-plating, electro-coating, spray coating or baked coating without chemical pretreatment or conversion.
Patent TW-565617-B (TW)
Title: Raw pellets containing oxidized metal for a reduction furnace, a method for production the same, a method for reducing the raw pellets and a reducing apparatus
Inventor: IBARAKI TETSUHARU
IPC: F27B9/16
Filed: 2001-10-30
Granted: 2003-12-11
Abstract: The present invention provides raw pellets, a method for producing the raw pellets having a high strength, using a raw powder material, preventing from pulverizing when used in a rotary hearth reduction furnace, and a method for reducing the raw pellets in the furnace effectively, and an apparatus for realizing the method. Mixing raw powder material supplied from raw material storage bin 1, containing oxidized metal and carbon (including 20 to 80 weight % of powder in diameter of 10 mum and below), in a mixer 5, and producing pellets in a pan type pelletizer 7, and screening these pellets by a sieve 9 and drying them in a pellet dryer 11. During these processes the pellets are continuously transferred an processed without crushing.
Patent TW-524998-B (TW)
Title: Add/drop channel filter and optical network using the filter
Inventor: CHANG SEAN
IPC: G02B6/26
Filed: 2001-11-26
Granted: 2003-03-21
Abstract: An add/drop channel filter is equipped with a drop path and an add path. When different wavelength signal inputs from a first system to the add/drop channel filter, a particular wavelength signal can be dropped to a second system or the particular wavelength signal can be added from the second system to the said first system. The add/drop channel filter is characterized by the ability of modulation of the dropped particular wavelength signal. Subsequently, control the save and read of a particular wavelength signal between two local area networks (LAN) by virtue of the add/drop channel filter of the invention.
Patent TW-543072-B (TW)
Title: Substrate treatment device using a dielectric barrier discharge lamp
Inventor: FUJITUGU HIDEKI
IPC: H05K3/06
Filed: 2001-12-19
Granted: 2003-07-21
Abstract: An irradiation treatment device is provided in which uniform irradiation treatment with high speed can be achieved without damaging a substrate, even in the case in which the substrate to be treated is enlarged and exceeds the length of the rod-shaped dielectric barrier discharge lamp. The object is achieved in a substrate treatment device using dielectric barrier discharge lamps in which the dielectric barrier discharge lamps 1, 1a, 1b and the substrate P are transported relative to one another and in which the surface of this substrate is irradiated with UV light from the dielectric barrier discharge lamps 1, 1a, 1b, whose feature is: the length for the above described dielectric barrier discharge lamps 1, 1a, 1b in the lengthwise direction is less than the length in the direction perpendicular to the transport direction of the substrate P. There are at least two dielectric barrier discharge lamps 1, 1a, 1b and there is an area of the above described substrate which has been irradiated by one dielectric barrier discharge lamp 1, 1a, 1b, and there is an area of the above described substrate which has been irradiated by the other dielectric barrier discharge lamp 1, 1a, 1b during transport of this substrate such that they come to rest on one another at least in one part, and that with respect to the UV light emitted by the respective dielectric barrier discharge lamp 1, 1a, 1b in this area in which superposition occurs, there are light screening means 4 by which a transition is effected between the two lamps.
Patent TW-I237465-B (TW)
Title: Estimating frequency offset
Inventor: YOUNG ROBERT WILLIAM
IPC: H04L27/152
Filed: 2002-03-27
Granted: 2005-08-01
Abstract: Frequency offset estimation apparatus for estimating the offset from a predetermined centre frequency of an input signal carrying a plurality of frequency shifted symbols, the apparatus comprising: a demodulator for demodulating the input signal to estimate the symbols; a first filter for forming a first estimate of the offset by determining the average of a first predetermined number of the last maxima and minima of the instantaneous frequency difference between the input signal and a signal at the centre frequency; a second filter for forming a second estimate of the offset by determining the average of the values of the instantaneous frequency difference between the input signal and a signal at the centre frequency associated with the estimation by the demodulator of those of the symbols having the greatest positive and negative frequency shifts; and a selector for selecting the first estimate or the second estimate as an output estimate of the frequency error.
Patent TW-594720-B (TW)
Title: Manufacturing method and apparatus for optical information medium
Inventor: YOSHINARI JIRO
IPC: G11B7/26
Filed: 2002-05-01
Granted: 2004-06-21
Abstract: After forming a resin layer on an information recording layer, a stamper capable of transmitting activation energy ray is contacted with the surface of the resin layer. Next, the activation energy ray is radiated to the resin layer, and then, a transparent intermediate layer including a transferred concave-convex pattern is formed by separating the stamper. The stamper, at least the surface where the concave-convex pattern is formed, is made of polyolefin-type resin or fluoric resin. The difference between the maximum and the minimum thickness of the transparent intermediate layer on an information recording area is equal to or smaller than 10 mum.
Patent TW-561126-B (TW)
Title: Curve conveyer
Inventor: SAEKI NAOYUKI
IPC: B65G39/071
Filed: 2002-05-07
Granted: 2003-11-11
Abstract: This invention provides a curve conveyer capable of restraining frictional noises from an end roller when rotating and driving a conveyer belt. The end roller (15) is formed by a spindle (15a) and plural short rollers (15b) rotatally inserted outside of the spindle (15a), and a bearing (15c) with an outer race with larger outside diameter than that of the short roller (15b) is interposed between the short rollers (15b), (15b) adjoining each other at least at a belt peripheral part side. Or the roller (15) is formed by the spindle (15a) and the plural short rollers (15b) rotatally inserted outside of the spindle (15a), and the bearing (15c) with the outer race with the same outside diameter as that of the short roller (15b) is interposed between the short rollers (15b), (15b) adjoining each other at least at the belt peripheral part side.