Patent GB-1136602-A (GB)
Title: Improvements in thickness-measuring apparatus
IPC: G01B17/02
Filed: 1965-12-14
Abstract: 1,136,602. Ultrasonic thickness - measuring system; transistor pulse and sawtooth generating circuits. ROCHAR ELECTRONIQUE. 14 Dec., 1965 [14 Dec., 1964(2); 11 Oct., 1965], No. 53115/65. Headings H3T and H4D. In a pulsed echo-sounding system for measuring the thickness of a workpiece, an electrical pulse of duration equal to the time interval between two selected echoes arising from a transmitted acoustic pulse is derived and applied to a circuit which generates a lengthened pulse of duration proportional to the duration of the applied pulse, the duration of the lengthened pulse being determined by digital apparatus. In the embodiment illustrated by Fig. 1 and a waveform diagram, Fig. 2 (not shown),: the transmission pulse and multiple echoes pass from a transmitting/receiving transducer 12 (coupled to a workpiece 10) through receiver circuits 18-22 and a gate 24 to a pulse-counting chain of bi-stable circuits 26, 28, 30. An output signal from bi-stable 30 closes gate 24 after the arrival of the fourth echo pulse (t 4 ). A pulse (S 28 ) of duration equal to the interval between the second (t 2 ) and fourth (t 4 ) echoes from the back surface of the workpiece 10 is obtained from bi-stable 28 and applied to a durationmultiplication circuit 34. The duration of the output pulse (S 34 ) of circuit 34 is determined by a digital counter 42 with a decimal read-out in terms of workpiece thickness, clock pulses being fed to the counter from a blocking oscillator 40 gated by the output of circuit 34. The use of circuit 34 enables the use of a lowperformance unit for counter 42.  The thickness measurement is monitored by comparing the interval between the second (t 2 ) and third (t 3 ) echoes from the back surface of workpiece 10 with the interval between the third (t 3 ) and fourth (t 4 ) back surface echoes as follows. The coincidence of output pulses from bi-stable circuits 26 and 28 is detected by an AND gate 32 providing a pulse (S 32 ) of duration (t 2 )-(t 3 ) which is applied to a duration-multiplication circuit 36 with a multiplication factor twice that of circuit 34. Any duration difference between the output pulses of circuits 34 and 36, representing an error in the thickness measurement, is detected by logic circuitry 44-64 and if the difference exceeds a predetermined value set by the circuitry a neon 66 is lit. Details of the operation of the logic circuitry are given. In alternative embodiments, echoes (t 2 ) and (t 5 ) may define the leading and trailing edges of the thickness measurement pulse (S 28 ), and echoes (t 3 ) and (t 4 ) may define the leading and trailing edges of the monitoring pulse (S 32 ), appropriate changes of the multiplication factors of circuits 34 and 36 being made. The duration-multiplication circuit (34 or 36), Fig. 3, comprises a capacitor C which discharges from a "rest" value at a nett current I 2 -I 1  when an input pulse of duration t. applied to the base of switching transistor S 4  causes transistor switches S 1  and S 3  to conduct. Following the end of the input pulse, S 3  is blocked and capacitor C is charged in time T to the "rest" value by current I 1  through switch S 1 . Transistor S 5  becomes blocked at the beginning of the period t and conducts again at the end of period T, providing an output pulse of duration t + T which is shown to be (R1/R2)t, R 1  and R 2  being the values of resistances R 1  and R 2 . The conduction of S 5  causes current from S 1  to be diverted through S 2  so that the charging of capacitor C ceases and the only current through S 1  is then the base current of S 5 . A modification of the duration - multiplication circuit, in which S 1  is blocked for the duration t, is described.