Patent GB-1422819-A (GB)
Title: Matrix data manipulator
IPC: G11C19/38
Filed: 1973-10-22
Abstract: 1422819 Digital storage systems BELL NORTHERN RESEARCH Ltd 22 Oct 1973 [20 Oct 1972] 49127/73 Heading G4C A circuit which may be used for parallel-toserial and serial-to-parallel conversion, bit order inversion, &c., comprises an array of modules comprising two registers each. Gating arrangements provide for transfer of data from one register to the other within a module and for connection of registers in rows or columns to operate as shift registers.  The embodiment illustrated in Fig. 1 comprises a 4 x 4 array of modules, each as shown at M14. The upper registers 10 in each row are serially connected as a shift register. A column of gates N11-N43 is provided to select the required outputs of the shift registers. The described modes of operation are as follows: Parallel word serial bit to serial word parallel bit.-The words are applied to inputs D1-D4 and stepped along the upper registers 10 under control of clock pulses C I . In response to pulses C T , C O  the data is then transferred to the lower registers 11. The parallel bit outputs V O  of the lowest row of registers pass via gates N11, N21, &c., enabled by signal A, to the outputs Q 1 - Q 4 . In response to pulses V T  the words in the rows of modules above the lowest row are stepped downwards through the array, so that successive words appear in parallel at Q 1 -Q 4 . Clock pulses C I , C O  need not be of the same rate. Since registers 10 and 11 are normally isolated from each other further parallel words can be read in while data is being read out. Serial word parallel bit to parallel word serial bit.-The operation is similar to that just described. Parallel word serial bit to serial word serial bit.- The words are read into registers 10 and transferred to registers 11 as before. In response to clock pulses C o  and signal H T  the data in registers 11 is shifted right to appear serially at outputs Q 1 -Q 4 , gates N13, N23 &c. being enabled by C. Outputs Q 2 -Q 4 , however, are connected back to inputs P 1 -P 3  so that the data in one row of registers 11 is stepped down into the next row, eventually to appear serially at output Q 1 . Serial word serial bit to serial word parallel bit.-The words are applied to D 4 , and because outputs E 2 -E 4  are coupled back to inputs D 1 - D 3  the array is filled serially. The data is then transferred to registers 11 and shifted downwards in response to V T  and C o  so that parallel bit words from the lowest row appear at Q 1 - Q 4 . Bit order inversion.-Serial bit words at D 1 - D 4  are read into. the array and transferred to registers 11. In response to signal R I  and clock C O  the fourth bit of a word is read from module M14, M24 &c. and passes, via gate N12, N22 &c. enabled by B, to outputs Q 1 -Q 4 , The Q output of the registers 11 in modules M13, M23 &c. is coupled via gate 16 to the input of the adjacent register to the left, and similarly for the remaining modules, so that the data shifts left and appears at the output of M14, M24 &c. in the bit order 4, 3, 2, 1. Delay mode.-By application of signal L T  the output of a register 11 is returned to its input so that the bit circulates within the module, in response to clock pulses C o , until L T  ceases.