Patent GB-967717-A (GB)
Title: Transistor circuits for digital computers
IPC: G06F7/50
Filed: 1961-03-16
Abstract: 967,717. Binary adders. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 16, 1961 [April 14, I960], No. 9623/61. Headings G4A and G4C. [Also in Division H3] A logical circuit comprises an AND block and an OR block, each comprising a plurality of transistors of like conductivity type, and complementary type to that of the transistors in the other block. Means are provided to apply different level potentials to the base electrodes and the emitters of the transistors in the respective blocks are coupled together to a source of bias current which flows in that transistor in which the base electrode is at the most favourable potential for conduction. The collector of a transistor in the AND block is coupled tb a base of a transistor in the OR block via a network which produces a signal corresponding to one of the level potentials applied to the AND circuit. Basic circuit. Fig. 1a. An AND circuit An comprises three PNP transistors T1, T2, T3 having a common emitter load 4501. The base of T3 is connected to earth and the bases of T1, T2 are connected to a "normal level" input signal -x being +0. 5v when off and -0. 6v when on, and a larger amplitude "third level" input signal -c being +0. 5v when off and -1. 6v when on respectively. The collector of T2 is taken to a reference potential, the collector of T1 is taken to a network NOP, Fig. 6a (not shown) producing a "normal level" output signal +a, and the collector of T3 is taken to a network TLP Fig. 65 (not shown), producing a "third level" output signal +b. The conductive transistor is that having the most negative base potential, i.e. expressed in Boolean algebra form, The OR block Op comprises four NPN transistors T4... T7 having a common emitter load 4502 the outputs +a, +b are connected to the bases of transistors T4, T6 respectively, a further "normal level" input +y is connected to the base of T5 and the base of T7 is taken to a reference potential. The collectors of T4, T5 are taken to a first network NON Fig. 6c (not shown), and the collectors of T6, T7 are taken to a second network NON, producing "normal level" outputs -L and -M respectively. Alternatively "third level" outputs may be produced by replacing network NON by a "third level" network, Fig. 6d (not shown). Expressed in Boolean algebra form the relation between the input and output of the OR circuit is - M is the complement of -L i.e.-M = +L. Modifications may be made to the interconnections between AND or OR blocks, to accomodate one or two positive inputs instead of the two negative inputs -x, -c Figs. 1c, 1d, 1e (not shown), or to form the basis of a escapement gate and register Figs. 1f 1g (not shown) respectively. Further modification may also be made by interchanging the conductivity types of the transistors in the two blocks e.g. Fig. 1e (not shown). The inputs may be either "static" or "dynamic", i.e. applied only under the control of clock pulses. Data latch, Fig. 2. A data latch circuit comprises a PNP AND block An fed with two positive inputs, a "normal level" input +q and a "third level" input +G1. The +a "hold on" and +b "hold off" signals are now derived from the opposite transistors by virtue of the positive signals and are therefore crossed before applying to the OR block. The +y input to the OR block consists of a number of data signals pD1... 3, each fed to an individual transistor T5, all of which have their emitter-collector paths connected in parallel to form an OR gate, and the +L (or -M) output from the OR block is fed back as the +q input to the AND block. In the absence of the +G1 signal the output -L follows the data input, in the presence of +G1, the output is locked to the last data input present when +G1 was applied. The inputs pD1,  pD2,pD3 may be static or dynamic and may be applied during mutually exclusive time periods, or concurrently. Escapement gate, Fig. 3. The collector connections of transistors T6, T7 in the OR block are separated, that of T7 being taken to earth, and the -L output is fed back to provide the -x input. As in the Data Latch, data inputs pD1, pD2, pD3 are provided and the circuit sets to either a and not b, or b and not a, upon application of +G depending on the presence or absence of a data input. Bipolar set trigger, Fig. 4. A number of input AND blocks 21, 22, 23 are connected in parallel to a common OR block, and the -L output from the OR block Op is fed back as its own +y input via an inverter Cn. The inverter comprises two PNP transistors connected as a long tailed pair Fig. 7 (not shown) positive and negative "normal level" outputs +pN and -pN are derived from an NOP circuit of the type previously referred to. Data pulses -nDB1, -nDB2, +nDB3 are applied during exclusive time intervals and the output follows these pulses during the presence of a gate pulse G1, in a similar manner to the escapement gate circuit. The circuit provides four outputs -nN, +nN, -pN, +pN. Register, Fig. 5: A register circuit comprises an escapement gate 31 and the input block 24 of the set trigger circuit of Fig. 4 connected to an OR block 30. A -L "third level" output from the OR block is connected as one input to an AND block 28, one output from which is applied as a third input block to the OR block. A +L "third level" output signal from the OR block is fed to a further AND block 28, having an output AND which indicates the state of the register. In the " set off" condition the +b signal is present, AND block 28 is open to allow gate complement signals -nGCW, -nGCX, to pass to the outputs +pBW, +pBX, and block 29 is inhibited. In the "set on" condition the +a signal is present, block 28 is inhibited and block 29 is open to allow true gate signals -nGTY, -nGTZ to pass to the outputs +pBY, +pBZ. Known circuits may be used in place of circuits 24, 31. The +pB outputs may be connected to the +pD1 &c. inputs to form a shift register. Accumulator, Fig. 8. An accumulator comprises two registers 40, 41 of the type previously described, connected to an adder 42, the output from the adder is fed to a latch of the type shown in Fig. 2, having an output fed back as the data input -nDB to register 40. Register 41 is provided with two signals-nGT AUG and -nGC SUB which insert the bit derived from the +pD signal into the adder either as an augend or as a subtrahend. Specification 959,390 is referred to.