Patent GB-780431-A (GB)
Title: Improvements in or relating to electronic calculating apparatus
Inventor: KNIGHT LORIN
IPC: G06F7/52
Filed: 1954-09-17
Abstract: 780,431. Digital electric calculating-apparatus. BRITISH TABULATING MACHINE CO., Ltd. Sept. 17, 1954, No. 27003/54. Class 106 (1). In electronic calculating-apparatus, division of decimal values is performed in a predetermined number of major cycles during each of which the divisor is repeatedly subtracted from a first remainder value until the difference becomes negative, further subtraction being then prevented and a quotient digit read out, the divisor is added to the negative difference and the sum is multiplied by ten to form a second remainder value, the first remainder value for one cycle being formed by the replacement of the least significant digit of the second remainder value of the previous cycle by a dividend digit and being formed from zero for the first cycle and the dividend digits being taken in sequence one for each cycle, commencing with the most significant. The elec. tronic calculator described is similar to that of Specification 767,692 including stores 1, 2 and 3, each comprising four shifting registers corresponding to code components 1, 2, 4, 8 of the decimal digit values; an adding unit 29 and a complementing circuit 42. A control unit (Fig. 2, not shown) comprises an arrangement of bi-stable trigger circuits and gates controlled by a " primary timer " (not shown) defining a minor cycle of 16 pulse periods, and a " programme timer " each stage of which may be used to control a separate calculating operation. The division operation commences with a preliminary minor cycle during which the dividend in store 1 (which may be entered from a punched card) is shifted so that the most significant digit is in the right-most position ; this is effected by a plug socket connection which determines the number of shift pulses applied over line 9c to gate 12, the control unit raising the potential on gate control lines M2, M7. Each of the following major cycles comprises eleven minor cycles during the first of which control lines D6, P1, P3, P5, A7, A10 are raised in potential ; this causes the divisor in store 2 to pass to the adder 29 via highway 31 and complementer 42 so that it is subtracted from the remainder in store 3 (zero during the first major cycle) passed to highway 30 together with the first dividend digit allowed through gates 71 by a pulse on line M5, the difference being fed back to 3 through gates 56. During the following minor cycles, the divisor in 2 is again subtracted from the remainder in 3, and a pulse is entered in a decimal minor cycle counter comprising four binary stages with gate connections for effecting a reset to zero when ten pulses have been received. When the remainder goes negative, however, a " 9 " in the highest denomination is detected by circuit 701-703 which raises the potential on line 599 thereby preventing further subtractions and causing the value registered on the minor cycle counter (representing the quotient digit) to be gated over line 650 to store 1 where it replaces the dividend digit read out. At the end of the tenth minor cycle, when the minor cycle counter is stepped to " 9," control lines D6, P1, P2, P5 are raised in potential to cause the divisor to be added to the remainder, and the sum sent to store 3 with a shift to the left (since one shift pulse less than is required for a complete recirculation is applied via gate 52 to the store). The dividend in store 1 also is shifted by applying one pulse short to line 9c. The major cycles are counted by a four-stage binary counter, similar to the predetermined minor cycle counters described in Specification 767,692, which may be set by a plug socket connection to produce a carry output to end the division after 1, 2, ... or 9 cycles. In a modification, the number of minor cycles in each major cycle instead of being constant, is the minimum necessary, i.e. it depends on the number of subtractions required.