baber/WOPTO huggingface dataset:
Patent TW-548875-B (TW)
Title: Patch antenna structure
Inventor: HUNG JIA-JIUN
IPC: H01Q1/36
Filed: 2001-08-03
Granted: 2003-08-21
Abstract: The present invention is a patch antenna structure. The patch antenna is designed and manufactured mainly by mounting a cylindrical feed-in pin into the feed-in hole of the substrate of the patch antenna, and adjust the main length of the feed-in pin to be 0.025 to 0.75 times of the substrate thickness range, and mount the other end of the mainbody on the portion inside the feed-in hole, which is designed to be a supporting portion with decreasing outer diameter, so that the connection portion of the part of the supporting portion protruded out from the other end of the supporting portion has sufficient strength, therefore, not only the thermal expansion/distortion resulted from baking the mainbody at high temperature can be reduced, but also the stress between it and the substrate can be reduced, which increases the yield rate of the product, varies the equivalent capacitance and inductance formed by the mainbody and the substrate to increase the bandwidth of the received signal effectively.
Patent TW-I287579-B (TW)
Title: Stereoselective reduction of substituted oxo-butanes
Inventor: PATEL RAMESH N
IPC: C12P7/02
Filed: 2001-08-16
Granted: 2007-10-01
Abstract: The present invention relates to a process for the stereoselective enzymatic reduction of 1-halo-2-oxo-3-(protected)amino-4-substituted-butanes utilizing certain species of Rhodococcus and Brevibacterium. The product 1-halo-2-hydroxy-3-(protected)amino-4-substituted-butanes, which are useful as intermediates in the synthesis of compounds that are inhibitors of ACE, renin and HIV proteases, are obtained in high yield and, particularly, in very high diastereomeric purity. The process is advantageously highly selective for the 3S, 2R enantiomer of the product.
Patent TW-529126-B (TW)
Title: Substrate for manufacturing a semiconductor device with three element alloy
Inventor: HONG SOON-SUNG
IPC: H01L23/495
Filed: 2001-08-21
Granted: 2003-04-21
Abstract: The substrate according to the present invention is comprised of a silver/gold/grain element alloy layer, wherein the alloy forms an outside layer of the product. The grain element is selected from a group consisting of selenium, antimony, bismuth, nickel, cobalt, indium and combination thereof. The present invention has a particular application in forming the outside layer of various items, including a lead frame, a ball grid array, a header, a printed circuit board, a reed switch and a connector.
Patent TW-535368-B (TW)
Title: System for closed loop power control using a linear or a non-linear power amplifier
Inventor: DAMGAARD MORTEN
IPC: H03G3/30
Filed: 2001-08-29
Granted: 2003-06-01
Abstract: A system for a closed power control feedback loop allows for the use of a non-linear amplifier for amplifying a phase modulated (PM) signal while introducing an inverse version of the desired amplitude modulation (AM) signal into the feedback loop using a variable gain element. By introducing an inverse version of the desired AM portion of the signal into the power control feedback loop, the non-linear, and highly efficient, power amplifier may be used to amplify only the PM portion of the signal, while the AM portion is introduced by the power control feedback loop. In another aspect of the invention, an inverse version of the AM portion of the desired transmit signal is introduced into the power control feedback loop of an amplifier that is amplifying both a phase modulated signal and an amplitude modulated signal. By introducing an inverse version of the desired AM signal into the power control feedback loop, the power control feedback loop may not cancel the AM component present at the output of the power amplifier. In yet another aspect of the invention, the desired AM signal is injected into the feedback loop along with the power control reference signal.
Patent TW-528956-B (TW)
Title: Authorization method and system for accessing resource
Inventor: CHIOU HUNG-LIANG
IPC: G06F13/14
Filed: 2001-09-06
Granted: 2003-04-21
Abstract: An authorization method and system for accessing resource, which is applied in connecting the terminal device network to the application software service provider. With the authorization system, the application software service provider can authorize the terminal device for interactive access of resource transmission, and make the authorization system having the user database with a plurality of user's data for the identification of the user requesting logging into the resource system, and the user account for authorizing the users to access the application software in the resource system, which includes the following steps: (1) the authorizing system receives the user data inputted by the user from the terminal device; (2) the authorizing system compares the user data sent by the terminal device in the user database, if there is no user data in the user database matched with the user data sent by the terminal device, then proceeding with step (3); otherwise, if there is one user data matched with the user data sent by the terminal device, then proceeding to step (4); (3) the authorizing system transmits a message for not logging into the resource system to the terminal device, and let the user at the terminal device to re-input the user data requested by the logging into the resource system, and then returning to step (1); (4) the authorization system transmits an user account to the resource system, and transmits the data message generated by the resource system to the terminal device, so that the user at the terminal device can proceed the interactive access of resource transmission to the resource system through the browser.
Patent TW-I284631-B (TW)
Title: Method and apparatus for treating liquid
Inventor: HAGINO TAKAO
IPC: C02F1/52
Filed: 2001-09-28
Granted: 2007-08-01
Abstract: The present invention relates to a technology which can efficiently concentrate a suspension liquid which needs to be concentrated in sewage treatment plants or various waste water treatment plants, particularly sludge or the like which contains a large amount of odor components which will adversely be decayed and is hard to concentrate. The present invention can prevent odor substances from being produced in a concentration process, and can remarkably reduce the amount of odor components, carbonic acid, and the like contained in concentrated sludge or a lower separated liquid. Specifically, in a process of concentrating or dewatering residual evaporated substances in a liquid, when sludge is held under a reduced pressure of 5 to 70 kPa for less than 15 minutes, a portion of gas components dissolved in the liquid is changed into gaseous phase, and activation of microorganisms in the liquid is restricted. After a decompressing process is performed under the reduced pressure, the liquid is introduced into a gravity concentration tank for gravity concentration, or the decompressed liquid or the gravity-concentrated sludge is introduced into a flocculation reaction tank for flocculation, and is then dewatered by a dewatering device.
Patent TW-535290-B (TW)
Title: NVRAM array device with enhanced write and erase
Inventor: LAM CHUNG H
IPC: H01L27/115
Filed: 2001-10-19
Granted: 2003-06-01
Abstract: Increased write and erase tunnelling currents are developed by enhancement of an electric field near a floating gate with a shaped edge structure overlapping a source/drain diffusion and developing increased floating gate area with angled regions joined by edges in order to reduce write and erase cycle times. The edge structure is formed by selective and preferential etching in accordance with the crystal structure of a monocrystalline semiconductor substrate. The sharpness of the edges and concentration of the electric field may be enhanced by consumption and stress effects of oxidation of the substrate to form a floating gate insulator.
Patent TW-531894-B (TW)
Title: Preparing method for semiconductor device
Inventor: YAMADA JUNJI
IPC: H01L21/8246
Filed: 2001-12-20
Granted: 2003-05-11
Abstract: This invention is to establish a preparing technique of changing the output form of output port when writing information into the elements constituting a mask ROM. The preparing method for semiconductor device comprises forming a gate electrode 8 on the semiconductor substrate through a gate insulating film 5, forming a source-drain area neighboring said gate electrode, forming a aluminum (Al) wiring 15 through interlayer insulating film 14 covering said gate electrode 8, and writing information into the elements constituting mask ROM, with changing the output form of output port by injecting impurity ions into the surface layer of said substrate using said Al wiring 15 and photoresist 23 formed thereon as a mask.
Patent TW-546770-B (TW)
Title: Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby
Inventor: CABRAL CYRIL JR
IPC: H01L29/45
Filed: 2002-04-12
Granted: 2003-08-11
Abstract: A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
Patent TW-I265540-B (TW)
Title: Light emitting flat-panel display
Inventor: COK RONALD S
IPC: G09G3/30
Filed: 2002-06-10
Granted: 2006-11-01
Abstract: A light emitting flat-panel display includes a plurality of light emitting diodes; a sensor for sensing the light output of at least one of the light emitting diodes to produce a light output signal; and a display controller responsive to the light output signal for producing a signal representing the remaining useful life of the display.
Patent TW-591640-B (TW)
Title: Optical pickup drive method, optical pickup and optical disc apparatus
Inventor: TANASE HIRONOBU
IPC: G11B7/135
Filed: 2002-06-18
Granted: 2004-06-11
Abstract: The present invention relates to an optical pickup drive method, optical pickup and optical disc apparatus, which is applied to the case in which an aberration correcting mechanism is constituted of a liquid crystal, for example, and a drive signal of an actuator and a drive signal of an aberration correction mechanism are transmitted after multiplexing them.
Patent TW-I224047-B (TW)
Title: A controlling machine for shifting a turntable on a double-color injection machine
Inventor: WANG RUEI-SIANG
IPC: B29C45/76
Filed: 2002-07-22
Granted: 2004-11-21
Abstract: The present invention relates to a controlling machine for switching a turntable on a double-color injection machine. More particularly, two slanted guiding plates corresponding to each other connects with a power source for being driven and the machine is provided securely with a control valve the guide wheel of which can stay close to slanted guiding plates bias and gradually in order to control the oil incoming and outgoing amount therethrough. According to the above-mentioned, as the turntable is operated to shift its direction, it can avoid the rising and falling gradient and have smoothly operating curve such as start, pre-stop, stop and restart in sequence for shifting directions.
Patent TW-I225408-B (TW)
Title: Hair cosmetic compositions
Inventor: GOAWA TAE
IPC: A61K8/368
Filed: 2002-07-31
Granted: 2004-12-21
Abstract: Provided is a hair cosmetic composition obtained by filling a non-aerosol type foam discharge vessel with a composition containing (a) an organic acid, (b) an organic solvent selected from benzyl alcohol, benzyloxyethanol and propylene carbonate, (c) a silicone and (d) a surfactant. The hair cosmetic composition is excellent in foaming property, and capable of imparting the hair with good feel with fine, creamy and soft foams, effectively suppressing excessive dryness or stiffness of the hair even after plural chemical treatments, and effectively preventing the hair damage such as separation of the cuticle, splitting of the hair end or broken hair. This hair cosmetic foam is free of a propellant so that it does not involve a safety-related or environmental problem.
Patent TW-579507-B (TW)
Title: Disc data storage apparatus with structure for preventing crack disc being jetted out
Inventor: CHIU HSIEN-TSUNG
IPC: G11B17/038
Filed: 2002-08-15
Granted: 2004-03-11
Abstract: The present invention relates to a disc data storage apparatus with structure for preventing crack disc being jetted out. The disc data storage apparatus has a tray for holding a disc and a housing. The housing includes an upper surface parallel with the tray. The upper surface has a barrier portion and a plurality of bending boundaries. When the disc cracks, the barrier portion is configured to stop the crack disc being jetted out. Moreover, the barrier portion may improve the rigid strength to prevent the deflection formed due to the fracture of the disc.
Patent TW-588473-B (TW)
Title: Polymer structure body, functional element having the structure, transistor, and display device using the transistor
Inventor: YAMAHARA MOTOHIRO
IPC: H01L51/05
Filed: 2002-09-05
Granted: 2004-05-21
Abstract: A functional element includes: a pair of electrodes 1 and 4; and a polymer structure including a hole conduction layer 5 and an electron conduction layer 2. The polymer structure includes a first superbranched polymer and a second superbranched polymer. At least one of the first and second superbranched polymers has either hole conductivity or electron conductivity. One of the hole and electron conduction layers includes one of the first and second superbranched polymers. A self-organized structure, which was produced through non-covalent interactions by way of the first or second superbranched polymer, is present in the hole conduction layer, in the electron conduction layer and/or between the hole and electron conduction layers.
Patent TW-I230504-B (TW)
Title: Apparatus and method for power efficient line driver
Inventor: WILCOX JEFFREY R
IPC: H03K19/00
Filed: 2002-09-24
Granted: 2005-04-01
Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.
Patent TW-580809-B (TW)
Title: Method to generate a priority port in Ethernet hub
Inventor: HUANG YIN-KUEN
IPC: H04L12/28
Filed: 2002-09-24
Granted: 2004-03-21
Abstract: The present invention relates to a method to generate a priority port in Ethernet hub, in which the state transitions of the first state machine and the second state machine of the hub are utilized to make the data terminal of the priority port output a jammed signal to the other data terminals connected to the non-priority port when the data terminal of the priority port transmits data, so as to avoid the other data terminals connected to the non-priority port from accessing the Ethernet. Thus, the data terminal connected to the priority port can proceed the data transmission without being interfered by the other data terminals connected to the non-priority port, thereby achieving the purpose of generating a priority port in the hub.
Patent TW-I223096-B (TW)
Title: Test board for testing semiconductor device
Inventor: LIOU MENG-SHIAN
IPC: H04L1/22
Filed: 2002-10-08
Granted: 2004-11-01
Abstract: The purpose of the present invention is to increase the reliability and the electric characteristic of DUT (device under test) and the tester, and to simplify the test procedure to increase test efficiency. The invention includes the followings: the test heat 5 for connecting plural DUT 20 and the semiconductor testing apparatus; the test board for testing semiconductor where test signal is inputted to plural DUT 20 from the test head 5; the mother board 4 connected with the test head 5, multi-layer layout base board 2 for connecting with each of plural DUT 20; and a scramble board 3 disposed in between the mother board 4 and multi-layer layout base board 2. Both female connectors 8, 10 and male connectors 9, respectively, are used to obtain connection in between the mother board 4 and the scramble board 3, as well as in between multi-layer layout base board 2 and the scramble board 3.
Patent TW-583758-B (TW)
Title: Semiconductor device
Inventor: HIRATA KOICHI
IPC: H01L23/495
Filed: 2002-11-28
Granted: 2004-04-11
Abstract: This invention provides a semiconductor device having semiconductor chip containing a electrode pad wire-bonded to a header, the semiconductor device being capable of controlling the diffusion of Ag-paste and securing the wire bonding region, to ensure a stable production of the semiconductor device without unnecessarily enlarging the package size. A projection is provided in the header and a chip is disposed on a position shifted in a direction away from the projection so as to secure the wire-bonding region. The electrode pad connected to the header is disposed towards the center of the chip in comparison with another electrode pad of the same chip edge, and the bonding wire extends from the electrode pad across the chip to the projection or the vicinity of the projection. As a result a reduced package size and a stable production of the semiconductor device can be realized.
Patent TW-I246714-B (TW)
Title: Resistless lithography method for fabricating fine structures
Inventor: FEHLHABER RODGER
IPC: B81C1/00
Filed: 2002-12-20
Granted: 2006-01-01
Abstract: The invention relates to a resistless lithography method for fabricating fine structures, a semiconductor mask layer (HM) being formed on a carrier material (TM, HM') and a selective ion implantation (I) being effected in order to dope selected regions (I) of the semiconductor mask layer (HM). Wet-chemical removal of the non-doped regions of the semiconductor mask layer (HM) yields a semiconductor mask which can be used foe further patterning. A simple and high-precision resistless lithography method for structures smaller than 100 nm is obtained in this way.
Patent TW-579586-B (TW)
Title: Chip package and method of manufacturing the same
Inventor: AHN MOON-BONG
IPC: H01L23/31
Filed: 2002-12-23
Granted: 2004-03-11
Abstract: A chip package includes a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first conductive layer formed on the first surface of the chip, a second conductive layer formed on the second surface of the chip, and a substrate attached to the second surface of the chip and including at least one conductive via hole connected to the second terminal of the chip. And the present invention provides a chip package assembly including the chip package. Further, a method of manufacturing the chip package and an assembly including the chip package are provided. The chip package does not use a bonding wire and additional conductive lands, thereby reducing the size of the package and simplifying the manufacturing process.
Patent TW-I273612-B (TW)
Title: Semiconductor device package and method of production and semiconductor device of same
Inventor: IIJIMA TAKAHIRO
IPC: H05K3/46
Filed: 2002-12-25
Granted: 2007-02-11
Abstract: A semiconductor device including a semiconductor device package providing a capacitor in its circuit board and a semiconductor chip mounted on that package, wherein the capacitor is provided directly under a semiconductor chip mounting surface of the circuit board on which the semiconductor chip is to be mounted and the conductor circuit electrically connecting the semiconductor chip and capacitor is made the shortest distance by having the external connection terminals of the capacitor directly connected to the other surface of the connection pads exposed at one surface at the semiconductor chip mounting surface of the circuit board and to which the electrode terminals of the semiconductor chip are to be directly connected.
Patent TW-I288172-B (TW)
Title: Formulations for coated diamond abrasive slurries
Inventor: HUNT WILLIAM JOHN
IPC: B24D3/02
Filed: 2003-02-21
Granted: 2007-10-11
Abstract: The present invention is directed to an abrasive article and methods of making the abrasive article. An abrasive coating on the abrasive article comprises at least 20% by weight of a superabrasive particle. The abrasive coating is derived from an abrasive slurry. The abrasive slurry may comprise and a dispersant having an AV wherein AV=1000*[(Amine Value)/(Mw)]. The dispersant comprises a polymer having a molecular weight (Mw) of greater than 500 g/mol and an AV of greater than 4.5, a polymer having a molecular weight (Mw) of greater than 10,000 g/mol and an AV of greater than 1.0, or a polymer having a molecular weight (Mw) of greater than 100,000 g/mol and an AV of greater than 0.
Patent TW-I220554-B (TW)
Title: Method of manufacturing multiple gate stacks with similar height and same separation on a semiconductor substrate
Inventor: POPP MARTIN
IPC: H01L21/265
Filed: 2003-03-13
Granted: 2004-08-21
Abstract: A kind of method for manufacturing multiple gate stacks (GS1, GS2, GS3) with similar heights and same separation on a semiconductor substrate (1) is disclosed in the present invention. The manufacturing method includes the steps as shown in the following. At least the first layer (10) and the second layer (20) are sequentially disposed on the gate dielectric material (5) to form the gate stack (GS1, GS2, GS3). Through the inclined injection manner (I1, I2), the material, which has the effect of blocking the growth of oxide, is injected inside two oppositely erect and exposed sidewall faces of the second layer (20) of the gate stack (GS1, GS2, GS3). In this step, the adjacent gate stack has the shielding effect on the exposed sidewall face of the first layer (10) of the gate stack (GS1, GS2, GS3). Through the oxidization effect, the first oxide layer (01) is formed on the exposed sidewall face of the first layer (10) of the gate stack (GS1, GS2, GS3); the second oxide layer (02) is formed on the exposed sidewall face of the second layer (20) of the gate stack (GS1, GS2, GS3); and additionally, the thickness of the first oxide layer (01) is larger than that of the second oxide layer (02).