baber/WOPTO huggingface dataset:
Patent TW-430812-B (TW)
Title: Node-precise voltage regulation for a MOS memory system
Inventor: LEE PETER-WUNG
IPC: G11C16/30
Filed: 1998-06-26
Granted: 2001-04-21
Abstract: An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.
Patent TW-438910-B (TW)
Title: Nickel electroplating solutions for providing composite nickel coatings
Inventor: WEI WEN-CHENG
IPC: C25D3/02
Filed: 1998-06-25
Granted: 2001-06-07
Abstract: The present invention relates to a nickel electroplating solution for providing a composite nickel coating comprising submicron silicon carbide particles and at least one compound which can provide a group having positive valence and containing Co, Mo, W or Fe and lone pair electrons. The composite coating provided from the solution of the present invention has increased hardness, smoothness and wear resistance.
Patent TW-413620-B (TW)
Title: Protective garment and method of manufacture
Inventor: WELCHEL DEBRA NELL
IPC: A41D13/00
Filed: 1998-08-19
Granted: 2000-12-01
Abstract: Disclosed is a protective garment without front facing seams. The protective garment contains a body piece composed of a single seamless sheet of material. The body piece has a right body side and a left body side. Each body side includes a first and second leg edge, a torso edge and a top body side edge extending approximately half-way across each body side form a left sleeve portion. Each sleeve portion has a first and second sleeve edge, and a top sleeve portion edge. Generally speaking, the garment's construction includes approximately five seams and a closure. The closure joins the torso edge of right body side to the torso edge of the left body side to form a resealable opening at a rear face of the garment. Sleeve seams join the first sleeve edges to the second sleeve edges on each body side. A back seam joins the top sleeve portion edge of the right sleeve at approximately the top body side edge of the right body side and the top sleeve portion edge of the left sleeve portion at approximately the top body side edge of the left body side. The back seam is located at the rear face of the garment. Also disclosed is a method of making a protective garment without front facing seams.
Patent TW-410506-B (TW)
Title: Line receiver circuit with large common mode range for differential input signals
Inventor: HEDBERG MATS
IPC: H04L25/02
Filed: 1998-08-26
Granted: 2000-11-01
Abstract: A line receiver circuit fo rreceiving differential digital signals from a symmetrical transmission line comprises a first differential input stage (1) adapted to receive and process differential signals having a common mode voltage within a first common mode voltage range, and a second differential input stage (2) adapted to receive and process differential signals having a common mode voltage within a secondd common mode voltage range. Means (N5, N6) detect an operating condition of said first input stage (1) which operating condition depends on a common mode input voltage at said inputs of said first input stage. Means (P1, N7, N8) are provided for enabling said second input stage depending on said detected operating condition of said first input stage.
Patent TW-498189-B (TW)
Title: Mobile computer
Inventor: TOYOSATO KAZUYUKI
IPC: G06F1/16
Filed: 1998-08-31
Granted: 2002-08-11
Abstract: This is a body-worn, hands-free activated computer that is constructed of materials that conduct heat and is heat insulating. The portion of the computer that is heat insulating is located closest to a wearer's body, the portion that is heat conducting is located farthest from the user's body. Heat is a major problem in wearable computers and this invention provides efficient ways for coping with heat generated by the CPU inside the computer housing. In addition to materials used in constructing the housing for this computer, a heat sink and heat-insulating legs are used to further deflect and direct heat away from a user.
Patent TW-411453-B (TW)
Title: Optical record carrier and apparatus for scanning such a record carrier
Inventor: VAN DEN ENDEN GIJSBERT JOSEPH
IPC: G11B7/24082
Filed: 1998-09-15
Granted: 2000-11-11
Abstract: An optical record carrier (10) comprises a recording layer for recording information in a pattern of optically detectable marks in substantially parallel tracks. The tracks comprise alternating first and second servo tracks (11, 13). The servo tracks hav a track modulation different from the information pattern and indicative of position information. The track modulations of the first and second servo tracks comprise different position information and have a fixed phase relation.
Patent TW-389841-B (TW)
Title: Electronic circuit for testing open/short circuit
Inventor: YANG JR-REN
IPC: G01R31/02
Filed: 1998-09-14
Granted: 2000-05-11
Abstract: An electronic circuit for testing open/short circuit property by using charging and discharging methods is composed of at least two charging and discharging capacitors. Plural signals to be tested are first connected by the probing pin of the film point probe to the transmission gate of the controllable switch on the test circuit, and finally to the amplifier and signal processing unit inside the circuit. At first, the referenced data is loaded when test circuit is in the load mode followed by the test mode where the charging capacitors are sequentially selected and their charges are discharged to the parasitic capacitors of the sequentially selected signal-lines to be tested, such that a charge-balanced signal is generated. This signal is amplified and compared with the loaded referenced-data in either digital or analog form. The compared result, which is related to the open/short circuit characteristic of the signal line to be tested, is going to be stored in the memory unit. At last, in the  reading mode, the stored data of the open/short circuit characteristic is going to be read to the external unit for further statistical process.
Patent TW-392258-B (TW)
Title: Semiconductor device having simple protective structure and process of fabrication thereof
Inventor: KIMURA NAOTO
IPC: H01L21/60
Filed: 1998-10-13
Granted: 2000-06-01
Abstract: A semiconductor integrated circuit device has a protective structure (23) between a semiconductor chip (21) and a ball grid array (22a), and the protective structure has a thin polyimide film (23a) bonded to the surface of the semiconductor chip (21) and a thick stress relaxation layer (23b) covering conductive strips (22d/22e) connected between pads (21c/21d) on the surface and the ball grid array (22a); when thermal stress is exerted on the ball grid array, the thick stress relaxation layer allows said ball grid array to move so as to take up the thermal stress.
Patent TW-445495-B (TW)
Title: Plasma processing apparatus
Inventor: HAMA KIICHI
IPC: H01L21/205
Filed: 1998-10-19
Granted: 2001-07-11
Abstract: An induction-coupling type etching apparatus (100) includes an RF antenna (110) which is provided on a ceiling plate (108) of a processing chamber (102), and a suscepter (116) mounted inside the processing chamber (102) for carrying a semiconductor wafer W. The ceiling plate (108) includes a matrix based on an alumina ceramics, and a heat-generating element formed by an oxide salt of a transition metal which is dispersed in the matrix and which itself can produce heat depending on the RF electric field.
Patent TW-407388-B (TW)
Title: Gas insulated switch device and the replacement method of its branch circuit element
Inventor: TSUZURA KEIICHI
IPC: H02B1/20
Filed: 1998-10-31
Granted: 2000-10-01
Abstract: This invention relates to a gas insulated switch device and the replacement method of its branch circuit element, particularly to the gas insulated switch device and the replacement method of its branch circuit element suitable for solving the accident. This invention is to provide: a gas-insulated switch device with an adequate construction by using one of the two circuits as a short circuit main bus unit during accident, without having to prepare a short-circuit bud unit in advance. In a gas-insulated switch device, in which connect first and second main buses and circuits branching from both the buses together in an unit housing breakers 51 or the like in an unit inside a container filled with a high pressure gas, repairing work can be performed without interrupting the electric power to an electric station by interrupting power either to a first or second main buses 1, 2. Main bus disconnector units with power interrupted are rotated and then reconnected, power is applied to the rotated main bus disconnector units. Then after the other main bus has been power-interrupted and gas has been taken out from the power-interrupted main bus disconnector unit, and a branch circuit unit to be repaired is removed from the main bus.
Patent TW-422983-B (TW)
Title: Redundancy circuitry with minimized area and reduced speed penalty for random access memories
Inventor: HUANG JIE
IPC: G11C29/00
Filed: 1999-04-30
Granted: 2001-02-21
Abstract: A system and method of implementing column redundancy in a memory system in which a single set of redundant columns is provided in one of a plurality of blocks of columns which is the fastest to receive decoded select signals or which is physically located closest to decode circuitry. In normal operation, the decode circuitry selects a single column and block as determined by the input address signal. In redundancy mode, the input address is compared to a pre-programmed repair column and block address corresponding to the a previously determined defective column and a match signal is generated. The match signal functions to enable the block having the redundant columns and disable the sense amplifiers of all other blocks. In addition, the match signal disables all of the columns in the selected redundancy block other than a single redundant column. As a result, all redundant columns have approximately the same access time as the fastest block of columns in the memory system. In addition since, redundant columns are not included in each block of columns, a reduced number of redundant columns are used and silicon space is conserved.
Patent TW-410342-B (TW)
Title: Integrated program verify page buffer
Inventor: KOWSHIK VIKRAM
IPC: G11C16/34
Filed: 1998-12-21
Granted: 2000-11-01
Abstract: A semiconductor memory includes a plurality of memory cells and a corresponding plurality of page buffers. When writing to a selected row of cells, input data is first latched into the page buffers. The cells in the selected row are then programmed according to the data latched within the page buffers. After programming, data stored in the cells is forwarded to the corresponding page buffers. If, for each cell, the data stored in the cell matches the data latched in its corresponding page buffer, the page buffer is reset. The selected row of cells are subsequently re-programmed, whereby only cells corresponding to those page buffers which have not been reset are re-programmed. In this manner, cells properly programmed during the first program operation are not re-programmed during program verify operations.
Patent TW-406383-B (TW)
Title: Stack type chip package
Inventor: HUANG JR-GUNG
IPC: H01L23/28
Filed: 1999-03-26
Granted: 2000-09-21
Abstract: A stack type chip package is able to form a module with a neighboring stack way to stack the packaged chip by utilizing said kind of the electricity connecting joint of the exposed package. The size of the lead finger of this package is smaller than the traditional one and corresponds with the trend of chip size package. This package could package a plurality of chip and conform with the trend of multiple chip module package.
Patent TW-403969-B (TW)
Title: Method for manufacturing metal oxide semiconductor
Inventor: CHEN JIN-LAI
IPC: H01L29/49
Filed: 1999-04-09
Granted: 2000-09-01
Abstract: A method for manufacturing metal oxide semiconductor comprises of producing a first dielectric layer that is formed conformal on both the gate electrode and the substrate surface; and then, form a spacer outside the first dielectric layer produced conformal on sidewall of the gate electrode. Then, use the isotropic etching method to remove part of the first dielectric layer until the first dielectric layer almost punch through the lower portion of the spacer, and the sidewall between the spacer and the gate electrode is also partially exposed. Then, deposit a second dielectric layer on the gate electrode. Therefore, during the process of depositing the second dielectric layer, it will form holes between the bottom of the spacer and the substrate, and holes between the gate electrode and the spacer.
Patent TW-409317-B (TW)
Title: Manufacture of semiconductor device and semiconductor device
Inventor: SHIOKAWA YOSHIMASA
IPC: H01L21/3215
Filed: 1999-05-12
Granted: 2000-10-21
Abstract: The objective of this invention is to shorten manufacturing process of a semiconductor device having a silicide diffusion layer and a non-silicide diffusion layer, and provide a manufacture method for semiconductors with even reliable non-silicide diffusion layers (high resistance non-silicide diffusion layer). Therefore ion implantation for forming a source and drain diffusion layer is performed, continuously, thermal oxidation treatment is rapidly performed in a short time, and a new thermal oxide film is formed while activating the ions. Then, the thermal oxide film 6 constituted of the newly formed thermal oxide film containing the protective oxide film 3 is etched to form an oxide film 8 for siliciding block to prevent the oxidation of the silicides and includes the entire surface of such oxide film 8. A Ti film 9 is formed on the whole surface containing the oxide film 8 for siliciding block. After the annealing treatment for siliciding is performed, Ti film 9 that has been reacted is eliminated. As a result, a diffusion layer 4 as a non-silicide layer having high non-silicide property, and a diffusion layer 5 having a silicide layer 10 on the surface are formed.
Patent TW-480813-B (TW)
Title: Miniaturized multi-layered ceramic low-pass filter
Inventor: SHEEN JYH-WEN
IPC: H03H7/12
Filed: 1999-05-20
Granted: 2002-03-21
Abstract: Under the stripe line framework, a low-pass filter contains the followings: the first dielectric layer with an upper and a lower surfaces, in which the first grounding metal layer is placed on the lower surface, and a first metal plate containing capacitive devices and a terminal is formed on the upper surface; the second dielectric layer, which is stacked on the first metal plate and has an upper and a lower surfaces such that the first metal layer is placed on the lower surface, and a second metal plate containing capacitive devices and terminals is formed on the upper surface; the third dielectric layer, which is stacked on the second metal plate and has an upper and a lower surfaces such that the second metal layer is connected to the lower surface, and a metal isolation layer is located on the upper surface of the second dielectric layer; the fourth dielectric layer, which is stacked on the metal isolation layer and has an upper and a lower surfaces such that the metal isolation layer is connected to the lower surface, and a stripe line treated as an inductive device on the upper surface of the fourth dielectric layer has the first and the second terminals; and the fifth dielectric layer, which is stacked on the stripe line layer and has an upper and a lower surfaces such that the stripe line layer is connected to the lower surface, and the second metal grounding layer is perpendicular to the upper surface of the fifth dielectric layer. The first side electrode is formed on the first side of the entire stacked layer, and the second side electrode is formed on the second side of the stacked layer stated above. The terminal point of the first metal plate and the first terminal point of the stripe line are connected with the first side electrode. The terminal point of the second metal plate and the second terminal point of the stripe line are connected with the second side electrode. The first and the second side electrodes stated above become the input/output terminal of the low-pass filter. The invented low-pass filter not only can be manufactured by the micro stripe line circuit and stripe line circuit, but also can be manufactured by using the multi-layered ceramic circuit that is obtained by mixing micro stripe line circuit and stripe line circuit.
Patent TW-376303-B (TW)
Title: Automatic device for shirring food
Inventor: QUE XIU-RU
Filed: 1999-05-25
Granted: 1999-12-11
Abstract: The present invention relates to an automatic device for shirring food, particularly an automatic device for making shirred food. The device comprises a plurality of material storage and feeding devices, a heating and shoveling device and a steel frame. The material in each storage and feeding device is delivered to the heating device via the material feeding device. The heating and shoveling device uses an upper heating device and a lower heating device to shirr and cook both sides of the material and control the shirring and cooking time. After the shirring and cooking is complete, the shoveling device pushes the product to a product removal position. The invented automatic device for shirring food can achieve a fully automated production of shirred food.
Patent TW-388739-B (TW)
Title: Method for constructing decorative optical fiber cluster and constituted object thereof
Inventor: LI JIN-HUEI
IPC: B44C5/00
Filed: 1999-06-30
Granted: 2000-05-01
Abstract: The present invention relates to a method for constructing a decorative optical fiber cluster and an constituted object thereof, particularly to a method for constructing a decorative cluster from an optical fiber rod, and an advanced use of the constructed article. The method essentially comprises arranging a plurality of optical fiber rods having a specified rigidity into a cloth-like optical fiber row; preforming the optical fiber row from the waist portion thereof into a gradually extending angle; winding the optical fiber row into a cluster where the optical fiber rods are uniformly distributed radially and the projecting end of the cluster can obtain a glob-shape point illumination and have a good positioning effect. Alternatively, the cluster can be carried by a carrier so that the projection end exhibits an optical ring of various shapes.
Patent TW-466443-B (TW)
Title: Method for preventing infection of computer virus
Inventor: LIN KUANG-SHIN
IPC: G06F9/00
Filed: 1999-07-05
Granted: 2001-12-01
Abstract: The invention relates to a method for preventing infection of computer virus, particularly specifying a method capable of instantly quarantining the infection paths prior to the occurrence of computer virus. By means of the synchronous processing and communication in Ring0 layer and Ring3 layer, the currently operating application program is monitored and controlled. When detecting operation code pertinent to the one issued by computer virus, all related operation messages are immediately intercepted, the related operation and a prompt message is simultaneously sent to inform the user. After the user has verified, corresponding virus protection processing is performed, thereby allowing to attain the goal in blocking intrusion of computer virus and distribution to other system, program or documents at the best timing.
Patent TW-522294-B (TW)
Title: Structure of revolving shaft of desktop liquid crystal display computer
Inventor: SUN MING-SHEN
IPC: G06F1/00
Filed: 1999-07-22
Granted: 2003-03-01
Abstract: The present invention provides a structure of revolving shaft of desktop liquid crystal display (LCD) computer. The revolving shaft includes a base, a supporter suitable for supporting the desktop LCD computer, and a positioner for preventing the supporter from moving relatively to the base. The base has a tip and a pair of separation positioning plates installed at the tip. The supporter is installed between the two separation positioning plates and can move from the first direction towards the second direction relatively to the base. The positioner is used for preventing the supporter from moving relatively to the base and, therefore, positioning the supporter.
Patent TW-414987-B (TW)
Title: Method of improving adherence between Al pad and Cu pad
Inventor: CHEN SHENG-SHIUNG
IPC: H01L21/60
Filed: 1999-08-10
Granted: 2000-12-11
Abstract: A method of improving the adherence between a Al pad and a Cu pad comprises forming an insulating layer on a substrate and forming a Cu pad in the insulating layer. A passivation layer is deposited on the Cu pad to prevent inner circuits from moisture erosion or outside damage. An opening is formed in the passivation layer by photolithography and etching process to expose the Cu pad. A plurality of pillars are formed in the opening. A thin buffer layer is deposited uniformly on the passivation layer, the opening and the surface of the pillar structures. The buffer layer can be made of TaN. An Al layer or Al-Cu alloy layer is formed on the buffer layer. A pattern is transferred from a photo mask to a photoresist layer on the Al layer. A Al pad is formed by patterning the Al layer and the buffer layer by etching process.
Patent TW-434866-B (TW)
Title: Manufacturing method for contact plug
Inventor: LIN DA-CHENG
IPC: H01L21/768
Filed: 1999-08-13
Granted: 2001-05-16
Abstract: A manufacturing method for contact plug which includes the following steps: firstly, providing the dielectric on a silicon substrate that the dielectric comprises an opening to expose the silicon substrate, so that the exposed silicon substrate has an original oxide thin layer; then, sequentially depositing the first conformal and the second conformal doped polysilicon layer to partly fill up the opening in which the dopant density of the first doped polysilicon layer is higher than the dopant density of the second doped polysilicon layer; next, depositing the third doped polysilicon layer in the opening to cover the first and the second doped polysilicon layer in which the dopant density of the doped polysilicon layer is smaller than the dopant density of the first and the second doped polysilicon layer; then, conducting annealing on the first, the second and the third doped polysilicon layers.
Patent TW-432826-B (TW)
Title: Method for improving signal transmission and reception of RF remote control
Inventor: JOU HUNG
IPC: H04B7/00
Filed: 1999-10-21
Granted: 2001-05-01
Abstract: The present invention relates to a method for improving signal transmission and reception of an RF remote control. By way of synchronous process, each bit transmitted forms a calibration signal consisting of a synchronous bit and a data bit. Then, by comparing the pulse widths of the two bits, whether the data bit is high or low can be determined so as to avoid any signal bandwidth variation due to weak signal. Consequently, transmission distance can be increased significantly and, thus, data reception will be accomplished correctly.