Patent GB-1265213-A (GB)
IPC: H04L1/24
Filed: 1969-07-03
Abstract: 1,265,213. Data transmission systems. NETHERLANDS POSTAL & TELECOMMUNICATION SERVICE, DIRECTOR GENERAL OF. 3 July, 1969 [12 July, 1968], No. 33558/69. Heading H4P. To equalize the numbers of 0's and 1's transmitted over a given period, groups of oddnumbered telegraph signals are analysed to determine the degree of disparity between the numbers, those signals exhibiting a predetermined major degree of disparity being converted to parity signals in accordance with a predetermined code and those exhibiting minor disparity being transmitted without conversion in either normal or inverted form in dependence upon a sense required to bring the numbers, during a given interval, most nearly to equality. A first number dependent on bits of one kind e.g. a "1", is compared with a second number representing the difference between numbers of the two kinds controls a selective inverting device which can invert the bits after a bit of the specified kind has been added. The receiver counts the bits of the same kind increased by one, which number is compared with the total number of bits hence a re-inverting device is operated.  In the transmitter, a pulse register 34 generates sequences of pulses a-f recurring each 8-bit period. A first counter 30 including flip-flops G-I is connected via AND gate 25 to shift registers CA-CG. A balancing counting device 32 (see also Fig. 5, not shown) is stepped up through AND gate 26 and down through AND gate 27 and has five flip-flops A-E of which only A has output terminals A0 and A1 into a comparison device 33 which compares the outputs of flip-flops G-I in counter 30 with that of balancing device 32 (see Fig. 3, not shown), and determines the state of a flip-flop F in a logic circuit comprising AND gates (35-40) and OR gates (37-41) which can pass a positive potential to F via AND gate (42) giving a positive output on line 1, and a logic circuit comprising AND gates (45, 46) and OR gates (44, 47) providing a positive potential through AND gate (43) fiving a positive output on line 0. Flip-flops CA-CG and DA-DG are connected by a circuit 29 which includes a converter controlled by gates G-I in counter 30 and DH provides the additional bit. The output of the arrangement is via a transmission flipflop 31. A pulse c appearing in the first bit period causes transfer of information from source 28 via gates 1-7 to flip-flops CA-CG contents of which are shifted via gates 8-14 by one register place every b pulse, 7b pulses restoring the register to the state before the first pulse. The 1 bits shifted via gate 8 to flip-flop CG are counted at 30. At the end of a 7-bit period the previous contents of register DA-DH have been transmitted by an a pulse controlling gates 15-21 which bits have been also summed in device 32, hence flip-flop A, counter 32 indicates the type of deficiency bits which sets the flipflop F to give a corresponding output thus determining the states of gates 22, 23 for the next 8-bit period and hence whether the bits in DA-DH will be transmitted directly or inverted, according to table C, Fig. 7 (not shown). Such inversion takes place when an e pulse occurs dependent on the states of AND gates (50 &c., Fig. 6, not shown). At the end of this 8-bit period, a pulses shift bits from register DA-DH, the state of flipflop F controlling normal/inverting gates 22, 23. For the purposes of classification, the 8-bit signals are divided into those having an equal number of 0's and 1's, i.e. having a 4 : 4 ratio, nine of which ending in a 1 bit are used for conversion and 26 ending in a 1 bit are used for instructions. A further eleven signals having other ratios, e.g. 2 : 6, may also be used for instructions. At the receiver signals are restored to their original form, the received 4 : 4 variations ending in a 1 bit being converted to their original form and other variations, e.g. 2 : 6 also ending in a 1 bit are inverted, both operations being controlled by a device counting the number of 1 bits in each variation. If in the transmitter the difference in numbers between 0 and 1 bits, e.g. zero, is compared with the difference registered in a similar device in the receiver, errors can be ascertained.