baber/WOPTO huggingface dataset:
Patent TW-I262488-B (TW)
Title: Power control method for laser beam of optical recording system and device thereof
Inventor: CHEN CHIH-YUAN
IPC: G11B7/0045
Filed: 2002-03-29
Granted: 2006-09-21
Abstract: The present invention relates to a power control method for laser beam of optical recording system and device thereof, in which the optical recording system has a light source providing an incidence light write signal for recording data on an optical recording medium; the method includes the following steps of: employing a light detection circuit to detect and obtain a reflected write pulse of the incidence light incidence write signal; using a mark formation effectiveness signal generation circuit to generate a mark formation performance signal representing the optical recording performance based on the reflected write pulse; and, employing a laser power compensation circuit containing a filter to separate a first and a second components from the mark formation effectiveness signal, and controlling the output power of the light source according to the first and second components.
Patent TW-I238634-B (TW)
Title: Data recording apparatus, data recording method, and data transfer system
Inventor: ABE MIKI
IPC: G06F21/62
Filed: 2002-04-02
Granted: 2005-08-21
Abstract: The subject of the present invention is to greatly reduce the processing and transferring time of content data. When plural encrypted content data stored in the primary recording media together with the key information of plural content data are transmitted to the sub-recording media, the root key inspection and processing are skipped if the key information of one content data desired to be transmitted from the primary recording media is the same as the key information of one content data that has been transmitted so as to greatly reduce the processing and transferring time of content data.
Patent TW-591945-B (TW)
Title: Image processing circuit, image display device, and an image processing method
Inventor: TOMIZAWA KAZUNARI
IPC: G09G3/36
Filed: 2002-04-24
Granted: 2004-06-11
Abstract: The present invention is arranged such that interlace image data, which has been supplied, is converted to progressive image data in an I/P conversion section, and the image data converted to progressive style in the I/P conversion section is subjected to image processing including data comparison in spatial or time series manner, in an image processing section.
Patent TW-I242129-B (TW)
Title: ATM-based VPN failure management software process
Inventor: SHIU TZU-YI
IPC: G06F13/00
Filed: 2002-05-07
Granted: 2005-10-21
Abstract: An ATM-based VPN failure management software process that is capable of transmitting the alarming information to the maintenance personnel or messages to the client's accounts, BB calls or cellular phones based on failure interpreter, failure screening and client information at the occurrences of the failure, so as to achieve of the object of active notification and immediate repair service. The method includes the use of a management and sorting module for managing and sorting the failures; a failure analyzing module for self-interpreting the failures; a failure screening module for providing subjects and methods of providing failure reports; and a failure post processor for eliminating duplicate transmission and tracking transmission.
Patent TW-550920-B (TW)
Title: Semiconductor integrated circuit and data conveying system
Inventor: OZAWA SEIICHI
IPC: H04N1/36
Filed: 2002-05-29
Granted: 2003-09-01
Abstract: A kind of semiconductor integrated circuit, in which the pixel data are continuously conveyed by the system as the primary data and the increase number of cable wire for transmission is not required, capable of maintaining the original conveying quantity and treating voice data as the secondary data for conveying is disclosed in the present invention. The semiconductor integrated circuit contains the followings: the primary data transmitting circuit, which changes the primary data into string column data, makes the string column data synchronous with the clock signal and transmit it via at least one transmitting path; and the secondary transmitting circuit, which uses the secondary data to conduct pulse width modulation onto the clock signal for generating the modulated clock signal with the determined order and at least three kinds of pulse width, and transmits the modulated clock signal via a transmitting path.
Patent TW-570819-B (TW)
Title: Dry powder inhalation system for transpulmonary administration
Inventor: YAMASHITA CHIKAMASA
IPC: A61K47/40
Filed: 2002-06-14
Granted: 2004-01-11
Abstract: The present invention provides a novel dry powder inhalation system suitable for transpulmonary administration. The dry powder inhalation system of the invention characterized by using a combination of: a vessel housing a freeze-dried composition that contains a single dose of an active ingredient, and has: (i) a non-powder cake-like form, (ii) a disintegration index of 0.015 or more, and (iii) a property of becoming fine particles having a mean particle diameter of 10 microns or less or a fine particle fraction of 10% or more upon receipt of an air impact having an air speed of at least 1 m/sec and an air flow rate of at least 17 ml/sec; and a device comprising means capable of applying said air impact to the freeze-dried composition in said vessel, and means for discharging the powder-form freeze-dried composition that has been made into fine particles.
Patent TW-578211-B (TW)
Title: Semiconductor structure
Inventor: BUCHANAN KEITH EDWARD
IPC: H01L21/768
Filed: 2002-07-18
Granted: 2004-03-01
Abstract: This invention relates to a semiconductor structure for dual damascene processing and includes upper and lower low k dielectric layers formed in a stack when the upper surface of the lower layer has an integral etch stop layer formed by exposing the upper surfaces of the layer to H2 plasma without any prior anneal prior to the deposition of the upper layer.
Patent TW-564546-B (TW)
Title: Semiconductor device, semiconductor memory device and the manufacturing method thereof
Inventor: IWATA HIROSHI
IPC: H01L21/8244
Filed: 2002-07-19
Granted: 2003-12-01
Abstract: A gate electrode side-wall conductive film 120 of the present invention is formed on the side wall of a gate electrode 118 via a gate electrode side-wall insulation film 119. This gate electrode side-wall conductive film 120 is properly removed by an anisotropic etching to be selective for the gate electrode side-wall insulation film 119, thereby separating the source region from the drain region and at the same time forming local wiring by the gate electrode side-wall conductive film 120. In addition, the gate electrode 118 is properly removed by etching to be selective for the gate electrode side-wall insulation film 119 to thereby form a gate electrode wiring at the same time. Accordingly, an SRAM device is provided that can be highly integrated by simplifying wiring and reducing the memory cell area.
Patent TW-548779-B (TW)
Title: Integrated capacitor and method of making same
Inventor: HU MAN-CHUN
IPC: H01L27/08
Filed: 2002-08-09
Granted: 2003-08-21
Abstract: An integrated capacitor including a semiconductor substrate is disclosed. An outer vertical plate is laid over the semiconductor substrate. The outer vertical plate consists of a plurality of first conductive slabs connected vertically using multiple first via plugs. The outer vertical plate defines a grid area. An inner vertical plate is laid over the semiconductor substrate in parallel with the first vertical plate and is encompassed by the grid area defined by the outer vertical plate. The inner vertical plate consists of a plurality of second conductive slabs connected vertically using multiple second via plugs. A parallel conductive plate is laid under the outer vertical plate and inner vertical plate over the semiconductor substrate for shielding the outer vertical plate from producing a plate-to-substrate parasitic capacitance thereof. The inner vertical plate is electrically connected with the parallel conductive plate using at least one third via plug.
Patent TW-565757-B (TW)
Title: Method and apparatus for determining liquid flow rate
Inventor: WINTERS LEONARDUS CORNELUS ROB
IPC: G01F1/704
Filed: 2002-09-19
Granted: 2003-12-11
Abstract: The present invention provides a method and related apparatus for determining the rate of flow of a liquid, the liquid comprising a first liquid delivered to a point (24) with at least a second liquid to form a solution of the first and at least second liquids, the method comprising the steps of determining the rate of flow of the at least second liquid, delivering the solution to a conductivity-measuring means (38) by which the conductivity of the solution is measured, determining the ratio between the first and the at least second liquids in the solution on the basis of the conductivity of the solution and determining the rate of flow of the first liquid on the basis of the rate of flow of the at least second liquid and said ratio and wherein the rate of flow can be employed in calibrating a flow controller controlling the rate of flow of the first liquid.
Patent TW-558815-B (TW)
Title: Semiconductor package with ground component and fabrication method thereof
Inventor: CHEN NAN-JANG
IPC: H01L23/36
Filed: 2002-10-09
Granted: 2003-10-21
Abstract: A semiconductor package with ground components and a fabrication method of the semiconductor package are provided, in which at least a folded ground lane is mounted onto an opening of a substrate with a chip being received in the opening. The folded ground plane is shaped to have an erect portion and a planar portion integrally formed with the erect portion. The erect portion is attached to a side wall of the opening without interfering with the chip; the planar portion is attached to a circuit surface of the substrate, and electrically connected to the chip by ground wires. When the substrate and the chip received within the opening are mounted on a heat sink, the erect portion of the ground plane is adapted to be electrically connected to the heat sink, thereby forming a grounding path including the chip, ground wires, ground plane and heat sink, so as to provide satisfactory grounding effect for the chip. Moreover, with the erect portion of the ground plane being mounted to the side wall of the opening and surrounding the chip, it provides excellent electromagnetic shielding effect to reduce electromagnetic interference (EMI) with the chip.
Patent TW-I239852-B (TW)
Title: Antiseptic absorber of chitosan and the method of making the same
Inventor: JUO FU-CHIUAN
IPC: A61L15/28
Filed: 2002-10-09
Granted: 2005-09-21
Abstract: An antiseptic absorber of chitosan comprises an absorber, an antiseptic coating formed by coating an antiseptic solution over the absorber and heating the coating. The production of chitosan antiseptic absorber includes the following steps: (1) preparing an antiseptic solution by mixing chitosan, acidic water solution, and an activator; and (2) smearing the antiseptic solution over the absorber and heating it until dry. This invention restrains the growth of bacteria, and is able to remain dry in case of liquid without ropiness for an antiseptic and mildew proof absorber.
Patent TW-I261917-B (TW)
Title: Non-volatile memory device with improved data retention and method therefor
Inventor: CHINDALORE GOWRISHANKAR L
IPC: H01L29/792
Filed: 2002-12-12
Granted: 2006-09-11
Abstract: A semiconductor device (30) comprises an underlying insulating layer (34), an overlying insulating layer (42) and a charge storage layer (36) between the insulating layers (34, 42). The charge storage layer (36) and the overlying insulating layer (42) form an interface, where at least a majority of charge in the charge storage layer (36) is stored. This can be accomplished by forming a charge storage layer (36) with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer (36) comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer (36) and the overlying insulating layer (42), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer (34) to be used.
Patent TW-574746-B (TW)
Title: Method for manufacturing MOSFET with recessed channel
Inventor: DIAZ CARLOS H
IPC: H01L21/8238
Filed: 2002-12-19
Granted: 2004-02-01
Abstract: A method for manufacturing a MOSFET with a recessed channel is described. To manufacture the MOSFET, a first sacrificial layer is formed on a semiconductor substrate first. Then, a source/drain is formed in the semiconductor substrate uncovered by the sacrificial layer. After a second sacrificial layer is formed on the source/drain, the first sacrificial layer and a portion of the semiconductor substrate under the first sacrificial layer are removed to form an opening. Thereafter, a sacrificial spacer is formed alongside an interior surface of the opening, a gate oxide layer is formed at the bottom of the opening, and a gate conductive layer is formed to fill the opening. The second sacrificial layer and the sacrificial spacer are removed. Finally, a lightly doped source/drain is formed in the semiconductor substrate.
Patent TW-589719-B (TW)
Title: Method for manufacturing flash memory
Inventor: JENG PEI-REN
IPC: H01L21/8247
Filed: 2003-01-24
Granted: 2004-06-01
Abstract: A manufacturing method of flash memory includes forming a tunnel dielectric layer and a conductive layer on a substrate sequentially; performing an etch process to pattern the conductive layer forming a floating gate; forming two source/drain regions beside floating gate and in the substrate; forming an inter-gate dielectric layer on the floating gate. The inter-gate dielectric layer comprises an oxide layer which is formed by in-situ steam generation (ISSG) process; forming a control gate on the inter-gate dielectric layer.
Patent TW-I231603-B (TW)
Title: Semiconductor device, thin film transistor, circuit device and liquid crystal display
Inventor: HIRAMATSU MASATO
IPC: H01L21/336
Filed: 2003-03-11
Granted: 2005-04-21
Abstract: A thin film transistor comprising a conductive semiconductor layer (11), a source area (12) and a drain area (13) separately disposed within the semiconductor layer, and a gate electrode (14) provided above or under the semiconductor layer with an insulative film interposed therebetween is disclosed, wherein the length (Ws) of the attachment surface between the source area and a channel area (16) disposed between the source area and the drain area differs from the length (Wd) of the attachment surface between the drain area and the channel area.
Patent TW-I264017-B (TW)
Title: Integrated memory using prefetch architecture and method for operating an integrated memory
Inventor: SCHROEDER STEPHAN
IPC: G11C7/10
Filed: 2003-04-23
Granted: 2006-10-11
Abstract: An integrated memory comprises not only a memory cell array with memory cells (MC) but also a connection area (AF) for externally tapping data of the memory cells which is to be read out. The memory is operated using a prefetch architecture, in which, when there is a memory access operation, a first data group (D1) of memory cells from a first zone (a) and a second data group (D2) of further memory cells from a second zone (b) of the memory cell array are fed in parallel to an output circuit (FFn) and the first and second data groups (D1, D2) are output successively via the connection area. The first and second zones (a, b) are always defined for a plurality of memory access operations in such a way that the first data group (D1) has a shorter signal transit time to the connection area (AF) than the second data group (D2). As a result, the external outputting of data can be brought forward, and the operating frequency can thus be increased.
Patent TW-I264220-B (TW)
Title: Progressive image transmission by adaptive interpolation
Inventor: SHIH TIMOTHY K
IPC: H04N1/64
Filed: 2003-04-28
Granted: 2006-10-11
Abstract: Progressive image transmission is a mechanism that transmits the most significant portion of an image, followed by its less important parts. Applications of such a mechanism include browsing large image files on the Internet. We propose an adaptive mechanism, based on the characteristics of images. The mechanism use neighbor pixels to guess a target pixel value, without actually transmitting the target pixel. An error correction scheme is also designed to cope with a failure guessing. Preliminary results should that the transmission rate is lower than others, with reasonable PSNR values of the transmitted images.
Patent TW-I225767-B (TW)
Title: Heat-dissipating module structure for electronic apparatus
Inventor: HSIEH HUNG-CHANG
IPC: H05K7/20
Filed: 2003-06-13
Granted: 2004-12-21
Abstract: A heat-dissipating module structure for electronic apparatus is disclosed. The heat-dissipating module structure includes a case having a top face, a bottom face, a first side and a second side, wherein the first side is opposite to the second side; a heat-dissipating fan disposed on the first side of the case a first vent disposed on the second side of the case; a second vent disposed on the top face of the case; and a printed circuit board disposed in the case to form a first airflow channel between the top face of the case and the printed circuit board and to form a second airflow channel between the bottom face of the case and the printed circuit board, wherein the heat generated in the second airflow channel by the printed circuit board is higher than that generated in the first airflow channel by the printed circuit board, and the sectional height of the second channel from the printed circuit board to the bottom face of the case is larger than that of the first airflow channel from the printed circuit board to the top face of the printed circuit board.
Patent TW-I229819-B (TW)
Title: Card connector with selective card stop mechanism
Inventor: HIRATA HIDEYUKI
IPC: H01R13/631
Filed: 2003-06-27
Granted: 2005-03-21
Abstract: A stop mechanism is disclosed for selectively restricting insertion of a card into a card slot of a card connector. The stop mechanism is positioned in the card slot along a path of insertion of the card into the card slot. A card having a thickness less than a predetermined thickness engages a stop portion of the stop mechanism when inserted into the card slot, preventing further insertion of the card past the stop mechanism. A card having a thickness greater than the predetermined thickness contacts an engagement portion of the stop mechanism when inserted into the card slot, producing a movement of the stop mechanism out of the path of card insertion.
Patent TW-I276426-B (TW)
Title: System for evaluating Chinese medicine yin-yang constitution of human body by variation of heart rate
Inventor: CHIU CHUANG-CHIEN
IPC: A61B5/02
Filed: 2003-06-27
Granted: 2007-03-21
Abstract: The present invention relates to a system for evaluating Chinese medicine yin-yang constitution of human body by variation of heart rate includes: an electrocardio signal retrieval module, an electrocardio signal analysis module, and a yin-yang constitution evaluation module. The electrocardio signal retrieval module and the electrocardio signal analysis module are used to retrieve a plurality of analog electrocardio signals of a person under examination for generating a spectrum analysis diagram and displaying the energy distribution of a low frequency region and a high frequency region. Based on the energy distribution of the low frequency region and the high frequency region, the yin-yang constitution evaluation module calculates a low frequency energy of the low frequency region and a high frequency energy of the high frequency region to evaluate the yin-yang constitution of the person under examination, in which, a person is strong in yang or weak in yin if his/her low frequency energy is far higher than his/her high frequency energy; on the other hand, a person is strong in yin or weak in yang if his/her high frequency energy is far higher than his/her low frequency energy. Thus, a yin-yang constitution evaluation system according to the present invention can use the electrocardio signal of a person under test to automatically determine the yin-yang constitution of the person for assisting the modernization and computerization of Chinese medicine and the clinical research of Chinese medicine, while objectively evaluating the yin-yang constitution of a person under test.
Patent TW-593871-B (TW)
Title: Intelligent diesel engine exhaust treatment system
Inventor: SHIU CHENG-WU
IPC: F01N13/04
Filed: 2003-07-08
Granted: 2004-06-21
Abstract: Disclosed is an intelligent diesel engine exhaust treatment system, including: an exhaust flowing zone, a microcomputer based controller and an exhaust detecting device. The exhaust flowing zone defines a first exhaust treatment path and a second exhaust treatment path. The microcomputer based controller employs an exhaust filter and a catalyst converter to purify the engine exhaust based on the degree of contamination of the engine exhaust as detected by the exhaust detecting device.
Patent TW-I285045-B (TW)
Title: Method and apparatus for flat patterned media inspection
Inventor: WEISS ADAM
IPC: G01B11/30
Filed: 2003-10-28
Granted: 2007-08-01
Abstract: A concurrent low resolution/high resolution parallel scanning system and method are provided as an improvement in the scanning process of an inspection system for planar objects, such as large flat plates employed in panel displays, whereby lower resolution defect detection efficiently overlaps and parallels higher resolution defect review and classification stages in which defects are automatically defined and resolved. Although the invention is a valid solution for the more general problem of optically inspecting the surface of a flat article for defects, the invention is particularly useful for detecting pattern defects on large glass plates deposited with integrated-circuits for forming LCD flat panel displays.
Patent TW-I269162-B (TW)
Title: Memory interleaving
Inventor: WOLRICH GILBERT
IPC: G06F12/06
Filed: 2004-01-05
Granted: 2006-12-21
Abstract: Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.
Patent TW-I270774-B (TW)
Title: Memory control method and related device
Inventor: HSU CHIEN-HUA
IPC: H04L12/28
Filed: 2004-01-20
Granted: 2007-01-11
Abstract: The present invention provides a memory control method and related device. The method includes storing a bit stream into a memory, reading from the memory a header corresponding to the bit stream, and rearranging data stored in the memory according to the header within a part of the region storing the bit stream. Wherein the rearranging step moves or copies the data in the memory to a part which is already read in the region storing the bit stream.