Patent GB-718895-A (GB)
Title: Improvements in or relating to electronic digital computing engines
Inventor: TURING ALAN MATHISON
IPC: G06F9/30
Filed: 1950-05-04
Abstract: 718,895. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. April 18, 1951 [May 4, 1950], No. 11087/50. Class 106 (1) In an electronic digital calculating-apparatus stored information is transferred from one part to another by setting un a transfer route in accordance with address signals in an instruction word and timing the transfer in accordance with a timing number and a characteristic code of at least two digits in the instruction word so that the timing member determines the commencement or the duration of the transfer in a manner which differs with some or all different permutations of the characteristic code digits. The apparatus described has a major cycle of 32 minor cycles each of 40 digits ; it has 256 sources and destinations (acoustic delay lines), of which 32 are for instructions, and 16 function circuits (not described) for performing arithmetical or logical operations. The output of each tank is connected through first and second "source" gates respectively to two buses. A further bus is connected to the inputs of the tanks through " destination " gates. Between the two " source " buses and the function circuits are connected a pair of gates which are conditioned by a timing trigger which also conditions the "destination" gates. Consequently, a transfer commences when the timing trigger goes on and continues until the trigger is restored. The instruction word includes a timing number n of five digits in the P35-P39 position and characteristic digits a and # in positions P34 and P40, the permutation of which determines which of four kinds of transfer shall take place. The kinds of transfer are known as immediate, long, deferred and serial. In the first two cases, the transfer commences in the minor cycle fo'lowing that in which the instruction is staticized and continues for n+1 or n+33 minor cycles. In the last two cases, the transfer lasts for one minor cycle only and takes place after n minor cycles. In all cases except the serial transfer, the next instruction is staticized in the minor cycle immediately following the end of the transfer, but in a serial transfer, it is staticized in minor cycle 33. An instruction is staticized under the control of a P40 pu'se at SN, Fig. 2. This pulse normally passes through a half-unit delay 11 to switch on a trigger SU which thereupon conditions a gate 19 so that the instruction passes to a staticizer STA from a short delay line INST to which it has been gated from an instruction source (long tank) selected by the previous instruction. The programme is so arranged that the instruction appearing at the end of the selected delay line at this time is the next to be carried out. The triggers set in accordance with the instruction word condition the source, destination, function and next instruction gates in preparation for a transfer which takes p!ace when the timing trigger is on. Digits P35-P39, i.e. the timing number, of the instruction word also pass through a gate 20 conditioned by a trigger C which is on during the period P34¢- P39¢. The timing number is then negated at a gate 21 supplied with ones during this initial minor cycle by the trigger SU which is switched off at the end of the minor cycle by a P40 pulse gated through a gate 16 by the trigger SU. The ones now in the P34 and P40 positions are removed at a gate 22 and ones are added in the P29 and P35 positions during each cycle by a half-adder 23, the output of which is fed through a short tank CO back to the gate 21. The pulses entering the tank CO represent two six digit numbers in the positions P29-P34 and P35-P40. During the first minor cycle, these numbers will be 32 and 32-n respectively. Thus a P34 pulse occurs in the first minor cycle and is repeated every major cycle and a P40 pulse occurs after n minor cycles and again repeats every major cycle. The P40 pulses are passed by the gate 25 and are called N pulses. Each P34 pulse is passed by a gate 24 and temporarily puts on a trigger H which conditions a gate 26 to pass the next P40 pulse. The latter P40 pulses are called Z pulses. The staticized α and # digits are applied to condition various gates in the circuit for controlling the timing trigger TT. An immediate transfer results when the α and # digits are both zero. Then the first Z pulses pass gates 27 and 28 and a half-unit delay 29 to switch on the trigger TT at P40¢ in the first minor cycle. The following N pulse, after n minor cycles, passes a unit de'ay 31. a gate 32 conditioned by the trigger TT, and a gate 34, controlied in accordance with the α and # digits, to switch on a trigger I at PI in the next minor cycle. The trigger I conditions a gate 38 to pass the next P40 pulse through a half-unit delay 49 to switch off the trigger TT. The trigger I also conditions a gate 41 to pass a P40 pulse from gates 39 and 40 to the lead SN to staticize the next instruction. This pu'se is also applied through a unit delay 42 to switch off the trigger I. In a long transfer (α=0; #=1), the trigger TT is switched on in the same manner at the end of the first minor cycle. The first N pulse is, however, gated by the gate 35 to switch on a trigger L. This conditions a gate 36 to pass the succeeding N pulse through a 2-unit delay 37 to switch on the trigger I which as before causes the trigger TT and itself to be switched off at the end of the minor cycle. The trigger L is also switched off by the trigger I. In a deferred transfer (a=1 ; # =0), the first N pulse passes gate 30 and 28 to switch on the trigger TT after n minor cycles. The same pulse passes the gate 34 to switch on the trigger I a half-unit later at P1 in the next minor cycle. Consequently, the trigger TT remains on for one minorcycle only. Finally, if a and # are both one, a serial transfer takes place. The trigger TT is switched on after n minor cycles, for one minor cycle only as in the last case but the P40 pulse normally giving rise to the pulse on SN is blocked at the gate 39. The trigger I thus remains on to condition the gate 41 to pass the next Z pulse to the lead SN to cause the next instruction to be staticized. In any transfer operation if a discriminating trigger D has been switched on, the pulse at SN cannot pass the gate 12. However, it switches on a trigger E through a unit delay 13 and the trigger E conditions a gate 15 to pass the next P40 pulse through the half-unit delay 11 to switch on the trigger SU to staticize the next instruction a minor cycle later than if the trigger D had not been operated. The P40 pu'se restores the trigger D so that the next P29 pulse can pass a gate 14 to restore the trigger E. If a switch S is opened, each transfer operation may be initiated an integral number of minor cycles after it would otherwise have been, by operating a manual push-button M to switch on a trigger X. The latter conditions gate 44 to pass a P29 pulse to switch on a trigger Y which in turn. through a unit delay 45, switches off the trigger X and conditions a gate 46 to pass the next N or Z pulse, according to the α and # digits set up, to the trigger TT. This pulse restores the trigger Y through a unit delay. In a modification, the short tank INST for the next instruction is replaced by a series of delay units 55-60, Fig. 3. and that staticizer for the instruction word is subdivided, each part being connected between a pair of the delay units. Thus the 40-digit word may be completely staticized in the early part of a minor cycle, e.g. in the period P3-P10. It is thus possible to arrange the digits representing, e.g. the next instruction source, at the end of the instruction word. for the corresponding staticizer will have become quite stable by the beginning of the next minor cycle. The timing number may then be arranged at the beginning of the instruction word. " And " gates conditioned by clock pulses may be arranged between the delay units to overcome pulse-distortion. As shown, the timing number is in the position P1- P5. After passing through a five-unit delay 66, this number is negated by a gate 73 and staticized in the period P6-P10 on triggers N1-N5 connected by end elements E to form a counter. The gate 73 is conditioned by the trigger SU switched on by the initiating pu'se SN to condition gates leading to the staticizers, and restored by a P20 pulse. The triggers N are all switched on by the SN pulse but are all restored by a P3 pulse app'ied to the trigger N1 priot to the staticizing operation. In a similar manner, a similar group or triggers Z1-Z5 is zeroized by the first P3 pulse after the SN pulse. During each succeeding minor cycle, a P3 pulse adds one to the count in each group of triggers. When all the Z triggers are off a gate 72 is conditioned to pass a P40 pulse and when all the N triggers are on, the negated outputs condition a gate 74 to pass a P40 pulse. Thus, a Z pu'se is produced at the end of the first minor cycle and is repeated each maior cycle, and an N pu'se is produced after n minor cycles and is repeated each major cyc'e. The remainder of the circuit controlling the timing trigger TT is similar to that of the first embodiment. The acoustic delay lines may be rep'aced by magnetic storage devices as described in Specifications 707,634, 707,635, 707,637 and 717,113. Specifications 717,114 and 718,894 also are referred to.