Patent GB-1327779-A (GB)
Title: Data processing systems
IPC: G06F9/46
Filed: 1970-09-08
Abstract: 1327779 Data processing systems HONEYWELL Inc 8 Sept 1970 [12 Nov 1969] 43008/70 Heading G4A In a multiprocessor system, processors P1 and P2 have different instruction repertoires and independently execute first and second programmes respectively whilst sharing a common memory system 13, and upon detecting an instruction which is not in its repertoire, processor P1 conditions processor P2 to execute the out of repertoire instruction. Processor P1 may execute a number of user programmes on fixed length data fields, and processor P2 may execute a number of user programmes on variable length data fields, tasks being assigned to the processors by a master programme group, high speed and scientific tasks being executed by P1 and communication and editing tasks by P2. Memory system 13 comprises modules M1-MN to which access requests by processors P1, P2 are routed over independent paths 17 by memory controller 16. Simultaneous access requests for the same memory module are allocated on priority basis. Predetermined segments IPC of the memory are assigned to P1, P2 for controlling inter-processor communications. Word processor P1, Fig. 2.-Instructions read from a main memory module to data register 152 have three fixed length address fields A, B, C and starting addresses for read-only control memories 142, 224. A sequence controller 150 derives from an instruction a starting address of a first microinstruction and sends it to address register 144. The microinstruction read from ROM 142 is decoded at 148 to produce subcommand signals controlling transfer gates in the processor, successive locations in ROM 142 being addressed by incrementing register 144 until the end of that microinstruction sequence is reached. Sequence controller 150 then provides the starting address for the next microinstruction sequence. Each operand address generated at 164 accesses main memory to read the contents of the specified address to AU 221. When the last microinstruction of the last sequence is reached, sequence controller 150 generates the starting address of a microinstruction sequence for computing the first main memory address for retrieving the next programme instruction. While the starting address of a first microinstruction sequence is being generated by sequence controller 150, the OP code of the programme instruction is transferred to register 230 providing the starting address of the AU control ROM 224 at which the sequence of microinstructions for executing the OP code are stored. If, during execution of a user programme, a multiprogramme control (MPC) instruction is reached, this instruction signifying that a character-oriented operation is required, the OP code is used to initiate a microinstruction sequence for determining the action required. Microinstruction decoder 228 signals address register 144 to read out a microinstruction from ROM 142 which results in generation of a main memory address assigned to the master programme group, the next microinstruction transfers the C address of the MPC instruction to this address and the next microinstruction causes a subcommand signal 164 to increment address register 222. The resulting microinstruction from ROM 224 causes a set of control signals to be supplied to a sequence traffic control 400 which decodes the B address of the MPC instruction to produce a trap signal forcing register 222 to address the start of a microinstruction sequence for transferring control to the master programme group. This operation involves storing a message word generated at 240 in the IPC segment for processor P1, loading a status word generated by AU 220 into IPC storage, and storing the master programme status in a control memory 302. The master programme then translates the message word into character instruction format suitable for processor P2 and calls that processor. Character processor P2, Fig. 3.-Before fetching an instruction, processor P2 executes a sequence of test (BST) instructions to check on certain system conditions, using logic 722. Presence of a call signal from P1 causes transfer of the contents of a branch address register to address register 704 to start a microinstruction sequence for transferring a memory block key from register 534 to register 508, transferring the base relocation address of the present programme to control memory 502, storing the machine status, and transferring the translated message word from P1 IPC storage into register 522 from which the OP code, key code and base relocation address are transferred to registers 616, 534 and 516. The A and B operand addresses are also transferred from IPC storage to A and B counters in memory 502. A bi-stable 802 is set to indicate a special instruction mode is on. The execution of the P1 instruction is initiated by addressing ROM 702 by the OP code, and during the operation the A and B addresses are transferred from memory 502 to be added in 510 with the base address in register 516. A memory protection check is performed by comparison at 530 between the key code in register 534 and lock codes, previously loaded into store 504 and corresponding to the programme of processor P1, which are addressed by the results from adder 510. A BST instruction detects the SIM state of bi-stable 802 (highest priority in logic 722) to initiate a microinstruction sequence, starting from a branch address registered in logic 720, to restore P2 to its previous status and provide a response to P1. The response received in P1 conditions logic 236, Fig. 2, to read out the next microinstruction which forces a starting address into register 144 to initiate an instruction fetch from main memory, return of the master programme to its previous state and selection of the next active programme by control 400. Processor P1 may also be arranged to execute instructions supplied to it by processor P2.