Patent GB-1269396-A (GB)
Title: Data processing apparatus
IPC: G05D1/00
Filed: 1969-05-20
Abstract: 1,269,396. Logic circuitry. INTERNATIONAL BUSINESS MACHINES CORP. 20 May, 1969 [3 Sept., 1968], No. 25659/69. Heading G4H. Data processing apparatus includes a plurality of active logic modules and at least one spare logic module, each module being capable of performing the same function and being responsive to a majority logic voting means, first means for detecting and temporarily correcting the failure of one of the active logic modules, and second means for temporarily removing the failed logic module from the system and for substituting a spare logic module therefor. Three multi-bit input data busses, carrying identical data, each go to each of n voters. Each voter uses majority logic to provide the majority value from the three values for each bit. Each voter feeds a respective one of n identical logic modules, the multi-bit outputs from three of which are passed by reconfiguration networks to respective ones of three output busses. Three state registers control the reconfiguration networks to select which logic modules are to feed the three output busses respectively, the first, second and third logic modules feeding the first, second and third output busses initially. The output busses are compared in pairs by discriminators to detect inequality and control failure detection circuitry to indicate which output buss is receiving faulty data. (If more than one is, only one is indicated, according to a priority order, and the fact that a fault will remain when the first fault is corrected as below, will cause one or more further operations as below to correct the remaining fault or faults.) According to which output buss is receiving faulty data, the corresponding state register is sampled to indicate which logic module is connected to it and therefore faulty. A stage of a mask register is set to indicate which module is faulty visually to an operator. Each fault signal from any of the discriminators increments a binary TEMP counter and the count of the latter is used to update the appropriate state register to deselect the faulty module and select the next free module instead. However, when any state register has reached the last of the series of modules the function of the TEMP counter is taken over by a binary LAST counter which is incremented, from now on, by each fault signal. The decoded outputs of the LAST counter are used for sampling respective stages of the mask register. If a sampled stage is off, indicating that the respective logic module is not faulty and therefore still in use, the LAST counter is incremented again. This continues until a logic module not in use is reached, the appropriate state register then being set according to the count in the LAST counter to replace the module which caused the fault signal with the module just reached. If the fault in the latter module which caused its original removal from service was transient, its reuse will of course be acceptable. A modification has only four logic modules i.e. only one spare, permitting each state register to have only one stage and the counters &c. to be dispensed with.