Patent GB-1185231-A (GB)
Title: Improvements in and relating to Monolithic Semiconductor Structures
IPC: G11C11/411
Filed: 1967-03-31
Abstract: 1,185,231. Monolithic integrated circuits. INTERNATIONAL BUSINESS MACHINES CORP. 31 March, 1967 [31 March, 1966 (2)], No. 10555/67. Heading H1K. A monolithic integrated semi-conductor structure comprises an array of interconnected memory cells each cell being a mirror image of cells adjacent thereto, and selected cells being interconnected by an underpass semi-conductor. Fig. 6 shows a basic cell (see Specification 1,065,702) comprising two transistors T and two resistors R forming a direct coupled storage unit; two " di-istors " D (transistor plus diode) provide read-write functions. Non- destructive read out is performed by coincident excitation of X-Y lines connected to common transistor T<SP>1</SP> causing current to flow through the diode of the di-istor with the highest base potential, sensing being effected from the diode line BOS. Write-in is effected by multicoincidence of X-Y excitation and a voltage decrease of the respective bit line (B1 or BOS) which forces one di-istor into saturation, the base current then being supplied by stored carriers in the trigger transistor and then via resistor R to switch the trigger circuit. Fig. 2A shows the basic cell in integrated circuit form comprising the two di-istors D (A being the diode), two transistors T, common transistor T<SP>1</SP> and resistors R. Fig. 2 shows a 4 x 4 array comprising 16 basic cells 1-16 as shown in Figs. 6 and 2A with 4 X-lands and 4 Y-lands for connections together with voltage, ground, B1 and BOS terminals. Each cell is constructed as a mirror image of its horizontally, vertically and diagonally adjacent cells i.e. cell 1 has cell 2 (horizontal), cell 5 (vertical) and cell 6 (diagonal) as its mirror images, which facilitates interconnections. Detailed description for constructing the whole arrangement is given; Fig. 1D (step 8) shows the completed di-istor structure comprising diode 32D, 18D and emitter 46D, base 41D and collector 18D. Fig. IT (step 7) shows a completed transistor structure comprising emitter 40T, base 42T and collector 38T. Fig. 1R (step 7) shows a completed resistor comprising P-region 30R with terminals 34R, 36R. Interconnecting zones are also provided as shown in Fig. 1C, step 10, in which P + zone 39C connects terminals 32C and 34C while other connections 44C cross above the oxide layer 30C; isolation by reverse-biased junctions is provided by biased N-type zone 18C. As described, photo-resist, etching, diffusion and deposition techniques are applied to a P- type silicon body to provide these devices; the main steps comprise diffusion utilizing arsenic doped silicon powder or etching depressions and epitaxial deposition to form N+ regions, then epitaxial growth of N-type regions, diffusion of boron to form P-type regions (e.g. to form isolation and underpass connecting regions), diffusion to form P-type resistor, base regions and P-type diode regions, diffusion utilizing POCl 3  to form N-type emitter regions and N+ connection regions and then a final oxidation and emitter diffusion drive in process. After this carrier lifetime killers such as gold or platinum are diffused in and the body annealed to increase current gain; alternatively (Fig. 3G, not shown) the killer impurities may be diffused in a non-oxidizing atmosphere before the emitter diffusion and the oxidation step is omitted. Aluminium is then deposited and selectively removed to form the conducting pattern; quartz is sputtered on, selected areas sputter cleaned and chromium, copper and gold deposited through metal masks. Lead-tin is then evaporated on and heated to form conducting pads. The wafer is diced into chips and each chip soldered to printed land portions on a ceramic substrate with glass dams between the contacts (Figs. 18, 18A, not shown).