Patent GB-830448-A (GB)
Title: Improvements in or relating to printing telegraph signal transmission systems
IPC: H04L5/24
Filed: 1956-12-03
Abstract: 830,448. Code telegraphy. COLLINS RADIO CO. Dec. 3, 1956 [Feb. 28, 1956], No. 36909/56. Class 40 (3). In an arrangement for receiving a non- synchronous, e.g. start-stop, code of mark-space elements from a teleprinter and transmitting the signals in a synchronous code, in which the received information elements are passed to a single storage level or group comprising a number of flip-flops individually switched to the conductive states representative of the mark or space condition of each code element, and in which a plurality of sequential voltage pulses controlling the synchronous transmission are applied individually to the storage flip-flops which in response to their conductive conditions successively control an output flip-flop to a corresponding conductive condition to transmit a mark or a space, an output control means operates to clamp the output flip-flop in the mark condition for the period of a complete synchronous output code character at such times as the start of a received input character arrives after the time at which a synchronous output character is due to start. The start-stop signals from the teleprinter are applied over conductor 200, Fig. 1, to a circuit providing the actual and reversed impulses over conductors 204, 205 to read-in gates 50 under control of pulses from a distributer timing ring 40 operated by pulses from an oscillator 30 normally quenched by an output from the sixth flip-flop of a distributer ring 40 in its rest position. If a start pulse is genuine and lasts more than 11 msecs., a pulse is passed to the sixth flip-flop which is changed over to remove the quench of the oscillator 30 and change over the first of five flops sequentially operated to provide pulses so that marks or spaces on conductors 204, 205 are passed via gates 50 to storage flip-flops 70. Clock pulses of a frequency slightly greater than that of the oscillator 30 are fed to read-out gates 80 to pass the impulses to an output flip-flop 105. At times the synchronous transmitter will be in advance of the start-stop input to such an extent that a service signal is transmitted to allow time for a signal to be applied to the storage flip-flops 70. The start pulse and a predetermined clock pulse are passed to a discriminating circuit 100 which operates so that if a start pulse has not been received at the time of occurrence of the selected clock pulse the transmission of code information pulses is inhibited for a cycle of the synchronous transmission, during which a continuous marking signal is sent. In the diagrammatic representation of the operation of the system, Figs. 2, 3 and 4, the input at 200 is squared in amplifier 11 and inverted over conductor 201. The positive-going start element on conductor 201 is differentiated at 21 and passed through gate 23 opened by cathode follower 22 when the flip-flop 46 is in the rest condition. The delay circuit 24 produces a positive pulse of 11 msecs. duration and the negative start pulse is applied over conductor 106 to a gate 26. If the spacing element is present on conductor 106 when the positive pulse from circuit 24 is reverted to negative at the end of 11 msecs. the gate 26 is opened and a pulse passes over conductor 208 to change over the sixth flip-flop 46 which receives the quenching control of the oscillator 31, operates circuit 22 to close gate 23, and passes a negative pulse over conductor 209 to change over the first flip-flop 41 of the distributer ring. The oscillator 31 operates at 46 c.p.s., and at the end of a complete oscillation, i.e. 22 msecs., produces a pulse changing over flip-flop 41 which now produces negative pulses over conductor 210, and successive pulses at 22 msecs. change over the flip-flops 42 ... 45 in succession. The pulses from the points 1 ... 5 after differentiation pass via conductors 310 to pairs of gates (51, 52), (53, 54) ... (59, 60) allocated to the marks and spaces of the five information elements. The storage flip-flops 71 ... 75 are operated according to the marks and spaces of the incoming signal to apply pulses to the mark gates 81, 83 ... 89 or the space gates 82, 84 ... 90 respectively. The outputs of the gates M1 ... M5 or S1 ... S5 are passed by the trailing edges of pulses #, 1 ... 4 of an output clock train in conjunction with the gates 91, 92 to an output flip-flop 110. The cycle of synchronous transmission is started by the trailing edge of clock pulse 6 which switches the mark-hold flip-flop 105 and produces a pulse via cathode follower 107 to remove the clamp of flip-flop 110 in the mark condition. At the same time a pulse from flip-flop 105 is differentiated and passes through gate 93 to trigger the output flip-flop 110 to space for the start element. The trailing edge of the # clock pulse passes through gate 81 or gate 82 if the first element is mark or space respectively, and via gate 92 or gate 91 to the output flip-flop. The clock pulses 1, 2, 3, 4 pass the 2nd, 3rd, 4th and 5th impulses from the storage flip-flops 72 ... 75 via gates 83 ... 89 to 84 ... 90 to the mark gate 92 or space gate 91 to control the output flip-flop 110. Clock pulse 5 through differentiator 109 switches the mark-hold flipflop 105 so that the output flip-flop 110 is changed over to mark for the stop element. At the start of a synchronous transmission cycle, the blank recognition flip-flop 101 is in a condition which shuts gate 104. The ring-start pulse over conductor 208 switches flip-flop 101 to the condition to open the gate 104 and if this occurs before the end of clock pulse 6 its trailing end operates the circuit 105 to remove the markclamping condition from flip-flop 110 which is able to respond to the elements stored in triggers 71 ... 75. Also a pulse from circuit 105 is applied via circuits 102, 103 to switch circuit 101 to close the gate 104 until the re-operation of circuit 101 by the next ring-start pulse. If the gate 104 is opened by the operation of the circuit 101 by the ring-start pulse after the end of clock pulse 6, the circuit 105 is not switched so that the output circuit 110 is clamped to the marking condition for a complete cycle. Further, the circuit 101 is not returned to the condition to close gate 104 so that the next clock pulse 6 passes through this gate to change over the mark-hold flip-flop 105 which removes the clamping of circuit 110 in the mark condition, and provides a pulse to switch over circuit 101 to close gate 104 until the next ring-start pulse is received over conductor 208. The removal of the clamping condition of circuit 110 allows the signal which was stored in flip-flops 71 ... 75 whilst the synchronous circuit was transmitting the all-mark signal to be transmitted in the following synchronous cycle.