Patent GB-1364775-A (GB)
Title: Speech synthesisers
Inventor: DECHAUX C
IPC: G10L19/02
Filed: 1972-03-24
Abstract: 1364775 Speech synthesis THOMSON-CSF 24 March 1972 [26 March 1971] 13994/72 Heading H4R A speech synthesizer comprises a number of variable frequency generators and an equal number of amplitude control devices respectively associated therewith, which are controlled by a main information relating to a language element in order to reconstitute main frequency components of the language element which are then summed by an adding circuit, the synthesizer being characterized in that it further comprises a rephasing device for rephasing each of said reconstituted main components simultaneously, the rephasing being controlled by an auxiliary frequency, and occurring at the auxiliary frequency at least when said auxiliary frequency corresponds to a pitch frequency associated with a voiced language element. Preferably the rephasing operation takes place whether or not the auxiliary frequency corresponds to a pitch frequency. The Figure shows the arrangement for reconstituting speech using three main frequency components and an auxiliary frequency, the main frequency components, their amplitudes and the auxiliary frequency being supplied from an information source 1, e.g. the final stage of a receiver, in parallel binary signal form, the signals being maintained at the output of the source 1 for a period T (the analysis period). The auxiliary frequency may be derived by peak detecting the speech which is now required to be reconstituted. When the speech is voiced the auxiliary frequency is therefore fairly constant and when the speech is unvoiced, varies widely. The production of the auxiliary frequency and the derivation of the main frequency components may be achieved by known means which are not described. The three main frequency components F 1 , F 2 , F 3  are reconstituted from binary form using converters 31-33, dividers 41-43 and signal generators 51-53 respectively. Taking the component F 1  as an example the binary number supplied to code converter 31 and representing F 1  is converted into a number N 1  = F 0 /2qF 1  which is supplied to a divider 41 driven by a clock frequency F 0  where q is an integer, e.g. 10 and F 0  is a frequency above the speech band. The divider 41 supplies pulses of frequency 2qF 1  to the frequency control input of a signal generator 51 of the shift-register and resistance network type which produces a step waveform whose envelope forms portions of sinusoidal waveforms having a frequency F 1 , such signal generators being known. The two other main frequency components and the auxiliary frequency are likewise reconstituted. The shift registers of the signal generators 51-53 associated with the three main components have a resetting input 71-73 which is connected to a NOR-gate 35 having its inputs connected to the first and last stages of the shift register associated with the auxiliary frequency signal generator 50. The result is that the shift registers of generators 51-53 are reset to contain all zeros whenever the register of generator 50 shows all zeros, i.e. the main frequency components are rephased whenever the auxiliary frequency passes through a minimum, the phase to which the main components are adjusted corresponding to +270 degrees of their respective sinusoidal signals. The three main components are then attenuated in respective attentuators 81-83 controlled by the information source 1 to give the correct frequency-amplitude spectrum and the components are then summed by adder 55. The summed signal is then amplitude modulated at the auxiliary frequency and is supplied to a transducer 85 via a low pass filter for smoothing out the steps of the step waveform produced. The modulation depth of the modulator is adjusted so that the modulated signal becomes zero at the same time as the modulating signal. To further improve the reconstitution of voiced sounds the modulating signal (auxiliary frequency) may be a periodic signal of periodicity # = 1/f, a cycle of which is formed by two sinusoidal "half cycles" of respective durations #/4 for the rise from zero to maximum and 30/4 for the descent from maximum to zero (th e signal having a D.C. level such that the minimum signal level is zero). French Specification 2,044,290 is referred to.