Patent GB-771301-A (GB)
Title: Improvements in or relating to electric telegraph systems
Inventor: WRIGHT ESMOND PHILIP GOODWIN
IPC: H03M13/51
Filed: 1953-12-10
Abstract: 771,301. Code telegraphy. STANDARD TELEPHONES & CABLES, Ltd. Dec. 10, 1953, No. 34415/53. Addition to 710,258. Class 40 (3). In the parent Specification a telegraph system using combinations of two signalling conditions only (mark and space) comprises at the transmitting station means for deriving from a plurality of signal combinations, a plurality of check elements, the kind (mark or space) of which expresses the region between the marks and spaces contained in a set of elements in said signal combinations, which set is different for each check element, and at the receiving station means for automatically determining the relations between the marks and spaces of the received combinations corresponding to those of the transmitted combinations from which the respective check elements were derived and for automatically correcting an element of the received combinations in accordance with the discrepancy between the relations so determined and the received check elements. According to the present invention, the check elements derived from a plurality of signal combinations are divided between those combinations and each signal combination transmitted comprises elements equal in number to and dependent upon the significant elements of a combination together with the check elements allocated thereto by said division. Transmitting-arrangements. The transmission is controlled by a time-scale circuit 11C operated on closure of switch 1K by pulses - P at 5000 kc/sec., running continuously and a timing circuit 12C which measures 139.8 m.s. and stops until it is returned to zero or other desired point in its cycle. The tube SP of the two-position switch 11F is normally conducting and the start (spacing) pulse over conductor 1S opens gate 113G so that tube ST fires and provides an impulse 11fST for gate 112G so that counter 12C is stepped by the pulses - P. Normally a two-position counter 13C is in the position 1 and spacing pulses received over 1S at instants 30, 50 ... 110 m.s. after the commencement of the start pulse are applied to element 5 of the storage register 11R, the pulses being stepped forward at times 40... 100 m.s. by gate 115G. At 139 m.s. the counter 13C is changed to position 2 and the tube SP fired over gate 125G. A pulse 11 ft., generated whenever the switch 11F changes over, restores the counter 12C to zero. On the occurrence of the start impulse of the second code combination ST is again fired, counter 12C stepped and the spacing impulses received over IS applied over gate 119G to element 5 of register 12R on which the pattern is set up by the stepping pulse applied over gate 118G. A pulse is applied to gate 124G at 8 m.s. so that if the input signal has changed from space to mark, i.e. a false start, the gate opens and tube SP of the switch 11F is fired so that an inpulse 11 ft. restores the counter circuit 12C to zero. A six-position switch 31F is normally in position 31FI and a gate 316G is opened at zero in the cycle of 11C to fire the mark tube M of a transmitting relay 32F which is returned to S at 19.8 m.s. and again to M at 20 m.s., the operation being repeated at 39.8, 40 m.s. and the effect being to transmit, in the absence of signals, mark from 0 to 99.8 m.s. and space until 144.8 m.s. When the second of a pair of combinations is being received, at 9 m.s. the gate 311 G is opened so that the switch is moved to position 31F2 and gate 316G is opened to control 32F to send mark until 99.8 m.s., followed by space until 144.8 m.s. At 144 m.s. in the cycle of 11C, gate 312G is opened to step switch 31F to position 3 and over gate 326G the condition of the element 11RI is read, a space opening gate 326G so that gate 316G is opened at the appropriate time 0, 20 ... 80 m.s., and the pattern on 11R1 is stepped by pulses applied at 10, 30 ... 70 m.s., in the cycle of 11C. At time 80 m.s. in the cycle of 11C the switch 31F is moved to position 4 and over gates 319G, 320G at times 100, 120 m.s. in the cycle of 11C the condition of counters 21C0 22C0, Fig. 2, which record the first two check elements are passed to the transmitting relay 32F, an impulse being passed if a counter is in the zero position which represents an even number of spaces among the elements examined. At time 144 m.s. in the same cycle of 11C the switch 31F is moved to position 5 and over gate 321G the condition of element 12R1 is successively examined at 0, 20 ... in the cycle of 11C, the pattern being stepped over register 12R by pulses applied over 121G at 10, 30, 50, 70 m.s. in the cycle of 11C. At 80 m.s. gate 315G is opened to bring switch 31F to position 6 in which the condition of counters 23C0, 24C0 is examined at 100, 120 m.s. to add the two check elements to the second code combination. At 124 m.s. in this cycle gate 325G is opened to return the switch 31F to the position 1. The check elements are derived by counting the number of spaces among prescribed elements as set up on the elements 11R1 ... 11R5, 12R1 ... 12R5, as indicated by Fig. 2 (not shown), an even number of spaces returning individual counters 21C ... 24C to the zero positions, 21C0 ... 24CO, and controlling the relay 32F to send a mark, and an odd number of spaces on a counter being transmitted as a space. Receiving-arrangements. A continuouslyrunning time scale 61C is set into operation by a pulse SYNC produced in response to specified signal from the transmitter as described in Specification 771,302. The incoming space signals on the conductor 6S are applied to element 7 of a register 61R at times 10, 30 ... 130 m.s., the register being stepped forward at 2, 22, 42 ... 132 m.s. so that the seven-unit signal is registered on 61R. At 141 m.s. counter 62C is driven to position 2 and if a space is received at any of the times 10... 90 m.s. in the cycle of 61C, 61F is driven to position 2 and at 142 m.s. the counter 62C is driven to position 3. Over gate 607G spacing pulses over conductor 6S at 10, 30 ... 90 m.s. are passed to element 5 of the register 62R and stepped forward at 2, 22 ... 82 m.s. so that the second code combination is registered as a pattern on 62R. The spacing impulses on the elements 61R1 ... 61R5 and 62R1...62R5 are examined by gates 609G ... 618G and applied through gates 619G ... 622G to respective counting circuits 63C ... 66C which are normally in the position 1. The elements 61R6, 61R7 of the register 61R are examined at 110, 130 m.s., and if the check derived locally is in accord with that received, the counter will be in the position 1. The second pair of check elements is not registered, but the conductor 6S is examined at 110, 130 m.s. in the cycle and in conjunction with the impulses applied to the counters 65C, 66C through gates 621G, 622G determines by the final setting of the counters whether the locally generated check element is in accord with that received. The retransmission to a teleprinter is controlled by a two-element counter 71C. Before a character is received 71C is operated to send a space which continues for 100 m.s. until the counter is returned to mark at 100.8 m.s. When a character is received switch 61F moves to position 2 and at 126 m.s. via gates 701G, 702G, 703G the counter 71C is returned to space and a spacing condition is transmitted for 119.8 m.s. until 100.8 m.s. in the next cycle when counter 71C is restored to mark. At 1, 21 ... 81 m.s. the element 61R1 is examined and spacing impulses operate gate 704G and via gates 702G, 703G to move counter 71C to send a mark, since the elements were reversed in transmission. The counter is restored to space at 0.8, 20.8 . . . 80.8 m.s. if during the period it has been stepped to the mark position by a pulse from 61R1. In a similar manner the impulses on the element 62R1 of the register 62R are examined by the gate 705G, and via gates 702G, 703G spacing impulses control the counter 71C to send the corresponding mark impulses to the teleprinter. Correction of an incorrectly received signal. If an element of a received signal is faulty, two or three of the counters 63C ... 66C will be in the position zero. For example, if the first element is faulty counters 63C, 64C will be in position 0 and at instant 1.2 m.s. gate 710G will open and via gates 706G, 703G operate to reverse 71C from the position taken in response to its setting by input 61r1 and gate 704G at time 1 m.s. in the cycle of 61C. If three of the first counters 63C ... 66C are in the zero position, then gate 721G is opened and at 131 m.s. switch 71F is moved to position 2 and gate 707G or 708G is appropriately controlled to open 703G to step the counter 71C to its opposite position. If all the counters 63C ... 66C are in the position 0, gate 723G is opened and a pulse at 132 m.s. opens gate 724G so that switch 71F is moved to position 3 and error correction cannot take place since more than one signal element must be faulty. Specifications 633,574, 692,411 and 692,457 also are referred to.