Patent GB-1269901-A (GB)
Title: Scanning and path search circuits
IPC: H04Q11/04
Filed: 1970-02-26
Abstract: 1,269,901. Automatic exchange systems. INTERNATIONAL STANDARD ELECTRIC CORP. 26 Feb., 1970 [6 March, 1969], No. 9274/70. Heading H4K. In a computer-controlled, TDM, PCM exchange in which each highway has an associated last-look typememory for recording its status and the signalling data thereon, the functions of path finding in respect of a new call and. path identification for the purpose-of breaking down a path on which conversation has ceased, are effected by logic circuitry which is distinct from the central processor. The exchange has groups of p junctions where p is the number of digits in a PCM word, fifteen groups of junctions being connected as a supergroup to a matrix of a twostage. space division switching network. Junetors which incorporate timedivision switching i.e. time slot interchange are connected as another supergroup to other matrices of the network. Each junctor incorporates the necessary memories for controlling operation of crosspoints in a column of one matrix in each stage as well as the usual space-path, time-path and intermediate speech memories of a TDM, PCM system. Each group of highways has associated therewith logic/memory for detecting the condition e.g. busy, free, synchronized or unsynchronized i.e. alarm status, and digital signals of the channels in its highways. Further details of these and related features of the exchange such as:timing, serial/parallel code conversion etc. are to be found in Specifications 1,261,599, 1,269,888 and 1,261,598. Path finding and path identification (P.F. and I.) is effected with the aid of 9 programmes: supplied by the processor and the current status in the highway groups' logic/memories and in the memories in the junctors. Each programme consists of five, 16 bit words that are stored in registers in the P.F. and I. logic. The execution of each programme involves up to four steps (corresponding to at least four exchange clock cycles), the result of the programme being transmitted to the processor: either on-demand or immediately the programme terminates. Theprogrammes comprise:- P20: Detection of new calls. The processor supplies to the P.F. and I. logic the code of the programme, the code of the supergroup to which it is to be related.and the code of those groups in. which no. action: is to be taken i.e. masking. Channels in the defined supergroup are scanned with the aid of the lastlook memories and a selection is made such that at any one-time slot only one calling channel on one highway is recorded in the P.F. and I. logic for subsequent action by the processor. If there are no. calling channels only two clock cycles are required. P24: Detection of a change of state of signal. bits. This is virtually identical to P20 buts is concerned with new calls that have been acknowledged by the processor. P21: Detection of desynchronized highways. P22: Detection of highways in which the alternate Mark Inversion rule of message signals has been infringed (Mark inversion means that if successive digits are identical then the transmitted bits corresponding thereto should be successively of opposite polarity). P23: Detection of highways in which the average phase signals are no longer available for reconstituting a message signal. In the last three programmes, the. processor supplies to the P.F. and I. logic, the code of the programme, the code of the supergroup involved, the masking code for forbidden groups, the code of a particular highway and the masking code for forbidden channels on the highway. Sufficient time is allowed to find the required trunk so as to assess whether: or not it is in a fault condition i.e. it has an alarm signal in its groups logic memory.  P16: Search for a free interstage link (or identify a busy link) at a specified time slot when each highway group has two appearances on the network. The processor supplies to the P.F. and I. logic, the programme code; the matrix switch code (this is the same as the code of the supergroup which is connected to it); the code of the required time slot tx (which is quite arbitrary since the incoming highways are each terminated in memories having a full-cycle storage capacity) to be used in connecting the calling channel via the network to a junctor ; the link-masking code; and a code distinguishing between path search and path identify. The cross-point-column memories for the first stage switches which are located in the junctors are accessed during this programme.  P17: This is the same as P16 but applies to the case where highway groups only have one appearance on the network. P18: Search for a free path between the link selected in P16 or P17 and one of the possible outgoing channels. The processor supplies the codes of:-the link selected in P16; the second stage switch Q on which the link terminates (thereby defining the group of junctors that are to be used; the relevant outgoing highway group; the first stage switch Q<SP>1</SP> to which this group is connected; the link between Q<SP>1</SP> and Q (if there is more than one link between these switches, the processor chooses one of them); the relevant outgoing highway; the mask for forbidden junctors; the mask for forbidden channels on the relevant outgoing highway; the time slot tx of P16; and the programme. The P.F. and I. logic firstly accesses the crosspoint-column memories associated with the switch Q during the time slot tx so as effectively to determine the free junctors. The logic then determines whether one of the relevant channels is free and can be connected over the link between Q<SP>1</SP> and Q to a free junctor using the cross-point-column memories associated with the switch Q<SP>1</SP> and the free/busy/alarm status stored in the logic/memory of the highway group. One of the free junctors is then selected. This search specifies the time slot ty during which the called side of the connection is to be set up. The results are communicated to the processor which then, via multisignallers of the type described in the abovementioned specifications, transfers the switching control data into the memories in the junctors.  P19: Identification of a path preparatory to breaking it down. The processor supplies the programme code, the identity of the busy link at time slot tx (discovered during a preceding P16 or P17 programme) and a mask for the forbidden junctors. The P.F. and I. logic determines whether the link is carrying conversation by accessing the logic/memory of the highway group and if it is not the logic then determines the junctor involved. With this information available, the called side of the connection is immediately identifiable by assessing the junctor's time path memory during tx. System security is achieved by duplicating at least the P.F. and I. circuits. The duplicates may be used alternately or simultaneously and in the latter case need not necessarily perform  the same programme concurrently.