Patent GB-1510148-A (GB)
Title: Digital scan converters
IPC: G01S7/298
Filed: 1975-04-17
Abstract: 1510148 Radar DEFENCE SECRETARY OF STATE FOR 11 March 1976 [17 April 1975] 15973/75 Heading H4D A scan conversion system is provided for a radar in a mobile surveillance apparatus, e.g. an aircraft or missile, involving the storage in a random access memory of the radar response signals at addresses corresponding to ground stabilized co-ordinant system i.e. independent of the aircraft motion and allowing scan to scan integration for signal to noise ratio improvement purposes. The read out of the random access memory is in a raster form and is processed to produce an aircraft stabilized display, i.e. the representation of the field of surveillance which moves with the aircraft. The response signals are digitized at 5, Fig. 4, and digital indication of the positions from which the response signals have been returned are provided in terms of coordinance XR, YR, Fig. 1, related to a ground fixed point O. To produce said position indication the position of the aircraft Xa, Ya in said co-ordinance system is made potentially available in a position register 3 and are combined in an input scan address generator 2 with the radial scan coordinance Rr sin # and Rr cos # respectively. The input scan address generator 2 feeds the coordinance XR, YR to the random access memory 8 to determine the address at which the digitized response signals should be stored. The output scan address generator produces a series of addresses making up a raster scan and is accordingly controlled by frame and line sync. pulses from the TV display unit 12. So that the TV display, Fig. 3, may be aircraft stabilized the starting point within the random access memory of the read out raster scan, i.e. point T', Fig. 2, is controlled as a function of the co-ordinance Xa, Ya, these co-ordinates being fed from the position register 3 to the generator 4. The system of Fig. 4 is shown in greater detail in Figs. 5 and 6. To produce the raster scan co-ordinates the output scan address generator 4 comprises line or OSX counter 21 fed with clock signals 20, the counter overflowing at the end of a line scan counter and the overflow being fed to a frame or OSY counter 22. Both counters are synchronized with respective line and frame sync. pulses from the TV display unit 12. The Xa and Ya co-ordinate signals from position register 3 are fed to add offset box 23 and there adds same to fixed numbers representing the desired difference between the scan starting points A' and T', Fig. 2. As shown A' and T' have the same Y co-ordinate such that the Y offset is zero whilst the X offset is N where N is the number of columns in the random access memory 8. It should be noted that in Fig. 1 both Xa and # are negative. Both counters 21 and 22 have the capacity of N, counter 21 counting up and counter 22 counting down whereby the addresses of the cells intersected by the lines T', U', V', W' are generated. The outputs of the X and Y counters 21 and 22 offset by the respective outputs of offset box 23 are fed to the random access memory 8. However the two least significant bits from the X counter are not used, the output of the generator 20 being used to control the shifting of the signals in TV register 10 instead. The input scan address generator 2, Fig. 4, comprises in Figs. 5 and 6 clock pulse generator 28, range counter 29, read only memory 30, two digital multipliers 31, 32 range scale switch unit 33, counters 34, 35, write address register 36 and delay unit 37. The range counter 29 zeroed by sync. pulses from radar 1 and counting clock pulses from generator 28 produces sampling pulses on line a defining the range increments for sampling for responses. The sampling pulses a are used to update the counter 34 and 35 and control the sampling and conversion in A to D converter 5. The radar azimuth # is converted to sin # and cos # by means of read only memory 30 and the X and Y range increment values r sin #, r cos # respectively are produced from respective multipliers 31, 32 using the outputs from the read only memory 30 and the output r from a range scale switch 33. X counter 34 or accumulator is reset to a value XA at the transmission of each radar pulse and is increased in value by r sin # each time a sampling pulse is received from counter 29 whereby the total accumulated in counter 34 is Xa+Rr Sin # or XR. A similar addition and accumulation in counter accumulator 35 produces an accumulated count of Ya + Rr Cos # or YR. The contents of the two accumulators thus form the X and Y co-ordinates of successive sample points. The contents of the X and the Y accumulators 34, 35 are read out into a write address register 36 under the control of the sample pulses via a delay 37. The two least significant bits of the X coordinate of the cell address are connected to the decoder 7, Fig. 4, while the other more significant bits of the X co-ordinate and all the Y co-ordinate bits are presented to the random access memory 8. The analogue to digital converter 5 produces each sample in a three bit form, each bit being fed in parallel to four multi input bi-stables of a twelve bistable store register 9 used to control the input and output of signals from the random access memory 8 and to enable the modifications of the signals as required in the input scanning process. Each bistable circuit has a clearing input (C), Fig. 7 (not shown) setting output (Q) to zero, resetting input (R) resetting Q to I and a data input (D) controlled by a clock input (CK) whereby Q is set or reset to match the data signal applied to (D) whenever input (CK) is energized. Random access memory 8 stores the digitized values of samples from locations associated with four cells which are consecutive in the output scan X direction, i.e. it stores 12 bits in total. Each word can thus be used to control the brightness of four consecutive spots on TV display 12. The data inputs of each bi-stable of register 9 are fed with an appropriate output from converter 5. The data out terminals of the random access memory 8 are connected to the R inputs of the bi-stable circuits. As seen from the waveforms of timing circuit 6, Fig. 8, the random access memory 8 undergoes a read in/read out cycle repeating at the sample rate of signal a. Signal b applied to select input of random access memory 8 causes, when in a one state, the random access memory to be sensitive to the output scan addresses of counters 21 and when it is in a zero state to be sensitive to the input scan addresses of write address register 36. Thus there is first a read out of one word during the output scan which is transmitted into the TV register since its write control input is simultaneously energized by the waveform D, then the register 9 is cleared by the waveform G while the analogue to digital converter 5 digitizes the next sample from the radar. The random access memory is now under the control of the input scan address and provides another read out to the store register 9. This read out is a word representing the amplitude of responses from four consecutive cells, one of these cells being required to be modified to bring it up to date in accordance with the newly digitized sample. The least significant two bits are the X co-ordinate of the input scan address controlling via gates 7A, 7B and decoder 7C which of the cells, i.e. the bi-stables in register 9, which should be so updated by having a signal applied to the clock input thereof. The energization of the respective clock inputs enables the outputs from the A to D converter 5 to update the selected bistables. The random address memory 8 is then caused to write by means of the waveform F the thus modified signals from the store of register 9 into its location at the input scan address. The signals being held in the TV register have been shifted by the waveform H such that the converter 11 has received the signals associated with the four samples represented in word read out from the output scan address. Thus the responses from four cells are read out for every one sample which is entered into the stored display information.