Patent GB-1356710-A (GB)
Title: Semiconductor resistor
IPC: H01L29/8605
Filed: 1972-02-15
Abstract: 1356710 Semi-conductor resistors INTERNATIONAL BUSINESS MACHINES CORP 15 Feb 1972 [26 March 1971] 6867/72 Heading H1S A semi-conductor resistor comprises a semiconductor body 20 of a first conductivity type, a resistor region 34, of the opposite conductivity type, formed in the surface of the body, two spaced semi-conductor contact regions 24 adjoining the resistor region, the regions being below the surface of the body. Two electrical contacts 40, situated on the surface of the body are spaced from the resistor region and are electrically connected to respective ones of the contact regions by regions 32. A first conductivity type substrate 20; e.g. of silicon, having a high quality polished surface is oxidized by placing the substrate in an oxidizing atmosphere at an elevated temperature with or without the addition of water vapour, or by pyrolitic deposition of silicon dioxide or other insulating materials, to form a layer 22. Openings in the layer are produced using photoresist and etching techniques, a suitable etchant for silicon dioxide being an ammonium fluoride buffered solution of hydrofluoric acid. After the etching process, the photoresist materials are removed and, for a P-type conducting substrate, an N<SP>+</SP> impurity, e.g. phosphorous, arsenic or antimony, is diffused through the openings to form the regions 24. These regions may be simultaneously formed with a sub collector diffusion layer for bi-polar transistors where an integrated circuit having both resistors and bipolar transistors is being made. The silicon dioxide layer is removed from the surface of the substrate and an epitaxial layer of N-material 26, is formed on the surface of the substrate. The regions 24 move into the epitaxial layer during its growth due to the elevated temperatures at which growth takes place. A silicon dioxide layer 30 with three openings is produced in a similar way as before and N+ impurities are diffused through the openings to form the regions 32 and 34. A continuous silicon dioxide layer is then formed over the resistor 34 to isolate and passivate the resistor surface. Metal vapour, e.g. aluminium, titanium, chromium, platinum or palladium, is deposited on the surface of the semi-conductor body and etched to leave the metal contacts 40, which can be ohmic. In a particular embodiment of the invention a P-type conductivity <100> orientated substrate was used. The N+ regions 24 were diffused into the substrate using a standard arsenic closed tube diffusion process. The reach through contact 32 diffusion was accomplished by an arsenic capsule diffusion. The metal contacts were produced by depositing a layer of platinum over the entire wafer, sintering to produce platinum silicide in those areas where the platinum was in contact with the silicon. The remaining pure platinum was then removed with an aqua regia etch and the whole surface of the substrate was covered with a layer of silver sandwiched between two chromium layers, photolithographic techniques being used to produce the required contact pattern. Details of anodizing times and temperatures, layer thicknesses and concentrations of impurities are also given.