Patent GB-1040741-A (GB)
Title: Fault alarm display systems
Inventor: TODMAN JOHN STANLEY
IPC: G05D1/00
Filed: 1961-12-04
Abstract: 1,040,741. Fault signallingsystems. ELLIOTT BROS. (LONDON) Ltd. Dec. 4, 1962 [Dec. 4, 1961], No. 43267/61. Heading G4H. A fault alarm display apparatus comprises means started by the occurrence of a fault for interrogating a series of circuits, each of which may indicate a fault, to cause for each faulting circuit a corresponding display to be produced on a cathode-ray tube in the form of a line trace. In the form of Fig. 1 (not shown), faults are indicated by closure of contacts AS1-ASn which apply an earth signal through delays D1-Dn to alarm gates AG1-AGn. The delays ensure that brief spurious closures of the contacts do not start the apparatus. Diodes also connect the outputs of the delays via a common line RL to a starting circuit RC. This serves to open a drive gate DG to allow pulses from a multivibrator MV to pass to a bi-stable circuit BC, the output of which passes to a counting chain SC. Outputs from each stage are connected to successive ones of gates AG1- AGn so that when the drive gate DG is open the contacts AS1-ASn are scanned successively. The outputs of the gates are applied through diodes and lead PL to a stop gate SF controlled by a pulse from bi-stable circuit BC. When the gate corresponding to a closed contact AS1-ASn is enabled, the signal in lead PL passes to circuit PC at the end of the current pulse to the bi-stable circuit. The circuit PC produces a signal to close gate DG for a period, e.g. 3 seconds, sufficient to produce a display. The scanner SC stops until the signal from PC is removed. The fault switches are identified by words which are displayed on the screen of a C.R.T. by controlling the X and Y deflections and the brightness to form letters, Fig. 3 (not shown). The control voltages are derived from resistor chains, the tappings of which are connected to selected stages of a ring counter FPG, Fig. 5 (not shown). The resistor chains are identified by the letters XFA, YFA, BFA for letter "A," XFR, YFR and BFR for letter " R " and so on, there being an assembly of circuits for each fault line. Each signal is applied through a gate XGA, YGA, BGA &c., controlled by a master gate MGA for each letter. For a particular fault the corresponding group of master gates is opened by a signal from the corresponding gate AG1-AGn on leads AL1- ALn. Pulses from the slow pulse generator SPG then pass to open the gates XGA, YGA, BGA &c. The letters of the display word are selected in turn by the slow pulse generator so that when the fault signal is present the corresponding letter signals are applied in turn to adders X1 and Y1, Fig. 6 (not shown), and a brighten up circuit BUC of the CRT. The fast pulse counter FPG makes a full count of 32 pulses between each step of slow pulse counter SPG. The successive letters of a word are displayed in a successive position, in a line on the C.R.T. screen. For this purpose a triple stair case X-voltage, Fig. 9 (not shown), and a triple level Y-voltage are provided by circuits ZSF and YSF. The letters are accordingly displayed in different areas of the C.R.T. screen. The three lines of letters may have different colours depending upon the importance of the fault indication. According to the line AL1-ALn giving a fault indication a word of not more than twelve letters is displayed in the appropriate region of the C.R.T. screen. The display lasts three seconds and is followed by the word relating to the next fault if any. In a modification, a button is provided which; when pressed, cancels the display by opening gates between the delays D1-Dn and alarm gates AG1-AGn.