Patent GB-1412463-A (GB)
Title: Digital and analogue data handling devices
IPC: H04N5/378
Filed: 1972-10-10
Abstract: 1412463 Charge storage system; analogue stores RCA CORPORATION 10 Oct 1972 [12 Oct 1971] 46624/72 Headings G4C and G4G [Also in Division H4] A plurality of charge storage stages forming a serial shift register are connected to further charge storage stages to permit parallel transfer of charge signals between the register and the further stages. As described in the system of Fig. 1 an input shift register 12 comprises, for each stage, two insulated gate field effect transistors Q 11 , Q 12 ; Q 21 , Q 22  ... of N conductivity type with nodes P 11 , P 21  ... between the transistors of a pair and nodes P 12 , P 22  between stages. The register is pulsed by a clock H1 with analogue or digital data being advanced from even numbered nodes to odd number nodes at negative transitions of the clock and from odd numbered nodes to even numbered nodes at positive transitions. Positive going transitions of a further clock H2 transfer data from register 12 into an array of parallel registers S1-S5, the register 12 being reset. As in the register 12 each subsequent transition advances the information. A third clock H3 transfers data from the last stages of the registers into and serially along an output shift register 14 which comprises pairs of transistors T 10 , T 11 ; T 20 , T 21  ... In the embodiment of Fig. 3 (not shown) in which P type transistors are used, data is transferred in parallel from an input shift register (500) to columns (C1-C4) of a memory array (504) via gating transistors (F11-F14). Each cell of the array comprises a transistor (M11- M24), the gate of which is connected to a row conductor. The junction capacitances of diodes (D11-D24) which may be photo-responsive and each of which is connected to the conduction path of an associated one of the transistors, are used to store charge. Data is read from the bottom row of the array (504) via gating transistors (F21-F24) to an output shift register 508, the first transistors (F11-F14) being cut off during read out. Figs. 5 and 6 (not shown) illustrate charge coupled devices forming analogue or digital delay lines. A positive going input signal applied to an electrode (611) creates a potential well beneath it proportional to the input signal. A positive going clock pulse from a clock applied to an electrode (612) causes electron flow from the first electrode (611) to the second electrode (612) the transfer being continued with successive applications of positive going pulses to further electrodes (613-619). The information present beneath electrodes (613, 616, 619) is transferred to further electrodes (621-623) when a positive going pulse from a clock is applied to the latter to effect series to parallel conversion, the data being then stepped along parallel paths by the successive application of clock pulses. A subsequent clock pulse applied to further electrodes (651-653) transfers the data into an output register (604) along which it is stepped by the application of further clock pulses. A D.C. bias section acts to extract the information which is amplified and produced at an output terminal (660). In the embodiment of Fig. 8 (not shown) an image sensor comprising an array (800) of photoconductive devices each in series with a resistor serves as a video coupler. A vertical scan driver (801) energizes the rows of the arrays one at a time to cause current to flow in response to incident light through the photo-responsive element to selectively lower the column potential of the array and so control storage transistors (F21-F23). Further gating transistors (F31- F34) isolate an output register (808) from the array (800). Clock pulses applied to transistors of the output register transfer charge to an output terminal (812).