Patent GB-951974-A (GB)
Title: Improvements in or relating to digital integrators
Inventor: NELSON ROY
IPC: G06F7/66
Filed: 1961-09-28
Abstract: 951,974. Digital integrators. A. V. ROE & CO. Ltd. Sept. 3, 1962 [Sept. 28, 1961] No. 34963/61. Heading G4A. The invention aims to obviate errors which occur due to inherent delays in a digital integrator and provides in a conventional integrator (Fig. 1) comprising integrand accumulator 1, 2 and remainder accumulator 12, 13, a correction circuit 14 which computes a term <SP>1</SP>/ 2 #yn #x* n-1 , where the x increment is the last-occurring non-zero increment of the variable of integration, which term is added to the remainder accumulator. An alternative embodiment is described in which to provide for delays in transmitting the integrand increment to the integrator a previous non-zero increment of x (instead of the last-occurring) is used in the correction term. Fig. 3 shows the remainder accumulator in relation to correction circuit 14. In this embodiment the correction term is entered in-the remainder accumulator before the up-dated integrand y n  + #y n . This term is generated in the integrand accumulator and appears on lines 49, 50 in true and inverse form after a delay of one digit period. In the embodiment #x n  can be only + 1, 0 or -1, so the multiplier (9, Fig. 1) reduces to a gate circuit. #x n  sets flip-flop 57 if positive, flip-flop 60 if negative (Fig. 3). With the flip-flop 57 set, circuit 54 gates the accumulated integrand to half digit delay 66 and flip-flop 68, where it forms one input to adder 13. With flip-flop 60 set, the inverse of the accumulated integrand is applied through delay 66 and flip-flop 68 to the adder. Additionally, flipflops 57 and 60 generate a fugitive one which is applied to the carry loop of the adder. Overflow of the remainder accumulator is detected by gates 94 and 95. If the sign digit is zero indicating positive remainder and there is a carry flip-flop 68 is in reset state and flip-flop 78 set. Gate 94 issues a +#z signal on line 104. The inverse conditions operate gate 94 to generate a -#z. Possibly, overflow may come from the correction circuit and lines 100, 101 transmit such overflow to the #z outputs. The correction circuit (Fig. 4) is included with remainder accumulator loop, lines 19 and 15. The contents of the loop pass through flip-flop 82 while a non-zero #x will set flip-flop 85 if positive, reset it if negative. The #y n  input is characterized by three signals on the six lines 29 to 34. It will be noted that the input on line 19 is delayed one digit period relative to the input on lines 29 to 34. Since the numbers used are binary and the basic time scale is that of the remainder accumulator, the quantity represented on lines 29 to 34 is <SP>1</SP>/ 2 #Yn. Gates 106, 107 detect a carry condition and gates 108, 109, 110 generate a carry digit which is passed through effectively an and circuit 142 to the carry loop 134. The group of gates 111 to 115 detect and generate borrows. If there is no #y input or only a + or - #y input no correction is generated and gates 116 to 118 permit the remainder to pass unmodified through the correction circuit. Sum and difference digits are formed by gates 121 to 124. Gates 125, 126 detect the condition for -#z, and gates 127, 128 for +#z. In the modification in which earlier non-zero #x's are used, these are stored in a shift register instead of the single flip-flop 85. In a second modification the correction circuit is not included in the remainder loop (Fig. 6 not shown).