Patent GB-945386-A (GB)
IPC: H04Q11/04
Abstract: 945,386. Automatic exchange systems. AUTOMATIC ELECTRIC LABORATORIES Inc. Aug. 2, 1960 [Sept. 30, 1959 (2) ; Oct. 8, 1959], No. 26766/60. Heading H4K. [Also in Division G4] Connections between terminating and connecting units are made under the control of a circulating memory store which registers the sequence state of each connection and the identity of the terminating unit involved, the store being shared by the connecting units on a time division multiplex basis. General description, Fig. 1. The exchange has 100 subscribers S11 to S00 with line circuits LC11 to LC00 interconnectible by way of link circuits LK1 to LK20 over the time division multiplex highway ML1, ML2 containing a transmission control circuit 110. Any two line circuits are connected by pulsing the calling line circuit in the same time slot as one side of a link circuit and, during the following time slot, pulsing the called line circuit and the other side of the link circuit. As there are 20 links and two time slots are devoted to a connection over each of them, there are 40 time slots in the multiplex cycle. If the links give access to a trunk highway two trunks may be associated with each link as only a single time slot is needed for the connection. The connecting gates of the time division multiplex highway are controlled by a high-speed store 150 which is a ferrite cored matrix one row of which is subjected to a read and write cycle in an associated time slot. An odd numbered row is permanently associated with the calling subscriber's side of a link circuit and the next, even numbered, row is permanently associated with the other side of the link which connects with called subscribers. Where no trunk circuits are provided, the half-write row wires DPI to DP40 are grouped in successive pairs extending to the twenty link circuits LK1 to LK20. The high-speed store 150 is served by a line number register 130 and a signal state register 1400. Ten columns TC to TG and UC to UG record a subscriber's tens and units digits, respectively, while columns BT, DT, RG, RT and ST, record requirement of busy tone, dial tone, ringing, ringing tone, or speech over the link circuit. A signalling circuit 170 applies tones over the highway and effects control of ringing over leads 134. Each row of the high-speed store has a read winding and a half-write winding and each column has a sense winding and a half-write winding. During the first portion of each time slot the associated row of the high-speed store 150 is read out and transferred over the sense windings to the line number store 130 and signal state store 1400, which comprise bi-stable circuits, and mark a tens and units lead of a line circuit and a signal source gate. During the remainder of each time slot the associated row is subjected to a half-write pulse which over the particular one of leads DPI to. DP40 pulses one of the transmission gates of its link circuit and allows the contents of stores 130, 1400, to be read back into the row either in its original state or in a revised state in face of new conditions. For each link the pulse on an odd numbered DP lead controls the calling line gate and the pulse on the next even numbered DP lead controls the called line gate. For a connection, therefore, each link uses adjacent time slots in the time division system. The store 150 is driven sequentially through the multiplex cycle by a distributer and associated clockpulse source in circuit 600. The state of line circuits, the availability of link circuits and their allotment, and the state of calls in progress, is detected and stored by control circuits 400 and the associated slow-speed store 140 which comprises a ferrite cored matrix of the same sort as the high-speed register 150 but has only 20 rows each of which is permanently associated with a link circuit LK. In the control circuits 400 a supervisory circuit 700 detects the condition of the line circuits. A circuit 800 allots an idle link to a call and marks the link busy in column S of store 140. A timing circuit 900 measures the persistence of line circuit conditions to detect dialled pulses and registers its count in columns FC, FD, FE, FF, of store 140. A sequence circuit 1000 records progress of a call to indicate dialling tens and units digits, testing a called subscriber for busy condition, ringing, and conversation and registers these states in the form of a count in columns HC, HD, HE of store 140. An auxiliary circuit 1100 is necessary to ensure that a dial pulse is detected once only and a column B of store 140 is set to mark the duration of a digit and column R is set to mark the duration of a dial pulse by this circuit. A line number advance circuit 1200 is used to cycle the line number register 130 to scan the line circuits in conjunction with an or each idle link and to transmit the numbers of wanted subscribers as these are dialled. The pulses necessary to cycle the slow speed store 140 are taken from a distributer in the circuit 600. Line circuits, link circuits, and transmission, Figs. 2 and 3. Each line circuit is gated to the highway ML and to the control circuits 400 by the coincidence of pulses on a tens lead and a units lead such as Tl and U1, shown in Fig. 2, which enable the AND gates 232, 234, 236 and 238. Gate 232, when also supplied with a short control pulse T-C which is explained shortly, sets transistor 224 conducting in line transmission gate TG1 so that capacitor 220 charges linearly over diode 221. In the link circuit, shown schematically in Fig. 3, transmission gate TG2 is enabled by the pulse DP-1  from the high-speed store 150, by a signal state pulse S-T permitting speech over the highway, and by the control pulse T-C. Gate TG2 is similar to TG1 but, when enabled, discharges a capacitor such as 220. When the capacitors in both gates TG1, TG2 reach the same potential, diode 222 conducts over the highway. As soon as current appears on the highway a transformer 362 in the control circuit 110 pulses the toggle circuit 366 to its O state to remove the control pulse T-C and close the transmission gates, thereby limiting current over the highway. Between transmission pulses, diode 221 is cut-off and capacitor 220 leaks into the audio circuit over the impedance converter 212 by way of transformer 210. Speech and audio signals produce modulation by causing the point at which potential on capacitors 220 become equal to occur earlier or later in a transmission time slot, this point normally being midway through the slot. An increase in the depth of modulation may be obtained by including a saw-tooth generator 364 in the control circuit 110 so that the potentials on capacitors 220 must overlap before diode 222 conducts. Transmission over the link circuit is by way of inductors 314, 316, 318, from gate TG2 to TG3 which is connected to the highway in the next time slot. Each time slot is 2Á sec. long of which the first 0.5Á sec. is a guard period and the remaining 1.5Á sec. is transmission. During the guard period a clamp circuit 363 in control circuit 110 earths the highway to reduce cross talk. Each subscriber's loop includes resistors 243, 244, 247 and 248 on each side of the audio by-pass capacitor 242 and with the handset off-hook AND gate 236 is enabled by lead 253 to pass a train of pulses on lead E to line supervision circuit 700. Busy condition is detected when, after a few multiplex cycles, capacitor 218 is charged to enable AND gate 234 which passes pulses on lead C to the supervision circuit 700. Ringing control and tones are supplied from the signalling circuits 170, Fig. 3, in which a tone sources 342 and 344, and interrupter 340 are provided. Interrupter leads RDA, RDB, RDC, are given potential for 2 secs. on and 4 sees. off cyclically and are distributed over subscribers to enable ringing control circuits 240 which reverse potential on the loop to operate a ringing generator at the substation and also interrupt the ringing tone source 344. Gates SG1, SG2, SG3 are controlled by the signal state register which connects tones to the highway as required and also, with pulse R-G, enables AND gate 238 in a line circuit to enable its ringing control circuit 240. While a subscriber is being rung the reversal of loop potential causes lead 253 to detect a spurious off-hook condition which is cancelled by removal of the normally enabling potential on lead 254. Pulses in multiplex and logic cycles.-As shown schematically in Fig. 6, the pulse source 600 includes a clock pulse generator 610 producing the complementary pulses CP 0.5, CP 1.5, and CP-IA, CP-IB, illustrated in Fig. 15, which have a cycle time of 2Á sec. equal to a time slot. These pulses drive a high-speed distributer 612 of 40 stages so that in each time slot a row of high-speed store 150 is read out during pulse CP 0.5 to the line number and signal state registers and is circulated back to the row while these registers control transmission over the highway in pulse CP 1.5. A multiplex cycle therefore comprises 40 time slots of 2Á sees. each. A logic cycle, or a cycle in which the control circuits 400 pursue their function relative to a link and associated line circuit, spans 17 time slots and comprises pulses P1 to P13, illustrated in Fig. 16 and produced by a seventeen stage distributer 614. At the completion of each logic cycle a 40 stage distributer 616 steps once to produce the slow-speed cycle for slow-speed store 140. The odd-numbered stages of distributer are earthed and not used while the even-numbered stages relay the pulses P1 and P12 as read and half-write pulses to the 20 rows of the slow-speed store in sequence cyclically. The information in a row is therefore read into the control circuits in P1 and circulated back in P12, the control circuits being cleared for the next logic cycle in P13. Each link circuit is associated permanently with the half-write pulse of an odd-numbered high-speed store row and the h