baber/WOPTO huggingface dataset:
Patent TW-412863-B (TW)
Title: Method to form P-type MOSFET with an elevated source/drain
Inventor: WU SHIE-LIN
IPC: H01L27/105
Filed: 1999-05-13
Granted: 2000-11-21
Abstract: A method of forming a transistor comprises: forming a gate insulating layer on a substrate; forming a first silicon layer on the gate insulating layer; forming an anti-reflective layer on the first silicon layer; defining a gate region; removing a portion of the gate insulating layer to provide a undercut space beneath the first silicon layer; forming a dielectric layer on the substrate, the sidewall of the gate region, and in the undercut space; forming a sidewall structure on the sidewall of the gate region; removing the anti-reflective layer; forming a second silicon layer on the substrate and on the first silicon layer; performing a thermal process to diffuse a first type ion and a second type ion into the substrate. The transistor structure comprises a gate structure on a substrate. The gate structure comprises a first silicon layer, a second silicon layer and a sidewall structure, in which the gate insulating layer is located between the first silicon layer and the substrate, and the second silicon layer is formed on the substrate in a region not covered by the gate structure; a source/drain region and an extended source/drain region.
Patent TW-445328-B (TW)
Title: Process for increasing bulk of foreshortened fibrous web
Inventor: RICHARDS MARK R
IPC: D21F11/00
Filed: 1999-11-17
Granted: 2001-07-11
Abstract: A process for increasing bulk of a foreshortened fibrous web comprises adding moisture to at least the web's selected portions, thereby causing the crepe in the selected portions to relax and the selected portions to expand, while retaining the crepe in the rest of the web. A preferred apparatus comprises a pair of opposite surfaces, at least one of which having expansion conduits therethrough, the web being impressed between the surfaces. A temperature differential is created between the two opposite surfaces, sufficient to drive the moisture added to the selected portions therethrough, thus relaxing crepe in the selected portions which expand into the expansion conduits, while the crepe is retained in the rest of the web impressed between the two surfaces.
Patent TW-412849-B (TW)
Title: Method for manufacturing embedded dynamic random access memory
Inventor: HUANG JENN-MING
IPC: H01L21/8242
Filed: 1999-06-14
Granted: 2000-11-21
Abstract: A method for manufacturing embedded dynamic random access memory is disclosed. It utilizes the variance of the etching selectivity of the insulating layers made by different materials and the sequence for executing dry etching and wet etching process depending on the actual requirement so as to enlarge the top opening of the plug contact window. Therefore, it is able to generate a plug with a top portion wider than the bottom portion, thereby increasing the tolerance in the subsequent process, and thus solving the formation problem of deep contact windows.
Patent TW-475166-B (TW)
Title: UISC accommodating adaptor and a method and apparatus for driving the same
Inventor: SEO YOUNG-SUN
IPC: G11B17/04
Filed: 1999-07-16
Granted: 2002-02-01
Abstract: An adaptor includes a sensor hole to be open/closed, and a method and an apparatus drive the adaptor. The adaptor includes at least one sensor hole determining the size of a disc received in an adaptor body which is received via a disc holder. The disc holder includes an elastic press extended therefrom and elastically support the disc, preventing a movement of the disc until the disc holder is inserted into the adaptor body. Further, a release is disposed on the adaptor body to release the disc from the elastic press when the disc holder is inserted into the adaptor body. A method for driving the adaptor includes determining whether the sensor hole is open; and determining the type of device inserted into a disc drive. The type of drive inserted into the disc drive is determined by the adaptor accommodating an 8-cm disc when the sensor hole is open, while a cartridge accommodates a 12-cm disc when the sensor hole is closed. An apparatus for driving the adaptor includes a sensing switch to be selectively inserted into the sensor hole of the inserted adaptor to be turned on/off and transmit the corresponding signal regarding the open/closed state of the sensor hole to a microcomputer.
Patent TW-419870-B (TW)
Title: High yield DFB laser with effective reject selection
Inventor: GRANESTRAND PER
IPC: H01S5/12
Filed: 1999-07-23
Granted: 2001-01-21
Abstract: The present invention relates to a high yield DFB laser with an effective reject selection using criteria on threshold current. The demand for high output power often will require use of lasers with asymmetric power distributions with most of the light power coming out from the front mirror. The laser according to the invention preferably has an ascleaved back mirror, an AR-coated front mirror and a 90-degree phase shift (wavelength/4) positioned at 43% of the laser length counted from the rear mirror. This type of laser gives a good SM-yield, an advantageous power asymmetry and a possibility to select good lasers using the threshold current as selection parameter.
Patent TW-561153-B (TW)
Title: Herbicidal phenoxypropionic acid N-alkyl-N-2-fluoro-phenyl amide compounds
Inventor: KIM DAE-WHANG
IPC: A01N43/76
Filed: 1999-07-23
Granted: 2003-11-11
Abstract: The present invention relates to novel herbicidal phenoxypropionic acid N-alkyl-N-2-fluorophenyl amides represented in the following formula (1), a method for preparing thereof, their use to control barnyard grass produced from rice and composition as suitable herbicides, wherein, R is methyl or ethyl group; X is hydrogen, halogen, cyano, C1-C6 alkyl, C1-C6 alkoxy, C1-C3 haloalkyl substituted with 1 to 3 of halogen atom(s), C1-C3 haloalkoxy substituted with 1 to 3 of halogen atom(s), C2-C4 alkoxyalkoxy, phenoxy, benzyloxy, C2-C6 alkenyl, C2-C6 alkinyl, C2-C6 alkenyloxy, C2-C6 alkinyloxy, or phenyl group; Y is hydrogen or fluoro; n is an integer of 1 or 2 and when n is 2, X can be in a combination of other substituents.
Patent TW-446871-B (TW)
Title: Testing system for network interface card with a wake on LAN function
Inventor: SHIE CHIAN-WEN
IPC: G06F11/30
Filed: 1999-07-29
Granted: 2001-07-21
Abstract: The invention relates to a testing system for network interface card with a wake on LAN function, in which there is primarily provided with a peripheral component interconnect (PCI) plug-in device and an industry standard architecture (ISA) plug-in device so that the ISA plug-in device is applied to control the actions of the PCI plug-in device for switching the host computer via the PCI plug-in device to simulate the power state of a network interface card (NIC) with a wake on LAN function under an economical mode of a power supply environment. The ISA plug-in device is used to further receive the reply signal of wake on LAN function of the NIC to be tested that is transmitted through the PCI plug-in device for analysis. Regardless of the old model or new model computer host, the invention can test whether the wake on LAN function of the NIC is normal.
Patent TW-417214-B (TW)
Title: Method of production of semiconductor device
Inventor: SAITO TAKASHI
IPC: H01L23/31
Filed: 1999-09-17
Granted: 2001-01-01
Abstract: A method of production of a semiconductor device having bumps on tis surface and having spaces between the bumps sealed by a resin capable of cutting a wafer accurately positioned to cutting lines giving a cutting margin on the wafer in a dicing step of the semiconductor device. On a semiconductor wafer 10 in which circuit patterns of semiconductor chips are formed in a first region and cutting lines 16 between semiconductor chips are formed extending across the first region and a second region, bumps are formed so as to be connected to the circuit patterns of the semiconductor chips, a resin coating 15 is formed on a bump forming surface of the semiconductor wafer to a predetermined thickness in the first region while sealing the spaces between the bumps and to a thickness enabling confirmation of positions of parts of the cutting lines in regions 16a containing at least the parts of the cutting lines in the second region, and the semiconductor wafer is cut along the cutting lines using as reference positions the cutting lines confirmed in the regions containing at least the parts of the cutting lines in the second region.
Patent TW-429455-B (TW)
Title: Fabricating method of self-aligned silicide
Inventor: JANG TZUNG-SHENG
IPC: H01L21/28
Filed: 1999-11-18
Granted: 2001-04-11
Abstract: This invention discloses the fabricating method of self-aligned silicide used in the fabricating process of gate structure. During the conventionally known fabricating method of self-aligned silicide, it is not easy to form fine self-aligned silicide in the region of polysilicon or silicon substrate that is not doped with the N<SP>+</SP> or P<SP>+</SP>. Therefore, ion implantation method is used to perform extra ion implantation onto wafer to compensate for the stated substrate region that is not doped with the N<SP>+</SP> or P<SP>+</SP> before forming the titanium metal layer in this invention. Self-aligned silicide with uniform thin-film and the same property fulfilling the requirements is then fabricated.
Patent TW-434748-B (TW)
Title: Method and apparatus for preventing formation of black silicon on edges of wafers
Inventor: PERNG DUNG-CHING
IPC: H01L21/306
Filed: 1999-11-26
Granted: 2001-05-16
Abstract: A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.
Patent TW-430958-B (TW)
Title: Package structure of surface mounting light emitting diode and the manufacturing method thereof
Inventor: SUNG KENT
IPC: H01L23/28
Filed: 1999-12-22
Granted: 2001-04-21
Abstract: There are provided a package structure of surface mounting light emitting diode and the manufacturing method thereof. The surface mounting light emitting diode provides a metal substrate having a plurality of pins. The plurality of pins are not connected and thus in separated status. One end of the plurality of pins has a groove preferably for weld bonding. At least one light emitting diode is electrically connected to one of the plurality of pins. The light emitting diode chip is coupled to another one of the plurality of pins by a bonding wire. A shield is covered on the upper surface of the metal substrate for protecting the light emitting diode chip and the bonding wire. Finally, the light emitting diode package structure is sliced to complete the packaging process.
Patent TW-454198-B (TW)
Title: Repair circuit of semiconductor memory device
Inventor: KU KIE-BONG
IPC: G11C29/00
Filed: 1999-12-28
Granted: 2001-09-11
Abstract: A repair circuit of a semiconductor memory device utilizes a plurality of current blocking circuits, each provided with a programmable anti-fuse, to reduce current consumption in DRAM devices, particularly during a normal operation mode. The repair circuit includes a first operation switch having an output for outputting a supply voltage in accordance with a CAS-before-RAS signal; a first fuse selector, including a first plurality of fuses connected to the output of the first operation switch, to output a sub-block select signal in accordance with the output voltage of the first operation switch and a spare column enable signal; a second operation switch having an output for outputting the supply voltage in accordance with the sub-block select signal output from the first fuse selector and an address transition detection signal for performing a pre-charge function during a normal operation mode of a DRAM device; and a second fuse selector, including a second plurality of fuses connected to the output of the second operation switch, to generate a repair column select signal in accordance with the sub-block select signal output from the first fuse selector. The current blocking circuit generate a repair value signal for controlling the operation of one or the other operation switch based on a programming status of the anti-fuse.
Patent TW-468060-B (TW)
Title: Dual lamp illumination system and projection system incorporating same
Inventor: STANTON DOUGLAS A
IPC: H04N9/31
Filed: 2000-01-13
Granted: 2001-12-11
Abstract: A dual lamp illumination system is described, in which the output beams of two lamps with collimating reflectors are directed into one another to produce a combined beam, and in which plane mirrors set at 90 degrees to one another are inserted half way into the combined beam, whereby half of the combined beam is directed out of the path of the combined beam to form a new combined beam having substantially the same etendue as the original combined beam, while the light rays in the unreflected half of the original combined beam are recycled until they strike one of the plane surfaces, and are thence reflected out into the new combined beam.
Patent TW-445592-B (TW)
Title: Design method of transistor in the fabricating process of dynamic random access memory
Inventor: LIN KUEN-JI
IPC: H01L21/8242
Filed: 2000-02-15
Granted: 2001-07-11
Abstract: The present invention discloses the method of forming transistor in the fabricating process of dynamic random access memory. This invention provides a metal oxide semiconductor structure, which can reduce P/N junction leakage current and raise the refresh time capability, and at least includes the following steps: providing a semiconductor substrate, which has at least one isolating device and the isolating device defines an adjacent active region on the semiconductor substrate; forming the first photoresist layer on semiconductor substrate and exposing the active region in the first direction; implanting the first conductive ion into semiconductor substrate to form a well region; implanting the second conductive ion into semiconductor substrate to form a field implant region; implanting the third conductive ion into semiconductor substrate to form a punchthrough implant region; removing the first photoresist layer; forming the second photoresist layer and exposing the active region in the second direction, in which the second direction is different from the first direction; implanting the fourth conductive ion to form a threshold implant region; and removing the second photoresist layer.
Patent TW-448503-B (TW)
Title: Method for dry etching
Inventor: NARITA MASAKI
IPC: C23F4/00
Filed: 2000-03-06
Granted: 2001-08-01
Abstract: This invention discloses a dry etching method that is used for the pattern of the laminated film comprising at least one thin film, which is from either titanium or titanium nitride, and a metal film, which is composed mainly of aluminum. In this dry etching method, the first etching gas comprising the gas that does not react with metal film (the mixed gas of CF4 gas, Ar gas and Cl gas) is used to etch thin film. After that, the second etching gas (the mixed gas of Cl gas and BCl3 gas), being different from the first etching gas, is used to perform dry etching process onto the metal film.
Patent TW-493982-B (TW)
Title: External fixation device for bone
Inventor: PIERSON GLEN J
IPC: A61B17/66
Filed: 2000-03-07
Granted: 2002-07-11
Abstract: The present invention is directed to a device for fixation of a bone fracture. The device comprises at least one distal pin having a mounting end for insertion on a distal side of the fracture, at least one proximal pin having a mounting end for insertion on a proximal side of the fracture, a distal member attached to the distal pins, a proximal member attached to the proximal pins and slideably connected to the distal member for reducing or distracting the bone fracture, a distraction assembly for controlling the movement between the proximal and distal members, and a removable engagement element. The distraction assembly has two modes of operation: an active configuration and an inactive configuration. In the active configuration, incremental relative sliding movement between the proximal and distal members is allowed, and, in the inactive configuration, free relative sliding movement between the proximal and distal members is allowed. The engagement element operatively engages the distraction assembly in the inactive configuration. Removal of the engagement element places the distraction assembly in the active configuration.
Patent TW-I221082-B (TW)
Title: Pesticidal compositions
Inventor: NAKAMURA SATOSHI
IPC: A01N27/00
Filed: 2000-03-17
Granted: 2004-09-21
Abstract: Pesticidal compositions containing 4-phenoxyphenyl 2-(2-pyridyloxy)propyl ether and 2-(2,6-difluorophenyl)-4-(2-ethoxy-4-tert-butyl-phenyl)-2-oxazoline as active ingredients have excellent pesticidal efficacy.
Patent TW-563276-B (TW)
Title: Low profile interconnection
Inventor: KOSMALA MICHAEL LAWRENCE
IPC: B42D15/10
Filed: 2000-04-05
Granted: 2003-11-21
Abstract: An electronic device such as an IC card (10), is provided with a plug-receiving receptacle connector (18) at its rear end which is of simple and compact design so it takes up a minimum of space and allows direct connection between the plug contacts (34) and circuitry (80) on the circuit board (12) of the electronic device. An IC card has a top cover (50) with a portion (56) of molded polymer material that forms a cavity (20) between its rear end and the rear of the circuit board upper face into which the plug can be inserted. The circuit board has traces (80) on its upper face and the molded portion of the cover forms cam walls for depressing plug contacts against the traces. The lower cover has a polymer cover portion (62) that supports the rear end of the circuit board and that forms a lead-in (86) for guiding a plug into the cavity. The plug has contacts whose free forward end portions each includes a horizontal rear section (106) and an inclined front section (108).
Patent TW-440481-B (TW)
Title: Straightener for rolled ferrous products, having horizontally openable shoulders for fast change of the rolls
Inventor: ROSSINI MARCO
IPC: B21B35/02
Filed: 2000-04-12
Granted: 2001-06-16
Abstract: The invention refers to a straightener for rolled ferrous products, of the type in which a framework (11) comprises a pair of opposed shoulders (12, 13) which support two sets of rolls, a top set (14) and a bottom set (15), which define between them a straightening path for straightening said rolled products. According to the invention, said opposed shoulders (12, 13) may be translated horizontally between a closed, operative, position of containment and support of said rolls (14, 15), and an open, non-operative, position, in which said sets of rolls (14, 15) may be removed for replacement with other sets of different rolls. Moreover provided are supporting and transporting means, which are independent of the aforesaid framework (11), for supporting said sets of rolls (14, 15) in said open, non-operative, position of the shoulders (12, 13).
Patent TW-465119-B (TW)
Title: EL display device and a method of manufacturing the same
Inventor: YAMAZAKI SHUNPEI
IPC: H05B33/26
Filed: 2000-07-07
Granted: 2001-11-21
Abstract: To provide an inexpensive EL display device of high definition. An anode, a light emitting layer, and a cathode are formed on a substrate, and selective doping using at least one selected from the group consisting of an alkali metal element, an alkaline earth metal element and a halogen element is then performed to form at least ones of electron transmitting regions and hole transmitting regions. In such a structure, only a part of the light emitting layer, where at least ones of the electron transmitting regions and the hole transmitting regions are formed, emits light when a given voltage is applied to the light emitting layer, whereby images are displayed as desired.
Patent TW-430597-B (TW)
Title: Round-shaped ratchet wrench
Inventor: SUZUKI SHOJI
IPC: B25B13/46
Filed: 2000-07-24
Granted: 2001-04-21
Abstract: This invention provides an improved round-shaped ratchet wrench allowing easy identification of the switching board being at an engaging side or a disengaging side. The wrench comprises a inner peripheral teeth provided on an annular portion formed at a tip end of body handle allowing swaying operation; a segment cam, capable of being engaged with or disengaged from the inner peripheral teeth, contained in the annular portion; a driving body having a driving salient; a spring provided on the driving body capable of urging the segment cam towards the inner peripheral teeth to engage with the inner peripheral teeth; and a cap body provided on a switching board, indicating with switching letters (R, L), which is above the driving body, and marked with an arrow on the surface.
Patent TW-538295-B (TW)
Title: Active-matrix in-plane switching mode LCD panel
Inventor: WATANABE MAKOTO
IPC: G02F1/1343
Filed: 2000-07-25
Granted: 2003-06-21
Abstract: An in-line switching mode LCD panel has three groups of common electrode lines corresponding to three colors defined by color layers in the pixels. The potentials of the groups of the common electrode lines are adjusted independently of one another so that the flicker level for the corresponding pixels assumes a minimum by compensating the difference in the feed-through voltage between the pixels.
Patent TW-465063-B (TW)
Title: Semiconductor device and fabricating method therefor
Inventor: YI SANG-DON
IPC: H01L21/60
Filed: 2000-08-01
Granted: 2001-11-21
Abstract: The present invention relates to a semiconductor device and a fabricating method therefor. According to the semiconductor device of the present invention, a phased layer of under bump metallurgy (UBM) is formed by repeatedly depositing chrome and copper layers with sputtering equipment in which chrome and copper targets are installed in singular or plural chambers. The chrome and copper layers of the phased layer are deposited in the structure of the same, thin multi-layers possible for mutual diffusion, wherein the chrome layers gradually get thinner and the copper layers gradually get thicker. As a consequence, reliability in the phased layer of the present invention is achieved with increase in the speed of depositing UBM to reduce the time and cost for all the fabricating processes of the semiconductor device.