Patent GB-1413161-A (GB)
Title: Process for manufacturing semiconductor devices
IPC: H01L21/306
Filed: 1972-10-04
Abstract: 1413161 Semiconductor devices FUJITSU Ltd 4 Oct 1972 [11 Oct 1971] 45647/72 Heading H1K A transistor (Fig. 4) is diffused into a semiconductor substrate 1 which is covered by a first insulant layer 2 of, e.g. SiO 2  and a first A1 layer 3 is deposited on layer 2 and the uncovered portion of the substrate, with thereupon a second insulant, e.g. phosphosilicate glass layer 4 in which a connection hole is etched. A1 is evaporated on the surface to form coating 6 entering the hole, and the device is dipped in warm aqueous H 3 PO 4  for electrolytic etching using a Pt cathode and layer 6 as anode to separate the A1 in the hole from the remaining coating; after which electrolytic etching of layer 6 continues while the Al deposit in the hole is only chemically etched, so that a deposit remains in the hole after disappearance of deposit 6. A third insulant layer 7 of e.g. phosphosilicate glass is vapour deposited and grooved at 8 (Fig. 5) to define a wiring pattern exposing the Al deposit after which an A1 layer is evaporated on the surface and differentially electrolytically etched as above to leave only a deposit of A1 in the groove to define the wiring pattern 9 lying flush with the surface (Fig. 6). Third, fourth or further A1 wiring patterns may be superimposed over phosphosilicate glass insulant layers and interconnected through metallic hole deposits as above. In a modification (Figs. 7, 8) after diffusion of the transistor base region 11 in a Si substrate 10 an oxidized insulant layer 12 is formed and a window 13 is etched, after which a surface layer 14 of, e.g. polycrystalline P doped Si is deposited by thermal decomposition of SiH 4 +PH 3 . Alternatively by operating at higher temperatures monocrystalline Si is deposited in the window and polycrystalline Si on layer 12. Thereafter the device is electrolytically etched in warm aqueous H 3 PO 4 +HF or CH 3 COOH + HNO 3  + HF to remove polycrystalline Si from layer 12 leaving the Si deposited in the window only slightly affected, in a process similar to the above. The substrate is then heated to drive the P dopant in the window Si into the substrate to define an emitter region after which a metal layer 15 is deposited on the surface to define a wiring pattern. The Si plug in the window is interposed between the wiring pattern and the emitter region as an intermediate conductor diffused into the Si. In a further modification (Figs. 12, 14) a N-type region 17 formed in a P-type substrate by thermal diffusion of Sb and a SiO 2  insulant layer 18 is thermally oxidized thereon and photoetched to leave portions of the layer overlying parts of the substrate which are to be isolated in a closed pattern. A N-type Si layer 19 is then epitaxially deposited to form monocrystal 20 on the substrate and polycrystal 21 on the insulant layer. Thereafter the device is electrolytically etched to remove the polycrystal and leave monocrystal islands 20 on the Si substrate which are isolated by the protruding closed SiO 2  pattern and the PN- junction between the monocrystal and the substrate. A thermally oxidized SiO 2  layer 22 is formed on each monocrystal layer flush with the surface of the remaining SiO 2  layer 18, and a semiconductor circuit element (not shown) is formed in each monocrystal island using layer 22 as mask. The closed pattern insulant layer 18 may alternatively be formed by etching over a Si 3 N 4  mask (Fig. 15, not shown). Prior to electrolytic etching impurites such as P may be diffused into N-type layer 19 at high concentration, which assists in the rapid removal of polycrystal islands 21.