Patent UA-93724-U (UA)
Title: driver of SINGLE SYMMETRIC CODE SERIES of pulses with programmable time parameters
Inventor: KOROBKOV MYKOLA HRYHOROVYCH
IPC: H03K3/78
Filed: 2014-05-19
Abstract: Drive of single symmetrical code series of pulses with programmable time parameters that are multiples of the period of continuous periodic sequence of pulses applied to the input from the output of quartz oscillator includes two reversible binary counters having input synchronization pulses, input for adjustment to the addition / subtraction mode, input of permit of synchronous parallel loading and data inputs, input of permit of count mode, input of asynchronous installation to zero state, the overflow output; first (four-input), second (three-input) and third (two-input) OR elements; two inverters; circuit of connected in series resistor and capacitor; synchronous D-flip-flop with input of asynchronous installation to zero state; the first and second two-input AND gates; first and second OR elements; the common point connected in series resistor and capacitor is connected to the data input of the first D-flip-flop, to one input of AND gates; output of first AND element is connected to the input asynchronous installation of the D-flip-flop to zero state; the clock input of D-flip-flop forms the input start pulses; the second input of second AND element is connected to the output of the second OR gate, one input of which is connected to the output of the D-flip-flop; output of the second AND gate is connected to the inputs of counter asynchronous installation to zero state; bit outputs of the second counter are connected to the inputs of the first element OR; clock inputs of the counters are connected together to form the driver input - input of continuous periodic pulse sequence from the output of external oscillator; parallel loading inputs of the first counter form the inputs of driver adjustment to set parameters of output pulses. There are included: a third reversible binary counter which has input for synchronization pulses, input for adjustment to the addition / subtraction mode, input of permit of synchronous parallel loading and data input, input of permit of count mode, the input of asynchronous installation to zero state, the overflow output; first and second two-input AND-NOT elements, wherein, the overflow output of the third counter which forms the output of the driver is connected to the input of permit of synchronous parallel loading, the second input of the second OR gate, permit input of the second counter count mode and the input of the first inverter, its output is connected to the third counter count mode permit input, to the second input of the first AND gate, and inputs of the first and second AND-NOT elements; output of the first OR element is connected to the third input of the second OR gate and the input of the second inverter, its output is connected to the first input of the third OR gate and the second input of the first AND-NOT element which output is connected to the permit input of the first counter counting mode; bit outputs of the second counter are connected to data inputs of the third counter; first counter overflow output is coupled to the second input of the second OR gate and the second input of the second AND-NOT element; output of the second OR element is connected to the loading mode permit input of the second counter; the output of the second AND-NOT element is connected to the input of loading mode permit of the first counter; the third counter clock input is connected to clock inputs of the first and second counters; input of asynchronous installation to zero state of the third counter is connected to the output of the second element AND.