Patent GB-1070423-A (GB)
Title: Improvements in or relating to variable word length data processing apparatus
IPC: G06F15/78
Filed: 1964-12-22
Abstract: 1,070,423. Data processors. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 22, 1964 [Dec. 23, 1963], No. 52004/64. Heading G4A. In a variable word length data-processing system in which n characters are read from a memory during a first cycle, if one group of n characters includes the first x (less than n) characters of an operand to be processed, the x characters may be temporarily stored and the next n characters read out during a second cycle so that n characters, comprising said x characters and the next n-x characters of the operand, are available to be fed to a " secondary channel " for processing. In the particular embodiment, the first cycle above is followed by a memory cycloduring which a group of n characters including the first y characters of a second operand is read out on to a " primary channel " if x#y, but if y>x the latter cycle is preceded by read-out of another group of n characters of the first oper- and so that there will be a first-operand character for each second-operand character available. Corresponding characters of the two operands are fed concurrently and serial by character, parallel by bit along the primary and secondary channels to the arithmetic unit. In the particular embodiment, n equals two but the pair of characters are an adjacent pair selected from ten adjacent characters read from the (core) memory together. The non-selected characters are re-written together with two characters from the arithmetic unit. Each character has 8 bits (1, 2, 4, 8, A, B, C, Wm, the last being ONE in the case of the last character of a word). Three one-character registers (X, Y, Z, Fig. 1, not shown) are provided between the memory and the secondary channel, the first being reached via the third and these two being in parallel with the second. Characters may be selected successively in either direction along the word. Error circuitry (Section 9 of Specification) signals representing primary channel error (no details), secondary channel parity error, address bus error, instruction errors (see "Comparison" and "Instruction circuits" below) and any other errors are fed to an OR gate (702, Fig. 41, not shown) to produce an ANY ERROR signal (Fig. 41, not shown) which is fed to an AND gate (722) in a check test circuit (Fig. 42, not shown) together with various of the error signals (direct) and a timing signal. In order to check the operation of the error circuitry, errors are forced into all circuits at a particular time so that if the circuitry is operating correctly the above AND circuit sets a latch. The latch is then tested to see if it has set properly, producing a CHECK SET FAULT signal if it hasn't. It is then reset and checked to see if it has reset properly; producing a CHECK RESET FAULT signal if it hasn't. Either the ANY ERROR or the CHECK SET FAULT signal will stop the computer, and this stopping or the CHECK RESET FAULT signal will effectively lock positive an OSC output of an oscillator controlling machine timing (Fig. 26, not shown).. A RAW OSC output continues to alternate. The above is the subject matter of Specification 1,070,421 which is referred to. See other sections for other error features. Basic timing and computer restart (Section 8 of Specification).-The OSC output of the machine oscillator is delayed and fed to an arrangement of AND-gates arranged as latches producing two " binary gate " signals (Fig. 27, not shown) from which a recurring sequence of four " clock pulses " are derived (Fig. 30, not shown). These are fed to a ring circuit (Figs. 31, 32; not shown) to produce timing signals for machine cycles of various different lengths. The second of the " binary gate " signals is prevented from changing in the presence of the CHECK RESET FAULT signal, and both "binary gate" signals are arranged to be positive on restarting of the computer after stopping so that the "clock pulse " first produced is always the same one. Instruction circuits (Sections 10, 13, of Specification).-The first character (OPeration portion) of an instruction has the Wm bit equal to ONE and an error signal is produced if this is not so. The other seven bits are decoded by AND gates to 1-out-of-n signals which may be grouped by OR-gates. After address characters, the instruction may end with an operation modifier character which, in a MOVE DATA instruction for example may specify which bits -of a character are. to be moved. In the Wm bit of an operation modifier character is ONE, an error signal is given. Read-out of successive characters of an instruction word is controlled by an I-ring (Figs. 66, 67, not shown) which comprises an OP " ring " latch (for the operation character) twelve further " ring " latches, and seven "ring control " latches. Once the ring is started by setting the OP latch, the "ring." latches control the "ring control" latches and the latter control the "ring" latches so that said twelve further " ring " latches are set in turn by the following combinations of "ring control" latches: the first to fifth " ring " latches are set by the seventh " ring control " latch (reset) together with the first to fifth " ring control " latches (set) respectively, then the sixth to eleventh "ring" latches are set by the seventh "ring control" latch (set) together with the first, to sixth " ring control " latches (set) respectively, then the twelfth " ring " latch is set by the combination of the sixth control latch (set) with the seventh (reset). The first, second, sixth and seventh stages of the I-ring can be skipped by causing the " ring " latches normally controlling the first "ring control" latch to control the third "ring control" latch instead, by means of AND-gates. Extra (non-I) cycles may be inserted within an I-cycle for indexing and address expansion. The I-ring is the subject matter of Specification 1,070,425 which is referred to. Serial scan (Section 11f of Specification).- Provision is made for recognizing when the two addresses in an instruction word differ by one, a situation which may be used in a MOVE DATA instruction for writing blanks successively in all the character positions of a word. The recognition is performed by modifying one address by one and comparing the addresses. If they are now equal (indicating they originally differed by one) an ADDRESS BUS ERROR signal (see "Comparison" below) is absent, allowing a serial scan latch to be set. Serial scan may also be used for I/O operations, but no details are given how. When two operand addresses differ by one (detected as above) processing of more than one character from each operand is prevented. Indexing (Section 17 of Specification).-If indexing is required, the address in memory of the required index register is obtained from the A and B bits of the tens and hundreds orders of the first address in the instruction word, the mere fact that any of these four bits is non-zero indicating that indexing is required (Figs. 81a, 81b, not shown). The four bits are used to obtain the address by gates (Figs. 82-84, not shown) which effectively use one bit to indicate which half of the decade the units order of the address lies in and converts the other three bits from pure binary to 1-out-of-n (and increments by two) treating the result as the tens order digit of the address. The other three decimal orders of the address are zero. All orders are then converted to 2-out-of-5-coded decimal form. Address modification (Section 18 of Specification).-Addresses may be modified by + 2, + 1, 0, - 1, - 2 by AND-gate matrices after conversion from 2-out-of-5-coded decimal to 1- out-of-10-coded decimal, conversion back being effected after modification (Figs. 85-93, not shown). The two operand addresses are normally modified by one and two respectively to obtain the next characters, and then one of the addresses remodified by one depending on the positions of the word boundaries, before the addresses are actually used. Comparison (Section 23 of Specification).- Addresses in a 2-out-of-5-coded decimal form on an address bus are checked in a circuit (Fig. 115, not shown) which provides for each decimal order a plurality of AND-gates each adapted to recognise a particular pair of ONE bits. The gate outputs are combined in two OR gates in such a way that if more than two of the five bits are ONE, both OR gates give outputs. If both or neither OR gates give outputs, an error signal is produced. The error signals from all orders are ORed together to give an ADDRESS BUS ERROR signal. The circuit may be used for testing the equality of two addresses by ORing corresponding bits of the two addresses together and feeding the result to the circuit. Non-equality will mean at least three ONE bits in at least one decimal order, resulting in the ADDRESS BUS ERROR signal being produced. The above is the subject matter of Specification 1,070,422 which is referred to. Modifications (Section 24 of Specification).- Registers of the type X, Y, Z (not shown, see above) may also be provided for the primary channel. Several characters could be processed in parallel.