baber/WOPTO huggingface dataset:
Patent JP-S61249271-A (JP)
Title: Grinding controller
Inventor: KAWAGUCHI KEIJI
IPC: B24B49/18
Filed: 1985-04-29
Abstract: PURPOSE:To maintain the accuracy of finishing for a long period of time in a stable manner, by calculating a dresses abrastion quantity of a dresser on the basis of dressing resistance at the time of dressing a grinding wheel, and installing a controlling device which compensates a grinding condition of the wheel with a work according to this dress abrasion quantity. CONSTITUTION:The actual dressing resistance Di detected by a dressing resistance detector 16 is collated and compared with a characteristic table stored in a storage part of a desired skip time operational circuit 22 whereby a constant K corresponding to the actual dressing resistance Di is searched. The value made up of subtracting this searched constant K from the initial skip frequency Ni set by an initial skip frequency setting circuit 21 is set down to Ni-K with which desired skip frequency No is calculated, but since the characteristic being stored in the storage part is one that the more a value of the constant K increases, the more the dressing resistance Di grows large, in proportion as the dressing resistance Di increases, the skip frequency No is decreased and compensated,so that the grinding wheel 5 is dressed by the dresser 12 at a short dressing interval, and sharpness in the wheel 5 is properly maintained for a long period of time.
Patent JP-S59218392-A (JP)
Title: Screw compressor
Inventor: MOTO MASAKI
IPC: F04C28/26
Filed: 1983-05-25
Abstract: PURPOSE:To aim at simplifying the control of volume, by providing such an arrangement that a suction port is communicated with a discharge port through shut-off valve, an intermediate port which offers an intermediate pressure between the pressures of suction and discharge ports, is communicated with the suction port through another shut-off valve, and both shut-off valves are selectively opened and closed in accordance with loads. CONSTITUTION:A discharge casing 11 is formed with an intermediate port 12 communicating between a male rotor 3 and a compression space, and a suction casing 9 is formed with an auxiliary suction port 13 opened to a suction port 6' which is communicated with an end wall suction port 6. The intermediate port 12 is communicated with the auxiliary suction port 13 through an automatic valve 14, and an auxiliary discharge port 15 opened to a discharge hole 7' which is communicated with an end wall discharge port 7 formed in the discharge casing 11, is communicated with the auxiliary suction port 13 through an automatic valve 16. When the automatic valve 16 is closed and the automatic valve 14 is opened upon partial load operation, working fluid under intermediate pressure is taken out from an end wall intermediate port 17, and is sucked into the end wall suction port 6 through the suction port 6' after passing through the intermediate port 12, the automatic valve 14 and the auxiliary suction port 13. Thereby, the discharge amount of working fluid is reduced. Accordingly, the control of volume is made possible with an extremely simple structure.
Patent JP-S60235439-A (JP)
Title: Formation of multi-layered wiring
Inventor: IWAMOTO NORIKO
IPC: H01L21/768
Filed: 1984-05-08
Abstract: PURPOSE:To provide a stable contact which can afford easy fine formation, by decomposing a metallic compound, after forming a contact hole in an interlayer insulation film, so as to form a metal projection in the contact hole with the use of light effective to decompose and separate the metallic compound. CONSTITUTION:An interlayer insulation film 3 is formed on a substrate 1 provided with a first wire 2, and then provided with a contact hole by etching with the use of the photo-lithography technique. The degree of vacuum is then increased. A metallic compound gas [e.g. Al2(CH3)6] is introduced and light is applied through a mask to deposit a metal projection 5 in the contact hole (the depositing speed of Al is 500Angstrom /min) until it is projected over the interlayer insulation film by 1,000-3,000Angstrom . A second wire 4 is then provided to cover the metal projection 5 so that the short circuit is prevented from occurring in the level difference in the wire. Accordingly, the manufacturing process can be rendered more efficient and simple, while the yield can be improved.
Patent JP-H07303333-A (JP)
Title: Method for detecting individual operation
Inventor: HORIO WATARU
IPC: H02M7/493
Filed: 1994-04-28
Abstract: PURPOSE:To improve system interruption detecting accuracy so that the individual operating state of an inverter can surely be detected by reducing the output power of the inverter when the steeply increasing state of a harmonic component does not continue for a fixed period of time and detecting the voltage drop at a tie point. CONSTITUTION:Third harmonic extracting signals from an integration circuit are sampled at regular time intervals and the average value of the sampled extracting signals is fetched as a detected value Vin (S1). Then it is judged whether or not the difference between the detected value Vin and a reference voltage value Vref is larger than a prescribed threshold el (S3). Thereafter, whether or not counting operations are carried on is judged from the counter of a time-limiting timer and, when the counting operations are carried on, the counting operations are started and the continuation of the counting operations for a fixed period of time is judged (S5, S7, and S9). From the above-mentioned operations, the individual operation of an inverter is surely detected by judging the steeply increasing state of a harmonic component resulting from a system interruption by judging the continuation of the steeply increasing state of the harmonic component for a fixed period of time T1 and suppressing the influence of noise.
Patent JP-H04323859-A (JP)
Title: Manufacture of stack type semiconductor storage device
Inventor: DOMAE SHINICHI
IPC: H01L27/10
Filed: 1991-04-23
Abstract: PURPOSE:To maintain excellent pause time characteristic by inserting a boron ion implanting step between a step of forming a storage node and a step of forming a capacity insulating film. CONSTITUTION:Before a storage node 5 is formed on an exposed surface of a semiconductor substrate 1, a p<+> type diffused layer 14 is formed on the exposed surface by boron ion implanting 13. Thus, even if a relative mask misalignment occurs between a step of forming a window 4 in a layer insulating film 3 and a step of forming the node 5, the layer 14 is etched together with a constituting material (polycrystalline silicon film) of the node 5 when an anisotropically etching is applied to form the node 5. Accordingly, even if a positive voltage is applied to a cell plate 8 and a negative voltage is applied to the substrate 1, a thick depleted layer is not formed in the substrate l. Thus, excellent pause time characteristic can be maintained.
Patent JP-S5617432-A (JP)
Title: Circuit control system
Inventor: ONODERA AKIRA
IPC: H04L69/14
Filed: 1979-07-20
Abstract: PURPOSE: To shorten the processing time of slots by synthetically judging the state of a controlled system in processing of one slot with regard to the address of a control word to be read out next and then by starting to read a new address right after slot switching.  
     CONSTITUTION: Circuit corresponding parts LT 0 WLTn are equipped for circuits L 0 WLn and circuit control memory CM stored with control data CCW that corresponds to each circuit is provided. The output of control memory CM is processed in time-division mode among circuits L 0 WLn under the control of a central controller. Namely, the address of a fixed circuit among L 0 WLn is generated by address counter LAC and address register ACR reads circuit control memory CM several times. Then, information obtained in one read is processed to determine an address for the following read and write. 
     COPYRIGHT: (C)1981,JPO&Japio
Patent JP-H07296214-A (JP)
Title: Coin supply device
Inventor: NAKAYASU MASAKANE
IPC: G07D1/00
Filed: 1994-04-28
Abstract: PURPOSE:To make a coin supply device small by designing an opening at the bottom of a hopper to be small. CONSTITUTION:A funnel shaped opening 24 is provided on the bottom of a hopper 21 containing lots of coins C. A rotor 28 having a nearly conical block member 30 at a cylinder 29 and an upper part of the cylinder 29 is turnably fitted to the opening 24 of the hopper 21. A guide port 38 leading each coin in the hopper 21 to the opening 24 which is open longitudinally with a width more than the diameter of each coin C is formed in one part around the cylinder section 29 to the rotor 28. A rotation drive means 55 is provided to drive the rotor 28. Since the coins C in the hopper 21 are led to the opening section 24 through the guide port 38 while the heap of the coins C is collapsed by the rotation of the rotor 28, the size of the opening section 24 of the hopper 21 can be decreased and the size of the device can be made small.
Patent JP-S59908-A (JP)
Title: Base plate material
Inventor: SAKAKIBARA MASAHIKO
IPC: C23C14/00
Filed: 1982-05-31
Abstract: PURPOSE:To obtain an optimum nonmagnetic material for base plate from an oxide having rock salt composition to be represented by the formula ZnxMny Ni2-x-yO2 (0<=x<=0.4, 0.4<=y<=1.0, 0.8<=x+y<=1.0). CONSTITUTION:As a nonmagnetic base material, an oxide having rock salt composition represented by the formula of ZnxMnyNi2-x-yO2 is used. Assuming that 0<=x<=0.4, 0.4<=y<=1.0 and 0.8<=x+y<=1.0, its thermal expansion coefficient alpha becomes substantially equal to the coefficient alpha of a metal magnetic film of Fe-Ni family or Fe-Al-Si family. By using this material, it is made possible to process a metal magnetic film by desired heat treatment for improving its magnetic characteristic after it is formed without the possibility of peeling-off of film. Consequently, it is enabled to produce electronic parts elements having films which are excellent in magnetic characteristics.
Patent JP-S58209274-A (JP)
Title: Infrared image pickup device
Inventor: YAMASHITA JIYUNICHIROU
IPC: H04N5/33
Filed: 1982-05-31
Abstract: PURPOSE:To make an AD converter in compeneating circuit unnecessary, by performing a compensation by using a linear function, which uses the average level of one frame of the output of a solid-state image pickup elements for infrared rays as a variable, as an offset component. CONSTITUTION:An output Xi4 of a solid image pickup element for infrared rays (IRCCD) is supplied to a one frame average circuit 16, whose output Xi is used as the reference voltage of a DA converter 14(a). A Bi memory 19 and Ai memory 20 store correction coefficients Bi and Ai and output them according to a synchronization signal 8. The output of the memories 19 and 20 is converted to an analog signal by the DA converters 14(a) and 14(b) and supplied to an analog adding and subtracting circuit 18 together with the IRCCD output Xi and outputted as a value of Yi as shown in an expression. As the result, arithmetic processing for correction is carried out in alalog so that an AD converter is made to be unnecessary.
Patent JP-H01264669-A (JP)
Title: Automatic gain controlling circuit
Inventor: KODA KUNIO
IPC: G11B20/10
Filed: 1988-04-15
Abstract: PURPOSE:To obtain a satisfactory response characteristic with a simple circuit constitution by inputting a write signal to be attenuated to an automatic gain controlling circuit at the time of a write condition, and decreasing the gain difference of the automatic gain controlling circuit between a time switched to a read condition and the time of the write condition. CONSTITUTION:In the read condition, the title circuit is operated in the same way as the conventional circuit. At the time of the write condition, the write signal is inputted to an attenuator 2, and the write signal to be amplitude- lowered by the attenuator 2 is inputted to one side of inputs of an automatic gain controlling circuit 1. An automatic gain controlling amplifier 1 has the gain balanced with the signal. Next, when the changeover from the write condition to the read condition is executed, a read signal inputted to the amplifier 1 is made into a large value in the read condition. However, since the write signal is inputted to the amplifier 1 by being attenuated into a level close to the read signal in the read condition by means of the attenuator 2 in the write condition just before, the gain of the amplifier 1 hardly needs to be changed, and consequently, a response time is sufficient to be very short.
Patent JP-S5231913-A (JP)
Title: Fluidized bed furnace of wire rod heat treatment
Inventor: FUJIMOTO YOSHITAKA
IPC: C21D9/567
Filed: 1975-07-30
Abstract: PURPOSE:Fluidized bed furnace for patenting of wire rod etc., having a mechanism of regulating effective fluidized layer thickness.
Patent JP-H04305371-A (JP)
Title: Pulse tig welding method
Inventor: MUNEYUKI TADASHI
IPC: B23K9/12
Filed: 1991-03-29
Abstract: PURPOSE:To suppress the occurrence of weld defects and to obtain a satisfactory welding state by once decreasing the wire feed rate and then, increasing it to the peak speed when the wire feed rate is changed over from the base speed to the peak speed. CONSTITUTION:Before a peak electric current is supplied to a nonconsumable electrode, the wire feed speed is once decreased to less than the base speed and afterward, the wire feed rate is increased up to the peak speed. Accordingly, the wire feed rate at the time of applying the peak current is regulated to the optimum speed corresponding to the peak current and the satisfactory welding state can be obtained.
Patent JP-H06310458-A (JP)
Title: Semiconductor element and its manufacture
Inventor: MATSUZAKI KAZUO
IPC: H01L21/28
Filed: 1993-04-21
Abstract: PURPOSE:To form a stable low-resistance contact regardless of the types of a base diffused layer without increasing the number of processes by metallizing a polycrystalline silicon plug which fills a contact hole so as to flatten it by permitting the plug to contain phosphorus and aluminum. CONSTITUTION:On an n-type silicon substrate 1, the p+ source/drain area 41, a p-well 42 and an n+ source/drain area 43 are previously formed, and a contact hole 3 is formed on an SiO2 film 2 which includes gate electrode 7 composed of polycrystalline silicon. Then, SiH4 is permitted to flow, a phosphorus doped polycrystalline silicon film 80 is formed by lowpressure CVD and the surface is flattened. The film 80 is etched back so as to leave the polycrystalline silicon plug 8 only in the contact hole 3 and the whole surface is flattened. Then, Al wiring 5 is formed by Al deposition and a photo process. The series of processes is completed by annealing the Al in a N2 atmosphere for 30 minutes.
Patent JP-S60236534-A (JP)
Title: Two-wire type mutual communication equipment
Inventor: MORI KEIJIROU
IPC: H04L5/16
Filed: 1984-05-10
Abstract: PURPOSE:To attain the high efficiency and the cost reduction of a signal line by adding a signal switch part for switch between the transmission and reception signals to an input/output port and using a single signal line for transmission of reciprocating signals. CONSTITUTION:When data are transmitted from a center main controller 1, a signal of +10V is sent to a signal switch part 8 from a transmission request terminal of an input/output port 2 through a signal control line 11. While a data signal of + or -10V is sent from a transmission data line 9, and the signals between 0V and -10V pass through an FET28. While the signals between 0V and +10V pass through an FET30. These two types of signals are synthesized and sent to a signal line 17. In this case, both FET29 and 31 are cut off and not connected to a reception data line 10. The signals sent from the line 17 pass through the FET29 in a range of 0V--10V and through the FET31 in a range of 0V- +10V via a signal switch part 12. These two types of signals are synthesized and transmitted to a terminal controller 3 through a reception data signal line 14. In this case, both FET28 and 30 are cut off and not connected to a transmission data line 13.
Patent JP-S5217095-A (JP)
Title: Coin selects system
Inventor: ABE MASAHIRO
IPC: G07D3/02
Filed: 1975-07-31
Abstract: PURPOSE: To make coins pass on selection holes for the detection of the outer dimensions while pressing the coins by the transmission belt, thereby ensuring the selection in the selection holes. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-S58209387-A (JP)
Inventor: ASAI YOSHIMI
IPC: D05B3/24
Filed: 1982-06-01
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H07275093-A (JP)
Title: Door device of show case
Inventor: KUBOTA TOSHIAKI
IPC: F25D23/02
Filed: 1994-04-06
Abstract: PURPOSE:To provide a door device of a show case capable of remarkably improving the opening and closing operability of a sliding door type door for opening and closing an opening. CONSTITUTION:An auxiliary rail 71 is provided on the lower edge of an opening 64 of a show case 1. A sliding door type resin made door 73 supported slidably by the auxiliary rail 71 to open and close the opening 64 is provided. A fluororesin is applied to or coated on the surface of the auxiliary rail 71.
Patent JP-H04325001-A (JP)
Title: Rotary tiller
Inventor: ISHIDA ARINOBU
IPC: A01B33/12
Filed: 1991-04-24
Abstract: PURPOSE:To obtain a rotary tiller, capable of preventing tilled soil from sticking to the inner surface of a cover and simplifying the structure though operation is not disturbed even in installing other working devices. CONSTITUTION:An auxiliary cover 9 composed of a soft rubber material is attached to the inner surface of a rotary case 7 in a cantilever form and the aforementioned auxiliary cover 9 is placed and supported on plural supporting arms 10 for receiving the auxiliary cover 9 in a posture along the tip locus of rotary tines 5 so as to enable evacuation on the supporting arms 10.
Patent JP-S5218876-A (JP)
Title: Method for preparing yeast cells
Inventor: TOMITA KOUICHI
IPC: C12N1/16
Filed: 1975-07-31
Abstract: PURPOSE: A method for collecting yeast cells from a culture fluid by culturing a yeast, Torulopsis S-189 in a medium containing methanol as a chief carbon source. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-2000282568-A (JP)
Title: Method for obtaining proof strength of beam-column connection section in steel-pipe column
Inventor: ITO HITOSHI
IPC: E04B1/24
Filed: 1999-03-31
Abstract: PROBLEM TO BE SOLVED: To provide a designing method of a beam-column connection section in a steel-pipe column presenting a simple and general-purpose method in which the proof strength of the beam-column connection section in the steel-pipe column is obtained, keeping the fixed accuracy of the proof strength of the beam- column connection section of the steel-pipe column and using a method in which such proof strength is acquired. SOLUTION: Each component is calculated by strength evaluation formula by an analytical technique, assuming disintegration into the two flow components of a flow to a column of beam-flange axial force, and the sum of the components is evaluated as the proof strength of the connection section. The flow (front shear force) P1 of the component 1 mainly represents the flow of force that a steel-pipe wall surface near a section on which a beam is mounted is bent and deflected and transmitted to the steel-pipe axial direction, and the flow (ring proof-strength) P2 of the components 2 represents the flow of force transmitted in the ring circumferential direction by the bending of a ring and a steel-pipe plate near to the ring.
Patent JP-S5619365-A (JP)
Title: Manufacture of stator
Inventor: MORI HIDEO
IPC: H02K15/12
Filed: 1979-07-23
Abstract: PURPOSE:To prevent the disconnection of winding in case of molding, etc. by a method wherein the winding is fastened under a condition that a fastening material has a temperature-hardness characteristic within a specified range while being molded under a molding mold temperature and injection time within specified ranges. CONSTITUTION:Winding is fastened under a condition that is within a range between a characteristic curve l2 which a temperature-hardness characteristic of a fastening material is to 25 deg. hardness or less at 20 deg.C temperature from 0 deg. hardness at 50 deg.C temperature and a characteristic curve l3 which that is to 10 deg. hardness or less at 10 deg.C temperature from 0 deg. hardness at 25 C temperature. The winding is molded in succession to said fastening within a molding-possible range joining four points at 7.5sec and 18sec effective injection time at 147 deg.C molding mold temperature and at 5.5sec and 9sec said time at 175 deg.C said temperature. Thus, since proper fastening force and adhesion are given to the winding, the generation of disconnection accidents in case of molding, etc. is prevented while the generation of the unhardening and the insufficiency of filling of a molding layer can be obviated.
Patent JP-2000288417-A (JP)
Title: Cutter
Inventor: TOKUNAGA YASUSHI
IPC: B02C18/06
Filed: 1999-03-31
Abstract: PROBLEM TO BE SOLVED: To provide a cutter in which efficiency of cutting work is improved and also failure is prevented form occurring. SOLUTION: When a control part 5 is given a signal of the existence of a material to be cut, it previously sets initial reverse conversion frequency at an inverter 3 and a three-phase ac motor 6 is subjected to rotary driving to drive a cutter 8. The control part 5 takes in a detected value given from an ammeter 4. The control part 5 seeks reverse conversion frequency corresponding to the taken detected value to set the obtained reverse conversion frequency in the inverter 3.
Patent JP-S5720473-A (JP)
Title: Charge transfer device
Inventor: MATSUMOTO HIROYUKI
IPC: H01L27/148
Filed: 1980-07-10
Abstract: PURPOSE:To accomplish a higher density of a device by transferring electric charge by a 2-phase driving on a 1 bit-3 stage basis with on gate voltage VG surface potential phiS characteristics differentiated in the gradient from others among 3 stages. CONSTITUTION:An electrode 13 is provided at a specified space on a p type Si substrate 11 through an SiO2 film 12a with a thickness of t1 and a common electrode 14 is applied at an intermediate position through films 12b and 12c with the thickness of t2>t1 separated from the electrode 13 by insulation. A p<-> layer 15 is provided under the film 12b. Clock voltages phi1 and phi2 are applied on the electrodes 13 and 14 in such a manner as to be the same in the amplitude and different by 90 deg. in the phase to compose one bit in stages V1-V3. The impurity concentration and film thickness are so selected that VG-phiS characteristics are set linear 16 in stages V1 and V3 and linear 17 in the stage V2. As the surface potential phiS turns over in the depth with the amplitudes of phi1 and phi2 including the intersection P, electric charge is transferred with the amplitudes phi1 and phi2 on a 1 bit-3stage basis thereby providing a higher density device.