Patent GB-1158339-A (GB)
Title: Data Processing Arrangements.
Inventor: BRASS ROBERT LOUIS
IPC: G06F15/16
Filed: 1966-10-13
Abstract: 1,158,339. Computers. WESTERN ELECTRIC CO. Inc. 13 Oct., 1966 [20 Oct., 1965], No. 45775/66. Heading G4A. [Also in Division H4] A data processing arrangement comprises main and auxiliary processors, and a memory containing programmes for controlling the auxiliary processor and data for operation upon by both processors, the main processor being able to access the memory via the auxiliary processor. A main processor 101 can access (read or write), along a first bus 106, either a location in a main memory 103 (storing instructions and data for it) or an auxiliary processor 171. Such an access request to the auxiliary processor 171 accesses a selected register therein or a location in an auxiliary memory 172. The auxiliary processor 171 can also access the auxiliary memory 172 on its own initiative. The auxiliary memory 172 stores instructions for the auxiliary processor 171 and data for both processors 101, 171. Both processors 101, 171 communicate with an input-output system 180 which in the particular embodiment is a telephone switching system to be sampled and controlled by the processors but other realtime applications are also mentioned. The telephone switching system is described in general terms only (Fig. 2, not shown), being the Bell System No. 1 Electronic Switching System, the September 1964 issue of the " Bell System Technical Journal " being referred to for details. The main processor 101 is driven by a 2 Mc/s. clock (461B, Fig. 6, not shown). These clock signals, and sync. pulses (T SYNC.) derived from them and occurring one every 5À5Á sees., are also used to increment and reset, respectively, a counter (4701, Fig. 7, not shown) in the auxiliary processor 171. The counter (4701) controls a C-pulse generator and a T-pulse generator. The T-pulse generator controls those operations of the auxiliary processor 171 which are independent of the main processor 101, whereas the C-pulse generator controls communication between the two processors 101, 171, execution of storage access commands coming from the main processor 101 and maintenance and error detection operations. The T-pulse generator is stopped during execution by the auxiliary processor 171 of storage access commands from the main processor 101. Detection of errors in data or instructions by the auxiliary processor 171 also stops the T-pulse generator. The T-pulse generator, if stopped, is stopped in the first half of an auxiliary processor cycle (5À5Á secs.). An attempt is automatically made to restart it in the second half of each cycle and if the stopping condition has disappeated the generator will actually restart in the first half of the next cycle. The main processor 101 can stop the T-pulse generator by supplying a pulse on a respective line (STOP SP) and the generator will remain stopped as long as the pulse is repeated once every 5À5Á secs. This facility is used to prevent interference when the main processor 101 wishes to communicate with the input-output system 180 directly as distinct from via the auxiliary processor 171. In the course of performing inputoutput functions, the auxiliary processor 171 puts information destined for the main processor 101 into a section of the auxiliary memory 172 and when this section is full, the T-pulse generator is stopped and an interrupt signal (of lowest priority) is sent to the main processor 101 setting a flip-flop therein (SPOA, Fig. 6, not shown). Detection of errors by the auxiliary processor 171 causes a higher-priority interrupt of the main processor 101 by setting a flip-flop (SPOT) therein. An interrupt of the latter priority is also caused if a command order failure or protected area violation is detected by the main processor 101 within itself. If the main processor 101 attempts to access a location in the auxiliary memory 172 currently being accessed by the auxiliary processor 171, comparison of the addresses causes a " critical match " condition which causes an error interrupt of the main processor 101 and the main processor's access attempt is blocked. The auxiliary processor 171 may interrupt the main processor 101 to send an urgent message, by setting a respective flip-flop (SPOB). Interrupts of other priority levels are shown in Fig. 8 (not shown). Diagnosis and correction of errors is done by the main processor 101. Three cycles are required by the auxiliary processor 171 to generate an input-output command the first being under control of the T- pulse generator and the second and third being under control of the C-pulse generator. Thus, if the main processor 101 attempts to stop the auxiliary processor 171 generating an inputoutput command (by stopping the T-pulse generator) in order to prevent interference with a 2-cycle input-output command of its own, the stop signal must be received before the start of the auxiliary command or the latter will proceed to completion. Besides the telephone network controls, the input-output system 180 includes a teleprinter, card writer and message accounting tape unit. The main processor 101 includes an index adder (466, Fig. 4, not shown), an add-one circuit (454), a logic circuit (469) capable of ANDing, ORing or EXCL-ORing two operands and selectively complementing the result, and "accumulator logic " (471) for ANDing, ORing or adding two operands. The auxiliary processor 171 includes logic combination means (30CBL, Fig. 3, not shown), and parity generators (11PG). The contents of the auxiliary memory 172 are initially provided from the main memory 103 and may be provided again in the event of information loss.