Patent GB-1486513-A (GB)
Title: Transmission system for transmission between a central station and terminal stations which are equipped with display devices
IPC: H04L1/00
Filed: 1975-01-24
Abstract: 1486513 Data transmission; methods of coding THOMSON-CSF 24 Jan 1975 [25 Jan 1974] 3300/75 Heading H4P A transmission system particularly between a central station, and remote stations each containing a visual device, e.g. teleprinter, utilizes a frame of bits for reproduction of a visual character comprising (N1 + 1) rows or groups of N2 bits of which the first row designates whether the bits following relate to the production of characters or to function and control information; function information includes some redundancy so that errors in transmission may be detected. Transmission may be in simplex and each bit may be represented by two half trains from a group of say 8 frequencies. In the embodiment described N1 = 7 and N2 = = 7 hence a frame = (N1 +1) N2 = 56 bits, and a block N1.N2 = 49 bits. The arrangement unites transmission of constant length blocks incorporating non redundant character data, where some errors would not prevent recognition of the character, with redundancy for functions where incorrect interpretation would cause malfunction. Each remote station, which may be reached through a radio HF/UHF channel comprises a FSK demodulator feeding a circuit 13 which recognizes start of code blocks STC or start of function blocks STF and taking account of redundancy identifies the function of such blocks and on multiple output 132 supplies successively N1 rows of N2 bits representing a character, and multiple output 133, N2 bits representing functions, both to teleprinter 14 connectible to a transmission 64 key board controlling and selecting 2 frequency words for transmission. The circuit 13, Fig. 2, comprises a clock 31 supplying a sampling signal of k (=at least 8) times received bit frequency applied to a shift input H of register 33 having k.N2 stages hence each bit is sampled k times and recorded in register 33. Outputs from this are respectively taken to k.N2 inputs of comparator 34 comprising k.N2 comparators and a further input with signals obtained from k times character sampling of each of the bits of each character block prefix, so that with perfect reception each of k.N2 comparisons will produce a parity signal; these are applied to a majority decision device providing an output to AND 50. Where the bits recorded in 33 result from reception of a function block start, they are passed through a comparator 35 of similar structure (to 34) to AND 51; AND's 50, 51 are connected to 1, 0 inputs respectively of multivibrator 40.  Another multivibrator 53 is placed in a 1 state at the end of each block hence enabling AND's 50, 51 hence line 41 delivers a 1 after a character start and line 42 after detection of a function, start. An OR 36 prevents false operation of the system. A clock extraction circuit 37 supplies pulses at bit frequency centres to step register 38 of N2 stages, also by division at 39 by N2 provides a N2 group end signal except for start groups. A further divider by N1 provides an end of block signal. A circuit 47 has N2 parallel counters with inputs connected to register 38 through AND gate 48 enabled by divider 39 and multivibrator 40, the N2 counters being reset at the beginning of each block by OR 36. Each counter has a decoder giving a 1 each count of ¢ (N2+1)=4 which through N2 AND gates, enabled at the end of each block by divider 46, give a multiple output 133 to teleprinter 14; 46 also gives an output to multivibrator 53 and AND 44 whose second input receives an output from multivibrator 40 hence AND 44 delivers an end of function code block signal. Fig. 4 (not shown) relates to a transceiver suitable for use at a central station.