Patent GB-926525-A (GB)
Title: Improvements relating to digital computing arrangements
Inventor: MYNALL DENNIS JAMES
IPC: G06F7/57
Filed: 1959-10-23
Abstract: 926,525. Digital electric calculating machine. ASSOCIATED ELECTRICAL INDUSTRIES LTD. Oct. 24, 1960 [Oct. 23, 1959], No. 36023/59. Class 106 (1). A serial binary digital computing circuit is arranged to add to or subtract from first input numbers numbers which are formed by multiplying second input numbers by a fixed predetermined factor. The invention may be applied to programme controlled machine tools, the first input numbers being position-representing numbers, the second input numbers being correction factors depending on the co-ordinate direction of movement and the fixed factor depending on the radius of the particular tool being used. As described, first and second input members are read in turn from a magnetic tape, each second number being read first in time with respect to its associated first number. The second number is applied to an input lead cf, Fig. 2, digit-by-digit commencing with the least significant digit, each digit being presented in parallel to adding circuits A1-A6 and a delay DL15 over switches in lines sc1- sc7, which switches are selectively closed in accordance with the binary digits of the fixed factor. The fixed factor may be set in decimal form on multi-position multi-bank digitizing switches (not shown) which control the switches in the leads sc1-sc7 on a binary basis. The adders A1-A6 and delay DL 15 each provide a one-digit delay so that successive partial products are accumulated and the desired product fed to an output terminal ot. This output is fed after delay, if necessary, to an adder/subtractor circuit CU which is also fed, synchronously, with the first input number on a lead pn, addition to subtraction being controlled by a lead sg according to a sign digit associated with the second input number. Adder circuits, Fig. 4. Each adder circuit comprises magnetic cores 1-10, the cores 1-4 and 5-8 forming two half-adders. The operation of the adder is controlled by staggered timing pulse trains p, q, r, one pulse from each timing train occurring during each digit pulse period. Assuming a " 1 " pulse on one but not both of input leads it1, it2, the core 1 or 2 is set and is reset by a p pulse to produce an output which sets a buffer core 9, the buffer being reset by a " q " pulse which, assuming there is no propagated carry pulse, sets the core 5, which, when reset by an r pulse produces an output at ot via a transistor amplifier TrO. If input pulses appear on both leads it1, it2, neither core 1, 2 is set due to the inhibit windings h, but a core 3 is set from the input it2, which core 3 produces an output in response to a pulse q to set a core 24 which is not inhibited since both inputs it1, it2 have been activated. The next r pulse sets a core 10 and during the next digit period this core is reset by a q pulse to provide the required carry input at it2<SP>1</SP> to the second half-adder. A circuit for the combining unit CU is described (Fig. 5, not shown), this circuit comprising an add/subtract control portion employing magnetic cores and an adder similar to that of Fig. 4. The add/subtract control portion is effective to invert the input on the lead rc in the case of subtraction. Specifications 926,524 and 926,527 are referred to.