Patent FR-2801419-A1 (FR)
Title: Method and device for reading integrated circuit memory
Inventor: FOURNEL RICHARD
IPC: G11C16/24
Filed: 1999-11-18
Abstract: The device (1) for reading an integrated circuit memory comprises a differential amplifier (2) with data (MTX) and reference (REF) inputs provided by respective outputs of data and reference current-voltage converters (CIVD, CIVR), which are connected to the data and reference bit lines (BL, BLref), respectively, a reading current generator (3) for the provision of a reference current (IR) and a data current (ID), which is a fraction of the reference current, a circuit (4) for an asymmetric precharge for bringing the data input (MTX) of differential amplifier to a higher voltage level than that of the reference input (REF), so to latch the output (Out) in a determined state. A detection circuit (5) and a logic circuit (6) are for detecting if there is a sufficiently large voltage gap between the two inputs of differential amplifier, and the provision of control signal to asymmetric precharge circuit (4), in order to stop the precharge and let the device automatically pass to an estimation phase. In the estimation phase, if the memory cell (Cm) is programmed, the output remains unchanged; if the memory cell is blank or erased, the output is latched in the other state.  The method for reading an integrated circuit memory includes a precharge phase for precharging the data bit line (BL), which comprises a memory cell (Cm) to be read, and the reference bit line (BLref), which comprises a reference cell (Cref), and an estimation phase established by the current generator (3), which provides the reference current (IR) for the reference bit line, and a fraction of it as the data current (ID) for the data bit line. The asymmetric precharge is carried out so that the precharge current in the data bit line is higher than that in the reference bit line, by the circuit (4) delivering a precharge current (Ipch). The asymmetric precharge circuit (4) and the current generator (3) are activated by the detection of a read control signal (SON), and the circuit (4) stops the precharging when the stop condition is met, which corresponds to the sufficiently large voltage gap. The read control signal (SON) is generated at the instant or after the selection of data and reference bit lines. The asymmetric precharge circuit (4) comprises a transistor (T8) for providing a supplementary precharge current to the bit line (BL) associated with the data input (MTX) of differential amplifier. Each current-voltage converter contains a transistor (Tp) connected between input and output nodes, and a feedback loop comprising an inverter (I1), for the control of gate voltage as a function of input node voltage. The logic circuit (6) provides the signal for activation of asymmetric precharge circuit as a function of stop control signal and the read control signal (SON). The logic circuit (6) contains a memory element of type latch RS. The differential amplifier comprises an output stage dimensioned so to favor the latching of output in opposite polarity to that of latching in the precharge phase, and a second output stage identical to the first and connected in the other branch. An integrated circuit memory comprises the proposed reading device.