Patent GB-794117-A (GB)
Title: Improvements in or relating to electronic counters
Inventor: GUTTRIDGE ERIC JOHN
IPC: H03K23/82
Filed: 1955-04-15
Abstract: 794,117. Digital electric calculating-apparatus. POWERS -SAMAS ACCOUNTING MACHINES, Ltd. March 22,1956 [April 15, 1955], No. 10987/55. Class 106 (1). In an electronic decimal counter, in which each denomination comprises a chain of four symmetrical bistable units connected by triggering circuits, a gating circuit connected to outputs of the first, third and fourth bi-stable units operates a restore triggering circuit connected to the inputs of the second and third units to restore the second, third and fourth units to a starting or zero condition on application of each tenth pulse to the input of the first unit of the chain. Fig. 1 shows one denomination of a decimal counter comprising bi-stable trigger stages S1-S4 corresponding to values - 1, - 2, +4, + 8, respectively; the code is such that the 9's complement of a decimal digit can be obtained by reversing all the stages. In the start or " 0 " condition, to which the counter may be reset by a positive pulse at R, anodes S1A0-S4A0 are all " down " in potential. The first stage S1 1 is switched by negative pulses applied to triggering circuit T1 in response to positive digit representing pulses at DP or carry pulses from the next lower denomination at C1. The stages S2-S4 are switched through triggering circuits T2-T4 when anodes S1A1, S2A1 and S3A0 respectively go negative. Thus in response to the first pulse at T1, all the first three stages are switched to the " 1 " condition (A0 anodes " up " in potential). The next three pulses cause stages S1, S2 to operate subtractively so that " 4 is represented by S3 only remaining in the "1" condition. The fifth pulse switches S1, S2 to " 1 " again, and restores S3 to " 0 " thus switching S4 to the " 1 " condition. After the next three pulses, all the first three stages are in the " 0 " condition, and the next (ninth) pulse acts like the first pulse to switch them to " 1." Since S1, S3, S4 are then all in the " 1 " condition, an " up " potential. is applied to all the diodes of a gate G; thus, when S1 is switched to " 0 " in response to the tenth pulse, the gate output drops, applying a negative restoring pulse through a further triggering circuit T5 to stages S2, S3. As S3 returns to " 0," S4 is also restored through T4, and a carry output pulse is obtained at CO. The trigger anodes are connected to read-out lines S1+ to S4+ and S1 - to S4 - , Fig. 2, the " + " or " - " lines being selected according to whether the registered result is positive or negative as indicated by an " up " potential on line P or N. When read-out switch ROS is opened, line A is allowed to rise in potential and signal-transmitting lines ST1- . ST4 can each attain a potential corresponding to the associated selected read-out line, thus applying signals via decoding apparatus (not shown) to a mechanical store associated with a record card punch. In Fig. 2, it is assumed that the counter registers " 5," and that the result, being negative, is read out as " -4." The counter may be incorporated in a calculating machine operating according to the cycle illustrated in Fig. 4. After a calculation, an read-out of the result registered on the counter, a check calculation with sign reversal is made at the end of which the counter should register zero (all 0's or all 9's according to the sign of the result). This is checked by opening switch CTS in series with ROS, thereby allowing lines A and B to rise in potential, whereupon if any value other than zero is registered, a positive error signal appears on line ESL which prevents the result read out being punched on a card.