Patent UA-73370-U (UA)
Title: Third harmonic-based low-noise transistor generator
Inventor: OMELIANENKO MYKHAILO YURIIOVYCH
IPC: H03B7/00
Filed: 2012-02-17
Abstract: A third harmonic-based low-noise transistor generator comprises a dielectric plate, whose face and back sides comprise s, two identical super-high-frequency field-effected or bipolar transistors. The plate is installed between wide walls of a rectangular waveguide along thereof axis in the middle of wide walls in such a manner that the plate surface is parallel to the narrow walls of said waveguide. The s of face and back sides are performed as two transmission lines (first and second) located one by one with axis parallel to the axis of the rectangular waveguide. Each section of the transmission lines comprises two strips located along the waveguide axis. The first transmission line adjacent to the plate face is finished by two opposite directed probes, which are not in contact with the walls of rectangular waveguide. In aria of said probes location the waveguide walls are narrow to size lesser than one sixth of generated signal wavelength. Each of the printed strips of the first transmission line at the end opposite to said probes is connected to drains of the similar field-effect super-high frequency transistors in such a manner that the drain of one transistor is connected to one printed strip of the transmission line, the drain of second transistor is connected to the second strip of transmission line. Transistor gates are connected to two strips of the second transmission line correspondingly. The printed strips of first and second length of the transmission line are located in such a manner that one of them is positioned on the face of the plate on one of the waveguide axis, the another- on the back face of the plate on the other side of said axis; arias of sides opposite to the said strips divided by the waveguide axis comprises solid conductor strips which are galvanic connected by a line of plated holes located along the waveguide axis. Field-effect transistors are installed on face and back sides and connected to conductor strips of the corresponding sides; probes opposite directed to one another are located out of projections of the solid printed conductors of the first transmission line and located on the opposite sides of the plate. End of the second transmission line, which is opposite to transistor gates is connected to aria of the plate comprising solid plated layers on the both side in a manner that solid conductor strips and printed strips of the transmission line are connected to them on the correspondent sides. The said aria of the dielectric plate comprises plated holes which galvanically connect the solid plated layers of the face and back sides of the dielectric plate. The holes are positioned in a manner that they limit the rectangular aria of plate with wall sizes that are equal to a half of wavelength within space where dielectric of the said plate is located. The plated holes are absent in the arias of connection of strips of second transmission line to the solid plated layers, the layers comprise two arias with removed metallization, width of which is equal to the width of strips located along the strips on both sides in a manner that they are adjacent to extension of the strips depthward plated layers in parallel to the waveguide axis.