Patent GB-1445897-A (GB)
Title: System for transfer of data between central units and controlled  units
IPC: G06F13/40
Filed: 1974-03-28
Abstract: 1445897 Data handling system INTERNATIONAL STANDARD ELECTRIC CORP 28 March 1974 [5 April 1973] 13731/74 Heading G4A A data handling system includes two central units UCA, UCB, and a plurality of groups of controlled units, e.g. OG1-OGn, each group being connected to each of the central units via respective interfaces, DR1A, DR1B &c., which transmit orders from the central units to the controlled units, and is arranged such that a central unit wishing to transmit an order does so directly via the appropriate interface if that interface is available, but if it is not available, transmits the order to the other central unit via a transmission link IPL for transmission by that other unit. The controlled units may be telephone or telegraph installation remotely controlled by central processing units. Each central unit includes a memory ME addressed by a normally incremented program counter CP, an instruction op code decoder DEC, and a register M for the address part of an instruction. The memory contains a series of instructions 1NS1-1NSn with op code, Cl, and address, AR, parts and a series of transmission control registers. These last registers include a register BPE# for each associated interface in which bit 0 indicates whether the unit has previously transmitted an order, bit 1 indicates whether the memory contains an order, in a register BPE3 one of which is provided for each interface, originating from the other central unit, bit 2 indicates when an order from the other central unit has been sent by the central unit via one of its own interfaces, and bit 4 indicates when the central unit has transmitted an order to the other central unit for transmission by that unit. Registers BT1A and BT1B respectively indicate at each bit position whether a corresponding one of the interfaces associated with the central unit and the other central unit is available. Register HL#, one of which is provided for each interface, points to one of the registers following, HL#A &c., which contains the next order to be sent by the central unit to the interface, the contents of HL# being decremented as each order is sent until the contents are zero which is interpreted as meaning that the unit has no more orders to send. Operation follows the flow charts of Figs. 3-5 (not shown) in which an interrupt from an interface to a central unit, say UCA, causes BPE# to be examined to see if the central unit had previously sent an order. If it had further examination of BPE# indicates whether it was sent on its own behalf or for the other central unit. In the latter case the appropriate data is sent to that other unit, BPE# is reset to zero, and the next order pointed to by HL# located. If this order exists the appropriate bit position of BT1A is examined to determine whether the appropriate interface is available. If so the order is sent and bit 0 of BPE# set to reflect the fact. If the previous order was sent by the central unit on its own behalf bit 1 of BPE# is examined to determine whether an instruction from the other central unit is stored in BPE3. If so and the appropriate interface is available bits 0 and 2 of BPE# are set and the instruction sent. If the unit had not sent an instruction when the interrupt occurs HL# is examined to locate the next instruction if it exists. If it does the order is sent as above. If not bit 1 of BPE# is examined to determine whether an instruction from the other central unit is stored in BPE3. If so the instruction is sent as above. If when UCA is to send an instruction, BT1A is examined and the appropriate interface is not available, BT1B is examined to determine whether the other central unit has access to the appropriate one of its interfaces. If it has bits 0 and 4 of BPE# are set and the instruction and the identity of the appropriate interface are sent to UCB where the instruction is stored in register BPE3 and bit 1 of BPE# is set.