Patent GB-1492491-A (GB)
Title: Coherent fixed baud rate fsk communication method and apparatus
IPC: H04L27/10
Filed: 1975-04-02
Abstract: 1492491 Selective signalling INFORMATION IDENTIFICATION CO Inc 2 April 1975 [5 April 1974] 13508/75 Heading G4H [Also in Divisions H3-H5] An FSK system transmitting N message bits in blocks forms at least two consecutive output signal levels for each message bit which are transmitted as related frequencies such that each message bit has the same transmission time, transmission clock pulses being derived from the FSK modulator output. For two level input signals a complemented pair i.e. 1/0 (0/1) for each message bit are transmitted as related frequencies FM/FS (FS/FM). Blocks may also include uncomplemented sync. bits related in level to each first message bit. At the transmitter.-To establish initial contact a determined N bit message block is inserted manually or otherwise into 16 then transferred parallely into encoder 18 which develops message bit complements plus sync bits, to control generator 24 producing frequencies FM, FS, which are used to modulate a carrier at 28 and pass to a transmitter 30; (FM-FS) may equal 2 x baud rate. Generator 24 output is also passed to a ¸P counter providing a master clock signal, in response to 1/P input zero crossings, to a counter 72, Fig. 2, in encoder 18 also to ¸2 counter 84 through NOR gate 70 when primed by a low signal on line 82, which is switched to high after N complemented bits have been transmitted. Parallel in/serial out N bit register 88 has a cyclic feedback path 92, is connected to AND gate 96, also through inverter 94 to AND 100; this also receives register 88 input through inverter 102; AND's 96, 100 control generator 24 through OR 104. When message bits from, and clock pulses to register 88 are both high AND 96 issues a 1 through OR 104 but when clock pulse goes low AND 96 is inhibited hence 104 issues a 0 i.e. the message bit complement. When clock pulses next go high if register output is low neither gate issues hence a 0 passes through 104 but when clock pulses next goes low, through inverters 94, 102, AND 100 is enabled and a 1 is issued thus gates 96, 100 issue 1-0 or 0-1 viz complemented pairs as appropriate.  Inverter 102 steps counter 74 and after 2 N transitions (N clock pulses) give a high output to M counter 42 also to counter 76 hence for every odd input line 82 goes low priming NOR 70, and on every even input NOR 70 is disabled and counter 72 is enabled thus counting clock pulses on path 40; after two clock pulses (four transitions) counter 72 output goes high thus resetting counters 74, 76 causing counter 76 output to go low thus deactivating counter 72. After N complemented pairs have been generated, counter 72 output is high causing the first message bit to be connected to generator 24 for the next two clock pulses thereby producing two sync bits identical to the first message bit prior to the second circulation of the determined message. The number of sync bits will be 2 less than the dividing value of 72, i.e. the first two pulses correspond to sync bits, the third corresponds to production of the first message bit and the fourth pulse causes NOR 70 to be enabled. The M counter 42 controls operation of modulator 28 and permits register 88 to be loaded with the determined message; after transmission M times the M counter output goes high and remains high for a further M cycles thus modulator 28 is rendered inoperative for a determined period (M cycles) during which the message in assembly 16 is transferred into register 88 after which M counter output goes low and transmission is resumed. The receiver also has a P counter receiving input signals which thus steps in synchronism with P counter 38, assuming nil loss of transmission. Counter 84 may have a dividing value of higher than 2 thus allowing more than one level to be produced following message bit, e.g. if counter 84 divides by 4, three signals would be produced on path 22 for each message bit by an additional network similar to that including gates 96, 100. The message bit complements are used in an error detecting arrangement in which message bits are clocked at half rate into a one bit register (120, Fig. 3, not shown) by comparing each message bit with its complement in exclusive OR gate (128) before passing into N bit register (122). If errors are detected or sync bits find their way into register (122) this circuit is reset by a high signal on line (180) derived through gates from (132) which resets counters (110, 158). The arrangement can detect odd and even adjacent and non adjacent errors. A comparison network is connected to register (122) to check, in one mode of operation, that the receiver identification code is correct and the number of times it has been received is recorded by an M counter. The decoder (60) is self synchronizing as the first bit of every message block is transmitted and repeated without complementing which simulates an error condition which resets the decoder to its initial receptive state. When a message block has been correctly received a valid data signal appears on path (66) and the receiver is deactivated temporarily until the content of register (122) is transferred out. The arrangement may be utilized in a one way communication system in which station identification codes can be used to control locks on vehicles, gates or doors, or in a paging system, the identification code when received being checked at least twice. A particular form of two way system is described in connection with Fig. 6 (not shown) in which a vehicle or cargo container which has been stolen or become lost may be identified by inserting an identification code in a transmitter, carried for example in a helicopter, which on reception by the vehicle container, &c. receiver and checked thereby initiates a return transmission with the same or another code to a receiver located adjacent to the prime transmitter.