Patent GB-1074755-A (GB)
Title: Communication system
IPC: H04B1/26
Filed: 1965-08-06
Abstract: 1,074,755. Radio receiving circuits; frequency synthesizing arrangements; transistor oscillator circuits. GENERAL DYNAMICS CORPORATION. Aug. 6, 1965 [Aug. 17,1964 (2)], No. 33896/65. Headings H3F, H3Q and H3T. The invention primarily relates to a double superheterodyne radio receiver which is tunable over a wide range by means of a frequency synthesizer controlled by a digital frequency counter. Aerial 10, Fig. 1, is coupled to an R.F. amplifier 11, tunable from 2-76 Mc/s. by means of a tuning voltage derived from digital frequency synthesizer 12. The R.F. output is applied to a first mixer 14, together with a first injection frequency, also derived from synthesizer 12. The output from first mixer 14 is applied via band switch 16, alternative selectable filters 24, 26a, 26b and switch 18 to a second mixer 28; on range A, however the output goes direct from first mixer 14 to I.F. circuits 22. Second mixer 12 derives an injection frequency from synthesizer 12 and when in use feeds via switch 20 into I.F. circuits 22; these are followed by demodulating circuits 40 appropriate to the modulation in use, and audio circuits H2. Transmission.-The arrangement may alter. natively be used in a radio transmitter, i.e. I.F. signal, suitably modulated is translated to a desired radio frequency using a similar arrangement of mixers 14, 28 and associated filters, together with digital frequency synthesizer 12. Digital frequency synthesizer.-The first mixer injections frequency, i.e. any of the frequencies spaced 1 kc/s. apart within a range 2-76 Mc/s. is synthesized from a reference frequency signal supplied by frequency standard 44, Fig. 2, and a further signal from switched crystal oscillator 46 which comprises ten crystals: errors in the latter frequencies are cancelled out in the synthesizer. Frequency standard 44, e.g. 36 Mc/s., may be crystal controlled and includes a pulse shaper circuit driving a plurality of frequency dividers 46a comprising flip-flop chains whereby pulse trains of frequency 450 kc/s. and 1 kc/s. are obtained, and also by the mixing of 900 kc/s. and 100 kc/s., derived from points in the chain, the frequency 1 Mc/s. Sine wave signals are derived from the respec. tive pulse trains by means of tuned circuits. The second mixer injection frequency comprises 1, 5 or 9 Mc/s. and is derived from the 1 Mc/s. output from divider 46a by means of spectrum generator 48 and filters 50, 52, 54: the output from the latter is selected by means of switch 56 ganged to the band switch and is applied to the second receiver mixer via amplifier 58. 1 Mc/s. signal from divider 46a is also converted into any selected one of the frequencies 24, 25, 26, 27 Mc/s. in synthesizer 60, which may comprise frequency multipliers and mixers: it may alternatively comprise a tunable voltagecontrolled oscillator locked to the 1 Mc/s. reference signal by means of a phase-locked loop, as described below. The 1 kc/s. signal from divider 46a controls a further similar synthesizer 62 which is controllable by 1, 10 and 100 kc/s. knobs in order to select any frequency between 2À000 and 2À999 Mc/s. in 1 kc/s. steps. The 450 kc/s. reference signal from divider 46a is translated, by mixing with an output from spectrum generator 48 in mixer 64, to 13À450 Mc/s. which is selected by crystal filter 66: alternatively the 450 kc/s. may be obtained by mixing the 9 Mc/s. output of filter 54 with that of a tunable oscillator of nominal frequency 9À450 Mc/s., the pass-band of filter 66 extending to 20 kc/s. and allowing a vernier frequency adjustment of this amount. The output from switched crystal oscillator 46, being any of the frequencies 4 Mc/s. apart - in the range 4À045-44À045 Mc/s., is combined with those derived from reference frequency standard 44, i.e. the outputs of spectrum generator 48, filter 66 and synthesizers 62, 60 in a loop 68 comprising mixers 72, 74, 76, 78, 80 and filters 84, 86, 88, 94, 96, 98, which is errorcancelling by virtue of the frequency from oscillator 46 being added in one of the two mixers 72, 80 and subtracted in the other. The Specification gives examples illustrating the manner in which a particular desired frequency may be built up, both by using addition in mixer 72 and also with subtraction in that mixer. The final output is derived from mixer 80 and used to control the frequency of adjustable oscillator 100, set manually to approximately the correct frequency and providing the first mixer injection frequency: the control loop comprises phase detector 102 and low-pass filter 104, the output of which in addition to controlling oscillator 100 provides the voltage for tuning. the R.F. amplifier. Preset divider synthesizer (62, Fig. 2).-An output variable over the range 2-2À999 Mc/s. is derived from variable oscillator 138, Fig. 3 which is tuned by means of voltage variable capacitors, being set manually to approximately the correct frequency by means of 100 kc/s. knob 34 which switches in separate variable capacitors and 10 kc/s. knob 32 which switches resistors determining the standing D.C. bias on each capacitor. The output of oscillator 138 is also converted in pulse shaping circuit 144 to a corresponding train of narrow pulses for application to a counter chain comprising cascaded decade counters 110, 112, 114 and binary counter 116. Each decade counter (Fig. 4, not shown) comprises four cascaded bi-stable circuits each interconnected with a corresponding diode gate in one of cascaded gate circuits 118, 120, 122 respectively: binary counter 116 comprises two cascaded bi-stable circuits each connected to a corresponding gate in gate circuit 124. The gate circuits, when set up for a chosen output frequency by means of corresponding selector switches 126, 128, 130 operated respectively by 1 kc/s. knob 30 and 10 and 100 kc/s. knobs 32, 34 referred to above, cause pulses to pass at a repetition frequency of approximately 1 kc/s. to phase detector 136, via pulse shaping circuit 144. This pulse train is compared in the phase detector with an accurate 1 kc/s. reference signal and the error is applied to oscillator 138 to correct its frequency. The pulse train is also fed to a pulse stretcher 134 which applies lengthened pulses to each of the counters 110-116 whereby the latter are reset to zero after each pulse. Oscillator circuit.-The switched crystal oscillator (46, Fig. 2) comprises a transistor 190, Fig. 5, in grounded base connection, the emitter circuit comprising an R.F. choke 198 and a tuned circuit comprising tapped inductor 209 and capacitor 206 being connected between collector and earth. The frequency of oscillation is determined by means of crystals 208a- 208j, which can be selectively switched in between the emitter and the tap on inductor 209 by means of switching diodes 210a-210j controlled by switches 218a-218j. At the same time, the resonance frequency of the tuned circuit is appropriately altered by means of shunt capacitors 222b-222j which are brought into circuit by switching diodes 224b-224j controlled by switches 1b-1j ganged with the switches 218b-218j. The variable frequency oscillator in the phaselocked loop (146, Fig. 3) and the error cancelling loop (68, Fig. 2) may be similar, the diode switching circuits being used to introduce tuning capacitors instead of the crystal circuits, so as to give coarse tuning, precise tuning being performed by means of a voltage variable capacitor or a back-to-back pair, connected across capacitor 206.