Patent GB-801908-A (GB)
Title: Gating circuit
Inventor: LANNING WALTER CLAYTON
IPC: H03K19/16
Filed: 1956-08-29
Abstract: 801,908. Circuits employing bi-stable magnetic elements. SPERRY RAND CORPORATION. Aug. 29, 1956, No. 26393/56. Class 40 (9). Two magnetic storage cores 10, 11, Fig. 1, have reset windings 14, 17, input windings 12, 15 and read windings 13, 16 which are sequentially energized by clock pulses over terminals 18, 19, 20, one of the windings 13, 16 presenting a high impedance during each read-out operation so that current is permitted to flow either from an output terminal 21 or to an output terminal 22 according to the magnetic state of the cores determined by the previous input pulse. The arrangement is termed a " functor " and may be of the " functor zero " (fo) type or the " functor one " ( f1 ) type depending respectively on whether the read-out windings 13, 16 are arranged as shown or whether they are both wound in the opposite direction. In operation, a functor one with a " 1 " input produces an " 0 " output at terminal 21 and a " 1 " output at terminal 22, whilse the converse applies when the input is " 0." A functor 300 yields the opposite results. A trigger unit, Fig. 4, may be formed by connecting two functor one units 28, 29 in series and providing a feedback loop 55. Both units have their second input terminals 27 earthed and employ their current output terminals 21 so that they function as logical NOT elements. Each functor unit is subjected to three out of four clock pulses in a pulse cycle, the order of the pulses 1, 2, 3, 4 applied to the windings of each unit being indicated by the rotation within each block 28, 29 in which the upper, lower left and lower right pulse-sequence references apply to the reset, input and read windings respectively. When a " 1 " pulse is applied to terminal 46, the functor 28 transmits a zero output pulse to functor 29 which in turn produces a " 1 " output at terminal 54. This output is also fed back to functor 28 to maintain the condition. To terminate the production of " 1 " output pulses, a " 1 " pulse is introduced over terminal 47 to functor 29 in clock pulse period 3. In a modification, Fig. 6, the output from functor 29 is applied to a delay circuit comprising functor zero units 69, 72, 73. This arrangement permits only a predetermined number of " 1 " output pulses to be produced at terminal 64 before a resetting " 1 " pulse is applied to functor 29 over a delay-selecting switch 71 and lead 80. It is stated that this arrangement has the disadvantage that the resetting period is prolonged by the " 1 " pulses stored in the delay circuit, during which period a further " 1 " output pulse series cannot be obtained. This defect may be overcome by the use of the delay circuit shown in Fig. 7 in which alternate functor zero units 72, 74, 76 each have an input terminal 27 connected to output terminal 22 of the final functor 77. When functor 77 delivers a " 1 " output at its terminal 21 to reset functor 29, a " 0 " output is obtained at terminal 22 which prevents " 1 " pulses from entering the functors 72, 74, 76. In this manner the information stored in the delay circuit is destroyed and the functors 28, 29 become available immediately to further signals. A suitable clock-pulse source is described in which a 100 kc/s. oscillator 30 feeds two centre-tapped transformers 31, 33, which provide pulses spaced by 180 degrees to pulse shaping and amplifying circuits. A 90 degrees phase shifter 32 is included in the circuit of transformer 33 so that clock pulses 1, 2, 3, 4, mutually spaced by 90 degrees appear in turn at terminals 38, 45, 39, 44.