Patent GB-1126437-A (GB)
Title: Network to determine an available route through a switching network
IPC: H04Q3/00
Filed: 1966-07-22
Abstract: 1,126,437. Automatic exchange systems. INTERNATIONAL STANDARD ELECTRIC CORP. 22 July, 1966 [24 July, 1965], No. 33052/66. Heading H4K. In an exchange system having a multistage switching network and a common control circuit, the latter includes a memory in which the busy/ idle state of each link (or cross-point) is recorded and a further temporary memory to which the state of those links usable for a call are transferred from the first memory prior to a selection operation. The latter is performed by means of a form of simulation network which has an AND gate in respect of each link and outlet of the switching network. The switches, which may be read relays, cross-bars or PNPN diodes, are arranged in three stages, each consisting of two, 2 x 2 arrays. It is suggested that in practice the network might consist of ten, 20 (inlet) x 8 A switches; eight, 10 x 10 B switches; and ten, 8 x 20 (outlet) C switches and that for such a network a plurality of simulation networks might be provided. It is further mentioned, that in case a busy outlet is " selected " at the end of a route search then those links giving access to this outlet are artificially busied and a new search is initiated. Another arrangement for this case is outlined below. Particular description, Fig. 2.-Since the identity of a calling inlet is known only two AND gates V1 and V2 are necessary in respect of the four AB links. However, as these links have access to all the BC links which in turn have access to all the outlets, two sets of four AND gates V3 to V6 and V9 to V12 respectively are provided in respect of these links and outlets. The links corresponding to gates V3 and V5 terminate on the same C switch so the outputs of these gates are connected via a common OR gate V7 to the input of gates V9 and V10 which correspond to the outlets of this switch. Similarly for V4 and V6. A number of temporary stores R1 to R3 having a cell for each possible link are connected on their input sides via multiple LB1 to the busy/free memory Sp and on their output sides to one input of the associated gates. A pulse generator which operates cyclically and which marks 3 out of its 10 outputs at any one time is connected to another input of each gate. In operation, central control St marks LB2 and L1, whereby memory Sp supplies the state of possible links to stores R1 to R3, e.g. outputs RA1, RB2 and RC3 are marked free and the generator is started, it being assumed that it has reached the position where outputs ZA1, ZB2 and ZC3 are marked. The particular simulation network relevant to the calling inlet is marked at N1. Consequently, gates V1, V4, V8, V11 and V13 are conductive, whereby central control is informed (over L2) that a unique route has been selected. The identity of the route is passed over LB3 to memory Sp so that this may be updated and the chosen path set up. The counter is either reset to zero, i.e. outputs on ZA1, ZB1, ZC1 or it is incremented by one. If RC3 is found to be busy, the generator may be stepped on, so that a different set of its outputs are marked, until a path to a free outlet is located.