Patent GB-1056511-A (GB)
Title: Interrupt logic system for computers
IPC: G06F13/26
Filed: 1964-01-03
Abstract: 1,056,511. Digital computers. T.R.W. Inc. Jan. 3, 1964 [Jan. 3, 1963], No. 425/64. Heading G4A. In a computer in which the execution of a programme can be interrupted in response to requests from a peripheral unit, means are provided which in response to an interruption available signal from the computer, and an interrupt request from the peripheral unit, are effective to inhibit the read out capability of the computer memory, means responsive to this inhibition causing the computer to carry out an interrupt subroutine. The interruption facility is provided in the computer described in Specification 1,025,646 which operates by stored microcommands called " logands " and comprises six 15-bit circulatory registers 12, 14, 16, 18, 20, 22, the E-register 14 acting as a buffer for inputoutput and memory access; the M-register 16 serving to address the magnetic core memory 10; the L-register 12 holding a logand for execution, and being capable of addressing locations 0-63 of the memory which serve as a "scratch-pad" " or working memory; the A- and P-registers 20, 18 being employed in arithmetic operations; and the T-register 22 being used in an output operation. The operation of the computer is controlled by a 7-state " state counter" 32 consisting of three flip-flops (Fig. 2D, not shown) responsive to inputs from various register stages and auxiliary gates to provide control outputs on lines RC, RL, WF, WL, HC, RP, WP. Interrupt mode. The computer has peripheral equipment comprising a magnetic tape, a printer, a card reader, a card punch and a typewriter, each of which can provide an "available" signal when it is available for an input-output operation, and an " unavailable " signal when it is not functioning or mal-functioning. There are three types of interrupt operations: " data interrupt " for data transfer; " command reject " interrupts which occur when an inoperative peripheral device is addressed; and " miscellaneous " interrupts for example due to a power failure. An interrupt signal is generated by the circuit shown in Fig. 5. For example an AND gate 264 is enabled in the presence of a signal indicating that the card reader is available; a signal INWBI produced by the L-register, Fig. 3, indicating that no data input transfer is presently occurring; and a signal F FIOIC from a flip-flop FFIO1 in a priority determining circuit comprising four flip-flops (Fig. 4, not shown). Gates 266- 276 produce outputs in response to other interrupt conditions. Operation of any of the gates 264-276 causes an " interrupt " signal INBFC false, Fig. 5, to be produced, this signal being applied to a gate 216, Fig. 3, to inhibit the next computer memory read operation so that the memory access register (E-register), Fig. 3, will contain all " 0 "s thereby producing a signal GAIT which enables gates in a circuit (Fig. 6, not shown) to set the second and third stages 2 and 03 of the E-register with an address in the " scratch-pad " memory dependent on the type of interrupt which has been generated. The resulting scratch-pad address is transferred to the L-register, the former contents of which are transferred via the E-register to the scratchpad memory. The presence in the L-register of this interrupt logand causes the current address to be transferred from the M-register to be stored in the scratch-pad memory. The presence in the L-register of this interrupt logand causes the current address to be transferred from the M-register to be stored in the scratch-pad address derived by adding unity to the address in the L-register. This new address being transferred to the M-register to become the first address of the interrupt subroutine. If the interrupt is for data input, the completion of the input of data is sensed by one of gates 300, 302, 304, Fig. 3, thereby causing a " terminate " logand to be placed in the L-register together with the scratch-pad address utilized for storing the contents of the M-register. The interrupted logand and interrupted address are then read out from the scratch-pad memory to the L- register and M-register respectively, and control is returned to the interrupted programme. Priority circuit.-With a " data " interrupt in operation the signal FF101C from flip-flop FF101 is no longer present at gates 264-268, Fig. 5, and prevents further " data " interrupt while a " command reject " interrupt, as at gate 272, may take place. Reference has been directed by the Comptroller to Specification 893,555.