Patent GB-937665-A (GB)
Title: Apparatus for performing conversions between analogue and digital signals
Inventor: AMDAHL GENE MYRON
IPC: H03M1/00
Filed: 1959-12-18
Abstract: 937,665. Analogue-to-digital and digital-to-analogue converters. THOMPSON RAMO WOOLDRIDGE Inc. Dec. 18, 1959, No. 43169/59. Class 40 (1). Apparatus for performing analogue - to - digital or digital - to - analogue conversions includes a summing amplifier adapted to provide an analogue signal proportional to the sum of predetermined proportions of two potentials supplied thereto, one being deter. mined by digital signals and the other being provided from the last preceding summing operation performed by the amplifier by way of transfer and storage means. Several different types of apparatus are described, in each of which the storage means are two series- or parallel - connected capacitors. Fig. 4 shows one embodiment of an analogueto-digital converter employmg series-connected capacitors S1, S2 and an amplifier CA1 having a gain of two and sum. ming the inputs from G2 and S1 in the proportions 1 : 2. Such apparatus requires two distinct phases of operation for each serial binary output digit produced. As an illustrative example of operation, an analogue output of 13 is entered through gate Mg, combined in the proportions 2 : 1 with a reference voltage Est of - 16 gated in by test digit Dt to produce an output of + 10, this being compared at Oc with a reference voltage zero to generate a 1 output digit during the second phase of the first digit cycle. This 1 output digit gates the - 16 reference voltage through G2 and the amplifier output of + 10 is stored in S2 by opening gate T2 at this time. In the first phase of the second cycle the + 10 stored on S2 is transferred to S1 and to the combining circuit, test digit Dt again supplying the - 16 reference voltage to one input of Ca1 which now produces an output of +4. The comparator output in the second phase is again 1 so that +4 is stored in S2. The output of Ca1 in the first phase of the third cycle is now - 8 so that the comparator output is O in the second phase of this cycle and the voltage on S1 (+4) is doubled and stored in S2 as + 8. In the final cycle the output of Ca1 is zero, the final digit 1 being produced by Oc and zero being stored in S2. The converter shown in Fig. 7 requires only five single-phase cycles to produce a four-digit output. Here the amplifier has a gain of 2 and adds the two inputs in equal proportions. An analogue input of 13 is thus doubled and +26 is stored in S during the first cycle. In the second cycle the +26 from S1 is compared with + 16 Ref. in Oc, the 1 output digit gating Est (- 16) through G so that +20 is stored in S2. In the third cycle a similar process occurs, 2 (20 - 16) = +8 being stored in S 1. During the fourth cycle a O is obtained from Oc and thus + 16 is stored in S2. The final cycle is similar to the second and third, zero being stored in S1. Other converters, Figs. 10, 12 (not shown), operate in a similar manner to that of Fig. 7. One embodiment of digital-to-analogue converter is shown in Fig. 13. For a binary 13 input i.e. 1101 (most significant digit first) the first 1 gates in +1 reference through G, this being stored in S2. The second 1 digit is added to twice the voltage transferred from S2 to S1 giving +3 in S2. Since the third digit is O the + 3 from S 1 is doubled and stored as + 6 in S2. The final 1 is then added to 2x 6 giving 13. In the embodiment of Fig. 14 the digits arrive in ascending order of significance, the amplifier summing half the voltage from M (which includes the parallel-connected capacitor S1, S2) with the voltage gated from G(Est= + 8). Thus in the four digit-cycles +8 8 is stored in S1, ¢ x 8 + +4 is stored in S2, ¢x4+8 = 10 is stored in S1 and x 10+8 = 13 is stored in S2.