baber/WOPTO huggingface dataset:
Patent JP-H05136216-A (JP)
Title: Semiconductor mounting device
Inventor: SEGAWA MASAO
IPC: H01L21/60
Filed: 1991-11-13
Abstract: PURPOSE:To enable the flip chip mounting of a semiconductor chip with simple process by connecting the electrode of a wiring board with a bare chip, by thermocompression bonding, at the bonding temperature in the solid phase region not more than the fusing point of a solder bump. CONSTITUTION:In a flip chip mounting where a semiconductor chip 21 is mounted directly on a wiring board 26 through a bump 24, a solder wire, which does not have eutectic composition, is used as bump formation method. And, a solder ball bump 24 is made directly on the electrode pad of the semiconductor chip 21. The flip chip mounting by thermocompression is performed at the bonding temperature not more than the fusing point of the solder ball bump 24 to the wiring board 26 where a conductor electrode 25 is made. Hereby, the flip chip mounting of the semiconductor chip becomes possible by simple process.
Patent JP-S63149919-A (JP)
Title: Memory control circuit for pcm equipment
Inventor: ISHIDA MASAYUKI
IPC: H03M13/00
Filed: 1986-12-12
Abstract: PURPOSE:To obtain much decoding time by applying decoding simultaneously when a reproducing signal is being written and inhibiting the write of a reproduction signal to a memory area where the decoding is finished already through the result of comparison of an address comparison circuit. CONSTITUTION:A write address generating circuit 130 generating an address to write a reproducing signal, a decoding address generating circuit 13 to generate an address for decoding and an address comparison circuit 132 comparing two address outputted from the address generating circuit are provided. Then decoding is applied simultaneously while a reproducing signal is being written in a memory 121 and the address comparison circuit 132 decides whether or not the area is finished for the decoding of the write address inputted from the write address generating circuit 130 and in the case the area into which the decoding is finished, the write of the reproducing signal is inhibited. Thus, the time used for decoding is not limited for the period without the reproducing signal.
Patent JP-H08264009-A (JP)
Title: Reflection-type hybrid lamp assembly
Inventor: BURD DAVID M
IPC: F21S8/00
Filed: 1995-11-15
Abstract: PROBLEM TO BE SOLVED: To combine the advantages of fluorescent lamps with versatility inherent in halogen incandescent light sources so as to provide an effective illumination by providing dim light, center-focused light, and a frigid weather illumination effect. SOLUTION: A plurality of small fluorescent annular lamps 3 are arranged in complementary concentric fashion about a miniature tungsten-halogen light source 7. All of the fluorescent lamps 3 are combined with appropriate reflecting portions 2, 26 in a single assembly with controls 5 therein. The fluorescent annular lamps 3 are triangular or igloo-shaped 3 in cross section and the reflecting portions 2, 26 reflect light from the base 11 of the lamps 3. This arrangement allows concentration of light for aesthetic or functional purpose and provides an effective illumination.
Patent JP-S62158706-A (JP)
Title: Optical resin composition
Inventor: KAWAI HIROMASA
IPC: C08K5/04
Filed: 1985-12-30
Abstract: PURPOSE:To form a resin composition suitable for molding optical elements excellent in low optical dispersion and heat resistance, by polymerizing a cycloaliphatic ester of methacrylic acid or a mixture thereof with a copolymerizable monomer in the presence of a specified thermal oxidation preventing compound. CONSTITUTION:This composition is formed by polymerizing a monomer (A) in the presence of a thermal oxidation preventing compound (B). (A) is a monomer comprising 100-10wt% methacrylic ester having a 5-22 C cycloaliphatic hydrocarbon group as its alcohol-derived moiety and 0-90wt% monomer copolymerizable therewith and (B) is a compound having a group of formula I (wherein R<1>-R<6>, which are independent of each other, are 1 C or higher alkyl groups) and/or a compound of formula II (wherein R<7>-R<12>, which are independent of each other, are 1 C or higher alkyl groups). Examples of the monomers copolymerizable with the methacrylic esters include aromatic vinyl compounds, vinyl cyanides, unsaturated dibasic acids or derivatives thereof and unsaturated fatty acids or derivatives thereof.
Patent JP-H04170222-A (JP)
Title: Ecl logic circuit
Inventor: HAMADA MITSUHIRO
IPC: H03K19/08
Filed: 1990-11-02
Abstract: PURPOSE:To reduce power consumption in latching data by employing a MOS transistor(TR) controlled by a signal from an external terminal as the constant current source of a differential amplifier comprising bipolar TRs. CONSTITUTION:When a high ECL level is applied to an input terminal VIN and the level is set higher by nearly 400mV. In such a case, a bipolar TR Q1 is turned on and the current flowing to the bipolar TR Q1 is equal to the sum of currents through nMOS TRs M3, M4 and flows to the collector of the bipolar TR Q1 through diodes D1, D2 from a power supply VCC. Then the level of (VCC-2 VF) appears at an output terminal VIN, where VF is a forward voltage of one of the diodes D1-D4. On the other hand, a bipolar TR Q2 is turned off and the level of an output terminal V'IN is boosted to the VCC. The boosting is implemented by a pMOS TR M2.
Patent JP-H04170479-A (JP)
Title: Ink for ink jet recording
Inventor: ONISHI HIROYUKI
IPC: C09D11/328
Filed: 1990-11-02
Abstract: PURPOSE:To obtain the title ink excellent in rapid driability and fixability and can give a highly dense clear recording excellent in water and light resistances by preparing a specified ink containing water, a dye and a high- boiling, lowly volatile water-soluble organic solvent and having specified properties. CONSTITUTION:An ink to be used for an ink jet printer in which a character or an image is recorded with a liquid ink, wherein water mad a dye (e.g. C.I. Direct Black 19) and a high-boiling, lowly volatile water-soluble organic solvent (e.g. glycerol and N-methyl-2-pyrrolidone) are contained, the solid component left after the water is perfectly evaporated can keep a state in which it is perfectly dissolved in the solvent, and the viscosity at this time is 30mPa.s at 20 deg.C.
Patent JP-2001118557-A (JP)
Title: Cylindrical alkaline battery
Inventor: OKAYAMA TEIJI
IPC: H01M2/12
Filed: 1999-10-20
Abstract: PROBLEM TO BE SOLVED: To provide a cylindrical alkaline battery for gently exhausting hydrogen gas, oxygen gas and alkaline electrolyte, and protecting alkaline electrolyte from dispersing, even when a safety valve is operated. SOLUTION: An cylindrical alkaline battery comprises a positive electrode mixture filled in a cylindrical metal can, having a bottom equipped with a positive electrode, a negative electrode current collecting rod inserted in the gel-like negative electrode filled in the vacancy part of the positive electrode mixture, a metal plate arranged between double ring-like parts of a double ring-like insulating gasket arranged in an outside of a protrusion part of the negative electrode current collecting rod and the inner side of an upper part of the metal case and a cap-shaped metal sealing plate, having negative electrode close to a leading part of the current collecting rod.  Because a gas exhaust hole is provided in the cap-shaped metal sealing plate and a cutout filter having a gas transmission property is provided in the inside of the cap- shaped metal sealing plate, exhausting of hydrogen gas and alkaline electrolyte become gentle and spattering of alkaline electrolyte is restrained.
Patent JP-H05243029-A (JP)
Title: Low-loss oxide magnetic material
Inventor: SAITO AKIRA
IPC: H01F1/34
Filed: 1991-10-17
Abstract: PURPOSE:To furnish a magnetic material for a high frequency which enables reduction of an eddy-current loss, in particular, and has an excellent magnetic characteristic, by making porosity high in addition to formation of an intergranular layer of high resistivity, in MnZn ferrite. CONSTITUTION:A low-loss oxide magnetic material which has a composition containing CaO of 0.01 to 0.2wt.% and SiO2 of 0.01 to 0.05wt.% for a fundamental composition constituted of Fe2O3 of 52.5 to 54.5mol% MnO of 34 to 37.5mol% and ZnO of 9 to 12.5mol% in conversion into oxide and of which the porosity after sintering is 8 to 13%.
Patent JP-H02143722-A (JP)
Title: Wireless communication equipment
Inventor: MURAMATSU TAKESHI
IPC: H04B7/26
Filed: 1988-11-25
Abstract: PURPOSE:To save power of a wireless communication equipment by decreasing the ratio of a feeding time when the frequency of communication is less. CONSTITUTION:As a discriminating means when the communication frequency is less and much, a sensor section 6 detects a physical quantity and outputs an ON/OFF signal through the comparison with a threshold level. A power supply control section 5 varies the feeding rate of a power supply fed interruptingly to a reception section 1 at the standby of reception depending on the ON/OFF signal from a sensor section 6 by changing the feeding time and the feeding stop time. Thus, the power consumption of the reception section 1 consumed at the reception standby state is lowered as required. Thus, the power of the wireless communication equipment is saved.
Patent JP-H10144942-A (JP)
Title: Amorphous semiconductor solar cell
Inventor: TAKEUCHI YOSHIAKI
IPC: H01L31/04
Filed: 1996-11-11
Abstract: PROBLEM TO BE SOLVED: To improve the junction state of the interface between a p-type amorphous semiconductor layer and a transparent conductive film, made of zinc oxide and to improve various kinds of characteristics. SOLUTION: A first transparent conductive film 11 made of tin oxide is formed on a glass substrate 10. A second transparent conductive film 12 made of zinc oxide is formed by 10nm thickness on the first transparent conductive film 11. Then, an extremely thin-film layer 13 made of III-group element is formed on the second transparent conductive film 12. A p-type a-SiC layer 14 is formed on the extremely thin-film layer 13. An i-type a-Si layer 15 is formed on the p-type a-SiC layer 14. Then, an n-type a-Si layer 16 is formed on the i-type a-Si layer 15. A rear surface electrode 17 is formed on the n-type a-Si layer 16. A protection film 18 made of resin is formed on the rear surface electrode 17.
Patent JP-H06148012-A (JP)
Title: Manufacture of oscillation transducer
Inventor: KISHI TADASHI
IPC: H01L29/84
Filed: 1992-11-09
Abstract: PURPOSE:To provide a manufacturing method allowing formation of an oscillation beam through reduced number of steps and formation of a protrusion for preventing adhesion effectively. CONSTITUTION:A dielectric layer 2 is formed on the surface of a silicon substrate 1 and a groove 3 is made in the dielectric layer 2 by means of an ion beam generated from a focus ion beam system. A polysilicon layer 4 is formed on the silicon substrate 1 including the groove 3 and then subjected to heating for imparting tension thus forming an oscillation beam of the polysilicon layer 4. A dielectric layer 5 is then formed on the substrate including the polysilicon layer 4 and a resist is formed on the dielectric layer 5. The dielectric layer 5 is then removed except a part slightly wider than the oscillation beam. Subsequently, resist is removed to form a dielectric layer 7 on the substrate 1 and a groove 3a is made in the surface of the dielectric layer 5 by means of an ion beam generated from a focus ion beam system. Polysilicon 8 is formed on 1 the substrate including the groove and eventually removed except a part slightly wider than the dielectric layer 5. The dielectric layers 2, 5 are then removed to form a void 10. Thereafter, polysilicon 8a is formed on the surfaces of the substrate 1 and the polysilicon 8 and the gap is closed to form a shell 8.
Patent JP-S62157514-A (JP)
Title: Apparatus for measuring displacement quantity of small caliber pipe embedding and propelling machine
Inventor: AKIBA TOSHIYASU
IPC: G01C15/00
Filed: 1985-12-28
Abstract: PURPOSE:To make is possible to measure a bend with high accuracy even in propelling over a long distance of 100-120nm, by arranging a translucent target scale plate to the hollow part in a leading pipe and allowing laser beam to be incident to the target scale plate form the laser oscillator provided behind the main body of a pipe propelling and embedding machine. CONSTITUTION:When the laser beam 3 oscillated by a laser oscillator 4 is incident on a translucent target scale plate 2, the incident position of said laser beam 3 is sharply projected to the backside of the target scale plate 2 as a laser spot and imagewise picked up by the TV camera arranged to the backside of the target scale plate 2. Because the TV camera picks up the laser spot projected to the target scale plate 2 at close range, the image of said laser spot is sharp and accurate and there is almost no mixing of disturbance. Further, because the laser beam 3 is straightly incident on the target scale plate 2 so far as a distance is 100-200m because of the non-diffusivity and straight advancement thereof, a bend can be measured with high accuracy in propelling over a long distance of about 100-120m.
Patent JP-H01140739-A (JP)
Title: Wafer centering and positioning apparatus of semiconductor wafer transfer equipment
Inventor: NARUSE SHIRO
IPC: H01L21/68
Filed: 1987-11-27
Abstract: PURPOSE:To hold a wafer in a correct centering position by a structure wherein centering pins are pulled to the peripheral edges of the wafer, the wafer is shifted to the centering position on a wafer-holding tool and the wafer is sucked in this position and is held again on the wafer-holding tool. CONSTITUTION:This apparatus is composed of the following: a guide base 10 which is arranged on a shifting locus of a wafer-holding tool 74; two or more centering pins 11 which protrude upward from a base face in dispersed positions so as to be symmetric with respect to a point with reference to the center of the guide base 10 and which are guided and supported to be movable in a radius direction of the guide base; a driving part 12 which shifts the individual centering pins 11 by an equal amount simultaneously in the radius direction. Accordingly, the wafer-holding tool 74 is shifted to the central position of the guide base 10 while a wafer 2 is being transferred; and while a suction operation of the wafer 2 is once released, the centering pins 11 are pulled to the peripheral edges of the wafer 2 and the wafer 2 is shifted to a corrected centering position of the wafer-holding tool 74; the wafer 2 is sucked in this position and can be held again.
Patent JP-H10144414-A (JP)
Title: Connector
Inventor: NAKADA HIROYUKI
IPC: H01R24/00
Filed: 1996-11-11
Abstract: PROBLEM TO BE SOLVED: To prevent a connector housing from being deformed by elastic restoration force of terminal metal fittings developed when it is fitted to a multi-fuse. SOLUTION: In a lengthwise central position of an external wall 13 of a connector housing 11, a bolt 35 is fixed to a circuit board providing the bolt 35 along an outer side surface thereof. In a state of the connector housing 11 as viewed from above, curved deformation to the outside of the external wall 13 is prevented by the bolt 35. In the lengthwise central position of the external wall 13, since a function of reinforcing material is displayed by the bolt 35, deflection to the outside in a state as viewed in the lengthwise direction of the external wall 13 is also prevented.
Patent JP-H07154168-A (JP)
Title: Buffer circuit
Inventor: NAKAGAWARA TOMOMASA
IPC: H03F3/34
Filed: 1993-11-30
Abstract: PURPOSE:To obtain the circuit suitable for circuit integration with low current consumption by connecting bases of a 2nd transistor(TR) pair to collectors and obtaining an output from emitters for the impedance conversion. CONSTITUTION:The circuit is made up of 1st TR pair 11 comprising TRs Q1, Q2 whose bases receive an input and a 2nd TR pair 14 comprising TRs Q3, Q4 whose collectors are connected to emitters of the TR pair 11 and whose bases and collectors are mutually connected. Then an output is obtained from emitters of the 2nd TR pair 14. Since the TR pair 14 forms positive feedback connection, an emitter differentiation resistance re indicates a negative resistance, that is, -re. Since an output impedance Zo is a combined impedance between the emitter differentiation resistance re of the TR pair 11 and an emitter differentiation resistance -re of the TR pair 14, the output impedance Zo is zero. Thus, ideal impedance conversion is conducted for the buffer circuit.
Patent JP-S62157400-A (JP)
Title: Semiconductor memory circuit
Inventor: OKAWA TAKASHI
IPC: H01L27/102
Filed: 1985-12-27
Abstract: PURPOSE:To correctly and easily decide the leakage between cells by providing a circuit to set a non-selective bit line to a low level. CONSTITUTION:When the input of a decoder circuit 3 is wholly made into a high level and a bit line 10 is selected, transistors TRs23 and 24 are turned off and a current distributor 4 comes to be ON-condition. On the other hand, since the input of at least either of the inputs of a decoder circuit 1 is a low level, TRs19 and 20 are turned on and a current distributor 2 comes to be the OFF-condition. Consequently, by a voltage for detecting leakage impressed to an output terminal, the leakage current is conducted through distributor 4   diode at the upper side of cell   inter-cell leakage resistance diode at the upper side of cell 7   diode 22   TR20   earth. By such a constitution, since the leakage electric current value when the leakage is between cells comparatively largely appears, the leakage between the cells can be decided correctly and easily.
Patent JP-H04171819-A (JP)
Title: Formation of silicon thin film
Inventor: NAKAMURA MASAAKI
IPC: H01L21/3063
Filed: 1990-11-05
Abstract: PURPOSE:To achieve equal etching accuracy with the etching accuracy achieved when etching is performed with an etching liquid maintained at a low temperature and, at the same time, to remarkably reduce the etching time by performing etching by lowering the temperature of the etching liquid before an N-type conductive layer is exposed. CONSTITUTION:In the first place, electrochemical etching is performed on a silicon substrate 21 in an etching liquid 23 and the substrate 21 and an negative electrode 22 are taken out from the liquid 23 before an N-layer is exposed. Then the substrate 21 and electrode 22 are dipped in another etching liquid 27 and successively etched in the liquid 27. Thus, the electrochemical etching is executed in two stages in the etching liquids which are maintained at 90 deg.C and 60 deg.C, respectively.
Patent JP-H10119919-A (JP)
Title: Aseptic egg packaging device
Inventor: TOMOSUE MASAO
IPC: B65B55/10
Filed: 1996-10-22
Abstract: PROBLEM TO BE SOLVED: To automatically package eggs under an aseptic state by utilizing a generally known processing device. SOLUTION: In a sterilizing box 1 where an egg washing machine 9, a dryer 10, and an automatic packer 19 are connected in order, ozone generators 24a, 24b are provided. Eggs which are fed from an egg feeding conveyor 18, are automatically washed, dried and packaged while being sterilized by ozone generated from the ozone generators 24a, 24b, and then, carried out to the outside of the sterilizing box as products from a carrying out conveyor 23.
Patent JP-H08161371-A (JP)
Title: Numerical simulation device and actively intelligent interactive cad system using the same
Inventor: KA KIRIN
IPC: G06F19/00
Filed: 1994-12-02
Abstract: PURPOSE: To enable design supporting with high reliability by efficiently supporting design which satisfies a performance value a designer expects. CONSTITUTION: A system is at least provided with a setting input part 4 which inputs a non-object model parameter and an object model variable which are respectively selected from the respective model parameters and the respective model variables in numerical experiment modeling and whose values are set and an object model parameter value calculating part 5 which obtains the value of the respective model variables (non-object model variable) excluding the object model variable from a nonlinear simultaneous equations for numerical experiment modeling and obtains the value of the respective model parameters (object model parameter) excluding the non-object model parameter with the non-object model variable value and the objectmodel variable value as the inconsistant resolusion of the nonlinear simultaneous equations.
Patent JP-H10190420-A (JP)
Title: Differential comparator circuit provided with improve common mode range
Inventor: FISHER JONATHAN HERMAN
IPC: H03K19/20
Filed: 1997-10-31
Abstract: PROBLEM TO BE SOLVED: To provide a large common mode range by operating a first comparator when a first input signal and a second input signal are higher than a prescribed level, operating a second comparator when they are lower and selecting the output of the operated comparator. SOLUTION: The first comparator 301 uses an (n) channel input device and the second comparator 302 uses a (p) channel input device. A circuit composed of buffers 303 and 304, a NAND 305 and an INV 306 generates selection signals in response to the size of a signal level in comparator input, controls a selection circuit composed of M1, M2, M3 and M4, selects the output of the first comparator or the second comparator and outputs comparator output Z. The selection signals are supplied to the comparators 301 and 302 also as EN signals and the power of the comparator on a non-selected side is brought down. Thus, a differential comparator capable of performing coping at the optional part of a wide rail-to-rail range respectively operated over the different ranges of the signal level is realized.
Patent JP-H03160837-A (JP)
Title: Serial loop transfer data monitor and control system
Inventor: MASUDA KINICHIRO
IPC: H04L12/42
Filed: 1989-11-20
Abstract: PURPOSE:To eliminate the need for waiting of synchronization for data transmission and reception by the software and to attain transmission and reception of lots of data by providing a transfer equipment and a display device between a data storage section and an SL loop center section. CONSTITUTION:A transfer equipment 9 transfers a data for each frame between a data storage section 6 and an SL loop center section 2, and a display device 10 displays a data transfer state in the equipment 9. Then a monitor data for each frame from the center section 2 in the monitor mode is stored in any of the storage sections 6 and the display device 10 displays the number of the storage section 6 during transfer and a CPU 5 processes a data in the storage section 6 whose number is younger by one than the displayed number. Moreover, the control data set to the storage section 6 from the CPU 5 is transferred to the center section 2 via the equipment 9 in the control mode and when a new control data is generated, the data of the storage section 6 is updated in response to the data number of the display device 10. Thus, the wait of synchronization of data transmission and reception by the software is not required and lots of data are processed.