Patent GB-867413-A (GB)
Title: Semiconductor devices
IPC: H01L29/00
Filed: 1957-06-04
Abstract: 867,413. Junction transistors. RADIO CORPORATION OF AMERICA. June 4, 1957 [June 18, 1956], No. 17784/57. Class 37. In a junction transistor comprising two zones of opposite conductivity type separated by a PN junction, the first zone consists of a semiconductor compound containing a conductivity type determining impurity and the second zone comprises a compound of said impurity and one of the components of the compound constituting the first zone. Such a transistor may be fabricated from a 0.3 mm. thick wafer of N- type indium phosphide by the following steps. The wafer is heated for 3 minutes at 800 C. in the vapour of the acceptor impurity cadmium. This produces a layer 42 (Fig. 1B) of cadmium doped P-type indium phosphide. beneath a surface layer 44 of N-type cadmium phosphide containing indium as donor impurity. One face of the treated wafer is masked with a layer of lacquer or polystyrene and the wafer etched in equal volumes of concentrated nitric and hydrochloric acids to remove the cadmium phosphide and P-type indium phosphide layers from the unmasked parts of the wafer. After removal of the masking layer a a cadmium blob 46, provided with a connecting-wire 47, is alloyed to the cadmium phosphide layer to form an emitter connection. The wafer is then out or ground at an angle (Fig. 1F) to expose a greater area of the base layer 42, to which an indium base connection is then fused. Finally an indium coated tab 50 of copper, nickel or alloys thereof is alloyed to the lower face of the wafer to form a collector connection. In an alternative embodiment after alloying the cadmium blob to the treated wafer the blob is masked and the wafer again etched for a sufficient time to remove only the surrounding cadmium phosphide layer. An indium base connection is then made directly to the exposed P-type indium phosphide face of the wafer and a collector con-. nection added as before. The small area emitter produced by this latter method makes the device particularly suitable for highfrequency applications. The above-described transistors have high emitter efficiencies because the energy gap width in the emitter zone of cadmium phosphide is greater than that of the indium phosphide base zone. The method of fabrication also results in an impurity gradient across the base zone which reduces the minority carrier transit time as also does the close spacing achieved between the emitter and collector junctions. Transistors formed by methods similar to the above and having the following zone compositions are also suggested. An emitter of cadmium arsenide, base of cadmium doped gallium arsenide, and collector of N-type gallium arsenide. A zinc phosphide emitter, zinc-doped indium phosphide base and N-type indium phosphide collector. An emitter of gallium telluride with a tellurium doped gallium arsenide base and P-type gallium arsenide collector. An emitter of indium selenide, base of selenium doped indium phosphide and collector of P-type indium phosphide, and the combination of an indium sulphide emitter with a sulphur doped indium phosphide base and P- type indium phosphide collector.