Patent FR-2845180-A1 (FR)
Title: CMOS logic cell characterizing method for accelerating simulation of temporal dependence of delays effect in design of CMOS logic cells
Inventor: POIROUX THIERRY
IPC: G06F17/50
Filed: 2002-09-27
Abstract: The method comprises the modelling of a CMOS logic cell and the phase of determining the internal potentials of the cell based on a functional simulation of the modelled cell by utilizing a simulation signal (ST) which is a periodic binary signal. The determining phase includes the injection of a charge into the floating substrate (B) of each transistor of the cell, where the charge is proportional to the variation of internal potential of the transistor determined in the course of a predetermined temporal interval (TC) of the simulation signal preceding the instant of injection and exempt of injection, in a manner to accelerate the charging or discharging of the floating substrate (B) of the transistor.  The injection current corresponds to the injected charge so that after the injection the variation of internal potential (Vb) of the transistor attains a value n times the measured variation of internal potential. The value of n is determined on the basis of measuring the variation of internal potential in the course of a cycle of the simulation signal and an estimated amplitude of the variation of the internal potential of the transistor between its states of static equilibrium (DC) and dynamic equilibrium (AC, steady state). The value of a coefficient of proportionality (A) is determined on the basis of the measuring of the variation of the internal potential and the variation of charge of the transistor in the course of a cycle of the simulation signal and the duration of injection. The simulation signal (ST) comprises in each period a transition separating two levels, corresponding to 0 and 1, and the instant of injection is situated on a level and at a distance from the transition. The duration of current injection is greater than the temporal step of functional simulation and lesser than the duration of a level. The two instants of consecutive injection are separated by a duration equal to two periods of the simulation signal, or by one period in a variant of the method, and the temporal interval (TC) has a duration equal to a period of the simulation signal. The initial instant of the temporal interval precedes the instant of injection by 1.5 periods of the simulation signal, and the final instant precedes the injection instant by 0.5 period of the simulation signal, and the final instant precedes the instant of injection by 0.5 period fo the simulation signal. In the functional simulation each transistor is replaced by a model of the transistor associated with three modelled sources of voltage controlled by voltage, allowing to determine a target internal potential (Vbc) to be attained after injection, and a modelled current source delivering the injection current proportional to a difference between the target potential and the internal potential at the instant of inejction. The evolution of internal potentials of the transistors is determined from the state of static equilibrium to the state of dynamic equilibrium relative to rising and falling transitions of the simulation signal and for two initial values of the simulation signal, and the internal potentials corresponding to the best and worst cases of temporal delay are deduced. A device (claimed) for characterizing a CMOS logic cell implements the method (claimed) and comprises modelling means and processing means.