Patent GB-1340716-A (GB)
Title: Apparatus for interrogating the availability of a communication path to peripheral device
IPC: G06F13/40
Filed: 1971-06-28
Abstract: 1340716 Communication with peripherals BURROUGHS CORP 28 June 1971 [9 July 1970] 30102/71 Heading G4A A data processing system includes a central processor and a number of peripheral units connected to an associated peripheral control unit for communication via multiplexors with the central processor, the system being arranged in response to a central processor instruction and peripheral control unit and multiplexor channel availability signals to determine whether a communication path is available between a designated peripheral unit and the central processor. Periphral units, e.g. magnetic tape or disc stores, magnetic card readers, printers, paper tape units &c., may be connected via respective peripheral control units to a multiplexor or a group of identical peripherals may be connected to a multiplexor via an exchange and one or more shared peripheral control units. In operation the central processor fetches an "interrogate path instruction" which designates a particular peripheral unit and contains a field specifying a particular one or all of the multiplexors. Each multiplexor includes an address decoder which responds to the instruction multiplexor designating field, signals being returned to the processor indicating which multiplexors are responding. The peripheral unit designating field of the instruction is fed to decoder 34 which activates one or more of its outputs each of which corresponds to a peripheral control unit which is available to the designated peripheral. The decoder 34 may be a printed circuit card to enable it to be replaced when the configuration and/or types of peripherals in the system are changed. The decoder outputs are connected to respective AND gates 42-44 which also receive a "not busy" signal from their associated peripheral control units when the latter are available. The outputs of the gates 42-44 are combined by OR 45 and gated, at 88, to the central processor in response to control signals. One of these control signals is generated in response to the state of a communication control word generator. Each multiplexor includes a buffer 92 containing control words for each active communication channel, the number of storage locations being less than the total number of peripheral control units connected via the multiplexor. An associative memory 90 enables a particular location in buffer 92 to be assigned to a channel. If all available word locations are occupied gating control signal NBL inhibits gate 88 preventing passage of signals to the processor. The gate 88 is also inhibited if the multiplexor is in the process of initiating an I/O operation. The output of gate 88 is used to enable a gating system 108 which provides a multiplexor identifying signal to the processor. A control word is established in the processor indicating the designated peripheral, the designated multiplexor and whether a path is available. When an available path has been located a descriptor is fetched from main memory by the central processor indicating an area in main memory from or to which data is to be transferred to or from the selected peripheral. The Specification contains a description of how an I/O operation is performed, reference being made to Specification 1,191,560.