Patent GB-1433063-A (GB)
Title: Data transmission systems
IPC: H04L1/00
Filed: 1974-01-17
Abstract: 1433063 Digital transmission; error correction STANDARD TELEPHONES & CABLES Ltd 17 Jan 1974 02168/74 Heading H4P In an electrical data transmission system in which block coding is used and in which error detection is provided with error correction effected cycles, an error control receiver, Fig. 1, has an output (shown as SECOND OUTPUT) at which correctly received data blocks are delivered once regardless of the sequence in which these blocks are received and a further output (shown as NORMAL OUTPUT) to which correctly received data blocks are delivered in correct sequence even where this introduces delays due to retransmission cycles. The error control receiver includes a system similar to Specification 1,409,184 where units 7-12 operates gates G7-G10 in a known manner to provide error free blocks at normal output in a correct sequence. A correct parity check and an O.K. (correct reception signal) from parity check unit 10 and store 9 cause G7 to enable data bits to pass to the normal output, unless a retransmission cycle has been started on reception of a RQ (request for repetition of an incorrectly received data block) when control signals from the receiver retransmission control unit 12 disables G7 for those blocks to be disregarded. To cater for delay sensitive data where minimization of delay in transmission is required and the sequence of the data is not important the receiver timing distributor 7 enables gates G101 to pass sequence numbering bits to a sequence number shift register store unit 103. A second accept/ reject unit 101 compares whether the sequence numbers of the received block and of the block received N blocks earlier now at the output of the unit 103 are identical. If the numbers differ and if parity check has been signalled from unit 10 the unit 10 enables G102 which allows the data bits of the block to occur at the second output for the delay sensitive data. G103 also opens to transfer the number in unit 102 to unit 103. If either the parity does not check or the two sequence numbers applied to the comparator in 101 are the same neither G102 or G103 is opened and instead G104 is enabled causing the number at the output of unit 103 to be reinserted at its input. In a modification of the error control transmitter of the application referred to above, Fig. 2, when delay sensitive data is catered for a timing distributor unit 91 applies for each block transmitted, one pulse to a sequence counter unit 104 which at the appropriate time enables a gate 105 to insert the sequence number digit in the block. When a retransmission cycle commences unit 2 applies an extra pulse to sequence counter 104 so that the retransmitted block obtained from retransmission data store 3 and gate G1 bears the same sequence number as on the first occasion they were transmitted. In order to speed up transmission of the delay sensitive data during a retransmission cycle the delay sensitive signals may replace the "idle" blocks. An idle detector 110 detects if a data word at output end of the shift register retransmission data store unit 3 is an "idle" and if there is then an enable input is applied from detector 110 to G107. If a retransmission cycle is in progress unit 2 also applies an enabling input to G107 and provided a delay sensitive data word is awaiting transmission a replace idle request is also applied to G107. When these conditions coincide G107 applies enabling polarity to two Module 2 Adder/or Exclusive- OR units 107 and 108 which close gate G1 and open gate G3 so that the data bits of the block being transmitted are the new delay sensitive block from the data source instead of the idle from unit 3. Any signal inserted in place of an idle signal is repeated N blocks later, where N is the number of blocks in a retransmission cycle, due to the operation of AND gate G108, adder 108, adder 105, inverter 106 and G106 which invert the control inputs to units 107 and 108. This enables the data bits of the transmitted block to be drawn from the store in unit 3 instead of from the data source N blocks after its first transmission. The system may be applied to duplex data circuits and in order to regain synchronization and resume data transmission after loss of block synchronization without omission or duplication of blocks some additional block marking device is necessary which can consist of numbering in a cycle of typically NH such as disclosed in Specification 1,428,050.