Patent GB-769909-A (GB)
Title: Message comparator
IPC: G06F7/02
Filed: 1954-11-01
Abstract: 769,909. Comparing digital data. RADIO CORPORATION OF AMERICA. Nov. 1, 1954 [Nov. 27, 1953], No. 31493/54. Class 106(1). A digital data comparing device comprises first and second channels for conveying respectively terminating signals of first and second messages and character precedence signals produced by a comparator, these signals being utilized to produce, at a first or second output, an indication of the order of precedence of the messages. The device is adapted to compare either alphabetic messages or numeric data, a four-pole, double-throw switch 50 a ... d being set in either an " L " position or an " R " position according to whether the characters to be compared are to be justified to the left or to the right. Alphabetic characters, e.g. names to be arranged in a directory, are normally justified to the left, thus:- Woods, John A Woodson, John A while numeric characters are justified to the right:- 9123 21456 The signals representative of each of the two messages are produced sequentially, with the most significant character first in each case, from magnetic tapes and registered on two staticizers 12 and 14. A six-channel binary code is used to represent each character, with a seventh channel for checking purposes. A comparator 10 responds to inequality between two characters in the staticizers with a signal on either the line b > a or the line a > b. Also, coincidence gates 16 and 18 are arranged to respond to special characters placed between items and at the end of a message. When alphabetic messages are being dealt with the first inequality detected by the comparator 10 decides the order of precedence, and a signal passes along line b > a, for example, through a delay element 24, a gate 30, switch contacts 50a and 50c (in the " L " position), an " or " gate 46 and a switching gate 76 to the output A < B. If, however, no inequality is detected, then the arrival of the first item separation signal (e.g. after " Woods " in the alphabetic example given above) would be the deciding factor. This signal, if emitted by the gate 16, for example, would be transmitted via a delay element 24 to a gate 34 and thence to the " or " gate 46 and switching gate 76, as above. The gates 30 and 34, and also the symmetrically opposite ones 32, 36, are described as " but not " gates; each has two inputs and will give an output signal if stimulated at one input but not at the other. Such gates are usually termed " anticoincidence " gates. The cross connections cause secondary signals from the comparator 10 and recognition gates 16 and 18 to be blocked. The devices 40, 42, 76 and 78 are termed " switching gates " and perform the function of permitting an input signal to pass and provide an output only if in the proper one of two alternate conditions. They each comprise a flip-flop controlling a gate of the Rossi type. When numeric data are being dealt with, inequality between a pair of digits (e.g. the first in each of the numbers given above) would not necessarily indicate the correct result and would, in fact, require to be reversed if an item separation signal arrived to indicate that the number with the higher-value digit had a lesser number of digits. The switch 50 being set in position R in this case, an inequality signal from the comparator 10 would be directed through switch contacts 50a, for example, and switching gate 40 to a flip-flop 52. The same signal would close the opposite switching gate 42 and thus prevent any subsequent signal from the comparator from being registered on the flip-flop 54. A subsequent signal from one of the recognition gates (18, say) would pass through delay 24, " but not " gate 36, " or " gate 48, and switching gate 78 to the A > B output terminal 62, and also via buffer 80 and delay 24 would shunt both the gates 76 and 78 to prevent any further signals reaching the output. In order to provide an " equality " output signal, control signals indicative of the existence of input characters are fed through a " but not " gate 22 and " or " gate 26 to a counter 28 which can be set to respond after a predetermined number of characters have been examined. A signal will be transmitted to the output terminal A = B if the predetermined count is reached. If one item terminates in an " end of message " signal at the same time as an " item separation " signal from the other message, the recognition gates 16, 18 respond simultaneously and transmit through delay units 24 and gates 34, 36 a signal through an "and" gate 38 to the counter 28. On the other hand a response by the comparator 10 will cut off the input pulses to the counter 28 at the " but not " gate 22 and thus prevent the counter from reaching the desired total before the resetting stage. When a " start message " signal is recognized by the gates 68 or 70 the response signal resets both flip-flops 52, 54 and the counter 28. The subsequent arrival of a reset signal at a buffer 74 opens all the switching gates 40, 42, 76 and 78. Circuit details of the combination of " or " gate 20, " but not " gate 22, and delay unit 24 are also described.