Patent GB-1104094-A (GB)
Title: Improvements in or relating to echo sounders
Inventor: WILLIAMSON ROBERT LAWTON
IPC: G01S15/14
Filed: 1963-11-29
Abstract: 1,104,094. Echo-sounding. PLESSEY-UK Ltd. 25 Nov., 1964 [29 Nov., 1963], No. 47171/63. Heading H4D. In a pulse-echo depth-sounding system, the bottom echo is identified by a circuit which detects the strongest echo arising from each transmission. Echo signals received by a transducer 11 are fed through an amplifier 12, whose gain is increased during the sounding cycle to preferentially amplify deep echoes, to an amplitude gate 13. Gate 13 passes those signals exceeding a given threshold level to an amplifier and rectifier unit 14 and an inverting amplifier 15. The leading edge of an echo pulse from unit 14 trips a bi-stable circuit B1 to its " set " state and, after a time delay introduced by a network R1, C1, trips a bi-stable circuit B2 to its " set " state. The bi-stable circuits B1, B2 are then " reset from amplifier 15 by the trailing edge of the echo pulse. An output signal from circuit B2 in its " set " state is fed to a capacitor C2 in a diode-pump type integrator R2, D1, C2 and the voltage developed across C2 is used to raise the threshold level in gate 13. The arrangement is therefore such that gate 13 will pass an echo signal only if it is stronger than the preceding echo signal, and consequently the bottom echo will be the final echo passed by gate 13 in each sounding cycle. Capacitor C2 is discharged at the beginning of each sounding cycle. An " AND " gate 16 provides an output signal while circuit B1 is in its " set " state and circuit B2 is in its " reset " state i.e. the output signal comprises a pulse of fixed width equal to the delay period of network R1, C1. For a voltmeter depth read-out (Fig. 3), the output pulse from " AND " gate 16 opens a gate (18) connected to a ramp voltage generator (17). The output from gate (18) thus comprises pulses whose amplitude depends on the time of occurrence of the pulses from gate 16 and hence on the depth from which the echo pulses are produced. The output pulses from gate (18) feed a diode pump circuit (D2, C3) and the voltage across (C3) is sampled near the end of the sounding cycle by a peak-reading voltmeter circuit (R3, 20, 21) connected over a sampling gate (19) to capacitor (C3), voltmeter (21) being calibrated directly in depth. Capacitor (C3) is discharged at the beginning of each sounding cycle. For a digital depth read-out (Fig. 5) a binary counter (22) is reset to zero at the beginning of each sounding cycle by a reset pulse on a line (26), and then counts clock pulses, fed in on a line (27), during the sounding cycle. The current count is recorded on a register (23) whenever an echo pulse, from the " AND " gate 16, is present on a line (28), and the stored count is fed to a display register (24) when a pulse is applied to a line (29) at or near the end of the sounding cycle. The count on register (24) is converted to decimal form by diode decoding matrices (25) and fed to a digital display apparatus. The repetition frequency of the clock pulses fed to line (27) is determined by the depth range and units of measurement displayed.