Patent GB-1396585-A (GB)
Title: Noise reduction in receiving apparatus
IPC: H03G9/18
Filed: 1972-06-21
Abstract: 1396585 Radio receiving circuits; stereophonic radio receivers; automatic gain control PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 21 June 1972 [24 June 1971] 29034/72 Headings H3T H4L and H4R Apparatus for receiving modulated carrier signals comprises a tuning device, an amplifier, a detector, and a low frequency amplifier, and is characterized in that the low frequency amplifier includes a noise reduction circuit which attenuates signals having a frequency higher than a given cut-off frequency and an amplitude smaller than a given threshold value. The noise reduction circuit is provided with an input stage S, Fig. 1, having a first and second output, and a summing stage O having a first and second input. A first path 1 between the stages S, O includes a high-pass filter F 1 , an optional amplifier A and an automatic gain control stage B 1 , the gain of which changes when its input exceeds the given threshold value, and an optional attenuator B 2 . The stage B 1  includes a control device for adjusting the threshold value in dependence upon a control signal derived by rectifying the modulated carrier wave. In a first mode of operation of the arrangement, the second signal path 2 includes a low-pass filter F 2  with the same cut-off frequency as the highpass filter F 1 , and the automatic gain control circuit B 1  reduces the gain in the high frequency signal path 1 at low signal levels. In an alternative arrangement, the filter F 2  is of all-pass type and the arrangement is such that at full gain of the automatic gain control circuit B 1  the high-frequencies passed by the channels 1, 2 balance each other out in the combining circuit O. The gain of the automatic gain control circuit B 1  is then arranged to be reduced as the signal level increases. In a stereophonic receiver, each of the two channels following the stereo decoder SD, Fig. 4, is provided with a noise-reducing circuit R L , R R , respectively, of the type described above, followed by corresponding low-pass filters LF L , LF R . In addition the devices R L , R R  are preceded by low-pass filters F L , F R , respectively which block the stereo pilot frequency, which would otherwise influence the operation of the devices R L , R R . Switches are provided for change over to tape (R) or disc (Pu) recording. The control voltage applied to the devices R L , R R  over line P is correspondingly switched from a variable voltage derived via a rectifier from the I.F. amplifier MF 1  to a fixed voltage V R , V pu , as the case may be. A noise reduction circuit of the second of the types referred to above includes a transistor Tr 1  with equal collector and emitter resistors R 3 , R 4 , respectively; the two outputs are combined by means of resistor R 5  and capacitor C 2 , the arrangement comprising the all-pass filter. A second output is taken from the emitter of the transistor Tr 1  and is applied over a high-pass network comprising capacitor C 3  and resistor R 3 , and capacitor C 4  to the base of a transistor Tr 2 . The output from the collector of transistor Tr 2  is applied to a further high-pass network comprising capacitor C 5  and the input impedance of transistor Tr 3 , which is provided with collector to base feedback over resistor R 11 . The output from transistor Tr 3  is fed via a limiter comprising diodes D 1 , D 2 , described below, and emitter-follower Tr 4 , to an amplifier Tr 5  in whose output is arranged the gain controlling circuit. Gain controlling circuit.-The output from the collector of transistor Tr 5  is fed via capacitors C 10 , C 11  to diode rectifiers D 3 , D 4  respectively, the outputs from which are smoothed by capacitors C 12 , C 13  respectively and from the bias for diodes D 5 , D 6 , respectively. Diodes D 5 , D 6  comprise a variable shunt on the signal path from the emitter of transistor Tr 5 , via blocking capacitor C 14  and resistor R 27 . The two outputs from the all-pass filter and from transistor Tr 5  are combined in network O, resistor R 28  being adjustable to balance out the high frequencies at low signal levels. The initial bias on diodes D 3 , D 4  is variable, bias resistor R 25  being shunted by the source to drain path of a field-effect transistor Tr 7 , the gate of which is biased over resistor R 30  from the A.G.C. line of the receiver. Limiter.-The signal path between the collector of transistor Tr 3  and base of transistor Tr 4  is shunted by a limiter comprising diodes D 1 , D 2 , which are biased over resistors R 18 , R 19 ; the limiting level is made dependent on the signal level by means of field-effect transistor Tr 6 , the source to drain path of which shunts resistors R 16 , R 17  in the biasing network. The gate of transistor Tr 6  is biased from the receiver A.G.C. line via resistor R 31 .