Patent GB-894316-A (GB)
Title: Improvements in switching circuits
IPC: H03K3/012
Filed: 1959-04-29
Abstract: 894,316. Transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 29, 1959 [July 30, 1958], No. 14630/59. Class 40(6). Fig. 1 shows a bi-stable circuit comprising reciprocally coupled transistors 11, 12 output transistors 50, 51 a control transistor 30 and associated pulse forming networks Dl, D2, D3. If it is assumed that transistor 11 is conducting and 12 non-conducting when a negative pulse P1 is applied from transistor 30 transistor 11 is turned off and the current flow thus stopped is diverted through Zener diode 15 and networks D1 &c. Thus a rising step voltage is produced at the base of transistor 12 which conducts when pulse P1 ends and transistor 12 is cut off. The trigger circuit remains in this state until a second pulse P1 occurs when transistor 12 is cut off so that current flows through Zener diode 16 and network D2. A step waveform is thus produced so that transistor 11 is conditioned to conduct when pulse P1 ends, the trigger circuit is conditioned for the next pulse when the cycle is repeated. The pulses such as P1 are produced from a clock pulse train input applied to terminal 42 to the base of a transistor 30 which is normally cut off, the clock pulse for example Cl causes transistor 30 to conduct to initiate the leading edge of pulse P1 the clock pulse also initiates current flow through pulse forming networks D3 the delay time of which is short compared with network Dl or D2. The reflected pulse from network D3 reduces the magnitude of the clock pulse C1 so that transistor 30 is turned off and pulse P1 is terminated so that the pulse generated at the base of transistor 30 is short compared with the clock pulse, Fig. 2 (not shown). When pulse P1 turns off transistor 11 the base of transistor 12 is more negative than that of 11 so that 12 is conditioned to conduct in preference to 11. Output circuits for example comprising transistors 50, 51 as shown have the same conductivity as transistors 12 and 11  respectively. The modification shown in Fig. 3 comprises the binary pair of Fig. 1, output stages 50a, 51a and two input gates. Considering the first gate comprising transistors 61, 62, 63, 66 which is of the type described in Specification 872,251 and to which a pulse input is applied at terminal 65 and an inhibiting input at terminal 64. If both transistors 61, 63 are non-conducting then transistor 62 is conducting but if either transistor 61 or 63 are conducting then 62 is non-conducting. The pulse forming network D4 limits the duration of pulses applied to the trigger pair and the transistor 66 provides positive feedback over transistor 62 so as to give certainty to the operation of the gates. When a negative pulse is applied at 65 and if transistor 61 is non-conducting then transistor 62 is turned on, this causes the conductive one of the trigger pair transistors 11, 12 to be turned off. The second gate comprises transistors 61a, 62a, 63a, 66a and has an input at 71 which is also energized when an input at 64 is present. When the reset push button switch 78 is operated transistor 79 is turned on the base of 11 is made positive relative to the base of 12 so 11 is non-conductive and 12 conductive. A negative pulse P1a applied to the common emitters of transistors 11, 12 turns off 12 and 16a is turned on. The large and sudden increased current through pulse forming network D2 initiates a pulse which is applied as a negative pulse to the base of transistor 81 and thus to 1 1 which conditions it to turn on when pulse P1a ends. When 11 is turned on outputs are produced via transistors 50, 50a. When 11 is conductive and 12 non-conductive the pulse P1 applied causes current through transistor 11 which causes its collector to go positive and thus transistor 16a is cut off. Since there is no current through coupling 13 transistor 82 is conductive and maintains 12 in a non-conductive state. This causes 16a to conduct and current to flow in coupling 14 and this via 18a causes a negative pulse to be applied to the base of transistor 81 which acts as an emitter follower and keeps transistor 11 on, thus transistors 50, 50a also conduct. If a negative pulse Pla is applied from gate 1 to lead 40 both transistors 11 and 12 will be made non-conductive, 15a will thus conduct and a negative pulse is applied to transistor 82 and thus to transistor 12. At the end of pulse P1a transistor 12 conducts and 16a is cut off thus positive is applied to the transistor 81 and to transistor 11 to maintain it cut off.