Patent GB-1459501-A (GB)
Title: Digital data signal receiver
IPC: H04L27/01
Filed: 1974-01-08
Abstract: 1459501 Automatic adaptive equalizers; automatic phase control HYCOM Inc 8 Jan 1974 [18 Jan 1973 11 Oct 1973] 00762/74 Headings H4R and H3A In a receiver for the reception of modulated analogue data signals representative of digital data in which the digital data modulates two quadrature related carriers, the received signals are sampled and the sample values converted to digital form in an a to d converter, the digital signal is demodulated in a non-coherent digital demodulator 46, 48, Fig. 3, to provide demodulated inphase XI and quadrature XQ signals which are applied to a phase correction system 59, the phase corrected signals being detected and an error signal derived from the corrected and the detected signals to be used in the adjustment of the phase correction system. As described at the transmitter digital data at either 2400 bits/sec, or 4800 bits/sec. is randomized, and split into two channels, each of which is converted to two level, Œ1 or four level Œ1, Œ3, signals, which are shaped for partial response 1,1, signalling and respectively modulate quadrature related carriers of 1600 Hz for transmission. At the receiver, Fig. 3, the signals pass through access equipment 19 and analogue band pass filter 43 to an A to D converter where the signal is sampled and converted to binary form for further processing. The binary signals are multiplied in 46 and 48 with digital samples of respective quadrature related carriers of 1600 Hz to provide non-coherent demodulation of the received signals, non-coherent since the phase is not controlled, and the phase of the incoming signal may be subject to jitter. After passing through digital low pass filters 53, 55, to remove multiple frequency terms, the signals are applied to a conventional form of adaptive transversal equalizer 57. The output signals from the transversal equalizer 57 are applied to a phase correction network 59 where they are multiplied by sine and cosine values of a phase angle #<SP>1</SP> which is dependent on the phase error of the equalized signal, as determined by the error calculator 65. The resulting signals, substantially free of distortion and phase error are applied to detectors 61 and 63 in order to derive the detected values of the signals, i.e. that one of the possible analogue values which the signal should take, to which the equalized signal is closest. By a comparison of the input signal to, and the output signal from, the detectors 61 and 63 an error signal is derived and used to up-date the adjustment of the transversal equalizer 56, adjust the value of phase error fed to the phase correction network 59, and provide adjustment of the sampling time of of the input signal in the a to d converter 45. Error detector and phase corrector, Fig. 6.-The error signals EI and EQ are determined by comparison of the equalized and phase corrected signals YTj and YQj with the detected signals DIj and DQj after they have been multiplied by the up-dated nominal signal sample value #l 0 . The error signals EI and EQ are used in a conventional way to up-date the transversal equalizer multipliers, by correlation with the detected output signals, with correlation performed in both the inphase and quadrature channel for both in channel and cross channel interference, the same multipliers being used in the two channels, and the multiplier increment being varied in accordance with a comparison of the correlation coefficients determined for the inphase and quadrature channels, e.g. if both channels indicate a positive increment the increment applied is larger than if one channel indicates a positive increment and the other indicates no increment required. To determine an error signal for the phase corrector, 59, the error signals EI and EQ are multiplied by the signs of the signals at the inputs to the detectors, YI and YQ and a difference determined as EISign(YQ)-EQSign(YI). The value is applied to a gain control device 139 having a gain where DI and DQ are the values of the encoded data samples. The resulting phase error signal is applied via a filter 140, comprising a limiter path 141 and a variable gain limited integrator path 142, the gain of which determines the bandwidth of the phase correcting loop, to the read only memory 117 in the phase corrector 59 to provide correction for phase errors and phase jitter in the demodulator carrier generator 47, Fig. 3. Sampling time control system, Fig. 8.-By correlation of successive error signal polarity with the changes in data signal from sample to sample it is possible to determine the error in sampling time, i.e. if sampling occurs too early or too late. The result of the correlation is used to add or subtract pulses fed to a divider 185, which generates the sampling pulse for a to d converter 45, Fig. 1, by division of an h.f. generator 183, Fig. 8.