Patent GB-1475831-A (GB)
Title: Method and apparatus for processing semi-conductor integrated  circuit chips
IPC: H01L21/78
Filed: 1975-01-10
Abstract: 1475831 Processing semiconductor devices COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII HONEYWELL BULL 10 Jan 1975 1178/75 Heading H1K Integrated circuit chips are prepared from a wafer RS of monocrystalline silicon (Fig. 1) which is formed in known manner into plural rectangular integrated circuit elements MP aligned in rows L1, 2, 3 &c. and columns C1, 2, 3 &c., and is wax mounted on a glass support plate PS, to be subdivided by a diamond saw leaving discrete chips in their original positions. Preliminary testing enables faulty chips MP to be identified and marked. A transfer strip RT (Fig. 2) of flexible inextensible synthetic resin has regular lateral perforations PL for transit motion and equidistant central openings FC into each of which an integrated circuit chip is mountable. The plural radiating interface connections C1 formed e.g. by photoengraving a conductive film are carried on the strip, and the inner ends extend over the aperture while the outer ends are positioned in a standard square pattern. In apparatus (Fig. 3) the transfer strip RT is translated by friction drive of motor 35 energized by generator 36 from a spool 31 to spool 32 through feed device 30 so as to move progressively in steps equivalent to the spaces between openings FC. Wafer RS carried by plate PS on which the chips MP have been subdivided is held e.g. by suction on an electro-mechanically controlled lifting table 10 carried by super-imposed X and Y slide-plates 11, 12 along which it may be translated by servo motors 13, 14. A soldering tool 20 with an electric bit is movable in a vertical slideway 23 normal to the table of lifting support 70. Pulse sources and counters 15, 16 feed servomotors 13, 14 to move support 10 in the required senses by successive increments #X, #Y which are counted and which are equivalent to the distances between the columns and rows of the chips, while the soldering tool 20 is vertically displaceable by a servomotor (not shown) and energized by a generator 22 so that bit 21 is periodically lowered to a soldering position and heated. The strip RT is successively moved through steps equivalent to the intervals between openings, which are automatically positionally located at 40 aligned with a chip of the wafer on support 10. Selected perforations of the strip are used for positioning. The generators 36, 15, 16, 22 are coupled for sequential operation, and the soldering tool is so shaped that its projections coincide with the respective interface connections and contact bumps of the wafers; the latter being automatically deflected so that they are aligned. The lifting support of the table 10 is actuated and the soldering tool lowered and energized to solder the chip contacts to the interface connections; after which the support and tool are restored and the chip is detached for retention in the strip opening FC. Thereafter the strip is translated and the process repeated for the next non-faulty chip; until the strip is filled. The movements of the various operators are synchronized, and may be programmed to omit faulty chips. Thereafter the successive chips are attached to their final wiring bases by the outer ends of the interface connections. A flow sheet (Fig. 4 not shown) is included. U.S.A. Specifications 3,825,161 and 3,811,809 are referred to.