Patent GB-1317493-A (GB)
Title: Surface-controlled field effect semiconductor device
IPC: G11C11/39
Filed: 1970-12-18
Abstract: 1317493 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 18 Dec 1970 [13 Jan 1970] 60205/70 Heading H1K [Also in Division H3] A surface controlled (e.g. Si) FET comprises (Fig. 1a) a P-doped substrate 10 into which N + doped regions 11, 12 are diffused; separated by a channel. An insulant layer, e.g. of SiO 2  has openings for source and drain electrodes S, D and gate electrode metallizing 14, while a conductor 15 penetrating the insulant interconnects the metallization with the channel zone to tap off potential at a predetermined point of the channel for application to the gate, and the device is bi-stable between non-conductivity and conductivity. A short positive gate pulse drives the channel conductive, and the voltage drop has highest gradient at pinch-off zone Z; and application to the gate holds the device conductive after pulse termination; the position of the connection being dependant on the required function. In construction a hole is etched through the insulant layer before metallization to form the gate, and the conductor is deposited therein, or the insulant is rendered conductive at the required point by selective in-diffusion of CoO, FeO or NnO + Al 2 O 3 ; the resistance being determined by the composition and area of the diffusion. Alternatively, Co + SiO 2  or Cr + SiO 2  may be vaporized into an etched hole of the insulant. Plural such connections of differing conductivities may be provided. In application to a data storage cell such FETs are interconnected (Fig. 2a) with gate G 1  connected to drain D 2 ; source S 1  connected to gate G 2 ; drain D 1  connected to positive supply, and source S 2  to earth; while FET 1 has a low resistance connection W 1  adjacent the pinch-off zone and FET 2 has a high resistance connection adjacent or within the source region. Further addressing FET's 3, 4 of normal type have sources connected to circuit points A at G 2 S 1  and B at G 1 D 2 , and word line WL connected to gates G 3 , G 4 ; while bit lines B 1 , B 2  are connected to drains D 3 , D 4 . Initially on "1" write-in a positive pulse (Fig. 2b, not shown) is applied to WL and renders 3, 4 conductive to the simultaneous bit line pulses, for the duration of which G 1 , G 2  are driven positive. Since G 1  potential equals S 1  and G 2  exceeds S 2 , FET 2 conducts first, and at the end of the bit line pulse at A, G 2  is discharged through W 2 . FET 1 is initially non-conductive, due to potential at A, so that G 1  discharges more slowly, until the potential at A is in defect of the potential at B by a threshold, when FET 1 conducts, applies a potential to A and G 2  and holds FET 2 conductive, so that stable potential values appear at A, B. On "0" write-in, gates G 1 , G 2  of FET 1, FET 2 have zero potential for the duration of the word line pulse on WL. For readout, the word line potential is increased and the potential at A or B is scanned through one of the addressing FET's 3, 4 (Fig. 2 2 , not shown). A defined stabilizing potential is maintained on the gates of FET 1, FET 2 during non-conduction. In a modification, the gates of FET's 3, 4 are connected to separate word lines receiving coincident pulses during write-in and the potential on a selected word line is increased at readout. In an alternative application (Fig. 3b, not shown) a second connection from channel to gate having high resistance is provided adjacent the source zone, and is formed simultaneously with the first connection. In a data storage cell (Fig. 3c, not shown) source and drain of this first FET are connected respectively to earth and positive supply, while the gate is connected to source of a second addressing FET of normal type whose gate is connected to a word line and whose drain to a bit line. For "1" write in, the bit line is positively pulsed while the word line is energized, and the first FET conducts and remains conducting after completion of the writing pulse, since the channel potential at the pinch off zone is applied to the first connection and current flows through the channel towards the source. For "0" write in, the word line is energized and the gate of the first FET is connected to zero potential of the bit line for duration of the pulse on the word line, and the FET thus remains non-conductive and stable. For read out, the second FET is rendered conductive by an addressing pulse on the word line, and the gate potential of the first FET is scanned over the bit line into high resistance. In a modification thereof (Figs. 4a, 4b, not shown) a region without field effect influenced carriers is inserted in the channel by interrupting the gate electrode over the channel zone, so that the channel resisl tance is increased. The second gate-channeinterconnection is taken to the source region or to the adjacent channel zone.