Patent ES-346339-A1 (ES)
Title: Multi-stage delay line using capacitor charge transfer
IPC: G11C19/18
Filed: 1967-10-23
Abstract: Charge is transferred from one capacitor to another through the emitter-collector path of a transistor, the first capacitor being in series with a switching voltage between base and emitter and the second capacitor being joined between collector and base. The switching voltage causes current to flow through the transistor until one capacitor is charged to the value of the switching voltage, the other losing charge. If the collector-emitter current gain is unity and the capacitors are equal, one will lose voltage to the same extent as the other gains it. A plurality of such circuits (Fig. 1, not shown) can be joined in cascade to form a delay line for audio or video signals (Fig. 3), the signal input Vi being applied to the emitter of a preliminary transistor T 0 . The bases of the transistors in the odd and even stages are driven respectively in antiphase by the switching voltage S 0 . The final stage is terminated by a transistor T n+1 with collector strapped to its base. The frequency of the switching source should be at least twice the highest frequency in the signal. The delay per stage is half the period of the switching voltage, the output being taken from any one of the collectors, depending on the required delay. By using a three phase switching source (Fig. 6, not shown) this may be increased to two thirds the switching period, and similarly for higher numbers of phases. The total number of stages necessary to produce a given delay may be reduced by feeding the signal to three chains in parallel (Fig. 8, not shown) with a staggered arrangement of the three phases of the switching voltage. The outputs of the three chains are combined in parallel via isolating diodes. This arrangement may be formed as an integrated circuit and two such arrangements X 1 and X 2 (Fig. 12) can be joined in cascade, the isolating diodes being replaced by switched transistors T 1 -T 3 which correspond to the transistor T n+1 of Fig. 3. The switching sources S are timed so that at successive instants pulses appear at points 1 and A, 4 and B, 2 and A, 5 and B, 3 and A, 6 and B, and so on. Modifications.-Losses due to the emittercollector gain not being unity can be compensated by including in each stage an auxiliary capacitor C 1 and transistors TR1 and TR2 (Fig. 10). The charge transferred from the previous stage to C m is handed on to C 1 which is discharged by the pump circuit of TR2, D2 and C2 so that the charge handed on to C m+1 is amplified by the factor (1 + C 1 /C). The components C2 and D2 may be in parallel with C 1 and D 1 with elimination of transistor TR1 and reversal of connections of TR2 (Fig. 11, not shown). Components C 1 and D 1 may be eliminated if an auxiliary voltage source is provided for the transistor (Fig. 19, not shown). A circuit similar to Fig. 10, may be included in the input and output to the arrangement of Fig. 12 (Fig. 14, not shown) to reduce variations with frequency. The transistors T 1 -T 6 of Fig. 12 are then replaced by three cascade transistors in Darlington configuration. Filters.-In Fig. 15 the outputs of a plurality of odd stages are connected to a transistor T22 and the outputs of a further plurality of odd stages are connected to a transistor T23, the outputs of these transistors being combined at U. If the input signal Vi contains a component of particular frequency this will appear at the outputs of the stages with a particular phase relationship and the amplitude of the summed output at U will depend on the frequency. The switched capacitor-diode network of Fig. 15 may be replaced by coupled transistors and resistors (Fig. 17, not shown). A comb filter may be obtained by feeding back from the collector of T n in Fig. 3 to the emitter of T 0 .