Patent GB-1297852-A (GB)
IPC: H04B7/216
Filed: 1970-02-27
Abstract: 1297852 Radio signalling; multipled pulse code systems LICENTIA-PATENT-VERWALTUNGS GmbH 27 Feb 1970 [29 March 1969] 9503/70 Heading H4L In a telecommunication system including a satellite relay station, in which address signals are included in the transmitted signals and compared at the ground station receiver with a locally generated address signal, means are provided at the receiver for deriving the bit timing of the address signal and a correctly phased high frequency carrier from the incoming signal. The system is of the type in which each earth subscriber is allotted an address signal and each address has the same duration and the same number of bits, the binary coded information to be transmitted being so encoded that overy information bit to be transmitted to another station is represented by the address code of that station in normal or inverted form to represent binary 1 or 0. As shown in Fig. 1, input signals (a) Fig. 2, containing the address signal phase modulated on the carrier, are applied at E and supplied to a multiplier 1 together with the high frequency carrier which has been phase corrected. The resulting output (b) is fed via a bandpass filter 2 supplying output (c) to two multipliers 3, 4 receiving also inputs from delay circuits 20, 21 respectively, the two delays differing by the duration of one bit of the address signal and the two delay circuits being supplied with the address signal generated at 19. The outputs of the phase comparators are integrated at 7 and 8, respectively, over an address period, the output of 8 being supplied via a switch 13 and diode 14 to one input of a differential amplifier 12 and the output of 7 being supplied via a switch 9, delay 10 (to compensate for the difference between delays 20, 21) and diode 11 to the other input of amplifier 12. When the two inputs are equal there will be no output from the amplifier 12 and the bit timing is assumed to be correct. Otherwise the amplifier 12 supplies an error signal which is supplied via two threshold circuits 16, 17 eliminating small upwards or downwards deviations, to control the frequency of an oscillator 18 in turn controlling the address signal generator 19 (e.g. a shift register with feedback). At the start or finish of an address from the generator 19 a pulse is supplied by an AND gate 22 via delay circuits 23, 24 similar to circuits 20, 21, respectively, to reset the integrators 8, 7 and close the normally open switches 13, 9. A search generator 25 may be provided which supplies a predetermined voltage via a switch 26 or 27 to one of the threshold circuits 16, 17. For correcting the phase of the carrier wave the input signal at E, Fig. 4a, is supplied to a multiplier 28 receiving also the output of the address signal generator 19, Fig. 4b, via a one-bit delay 29 to bring it into the correct phase. The output, Fig. 4c, of the multiplier 28 is squared at 30 resulting in frequency-doubling, and supplied via a bandpass filter 31 to control the frequency of an oscillator VCO1 through a known phase locked loop circuit. The output frequency of oscillator VCO1 is divided by two at 33 and the resulting correctly phased carrier is supplied as previously described to the phase detector 1 and also to a multiplier 34 together with the address signal from delay 29. The resulting re-phased carrier modulated with the address signal is combined at 35 with the incoming signal E and integrated at 36 to derive the information signal for the appropriate subscriber via a threshold circuit 37. In a modification, Fig. 5 (not shown), the output of the differential amplifier controls a variable delay in the output of a bit frequency oscillator driving the address signal generator. In a modification of the carrier phase correction circuit, Fig. 6 (not shown), the output of the threshold circuit 37 is fed back as a third input to the multiplier receiving the input signal E, and the squaring circuit 38 and frequency divider 33 dispensed with.