Patent GB-1271127-A (GB)
Title: A digital electronic computer including an instruction buffer
IPC: G06F9/38
Filed: 1969-10-29
Abstract: 1,271,127. Digital computers; instruction buffer. HITACHI Ltd. 29 Oct., 1969 [31 Oct., 1968], No. 53070/69. Heading G4A. A digital electronic computer has an instruction buffer comprising two identical stores 1, 2, instructions read out from a memory unit being stored in a first store until the instructions are executed at a central processor, a buffer control unit 5 for designating said first store and for designating the second store for storing an instruction at the address of a branch read out or memory when the processor detects an instruction read out from the first store to be a conditional branch instruction, said buffer control means selecting said first or second store depending on whether the branch condition is fulfilled or not. Each store 1, 2 consists of four registers, each register having an instruction part for holding double words and an indicator part 3, 4 of two bits, and the buffer control 5 receives signals from the central processor. Normal operation.-Signals A1, A2 from control 5 designate one store 1, 2 for instruction storage. Address information from the program counter 6 is transmitted to the memory along with signal A1 set in portion 8. The least significant two bits 7 are sent to decoder 10 with signal A1 and designate a particular register within a store. Each register has two bits 3, 4; a reserve indicator which indicates that a request for an instruction to be stored has been sent and an occupation indicator which indicates whether an instruction is currently stored. The reserve indicator's are sent to gate 12, the reserve of the register selected by decoder 10 is checked, a request signal X is sent to the memory (if one has not already been sent) and the reserve is set to "1". Thus this register is reserved for the specific instruction. When the memory has acknowledged receipt of the request, the counter 6 steps up by one and the next register is reserved. The instruction is sent from the memory to register 14 together with the two bits and reserve indicator already sent to the memory which are stored in portion 15. These three bits are decoded in unit 16 and the instruction sent to its reserved register. The instructions are not necessarily brought to the buffer in order of request hence a plurality of memories of different access speeds can supply instructions without processor delay while the previous instructions are being processed and this continues until all the registers of the designated store hold an instruction. The instructions are sent to the processor using the program counter 17 and, as each register is vacated, its reserve and indicator bits are set appropriately. Conditional branch.-If an instruction which reaches the processor is found to be a conditional branch instruction, a signal BI is sent to buffer control 5, the information in counters 6, 17 is sent to auxiliary registers, and the address of the branch designated by the conditional branch instruction is set in counters 6, 17. The unit 5 reverses the signal A1 to designate the other store which has hitherto been unoccupied and the branch instructions are then directed to this store. If the processor finds the branch condition is fulfilled, signal B goes to unit 5, signal R1 resets the indicator portions of the initially designated storage unit and the branch instructions are sent to the central processor. If the branch condition is not fulfilled signal NB goes to unit 5, signal R2 resets the indicators of the store holding the branch instructions, the information is returned to the counters 6, 17, and the normal operation resumed. In an alternative, the counters 6, 17 are only evacuated when the branch condition is known to have been fulfilled. The various operations are controlled by clock pulses. The buffer control unit 5 comprises conventional logic circuits (Figs. 2 and 3, not shown). The indication of a particular register can be modified (Fig. 4, not shown). In another modification (Fig. 5, not shown) all the instructions of a small programme loop can be stored in both stores 1, 2 by modifying the buffer control unit 5.