Patent GB-1205470-A (GB)
Title: Improvements to electric scanners
IPC: H04Q3/545
Filed: 1968-12-05
Abstract: 1,205,470. Telephone exchange apparatus. INTERNATIONAL STANDARD ELECTRIC CORP. 5 Dec., 1968 [7 Dec., 1967], No. 57767/68. Heading H4K. A scanning system comprises contacts indicating the states of engagement of both sides of exchange junctors and arranged as crosspoints of a matrix. Current supplied to a column wire of the matrix in accordance with address data allowing the rows of the matrix to exhibit the states of the group of junctor contacts appearing in the column, the rows of the matrix being selectively gated one section at a time in accordance with address data to provide output indicative of the states of a section of the junctor group, a column of the matrix continuing to be energized after a section of its associated group has been read, the identity of the energized column being recorded for comparison with the address data received in connection with the next appearing read out instruction so that if a section in the same column needs to be interrogated that column stands ready and time is saved by discarding the routine of column selection and energization. A section of a group comprises a set of 16 contacts serving a corresponding set of 8 junctors. The scanning system may comprise a number of such matrices; address data from a computer processing calls indicating the matrix and column of a wanted group section. The address data is placed in a register along with a start bit which steps a 16-bit sequence counter off normal. If the register holding the address of the last matrix and matrix column interrogated agrees with the corresponding part of the address delivered from the processor, the address of the wanted section is applied promptly to gate the states of the associated junctors to a common 16 wire output. In this process the sequence counter steps under clock pulse drive and without hindrance until it returns to its zero stand-by state. On its 15th step the counter erases the start bit from the address register. The processor scans the start bit periodically and when it finds the bit reset it collects the data presented on the common output. If the register holding the address of the matrix and column last interrogated does not agree with the corresponding part of the address delivered from the processor, the column being energized is disconnected and the column required by the new address is connected up and energized with the sequence counter advancing with delays introduced in its second and third steps to enable the current to establish itself in the newly energized column circuit. At the 14th step the sequence counter gates the identity of the new column into the register recording the last column to be interrogated. The address of a matrix column is decoded to pulse the gate electrode of a silicon controlled rectifier over which the column circuit is energized, Fig. 3 (not shown). The control circuitry for handling the address data from the processor comprises NAND circuits, Fig. 4 (not shown. An algorithm for the processor in handling the sequential scanning of junctor sections with interrupts for detected changes of state is given with reference to Figs. 5 and 6 (not shown)