Patent GB-1167945-A (GB)
Title: Data Processing System with Acces Control for Subsystems.
IPC: G06F9/48
Filed: 1967-05-23
Abstract: 1,167,945. Priority arrangements in data processing. GENERAL ELECTRIC CO. 23 May, 1967 [25 May, 1966], No. 23873/67. Heading G4A. In a data processing system, a memory controller comprises a plurality of first storage devices each settable by a memory access request from a respective communicating device, status means generating a not busy signal continuously during any period when the memory controller is not occupied in processing a prior access request and operable for generating a not busy signal at a predetermined time during the processing of a prior access request by the memory controller, and a second storage device respective to each first storage device and settable to obtain memory access in response to the simultaneous occurrence of the not busy signal and the set state of the first storage device. Each of a plurality of memory controllers grants requests from processors and input/output controllers for access to a memory associated with the memory controller, on a priority basis as follows. In Fig. 4, semi-circles with an extra bar are AND gates when embedded in flip-flop and NAND gates otherwise. Semicircles without a bar are inverters. A 0 input to a simple junction will override any other inputs. During each access the timing pulses T s , PIN and SI are produced in turn, SI indicating that an access has progressed to the point where the next access request to be granted may proceed. Fig. 4 shows two request channels 0, 1 (indicated by subscripts) and part of a third 2. An access request at I (i.e. I 0 , I 1  or &c., depending on the channel) sets a corresponding (i.e. relating to the same channel) flip-flop A. Provided corresponding masking flip-flops M are set and corresponding flip-flops C are reset, flip-flops B corresponding to the set flip-flops A will be set when the memory is about to become free as indicated by the reset state of a "busy" flip-flop 734 common to all the channels. The busy flip-flop will next be set in response to the set state of any A flip-flop. A flip-flop PRFF is set in the highest priority channel in which the B flip-flop is set to control gates granting access to that channel and permitting transmission of data, address and command information. The highest priority is determined by inverter and junction logic 736, 740, 742 &c. The lowest numbered channels have the highest priority except that a manually-operated testing and diagnosis channel (not shown in Fig. 4) has highest priority of all. Setting of a PRFF flip-flop resets the corresponding A flip-flop and sets the corresponding C flip-flop. The C flip-flop of a given channel can be reset through NAND's 820, 821, 825 from lower priority channels as shown. The C flipflops ensure that if access requests for lower priority channels arrive while a request on a given channel is being serviced, they (one from each channel) will be serviced before any second request on the given channel. However, by changing over a switch 830 in any given channel, automatic reset of the corresponding C flip-flop is provided with the result that the given channel and all higher priority channels (if any) do not participate in this anti-hog arrangement with respect to any channels of lower priority than the given channel (but do with each other). The testing and diagnosis channel never participates in the anti-hog arrangement. The mask flip-flops M are under programme control (overridable manually), responding to bit 32 of a word in conjunction with the presence of a signal SMSKU for the upper group of channels or a corresponding signal for the lower group of channels (not shown), the reset state of a given M flip-flop preventing accesses by the associated channel by blocking the transfer from flip-flop A to flip-flop B and preventing flip-flop A from setting the busy flip-flop. The memory controllers may also permit accessing of processors and input/output controllers by other processors and input/output controllers