Patent UA-83412-U (UA)
Title: Code converter
Inventor: KULYK IHOR ANATOLIIOVYCH
IPC: H03M7/00
Filed: 2013-03-05
Abstract: A code converter comprises an input bus and n bits, each of which comprises a trigger and two AND elements, a first OR element, and NOT element and an adder, a second OR element is introduced to bits from second to k- th , where k – a check value less than number of bits, but more than zero, a first group of adder inputs is connected to the adder direct and inverse outputs of the trigger, set inputs and reset inputs of which are connected correspondingly to the outputs of first and second AND elements, the first input of AND element is connected to the input of NOT element, whose output is connected to the first input of first element AND, second elements of first and second element AND of every bit beginning from (k+1)-th is connected to the output of second element AND of the previous bit, the second group of adder, inputs of which is connected to outputs of an adder of the next bit, the input bus is connected to the second inputs of first and second AND elements of first bit. In each bit the first and second inputs and an output of first OR element are connected correspondingly to the direct output of the trigger, output of the adder corresponding to the k-th number, and input of the NOT element, output of the second OR element is connected to the second input of the first AND element, third input of which is connected to an input bus, the first input of second OR element is connected to the output of second AND element of previous bit, the outputs of adder of first bit corresponding to the numbers from "0" to (k -1) are connected correspondingly to the second inputs of second OR elements from k-th bit to the second bit and third input of first AND element of first bit, moreover a parallel-to-series code converter is introduced, data inputs of which are connected to the second group of adder outputs of first bit correspondingly, a zero counter and a bit number counter, first inputs of which are connected to output of the parallel-to-series code converter, the zero counter output is connected to the control inputs of the parallel-to-series code converter and the bit number counter, a decoder to inputs 1, 2,…, f-th of which, where f=log[n] , 1 , 2 , ... , f–th outputs of the bit number counter are connected; a group of (k-2)–th OR elements, (n-k+1) decoder output is connected to the first input of first element OR of said group, to the second inputs of said group of elements OR (n-k+2), (n-k+i), ...., n-th decoder outputs are connected correspondingly, the outputs of each previous element of group (k-2)-th OR elements are united to the inputs of next OR elements of said group correspondingly, (k-1) group of exclusive OR elements, to first inputs of which the second group of first bit adder outputs are correspondingly connected; to the second inputs beginning from second element of said group of exclusive OR outputs of (k-2)–th elements OR are correspondingly connected; while to the second input of first element exclusive OR ( n - k +1 )-th decoder output is connected; register inputs of which 1 ' , 2 ' , ... , i , ... , (k -1)-th are connected to the outputs of group elements exclusive OR correspondingly and to 1 , 2 , ... , j , ... , (n-k+1)-th inputs of which there are connected 1 , 2 , ... , j , ... , ( n - k +1 )-outputs of second group of adder outputs of first bit; the register output is the output of device.