Patent GB-819909-A (GB)
Title: Improvements in or relating to coding apparatus
IPC: H03M5/00
Filed: 1955-08-26
Abstract: 819,909. Television. SKIATRON ELECTRONICS & TELEVISION CORPORATION. Aug. 26, 1955 [Aug. 26, 1954], No. 24642/55. Class 40 (3). [Also in Group XXXVIII] An apparatus for selective signalling or control establishes a given condition of selection signals in response to input code signals during a predetermined time period and utilizes that condition in combination with the condition established by a later supply of input code signals to select the signal or control during a later time period. It is stated that the apparatus may be utilized for coding in scrambled television systems of the type described in Specification 783,854. As shown in Fig. 2, binary signals A, B, C, Fig. 1, are applied during repetitive time periods a, b, c, to right-hand inputs 10, 12, 14, of flip-flops 16, 18, 20. A negative input on one input line of a flip-flop produces a relatively high potential on the output line aligned with that input line. The left-hand inputs of the flip-flops are connected to a line 22 and through a delay circuit 58 to a source of reset pulses. The two outputs of each flip-flop are connected as shown to the lines 28 of a matrix circuit, the vertical and horizontal lines of the matrix being interconnected by resistors 36 as shown in the magnification circle. The right-hand or " 1 " outputs of flip-flops 16, 18, 20, are further connected via differentiating circuits 46, 60, to the right-hand inputs of flip-flops 48, 50, 52 respectively, the left-hand inputs of flip-flops 48, 50, 52 being connected to a line 54 which carries a reset pulse. The outputs of flip-flops 48, 50, 52 are connected to lines 56 in the matrix, the matrix being so arranged that for each of the sixty-four possible combinations of the flipflops a corresponding one of the sixty-four vertical lines 32 will carry a predetermined maximum potential. A reset pulse is applied to line 54 at time to reset flip-flops 48, 50, 52 to " 0 and at time t 1  to reset flip-flops 16, 18, 20 to " 0 " where they are not already in that state. Whenever a flip-flop 16, 18, 20 moves from the " 1 " state to the " 0 " state it produces a pulse at the right-hand input of the corresponding flip-flop 48, 50, 52. Thus, immediately after time t 1 , flip-flops 48, 50, 52 represent the previous states of flip-flops 16, 18, 20, and a new condition is set up in flip-flops 16, 18, 20. As soon as this is completed, at say time t 2 , a corresponding one of the lines 32 is energized at the maximum voltage value to enable its gate valve 38 to pass a signal on line 40. Further banks of flip-flops may be added in the same way and the matrix augmented accordingly. In an alternative arrangement, Fig. 3, signals A are applied to line 80 connected to one of two enabling inputs of a gate 84, and signals B are applied to line 82 providing one of two enabling inputs of gate 86. The output of gate 84 provides the left-hand input for a flip-flop 88, and the output of gate 86 provides the left-hand input for a flip-flop 90, the righthand inputs of both flip-flops being connected to a line 92 for reset purposes. After the application of signals A, B, the output lines of the flip-flops assume particular conditions, and capacitors 96 serve to retain a memory of the potential level in each line following the time when a pulse on line 92 has reset the flip-flops. The discharge time of the capacitors is such as to hold this memory through the next code period, the outputs being applied to the vertical lines 100 of a matrix similar to that shown in Fig. 2 to control a selected gate valve. The lines 100 of a matrix similar to that shown in 104 in which the vertical and horizontal lines are interconnected by diodes as shown in the magnification circle. Thus when line I is at its highest potential, conduction through a diode at the junction with line R will cause current flow through a resistor 106 to enable gate 86. In this way voltages stored by capacitors 96 from a previous code period may or may not open one or both gates 84, 86, during the occurrence of signals A, B, and during a given code period the values of the voltages on the output lines 100 reflect the input code signal condition during the previous code period. An additional gate 110 may be provided having as one input the line S and as a second input a line 112 which may be connected through a switch 116 to a source of reset pulses on line 114. The line 114 is normally connected to line 92, but if the reset pulses are switched to the gate 110 these pulses will be applied to the flip-flops only at such times as no circuit is made between the selected one of the output lines 100 and the line S. The output lines 32, Fig. 2, or 102, Fig. 3, may be applied to gates 120, Fig. 6, and pulses from sources D, E, F, which occur at different time instants within repeating time periods applied to lines 122, 124, 126, switches 130 connected respectively to the second input of the gates, selecting which of the pulses D, E, F, control each particular gate. The outputs of the gates are collected on a common line 132.