Patent GB-1189459-A (GB)
Title: Improvements in or relating to synchronising arrangements for Electrical Signalling Systems
Inventor: STRATHDEE JEFFREY CHARLES
IPC: H04J3/06
Filed: 1967-10-02
Abstract: 1,189,459. Multiplex pulse code signalling. PLESSEY B.T.R. Ltd. 30 Sept., 1968 [2 Oct., 1967], No. 44815/67. Heading H4L. Means are provided for searching for and responding to a synchronizing signal at a receiver in a P.C.M. system. General description.-As described there are eight bits per channel period, twenty-four channel periods per frame and four frame periods to each superframe period. The sync. signal is transmitted during the fourth frame period and comprises binary 1 as the first digit of channels nine and ten followed by a sequence of alternate 0 and 1 as the first digit in channels eleven to twenty-four. The receiver includes two types of gate circuit, diode gates D in which the output is negative when the specified number of inputs are positive, otherwise the output being positive and transistor gates T which operate in the opposite manner. An eight-way bit clock TB (not shown), a twenty-four-way channel clock TC (not shown) and a four-way frame clock TF (not shown) are provided at the receiver. Toggles 20, 21 are arranged to recognize two successive 1's in the ninth and tenth channels, toggles 23 to 26 form a binary divider chain which counts the alternate 0's and 1's in channels eleven to twenty-four and toggle 22 is a divide-by-two stage whose state is constantly compared with that of toggle 23 so that if alternate 0's and 1's are being received these two toggles change state at the same time. The toggles have normal set and reset inputs and outputs and also a preset input and a strobe input and when a positive potential is applied to the preset input the set output becomes negative and the reset output positive on the occurrence of the next strobe signal regardless of the signals applied to the set and reset inputs. Operation; assuming correct channel timing.- When the circuit is first switched on a negative potential is applied to terminals SO1 to SO4 for a short time to preset toggles 20, 21 via gate G7, toggles 22 to 26 via gate G9, toggle N via inverter G14, toggle DB via inverter G18 and toggles 32, 33, 34 via gate G28. Clocks TB, TC and TF are also reset to their final count position. Toggle N now supplies an input to gate G1 and the other inputs are strobe pulses B and output TB1 of the clock TB, the output of gate G1 being inverted at G2 and supplied either via gate G3 to strobe the toggles 20 21 or via gate G6 to strobe the toggles 22, 23. The set outputs of toggles 20, 21 via gate G4 hold gate G3 open and also via inverter G5 hold gate G6 open. Incoming signals are supplied via terminals 30, 31 to the set and reset inputs of toggle 20 so that toggle 20 is preset or set for a received 1 or 0 respectively in a first bit period. If the signal in the first bit period of the next channel is different the toggle 20 will change state on being strobed by pulse B but if the signal is the same the toggle 21 takes up the same state as toggle 20. If both digits are 1's the toggles 20, 21 are reset and gate G4 is operated to close gate G3 and via inverter G5 to open gate G6 so that strobe signals are now applied to toggles 22, 23 and toggle 22 assumes the reset condition. If the next digit of the sync. signal is 0 the toggle 23 is reset and if this is followed by a 1 toggle 23 is set together with toggle 22 and toggle 24 is reset. Subsequent changes of state of toggle 23 are similarly counted by toggles 24, 25, 26. If two successive 0's are detected by toggle 23 a gate G11 operates at pulse TB2 and a preset pulse is supplied to toggles 20 to 26 via gates G7, G9 and this restarts the synchronization search completely. If, however, two successive 1's are received a gate G10 is operated and only the toggles 22 to 26 are reset it being assumed that this is the start of the sync. code. At the end of the sync. signal toggles 23, 25, 26 are reset and toggle 24 is set so that gate G12 operates, inhibits gates G10, G11 and via inverter G26 and gate G13 resets the channel clock TC to TC24. The outputs of inverter G26 and TC24 are supplied to gate G17 to reset the frame clock TF at time TB3 to TF4 and at time TF4, TC24, TB4 a gate G25 is operated to strobe the shift register comprising toggles 32, 33, 34 which were preset by the " switch on " signal via gate G28. The output of gate G12 provides an input to the shift register so that when a synchronizing code has been detected this information fed into the first stage of the shift register inhibits a gate G20 to prevent any further reset pulses being applied to the clocks. At time TC24, TB6 the gate G16 is operated through inverter G27 to change the state of toggle N and inhibit gate G1 thus preventing any strobe pulse from operating toggles 20 to 26. At time TB7 gate G8 is operated to preset toggles 20 to 26 to prepare for another search, the state of toggle N being changed again by a signal via gate G15 at time TF4, TC8, TB4 at which the next sync. code should start. Shift register 32, 33, 34 ensures that a new search for the sync. signal when synchronism is lost will not be instigated until it has failed to appear at the expected time on three successive occasions. Operation; incorrect channel timing.-If the sync. code has not been identified after a period of five frames it is arranged for the next time slot to be inspected for a five frame period and so on until the sync. code is found. The initial switch-on signal presets divide-by-two toggle DB via inverter G18 and the toggle is strobed at time TF1, TC8 via gate G19 so that gates G23, G24 are inhibited. If a sync. signal has not been identified by the next time period TF1, TC8, toggle DB is set and opens gates G23, G24 and during bit period TB7, TF1, TC22, the strobe signal B is supplied as a bit slip strobe to the bit clock TB to move the clock TB on by one position. At time TF1, TC23 gate 24 transmits a pulse to reset clock TF to time TF4 and at the next time TF1, TC8 the sequence is repeated and continues until the sync. code has been identified whereupon the output of gate G20 inhibits the gates G23, G24 so that the clocks keep normal time.