Patent GB-1057085-A (GB)
Title: Data processing system
IPC: G06F13/26
Filed: 1963-12-24
Abstract: 1,057,085. Buffer stores. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 24, 1963 [Dec. 31, 1962 (2)], No. 51015/63. Headings G4A and G4C. In a data processing system in which bidirectional data flow can take place between an input-output device and a main data memory via a buffer store (16), the buffer store may be operated by read-only and write-only timing cycles and may be addressed for a next cycle of operation prior to the termination of a current cycle of operation. Four input-output (I/O) units can communicate with a main memory of a central processing unit (CPU) via a core buffer store (16) which has in respect of each I/O unit three sections A, B, DCW, each capable of holding eight 9-bit bytes (includes one parity bit per byte). Data is transferred to and from the buffer store (16) one byte at a time via a byte buffer register (38), the sections A and B being used alternately and the section DCW holding a data control word (DCW) which is transferred to a DCW register (12) during CPU- buffer communication and has fields specifying the address in the CPU main memory concerned (ADDR), the number of words in consecutive addresses to be transferred under control of the same DCW (COUNT), the address in the main memory of the next DCW (REFILL) and also a control field (CTLS). As each word is transferred from the CPU memory to the buffer store (16), for example, the ADDR field is incremented by 1 and the COUNT field decremented by 1 until the count field is zero when the REFILL field is stored in a main memory address register (MAR) to transfer the next DCW from the main memory to the DCW register (12). The CPU word is composed of eight 8-bit bytes, assembly of this 64-bit word for parallel transmission to the CPU from eight bytes serially supplied from the buffer store (16) being accomplished in a register (10), this register also serving for the reverse process (disassembly). CPU-buffer communication (referred to as A/D operation, meaning assembly-disassembly) may be ordered by the CPU which supplies one of four signals (A/D1, A/D2, A/D3, A/D4) to select the I/O unit and also sets a read/write trigger for that I/O unit to control the direction of flow of data. A 3-stage binary status counter (54) keeps track of the bytes being transferred to or from a section (A, B or DCW) of the buffer store (16) and a trigger (A/B, one per I/O unit) ensures that the sections A and B are used alternately (i.e. one section filled or emptied, then the other). Buffer-I/O unit communication (referred to as S/R operation, meaning servicerequest) is at the request of any I/O unit which signals to a priority selector (21) for selecting the I/O unit to be serviced. An A/B trigger, read/write trigger (shown separately but may be those used for AID operation) and a status counter are provided for each I/O unit. An S/R operation takes precedence over an A/D operation and may interrupt one at the end of the current byte cycle. Unless such an interruption takes place, an S/R operation in which a section A or B has been completely filled is followed by an A/D operation (ordered by the status counter). During an A/D operation, transfer of data to or from an A or B section of the buffer store (16) is preceded by transfer of the data control word DCW from section DCW of the buffer store (16) to the DCW register (12) and followed by the transfer of the modified (or new) DCW back to the buffer store (16). These transfers are controlled by a counter (108). " Read" " and "Write" tapped delay lines are used to provide control pulses, the appropriate one receiving an input pulse during each byte cycle and producing, among others, a pulse (29) slightly before the end of the byte cycle to serve as the input pulse for the next byte cycle if required. The pulse (29) also serves for setting up in a buffer address register (BAR 23) the buffer store address concerned in the next byte cycle, this address being provided on parallel lines from the status counter concerned &c.