baber/WOPTO huggingface dataset:
Patent TW-387851-B (TW)
Title: Tote transport system
Inventor: KIERPAUL CHESTER F
IPC: B64F1/36
Filed: 1997-02-21
Granted: 2000-04-21
Abstract: A tote conveyor system for transporting totes from an end-of-use point to the point-of-use. The conveyor system comprising a combination of conveyors including a vertical conveyor and substantial horizontal conveyor with a means to transferring totes between the two different systems.
Patent TW-539675-B (TW)
Title: Novel 2,3-disubstituted-4(3H)-quinazolinones
Inventor: ELLIOTT MARK L
IPC: C07D401/04
Filed: 1997-04-08
Granted: 2003-07-01
Abstract: The present invention relates to novel 2,3-disubstituted-4(3H)-quinazolinones compounds of formula I, and their pharmaceutically acceptable salts, and pharmaceutical compositions and methods of treating neurodegenerative and CNS-trauma related conditions.
Patent TW-352451-B (TW)
Title: Automatic thinner supplying apparatus and method for semiconductor manufacturing process
Inventor: WOO JAE-YOUNG
IPC: H01L21/00
Filed: 1997-07-03
Granted: 1999-02-11
Abstract: An automatic thinner supply apparatus is used to clean wafer rinsing nozzle, including: a main supply tank; an auxuiliary supply tank connected to the main supply tank by the supply pipe; and a manifold connected to the auxiliary tank and having spray nozzle at the end.
Patent TW-326551-B (TW)
Title: The manufacturing method for Ti-salicide in IC
Inventor: CHEN CHORNG-JOU
IPC: H01L21/02
Filed: 1997-07-11
Granted: 1998-02-11
Abstract: A manufacturing method for Ti-salicide in IC includes the following steps: (a) Form field oxide and transistor used for isolating on semiconductor Si substrate; (b) Use Ar+ plasma to clean the surface of Si substrate; (c) Form Ti film on whole Si substrate surface; (d) Proceed 1st rapid thermal annealing on Si substrate to transfer Ti into Ti-salicide by two-staged way and at mixing gas of Ar!Oand N2 environment; (e) Selectively etch Si substrate to remove non-reaction Ti film; (f) Proceed 2nd rapid thermal annealing on Si substrate by two-staged way and at mixing gas of H2 and N2 environment.
Patent TW-356616-B (TW)
Title: Power supply circuit having high power factor correction circuit
Inventor: CHOI NAK-CHOON
IPC: H02M7/217
Filed: 1997-08-21
Granted: 1999-04-21
Abstract: A power supply circuit includes a booster converter and a high power factor correction circuit. The booster converter supplies a load through a diode when a switching transistor is switched off with as a boosted DC voltage energy accumulated in an inductor when the switching transistor is switched on, by switching the input current through the inductor and the switching transistor, the input current being obtained by full-wave rectifying an AC power supply; and a high power factor correction circuit, used to control an off-time of the switching transistor by comparing a comparison voltage and an inverse sawtooth wave, the comparison voltage being obtained by combining an error voltage detected from the DC voltage supplied to the load and a detection voltage obtained by sensing the input current flowing through the inductor when the switching transistor is switched on.
Patent TW-350830-B (TW)
Title: Conveyor assembly, length adjusting conveyor, method of conveying an associated strip material along a conveyor assembly and method of adjusting the length of a conveyor system
Inventor: BANAS MARK DANIEL
IPC: B29D30/38
Filed: 1997-09-12
Granted: 1999-01-21
Abstract: A sort of conveyor assembly, for conveying on conveying systems, with accumulation of relevant tapes; having the conveyor assembly: an up conveyor for housing and conveying said tapes, having the up conveyor a first conveying belt and a first drive for driving of the first conveyor belt, being the up conveyor in physical fixation; a central conveyor, for housing of relevant tapes coming from said up conveyor, having the central conveyor a second conveyor belt and a second drive for driving of the second conveyor belt, being the central conveyor in movement along a physically horizontal route; length adjuster for movement of the central conveyor along said route; and a lower conveyor, for housing of said relevant tapes coming from said central conveyor, having said lower conveyor a third conveyor belt and a third drive for driving the third conveyor belt, being the lower conveyor in physical fixation.
Patent TW-351708-B (TW)
Title: Method and apparatus for treating substrate
Inventor: SCHOENLEBER DIETMAR
IPC: B08B3/04
Filed: 1997-09-27
Granted: 1999-02-01
Abstract: A method for treating a substrate in which a substrate (3) is disposed in a treating fluid (9) and lifted and lowered by a hoisting mechanism, being characterized in that the substrate is being lifted from the treating fluid in a first tray (1), then transferred to a second tray (1).
Patent TW-541184-B (TW)
Title: Use of annexin for imaging cell death in vivo
Inventor: BLANKENBERG FRANCIS G
IPC: A61K51/08
Filed: 1998-04-28
Granted: 2003-07-11
Abstract: A method of imaging apoptosis in vivo, using radiolabeled annexin, is described. Use of annexin labeled with a biocompatible radionuclide in a method of imaging cell death in a region of a mammalian subject in vivo, comprising (a) administering to a subject, annexin labeled with a biocompatible radionuclide, (b) positioning the subject within the detection field of a radiation detector device, and (c) measuring radiation emission from the radionuclide in the subject, with the radiation detector device, to construct an image of radiation emission, wherein said image is a representation of cell death in said region of said mammalian subject.
Patent TW-444385-B (TW)
Title: Stacked low voltage triggering silicon control rectifier and the application in the electrostatic discharge protection for integrated circuit
Inventor: KE MING-DAU
IPC: H01L23/60
Filed: 1998-04-28
Granted: 2001-07-01
Abstract: The stacked low voltage triggering silicon control rectifier in the present invention comprises two or more silicon control rectifiers, each silicon control rectifier comprising an anode, a control gate and a cathode. The silicon control rectifier connects the control gates of the same type of silicon control rectifier, and connects the cathode of each silicon control rectifier and the anode of next silicon control rectifier, so as to achieve the stacking of silicon control rectifiers, change the stacking number for silicon control rectifier, and adjust the overall opening holding voltage of the stacked low voltage triggering silicon control rectifier. The electrostatic discharge protection circuit comprises a protection device and an electrostatic discharge detector to protect the internal circuit. The protection device comprises at least the stacked low voltage triggering silicon control rectifier. The electrostatic discharge detector is used to detect the electrostatic discharge current from the power contact to trigger the protection device to leak the electrostatic discharge current; adjust the stacking number of the stacked low voltage triggering silicon control rectifier to avoid the occurrence of latch-up. Therefore, the inventive electrostatic discharge protection circuit can be effectively and safely applied in the integrated circuit without the latch-up problem.
Patent TW-391004-B (TW)
Title: Semiconductor memory for secure data storage
Inventor: PATHAK SAROJ
IPC: G11C16/28
Filed: 1998-05-15
Granted: 2000-05-21
Abstract: A memory device (Fig. 1) includes a memory cell (102) whose data state is sensed by a sense amplifier (100). A balance amplifier (200) having the same construction as the sense amplifier is utilized to sense a balance cell (202) having the same construction as the memory cell. The balance cell is maintained in an erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit (208) is used to adjust the conductivity of the blance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.
Patent TW-397971-B (TW)
Title: A method and apparatus for dust proofing a removable data storage cartridge and drive
Inventor: KATAO HISASHI
IPC: G11B23/03
Filed: 1998-05-26
Granted: 2000-07-11
Abstract: A dust proof apparatus for removable data storage drive includes a cartridge housing a data storage medium. The cartridge comprises: an enclosure within which the data storage medium resides, one surface of the enclosure defining an aperture therethrough granting access to the data storage medium; a guide plate adjacent the one surface of the enclosure, the guide plate and the one surface defining a pocket; and a door slidably mounted to the enclosure, the door slidable from a first position substantially covering the aperture to a second position substantially within the pocket. The apparatus can also include a drive housing for receiving the cartridge. Such a system includes a locking mechanism including a feature which engages the door to prevent accidental opening thereof. The cartridge or drive housing may be divided into plural compartments and may include air filters.
Patent TW-414954-B (TW)
Title: Electrode arrangement, method for its generation or contact
Inventor: ENGELHARDT MANFRED
IPC: H01L21/3205
Filed: 1998-06-10
Granted: 2000-12-11
Abstract: According to this invention, a method is provided to structurize at least one to-be-structurized layer, this method includes the following steps: said to-be-structurized layer is provided, a mask is provided on said to-be-structurized layer, said to-be-structurized layer is drily etched. The method according to this invention is characterized in that the mask includes a metal-silicid, a metal-nitride or a metal-oxide.
Patent TW-505661-B (TW)
Title: Process for producing hyperbranched polymers
Inventor: CAMPBELL J DAVID
IPC: C08F212/04
Filed: 1999-02-04
Granted: 2002-10-11
Abstract: A method is provided for producing hyperbranched polymers comprising heating a polymerizable reaction charge comprising (a) a monomer mixture comprising 50-99.1% by weight of at least one monoethylenically unsaturated monomer and 0.1-50% by weight of one or more multiethylenically unsaturated monomers and (b) if at least one ethylenically unsaturated monomer of the monomer mixture is not a thermally initiating monomer, a free radical polymerization initiator, to a temperature in the range from about 250 DEG C to about 400 DEG C in a continuous reactor which allows mixing of the reactor contents for a residence time of from about 2 minutes to about 60 minutes, provided that if the total amount of multiethylenically unsaturated monomer is less than 3% by weight of the monomer mixture than at least one of said one or more multiethylenically unsaturated monomers must be tri- or greater ethylenically unsaturated. The hyperbranched polymers prepared by this process are also described.
Patent TW-388890-B (TW)
Title: Variable capacitor
Inventor: SHIBATA YASUNOBU
IPC: H01G5/00
Filed: 1998-09-02
Granted: 2000-05-01
Abstract: A variable capacitor includes a stator, a conductive rotor, and a spring-action portion. The rotor electrode projects from the rotor, and a protrusion extends from the rotor as far as the rotor electrode, wherein the protrusion is formed on the rotor in a region other than that where the rotor electrode is formed. The spring-action portion applies a spring force on the rotor so as to press the rotor agains the stator. The spring-action portion is formed on a cover around an adjustment hole formed in the cover. The cover allows the rotor to rotate relative to the stator, and the adjustment hole permits the introduction of a tool for rotating the rotor by inserting the tool therethrough. The radial position of the protrusion is selected so as to substantially fall on a oiroular trajectory which as the rotor rutates, is swept out on the rotor by a section of the spring-action portion, which section is in contact with the rotor. Thus, even when the rotor is made thinner, a pressing force applied to the rotor by the spring-action portion is less likely to cause rotor deformation.
Patent TW-426907-B (TW)
Title: Improved dishing resistance
Inventor: HUCKELS KAI
IPC: H01L21/304
Filed: 1998-12-08
Granted: 2001-03-21
Abstract: Fabrication of devices that produces a surface with reduced dishing caused by polishing. The reduced dishing is the result of forming a first layer that partially covers a complex surface topography and a second layer the covers the surface topography. The second layer being more resistant to polishing than the first so as to reduce dishing in the wide spaces of the complex topography.
Patent TW-406197-B (TW)
Title: Optical system and method for providing corrected optical images
Inventor: MCKENNEY DEAN B
IPC: G02B27/64
Filed: 1998-12-17
Granted: 2000-09-21
Abstract: An optical system includes a housing having an axis of elongation, and a non-spherical window affixed to the housing. An optical corrector, preferably in the form of an aspherical strip of transparent material, is positioned adjacent to the curved inner surface of the window. The optical corrector is mounted on an optical corrector support, which is rotatable about the axis of elongation. An optical train is positioned such that the optical corrector lies between the window and the optical train. The optical train includes at least one optical element operable to alter an optical ray incident thereon, and a gimbal upon which the at least one optical element is mounted. The gimbal is pivotable about a transverse axis perpendicular to the axis of elongation. The optical train is mounted on an optical train support, which is movable independently of the optical corrector support. A sensor is positioned to receive the optical ray passing sequentially through the window, the optical corrector, and the optical train.
Patent TW-502284-B (TW)
Title: Multichamber system of etching facility for manufacturing semiconductor device
Inventor: KIM KI-SANG
IPC: H01L21/00
Filed: 1998-10-22
Granted: 2002-09-11
Abstract: There is provided a multichamber system of etching facility for manufacturing semiconductor devices, wherein the space for the facilities can be minimized by installing a plurality of process chambers in parallel having a transfer path between them. The multichamber system for manufacturing semiconductor devices comprises: a cassette stage for mounting a cassette having wafers stacked thereon; a transfer path for providing a space for the transportation of wafers with attached on the cassette stage; a plurality of process chambers aligned on the side of the transfer path; and a transfer mechanism installed in the transfer path and loading/unloading the wafers stacked on the cassette stage to the plurality of process chambers.
Patent TW-403687-B (TW)
Title: Oxycutting process using high-purity high-pressure oxygen
Inventor: SUZON SERGE
IPC: B23K7/00
Filed: 1998-11-20
Granted: 2000-09-01
Abstract: Process for cutting steels and steel alloys, in which high-purity oxygen, containing at most 0.1% of impurities, at high pressure, i.e. at a pressure of at least 10<6> Pa, is used as cutting gas. The invention also relates to an oxycutting device for implementing the process, comprising a nozzle having a convergent/divergent profile, and it being possible for high-purity cutting oxygen to be used in such a process.
Patent TW-440765-B (TW)
Title: L2 cache testing method
Inventor: JANG YOU-CHIUAN
IPC: G06F13/00
Filed: 1998-12-04
Granted: 2001-06-16
Abstract: This invention provides a L2 cache testing method for directly testing the L2 cache of computer system through the execution of computer to check if the function of L2 cache works properly. The method includes: getting the allocation parameter and capacity size of the L2 cache; then initiating the L2 cache to make the content of cache (including a L1 cache and a L2 cache) identical to that of the memory; and finally using the cache bus related control registers to access the L2 cache to check if the function of L2 cache works correctly.
Patent TW-470645-B (TW)
Title: Compound for inhibiting or preventing HIV infection, its preparation and pharmaceutical composition comprising same
Inventor: SAHLBERG CHRISTER
IPC: C07D213/75
Filed: 1999-01-15
Granted: 2002-01-01
Abstract: Compounds of the formula I: wherein Rx is cyano or bromo; Rt is halo; R2 is C1-C3 alkyl, and pharmaceutically acceptable salts and prodrugs thereof have activity as antiretrovirals.
Patent TW-370591-B (TW)
Title: Control device of internal-combustion engine used in car
Inventor: ONOZUKA TADASHI
IPC: F02P5/15
Filed: 1999-02-22
Granted: 1999-09-21
Abstract: The subject of the invention is to provide a control device which can change the control characteristics of an internal-combustion mechanism used in cars depending on deterioration degree of car parts. To solve this subject, the resolution of the invention comprises: a deterioration degree check part 21 of car parts, which detects the deterioration degrees of one or more parts affecting the noise control, fuel efficiency, exhaust characteristics and driving performance; a control characteristics switch part 22, which selects the control characteristics capable of raising the noise control, fuel efficiency, exhaust characteristics and driving performance or suppressing the deterioration degrees of those characteristics noted above from various control characteristics memorized in control characteristics memory part 23, depending on the deterioration degrees detected by the deterioration degree check part 21; and the control characteristics selected by the control characteristics switch part 22 are transported to the internal-combustion mechanism part 24 which produces signals such as an ignition signal to drive the spark-plug using gained time of the transported control characteristics.
Patent TW-427026-B (TW)
Title: Gate biasing arrangement
Inventor: JOHANSSON JAN
IPC: H03F1/30
Filed: 1999-02-26
Granted: 2001-03-21
Abstract: To eliminate the temperature dependency of the quiescent current of a power tran-sistor (1), the gate bias voltage of the power transistor (1) is controlled by means of the output voltage of a biasing transistor (3) residing on the same silicon chip as the power transistor (1), and by interconnecting the gate (G3) and drain (D3) of the biasing transistor (3) and feeding it with a constant current (IB) from external circuitry.
Patent TW-439165-B (TW)
Title: A pixel based machine for patterned wafers
Inventor: SMILANSKY ZEEV
IPC: G01N21/956
Filed: 2000-03-28
Granted: 2001-06-07
Abstract: A method is provided for the detection of defects on a semiconductor wafer by checking individual pixels on the wafer, collecting the signature of each pixel, defined by the way in which it responds to the light of a scanning beam, and determining whether the signature is that of a faultless pixel or of a pixel that is defective or suspect to be defective. An apparatus is also provided for the determination of such defects, which comprises a stage for supporting a wafer, a laser source generating a beam that is directed onto the wafer, collecting optics and photoelectric sensors for collecting the laser light scattered by the wafer in a number of directions and generating corresponding analog signals, an A/D converter deriving from said signals digital components defining pixel signatures, and selection systems for identifying the signatures of suspect pixels and verifying whether the suspect pixels are indeed defective.
Patent TW-431041-B (TW)
Title: Semiconductor light emitting element and semiconductor laser
Inventor: TANABE TETSUHIRO
Filed: 1999-09-10
Granted: 2001-04-21
Abstract: A semiconductor laminate containing a luminous layer forming part (11), having at least a n-type layer (4) and a p-type layer (6) consisting of a compound semiconductor of group III elements and nitrogen and laminated to form a luminous layer, is provided on the surface of a conductive substrate (1) of GaAs, Ge, Si etc. via a buffer layer (2) suitable for the substrate, thereby providing a vertical semiconductor luminous element which permits a lead-out from an electrode through both upper and lower surfaces of a chip and uses a group III nitride compound semiconductor which is excellent in semiconductor layer crystalline and luminous efficiency and can be cleaved. Therefore, an LD chip can be mounted easily on a heat-conductive submount to prevent lowering the luminous efficiency by heat (quantum differential efficiency), and deteriorate on it.
Patent TW-434904-B (TW)
Title: Method for reducing inverse narrow width effect
Inventor: LI JUNG-SHIUNG
IPC: H01L29/772
Filed: 1999-12-08
Granted: 2001-05-16
Abstract: This invention relates to a method for reducing inverse narrow width effect. In this method, a gate oxide layer is formed on the active region, in which the gate oxide thickness is larger at the edge region and smaller at the central part. Through the gate oxide layer with thicker edge, the effect of local intensified field on the threshold voltage for the part of transistors adjacent to shallow trench isolation structure is mitigated. Therefore, the sub-threshold leakage current of transistor can be reduced so as to decrease the inverse narrow width effect.
Patent TW-487996-B (TW)
Title: Wiring substrate and semiconductor device
Inventor: SOTA YOSHIKI
IPC: H01L23/498
Filed: 2000-01-31
Granted: 2002-05-21
Abstract: A semiconductor device includes a wiring substrate which includes a wiring pattern provided per each wiring with a land covering an external terminal mounting perforation for mounting an external terminal, said land being provided on a side of the wiring pattern on which side a semiconductor chip is mounted, wherein a plurality of second pads for electrically connecting the wiring and the semiconductor chip by wire bonding are provided per each wiring, and at least one of the second pads is provided between lands.
Patent TW-442964-B (TW)
Title: DRAM having COB structure and its fabrication method
Inventor: KAWAZOE TAKAYUKI
IPC: H01L27/108
Filed: 2000-02-02
Granted: 2001-06-23
Abstract: A DRAM having a COB structure according to the invention including a semiconductor substrate formed with a diffusion layer, a word line formed on the semiconductor substrate, an interlayer insulating film formed on the word line, a capacitor contact formed at the interlayer insulating film and connected to the diffusion layer, a bit line formed on the interlayer insulating film, a side wall insulating film formed on a side face of the bit line, a stack electrode formed by utilizing a side face of an insulating film selectively formed at a potion thereof directly above the bit line to be brought into contact with the capacitor contact, a capacitance insulating film formed on a surface of the stack electrode and a plate electrode formed on the capacitance insulating film.