Patent GB-734072-A (GB)
Title: Improvements in or relating to digital computors
Inventor: WILLIAMS FREDERIC CALLAND
IPC: G11C11/23
Filed: 1949-06-22
Abstract: 734,072. Digital electric calculating apparatus. NATIONAL. RESEARCH DEVELOPMENT CORPORATION. June 21, 1950 [June 22, 1949], No. 16584/49. Class 106 (1). In a digital computing machine comprising a C.R.T. storage device, means for controlling the irradiation of the C.R.T. screen, and a regeneration circuit between the pick-up electrode of the storage device and the controlling means, the regeneration circuit includes a plurality of computing circuit devices and switching means by which any one of the computing circuits may be alternatively switched into the regeneration circuit so that the signal supplied to the controlling means may be the result of any chosen one of a number'of different computing operations performed upon the signal from the pick-up electrode and a signal from an external source. The described embodiment, apart from the computing unit, is the same as the series-mode binary calculator described in Specification 731,341. It comprises a main store MS, Fig. 1, a Y-shift generator YSG for providing Y-deflection to the beam of the C.R.T. in the main store whereby any desired raster line or word may be selected, a staticisor MSTR for translating dynamic signals into static control voltages, and a control unit CL, including a single C.R.T: arranged for two-line storage. Control of the selection of the appropriate line is by an instruction gate IG and Y-plate waveform generator GYWG. The computing unit or accumulator A has in addition to a storage tube 16, pick-up electrode 17, amplifier, 18, read unit 19, write unit 20 and other ancillary items, a plurality of computing circuits 21, 22 and 23 each connected in series with an associated controlling gate circuit G6, G7 and G8 respectively, so as to provide three alternative paths for the signal output from the read unit to the write unit. An external signal arriving via the outward transfer gate OTG is supplied by way of isolating buffer amplifiers BA5, BA6, BA7. A further connection between the re.ad unit 19 and the write unit 20 comprises a simple gate circuit G5. whereby simple regeneration of the contents of the storage device, without arithrnetical operation, can be effected. The computing circuits may be of the types described in Specifications 705,476 and 705,479. The gate circuits G5 .... G8 may be controlled by certain digits of the function-determining portion of the instruction word set up in the main store staticisor MSTR which is described in Specification 731,341. Staticisor. Each section of the staticisor comprises a circuit as shown in Fig. 4. While the instruction, word in dynamic form is apllied via a terminal 33 to the anode of a diode D1, a negative-going pulse is applied at the time identified with the particular section of the staticisor to the anode of diode D2 via a terminal 32. If a negative-going pulse representing a "dash" or binary " 1 " in the signal appearing at terminal 33 coincides with the negative pulse at terminal 32, both diodes cease conducting simultaneously and the normally conducting valve V1 of a trigger pair V1, V2 is cut off, reversing the trigger. Four alternative outputs via cathode-followers V3, V4, V5 and V6, are available from the staticisor element for application to the various gates which determine the path of the number word in the accumulator unit and the particular operation to be performed on it. Specifications 645,691, 657,591, 682,156. 693,424, 705,474, 712,172 and 734,075 also are referred to.