baber/WOPTO huggingface dataset:
Patent TW-I708314-B (TW)
Title: 靜電吸盤
Inventor: SASAKI HITOSHI
IPC: H01L21/683
Filed: 2020-03-18
Granted: 2020-10-21
Abstract: 本發明的課題為提供一種可提高電漿密度的面內均勻性的靜電吸盤。
        本發明的解決手段為一種靜電吸盤，其特徵在於包含：陶瓷介電質基板，具有第一、第二主表面；基座板；第一電極層，配設於陶瓷介電質基板的內部，與高頻電源連接；第二電極層，配設於陶瓷介電質基板的內部，與吸附用電源連接，第一電極層在Z軸方向上配設於第一主表面與第二主表面之間，第一電極層的Z軸方向上的尺寸比第二電極層的Z軸方向上的尺寸還大，第二電極層在Z軸方向上配設於第一電極層與第一主表面之間，第一電極層具有第一主表面側的第一面，和與第一面相反側的第二面，被從第二面側供電，第一電極層包含陶瓷成分與金屬成分，陶瓷成分的濃度及金屬成分的濃度的至少任一個在Z軸方向上不均勻。
Patent TW-I785319-B (TW)
Title: 加壓接合用組合物、以及導電體之接合構造及其製造方法
Inventor: ANAI KEI
IPC: H01L21/52
Filed: 2020-03-26
Granted: 2022-12-01
Abstract: 本發明之加壓接合用組合物包含金屬粉及固體還原劑，且由使用乾燥塗膜之厚度A及燒結體之厚度B之關係式所表示之壓縮率為10%以上90%以下，該乾燥塗膜係於大氣氛圍下於110℃、大氣壓下將上述組合物乾燥20分鐘而形成，該燒結體係於氮氣氛圍下於280℃、6 MPa下將該乾燥塗膜處理20分鐘而形成。固體還原劑亦較佳為BIS-TRIS。又，本發明亦提供一種於加壓下對2個導電體及配置於該等之間之上述加壓接合組合物之塗膜進行處理，形成接合各導電體之接合部位之導電體之接合構造。
Patent TW-I730775-B (TW)
Title: Temperature control cycle leafless fan
Inventor: LIU CHIEN TE
IPC: F24F1/04
Filed: 2020-05-21
Granted: 2021-06-11
Abstract: A temperature control cycle leafless fan comprises a tubular structure, a first wind deflector, a second wind deflector, a base, a fan and a pump. The tubular structure has a hollow pipe wall to be used as a circulating heat transfer fluid tank. The tubular structure has a first port and a second port at both ends. The first wind deflector is provided at the first port. The second wind deflector is provided at the second port. The first wind deflector, the second wind deflector and the hollow tube wall form a gas channel together. The base is connected under the tubular structure. The fan is set in the base. The pump is connected to the circulating heat transfer fluid tank via pipelines. Thereby, the present invention can meet the cooling or heating needs of users by using the space 
between the inner and outer tube walls of the tubular structure as a heat transfer fluid tank.
Patent TW-I812863-B (TW)
Inventor: LANGVIN ELIZABETH
IPC: A43B13/20
Filed: 2020-06-01
Granted: 2023-08-21
Abstract: A sole structure for an article of footwear includes a bladder and at least one foam insert. The bladder includes an upper surface having a first portion defining a chamber and a second portion defining at least one recess adjacent to the chamber. The at least one foam insert is disposed within the at least one recess and has a top surface that is substantially flush with the first portion of the upper surface of the bladder. The first portion of the upper surface is exposed to the at least one foam insert.
Patent TW-I776166-B (TW)
Inventor: KIM JONGYOUN
IPC: H01L23/488
Filed: 2020-06-08
Granted: 2022-09-01
Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.
Patent TW-I779321-B (TW)
Inventor: CHEN KUAN-JU
IPC: G06F9/455
Filed: 2020-07-22
Granted: 2022-10-01
Abstract: A resource integration method suitable for a virtual environment, the steps of the resource integration method include: communicating a local Host OSt operation system with an external device through a bridge module and obtaining external device information; and receiving an access instruction from a guest operation system to a Host OSt machine through a receiving module, receiving a hardware processing result from the Host OSt machine, and selectively transmitting the access instruction to an external device through a bridge module and receiving hardware processing results from external devices. The hardware processing result corresponds to the access instruction. The Host OSt machine runs a virtual environment on the Host OSt operation system, runs the guest operation system in the virtual environment. The guest operation system runs an application program, and the application program is used to issue the access instruction.
Patent TW-I724963-B (TW)
Title: 垂直噴淋裝置及表面處理設備
IPC: C23C16/44
Filed: 2020-08-17
Granted: 2021-04-11
Abstract: 本發明提供了一種垂直噴淋裝置及表面處理設備；垂直噴淋裝置包括機架、垂直噴淋架和驅動該垂直噴淋架升降移動的升降機構，該垂直噴淋架支撐於該升降機構上，該升降機構安裝於該機架上。本發明透過設置垂直噴淋架，以實現垂直噴淋；設置升降機構來推動垂直噴淋架升降移動，則噴到線路板上的藥液可以被擾動，以更好的線路板上流動，以對線路板表面進行處理；由於垂直噴淋架為升降移動，可以避免線路板受到側邊受到較大的衝擊，以保證線路板的製作品質。
Patent TW-I729920-B (TW)
Title: Apparatus, method, and computer program product thereof for generating a cutting path for a printed circuit board
Inventor: JIANG YAN-MEI
IPC: G06F30/392
Filed: 2020-08-21
Granted: 2021-06-01
Abstract: An apparatus, method, and computer program product thereof for generating a cutting path for a printed circuit board. The apparatus stores a computer-aided design file of the printed circuit board, wherein the computer-aided design file defines a plurality of initial geometric objects, and each of the initial geometric objects has a piece of coordinate information. The apparatus preprocesses the initial geometric objects to obtain a plurality of processed geometric objects according to the pieces of coordinate information and a threshold, wherein a distance between any two processed geometric objects is not less than the threshold. The apparatus receives a plurality of control points and determines a plurality of subpaths from the processed geometric objects according to the control points, wherein the subpaths cover the control points. The apparatus further connects the subpaths as the cutting path.
Patent TW-I772940-B (TW)
Title: 圖像採集裝置
Inventor: HUANG JIAN-DONG
IPC: G06F3/041
Filed: 2020-10-27
Granted: 2022-08-01
Abstract: 一種圖像採集裝置，包括：光源部件，該光源部件沿厚度方向具有相對的第一面和第二面；LCD模組，該LCD模組沿厚度方向具有相對的第一面和第二面，該LCD模組的第二面貼合於該光源部件的第一面設置；透光蓋板，該透光蓋板沿厚度方向具有相對的第一面和第二面，該透光蓋板的第一面適於與待採集物體相接觸，該透光蓋板的第二面朝向該LCD模組的第一面設置；感測器部件，用於採集自該透光蓋板反射的入射光。藉由本發明提供的方案能夠在LCD螢幕下實現基於全反射原理的圖像採集，優化成像效果，提高成像清晰度。
Patent TW-I762066-B (TW)
Title: Food interactive management system, method and readable storage medium
Inventor: CHIANG YAMEI
IPC: G06F16/9535
Filed: 2020-12-04
Granted: 2022-04-21
Abstract: A food interactive management system, method and readable storage medium is provided. The system can judge whether the fitness data curve is up to standard by measuring the user's physical fitness data, user's behavior and commodity purchase situation for many times. Through the interaction of reward, increasing the intensity and frequency of sports types and card competition, the system can stimulate users to understand diet health and maintain body posture, and cooperate with stores to increase consumers' purchase desire. This application can be widely used in app developers and healthy food industry, so that users can understand the caloric intake of food through the happy process of participating in the game, so as to form a correct and balanced eating habit.
Patent TW-I777355-B (TW)
Title: Reflective type blankmask and photomask for euv
Inventor: SHIN CHEOL
IPC: G03F7/20
Filed: 2021-01-07
Granted: 2022-09-11
Abstract: Disclosed is a blankmask for EUV includes a substrate, a reflection 
film that is stacked on the substrate; and an absorbing film that is stacked on the reflection film. The reflection film has a structure in which a pair including a first layer made of Ru or a Ru compound in which one or more of Mo, Nb, and Zr are added to Ru, and a second layer made of Si is stacked plural times. Interdiffusion between the respective layers constituting the reflection film is suppressed.
Patent TW-I763279-B (TW)
Title: 半導體記憶裝置
Inventor: MURAYAMA AKIYUKI
IPC: G11C7/18
Filed: 2021-01-27
Granted: 2022-05-01
Abstract: 本發明之實施方式提供一種可靠性高之半導體記憶裝置。
        本發明之實施方式之半導體記憶裝置具備：第1記憶體串，其包含第1記憶胞；第2記憶體串，其包含第2記憶胞；第1位元線，其連接於第1記憶體串；及第2位元線，其連接於第2記憶體串。於第1編程動作中，向第1位元線及第2位元線供給第1位元線電壓。於第2編程動作中，向第1位元線及第2位元線供給大於第1位元線電壓之第2位元線電壓或大於第2位元線電壓之第3位元線電壓。於第3編程動作中，向第1位元線供給第2位元線電壓，向第2位元線供給第3位元線電壓。於第4編程動作中，向第1位元線供給第3位元線電壓，向第2位元線供給第2位元線電壓。
Patent TW-I768688-B (TW)
Title: Mini radio frequency connector
Inventor: LIN HSIEN CHANG
IPC: H01R13/514
Filed: 2021-01-29
Granted: 2022-06-21
Abstract: The present invention provides a small radio frequency connector capable of connecting an external connector and a printed circuit board. The small radio frequency connector includes a rubber core, a terminal module and a conductive organic layer. The rubber core forms an accommodating space, a first opening and a second opening. The wire module includes a terminal, a shell, a sleeve and a fixing seat. The terminal has a first contact part, a connection part and a second contact part. The shell covers the connecting portion and exposes the first 
contact portion and the second contact portion. The sleeve is combined with the housing at the first contact portion to cover the first contact portion. The sleeve is disposed in the accommodating space through the second opening. The fixing seat is combined with the housing at the second contact portion to fix the second contact portion. The conductive organic layer is formed on the shell and part of the tube by a mold.
Patent TW-I775307-B (TW)
Title: Semiconductor device and operation method thereof
Inventor: LIN ZONG-MIN
IPC: G06F9/445
Filed: 2021-02-04
Granted: 2022-08-21
Abstract: A semiconductor device includes a debug port, a first access port, a second access port, a first processing unit, a second processing unit and an embedded emulator unit. The first access port is coupled to the debug port. The second access port is coupled to the debug port. The first processing unit is coupled to the first access port. The second processing unit is coupled to the second access port. The embedded emulator unit is coupled to the debug port, the first processing unit and the second processing unit. The first processing unit generates a debug instruction to access the embedded emulator unit, such that the embedded emulator unit generates a debug signal. The debug signal is outputted to the second processing unit through the debug port and the second access port, so as to perform a debug operation on the second processing unit.
Patent TW-I765566-B (TW)
Title: 引擎控制裝置之控制方法及跨坐型車輛
Inventor: NIWA JUNYA
IPC: F02D45/00
Filed: 2021-02-08
Granted: 2022-05-21
Abstract: 本發明提供一種可將ACG啟動馬達之旋轉狀態高效率地傳遞至分割成2個引擎控制裝置的引擎控制裝置、引擎控制裝置之控制方法及跨坐型車輛。
本發明之引擎控制裝置包含有：第1控制裝置(70)，其對被直接連接於引擎(E)之曲軸(C)的ACG啟動馬達(50)進行控制；及第2控制裝置(80)，其對燃料噴射裝置(90)進行控制；且將第1控制裝置(70)連接至檢測ACG啟動馬達(50)之旋轉狀態的曲柄角感測器(40)。第2控制裝置(80)構成為自第1控制裝置(70)接收曲柄角感測器(40)之輸出信號。第1控制裝置(70)係於ACG啟動馬達(50)正轉時，將曲柄角感測器(40)之輸出信號利用脈衝信號傳送至第2控制裝置(80)，且於ACG啟動馬達(50)反轉時，將曲柄角感測器(40)之輸出信號轉換為平坦之信號而進行傳送。
Patent TW-I794760-B (TW)
Inventor: CIN DAVID JONATHAN
IPC: A43B13/16
Filed: 2021-03-03
Granted: 2023-03-01
Abstract: 本發明提供一種鞋類製品的鞋底結構，鞋底結構可包含具有底部壁及周邊壁的鞋底組件，周邊壁自底部壁向上延伸且部分地包圍底部壁上方的空間。鞋底結構可具有包含巢套於空間中的發泡核的中底。鞋底組件的周邊壁可安置於發泡核的側表面外部。鞋底組件可附接至側表面的第一部分，且自側表面的第二部分剝離。側表面的第二部分可安置於第一部分與底部壁之間。
Patent TW-I768785-B (TW)
Title: Universal serial bus interface circuit
Inventor: YANG YA CHIH
IPC: G06F13/20
Filed: 2021-03-24
Granted: 2022-06-21
Abstract: A universal serial bus (USB) interface circuit, configured on the motherboard and including a chipset, a universal serial bus driver, Peripheral Component Interconnection Express (PCIe) driver, a first USB slot, a second USB slot and a bridge, is provided. The USB driver is coupled to the chipset and receives USB signals. The PCIe driver is coupled to the chipset and receives PCIe signals. The USB slot is coupled to the USB driver. The bridge is coupled to the second USB slot and the PCIe driver, and is used to convert USB signals from the second USB slot into the PCIe signals and then transmit it to the PCIe driver.
Patent TW-I804841-B (TW)
Title: 安全插座之結構
Inventor: SUN SHIH CHIANG
IPC: H01R13/703
Filed: 2021-03-31
Granted: 2023-06-11
Abstract: 本發明提供一種安全插座之結構，其係將一繼電器耦接一插座銅片組，並於該插座銅片組對應設置用於感測一插頭銅片組位置之一感測件，當該插頭銅片組插入或拔出該插座銅片組時，該感測件發出訊號至一控制模組，該控制模組依感測件之訊號對應開啟該繼電器，控制該插座銅片組傳輸電能至該插頭銅片組。
Patent TW-I764673-B (TW)
Inventor: HOSODA YUJI
IPC: A47K1/02
Filed: 2021-04-14
Granted: 2022-05-11
Abstract: 本發明旨在提供往照明部之前方行進的光之量易增加的箱櫃及照明裝置。本發明之箱櫃包含箱櫃本體(1)、複數之門(2)、及照明單元(3)。箱櫃本體(1)具有分隔成複數之收納空間(10)的分隔壁(15)。照明單元(3)配置於分隔壁(15)之前端部並於上下方向延伸。照明單元(3)具有具出光部(40)並於上下方向延伸之照明部(4)、及覆蓋照明部(4)之前方的照明蓋(5)。照明蓋(5)具有位於照明部(4)之前方的前面部(51)、側面部(52)。側面部(52)於左右方向拉開距離且從前面部(51)分別往後方延伸而位於照明部(4)之左右側邊。前面部(51)之透光度高於側面部(52)之後端部的透光度。照明裝置具有照明單元(3)。
Patent TW-I778576-B (TW)
Title: 凝固層的變動檢測方法和高爐操作方法
Inventor: ICHIKAWA Kazuhira
IPC: C21B5/00
Filed: 2021-04-14
Granted: 2022-09-21
Abstract: 本發明提供一種能夠早期檢測凝固層的變動的凝固層的變動檢測方法及使用該方法的高爐操作方法。本發明的凝固層的變動檢測方法為使用特定期間內向高爐爐下部的熔鐵供給的熱量與出鐵的熔鐵的熱量對高爐爐下部的凝固層的變動進行檢測。
Patent TW-I771039-B (TW)
Title: 高光轉換效率之led驅動系統
Inventor: WANG SHUN-ZHONG
IPC: H05B45/325
Filed: 2021-06-04
Granted: 2022-07-11
Abstract: 一種高光轉換效率之LED驅動系統，其具有：一全橋式開關電路、一電容-電感串聯電路、一變壓器、一第一二極體、一第二二極體、一第一電感、一第二電感、一輸出電容、一LED負載、一電壓回授電路、一控制單元及一閘極驅動器，其中，該控制單元係用以依一調光命令電流進行一調光操作使該LED負載之匯集電流之一平均電流等於該調光命令電流，該調光操作包括：在五段電流區間(0,I
         1 ]、(I
         1 ,I
         2 ]、(I
         2 ,I
         3 ]、(I
         3 ,I
         4 ] 及(I
         4 ,I
         5 ]中找出該調光命令電流之一所屬區間，以致能五個PWM信號組合(PWM1)、(PWM1,PWM2)、(PWM2,PWM3)、(PWM3,PWM4)、(PWM4,PWM5)中之一選定PWM信號組合，及依一電流回授信號和該調光命令電流之差值進行一負回授控制計算程序以產生一責任週期D以決定該選定PWM信號組合內之各PWM信號之脈衝寬度，D為一不大於1之非負實數。
Patent TW-I785764-B (TW)
Title: 3d and flash memory device and method of fabricating the same
Inventor: HUNG MIN-FENG
IPC: H01L27/11524
Filed: 2021-08-30
Granted: 2022-12-01
Abstract: A 3D AND flash memory device includes: a gate stack structure, disposed on a dielectric substrate, and including multiple gate layers and multiple insulating layers alternately stacked with each other; a channel pillar penetrating through the gate stack structure; a first conductive pillar and a second conductive pillar disposed in the channel pillar and penetrating the gate stack structure, wherein 
the first conductive pillar and a second conductive pillar are separated from each other and each connected to the channel pillar; a charge storage structure disposed between the gate layers and a sidewall of the channel pillar; and a protective cap covering at least a top surface of the channel pillar to isolate the first conductive pillar from a top gate layer of the multiple gate layers, and isolate the second conductive pillar from the top gate layer.
Patent TW-I777769-B (TW)
Title: Vehicle and method for locking the same
Inventor: WALL KENNETH EDWARD
IPC: H04W4/80
Filed: 2019-08-23
Granted: 2022-09-11
Abstract: The present disclosure relates to apparatus and methods for locking and/or unlocking a vehicle based on a location of a mobile device associated with the vehicle. In one embodiment, a processor in a vehicle analyzes a position of a mobile device relative to the vehicle and allows the vehicle to be unlocked when the mobile device is determined to be approaching the vehicle.
Patent TW-I783688-B (TW)
Title: 防塵護蓋之補強結構
Inventor: WANG ZHOU-YONG
IPC: B23Q11/08
Filed: 2021-09-17
Granted: 2022-11-11
Abstract: 一種防塵護蓋之補強結構，尤特指防塵護蓋係由複數個呈ㄇ型的蓋板主體由小至大的所疊加重置而成，該蓋板主體一體成型設有接合板，作為接合立板之用，該立板係由左、右兩片的第一板面與中間一片的第二板面所組合成一體，該第一板面對應於該第二板面處設有一縫隙，作為該第二板面嵌設結合之用，再透過焊接方式結合增進強度，該第一板面與該第二板面對應處彎折設有第一、第二補強部，或在該第一、第二補強部彎折增設第三補強部，藉以避免因為部分該蓋板主體承靠處的腳高過高，而導致容易晃動偏擺的情形發生，確保該蓋板主體伸展收合定位之品質穩定性，為其特徵者。
Patent TW-I813074-B (TW)
Title: 用於測試積體電路半導體晶圓的多個電路之系統及方法
Inventor: KABBANI SAMER
IPC: G01R31/28
Filed: 2021-11-18
Granted: 2023-08-21
Abstract: 一種用於測試一積體電路半導體晶圓之電路之系統包括：一測試器系統，其用於產生用於輸入至該等電路之信號且用於處理來自該等電路之輸出信號以用於測試該晶圓；及一測試堆疊，其耦接至該測試器系統。該測試堆疊包括：一晶圓探針，其用於接觸該晶圓之一第一表面且用於探測該晶圓之該等電路中之個別電路；一晶圓熱中介件(TI)層，其可操作以接觸該晶圓之一第二表面且可操作以選擇性地加熱該晶圓之區域；及一冷板，其設置於該晶圓TI層下方且可操作以冷卻該晶圓。該系統進一步包括一熱控制器，該熱控制器用於藉由控制該冷板之冷卻且藉由控制該晶圓TI層之選擇性加熱來選擇性地加熱及維持該晶圓之該等區域之溫度。
Patent TW-I792747-B (TW)
Inventor: TSENG GUO-FU
IPC: G06F9/312
Filed: 2020-01-02
Granted: 2023-02-11
Abstract: A method for performing pipeline-based accessing management in a storage server and associated apparatus are provided. The method includes: in response to a request of writing user data into the storage server, utilizing a host device within the storage server to write the user data into a storage device layer of the storage server and start processing an object write command corresponding to the request of writing the user data with a pipeline architecture of the storage server; utilizing the host device to input metadata corresponding to the user data into at least one pipeline within the pipeline architecture; and utilizing the host device to cache the metadata 
with a first cache module of the pipeline, for controlling the storage server completing the request without generating write amplification of the metadata, wherein the first cache module is a hardware pipeline module outside the storage device layer.
Patent TW-I804210-B (TW)
Title: 恆溫槽型壓電振盪器
Inventor: KOJO TAKUYA
IPC: H03B5/32
Filed: 2022-02-25
Granted: 2023-06-01
Abstract: 本發明提供一種恆溫槽型壓電振盪器，即，OCXO(1)。OCXO(1)中，核心部(5)以密閉狀態被封入隔熱用的封裝體(2)的內部。核心部(5)包含振盪器IC(51)、晶體振動子(50)、及發熱器IC(52)，並由核心基板(4)支撐在封裝體(2)中。核心基板(4)通過非導電性黏合劑(7)與封裝體(2)機械性地接合。核心部(5)與封裝體(2)之間通過使用了電線(6a、6b)的打線接合實現電連接。
Patent TW-I802298-B (TW)
Inventor: PAN YUNG-TAI
IPC: G03B17/14
Filed: 2022-02-25
Granted: 2023-05-11
Abstract: 本發明提供一種影像擷取裝置，包括殼體、攝像組件、調整件、第一止擋結構以及第二止擋結構。攝像組件配置於殼體內，且部分攝像組件露出於殼體。調整件連接於攝像組件。調整件相對殼體進行轉動，進而帶動攝像組件轉動而於橫拍模式與直拍模式之間切換，且調整件具有抵靠結構。第一止擋結構與第二止擋結構配置於殼體與調整件之間，且第一止擋結構與第二止擋結構分別位於不同的位置。當調整件帶動攝像組件轉動而切換至橫拍模式時，抵靠結構定位於第一止擋結構，當調整件帶動攝像組件轉動而切換至直拍模式時，抵靠結構定位於第二止擋結構。
Patent TW-I802305-B (TW)
Inventor: CHANG CHIA-HAO
IPC: H01L29/06
Filed: 2022-03-03
Granted: 2023-05-11
Abstract: This disclosure provides a semiconductor structure and a method for manufacturing buried field plates. The semiconductor structure includes a substrate, multiples of buried field plates, and a gate. The substrate incudes a first side and a second side opposite the first side. The buried field plates include a conductive structure and an insulation structure around the conductive structure. The conductive structure incudes many portions disposed in a direction perpendicular to the first side of the substrate, and the conductive structure has different widths in a direction parallel to the first side of the substrate.
Patent TW-I796182-B (TW)
Title: Chip and chip test method
Inventor: THIS INVENTOR HAS AGREED TO WAIVE THE ENTITLEMENT TO DESIGNATION
IPC: G06F11/26
Filed: 2022-03-25
Granted: 2023-03-11
Abstract: A chip and a chip test method are provided. The chip includes a transmitter circuit and a test circuit. The transmitter circuit includes a signal transmission unit and a first signal bump. The first signal bump is coupled to the signal transmission unit. The test circuit is coupled to a circuit node between the signal transmission unit and the first signal bump. The test circuit includes a first resistor, a unit gain buffer, and an analog-to-digital converter. A first terminal of the first resistor is coupled to the circuit node. A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer. An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.
Patent TW-I805324-B (TW)
Inventor: LEE DA YE
IPC: G02B9/62
Filed: 2022-04-14
Granted: 2023-06-11
Abstract: An imaging lens system includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens disposed in order from an object side, wherein the imaging lens system satisfies conditional expressions of 0.23 mm /°＜ D1/HFOV ＜ 0.35 mm /° and 0.15 ＜ ImgH/TTL ＜ 0.20, where D1 is an effective diameter of the first lens, HFOV is a field of view of the imaging plane in a horizontal direction, ImgH is a height of the imaging plane, TTL is a distance from an object-side surface of the first lens to the imaging plane.
Patent TW-I806641-B (TW)
Title: Memory device and operating method thereof
Inventor: WANG WEI-CHEN
IPC: G11C16/10
Filed: 2022-06-02
Granted: 2023-06-21
Abstract: A memory device is disclosed, which includes a memory array for storing a plurality of vector data. Each of the vector data has an MSB vector and a LSB vector. The memory array includes a plurality of memory units, each of the memory units has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, and the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector of each vector data is executed with a first group-counting operation, 
the LSB vector of each vector data is executed with a second group-counting operation. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
Patent TW-I796238-B (TW)
Title: Cycling performance level classification analysis system
Inventor: CHEN CHIEN YUAN
IPC: A63B69/16
Filed: 2022-06-09
Granted: 2023-03-11
Abstract: A cycling performance level classification analysis system includes an artificial intelligence classification analysis module, a bicycle apparatus, a classification knowledge rule module and a cyclist information module. The classification knowledge rule module transmits a classification test task rule including a track information to the artificial intelligence classification analysis module and the bicycle apparatus. The bicycle apparatus performs the classification test task rule and collects a sport sensing information which is sensed to transmit the sport sensing information to the artificial intelligence 
classification analysis module. The cyclist information module transmits a cyclist basic information and a track historical riding information to the artificial intelligence classification analysis module. The artificial intelligence classification analysis module analyzes the sport sensing information, the track information, the cyclist basic information and the track historical riding information to generate a cycling sport performance level analysis result.
Patent TW-I815722-B (TW)
Title: System and method for pre-judging situation of server before test according to server log data
Inventor: LIAO HUIHUI
IPC: G06F11/277
Filed: 2022-11-07
Granted: 2023-09-11
Abstract: A system and method is provided for pre-judging situation of a server before test according to a server log data. In the system and method, before executing a test flow, when an abnormal character string data comparison unit compares a configuration text of the server log data includes at least one abnormal-related character string, the server is defined as an abnormal server, which does not comply with a test requirement. Moreover, when a monitoring data comparison unit compares at least one monitoring data of the server log data being out of the at least one respective requirement range for test, the server is also defined as the abnormal server, and further more an abnormal-information generation module generates an abnormal information when the server is finally determined as the abnormal server before executing the test flow.
Patent ZA-200210236-B (ZA)
Title: Paper towel.
Inventor: HAUKE HARALD
IPC: A47K7/00
Filed: 2002-11-21
Abstract: Paper towel (1) has three layers (2,3,4), two outer layers (3,4) with inner layer (2). Outer layers are embossed (6) with raised (7) and hollow (8) areas and inner layer is printed (5). Layers are partially transparent and adhered by tinted glue (9) applied to raised areas (7) which also provides change in appearance of color of print beneath.