Patent GB-1145661-A (GB)
Title: Electronic calculators
Inventor: CAROUSSOS PANAYOTIS
IPC: H03M7/24
Filed: 1966-03-02
Abstract: 1,145,661. Electric digital calculators; fixed or floating point representation. CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE. 2 March, 1966 [2 March, 1965], No. 9208/66. Heading G4A. An electronic arithmetic calculator may perform calculations on numbers expressed in fixed and/or floating point representation and produces results in either representation according to certain predetermined conditions. An initial check is made to see if both numbers to be operated on are expressed in the same notation, if not, the fixed point number is converted to floating point representation and the calculation is performed in floating point. If both are in floating point, the calculation is performed in floating point whereas, if both are in fixed point, the result is expressed in fixed point unless overflow occurs or greater accuracy can be achieved in floating point. Floating point numbers may be converted to fixed point numbers when the value of the exponent is such that this can be done. 35-bit words are described in which for fixed point numbers the decimal point is taken to occur between bits 16 and 17 whereas for floating point numbers, bits 1-8 store the exponents and 9-32 the mantissa. In both cases, bit 33 is used to indicate overflow condition, bit 34 the sign and 35 the notation (binary 1 for floating point and 0 for fixed point). In the adding circuit of Fig. 1 (not shown), two fixed point numbers to be added are initially stored in shift registers (rl and r2). They are added serially bit-by-bit (during cycle t1) in adder (A), the result passing by way of OR-gate (D) to shift register (r3). The state of the overflow bit 33 is checked as it passes through digit 34 position of register r3 whereby bi-stable element (5) is either set or reset. If set (S=1), indicating overflow, then during cycle t2 the number is merely recirculated within register r3, and a microprogramme is called for to convert the number to floating point representation. If reset (S = 0), then during cycle t2 the sum in register (r3) is transferred by way of AND-gate (C2) to register (r1). In the multiplying circuit of Fig. 2, two fixed point operands are initially stored in shift registers r1 and r2. The result of the multiplication operation is transmitted serially bit-by-bit to two linked shift registers r3 and r4. AND gate C1 is enabled during digit times 14-29 of cycle t2 to check if any of the bits 14-29 (Group I) of register r3 are significant. If not, then the bits from bit 17 of r4 to 13 of r3 (Group III) are transferred to r1 as the result. If any of the checked (Group I) bits are found to be significant then signal #m is called for through OR gate D1 and flip-flop #m to cause the multiplication to be repeated in floating point. A switch B is provided whereby, when in the position indicated, the significance of bits 1-16 (Group II) of r4 and of bits 6-13 (Group VI) of r3 are respectively checked by appropriately timed enablement of AND-gates C2 and C3. If bits of Group VI are all zero and there are some bits of Group II equal to 1, then #m = 1 is generated and a recalculation of the product in floating point is called for whereby greater relative accuracy may be attained. If any of the Group VI bits are equal to 1 then the generation of #m is suppressed. In its other position, switch B is rendered inoperative.