Patent GB-1015518-A (GB)
Title: Selective data transfer system
Inventor: BUCK ROBERT DANIEL
Filed: 1964-06-24
Abstract: 1,015,518. Electric selective signalling. INTERNATIONAL BUSINESS MACHINE CORPORATION. June 24, 1964, No. 26045/64. Heading G4H. [Also in Division H4] An input system for data processing apparatus comprises means to provide data signals in a plurality of parallel trains, transfer means normally operative on termination of each train to transfer signals corresponding to the data represented by the train to the dataprocessing apparatus, and control means operaative on termination of one of said trains no later than the others to prevent transfer of signals corresponding to any other train which is already longer than said one train. The system is used in radar systems of the type in which three radar signals are transmitted successively, having fixed, linearly decreasing and linearly increasing frequencies respectively. The echoes of the variable frequency signals are separately combined with local oscillator signals having the same kind of frequency variation as the transmitted signal to produce intermediate frequencies which are quantized using banks of crystal filters with contiguous pass-bands and then fed to a digital computer for comparison with intermediate frequencies derived from fixed frequency echoes, to determine the target range. In fact, each variable frequency echo is separately combined with a number of local oscillator signals having slightly different rates of change of frequency and each resulting intermediate frequency (one per local oscillator) is fed to a respective filter bank. All the filter banks relating to a given variable frequency echo are scanned simultaneously to produce a pulse train from each bank, presence or absence of a pulse in a particular position in the train indicating whether or not the corresponding filter is producing an output. Each filter bank gives an indication of the target and the purpose of the invention is to choose the most reliable of these indications to be fed to the computer. In Figs. 1 and 2 (not shown), pulse trains from three filter banks relating to the same echo arrive at L1, L2 and L3 respectively (Fig. 1, not shown, left). In each pulse interval, five timing pulses P1 to P5 (Figs. 1, 2, not shown), are produced by conventional means not shown. The pulses in each train are counted in a corresponding counter consisting of flip-flops F5 to F8 and gates G9 to G11 in the case of L1 for example (Fig. 2, not shown), Each train has associated control circuitry comprising gates and flip-flops (F1 to F4 in the case of L1 for example, Fig. 1, not shown), which ensure that each count is read out (and the counter reset) when the train ends (i.e. when a pulse period without a pulse therein occurs), except when counts end in two or more counters at the same time when only the last count to begin is read out, the other completed counts being deleted. Uncompleted counts which began no later than the completed count are also deleted whenever a completed count is read out. The general purposes of the flip-flops F1 to F4 (Fig. 1, not shown), and their counterparts in the control circuitry for the other trains are respectively to record the presence of a pulse in the current pulse interval, to prevent the read-out of a count when set as a consequence of the read out of another related count, to indicate that a count is in progress, and to indicate whether any count has begun more recently than another. As the filter banks are scanned, the timing pulses P1 (Fig. 2, not shown), are fed to a counter C1 (Fig. 2, not shown), and when a count of one of the other counters is read-out as described (into flip-flops F19 to F22 (Fig. 2, not shown), the count (indicating the filter reached) of counter C1 (Fig. 2, not shown) is passed to flip-flops F9 to F18 (Fig. 2, not shown), the contents of which are passed to the computer and the flip-flops reset, by timing pulse P5 Fig. 2, (not shown).