Patent GB-1309754-A (GB)
Title: Electrical signalling systems
IPC: H04L5/02
Filed: 1969-07-30
Abstract: 1309754 Digital transmission systems; coding and decoding PLESSEY TELECOMMUNICATIONS RESEARCH Ltd 24 July 1970 [30 July 1969] 38273/69 Heading H4P A digital transmitter in a code division multiplex system has a first means sampling each digit of an input signal, a coding means responsive to the sampling for producing a first plurality of multi-level signals each representing one of a plurality of digit values from each successive group, at least one orthogonal transformation matrix for producing a second plurality of multi-level signals the level of each of which is dependent on all of the first plurality, and a second sampling means responsive to the matrix for producing sequential signals from the second plurality to modulate a carrier signal for transmission. Synchronous orthogonal multiplexing of fifteen quaternary base band signals may be employed together with a sixteenth not used for data and as the fifteen are orthogonal to this they contain no D.C. component regardless of their element values. It is stated that once a receiver is correctly synchronized, synchronization is maintained regardless of the data signal transmission and that the system is fully transparent in the sense that any data signal may be transmitted. Multiplexing and demultiplexing is achieved via resistor matrices and only one process of modulation and demodulation is involved in a one-way link. The transmission rate may be doubled by transmitting two modulated carrier signals of the same frequency but in phase quadrature. At the transmitter the signals comprising thirty input binary elements in a 100 band period are fed into a store 16 where they are sampled by thirty corresponding pulses from generator 18 and passed into a fifteen pair code and store circuit and then transferred into a buffer store 20, where they are held until the end of the next 100 bd period, at a negative going transition of a timing waveform (B, Fig. 2, not shown), then passed into a transformation matrix 22 through terminals G2-G6, a constant 3 volt potential being applied to terminal G1. A sequential sampler 24 acting as a distributer is gated by a 100 h.z. signals derived through a ¸16 circuit 12 from a 1600 h.z. generator 10 so that each 100 bd period is divided into sixteen, so that sixteen separate signals each comprising a negative pulse time displaced from its neighbour the remainder of the 100 bd period being positive are directed into sixteen lines. Resultant signals are passed to a switched inverter 28 synchronized with generator 10 through a phase delay arrangement 26. The switched inverter only inverts when signals at J are negative. The output is passed through an amplitude limiter 30 and band pass filter 32 to a line.  At the receiver signals are passed through a band pass filter 40 and automatic gain amplifier 42 to a phase locked 1600 h.z. phase locked oscillator where clock pulses are extracted. Where frequency deviation is small, a tuned circuit followed by an amplifier limiter may be used. Signals are passed through a switched inverter 46, which only inverts when clock pulses are negative, followed by a low pass filter 48 and passed to another phase locked oscillator 50 which is automatically brought into correct phase relation when a signal is first received, the output being divided by sixteen and passed through sixteen terminals T which form sampling pulses for signal Q, the result being passed into store 58 until the next 100 bd period and then fed to matrix 60 and passed out of output terminals V2-V16. An error counting circuit 78 has a settable threshold value which when exceeded sends a request sync. signal to the transmitter. Output of matrix 60 is fed to a buffer store 80 having separate bi-stable circuits each giving an output of the same sign as the input, for each of the terminals V2-V16. A level detector 82 has fifteen detectors giving output signals the same as the input, biased by - 2 volts, and passed to another buffer store 84 similar to 80 both of which outputs are passed sequentially to a sampler 90 where the thirty signals are sampled sequentially, the reconstituted signal being passed out over line Z. Another similar arrangement for thirty multiplexed channels operating at 80 bd is described in connection with Figs. 5 and 6 (not shown). A mathematical treatment is given in the Specification.