Patent GB-846100-A (GB)
Title: Improvements in or relating to digital computer circuits
IPC: G06F7/552
Filed: 1956-10-31
Abstract: 846,100. Digital electric calculating-apparatus. PHILCO CORPORATION. Oct. 31, 1956 [Oct. 31, 1955], No. 33229/56. Class Class 106 (1). General.-The computer arithmetic unit described comprises binary registers 10, 12, 14, 16, 18 and 20, Fig. 1A, each comprising bistable elements (1-20). The register elements are connected in parallel by multiple gates represented by triangles, the apex of each triangle indicating the direction of possible transfer of " 1 " digits and whether there is a one-digit left or right shift ; e.g. gate 26 enables the " 1 " digits stored in elements 1-19 of output register 16 to be copied into elements 1-19 of input register 10 (no shift) while gate 36 enables the " 1 " digits in elements 1-19 of accumulator " master rank " register 14 to be copied into elements 2-20 of accumulator " slave rank " register 12, i.e. to be transferred with a right-shift. Information may be entered in register 10, e.g. from a memory system, through gate 22, and may be read out from register 16 through gate 60. The registers 10, 12, 14, 16 are each designed to store a 19-digit binary fraction in positions 2-20 with a sign S in position 1 (" 0 " for "+"), negative numbers being represented by the 2's complement. Auxiliary bistable elements 12a, 14a (Fig. 1B, not shown), indicated as position 0, are associated with the " sign " elements (position 1) of the accumulator registers. Registers 10 and 12 are connected directly to a parallel addersubtracter 40 whose output is connected through gate 44 to register 14. The " slave rank " and " master rank registers 18 and 20 form a "step counter which registers a single " 1 " only, this " 1 being shifted along, e.g. to count the number of cycles of a multicycle operation such as multiplication. Each cycle of any operation comprises a sequence of steps controlled by a multivibrator chain (Fig. 1c, not shown). An operation is selected by supplying a signal to a corresponding lead from programme control circuits (not described in detail), these leads, together with the multivibrator outputs, being connected to a gating network (Fig. 1C, not shown), which provides control signals for opening the appropriate register transfer gates in the required sequence. A register is cleared by supplying a control signal to the associated clearing circuit 10c- 20c. An overflow-sensing circuit (Fig. 1B, not shown), checks whether an overflow occurs, e.g. during addition or subtraction. Modifications are referred to in which the sequence-control multivibrator chain is replaced by tapped delay lines and in which the step counter operates in a binary code and is coupled to a decoder. Reference is made also to a floating- point computer. Circuit details; adder-subtracter.- The circuits employed consist primarily of transistor bistable circuits as disclosed in Specification 831,265 and gates as disclosed in Specification 831,266. Fig. 2 shows the nth bistable element of each of the registers of Fig. 1A, together with the associated gates, and the nth stage of the adder-subtracter 40; all these circuits may be mounted on a single card, so that an arithmetic section with a capacity of any number of digits may be assembled by taking the corresponding number of cards. Each bistable circuit comprises a pair of cross-coupled transistors, such as 404, 406 for register 10; when such circuit registers a " 1," transistor 404 is conducting and transistor 406 is cut off, so that its collector is at a high potential. A transfer gate, such as 26, comprises a transistor in which current flow in the emitter-collector path is controlled by a signal applied to the base. The addersubtracter stage comprises a network of transistor gates with series-connected emittercollector paths, the base potentials being controlled by complementary signals on lines 40a<SP>1</SP>, 40a<SP>11</SP> from register 10, lines 40b<SP>1</SP>, 40b<SP>11</SP> from register 12 and " 1 " and " 0 " carry lines 40i, 40j. The adder-subtracter is selectively conditioned to add or subtract by signals on lines 40e, 40d from opposite sides of a bistable circuit (Fig. 1B, not shown). The carry output is applied to the next lower stage over " 1 " and " 0 " lines 40f<SP>1</SP> 40f<SP>11</SP> and the sum output is applied to transistor gate 44. The multivibrator sequence - control chain (not shown) also comprises transistor circuits; one of the multivibrators provides a delay to allow for carry ripple time in the adder-subtracter, and is by-passed during operations in which addition or subtraction does not occur. Operations.-The operations particularly described, viz. the four rules, square-rooting, left and right shift and determining the sign and absolute magnitude of a number, are explained separately below. Addition and subtraction.-The number in input register 10 is added to or subtracted from the number in accumulator register 14 and the result placed in register 14. The single-cycle sequence comprises the following steps: clearing register 16; clearing register 12; copying the number in register 14 into 12; clearing register 14; and entering the output of the adder-subtracter into register 14, this result number being also copied into output register 16. If an overflow is detected, the register 14 receives, not the output of the adder-subtracter, but the original number now in register 12, and the computer is stopped. Multiplication. This is performed by repeated addition of the multiplicand in the input register 10 under control of the digits of the multiplier in register 16, the product being built up in accumulator register 14. Initially, a " 1 " is inserted at the right-hand end (position 20) of step counter register 20, for counting 20 cycles, the adder-subtracter is set to add, and the multiplier sign digit is set up on an auxiliary bistable circuit (not shown). The sequence during each of the first 19 cycles comprises the following steps: clearing the slave rank registers 12, 18; copying the " 1 " in register 20 into register 18, and entering into register 12 a rounding-off " 1 " digit in position 2 during the first cycle, and the contents of register 14, via right shift gate 36, during subsequent cycles; clearing the master rank registers 14, 20; copying the " 1 " in register 18 into register 20 via left shift gate 70 and, if the multiplier digit selected by the " 1 " in 18 through gate 62 is " 1," entering the output of the adder-subtracter into register 14, but if the multiplier digit is " 0 " copying into register 14 the contents of register 12. Thus at the end of each cycle, the " 1 " in register 20 is left-shifted and the new sum of partial products in register 14 is right-shifted by one digit. During the last cycle, the sequence is similar except that the adder-subtracter is set for subtraction (since the sign digit of the multiplier is being dealt with), and register 16 is cleared and then receives the final product copied from register 14. Division.-The division calculation may be preceded by an overflow checking operation controlled by a manual switch; if the check indicates that the divisor in register 10 is less in absolute value than the dividend in register 14, so that overflow would occur, the computer is stopped. The calculation is begun with a " 1 " in position 2 of register 20, and comprises 19 cycles. The sequence in which the registers are cleared and operated in each of these cycles is generally similar to that used in multiplication, but the " 1 " in step counter register 20 is right-shifted and the dividend or partial remainder in register 14 is left-shifted. The sign of this number is compared with the sign of the output from adder-subtracter 40 which is set to subtract or add according to whether these signs are alike or not. If the adder-subtracter is already set to subtract and the signs are alike or if it is set to add and the signs are different, indicating that the divisor is less than the dividend or partial remainder, the " 1 " in the step counter is transferred to the corresponding digit position in register 16 and the output of the adder-subtracter is passed to register 14 to form a new partial remainder. The quotient is built up in this way in register 16 and, during the final cycle, is copied in register 14. Square rooting; trigonometrical functions.- The method employed for finding the square root of the number in register 14 is similar to the usual long-hand method; a trial root is built up in register 16 and is effectively doubled at each cycle and a further " 1 " digit is added to form a new trial divisor in register 10. Initially, a " 1 " is inserted in position 2 of register 20 for counting 19 cycles. the addersubtracter is set to subtract, the sign digit in register 14 is set to " 0 " (since the computer deals only with real numbers) and register 16 is cleared. Each cycle comprises the following steps: clearing the registers 10, 12 and 18; copying the " 1 " in register 20 into register 18 and also entering this " 1 " (right-shifted), together with the contents of register 16, into register 10, and copying the number in register 14 into register 12 (with a left shift after the 1st cycle); clearing registers 14 and 20; copying the " 1 " in register 18 into register 20 with a right shift and, if the difference output of the adder-subtracter is positive, entering this difference in register 14 and copying the " 1 " in register 18 into the corresponding position in register 16, but, if this difference is negative, copying into register 14 the contents of register 12. During the last cycle, the root in register 16 is copied into register 14. It is explained in the Specification how e.g. the value of sin # can be obtained, where cos # is known, by squaring, complementing and square rooting. Left and right shift.-The number in accumulator register 14 is shifted left or right by employing gate 30 or 36, the number of cycles, and therefore the number