Patent ES-352769-A1 (ES)
Title: Improvements in or relating to communication systems
IPC: H04B14/06
Filed: 1968-04-06
Abstract: In a TDM communication system utilizing delta modulation, the duration of each frame (exchange cycle) is proportional to the number of active stations. A recirculating type memory contains the address of each pair of stations in communication (separate time slots are used for Go and Return signals) and on the appearance of each pair of addresses the corresponding stations are interrogated to determine whether or not a delta modulation " 1 " bit viz a positive change in amplitude of a speech signal, is present. If there is a " 1 " bit the cycle is interrupted for 10 nanoseconds so that this bit can be transferred between the stations. If a " 0 " bit viz. a negative change in amplitude of a speech signal, is present, however, the cycle is not interrupted and at the end of the 3 nanosecond interrogation period the next pair of addresses are retrieved. Transmission quality increases with a decrease in the number of active stations due to,the increased sampling rate. Particular description, first embodiment, Fig. 2. - It is assumed that stations 10 and 10n are in communication and that their addresses are written in two time slots in memory 15. It should be remembered that a time slot is 3 nsecs. long for a non-talking station and 10 nsecs. long for a talking station. In one time slot (Go) the address of station 10's transmitter 11 is written in the codes address side of memory 15 and the address of station 10n's receiver 12n is written in the decoder address side of the memory. In the other time slot-which is not necessarily adjacent to the first slot-the address of 10n's transmitter 11n and 10's receiver 12 are written in the coder and decoder sides.respectively of the memory. In response to the simultaneous appearance of the addresses 11, 12n from the memory and provided that a delta " 1 " bit is present at the output of 10's transmitter 11, then AND gates 160 and 161n are opened to "convey" " this bit to 10n's receiver 12n. A monopulser 163 causes a 1 nsec. delay between the openings of the two gates and also steps the memory on via OR gate 169. However, if, in the same time slot (viz. addresses 11, 12n present) a " 0 " bit had been present at 11's output, then gate 160 would not have been opened and hence monopulses 163 and gate 161n would not become operative. However, inverter 162 would be immediately operative i.e. within 3 nsecs. so as to step the memory on. A similar sequence occurs during each time slot. Line circuits. Coder 11. An incoming speech signal is compared in differential amplifier 110 with a datum level established on capacitor 114. In dependence on whether the signal's amplitude is greater or less than the datum, a 1 or 0 bit level appears at the output. In the case of a 1 bit level, a control signal is reverted to the line circuit (at AND gate 111) during the relevant time slot whereby a capacitor in store 112 is discharged into integrating capacitor 114 by an amount corresponding to a 1 bit. No such action occurs for a 0 bit level. At the end of the current exchange cycle, a pulse is reverted from monopulser 167 to the store 113 in each coder 11-1 In so as to cause a capacitor therein to discharge into capacitor 114 by an amount equal to a 0 bit level. The quantization level for the next sampling bit is thus determined by the remaining charge on capacitor 114 (see also next paragraph). Line circuits. Decoder 12n.-During the relevant time slot, a 1 bit from coder 11 via gate 160, monopulser 163 and gate 161n causes a capacitor in store 121. to discharge into integrating capacitor 122 by an amount equivalent to a 1 bit level. No action ensues from a 0 bit at coder 11. At the end of the exchange cycle a capacitor in store 123 is discharged into capacitor 122 by an amount equivalent to a 0 bit level. The amplifier 124 provides a corresponding analogue signal to the station 10n. The end of cycle pulse from pulser 167 may be eliminated if the integrating capacitors in the coder and decoder are shunted by bleeder resistances which are such that the CR time constant allows leakage equivalent to a 0 bit level (Fig. 4, not shown). A transistorized circuit incorporating decoupling and directional diodes as well as a limiting Zener diode for stores 112, 113 . . . 121, 123 is depicted in Fig. 3 (not shown). Second embodiment (Figs. 6, 7, not shown).- In order to eliminate transmission of steady state conditions viz. 101010 . . . each coder comprises a pair of flip flops for storing present and just-preceding bit levels. Only if the two bits are of the same type are they forwarded to the switching centre (16 in Fig. 2) over a respective " 1 " or " 0 " lead. The 1 or 0 bit is sent on to the relevant decoder as a voltage level on a single lead common to all the decoders. A simultaneous bit sent on the address lead of the relevant decoder ensures that only that decoder responds. Since the coders distinguish between 0 and 1 bits by using separate leads, the gates 164 . . . 164n and 111 of Fig. 2 are unnecessary, the decrementing of stores 112, 113 being accomplished by local connections from the 1 and 0 leads. Large system modification.-A number of ways of grouping the coders, decoders, memories and switching logic (16), together, with the necessary group translators, are described briefly and one such grouping scheme is depicted in Fig. 5 (not shown).