baber/WOPTO huggingface dataset:
Patent TW-451302-B (TW)
Title: Manufacturing method of capacitor
Inventor: JUNG TZ-GUEI
IPC: H01L21/04
Filed: 2000-08-18
Granted: 2001-08-21
Abstract: A kind of manufacturing method of capacitor includes the following steps. At first, a semiconductor substrate that has the peripheral circuit region and the memory cell region is provided, in which an isolation structure has been formed in the memory cell region. A gate oxide layer is formed on the substrate outside the isolation structure. After that, a polysilicon layer is formed to cover the gate oxide layer and the isolation structure. Then, the polysilicon layer and the gate oxide layer are defined in order to form a bottom electrode on the isolation structure and form a polysilicon gate on the peripheral circuit region at the same time. A spacer is formed individually on the sidewall of polysilicon gate and the sidewall of the bottom electrode. Then, a metal silicide layer is formed individually on the upper surface of the bottom electrode and the upper surface of the polysilicon gate. After that, a dielectric layer is formed on the metal silicide layer on the upper surface of the bottom electrode. Additionally, a metal layer is formed on the dielectric layer.
Patent TW-518750-B (TW)
Title: DRAM-cells arrangement and its production method
Inventor: SCHLOESSER TILL
IPC: H01L21/8242
Filed: 2000-11-14
Granted: 2003-01-21
Abstract: The memory-cells have respectively a capacitor and a transistor. A memory-node (SK) of the capacitor is arranged in a first recess (V1) of a substrate (1). A gate-electrode of the transistor is arranged on a first side-area of a second recess (V2), which is separated from the first recess (V1). An upper source-/drain-region (S/DO) of the transistor is adjacent on the memory-node (SK) and on the second recess (V2). An under source-/drain-region (S/DU) of the transistor is arranged in the substrate (1) deeperly than the upper source-/drain-region (S/DO) and adjacent on the second recess (V2).
Patent TW-I228616-B (TW)
Title: Liquid crystal display device
Inventor: LEE SANG-DUK
IPC: G02F1/1335
Filed: 2000-11-20
Granted: 2005-03-01
Abstract: A liquid crystal display device in which an integrated printed circuit board is manufactured by integrating a circuit of a gate portion with a source portion and is located on the source side of the liquid crystal panel, and a flexible circuit board according to the COF method is provided on the gate side, and the flexible circuit board is supported towards a mold frame to reduce the area and the volume which is occupied by a portion except for a screen is disclosed. The liquid crystal display device comprises a liquid crystal display panel, an integrated printed circuit board, a flexible circuit board for transferring a gate driving signal and a data driving signal to the liquid crystal display panel, and a mold frame for receiving the liquid crystal display panel and a back light assembly. A support member for supporting the flexible circuit board towards the mold frame is provided on one side of a chassis. Since the gate side flexible circuit board is easily supported by the support member towards the mold frame, the planar area increasing of the liquid crystal display device is prevented.
Patent TW-478100-B (TW)
Title: Method for producing silicon-on-insulator semiconductor device
Inventor: WU DE-YUAN
IPC: H01L21/76
Filed: 2000-11-21
Granted: 2002-03-01
Abstract: The present invention discloses a method for producing a silicon-on-insulator (SOI) substrate semiconductor device having a shallow channel. The method uses a dielectric layer as a mask, an oxygen implantation, and a heating process to form a silicon dioxide layer in a SOI substrate prior to forming a gate on the SOI substrate, i.e. reducing the junction depth of the channel. The method comprises: providing a SOI substrate at least comprising a silicon layer and an insulating layer; depositing a first dielectric layer on the silicon layer; transferring a pattern of a gate region to the first dielectric layer to form a trench and exposing the silicon layer; implanting oxygen to the silicon layer; heating the SOI substrate to form a silicon dioxide layer in the silicon layer; depositing a second dielectric layer and filling up the trench; anisotropically etching the second dielectric layer to form two spacers in the trench; filling up the trench with a conductor layer to form a gate; removing the first dielectric layer; and forming a source and a drain in the silicon layer.
Patent TW-512215-B (TW)
Title: Solid state lamp
Inventor: TARSA ERIC J
IPC: F21V29/00
Filed: 2000-12-01
Granted: 2002-12-01
Abstract: The invention provides a new solid state lamp (10) emitting a light useful for room illumination and other applications. It comprises a solid state light source (12) which transmits light through a separator (14) to a disperser (16) that disperses the light in a desired pattern and/or changes its color. In one embodiment, the light source (12) is a blue emitting LED operating with current high enough for room illumination, the separator (14) is a light pipe or fiber optic device, and the disperser (16) disperses the light radially and converts some of the blue light to yellow to produce a white light mixture. The separator (14) spaces the light source a sufficient distance from the disperser (16) such that heat from the light source (12) will not transfer to the disperser (16) when the light source (12) is carrying elevated currents necessary for room illumination.
Patent TW-I267386-B (TW)
Title: Hydrous hot melt type binder paste, method for preparing it and an external plaster
Inventor: KAWACHI TOSHIKUNI
IPC: A61K9/70
Filed: 2000-12-05
Granted: 2006-12-01
Abstract: A water containing hot melt type binder which combines water soluble drug stably, well release the drug from the binder, and has a high bioavailability based on the percutaneous absorption is provided. An external plaster, characterized by that the percutaneous absorptable drug is combined with the water containing hot melt type binder plaster in which contains styrene-isoprene-styrene block copolymer, binding resin, antioxidant, lanolin and water as the essential component is disclosed.
Patent TW-477022-B (TW)
Title: Semiconductor chip removing and conveying method and device
Inventor: WATANABE MITSUHISA
IPC: H01L21/78
Filed: 2000-12-22
Granted: 2002-02-21
Abstract: Semiconductor chips are formed on a wafer. The wafer is diced, while a dicing tape applied to the wafer is kept intact. Each of the semiconductor chips is fixed by suction and then removed from the dicing tape. Each of the semiconductor chips is unfixed by ceasing the suction and picked up and conveyed.
Patent TW-508789-B (TW)
Title: Semiconductor device and fabrication method, circuit substrate and electronic machine therefor
Inventor: WADA KENJI
IPC: H01L23/48
Filed: 2001-01-18
Granted: 2002-11-01
Abstract: The method of manufacturing a semiconductor device comprises a step of forming a through-hole 50 in a semiconductor chip 10 having an electrode and forming a conductive layer 70 on a region comprising an inner side of the through-hole 50. An intermediate portion of the through-hole 50 is formed to be larger than an edge portion thereof, and the conductive layer 70 is formed by electroless plating.
Patent TW-541559-B (TW)
Title: Fuse
Inventor: ENDO TAKAYOSHI
IPC: H01H85/157
Filed: 2001-02-16
Granted: 2003-07-11
Abstract: A fuse (20) includes a fuse element (25), having a fusible portion (22) provided between inner side edges (21a) of a pair of parallel flat-plate terminal portions (21, 21), and an insulating housing (23) covering the inner side edges (21a) of the flat-plate terminal portions (21) and the fusible portion (22). A middle portion (21f) of each of the flat-plate terminal portions (21), located at the lateral position relative to the fusible portion (22), is fixedly gripped by a mating terminal (11) of a fuse mounting portion, so that the flat-plate terminal portion is electrically connected to the mating terminal.
Patent TW-I235935-B (TW)
Title: A knowledge-engineering protocol-suite system
Inventor: GOLDMAN ARNOLD J
IPC: G05B15/02
Filed: 2001-04-27
Granted: 2005-07-11
Abstract: A knowledge-engineering protocol-suite is presented that generally includes methods and systems, apparatus for search-space organizational validation, and appurtenance for use therewith. The protocol-suite includes a search-space organizational validation method for synergistically combining knowledge bases of disparate resolution data-sets, such as by actual or simulated integrating of lower resolution empirical data-capture dense quantitative search-spaces. Furthermore, from alternative technological vantages, the suite relates to situations where this synergetic combining is beneficially accomplished, such as in control systems, command control systems, command control communications system, computational apparatus associated with the aforesaid, and to quantitative modeling and measuring tools used therewith. The protocol-suite also includes facile algorithmic tools for use with method and a process-modeling computer for use in a distributed asynchronous system of process modeling computers.
Patent TW-480200-B (TW)
Title: Flux supply device and liquid flux supply method
Inventor: ISHIDA KAZUTAKA
IPC: F17C13/04
Filed: 2001-06-04
Granted: 2002-03-21
Abstract: This invention provides a flux supply device comprising a liquid replenishing portion 49 containing a liquid flux 15 for replenishment, a liquid holding portion 50 connected to the lower end of the liquid replenishing portion 49 with a first electromagnetic valve 33 provided in between, and a liquid supply portion 51 connected to the lower end of the liquid holding portion 50 with a second electromagnetic valve 34 provided in between. The lower end of the liquid supply portion 51 is located in a flux storage tank 11 in which a mixed gas is generated. A gas blow-in pipe 18 for supplying a combustible gas is also located in the flux storage tank 11. The first electromagnetic valve 33 and the second electromagnetic valve 34 are controlled in given timing so that one opens and closes and then the other opens and closes, alternately and repeatedly. This prevents the pressure variation in the flux storage tank 11 from affecting the liquid replenishing portion 49 and the surface level of the liquid flux 15 in the flux storage tank 11 is kept unchanged.
Patent TW-519642-B (TW)
Title: Ferroelectric random access memory device
Inventor: CHOI MUN-KYU
IPC: G11C11/22
Filed: 2001-06-18
Granted: 2003-02-01
Abstract: A nonvolatile memory device comprises a plate line driving circuit having a hierarchical word line structure. The plate line driving circuit is coupled to plate lines corresponding to a main word line. The plate line driving circuit transmits a plate line drive signal to the plate lines when the main word line is selected, and connects the plate lines to the main word line when the main word line is unselected. Therefore, it can be prevented that the plate lines are floated when the main word line is unselected.
Patent TW-I282706-B (TW)
Title: EL phosphor multilayer thin film and EL device
Inventor: YANO YOSHIHIKO
IPC: H05B33/14
Filed: 2001-07-05
Granted: 2007-06-11
Abstract: The invention has for its object to provide an EL phosphor multilayer thin film and EL device which can emit light with improved luminance. This object is achieved by the provision of an EL phosphor multilayer thin film wherein a phosphor thin film and a dielectric thin film are stacked one upon another. The phosphor thin film comprises a matrix material containing as a main component at least one compound selected from an alkaline earth thioaluminate, an alaline earth thiogallate and an alkaline earth thioindate, and a rare earth element as a luminescent center, and the dielectric thin film comprises an alkaline earth oxide. There is also provided an EL device comprising such an EL phosphor multilayer thin film.
Patent TW-514564-B (TW)
Title: Method of manufacturing a support plane frame tubing of furniture
Inventor: LIOU TZUNG-SHIN
IPC: B21D13/00
Filed: 2001-07-20
Granted: 2002-12-21
Abstract: Disclosed is a method of manufacturing a support plane frame tubing of furniture, comprising the step of rolling a raw material to form a tubing for use in a support plane frame of furniture. In manufacturing the tubing, a steel sheet is conveyed to a flattener for flattening. After being flattened, and rolled by a first, second, third, fourth roller sets, the steel sheet is rolled to form a semi-product, which is conveyed to a ultrasonic generator to be fused and welded under high temperature. The semi-product is then conveyed to a trimming machine for trimming the welded joint. After the semi-product is trimmed, the tubing is conveyed to a fifth roller set to form a tubing, thereby obtaining a tubing for use in a support frame of furniture.
Patent TW-523757-B (TW)
Title: Dual-port DRAM architecture system
Inventor: HSU LOUIS L
IPC: G11C11/405
Filed: 2001-08-22
Granted: 2003-03-11
Abstract: A dual-port, folded-bitline DRAM architecture system is presented which prioritizes two simultaneous access requests slated for a DRAM cell of a data array prior to performing at least one of the access requests to prevent affecting the integrity of the data while suppressing noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling. If the two access requests are write-read, the system prioritizes the two access requests as being equal to each other. The system then simultaneously performs the write and read access by accessing the corresponding DRAM cell through the first port to write the data while simultaneously writing the data through to an output bus, which is equivalent to a read access. In another embodiment of the present invention, a dual-port, shared-address bus DRAM architecture system is presented which also prioritizes two simultaneous access requests slated for the DRAM cell of a data array. If the two access requests are write-read or read-write, then the system prioritizes the two access requests as being equal to each other. The system then simultaneously performs the write and read access or the read and write access requests by accessing the corresponding DRAM cell through the first port or second port, respectively, to write the data while simultaneously writing the data through to an output bus. This system further includes shared-address buses, thereby enabling control circuitry to be shared by both ports, since only one port of the corresponding DRAM cell can be used at a time. Hence, less control circuitry is required and all of the control circuitry can be provided at one side of the data array. Prioritization is realized, in order to maintain data integrity in both DRAM architecture systems, by designating one port of each DRAM cell a master port and the other port a slave port, where the access request slated through the master port has typically a higher priority than the access request slated through the slave port. Accordingly, accesses to the DRAM cell through the master port, with some exceptions, take precedence over accesses through the slave port. Each DRAM architecture system suppresses noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling by providing at least a complementary bitline on the data array for each true bitline to form bitline pairs.
Patent TW-I261961-B (TW)
Title: Active power factor correction circuit
Inventor: LIN PAO-CHUAN
IPC: H02M1/00
Filed: 2001-11-12
Granted: 2006-09-11
Abstract: An active power factor correction (PFC) circuit includes an input voltage source having a first end and a second end; an inductor having one end coupled to the first end of the input voltage source; a first and a second LEDs each having a first end and a second end, in which the first end of the first LED is coupled to the second end of the inductor, and the second ends of the first and the second LEDs are connected; a first and a second switch elements each having a first end, a second end and an enable end, in which the first end of the first switch element is coupled to the first end of the first LED, the first end of the second switch element is coupled to the second end of the input voltage source and the first end of the second LED, and the second ends of the first and the second switch elements are coupled together; a capacitive element having two ends respectively coupled to the second end of the second LED and the second end of the second switch element; and a switch auxiliary circuit coupled to the PFC circuit for the first and the second switch elements to switch at zero voltage, in which the first and the second switch elements are conducted and cut off to switch power supply.
Patent TW-512222-B (TW)
Title: Trapezoidal line width measurement device and method thereof
Inventor: WANG GUANG-SHIA
IPC: G01B11/02
Filed: 2001-12-11
Granted: 2002-12-01
Abstract: The present invention discloses an adjustable, multi-angled trapezoidal line width measurement device and method thereof. In the device of the present invention, two pairs or more than two pairs of light sources with different angles are utilized as the projection lights from the side to be projected onto the object to be measured. Thus, no matter the measured object is measured in whatever direction, the measured values are accurate.
Patent TW-543045-B (TW)
Title: Multilayer impedance component
Inventor: TAKASHIMA KOICHI
IPC: H01F27/28
Filed: 2002-02-18
Granted: 2003-07-21
Abstract: The present invention provides a multilayer impedance component, which has no directivity when mounted and can obtain excellent electrical characteristics. The multilayer impedance component includes a high permeability coil having a first winding portion and a third winding portion formed by stacking relatively high permeability magnetic sheets, a low permeability coil having a second winding portion formed by stacking relatively low permeability magnetic sheets, and an intermediate layer formed by an intermediate sheet. The three winding portions are electrically connected in order in series with each other to form a helical coil. Each end of the helical coil is led from coil conductor patterns formed in the high-permeability coil to each of input and output external electrodes.
Patent TW-569412-B (TW)
Title: Composite material member for semiconductor device and insulated and non-insulated semiconductor devices using composite material member
Inventor: KURIHARA YASUTOSHI
IPC: H01L23/373
Filed: 2002-03-11
Granted: 2004-01-01
Abstract: To provide a composite material member for semiconductor device, an insulated semiconductor device and non-insulated semiconductor device using the composite material member, which are effective for obtaining a semiconductor device that alleviates thermal stress or thermal strain occurring during production or operation, has no possibilities of deformation, degeneration and rupture of each member, and is highly reliably and inexpensive. The composite material member for semiconductor device is characterized by being a composite metal plate with particles composed of cuprous oxide dispersed in a copper matrix, in which a surface of the composite metal plate is covered with a metal layer, and a copper layer with thickness of 0.5 mum or larger exists in an interface formed by the composite metal plate and the metal layer.
Patent TW-I308495-B (TW)
Title: Analgesic/ antiinflammatory patches for topical use
Inventor: YASUHIKO SASAKI
IPC: A61P17/00
Filed: 2002-05-23
Granted: 2009-04-11
Abstract: The invention provides an analgesic anti-inflammatory patch of a hydrophobic type for topical application containing, in a Pressure Sensitive Adhesive(PSA), diclofenac sodium, pyrrolidone or a derivative thereof, a polyhydric alcohol fatty acid ester, and an organic acid. The patch exerts the following effects:   (1) diclofenac sodium is effectively and continuously released from a Pressure Sensitive Adhesive(PSA) and percutaneously absorbed, thereby attaining sustained, excellent pharmaceutical and pharmacological effects;   (2) the patch per se has high tackiness and safety; and (3) diclofenac sodium remains stable in the Pressure Sensitive Adhesive(PSA).
Patent TW-551002-B (TW)
Title: Improved process for grid array assembly and electronic device made thereby
Inventor: TZOU GEORGE
IPC: H05K3/00
Filed: 2002-06-21
Granted: 2003-09-01
Abstract: A process is provided to modify the conventional process of concurrently spreading solder pastes for both of the SMT components and the BGA components by conducting different novel printing processes for the respective components. The novel printing process of the present invention comprises the steps of: spreading or syringing a paste flux on the soldering pads of the printed circuit board for the BGA components, wherein the paste flux does not contain solder balls or other types of solder; spreading a solder paste on the soldering pads of the printed circuit board for the SMT components; and reflowing the circuit components on the soldering pads of the printed circuit board for the BGA components and the SMT components, respectively. The present invention further provides an electronic device made by the above printing process.
Patent TW-I258730-B (TW)
Title: Woodwind instrument with key mechanism perfectly closing holes
Inventor: OKADA SHIGERU
IPC: G10D9/04
Filed: 2002-07-26
Granted: 2006-07-21
Abstract: A woodwind instrument has a key mechanism (3) provided on a tube (1), and a player selectively closes and opens holes (2) formed in the tube (1) through a fingering; the key mechanism includes keys (20) corresponding to the holes (2), and each of the key (20) has an automatic regulator (21) for uniformly pressing a pad washer (23) to a pad (10) received in a pad cup (11) so that, even if the pad cup (11) is inaccurately fixed to a linkage (3b) of the key mechanism (3), the hole (2) is surely closed with the pad (10).
Patent TW-571213-B (TW)
Title: Networking system and method assessing economical effect in enterprise improvement project
Inventor: WANG JENG-JUNG
Filed: 2002-08-26
Granted: 2004-01-11
Abstract: A networking system and method assessing economical effect in enterprise improvement project are adapted for corporate to help working personnel involved with enterprise improvement project capable of going through a networking system to efficiently calculate all economical effects of enterprise project with real-time on-line method. The networking system and method assessing economical effect in enterprise improvement project are characterized by employing computer network technology to allow related working personnel in enterprise improvement project capable of using real-time on-line method to calculate each economical effect of enterprise improvement project. Such feature can make whole process of enterprise improvement project more efficient so as to be more improved and practical than conventional technique.
Patent TW-567565-B (TW)
Title: Chip-on-board module, and method of manufacturing the same
Inventor: SHINONAGA NAOYUKI
IPC: H01L21/58
Filed: 2002-10-22
Granted: 2003-12-21
Abstract: A chip-on-board module has a multilayer interconnection board having die mount sections; dies mounted on respective die mount sections such that a single die is mounted on each die mount section or two or more dies are being stacked and mounted there; bonding pads provided on the multilayer and connected to single dies or uppermost dies; contact pads provided on the multilayer board and connected to corresponding bonding pads; jumper pads provided in proximity to the contact pads and connected to edge terminals of the multilayer board, circuit elements mounted on the multilayer interconnection board, or through holes formed so as to extend across layers of the multilayer board; and molding resin for molding the dies and the pads. The uppermost dies of the respective die mount sections where dies are stacked in two or more layers have passed an electric property test.