Patent GB-1432244-A (GB)
Title: Pulse radar apparatus
IPC: G01S13/528
Filed: 1973-04-18
Abstract: 1432244 Pulse radar HOLLANDSE SIGNAALAPPARATEN BV 18 April 1973 [25 April 1972] 18829/73 Heading H4D A pulse radar apparatus, for use, e.g. in M.T.I. apparatus, is arranged to suppress at least some multiple time around echoes by varying the transmitted pulse repetition rate to produce multiple staggering of the transmitter interpulse period, and processing the video signals in the receiver such that the positions on the time axis of first time around echoes are maintained and therefore passed to the display, e.g. P.P.I., time delays being applied to the quantized received video signal, by at least one memory device constituted by a shift register operable with a shift period which is not greater than the duration of the shortest interpulse period and which shift period commences with the start of each interpulse period so that a pulse entered into the shift register at a certain time relative to the start of one interpulse period appears at the shift register output at the same time relative to the start of the next following interpulse period. The input and output signals from the/or each memory device are combined to provide a signal which is then processed such that these signals, having an invariant position on the time axis are passed. In a first embodiment, Fig. 1, TX/RX 1, generates a train of pulses having two staggered interpulse periods T and T + #T. The video signal therefrom is quantized at 3, and is processed by devide 4 comprising a delay means 5 and a combination circuit, e.g. an OR gate. It is shown that first time around echo will produce coincident signals at OR gate 6 whereas a second time around echo will produce two signals separated in time by #T at the output thereof. Pulse suppression circuit 7 comprises #T delay elements, e.g. shift registers. 11, 11<SP>1</SP>, AND gates 12, 12<SP>1</SP>, OR gate 13, delay element 9, gating circuit 10 and P.P.I. display 14. Gate circuit 10 operates to cut off the video signal from delay 9 when a pair of pulses separated by #T is detected by correlator circuit 8, since the first pulse is delayed by 11 and appears coincidently at AND gate 12 with the second pulse so that an enable signal is fed to gate 10 to cut off the #T delayed signal from delay 9, thus suppressing second time around delays. In a second embodiment Fig. 3, the TX/RX produces a quadruple interpulse period variation: T 1 , T 2 , T 1 +#T, T 2 +#T transmitted consecutively. The video signal is quantized at 3A and is subjected to clutter reduction by means of a double canceller 4A. It is stated that the number of blind speeds is reduced and the first time around echoes retain their position in each (varying) interpulse period, while second and subsequent time around echoes are not separated by a constant time difference (#T as in Fig. 1). Discriminator circuit 2B corresponding to circuit 2 in Fig. 1, receives the two replicas of the video signal pulses in the sequential interpulse periods from double canceller 2A via a D-to-A converter 19. Quantizer 3B converts these signals to standard pulses, which are passed through delay line integrator 4B, comprising #T delay lines 5a ... 5n where n is taken to be 10, and also to an input of combination circuit 6B, at the output of which, any pulses simultaneously appearing as a result of different delay times, are increased in magnitude according to the number of such signals simultaneously appearing (see Figs. 5A- 5J, not shown). These signals are applied in parallel to comparators 20, and 20<SP>1</SP>, which have their levels set to five or preferably 7, and three pulse magnitudes respectively. Comparator 20 is therefore stated to produce an optimum signal/noise ratio. Comparator 20<SP>1</SP> passes such signals to a correlator 8 which then enables suppression by gate 10 of signals separated by #T as in Fig. 1. Second, third and fifth time around signals are stated to be supressed in this way. Various other combinations of pulse interperiod staggering are considered; e.g. the series T 1 , T 2 , T 3 , T 1 +#T, T 2 +#T, T 3 +#T, but suppression of only the 2nth time around echo is stated to be effected. In another embodiment the comparator 20<SP>1</SP> and suppression circuit 7 are omitted, resulting in reduction in the number of blind speeds.