Patent GB-853695-A (GB)
Title: Improvements in or relating to electric calculators
IPC: G06F15/78
Filed: 1958-03-21
Abstract: 853,695. Digital electric calculating and data-storage apparatus. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. March 21, 1958 [March 21, 1957; Feb. 26, 1958], No. 9134/58. Class 106 (1). In an electric calculator comprising a main slow access memory TM, an intermediate rapid access memory MR, an arithmetic unit BC, and control equipment CC including an instruction memory MO with associated decoders, a phaseof-operation control circuit CCP and a member (counter CO) for sequentially introducing instructions into the instruction memory; circuits are provided for controlling block transfers in both directions between the memories TM and MR, the rapid memory MR is divided into groups each having the capacity of a predetermined group of addresses in the main memory TM, and with each rapid memory group is associated an erasable register T4 ... T11 into which, upon each block transfer from TM, is written the main memory group address concerned, and the rapid memory group address is stored in a register f which coacts with the member CO in selecting the instructions. As described, the main memory TM comprises a magnetic drum having 128 tracks each storing 128 words, together with timing signal tracks. A word period or minor cycle comprises 28 pulse periods (d 1 -d 28 ) of which d 27  contains a parity check bit and d 28  is blank. The rapid access memory MR comprises a set of magnetic core twodimensional matrices, each word being stored in parallel one bit in each matrix, and each of the 8 groups in MR stores 128 words (corresponding to one track on the drum). The unit BC comprises four serial accumulators which may be selectively connected via circuit LC to the main memory. Registers R1, R2 effect series-parallel conversions between TM and MR, and MR and BC respectively. The selected instructions are transferred in parallel from MR to memory MO which comprises an address section (AN) and a function section (LF) each comprising a separate delay line loop store. The address section loop includes an adder/subtracter (Fig. 3, not shown) whereby addresses may be modified. The address may comprise 14 digits or 10 digits for selecting a word from the drum TM and memory MR respectively. That portion of an instruction stored in (LF) may include, as well as a function letter, special " indices," and second addresses (e.g. an accumulator address). The counter CO comprises a delay line loop including a half adder whereby the instruction address therein is normally successively increased by "1." This address includes a 7-digit word-selecting portion which is used with the 3-digit group address in f for selecting an instruction from MR and a magnetic drum track-selecting portion (main memory group address). The old and new addresses in CO are passed to a comparator COMP which, when the track-selecting portions differ, operates in a manner similar to that described in Specification 809,507 to cause an automatic transfer, if necessary, from the new track on the drum to one of the groups of MR other than that from which the previous instruction was obtained. This transfer is preceded by a test operation in which the new address is compared in comparators COMP 4-11 with the addresses stored in registers T4-T11 to determine whether the new instruction is already stored in one of the other groups of MR, in which case register f is set to the address of this new group and the programme sequence continues. If, however, the test fails, a search is made for a group in MR which is free to receive new data from the drum. This free condition is indicated by a bi-stable flipflop B4-B11 which is controlled by circuits including inhibition flip-flop I4-I11 which can be set to prevent erasure of data from the associated rapid memory group. The search may begin always at the same group (Fig. 5B, not shown) or on the group next to the one which has just been used (Fig. 7, not shown). The address of the selected group is set on register f and transferred via MO to register g which together with routing circuits (Fig. 3, not shown) controls the distribution in MR of the words read from the new drum track, the track address being entered in the appropriate register T4-T11. A block transfer operation in which either a complete track, or a block of 32 words, is transferred from the drum TM to memory MR, or vice versa, may be effected also in response to an instruction (function letter T or W) the direction of transfer being determined by a special index (Á). Other instructioncontrolled operations are referred to including e.g. multiplication, a double-length product being formed in two of the accumulators; division, in which the quotient is obtained in one accumulator and the remainder in another; accumulator right or left shift or normalizing; conditional or unconditional transfer-of-control in which a new address from MO is introduced into CO; and introduction of sub-routines (" symbolized operations ") the previous contact of CO being held in a predetermined accumulator. The phases of operation in the performance of each instruction are controlled by circuit CCP (Fig. 4, not shown); the arrangement being such that the phases for successive instructions overlap. A checking circuit (Fig. 6, not shown) operates if an error is detected e.g. in a number overflow or a parity check, to stop the calculator or to introduce a special checking sub-routine.