Patent GB-1374821-A (GB)
Title: Analytic call distributor for telecommunications systems
IPC: H04M3/523
Filed: 1971-12-31
Abstract: 1374821 Automatic exchange systems COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 31 Dec 1971 [31 Dec 1970] 61027/71 Heading H4K In a semi automatic exchange incoming calls are categorized in terms of the junction on which they arrive and are distributed to operators partly in accordance with the category and partly in accordance with their waiting time. The junctions JR (Fig. 1) are monitored on a cyclic basis by a logic LJR in conjunction with a last look memory M having a compartment for each junctor and also a compartment for each operator TO. The latter are cyclically scannable for call distributing purposes by logic LO. Data concerning a call via a junction is amassed in memory and in addition is displayed at an operator position allocated to the call. Data transmission to the operators is effected over a common bus OV in the manner described in Specification 1,355,547. The call distributer DA monitors the logic circuit outputs so as to determine a new call and to allocate thereto a least-busy operator. The call distributer is illustrated in some detail in Figure 2. Essentially is analyses all call data incoming thereto by means of device AA so as to allot a "call-type" code thereto, which code involves the identity of the junction and the "call category" i.e. the nature of the calling subscriber line viz. non fee paying. The operators are each allocated (except in emergency overload) to a particular call-type. The latter always includes more than one call category. The operation of the distributer takes place in a number of phases during the first of which #1 the junctions are scanned in turn (c.f. Specification 1,355,547), the results of scanning are passed to AA over inputs I1, I2 and the resultant code is entered into one of registers RC1, RC2. As each junction is scanned, an indication of the time for which it has been waiting (that is of course only if it is a calling junction) is entered over I3 into one of registers RT1, RT2. The choice of registers is governed by a two step counter CR1 which is stepped on only if (a) an operator is available to handle the call as defined by the particular code allotted thereto (b) phase #1 is present and (c) the new waiting time on I3 exceeds the previous waiting time present in RT1 or RT2 (comparator C1 determines (c)). Thus if the new time is longer it is entered into that one of RT1 and RT2 which was previously empty and the other one having emptied itself of the preceding longest time awaits the entry of a newer longest time. It will be noted that if RT accepts a new longest time, the code of the junction to which it relates is simultaneously entered in an RC register. When all the junctions have been scanned, phase #2 is started during which the code finally set in RC is sent to the operator logic circuit LO so that a hunt may be made through memory to locate the operator denoted by a tag marking who last handled a call having this code. This operator marking serves to denote the point, in the group of operators able to handle calls having the particular code, at which a search for a least busy operator should start. During phase #3, the degree of business of each of the operators within the group is fed via I4 into registers RG. These operate under the control of two step counter CR2 in a similar manner to RT and CR1 so that at the end of the cycle, the least degree of business (but not the identity) of the least busy operator is present in RG. When the cycle ends as denoted by a return to the tag marked operator, the mark is expunged and phase #4 commences during which each operator's business is compared with that recorded in RG. When the first operator who is not busier than that recorded is reached gate P3 is enabled to permit the operator logic LO to mark her position over the common operator data bus and also to enter her identity into store RI. Phase #5 commences wherein all the junctions carrying the particular code, which is still stored in RC, are tested for waiting time so that the one having the longest time as denoted by a comparison with the time stored in RT is selected by the opening of gate P4. The junction identity is passed to the preselected operator and her identity is gated out of store RI and entered into the memory compartment associated with the junction. The distributer resets and a new cycle of operations commences. The full cycle should take 100 msces., if this is exceeded timer OT times out to advance the phase sequences. Overload in the sense of calls waiting longer than a preset period are denoted by the illumination of a lamp ES on a supervisor's panel. She may initiate a hunt, over manual swtch CM, for those calls of a particular category that are experiencing the overload so that they can be dealt with immediately.