baber/WOPTO huggingface dataset:
Patent TW-388764-B (TW)
Title: Process for the crystallization of polyethylene naphthalate prepolymers and the solid stating of those crystallized prepolymers
Inventor: DUH BEN
IPC: C08G63/88
Filed: 1997-10-21
Granted: 2000-05-01
Abstract: A process is disclosed for the crystallization of a PEN prepolymer containing volatile components. The temperature is maintained at a temperature in the range of about 20 DEG C above the Tg and about 10 DEG C below the Tm while the PEN prepolymer is agitated. The PEN prepolymer is present as chips or pellets. The pressure during crystallization is maintained at a level higher than the vapor pressure of the volatile components in the PEN prepolymer chips or pellets, suitably by the presence of a gas and/or a liquid or mixture of liquids.
Patent TW-400432-B (TW)
Title: Analytical apparatus
Inventor: PERKINS ELAINE ANN
IPC: G01N21/55
Filed: 1997-11-25
Granted: 2000-08-01
Abstract: A surface plasmon resonance apparatus for detecting a soluble analyte (e. g. a protein) or a particulate analyte (e. g. a cell), the apparatus comprising: (a) a sensor block adapted to receive a sensor, said sensor, for example a sensor slide, having a metallised sensor surface capable of binding the analyte; (b) a light source capable of generating an evanescent wave at the sensor surface of a sensor slide on the sensor block; (c) a first detector capable of detecting light from the light source which is internally reflected from the sensor surface; and (d) a second detector (e. g. a video camera) capable of detecting light scattered or emitted from an analyte bound thereto. Optionally the apparatus further comprises a second light source for increasing the intensity of the light scattered or emitted from an analyte bound to the sensor surface, preferably this is sited to such as to minimise the amount of light transmitted therefrom which is detected by the first detector. Also disclosed are sensor adapted for use in the apparatus, and methods of detecting analytes in samples comprising exposing samples to the sensor surface of the apparatus.
Patent TW-355177-B (TW)
Title: Semiconductor devices testing apparatus
Inventor: FURUTA KATSUNOBU
IPC: G01B5/008
Filed: 1997-12-24
Granted: 1999-04-01
Abstract: A semiconductor test apparatus, using a semiconductor conveyor and processing means, including a carrying head for snatching the semiconductor, a X-Y moving member for moving the carrying head on the horizontal plane along the X-Y direction, the moving member including a moving driven member and a Z-axis driven member for lowering the carrying head, the semiconductor being moved to the carrying head of the test receptacle and contact the test receptacle, the semiconductor test means is a architecture to move the test receptacle by a first and second match activation on the carrying head and the test receptacle engage with the semiconductor correctly and contact the test receptacle, the test means characterized in a controlling mechanism, including: a mechanism for moving the X-Y driven mechanism of the carrying head to a natural state, in this state the X-Y driven mechanism being moved manually: a mechanism for turning on the Z-axis mechanism to lower the carrying head, and the test receptacle engage with the semiconductor, and the X-Y driven mechanism being maintained in the natural state; a mechanism for adjusting the engagement between the first and second guide mechanism to enable these guide mechanism to align concentrically; and a storage mechanism for storing the information which is used to controlling the X-Y driven mechanism.
Patent TW-394805-B (TW)
Title: Paper structures having at least three regions including decorative indicia comprising low basis weight regions
Inventor: PHAN DEAN VAN
IPC: D21F11/00
Filed: 1998-02-27
Granted: 2000-06-21
Abstract: A paper web and method of making the paper web are disclosed. The paper web includes at least three regions disposed in a nonrandom, repeating pattern. The three regions are distinguishable from each other by at least one property selected from the group consisting of basis weight, density, and fiber composition. The paper web has a relatively high basis weight background portion and decorative indicia. The decorative indicia comprise one or more relatively low basis weight regions.
Patent TW-541733-B (TW)
Title: Epitaxial wafer having a gallium nitride epitaxial layer deposited on semiconductor substrate and method for preparing the same
Inventor: MOTOKI KENSAKU
IPC: H01L33/00
Filed: 1998-03-13
Granted: 2003-07-11
Abstract: The present invention provides an epitaxial wafer comprising a (111) substrate of a semiconductor having cubic crystal structure, a first GaN layer having a thickness of 60 nanometers or more, a second GaN layer having a thickness of 0.1 mum or more and a method for preparing it. A method for preparing an epitaxial wafer comprising a GaAs (111) semiconductor substrate, a first GaN layer having a thickness of 60 nanometers to 200 nanometers, a second GaN layer having a thickness of 0.1 mum or more, comprising the steps of: supplying a first mixture of material gases comprising a metalorganic including Ga and HCl and a second mixture of material gases comprising NH3 into a chamber heated by a heat source disposed outside of said chamber; growing a buffer layer by vapor deposition on a GaAs substrate disposed in the chamber at a first temperature of 400-600 DEG C; improving crystallinity of the buffer layer by increasing substrate temperature from the first temperature; and supplying said first and second mixtures of material gases into said chamber in which the substrate is heated at a second temperature higher than said first temperature to grow a GaN layer on said buffer layer.
Patent TW-414748-B (TW)
Title: Brazed diamond tools by infiltration
Inventor: SUNG CHIEN-MIN
IPC: B24D3/00
Filed: 1998-03-21
Granted: 2000-12-11
Abstract: The present invention describes a diamond tool with diamond bonded chemically by a braze that contains either Cr, Mn, SI, or Al or mixtures or alloys thereof. The diamond tool is made by infiltrating the braze into a matrix metal that contains diamond in either form of grits or polycrystalline bodies.
Patent TW-399316-B (TW)
Title: A locking device
Inventor: TERNULLO LUIGI JR
IPC: H01L27/00
Filed: 1998-03-23
Granted: 2000-07-21
Abstract: This is a locking device with a series connected P channel transistor and a series connected N channel transistor onto the P channel transistor. N channel transistor is equipped originally, in order to gain the import capacitance of a small feedback inverter. It is still capable of maintaining the low export capacity of the feedback inverter.
Patent TW-594450-B (TW)
Title: Azine-containing photoconductive element
Inventor: DERKS PETRUS JOHANNES MARIA
IPC: G03G5/06
Filed: 1998-03-24
Granted: 2004-06-21
Abstract: A photoconductive element containing a transport substance and an azine, wherein the azine selected is a transport substance having the molecular formula: wherein R1-R6 can be different or the same constituents, selected from the group: a hydrogen atom and C1-C4 alkyl groups. The transport substance is preferably a tri-aryl amine or a substituted stilbene compound. These photoconductive elements reduce the deterioration of the phototechnical properties.
Patent TW-381265-B (TW)
Title: Semiconductor integrated circuit having triple-state logic gate circuits
Inventor: KAWAGOE MASAKUNI
IPC: G11C11/407
Filed: 1998-04-04
Granted: 2000-02-01
Abstract: The triple-state logic gate circuit preferably comprises: a first inverter circuit used for selectively outputting power voltage and grounding potential; a second inverter circuit used for selectively outputting from one of the output of the first inverter circuit or boosted power voltage; a resistor connected between the first and the second inverter circuits; and a phase lock circuit. Therefore, the triple-state logic gate circuit can avoid phase lock.
Patent TW-405219-B (TW)
Title: Manufacturing process for borderless juncture channel
Inventor: TSAI JAU-JIE
IPC: H01L21/768
Filed: 1998-04-07
Granted: 2000-09-11
Abstract: Manufacturing process for borderless juncture channel is provided, which comprises the steps as follows: provide a semiconductor substrate containing devices, form a inter-metal dielectric layer on said substrate, proceed the flatten process, form a hard mask layer on said inter-metal dielectric layer, define said mask and form sliver windows to expose the dielectric layer surface at the area for juncture pass, form a contact hole at said sliver window downside for juncture pass to connect with said devices; fill said contact hole with the first contact layer, strip the part of said inter-metal dielectric layer not covered with said mask, and form the second contact layer on said first layer and fill up the contact hole to accomplish the process for juncture pass without up-edge.
Patent TW-400299-B (TW)
Title: A strapping tool and a timing control arrangement therefor
Inventor: NIX ROBERT J
IPC: B65B13/32
Filed: 1998-06-08
Granted: 2000-08-01
Abstract: A strapping tool has a timing control circuit incorporated therein which comprises a first pressure-operable value for time-controlling a plastic strap welding operation, and a second pressure-operable value for restricting fluid line flow from a source of fluid to an air drive motor of the tool during the tensioning phase of the strapping operation while permitting unrestricted fluid line flow from the source of fluid to the air drive motor of the tool during the welding stage of the strapping operation.
Patent TW-486488-B (TW)
Title: Polymerization inhibition of acrylates using blends of nitroxides
Inventor: GANDE MATTHEW EDWARD
IPC: C07C69/54
Filed: 1998-06-11
Granted: 2002-05-11
Abstract: Ethylenically unsaturated carboxyl monomers, such as acrylic or methacrylic acid or their esters, are protected from premature polymerization during manufacture and storage in the presence or absence of water by the incorporation therein of an effective stabilizing amount of a blend two or more nitroxides. Some of these blends provide synergistic stabilization efficacy much superior to the stabilization results obtained by use of either nitroxide alone.
Patent TW-434323-B (TW)
Title: Method of manufacturing spongy metallic material capable of controlling hole shape and hole diameter of the structure
Inventor: TZENG SHAU-CHIAN
IPC: C22C29/00
Filed: 1998-06-26
Granted: 2001-05-16
Abstract: This invention provides a method of manufacturing spongy metallic material capable of controlling hole shape and hole diameter of the structure. According to the structural configuration of the hole size and shape to be formed, suitable form and structure of the organic material is selected as blank material. Based upon the metallic material to be formed is either high melting point alloy or low melting point alloy, suitable refractory slurry is mixed. The organic blank is soaked with the refractory slurry and dried to make each organic blank wrapped with a refractory layer. Using the sintering method, the organic blank in the refractory layer is burn out and carbonized to make a hollow ceramic ball with the needed diameter and shape. Further, according to the structural configuration needed, the hollow ceramic balls of different kinds are selected and mixed, and directly put into the mold cavity of a low pressure casting equipment and layered, and then preheated. After pre-heating, low pressure casting operation is processed to bond those hollow ceramic balls, and further to manufacture the spongy metallic material cast with the hollow ceramic balls. The spongy metallic material can be manufactured with controlled single or compound properties of low specific weight, compression resistance, high specific strength, high toughness, fire resistance, sound insulation, heat resistance and anti magnetic interference.
Patent TW-451185-B (TW)
Title: An error correction method and system
Inventor: NAGURA HIROHISA
IPC: H03M13/29
Filed: 1998-07-10
Granted: 2001-08-21
Abstract: The problem in a prior processing scheme of a product code scheme is that a long processing time was required due to a large number of access to the main memory 1. In an error correction in a column direction performed after an error correction in a row direction in an error correction method based upon a product code scheme, data of adjacent at least two positions in one row classified as an erasure and at least two first information blocks relating to the data are fetched to correct the data at the adjacent at least two positions based upon patterns included in the first information blocks.
Patent TW-416263-B (TW)
Title: Flexible printed circuit board unit having electronic parts mounted thereon
Inventor: MORIYAMA YOSHIFUMI
IPC: H01L23/28
Filed: 1998-11-24
Granted: 2000-12-21
Abstract: A flexible printed circuit unit includes a flexible printed circuit board having one or more electronic parts mounted on a front surface thereof. A reverse side reinforcing plate is provided at a location of the reverse side of the flexible printed circuit board corresponding to a region in which the electronic parts are mounted. An upper reinforcing structure is provided on the front surface of the flexible printed circuit board for covering at least one of the electronic parts.
Patent TW-386964-B (TW)
Title: Rear derailleur with shock absorber
IPC: F16H9/00
Filed: 1998-11-27
Granted: 2000-04-11
Abstract: A bicycle derailleur for attachment to a bicycle frame includes a base member apparatus having a first projection and a coupling member for coupling the base member apparatus to the bicycle frame. A chain guide is coupled to the base member apparatus for movement relative to the base member apparatus and for guiding a chain among a plurality of sprockets. The first projection is adapted to rotate relative to a second projection formed on a second member facing the first projection when the base member apparatus is mounted to the bicycle, and a shock absorber is adapted to be disposed between the first projection and the second projection for absorbing shocks between the first projection and second projection.
Patent TW-418468-B (TW)
Title: Thin tube for wire connection
Inventor: SUZUKI TAKESI
IPC: H01L21/607
Filed: 1998-12-16
Granted: 2001-01-11
Abstract: The present invention provides a thin tube for wire connection suitable for the wiring layout for long wire and low loop and reducing the sliding resistance of the wires. The thin tube 1 for wire connection comprises the penetration holes 5 for the wires and funneled holes 3 and the drawing portion 11 on the exit of penetration hole 5. The length of the penetration hole 5 is set to be 0.2-1.5 times of the hole diameter and the drawing portion 11 is formed as two-step drawing.
Patent TW-406369-B (TW)
Title: Method for manufacturing damascene
Inventor: YOU JIA-JIE
IPC: H01L21/768
Filed: 1998-12-18
Granted: 2000-09-21
Abstract: A method for manufacturing damascene is provided, which forms a patterned mask layer on an area of a substrate where the trench is to be fabricated. Then, a dielectric layer with low dielectric constant is formed on the substrate portion which is not covered by the mask layer. Then, the patterned mask layer is removed to form the trench in dielectric layer. Finally, a metal layer is formed in said trench and fills up these trenches to complete the damascene structure.
Patent TW-431916-B (TW)
Title: Plant for the manufacture of cold rolled stainless steel strip
Inventor: LEGRAND HUGUES
IPC: B21B1/46
Filed: 1999-05-03
Granted: 2001-05-01
Abstract: The invention relates to a method for manufacturing thin stainless steel strips, in which the following are performed in succession and continuously in a single treatment line: the continuous casting of a stainless steel strip directly from liquid metal; a descaling of the said strip; a cold rolling of the said strip; an operation of annealing and pickling or of bright annealing of the said strip; an operation of converting the said strip into its final form, such as a final cold rolling operation and/or passage through a skin pass mill; a coiling of the said strip. The invention also relates to a plant for implementing this method.
Patent TW-408427-B (TW)
Title: The manufacture method of shallow trench isolation
Inventor: LIOU JIUN-LIANG
IPC: H01L21/762
Filed: 1999-03-06
Granted: 2000-10-11
Abstract: A kind of manufacture method of shallow trench isolation is as follows form a mask layer on the substrate; define the mask layer and the substrate to form the trench; form the first insulated layer on the substrate, and fill up said trench; form the second insulated layer with more fluidity on the first insulated layer, using the mask layer as the stop layer to proceed the chemical mechanical polishing to acquire a planar surface.
Patent TW-460566-B (TW)
Title: Method for producing uniform quality coke
Inventor: CALDERON ALBERT
IPC: C10B39/02
Filed: 1999-03-23
Granted: 2001-10-21
Abstract: The present invention deals with a method to produce uniform quality coke for a blast furnace by quenching coke at a pre-determined rate to produce coke with essentially uniform moisture; further, this invention possesses specific features to produce coke of uniform stability (strength) by equilibrating the temperature of the coke prior to its being quenched. Uniform moisture and uniform stability are very important factors that contribute to the efficient operation of the blast furnace to result in lowering the cost of making a ton of iron. This method is carried out under pressure, in a closed system, and in an environmentally acceptable manner with minimum formation of CO2. Further, the method possesses additional features which lead to the production of coke of higher stability than obtained conventionally.
Patent TW-409372-B (TW)
Title: Co-packaged MOS-gated device and control integrated circuit
Inventor: MARTINEZ ROBERTO
IPC: H01L23/00
Filed: 1999-05-11
Granted: 2000-10-21
Abstract: An electronic package for an electronic device includes a substrate. A power transistor die has a lower surface and a upper surface, and the upper die surface of the power transistor Q is mounted on the substrate. A control circuit for controlling the power transistor is mounted to the upper die surface of the power transistor Q using an insulating epoxy.
Patent TW-429705-B (TW)
Title: Shared memory allocation method to improve the accessing efficiency
Inventor: CHEN REN-KAI
IPC: G06F13/38
Filed: 1999-05-15
Granted: 2001-04-11
Abstract: There is provided a shared memory allocation method to improve the accessing efficiency, which is suitable to the method for allocating the buffer in the shared memory of a network switch. The method comprises the steps of: providing a memory with multiple memory sets, each having multiple memory pages; next, allocating multiple buffer areas in the memory, each buffer area being divided into multiple blocks; and allocating the blocks of each buffer area in the memory pages, wherein the continuous blocks of each buffer area are allocated in the memory pages of different memory set.
Patent TW-438845-B (TW)
Title: Trace metal ion reduction by ion exchange pack
Inventor: RAHMAN M DALIL
IPC: C08G8/12
Filed: 1999-06-10
Granted: 2001-06-07
Abstract: The present invention provides methods for solutions having a very low level of metal ions, utilizing a specially designed ion exchange pack. A method is also provided for producing photoresist composition having a very low level of metal ions from novolak resins purified in a process using such an ion exchange pack.
Patent TW-416214-B (TW)
Title: Scanning device and recognition method capable of automatically identifying the range of object scanned
Inventor: YOU CHING-TU
IPC: G06T1/00
Filed: 1999-06-25
Granted: 2000-12-21
Abstract: The invention relates to a scanning device and recognition method capable of automatically identifying the range of object scanned. It is used to automatically identify the position and size of the document, picture or other similar planar object on the scanning platform relative to the scanning platform. The invention employs a plane sensor to convert the image of the document to be scanned on the scanning platform into electronic signal and automatically determine the position and size (or range) of the object to be scanned relative to the scanning platform by means of the processing and analysis of a logic operation circuit. The actual range of the scanning object can be directly scanned in comparison with the conventional scanning device requiring prescan before determining the actual scanning range so that better operation convenience can be acquired.
Patent TW-455782-B (TW)
Title: Embedded information detection method and system
Inventor: NUMAO MASAYUKI
IPC: G06F21/16
Filed: 1999-08-19
Granted: 2001-09-21
Abstract: To provide a method and a system by which additional electronically embedded information can be safely detected in many and unspecified places. A server reads data in which additional information is embedded, and requests that a tamper resistant device, on which is stored a secret key, perform the detection of the additional information. At this time, the server reads mask patterns from mask data, calculates inner products for the mask patterns and the data in which the additional information is embedded, and transmits the inner products to the tamper resistant device. In order to detect the additional information, the tamper resistant device adds the inner products received from the server, and uses the secret key to determine a threshold value. To determine a threshold value, a mask pattern used for detection is created by using a secret key that is internally stored in the tamper resistant device. The inner product of the data received from the server and the mask pattern is calculated to determine whether information has been embedded.
Patent TW-436917-B (TW)
Title: Method of enhancing semiconductor wafer release
Inventor: LIN CHENTING
IPC: B24B37/04
Filed: 1999-09-23
Granted: 2001-05-28
Abstract: In accordance with the present invention, a method is disclosed for releasing semiconductor wafers from a polishing pad. The method includes the steps of applying a slurry to a polishing pad, rotating the polishing pad having slurry thereon while applying pressure against a wafer such that the wafer is polished by the slurry, introducing water to the polishing pad, increasing the rotational speed of the polishing pad to remove a portion of the slurry, decreasing the pressure during the step of increasing rotational speed to substantially prevent further polishing and removing the wafer from the polishing pad.
Patent TW-478148-B (TW)
Title: Deep trench type capacitor structure and the manufacturing method thereof
Inventor: LUO JI-JIN
IPC: H01L27/108
Filed: 1999-10-29
Granted: 2002-03-01
Abstract: A deep trench type capacitor structure and the manufacturing method thereof are disclosed, wherein the method comprises forming a deep trench whose depth is more shallow than the traditional one in the substrate, forming a dielectric layer in the deep trench, forming plural discrete hemispherical polysilicon grains, proceeding an etching process to the dielectric layer on the bottom of the deep trench using this hemispherical polysilicon as the etching mask, defining the dielectric layer with similar shape as the hemispherical polysilicon, proceeding a polysilicon etching process to remove the hemispherical polysilicon, and at the same time, forming plural fin structures on the substrate under the deep trench using the dielectric layer with similar shape as the hemispherical polysilicon for use as the etching mask, and then proceeding the fabrication of capacitor.