Patent GB-1184511-A (GB)
Title: Improvements in or relating to Translators for Use in Telecommunication Switching Systems.
Inventor: HILLS MICHAEL TURNER
IPC: H04Q3/545
Filed: 1966-03-28
Abstract: 1,184,511. Automatic exchange systems. GENERAL ELECTRIC & ENGLISH ELECTRIC COMPANIES Ltd. 22 March, 1967 [28 March, 1966], No. 13496/66. Headings H3B and H4K. [Also in Division G4] In a translator for translating selected subscriber dialled exchange designations into routing pulses, of the type in which the translations are stored at different locations in a data store, the locations used may be selected on a random basis. Thus storage locations need not be allotted for those dialled exchange designations for which no translation is required. The register translator described connects sequentially to sixty four conversion units on a time shared basis. On initiation of a call a uniselector switch hunts for a free conversion unit and allots it to that call for the duration of the translation unless released due to dilatory dialling. The translator incorporates three separate core storage units, an increment unit which can add or subtract one from a five-bit binary number and test the result for zero, and a decision unit which can test a five bit word or any bit for zero. These units can be selectively interconnected through three five wire buses. One of the storage units comprises sixty four separate registers each of which stores information relating to the call allotted to its conversion unit, e.g. the dial pulse sequence received from the subscriber, or the route selecting pulses to be transmitted to the exchange. During the variable period in which the translator connects to a conversion unit a pulse may be received or transmitted and the data in the associated register updated and tested for critical conditions e.g. the timing for interdigit pauses, time outs to deal with dilatory dialling &c. for this call are effected by numbers stored in the register, periodically reduced by one and tested for zero. Overall control is effected by instructions read from a program store and normally selected sequentially by an instruction counter, and an instruction decoder which passes various clock pulses enabling gates specified by the instruction or any sub-routine instructions selected by it. Since the translations required are stored at random locations in the translation store an index as to their locations must be included. This is effected by allotting a random location for each number for which a translation is required, and for each number that can be obtained from such a number by deleting digits from the least significant end of that number, e.g. if a translation for 431 is required directory locations must be allotted to 4 and 43. When four pulses followed by an interdigit pause have been received, the location allotted to 4 is addressed and from it the address of the location allotted to 43 can be read out giving the address of the translation 431. If, for example, translations starting with 46 and 48 are required the location allotted to 43 also gives the address of the location allotted to 46 which gives the address of a required translation, e.g. 463 and the address of the location allotted to 48. Thus each directory location stores two addresses. Each directory location also stores indications of the numbers of pulses yet to be received to complete the codes to which these addresses were allotted, e.g. The location 46 indicates that two pulses are to be received to complete code 48 and that three pulses following an interdigit pause are to be received to complete code 463. These indications are read out and one or other decreased by one each time a pulse is received. After each complete digit has been dialled one of these indications will have reached zero indicating that its associated address is required. The read only program store (Fig. 13) comprises a set of wires individually selected by code point technique (co-incidence selection of both ends). Each wire links selected ones of a set of magnetic cores, arranged to operate over a linear part of their characteristic. Each core 23 is linked to a second smaller core 22 by a closed loop 24. When the selected wire is pulsed the cores 23 switch their associated cores 22 to their other saturated state. A three dimensional storage array of ferrite cores selected by coordinate techniques (Fig. 14) and having X and Y driving wires which each link all cores of an associated plane is used as the register store. The sense and inhibit wires link all cores in planes perpendicular to the X and Y planes.