Patent GB-1412689-A (GB)
Title: Description driven micro-programmable multi-processor system
IPC: G06F9/46
Filed: 1973-05-01
Abstract: 1412689 Data processing systems BURROUGHS CORP 1 May 1973 [16 May 1972] 20624/73 Heading G4A In a microprogrammed multiprocessor system data is accessed, during execution of programs, by assigning a block of memory to each program and providing in each block a source of descriptions for referencing information stored in the memory and a source of name registers for isolating specific data within the stored information, the specific data being retrieved using name register and description pointers in at least one of the program instructions. In Fig. 14, an instruction 188 contains an address field 194 pointing to a chain of descriptions 196-202 defining the sides of basic and larger data units, up to the size of a dataarea 204 in memory, and the starting address of that area. The instruction 188 also includes a pointer to a name register 192 whose contents define the number of basic data units to be accessed and their location within the area 204 in terms of the various data units. When a program or process is initiated it is assigned a work area and the base address of the work area is placed in the base register 62 of the processor assigned to the process, Fig. 4. The work area 100, Fig. 9, includes a state vector 102 containing all the information necessary to start the process running. The starting address of the program in BPR 112, is pointed to by a description. Descriptions are direct or indirect, pointing to information to be accessed or another description respectively. Each has a format field defining the structure and unit size of the information element it is associated with. A tag bit indicates whether the location field is an absolute memory address or whether it is an address relative to the base work area BWA or a base subroutine register BSR of the state vector, BWA or BSR being specified by the highest bit of the field. A qualification field specifies the allowed usage of the associated information, and further tags determine how the various fields are to be interpreted. A name register tag designates the number of a name register which contains the value to be used in locating the next description.  Microprogrammed processor Fig. 4.-Each processor includes a microprogram memory 26 which is addressed by a selected one of registers 25, 27 with or without incrementing by 1 or 2. Each microinstruction read from memory 26 addresses an N-memory 24 (read-only, readwrite, or wired logic) to produce an enable word for the various functional units to execute the microinstruction. The logic unit LU can perform arithmetic, shift and logic operations and includes an adder, a set of A registers, a B register which can be loaded from a switch interlock providing communication between the processors, memory modules and I/O devices or from the adder before or after shifting by a shift network (barrel switch). Control unit CU includes a shift amount register SAR, a condition register 30 and associated testing logic and part of a control register 34a for controlling LU. Memory control unit MCU has a microprogram addressing section 54, a memory/I/O device addressing section 58, and a Z register section 68 providing a further input to the adder in LU in addition to those from the A and B registers. The switch interlock communicating between processors memory modules and I/O devices has a parallel-serial shift register for each processor and a serial-parallel shift register for each memory module or I/O device. The interlock resolves conflicts between processors requesting use of the same memory module or I/O device such as a disc file, magnetic tape unit, card punch or printer.