baber/WOPTO huggingface dataset:
Patent TW-531726-B (TW)
Title: Device circuit of a liquid crystal display device
Inventor: NISHIMURA MITSUHISA
IPC: G09G3/20
Filed: 2000-11-30
Granted: 2003-05-11
Abstract: The present invention discloses a drive circuit of a liquid crystal display device that transfers image data to a liquid crystal panel which is able to reduce the amount of change of the value of each bit of data transferred over a bus line. In the case the number of data signals that cause a polarity change in the output to a bus line is equal to or greater than the majority of data signals for each of four output ports, controller 2 inverts the polarity of all data signals, and outputs each data BUS-A1-24, BUS-B1-24, BUS-C1-24 and BUS-D1-24 from each output port to the bus line. In addition, since controller 2 outputs polarity inversion signals INV-A through INV-D, which indicate that the polarity of data signals output to the bus line has been inverted, for each of the four output ports, the amount of change in polarity of the output to the bus line can be reduced by half or more of the transferred data signals.
Patent TW-487917-B (TW)
Title: Semiconductor memory device
Inventor: KOJIMA MAKOTO
IPC: G11C16/06
Filed: 2000-12-08
Granted: 2002-05-21
Abstract: A semiconductor memory device 100 includes: a differential sense amplifier 9 having an input node 9a and an input node 9b, an information read section 110a, a reference section 110b, and a control section 140. The information read section 110a includes: a main bit line MBL coupled to the input node 9a; a select gate 4a; a sub-bit line SBL which is coupled to the main bit line MBL via the select gate 4a; a memory cell 1 which is coupled to the sub-bit line SBL and which is selectively activated in accordance with a voltage on a word line WL; a precharge section 120a for precharging the input node 9a and the main bit line MBL to a supply voltage Vdd; and a reset section 130b for resetting the sub-bit line SBL to a ground voltage Vss. The control section 140 controls the precharge section 120a, the reset section 130a, and the select gate 4a so that a portion of a charge which is precharged in the input node 9a and the main bit line MBL is redistributed to the sub-bit line SBL after precharging the input node 9a and the main bit line MBL to the supply voltage Vdd and resetting the sub-bit line SBL to the ground voltage Vss.
Patent TW-492168-B (TW)
Title: Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size
Inventor: ESKILDSEN STEVEN R
IPC: H01L25/065
Filed: 2000-12-20
Granted: 2002-06-21
Abstract: Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size. A lower die has keep out areas on its top surface. The keep out areas correspond to two adjacent edges of the lower die. The lower die has bond pads within the keep out areas. An upper die is stacked on the top surface of the lower die such that the bond pads within the keep out areas of the lower die are exposed to accept wire bonds. The configuration of the keep out areas next to adjacent edges of the lower die thus provides flexibility in the design of stacked chip packages because the size of the upper die is not limited by the bond pad configuration of the lower die.
Patent TW-I262082-B (TW)
Title: Minari extract for prevention of induction and metastasis of cancer due to carcinogens within cigarette smoke or fermented foods or alcoholic beverages
Inventor: LEE INSU P
IPC: A61K36/23
Filed: 2000-12-26
Granted: 2006-09-21
Abstract: The present invention relates to an extract of the Minari plant containing a component which prevents cancer and cancer metastasis. More particularly, the present invention relates to a Minari extract which is useful for the prevention of cancer and cancer metastasis induced by urethane (EC (ethylcarbamate)), which is a carcinogen present in fermented foods or alcoholic beverages, or by NNK[{(4-N-methyl-N-nitrosoamino)-1-(3-pyridyl)-1-butanone}], which is a carcinogen present in cigarette smoke.
Patent TW-518686-B (TW)
Title: System for automatic control of the wall bombardment to control wall deposition
Inventor: JOHNSON WAYNE L
IPC: G01B15/02
Filed: 2000-12-28
Granted: 2003-01-21
Abstract: A method and system for controlling the bombardment of a wall of an electrically shielded RF (ESRF) source to control wall deposition. By measuring a thickness of a deposit on a wall, the method and system can determine how to control the bias voltage applied to the bias shield of the ESRF source. Thickness can be measured using any measurement technique (e. g., microwave, eddy current probe, capacitive probe and interferometric).
Patent TW-552183-B (TW)
Title: Power tools
Inventor: BEER JOSHUA M
IPC: B25F5/00
Filed: 2001-01-20
Granted: 2003-09-11
Abstract: A power tool is provided which includes a motor assembly having a rotatable motor shaft mechanism, and a motor control coupled to the motor assembly and operable between a normal off condition de-energizing the motor and an on condition energizing the motor. The tool includes a rotatable tool shaft mechanism, and a clutch shiftable between a normal disengaged condition decoupling the motor shaft mechanism from the tool shaft mechanism and an engaged condition coupling the motor shaft mechanism to the tool shaft mechanism. A trigger member is engageable with both the motor control and the clutch and is moveable between a first position, wherein the motor control is in its off condition and the clutch is in its disengaged condition, and a second position holding the motor control in its on condition and the clutch in its engaged condition for driving the tool shaft mechanism. The trigger member is designed to prevent premature energization of the motor assembly.
Patent TW-556163-B (TW)
Title: Data recording apparatus, data recording method, and optical recording medium
Inventor: SHISHIDO YUKIO
IPC: G11B27/24
Filed: 2001-03-29
Granted: 2003-10-01
Abstract: Data is recorded on packet basis to a track of an optical recording medium and the data is pseudo-erased by erasing contents information of the track having the data. Information indicating the end position of the packet containing the data is recorded on the optical recording medium and a new data is recorded to the track where the data has been pseudo-erased in accordance with the information indicating the end position of the packet.
Patent TW-504932-B (TW)
Title: Video conference system of wireless network browsing device and its implementation method
Inventor: CHANG JU-NAN
IPC: H04L12/58
Filed: 2001-04-04
Granted: 2002-10-01
Abstract: There are provided a video conference system of wireless network browsing device and its implementation method. A wireless network browsing device is provided at one side of each user for coupling to an image capturing device, a voice capturing device, an image output device and a voice output device, wherein the wireless network browsing device includes a first video processing unit, a second video processing unit and a voice encoding/decoding unit. The other sides of the users to be connected perform a video conference with one another by the wireless network browsing devices through a wireless local area network (WLAN).
Patent TW-I246401-B (TW)
Title: Process for producing cysteinylglycine-enriched food material and process for producing flavor-enhancing agent
Inventor: NISHIMURA YASUSHI
IPC: A23L27/00
Filed: 2001-04-04
Granted: 2006-01-01
Abstract: Disclosed in this application are a method for producing a food material containing cysteinylglycine at a high content, which comprises the step of (a) maintaining a starting food material containing glutathione in a ratio of 1% by weight or more based on the solid content at a temperature of 50 to 120 DEG C and a pH of 1 to 7 in the presence of water, or (b) treating the food material with a gamma-glutamylpeptide hydrolase at a temperature of 15 to 70 DEG C and a pH of 3 to 9 in the presence of water, whereby a food material rich in cysteinylglycine is allowed to result, as well as a method for producing a food flavor (or savor) enhancer, which comprises the steps of (a) adding a sugar to cysteinylglycine or a food material containing cysteinylglycine in a ratio of 0.5% by weight or more based on the solid content, and (b) heating the resulting mixture at a temperature of 70 to 180 DEG C for a period of 10 to 180 minutes in the presence of water, whereby a natural food material containing cysteinylglycine at a high content, and therefore, a food savor enhancer rich in cysteinylglycine, can be easily provided.
Patent TW-528809-B (TW)
Title: Method for manufacturing high strength bolt excellent in resistance to delayed fracture and to relaxation
Inventor: KOIKE SEIICHI
IPC: C21D8/06
Filed: 2001-04-06
Granted: 2003-04-21
Abstract: A high-strength bolt having excellent delayed fracture resistance and stress relaxation resistance in addition to a tensile strength of 1200 N/mm<SP>2</SP> or higher is disclosed. A steel material for the high-strength bolt includes C: 0.50 to 1.0% by mass (hereinafter, referred to simply as ""%""), Si: 0.5% or less (not including 0%), Mn: 0.2 to 1%, P: 0.03% or less (including 0%) and S: 0.03% or less (including 0%). The steel material has pro-eutectoid ferrite, pro-eutectoid cementite, bainite and martensite structures at less than 20% in total and a pearlite structure as the remainder. The high-strength bolt is produced by drawing the steel material severely to obtain a steel wire, forming the steel wire into a bolt shape through a cold heading, and subjecting the shaped steel wire to a blueing treatment at a temperature within a range of 100 to 400 DEG C.
Patent TW-I287131-B (TW)
Title: Light guide plate of a liquid crystal display fabricated by molding aggregation method
Inventor: GUO JIN-BIAU
IPC: G02F1/13
Filed: 2001-05-11
Granted: 2007-09-21
Abstract: This invention is a technology with molding aggregation method to fabricate the light guiding plate of the liquid crystal display. The manufacturing method includes: preparing a double-wedge mold for the aggregating process; blending compounds of the methyl methacrylate and the polymerization; polymerizing the compound; liquidizing the polymerized compound; mixed the liquidized compound into the mold; polymerizing the compound in the mold by the heat treatment; finally, removing mold. Thus, a light guide plate with double-wedge shaped transparent acrylic is provided. This invention provides the method suitable to produce the double-wedge light guide plate in quantity, especially for the large size liquid crystal display.
Patent TW-517408-B (TW)
Title: Antenna and wireless device incorporating the same
Inventor: OHARA MASAHIRO
IPC: H01Q5/10
Filed: 2001-06-07
Granted: 2003-01-11
Abstract: This invention provides an inverted F-shaped antenna and a wireless device incorporating the same. The device has an antenna element, which is formed from a conductor that is disposed on and that is spaced apart from a ground conductive plate. The conductor has at least one part that is generally coiled. A stub is connected to both an end of the antenna element and the ground conductive plate. A power supply line is connected electrically to both a power supply point of the antenna element and an external circuit, which are spaced apart from each other at a predetermined distance. The antenna element is attached fixedly to the ground conductive plate by means of a retaining member that is made of a dielectric material.
Patent TW-519661-B (TW)
Title: Semiconductor memory device and method of identifying programmed defective address thereof
Inventor: CHOI JONG-HYUN
IPC: G11C29/00
Filed: 2001-06-27
Granted: 2003-02-01
Abstract: A semiconductor memory device includes a memory cell array, a defective address programming means, a redundant enable signal generating means, an output means, and a mode control signal setting means. The memory cell array comprises a plurality of memory cells. The defective address programming means programs a redundant control signal and a defective address of defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion. The redundant enable signal generating means generates a comparison coincident signal in response to the redundant control signal when the address is consistent with the defective address. The output means outputs the comparison coincident signal to an external portion in response to a second control signal during a test operation. The mode control signal setting means sets a state of the first and second control signals in response to a command signal and a mode setting signal applied from an external portion.
Patent TW-519731-B (TW)
Title: Method for producing bipolar complementary metal oxide semiconductor
Inventor: LI CHUAN-YING
IPC: H01L21/8238
Filed: 2001-07-02
Granted: 2003-02-01
Abstract: The present invention discloses a method for producing a bipolar complementary metal oxide semiconductor (CMOS) capable of producing a radio CMOS and a high performance bipolar transistor at the same time. The invented method not only can integrate the merits of having a high speed and a high driving current of a bipolar transistor with the merits of having a high integration and a low energy consumption of a CMOS, but also applies the HBT process of the bipolar transistor on the MOS part of the bipolar CMOS, thereby simultaneously increasing the performance of the two devices such that the combined device is more suitable for the industrial applications.
Patent TW-494457-B (TW)
Title: Method for predicting consumption of consumable part, method for predicting deposited-film thickness, and plasma processor
Inventor: SAKANO SHINJI
IPC: H01L21/302
Filed: 2001-07-03
Granted: 2002-07-11
Abstract: There has been conventionally no method for predicting the consumption of a consumable part and the deposited film thickness without opening a processing chamber. The method for predicting the consumption of a consumable part of the present invention used for a plasma processor which subjects a wafer W to a predetermined processing with a plasma generated from a processing gas by impressing a high-frequency power and for predicting the thickness of a deposited film has the characteristics: the voltages and current of a fundamental wave and a harmonic wave of a high-frequency power source (20) which vary with the thickness of a focus ring (21) and the thickness of the deposited film are measured with time, and measurement data on the voltages and the currents is used for multiple-regressive analysis to predict the thickness of the focus ring (21) and the thickness of the deposited film.
Patent TW-505598-B (TW)
Title: Heat resistant neck part of synthetic resin bottle body
Inventor: OZAWA TOMOYUKI
IPC: B29C49/64
Filed: 2001-07-09
Granted: 2002-10-11
Abstract: A PCO (plastic closure only) heat resistant neck part capable of surely and easily providing the heat resistance of a PCO neck part and remarkably saving resources by providing the heat resistant PCO neck part with a pressure resistance using the structure of the PCO neck part; wherein a thread extension part (4) having a tubular wall (2) of the same inside and outside diameter dimensions as those of the tubular wall (21) of the heat resistant neck part (20) and forming the start end portion of a thread (3) of a continuous thread structure is formed extendably through a large center angular range in the structure at a specified distance from the upper end surface of the tubular wall (2); a bead ring (6) and a neck ring (6) are formed in the same structure as those of the PCO neck part (10), and the entire part of the neck part is flashed by thermal crystallization, whereby a sufficient heat resistance and resources saving effect can be provided without producing an improper shrink deformation.
Patent TW-546402-B (TW)
Title: A method of forming silicon containing thin films by atomic layer deposition utilizing trisdimethylaminosilane
Inventor: KIM YEONG-KWAN
IPC: C23C16/34
Filed: 2001-07-16
Granted: 2003-08-11
Abstract: An atomic layer deposition method of forming a solid thin film layer containing silicon. A substrate is loaded into a chamber, after which a first reactant containing Si and an aminosilane is injected into the chamber. A first portion of the first reactant is chemisorbed onto the substrate, and a second portion of the first reactant is physisorbed onto the substrate. The physisorbed second portion of the first reactant is then removed from the substrate, by purging and flushing the chamber in one preferred embodiment. A second reactant is then injected into the chamber, where a first portion of the second reactant is chemically reacted with the chemisorbed first portion of the first reactant to form, a silicon-containing solid on the substrate. The non-chemically reacted portion of the second reactant is then removed from the chamber. In one preferred embodiment, the silicon-containing solid formed on the substrate is a thin film layer, a silicon nitride layer for example. In other preferred embodiments, the first reactant is at least one selected from the group consisting of Si[N(CH3)2]4, SiH[N(CH3)2]3, SiH2[N(CH3)2]2 and SiH3[N(CH3)2]. The second reactant is preferably activated NH3. The chamber pressure is preferably maintained in a range of 0.01-100 torr. and in preferred embodiments can be maintained constant throughout the process, or can be varied in at least one of the four steps. One or more of the foregoing steps can be repeated to achieve a thicker solid on the substrate.
Patent TW-519727-B (TW)
Title: Semiconductor wafer, semiconductor device and manufacturing method therefor
Inventor: MIYAGAWA YUICHI
IPC: H01L21/78
Filed: 2001-07-31
Granted: 2003-02-01
Abstract: The invention aims to easily suppress chipping on the reverse face of a semiconductor when a semiconductor wafer is cut, and to make it possible to easily prevent edge contact of bonding wires. A resin film (14) is formed at the periphery of boundary regions (corresponding to 6) provided for chip separation of semiconductor chips (8). Then, the semiconductor wafer (1) is diced by cutting along the central part (corresponding to 7) of the boundary region. Furthermore, in a semiconductor device having semiconductor elements formed on a semiconductor substrate, the resin film (14) is formed on a part of the boundary regions provided for chip separation, matching the bonding pads (3) of each chip. Alternatively, the resin film (14) is formed with a predetermined width on the periphery of the abovementioned boundary regions. Additionally, the arrangement is such that the semiconductor substrate (9) and the abovementioned wires do not touch when bonding wires (16) are connected at the time of mounting the semiconductor chips.
Patent TW-504412-B (TW)
Title: Replacing facility of roller and method thereof for six-sectional rolling mill
Inventor: YAMADA SHIGEKAZU
IPC: B21B31/10
Filed: 2001-08-09
Granted: 2002-10-01
Abstract: This invention is of replacing facility of roller and method thereof for six-sectional rolling mill used in altering four-sectional rolling mill into six-sectional rolling mill. For top and bottom processing roller 11, 12 and top middle roller 13, a conventional technique is applied to set rolling mill replacing device 1 of side displacement type. For altering bottom middle roller 14, a side displacing device 5 set on ground level (work level) 101 and a lift 28a of side displacing device 5 will descend the bottom middle roller 14 to the under side of ground level 101 after roller 14 is connected to trolley 2 and dragged out. In addition, the displacing device will replace the used bottom middle roller with a new one under the ground level, then lift 28a will uplift the new roller and the trolley will drive it into the rolling mill. The replacing method and procedures mentioned above require no alteration of the height of roller replacing device before the four-sectional rolling mill altered into six-sectional rolling mill and require almost no digging work in the side front operation space of the rolling mill.
Patent TW-495475-B (TW)
Title: Sucking nozzle of compression preservation bag
Inventor: OTSUBO RYOICHI
IPC: B65B31/04
Filed: 2001-10-15
Granted: 2002-07-21
Abstract: A sucking nozzle of a compressive preservation bag capable of normally compressively accommodating a to-be-accommodated object without air leakage when the sucking nozzle is inserted into the compressive preservation bag to compressively accommodate the to-be-accommodated object by using the sucking nozzle. A sucking nozzle (10), for use in a compressive preservation bag (100), which is made of air-unpermeable synthetic resinous material and has a check valve (110) made of synthetic resinous material at a portion thereof. The sucking nozzle (10) has a body (12) which is long and has an insertion section (16) which is made flatly cylindrical and tapered to be inserted into said check valve (110). The insertion section (16) of said body (12) has a plurality of openings (20, 22, 24) communicating with an inside of said body (12).
Patent TW-495945-B (TW)
Title: Semiconductor packaging method for preventing whisker growing on outer leads of a lead frame
Inventor: CHUNG CHO-LIANG
IPC: H01L23/495
Filed: 2001-10-18
Granted: 2002-07-21
Abstract: A semiconductor packaging method for preventing whisker growing on outer leads of a lead frame comprises: providing a lead frame, packaging semiconductors, plating the lead frame, reflow heating the lead frame, and trimming the lead frame. A plurality of semiconductor chips are packaged on a lead frame, then plating the lead frame to form a metal layer such as tin or tin alloy, and reflow heating the metal layer to eliminate stress, then trimming the lead frame. Therefore, whisker-growth is prevented.
Patent TW-519570-B (TW)
Title: Software simulation test method of sequential circuit
Inventor: JENG SHIN-YUAN
IPC: G01R31/26
Filed: 2001-10-24
Granted: 2003-02-01
Abstract: A kind of software simulation test method of sequential circuit is disclosed in the present invention. In the method, plural virtual register variables are first defined in the simulation test program. After that, each test data in a test data row is inputted and stored in the corresponding virtual register variable. The, by using the parallel loading manner, each test data is inputted to the corresponding scan flip-flop from each virtual register variable, and is followed by sequentially executing hold sequence, capture sequence and reshift sequence. From the primary output signal outputted from the primary output terminal of the combinational circuit and the output signal outputted from the signal output terminal of each scan flip-flop, whether there is an error in the circuit design of the sequential circuit or not is known.
Patent TW-550401-B (TW)
Title: Optical passive device
Inventor: CHANG SEAN
IPC: G02B6/26
Filed: 2001-11-22
Granted: 2003-09-01
Abstract: An optical passive device is disclosed, which comprises a collimator and a reflective unit. The collimator is provided to collimate an optical signal, and has a light source input terminal and at least a light source output terminal, wherein the light source input terminal receives the optical signal, and the light source output terminal outputs the optical signal. The reflective unit has a first reflective surface and a second reflective surface, and at least one part of the optical signal is reflected by the first reflective surface and the second reflective surface to the light source output terminal.