Patent GB-1023029-A (GB)
Title: Circuitry for reducing the number of bits required to represent a given sequence of data
IPC: H03M7/42
Filed: 1963-07-16
Abstract: 1,023,029. Learning circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. July 16, 1963 [July 17, 1962], No. 28034/63. Heading G4R.  A device for converting a digital data code to a more compact form automatically adjusts its choice of code as the statistics of its input changes. In one form (Fig. 2, not shown) an array of eight groups of four magnetic core ring counters is arranged to record, for each of the eight possible combinations of three bits, the number of times that each of the four possible two-bit combinations follows the particular three-bit combination. From these counts the current most likely two-bit combination to follow each threebit combination is determined and recorded in a random access core store 68. When a three-bit combination is received on a line 10 from a source 40 it is converted to parallel form by a shift register 44 and passed to a decoder 62 which passes a clock pulse from a line 64 to energize one of eight drivers 66 to read out the current likely bit pair for the particular three-bit combination to a shift register 72. This predicted bit pair is compared in an exclusive or gate with the next two bits from the source 10 and if they agree a zero appears on output 32, alternatively a one appears. In this manner, strings of zeros indicating correct predictions are produced with occasional ones in between. The zeros may then be run coded for transmission. At the receiving station a similar apparatus makes the same predictions to reconstruct the message. A counter 80 which is periodically reset is provided to count the number of incorrect predictions in each time interval. If this count exceeds a predetermined amount an overflow is generated causing an inhibit signal, to prevent the current values in the store 68 from being recirculated and rerecorded and triggers a clock 92 so that a comparator 102 redetermines the current most likely bit pair to follow each bit triplet by finding which of the four counters in 58 for each bit triplet has the highest value recorded. When any one of a group of four counters 58 is full the current value of all the four may be halved. In the form shown in Fig. 3 (not shown) an M bit sequence from source 40 is fed to a shift register 142 which produces an output on one of 2<SP>M</SP> lines, which output is particular to a single combination. The output is gated to one of a corresponding pair of counters, e.g. 152, 154 according as the next bit from the source 4D is a one or zero. A corresponding comparator 158 generates a one or a zero according to whether the " one " counter 152 is at a higher or lower count than the " zero " counter 154. An OR gate 160 passes this predicted next bit to a line 140 where it is combined with the actual next bit in an exclusive OR gate 18 as in the first embodiment. An additional weighted count may also be added to the counters. In further embodiments a Shannon-Fano code converter is used. This takes the input bits and for each group of, say, three bits converts them to a code with variable length words (2, 3 or 4 bits long) so chosen so that the more frequent input words are converted to two-bit words. Counting circuits similar to those already described are used to update the choice of code.