Patent GB-1219549-A (GB)
Title: A character reader
Inventor: KOBAYASHI KIRAO
IPC: G06V30/10
Filed: 1969-04-18
Abstract: 1,219,549. Character recognition. NIPPON ELECTRIC CO. Ltd. 18 April, 1969 [18 April, 1968], No. 20034/69. Heading G4R. In a character reader, the positions of two opposite edges of the character are monitored during scanning of the character to determine the relative positions of strokes detected and used in recognition. The character is moved horizontally past a column of 40 photo-cells 201, Fig. 3 (a) left, the outputs of which are amplified and digitized at 202, then sampled in turn, to give repeated vertical scans, under control of counters 207 cycled by a bit-time oscillator 700, to feed a shift register 300 having cells for one and a part vertical scans. A character-present detector 801, Fig. 3 (b) top left, responds to shift register stages as shown to set a flip-flop 803 which via a monostable 822 sets a VC counter to 2 (since 3 adjacent black bits are required to satisfy 801) and sets an XC counter 832 to 0. Flip-flop 803 also enables AND 804 so that the VC and XC counters can be cycled by oscillator 700. Since the VC counter has a capacity of 40, it indicates the vertical scanning position relative to the top of the character (the vertical scanning is downwards) as so far determined, the top corresponding to a count of 0. Decoders 806-818, 833- 835 connected to the outputs of the VC and XC counters produce an output pulse whenever the count has the indicated value or values, e.g. decoder 806 at a VC count of 1 and decoder 807 at each VC count in the range 1-17. The bottom of the character is detected by AND 830, Fig. 3 (b) bottom left, in response to the shift register 300 (via logic network 825), the VC decoder 807 and the XC decoder 834, to set the XC counter to 0, whereafter it indicates the vertical scanning position relative to the bottom of the character, the bottom corresponding to a count of 0, since it has a capacity of 40 and is cycled by the oscillator 700. The significance of the particular counts detected by the VC and XC decoders can be seen if it is remembered that the vertical scan is 40, the zero counts correspond to character top and bottom, and the character height is typically 16. The VC counter may not indicate the true top of the character, but rather the top of some lower first-encountered portion of the character. If so, it is corrected by AND 820, Fig. 3 (b) middle left, in response to logic network 825, VC decoder 814 and XC decoder 835, the AND 820 setting a flip-flop 821 to set the VC counter to 1 via a monostable 823. Flip-flop 821 is reset every vertical scan by VC decoder 810, which also increments an HC vertical scan counter 841 having decoders 842-845. The character can have upper and lower vertical strokes in each of 5 horizontally-displaced positions. Upper and lower vertical stroke detectors 401, 402, Fig. 3(a), respond to the shift register 300 at the appropriate times, as defined by VC decoders 808, 809, during every second scan (HC decoder 842), to feed a vertical stroke shift register 407, connected as shown. Shift register 407 is shifted twice every scan line, to enter an upper and a lower vertical stroke indication if present, by the upper input to OR 852, Fig. 3(b) middle right, but an extra correction shift is provided via the lower input of OR 852 if the first vertical stroke detected is a lower stroke and is erroneously taken as an upper stroke. The lower input of OR 852 is fed from a monostable 857 on setting of a flip-flop 860 which occurs on conjunction of pulses from VC decoder 806, XC decoder 833 and logic network 861, provided a flip-flop 856 has not been set by the conjunction of outputs from VC decoder 813 and logic network 825. Logic network 861 produces an output if any of the upper stroke stages of shift register 407 is set and none of the lower stroke stages is. The character can also have upper, middle and lower horizontal strokes. To detect these, signals from the shift register 300 at OR 501, Fig. 3(c) top left, are fed at appropriate times defined by VC decoders 815-818 (which produce pulses VTU, VTM, VTL, VTT) to UC, MC, LC, TC counters 508-511, according to the time and whether or not a correction shift at register 407, Fig. 3(a), has occurred, as indicated by signals EXP, NXP from flip-flop 860, Fig. 3(b). Decoders 512-515 respond to counts of 6 to set flip-flops 516-519, the outputs of which are combined with signals EXP, NXP in logic 520 to produce upper, middle and lower horizontal stroke indications HU, HM, HL. A counter reset block 521 responds to the signals shown to selectively reset particular counters 508-511 to prevent vertical strokes being detected as horizontal. The equations for logic 520 and block 521 are given in the Specification. Recognition logic 600, Fig. 3(a) right, responds to the vertical strokes register 407 and the horizontal stroke indications HU, HM, HL to identify the character when HC decoder 844 and VC decoder 811 in combination produce a signal CSP. Fig. 5 (not shown) shows a truth table for the recognition logic 600. A flying-spot scanner, or magnetic heads, may be used instead. The scanning could be horizontal rather than vertical as above, the side edges of the character being monitored instead of the top and bottom.