Patent GB-1291973-A (GB)
Title: Arrangement for controlling the supply of pulses
IPC: H04Q3/545
Filed: 1970-01-07
Abstract: 1291973 Automatic exchange systems TELE FONAKTIEBOLAGET L M ERICSSON 7 Jan 1970 [8 Jan 1969] 875/70 Heading H4K An inpulse regenerator for use in conjunction with senders of a programme controlled exchange comprises a plurality of buffer units each of which includes a counter and a number of sender-address stores. The counter contains the total number of impulses and impulse intervals pertaining to a digit to be sent. Whenever a digit is to be sent by a particular sender, the counters in the various buffers are scanned until one is found which contains this digit whereupon the address of the sender is written into one of the stores associated with this counter. If none of the counters contains the required digit a free counter is selected and the digit is inserted therein while the address of the relevant sender is written into one of the stores. When the digit has been counted out of the counter, the associated stores are cleared. Optimum use of a minimum number of buffer units without the necessity to synchronize the operation of all the buffers is thereby obtained. The arrangement finds utility where programme controlled exchanges have to work compatibly with electromechanical exchanges. Particular description.-The buffer units Bq are accessed cyclically by a shift register SH which is only operative during the search for a suitable buffer i.e. it stops on finding. A clock CL provides 2 degrees m.sec. pulses to a local timer T in each of the buffers. In operation, the address of a sender which is to be used is inserted in register REG R and the value of the digit e.g. 5 to be sent (in terms of the number of impulses e.g. 5, number of pauses i.e. 4 and a fixed integer 1 viz, 5 + 4 + 1 = 10) is inserted in register S. Shift register SH is started so that at each stage, e.g. Eq, the contents of REG S and the buffer unit Bq's counter PC can be compared in C1 Assuming that coincidence occurs for buffer Bq, the address in REG R is written into one of storage cells bl-b15. Thereafter the contents of local timer T are compared with the real time from CL so as to activate a comparator C2 on coincidence. Since PC always contains an even number viz 10 in the present circumstances the first coincidence decrements the count in PC by 1 and opens gate OP2 so that a the time in timer T is incremented by 40 m.sec. and b a signal is passed to bi-stables V1-Vn to the effect that an impulse interval of 40 m.sec. is to be provided by the senders connected to terminals R. The sender addresses in b1-bn are translated in AVKR so as to provide second inputs for the gates 01... On. At the next coincidence in C2, PC is again decremented by 1 but on this occasion gate OP1 is opened to a increment timer T by 60 m.secs. and b signal the bi-stables and hence the senders that an impulse should be sent. This procedure repeats with additional senders addresses being written into bI-b15 if these senders need to send a digit that corresponds to the instantaneous count in PC. Eventually PC counts-out and the buffer is then cleared. Considering now the possibility that no buffer counter contains the required digit so that all the stores b1-15 in a suitable buffer are full, then shift register starts a new step at stage 21 whereby a free buffer is sought. Assuming now that Bq is free, the contents REG S are written into PC via gate OZ2 and the contents of REG R are written into b1 (CC steps through stores bl-b15 in turn inserting each new sender address in the next free store) via OE3, OE2. Real time is inserted in local timer T via gate OS. The count down proceeds as outlined above. If the latter possibility is not effective, the shift register is restarted-its total stepping time is kept below 20 m.secs-and the search for a suitable buffer is recommenced.