Patent GB-829950-A (GB)
Title: Electronic multiplier
IPC: G06F7/491
Filed: 1956-06-04
Abstract: 829,950. Digital electric calculating-apparatus ; electric - -digital - data storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 4,1956 [June 2, 1955], No. 17150/56. Class 106 (1). An electronic multiplying device forming part of a series-mode general purpose computer of the type in which single-address instructions are taken in order under the control of an instruction counter is described. The computer employs a C.R.T. main store, uses binary-codeddecimal digits having seven bits per digit (including the zone and the parity checking bit) and uses a C.R.T. store in conjunction with a serial adder to form an accumulator. Multiplication is effected by accumulating successive products of the complete multiplicand with successive digits (starting with the lowest denomination) of the multiplier, the successive products being appropriately shifted with respect to each other. Initially the multiplicand is stored at a specified address of the main store or memory, Fig. 1a, and the multiplier is stored in the accumulator store, Fig. 1d. The first digit of the multiplier is read from the accumulator, passed via a character register 2 and staticized in a multiple-control unit, Fig. 1e, where it causes two leads, such that the sum of their weights is equal to the staticized digit, to be energized, and simultaneously with this, the first digit of the multiplicand passes via a character register 1 and arithmetic input switching, Fig. 1b, directly to a multiple selection unit and also via a doubler, quadrupler and quintupler to the multiple selection unit, which unit is so controlled by the multiple control unit, Fig. 1e, that it only passes those two multiples corresponding to the two energized output leads of the multiple control unit. The two multiples, labelled A and B, that pass through the multiple selection unit, are summed by an adding unit comprising a multiple adder, Fig. 1c, and its associated multiple adder correction circuits. Thus there emerges from the multiple adder and its correction unit on leads " MPL 1," " CMPL 2," " CMPL 4 " and " CMPL 8 " the units digit of the product of the first digits of the multiplier and the multiplicand, which digit is added to zero (the previous partial product) in a digit adder and its associated correction and decimal carry units, from where it passes via an output switch to accumulator, Fig. 1f, to be stored in the accumulator, Fig. 1d (at an address 256 positions away from the units digit of the multiplier). Further digits of the multiplicand follow immediately after the units digit, while the units digit of the multiplier remains staticized in the multiple control unit. This continues until a special character is read from the memory-indicating that all the digits of the multiplicand have been read out-which character is recognized by a recognition circuit, Fig. 1d, and whereupon the tens digit of the multiplier is read into the multiple control unit. The multiplicand is then re-read from memory (having been recirculated via the output switch to memory, Fig. 1f, upon its first reading) and the above sequence is repeated, with the additional feature that the number obtained at the end of the above sequence-the first partial product, which is now in the accumulator-is read from the accumulator and entered into the digit adder via the arithmetic input switching and a true/complement unit, so that it is added to the second partial product, as it is formed, and the resulting sum is entered into the accumulator as before. This sequence of events is repeated until all the multiplier digits have been used when the final product will be in the accumulator. Signed multiplication is possible, the zone bits of the units digit of each number representing its sign. Basic timing cycle, and C.R.T. store.-The basic machine timing cycle (or character cycle) is of fixed length and comprises three periods, Fig. 5b, a read-out period RO in which a single character can be read-out (but not regenerated) from the C.R.T. store, an arithmetic period AO during which a single character is processed by the arithmetic circuits (the machine being serial by characters) and during which a single character is regenerated in the store, and a read-in or write period WO in which a new character can be entered into a store. The C.R.T. store comprises 70 cathode-ray tubes divided into groups of seven, each group storing the seven bits of a character, one bit in each tube, at the same relative beam position in each tube, and the deflection plates of the 7 tubes are connected in parallel. Thus the selection of a particular character requires firstly the positioning of the C.R.T. beams and secondly the selection of a particular group of seven tubes. This is effected by a memory deflection register which can have addresses entered into it from either a memory address register (thus giving access to any part of the store) or an instruction counter (which is advanced at the end of each instruction, thereby causing instructions to be taken from the instruction portion of the store successively) or from a memory regeneration counter (which is advanced at the end of each machine, thereby causing the complete store to be regenerated every 2000 cycles-2000 characters being the store capacity). The 10 groups of 7 storage tubes are associated in pairs to form 5 storage units, and in one tube of each storage unit-the left tubedashes are written by extending dots leftwards, while in the other tube-the right tube-they are written by extending dots rightwards. This is said to permit economies to be effected in the dash deflecting circuits. The operation of the store during one machine cycle, and in particular the operation of one storage unit (2 tubes) thereof takes place as follows:-at the beginning of a cycle a reset pulse (see Fig. 5b) is applied to a trigger 275b, Fig. 2x; at time RO(4) an interrogate pulse writes a dot by momentarily raising the potential of the control grid of the selected tube, the C.R.T. beams having previously been positioned, and a particular group of tubes selected by the memory deflection register into which an address will have been inserted by the memory address register; the bit read-out is amplified and sampled (i.e. " strobed ") by a sample pulse at a gate 274b to appropriately set the trigger 275b, which via two series-connected cathode followers provides the memory output; at time AO the contents of the memory regeneration counter are transferred to the memory deflection register and at time AO(2) the trigger is again reset; at time AO(4) a further interrogation pulse reads out the bit at the selected address which bit is immediately re-entered into the store via the regeneration loop from the pick-up plate of the C.R.T. via amplifier 271b, gate 274b, trigger 275b, cathode follower 272b, mixer 260b, one of gates 259b and 261b to the control grid of the tube, the arrangement being such that the bit read out is stored in the trigger 275b, and if it is a " dash " the trigger causes the control grid to remain positive for the remainder of the AO period, to convert the written dot into a dash (the " select " signals extend for substantially all of the AO and WO periods but only until just after the interrogation pulse in the RO period and the C.R.T. beams are moved slightly by a bit sweep signal only during the AO and WO periods); the operation during the WO period is similar to the operation in the AO period except that no interrogate pulse occurs, the trigger 275b being set by the incoming bit which is to be stored. The address of a word in storage is defined as the address of the first character of the word and circuits are provided for successively increasing the address in the memory address register by unit whereby the successive digits of a word are read out in successive character cycles, until the last character of the word has been read (the word being of arbitrary length), which character is followed by an end of word mark, which when read causes the successive advancement of the address in the memory address register by unity to cease. Accumulator store.-The accumulator store comprises seven storage units of the type used in the main memory, the left-hand units forming an " A " accumulator store and the right-hand units a " B " accumulator store. The accumulator stores differ from the main memory in that they employ a pure binary address instead of a binary coded decimal address. Product generating circuits.-Doubling, quadtupling and quintupling circuits, Figs. 4b, 4c, are described which when a number is applied to them in binary coded decimal form, serial by digit and parallel by bit, provide substantially immediately (there being no delays in the circuits) the two, four and five multiples of the applied number. The doubler (upper half, Fig. 4b), receives the 1, 2, 4 and 8 bits of each input digit on terminals "CR1 to adder 1," " CR1 to adder 2," " CR1 to adder 4 " and " CR1 to adder 8," respectively (the digits coming from character register 1) and it also receives the 1-bit in inverted form on terminal " CR1 to adder 4 " and " CR1 to adder 8 " respectively (the digits coming from character register 1) and it also receives the 1-bit in inverted form on terminal " CR1 to adder T," and the outputs of cathode followers 477, 475, 472 and 469 constitute the 1, 2, 4 and 8 bits of twice the input number. A trigger 465 effects carry storage between the decimal denominations (i.e. successive digits of the input numbers). The output of the doubler is passed to a second doubler to provide (lower edge, Fig. 4b) the bits of four times the input number. The quintupler, Fig. 4c, is similar in principle to the doubler, differing mainly in that as it has to accommodate a carry of up to 4 it includes three carry storage triggers 484, 490, 496. Multiple control and selection circuits.-The multiple control circuit, Fig. 4k,