Patent GB-1463834-A (GB)
Title: Pcm time division multiplex telecommunications systems
IPC: H04Q11/04
Filed: 1974-03-18
Abstract: 1463834 Automatic exchange systems SIEMENS AG 18 March 1974 [29 March 1973] 11882/74 Heading H4K In a time-space time, 4-wire, switching system having control stores for addressing during each connection time slot both the PCM speech stores associated with each highway and the crosspoints of the switching network, the control stores are stepped by connection time slot addresses supplied by a single, phase-counter which is stepped non-uniformly by the exchange clock. The number of connection time slots is double the number of channel time slots on the highways so as to ensure that switching is non-blocking. Serial 8 bit PCM is utilized on the highways and within the space switches, parallel 8 bit PCM being used in the speech stores. General outline of system.-Incoming speech (and signalling) words on a highway Ak are buffered into an incoming store KVS under control of a counter LZ which is stepped at the time slot rate prevalent on the highway. A 4À096 MHz exchange clock T drives a 4-stage counter BZ whose outputs are coded at TS and applied as stepping signals to an 8-stage phase counter PAZ and as control signals to a controllable OR gate OS. The effect of the latter is to distinguish between write control signals supplied by LZ during each incoming time slot, read and write control signals supplied by VHS during each connection time slot and used respectively in addressing incoming and outgoing speech stores KVS and GVS, and read control signals supplied by PAZ during each outgoing channel time slot for the transfer of a speech word from GVS to the outgoing highway Ag. Crosspoint control store KHS is addressed during each connection time slot directly by PAZ. In order to compensate for a 1 bit delay introduced by the gates O1, OZ and amplifiers LS, LF in the space switching network, the buffers DR and MR which respectively operate the decoder D and multiplexer M are arranged to introduce therebetween a 1 bit delay in each cross-point control word supplied from KHS. The 4À096 MHz clock pulse stream T is divided by counter BZ such as to step the phase-counter PAZ at a 2À048 MHz rate which corresponds to the bit rate on the highways of the system. During each cycle of the counter (this corresponding to twice the highway channel time slot rate i.e. being equal to the connection time slot rate) the phase counter is stopped for one counter bit interval (see pulse sequence PAZN) and stepped backwards for another one counter bit interval (see pulse sequence PAZR). Thereby the output coded signal from PAZ has the waveform shown at line PAZ in the Fig. Each switching phase P i.e. a connection time slot address, thus occurs three times during any channel time slot period and these different occurrences in conjunction with the state of the bit counter permit the different read/write operations on the various control and speech stores to be effected in proper sequence. The symbols LZ, VHS, PAZ on the lines KVS, GVS in conjunction with the "write-in" and "read-out" arrows depict in an obvious manner how a speech word is transferred through the speech stores. The symbols in the lower part of the Figure depict how a word 11011001 in the kth highway time slot is switched through the space switch during the pth connection time slot.