Patent GB-1404379-A (GB)
Title: Data processing apparatus
IPC: G06F12/0897
Filed: 1973-11-27
Abstract: 1404379 Data processing systems INTERNATIONAL BUSINESS MACHINES CORP 27 Nov 1973 [2 Jan 1973 (2)] 54954/73 Heading G4A The performance of a proposed multi-level storage system, utilizing selected storage philosophies (defining the manner in which data is to be stored in the different levels) and replacement algorithms, is evaluated by a special purpose hardware monitor which includes directories which emulate the higher levels of storage and counters which record the number of successful and/or unsuccessful accesses made at the various storage levels when a stream of addresses is supplied to the monitor. The average access time can then be computed from the recorded counts and the individual store and fetch operation times at the different levels. Emulation of a storage system employing the set associative buffer technique is described i.e. a system in which blocks in the high speed buffer level L1 are divided into sets of two blocks each, and each block has an associated tag whereby, by inspecting two tags in buffer it can be decided which of a number of specific main memory blocks are in the buffer. For a three-level system the monitor has two directories 102, 105 for storing the block addresses (segment and class names) for levels L1 and L2, and is connected to the address bus 100 of a digital computer employing a single level of storage to provide a stream of addresses to be monitored. Each address originated by the CPU of the computer is broken down by a matrix 101 into segment and class address form appropriate to L1 according to the setting of block and class size selector switches, Fig. 5 (not shown). If the address is found in directory 102, a "hit" is recorded in the appropriate counter 103 according to the type of access, i.e. fetch or store, and if the address is not found, it is passed on to the L2 directory 105. I/O references to storage are made initially to L2, each address being broken down by matrix 104 into segment and class address form appropriate to L2. It is assumed that L1 and L2 have different class configurations so that a change of format is performed by a generator 107 on passing an address from L1 to L2. Directory 105 is searched and a "hit" or "miss" is recorded on appropriate counters 103. Whenever an address is not found in a directory, updating operations are performed according to the storage philosophy adopted: Store Through (a store operation is performed at whichever level the requested block is found and copies at lower levels are updated); Store Wherever (a store operation is performed at whichever level the requested block is found); Store in Buffer (requested block is moved, if necessary, to buffer where all store operations are performed). The directories are, as a result, updated according to the replacement algorithms being utilized, a least recently used replacement alogorithm circuit being described, Figs. 7, 8 (not shown). Counters may also be provided to record which particular blocks within the replacement priority order satisfied the requests and the number of replacements required. The directories and counters are preferably duplicated in the monitor whereby two storage philosophies may be tested simultaneously with the same address stream, and different replacement algorithms may also be selected. The different storage levels may utilize different storage philosophies.