Patent GB-1161993-A (GB)
Title: Improvements in or relating to PCM Systems
IPC: H04J3/07
Filed: 1966-10-13
Abstract: 1,161,993. Multiplex pulse code signalling. NIPPON TELEGRAPH & TELEPHONE PUBLIC CORP. 13 Oct.. 1966 [15 Oct., 1965; 16 Nov., 1965], No. 45730/66. Heading H4L. A system is provided for combining a plurality of low bit speed P.C.M. systems into a high bit speed time division multiplex P.C.M. system by the use of a delay line register which generates a plurality of pulses for each incoming low speed bit and includes means for reading out pulses of any desired phase at the high bit speed so that differences in pulse timing arising between the high and low speed systems may be compensated for. Additional compensation is effected by inserting stuffing pulses in appropriate frames. The delay line register is used in an inverse manner to recover the low bit speed signals. Two types of system are described in which (a) the bits of the low bit speed systems are interlaced bit by bit in the high bit speed system and a single stuffing bit is transmitted as required and (b) wherein the low bit speed signals are combined channel by channel and the stuffing bits occupy a complete channel. System details.-In an embodiment of type (b), Figs. 2a, 2b, 3a, 3b, for converting the low bit speed of signals S1 applied at terminal 101 to a higher bit speed Sh at about terminal 102, it is assumed that each low speed channel consists of four bits and five low speed systems l c1  &c. are to be multiplexed. High speed digit sampling pulses hv and low speed channel pulses l co  are supplied together with the input signal to a gate A 1 . (Pulses l co  and l ce  cause the gates A 1 , A 2  to operate for alternate low speed channels.) The output of A 1  consisting of bits 1<SP>1</SP> to 4<SP>1</SP> of low speed channel l c1  is supplied to a delay line register D 1 . The register D 1  includes a reflecting delay line with a delay 4TH and is arranged to produce a plurality of groups of four short bit signals e 1  to e 7 , each bit in a group being spaced by T h , for each four-bit low speed channel input. A high speed channel timing pulse h co  is supplied to AND gate A 3  so that the group e 4  is read out of the register via OR gate O 1  to provide the high speed P.C.M. signal S h . The pulse h co  is also delayed by 4TH at S 1  and the resulting pulse h do  resets the register D 1  and erases the pulse trains e 5  to e 7 . The gate A 2  and associated circuitry operate in a similar manner, the pulses h<SP>1</SP>p via OR gate 0 3  operating bi-stable # to produce pulses h co , h cc  alternately. Pulses l<SP>1</SP>p of duration Th equal to that of the high speed bit time slots, and coinciding with the leading edge of each low speed channel signal S 1 , are supplied to a phase detector P together with pulses h<SP>1</SP> v  which are phase advanced high speed channel pulses hv. When the phase difference between the two inputs reduces to zero an output p<SP>1</SP> is obtained in phase with the leading edge of low speed channel l c3  which is supplied to a monostable device M 0  to produce a widened pulse p which inhibits gate A 1 . Pulse p<SP>1</SP> shifts the output of a shift register R from h<SP>1</SP> 02  to h<SP>1</SP> 03 , and after a delay of T h  at # 3  the sampling pulse h v  changes from h 2  to h 3  and is phase advanced by T h . Thus, whenever a pulse p occurs, the phase of high speed sampling pulses h #  is advanced by T h  as at h 1 , h 2 -h 5 , causing a different group of pulses d 1  (e 1  to e 4 ) to be read out. When the sampling pulses h<SP>1</SP> 0 q (h 5 ) are used, the pulse train e 1  is read out (Fig. 3b) and when a further phase difference occurs it is necessary to insert a stuffing pulse group I. In this case the output of the phase detector P and output h<SP>1</SP> 0q  of the shift register R are supplied to an AND gate A 5  and the resulting signal via OR gate O 3  changes over the bistable # so that the pulse (h co  or h ce ) at the output of gate A 6  or A 7  is repeated and a special pattern I of stuffing pulses for one channel is read out of the register D 1  or D 2  (as shown in Fig. 3b it is read out of D 1 ). The next pulse h ce  reads out the low speed channel l<SP>1</SP> c2  (pulse train e 5 ) delayed by one channel cycle time. Similar apparatus operating in an inverse manner to separate low bit speed systems from a high bit speed system is described, Figs. 8, 9 (not shown). A type (a) system also is described, Figs. 4, 5a, 5b (transmitting) and Figs. 10, 11a, 11b (receiving) (not shown) in which at the transmitting end a four-bit low speed system is translated into a high speed interlaced bit system. In this system a group of narrow bit signals is produced for each low speed bit signal, an appropriate one of which is selected by each high speed bit sampling pulse. The operation is similar to that previously described, but in addition, a frame sync. signal is inserted at predetermined intervals in the high speed system and when a stuffing pulse is inserted it follows the framing signal.