Patent GB-1130270-A (GB)
Title: Data processing apparatus
IPC: G06F11/10
Filed: 1967-08-17
Abstract: 1,130,270. Data processing systems. INTERNATIONAL BUSINESS MACHINES CORP. 17 Aug., 1967 [21 Sept., 1966], No. 37922/67. Heading G4A. In data processing apparatus, instructions are prefetched into buffers, decoding of a branchon-condition instruction on which the condition data is not yet available causing interruption of normal instruction prefetching and prefetching of at least one instruction along the branch path. As described, two instructions along the branch path are prefetched into the buffers, then successive instructions which will be needed if the branch is not taken are prefetched, decoded and issued to execution circuitry but with a tag attached which prevents their actual execution unless and until the condition is shown to be not met. If the condition is met they are cancelled, the instructions prefetched along the branch path are used and further prefetching occurs along the branch path. The instructions referred to above are 72-bit instruction words and each may include more than one actual instruction, the possible instruction lengths being 16, 32 and 48 bits. Three incrementable control registers specify the memory address of the last instruction word prefetched, the address of the instruction being decoded and the address of the oldest instruction word remaining in the buffers. If comparison of the contents of the last control register with the branch address in a branch-on-condition instruction (when the latter is being decoded) indicates that the whole instruction loop is in the buffers, the third control register is set to the branch address and the loop is iterated using the instructions in the buffers until the branch condition is shown to be not satisfied, further prefetching being inhibited, but the tagging arrangements above still apply. If the whole loop could be contained in the buffers but is not, the three control registers are initialized to the branch address (loop beginning) and the loop is prefetched into the buffers, from which it can be iterated without further prefetching from memory, as before. The instructions use indirect and modified addressing for operand and branch addresses, a three-input adder being provided for the modification. General-purpose registers which are some way away but feed the adder are gated to it at the adder and a temporary register receives the adder output to feed one input of the adder direct if necessary without the transmission delays to and from the general-purpose registers. Whenever, during iteration of a loop wholly held within the buffers, a branch instruction is found, the second control register (holding the address of the instruction being decoded) is compared with the value it held at the branch instruction on the first iteration (saved in a register), equality causing the branch address (previously fed to a register from the adder output) to be gated into the second control register (to select the loop beginning for decoding), thus saving a machine cycle on each iteration of the loop. If any of the general-purpose registers used in generating the branch address alter their contents, the branch address used will be incorrect and a new branch address is generated.