Patent GB-894746-A (GB)
Title: Electronic switching unit for the construction of information storage devices, counters and the like
IPC: H03K23/00
Filed: 1958-11-11
Abstract: 894,746. Transistor pulse circuits. STANDARD TELEPHONES & CABLES Ltd. (Standard Elektrik A.G.) Nov. 11, 1958, No. 36150/58. Class 40(6). A switching unit for use for example, in an information storage device, counter, shiftregister or pulse distributer, comprises a capacitor connected in parallel to at least one non-linear switching element which is set via a control lead to a blocked or unblocked condition, the capacitor being connected in series with a load resistor to one or more input leads so as to pass pulses applied to the leads in dependence upon the state of charge of the capacitor. Fig. 2 shows a gating circuit comprising a capacitor C connected in parallel with a PNP junction transistor T so that C is discharged when transistor T conducts during the incidence of a negative control pulse USt applied to its base. When an input pulse Ue is applied via decoupling diode D after the incidence of a control pulse capacitor C is charged to generate an output pulse Ua at the load resistors R, R<SP>1</SP>, R". Thus the gate is conditioned by each control pulse USt to pass the next occurring input pulse Ue. Fig. 3 shows a ring counter comprising switching units E1, E2, E3 of the type described with reference to Fig. 2 and time delay units V1, V2, V3. If initially the capacitors in units E2, E3 are charged and that in unit El is discharged the first input pulse at terminal e causes the capacitor in units El to charge which delivers an output signal via delay element Vt to the control lead of units E2. The switching element in E2 is unblocked and the capacitor in E2 discharged so that upon the arrival of the next input pulse the capacitor in E2 recharges and that in E3 discharges, the process repeating itself so that the circuit functions as a scale of three counter. If in a multi-stage counter of similar type the capacitors are discharged in several switching units then the counter may function as a shift register the control lead of the first stage being connected with the lead in the conductor for information pulses and the busbar S with the lead-in conductor for transfer pulses. In a ring counter stage, Fig. 4, two staggered trains of input pulses are applied respectively to the odd and even numbered stages of the ring. Fig. 5 shows a distributer comprising ring connected switching stages El, E2..E12 having four inputs e1. .e4 and two lead-in conductors to each counting stage. Fig. 6 shows an AND gate in which transistors T1, T2 are normally blocked by bias voltages UV1, UV2. When negative control pulses are applied on both leads ST1, ST2 capacitor C is discharged and the next input pulse at e recharges the capacitor to produce an output pulse at a. The discharge of capacitor C when negative pulses are on both inputs ST1, ST2 may also be used to produce an output pulse. Fig. 7 shows an OR gate. When the capacitor C is charged an output pulse at a will only be produced if prior thereto, via one or the other or both control leads T1, ST2, at least one of the transistors T1, T2 has been unblocked to discharge the capacitor. Fig. 8 shows an OR gate in which normally capacitor C is discharged, an output at a in dependence upon an input at e will be produced only when capacitor C is charged which occurs only when pulses are present on one or both of the control leads ST1, ST2. Fig. 9 shows an AND gate in which transistor T2 acts as decoupling, only during the coincidence of input pulses on control leads ST1, ST2 will an output pulse from input e be produced at output a. The output may be coupled back to the input via a time delay element so that the arrangement having indicated the coincidence will automatically be ready to operate again.