Patent GB-1002782-A (GB)
Title: Signal level control circuit arrangements
Inventor: BALDWIN JOHN LEWIS EDWIN
IPC: H04N5/18
Filed: 1963-02-12
Abstract: 1,002,782. Television; transistor pulse circuits. RANK-BUSH MURPHY Ltd. Feb. 12, 1964 [Feb. 12, 1963], No. 5664/63. Headings H3T and H4F. [Also in Division G3] The invention relates to signal level contro arrangements which maintain the periodically recurrent reference level e.g. black level in a television video signal at a predetermined potential. The video signal is received at input terminal 1, Fig. 1, and passes to output terminal 4 by way of a coupling circuit 2 and a directcoupled amplifier 3, the output signals from amplifier 3 being also applied to a circuit arrangement 5 controlled by pulses from terminal 6 which occur during times when the output signal has the periodic reference value. Circuit 5 develops two simultaneous output pulses of like polarity, their amplitudes varying oppositely as the reference level rises above or falls below the desired value, and these pulses are applied to the two inputs of a difference amplifier 7 which develops on a storage capacitor 8 a potential proportional to the error in the reference level, and this potential is supplied by way of resistance 9 to the input electrode of amplifier 3. An embodiment of the invention is shown in Fig. 2 in which terminal 21 is the input terminal and terminal 34 is the output terminal. The input television video signal is fed via resistor 22 and capacitor 23 to the base of emitter-follower transistor 24 and the signal appearing at the emitter of transistor 24 is applied to the base of transistor 26 of emittercoupled pair 26, 27. The signal occurring at the collector of transistor 27 is applied to the base of emitter follower transistor 31, a fraction of the output of which, determined by resistors 32 and 33, is returned to the base of transistor 27, thus providing gain stabilization by negative feedback. The signal appearing at output terminal 34 is applied to the base of NPN transistor 35 which together with a similar transistor 36 forms an emitter-coupled pair. The base of transistor 36 is held at a constant potential equal to the desired potential of the reference level in the output signal at terminal 34 by a voltage divider 40, 41 between the negative and positive supply lines. The emitters of transistors 35, 36 are connected to the positive supply line by way of PNP transistor 42, the base of which is connected to a terminal 43 at which is received a bias, such that transistor 42 is normally bottomed thus rendering transistors 35 and 36 inoperative, together with positive-going pulses which cut off transistor 42 and thus makes transistors 35, 36 operative, these pulses occurring during times when the output signal has the periodic reference value. At the collectors of transistors 35, 36 there thus arises negative-going pulses of which the amplitudes vary complementarily in proportion to any variation of the reference level in the output signal. When an error is present, the potential across capacitor 52 changes such that it modifies the signal appearing at the base of transistor 24 so as to rebalance the currents taken by transistors 35, 36. If the time-constant of resistor 54 and capacitor 23 is (a) very large compared with the interval between impulses, then at each such impulse complete correction occurs; (b) equal to the interval between impulses, then not only is the error corrected during each impulse but also correction is made for an error increasing uniformly with time even between control impulses (anticipatory control); and (c) less than half the interval between impulses, then the circuit becomes unstable. To cause the emitter-coupled pair of transistors 35, 36 to be self-balancing to sudden changes in the reference level the circuit shown in Fig. 2 is modified (Fig. 3, not shown).