Patent GB-1293548-A (GB)
Title: Look-ahead control for operation of program loops
Inventor: WATSON WILLIAM JOSEPH
IPC: G06F9/38
Filed: 1969-10-20
Abstract: 1293548 Data processing; instruction look ahead TEXAS INSTRUMENTS Inc 20 Oct 1969 [4 Dec 1968] 51376/69 Heading G4A In a digital computer, e.g. as described in Specification 1,278,101, the speed of the memory is matched to the speed of the arithmetic unit by means of a " look ahead " operation. General.-In an embodiment instruction words are retrieved from the memory 18 in parallel in blocks of 8 by means of register 276 which increased in steps of 8 and stored in the register banks 129, 130 to provide a " pipeline " of instructions so that the arithmetic unit does not have to wait for memory access. The instructions are successively gated to the register 221 in response to the contents of register 244 which is normally successively incremented by one. The instructions are passed through registers 221, 224 and 229 which provide a secondary " pipeline " in order further to isolate the arithmetic unit from the restrictions of memory access time. Look ahead operation.-Each conditional branch instruction, i.e. an instruction specifying, in this particular case, that under certain conditions a given sequence of instructions is to be repeated, is preceded by a " look ahead " instruction located immediately before the first instruction of the sequence to be repeated. The presence of a "look ahead" instruction in register 221 is detected by the decoder 226 which sets the counter 258 to a number equal to the number of instructions between the look ahead and conditional branch instructions. The count is then decremented by 1 for each instruction passed to the arithmetic unit 101. When the count drops below 11 the address of the top instruction of the block in which the look ahead instruction lies is loaded in register 276, and the corresponding block is accessed from memory 18 and loaded in one of the stacks 129, 130. Meanwhile processing of instructions continues until the conditional branch instruction arrives in register 224 whereupon it is detected by decoder 234. The decoder, when enabled by a signal from the arithmetic unit when the latter has tested the branch instruction and found it not to be satisfied, passes a signal on line 234a which prevents the contents of register 244 being incremented, transfers the contents of register 232, i.e. the address of the look ahead instruction, to register 244, and resets counter 258 to zero. Any instructions beyond the branch in the main stream which have already been loaded into pipeline 221, 224, 229 are not transferred through the pipeline and are overwritten by the loop instructions, starting with the look ahead instruction, which are gated into the pipeline by the action of decoder 218 acting on the modified contents of register 244. The system then repeats the loop and the sequence continues as above. Should the conditional branch instruction be satisfied after any iteration a signal is generated on line 234e which inhibits the decoder 234 and register 244 is incremented in the normal manner; the operation proceeding downstream of the branch instruction. The Specification describes the sequence of operations in some detail, giving the responses of various gates, counters, registers &c. to each instruction. Multiprogramme memory protection is mentioned.