Patent GB-913461-A (GB)
Title: Logical element
IPC: G11C19/04
Filed: 1958-12-19
Abstract: 913,461. Circuits employing bi-stable magnetic elements. KOKUSAI DENSHIN DENWA KABUSHIKI KAISHA. Dec. 19, 1958 [Dec. 23, 1957 ; June 25, 1958], No. 41098/58. Class 40 (9). [Also in Group XIX] A logical element or stage in a shifting register comprises a group of four storage cores to which a binary signal pulse, the value of which is denoted by one polarity or the other is applied simultaneously with a writing pulse, the input and writing windings being so wound relative to each other that all the cores are brought from alternate respective magnetic states to the same one state by a binary signal of one polarity, and are brought to the same opposite state by a binary signal of the other value. In one arrangement, Fig. 3A, four cores Ma-Md with rectangular hysteresis characteristics have signal input windings IN, a winding WS to which writing and resetting pulses are applied at appropriate times, an erase winding E and an output winding O, the output circuit including a centre-tapped output transformer T and a source of read pulse current R. Initially the cores are brought to alternate states by a resetting pulse s in winding WS. A signal pulse Si and a writing pulse w are then applied simultaneously to windings IN and WS, respectively, and set all the cores to the same magnetic state in accordance with the signal pulse polarity. An erase pulse e is subsequently applied to winding E and changes either core Ma or core Md to the other magnetic state, depending on whether the signal registered was positive or negative. The reading pulse R is next effective in the output circuit, and reverses the state of core Mc if Ma was previously reversed, or reverses core Mb if Md was the core previously acted upon. The change of state of either core Mb, Mc presents a high impedance to reading current in the associated branch of the centre-tapped output circuit, and an output current pulse is applied to one half or the other of the transformer winding with a direction characteristic of the binary value stored. It is stated that the arrangement avoids the use of rectifiers between stages to control the direction of signal propagation since changeover of the core states in pairs induces opposing output signals. In a modification, Fig. 3B (not shown), a diode is included in each branch of the output circuit to eliminate spurious outputs at the erasing stage of operation. A modified arrangement of winding WS is shown in Fig. 8, in which embodiment the use of a transformer in the output circuit is avoided by providing a separate reading winding RS. It is stated that the resetting pulse s and the reading pulse r may be applied in coincidence, or the reading pulse may be of such increased amplitude as to make the resetting pulse unnecessary. It is stated that any of the circuits described may function as a NOT logical circuit by reversing the polarity of the output terminals, Fig. 12 (not shown). A majority circuit is also described, Fig. 13, in which three separate input signals are applied to primary windings Ti 1 , Ti 2 , Ti 3  of an input transformer T3. The circuit shown in Fig. 3A may be applied to a shifting register, Fig. 9, in which successive stages are controlled by pulses on leads I, II and III which are mutually displaced by 120 degrees of cyclic operating time. An embodiment is also described, Fig. 14, in which the erasing winding E is also used as a reading winding for the reading pulses r; this arrangement is used in the shifting register shown in Fig. 15 in which the controlling pulses on leads I-IV are displaced by 90 degrees of cyclic operating time.