Patent GB-1251852-A (GB)
IPC: H04Q3/00
Filed: 1969-01-17
Abstract: 1,251,852. Automatic exchange systems. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 17 Jan., 1969 [19 Jan., 1968], No. 2871/69. Heading H4K. In a multi-stage switching network, each stage comprises a plurality of relay switching matrices and each other than the first is coupled by associated intermediate lines to switches of the preceding stage, intermediate lines between each stage being marked with a first low current signal for marking each stage of a route through the network, for testing it for idle condition or for selecting a free route through the network, and with a second potential to establish a communication path through the network. Two embodiments are described; In both embodiments each intermediate path comprises the "a", "b" and "c" wires of a speech path, the "c" wire being used in succession for marking or selecting a route and for establishing and holding a connection over that route. In one embodiment (not shown) there are three switching stages and only one possible route through the switching network between a specified inlet and a specified outlet exists. The "c" wires of the outlets of the switches to be used are marked from high resistance positive voltage divider sources. If the two relevant intermediate lines between the stages are both free two positive potentials are applied simultaneously to an AND gate which responds indicating that the wanted route is free and low resistance positive voltage dividers are connected in parallel with the high resistance dividers increasing the current in the "c" wires of these intermediate lines until crosspoint relays (the windings of which are in those wires) respond completing the connection and providing a holding path over the "c" wire supplied at this time by a negative potential at the inlet end. If either of the intermediate line links is busy a negative potential is already present on that portion of the "c" wire and the corresponding high resistance marking is masked so that the AND gate does not respond. The Figure relates to a four stage switching network with alternative paths through the network. Only the path to be selected over intermediate lines AB11, BCr1 and CD2r together with the four crosspoint relays KA111, KB11r, KCr12 and KD2rn (one to each stage) and their contacts 1 Ka 111-3 Ka 111 &c. are shown. Route selection.-To select a free route the "c" wire of the wanted outlet of the last stage is marked by a selector WF from a high resistance (low current) voltage divider 104, the marking propagated back through the network stage by stage with regeneration at each stage over every free path and a unique selection is effected stage by stage from the free paths starting at the inlet end of the network. Each relay switching matrix has an OR gate such as PICr (associated with the third stage to which many subsequent reference characters refer), which OR gate detects the presence of marking signals propagated from the previous stage (provided those signals are not marked by a busy negative signal on the "c" wire) and applies a gating signal to a set of associated AND gates P2BCr1 to P2BCrq simultaneously enabled at this time by a selector WB. The AND gates open simultaneously switching corresponding transistor TBCr1 to TBCq to conduction connecting a high resistance voltage divider 10c to the "c" wires of that matrix propagating the marking signal over free paths to the preceding stage. The signal is propagated in this manner over all free links to the first switching stage. Assuming that a marking arrives as the outlet of at least one switching matrix of the stage A, a call can be established and OR gates P3A1 to P3AP individually associated with these matrices are each enabled if one or more outlets of the corresponding matrix is marked. The enabled gates mark corresponding inputs of the selector WA which removes all its output markings but one leaving only one of the AND gates P2AB11 to P2AB1P enabled, thus of the free links between the first (A) and second (B) stages only those leading to the selected A stage matrix are marked. The selector WA signals to a selector WB which receives indications of which AB links are still marked from OR gates P3B1 to P3Bq and selects a B matrix in similar manner. When a unique free path has been selected the marker M enables lines 112 switching transistors TABOO, TBCOO, TCDOO and TFOO to conduction connecting low resistance potential dividers 113 to 116 in parallel with the high resistance potential dividers 104 to 107 increasing the current in the "c" wires of the selected link causing the selected relays KA111 to KD2rn to operate, the path being held by negative potential applied to the inlet end of the "c" wire and earth applied to the outlet end.