Patent DE-3464421-D1 (DE)
Title: Hybrid-associative memory comprising a non associative base memory and an associative surface
Inventor: WOLF GERHARD DIPL ING
IPC: G06F12/02
Filed: 1984-03-29
Granted: 1987-07-30
Abstract: 1. A hybrid associative store, comprising a non-associative base store (B-SP) with write- and read devices for the selected input and output of data units via an input/output transmission system (DEG/D-AG) which corresponds to the length of the data units and comprising an associative area (ASS-FL) for testing the data units supplied from the base store (B-SP), characterised in that - each data unit (e.g. A0) is sub-divided into a given number (e.g. 4) of sub-units (e.g. bytes A00 to A03), each of which comprises a plurality of bits (e.g. 8 bits), - that the base store (B-SP) is sub-divided into arrays (e.g. F0 to Fn), each of which can be activated by an array address (e.g. F-AD0) of an address control unit (AD-ST) and each of which is formed by a number of data unit store sections - corresponding to the number of sub-units per data unit - in various data unit levels, where a row address (Z-AD), which supplements the respective array address (F-AD) to form a standard access address (AD), specifies the respective data unit store section within the respective array, - that in dependence upon an address reclassifier (AD-UM), which analyses the row address (Z-AD), in the address control unit (AD-ST), the sub-unit store sections within the array (F0), which correspond to the sub-units of the data units (e.g. A0, B0, C0 and D0) which each form an array (e.g. F0), are separated and can be activated, distributed in accordance with a given classification plan, in such manner that the mutually-corresponding sub-units (e.g. A00, B00, C00 and D00) of all the data units (A0 to D0) of the array (F0) can each be stored in different sub-unit store sections of the individual data unit levels and, in dependence upon the selected operating mode (MOD), either the purposive, simultaneous selection of the sub-units (e.g. A00, A01, A02 and A03) which form a data unit is possible in the case of normal store operation or the purposive, simultaneous selection of the mutually corresponding sub-units (e.g. A00, B00, C00 and D00) of all the data units of an array (F0) is possible in the case of associative store operation, - that in the address control unit (AD-ST), not only the access address (AD) but also the array address (F-AD), when the row address (ZAD) is constant, can be changed in stepped fashion so that consecutive data units (e.g. AO to An) which are directly linked on the basis of the selected classification plan can each be allocated to the data unit levels, specified by the constant row address (Z-AD), f consecutive arrays (F0 to Fn), - that in dependence upon reclassification devices (D-UM-EG, D-UM-AG) which likewise analyse the row address (Z-AD), the sub-units of the group of sub-units which is to be input or output, corresponding to a data unit, can be regrouped in accordance with the selected classification plan for the arrays (e.g. F0 to Fn) prior to input or prior to output in order to ensure the necessary storage sequence during input and in order to ensure the original sequence following output and - that in respect of each sub-unit, the associative area (ASS-FL) is assigned a universal logic-linking unit (e.g. ALV1 to ALV4) which carries out parallel processing of the bits of the supplied sub-unit and whose result outputs are coupled to the associated hit analysis control unit (T-AUSW.).