Patent GB-1423397-A (GB)
Title: Multi-dimensional access solid state memory
IPC: G06F12/02
Filed: 1973-04-04
Abstract: 1423397 Digital data stores GOODYEAR AEROSPACE CORP 4 April 1973 [15 May 1972] 16170/73 Heading G4C A solid state digital data matrix store is arranged to be accessed in any of three modes. In a first mode a word comprising a number of bits is accessed, in a second mode the sameordered bit from each word is accessed, and in a third mode sets of bits from some of the words are accessed. The store is formed of a number of modules each having a number of bit positions. The module, and the position within the module, of a particular bit of a word depends on the position of the bit within the word and on the ordinal number of the word. The store may form a square array of 2<SP>n</SP> modules, each of 2<SP>n</SP> bit positions. In Fig. 6, for example, n is 3. Data is stored such that bit B of word W is stored in bit position B of module M, where M is B#W where # signifies the modulo-2 sum. Thus in Fig. 6, bit 5 (101) of word 3 (011) appears in bit position 5 of module 6 (110). In Fig. 6 the numbers in the boxes represent the word number and the column order the bit order. From Fig. 6 it is seen that W = M#B. Each module has n  address lines. For a store as in Fig. 6 the addressing is as in Fig. 7 each module has n = 3 address lines selected from 2n = 6 selection lines X, Y. To operate in mode 1 (word access) the X lines are set equal to the word number W. For example, to access word 3 (011), X2 = 0 and X1 = X0 = 1. Also the Y lines are set to W, i.e. Y2 = 1 and Y1 = Y0 = 0. As a result each bit of the required word is accessed. However, the bits are not in the correct order (for word 3 the accessed order is 32107654). An ordering or permutation network ensures that the bits read in to or out of the store are arranged in the necessary order. The network is such that data associated with a particular bit position of a module is always placed at a corresponding data interface position P = B. Thus the bits of a word will appear in the interface in the correct order. In mode 2 (bit access), to access bit B of each word the X and Y lines are set to B. Since the words are not in the correct order (for bit 5 the accessed order is 54761032) the permutation network is again used. It ensures that the bit associated with a particular word is always placed at a corresponding data interface position P = W. In mode 3 (mixed access), if some of the X lines are set to the same state as the corresponding Y-lines and some set to the inverse state of the corresponding Y-lines some of the bits of some of the words will be accessed. The mode of operation may be controlled by an n-bit mode signal S which, for selected address lines X, causes the relevant selection of Y-lines such that Y = X # S (e.g., Fig. 8, not shown). For example, 2<SP>j</SP> contiguous bits of 2<SP>n-j</SP> words are accessed, the words being each 2<SP>j</SP>th word. Other combinations of words and bits of words are possible. The mode signal S also controls the permutation network. The arrangement of the store may differ from that described above. For example the word number W bits may be reversed. In mode 2 (bit access) the bits on the interface are then in reverse order of the words. In mode 3 (mixed access) contiguous sets of contiguous words are obtainable. A generalized form of the store (N bit x N bit) is described. In this, there are sets of address lines each associated with one component of an address vector having radices additional to the radix 2, and the data bits are ordered such that bit B of word W is stored in bit position B of module M such that M = B # W where # means subtraction modulo-Z k  (Z k  # 2). The store need not be square, but is then subdivided to form a number of square arrays.