Patent GB-970552-A (GB)
Title: Digital data processor visual display
IPC: G06F11/07
Filed: 1962-02-23
Abstract: 970, 552. Indicating arrangement for computers. SPERRY RAND CORPORATION. Feb. 23, 1962 [March 24,1961], No. 7077/62. Heading G4A.  In a digital data processing system manually operated switches are effective to connect "and" gating means in the input to a static display register to any one of a plurality of points in the circuitry of system, whereby the state of the circuitry at a selected point is displayed. The arrangement may be employed, for instance, to indicate errors which have been detected in the processing system and is described in relation to a parallel processing system having a display register 10 with n stages where n is the number of bits in a computer word. The register 10 is connected to a binary neon bulb indicator 16 and, for binary coded decimal data, via translators 18 to a decimal display 20. Manual mutually exclusively operable switches 22 are provided for selecting the register or points in the system of which-Indication is required. An output from an "and" gate 26 is effective to enable the particular one of gates 24 which is alerted by the closed switch. 22 thereby producing an output to effect the transfer of the selected data to the register 10. The "and" gate 26 has permissive inputs 30, 32, 34 and inhibitive inputs 36, 38. Display mode selection. There are three possible display modes: (1) manual, (2) programme, (3) error; and corresponding switches 56, 58, 60. (1) Closure of switch 56 provides a permissive signal to "and" gate 26 via an "or" circuit 62 (2) Closure of switch 58 provides an alerting signal to an "and" gate 64, the other input is a "tracing digit" from control circuits (not shown) in which a sensing circuit examines a particular digit position in all instructions. The output of the gate 64 is applied to the "or" gate 62. (3) Closure of switch 60 alerts an "and" gate 66 whose other input is derived from the set output of a flip-flop 70 which is set when an error is detected in the system. The output of the gate 66 is applied to the "or" gate 62. Further inputs 32, 34 to the "and" gate 26 are, if the manual or programme display modes are selected, controlled by the step in the operation cycle and time interval selection respectively. In the error display mode, the inputs 32, 34 are enabled by the closure of the switch 60. In the error mode the display is preserved by an input to an "or" gate 46,this gate being also actuated by closure of a switch 44 in other modes in which it is required to retain the display. A further switch 76 when closed together with the manual or programme display switch 56 or 58 causes the existing display to be retained when an error is detected. A timing pulse selector 80 permits the selection of the particular clock time within a selected step of an operation cycle at which display is effected. Selection of step in operation cycle. This is effected by operation of one of a set of mutually exclusive switches 86, 88, 90, 92, 94, Fig. 1. Operation of switch 94 causes a new display on each step of the operation cycle. Operation of switch 90 causes display in a selected execution step of an instruction cycle, the particular step being selected by a selector 98. The permissive signal for gate 26 on input 32 for the other selection is obtained from a flip-flop 106 which has as inputs the outputs of "and" gates 110,112,114 which are alerted respectively by the operation of switch 86, which selects a "call for an instruction word from memory" step; switch 88, which selects an "instruction word into control section and set-up of control signals" step; and switch 92, which selects a "transfer result to designated location" step. In order to prevent a new display during either the "call" or "execute" steps, if access to the memory is prevented because it is in use, there is provided a further switch 144. When the switch 144 is operated and subsequently the memory is busy, a gate 146 is opened at a suitable time to set a "memory busy" flip-flop 148 to inhibit gates 110, 138 in the "call" and "execute" selection circuitry.