Patent GB-748267-A (GB)
Title: Digital differential analyzer
IPC: G06F7/66
Filed: 1952-03-13
Abstract: 748,267. Digital electric calculating-apparatus; electric digital-data-storage apparatus. BENDIX AVIATION CORPORATION. March 13, 1952 [March 26, 1951], No. 6580/52. Class 106 (1). A digital calculator for performing integration and differential analysis comprises a set of storages sections, a common computer means associated with all the storage sections and so arranged as to coact with each section to perform a fixed sequence of operations whereby in response to first and second input trains of pulses representing increments of an integrand variable '(y) and a variable of integration (x) respectively, an output train (z) of similar pulses is produced such that its effective rate (z) at any time corresponds to the product of a number (y) cumulated from the pulses in the first train with the effective rate (x) of the pulses in the second train, and means whereby the output train can be introduced as the first or second input train for any storage section. In the apparatus described, numbers are represented by series-mode pulse trains which are recorded, together with code pulses, on a magnetic drum or " wheel " 116, Fig. 4, which is connected to a single electronic computing (integrating) circuit, Fig. 16. An entry and control keyboard is provided including " 0 " and " 1 " binary digit keys 349, 350, Fig. 57, and the results may be indicated on a counter or, as shown, on a cathode-ray tube 463. The computing circuit consists primarily of bistable trigger circuits (called " flip-flops ") connected by crystal diode gating networks corresponding to given logical algebra equations. The principle of obtaining J ydx is illustrated in Fig. 2. The binary-digital number corresponding to the dependent variable y is stored in counter 108, to which pulses each corresponding to a unit increment dy (positive or negative) are applied on line 109, and is added in an accumulator 110 whenever a unit pulse dx is applied to a transfer device 112. Whenever the capacity, say 2<SP>n</SP>, of accumulator 110 is exceeded, an output pulse dz is sent over line 111. Thus f dz = 1/2<SP>n</SP> #ydx-r/2<SP>n</SP> where r is the remainder in the accumulator, and # is interpreted as the corresponding summation of values occurring in digital steps determined by increments dx, dy. Magnetic memory.-The magnetic wheel 116, Fig. 4, continuously rotated by a motor 115, has four parallel channels 132-135, from which recorded information is continually picked up by heads 128-131 and sent to the computing circuit 136. The information on channels 132- 134 is subsequently erased by heads 150 and replaced by the output of circuit 136 supplied to heads 141, 142 and 147. The channel 135 has a sine wave recorded thereon to define synchronizing or clock pulses. The channels 132 and 133 (Y and R) are each divided into 22 successive integrator memory sections I 1 -I 22  each the length of 48 clock pulses. Each pulse position corresponds to a binary digit, the digits being recorded by the non-retum-to-zero method, i.e. the magnetic pattern M, Fig. 6, changes only for a change in the values of successive digits. Each Y-section contains dy code pulses in up to 7 of the pulse positions P 1 -P 22 , and a number y with its sign in some or all of positions P 25 -P 47 , the first digit being indicated by a recorded start pulse shown in position P 24 . Each R-section similarly contains not more than one dx code pulse, and a remainder number r, and also a dz sign pulse in position P48. The Z channel 134 comprises a single temporary memory (" dz precession line ") for the dz output pulses produced at times P 48  as the result of the information on the memory sections I 1 -I 22  passing through the computing circuit 136. Each pulse position represents a dz value, positive for a pulse and negative for no pulse. Fig. 34 shows how the outputs corresponding to the sections I 1 -I 22  (represented by corresponding numbers 1-22) travel along the " precession line ". At time P 48  I 1 , output 1 is recorded, and since, during computing operations, the line is 49 pulses in length, at time P 48  I 2 . output 1 is one step behind so that output 2 can be recorded in front of it, and so on for the other outputs. The dz pulses coact with the dx and dy code pulses, Fig. 6, as described below. Pick-up circuits for memory channels.-The sine wave on clock channel 135, Fig. 4, picked up by head 131, is impressed on the grid of an amplifying triode 156, Fig. 8, the anode output of which is applied to a Schmidt trigger circuit 157, 159. The resultant square wave is sent through cathode follower 161 to parallel-connected triodes 162, so that the required clock pulses C appear on output line 163 the potential of which is maintained between 100 v. and 130 v. by diodes 164, 165. The square magnetic pattern M on channels 132-134, Fig. 4, is differentiated in the pick-up heads 128-130, and the resultant positive and negative pulses are impressed on the grid of an amplifying triode such as 169, Fig. 9, the anode output of which is applied through a cathode follower 171 to an inverting circuit 173 comprising two cathode-commoned triodes 174, 175 providing opposed outputs as shown. The positive pulses of these outputs cause conduction of triodes 181, 182, the resultant negative anode pulses being differentiated by circuits 190, 192 and applied to opposite sides of a flip-flop circuit Ym through diodes 193, 191. The circuit Ym is thus triggered by the negative portion of the differentiated pulses so that the output potentials on lines Ym, Y<SP>1</SP>m exactly correspond to the magnetic pattern M, the potentials being high when the pattern represents " 1 " and " 0 " respectively. These potential are applied together with clock pulses C to synchronizing gates 203, 204, Fig. 12, the outputs of which are applied, through input circuits similar to those for Ym, to a flip-flop Y 1  and a parallelconnected supplementary flip-flop YD, the flipflops being triggered by the trailing edges of the clock pulses. Similar flip-flop circuits Rm (not shown) and Zm, Fig. 14, for the R and Z channels, control synchronizing flip-flops R 1  and Z 1 . The outputs from Z 1  similarly control a further flip-flop Za (to provide a delay of one pulse period) which, in turn, controls Zb. The circuit 136 is normally supplied with the output of Zb to provide the precession line length of 49 pulses, but a line of 47 pulse lengths (for data entry) or 48 pulse lengths (during idling) may be obtained by using Z 1 , Za respectively (see Fig. 34). Trigger circuits.-The flip-flops or trigger circuits used in the computing circuit 136 are all similar to Ym, Fig. 9, described above, and are each regarded as representing a logical proposition. For example, flip-flop K 1  of a counter, Fig. 24 (further described below under " (iii) clock pulse counters "), registers a binary digit and the proposition is that the digit is " 1 ". If this is true output K 1  is at high potential, otherwise K1. The inputs for triggering the flip-flop to the " true " and " false " state are designated k 1 , ok 1  respectively, and are supplied from gates G which pass triggering clock pulses only when the appended logical algebra equations, in terms of the outputs of other flip-flops, are satisfied (i.e. give a resultant high potential). Gating networks.-These comprise two basic crystal diode circuits for performing logical addition (" or ") and multiplication (" and "). In the " or " circuit of Fig. 10, if either a or b (or both) are at high potential current will flow through resistance 196 thus producing a high potential on output line 199. In the "and" circuit of Fig. 11, output line 200 will be at a high potential only if c and d are at high potential to prevent current flowing through resistance 204. These circuits can operate on any number of inputs and can be combined into " tree " circuits. Computing circuit.-The circuit 136, illustrated diagrammatically in Fig. 16, comprises three distinct sections: (i) a loop for obtaining the y number from a section of the magnetic memory 116, adding dy pulses selected from the dz precession line by the dy code pulses, and recording the new y number thus obtained; (ii) a loop for performing the integration by adding the y number (or its complement) to the r number to obtain the new r number and the dz output pulse; and (iii) clock pulse counters 240, 241 for marking off pulse times P 1 -P 48  and intervals I 1 -I 22  respectively. (i) y-loop. Starting with pulse time P 1  for a given memory section, Fig. 6, the dy code pulses in positions P 1 -P 22  of the Y-channel are fed through gate 212 to a decoder 214 to which are fed simultaneously the dz pulses from the Z channel. According to whether a dy code pulse coincides with a positive or negative dz value (pulse or no pulse), a unit is added or subtracted in counter 215. The dy code pulses are also fed back onto the memory wheel via line 216. The start pulse is fed through gate 213 to trigger flip-flop 5 which then applies an operative potential to gates 217, 220. The number y is then passed through gate 217 to adder 219 where it is combined digit by digit with the number #dy stepped out of counter 215 by clock pulses sent through gate 220, carry being effected by a flip-flop D1. The adder output is fed back to the memory 116 on line 140. The counter 215 comprises flip-flops A1- A4, Fig. 29, the input equations being shown for positive and negative counting, stepping out and resetting. Numbers are represented according to the table of Fig. 30, A4 being used to represent the sign. During the stepping operation, Fig. 32, the number is shifted stepby-step to the left until the sign digit appears in flip-flop A1, and the output potential A1- controls the adder 219 as indicated by the table of Fig. 38. Thus the A4 sign digit is repeated in all positions up to P47 in the y + #dy addition, of which Fig. 37 sh