Patent GB-1000835-A (GB)
Title: A magnetic core memory system
IPC: G11C11/06
Filed: 1961-10-20
Abstract: 1,000,835. Magnetic core matrix stores. DI-AN CONTROLS Inc. Oct. 20, 1961 [Oct. 25, 1960], No. 37793/61. Heading G4C. [Also in Division H3] A memory system includes a frame 22 of bi-stable magnetic cores having first (X) and second (Y) series of selection lines, an inhibit line and a sense line, each line communicating magnetically with the cores, at least one first ring counter 52 having a first sequence of cores, and at least one second ring counter 60. having a second sequence of cores, there being means for applying sequences of pulses to the shift lines of the ring counters, means for applying a sequence of inhibit pulses to the inhibit line, and means communicating with the sense line to indicate a change in magnetic state of a core, the magnetic state of a core being altered only when coincident pulses are applied to the two selection lines communicating with it, in the absence of an inhibit pulse. A three-dimensional array 20 comprises a stack of frames 22 with corresponding selection lines in successive frames connected in series. Separate inhibit and sense lines are provided for each frame, and frame selection circuit 24 includes inhibit drive circuits (magnetic amplifiers) 42 and sense circuits (magnetic amplifiers) 44, the latter being connected to flip-flops 46 arranged to indicate the states of the sensed cores. Core selection read control circuit 26 includes X-axis network 48 and Y- axis network 50, and the write control circuit 28 includes corresponding networks 52, 54. Each network operates in a similar manner: selection line drivers 62 each comprise a bi-stable core 64 (Fig. 3), a load line 66 connected to the output of a preceding core, a shift line 68 to reset the core and an output line connected to transistor amplifier 72, arranged to be driven to saturation by a shift pulse. Driver Y1, initially set to " 1," is reset by a shift pulse from line 68, giving an output to a column selection line 73 of the store, and setting core Y2 to " 1." The ring counter is a three-phase arrangement, so that a set pulse never coincides with a shift pulse in any core. The shift lines are energized through power drivers 59 from an input ring counter 56 including three phase-drivers 58. The phasedrivers each include a core 70 (Fig. 4), load line 72 connected to the output from a previous phase driver, shift line 74, and an output line 76 connected to a transistor amplifier 78. The latter supplies an output directly through power drivers 59 to lines 68, and also supplies a delayed pulse through LC delay network 80 to the load line of the next phase driver 58. Shift pulses for phase drivers 58 are supplied from a master driver 88. The master control network 30 includes inhibit and sense enable circuits 82, 84, read and write master drivers 86, 88, and memory clear and address reset circuits 90, 92. A marker core 94, energized by coincident pulses from the last X and Y selection line drivers of a sequence, indicates the end of the sequence. Cross-inhibit lines 96, 98 may be provided so that one read driver can select a field normally under the control of another.