Patent GB-883890-A (GB)
Title: Improvements in magnetic core circuits
IPC: G11C19/04
Filed: 1958-06-16
Abstract: 883,890. Circuits employing bi-stable magnetic elements. GENERAL ELECTRIC CO. June 16, 1958 [June 17, 1957], No. 19164/58. Class 40 (9). [Also in Group XIX] In a shifting register or a logical gate utilizing magnetic cores with rectangular hysteresis characteristics, each with input windings 15, advance windings. 16 and output windings 17, Fig. 1, the advance and output windings on each core are connected by way of a rectifier 24, 27, 30 to an alternating power source 19, the rectifiers in successive stages being connected in opposite respects so that positive advance pulses from the power source are effective in alternate stages while the negative advance pulses act on the remaining stages. Each advance winding has a series resistor 21 and inductor 22 which stabilize current flow and prevent induced voltages from passing to the supply. The shifting register is shown in Fig. 1 in which cores 11, 12, 13 constitute successive stages the output windings 17 of which are coupled to the input windings 15 of subsequent stages by rectifiers 25, 28, bias voltages 32 being provided to suppress spurious signals. Cores 11 and 13 are controlled by positive advance pulses while core 12 responds to negative advance pulses. In operation, a positive or negative advance pulse, depending on the stage concerned, passes directly to the input winding 15 of the next stage over a rectifier 25 or 28 if the core acted on by the pulse is in the " one " magnetic state, since the output winding presents a high impedance. If, on the other hand, the core is in the " zero " state, the core flux is unchanged and the output winding 17 provides a short-circuit path for the advance pulse. Successive positive and negative pulses thus transfer binary information from core to core through the register. The same operating principle is used in an AND gate, Fig. 2, in which separate imputs are applied to cores 33, 35 and a positive advance pulse is applied to the input winding of a further core 34 by way of a rectifier 39 only when both cores 33, 35 are in the " one " state. If either core is in the " zero " state, then the respective output winding provides a shortcircuit path for an advance pulse. The switch 41 is normally closed, but if this switch is opened so that a rectifier 40 is connected in circuit, then an effective output from core 35 is unable to pass to core 34. This output may then be applied to other cores (not shown) over lead 42. A modified circuit is shown in Fig. 3 which performs the exclusive OR operation, the two output circuits of cores 43, 45 being connected in parallel to the input winding of core 44. Further rectifiers 50, 52 provide return current paths by way of the output windings so that if both cores are in state " one," both return paths are blocked. An inclusive OR circuit is also described, Fig. 4, in which an input pulse is applied to a core 56 if at least one of cores 55, 57 is in the " one " state. In a further embodiment, Fig. 5, a pulse passes to the input winding of core 66 only if core 65 is in the " one " state and cores 67, 69 are in the " zero " state, since the input winding of the former circuit completes its circuit by way of rectifiers 73, 74 and the output windings of cores 67, 69. In this arrangement a further connection is made to the output winding of core 66 from the power supply by way of a rectifier 79 to augment the output pulse to a further stage.