Patent GB-1453790-A (GB)
Title: Device for automatically searching for the frame synchronising words of a time division multiplex frame
IPC: H04J3/06
Filed: 1974-02-12
Abstract: 1453790 Identifying multiplex frames and synchronizing signals COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 12 Feb 1974 [12 Feb 1973] 6250/74 Heading H4M In an arrangement for automatically searching for the frame synchronizing words in the recieved bit stream of a time division multiplex communication signal having an unknown number N of bits per frame, the bits in the frame occurring as ones or zeros with substantially equal probability, the received bit stream S is applied to a variable delay 1 under the control of clock signals H. The received and delayed streams are compared, e.g. by exclusive OR gate 2. A detection circuit 3, 4 is arranged to detect when s successive coincidences between s successive bits of the received and delayed streams occur, s being a predetermined number greater than 2. A control system varies the delay until s successive coincidences are obtained, when there is a high probability that the number N of bits in the frame is equal to the number n of clock intervals by which the received stream is delayed in the delay circuit. The exclusive OR gate 2 provides a "1" output when both inputs are the same, zero otherwise, and the gate output is passed to a shift register 3 of length s controlled by the clock signal H. The register has s parallel outputs, one from each of its stages, and these are connected to an AND gate 4 having an output B which will thus be "1" if s consecutive bits in the delayed and undelayed signal S are the same. It is explained in the Specification that the probability of obtaining a one output at B is very low unless the delay n is the same as the length N of the mutliplex frame, in which circumstance, if the length of the sync word k is greater than s, at some stage during the frame a "1" output at B will be obtained. The remainder of the system shown in Fig. 4 is concerned with searching for the instants where B = 1 and eliminating error due to the possibility of obtaining a "1" at B when n#N. The system also indicates when the frame length and sync word have been found. Operations commence by setting an arbitrary (low) value of n in the main counter 23, which sets the reverse counters 11 and 18, and by resetting a bi-stable 20 (at T) to hold open an AND gate 22. During the first cycle of operation, the output "a" from zero state decoder 12 is zero, so that the output m of NAND gate 8 is "1", AND gate 10 is open and clock pulses to the reverse counter 11. When this counts down to zero, "a" becomes "1". The correlation output B, which will normally be 0, is passed via a slight delay 6 and inverter 7 to the other input of NAND gate 8, causing m to become "0", stopping the clock signals to reverse counter 11 and applying them to reverse counter 18. If no "1"s appear at B, showing that there is no correlation anywhere between bits n clock pulses apart and thus n #N, a pulse is obtained from the zero detector 19 and passed via the open AND gate 22 to advance the counter 23 to n + 1. The reverse counters are reset and the search continues. If however a "1" appears at B during this reverse count the output m from NAND gate 8 again becomes "1" (since "a" is still "1") the counter 11 is reset, "a" becomes "0" and the counter again counts down to zero as clock pulses h 1  are once more applied. If, immediately after, "a" rises to "1" again when this zero is reached, a further "1" appears at B, m will remain at "1" and it seems very likely that the frame has been found. The successive "a" pulses are fed to a counter 15, which is reset by the h 2  pulses. If three successive "a" pulses appear without resetting, a pulse b is delivered to reset the bi-stable 20 to zero and light a lamp 21, indicating that the frame has been found. However synchronism slightly off the sync word may have been obtained due to the difference between the sync word length and the length of the register 3. Therefore when six consecutive pulses have been obtained the counter delivers an output c to reset the bi-stable 26. This illuminates a lamp 27, showing that proper sync has been established and applies a "1" to permanently open an AND gate 10 so that the system continuously cycles on the n bit frame. The first "1" appearing at B may have been a random one, not indicating that the frame has been found. In this case, it is very unlikely that B will be "1" n clock cycles later and if it is not the output m from NAND gate 8 will fall to zero when a appears, the counter 15 will be reset and the reverse counter 18 will continue its count. The count in 18 will thus be picked up after any random "1" at B until zero is reached and the main counter 23 advanced. The procedure continues until the correct bit frame length appears in the counter 23. At each "a" pulse, a register 5 connected directly to the input S is read out into indicators 5b and when the system locates the frame, this will show as much of the sync word as the register holds. A simple manual arrangement for dropping individual clock pulses from the count to shift the word through the register so that it may all be observed is explained (Fig. 7, not shown). If the system loses phase such that B ceases to be "1" at the expected time for q frames, a shift register 24 delivers q "1" outputs to AND gate 25 whose output resets a bi-stable 26, unlocking the system and enabling it to hunt for sync again. The delay in unit 1 is coupled to the main counter 23 by logically switching in and out successive delay elements automatically in accordance with the count (Fig. 8, not shown).