baber/WOPTO huggingface dataset:
Patent JP-H032528-A (JP)
Title: Water level detector for water tank of cooling water supply device
Inventor: TOMIMATSU KAZUNARI
IPC: G05D9/00
Filed: 1989-01-12
Abstract: PURPOSE:To detect a water level without being affected by the wave motion of cooling water and to easily set the operation position of a float by providing a slit which travels vertically in a cylindrical wave preventive cover. CONSTITUTION:The wave preventive cover 8 is cylindrical and has its bottom surface open and fixed detachably having its upper end surface adhered to a fitting plate 3 to cover the float 5. A scale 82 indicates a position where the float 5 should operate is displayed along the slit 81 of the cover 8. The water level detecting device 2 is only sunk gradually in a container containing water to enable the operation of the slit 5 to easily be confirmed through the slit 81. Then the operation position is matched with the scale 82 to easily judge whether or not the setting of the operation position is correct. Further, when the cooling water supply device is in operation, wave motion generated by the cooling water is interrupted by the cover 8 because the slit 81 is fitted deviating from the entrance of the water tank, so that the float 5 will not fluctuate. The operating water level is therefore accurately detected and trans mitted to a switch, which never chatters.
Patent JP-H08191786-A (JP)
Title: Vacuum cleaner
Inventor: ODAWARA HIROSHI
IPC: A47L9/28
Filed: 1995-01-18
Abstract: PURPOSE: To simplify the assembling and disassembling by arranging a bypass valve and a power source switch on the upper part of an upper case, providing an operation confirming window for the bypass valve on an upper cover, and using the upper cover also as the push button of the power source switch. CONSTITUTION: This vacuum cleaner is formed of an upper case 610 covering the upper part of a lower case to form an electric blower chamber; a handle 614 rotatably supported on the upper part of the upper case 610; and an upper cover 617 having a bypass valve 615, a power source switch 616, and a switch spring 101 arranged thereon, and rotatably supported on the upper case 610. The upper cover 617 has a confirming window 621 for confirming the operating state of the bypass valve 615 and a switch control part 102. When the switch control part 102 is pushed, the upper cover 617 is rotated around a rotating shaft 103, and a push rib 201 presses down the power source switch 616 to perform ON/OFF operation.
Patent JP-H10271260-A (JP)
Title: Method and system for displaying user interface proper for multifunction machine
Inventor: DASH ROBERT J
IPC: G06F3/048
Filed: 1998-01-14
Abstract: PROBLEM TO BE SOLVED: To provide a method and device which detect and display the function picture of a proper user interface of a multifunction machine based on preparatory operation unrelated to user interfaces. SOLUTION: A control unit 30 changes display contents of a user interface 40 to a function picture corresponding to a copy function when detecting that a document is placed on a document handler 42, and the control unit 30 changes display contents of the user interface 40 to a function picture corresponding to a facsimile function when detecting that a telephone number is inputted through a handset 50 or a telephone key pad 36. The control unit 30 changes display contents of a user interface 40 to the function picture corresponding to the copy function when a platen cover sensor 34 detects that a platen cover is opened. The control unit 30 changes display contents of the user interface 40 to a function picture corresponding to a print function when detecting that a portable memory device is inserted to an input/output drive 46.
Patent JP-S59130478-A (JP)
Title: Manufacture of field effect transistor
Inventor: KOZUKA MICHI
IPC: H01L29/80
Filed: 1983-01-17
Abstract: PURPOSE:To obtain a field effect transistor whose controllability by a monitor element is excellent and which can be manufactured with a high yield by a method wherein apertures of masking materials are provided in one or both of the source electrode and the drain electrode of an MESFET100, and the source electrode is electrically connected to the drain electrode via an operating layer. CONSTITUTION:The N type GaAs operating layers 22 and 23 are formed on a semi-insulation GaAs substrate 21. Next, the entire surface is covered with a photoresist film 28, and the apertures 29-32 are provided in at least one of the source electrode 24 and the drain electrode 25 of the MESFET100, e.g. a part of both the electrodes, the part for placing a gate electrode, electrodes 26, 27 of the monitor element 200, and a part of the GaAs held between these electrodes 26 and 27. Then, using the mixed solution of H2O2, H3PO4, and H2O, the GaAs is etched, thus providing recesses 33 and 34, and the current-voltage characteristic between the electrodes 26 and 27 is measured by pulling up the mixed solution some times. When the current-voltage characteristic reaches a desired value by repeating this work, the etching is stopped. The gate electrode is formed by successively vacuum-depositing e.g. Ti, Pt, and Au as the gate metal, and then the bonding pad of each electrode is formed.
Patent JP-H04240429-A (JP)
Title: Vacuum cleaner
Inventor: SENDA NORIAKI
IPC: G08B5/36
Filed: 1991-01-22
Abstract: PURPOSE:To display various indications on a display and easily confirm the input condition of a motor-driven fan with a plurality of control conditions. CONSTITUTION:This electric vacuum cleaner is provided with detectors 34, 35 transmitting the output in accordance with an air-path condition or a cleaning floor condition and a plurality of indicators 42 showing the control condition of the motor-driven fan 12. The controller 30 selects one of condition controllers 38 from respective condition controllers 38 by a control selection means 39 to variably regulate the input of the motor-driven fan 12, when the preset judgement interval has elapsed within the memorized preset range in the memory 37 in accordance with the output of the detectors 34, 35. In the indicating means 41, a plurality of indicators 42 are actuated to indicate in a plurality of indication patterns in accordance with respective condition controllers 38 selected by the control selection means 39. And hence, the actuation condition of the motor-driven fan can be easily confirmed. And even if various input controls of the motor-driven fan are given, there is no necessity to increase indication parts.
Patent JP-H03209642-A (JP)
Title: Optical information medium, its production and its cassette case
Inventor: NAGASHIMA MICHIYOSHI
IPC: G11B7/1365
Filed: 1990-01-11
Abstract: PURPOSE:To independently read out the information faces of respective layers and to improve recording density by constituting two or more layered information faces so that the reflection factors of respective information faces are successively reduced in the direction of the laser incident side. CONSTITUTION:The information face 2 is formed on one side of a transparent substance layer 1 consisting of glass or resin and a translucent thin film 3 is formed on the face 2 so that a part of an incident laser is reflected. A transparent substance layer 4 is formed on the film 3 and an information face 5 is formed on one face of the layer 4. Then a reflection film 6 consisting of aluminium or the like and capable of almost reflecting laser beams is formed on the face 5. When a laser beam 7 is made incident so as to be converged upon the face 5 in the constitution, an information signal on the face 5 can be reproduced and the laser beam reflected on the face 2 does not exert influence upon the reproduced signal on the face 5 because a beam diameter on the face 2 is large. When the laser beam 7 is made incident so as to be converged upon the face 2, information on the face 2 can be reproduced and the reflected light from the face 5 exerts no influence. Consequently, the information faces of respective layers are independently read out and the recording density is improved.
Patent JP-S52121712-A (JP)
Title: Elevating of transient stablity of synchroneous machine
Inventor: ISONO AKIRA
IPC: H02P9/10
Filed: 1977-01-24
Abstract: PURPOSE: To elevate stability on transient time to make do with small variation of of phase angle increasing inner induced electric voltage of generator in order to hold field voltage to the peak voltage by short time after eliminating trouble also in case of out breaking troubles on electric power system. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-S5597799-A (JP)
Title: Electro-mechanical transducer
Inventor: SOUBE YOSHIYUKI
IPC: H04R17/00
Filed: 1979-01-20
Abstract: PURPOSE:To lower the minimum resonance frequency to make the frequency characteristic flatter by connecting partially a vibrating material and a diaphragm through an elastic material and by forming a gap between them. CONSTITUTION:Piezoelectric ceramic 1 consisting of barium titanate, etc., converts an electric signal to a mechanical displacement, and electrodes 6 and 7 are formed on both faces of it. The upper electrode 7 is connected to metallic plate 2 through silver paste layer 9 and adhesive layer 10, and further, metallic plate 2 is connected partially to a diaphragm through ring rubber material 11. Diaphragm 3 consists of a flexible material except metal and is constituted into, for example, an asymmetrical square except a round form symmetrical for center point 12. By constituting diaphragm 3 into a form asymmetrical for center point 12 in this manner, generation of standing waves in diaphragm 3 can be prevented to obtain a flat frequency characteristic as the whole.
Patent JP-S58170396-A (JP)
Inventor: MISHIERU JIYANDOROORU
IPC: H02P27/02
Filed: 1983-01-19
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S62165327-A (JP)
Title: Manufacture of semiconductor device
Inventor: KITAOKA NOBUYASU
IPC: H01L21/28
Filed: 1986-01-17
Abstract: PURPOSE:To enable the heat treatment to be performed without fail while preventing the members to be heat treated from being oxidized by a method wherein, after inserting the members to be heat treated into a furnace core tube of an electric furnace, and opening of the furnace core tube is covered to heat treat the members as they are. CONSTITUTION:Semiconductor wafers 5 containing high melting point metallic silicide as members to be heat treated are loaded upon a boat loader 4 to be inserted into a furnace core tube 1 from the other end opening using a pull out bar 6. The semiconductor wafers 5 are once held at the part near the opening at low temperature immediately covering the opening with a cover 7 at this temperature to prevent air from running into the furnace core tube 1. On the other hand, inert gas or nitrogen gas is led in the furnace core tube 1 from a gas leading-in port 2 and after filling the furnace core tube 1 with said gas to purge the oxygen in the furnace core tube 1, the semiconductor wafers 5 are shifted to the central part of furnace core tube 1 at high temperature to be heat treated as specified. At this time, hydrogen is added to the led in gas so that any residual oxygen in the furnace core tube 1 may be reacted to hydrogen to be extinguished never oxidizing the semiconductor wafers 5.
Patent JP-S61165675-A (JP)
Title: System for automatically measuring logical wave from
Inventor: SOENO SHIGERU
IPC: G01R31/28
Filed: 1985-01-17
Abstract: PURPOSE:To further promote automation, by performing the comparison of a number of succeeding sampling state values prescribed corresponding to an irregularity tolerant value by a tolerant value comparing means and detecting non-coincidence exceeding the tolerant value by the tolerant value comparing means. CONSTITUTION:The memory data of an auxiliary memory circuit 3 and a main memory circuit 4 are compared by a comparing circuit 5 and, when the compared result became inferior, the memory address thereof is outputted to an address adder circuit 6. A tolerant value comparing circuit 7 receives the data of addresses concerned from the auxiliary memory circuit 3 and the main memory circuit 4 to compare the same. When the compared result is inferior, the tolerant value comparing circuit 7 sends a signal having to again add 1 to the address adder circuit 6 and compares the next address logical values obtained from both memory circuits. When the compared result is out of a tolerant value range, an inferiority signal is outputted to a character display 8. By this method, the automatic judgment of a logical state value is enabled by the sequence operation of the address adder circuit 6 and the tolerant value comparing circuit 7 and automation can be further promoted.
Patent JP-H03211661-A (JP)
Title: Sentence read-aloud device
Inventor: NEMOTO JIRO
IPC: G06F17/21
Filed: 1990-01-17
Abstract: PURPOSE:To reduce the burden of a user by automatically setting a read speed in accordance with the quantity of morae which a read speed information setting part analyzes in a document analysis part. CONSTITUTION:The document analysis part 2 refers to a dictionary held in a dictionary holding part 3 while it analyzes the document held in a document holding part 1 and calculates the quantity of the unit (mora) of a pronunciation included in the document in the middle of a processing. The read speed informa tion setting part 7 refers to time information held in a time information holding part 5 and a sentence analysis result held in a sentence analysis result holding part 4 while it obtains the speed for reading the sentence. A sentence read part 8 reads the sentence based on read speed information held in a read speed information holding part 6. Thus, the read speed is automatically set in such a way the sentence is read in time which the user desires, and the sentence is read in desired time.
Patent JP-H11204574-A (JP)
Title: Apparatus and method for bonding
Inventor: MUSHA HITOSHI
IPC: H01L21/60
Filed: 1998-01-16
Abstract: PROBLEM TO BE SOLVED: To provide a bonding apparatus which suppresses dust mixing and can efficiently mount electronic components and optical glasses on the front and back surfaces of a board, such as tape carrier package(TCP). SOLUTION: A loader unit 20 for feeding a TCP board, UV-curing type adhesive coating unit 30 for coating a UV-curing type adhesive on the TCP board, glass mounting unit 50 for bonding optical glasses at specified positions on the back surface of the TCP board coated with the UV-curing type adhesive, a UV light irradiating unit 60 for irradiating UV light through the optical glass on the TCP board, a CP coating unit 70 for coating ACP on electrodes CO of the TCP board, a chip mounting unit 80 for mounting electronic components on the TCP board, an unloader unit 90 for unloading the TCP board, which mounts the optical glasses and electronic components and the feeder unit 30 for feeding the TCP board between the units are provided.
Patent JP-S61178895-A (JP)
Inventor: DENDA MAMORU
IPC: B67D7/16
Filed: 1985-01-16
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S60151897-A (JP)
Title: Semiconductor memory device
Inventor: YUASA HIROKAZU
IPC: G11C11/412
Filed: 1984-01-18
Abstract: PURPOSE:To obtain a semiconductor memory device which is hard to cause malfunction and characteristic deterioration due to absorption of ionizing radiation by utilizing a P-channel enhancement-type MOS transistor for a transfer gate. CONSTITUTION:This device is constituted of a memory cell and a transfer gate; the former is constituted in such a way that a P-channel MOS transistor is connected to an N-channel MOS transistor in serial, a serial connecting point 1 of one set of transistors MOS1 and MOS3 is connected to a common connecting point of the other set of transistors MOS2 and MOS4 and in these two sets their gates are connected in common. The latter consists of two P-channel enhancement MOS transistors MOS7 and MOS8 in which a source is connected to a drain between serial connecting points 1 and 2 of a CMOS transistor and data lines DATA and -DATA and a gate is connected to a word line Word (A/i).
Patent JP-S60150357-A (JP)
Title: Pseudo transmission line
Inventor: JINBO TOORU
IPC: H04L69/40
Filed: 1984-01-18
Abstract: PURPOSE:To execute efficiently the test up to the limit of data transmission/reception without requiring aid of opposite station by providing a delay time variable set circuit and a frequency variable set circuit to decrease the test time of a data communication system. CONSTITUTION:A data inputted in synchronizing with a clock is stored once in an input buffer (INB) 1 comprising 1 bit or two and inputted again in a first in first out (FIFOM) memory 2 in synchronizing with the clock. The number of bits is decided by the test range of the data speed, delay set time and clock set time. The data inputted to the memory 2 is read in the order of input by a request of an output buffer (OUTB) 2 and transmitted from an output buffer 3. The output buffer 3 reads and transmits data by the control of a delay time set circuit (DLC) 4 and a clock set circuit (FQC) 5 and the data transmitted from a communication controller is reflected as a data having the delay time and data speed in matching with the test range and inputted to the communication controller.
Patent JP-S57120331-A (JP)
Title: Manufacture of semiconductor device
Inventor: KOSHIMURA TSUTOMU
IPC: H01L21/223
Filed: 1981-01-19
Abstract: PURPOSE:To protect a semiconductor substrate against the influence of a thermal strain and to stabilize a thermal diffusion method by performing the temperature rise to a target diffusing temperature via the diffusing treatment to the temperature fall from the diffusing temperature in the same heat treating unit when a conductive type deciding impurity is diffused by the thermal diffusion method. CONSTITUTION:A diffusion preventive layer 3 is formed for selective diffusion on a GaAs substrate 2 grown in gas phase for GaAsP crystal 2. the layer 3 as a mask an impurity is diffused in the substrate 1 to produce a P-N junction 4 in an arbitrary depth. At this time, a spike 5 might occur due to an abnormal diffusion to the slip line in the crystal 2 due to the difference of lattice constant between the substrate 1 and the crystal 2. A strain is produced at the side of the crystal 2 due to the difference of the thermal expansion coefficient between the layer 3 and the crystal 2 at the end of the layer 3, and an abnormal diffused region 6 might be produced similarly. Accordingly, the temperature in the furnace is reduced to approx. 450 deg.C, the substrate and the impurity are filled in the furnace, and are secured at approx. 800 deg.C, and are maintained at the same heat treating unit until they are lowered to 450 deg.C.
Patent JP-H10209765-A (JP)
Title: Voltage control amplifier circuit
Inventor: TAJIMA OSAMU
IPC: H03F1/30
Filed: 1997-01-17
Abstract: PROBLEM TO BE SOLVED: To reduce variations in gain due to temperature fluctuation by detecting variation in emitter resistance of respective transistors(TR) with temperature by buffers having inverted terminals connected to the respective emitters, and varying the supply potentials of the respective bases for compensation according to the variation of respective emitter potentials. SOLUTION: A TR Q3 increases in collector potential and decreases in emitter potential, as the emitter resistance increases with the rise in temperature. This is detected by a buffer 4, having its inversion terminal connected to the emitter and raises the base potential to increase the collector current, so that a rise in the collector potential due to an increase in the emitter resistance can be compensated. Further, buffers 5 to 7 are also connected also with respect to TRs Q4, Q9, and Q10 similarly to the buffer 4 and compensates variations in emitter resistance by a similar operation. Consequently, an emitter resistance component with large temperature variations is offset from the grain to reduce the variations in the gain due to the temperature variation.
Patent JP-S62164501-A (JP)
Inventor: NISHIZAWA SHIGEO
IPC: B27D1/00
Filed: 1986-01-16
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H03212625-A (JP)
Title: Optical material
Inventor: YAMAZAKI YUMIE
IPC: H01S3/108
Filed: 1990-01-18
Abstract: PURPOSE:To increase the rate of filling of hyperfine particles and to obtain an optical material having high nonlinearity by separately coating Si semiconductor-based nuclei of <= 200Angstrom  size with Si nitride layers and using the resulting hyperfine particles having dual layer structure. CONSTITUTION:Si semiconductor-based nuclei 2 are separatedly coated with Si nitride layers 3 having a large band gap to obtain hyperfine particles 1. The size of the nuclei 2 is <=200Angstrom , preferably <=100 Angstrom , especially preferably <=50Angstrom . As the size of the nuclei 2 is reduced, a confining effect can be produced and high nonlinearity can be expected. The Si nitride layers 3 are required to have >= 10 Angstrom  thickness so as to separated the nuclei 2. Though the max. thickness is not especially limited, the rate of filling of hyperfine particles lowers in accordance with the increase of the thickness. Since the hyperfine particles 1 can densely be deposited on a substrate, an optical material having higher nonlinear sensitivity than a binder dispersion type optical element material is obtd.
Patent JP-H05277311-A (JP)
Title: Apparatus for separating particle from flow of fluid
IPC: B01D29/62
Filed: 1993-01-20
Abstract: PURPOSE: To provide a maintenance structure that is continuously driven over the surface of a filter medium to maintain an optimum condition of the surface of the filter medium. CONSTITUTION: The apparatus for separating a clean filtrate from the main body of fluid in which particles are suspended includes the filter medium 17 in the tubular structure 11 composed to a type of a closed loop circuit 14. The filter maintaining structure 28 mounted on a continuous string existing within the lumen of the tubular structure is continuously driven on the surface of the filter medium and maintains the optimum conditions of the filter surface. The string mounted with the filter maintaining structure is so driven as to move around the annular circuit of the tubular structure by the hydraulic pressure generated by the fluid introduced into a separator for the purpose of filtration.
Patent JP-S63279067-A (JP)
Inventor: SONE KIYOHARU
IPC: F25B39/02
Filed: 1987-01-14
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H08200138-A (JP)
Title: Engine stop preventing device
Inventor: ISHII NOBUYUKI
IPC: F15B1/00
Filed: 1995-01-20
Abstract: PURPOSE: To prevent engine stalling by judging the engine overloading state by a means for detecting the magnitude of the engine load, and decreasing the engine load in the overloading. CONSTITUTION: An engine rotational signal N detected by an engine rotational sensor 8 is read by a controller 7, and the full rack position for showing the state where the engine load is 100% or more is calculated on the basis of the engine rotational signal N. The rack position Ra detected by a rack sensor 2 is read by the controller 7, the fullrack position and the rack position Ra are compared with each other. If the rack position Ra >= the full rack position, an input signal Rz is converted into a voltage signal V and output to an electromagnetic proportional valve controller 6, so that the value of the input signal Rz to a regulator 4 from an electromagnetic proportional pressure reducing valve 5 is increased only by ΔP, and the control current Isol is output to the electromagnetic proportional pressure reducing valve 5.  Secondary pressure of the electromagnetic proportional pressure reducing valve 5 satisfies Pz=Pz+ΔP according to the control current Isol, and the pump horsepower is decreased.