Patent GB-1241403-A (GB)
Title: Data processing apparatus
IPC: G06F9/46
Filed: 1970-03-26
Abstract: 1,241,403. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 26 March, 1970 [3 April, 1969], No. 14658/70. Heading G4A. Data processing apparatus has a plurality of data processing devices each of which is capable of addressing a programmed series of instructions for execution by an instruction execution unit shared amonst the data processing devices, the data processing devices being arranged in a plurality of arrays within each of which the data processing devices are timed so that no two data processing devices in any one array have coincident instructions, priority determining means being provided which, in the event of coincident instructions from different ones of the arrays of data processing devices, assigns an order of priority to the coincident instructions. Virtual processors, arranged in 4 arrays of 8 each, obtain instructions and operands from, and supply results to, a common main storage, the instructions going via instruction buffers respective to the arrays. Each virtual processor assembles an op code, two operands and a tag (identifying the virtual processor) into an "operand" word and sets a respective request bistable to produce a request signal. Clock pulses each increment a ring counter in each array in step to sample the request signals in turn. Each sampled request signal produces an array request signal from an OR gate and gates the "operand" word to a bus. A priority network receives the four array request signals if present. The highest priority request causes the corresponding "operand" word and a request signal to be sent to a common execution unit. In normal operation, the array priority is defined by a scaled priority ring counter having four outputs (one per array), incremented every 8 clock pulses to alter the priority order cyclically. In extended priority operation, a stage of a 4-bit excite register is set to control the priority network via a 4-bit inhibit register set in accordance with the excite register, scaled priority counter output and array requests present, so that if a request is present from the array corresponding to the set stage of the excite register it has priority over all other requests, whatever the output of the scaled priority counter, but if such a request is absent, priority is as in normal operation. The execution unit has separate execution boxes for floating point add/subtract, multiply and divide, fixed point add/subtract and multiply/divide, and boolean and shift operations. Any request signal sent to the execution unit causes the op code in the "operand" word to be decoded to signal the appropriate execution box. If this is not busy (i.e. free or at least sufficiently far advanced with the previous operation to be able to accept another) it stores the operands and tag and enables the common tag decoder to decode the tag and send an accept signal to the request virtual processor. This signal, via an accept bi-stable, resets the request bi-stable in the virtual processor. Sequencing of the virtual processor is inhibited while the request bi-stable is set and also if a respective inhibit bi-stable is set. The inhibit bi-stable is set and subsequently reset by the appropriate execution box in the execution unit in the case of divide operations since these take longer. When an execution box has completed its operation it passes the result and tag to a bus, the tag being decoded to cause the appropriate virtual processor to accept the result into an accumulator register. The virtual processors execute branch instructions (no details).