Patent RU-94036220-A (RU)
Inventor: GLEBOV V A
IPC: H03K3/84
Filed: 1994-09-26
Abstract: FIELD: active jamming equipment. SUBSTANCE: generator has a first and a second subtract counters, a first and a second synchronous pulse shapers, a NOR gate, a summary counter, a first and a second summators, a synchronous register and a clock driver. One input of the NOR gate is connected with a next-to-last digit output of the first subtract counter. First clock frequency output of the clock driver is connected with a sync input of the first subtract counter, a sync input of the register and a sync input of the first pulse shaper. Second clock frequency output of the clock driver is connected with a count enable input of the first subtract counter. Third clock frequency output of the clock driver is connected with a sync input of the second subtract counter. First digit writing input of the first subtract counter is connected with 2nd to kth digit writing inputs of this counter, inputs of the second summator for 1st to (k - 1)th digits of the first number and an off-bit signal supply terminal. (k + 1)th digit writing input of the first subtract counter is connected with a next-to-last, (k - 1)th digit output of the second subtract counter. (k + 2)th digit writing input of the first subtract counter is connected with (k - 2)th digit output of the second subtract counter. (k + 3)th digit writing input of the first subtract counter is connected with (k - 3)th digit output of the second subtract counter and an input of the second summator for kth digit of the first number. (k + 4)th digit writing input of the first subtract counter is connected with 2nd digit output of the second subtract counter and an output of the second summator for last, nth digit of the first number. Next-to-last, (m - 1)th digit writing input of the first subtract counter is connected with an input of the second summator for last, nth digit of the first number and an on-bit signal supply terminal. Last, mth digit writing input of the first subtract counter is connected with last, kth digit output of the second subtract counter. Digit write enable input of the first subtract counter is connected with output of the second pulse shaper whose information input is connected with 1st digit output of the second subtract counter. Asynchronous reset input of the first subtract counter is connected with output of the first pulse shaper whose information input is connected with inverting output of the NOR gate. 1st to (m - 1)th digit outputs of the first subtract counter are connected digit-by-digit with inputs of the first summator for 1st to next- to-last digits of the first number. Last, mth digit output of the first subtract counter is connected with the first summator output for the last digit of the first number and the other input of the NOR gate. Asynchronous reset input of the second subtract counter is connected with a switch-on instruction initiating terminal. Count enable input of the summary counter is connected with an overflow output of the first summator. 3rd to (n + 2)th digit outputs of the summary counter are connected digit-by-digit in order of increasing the digit number with inputs of the second summator for 1st to nth digits of the second number. An overflow output of the second summator is connected with an output terminal of the generator. 1st to mth digit inputs of the register are connected digit-by-digit with inputs of the first summator for digits of a sum. 1st to mth digit outputs of the register are connected digit- by-digit with inputs of the first summator for digits of the second number. EFFECT: improved design.