Patent GB-1057392-A (GB)
Title: Improvements in or relating to trigger circuits for firing silicon controlled rectifiers
Inventor: THOMPSON RAYMOND
IPC: H02M1/08
Filed: 1962-08-24
Abstract: 1,057,392. Semi-conductor circuits. PLESSEY CO. Ltd. Aug. 23, 1963 [Aug. 24, 1962], No. 32554/62. Heading H3T. A circuit for firing a plurality of siliconcontrolled rectifiers, one at a time, in a predetermined sequence, comprises a ring circuit composed of a plurality of blocking oscillators, one for each SCR to be fired, and means whereby when one SCR is fired a corresponding blocking oscillator is conditioned so as to be triggered on the next application of a trigger pulse to a common input terminal, the triggering of this blocking oscillator causing a subsequent SCR to be fired, this extinguishing the previously fired SCR and conditioning the next blocking oscillator in the ring to be triggered on the next application of a trigger pulse. Fig. 1 shows a circuit in which the triggering of blocking oscillators 1, 2, 3 by pulses applied on line 4 cause the firing of SCR's 5, 6, 7 respectively. commutating capacitors 12, 13, 14 ensuring that the firing of any one SCR causes all others to be extinguished. The blocking oscillators are normally biased so as not to be triggered by the application of pulses on line 4; however, the firing of any one SCR, e.g. 5, results in a bias voltage developed across the corresponding anode load, e.g. 9, being applied to the next subsequent blocking oscillator, e.g. 2, so that it is triggered by the next pulse applied via line 4. SCR's 5, 6, 7 are thus fired cyclically and sequentially on the application of trigger pulses to the circuit. Additional outputs A, B, C from blocking oscillators 1, 2, 3 may be used for the firing of further SCR's. Fig. 2 shows a modified circuit in which the first trigger pulse after switching on always causes SCR 5 to be fired. Blocking oscillator 1 is normally biased so as to respond to an applied trigger pulse while oscillators 2, 3 are biased so as not to respond to such pulses. Thus the initial pulse triggers blocking oscillator 1 and SCR 5 is fired. A bias is then applied via diode 16 to render oscillator 1 non-responsive while simultaneously oscillator 2 is conditioned by the bias applied from load 9. A subsequent pulse thus causes SCR 6 to fire so that oscillator 3 becomes conditioned while oscillator 1 remains non-responsive due to bias applied via diode 17. Finally, when SCR 7 is fired, bias is no longer applied via diodes 16, 17 to oscillator 1 which thus is able to respond on the next application of a trigger pulse. Fig. 3 (not shown) shows the circuit of Fig. 2 in greater detail. The emitter circuit of a transistor (VT2) constituting the blocking oscillator 1 is normally biased positively with respect to the emitters of the transistors (VT3, VT4) of the blocking oscillators 2 and 3 so that a positive trigger pulse tends to trigger oscillator 1. When either of SCR's 5, 6 conducts, however, negative bias is applied to the emitter of the first transistor (VT2) to render it non-responsive to trigger pulses while simultaneously negative bias applied to the base respective one of the other transistors (VT3, VT4) renders the latter responsive to the trigger pulses.