Patent GB-945112-A (GB)
Title: Improvements in or relating to signal translating arrangements using two terminal negative resistance semi-conductive devices
IPC: H01L29/00
Filed: 1960-01-11
Abstract: 945,112. Semi-conductor switching circuits. SHOCKLEY TRANSISTOR CORPORATION. Jan. 11, 1960 [Jan. 14, 1959], No. 1001/60. Heading H3T. [Also in Division H1] A signal translating arrangement comprises a negative resistance PNP or PNPN device and means for applying a short, steep impulse across the device sufficient to cause breakdown and to change the base layer rapidly with carriers and a load circuit through which flows avalanche current from the device. Fig. 1 shows a two electrode PNP switching device with " emitter " e and " collector " C; the arrangement is such that alpha (the proportion of minority carrier reaching the collector junction) increases with emitter current, such as in a suitable silicon device or one with a resistor connected across the emitter junction. The voltage current characteristic of the device (Fig. 2, not shown), has a negative resistance portion due to the interaction of avalanche effect at the collector junction and alpha of the emitter junction. It is explained that instability can arise in large area devices of this type due to lateral resistance in the base zone. This can be avoided by applying a steep, short impulse to the device which results in a charging of the base layer with majority carriers before the injected carriers from the emitter can pass through the base. A suitable circuit is shown in Fig. 8 which shows a PNP device across which is connected a diode rectifier and a condenser C 2 , charged to a voltage V 2 . A short impulse is applied to the device from the INPUT terminal so that it initially acts as a conventional avalanche diode since there is insufficient time for the injected carriers to pass through the base, and then as the voltage across the device falls below V 2 , the rectifier conducts and the capacitor discharges through the device a quantity of current equal to about twenty times (assuming an alpha of about 0.95) that which was provided by the input circuit. Conduction does not continue indefinitely even if C 2  is large since V 2  is less than the " holding " voltage for the device when this is in the avalanche conducting state. Fig. 10 (not shown), describes the conditions applying to a NPNP device; in this case a small " reverse " bias (i.e. collector junction forward biased) is initially applied to the device so that majority carriers are drained from the base zones to provide space charge zones at each of the emitter junctions. Forward voltage is then applied and avalanche conditions arise at the collector junction before the emitter space charge zones have been eliminated; when avalanche occurs the space charge zones are quickly discharged, current flows by injection, alphas increase and turn-on begins. Turn-off is assisted by the passing of verse current. The Specification describes the construction of a large area PNP device shown in Fig. 6. This includes a ring of heavily doped N+ + material around the base zone to prevent surface conduction channels and provide a ring of constant voltage value in the base zone. A lower concentration gradient is produced at the surface regions of the collector junction so that avalanche multiplication occurs in the central working region. Fig. 7 shows a further large area arrangement comprising a rib and web structure. Specification 813,862 is referred to.