Patent GB-1287093-A (GB)
Title: Improvements in or relating to data transmission
Inventor: MARSHALL ANTHONY ROBERT JOHN
IPC: H04L1/00
Filed: 1968-08-22
Abstract: 1287093 Telegraphy PLESSEY CO Ltd 21 Nov 1969 [22 Aug 1968] 40305/68 Heading H4P A selected pattern of signal elements are inverted prior to transmission and re-inverted on reception whereby in the absence of correct synchronizing an operation is effected in dependance upon the error pattern in order to synchronize the receiver to the received stream of signal elements. A plurality of signal elements in each transmitted character may be inverted for example the first three signal elements comprising alternate information and check signal elements. In the bit stream illustrated in Fig. 2 (not shown) each signal element I is interleaved with a check element C the latter being produced by modulo 2 units (7-9) which produce a 0 output if the inputs are the same and a 1 if the inputs are different. The bit stream travels to the left in the dwg. and depending on the relation of the signal elements (a, b) a 0, 1 check bit is inserted at (d) similarly at f, g) hence as the detectors scan the bit stream each signal element is used twice. The first three elements in every twelve are inverted before transmission and are reinverted on reception in a unit 14 controlled by a highly stable timing arrangement 15, which also controls a switch 16, which if correctly synchronized to the incoming signal directs information bits to path 17 and check elements to path 18. Information signals are delayed by one element in unit 19 and then are passed into 6-stage serially connected shift registers 20-22 the outputs from registers 20, 21 being applied to a modulo 2 unit 23 having an output into modulo unit 24 also receiving the check elements, unit 24 has an output to a syndrome shift register comprising two serially connected six-stage registers 26, 27 which feed into an AND gate 28. This also has an input from shift register 26 and from unit 24 via an inverter 29. The output from gate 28 controls an inverter 30 passing information elements from register 22 to an output terminal 31. Selected pairs of incoming information signals are compared in unit 23 to produce check element stream on line 32 which is compared with check elements on line 18 and in the event of discrepancy unit 24 supplies a 1 signal to shift registers 26, 27. Selected pairs of incoming information signals are compared in unit 23 to produce a check element stream on line 32 which is compared with the check elements received on line 18 and in the event of discrepancy a 1 signal supplied to shift registers 26, 27 so that error pulses are in evidence at points f<SP>1</SP>, d<SP>1</SP>. If an error pulse is applied to inverter 29 then the pulse present at point b<SP>1</SP> is incorrect hence an output is provided from AND gate 28 to cause an invertion in unit 30 of the information signal before it is applied to output terminal 31. If an incoming signal is displaced by one bit so that check elements are applied to line 17 instead of line 18 the check elements will be displaced by an odd number of places and an error pattern in the syndrome register will not be recognizable. In the circumstances an output would be provided on line 33 to timing unit 15 to cause it to be displaced by one element hence if the signal stream is then correct no further correction is required but if the signal element stream is out of phase with the receiver by an even number of elements an error pattern will occur in the syndrome register so that timing unit 15 will be retarded by the required number. Time constants should be applied to the system such that re-timing does not occur until a predetermined time after the detection of errors, or a determined number of error signals have been received.