Patent GB-1311683-A (GB)
Title: Electronic memory systems
IPC: H03K19/013
Filed: 1970-04-23
Abstract: 1311683 Memory addressing HONEYWELL Inc 23 April 1970 [23 June 1969] 19642/70 Heading G4C [Also in Division H3] An addressable matrix memory system comprises a number of selection circuits 10A-10D which consist of a first binary circuit coupled to (; memory address line and responsive to the leading edge of an input pulse (supplied at terminal 12) to generate a first output pulse Ao having a leading edge delayed with respect to the leading edge of the input pulse, and a second binary circuit connected to a memory address line and responsive to the leading edge of the first output signal Ao to generate a second output pulse A<SP>1</SP>o having a leading edge delayed with respect to the leading edge of the first output pulse, the second circuit being responsive to the trailing edge of the input pulse to generate the trailing edge of the second output pulse A<SP>1</SP>o which is delayed with respect to the trailing edge of the input pulse, the trailing edge of the firs output pulse Ao being delayed with respect to the trailing edge of the second output signal, the first and second output pulses being complementary. The system also includes a decoder connected to the selection circuits and operates so as to prevent the concurrent selection of more than one address line. Memory cells.-As described each cell consists of a pair of cross-coupled double emitter transistors acting as a bistable circuit. Address selection is effected when no current flows in the corresponding address line. If transistor 83 had been previously conducting and 81 non- conducting, current flows in data line 90, via emitter 83a, when line 82 is selected. This current is sensed by the sense circuits 88 which are also used for writing data into the cells. Address circuitry.-When input terminal 12 is at ground potential transistors 20 and 40 are non-conductive, transistor 30 is conductive, output terminal 50 is at ground and output terminal 52 at its positive (ONE) level. When terminal 12 is driven positive transistor 20 conducts, transistor 40 conducts at time t2 (Fig. 2b) and transistor 30 turns off at time t3. When input 12 reverts to ground potential transistor 20 turns off, transistor 30 conducts at time t5 and transistor 40 turns off at time t6. The complementary output waveforms illustrated in Fig. 2b, 51, 53 are therefore produced at output terminals 50 and 52 respectively. Four selection circuits are provided and their outputs are connected to the decode circuits 100 as ahown. Address lines are not selected unlsss a signal is present at the enable circuit 111. When a ground potential is present at terminal 111 transistor 112 conducts and transistor 116 is held off. Similarly transistors 122 and 124 are held off and the output terminals are free to assume complementary levels. A positive signal level at terminal 111 reverses the above situation and the collectors of transistors 122, 124 go to ground and thus clamp terminals 50 and 52 at ground potential inhibiting addressing. Multiple emitter transistors are provided as decode gates, there being sixteen in all each receiving a unique permutation of the selection circuit outputs. When all the inputs to a decorder are positive the transistor turns off and the corresponding address line, e.g. 82, is selected. The circuitry is such that at no time will the outputs from a selection circuit both be in their high (select) level.