Patent GB-997411-A (GB)
Title: Improvements in or relating to digital storage systems
Inventor: EDWARDS DAVID BEVERLEY GEORGE
IPC: G11C11/06
Filed: 1960-08-30
Abstract: 997,411. Circuits employing bi-stable magnetic elements. NATIONAL RESEARCH DEVELOPMENT CORPORATION. July 27, 1961 [Aug. 30, 1960], No. 29929/60. Heading H3B. [Also in Division G4] A word-organized array for storing h words of N binary digits each and requiring two magnetic cores for each stored bit comprises N columns of cores A, B . . . X, the binary digits of the various words being represented by the relative states of adjacent pairs of cores in the same column, such as cores a1 a2, the cores of such pairs being in opposite saturation states. All the cores in which a word is stored are linked by a common word wire such as 12a, the various word wires being connected to word selection means 13 which is supplied from a read/write waveform generator 16. Column wires 11a are connected to digit write circuit means 18a and column wires 10a are connected to read circuit means 17a, the read wires 10a threading successive cores a1, a2 in opposite senses. For reading, a read pulse is applied to the selected word wire 12a to return all cores to the " 0 " state, the polarity of the output pulse on the read wire 10a indicating the value of the corresponding binary digit. During a subsequent read operation, the current in the word wire 12a is reversed and simultaneously a positive or negative half current applied to the various wires 11a in accordance with the desired digit values to be stores, such currents assisting the word wire current in one core of a pair and inhibiting it in the other. With this arrangement the load on the driving circuits is always constant. In a modified arrangement, Fig. 4, for reducing the load on the word wires 12a &c., groups of two binary digits are represented by the relative states of four cores such as al, a2, b1 b2, only one-core of the four being in the " 1 " state, as shown in Fig. 3, a coder being provided for each pair of digit wires 11a, 116 and a decoder 14 for each pair of read wires 10a, 10b. In this modified arrangement, to provide switching of one core only of the two cores of the word in each column the value of the write current may be limited Alternatively, separate writes wires 11a<SP>1</SP>, 11a<SP>11</SP> may be provided for each core of a pair, Fig. 5, the cores al, b1 ... being arranged in one plane, the cores a2, b2... being arranged in an adjacent plane, each read wire 10a being earthed at its centre point where it passes from one plane to the other. Biasing arrangements.-A bias wire 17 threading all the cores of the matrix is provided with a current of + If/2, Fig. 6, the read current thus being + 3 If/2 and the write current - If/2 which combined with a digit write current of - If, for writing a binary "1," gives a total drive of - 3 If/2. The cycle time may be reduced by increasing the magnitude and reducing the duration of the read current (Fig. 7, not shown). A resistor 19, Fig. 5, may be included in each word wire to reduce the time constant associated with the loop inductance. Oil bath immersion may be employed to improve heat dissipation. The cycle time may be further reduced by employing a read/write word current of  2 If (Fig. 8, not shown) instead of the If current of Fig. 6, the duration of this current being reduced so that an ineffective partial switching only is achieved in cores which it is not desired to switch. In a modified scheme, applicable to all the embodiments, the amount of flux change is deliberately limited to a value less than that necessary to effect full switching from one state to the other (Fig. 10, not shown).