Patent GB-1349538-A (GB)
Title: Signal systems
IPC: H04L25/02
Filed: 1971-06-03
Abstract: 1349538 Adapline equalizers PHILCO-FORD CORP 3 June 1971 [3 June 1970] 18909/71 Heading H4R The invention resides in the provision of an estimator (12) in an otherwise conventional receiver illustrated in Fig. 1 (not shown), for multi level signals i.e. 2-8 levels transmitted at high bit rate so that there is substantial risk of inter-symbol interference.  The estimator operates on the principle of storing signals, which are subtracted from successive signals in order that interference may be balanced out, and this is performed successively in a series of stages each comprising a feedback loop. In order that 2, 4 and 8 level signals may be accommodated, the apparatus is designed for 8 level signals with 2 and 4 level signals coded to 8 before processing and decoded after which arrangement reduces switching complexity. Entry to the estimator (12) of information signals Xk from sampler (24) is through a gate 50 stepped by a clock pulse at symbol rate, on 56 which signals are passed through an adder 52 and decision circuit 54 to input B8 of shift register 46, also stepped at symbol rate. For 8 level signals, three bits per symbol, each of stages B8- B45 may comprise three stages in parallel. Serial readout may be provided from B45 only at a multiple of symbol rate so that circulation occurs once per symbol. Input to adder 52 is in "two's complement" form, hence adder 52 supplies a difference signal from inputs 50, 80. Gated signals Xk are also supplied through a delay 58 to adder 90 and through successive delays 60, 62, 64 to adders 92, 94, 66 the output from the latter being supplied in parallel to divider circuits 48a-48p the outputs from which are supplied in parallel once per symbol period through gate 70 to accumulator 72a-72o which is again gated by 76 to storage stages 74a-74p. Each of stages 72a-72p, 72a-72p and 74a-74p may comprise three stages in parallel. Appropriate outputs of shift register 46 and stages 74 are fed to summing circuit 80-86 which together with inputs from delay lines 58, 60, 62 feed the adding circuits which through decision circuits 96 &c. replace in relevant sections of shift register 46, signals supplied by the preceding section. Signals supplied to the adders are in "two/s" complement form i.e. have an output representative of a difference between signals from delay lines and corresponding summing circuits 80, 82 &e; i.e. the adders subtract interfering terms developed by circuits 80-88 from received signals and the remainder is passed to decision circuits to determine with high probability which symbol was transmitted. These decisions are then placed in the relevant stage of shift register 46 and are used to compute succeeding interference terms. The first approximate signal is placed in B8 which is shifted through the register to B15 and successive samples likewise. The B15 to B8 decisions are then used in computing a new lagging interference term in summing circuit 80. The Xk signal delayed by 8T is applied to adder 90 also receiving leading interference H1-H7 as well as lagging interference terms H9-H16 which have accumulated by this time, resulting in an improved term being placed into B16 through decision circuit 96. Two more iterations of this process produce inputs to stages B23, B30. Subsequent shifts place the best decisions in stages B30-B45. During the next symbol time the process is repeated with a new set of quotients added to 72a-72p. After 4096 cycles, each quantity stored in these stages is divided by this number and passed into 74a-74p. A more detailed explanation of the estimator (12) and how product summation may be formed in circuits even nos. 80-88 is given with reference to Fig. 6 (not shown).