Patent SG-11201807962Q-A (SG)
Title: Thermal insulation for three-dimensional memory arrays
Inventor: FANTINI PAOLO
IPC: H01L27/24
Filed: 2017-03-17
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -, Organization 11111111011110111010101111101011111011101011111011110111101101111101111011111 International Bureau 0.. .... .. (10) International Publication Number (43) International Publication Date ..... ...r .....1 WO 2017/172389 Al 5 October 2017 (05.10.2017) WI P0 I P CT (51) International Patent Classification: HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, HO1L 27/24 (2006.01) KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, (21) International Application Number: NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, PCT/US2017/022984 RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, (22) International Filing Date: TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, 17 March 2017 (17.03.2017) ZA, ZM, ZW. (25) Filing Language: English (8 4 ) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, (26) Publication Language: English GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, (30) Priority Data: TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, 15/088,475 1 April 2016 (01.04.2016) US TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, 8000 S. Federal Way, Boise, Idaho 83716 (US). SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, (72) Inventor: FANTINI, Paolo; 8000 S. Federal Way, Boise, GW, KM, ML, MR, NE, SN, TD, TG). Idaho 83716 (US). Declarations under Rule 4.17: (74) Agent: KRAFT, Aaron J.; Holland & Hart LLP., P.O. — as to applicant's entitlement to apply for and be granted a Box 11583, Salt Lake City, Utah 84147 (US). patent (Rule 4.1700) (81) Designated States (unless otherwise indicated, for every — as to the applicant's entitlement to claim the priority of the = kind of national protection available): AE, AG, AL, AM, earlier application (Rule 4.17(iii)) = AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, Published: — BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, — with international search report (Art. 21 ( 3 )) = (54) Title: THERMAL INSULATION FOR THREE-DIMENSIONAL MEMORY ARRAYS = (57) : Methods, systems, and devices for — a three-dimensional memory array are described. — = Memory cells may transform when exposed to el- _ = ;- . 2%.%-' , ,-%:///, //,%%../ %- .%• /./LLz.< 1 / 2 /7.././ 0./ A ;4&/ including evated temperatures, elevated temperat- ures associated with a read or write operation of a = neighboring cell, corrupting the data stored in = them. To prevent this thermal disturb effect, = — //, .// //A 2/ memory cells may be separated from one another by thermally insulating regions that include one or = several interfaces. The interfaces may be formed = by layering different materials upon one another = = - - %......%/4/.%.' /, . . ,, \" 2% %',///4%. 1 / 4 2, - /.; .''%;i%; ''%i.%; or adjusting the deposition parameters of a materi- al during formation. The layers may be created deposition for with planar thin-film techniques, _ = _ 11 GC en ei N 1-1 --.... IN 1-1 0 ei 1—j I 01 310-c 110.d Insulating sublayer [t i WAord Memory cell Electrode c.:3-d 220-b FIG. l_ y _J _ 0-b Line 4 410 rj • Selection component n Electrode 405 '''---- example. 400 O