Patent EA-000570-B1 (EA)
Title: Ink jet print head identification circuit with serial out, dynamic shift registers
Inventor: PARISH GEORGE K
IPC: B41J2/125
Filed: 1996-09-26
Abstract: 1. An identification system for providing ink jet print head identifying information in ink jet printers having ink jet print heads, comprising: a controller and drive circuit for transmitting signals including at least one clock signal in the form of clock pulses and for receiving signals; a plurality of address lines for transmitting signals including said at least one clock signal from the controller and drive circuit to the ink jet print head; an identification circuit disposed in the ink jet print head and containing a digital code corresponding to the print head identifying information, being connected to receive said at least one clock signal from said address lines and being responsive to said at least one clock signal to serially transmit the digital code; an output line connected to said identification circuit for transmitting the bits of the digital code to the controller; and said controller being connected to receive the bits of the digital code from the output line and being programmed to interpret the digital code and determine the print head identifying information. 2. The system of Claim 1 wherein said identification circuit further comprises a predetermined number of shift registers, each of said shift registers being programmed in accordance with the digital code to produce an output of either a logic one or a logic zero in response to said at least one clock signal. 3. The system of Claim 1 further comprising: said controller and drive circuit further transmitting at least one load signal; said address lines for transmitting said at least one load signal; said identification circuit including a predetermined number of shift registers, each of said shift registers being programmed in accordance with the digital code to produce an output of either a logical one or a logical zero in response to said at least one load signal and at least one clock signal; and said controller being programmed to transmit the load signal and, following the load signal transmission, interpret a next predetermined number of bits on the output line as the digital code. 4. The system of Claim 1 further comprising: said controller and drive circuit further transmitting at least one load signal; said address lines for transmitting the load signal; said identification circuit including a load circuit and a transmit circuit, said load circuit being connected to receive said load signal from said address lines and being responsive to the load signal to load the digital code into the transmit circuit, said transmit circuit being responsive to said at least one clock signal after being loaded with the digital code to serially transmit the digital code on the output line; said controller being programmed to transmit the load signal and, following the load signal transmission, interpret a next predetermined number of bits on the output line as the digital code. 5. The system of Claim l further comprising: said controller and drive circuit further transmitting at least one load signal and first and second clock signals; said address lines for transmitting said at least one load signal and said first and second clock signals; said identification circuit including a load circuit and a transmit circuit, said load circuit being connected to receive said load signal from said address lines and being responsive to the load signal to load the digital code into the transmit circuit as the loaded digital code, said transmit circuit being responsive to the loaded digital code and the first and second clock signals to serially transmit the digital code on the output line; said controller being programmed to transmit the load signal and, following the load signal transmission, interpret a next predetermined number of bits on the output line as the digital code. 6. The system of Claim I wherein said identification circuit further comprises: a load circuit connected to receive the load signal from said address lines and being responsive to the load signal to load the digital code for serial transmission; and a transmit circuit for being loaded with the digital code by the load circuit and being responsive to said at least one clock signal to serially transmit the multibit code to said output line 7. The system of Claim 6 wherein said transmit circuit further comprises a discharge device for discharging the transmit circuit after serial transmission of the digital code. 8. The system of Claim 1, further comprising a temperature sense circuit connected to said output line for transmitting information corresponding to the temperature of the print head. 9. A method for providing ink jet print head identifying information to an ink jet printer having printer electronics and an ink jet print head, the print head including an integrated circuit having print head array electronics, a temperature sense circuit with an output connected to the printer electronics, an identification circuit, an output device connected to the temperature sense circuit output, and a plurality of address lines interconnecting the identification circuit and printer electronics, the method comprising the steps of: programming a digital code having one or more bits into the identification circuit, each bit of the code being programmed as either an electrically conducting short or a non-conducting gap the digital code corresponding to the print head identifying information; transmitting signals generated by the printer electronics including at least one clock signal in the form of clock pulses, on the address lines to the identification circuit; transmitting one or more bits of the digital code to the output device in serial digital format in response to the signals generated by the printer electronics; and reading the digital code by the printer electronics as the digital code is transmitted to the output device. 10. The method of Claim 15, further comprising the step of determining the identifying information from the transmitted digital code by the printer electronics based in part on the condition of each bit as either a gap or a short. 11. The method of Claim 15, further comprising the step of transmitting a load signal, as a printer electronics signal, to the identification circuit via the address lines. 12. The method of Claim 15, further comprising the step of resetting the output device following transmission of the digital code to the output device.