baber/WOPTO huggingface dataset:
Patent TW-447024-B (TW)
Title: Asymmetric channel doped MOS structure and method for same
Inventor: HSU SHENG-TENG
IPC: H01L21/336
Filed: 1998-07-31
Granted: 2001-07-21
Abstract: A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, a directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger Id currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.
Patent TW-394980-B (TW)
Title: Semiconductor device fabrication system and method of forming semiconductor device pattern using the same
Inventor: JEOUNG GYU-CHAN
IPC: H01L21/30
Filed: 1998-07-31
Granted: 2000-06-21
Abstract: There are provided a semiconductor device fabrication system for carrying out a UV-bake on a photoresist pattern in the semiconductor device pattern formation and a method of forming a semiconductor device pattern using the same. The semiconductor device fabrication system comprises a photoresist coating unit for coating a wafer transferred from a wafer loading unit with a specific photoresist; a developing unit for forming a photoresist pattern on the wafer by aligning a photo mask on the wafer, exposing the wafer, and developing the exposed wafer; and a UV bake unit for irradiating the developed wafer with a UV light in order to guide a stabilized flow during the flow process for the photoresist pattern. The method of forming a semiconductor device pattern comprises the steps of: forming a photoresist pattern by coating a wafer with a photoresist by exposing the photoresist, and developing and cleaning the photoresist; carrying out a UV bake for the photoresist; and carrying out a flow bake for the photoresist pattern after the UV bake.
Patent TW-486483-B (TW)
Title: Preparation of phosphonic acid derivatives
Inventor: WOODWARD GARY
IPC: C07F9/38
Filed: 1998-12-30
Granted: 2002-05-11
Abstract: The method provides for the preparation of alkene phosphonic acids and salts thereof, such as VDPA (vinylidene diphosphonic acid). The products can be in a produced in a stable, substantially pure form and in high yield. The method includes the azeotropic removal of water from salts of Α-hydroxy-alkane disphosphonic acid dimer or corresponding acids thereof, and the pyrolysis of the dehydrated reactant at a temperature of from 170 DEG C to 300 DEG C. There may be included a step to convert anhydrides which have been formed during the pyrolysis. The method may include the use of heat transfer agents and/or bases, and may be carried out at elevated or reduced pressure.
Patent TW-438617-B (TW)
Title: Filter pre-wet system
Inventor: CHENG WAN-LI
IPC: B01D35/00
Filed: 1999-01-08
Granted: 2001-06-07
Abstract: Impurities and particles in liquid chemical materials need to be removed with filters in semiconductor manufacturing processes. The filters for performing the effect of filtration need to be pre-wet before use to wet the hydrophobic filter membrane. Conventional pre-wet process is performed manually, which not only is time and labor consuming, pre-wet is incomplete, but also is vulnerable to contamination in the process and causes the defect in manufacturing. The invention presents a filter pre-wet system, which includes a wetting solution circulation supply apparatus that connects to the filter needed to be pre-wetted, and at least a pump to circulate and supply the wetting solution to the filter; a pure water supply apparatus that connects to the filter needed to be pre-wetted and supplies pure water to the filter; and a filtrate discharge apparatus that connects to the filter needed to be pre-wetted and discharges filtrate produced during pre-wet treatment, the filtrate can be recycled after further treatment. The present invention can effectively improve the disadvantages of the previous technologies.
Patent TW-408353-B (TW)
Title: A semiconductor device and a method of manufacturing the same
Inventor: SHINTAKU HIDEOMI
IPC: H01L21/3205
Filed: 1999-01-13
Granted: 2000-10-11
Abstract: In a semiconductor device, a contact region is formed with polycrystalline silicon or the like to be connected to a drain fabricated at a predetermined position of a semiconductor substrate. A bit line is formed with polycrystalline silicone or the like to be coupled with the contact region 116 and then a dummy wiring is simultaneously fabricated at a predetermined position in a peripheral region of the substrate. Thanks to the provision, a film formed through a coating process has a uniform thickness.
Patent TW-I257930-B (TW)
Title: Process for preparing polymers
Inventor: MCGRAIL PATRICK TERENCE
IPC: C08J5/24
Filed: 1999-02-24
Granted: 2006-07-11
Abstract: Process for the preparation of a polymer composition comprising at least one aromatic or a mixture thereof, the process comprising: (i) obtaining a reaction mixture comprising polymer precursors in a first fluid boiling in excess of 100 DEG C; (ii) subjecting the reaction mixture to a first elevated temperature in excess of 100 DEG C to generate the alkali metal salts of polymer precursors and the polymer reaction products thereof; and (iii) subjecting the reaction product mixture to at least a second temperature and isolating the reaction product in the form of a polymer composition which is substantially insoluble in a second fluid, from the first fluid which is substantially soluble in the second fluid, by contacting with an amount of second fluid; wherein the process is conducted in substantial absence of an effective amount of an azeotrope; novel intermediates thereof; polymer composition obtained thereby; resin formulations thereof; method for manufacture of composites thereof; and uses thereof.
Patent TW-440850-B (TW)
Title: Nonvolatile semiconductor memory device
Inventor: SUDO NAOAKI
IPC: G11C16/06
Filed: 1999-03-24
Granted: 2001-06-16
Abstract: The object of the present invention is to reduce the dispersion of the threshold after writing while maintaining the high speed nature of a write system in a nonvolatile semiconductor memory such as a flash memory of channel hot electron write type. The feature of this invention is to provide a memory with a write current detection type write circuit and a sense amplifier for read, and to switch, for verification at the time of write, between verification by the write current type write circuit and verification of normal read mode which uses the sense amplifier for read. In other words, when a cell threshold of write level is designated as a first threshold and a specified threshold level lower than the first threshold is designated as a second threshold, write operation by the write current detection type write circuit is performed at the beginning of write mode, and stops the write operation when the current flowing between the drain and the source of the memory cell falls to below or equal to the reference current corresponding to the second threshold. Thereafter, the write operation is performed by repeating the write operation and verification operation using the sense amplifier until the cell threshold reaches the first threshold.
Patent TW-452752-B (TW)
Title: A display device
Inventor: SURGUY PAUL WILLIAM HERBERT
IPC: G02F1/13357
Filed: 1999-04-01
Granted: 2001-09-01
Abstract: A display device comprises a matrix (11) of pixels (10) arranged in rows and columns, each pixel (10) being selectively settable into a light transmissive condition and an opaque condition, and an illumination system, comprising an array of elongate elements (4, 5, 6) which provide light in response to electrical impulses, the elements (4, 5, 6) being arranged side by side to give a striped appearance and to face the matrix (11). Adjacent elements provide light having a different one of a plurality of colours. The matrix (11) is addressed using a row by row addressing sequence. During part of this sequence, a row of pixels (10) is illuminated with light of a first colour from a first element, whilst a remote row of pixels is illuminated with light of a different colour from a further element. This enables more efficient illumination of the matrix (11) than with conventional colour sequential displays in which all rows are illuminated with the same colour at the same time.
Patent TW-394711-B (TW)
Title: Duct-cleaning unit
Inventor: ANDO SUMIO
IPC: B08B9/055
Filed: 1999-04-29
Granted: 2000-06-21
Abstract: An improvement of the duct-cleaning unit is disclosed for scraping the deposits from the inner surface of the flow line, which are residual in the flow lines after the completion of conveyance of any fluid material to thereby clean the flow lines as well as recover the material left in the tubing. The improvement is comprised of a pair of spherical guiding bodies 1,1 coupled to lengthwise opposing ends of a connector member 3, one to each end, through universal joints. The spherical guiding bodies 1,1 are each provided at the location near the connector 3 with an annular pressure-carrying surface 7 that makes fluid-tight contact at its outermost periphery with the inner surface of the tubing A. The design of the present invention may make the cleaning unit smaller in size, so that the residual deposits in flow lines, in particular, at the relatively small radius bent in the flow line, may be reliably removed and pumped out the flow lines with the result of the high efficiency in cleaning process.
Patent TW-405013-B (TW)
Title: Glass panel
Inventor: ENOMOTO TAKANOBU
IPC: E06B3/66
Filed: 1999-04-30
Granted: 2000-09-11
Abstract: A glass panel comprising a glass panel body (P1) having a pair of pieces of flat glass (1A, 1B) disposed with a width-direction gap therebetween and a vacuum-enclosed space part (V) formed therebetween, a suction part (6) formed by projectingly providing a suction port blocking part (7), used after the evacuation of the space part (V), on the surface of one of the pair of pieces of flat glass (1A, 1B), and a suction-port-blocking-part (7) protecting cap (9) bonded to the one flat glass (1A) so as to cover the suction part (6), wherein a tapering first inclined surface (10) is formed on the outer periphery of the cap (9) and a space (S) is formed between the inner space peripheral wall of the cap (9) and the suction port blocking part (7).
Patent TW-469149-B (TW)
Title: Game system for playing with medals
Inventor: OGINUMA TAKESHI
IPC: G07F17/38
Filed: 1999-05-31
Granted: 2001-12-21
Abstract: To diversify the progress of a game and to properly manage the flows of medals, a medal game system is provided. The game system comprises a container for storing the medal, an escalator for guiding the medal in an aligned state, a mechanism for sending out the medal stored in the container toward the escalator, and a discharge mechanism for flipping the medal in the escalator out through an exit thereof.
Patent TW-401489-B (TW)
Title: Combination of screw with driver bit or wrench
Inventor: TOZU KATSUYUKI
IPC: F16B23/00
Filed: 1999-06-07
Granted: 2000-08-11
Abstract: A screw with a polygonal hole (30) formed with a polygonal hole (32)disposed in the center of a screw head (30a) and comprising a vertical wall (33) with a preset depth, and with a cone base oriented from the lower edge of the vertical wall toward the center of a screw neck, wherein a vertical step forming an inscribed circle of the polygon is provided at the lower edge (33a) of the vertical wall (33) of the polygonal hole (32) formed in the screw head (30a), the cone base (35) oriented from the lower edge (34a) of the vertical step (34) toward the center of the screw neck is formed, and a driver bit (40) or wrench (41) to be fitted to this screw is provided at the tip of a peak edge (42) with a cylindrical projection (44) forming the inscribed circle of the polygon.
Patent TW-528847-B (TW)
Title: Refrigerator
Inventor: TAKAGI JUNICHI
IPC: F25B49/00
Filed: 1999-06-14
Granted: 2003-04-21
Abstract: When inverter control is implemented in a refrigerator or the like, the rotating speed of a compressor motor is often operated at the preset minimum rotating speed. At this time, there has been a problem that when the DC voltage is boosted, the efficiency of the circuit drops due to switching loss in the power element. Still more, when the DC voltage is boosted even at the minimum rotating speed, the lowest voltage of the DC voltage must be controlled at 163 V or more including the fluctuation of the voltage. Therefore, there has been a problem in that the efficiency of the compressor motor also drops. To avoid these problems, when the temperature within a compartment of a refrigerator is cooled and approaches a preset temperature, and when a conduction ratio of the compressor motor falls below a preset value or a command on a rotating speed of the compressor motor becomes a preset rotating speed and the actual rotating speed also becomes the preset rotating speed, the control of the converter control circuit is turned off.
Patent TW-461973-B (TW)
Title: Progressive addition lenses
Inventor: CHIPMAN RUSSELL A
IPC: G02B7/04
Filed: 1999-07-30
Granted: 2001-11-01
Abstract: The present invention relates to ophthalmic lenses. In particular, the invention provides ophthalmic lenses with reduced astigmatism. The lenses are composed of a surface and a compensating surface, the surface geometries of which are defined by segments of a size suitable to be defined by a tenth order x, y polynomial with Zernike coefficients.
Patent TW-476732-B (TW)
Title: L-type zeolite catalyst supporting metal and halogen components
Inventor: FUKUNAGA TETSUYA
IPC: B01J29/62
Filed: 1999-08-11
Granted: 2002-02-21
Abstract: There are herein disclosed an L-type zeolite catalyst which is obtainable by supporting a platinum component, one or more halogen components and one or more metal components selected from the group Ib of the periodic table on an L-type zeolite, the support amount of one or more metal components selected from the group Ib being in the range of 0.001 to 3% by weight based on the total weight of the catalyst in terms of the metal, a molar ration of one or more metal components selected from the group Ib/platinum being in the range of 0.01 to 1; and a method for producing aromatic hydrocarbons or a gasoline having a high octane number which comprises the step of bringing one or more fractions selected from a C6 fraction, a C7 fraction, and a C8+ fraction into contact with this catalyst. According to the present invention, there are provided a catalyst containing an L-type zeolite as a carrier which is desirable as a catalyst for the production of aromatic hydrocarbons or a gasoline having a high octane number and which can inhibit a cracking activity and the formation of coke and can improve an aromatic selectivity and a liquid yield.
Patent TW-430905-B (TW)
Title: Manufacturing method of MOS transistor
Inventor: HUANG JEI-TSEN
IPC: H01L21/336
Filed: 1999-09-15
Granted: 2001-04-21
Abstract: The present invention provides a method for manufacturing a MOS transistor on a semiconductor chip. The semiconductor chip has a surface formed thereon a silicon substrate, and a dielectric layer formed on the surface of the silicon substrate. The manufacturing method comprises: forming a gate on at least a predefined area of the dielectric layer surface, and forming a first oxide layer on the surface of the gate; performing a first ion implantation process to form two doped region on the silicon substrate surface at two sides of the gate for being used as lightly doped drain of the MOS transistor; sequentially forming a second silicon oxide layer and a sacrificial layer on the first silicon oxide layer; performing a first etching process to remove the sacrificial layer on the gate, and making the top of the gate protruded out of the remained sacrificial layer by a predefined height; performing a second etching process to remove the first and the second silicon oxide layers on the surface of the protruded portion of the gate top; completely removing the sacrificial layer, and uniformly forming a silicon nitride layer on the surface of the semiconductor chip to cover the protruded portion of the gate and the surface of the first and second silicon oxide; performing a third etching process to perpendicularly remove the silicon nitride layer on the gate, and form a spacer on the silicon nitride layer located at the peripheral of the gate; and performing a second ion implantation process to form two doped regions on the silicon substrate at the edge of the spacer for being used as source and drain of the MOS transistor thereby completing the manufacture of the MOS transistor.
Patent TW-479180-B (TW)
Title: Electronic payment mechanism
Inventor: LEE CHAO-CHIH
Filed: 1999-11-22
Granted: 2002-03-11
Abstract: This invention is a method and device of digital money transfer and transaction for electronic commerce which includes the receipt terminal, operating terminal, code check terminal, user terminal, charge terminal, structure relation and operation procedure, etc. The method integrates the payment mechanism and receipt terminal to transfer money to digital money or digital account deposit. It uses the relative password or network call execution method of reversible operation to check password legality or account remaining balance when the user proceed transaction to get and confirm the related business owner data and redirect fees to the business owner collected from users by the business owner to complete the whole transaction.
Patent TW-439211-B (TW)
Title: Method to reduce the damage resulted from the process discharging phenomena
Inventor: LEE TZUNG-HAN
IPC: H01L23/544
Filed: 1999-11-26
Granted: 2001-06-07
Abstract: The present invention is a method to reduce the damage resulted from the process discharging phenomena in integrated circuits, which comprises the following steps: first, providing a substrate and defining a plurality of crystal cell regions and cutting ways on this substrate, whereby any crystal cell region is separated from the other crystal cell regions by these cutting ways;second, forming plural basic structures in these crystal cell regions, these basic structures being located inside and on the surface of the substrate; third, forming the first dielectric layer on the substrate, the first dielectric layer being located in the plural of crystal cell regions and plural of cutting ways; fourth, forming plural contact vias on these cutting ways, the bottom of any contact via being located inside the substrate and the top of any contact via being located on the surface of the first dielectric layer; fifth, forming a conductive layer on the first dielectric layer which fills these contact vias to form plural plugs electrically coupled to the substrate; sixth, proceeding the pattern transferring procedure to the conductive layer so that the conductive layer of these crystal cell regions is not connected with the conductive layers of these cutting ways; seventh, processing the conductive layer to form plural structures in these crystal cell regions; eighth, forming the second dielectric layer on the conductive layer. Apparently, since the conductive layer is formed in the crystal cell region and the cutting ways simultaneously, and the conductive layer in the cutting ways is electrically coupled to the substrate, the function of the conductive layer is just like a lightening rod in integrated circuit process, particularly in said seventh step, which can guide the charges into the substrate to reduce the damage resulted from the discharging phenomena. In addition, when the multilevel interconnect is applied, sufficient protection can be provided to each metal layer by proceeding the third to the seventh steps of the present invention repeatedly.
Patent TW-437092-B (TW)
Title: Semiconductor device and method for making the layout thereof
Inventor: YAMAZAKI HARUJI
IPC: H01L27/02
Filed: 1999-12-30
Granted: 2001-05-28
Abstract: The present invention provides a semiconductor device to easily change the size of the protection transistor and output transistor, which comprises an N-type channel output transistor N1 and an N-type channel protection transistor N2; an N-type channel output transistor N1 having a gate GP11A surrounding the contact hole C11 formed in the drain area and contacted with the metal wire M11 connected at the OUT terminal therewith; and a gate GP12A connected with the grounding line VSS and surrounding the contact hole C12 formed in the drain area and contacted with the metal wire M12 connected with the grounding line VSS. The invention is characterized in that the pitch from the contact hole C12 to the contact hole C12 is based on the number of contact holes C11, C12 surrounding the gates GP11A, GP12A to change the size of the N-type channel output transistor N1 and the N-type channel protection transistor N2.
Patent TW-455863-B (TW)
Title: Disc drive
Inventor: IIDA MICHIHIKO
IPC: G11B19/28
Filed: 1999-12-31
Granted: 2001-09-21
Abstract: The present invention is to realize stable focus jump corresponding to the plane wobble of a disc. Focus jump is conducted after moving to the inner circumference side where plane wobble is small in the radial direction of a disc. Moreover, the focus error signal corresponding to the plane wobble is fed forward at the time of focus jump to follow the plane wobble even if focus jump occurs. Moreover, position of objective lens is held until the signal recording plane reaches the focusing position due to the plane wobble. Thereby the rotating speed of disc is controlled depending on the amount of plane wobble.
Patent TW-498193-B (TW)
Title: Method for reducing power consumption, and portable electronic device and entertainment system that employ the method
Inventor: MORITA TORU
IPC: G06F1/32
Filed: 2000-01-21
Granted: 2002-08-11
Abstract: It is an object of the present invention is to provide a method and device which can efficiently use a battery used for a portable electronic device without lowing quality of sound emission of a musical piece, an effect sound and so on. According to the present invention, in order to achieve both the longer battery life of the portable electronic device and better quality of the sound emission, an operation clock of the CPU of the portable electronic device and the processing wait time of image drawing are controlled dynamically. When there is no sound emission, the CPU is run at a low clock, and if there is a sound emission request, the CPU is switched to run at a high clock (ST7), and when the sound emission ends, the CPU is again made to run at a low clock. Since changing the CPU clock also changes the speed of the screen drawing, it is arranged so that one does not feel any apparent clock change, by making the processing wait longer if the clock is high (ST6 and ST4), and making the processing wait shorter if the clock is low.
Patent TW-454206-B (TW)
Title: Device for connecting a guide tube for the head of a pressurized-water nuclear reactor vessel
Inventor: GIL DOMINIQUE
IPC: G21C13/028
Filed: 2000-03-01
Granted: 2001-09-11
Abstract: The subject of the invention is a device for connecting to a guide tube (3) of the head of a pressurized-water nuclear reactor vessel. The guide tube (3) includes a cylindrical body (3a) passing through the head and a tube head (3b) equipped with an external screwthread (3c). The device comprises, on the one hand, a casing (20) which can be fitted onto the head (3b) of the guide tube (3) and which is equipped with means (24) of sealing with the said tube head (3b) and, on the other hand, independent means (40) of clamping the casing (20), exerting a force that presses this casing onto the head of the guide tube (3).