baber/WOPTO huggingface dataset:
Patent TW-417287-B (TW)
Title: Manufacturing method of the HSG DRAM capacitor formed upon amorphous silicon
Inventor: LIOU JI-JIN
IPC: H01L21/8242
Filed: 1998-11-18
Granted: 2001-01-01
Abstract: The present invention provides a method for manufacturing lower electrode of capacitor, including the following steps: providing a semiconductor substrate formed thereon an insulating layer; performing photolithography and etching processes to the insulating layer, so as to form contact window opening to expose the substrate; forming doped polysilicon layer in the contact window opening and on the insulating layer; forming first amorphous silicon layer over the doped polysilicon layer; performing photolithography and etching processes to the doped polysilicon silicon layer and first amorphous silicon layer to form mixed structure; forming second amorphous silicon layer over the mixed structure and insulating layer; etching second amorphous silicon layer to form gap wall on the side wall of mixed structure, and form semi-spherical grain layer over first amorphous silicon layer and along said gap wall.
Patent TW-425586-B (TW)
Title: Improved reed switch and method of making same
Inventor: SHUTES BRADLEY E
IPC: H01H11/00
Filed: 1998-11-24
Granted: 2001-03-11
Abstract: A reed switch employs contact blades which have enhanced flexibility and performance, as a result of the selective removal of material from one or more of the blades without work hardening the remaining blade material. The blades are masked and acid etched in predetermined patterns to provide either a contact region, a hinge or fulcrum region, or one or more of both. The contact region of the blade optimizes the alignment and magnetic coupling of the switch while minimizing the electrical capacitance in the space between the blades when the switch is open. The hinge or fulcrum region improves blade compliance and flexibility under an applied load. Various geometries of the contact region can be employed to improve the performance and longevity of the switch.
Patent TW-402741-B (TW)
Title: Method of producing a molybdenum nitride barrier layer for the copper process
Inventor: SUEN SHI-JUNG
IPC: C23C16/34
Filed: 1998-12-04
Granted: 2000-08-21
Abstract: This invention discloses to a method of producing a molybdenum nitride barrier layer for the copper process. The bis-diethylamino-bis-tertbutylamido molybdenum is used to produce a thin membrane of molybdenum nitride by LPCVD as the barrier layer for the following copper lines. The thin membrane of the molybdenum nitride has excellent step coverage capability, low resistance coefficient, low leakage current, and excellent temperature stability. It can prevent the copper and silicon from inter-diffusion for at least 30 minutes at the temperature as high as 550 DEG C.
Patent TW-387877-B (TW)
Title: Production of propylene
Inventor: DATH JEAN-PIERRE
IPC: B01J29/40
Filed: 1998-12-04
Granted: 2000-04-21
Abstract: A process for the production of propylene from an olefinic feedstock containing one or more olefins of C4 or greater, the process comprising contacting the olefinic feedstock with a catalyst of the MFI-type having a silicon/aluminium atomic ratio of at least about 180 to produce an effluent containing propylene, the prophlene yield on an olefin basis being from 30 to 50% based on the olefinic content of the feedstock.
Patent TW-457283-B (TW)
Title: UV-curable composition and disk and process for producing compact disk
Inventor: MURAKAMI KAZUO
IPC: G11B7/24024
Filed: 1999-05-27
Granted: 2001-10-01
Abstract: The present invention is to provide an UV-curable composition for obtaining a digital video disk which is excellent in durability and has high reliability under an atmosphere of high temperature and high humidity. It is used as adhesive for pasting two disks, having information recording layers formed by the films of different material, together. The cured coating is adjusted to have a specific conductivity of less than 100 μS/cm after immersing in water.
Patent TW-432532-B (TW)
Title: Semiconductor device and method for producing the same
Inventor: NAKAJIMA AKIO
IPC: H01L23/552
Filed: 1999-06-04
Granted: 2001-05-01
Abstract: The present invention provides a semiconductor device having multilayer interconnections including a first interconnection and a second interconnection, wherein: the second interconnection is formed to be connected to one of a ground, a positive power source and a negative power source; the second interconnection is formed either not to be electrically connected to the first interconnection or to be connected to the first interconnection in a high impedance state; and the first interconnection and the second interconnection are electrically connected to each other during or after a characteristic inspection during which the second interconnection is provided with a pad for inspecting characteristics of the semiconductor device.
Patent TW-464544-B (TW)
Title: Filtering material and device and method of its manufacture
Inventor: DUBSON ALEXANDER
IPC: B01D39/16
Filed: 1999-06-05
Granted: 2001-11-21
Abstract: A device and method for producing a porous fiber structure. One or more points of high surface curvature is produced in a liquefied polymer, such as a polymer solution or a polymer melt. The points of high surface curvature may be produced by forcing the liquefied polymer through narrow nozzles, or by wetting sharp protrusions with the liquefied polymer. The liquefied polymer is charged to a high negative electrical potential relative to a grounded moving belt. Thin jets of liquefied polymer emerge from the points of high surface curvature to impinge as fibers on the moving belt, thereby forming an unwoven fiber structure of relatively uniform porosity. A powdered aerosol is charged to a high positive electrical potential relative to the moving belt. As the belt moves past the aerosol, the aerosol particles are attracted to fill interstices in the fiber structure, thereby creating a composite filtering material.
Patent TW-440891-B (TW)
Title: Method for mounting semiconductor chip onto circuit board
Inventor: MURAYAMA KEI
IPC: H01L21/60
Filed: 1999-09-14
Granted: 2001-06-16
Abstract: To provide a process for mounting a semiconductor chip onto a circuit board, capable of adhering resin of ACF to a peripheral lateral surface of the semiconductor chip to a higher height level while avoiding the generation of voids in the inside of the resin of the ACF extending out of the periphery of the semiconductor chip. A semiconductor chip 20 is mounted onto a circuit board 10 via ACF 30 and is pressed against the circuit board 10 while heating the ACF 30 and the peripheral region thereof extending out of the periphery of the semiconductor chip 20. A frame 100 for adding a load is placed on the peripheral region of the ACF so that a gap 110 is formed between the inside surface of the frame and the lateral surface of the semiconductor chip 20, and presses the peripheral region of the ACF 30 against the circuit board 10, whereby the resin of the ACF 30 is forced into the gap 110 and adheres to the peripheral lateral surface of the semiconductor chip 20. Together therewith, gas dwelling in the inside of the peripheral region of the ACF 30 is expelled therefrom to the outer air.
Patent TW-423125-B (TW)
Title: Semiconductor device and method of producing the same
Inventor: KATOH YOSHITSUGU
IPC: H01L23/12
Filed: 1999-06-22
Granted: 2001-02-21
Abstract: A semiconductor device and a method of producing the same are provided. This semiconductor device includes: a semiconductor chip; balls which function as external connecting terminals; a substrate which electrically connects the semiconductor chip and the balls; a mold resin which seals at least a part of the semiconductor chip; and a connecting portion sealing resin which seals the connecting portion between substrate and the semiconductor chip. The semiconductor device is mounted onto a printed circuit board via the balls. The thermal expansion coefficient of the mold resin is matched with the thermal expansion coefficient of the printed circuit board. A side surface holding portion for holding the side surfaces of the semiconductor chip is formed in the mold resin to restrict thermal deformation of the semiconductor chip.
Patent TW-429586-B (TW)
Title: High-voltage power NMOS transistor combined with SCR electrostatic protection device
Inventor: LI JIAN-SHING
IPC: H01L23/60
Filed: 1999-07-14
Granted: 2001-04-11
Abstract: A high-voltage power NMOS transistor combining with SCR electrostatic protection device is formed on a first type semiconductor substrate having a second type well area, which comprises a second type drain area composed of a second type well region; a second type source area formed in the first type of semiconductor substrate; and a high voltage power gate structure formed between the second type source area and the second type drain area, in which a first type doping area is further formed in the second type well area, and therefore a first type bipolar transistor is formed by the first type doping area, the second type well area and the first type semiconductor substrate; and a second type bipolar transistor formed by the second type source area, the first type semiconductor substrate and the second type well area. The two bipolar transistors are provided to form a SCR electrostatic protection device. When an electrostatic stress is applied, the invention can provide a substrate current to conduct the SCR electrostatic protection device and further release the electrostatic stress to prevent the ESD of high voltage power transistor.
Patent TW-423132-B (TW)
Title: Bumpless flip chip package and method for fabricating
Inventor: WANG TSUNG-HSIUNG
IPC: H01L23/48
Filed: 1999-07-27
Granted: 2001-02-21
Abstract: This invention discloses the bumpless flip chip package and method for fabricating. The invention is accomplished by using the connection layer with single-layer or multi-layer structure, which has plural conduction bump-pad stages. The connection layer having the conduction bump-pad stage is thermal resist type and is with low coefficient of thermal expansion. In addition, this connection layer is composed of soft, electric-insulation polymer material that has adhesion characteristic and elastic structure. The top portion and bottom portion of this connection layer are composed of the homogeneous or heterogeneous electrically-insulated polymer material that has adhesion characteristic such that it has substantial adhesion strength for both integrated circuit chip surface and substrate surface. The connection layer is placed in between the integrated circuit chip and substrate so that the connection behavior of electric conduction is obtained by using thermal press process. This connection layer can be designed as the connection layer that has layer-added type with multi layer structure according to the input/output redistribution requirement of the integrated circuit chip and can be combined with flip chip technique to change the peripheral array package into grid point array package so as to expand the application field range. By using the bumpless flip chip package structure and fabrication process of this invention, the fabrication process can be simplified, in which the deposition process of bump on chip, the flux cleaning process and the bottom glue adding process are not required, and the utilization of material such as flux, bottom glue and so on can be eliminated such that the requirements of production cost down and reliability increase can be obtained.
Patent TW-437225-B (TW)
Title: Synchronous circuit
Inventor: HOHLER RAINER
IPC: G11C7/10
Filed: 1999-09-14
Granted: 2001-05-28
Abstract: The circuit (M) has a clock-input to transmit a 1st clock (CLKE) and a clock-generator (G) to generate a 2nd clock (CLKINT), which is phase-locked relative to said 1st clock (CLKE). The clock-output of said clock-generator (G) is connected with a control-input of a data-transfer-unit (DRV), which is used to output the data (7) from the and/or to read-in into the circuit (M) basically in synchronization with the 1st clock (CLKE). The clock-generator (G) has at least two regulation-circuit (1, 2) connected in series, which are used to regulate the phase-state of the 2nd clock (CLKINT), wherein the 1st regulation-circuit (1) is used to generate at least two middle-clocks (CLKi) from the 1st clock (CLKE), in which each has a specified phase-state relative to the 1st clock, and the 2nd regulation-circuit (2) is used to generate the 2nd clock (CLKINT) from the meddle-clocks (CLKi). The 1st regulation-circuit (1) will be de-activated during the transmission of the data through said data-transfer-unit (DRV), so that the regulation of the phase-state of the middle-clock (CLKi) can be interrupted.
Patent TW-469175-B (TW)
Title: Non-stick wok surface treatment method and wok body structure
Inventor: LI CHANG-GENG
IPC: B05D7/00
Filed: 1999-10-26
Granted: 2001-12-21
Abstract: This invention provides non-stick wok surface treatment method and wok body structure. The surface treatment and layer structure as an anode treatment layer, a ceramic layer, a ceramic titanium powder layer and a Teflon layer are formed in order on the wok body of the non-stick wok. By using such design, the non-stick characteristics of the wok can be maintained through the existence of abrasion-resistant ceramic titanium powder layer, even if the Teflon layer is scraped off. This achieves the goal of maintaining non-stick property of the wok after long time of using.
Patent TW-460793-B (TW)
Title: Computer system having an integrated core and graphic controller device capable of accessing memory data simultaneously form a system memory pool and a separate stand-alone frame buffer memory pool
Inventor: LI MING-SHIAN
IPC: G06F3/14
Filed: 1999-11-01
Granted: 2001-10-21
Abstract: A computer system includes an integrated core and graphic controller device having a core logic controller portion and a graphic controller portion, a system memory pool, and a stand-along frame buffer memory pool separate from the system memory pool. A first memory data bus interconnects the integrated core and graphic controller device and the system memory pool. A second memory data bus interconnects the integrated core and graphic controller device and the frame buffer memory pool. A memory address and control signal bus interconnects the integrated core and graphic controller device, the system memory pool and the frame buffer memory pool. The graphic controller portion of the integrated core and graphic controller device generates a same set of address signals received by the system memory pool and the frame buffer memory pool via the memory address and control signal bus such that the graphic controller portion is able to access simultaneously first word part display data from the system memory pool via the first memory data bus and second word part display data from the frame buffer memory pool via the second memory data bus.
Patent TW-493059-B (TW)
Title: Plate heat exchanger and method of making same
Inventor: MATSUMOTO SATOSHI
IPC: F28F3/08
Filed: 1999-11-17
Granted: 2002-07-01
Abstract: A plate heat exchanger includes a plurality of plates sandwiched between a pair of end plates. Each of the plurality of plates has two passageways defined therein that are not in fluid communication with each other. Alternatively, some of the plurality of plates have a passageway, while some of the remaining plates have another passageway. Two fluids flow through the two passageways in a countercurrent fashion. Because the countercurrent flows are superior in heat transfer efficiency, it is possible to enhance the performance and reduce the size of the plate heat exchangers.
Patent TW-418272-B (TW)
Title: Advancing stationary shoring system and its construction method
Inventor: JANG CHI-GUANG
IPC: E01D21/00
Filed: 2000-01-07
Granted: 2001-01-11
Abstract: This invention of advancing stationary shoring system and its construction method is mainly used in overpass or bridge construction, aims to reduce construction cost and time. This system includes followings. (1) A rail body based on the ground. (2) At least a movable device, moving on the rail body, and with at least a jack on the bottom level. The jack lifts the movable device to let it detach from the rail body while the jack at its lift-shift; and the movable device is against the rail body to move on it while the jack at its relief-shift. There are several framing supporting units set on the movable device and they are assembled by lapping on top of each other to form a supporting tower. (3) Several upper jacks are set on the side top of the supporting tower. (4) Supporting frame of base forms are set on the upper jack to allow form assembling. Moreover, the upper jack aims to adjust the slope on both X-axis and Y-axis of the supporting frame of base forms.
Patent TW-I247751-B (TW)
Title: Sulfated fucogalactan
Inventor: SAKAI TAKESHI
IPC: C12P19/00
Filed: 2000-02-23
Granted: 2006-01-21
Abstract: Sulfated fucogalactan or its salt useful as a reagent for sugar chain engineering or an HGF-production inducer; a degraded product or its salt obtained by treating the sulfated fucogalactan with a sulfated fucogalactan digesting enzyme; the sulfated fucogalactan digesting enzyme useful in sugar chain engineering; a process for producing the degraded product by treating sulfated fucogalactan or its salt with the above enzyme; and a process for producing the sulfated fucogalactan digesting enzyme.
Patent TW-449847-B (TW)
Title: Semiconductor device testing device
Inventor: OHTAKI MIKIO
IPC: G01R31/26
Filed: 2000-03-07
Granted: 2001-08-11
Abstract: A semiconductor device testing device is disclosed, which comprises a circuit board 103 and a thin film 105. A plurality of electrodes 103c are allocated in the circuit board 103, which correspond to and face the electrode 201a of the device 201 to be tested, and a bump 105b is allocated on the surface of the film 105, which corresponds to and faces the electrode 201a in the device 201 to be tested. An electrode 105c is allocated on the surface of the film 105, which corresponds to and faces the electrodes 103c in the circuit board 103. The bump 105b is formed on one side of the thin film 105, and the electrode 105c is formed on the other side of the film 105 and is electrically connected to the bump 105b via a through hole 105d, thereby being adaptable to a semiconductor device having a fine-pitch electrode to improved the durability.
Patent TW-I258464-B (TW)
Title: Flame resistant aromatic cyanate ester compounds, prepolymers thereof, and composition containing the same
Inventor: LIN BOR-SHENG
IPC: C08G73/06
Filed: 2000-03-10
Granted: 2006-07-21
Abstract: The present invention relates to novel aromatic cyanate ester compounds containing at least two rings linked by a group containing an unsaturated group. The present invention further relates to compositions and prepolymers of said novel aromatic cyanate ester compounds. The present invention further relates to a process for preparing said compounds and cured articles resulting from curable mixtures thereof.
Patent TW-444354-B (TW)
Title: Method of fabricating MOS transistor
Inventor: CHENG YAO-CHIN
IPC: H01L21/8232
Filed: 2000-03-24
Granted: 2001-07-01
Abstract: The present invention provides a method of fabricating MOS transistor on the substrate of semiconductor wafer. The method of the present invention comprises forming the gate of the MOS transistor on the surface of the substrate of the semiconductor wafer, then forming the source and drain of the MOS transistor on the substrate of both sides of the gate; then proceeding an ion implantation process to form the first, second, and third doped region of the same semiconductor type as that of source and drain on the substrate of semiconductor wafer, wherein the first doped region is located under the gate and is overlapped with the channel region of the MOS transistor, and the second and the third doped regions are located in the predetermined region under the source and drain.
Patent TW-475063-B (TW)
Title: Measurement of fluid concentrations
Inventor: THURSTON ROBERT RICHARD
IPC: F02D41/00
Filed: 2000-04-20
Granted: 2002-02-01
Abstract: An apparatus and method for determining the proportion of at least one of the components of a fluid mixture of liquid natural gas (LNG). The percentage of methane or ethane/methane ratio of the LNG is determined by measuring the thermal conductivity of the LNG at two temperatures.
Patent TW-490968-B (TW)
Title: Apparatus for encrypting data and cipher system
Inventor: HOFFMAN JEFFREY D
IPC: H04L9/06
Filed: 2000-06-08
Granted: 2002-06-11
Abstract: A cipher system having a cipher core to encrypt plaintext data into ciphertext data, and a bus interface coupled to the cipher core to transfer the ciphertext data to a bus. In one embodiment, the cipher core comprises a block assembler to receive words of data and to assemble the words into a block, an encryption function to encrypt the block based on an encryption function key, a block transmitter to receive the encrypted block and to disassemble the encrypted block into encrypted data words, and a controller to control multiple rounds of encryption by the encryption function for the block. In another embodiment, the encryption function is duplicated and the controller is replaced by two controllers, the first controller controlling the first five rounds of encryption of the block and the second controller controlling the second five rounds of encryption of the block.
Patent TW-463305-B (TW)
Title: Method for decreasing the RC delay time of conductor contact
Inventor: CHEN DIAN-HAU
IPC: H01L21/768
Filed: 2000-05-19
Granted: 2001-11-11
Abstract: The method for decreasing the RC delay time of conductor contact of the present invention comprises the basic steps of: providing a substrate; forming an organic low dielectric constant material layer on the substrate; forming a dielectric material layer on the organic low dielectric constant material layer; forming a photoresist layer on the dielectric material layer for defining a contact area; using the organic low dielectric constant material layer as an etching stop layer to perform an etching process on the dielectric material layer for thereby forming a contact in the contact area; removing the photoresist layer and filling conductor into the contact. It is obvious that the present invention is characterized in using the organic low dielectric constant material layer as the etching stop layer to decrease the RC delay time of conductor contact and dielectric material at the periphery.
Patent TW-460305-B (TW)
Title: Body weight supports and teaching aid
Inventor: EASTWOOD OWEN
IPC: A61F5/01
Filed: 2000-06-27
Granted: 2001-10-21
Abstract: The invention relates to body supports and teaching aids particular for use during skiing. Skiing to greater or to lesser degrees imposes strains on the muscles of the skier causing fatigue and encouraging a skier to adopt an incorrect stance or posture not conducive to good and correct skiing. The object of the invention is to provide a simple and effective body support and teaching aid that is effective during skiing and does not need to be removed during a temporary cessation of activity but allows substantial freedom of movement of the legs during walking and sitting. This objective is met by a construction comprising a first (upper) member adapted for location against the thigh area of the leg, a second (lower) member adapted for location against the calf area of the leg, a pivotal connection between the first and second members, the second member being connectable to the boot of a user, load bearing means located on the support to provide a resistance to pivotal movement between the first and second members, and said load bearing means being deactivatable to permit substantially free pivotal movement between the first and second members.