Patent GB-1316830-A (GB)
Title: Methods of manufacturing semiconductor devices
IPC: H01L21/762
Filed: 1970-07-02
Abstract: 1316830 Electrolytically etching semiconductors PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 2 July 1970 [4 July 1969] 32261/70 Heading C7B [Also in Division H1] In a method of manufacturing a semi-conductor device having a high-resistivity layer on a lowresistivity substrate in which the substrate is selectively removed by electrolytic etching, the spacing between a readily conductive region on the high resistively layer and the substrate is greater than the thickness of the depletion layer formed during the etching to prevent removal of the high conductivity region or the high resistivity region. The conditions for the thickness of the high resistivity layer are discussed and applied to the structures of the following embodiments. As shown, Figs.4 and 5, an N type Si substrate 41 doped with Sb is provided with a high resistivity N type epitaxial layer 42, doped with P, into which are diffused B and P by the planar technique to form P type region 45 and readily conductive N+ type region 46 respectively. The glass layers formed during diffusion are removed and conductive tracks 51, 52 (Fig.5) are applied. The upper face of the wafer is secured to a glass support by means of beeswax, the lower face is contacted by a Pt electrode held by a clamp and the device is subjected to electrolytic etching to selectively remove substrate 41, the etching stopping when layer 42 is reached. The lower part of layer 42 is then removed by chemical etching to produce the device shown in Fig.5. In a second embodiment, Figs.6 and 7 (not shown) a low resistivity N type substrate (61) is provided with consecutive epitaxial layers comprising, a high resistivity P type layer (62), a readily conductive N type layer (63) and a high resistivity N type layer (64). Transistors are formed in the top N type layer by the planar process and connections are applied. The top of the wafer is secured to a glass support with epoxy resin and the substrate 61 removed by electrolytic etching. The exposed high resistivity P type layer 62 is then removed by chemical etching and the surface of the readily conductive N type layer (63) then exposed is covered with a layer (71) of Cu by electro-deposition. Apertures are formed in the Cu layer which is then used as a mask during an anisotropic etching step using KOH and isopropanol which forms V-shaped isolation grooves between the transistors. In a further embodiment, Figs.8 and 9 (not shown), a high resistivity N type layer (82) followed by a readily conductive N- type layer (83) are epitaxially deposited on a substrate (81), grooves are etched into the epitaxial layers reaching nearly to the substrate, the surface is oxidized and a support (85) of polycrystalline Si is deposited to fill the grooves. The substrate (81) is then removed by electrolytic etching and the exposed surface of the high resistivity N type layer (82) is chemically etched to divide the epitaxial layer into pockets in each of which a transistor may be formed. The semi-conductor material may also be Ge, and the readily conductive layer may be of a metal eg Mo.