Patent GB-1143886-A (GB)
IPC: G11C15/04
Abstract: 1,143,886. Associative stores; coders. INTERNATIONAL STANDARD ELECTRIC CORP. 5 Oct., 1967 [13 Oct., 1966], No. 45394/67. Headings G4C and G4H. [Also in Division H4] A scanner which produces, as an n digit binary number or as a sequence of such numbers, the identity of a marked one or the identities of concurrently marked ones of 2 n  wires comprises a 2 n -by- 2n diode matrix (Fig. 1), complementary pairs of column wires representing logical one and logical zero for each binary digit and each such column wire being selectively switched to logical zero under control of a logic circuit (Fig. 2) so as to remove the effect of successive sets of inputs to the row wires in order to reduce the effective inputs to an unambiguously indicated one. As shown in Fig. 1, 1 out-of 8 markings on matrix row wires are converted to three digit binary codes signalled on columns of which E0<SP>1</SP>, E1<SP>1</SP>, E2<SP>1</SP> represent logical one and E0, E1, E2 represent the corresponding logical zeroes of each digit. Switches S0 S0<SP>1</SP>; S1 S1<SP>1</SP>; and S2, S2<SP>1</SP> are controlled by corresponding tri-stable circuits F0, F1, F2; the 0 states of which actuate switches S0 S1 S2; the L states of which actuate switches S0<SP>1</SP>, S1<SP>1</SP>, S2<SP>1</SP>; and the X states of which actuate neither switch of the associated set. An input to a terminal 1, 2 or 3 of a tristable sets the tri-stable in its correspondingly indicated output state. Elements Z introduce a delay equal to the time between one clock pulse and the next. The condition of the column wires is signalled to the logic circuit as indicated by terminals E0-E2<SP>1</SP>. To indicate that at least one input mark is present, one pair of complementary column leads is coupled to an OR gate to produce signal M1. To indicate that more than one input mark is present the pairs of complementary column wires are coupled to AND gates to produce signals D0, D1, D2 corresponding to each binary digit; the presence of any one of these producing signal M2. So long as M2 is present a clock pulse source T is coupled to a lead T2 which controls the tristables to blank out input marks giving rise to column marks on wires E2<SP>1</SP> ,  E1<SP>1</SP> and E0<SP>1</SP> in that order, in so far as the signals D2, D1 and D0 signal ambiguity and until none of the signals D0 to D2 exist. When this state is achieved M2 ceases and the pulse train T is diverted to lead Ti in response to which the leftmost active tri-stable is switched from its L to its 0 state while tri-stables further to the left, if such exist, are switched to neutral X state. If a second code is thus uncovered, M1 being present and M2 being absent, the process is repeated by switching to 0 the next tri-stable to the right, and so on. If during this process, with the tri-stables being set progressively to neutral X state starting from the left, ambiguity is signalled by one of the AND gate outputs D0-D3, the signal M2 reappears and the pulse train is switched back to lead T2 so as to switch the tri-stables progressively to L states starting from the right until ambiguity is removed. Read out is effected from terminals I0, I1, I2 which are the matrix column wires gated by the condition M1 present, M2 absent. When all codes have been read out, the tri-stable F2 is set to neutral and an end-of-scan signal W is produced. The arrangement may be employed to identify calling subscriber lines or to nominate a first free circuit from a number marked as free to the matrix, the scan in the latter case being halted as soon as the first unambiguous code is found. The arrangement is also said to be of use in associative stores where an interrogation results in a variable number of significant outputs, each of which requires to be identified.