baber/WOPTO huggingface dataset:
Patent JP-H09152596-A (JP)
Title: Reflection type color liquid crystal display device
Inventor: OZEKI MASAO
IPC: G02F1/133
Filed: 1996-06-07
Abstract: PROBLEM TO BE SOLVED: To generate white when no voltage is applied and red, blue, and green when intermediate voltages are applied without using any color filter. SOLUTION: This device is equipped with a polarizing plate 1 which has an axis 18 of absorption, a phase difference plate 3, a liquid crystal layer 6, and a reflecting layer 8 in order from the side where a person 20 views the display. Then the axis 18 of absorption, a 1st orientation direction 14 and a 2nd orientation angle 15, and a 1st optical anisotropy axis 16 and a 2nd optical anisotropy axis 17 are set to specific angles θ1 , θ2 , θ3 and θ4 of intersection and >=3 voltage values are multiplexed to apply a voltage from a driving circuit 10 to the liquid crystal layer 6. Consequently, a multicolored display can be made even by high-duty driving.
Patent JP-S5270708-A (JP)
Title: Reception system for reception equipment
Inventor: SUZUKI SHIGEHISA
IPC: H04B1/10
Filed: 1975-12-10
Abstract: PURPOSE:To enlarge dynamic range of reception equipment by deleting atmospheric ratio noise from reception signal after detecting the noise of reception frequency at ahort wave band.
Patent JP-H10334252-A (JP)
Title: Image processor
Inventor: NAKAYAMA MITSUTOMO
IPC: G09G5/36
Filed: 1997-06-04
Abstract: PROBLEM TO BE SOLVED: To attain the fast execution of an anti-aliasing process. SOLUTION: A sub-span start point generation circuit 6 outputs the start point X coordinates of each sub-span contained in a span which crosses a triangle area, and a sub-span end point generation circuit 7 outputs the end point X coordinates of each sub-span contained in the span. A drawing X coordinate generation circuit 10 outputs the X coordinate XD of the pixel overlapping the triangle area. A sub-span difference calculation circuit 14 calculates the effective length of each sub-span of the pixel of the coordinate XD. Then a sub-span addition circuit 15 calculates the sum total of effective length of sub- spans as an area (SQ) which overlaps the triangle area for the pixel of the coordinate XD.
Patent JP-S628558-A (JP)
Title: Semiconductor integrated circuit device
Inventor: SHIBATA TAKASHI
IPC: H01L21/8246
Filed: 1985-07-05
Abstract: PURPOSE:To make it possible to write data after data-line forming processes and to shorten process completing time, by extending the data lines, which are connected to memory cell rows, to the outside of the upper parts of the channel forming region of an MISFET, in a logitudinal mask ROM. CONSTITUTION:Conductor layers 10A and 10B are electrically connected to specified semiconductor regions 7 and 8 through a connecting hole 9A. The upper part of an insulating film 9 is extended to the direction of rows. Data lines are extended to the outside of the upper parts of the channel forming regions of memory cells Q1-Q8. After the forming processes of the memory cells Q1-Q8 and the data lines DLs, n-type impurity ions are introduced in the channel forming region 2 through gate electrode 6A by ion implantation technology. Thus the first threshold voltage is converted into the second threshold voltage. After the forming processes of the data lines DLs, the data is written.
Patent JP-H09300895-A (JP)
Title: Molding utilizing light storing and fluorescent material and manufacture thereof
Inventor: SUGIYAMA YOSHITAKA
IPC: B44C5/08
Filed: 1996-05-15
Abstract: PROBLEM TO BE SOLVED: To make it possible to increase the ornamental effect of a monument, an object or the like. SOLUTION: The base of a molding is formed in the form of a plastic molding article, a ceramic ware or the like. A powdered light storing material 6 or fluorescent material is mixed with a volatile solution 7 at the step S1. The resultant solution is atomized with an air gun or the like and spray-applied to the surface of the molding at the step S2. When the application portion of the molding is limited, the portion, at which no application is necessary, is taped or the like. After the surface of the molding is dried, clear lacquer 8 is atomized with an air gun or the like so as to spray-applied to the top surface of the molding at the step S3.
Patent JP-S5849138-A (JP)
Inventor: SUZUKI TATSUO
IPC: A61M25/00
Filed: 1981-09-17
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S634714-A (JP)
Title: Semiconductor integrated circuit device
Inventor: KURAISHI TAKASHI
IPC: H03K19/086
Filed: 1986-06-25
Abstract: PURPOSE:To decrease number of components and also power consumption remarkably by providing a current mirror circuit using a current flowing directly from a power supply via an impedance element as a mapping input and using a mapping output of the said circuit so as to give a common emitter current of an ECL gate circuit section formed to an internal circuit section of a semiconductor integrated circuit device. CONSTITUTION:The current mirror circuit 2 taking a current flowing directly from a power supply Vcc-VEE as an image input via an impedance element, i.e., a series circuit comprising resistors R13, R12 is constituted to give a common emitter current. Then a common emitter current for a differential bipolar transistor pair (Q1A, Q1B and Q2) being a component of an ECL gate circuit section G1 is given by an image output of the current mirror circuit 2. Thus, number of components required to make the common emitter current of the ECL gate circuit section constant is reduced remarkably and the power consumption is reduced.
Patent JP-H07337007-A (JP)
Title: Dc voltage supply circuit
Inventor: FURUKAWA KOJI
IPC: H02M3/28
Filed: 1994-06-07
Abstract: PURPOSE:To realize a DC voltage supply circuit having high power efficiency by detecting the load current flowing through an output terminal and controlling the current flowing through a bleeder circuit based on the load current value. CONSTITUTION:Under no-load or when the load is extremely light, a current larger than a prescribed level does not flow through a resistor R4. Consequently, a transistor TR1 is turned ON and a current flows through a bleeder resistor circuit R1 connected between the output terminals thus stabilizing the operation of a switching circuit. When the load current begins to flow, a potential corresponding to the quantity of current appears across the resistor R4. The potential is amplified through an operational amplifier IC1 and the base potential of the transistor TR1 is increased. When the current value of the bleeder resitstor R1 decreases and the load current exceeds the prescribed level, the transistor TR1 is turned OFF and a current does not flow through the bleeder resistor R1. This circuitry realizes a DC voltage supply circuit having high current efficiency.
Patent JP-H09330970-A (JP)
Title: Manufacture of semiconductor element
Inventor: SHIMODA ATSUSHI
IPC: G06F19/00
Filed: 1996-06-10
Abstract: PROBLEM TO BE SOLVED: To calculate the rate of participation to a reduction in the yield of a wafer of quality data in each process and enable judgement of an abnormality in the processes by a method wherein a presently advancing process step and quality information on a product are processed by using a stored yield-reduction participation rate and a detected quality data, and the quality information is utilized. SOLUTION: Quality data is detected by an inspection device 3 in each process of performing a treatment about the whole or one part of the same wafer by manufacturing devices 1. With the detected quality data stored in a storage means 4, the quality data is fed to a failure analysis part 7. The quality data stored in the means 4 and inspection data detected by an inspection of the yield of the same wafer are processed in a yield-reduction participation rate calculating part 5 and the participation rate of a defect in the wafer to a reduction in the yield of the wafer in each treatment process is calculated. A presently advancing process step in the analysis means 7 and quality information on a product are processed by using the calculated participation rate and the quality data detected by the device 3 and the yield of the product is estimated.
Patent JP-S5937735-A (JP)
Title: Key input device
Inventor: KANBE YUKIHIKO
IPC: H03K17/94
Filed: 1982-08-25
Abstract: PURPOSE:To perform an accurate key input decision, by setting a reference level higher or lower than the high/low decision level of the 1st OR circuit according to whether the signal processing of two key matrix circuits is based upon negative or positive logic. CONSTITUTION:The key matrix circuits 11 and 12 connect with respective longitudinal lines l10-l17 and l31-l47; a key scanning signal KS outputted by a key scanning counter 13 is supplied to a decoder 14, which supplies a step signal to each lateral lines l20-l27 and l40-l47 to specify lines. Then, the corresponding lateral lines l20-l27 and l40-l47 of the circuits 11 and 12 are coupled mutually and their outputs are sent to two-input OR gates 151-158 forming the 1st OR circuit. Thus, key return signals R0-R7 are obtained from gates 151-158. For example, if the longitudinal and lateral lines l10 and l40 drop in level when a key contact K65 is made, a key return signal is outputted from the gate 151 and a comparator 161 outputs a shift signal SO.
Patent JP-S5936598-A (JP)
Title: Biological treatment of waste water containing organic material
Inventor: UCHIMIZU MAMORU
IPC: C02F3/30
Filed: 1982-08-24
Abstract: PURPOSE:To activate the bacteria in the waste water in an anaeration tank and an aeration tank by maintaining the state of anaerobic sludge by the aeration suited for activation of anaerobic bacteria in the anaeration tank and mixing and aerating the anaerobic sludge and the aerobic sludge in the aeration tank. CONSTITUTION:Waste water is stagnated for the purpose of making liquid nature uniform in a control tank 1 and is then supplied continuously to an anaeration tank 2. The waste water in the tank 2 is aerated by the air from a fan 5 to activate facultative anaerobic bacteria and the state wherein the anaerobic sludge activated therein with the anaerobic bacteria live is maintained. The anaerobic sludge supplied from the tank 2 and the anaerobic sludge contg. zooglea bacteria returned from a settling sepn. tank 4 are mixed and charged into an aeration tank 3 and the mixture is aerated by the air from the fan 5. The settled aerobic sludge in the tank 4 is returned by a sludge pump 10 to the tank 3 and the supernatant liquid is released as treated water.
Patent JP-S58161984-A (JP)
Inventor: MATSUI KENICHI
IPC: C04B41/63
Filed: 1981-09-17
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S5773281-A (JP)
Title: Equipment drain device
Inventor: AKAI TOSHIHARU
IPC: F16K31/70
Filed: 1980-10-20
Abstract: PURPOSE: To open or close a valve without noise of an electromagnet by employing a shape-memorizing alloy for the drain mechanism of a washing machine, etc.  
     CONSTITUTION: A shape-memorizing alloy 20 has its one end fixed to a metal part 19 and another end to fixed body 21. When water level reaches a certain level, water supply is stopped and current supplied to the timer motor making the washer motor 5 rotate to start washing. Upon completion of washing, the contact point to closes to the drain valve side and the valve body 14 is pulled to accomplish drainage. Details are that the shape-memorizing alloy 20 and a heater are provided at the side of drain valve, and at the time of draininage, heat of the heater makes the shape- memorizing alloy 20 change its shape to the dotted line 20' changes its shape to the dotted line 20' pulling the valve body 14 against a spring 14, and openes the valve. After a certain period of time, the heater stops, the shape-memorizing alloy is cooled losing its shape holding power and the valve is closed. 
     COPYRIGHT: (C)1982,JPO&Japio
Patent JP-H09330117-A (JP)
Title: Batch plant control system
Inventor: SHIMADA CHIAKI
IPC: G06Q50/00
Filed: 1996-06-10
Abstract: PROBLEM TO BE SOLVED: To provide the batch plant control system which can easily analyze processes of manufacturing products by brands and control the quality of the products by the brands. SOLUTION: A data gathering means 23 gathers various time-series data present in a batch plant PLT during the execution of batch processing. A data storage means 25 saves various gathered timeseries data in the memory 24 together in batch units. Further, the memory 24 stores batch trend files provided by batches. The batch trend files are given identifiers. The data storage means 25 saves time-series data, gathered by the same batch, in the same batch trend file.
Patent JP-H05338319-A (JP)
Title: Recorder
Inventor: ASANO SHINYA
IPC: B41J29/00
Filed: 1992-06-08
Abstract: PURPOSE:To prevent inconveniences of an injury or the like in change of an ink ribbon from occurring by a method wherein a thin earth sheet of which a longitudinal fringe part has a wavy form is laminated on one face of a flat cable which sends an electric signal to a carriage. CONSTITUTION:By superimposing a thin metallic earth sheet 4 on a flat cable connecting a carriage to a substrate on which a driver or the like are provided to a bottom surface of a printer, a recorder is protected from statistic electricity of the flat cable and a noise, and disconnection by buckling or the like in use is prevented. Further, a longitudinal fringe part of the earth sheet is formed wave and thereby hands are prevented from being injured in assembly and in change of an ink ribbon cassette. Furthermore, a form wherein a curved part is connected to a straight line part may be also used as the fringe part form.
Patent JP-S633305-A (JP)
Title: Method for correcting action control point of industrial robot
Inventor: KAMETANI YASUHIRO
IPC: B25J9/10
Filed: 1986-06-24
Abstract: PURPOSE:To obtain the highly accurate correction value from a simple numerical formula by performing the positioning job of an industrial robot by means of a positioning tool for control point. CONSTITUTION:An optional reference point P is decided by a tool, etc., and only a J1 axis 7 and a W axis 9 are moved to secure the coincidence between a work point 4 and the point P. Then the values approx.=1 and W1 of both axis 7 and 9 are read out. The robot arm positions are moved symmetrically to secure again the coincidence between the point 4 and the point P. Then the values approx.=2 and W2 of both points 4 and P. The value  theta is obtained and given to a controller as a compensation constant together with  l for calculation of correction. Thus a work point 10 can be shifted directly to a shown point.
Patent JP-S5670066-A (JP)
Title: Quickly curable coating composition for resistive element
Inventor: OKUYA TAKESHI
IPC: C09D5/24
Filed: 1979-11-14
Abstract: PURPOSE: The titled composition curable in a short time by light irradiation, forming a stabilized resistive element, comprising a radically crosslinkable resin composition, carbon powder, benzyl dimethyl ketal as a polymerization initiator in a specific ratio.  
     CONSTITUTION: (A) 25W90wt% resin composition comprising a radically crosslinkable prepolymer, e.g., epoxy acrylate, etc. and vinyl monomer, e.g., 2-hydroxyethyl acrylate, etc. is blended with (B) 5W70wt% carbon powder, e.g., graphite, etc. and (C) 0.1W10wt% 2,2-dimethoxy-2-phenylacetophenone (another name: benxyl dimethyl ketal) as a polymerization initiator to give the desired composition. 
     COPYRIGHT: (C)1981,JPO&Japio
Patent JP-H075101-A (JP)
Title: Absorptiometric system for light scattering medium
Inventor: MIYAGAWA ICHIRO
IPC: G01N21/17
Filed: 1993-06-18
Abstract: PURPOSE:To provide an absorptiometric system for light scattering medium in which the absorptiometric information of the medium can be obtained with high S/N by separating the light transmitted directly through the medium from the scattered light. CONSTITUTION:An optical path difference controller 37, a piezoelectric element 32 for sweeping the frequency of a light a4 traveling on an optical path B temporally according to a saw-tooth wave, and a saw-tooth wave generating circuit 33 for driving the piezoelectric element 32 are disposed on one B of two optical paths A, B having substantially identical length on which two synchronized SLD lights a3, a4 having same frequency travel. The light a3 traveling on the optical path A impinges on a light scattering medium 10 and the light a10 transmitting straightly through the medium 10 along a shortest path interferes with a frequency sweeped light a5 along with a cross-talk light a21 passes through the medium 10 along a path of excess length. The interfering light a5 exhibits different frequency between the straightly transmitted light a10 and the cross-talk light a21, and then the difference is detected.
Patent JP-H0311742-A (JP)
Title: Manufacture of semiconductor device
Inventor: NAGASE YOJI
IPC: H01L29/73
Filed: 1989-06-09
Abstract: PURPOSE:To lessen the number of processes by a method wherein the surface of a semiconductor substrate consisting of some one of laminated wafers is shaved off so as to leave a necessary thickness at the bonding part of the substrate with an intrinsic base and a single crystal is buried in a hole formed by anisotropic etching. CONSTITUTION:A P-type single crystal substrate 3 is prepared, oxide layers 2 and 4 are arranged so as to come into contact with each other and an electrostatic contact bonding is performed. Then, a hole, which passes through the layers 2 and 4 and reaches the P-type Si substrate 3, is opened by anisotropic etching and this hole is filled with a single crystal Si film 5 by an epitaxial growth. The silicon film 5 deposited on a place other than this hole is removed. An emitter window is opened in an oxide layer 11 by anisotropic etching. An oxide layer 21 is etched to form an emitter diffusion window. A polycrystalline silicon film 22 is deposited in the vicinity of this window, an annealing is performed to form a P-N-P transistor and an N-type emitter diffused region 9, a P-type diffused region 10 and a collector contact compensation diffused region 8 are simultaneously formed. Thereby, a bipolar transistor structure can be manufactured in a process of the number of few processes.
Patent JP-S628005-A (JP)
Title: Apparatus for measuring thickness of film
Inventor: IDA YOSHIAKI
IPC: G01B11/06
Filed: 1985-07-03
Abstract: PURPOSE:To make it possible to measure the thickness of a film to be measured even if the position of said film changes, by obtaining the signal having the value proportional to the thickness of the film to be measured. CONSTITUTION:When a light source 2 is driven, the light emitted from the light source 2 is condensed by a condensing lens 3 and transmits through a magnetic tape 1 being a film to be measured. The light transmitted through the tape 1 is branched by a spectroscope 4 and both lights respectively pass narrow band-pass filters 5, 6 having different wavelength bands to form first and second lights which, in turn, respectively receive photoelectric conversion by light receivers 7, 8, to obtain signals A, B corresponding to the first and second lights. Hereupon, the light transmitting characteristic of the coating film 1b of the tape 1 shows wavelength dependency and a transmission start wavelength is different while the variation in the luminous intensity of the light source 2 is same in the transmission start wavelength and the inclination thereof is different. Therefore, the output signals A, B of the light receivers 7, 8 are respectively amplified by AC amplifiers 9, 10 and the outputs of the AC amplifier 9, 10 are operated by a divider 13 and, when the ratio of the signals A, B is detected, change is generated when the transmission start wavelength moved. By this method, the output proportional to the thickness of the coating film 1b is obtained.
Patent JP-S5849966-A (JP)
Title: Driver of exposure lamp cooling fan
Inventor: FUKUDA HARUHIKO
IPC: G03G15/04
Filed: 1981-09-18
Abstract: PURPOSE:To reduce noises and power consumption through a simple structure, by driving a cooling fan by application of voltage fed to an exposure lamp. CONSTITUTION:A cooling fan is connected in parallel to an exposure lamp 1. When a power supply switch 3 is closed, an exposure lamp input controlling circuit 2 applies input voltage to the lamp 1 during copying operation. This input voltage is controlled by the operation part of a copying machine in accordance with the set value of density of a copy image. The fan 6 is driven by the same voltage as that of the lamp 1 to cool the lamp 1, etc. The input voltage of the lamp 1 is optionally set manually with density controlling buttons installed in the operation part, thus permitting the cooling fan to require no controller of fan drive in accordance with temp., etc., and to be able to blow the amount of air corresponding to the light intensity, that is, the amount of heat generated by the lamp 1 through a simple structure, noises and power consumption to be reduced, and cooling efficiency to be raised.
Patent JP-H11340280-A (JP)
Title: Mounting method for semiconductor ic
Inventor: KAWABATA MICHIHITO
IPC: H01L23/28
Filed: 1998-05-28
Abstract: PROBLEM TO BE SOLVED: To perform highly reliable electric connection by a conductive adhesive material and to improve productivity, in the mounting method of a semiconductor, IC for connecting the bump of a semiconductor IC chip and the electrode terminal of a wiring board by the conductive adhesive material, filling sealing resin in the clearance part of the semiconductor IC chip and the wiring board, and fixing both. SOLUTION: As the conductive adhesive material 13, the adhesive material of small compatibility to the sealing resin 15 is used. The bump 2 of the semiconductor IC chip 1 supplied with the conductive adhesive material 13 is positioned and brought into contact with the electrode terminal 6 of the wiring board 4, then the sealing resin 15 is filled in the clearance part of the semiconductor IC chip 1 and the wiring board 4 and then, the conductive adhesive material 13 and the sealing resin 15 are simultaneously hardened. Since the conductive adhesive material 13 of the small compatibility is used, it is hardly mixed with the sealing resin 15.
Patent JP-H076269-A (JP)
Title: Electronic cash register
Inventor: SAKAGUCHI YUKIO
IPC: G07G1/12
Filed: 1993-06-18
Abstract: PURPOSE:To prevent revision of data and to allow the user to easily recognize the occurrence of an area not revised even when a data revision command comes from a host computer by setting a range of inhibiting data revision in a memory in advance. CONSTITUTION:Start address and end address data in an area in which data revision in a data memory 4 is inhibited are entered from a key board 1 by a predetermined key operation prior to data communication and set in an area of the data memory 4. when a data revision command comes from a host computer and the transmission data are data whose write is in a range of addresses in which write is inhibited, the data are not rewritten but start address and end address data not written are stored in the area of the memory 4. Then a control circuit 2 reads the address data not written to control a printer 6 for print and informs a range in which data are not revised to the user.
Patent JP-S623340-A (JP)
Title: Branching system
Inventor: RUBII BEIRUU RII
IPC: G06F9/38
Filed: 1986-06-24
Abstract: PURPOSE:To minimize a branch range by deciding the execution of an instruction in a delay slot according to the branching direction of a computer of a pipeline system. CONSTITUTION:The ON/OFF state of a cancel bit is checked in the first step 201. Then a delay slot instruction is always executed as long as the cancel bit is kept in an OFF state. While it is checked whether or not the branch is carried out n the next step 202 when the cancel bit is kept in an ON state. If the branch is carried out and the branch displacement is negative or no branch is carried out and the branch displacement is positive, the delay slot instruction is executed. Otherwise the delay slot instruction is cancelled.