Patent GB-1130401-A (GB)
Title: Digital communications systems
Inventor: DUERDOTH WINSTON THEODORE
IPC: H04J3/06
Filed: 1965-08-17
Abstract: 1,130,401. Multiplex pulse code signalling. HER MAJESTY'S POSTMASTER GENERAL. 17 Aug., 1966 [17 Aug., 1965], No. 35203/65. Heading H4L. In a time division multiplex digital communication system, e.g. a P.C.M. telephone system wherein means are provided for inter-connecting a plurality of exchanges and compensating for variations in pulse timing, each exchange has a master timing oscillator whose frequency is adjustable by control signals, digit storage means under control of the master oscillator and incoming digits to absorb differences between incoming and local digit timing and means responsive to the contents of the storage means approaching the full and empty conditions temporarily to apply, respectively, a frequency increasing or frequency decreasing signal to a control circuit of the master oscillator and to transmit in an outgoing channel a frequency decreasing or frequency increasing control signal respectively and means for receiving from an incoming channel a frequency increasing or frequency decreasing control signal and for applying this signal to adjust the frequency of the master oscillator, the control circuit being effective to adjust the frequency of the master oscillator only when one or more control signals of one sense are received in the absence of a control signal of the opposite sense. Exchange equipment.-Each exchange has equipment E, Fig. 2, common to all the links connected to that exchange, and line equipment EL individual to each link connected to it. A 24-channel system is described using an 8-digit code, the eight digits forming a time slot, and the 24 slot periods including one synchronizing slot. In the synchronizing time slot six digits are used for the sync. signal and two digit periods are used for controlling the frequency of the exchange master oscillator EO over advance or retard terminals ECA or ECR, respectively. Oscillator EO through a pulse generator EPG defines the digit periods tl to t8 and the 24- channel slots including the synchronizing slot. A switching network ESW switches transmissions to the outgoing line LA of a link L and via line equipment EL to the incoming line LB. An oscillator LCO is locked to the P.R.F. of the incoming digits and via a filter EF applies a locking control to the oscillator EO which operates in conjunction with a further control signal applied via a logic circuit ECL. Incoming digits on line LB are written into a variable delay network store LDN under the control of pulse generator LPG which generates pulses p<SP>1</SP> to p8 at the incoming digit frequency and is synchronized by unit LCU which is responsive to the synchronizing signal. The amount of delay inserted by LDN is determined by a comparison at LCOM of the pulses from local generator EPG and pulses from generator LPG controlled by the incoming pulses. The digits written into store LDN are subsequently read out under the control of local generator EPG and fed to the switching network ESW. A detector LDET detects when the store LDN is adjacent to the empty or adjacent to the full condition and provides control signals on lines LD1 or LD2 respectively, an output on LD1 being applied via terminal ECR to decrease the frequency of oscillator EO and an output on LD2 via terminal ECA increasing the frequency of oscillator EO. The outputs on LD1 and LD2 are also supplied to a network LFC1 which generates digital frequency control signals in the two vacant digit periods of the sync. time slot. A binary code 10 is generated in response to a signal on lead LD1 and 01 represents a signal on lead LD2, these coded signals being fed to the outgoing line LA to control the remote exchange oscillator. Similar information on the incoming line LB is selected at LFC2, the code 10 providing an output on lead A controlling oscillator EO via terminal ECR, and code 01 providing an output on lead R2 controlling the oscillator via terminal ECA. If control signals should exist on terminals ECR and ECA at the same time the logic unit ECL is arranged to provide no output. Pulses t<SP>1</SP> 1  to t<SP>1</SP> 8  are supplied by generator EPG to reset the store LDN. A frequency advancing or frequency retarding signal could be transmitted continuously due to a failure at an exchange thus preventing normal operation of the network and this may be avoided by arranging that a control signal persisting for longer than a predetermined time is disconnected.