Patent GB-1524046-A (GB)
Title: Beam repositioning circuit for a cathode ray tube calligraphic display system
IPC: G09G1/04
Filed: 1975-09-09
Abstract: 1524046 Cathode-ray-tube displays GENERAL ELECTRIC CO 9 Sept 1975 [19 Sept 1974] 37018/75 Heading H4T The invention is concerned with cathode-raytube calligraphic display systems (i.e. systems in which the beam is deflected to trace symbols) and is particularly directed to positioning or re-positioning the beam at the point on the tube screen at which the (next) symbol is to be displayed in a time period which is dependent only on the amount of movement necessary for such re-positioning plus a short additional fixed period to allow the beam to settle at such re-positioned point. As shown in Fig. 1, symbol write data for the X and Y co-ordinate deflections are supplied to respective D/A converters 14, 15 the outputs of which are supplied to respective integrating circuits 16, 18 and 17, 19 producing deflection ramp voltage outputs for application via respective summers 25, 26 and deflection amplifiers 20, 21 to the horizontal and vertical deflection coils 12, 13. When the beam is to be (re)positioned the (new) position data is supplied to respective X-Y D/A converters 23, 24 the respective outputs of which, comprising step waveforms, are supplied to the summers 25, 26. The resulting current in the deflection coils 12, 13 is "sensed" by resistors 31,32 the voltages developed across which are differentiated by respective circuits 34, 35 producing respective voltages proportional to the rate of change of the deflection current. The latter voltages are converted to rectangular form by high-gain switching amplifiers 37, 38 and supplied as respective input to an OR gate 39 the output of which is employed to control a logic gate 40. Simultaneously with the supply of the (new) position data to D/A converters 23, 24 a reset pulse is applied to the rest input 59 of a counter 42 which is reset to zero count and resets a flip-flop 56 and the occurrence of a logic "one" at the output of OR gate 39 causes logic gate 40 to hold the counter in the non-counting (zero) state. This results in a timer output on line 44 which removes previously applied disabling signals via line 55 from an AND gate 47 through which clock pulse are supplied to the counter 42 (now held at zero count), and from an integrator blanking switch 45. The output of the latter operates to blank the beam (so that the repositioning trace is not visible) and to short-circuit the integrators by rendering respective transistors 22, 23 conductive (to prevent the generation of "write" ramp voltages). When the re-positioning current stops "slewing", the logic "one" input to OR gate 39 is replaced by a logic "zero" causing the logic gate 40 to allow counter 42 to commence counting. If there is no overshoot or undershoot of the beams no further output is produced by the networks 34, 35 and the logic level input to logic gate 40 remains at logic "zero". Counter 42 therefore continues to count and at a first predetermined count the output on leads 51, 52 operate via the timer 43 to produce a signal which resets flipflop 56 which via lead 57 inhibits logic gate 40 and prevents response to any further logic level inputs from OR gate 39. Counter 42 then reaches a second predetermined count representing a time sufficient to permit the beam to settle at the desired position. At the end of this count outputs on leads 49, 50 operate via the timer 43 over lead 44 to disable the integrator blanking switch 45 and over lead 55 to inhibit gate 47 and so prevent clock pulses from reaching counter 42. If the beam overshoots or undershoots (e.g. if the yoke is not critically damped) the differentiating circuits 34, 35 will respond and the logic output of OR gate 39 will change from logic "one" to logic "zero" and then back to logic "one". If this occurs within the duration of the first predetermined count, counter 42 will be reset to zero and this operation will continue until the beam has been repositioned and the output of OR gate 39 has remained at the logic "zero" level for the duration of the first predetermined count. The complete operation is described with reference to waveform diagrams Figs. (2a) to (2f) none shown.