Patent GB-991267-A (GB)
Title: Hermetically sealed semiconductor devices
IPC: H01L23/488
Filed: 1963-04-09
Abstract: 991,267. Semi-conductor devices. UNITED AIRCRAFT CORPORATION. April 9, 1963 [April 10, 1962], No. 14100/63. Heading H1K. A method of hermetically sealing a face of an integrated circuit device comprises joining an impervious encapsulating membrane to the face of the device, connections to the circuit being made by hermetically sealed conductive paths through the membrane. As shown, Fig. 27, a silicon wafer 92, provided with an oxide layer and having an integrated circuit diffused into one face, is encapsulated by applying a membrane 90 of high resistivity silicon, which may have a surface layer of silicon oxide and is provided with conductive paths 100, 102, to the diffused surface, and welding the membrane to the wafer, as at 94, by electron beam welding in vacuo. The conductive paths 100, 102 are joined to contacts 96, 98, alloyed to the circuit, by heating with an electron beam 104. The membrane can also be bonded to the wafer using an intermediate member of, for example, gold, indium, gallium, tin, lead, chromium, aluminium or other elements and alloys thereof from Group II, III, V, VI or VIII, which is fused to both the membrane and the wafer by electron beam welding, or is bonded to the membrane by other methods prior to joining to the wafer. Several wafers can be joined to a single membrane and an electron beam may be used to penetrate the membrane to form the fusion bonds. The membrane may be of glass, fused quartz, ceramic such as high density alumina or beryllium oxide, or a high resistivity semi-conductor material such as silicon. The hermetically sealed conductive paths through the membrane are formed by drilling a hole using an electron beam, placing the membrane on a refractory block, filling the hole with metal powder or a metal wire, and heating with an electron beam to fuse the metal which is then allowed to cool. The paths may also be made by placing the membrane on a refractory block having wells containing a material such as indium. A hole is then drilled through the membrane with an electron beam and the indium is melted and rises up the hole by the combined effects of thermal expansion and capillary action. The paths may also be formed by vacuum depositing a dot of material on the surface of the membrane and heating with an electron beam to cause localized diffusion of the material through the membrane, and then applying contact pads to the ends of the path. In the case of a complex metal oxide membrane, which may be a ceramic such as Al 2 O 3 , the paths may be formed by heating with an electron beam while playing a gas, such as H 2 , on the surface. This produces local decomposition of the membrane to form a conductive mixture of ceramic and metal. Contact pads are then vacuum deposited or plated on the ends of the path to provide ohmic contacts. When electron beam welding is used to join the membrane to the wafer the conductive paths may be formed by drilling holes in the membrane and metallizing the surface of the holes by deposition of titanium hydride. The membrane is then welded to the wafer and a ball of material, such as indium, gallium, gold, tin, lead, antimony and alloys of these and other elements from Group II, III, V, VI and VIII, is dropped into the hole and melted with an electron beam to form a hermetically sealed contact between the contact on the wafer and the metallized wall of the hole. The conductive paths may be formed by diffusion through the membrane after it has been welded to the wafer and may also be arranged to contact conductive tracks deposited on the lower surface of the membrane. Conductors and other passive elements may be deposited on the outer face of the membrane to reduce stray capacitances. Connections at the edge of the wafer between a conductive track deposited on the oxide surface of the wafer and a conductor deposited on the underside of the membrane may be made by forming a fusion zone, a degenerative region being provided at that point to provide a back-biased junction to insulate the connection from the bulk of the wafer. As shown, Fig. 1, a planar integrated circuit is formed by double diffusing a P-type silicon wafer provided with an epitaxial oxide layer using a photo-resist method to etch the oxide, and alloying on ohmic contacts. All the junctions emerge at the upper surface of the wafer and this face is encapsulated as described above. Fig. 2 shows the equivalent circuit of the device.