Patent GB-840548-A (GB)
Title: Digital counter
IPC: H03K23/76
Filed: 1956-05-18
Abstract: 840,548. Parametrically-excited resonators. GOTO, E. May 18, 1956 [May 21, 1955; Aug. 31, 1955], No. 15650/56. Class 40 (9). [Also in Group XIX] Parametrons, described in Specification 778,883, are used in counting circuits. Pulses of alternating current in a characteristic phase 1, representing the digit 1, can be added to or subtracted from the total registered. Simultaneously, separate trains of pulses on two input leads may be respectively added to and subtracted from the sum registered. Symbols used.-An OR element for phase 1 signals, Fig. 2 (c), consists of a parametron with three control leads 4a, 4b and a third lead, not shown, which is marked with a phase 1 signal denoted by +. An AND element, Fig. 2 (d), consists of a similar parametron with a phase 0 marking denoted by - . An element may be an AND element or an OR element according to the nature of a control x, Fig. 2 (f ). Storing signals.-A storage unit comprises a ring of three parametrons 100, 200, 300, Fig. 4, excited respectively in three overlapping phases I, II, III, Fig. 3. A signal entered at terminal 6 circulates in the ring. Counting, Fig. 10.-A counter counting on a scale of 32 comprises five storage rings 1112- 1141 to 1123-1162, six coupling parametrons 1132 to 1143 and one other parametron 1131. Normally all the storage rings are set to 0. Considering the first ring, a first 1 signal from A is entered into the ring and coupling 1132 is unaffected. A second 1 signal from A is entered into the second ring by coupling 1132 (an AND element) and 0 is entered into the first ring by a NOT operation on AND element 1171. Thus coupling 1132 transmits a 1 signal for every two 1 signals from A and couplings 1133 to 1143 likewise transmit one signal respectively for 2<SP>2</SP> to 2<SP>5</SP> signals from A. When a signal appears on terminal Q after 32 signals on A, the counter returns to normal. Reversible counting, Fig. 7.-A reversible counter counting in a scale of 64 comprises a simple parametron 7133, six coupling parametrons 721, 732, 743, 761, 772 and 783, six storage rings and a control circuit with terminals R, S and control leads α, # . . . # and α, # . . . #. When a 1 signal is applied to the reset terminal R and 0 signals to terminals S and A, all the storage rings are set to 0. With 0 signals on both terminals R, S, the α, # . . . # elements become AND elements, the #α, ## . . . ## elements become OR elements and 1 signals on lead A are counted as in Fig. 10. With 0 signals on terminals A, R, 1 signals on terminal S are subtracted from the number registered. During a 1 signal on S, the α,# . . .# elements become OR elements and the #α, ## . . . ## elements become AND elements. Tetral counters. Fig. 11.-Two binary storage rings can be combined to form a tetral counter. A reversible counter uses tetral counters L, M, N to count in the mode of 43. A parametron such as 1241 with a reference 2α has a control current of double the normal intensity on lead α. A parametron such as 1231 with a double line input has an input with double th e normal intensity. The first ring 1211-1223 responds to the first 1 signal as before. The second ring 1231-1233 responds to the second digit and remains set to 1 when the first ring is again set to 1 by the third 1 signal. The fourth 1 signal is transmitted by 1241. Thus parametron 1241 gives one signal for every four signals from A, and parametron 1293 gives one signal for every 64 signals from A. Other counters.-A counter transmitting one signal for every three signals on A, Fig. 12, comprises two storage rings which would normally transmit a 1 signal from Q after 4 signals from A. A signal from Q, however, enters 1 into the first ring so that each count starts with 1(01) already registered. After two signals 3(11) is registered and the third signal produces a signal from Q which resets the counter to 1(01). A quinary counter, Fig. 13(a) comprises three storage rings and would normally transmit a signal from Q after 8 signals on A. A signal on A, however, enters 1 into the first and second rings so that each count starts with the number 3 (011) already stored. After 4 signals on A, the counter registers 7(111) and the fifth signal produces a signal at Q and resets the counter to 3(011). In another quinary counter, Fig. 13b, the counter starts at 0(000) and gives a signal at Q when it counts to 5(101). AND element 1431 then has a 1 signal on both input leads. In a third quinary counter, Fig. 13c, the counter starts at 1(001) and gives a signal at Q when it counts to 6(110). In a fourth quinary counter, Fig. 13d, the counter starts at 3(011) and gives a signal at Q when it counts to 8. The Specification describes similar counters counting in the modes of 6, 7, 10, 11, 17, 57. A decimal counter, for example, may comprise a binary counter followed by a quinary counter.