Patent GB-1192241-A (GB)
Title: Improved Systems or Converters for Measuring Analog Signals.
IPC: H03M1/00
Filed: 1967-05-09
Abstract: 1,192,241. A/D converters. RELIANCE ELECTRIC & ENG. CO. 9 May, 1967 [15 June, 1966], No. 21444/67. Heading G4H. Unwanted signals e.g. noise are removed from the output of load cells 20 before measurement, by means of a feedback circuit including an amplifier 22 which is switchable to operate in an integrating or a holding mode. Either amplifier 22 integrates the signal plus noise from cells 20 with power supplied over switch 44 and then, with the power removed, holds the signal plus noise value (switch 33 open) for subtraction with the noise signal remaining at summing junction 21, or amplifier 22 integrates the noise signal (switch 44 open) then with switch 44 closed and switch 33 open, the held noise value from amplifier 22 is subtracted at 21 from the signal plus noise from cells 20. Modes of operation.-The " Track " mode is one in which read-out is performed at regular intervals determined by timer TD3. The bandwidth of filter 31 is determined at the same time as the setting of TD3 to automatically select the optimum bandwidth for the read-out interval selected. In the " Demand " mode, timer TD3 is out of circuit, and knob 46 only controls the selection of bandwidth (and hence response time) of the system. Each measurement indication obtained is maintained until a fresh manual read-out demand is made. The " Demand-null " mode is one in which, after a read-out demand and a subsequent zero output from comparator 43, switch 49 is closed to set the time constant to the setting of knob 46 and to start timer TD14 which provides a signal averaging time and prevents initiation of readout until comparator 43 again indicates balance after TD14 has timed out. Digitizing operation.-Programmer 37 includes a ring counter controlling the sequence of operations. When a read-out is initiated, programmer 37 resets counters 38-41 and the various logic circuits and opens switches 33, 44 (or opens 33 and closes 44). Comparator 43 then determines whether the output of summing junction 21 is positive or negative, the bandwidth of circuit 25 being reduced during the read-out cycle. One or other of staircase generators 27, 28 is selected, each generator comprising a resistor for each of the stages of ring counters 38-41 and an additional resistor for the 1000's, 100's and 10's digits connected to stages of the programmer 37 counter. With the programmer counter producing 1000 units output from generator 27 or 28 and switch 29 closed, clock pulses are fed to counter 38 to produce increments of 1000 units in the comparison voltage until comparator 43 detects that the output of summing junction 26 has changed sign. The programmer counter is then stepped on, thus removing the initial 1000 units of reference voltage and replacing it with an initial 100 units. The remaining digits are determined successively in a similar manner, except that the units digit is determined ten times in succession and the average is taken, Fig. 5 (not shown). Tare circuit.-Switches 168-327 are set to offset the tare weight, though gross weighing may be performed if desired. The 1000's digit of the tare circuit uses some of the 1000's resistors in the staircase generator, an interlock circuit providing a warning if the gross weight thousands digit exceeds 10.