Patent GB-1468465-A (GB)
Title: Timing correction for electrical pulse signals
IPC: H04N9/89
Filed: 1975-02-28
Abstract: 1468465 Television systems BRITISH BROADCASTING CORP 28 Feb 1975 [28 Feb 1974] 43593/76 Divided out of 1468464 Addition to 1355648 Heading H4F An apparatus for timing or retiming pulse signals, e.g. a digital television signal, includes at least three stores which are connected sequentially to the pulse input terminal and to the output of the apparatus via switches. The switches are so controlled that read-out from any one store cannot occur during write-in to that store, and vice versa. Write and read clock pulses are applied to the relevant stores only when required. They are derived from a common generator, the write clock pulses being adjusted in dependence on the signal at the input terminal. In the arrangement shown in Fig. 1 the common generator 28 provides reference line sync. pulses and a reference subcarrier to write and read control units 24, 26. The units generate the write and read clock pulses for the stores 14-16 and also control the switches 12, 20 connected to the stores. An interlock 30 ensures that no store is selected both for write-in and read-out simultaneously. An input colour television video signal (10) is digitized (11) prior to being fed to the stores and reconverted (21) to analog form at their output. The phase of the write clock pulses is adjusted relative to the input video in dependence on both the line sync. and the colour burst of the input video. In one embodiment of the write control unit, Fig. 2, at the start of an input video line an oscillator 40, synchronized by the reference line sync. pulses, supplies pulses to phase detector 52 and delay 50. The delay 50 is adjusted according to the phase error between the pulses and the input video line sync. pulse (54). During the colour burst the reference sub-carrier is applied via phase interpolator 44 and delay 50 to phase detector 58 and delay 56. Delay 56 provides fine timing adjustment according to the phase error between the reference sub-carrier (36) and the input sub-carrier (60). Because the input colour sub-carrier frequency is not an integral multiple of the line frequency the phase relationship of these signals varies cyclically. Interpolator 44 compensates for this by cyclically varying the phase of the reference sub-carrier. The correctly-phased pulses at the output of delay 56 are multiplied by three to provide the write clock pulses. In a modification of Fig. 2 (Fig. 5, not shown) any fixed timing off-set resulting from the unspecified phase relationship of the video line sync. and sub-carrier signal is removed by delaying (74) the input line sync. signal fed to detector 52 by an amount dependent on the integrated error signal output of detector 58. This delayed signal may also control a gate (78) between delays 50, 56 to inhibit input to delay 56 and detector 58 for a certain period shortly after each input line sync. pulse, the resulting gap being detected and used as a command pulse to cause the next store to be selected for storage. In a further modification interpolator 44 is omitted and reference sub-carrier is applied to delay 50 and detector 52 so that delay 56 provides a colour sub-carrier line-locked to the input colour burst, for example for use with a video tape unit monitor.