Patent GB-1323612-A (GB)
Title: Associative processor
Inventor: EDDEY E
IPC: G11C15/02
Filed: 1970-12-07
Abstract: 1323612 Associative processor GOODYEAR AEROSPACE CORP 7 Dec 1970 [29 Dec 1969] 57970/70 Headings G4A and G4C An associative processor comprises a memory array, response store circuits series connected with all the bits in their associated stored word, bit interrogate drivers serially connected with corresponding bits in each word, a logic control which in conjunction with the response store circuits and the bit interrogate drivers performs logic functions on the contents of the memory, a sequential controller co-operating with the logic control to enable a programmed sequence of logic operations to be performed on the contents of the memory, and a common data bus and associated control systems to enable data to be read from or written into the memory in a serial by bit parallel by word format. The memory.-As described the memory is a plated wire system in which circular sectioned wires 50 are coated with an anisotropic permalloy film, the wires being preferably of beryllium-copper. Each wire stores a word, the bit storage locations being the areas 52 common to the intersection of the plated wire and orthogonal bit straps 54. Bit and word currents are applied and the magnetization is rotated toward the axial direction as indicated at 56. A bipolar word driver controls the direction of the word current in accordance with the polarity of the data input. The word current remains after the bit current has been removed and the magnetization adopts a clockwise or anticlockwise sense dependent on the stored datum. To read the data the appropriate bit strap is pulsed and the magnetization reversible rotates through 90 degrees causing a voltage to be applied to the wire 50. So long as the bit current results in a hard axis field less than the anisotropy field read out is non destructive and the magnetization reverts causing a further voltage pulse on the wire 50. The pulses emitted are of opposite polarity, their order depending on the polarity of the datum stored. Sense amplifiers are provided which respond only to one polarity so the store output is a pulse whose time of arrival is indicative of the datum stored. Further constructional features of the plated wire memory are described, including cooling arrangements and the specification states that other types of memory, e.g. magnetic cores, semi-conductor elements, etc., may be used. Processing.-The output from the memory is detected by a response store circuit. A number of embodiments of such circuits which permit the performance of logic functions on the stored data are described. In the simplest Fig. 8 a flip-flop Q is connected to the sense amplifier via AND gates A1 and A2. The lines K1 and K2 are pulsed at appropriate times so that the flipflop is set to a state corresponding to the stored datum. If the times of the pulses K1 and K2 are reversed the flip-flop will store the complement of the stored datum. If only K1 is pulsed at a time corresponding to the arrival of a pulse signifying a "1" bit then the final state of Q is the logical OR of the datum with the previous state of the flip-flop. If Q is a JK flip-flop so that simultaneous pulses from both AND gates reverse its state then all possible combinations of pulses to K1 and K2 will produce all 16 possible logical functions of two variables. If the choice of logical function depends on the value of a comparand bit, associative search operations can be performed. Fig. 9 shows another response circuit which is similar to that of Fig. 8 except for the provision of an additional flip-flop S. The flip-flop S allows a single or a plurality of words to be selected for read out. An exact match associative search can now be performed with a mismatch at any bit of a word causing its associated flip-flop S to become reset and prevent the word taking any further part in the search. A large number of other logical and arithmetic functions can be performed as well as data shift operations using a two flip-flop system. The specification enumerates all the possibilities and gives details of a number, the shift operations being utilized when arithmetic operations are performed on more than one word. A three flip-flop system is illustrated in Fig. 13 (not shown) which although of comparable speed to the two flip-flop system for logic operations is approximately twice as fast for the more complex arithmetic operations. The processor will thus perform logic or arithmetic functions on all the words, or a selected group of words, simultaneously. The specification states that the processor may be used in conjunction with a radar system for air traffic control purposes.