baber/WOPTO huggingface dataset:
Patent TW-546635-B (TW)
Title: Method and device for recording information in units
Inventor: SPRUIT JOHANNES HENDRIKUS MARI
IPC: G11B20/10
Filed: 2000-03-28
Granted: 2003-08-11
Abstract: A method and device for recording information in units on a partly recorded writable record carrier (11), e.g. an optical disc. The information is recorded in a track represented by series of marks of different runlengths between a minimum runlength and a maximum runlength and synchronizing patterns of marks, which patterns do not occur in the series of marks and comprise at least one long mark of at least the maximum runlength. At least one information unit is encoded into a modulated signal comprising signal elements corresponding to said marks. The track is scanned up to a link position before a selected one of said addressable locations, and the modulated signal is recorded from the link position. The modulated signal is provided at the begin and/or at the end with a link signal element corresponding to a mark of at most the minimum runlength.
Patent TW-473413-B (TW)
Title: Method for the making of solder connection pads on a substrate and guide for the implementation of the method
Inventor: PILAT ERIC
IPC: H05K3/34
Filed: 2000-04-27
Granted: 2002-01-21
Abstract: A method for molding and soldering electrical connection pads to the electrical connection-receiving zones of electronic components or circuits comprises an operation for the injection of conductive liquid alloy into a guide open at one end placed so as to face the connection-receiving zone of the component. The guide is formed by two separable parts, a mold and an injection matrix, the mold and the injection matrix comprising passages, with a narrowing of the guide at the level of the separation of the parts, and the parts of the guide are separated while the alloy is in the liquid state. Applications: making of connection pads for substrates or electronic components.
Patent TW-490594-B (TW)
Title: Lithographic projection method
Inventor: KUIT JAN JAAP
IPC: G03F7/20
Filed: 2000-05-26
Granted: 2002-06-11
Abstract: A method of projecting an image onto a plurality of target areas on a substrate whereby use is made of a lithographic projection apparatus comprising: a radiation system for supplying a projection beam of radiation; a mask table provided with a mask holder for holding a mask; a substrate table provided with a substrate holder for holding a substrate; a projection system for imaging an irradiated portion of the mask onto a target area of the substrate, whereby the substrate is to be irradiated with images from at least two different masks, characterized by the following steps: (a) providing a batch of substrates, each at least partially coated with layer of radiation-sensitive material; (b) providing storage means for temporary storage of the batch; (c) providing a first mask on the mask table; (d) irradiating a first set of target areas of a first substrate with an image from the first mask, and then placing that substrate in the storage means; (e) repeating step (d) for each of the other substrates in the batch; (f) replacing the first mask by a second mask; (g) providing a primary substrate from the storage means on the substrate table and irradiating a second set of target areas of that substrate with an image from the second mask; (h) repeating step (g) for each of the other substrates stored in the storage means.
Patent TW-445614-B (TW)
Title: Heat dissipation control device and method of integrated circuits
Inventor: LIOU CHU-GANG
IPC: H01L23/34
Filed: 2000-06-30
Granted: 2001-07-11
Abstract: The present invention is a heat dissipation control device and method of integrated circuits, which is applied in controlling the active heat dissipater of integrated circuits, the heat dissipation control device comprises: a thermal energy computation circuit which is electrically connected to the integrated circuit to calculate the accumulated thermal energy of the integrated circuit in each unit time corresponding to the variation of the loading current of the integrated circuit, and thereby send out a thermal energy accumulation signal; a temperature detection circuit to detect the surface temperature of the integrated circuit to thereby send out a temperature signal; and a signal processing driver which is electrically connected to the thermal energy computation circuit, the temperature detection circuit and the active heat dissipater of the integrated circuit, which can vary the heat dissipation performance of the active heat dissipater of the integrated circuit corresponding to the variation of the accumulated thermal energy signal and the temperature difference signal.
Patent TW-503184-B (TW)
Title: Segmented resistor inkjet drop generator with current crowding reduction
Inventor: GIERE MATTHEW
IPC: B41J2/14
Filed: 2000-07-06
Granted: 2002-09-21
Abstract: In order to overcome inefficient power dissipation in parasitic resistances and to provide economies in the power supply, a higher resistance value heater resistor is employed in a thermal inkjet printhead. Higher current densities in a high resistance segmented heater resistor are reduced by employing a shorting bar (511) divided by a current balancing resistor (601).
Patent TW-525412-B (TW)
Title: Electronic ballast for discharge lamp
Inventor: YAMANAKA YUKIO
IPC: H05K3/34
Filed: 2000-08-25
Granted: 2003-03-21
Abstract: The present invention provides an electronic ballast for a discharge lamp which is capable of detecting the operating condition of the discharge lamp, and is designed to tightly arrange the circuit components for forming the ballast. The ballast comprises: an AC-DC converter adapted to receive a source AC voltage and convert the source AC voltage into a DC voltage; and an inverter providing a high frequency output voltage from said DC voltage for operating the discharge lamp. The inverter comprises at least one switching element, a control circuit for said switching element, and an output transformer connected to said discharge lamp. The control circuit activates said switching element to provide the high frequency output voltage to said discharge lamp through said output transformer. A single circuit board is mounted with electric parts for constituting said converter and said inverter. The circuit board is accommodated in a tubular casing. A dielectric sheet is interposed between said circuit board and said casing for insulation of said circuit board and said electric parts from said casing. The output transformer and other circuit components are soldered together on the upper surface of the circuit board. The ballast includes a plurality of chip components forming a detection circuit for detection of a condition of said lamp, and said chip components of the detection circuit are soldered on the bottom surface of the circuit board at a location immediately opposite to said output transformer.
Patent TW-531521-B (TW)
Title: Method and arrangement for shipping reels; tweendeck and tweendeck arrangement in cargo space of ship
Inventor: LANGH HANS
IPC: B63B35/04
Filed: 2000-12-22
Granted: 2003-05-11
Abstract: The invention relates to a method and an arrangement for shipping a reel (1) onboard a ship (2) where the reel (1) is at least partly placed into a cargo space (3) of the ship. The arrangement comprises a reel holder (4), which holds the reel (1) placed therein substantially in position at least in the horizontal and downward direction, and the reel holder (4) is arranged onto a tweendeck (5) in the ship's cargo space (3) that is placed at a distance from the bottom (6) of the ship's cargo space, closer to the metacentre of the ship (2) than to the bottom (6) of the ship. The invention also relates to a tweendeck to be used as a transport support for the reel (1) in sea transport and to a tweendeck arrangement in the ship's cargo space (3).
Patent TW-479356-B (TW)
Title: Circuit for performing the erasing procedure onto reference cell array of the split-gate flash memory device
Inventor: JOU SHAU-YU
IPC: H01L27/115
Filed: 2001-01-12
Granted: 2002-03-11
Abstract: A kind of circuit structure for flash memory device is disclosed in the present invention. The flash memory device includes a memory cell array and a reference cell array. When a control logic apparatus performs reading action onto the memory cell array based on the input address, a reading current can be generated by a specific memory cell, and a reference current is generated by a reference cell, in which the reading current is compared with the reference current to judge the logic status of the read memory cell. The reference cell array can respond to a power on reset apparatus to conduct the erasing procedure so as to maintain the stored data of the reference cell. When a voltage supplied by a power source is input, the power on reset apparatus can transmit high-voltage signals to the reference cell array through a high-voltage apparatus in order to conduct the erasing procedure onto the entire reference cells and maintain the stored data of the reference cell.
Patent TW-483288-B (TW)
Title: Organic electroluminescent device, polarizing surface light source, and liquid-crystal display
Inventor: MIYATAKE MINORU
IPC: H01L51/50
Filed: 2001-01-17
Granted: 2002-04-11
Abstract: An organic electroluminescent device is disclosed which has a simple constitution, is excellent in device stability and emission efficiency, and attains high brightness. The organic electroluminescent device comprises an organic electroluminescent element (2) and a polarized-light scattering film (1) which comprises a light-transmitting resin (11) and dispersedly contained therein minute regions (12) differing from the light-transmitting resin in birefringent characteristics and in which the difference in refractive index between the minute regions and the light-transmitting resin in the axis direction in which a linearly polarized light has a maximum transmittance, Δn1 is smaller than 0.03 and that in a direction perpendicular to the Δn1 direction, Δn2, is from 0.03 to 0.5, the light produced by the organic electroluminescent element being emitted from the device through the polarized-light scattering film. Also disclosed are: a polarizing surface light source which comprises the organic electroluminescent device and which has an illuminating planar surface and emits a polarized light; and a liquid-crystal display which comprises the polarizing surface light source and a liquid-crystal cell disposed on the light emission side of the light source.
Patent TW-506186-B (TW)
Title: Focus control for search lights
Inventor: FRICKE KENNETH J
IPC: F21Y101/00
Filed: 2001-02-07
Granted: 2002-10-11
Abstract: The focus angle θ of a search light (12) mounted on a helicopter (10) or other platform (10) is narrowed or widened by rotating a bidirectional focus control cam (42) in a clockwise or counterclockwise direction as selected by a manually operated three-position control switch (SW1) which determines the rotational direction of a DC motor (28) driving the bidirectional focus control cam (42). The DC motor (28) has first and second terminals (92, 93) which are selectively connected to either a DC power source (72) or ground (73) by a double-pole, single throw dual relay (64) which reverses the polarity and thus the direction of rotation of the DC motor (28). The dual relay (64) is connected by the same single wire interface (32) to the manually operated control switch (SW1), which manually operated control switch (SW1) is within a control box (62) located in the helicopter (10). By operating the manually operated control switch (SW1) to connect coils (76, 78) in the dual relay (64) to either a power source (72) or to ground (73), the coils (76, 78) are selectively energized or deenergized causing the dual relay (64) to operate switches (SWR, SW3) that reverse polarity of current flowing through the DC motor (28). This selectively changes the direction of rotation of the bidirectional cam (42) which advances and retracts a focusing reflector (47) within the search light (12) to widen and narrow its focus angle θ, thereby widening and narrowing the area (16) illuminated by the search light beam (14).
Patent TW-558754-B (TW)
Title: Self-aligned silicide process method
Inventor: WANG SHIUE-WEN
IPC: H01L21/28
Filed: 2001-02-14
Granted: 2003-10-21
Abstract: A kind of self-aligned silicide (salicide) process method is disclosed, in which, before a metal silicide barrier layer is used to cover a substrate, an N-type pre-amorphous ion implantation process and a P-type pre-amorphous ion implantation process are performed onto an N-type MOS transistor and a P-type MOS transistor of the substrate, respectively, to make the surface of the gate and source/drain of the N-type MOS transistor and P-type MOS transistor become amorphous. Subsequently, a metal silicide barrier layer is used to cover the area of the substrate with pre-amorphous silicide layer, which is followed by covering the substrate with a metal layer and performing a thermal process to incur silicidation of the part of the metal layer to form silicide. Finally, the metal layer which has not reacted and the metal silicide barrier layer are removed.
Patent TW-480206-B (TW)
Title: Wafer carrier head assembly
Inventor: TRAVIS GLENN W
IPC: B24B37/32
Filed: 2001-04-04
Granted: 2002-03-21
Abstract: A wafer carrier head assembly for holding a wafer in chemical mechanical planarization applications is disclosed that includes a downwardly protruding wafer retaining ring that moves independent of the wafer carrier head and retains an edge of the wafer on said polishing surface. An adjustable wafer holding mechanism that applies one of a unform downward force and a uniform upward force to the wafer is also included. Application of the upward force allows the wafer holding mechanism to retain and transport the wafer to a polishing surface. Application of the downward force allows the wafer holding mechanism to retain the wafer on the polishing surface and allows the wafer to be uniformly polished. The wafer carrier head assembly herein disclosed is also configured to pivotally accommodate changes in parallelism between the wafer and the polishing surface when the wafer is being polished.
Patent TW-555939-B (TW)
Title: Apparatus for controlling a magnetic bearing
Inventor: TAIRA AKIKO
IPC: H02P29/00
Filed: 2001-04-20
Granted: 2003-10-01
Abstract: The present invention provides apparatus for controlling a magnetic bearing capable of operating a motor under the low noise, and the whole system holds simple structure, small size and low production cost, and comprising at least a pair of opposed electromagnets floatingly supporting a floated body, a motor M rotating the floated body, and a controller driving and controlling the above devices, wherein a DC/DC converter (13) supplies driving power to an inverter 14 for driving the motor M. The inverter 14 of the motor M rotates and drives the motor M in concurrent use of a PWM control mode and a PAM control mode.
Patent TW-550688-B (TW)
Title: Cleaning sheet, conveying member using the same, and substrate processing equipment cleaning method using them
Inventor: YOSHIO TERADA
IPC: C09J7/02
Filed: 2001-05-08
Granted: 2003-09-01
Abstract: A cleaning sheet for cleaning foreign matters away from the interior of the substrate processing equipment is provided. The cleaning sheet includes a cleaning layer having substantially no tackiness and having a tensile modulus of not lower than 0.98 N/mm<2> as determined according to JIS K7127. Alternatively, the cleaning sheet includes a cleaning layer. having a Vickers hardness of not lower than 10.
Patent TW-I302913-B (TW)
Title: Thrombin receptor antagonists
Inventor: SAMUEL CHACKALAMANNIL
IPC: C07D409/14
Filed: 2001-06-13
Granted: 2008-11-11
Abstract: Heterocyclic-substituted compounds of formula (I) or a pharmaceutically acceptable salt thereof, are disclosed, wherein: Z is - (CH2)n-; (a); (b), wherein R 10  is absent; or, (c) wherein R 3  is absent; the single dotted line represents an optional double bond; the double dotted line represents an optional single bond; n is 0-2; Het is an optionally substituted mono-, bi- or tri-cyclic heteroaromatic group; B is -(CH 2 ) n3 -. wherein n 3  is 0-5, -CH 2 -O-, -CH 2 S-, -CH 2 -NR 6 -, -C(O)NR 6 -. -NR 6 C(O)-, (d), optionally substituted alkenyl or optionally substituted alkynyl; X is -O- or -NR 6 - when the double dotted line represents a single bond, or X is H, -OH or -NHR 20  when the bond is absent; Y is =O, =S, (H, H), (H, OH) or (H, C 1 -C 6  alkoxy) when the double dotted line represents a single bond or when the bond is absent, Y is =O, =NOR 17  (H, H). (H, OH), (H, SH), (H, C 1 -C 6  alkoxy) or (H, substituted-amino); R 22  and R 23  are independently -OH, -OC(O)R 30 , OC(O)NR 30 R 31 , or optionally substituted alkyl, alkenyl, alkynyl, heterocycloalkyl, aryl, cycloalkyl, cycloalkenyl, carbonyl, amino, alkoxy, alkenyloxy, alkynyloxy, heterocycloalkyloxy, cycloalkyloxy, or cycloalkenyloxy; or R 22  and R 10 , or R 23  and R 11 , can form a carbocyclic or heterocyclic ring; and the remaining variables are as described in the specification, Also disclosed are pharmaceutical compositions containing said compounds and their use as thrombin receptor antagonists and blinders to cannabinoid receptors.
Patent TW-512514-B (TW)
Title: Ending structure of high-voltage resistant device
Inventor: HE JI-SHIUN
IPC: H01L27/088
Filed: 2001-06-29
Granted: 2002-12-01
Abstract: The present invention discloses an ending structure which comprises a main field plate electrically connected to a main junction; and a secondary field plate electrically connected to a field ring. The field ring and the main junction are separated by a certain distance. A floating field plate is located between the main field plate and secondary plate. The main field plate has the first extended portion formed on an insulation layer, and the secondary field plate has the first extended portion and the second extended portion formed on the insulation layer. The floating field plate is buried in the insulation layer. Both ends of the floating field plate are aligned to the end of the first extended portion of the main field plate and the secondary field plate respectively, so that the main field plate, secondary field plate and floating field plate are capacitively coupled to alleviate the electrical crowding, and save the required area of the ending structure.
Patent TW-513902-B (TW)
Title: Defective unit piece removal and filling method for various printed circuit boards
Inventor: JOU JENG-SHIAN
IPC: H05K3/04
Filed: 2001-07-12
Granted: 2002-12-11
Abstract: This invention relates to a defective unit piece removal and filling method applicable for various printed circuit boards. On a plural number of connection sheets surrounding the periphery of a defective unit piece, a router is used to cut out a split opening with an adequate range at the same position of each connection sheet, in which both sides of the split opening have two connection corners of 50 μm remained. The connection corners of each split opening are broken by one punch so that the defective unit piece can be removed from a usable substrate. The same method is further utilized to remove good unit pieces from a discarded substrate. The good unit piece is made to be fully equal to the defective unit piece and the individual connection sheets have the connection corners of the same shape. On a usable substrate with defective unit pieces removed, good unit pieces are then inserted to replace the defective unit pieces which have been removed. Each connection corner is used to precisely position the good unit pieces and thus a split opening is formed on each connection sheet. An adhesive is used to fill each split opening so that the inserted good unit piece can be steadily joined with the substrate and thus subsequent printing tin paste layer or surface mounting insertion process can be performed successfully. Rework process of the substrate can achieve utilization value in industry when defective situations such as fall-off or displacement can be prevented by sufficient endurance of surface stress.
Patent TW-533485-B (TW)
Title: Semicondcutor integrated circuit device with moisture-proof ring and its manufacture method
Inventor: KOMADA DAISUKE
IPC: H01L23/58
Filed: 2001-09-25
Granted: 2003-05-21
Abstract: A semiconductor integrated circuit device, having: a plurality of semiconductor elements formed in a central circuit area of a semiconductor chip; a plurality of insulating layers formed on the semiconductor chip; cavities for forming wiring layers of a multi-layer structure, each of the cavities in each wiring layer having a via hole and a wiring pattern trench; wiring layers of the multi-layer structure including a via conductor filled in the via hole and a wiring pattern filled in the wiring pattern trench; moisture-proof ring trenches of a multi-layer structure corresponding to the cavities for forming the wiring layers of the multi-layer structure, the moisture-proof ring trenches surrounding the circuit area in a loop-shape and formed through the insulating layers, a width of each of the moisture-proof ring trenches corresponding to a corresponding one or ones of the via holes being set smaller than a minimum diameter of the via holes; and a conductive moisture-proof ring filled in a corresponding one of the moisture-proof ring trenches. In etching via holes and a moisture-proof ring trench, it is possible to suppress the stopper film in the moisture-proof ring trench from being thinned and to minimize damages to the underlying wiring layer.
Patent TW-532005-B (TW)
Title: Multi-loop testing equipment of community network system and method therefor
Inventor: WU CHIAN-SHUEN
IPC: H04L12/00
Filed: 2001-10-26
Granted: 2003-05-11
Abstract: The invention relates to a multi-loop testing equipment of community network system and method therefor, which adds a loop testing equipment among each community Ethernet network switch and central office (CO) equipment so that the network management system of CO can utilize the loop testing equipment to perform three-layer loop test with respect to the community network system, allowing to know if there's any fault between CO and the loop testing equipment and to detect if the link of the Ethernet switch is functioning and if the loop testing equipment is functioning. As such, the invention can significantly reduce services management cost and effectively increase quality of services (QoS) of network transmission.
Patent TW-523881-B (TW)
Title: Non-volatile memory device and method of manufacturing the same
Inventor: PARK WEON-HO
IPC: H01L21/8247
Filed: 2001-11-16
Granted: 2003-03-11
Abstract: A non-volatile memory device includes gate insulating films formed on a semiconductor substrate and spaced apart from each other; a tunnel insulating film formed on the semiconductor substrate and interposed between the adjacent gate insulating films; a memory transistor gate formed on the tunnel insulating film and the gate insulating film interposing the tunnel insulating film therebetween; a select transistor gate formed on the gate insulating film spaced apart from the memory transistor gate; a first doped region formed in a portion of the semiconductor substrate under the memory transistor gate and extending to overlap one end of the select transistor gate; a second doped region formed in a portion of the semiconductor substrate spaced apart from the first doped region and overlapping one end of the memory transistor opposite to the select transistor gate; and a third doped region formed in a portion of the semiconductor substrate spaced apart from the first doped region and overlapping the other end of the select transistor gate, wherein the second doped region has a low-density doped region and a high-density doped region and is shallower in depth than the first and third doped regions.