baber/WOPTO huggingface dataset:
Patent TW-325499-B (TW)
Title: Method and device for operating dual-container electric arc furnace
Inventor: ANDREAS HUEBERS
IPC: C21B13/12
Filed: 1995-12-06
Granted: 1998-01-21
Abstract: A method for operating a dual-container electric arc furnace, in particular a method for a dual-container electric arc furnace used in steelmaking, in which the dual-container electric arc furnace is equipped with electrodes installed on a swing device and one of the containers, I or II, is completely separated from the electric network while the other container remains in the electric network; the container which is separated from the electric network is loaded with the metallic furnace material and is subsequently sealed by a furnace cover, and the container which remains in the electric network undergoes the further smelting operation such as smelting the molten metal and overheating it until discharging the iron liquid, which is characterized in that the container I or II comprises the following steps: for container I: (a) loading the liquid raw iron until the liquid raw iron occupies 70% of the metal furnace material in the container I (1); (b) through a blowing gun (14) blowing in oxygen gas from the above, meanwhile based on the heat balance during the blowing process adding minerals, waste steel, spongy iron or other cooling agent for the metallic furnace materials, and based on the analysis on the metallic furnace materials adding cinder forming agent such as lime, dolomite, etc.; (c) continuously discharging cinder and/or partially discharging cinder (26) through the cinder outlet (21) and the preheater (22) during the intermittence or end of blowing; (d) from the container I (1) removing and putting aside the blowing gun (14, 16); (e) inwardly swinging the electrodes (3), which is installed on the swinging device (8) and connected to the transformer (10) through a high current lead (9), to a place on the lower container I (1); (f) powering-on the electrodes (3) of the container I (1) while adding the remaining metallic furnace materials (minerals, waste steel, spongy iron or others) until the weight of outputting material has been reached, and using a side spraying gun to add in lime and continue blowing oxygen during the smelting and overheating process; (g) during the step (f) continuously partially discharging cinder and/or partially discharging cinder (26) through the cinder outlet (21) and the preheater (22) during the smelting process or at the end of the smelting process to overheating the molten metal (27) in the end; (h) through a steel outlet (23) discharging the molten metal (27) to a liquid iron bucket, while retaining a part of the molten metal (27) in the furnace bed (24, 25) of the container I (1) as a liquid pool; for container II: applying the steps (e) to (h) on the lower container II (2) at the same time while applying the steps (a) to (d) on the lower container I (1); applying the steps (a) to (d) on the lower container II (2) at the same time while applying the steps (e) and (h) on the lower container I (1).
Patent TW-307028-B (TW)
Title: The manufacturing method of plug with sacrificed layer
Inventor: TZENG HORNG-HUEI
IPC: H01L21/311
Filed: 1996-02-09
Granted: 1997-06-01
Abstract: A manufacturing method for conductor plug of IC includes: Form 1st conducting region; Form 1st and 2nd dielectric, and planarize the 1st dielectric; Etch 1st and 2nd dielectric by lithography and etching technology to form hole; Deposit a conductor layer to stride over and fill the hole, and do contacting with 1st conducting region; Proceed anisotropic etchback on conductor layer to totally etch the conductor surrounded the hole and keep partially conductor inside the hole;Remove 2nd dielectric; Form 2nd conducting region to stride over the hole and contact with conductor inside the hole.
Patent TW-332346-B (TW)
Title: Light-emitting diode
Inventor: GERNER JOCHEN
IPC: H01L33/38
Filed: 1996-03-20
Granted: 1998-05-21
Abstract: A light-emitting diode includes: a) a substrate b) a light-emission generating layer embedded between the cladding layers of a double heterostructure and located on the substrate c) a current diffusion layer on the top cladding layer on which there is a further contact layer structure; the current diffusion layer is sufficiently thin so as to hardly absorb any light-emission and the diode can be economically produced by means of the MOCVD process d) the contact layer structure is provided with branched and finger-type electrodes for distributing the current together with the current diffusion layer onto the surface of the light-emission generating layer.
Patent TW-299420-B (TW)
Title: Voice processor for controlling electric device
Inventor: CHEN WEI-DER
IPC: G06F40/00
Filed: 1996-04-19
Granted: 1997-03-01
Abstract: A voice processor for controlling electric device comprises of: (1) one microphone for receiving voice signal; (2) one analog/digital converter for digitizing the voice signal; (3) one instruction recorder for recording first digitized voice signal as voice instruction of starting some specific electric function of the electric device; (4) one instruction analyzer for comparing second digitized voice signal with the voice instruction, if the second digitized voice signal is recognized as same with the voice instruction, then starting the specific electric function.
Patent TW-426596-B (TW)
Title: Method for transiently wetting lens molds in production of contact lens blanks to reduce lens hole defects
Inventor: WIDMAN MICHAEL
IPC: B29K105/24
Filed: 1996-11-11
Granted: 2001-03-21
Abstract: Hydrophilic contact lens molds are transiently modified to provide a water dynamic contact angle equal to or less than 100 DEG by treatment with a wetting agent which may be water or a surfactant composition which provides a mold surface having a water wetting force of at least 70 mg to afford a reduction in lens hole defects in hydrophilic contact lens manufacture.
Patent TW-373133-B (TW)
Title: Work on site limit GF (2m) AB2+C cellular-array power-sum circuit method and apparatus
Inventor: Wei xue-wen
IPC: G06F11/14
Filed: 1996-12-24
Granted: 1999-11-01
Abstract: This invention is a kind of work on site limit GF (2m)(GF: Galois Field) AB2+C cellular-array power-sum circuit method and apparatus, especially regarding a kind of site limit GF (2m) to execute AB2+C cellular-array power-sum circuit method and its computation method, wherein A, B and C are about any component among site limit GF (2m); this invention newly set up circuit is (Power-sum circuit erection) is formed with m<SP>2</SP> nos. of tiny cells, and the computation time of the said circuit is 2m nos of logical gate delays, with the said basic AB2+C cellular-array power-sum circuit as foundation, to make one or many combination to make site limit GF (2m) as exponentiation, multiplicative inverse, division linear systolic array circuit systolic array circuit to be proposed at the same time, wherein the proposed linear systolic array circuit structure are able to take single-stage or multi-stage pipeline structure as formation, the said multi-stage pipeline structure only needs 2m nos. of logical gate delays with average computing time, but it needs m (or m-1) nos. of AB2+C cellular-array power-sum circuit to form the combination, and even though single-stage pipeline structure needs 2 m<SP>2</SP> nos. of logical gate delays for computation time, but only needs an AB2+C cellular-array circuit to complete.
Patent TW-374077-B (TW)
Title: Partially hydrophobic precipitated silicas
Inventor: LUX HEINZ-GUNTER
IPC: C11D3/12
Filed: 1997-03-26
Granted: 1999-11-11
Abstract: A partially hydrophobic precipitated silica, characterized by a methanol wettability of 10 to 39%, in particular with a DBP uptake anhydrous of greater than 350 g/100 g and a mean particles sized of 1 to 12 μm and/or a carbon content of 0.3 to 1.85% and/or a loss on drying of 2.6 to 10.0% and/or a pH value of 5.5 to 10.0, is prepared by mixing the amount of water repellent agent with the precipitated silica suspension at very short residence time and low pH value, filtering off the solid substance, washing free of salt, drying, post-treating thermally and milling. The partially hydrophobic precipitated silica can be used in active substance formulations and active substance formulations of hydrolysis-sensitive substance and in defoaming agents.
Patent TW-362044-B (TW)
Title: A process for presulphiding hydrocarbon conversion catalysts
Inventor: LOCKEMEYER JOHN ROBERT
IPC: C10G47/16
Filed: 1997-07-08
Granted: 1999-06-21
Abstract: The invention provides a process for presulphurizing porous particles of a sulphidable catalyst containing at least one metal or metal oxide, which comprises (a) impregnating the catalyst with an inorganic poly-sulphide solution and at least one water-soluble oxygenated hydrocarbon to obtain a sulphur-incorporated catalyst in which at least a portion of the sulphide or sulphur is incorporated in the pores of the catalyst; and (b) heating the sulphur-incorporated catalyst in the presence of a non-oxidizing atmosphere; presulphurized catalysts and their use in hydrocarbon conversion processes.
Patent TW-377333-B (TW)
Title: Improvements in and relating to liquid dispensing apparatus
Inventor: BOLTON TERENCE WILLIAM
IPC: B05B11/00
Filed: 1997-07-18
Granted: 1999-12-21
Abstract: Liquid dispensing apparatus comprises a tubular casing having at one end an inlet nozzle connectable to a source of gas under pressure and at its end an outlet nozzle having an orifice in communication with an expansion chamber bounded by sides which diverge away from or converge towards the orifice. Means are provided for locating a pen-like liquid source having an absorbent nib at least partially within the casing with the nib within or in close proximity to the nozzle orifice. The pen-like source may comprise a felt-tipped pen.
Patent TW-365035-B (TW)
Title: Semiconductor device package having a board, manufacturing method thereof and stack package using the same
Inventor: JEONG MOON-CHEA
IPC: H01L23/24
Filed: 1997-08-02
Granted: 1999-07-21
Abstract: There are provided a semiconductor device package which comprises a board having metal patterns made of conductive metal which are formed on an upper and a lower surfaces of the board, a cavity which is formed on the lower surface, and an opening which is connected to the cavity, a semiconductor chip which is attached to the lower surface of the board by an adhesive means so that bonding pads of the chip are exposed to the opening, plating layers which are formed on side surfaces of the board and electrically interconnected to the metal patterns, and an encapsulating means for encapsulating electrical interconnection parts, and a manufacturing method thereof, and a stack package using the same. The present invention has advantages that it is effectively used for the smaller and thinner electronic apparatus and increases operational speed of the semiconductor chip due to the short distance from the semiconductor chip to the metal patterns of the lower surface of the board which is used as an external connection means. Further, the manufacturing method of the present invention does not require the step of attaching the separated external connection means, because the metal patterns of the board is used as the external connection means. Therefore, time and cost for manufacturing the external connection means can be reduced.
Patent TW-358216-B (TW)
Title: Color picture tube having improved funnel
Inventor: OPRESKO STEPHEN THOMAS
IPC: H01J29/86
Filed: 1997-08-04
Granted: 1999-05-11
Abstract: A sort of color picture tube having a glass envelope, including the glass envelope a rectangular surface panel, a conic tube and a tube neck, including the envelope 3 orthogonal axes, a major axis in roughly parallel to the panel and of a wider side, a minor axis, substantially parallel to a narrower dimension of the panel, and a longitudinal axis, extending through the center of the neck and the center of the panel, having the envelope center a main body portion and a yoke region which is sealed to the neck; where the main body portion of the conic tube having a first lateral wall of reduced thickness and the second lateral wall by varying the thickness of a lateral wall in the yoke region, so that the greatest thickness in the lateral wall in the yoke region occurs in proximity to the major axis.
Patent TW-346545-B (TW)
Title: Optical guide
Inventor: ANDERS HULT
IPC: G02B6/02
Filed: 1997-10-16
Granted: 1998-12-01
Abstract: An optical guide made of a polymer material comprising a a photo initiator and different monomers arranged into a random copolymer, which is characterized in that the first monomer is glycidyl acrylate (2,3-glycidyl acrylate), the second monomer is 2,3,4,5,6-pentafluorostyrene "p-F-St", the photo initiator includes 4,4(phenyl)phenyldiphenylhexafluoro antimonic acid sulfonium and/or triphenylhexafluoro antimonic acid.
Patent TW-360809-B (TW)
Title: Ocular lens material
Inventor: HIRATANI HARUYUKI
IPC: C08F220/00
Filed: 1997-11-05
Granted: 1999-06-11
Abstract: An ocular lens material made of a polymer obtained by polymerizing polymerizable components comprising a monomer of the formula (I), wherein R1 is a group of the formula, wherein R3 is a hydrogen atom or a methyl group, or a group of the formula, R2 is a C1-5 alkylene group, and X is a group of the formula (formula), a group of the formula (formula), a group of the formula (formula), or a group of the formula (formula).
Patent TW-585869-B (TW)
Title: Synthesis of ruthenium or osmium metathesis catalysts
Inventor: GRUBBS ROBERT H
IPC: B01J31/00
Filed: 1997-11-15
Granted: 2004-05-01
Abstract: The present invention relates to the synthesis of highly active ruthenium and osmium carbene metathesis catalyst in good yield from readily available starting materials. The catalysts that may be synthesized are of the general formula, wherein: M is ruthenium or osmium; X and X1 are independently any anionic ligand; L and L1 are any neutral electron donor ligand; and, R and R1 are each hydrogen or one of the following substituent groups: C2-C20 alkenyl, C2-C20 alkenyl alkynyl, C1-C20 alkyl, aryl, C1-C20 carboxylate, C1-C20 is alkoxy, C2-C20 alkenyl, alkenyloxy, C2-C20 alkenyl alkynyloxy, aryloxy, C2-C20 alkenyl alkoxycarbonyl, C1-C20 alkylthio, C1-C20alkenyl alkylsulfonyl and C1-C20 alkenyl alkylsulfinyl. Optionally, the substituent group may be substituted with one or more groups selected from C1-C5 alkyl, halogen, C1-C5 alkoxy, and aryl. When the substitute aryl group is phenyl, it may be further substituted with one or more groups selected from a halogen, a C1-C5 alkyl, or a C1-C5 alkoxy. Specific synthetic protocols for vinyl alkylidene catalysts wherein R is hydrogen and R1 is CHCR12R13 and non-vinyl alkylidene catalysts are also disclosed. In addition to the ease of synthesis (typically a one-step synthesis), the reactions generally may be run at or above room temperature and the resulting products usually may be used without extensive post synthesis purification.
Patent TW-406303-B (TW)
Title: Silicon semiconductor single crystal and the method of manufacturing the same
Inventor: HANEBUKA HITOSHI
IPC: H01L21/312
Filed: 1998-02-26
Granted: 2000-09-21
Abstract: To provide a stable protective film that could be easily removed and is made of silicon semiconductor single-crystal, and the method of manufacturing the same. Adhere directly the organic protective film 4 on the surface of the silicon semiconductor single-crystal. The thickness of the organic protective film 4 is above 0.1 nm, below 10 nm. The organic protective film 4 is formed by the silicon oxidation film containing the organic protective material, or is the protective film formed by the phthalic acid ester containing the phthalic acid diethyl ester or the phthalic acid dioctyl ester. The manufacture method of the surface of the silicon semiconductor single-crystal with the organic protective film 4 is to remove said organic protective film 4 after adhering the organic protective film 4 on the surface of the silicon semiconductor single-crystal formed by the silicon oxidation film 8, and directly adhere said organic protective film 4 on the surface of the silicon semiconductor single-crystal; then, remove said organic protective film 4; finally, proceed the silicon semiconductor single-crystal.
Patent TW-362257-B (TW)
Title: Planarization method of dielectric layer
Inventor: Wang yu-biao
IPC: H01L21/316
Filed: 1998-03-11
Granted: 1999-06-21
Abstract: A kind of planarization method of dielectric layer which after forming the borophosphosilicate glass dielectric layer on the substrate, apply the high temperature thermal flow of the heating process so as to make appearance of borophosphosilicate glass dielectric layer more flat. Then, there forms a protection layer on the borophosphosilicate glass dielectric layer in order to prevent the pittings during the pre-metal etching process.
Patent TW-381403-B (TW)
Title: Apparatus and method for bass enhancement
Inventor: SHASHOUA MEIR
IPC: G10L21/007
Filed: 1998-05-11
Granted: 2000-02-01
Abstract: An apparatus for conveying to a listener a pseudo low frequency psycho-acoustic sensation (Pseudo-LFPS) of a sound signal, including: frequency unit capable of deriving from the sound signal high frequency signal and low frequency signal (LF signal) that extends over a low frequency range of interest. Harmonics generator coupled to the frequency generator and being capable of generating, for each fundamental frequency within the low frequency range of interest, a residue harmonic signal having a sequence of harmonics. The sequence of harmonics, generated with respect to each fundamental frequency contains a first group of harmonics that includes at least two consecutive harmonics from among a primary set of harmonics of the fundamental frequency. Loudness generator coupled to the harmonics generator and being capable of brining the loudness of the residue harmonic signal to match the loudness of the low frequency signal. Summation unit capable of summing the residue harmonic signal and the high frequency signal so as to obtain psycho-acoustic alternative signal.
Patent TW-384525-B (TW)
Title: Manufacturing method for self-aligned contacts
Inventor: LI JIN-HUEI
IPC: H01L21/60
Filed: 1998-06-17
Granted: 2000-03-11
Abstract: A manufacturing method for self-aligned contacts is as follows : forming a thicker dielectric layer on the substrate, then defining the contact in larger size than that of the target contact on dielectric layer, using slope etching until the substrate is exposed; forming a layer of filler on the surface of the dielectric layer and back etching of the filler to a specific depth. Using the top surface of filler for determination of the etching stop for etching the dielectric layer, employing self-alignment process to let the contact on the surface of the dielectric layer reach the target contact size; lastly, according to the requirement of the manufacture process, selectively remove or reserve the filler.
Patent TW-432635-B (TW)
Title: Energy absorbing structures to prevent damage to an integrated circuit
Inventor: SESHAN KRISHNA
IPC: H01L23/58
Filed: 1998-07-14
Granted: 2001-05-01
Abstract: The present invention provides in one embodiment thereof an integrated circuit (IC). The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further includes a terminal metal layer (TML) formed upon the dielectric layer. The dielectric layer and the TML form a die active area. The IC also includes a first guard ring formed out of the TML. The first guard encloses the die active area. Furthermore the IC includes a second guard ring formed out of the TML. The second guard ring encloses the first guard ring.
Patent TW-413863-B (TW)
Title: Method for simultaneously forming oxide layers with different thickness in semiconductor circuit
Inventor: NI CHENG-TSUNG
IPC: H01L21/31
Filed: 1998-10-07
Granted: 2000-12-01
Abstract: A method for simultaneously forming oxide layers with different thickness in semiconductor circuit comprises: providing a semiconductor substrate formed thereon an isolation region; forming a sacrificial layer on the surface of the semiconductor substrate; forming a first photo-resist pattern to protect low-voltage device region; performing a step of implanting fluorine in the high-voltage device region to add impurities into the silicon substrate layer of the high-voltage device region, thereby forming shallow-junction doped area and resulting in a different oxidation rate for the silicon substrate of the high-voltage region in the subsequent oxidation process; sequentially peeling off the photo-resist layer and the sacrificial layer thereby obtaining high-voltage device region and low-voltage device region having different gate oxide thickness; and forming transistor structures of high-voltage device region and low-voltage device region, respectively.
Patent TW-393740-B (TW)
Title: A method for forming the bottom electrode of capacitor
Inventor: HUANG GUO-TAI
IPC: H01L21/8242
Filed: 1998-10-28
Granted: 2000-06-11
Abstract: This is a method for forming the bottom electrode of capacitor. During the manufacturing process of capacitor electrode, when forming amorphous silicon conductive layer, the forming of thickness needed by the amorphous silicon layer is separated into more than one step with dis-contiguous intermittent way, thereby reducing the posibility of generating micropolygon in the amorphous silicon layer, and raising usage ration and increasing economic effect.
Patent TW-392400-B (TW)
Title: Method and system for synchronizing time-division-duplexed transceivers
Inventor: SANDS NICHOLAS P
IPC: H04L5/14
Filed: 1999-05-12
Granted: 2000-06-01
Abstract: Improved techniques for synchronizing transmissions and receptions of a data transmission system utilizing time division duplexing is disclosed. The improved synchronization techniques utilize the time-varying nature of the energy of the received data to obtain synchronization. In one embodiment, an improved synchronization processing (500) measures energy (502) in n consecutive frames of received data. An alignment error es timate is then computed (504) based on the measured energy values for the n consecutive frames. In another embodiment, the improved synchronization technique uses the output signals from a multicarrier modulation unit (FFT unit) and thus provides the ability to avoid frequency tones that are susceptible to RF interference. The improved synchronization techniques can also utilize crosstalk interference levels to obtain synchronization. Remote receivers in the data transmission system are able to synchronize to central transmitters, central receivers in the data transmission system are able to synchronize to remote transmitters, and central transmitters are able to synchronize with one another.
Patent TW-402750-B (TW)
Title: A process for manufacturing a salicide
Inventor: CHOU CHEN-CHENG
IPC: H01L21/28
Filed: 1998-11-25
Granted: 2000-08-21
Abstract: A process for manufacturing a salicide is provided, which comprises the following steps: (a) adopting a silicon substrate with a memory bank unit area and a periphery circuit area; each of the two said areas possess the gate and the source/drain individually and are separated with shallow trench oxide isolation; (b) globally forming a silicon nitride layer or plenty silicon oxide layer; (c) etching the silicon nitride layer or plenty silicon oxide layer in the said memory bank unit area to form a passivation layer in the said periphery circuit area to avoid the production of salicide, and (d) depositing a salicide layer on the surface of the gate, source/drain in the said memory bank unit area. By referencing the process in the present invention, it could avoid the isolation from being over etched.