Patent GB-741587-A (GB)
Title: Improvements in and relating to electrical timing circuits
Inventor: THOMAS DAVID CALDWELL
IPC: G01S1/02
Filed: 1953-10-19
Abstract: 741,587. Phase difference measurements. BRITISH THOMSON-HOUSTON CO., Ltd. Oct. 19, 1953, No. 28802/53. Class 37. [Also in Group XL (c)] Relates to a system for adjustably delaying a marker pulse a relative to a triggering pulse P, the marker pulse being used as a brilliance or deflection range marker on a cathode-ray tube radar display or as a triggering pulse for initiating a succeeding cycle, thereby generating a pulse train having a continuously-variable and accurately known recurrence period as disclosed in Specification 741,580, [Group XL (c)]. According to the present invention the trigger pulse initiates a train of oscillations of period T in a generator 1 which is applied in series to a phase shifter 2, a pulse generator 9, and a plurality of counting stages, 4, 6, 8, each counting stage being adapted to produce a pulse output after a selectable number x of input. pulses and thereafter an output pulse after each group of a predetermined number y of input pulses (x less than y) so that the first output pulse from the nth counter is delayed relative to the triggering pulse P by an integral number N of periods T equal to x 1 +(x 2 Îy 1 )+(x 3 Îy 1 x y 2 )+ . . . +(x n Îy 1 Îy n Î ... Î y n-1 ) plus a fraction α of a period T determined by the setting of the phase shifter. Preferably the first output pulse from the final counter (i.e. the marker pulse a) cuts off the input to the counting chain until the next triggering pulse P occurs. When setting the counters, x 1  is made equal to the remainder obtained on dividing N by y 1 , the resultant quotient being N1; x 2  is made equal to the remainder obtained on dividing N1 by y 2  and so on. Fig. 4 lines B, C, D and E show respectively the input pulses to counters 4, 6 and 8 and the output pulse a from counter 8 for a selected example in which N=138, y 1 =y 2 =5 and y 3 =6 so that the selected values of x 1 , x 2  and x 3  are 3, 2 and 5 respectively. Each counter may be of the type in which the counting factor is determined by the sweep time of a saw-tooth voltage between an initial voltage level M or M<SP>1</SP> and a final voltage level N. When the saw-tooth reaches level N it generates a gate pulse which selects the first succeeding input pulse and the selected pulse retriggers the saw-tooth and is also applied as an input pulse to the next counter. The gating circuit may be of the type disclosed in Specification 729,293, [Group XL (c)]. For the first cycle the saw-tooth is initiated by the trigger pulse P and the initial level M<SP>1</SP> is set by a toroidal potentiometer, Fig. 6 (not shown) in the corresponding " priming " stage 3, 5 or 7 to give the required initial count x; in the succeeding cycles the initial level has a fixed value M giving a fixed count y. The shafts of the phase shifter 2 and of the potentiometers in the priming circuits 3, 5 and 7 may be geared to a single control H and each shaft carries a pointer which indicates on a corresponding dial, Fig. 8 (not shown), the component part x 1 , (x 2  Îy 1 ) of the total delay.