Patent GB-1315150-A (GB)
Title: Data terminal processor
IPC: G06F3/048
Filed: 1970-09-23
Abstract: 1315150 Data processor display INCOTERM CORP 23 Sept 1970 [3 Nov 1969] 45252/70 Heading G4A A data terminal including a display unit 24 and addressable memory 46, has a data processor which is controlled to read characters from the memory 46 and supply them to display unit 24 when that unit is operating at character display positions and to fetch instructions from memory 46 and execute these instructions when display unit 24 is operating at non-display positions, e.g. above and below the area at which a message is to be displayed or in the inter-line spaces of the message. In the described embodiment, display unit 24 includes a CRT which performs two interlaced raster scans to display a complete field. The use of an arrangement in which each individual charater is built up, e.g. by a dot matrix or series of strokes, before the next character in the message is also mentioned. As the CRT screen is scanned, counter 76 counts timing pulses from 94, trace counter 78 is advanced by the overflow of character counter 76 at the end of each horizontal trace, and line counter 80 is advanced at the end of each message line plus space segment. Line counter 80 switches toggle 82 at the end of each field, its contents are also supplied to a subtractor 92 together with the contents of a start line register 90 in which is entered, from memory 46 or a keyboard, the position of the first message line. The output of subtractor 92 together with the contents of counters 76, 78 cause a control unit 96 to maintain the processor in a non- refresh mode until just before the first message line position. In the non-refresh mode, an instruction address in program counter 66 is fed over bus 86 to an auxiliary arithmetic unit 84 and thence to register 87 and memory address register 48 to cause read-out from memory 46 to memory data register 50 for execution. Program counter may be modified by AAU 84 and thus need only be a simple register. When control unit 96 produces a refresh request signal just prior to the first message line, the processor completes execution of the current instruction and is switched to the refresh mode, the status of the last instruction being held in program counter 66 and accumulator register 60. In the refresh mode, the addresses of characters to be displayed are formulated by AAU 84 from the character counter 76 and subtracter 92 which gives the message line number relative to the start-line. Each such address in fact causes read-out of two adjacent characters and the last bit of MAR 48 selects one character or the other from MDR 50 for supply to display 24. The complement of register AAR 87 is then supplied to AAU 84 together with the contents of a cursar register 68 which stores the position at which a cursor pattern is to be displayed, and an indication that this position is being scanned is given by a zero output from AAU 84 at this point. Toggle 82 increments a counter in a timer 83 to cause a flashing cursor pattern to be displayed. Control unit 96 also decodes the trace counter contents to maintain a refresh operation during line traces below the start line but to cause switching of the processor to the compute mode during inter-line space traces, compute operation being resumed at the point indicated by program counter 66. A last line register 102 and comparator 104 may be provided to allow switching to compute operation after display of the last message line, but preferably this function is achieved using an end of message character which is decoded to signal unit 96.