Patent GB-1220138-A (GB)
Title: Control and supervisory apparatus for program interrupt requests arising in computer systems
Inventor: HARMON SHERRIL ALLAN
IPC: G06F9/48
Filed: 1968-05-14
Abstract: 1,220,138. Program interruption arrangements. GENERAL ELECTRIC CO. 14 May, 1968 [3 July, 1967], No. 22908/68. Heading G4A. In a computer system having provision for servicing main program interrupt requests, means are provided for checking that an interrupt request is serviced before a similar request occurs and for generating an error signal if this condition is not met. As shown (Fig. 1), main program interrupt requests, for example from a peripheral unit 153, are stored in automatic program interrupt unit 15 and scanned in order of priority to generate, when accepted, an address for accessing from magnetic core memory 13 an associated word comprising a control word instruction or one of a sequence of instructions for servicing of the accepted request by arithmetic and control unit 10. Interrupt request source 152 generates periodic square-wave clock signals ARTC (Figs. 8-10, not shown) defining periods in which interrupt requests may be serviced and an interrupt monitor 150 (see below) checks that the aforementioned conditions regarding servicing of requests are observed. Automatic program interrupt unit 15 (Fig. 2). Program interrupt requests are stored in flipflops 130, highest priority to the left, and an address generator 132 scans these requests in turn starting from the left. On finding a match between address generator 132 and a stored request, address comparator 131 signals generator 132 to stop scanning whereupon the address on line 12<SP>1</SP> identifying the accepted request is used to cause the contents of the corresponding location in main memory 13 to be read into the control unit 10. The flip-flops 130 are time-shared with a further set of similar flip-flops (Fig. 3, not shown) which are set respectively by the timing signals ARTC, peripheral interrupt signals DAPI and signal DECH from echo generator 136 and which indicates that a counter (e.g. a real time cock (counter) has been decremented to - 1. The outputs from these latter flip-flops are utilized by the interrupt monitor 150 (see below) and they also control program interuption for the following purposes respectively: decrement real time clock and test, service peripheral interrupt request and reset real time counter to initial count. Signal FPMT to unit 135 originates from a program instruction settable flip-flop PMT (Fig. 4, not shown) which controls the selective inhibiting of certain ones of the interrupt requests. Interrupt monitor 150 (Fig. 6, not shown). Said further set of flip-flops (Fig. 3, not shown) are reset when signals indicating that the corresponding request has been serviced are received. The monitor 150 detects, by means of AND-gates, the presence of a set flip-flop of this set and a new request or setting signal for the same flip-flop (or, in the case of the flip-flop set by signal DECH, a special timing signal). The outputs of these AND-gates are combined and manipulated to generate signals on the one hand to suppress normal processing operations and the request inhibiting flip-flop and on the other hand to force the control unit 10 into accessing corrective action instructions from memory 13. Since said set of further flip-flops are set by the negative going or trailing edges of the control signals and the AND-gates of the interrupt monitor are opened by the positive going or leading edges, a delay period is thereby provided during which a stored request can be serviced and as a result no interrupt requests are lost.