baber/WOPTO huggingface dataset:
Patent TW-444278-B (TW)
Title: Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor
Inventor: KANG SANG-BOM
IPC: H01L21/768
Filed: 2000-03-22
Granted: 2001-07-01
Abstract: A method of forming a metal layer having excellent thermal and oxidation resistant characteristics using atomic layer deposition is provided. The metal layer includes a reactive metal (A), an element (B) for the amorphous combination between the reactive metal (A) and nitrogen (N), and nitrogen (N). The reactive metal (A) may be titanium (Ti), tantalum (Ta), tungsten (W), zirconium (Zr), hafnium (Hf), molybdenum (Mo) or niobium (Nb). The amorphous combination element (B) may be aluminum (A1), silicon (Si) or boron (B). The metal layer is formed by alternately injecting pulsed source gases for the elements (A, B and N) into a chamber according to atomic layer deposition to thereby alternately stack atomic layers. Accordingly, the composition ratio of a metal layer (A-B-N) can be desirably adjusted just by appropriately determining the number of injection pulses of each source gas. According to the composition ratio, a desirable electrical conductivity and resistance of the metal layer can be accurately obtained. The atomic layers are individually deposited, thereby realizing excellent step coverage even in a complex and compact region. A metal layer formed by atomic layer deposition can be employed as a barrier metal layer, a lower electrode or an upper electrode in a semiconductor device.
Patent TW-445710-B (TW)
Title: Surface acoustic wave resonator, surface acoustic wave device, and communication device
Inventor: NAKAO TAKESHI
IPC: H03H9/25
Filed: 2000-04-24
Granted: 2001-07-11
Abstract: A surface acoustic wave resonator includes a piezoelectric substrate and an interdigital transducer disposed on the piezoelectric substrate and made of a metal or an alloy having a higher specific weight than that of the piezoelectric material of the piezoelectric substrate so as to generate shear horizontal waves. The interdigital transducer includes a plurality of electrode fingers. A ratio of the electrode finger width relative to the electrode finger width plus the space between adjacent electrode fingers is about 0.55 to about 0.85.
Patent TW-434365-B (TW)
Title: Structure of inner wall of cylinder or cylinder sleeve and the manufacturing method thereof
Inventor: HUANG YUN-FU
IPC: F02F1/08
Filed: 2000-04-24
Granted: 2001-05-16
Abstract: Disclosed is a structure of inner wall of cylinder or cylinder sleeve and the manufacturing method thereof, comprising the steps of: machining the internal wall of the cylinder or the cylinder sleeve into an sunken area having a spiral-shape or other patterns, covering the entire or part of the surface of the inner wall with a layer of metallic or non-metallic material harder than the original inner wall material by melt-injecting or electroplating method, grinding the inner wall to remove the metallic or non-metallic material covered on the protruding portion of the inner wall by internal diameter polishing method, to make the inner wall having the surface constructed with areas alternate soft and hard materials, so as to make the inner wall possessing the efficacy of easy heat dissipation, better oil-bearing property, high hardness, better smoothness, and excellent wear resistance.
Patent TW-534918-B (TW)
Title: Polymer foam and method of making using oil-containing furnace black as an insulation enhancer
Inventor: CHAUDHARY BHARAT I
IPC: C08G18/00
Filed: 2000-06-16
Granted: 2003-06-01
Abstract: A closed-cell polymeric foam is provided which is formed using oil-containing furnace black as an insulation enhancer. Other foam properties (for example, cell sizes, densities, limiting oxygen index performance) are similar to those obtained with the use of thermal blacks. A polymer foam prepared from a foamable polymeric material that contains a quantity of furnace black sufficient to reduce foam thermal conductivity below that of a corresponding foam prepared from the same foamable polymeric material save for omission of the furnace black, said furnace black having from 3-10% by weight oil incorporated therein, based on total furnace black weight.
Patent TW-465081-B (TW)
Title: Non-volatile semiconductor memory device
Inventor: KAWAMURA SHOICHI
IPC: G11C16/06
Filed: 2000-06-19
Granted: 2001-11-21
Abstract: A non-volatile semiconductor memory device comprises a plurality of memory cell units each of which includes a plurality of non-volatile memory cells capable of having data electrically rewritten; a storage unit; and an access inhibiting circuit. The storage unit stores therein the defect information of the memory cell unit not normally operating. The access inhibiting circuit judges the condition of the memory cell unit within the device according to the defect information stored in the storage unit. Access to the memory cell unit not normally operating is inhibited in accordance with the result of the judgement. Since the device can control the information of the memory cell unit not normally operating by itself, users of the device need not manage the defective memory cell unit. Consequently, the usability of the device is enhanced and the cost of a system mounting the device is curtailed. Particularly, it is effective for the non-volatile semiconductor memory device for file allowing the presence of inoperative memory cells.
Patent TW-558552-B (TW)
Title: Substituted phenyl propionic acid derivatives as human peroxisome proliferative drug activate receptor (PPAR) alpha antagonist
Inventor: NOMURA MASAHIRO
IPC: C07C323/60
Filed: 2000-06-21
Granted: 2003-10-21
Abstract: Novel substituted phenyl propionic acid derivatives which can be as human peroxisome proliferative drug activate receptor alpha (PPAR alpha) ligand binding to receptor and activated. Showing strong reduction action to lipemia (cholesterol and neutrolipid) are provided. Concerning to substituted-phenyl-propionic acid derivatives of formula (1) and its pharmaceutical acceptable salt and hydrate thereof and their preparation.
Patent TW-589930-B (TW)
Title: Electrostatic discharge protection device for a high density printed circuit board
Inventor: ARLEDGE JOHN K
IPC: H05K9/00
Filed: 2001-02-14
Granted: 2004-06-01
Abstract: An electrostatic discharge protection device for a high-density printed circuit board consists of a layered structure starting at the bottom layer with a ground conductor (10). A dielectric layer (30) covers the ground conductor to electrically isolate it from a circuit trace (50) that is on top of the dielectric layer. A via (40) is formed in the dielectric layer such that a portion (15) of the ground conductor is exposed, and the via is strategically located such that the edge of the via is tangent to an edge portion (52) of the circuit trace. The via forms a spark gap between the edge portion of the circuit trace and the underlying ground conductor, using air as the dielectric medium.
Patent TW-I224440-B (TW)
Title: System and method for managing storage resources in a clustered computing environment
Inventor: TAWIL AHMAD H
IPC: H04L69/14
Filed: 2001-02-26
Granted: 2004-11-21
Abstract: A system and method for managing storage resources in a clustered computing environment are disclosed. A method incorporating teachings of the present disclosure may include holding a reservation on a storage resource for a first node of a clustered computing environment. A third party process log out for the first node may be performed and the reservation held for the first node may be released.
Patent TW-478212-B (TW)
Title: Electrical connection system
Inventor: SHIRAKI KAZUAKI
IPC: H01R13/639
Filed: 2001-03-01
Granted: 2002-03-01
Abstract: An electrical connection system includes a first component 2 for supporting a first electrical connector element 13 and a second component 3 engaged with the first component 2 and supporting a second female electrical connector element engageable with the first male electrical connector element 13. A shorting element 4 is mounted in advance on the first component 2, for electrically shorting the first male electrical connector element13. A latch element 5 is latched in advance in a first position with respect to the second component 3. By pressing the latch element 5, the second component 3 is engaged with the first component 2 and simultaneously the latch element 5 latched in the first latching position is released and is pressed further to the second latching position in which the shorting of the shorting element 4 is released by the latch element 5.
Patent TW-490813-B (TW)
Title: Cell array, operating method of the same and manufacturing method of the same
Inventor: YAMAUCHI YOSHIMITSU
IPC: H01L21/8247
Filed: 2001-03-02
Granted: 2002-06-11
Abstract: A cell array comprising a nonvolatile memory cells having; a floating gate formed on a semiconductor substrate with the intervention of a first insulating film; a split gate formed with the intervention of a second insulating film at a predetermined distance from the floating gate; a control gate formed at least on the floating gate with the intervention of a third insulating film; and an impurity diffusion layer formed in a surface layer of the semiconductor substrate and capacitively coupled with an edge of the floating gate on an opposite side to the split gate in an X direction in parallel with a channel direction; wherein two or more cells are arranged in matrix along the X direction and a Y direction vertical to the X direction, the floating gates and the split gates are alternately arranged in the X direction and the impurity diffusion layer of one cell is capacitively coupled with a split gate of another cell adjacent to said' one cell in the X direction, the control gates of the cells arranged along the X direction are commonly connected along the X direction, the impurity diffusion layers of the cells arranged along the Y direction are commonly connected along the Y direction, and the split gates commonly connected along the Y direction are also commonly connected alone the X direction through at least one conductive layer.
Patent TW-513388-B (TW)
Title: Apparatus and method for etching glass panels
Inventor: CHEN TAI-HONG
IPC: C03C15/00
Filed: 2001-04-04
Granted: 2002-12-11
Abstract: An apparatus and a method for etching a plurality of glass panels are disclosed. The apparatus is constructed by mounting a panel holder in an etch tank equipped with a rotating means for rotating the panel holder during the etching process. The panel holder is adapted for receiving a plurality of glass panels and mounting the panels in a vertical position with at least two edges of the panels mounted in a plurality of tracks for protecting conductive elements formed on the edges of the panels and also for holding the panels securely during the rotation of the panel holder. The method for etching the panels can be carried about at a rotational speed between about 5 rpm and about 60 rpm in an etchant solution of a diluted acid such as HF having a concentration of at least 5 vol.%. A suitable immersing time for the plurality of glass panels in the diluted etchant for producing panels of smaller thicknesses is at least 3 min.
Patent TW-499730-B (TW)
Title: Dielectric layer for semiconductor device and method of manufacturing the same
Inventor: LEE JOHGHOI
IPC: H01L27/108
Filed: 2001-05-10
Granted: 2002-08-21
Abstract: A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.
Patent TW-500607-B (TW)
Title: Medicated wrap
Inventor: HYSON MORTON I
IPC: A61K9/70
Filed: 2001-05-16
Granted: 2002-09-01
Abstract: A device for treating pain in an injured body member includes a wrap having an interior section which can be loaded with medicament. The wrap also includes at least one inwardly extending nodule adapted to exert pressure on and compress a specific area of the injured member, having acupressure like effect in producing pain relief. The wrap has adjustable means for fastening the wrap around the body member, thereby enabling the wearer to extent a specific amount of pressure on the nodule to achieve the desired results. The combination of restricted movement imparted by the wrap along with the medicament and acupressure affords the wearer more rapid pain relief than any of the treatments applied separately.
Patent TW-593600-B (TW)
Title: Composite molding comprising polyarylene sulfide and silicone rubber
Inventor: REIL FRANK
IPC: B29C48/03
Filed: 2001-05-18
Granted: 2004-06-21
Abstract: The present invention describes a composite molding comprising at least one polyarylene sulfide and comprising at least one silicone rubber having one or more components. The present invention further describes a process for producing of a composite molding, where molding-on is carried out in a single-stage process. Finally, the present invention describes the use of a composite molding as a housing, such as a pump housing or as a resonator.
Patent TW-486787-B (TW)
Title: Self-limiting polysilicon buffered LOCOS for DRAM cell
Inventor: NESBIT LARRY A
IPC: H01L21/8242
Filed: 2001-06-01
Granted: 2002-05-11
Abstract: A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.
Patent TW-513871-B (TW)
Title: Communication system provided with control apparatus between local network and external network
Inventor: TAKEYAMA HIROAKI
IPC: G08B25/01
Filed: 2001-06-14
Granted: 2002-12-11
Abstract: A communication system includes a local terminal apparatus connected with a local network, a remote terminal apparatus connected with an external network, and a control apparatus interposed between the local network and the external network. The local terminal apparatus includes a reply section for returning an answer signal including a status information of a processing executing section via the local network in response to a request signal received via the local network. The control apparatus includes a gateway section for receiving the request signal transmitted from the remote terminal apparatus via the external network, and thereafter, transmitting the received request signal to the local terminal apparatus via the local network, and for receiving an answer signal corresponding to the request signal from the local terminal apparatus via the local network, and thereafter, transmitting the received answer signal to the remote terminal apparatus via the external network.
Patent TW-I222039-B (TW)
Title: Information conversion system
Inventor: IWANE WARO
IPC: G06T7/00
Filed: 2001-06-22
Granted: 2004-10-11
Abstract: The present invention provides an information conversion system, which comprises: a database (300) for registering attribute data and identification codes for various objects containing three-dimensional shape data of modularized parts; a comparison part generation portion (400) for generating comparison part information from the attribute data of each part; an input portion (100) for obtaining the inputted image containing the image for the object; a comparison image generation portion (200) for performing image processing on the inputted image, and generating the comparison image information without clipping on the image of the object; and, a specific processing portion (500) for searching the portion corresponding to the comparison part information from the comparison image information and specifying the part containing the comparison part information as the part corresponding to the image of the object when using the corresponding portion in the comparison image information as the object image for identification.
Patent TW-483114-B (TW)
Title: Local formation method of metal silicide
Inventor: CHEN YING-TSO
IPC: H01L21/768
Filed: 2001-07-25
Granted: 2002-04-11
Abstract: This invention provides a method to form metal silicide locally on an integrated circuit and prevent the leakage current occurrence due to formation of metal silicide on the adjacent memory cells of the same word line. The invention achieves the desired purpose by properly arranging the distance among devices according to the design rule. In an embodiment of the present invention, in order to avoid forming metal silicide on the adjacent memory cells of the same word line during formation of metal silicide on integrated circuit, a dielectric layer is formed on the separation region between the adjacent memory cells in advance to function as mask. Therefore, the subsequent selective etching step will not expose the silicon substrate on the protected separation region and thus there is no formation of metal silicide in the separation region.
Patent TW-518738-B (TW)
Title: Chip with built-in CMOS having whole-chip ESD protection circuit with low capacitance
Inventor: HUNG GEN-GANG
IPC: H01L23/60
Filed: 2001-09-24
Granted: 2003-01-21
Abstract: A kind of chip with built-in CMOS having whole-chip ESD (electrostatic discharge) protection circuit with low capacitance is disclosed in the present invention for protecting the internal circuit in the chip. The first voltage source and the second voltage source are provided to the ESD protection circuit, which is connected between the pad and the internal circuit. The ESD protection circuit includes the first diode string, the second diode string, the first control circuit, the third diode string, the first SCR, the second control circuit, the fourth diode string and the second SCR. The ESD protection circuit uses the control circuit to perform substrate trigger for reducing the SCR conduction voltage and increasing the holding voltage when SCR is in a conduction state so as to have whole-chip ESD protection function and reduce the input capacitance.
Patent TW-532017-B (TW)
Title: Gated clock recovery circuit
Inventor: DUNLOP ALFRED EARL
IPC: H04L7/00
Filed: 2001-10-18
Granted: 2003-05-11
Abstract: A gated clock recovery circuit is disclosed that receives an input data stream and generates a frequency and phase aligned clock output. The gated clock recovery circuit substantially instantaneously adjusts the generated clock signal to phase changes in the incoming data stream. In addition, the gated clock recovery circuit generates the clock output signal using only transmitted non-predetermined data. The gated clock recovery circuit includes two PLL circuits. The first PLL (PLL1) adjusts to the frequency of the transmitter, and provides a bias voltage, CAP1, to the second PLL (PLL2) to indirectly initially tune the second PLL. The bias voltage, CAP1, is applied to the second PLL through a transmission gate (or switch) that is initially in a closed (short) position. Thus, the first PLL drives the bias voltage, CAP2, of the second PLL, to align the frequency with the transmitter, until received data opens the transmission gate. Thereafter, the bias voltage, CAP2, is removed and the second PLL can operate without being controlled by PLL1 so that the second PLL oscillates in phase with the received data. Simultaneously, the received data starts the oscillator in the second PLL so that the second oscillator is in phase with the received data. The second PLL then maintains this phase relationship between the second oscillator and the received data.
Patent TW-I272653-B (TW)
Title: Method for exposing a semiconductor wafer
Inventor: SCHEDEL THORSTEN
IPC: G03F7/20
Filed: 2001-10-29
Granted: 2007-02-01
Abstract: A method for exposing a semiconductor wafer is provided, which provides a compensation of the effects of process inhomogeneities, e.g. in semiconductor etching or deposition processes, by adjusting sets of exposure parameters (30), preferably dose and focus, of an exposure tool for any exposure field (21) individually across a semiconductor wafer (10).
Patent TW-536752-B (TW)
Title: Compensation type CMP method and apparatus
Inventor: LAI JE-SHIUNG
IPC: B24B37/013
Filed: 2001-11-26
Granted: 2003-06-11
Abstract: A compensation type CMP method and apparatus are introduced. The wafer is polished by a main polish head whose diameter is smaller than that of the wafer and compensation polish head, wherein the polish surface of the wafer faces upward and the polish pad is pasted on the polish head. The use of the compensation polish head can proceed the compensation polish on the region that the main head cannot effectively and uniformly polish. This method is better than the traditional polish method and can improve the shortcoming of the traditional method. The flatness and uniformity are good, the end point detection is easier, the slurry quantity is reduced and the volume of the machine is also reduced.
Patent TW-592927-B (TW)
Title: Detergent
Inventor: ITOH MIKIHITO
IPC: C11D1/22
Filed: 2001-12-10
Granted: 2004-06-21
Abstract: A detergent comprising ethanol and limonene is provided, which is used for removing deposits from molds for thermoplastic resin molding. The deposit which has adhered to the surface of a mold during the molding of a thermoplastic resin (the so-called mold deposit) and the anticorrosive, release agent, and lubricant can be easily removed by cleansing with the detergent. The detergent for mold deposit removal is preferable from the standpoint of working atmosphere and is applicable to a wide range of thermoplastic resins.
Patent TW-I231208-B (TW)
Title: Fitness device for rehabilitating and hygienic use
Inventor: GUO YI-SHIN
IPC: A61H1/02
Filed: 2001-12-11
Granted: 2005-04-21
Abstract: This invention provides a kind of fitness device for rehabilitating and hygienic use. The disclosed device comprises mainly a permeable flywheel which is driven to rotate by the motion force of a rehabilitant; a permanent magnet set, which is driven to rotate by the electro-driven device, which is spaced at interval away from the rim of the flywheel. By means of rotating the permanent magnet set on the electro-driven device and adjusting the relative speed between the magnet set and the flywheel to change the assistance or resistance value, the amount of exercise of rehabilitants can be controlled, attaining better rehabilitating and hygienic effect.