Patent GB-1363154-A (GB)
Title: Data converter for a computer systems
IPC: H03M7/30
Filed: 1971-08-27
Abstract: 1363154 Data packing NIPPON ELECTRIC CO Ltd 27 Aug 1971 [28 Aug 1970] 40388/71 Heading G4A [Also in Division H4] A hardware data conversion apparatus is arranged to pack numeric and alpha-numeric n bit characters into m bit bytes and to unpack m bit bytes into n bit numeric and alpha-numeric characters. In an embodiment the numeric characters consist of four significant (BCD) bits and two non-significant bits which identify the character as being numeric and the alpha-numeric characters consist of six significant bits. Successive characters are packed into eight bit bytes such that a byte in which the last four bits are all "1" is a single numeric character given by bits 1-4, a byte in which bits 3 and 4 are both "1" is a single alpha-numeric character given by bits 1, 2 and 5-8, and any other byte is two numeric characters given by bits 1-4 and 5-8 respectively. Data, e.g. from a computer, is fed into a six bit register, the last two bits being zero for a numeric character. A gate circuit generates an output on line 63 in response to those last two bits to set and reset flip-flop 34, Fig. 6A, according to whether the data represents a numeric or alpha-numeric character respectively. The flipflop is actually set or reset on the occurrence of an output on line 101 from multivibrator (MV) T1 which is energized by a "start conversion" signal on line 64. The output of T1 triggers T2 whose output is fed to the AND gates 124-128 and to gate 107. Assuming that the data is a numeric character, flip-flop 34 will be set and its output is passed to gates 124 and 125 and, via OR gate 123, to AND gate 107, which, via OR gate 109 triggers T3. Meanwhile, AND gate 124 will conduct (all its inputs, i.e. the outputs of T2, set output of 34, and reset output of 35, being 1) and generate a signal M1 which is passed to a gating system, Fig. 9. It will be apparent from Fig. 9 that the signal M1 causes the first four bits of the six bits being converted to be loaded into the first four bit positions 1, 2, 4, 8 of a byte register (not shown). When T3 triggers its output enables gates 117 and 118, causing flip-flop 35 to assume the state of flipflop 34, i.e. set, and the six bit register to be loaded with the next character by means of a signal in one of the group of lines 66. T3 triggers T4, whose output resets flip-flop 34, but is blocked at AND gate 138 due to the state of flip-flop 35. The process then repeats. However, if the new character is alpha numeric (i.e. six bits) it will not fit into the remaining byte positions and the system operates (by having flip-flop 34 reset) to generate by means of gate 127 a signal M4 which loads four 1's into the remaining byte positions, see Fig. 9. If the next character is numeric a signal M2 is produced by gate 125 and the relevant four bits are loaded into the remaining byte positions. Following the filling of the remaining bit position of the byte a signal 75 is generated either in response to the output of T4 together with a reset output from flip-flop 35 or to the output of T2 together with a set output from flip-flop 34 and a set output of flip-flop 35. The signal 75 causes the assembled byte to be loaded into an output register, the byte register being cleared. The operation is analogous for an alpha-numeric character, flipflop 34 remaining reset due to the presence of a 1 bit in one of the last two positions of the six bit register. The reverse conversion is performed by the device shown in Fig. 6B. In response to a start signal multivibrator S1 is triggered. The output of S1 by means of a gating circuit sets flipflop 37 if the last four bits of the byte being converted are 1's, sets flip-flop 38 if bits 3 and 4 of the byte are 1's, and sets neither flip-flop otherwise. In a manner analogous to that of Fig. 6A, signals N1, N2 and N3 are generated, in response to the triggering of the multivibrators S1-S6 and the states of flip-flops 37 and 38, to load various bits from the byte register into a six bit register, see Fig. 10. The six bit register contents are transmitted and the register cleared in response to signals on line 65. The possibilities of using characters represented by different numbers of bits and the inclusion of parity bits are mentioned.