Patent GB-950097-A (GB)
Title: Improvements in or relating to pulse code modulation systems
Inventor: CLEMETT COLIN JOHN
IPC: H04B14/04
Filed: 1961-03-08
Abstract: 950,097. Pulse code modulation multiplex system. GENERAL ELECTRIC CO. Ltd. March 7, 1962 [March 8, 1961], No. 8577/61. Heading H4L. A pulse code modulation multiplex system comprises means for sampling each channel signal and comparing the amplitude of the sample signal with a linearly increasing ramp signal, means for counting the number of pulses supplied by a pulse generator during the period between the commencement of the ramp signal and the time of its coincidence with the sample signal, said pulse generator supplying pulses at a varying pulse recurrence frequency such that the number of pulses generated per unit amplitude variation in sample signal is greater for low amplitudes of signal, means for trans-  mitting the number of pulses counted and receive terminal equipment for reconstituting the channel signals. A six channel system is described, each channel being sampled during the same pulse period. Pulse generator.-The equipment shown in Fig. 2 is common to all channels and is provided at both transmit and receive terminals. It includes an oscillator 13 which produces a pulsed output signal at a frequency of 1 Mc/s., a bi-stable circuit 14 which divides the frequency of this signal by two and supplies a 500 kc./s. output signal which is further divided in bistable circuit 15 to provide an output pulsed signal at 250 kc./s. This signal is supplied to a six stage binary counter 16, each stage of which is connected to a diode matrix 17 which recognises and provides an output pulse at its terminals 19-24 when the counter registers 11, 16, 21, 26, 36 and 37 pulses, respectively. The first four of these output pulses act on bi-stable circuits 25, 26, 27, controlling gates 28, 29, 30, such that during the periods the counter counts 0-11 pulses, 11-16 pulses, 16-21 pulses, 21-26 pulses and over 26 pulses, a pulsed signal at recurrence frequencies of 250 kc./s., 500 kc./s., 1 Mc/s., 500 kc./s. and 250 kc./s. respectively, is supplied from osc. 13 and bi-stable circuits 14 and 15 to terminal 32. The registration of the 36th and 37th pulses trigger on and off, respectively, a clamp signal generator 5 which supplies an output to terminal 33 and the registration of the 37th pulse starts the cycle of a ramp signal generator 7 and also resets counter 16 for the next frame of 37 pulses. On registration of the 36th pulse in the next frame, the ramp signal cycle is terminated. Transmit terminal.-The apparatus provided for each channel is shown in Fig. 1. Each channel is sampled in a network 4 by a clamp pulse supplied from terminal 33, Fig. 2. A D.C. component, equal to the maximum sample signal obtainable, is added to the sample pulse and the resultant is applied, with the ramp signal, to a comparator 6. During the period between the commencement of the ramp signal and the time its value coincides with the resultant signal, the comparator provides a signal which opens a gate 8 and allows counting pulses, supplied from terminal 32, Fig. 2, to be applied to a six-stage binary channel counter 10. The ramp signal is arranged to increase to an amplitude which exceeds the maximum possible resultant signal by a small amount, hence a low amplitude sample signal coincides with a ramp signal at approximately midamplitude. Since the ramp signal increases during the period between the 37th pulse of one frame and the 36th pulse of the next frame, coincidence for low amplitude signals occurs when the pulse recurrence frequency of the signal at terminal 32 is a maximum. As a result, the number of pulses counter per unit amplitude of sample signal is greatest for low amplitude signals. On the occurrence of the next clamp pulse at terminal 33, the count in channel counter 10 is transferred to a six stage channel output register 12 which is connected in series with the registers 37, 38, 39, &c. of the other five channels. Clock pulses from terminal 35, Fig. 2, transfer the stored information to line for transmission via amplifier 40. The 37th digit position is occupied in alternate frames by a pulse supplied from bi-stable circuit 42 which is triggered on and off by succeeding clamp pulses. This pulse is used for synchronizing purposes. Receive terminal.-Six series connected, six stage channel registers are provided to receive the transmitted signal, each register being associated with one channel. On receipt of a clamp pulse from terminal 33 of the apparatus shown in Fig. 2 provided at the receive terminal, the binary number stored in e.g. register 46 is transferred to a channel input register 51 and counting pulses at the same varying pulse recurrence frequency as were provided at the transmit terminal are fed to a coincidence counter 53. On coincidence between the counts in register 51 and counter 53, a circuit 52 supplies a pulse to a network 54 which samples the ramp signal supplied from generator 7. The sample signal is applied at the next clamp signal, via an integrating filter 56 and amplifier 57 to the relevant channel. The 37th pulse present in alternate frames is compared in a synchronizing detector 61 with a similar pulse generated by the receive terminal clamp generator.