Patent GB-770952-A (GB)
Title: Electronic digital computers
IPC: G06F15/78
Filed: 1953-11-25
Abstract: 770,952. Digital electric calculating-apparatus; electric digital-data-storage apparatus. NATIONAL CASH REGISTER CO. Nov. 25, 1953 [Dec. 10, 1952], No. 32718/53. Class 106(1). An electronic digital computer comprises an arithmetic unit including logical circuits, and a programme counter operable in predetermined sequential steps and producing output signals which render the logical circuits selectively operable. General arrangement. The computer described comprises a magnetic storage drum 100, Fig. 1, arithmetic unit 112, manual input and control panel 129, and output equipment comprising a typewriter 130 and magnetic tape 134. The drum 100, rotated by a motor 104, has a channel 108 from which clock pulses are obtained by a read head 110 connected to scaleof-three and scale-of-fourteen counters 121, 122 for defining the binary digit periods P 0 -P 2  (see Figs. 2 and 3) within an octal digit period and the octal digit periods O 0 -O 13  within a " word " (number or command) respectively; a synchronizing channel Ch17, Fig. 5, providing a signal in position P 0  O  13  of each word; and an " arc address " channel Ch 16  containing numbers 0-63 defining the addresses of each of the 64 words which may be recorded around each of the main memory channels Ch15-Ch0. The read/record heads associated with channels Ch17-Ch0 are connected to the unit 112 through gating circuits 119 which are controlled by a series of bi-stable hard valve trigger cir. cuits (called " flip-flops ") A1-A5 so as to select only one channel at a time. The unit 112 also receives words continuously recirculated in loops or registers E, F, G, each compris. ing read and record heads, such as 117, 116, so spaced around a channel on the drum to provide a total delay of one word length in the loops; the unit consists primarily of connections between flip-flops, the connections comprising a diode gating network 168, Fig. 22, corresponding to given logical algebra equations. The operating sequence is determined by a programme counter 118 which is controlled by a flip-flop K1 so as either to step on to the next value or to skip to another value at the end of each word period. Number and command codes. Each word may consist of a binary number, Fig. 2, or a command, Fig. 3. The number comprises 36 digits in positions O 0 - O 11 ; the sign (" 1 " for plus) is placed in position P 0  0 12  and an overflow digit in P 1 O 12  (all numbers are regarded as lying between +1 and -1). The command comprises addresses m 1 , m 2  and m 3  in positions O 11 -O 8 , O 7 -O 4 , and O 3 -O 0  and an instruction I in O 13 -O 12 . Each address is divided into an arc address portion (a) containing a binary number from 0 to 63 and a channel address portion (c) containing a binary number from 0 to 15. The instruction comprises " 1 " in P 0  O 12'  " 0 " in P 2  O 13  and the instruction proper, viz. one of fourteen combinations of four binary digits indicating the function to be performed, in positions P 1  O 13 -P 1  O 12 . In general, the command involves placing the words in main memory addresses m 1 , m 2  in registers E, F respectively, operating on these words in unit 112 in accordance with the instruction, and placing the result of the operation, found in E, into main memory address m 3 . Clock pulse counters; trigger circuits. The counters 121, 122, Figs. 1 and 22, comprise respectively two and four trigger circuits or flip-flops B1-B2, D1-D4 so connected by diode gating networks as to count in normal binary fashion up to 3 and 14 respectively and then return to zero. Counter 121 is stepped on by each clock pulse C and counter 122 by each clock pulse occurring during a period P 2  defined by 121. Signals defining the different periods within a word are obtained from diode matrix networks (Figs. 20 and 21, not shown) controlled by the counter flip-flops. All flipflops in the counters and elsewhere in the computer are similar to B1, Fig. 16, which comprises a pair of anode-to-grid cross-connected triodes 264a and 264b having their grids connected through blocking diodes and R.C. differentiating circuits to diode input networks 274, 273. If all the inputs to the diodes in a network are positive, the negative-going edge of the clock pulse C will be differentiated and will trigger the flip-flop to the opposite condition. Each flip-flop is regarded as representing a logical proposition. For example, if flip-flop B1 registers " 1," the corresponding proposition is " true " and output B 1  is at a high potential (indicated by neon lamp 270), otherwise B1<SP>1</SP>. The inputs for triggering the flip-flop to the " true " and " false " state are designated b 1 , ob 1  respectively and are operative only when associated local algebra equation expressed in terms of the outputs of the same and/or other flip-flops, are satisfied (i.e. give a resultant high potential). Programme counter and performance of instructions. The counter 118, Fig. 1, comprises flip-flops N1-N8 which are so connected by diode gating networks as to count in normal binary fashion, starting from zero, in response to clock pulses at times P 2  O 13  as indicated by horizontal connecting lines in the flow diagram of Fig. 23. If, however, the discriminating flip-flop K1 is in the " 1 " or true state at the end of a word period, the counter skips or stays in the same condition as indicated by the vertical lines. When the computer is idling, K1 is in the " 1 " state and the counter remains in the " 0 " condition due to connection 318. When a " start " flip-flop S1, Fig. 22, has been triggered, K1 is set to " 0 " and the normal count begins, a branch-off occurring at one of the stages as indicated (due to K1 again being set to " 1 ") in accordance with the operations to be performed. The branches from stages 1-3 corresponding to filling the computer from the control panel 129, Fig. 1. Stages 4-7 are used for obtaining a command from the memory. During each of stages 8-13, 18, 24-28 and 33, " 1 " is added to the instruction in positions P 1  O 13 -P 1  O 12  of the command; if a carry is produced as a result of this addition (i.e. if I=1111), K1 is set to " 1 " at time P 2  O 13  and the counter follows the branch routine corresponding, to the instruction. The instructions, which are described separately below, are halt (H), fill (F), record (P1-P4), test (To, T), extract (E), subtract (S), add (A), shift (Sh), multiply (M), divide (D). Stages 14-17 and 19-23 are used for reading out from addresses m 1'  m 2  and stages 29-33 are used for transferring data from G to address arc O, Ch0 prior to multiplication or division. Stages 41-44 are used for putting away the result in address m 3 . The outputs from flip-flops N1-N8 are applied to a decoding diode matrix (Fig. 35, not shown) to provide a potential on a single line corresponding to each of the 140 states of the programme counter which are used. These potentials, some of which are combined in logical sum networks (Figs. 42-45, not shown) are used to control the network 168, Fig. 22, to cause the unit 112, Fig. 1, to perform the required operations. Two sets of test switches (X and Y, not shown) are associated with the programme counter. The X switches cause the counter to return to O when it reaches the number set up thereon while proceeding through a sequence of steps as indicated in Fig. 23, while the Y switches cause the counter to step immediately from O to the number set up. Memory read/record circuits, Figs. 7 and 7A illustrate the read/record circuitry associated with memory channels Ch0-Ch17, Fig. 5. The head 115 for Ch0 comprises a core 157 wound with coils 158, 159 connected in series with common supply terminal 160. Binary information is recorded on the drum 100 by the non-return-to-zero method so that the flux pattern m changes only for a change from 1 to 0 or 0 to 1. These changes cause positive and negative pulses e<SP>+</SP>, e _ to be applied from coil 158 to the control grid of a gate tube 162 forming part of the channel-selecting circuit 119, Fig. 1, or 119a, Fig. 22. Assuming that Ch0 is to be selected to be read, flip-flops A1-A5 will be set to represent " O " and a flip-flop A7 (not shown) will be set " false," thus providing a positive potential on the suppressor grid 163 which permits tube 162 to produce an inverted and amplified signal e<SP>+</SP>, e_ on line 164,leading to common junction 165 to which lines 166 from similar pick-up circuits for the other channels also are connected. The signal at 165 is fed through a degenerative amplifier 167, and a half-clock-period-delay line 173 to a phasesplitting circuit 174 producing outputs of opposite polarity on lines 180, 181. These outputs are applied through a clipper circuit 183, which eliminates negative and inverts positive pulses, thus producing negative pulse e+, e_ on separate lines 193, 192 connected to the opposite triggering inputs m 1 ,  0 m 1  of flipflop M1 whose output waveforms M1, M1<SP>1</SP>, which are applied to network 168, Figs. 7A and 22, are of similar form to the flux pattern m. The flip-flop is set to " O " at the beginning of each period P 2  O 13  by further triggering input signals applied to diode gate 226. Data to be recorded on the drum is represented by output potentials R 1 , R 2  (positive for " 1 " and " 0 " respectively) from network 168 applied to gates, such as Ch0 gates 203b, 203a, forming part of channel-selecting circuit 119b, Fig. 22. Flip-flop A7 will be set " true " for recording, and the gates for the selected channel will produce outputs such as ro, ro<SP>1</SP> applied through amplifying tubes 213, 214 to coils 159, 158 respectively. The read/record circuitry for registers E, F, G is similar to that described above, but includes separate read and record heads and no gates. For example, for register G, information read from the drum controls flip-flop Gm, Fig. 22, which in turn controls the trigger