Patent GB-1092481-A (GB)
Title: Improvements relating to radar apparatus
Inventor: MCQUEEN JACK GORDON
IPC: G01S13/08
Filed: 1964-03-06
Abstract: 1,092,481. Pulse radar. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. March 1. 1965 [March 6, 1964], No. 9706/64. Heading H4D. In a pulse radar system, wherein a scanning beam of finite width is used, such that echoes from a target are received on several successive scans, a scan count is started on receipt of an echo above noise level, which is stopped when no further echo has been received for a time indicative of the complete passage of the target through the beam. A compensating count is now started and is continued until it reaches a threshold whence it is known that the beam axis was on the target a constant number of scans previous to the time of said threshold. In Figs. 3A and 3B noise is filtered out from received signals by a receiver threshold means 1 and the remaining target echoes are separated out according to range by means of range switch RS actuated by a clock-like actuator 2. Each range gate so produced precedes a counting circuit such as shown. The first echo pulse from a target produces a signal at the YES output of means 3 which starts the echo count of counter 5 and the scan count of counter 4 via lead a and actuated switch S1. As further echoes are received from the same target on successive scans, the count in counters 4 and 5 increase equally. When the beam has passed through the target, no echo pulses are received and signal appears at the NO output of means 3 producing a count of one in counter 6. At the next scan the count is increased to two, and threshold means 7 produces a signal on line d which is fed to one input of AND gate 8. If enough consecutive echo pulses have been received to indicate a real target, threshold means 9 passes a signal to the second input of AND gate 8. The resulting output from AND gate 8 stops the count in counter 4 and then opens switch S2 by means of actuator 10. The count in counter 4 is then halved, and if necessary, rounded up to the nearest whole number. The scan count then continues from this whole number, until a count of eight is reached. Threshold means 11 then produces a signal such that a mark is produced on a P.P.I. display at the correct range, and at a bearing reached by the axis of the beam nine scans previously. The output of threshold means 11 also resets counters 5 and 4 and replaces switches S1 and S2 into the positions shown. If there is no output from threshold means 9, indicating that the echo was possibly due to noise, there is similarly no output from AND gate 8. The noise pulse however will be followed by pulse-free scans, such that threshold means 7 gives an output signal This output signal and the no-output from gate 8 are applied to NAND gate 12 which produces a signal, which, via OR gate 12 resets the counters and switches, in a similar manner to the output of threshold means 11. A second embodiment, Figs. 2 and 4-9, all not shown, is for use with a radar of the stacked beam type wherein echoes from a target can appear simultaneously on two adjacent beams. In the general arrangement, Fig. 4, each beam has a receiver which feeds received echoes to an input routine, Fig. 5, which determines for each range increment, which of any beam has the strongest echo and whether the two adjacent beams also contain the echo. This information is fed to an input register, Fig. 5, as a beam number n, a 0 or 1 beam n - 1 success and a 0 or 1 beam n + 1 success. In detail, the input routine comprises, Fig. 5, a threshold device for each beam receivers outputs (five beams only being shown) feeding a beam selector circuit. This circuit determines which beam has received the strongest echo and produces, after a delay of one pulse width, an appropriate " beam N " signal on line C which is fed to the input register, and instantaneously, an opening signal to the appropriate gate A1-A5. To determine whether adjacent beams have also received the echo, the beam selector circuit also produces a one pulse width sampling pulse which is fed, via the opened one of gates A1-A5, to open the two appropriate gates in the series G1 to G9. For example, if N = 4, then gate A4 will pass the sampling pulse to open gates G4 and G9 which respectively pass the beam 3 signal to an (N - 1) beam combining circuit and beam 5 signal to an (N + 1) beam combining circuit. The adjacent beam signals, in the form of 0 or 1 signals, respectively representing YES or NO, are stored in (N + 1) and (N - 1) stores. In order that for each scan the system should synchronously sweep through the range increments clock pulses, commencing with the transmission of the radar pulse and having an interval representing a range increment are provided. The sampling pulse after having beam delayed by one range increment or pulse width, opens gate 10 to allow the next clock pulse to allow the beam N information, and the contents of the two stores to be passed to the input register. The gated clock pulse is delayed in delay 2 to produce a signal which cancels the beam selector circuit and the two stores, and causes the input register to destructively read out to an echo associator, Fig. 6. The circuit of Fig. 5 is now ready to process echoes occurring in the next range increment. Three consecutive range increments are investigated, due to the possibility that due to jitter &C an echo in one range increment may be received in an adjacent range increment in the next scan. Three registers A, B and C, Fig. 4, are therefor provided to store the information shown in register A for three successive range increments R+ 1, R and R - 1. When a clock pulse is received the registers shift information to the right and so respectively store the information for ranges R+2, R + 1 and R. This is continued until the end of the scan, and the procedure is then repeated. The register C reads out into an output register D. A range store is provided for each range increment having a read out connection R and a write in connection W. Register A is fed by the read out from the (R + 1) range store, the read out correspondingly switching to the (R + 2) range store when the register shifts. The shift of the read out of the range stores in step with the shifting of registers A, B and C is caused by a range cycling switch synchronized by the clock pulses. The contents of output register D may be written into the appropriate range store for eventual rewriting into register A during the next scan, or it may cause a mark to be produced on the display, depending on switch SB1. The contents of the registers and range stores, and the action of switch SB1 is controlled by the logic sequence of the echo associator. The logic sequence is, Fig. 6 :- (a) Is there any new echo information in the input register? If not, no action is taken and the next range increment is investigated. If there is then- (b) Are any of registers A, B or C occupied ? If not, the new echo information is written into register B together with an up to date symbol showing that the information has resulted from the present scan. If some are occupied, then- (c) Is register B occupied ? If not, then see step (f). If it is, then- (d) Is the information therein new, i.e. is there an up to date symbol. If it is indicating that the information was read into register A during the preceding range increment, then see step (f). If it is not, then- (e) Is the beam on which the old information was found the same as or adjacent to the beam producing the new information? If it is, then the information in register B is updated according to Fig. 8. If it is not, then- (f) Is register A occupied? If not, then see step (h). If it is then- (g) Is the beam on which the information was found the same as or adjacent to the beam producing the new information? If it is, then the information in register A is updated according to Fig. 8. If it is not, then- (h) Is register C occupied ? If not, then the sequence returns to register B. If it is, then steps (d) and (e) are carried out, ending with the updating of register C on the return of the sequence to register B. (i) Finally, if the total success count in register B is not greater than one, indicating a false alarm, the content of register B is cancelled. Echo information, if any, in each range increment thus passes sequentially into output register D, suitably updated. The logic sequence in output routine, Fig. 7, is as follows:- (a) Is register D occupied? If not, no action is taken. If yes- (b) Does the failure count exceed the limit (2) ? If not, add 1 to total count. Ask, is the information new ? If not, add 1 to the failure count. If it is, reduce the failure count by 1. Return the adjusted information to the appropriate range store for recycling. If yes, then- (c) Does the success count exceed the limit indicating a true target ? If not, the information is erased. If it is, an acceptance symbol is added to the information, and then- (d) Does the total count exceed the limit (8) ? If yes, a radar plot is made on the display and the information is passed to an output stage, Fig. 9, which may include heightfinding means and a tracking computer. If not, then 2 is added to the total count (this is an alternative to the halving of the main count) and the adjusted information is returned to the appropriate range store.