Patent GB-1281056-A (GB)
Title: A digital sine-cosine generator
Inventor: GARDE DOUGLAS
IPC: G06F7/66
Filed: 1969-10-23
Abstract: 1281056 Sine-cosine generator SOLARTRON ELECTRONIC GROUP Ltd 23 Oct 1970 [23 Oct 1969] 52053/69 Heading G4A  A digital sine-cosine generator comprises two shift registers 14 and 16 which are arranged to cycle in step and which are connected in closed loops A and B to two full adders 18 and 24, cross connections being provided between the adders. The generator operates in accordance with the algorithms sin # n + 1=sin # + ## cos #n (1) cos # n + 1 = cos #n - ## sin #n (2) where sin # n and cos #n are the values of the functions after n increments ## and ## is small. First embodiment.-From equations 1 and 2 above the following may be derived The contents of registers 14 and 16 are serially added in adder 18 in order to form the new sum terms # cos #i and # sin #i in each iteration. However because of the effect of ## (which is small = 2<SP>-N</SP> radians) in equations 3 and 4 above the new sum terms are not permitted to affect the values of sin 0 and cos # respectively stored in register 16 unless their formation results in the generation of an overflow carry 20. If an overflow carry is produced by the addition of ú cos #i and cos #n, the carry bit is passed to adder 24 and added into the least significant bit position of sin #n (eqn. 3). Similarly if the formation of the new sum # sin # in adder 18 produces an overflow carry, the carry bit is subtracted by adder 24 from the least significant bit position of cos #n (eqn. 4). Each time # is to be incremented by ## a pulse is applied to terminal 26 and shift pulses are gated from oscillator 32 to the registers on line 34. A divider 36 and a monostable 37 generate two pulses per shift cycle to mark the passage of the two halves of the register. If a carry bit is generated by adder 18 when the most significant bit of # cos #i has been generated it passes through gate 42, enabled by the first mark pulse on line 38, to set flip-flop 44, a divide by two flip-flop 46 also being set by the mark pulse. The set flip-flop 44 applies a "1" bit to adder 24 so that 1 is added to the least significant bit of sin #n and is then immediately reset by a shift pulse from gate 48. The carry from adder 18 is prevented from propagating within that adder by a clear pulse generated by delay 39 from the mark line 38. When # sin #i produces a carry overflow the carry is subtracted from cos On by adding a 1 to each bit in cos #n, the carry again being prevented from propagating. The overflow sets flip-flop 44 which is not reset by a shift pulse via gate 48 since that gate is blocked by flip-flop 46 which is reset by the second mark pulse on line 38. Thus a 1 bit is added to each bit of cos #n. To prevent accumulated errors, due to the fact that a non-integral number of increments is required to rotate # through #/2 radians since # is a transcendental number, one half of register 16 is set to zero each time the other half reaches 1. Second embodiment.-In the second embodiment, Fig. 4 (not shown), the original values of sin # and cos 0 are loaded into the two shift registers one of which is then rotated through half the number of bits in the register so that the least significant bits of sin 0, i.e. 0 sin 0 (since ## is small) appear concurrently with the most significant bits of cos # for subtraction (eqn. 2) and the least significant bits of cos #, i.e. ## cos # appear concurrently with the most significant bits of sin 0 for addition (eqn. 1) Inhibit gates are provided to prevent the most significant bit of sin # being added into the initially rotated register and the most significant bits of cos 0 being added into the initially non- rotated register.