Patent GB-2051436-A (GB)
Title: Data processing system
IPC: G06F9/26
Filed: 1978-10-13
Abstract: A cache oriented pipeline data processing unit includes an execution unit, apparatus for fetching data and instructions, hardware decoder and sequencing circuits and a microprogrammed control unit. The microprogrammed control unit includes first and second control stores. The first control store includes a plurality of storage locations, each location for storing at least an address field and a control sequence field for each of the program instructions required to be executed by the data processing unit. The control sequence field is coded to designate which one of a group of hardware control sequences is to be executed by the hardware sequencing circuits for matching the performance of the execution unit and fetching apparatus. The second control store includes a plurality of groups of storage locations, each group for storing the microinstructions required for executing at least a portion of a program instruction. The microprogrammed control unit in response to each instruction opcode reads out signals corresponding to a control sequence field which are decoded to condition the hardware sequencing circuits for performing those operations required for execution of the instruction. The starting location in the second control store is referenced at the end of the hardware sequence and instruction execution proceeds under microprogram control. During the processing of various program instructions, the hardware sequencing circuits are operative to load signals corresponding to the constant field selected into one of a plurality of registers of the control unit. The constant signals selectively condition apparatus within the data processing unit enabling the hardware sequencing circuits and sequences of microinstructions from the second control store to execute the operation more particularly specified by the constant field in accordance with the operation code without requiring further decoding of such operation code. Each control sequence includes at least one microinstruction which contains a restart field coded to specify the conditions under which the hardware sequence circuits continue instruction execution. For each program instruction which cannot be executed by the plurality of hardware sequence circuits in a pipeline mode, the control sequence field is coded to include a predetermined bit pattern. When decoded, the hardware sequence circuits are conditioned to enter an escape state enabling control to be transferred to a sequence specified by the address field. Instruction execution proceeds under microprogram control while the hardware sequence circuits remain in the same state. Upon the decoding of a microinstruction containing a restart field, the hardware sequence circuits are switched from the escape state to a state which enables the continuing of hardware instruction execution in a pipeline mode. Each storage location of the first control store may store additionally a register control field. The register control field is used to condition register circuits, register busy circuits or increment circuits for selecting various program visible registers, for controlling the updating of registers or for specifying an increment value to be added to the program instruction counter respectively during the processing of program instructions in the hardware sequence circuits and microinstruction sequences stored in the second control store.