Patent GB-1026888-A (GB)
Title: Computer
IPC: G06F15/80
Filed: 1963-12-03
Abstract: 1,026,888. Electric digital calculators. WESTINGHOUSE ELECTRIC CORPORATION. Dec. 3, 1963 [Dec. 4, 1962], No. 47679/63. Heading G4A. A computer comprises an array of similar processing elements under simultaneous control of a central control unit, each processing element possessing memory means, logic and arithmetic means for operating on information from the memory means and means for transferring information located in said memory means to another element in the array. In the particular embodiment, all the processing elements are at any instant performing the same operation on operands stored in the same memory locations (in the different elements). Processing element (Figs. 7A, 7B, 7C, not shown).-Each processing element contains two memory frames 20, 30, a bit position in which can be selected by word selection units and bit counters all in the central control unit (and common to all the processing elements). The bit read-out or about to be written in is stored in flip-flops 68, 78, 74, 84. Frame selection means 40, employing STROKE (i.e. NAND) gates, responds to signals CC1, CC2 from the central control unit as follows: (a) if CC1 = 1, CC2 = 1, the bits read from frames 20, 30 are written into frames 30, 20 respectively; (b) if CC1 = 1, CC2 = 0, the bit read from frame 20 is rewritten into frame 20 and a bit S1 from a logic and arithmetic unit 38 is written into frame 30; (c) if CC1 = 0, CC2 = 1, as (b) but with 20, 30 interchanged; (d) if CC1 = 0, CC2 = 0, the bits read from frames 20, 30 are rewritten in the same frames. The bit F1 from the flip-flop 68 (fed by frame 20) is also passed to routing means 45 (Fig. 7C, not shown) controlled from the central control unit to route the bit F1 to one of the four neighbouring processing elements N1, N2, N3, N4 or to an operation selection means 47 as the bit ax. Routing means 45 also allows a bit received from one of the neighbouring processing elements N1, N2, N3, N4 to be routed (as ax) to operation selection means 47. Means 47, in response to signals from the central control unit selects the bit ax or its complement to constitute the bit a and also the bit F2 (from the flip-flop 78 fed by frame 30) or its complement to constitute the bit b. Alternatively, either a or b may be zero irrespective of ax. The bits a, b, together with their complements as provided by STROKE gates 156, 166 form, together with a bit C, the data inputs of the logic and arithmetic unit 38 which is controlled by the central control unit to produce the bit S1. Unit 38 includes a carry flip-flop 220. Instruction word and central control unit (Fig. 8, not shown).-The instruction word used has a portion specifying the operation to be performed, a portion to control frame selection means 40, portions specifying the frame 20 and 30 addresses (word and bit), a tag section for each frame 20, 30 to select an index register for address modification and a routing portion specifying to which neighbouring processing element (if any) the data in the frame 20 memory is to be routed. In the central control unit, a programme memory is addressed by an instruction counter which reads instructions into an instruction register in parallel mode, either in sequence or in accordance with jump commands. Diode decoding matrices for the instructions are provided. A clock is provided for synchronous computer operation. Other units shown in block form in Fig. 8 (not shown) are implied by the above. Input-output means.-Input to and output from a rectangular array of processing elements each as above is via one edge of the array. Fig. 11 (not shown) shows an input-output unit in block form. For input, a first buffer accepts data serially until full when the central control unit transfers this data in parallel mode into a selected row of a three-dimensional core memory. Successive rows are filled in this way. The central control unit then causes the first bits of each row to be read out in parallel through a second buffer into the edge processing elements of the array. Then the second bits are read out, &c. Output from the array is done by the reverse of the above procedure, the data going to a magnetic tape unit or printer. As a modification, separate input and output units may be used on different edges of the array. Addition.-Initially the control bit CL (Fig. 7B, not shown) is made zero to clear the carry flip-flop 220, then the lowest order bits of the two numbers to be added are read out (as F1, F2) from the frames 20, 30 and routed via units 45, 47 (Fig. 7C, not shown) to the logic and arithmetic unit 38, the control bits to unit 47 being such that a = F1 and b = F2. In the arithmetic unit 38, the control bits take the following values: AZ = EO = 1, AN = OR = O. The first bit of the sum appears as S1 and the carry bit is stored in flip-flop 220. Higher order bits are added similarly. Multiplication.-Initially the multiplier and multiplicand are stored in frames 30, 20 respectively. First the multiplier is transferred to a special location in frame 20 by adding it to zero and routing the answer to frame 20. For this CM1 = CM2 = AC1 = SC1 = 0 and AC2 = 1 so that b = F2 and a = 0, and in the arithmetic unit 38, AZ = EO = 1 nad AN = OR = 0 for addition. The carry flip-flop 220 is then cleared (by CL) and an arithmetic control flip-flop 178 set (by LO) to provide C = 1. The first bit of the multiplier is read from frame 20 (as F1) and passed through units 45, 47 to be added to zero (a = F1, b = 0). The result of the addition S1 (= F1) is passed back to set (or not) arithmetic control flip-flop 178. The multiplicand is then read from frame 20 (as F1) and routed to unit 47 to be added to zero if the last mentioned S1 (first bit of the multiplier) was 1 and blocked if it was 0, flip-flop 178 controlling STROKE gate 186 for this purpose. The resulting partial product is stored in frame 30. The above procedure is then repeated for each bit of the multiplier, except that the multiplicand (if not blocked) is added to the partial product rather than to zero. A separate correction cycle (no details given) to determine the sign of the product must be done afterwards if multiplier and multiplicand are not both positive. Other operations mentioned are AND, OR, exclusive OR, complementing, subtraction, inverse subtraction, division and scaling. Modification.-In addition to routing means 45 for transferring bits from frame 20, a routing means may be provided for frame 30.