Patent SG-11201807803S-A (SG)
Title: Semiconductor package and method of forming the same
Inventor: WEERASEKERA ROSHAN
IPC: H01L21/768
Filed: 2017-03-17
Abstract: coupledFirst layer contact elements Routing layer 106 Second layer contact elements - 116 102 112 I coupled Second electrical die / contact elements 114 Second semiconductor die Mold structure W O 20 17 / 16 48 10 Al (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (10) International Publication Number (43) International Publication Date WO 2017/164810 Al 28 September 2017 (28.09.2017) WIPO I PCT 111111111111110111011111111111010111110 III 01111111111111H 0101111111111111110111111 FIG. 1 (51) International Patent Classification: HOlL 21/768 (2006.01) HOlL 23/538 (2006.01) (21) International Application Number: PCT/SG2017/050133 (22) International Filing Date: 17 March 2017 (17.03.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 10201602169T 21 March 2016 (21.03.2016) SG (71) Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH [SG/SG]; 1 Fusionopolis Way, #20-10 Connexis North Tower, Singapore 138632 (SG). (72) Inventors: WEERASEKERA, Roshan; c/o Industry De- velopment, Institute of Microelectronics, 2 Fusionopolis Way, #08-02 Innovis Tower, Singapore 138634 (SG). BHATTACHARYA, Surya; c/o Industry Development, Institute of Microelectronics, 2 Fusionopolis Way, #08-02 hmovis Tower, Singapore 138634 (SG). CHANG, Ka Fai; c/o Industry Development, Institute of Microelectronics, 2 Fusionopolis Way, #08-02 Innovis Tower, Singapore 138634 (SG). RAO, Vempati Srinivasa; c/o Industry De- velopment, Institute of Microelectronics, 2 Fusionopolis Way, #08-02 Innovis Tower, Singapore 138634 (SG). (74) Agent: VIERING, JENTSCHURA & PARTNER LLP; P.O. Box 1088, Rochor Post Office, Rochor Road, Singa- pore 911833 (SG). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. [Continued on next page] (54) Title: SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME (57) : Various embodiments may provide a semiconductor package. The semiconductor package may include a routing layer including a plurality of 100 first layer contact elements on a first side and a plurality of second layer con- tact elements on a second side opposite the first side, and a first semiconductor 108 die including a plurality of first electrical die contact elements coupled to the plurality of first layer contact elements. The semiconductor package may fur- ther include a second semiconductor die including a plurality of second elec- trical die contact elements coupled to the plurality of second layer contact ele- ments, and a mold structure covering the second semiconductor die. A first pitch between neighbouring first electrical die contact elements may be greater than a second pitch between neighbouring second electrical die contact ele- ments. WO 2017/164810 All#110HOMOIDEIR010130111001111HOMMOVOIMIE (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: with international search report (Art. 21(3))