baber/WOPTO huggingface dataset:
Patent JP-H11261922-A (JP)
Title: Digital television tuner
Inventor: KUNISHIMA TSUTOMU
IPC: H04N5/44
Filed: 1998-03-16
Abstract: PROBLEM TO BE SOLVED: To eliminate the influence by the first gain control voltage by interrupting the supply of the first gain control voltage to a gain control terminal at the time of receiving the television signal of an analog system. SOLUTION: At the time of receiving a digital television signal, a second switching means supplies a power source voltage to a digital processing part 3 and a first switching means 4 inputs a digital IF signal outputted from a tuner part 2 to the part 3 to open an opening and closing means 6 to supply the first gain control voltage (AGC1) generated from the gain control voltage generator 3a of the part 3 to the gain control amplifier 2a of the part 2. At the time of receiving an analog television signal, an analog If signal from power source voltage and the part 2 is inputted to an analog processing part. AGC 2 generated from a gain control voltage generator 8a is supplied to the amplifier 2a. At this time, the means 6 is opened to cut off the generator 3a of the part 3 from the gain control tip 2c of the tuner part 2.
Patent JP-H10321535-A (JP)
Title: Semiconductor substrate having compound semiconductor layer, producing method therefor and electronic device produced on semiconductor substrate
Inventor: SATO NOBUHIKO
IPC: H01L21/02
Filed: 1998-03-16
Abstract: PROBLEM TO BE SOLVED: To provide a producing method for semiconductor substrate for economically producing a crystal defect reduced monocrystal compound semiconductor film on a silicon substrate over a wide area with high productivity, uniformity and controllability, semiconductor substrate based on that method and semiconductor device produced on this substrate. SOLUTION: This semiconductor substrate has a semiconductor layer 14, composed of a monocrystal compound on a surface 13 having a sealed hole 12 in a porous region 11. Furthermore, this producing method has a process (b) for performing heat treatment to an Si substrate 10 having the porous region 11, in order to seal the hole 12 on the surface of this porous region and a process (c) for heteroepitaxially developing a monocrystal compound semiconductor layer 14 on the porous region having the hole 12 sealed by this heat treatment.
Patent JP-H01237807-A (JP)
Title: Semiconductor integrated circuit device
Inventor: HIRAYAMA HIROMITSU
IPC: G05F3/24
Filed: 1988-03-18
Abstract: PURPOSE:To prevent power from being consumed wastefully by forming a constant voltage generation circuit essentially by a resistance element and plural diodes connected in series. CONSTITUTION:A laser driver, in which a various kinds of FETs, etc., being constituted in Schottky junction type, is formed on a GaAs substrate with another constituent. And a first level shift circuit 25 consisting of the FETQ11, a level shift diode D11, and a current source FETQ13 and a second level shift circuit 26 with the same constitution are connected between a ground terminal 1 and a power source terminal 12, and an output differential circuit 27 consisting of the FETs Q15-Q16 and a power source FETQ17 is connected to the succeeding stage of those circuits. Also, the FETQ18 for offset current driving and the FETQ19 for voltage division connected in series are connected to the succeeding stage of the circuit 27, and furthermore, the constant voltage generation circuit 28 consisting of a resistor R11 and the diodes D13-D16 connected in series is connected to the succeeding stage of the above FETs Q18 and Q19. In such a way, excessive voltage between a gate and a drain can be prevented from being impressed, and also, power consumption can be reduced.
Patent JP-H02244326-A (JP)
Title: Command input line setting processing system
Inventor: YAMAGUCHI SHIGETOSHI
IPC: G06F3/153
Filed: 1989-03-17
Abstract: PURPOSE:To input an operand which consists of many characters and a command which has many operands by opening a window for an extended command input line dynamically irrelevantly to the definition of the image screen definition body of a full-screen. CONSTITUTION:When a user needs the input of a long command in line mode, the user inputs the extension request for a command input line on the keyboard of a man-machine interface 20 with a key. Then when an extension request detection part 15 detects the extension request for the command input line, a command input line extension part 16 opens the window for a little bit larger number of, e.g. 3 extension command input lines 22 for command input in the full-screen. Thus, the window for the extension command input lines 22 is opened dynamically irrelevantly to the definition of the screen definition body 11 of the full-screen 21. Consequently, the operand consisting of a large number of characters and the command having many operands can be inputted.
Patent JP-S51141638-A (JP)
Title: Electrostatic charged image developing apparatus
Inventor: ISHIDA MASAMI
IPC: G03G15/09
Filed: 1975-06-01
Abstract: PURPOSE:To make apparatus smaller and construction simpler to prevent deterioration of developing agent, pollution of latent image forming faces, damages, etc.
Patent JP-S61225156-A (JP)
Title: Synthesis of glycine
Inventor: FUJIMOTO KAORU
IPC: C07B61/00
Filed: 1985-03-29
Abstract: PURPOSE:To obtain glycine easily and economically, by oxidizing monoethanolamine as a starting material in the liquid phase in the presence of a catalyst and oxygene under pressure. CONSTITUTION:Monoethanolamine is oxidized in the liquid phase under for example >=5kg/cm<2>, preferably >=10kg/cm<2> pressure in the presence of a Pd catalyst and oxygen to obtain glycine. For example, the reaction is supposed to proceed as indicated by the reaction scheme. The reaction proceeds even at normal temperature under an appropriate pressure; however, the highest reaction rate is achieved at >=about 50 deg.C, preferably at about 70 deg.C. When a catalyst other than Pd is used, the reaction is of almost no industrial value because the yield of glycine is extremely low. Further addition of NaOH into the reaction system improves remarkably the yield and reaction rate.
Patent JP-S6470288-A (JP)
Title: Motorcycle
Inventor: TOMINAGA NOBUYOSHI
IPC: B62J99/00
Filed: 1988-03-18
Abstract: PURPOSE: To attain a mounting space with high efficiency by connecting intake passages with a carburetor to the rear side of the front cylinder and the front side of a rear cylinder of a V-type engine respectively, crossing both the intake passages each other so that the two carburetors may overlap with each other, and directing respective intake openings upwards. CONSTITUTION: Intake passages 41, 42 are formed on the front side of a rear cylinder 22 and the rear side of a front cylinder 21 respectively, and carburetors 27, 28 are fitted at both the intake passages 41, 42. The intake passages 41, 42 are crossed so that the carburetors 27, 28 may overlap each other when viewed from the side. The intake openings of the intake passages 41, 42 are directed upwards, and each of them are connected to the intake piping connection part of a main frame 1 respectively. The two carburetors 27, 28 are fitted in a line to the right and left side, and both the intake passages 41, 42 are stored in the width of the cylinder. It is thus reduce the side of a section corresponding to the leg part of an occupant for attainment of a mounting space with high efficiency.
Patent JP-H09237675-A (JP)
Title: Heater and image forming apparatus
Inventor: KISU HIROKI
IPC: H05B6/10
Filed: 1996-02-27
Abstract: PROBLEM TO BE SOLVED: To simplify an apparatus by constituting an exciting coil in such a manner as to guide motion of a movable member. SOLUTION: A Fixing device 100 serving as an image heater comprises an exciting coil unit 20, a fixing film 10 and a pressurizing roller 30. The coil unit 20 is provided with a heat resistant coil 20-1, a highly permeable core 40, a holding member 20-2 for holding the coil unit 20 and the like. The film 10 is formed into a cylindrical shape, and is fitted around the coil unit 20. The film 10 is a lamination having a heat generating layer 10-1 serving as a conductive heat generator, an elastic layer 10-2 and a separating layer 10-3. The roller 30 is constituted of a mandrel 30-2, a silicone rubber layer 30-1 laminated around the mandrel 30-2, a thermistor 30-3 for measuring a surface temperature of the roller 30 and the like. The roller 30 is brought into press-contact with the coil unit 20 with the film 10 nipped therebetween, thereby forming a nipped portion N. The roller 30 is rotated counterclockwise so as to drive the film 10 in cooperation with a recording medium P which is led to the nipped portion N. At this time, the lower surface of the coil unit 20 is brought into direct press-contact with the film 10, to thus serve as a film guide for guiding the film 10 in such a manner as to stably feed the film 10.
Patent JP-H01238282-A (JP)
Title: Camera-integrated vtr
Inventor: YOSHIKAWA SHINICHI
IPC: H04N5/93
Filed: 1988-03-17
Abstract: PURPOSE:To make the operability excellent when consecutive recording is executed by providing a memory to store images and a circuit to control the input/output of an image signal to/from said memory to a title VTR which allows observation through its view finder, and making the VTR display a still picture on the view finder when the pausing mode is set. CONSTITUTION:A signal from a CCD 1 subjected to gamma, white, balancing, and aperture processings in a camera processing circuit 2, converted to a digital signal in an A/D converter 3, and written in a frame memory 4. The operation of the memory 4 is so controlled by a memory controller 9 that it operates in a mode designated by a microcomputer 10. On operator instructs a desired picture mode of enlargement/still picture/storing mode in the computer 10 through a picture mode switch 15 to execute it. An output from the memory 4 is converted to an analog signal by a D/A converter 5, undergoes an FM processing circuit 6 and a magnetic head 7 to be recorded on a tape 8. An output from the converter 5, at the same time, is adjusted of its luminance and contract in a processing circuit 11 for electronic viewfinder, and displayed on a cathode-ray tube 12.
Patent JP-H04278744-A (JP)
Title: Data transmission system
Inventor: KUNITSUCHI JIYUNICHI
IPC: H04L7/08
Filed: 1991-03-06
Abstract: PURPOSE:To unnecessitate speed conversion at an intermediate repeater station by constituting in such a way that the integral multiple of the number of information bits except a radio section overhead(ROH) bit which is encoded by means of an error correction code coincides with the number of bits in one frame of a synchronous digital hierarchy(SDH) synchronizing network. CONSTITUTION:Information bits are shown as 11-16 inside a signal format in a figure (A) and respective strings have 360 bits. R1-R6 are the radio section overhead(ROH) bits, respective strings have two bits, S1-S6 are redundant(FEC) bits and respective strings have 10 bits. The frame format of 155.52Mb/s STM-1 signal in the synchronizing network corresponding to SDH is shown in the figure B, is constituted of 2160 bits X 9 string bits per one frame and serially succeeds to respective rows where the signal is permitted to flow. The sum of information bits of one block-six strings in (A) is 2160 bits and the integral multiple of the numbers of bits in information bits 11-16 is equal to the number of the bits in one frame of the SDH synchronizing network.
Patent JP-H08258469-A (JP)
Title: Electronic nameplate
Inventor: ANDO MASAAKI
IPC: B42D15/10
Filed: 1995-03-24
Abstract: PURPOSE: To obtain an electronic nameplate which can be rewritten, by providing a liquid crystal display means as a name display means and providing a means for rewriting character data to be displayed on the liquid crystal means by an electric signal from the outside. CONSTITUTION: An electronic nameplate 1 has a non-volatile memory means therein and a liquid crystal display device 2 on its surface. Items of information (company name, name of department and division, personal name) for the nameplate are displayed on the liquid crystal display device 2. On the side face of the electronic nameplate 1, a signal input/output connector 3 for writing the nameplate information in the liquid crystal display device 2 is arranged. By connecting an external server to the connector 3, the names are rewritten. The input/output connector 3 functions also as a signal input/output terminal when an ID card is used together. Further, by housing a beeper in the electronic nameplate 2 and integrating it, one can carry the beeper without consciousness of having the beeper.
Patent JP-S52148466-A (JP)
Title: Treatment of exhaust gas
Inventor: SAKURAI HIROSHI
IPC: B01J27/32
Filed: 1976-06-07
Abstract: PURPOSE: To reactivate deteriorated activated carbon catalyst and to restore the NO 2 -removal ratio by washing the deteriorated activated carbon catalyst with water to remove selectively ammonium sulfate formed on the catalyst. To the activated carbon catalyst is adhered halogen for removing SOx, NOx. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-S51141554-A (JP)
Title: Method of segmentation
Inventor: SHIMAKURA TATSUROU
IPC: G06F12/10
Filed: 1975-05-31
Abstract: PURPOSE: To enable dynamic change of segmentation operation during execution of a program by giving the function to modify and re-define to segment description element describing a segment. 
     COPYRIGHT: (C)1976,JPO&Japio
Patent JP-H0836787-A (JP)
Title: High-density optical memory disk recording original board and manufacture thereof
Inventor: NISHIDA RYOICHI
IPC: G11B7/26
Filed: 1995-03-24
Abstract: PURPOSE:To record with a short wavelength and to obtain a high-density recording capacity by providing an organic polymer material thin film having absorption in an ultraviolet region on a recording medium on a substrate. CONSTITUTION:A thin film 2 of methylphenylpolysilane is formed on a substrate 1 of transparent glass by a spin coating method to form an optical memory disk original board 3. Then, the board 3 is emitted with KrF excimer laser light by using a laser 4, then, the low molecular SiOx of the exposed part 6 of the film 2 is developed by using developer containing butyl acetate and 2-propanol, thereby forming a pit. Since the diameter of the pit can be reduced to about half of the prior art, about 0.3mum, the recording density of the board and a replica obtained from the original board can be raised as large as about four times.
Patent JP-S54157459-A (JP)
Title: Amplifier circuit
Inventor: AMADA NOBUTAKA
IPC: H03F3/30
Filed: 1978-06-02
Abstract: PURPOSE:To obtain a high-efficiency amplifier circuit featuring the steady idle current and an improved distortion factor by applying the bias voltage to the output transistor and at the same time supplying a constant current to the saturation preventing diode. CONSTITUTION:Diode 14 and 15 are connected between the input of output transistor Tr10/12 and 11/13. At the same time, the bias voltage caused by diode 18 is applied directly between the base and the emitter of Tr10 and 11 to compensate the temperature of them. As diode 14 and 15 are not inserted into the input of Tr10 and 11, the idle current of Tr10 and 11 is not affected at all by the temperature characteristics of diode 14 and 15. Furthermore, the DC current large enough compared with the signal current is supplied to diode 14 and 15 via driving circuit 2, and thus the operation resistance does not change substantially. Accordingly, the transmission characteristics is not fluctuated with supply of the input signal to Tr10 and 11, with no distortion caused.
Patent JP-H09258698-A (JP)
Title: Driving method of display device
Inventor: SEIKE TAKESHI
IPC: G09G3/36
Filed: 1996-03-22
Abstract: PROBLEM TO BE SOLVED: To maintain high contrast in a wide temp. range by changing the ratio of the pulse width of a voltage for charge to a voltage for discharge to be impressed on a pixel in accordance with ambient temps. SOLUTION: The selection period of each pixel is defined as T and it is divided into a write period T1 and an erase period T2 and, in the resultant waveform (SEG-COM waveform) between a scan signal waveform (COM waveform) and a data signal waveform (SEG waveform), the ratio of the pulse width of a voltage waveform to be impressed in the write period T1 to the pulse width of a voltage waveform to be impressed in the erase period T2 is made to be changed in accordance with the temp. detected by a temp. detecting means. For example, the pulse width of the erase period T2 is made large by judging the ambient temp. becoming equal to or lower than 5 deg.C by the temp. detecting means as a low temp. (a). And the pulse width of the erase period T2 is made small by judging the ambient temp. becoming equal to or higher than 45 deg.C as a high temp. (b).  Thus, a voltage-contrast characteristic becomes near the characteristic in an ordinary temp. in the wide temp. range and then a sufficient contrast is obtained in the wide temp. range with respect to one driving voltage.
Patent JP-S54860-A (JP)
Title: Scribing method for semiconductor wafer
Inventor: KACHI MASAO
IPC: B23K26/364
Filed: 1977-06-03
Abstract: PURPOSE: To ensure a good scribing by irradiating the laser pulse more than twice onto the same street of the substrate with variation of the repetitive frequency. 
     COPYRIGHT: (C)1979,JPO&Japio
Patent JP-S60208299-A (JP)
Inventor: KONDOU SEIJI
IPC: B43L13/00
Filed: 1984-04-03
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H01238137-A (JP)
Title: Manufacture of semiconductor device
Inventor: WATABE TAKUYA
IPC: H01L21/761
Filed: 1988-03-18
Abstract: PURPOSE:To eliminate the need for heat treatment for activation, and to obtain a low-cost compound semiconductor substrate having excellent crystallizability by growing an n-type or p-type conductive-compound semiconductor substrate onto a substrate of a different kind, implanting impurity ions to the substrate and using an implanting region as an insulating region for element isolation. CONSTITUTION:Resist masks 3 are formed selectively onto the surface of an n-type GaAs layer 2, the ions of iron or chromium are implanted from a top face, and implanting regions are brought to an insulating state. When the resist masks 3 are removed through etching, the removing sections are employed as element forming regions composed of the n-type GaAs layers 2, and the ion implanting regions are used as insulating regions 4. Crystallizability is broken in the ion implanting regions at that time, but an activation heat treatment for recovering crystallizability is unnecessitated because the ion implanting regions are employed as the insulating regions. Accordingly, no trouble in which the crystallizability of the element forming regions is deteriorated is caused.
Patent JP-H11252021-A (JP)
Title: Optical transmitter
Inventor: MANABE SATOSHI
IPC: H04B10/50
Filed: 1998-03-02
Abstract: PROBLEM TO BE SOLVED: To stop an excitation light source before the bias current of an LD is saturated not only by the decline of the output light level of an electric/optic conversion part detected in a light amplification part but also the degradation of the LD of the electric/optic conversion part or the like. SOLUTION: The electric/optic conversion part 100 is provided with a light source for converting input electric signals into optical signals and a first control circuit 110 for controlling the driving current of the light source so as to fix the output light level. The light amplification part 200 is provided with a light amplification fiber 201 for amplifying the output light of the electric/optic conversion part 100 by excitation light outputted from the excitation light source, a second control circuit 210 for controlling the driving current of the excitation light source so as to fix the output light level or a gain and a first alarm circuit 120 for stopping the excitation light source when the output light level of the electric/optic conversion part 100 becomes lower than a threshold value.  Further, a second alarm circuit 280 for stopping the excitation light source of the light amplification part when the driving current of the light source of the electric/ optic conversion part 100 exceeds the threshold value by the control of the first control circuit 110 is provided.
Patent JP-S63231694-A (JP)
Inventor: SASAKI SHIGERU
IPC: G07D7/00
Filed: 1987-03-20
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S60210018-A (JP)
Title: Thin film piezoelectric oscillator
Inventor: MIYASAKA YOUICHI
IPC: H03H9/17
Filed: 1984-04-03
Abstract: PURPOSE:To increase both the coupling coefficient and Q value by forming an oxide single crystal thin film on a thin film member of a silicon single crystal obtained by doping boron in high density, forming a vibration area on said thin film with a piezoelectric single crystal thin film and an electrode and supporting the fringe of the vibration area by a substrate. CONSTITUTION:A silicon thin film 12 which is doped in the density higher than a prescribed level is formed on a silicon substrate by epitaxial growth or diffusion. Then an oxide single crystal thin film 16 is formed on the film 12. The substrate 11 is etched to form a through-hole 10 and a piezoelectric thin film 13 is formed on the film 16 by epitaxial growth. Furthermore, electrodes 14 and 15 are formed on the surface of the film 13 and the lower side surface of the film 12 respectively. The fringe part of a vibration area formed with films 13 and 12 is supported by the substrate 11. In such a way, the acoustic loss of the film 13 is reduced and the Q value of the film 13 is increased even in case the thickness of the film 13 is larger than that of the film 12.
Patent JP-2000261000-A (JP)
Title: Semiconductor device
Inventor: TERAMAE SATOSHI
IPC: H01L29/80
Filed: 1999-03-12
Abstract: PROBLEM TO BE SOLVED: To make an impurity region fine, when a plurality of impurity areas are formed selectively in a semiconductor substrate. SOLUTION: This semiconductor device is provided with a first conductivity collector substrate 1, a plurality of grooved second conductivity base regions 5 at a plurality of points on the surface of the collector substrate 1, one or a plurality of first conductivity emitter regions 8 on surfaces among the base regions 5 on the collector substrate 1, and a diffusion base region 4 which impurities are diffused in a first conductivity region around the grooved the region 5 from the base region 5.
Patent JP-H03265978-A (JP)
Title: Definite element mesh generator
Inventor: MOCHIZUKI OSAMU
IPC: G06F17/50
Filed: 1990-03-15
Abstract: PURPOSE:To reduce model-shaped external form block division by using linear inclined mapping with a nodal point train on an external form side as a contour curve. CONSTITUTION:A nodal point on external form side generation part 1-1 is provided to generate nodal points on a real external form side for regulating a dividing number and a dividing position when generating a mesh, and an input/output part 1-6 is provided for the time of nodal point generation on the external form side. Then, a mesh generation center part 1-5 is provided to produce a curved coordinate system from the generated nodal points on the external form side and to generate the mesh on a lattice. The linear inclined mapping is used with the nodal point train on the external form side. Thus, a complicated curved surface or object can be approximated with required accuracy and there is no trouble even when the external form side of an external form block as the fundamental unit of mesh generation is made discontinuous (composed of plural line segments). Therefore, the external form block division of the model shape is reduced.