Patent GB-1203768-A (GB)
Title: Improvements in or relating to telecommunications apparatus
Inventor: JONES ELWYN TUDOR
IPC: H04J3/12
Filed: 1966-10-27
Abstract: 1,203,768. Multiplex pulse code signalling. MINISTER OF TECHNOLOGY. 26 Oct., 1967 [27 Oct., 1966], No. 48184/66. Heading H4L. Telecommunication apparatus includes an analogue-to-digital converter, and switching means for suppressing a proportion of the signal elements in the digital output of the converter and replacing them by signal elements representing digits of a data signal, means being provided to minimize the distortion caused by the introduction of the data signal. As shown in Fig. 1 an input analogue signal is supplied to a delta-modulator 3, the output S of the modulator being supplied to an AND- gate 7, and a data signal T is supplied to an AND-gate 6. The modulator 1 controls a timing circuit 5 consisting of a counter arranged to produce a pulse H at every nth signal element produced by the delta-modulator to open the AND-gate 6 and pass a data signal element T via an OR-gate 9 to the transmission channel 10. At the same time a complementary pulse H closes the gate 7 and blocks the corresponding signal element from the modulator 1. At the receiver a timing circuit 11 similar to circuit 5 is synchronized by known means so that its output H<SP>1</SP> coincides with the received data signal elements to open a gate 12 at the appropriate time. The combined signals are passed to a low-pass filter 13 which smoothes the pulse-coded signals to reconstitute the analogue signal. It is stated that the signal is only slightly degraded since although the feedback circuit 4 of the delta modulator 1 is modified by the insertion of a data signal element, the modulator tends to produce a complementary signal element during the next signal element period which effects some compensation. Compander circuits 14, 15 may be included at the transmitter and receiver respectively. A synchronizing signal for the control of the timing circuit at the receiver may be provided by a frequency divider at the transmitter and consists of alternate " 1 " and " 0 " at every mth signal element, Fig. 3 (not shown). The timing circuits at the transmitter and receiver may be controlled by a quasi-random code signal generator so that the data signal is inserted in a quasi-random sequence, Fig. 4 (not shown). The feedback circuit of the coder in these embodiments may be modified in that it is clamped to a neutral voltage midway between the voltages representing " 1 " and " 0 " when a data signal element is inserted, Fig. 5 (transmitter) and Fig. 6 (receiver) (not shown). In a further modification, Fig. 7 (not shown) a bistable circuit is arranged to introduce into the feedback circuit of the coder a signal element which is the complement of the immediately preceding signal element S whenever a dat a signal element is transmitted. A corresponding g arrangement may be provided at a receiver, Fig. 8 (not shown). In a further arrangement, Fig. 9 (not shown) the output S of the delta modulator is supplied to a chain of four bistable circuits interconnected by gating circuits so that consecutive digits in the output S are registered, permitting the digits immediately preceding and following each data insertion to be examined. When no data insertion is taking place the device acts as a shift register transmitting the digitized analogue signal normally. A data signal to be inserted is gated into the third bi-stable in the chain to replace the normal signal element and the logic is such that if the signal element to be replaced is the same as that inserted no compensation takes place but if it is different and one of the adjacent signal elements is the same then that signal element is inverted. A table giving the various possibilities and compensation effected is included. Alternatively, Fig. 11, compensation is effected at the receiver. The transmitter is similar to that shown in Fig. 1 but the coder feedback circuit is not modified by the inserted data signals. At the receiver the bi-stable circuits 90 to 93 act as a shift register and produce outputs representing the consecutive signal elements and their complements which when the analogue signal is at zero level consist of alternate ones and zeros. When an inserted data signal element arrives at bi-stable 90 the pulse H ceases, closing gate 39, and pulse H1 is applied to gate 96 and via a potential divider 97 to gate 98. When the signal elements A1, A2, A3, A4 immediately preceding a data signal element are 0, 1, 0, 1 respectively, both gates 96, 98 are opened but only the output level at gate 96 is effective as the output of gate 98 is at a neutral level determined by the potential divider 97. Hence a " 1 " is supplied via OR gate 99 to the low pass filter 13 in place of the inserted data element which is blocked by gate 39. If these signal elements A1, A2, A3, A4 are 1, 0, 1, 0 respectively, the gates 94, 95, 96, 98 are closed and a " 0 " signal is supplied to the filter 13. In the cases where the digits A1, A2, A3, A4 do not form an alternating pattern, the gate 94 is closed and gate 95 open and a neutral voltage from the potential divider is supplied to the filter 13.