Patent GB-802952-A (GB)
Title: Improvements relating to time division multiplex transmission systems
Inventor: FLOOD JOHN EDWARD
IPC: H04Q11/04
Filed: 1953-11-11
Abstract: 802,952. Automatic exchange systems. SIEMENS EDISON SWAN, Ltd., [formerly SIEMENS BROS. & CO., Ltd.]. Feb. 11, 1955 [Nov. 11, 1953], No. 31259/53. Class 40 (4). In a telephone system using time division multiplex transmission, a master selector translates pulses on one channel into code markings on a number of control wires. The control wires are multiplied to slave selectors. One slave, marked by an engaging tone, translates the code marking into pulses in the same channel as before. A slave selector may control a switch in a telephone connection so that it functions only during the time period allocated to the connection. Binary codes and four-in-nine codes are used. The 126 possible combinationsof four leads out of nine are cyclically marked with pulses by means of a generator comprising a pulse source and four interlocked electronic distributers. In a master selector, Fig. 1, for converting pulses on highway 11 into code markings on leads SWo to SWn, a trigger circuit T3 is set " on " by the first pulse passing through normally open gate 13. Gate I1 then opens and the first pulse passed by gates I1, I2 also passes one or more coincidence gates GAo to GAn marked by pulses on leads Po to Pn. The gated pulses are lengthened by devices LAo to LAn and the corresponding trigger circuits of TAo to TAn apply markings to the wires SWo to SWn. When a marking appears on any of the wires SWo to SWn, slow-to-release element SR1 and slow-to-operate element S02 respectively close gates II, I3 and restore triggers T3 and TAo to TAn, the slave selector controlled by SWo to SWn having had time to respond during the operating period of SO2. Gate 13 re-opens when element SRI releases. Trigger circuit T1 permits gate 12 to pass only one pulse per cycle. The trigger T1 closes gate I2 in response to the first pulse and restores only after the operating period of element SO1. In Fig. 2, which shows the same selector in detail, the gate 13 comprises rectifiers MR1, MR2, MR4 and feeds a positive pulse from lead 11 to trigger circuit T3 only when rectifier MR4 is non-conductive. The circuit T3 comprises a trigger-pair V1, V2 and a cathode-follower V3. Cathode follower V3 controls rectifier MR7 and provides H.T. for tubes V8 and V6X. A pulse on lead 11 is also transmitted by triode V4 (gate I1) providing that rectifiers MR7, MR8 are both non-conductive. A blocking oscillator V5 constitutes the gate 12 and the elements T1, SO1. A negative pulse on lead 12 is repeated as a positive pulse on lead 13. The time taken for the negative charge on the grid condenser Q3 to leak away after a pulse is longer than a cycle. A typical coincidence gate GAx is a rectifier gate marked by pulses on lead Px. The pulse lengthener LAx comprises a cold-cathode gas-filled valve V6X with an auxiliary gap in which a continuous discharge is maintained. The trigger circuit responds to mark lead SWx only when H.T. is provided by valve V3 in T3. The valve V6X is extinguished when T3 restores. The cathode follower V7 (isolating gate G2) responds to a marking on any of the leads SWx &c. to make triode V9 (SR1) and rectifiers MR4, MR7 conductive thereby closing gates I1, I3. Rectifier MR14 is blocked and gas discharge tube V8. receives a striking potential through a delay circuit R25, C7 to restore the trigger pairs V1, V2 (T3). The valve V3 is then cut off and the circuit returns to normal. The code markings on the n wires SWo to SWn may be made on a binary basis or on a code basis in which m out of n wires are marked. In a slave selector, Fig. 5, binary code' markings on seven wires SW0 to SW6 are converted into a pulse train on output lead 26 when the slave is signalled by an engaging tone on leads 28A. On removal of the markings, the pulse train continues until the engaging tone: stops. The engaging tone lowers the potential on leads 28B, 28D and enables the tubes VAO to VA6 to strike in response to the markings. The, potential on lead 28C is raised to close gate MR 19 which otherwise clamps lead 27 to a near ground potential. If VAO strikes, gate MRB0 closes for the whole of each cycle and MRC0 closes only during P0 (Phase 1) pulses. If VAO does not strike, gate MRC0 closes and gate MRBO closes only during the P0 (Phase 0) pulses. A positive pulse is transmitted over output lead 26 once in a cycle when all the gates MR19 and MRB0, MRC0 to MRB6, MRC6 are closed, i.e. in the one period defined by the binary code marking on the leads SWO to SW6 a complete cycle being 128 periods. The pulse markings on leads P0 (Phase 1), PO (Phase 0) to P6 (phase 1), P6 (Phase 0), are shown in Fig. 4. When the marking first appears on leads SW0 to SW6, tube V10 is not affected as resistor R36 is shortcircuited by rectifier MR50. On removal of the marking, V10 strikes and is maintained conductive as long as the engaging signal persists. The trigger electrodes are meantime backed off. In a modified slave selector, Fig. 8, the pulse channel is identified by a four-in-nine code illustrated in Fig. 7. The pulse marking leads PW1 to PW9 are fed by a generator to be desscribed, each time position being identified by pulses on a combination of four out of nine leads there being 126 different combinations per cycle. As before, an engaging tone on terminals 32A makes leads 32B, 32D more negative to enable gas discharge tubes VB1 to VB9 to strike in response to markings on leads SW1 to SW9. Lead 32C is made more positive to close gate MR24. When a marked tube VB1 strikes, the gate MRD1 opens and is subsequently closed only during marking pulses on lead PW1. A positive pulse is transmitted on lead 30 once per cycle in the channel identified by the four markings on leads SW1 to SW9. As before, the pulses are transmitted as long as the engaging tone persists and tube V11 guards against further selection. A generator for applying simultaneous pulses to the wires PW1 to PW9 four at a time and for running cyclicailly through all 126 possible combinations of four out of nine wires comprises a pulse source K, Fig. 9, and four interlocked electronic distributers A, B, C, D. Each distributer has six output terminals A1 to A6, B1 to B6, &c. which are multipled to the terminals PW1 to PW9 as shown. The distributers are so interlocked that C takes one step whilst D runs a cycle. B takes one step whilst C runs a cycle and so on. A complete cycle starts A1, B1 with C1, D1; C1, D2; C1, D3; C1, D4; C1, D5; C1, D6; C2, D2; C2, D3, &c. and involves 126 steps. The multiple connections translate the 126 combination into the 126.combinations of four of the nine wires PW1 to PW9. The distributer D, Fig. 10, comprises six output leads D1 to D6 and five similar switching stages, the first consisting of a trigger circuit ZD1, a normally open control gate CGID, a normally closed output gate OGID, a trigger control gate ND1 and an end element ED1 which sets the trigger " on " at the end of a pulse. The first pulse on lead 33 is passed to lead D1. Trigger ZD1 is set to "on," gate CGID closes arid OGID opens. The second pulse passes to D2, trigger ZD2 is set to " on " and so on. After the sixth pulse, end element ED6 restores all the triggers ZD1 to ZD5 to " off " and signals distributer C over lead LDC. A signal from distributer C on lead LCD1 sets ZD1 " on " again and the seventh pulse passes to D2. The trigger ZD1 is a trigger pair VDIE, VDIF, Fig. 12A, and gates CGID, OGID, NDI consist respectively of rectifiers MDIE and MDIF, MDIG and MDIH (Fig. 12B), MDIJ arid MDIK. Each output lead includes two amplifying triodes such as VDIJ, VDIK. The trigger pairs are normally " off " with VDIE conducting and VDIF cut off. The first pulse on lead 33 blocks rectifier MD5E in gate CG5D and the pulse is repeated by cathode follower VD5J to the control gate CG4D which repeats it likewise to CG3D and so on until the pulse passes to leads 51 and D1. As the anode potential of VD5E is low, triode VD5G is unaffected by pulses on lead 33 and gate OG5D is in effect closed. At the end of the first pulse, the end element ED1comprising a condenser CDIJ and a resistor . RDIQ transmits a positive pulse over lead 81 to set the trigger pair ZD1 " on " by making VDIF conductive. With a low anode potential on VDIF any positive pulse from CG2D is not repeated over lead 51. Gate CGID closes and OGID opens. With a high anode potential on VDIE, however, the pulse is repeated by triode VDIG. Thus gate CGID closes and OGID opens. The end element ED6 comprises a triode VD6L and a blocking oscillator VD6M which repeates a single pulse on lead 86A to reset the trigger pairs ZD1 to ZD5 and to signal distributer C over lead LDC. The distributer C, Fig. 11, which is the same as A and B, has trigger circuits ZC1 to ZC5, .control gates CGIC to CG5C, output gates OGIC to OG5C, &c. as in D. The pulses are fed from lead 33 to leads C1 to C6 as before but the triggers are set by pulses on LDC from distributer D. Six pulses from 33 pass to lead C1 before a pulse on LDC passes normally open control gate XC and sets trigger ZC1 to " on." After a delay introduced by slow-to-operate element SC1, to avoid a double trigger response, trigger control gate MC1 opens in readiness for the next pulse on LDC. When trigger ZC1 is set to " on " a signal is returned to D over lead LCD1. At the end of the single pulse transmitted over lead C6, end element EC closes XC, restores the trigger ZC1 to ZC5 and signals distributer B over lead LCB. A signal returned by distributer B over lead LBC1 and gate NC1 sets trigger ZC1 " on " again so that the next pulse, i.e. the first of the second full cycle of D, passes to C2.