Patent GB-1003923-A (GB)
Title: Digital computing system
IPC: G06F9/32
Filed: 1962-03-15
Abstract: 1,003,923. Electronic digital computers' SPERRY RAND CORPORATION. March 15' 1962 [March 24, 1961], No. 10005/62. Headings G4A and G4C. An electronic computing system comprises a plurality of computers, a common memory, a plurality of input-output units for feeding data to and receiving data from the memory, and an input-output processor effective to control by a programme the exchange of data between the memory and the several input-output units in accordance with predetermined priorities for the input-output units. General arrangement, Fig. 1.-The system described comprises digital computers 1-10, 1-11, an input-output section 1-12 which may comprise high-speed, medium speed and low speed I/O devices, such as magnetic drums, magnetic tape and printers respectively; an input-output processor comprising a central processor 1-14 generally similar to the computers 1-10, 1-11 but adapted to control the exchange of data between the I/O apparatus and a magnetic core matrix memory 1-15 common to all the elements of the system, the I/O processor also comprising a dispatcher 1-13 which includes I/O device priority circuits, conventional I/O buffer stores and address modifying circuits arranged to control the extraction of data and placing of data in sequential locations in the memory. The various components are arranged to address the memory 1-15 on a multiplex basis, the system operation being divided for this purpose into minor cycles of eight ¢ Ás time slots t0-t7, the computer 1-10 for instance addressing the memory only in time slots t0, t5. The memory is divided into 39 memory units, each unit comprising a core matrix such as is disclosed in Specification 769,384, and if a given unit is being addressed it is one minor cycle before it can be addressed again. Each memory unit includes a component priority circuit arranged to give priority to the various components in the order: (1) Dispatcher 1-13, (2) Central processor 1-14, (3) Computers 1-10, 1-11. Codes employed.-The system employs two codes: an " L " code in the central processor, and an " M " code in the memory. In the " M " code shown in Fig. 6, the decimal digits 0-9 are represented in a 5-bit " biquinary " type code of which bit 5 is a combined parity check and odd/even indicator. Bit 4 is a weighted bit, 0 for 0-4 and 1 for 5-9, and bits 1-3 are non-weighted but their components for digits 0-4 are the same as those for 5-9. The " L " code is another similar 5-bit code. An instruction word is of the form IINNNNNMMMMM (12 digits) where digits II represent a function and the digits N, M represent two respective memory addresses, the N digits also being capable of identifying particular I/O devices. System memory.-The memory, Fig. 2, comprises 39 3-dimensional matrix core units arranged in 10 cabinets and has a capacity of 97,500 words. To select a given storage address, the address digits are decoded in a memory address decoder (Figs. 4A-B, 8, not shown) to provide (1) a unit select signal on one of 39 unit select lines to select a particular memory unit and (2) X and Y address signals to select the word in the particular unit. The address digits are obtained either from the N or M digits of an instruction or from the address modifier circuits of the dispatcher 1-13 or from the control counter of the central processor 1-14 or from the control circuits of the computers 1-10, 1-11. In the operation of the memory both for reading and for writing, the memory goes through a read-write cycle, whereby the data contained in an address location interrogated is cleared or read out and new data or the old data is entered into the location. The memory control and priority circuits (Figs. 9A-C, not shown) include for each unit an interlock flip-flop adapted to prevent access to that unit when it is busy. Also included for each unit are interlock flipflops to control the access priorities of the inputoutput equipment and the central processor, the former having the greater priority. Central processor, Figs. 10, 10B.-This is a general-purpose stored-programme computer arranged to control the operation of the inputoutput devices and the dispatcher. The processor can perform various types of instruction: " book-keeping orders," " summary orders," " input-output instructions." A summary order is one delivered by a computer to the central processor where it is tested using the bookkeeping orders. In response to these tests, control is transferred to a particular sequence of central processor instructions. However, a sequence of instructions may be left and later rejoined at the same point. The central processor comprises various control and timing circuits, an arithmetic unit 10-41, instruction registers IR1, IR2 and temporary storage registers RP1, RP2. The " book-keeping orders " include " skip " (i.e. proceed to next instruction), " shift," " add," " subtract," conditional and unconditional transfer of control and various data transfer instructions for transferring data between the memory and the registers RP-1, RP-2. A high speed read bus HSB-R is adapted to carry information read from the memory 1-15, Fig. 1, either to the 1-word instruction register IR2, 10-11 via gates 10-10 if the information read out is an instruction, or to registers RP-1 or RP-2 if the information represents an operand, via gates 10-25 or 10-24 respectively. An instruction entered into the register IR2 is subsequently transferred to the register IB1, where the flipflops which register the two instruction function digits II are connected to an instruction decoder 10-17 (Figs. 12, 12A, not shown) comprising a gating matrix which produces a signal on a single output line, the particular line effective being also dependent on the output of a programme counter 10-19 (Fig. 16, not shown) adapted to cause to be generated various function table signals for instructions requiring a plurality of steps. The decoder 10-17 is connected to an instruction encoder 10-18 which produces a different set of output function table signals FT for each input from the instruction encoder 10-17, the FT signals being employed to control the various operations in the processor, dispatcher and drum and tape units. The " M " and " N " digits of the instruction in the register IR1 are transmitted in turn via " or " gates 3-31 to the memory address decoder 10-64, the " N " digits being also capable of addressing other items of equipment over connections not shown. The control counter 10-35 serves to address the memory for instructions to be executed by the central processor, and is normally stepped in response to a signal from the instruction cycle control 10-22, but in operations requiring a transfer of control, the normal sequence may be altered by transferring the " M " digits of the instruction in the register IR2 to the control counter 10-35 via gates 10-37. The contents of the control counter 10-35 can be transferred to the memory, if this is required, via gates 10-36. Thus, in a " return jump " instruction, the " M " digits sorted in the register IR1 are transferred to the control counter 10-35, the 5-digits contents of which are stored in the address designated by the " N " digits of the instruction. The remaining seven most significant digits are derived from a register 10-38 which stores the digits 0500000, the " 05 " function digits of the instruction thus formed, denoting the unconditional transfer instruction. Data paths.-The data read from the memory in response to an instruction in the register IR1 is transferred via the bus HSB-R either to register RP1 or to register RP2 from which data may be transferred back to the memory, or, via gates 10-47, 10-48, 10-65 to the addercomparator 10-41. The adder-comparator 10-41 (Figs. 18-25, not shown) produces sum or difference signals and also, on lines FC, EQ during a comparison operation signals indicating that the content of RP1 is greater than that of RP2 or that the contents are equal, respectively. These signals cause recomplementing of the result if this is required. The arithmetic control circuits 10-42 (Fig. 27, not shown) are also supplied with the content of the registers RP1, RP2 and produce a CP signal applied to the adder-comparator 10-41 and adapted to control addition or subtraction according to the signs of the contents of the registers RP1, RP2. Performance of instructions.-The instruction cycle control circuit 10-22 (Fig. 11, not shown) causes the performance of instructions in three steps: (1) the memory is addressed and the selected instruction stored in the register IR2, (2) the instruction is read into the register IR1, (3) the control counter 10-35 is stepped. The first instruction is selected by the control counter 10-35. Subsequently, the " M " and "N" portions of an instruction are given priority over the control counter in addressing the memory. The operation of the various components in the central processor is described in detail in the Specification, with reference to Figs. 11-28 (not shown). Book-keeping instructions.-The following thirteen central processor instructions are described in detail in the Specification, with reference to timing diagrams, Figs. 87-94 (not shown):- (i), (ii). The " 15 " and " 12 " instructions are effective to transfer data from the memory location specified by the " N " digits of the instruction to one of the registers RP1, RP2. (iii), (iv). The " 13 " and " 16 " instructions are effective to transfer the contents of the registers RP1 or RP2 to the memory location specified by the " N " digits of the instruction. (v). In the unconditional transfer instruction, " 05," the five " M " digits thereof are transferred to the control counter 10-35 and designate the address of the next instruction. (vi). In the return jump instruction, " 14," which has the form 14 NNNNNMMMMM, the five " M " digits are transferred to the control counter 10-35 and the contents of the c