Patent GB-1480764-A (GB)
Title: Transit exchange for asynchronous data
IPC: H04L12/52
Filed: 1974-07-29
Abstract: 1480764 Data exchanges TELEFONAKTIEBOLAGET L M ERICSSON 29 July 1974 [10 Aug 1973] 33465/74 Heading H4P  In a transit exchange for transmission of asynchronous data signals with unknown character structure and data rate from sending terminal equipments to receiving terminal equipments the exchange comprises control equipment SU, Fig. 1, including a processor and sampling equipment SA common to sending terminal equipments and working in a time division multiplex manner to sample the momentary values of received data signals on incoming lines by means of sampling pulses. The processor includes an encoder KA, Figs. 1 and 3, which works synchronously with the sampling equipment SA and consists of a flank encoder logic FKL which works in a time division manner and a flank encoder memory FKM connected to it. The encoder is such that by successive processing of the sampling pulses it establishes whether the data signals have changed their value between two consecutive sampling pulses. If they have changed their value the encoder KA delivers an indication signal in the form of a code word comprising a specific number of binary bits which indicate the time position for the sampling pulse occurring after the change. The processor also includes an intermediate memory FM to which the binary bits are transferred in serial form and stored one at a time at an address belonging to the receiving terminal equipment and a decoder AA which consists of a decoder logic AKL working in a time division manner and a decoder memory AKM connected to it. The decoder is such that through successive processing of the binary bits it forms indication signals which alter their values in accordance with time position indicated by the code word. The processor further includes regeneration devices RA101-RA416 each associated with a respective receiving terminal equipment and read out equipment UA which works synchronously with the decoder AA for transferring the values of the indication signals cyclically from the decoder to the respective regeneration devices to form from the received indication values data signals which change their value in synchronism with the indication signals. For character elements arriving from A or B subscribers information is stored in addresses 101 and 416 of the encoder memory FKM. On write-in in the buffer memory BM of the intermediate memory FM which comprises a parallel series converter the element information derived from the A subscriber is placed in the B subscriber's memory cell and vice-versa. For this purpose address information is used which has been stored in the address register memory ARM during a switching phase during which selection information has been received from the A subscriber and analysed by the control processor SU. The control processor SU has a switch memory KM in which received character elements are temporarily stored while being processed by a logic equipment KL. A detailed operation of the encoder KA and decoder AA is disclosed (Figs. 5 and 6, not shown) in which each encoder and decoder employs three memories (M1, M2 and M3) for their respective memories FKM, AKM. The processing of the indication signals in the control equipment SU and intermediate memory FM takes place at a speed which is considerably lower than that at which the other units work. The speeds can differ by a factor of 8. This can be used for extending the capacity of a transit exchange by allowing up to eight sampling equipments and encoders and decoders and read out equipments each with its line group to interwork with a common extended buffer memory while retaining a common control equipment SU with a correspondingly extended switch memory. In an example the capacity of the transit exchange can be extended by employing three sampling equipments (SA1- SA3, Fig. 7, not shown), three decoders (AA1- AA3) and three corresponding read out equipments (UA1-UA3) successively operated in cyclic pattern. Alternately the capacity can be extended by increasing the capacity of the buffer memory BM and output buffer UB in a number of identical units of the type described in Figs. 1 and 3 and interconnecting these units with one another with OR circuits (G1-G3, Fig. 8, not shown).