Patent GB-1098332-A (GB)
Title: Multiple receiver acoustic well logging
Inventor: ZEMANEK JOSEPH
IPC: G01V1/44
Filed: 1965-03-11
Abstract: 1,098,332. Acoustic velocity well logging; switching circuits. MOBIL OIL CORPORATION. March 11, 1965 [March 16, 1964], No. 10373/65. Headings H3T and H4D. In an acoustic velocity well-logging system, the effects of local variations in the well diameter on the measurement of the travel time of an acoustic pulse between transmitter and receiver in a logging tool are reduced by deriving first signals representing the difference between the respective travel times of an acoustic pulse between a transmitter and a first pair of receivers, deriving second signals representing the difference between the respective travel times of an acoustic pulse between the transmitter and a second pair of receivers, delaying said first derived signals and combining them with said second derived signals. In a first embodiment, a transmitter (T) is arranged between a pair of receivers (R 1 , R 2 ) and a pair of receivers (R 3 , R 4 ), (Fig. 2), and is operated at intervals by a pulser (12) which also triggers a ramp voltage generator 29. Receivers (R 1 , R 2 , R 3 , R 4 ) are cyclically connected to uphole equipment through twoinput OR-gates (20, 21, 23) which are set in their appropriate open or closed states after each reception of an acoustic pulse, the gate settings being determined by two two-level control voltages applied to a pair of signal lines 14, 19. A pulse received when (R 3 ) is connected to the uphole equipment passes through a gate 31, which is opened only during the interval in which reception of a pulse is expected, and causes the operation of a switch 34, whereby the instantaneous ramp voltage of generator 29, representing the travel time (t 3 ) of the pulse, is sampled on a capacitor 41. The received pulse also triggers bi-stable circuits 36, 37, whose outputs provide the gate control voltages for lines 14 and 19 and also control relays 39, 43 for selectively connecting switch 34 to capacitor 41 or three further capacitors 35, 40, 42. The arrangement is such that the next acoustic pulse is detected by receiver (R 4 ) and its travel time (t 4 ) recorded on capacitor 42. The measurement of travel times (t 1  and t 2 ) to receivers (R 1 ) and (R 2 ) is made when the logging tool has been lowered in the well a distance d to a position such that the acoustic pulse travels through the same earth section to receivers (R 1 ) and (R 2 ) as it did to receivers (R 3 ) and (R 4 ), (Figs. 1, 1A). The voltages on capacitors 35 and 40 are applied to circuits 45, 46, 47 for obtaining a signal representing the difference between the travel times t 1  and t 2 . A similar difference signal is obtained from circuits 50, 51, 54 for the travel times t 3  and t 4 . It is shown mathematically that the mean of the two difference signals represents the acoustic velocity free from error due to welldiameter variation and independent of any coupling medium between the well walls and the logging tool. The mean value is obtained by applying the difference signal t 3 #t 4  to a tape delay unit 55, which introduces a delay equal to that involved in lowering the logging tool the distance d, and combining the delayed difference signal with the difference signal t 1 #t 2  in a circuit 56, 57, 58. The representation of the acoustic velocity is then logged as a function of depth by a recorder 59. For making measurements at the bottom of a well, the difference signal t 3 #t 4  may be recorded directly on recorder 59. In a second embodiment, the downhole receiver gates are selectively opened by a four-level D.C. control voltage applied to a single signal line (75), (Fig. 5). The D.C. levels are derived from a resistive potential divider (Fig. 6, not shown), or a diode-transistor circuit (Fig. 7, not shown), and the particular D.C. level appearing on line (75) is determined by the bi-stable circuits 36 and 37. Production and utilization of the four-level D.C. control voltage.-In the Fig. 6 circuit, relays 39 and 43 are controlled by the bistable circuits 36, 37 so as to cyclically connect 0, 5, 10 and 15 volt tappings on a potential divider chain (101, 102, 103) through an emitter follower stage (104) to line (75). In the Fig. 7 circuit, when the right-hand element in each of the bi-stable circuits 36, 37 is conducting diodes (105 and 110) are forward biased by a D.C. voltage source (108), and the voltage across emitter resistor (113) is zero. If bistable circuit 36 is switched to its second stable state, diode (105) is reverse-biased and base current through resistor (109) gives a 5-volt drop across resistor (113). If bi-stable circuit 37 is switched to its second stable state, base current through resistor (112) gives a 10 volt drop across resistor (113). With circuits 36 and 37 both in their second stable state, 15 volts appear across resistor (113). The four-level D.C. signal is fed downhole over line (75) to three parallelled potential divider networks having tappings connected to bistable circuits (MV1, MV2, MV3), (Fig. 2), which control the two-input OR-gates. The bi-stable circuits (MV1, MV2, MV3) require a 5 volt trigger signal, and the component values of the potential divider networks are such that a 5-9 volt signal on line (75) triggers (MV1), a 10-14 volt signal on line (75) triggers (MV1) and (MV3), and a signal greater than 15 volts on line (75) triggers (MV1), (MV2), (MV3). Zener diodes (80, 84) prevent excess voltages from being applied to the trigger inputs of (MV1) and (MV3). Circuits for a bi-stable circuit and a two-input OR-gate are given (Figs. 8 and 9, not shown).