Patent GB-1320729-A (GB)
Title: Semiconductor devices
IPC: H01L23/485
Filed: 1970-10-01
Abstract: 1320729 Semi-conductor devices SONY CORP 1 Oct 1970 [2 Oct 1969] 46778/70 Heading H1K A high impurity N-type silicon substrate 1 has on one surface a vapour growth layer 2 of low impurity silicon of the same conductivity type as the substrate to serve as collector on which is deposited an impurity diffusion mask insulent 3 of silicon dioxide or nitride or alumina. An amorphous polycrystalline semi-conductor silicon layer 4 is formed by vapour growth or sputtering and an etching mask of photoresist 17 are formed on the insulant, and a window A B  in the layers 4, 3 is formed by etching, through which p-type impurity is diffused into layer 2 to form base region 7 and collector junction J C ; in an oxidant atmosphere without pitting (Fig. 2c). Simultaneously insulant silicon oxide films 35 are formed by thermal oxidation of the layer 4 and base regions after which window AE is etched and N-type impurity diffused therethrough to form emitter 8 and emitter junction J E , after which windows 9B, 9E, 6 are etched and metal base and emitter electrodes E B , E E  are deposited therethrough (Fig. 2E) the base electrode being extended through window 6 to layer 4 with ohmic contact to reverse bias junction J C  (Figs. 2F, 2F<SP>1</SP>) a collector electrode E C  being superimposed on the back of the substrate. The layer 4 overlies junction J C  and insulant layer 3 and is rendered highly conductive by diffusion during formation of region so that it is supplied with base electrode voltage. Since junction J C  is covered with insulant 5, the emitter electrode E E  can overly the latter. Thus the breakdown voltage of the device is enhanced and electrodes E B , E E  are unlimited in size to facilitate attachment of bonding pads by extension. Since the base region 7 is diffused through layer 4 forming a mask fixed with relation to junction J C , region 7 may be minimised in area. In a modification applied to an integrated circuit containing plural S/C elements, N-type silicon layer 11 is formed by vapour growth on a p-type substrate 10 and a p-type region 12 is diffused into layer 11 to divide it into plural islands of N-type material 13A, 13B, 13C and an overall oxide film 14 is formed, over which a silicon polycrystalline layer 15 is deposited. Layers 14, 15 on islands 13B are etched to form a window 17 into which p-type impurity is diffused to form base region 18 and layer 15 is also etched into window 20 for collector electrode; the diffusion process doping layer 15 to raise its conductivity and depositing oxide layers 19, 21 on layer 15 and base region 18. Layer 21 is etched to window 22 for diffusion of N-type impurity to form emitter region 23 (Fig. 3b) and layer 19 is etched to window 29 for electrode 30 deposited on the polycrystalline layer and connected to substrate electrode 31 (Fig. 3C). Similarly collector base and emitter electrodes are deposited on corresponding regions 13B, 18, 23. Transistor, diode, or resistor elements are similarly formed on islands 13A, 13C. Substrate 31 and layer 15 are held at a low potential with reference to the remaining electrodes and to enhance the breakdown voltage of the PN junctions in the islands, and at the junctions between islands and isolant regions.