Patent GB-1329220-A (GB)
Title: Stored charge device
IPC: H01L29/00
Filed: 1970-04-21
Abstract: 1329220 Semi-conductor devices CALIFORNIA INSTITUTE OF TECHNOLOGY 11 Aug 1970 [11 Aug 1969] 19075/73 Divided out of 1326794 Heading H1K A metal nitride oxide silicon FET for charge storage comprises a semi-conductor substrate of, e.g. N-type Si overlain by a thin insulant layer 18 of thermal SiO 2  (#100 Š) covered by a thin (#100 Š) buried laterally discontinuous metal layer 30 buried by an overlying metal oxide or nitride insulant layer 20 formed thermally or by plasma discharge. On the latter is placed a gate electrode 22 the field effect of which produces an inversion P-type channel layer 12 interconnecting P + diffused regions 13 having source and drain electrodes 14, 16. A pulse generator 24 between gate and drain applies high voltage pulse for charge storage, and for readout a lower amplitude pulse is applied between gate and drain while a current detector 26 and D.C. supply 27 is connected between source and drain; the level of current on readout differing in amplitude between stored charge and zero or reversed charge. Layer 30 introduces a deep energy well operating as a charge trap with unity capture probability, so that high voltage gate-drain pulses add or remove electrons as the pulse is negative or positive, and the electrons are retained in the wall in the absence of applied field (Fig. 3, not shown). Insulator 20 is formed, e.g. by oxidizing or nitriding metal layer 30, e.g. of Al and the films may be of #100 Š thickness, and in formation the Si substrate is thermally oxidized to SiO 2 , and an, e.g. Al layer is applied, and is oxidized or nitrided to form the outer insulant. To improve charge retention, the buried metal layer is formed as plural laterally spaced and separately insulated buried layers. In a modification (Fig. 4, not shown) a semiconductor film (which may be depletion mode polycrystalline) is deposited on an insulant substrate to support insulant layer 18. Plural such devices 82 may be assembled in a memory network (Fig. 5) with drains 84 connected to Y line 86 of Y access switch 88, and gates 96 connected to X lines 94 of X access switches 92; the sources being connected to common lead 100. Write in is produced by an appropriate polarity voltage pulse of amplitude exceeding a critical value to store charge; derived from pulse generator 80 between inputs of X and Y access switches 92, 88 enabling selective addressing of single X and Y lines 94, 86 to apply or remove charge at intersection. Read out is produced by current detector 90 and D.C. source 91 in series between lead 100 and input to Y access switch 88, and for destructive readout an excitation pulse of predetermined polarity and amplitude is applied between gate and drain to produce a detectable current increase if the pulse exceeds stored charge threshold voltage. N on destructive readout is produced by optical or electron beam scanning; optically dependent on internal photoemission over the barrier height of the insulant films varying with stored charge to produce photoemission currents of corresponding amplitude, or electrically dependent on stored charge surface potential in similar manner to an electron microscope.