Patent GB-1403805-A (GB)
Title: Testing of non-linear circuits
IPC: G06F11/26
Filed: 1973-03-13
Abstract: 1403805 Circuit testing systems INTERNATIONAL BUSINESS MACHINES CORP 13 March 1973 [17 March 1972] 12109/73 Heading G4A A system for determining which steps of a test pattern comprising a number of sequential steps are required in order to detect all possible "stuck" faults in a non-linear electrical circuit includes computer simulation of the fault-free (good) circuit and of faulty (bad) circuits. A stuck fault is one in which a node of the circuit is fixed at a certain voltage level. Each faulty circuit simulation simulates the circuit when a particular one of the stuck faults exists in it. The circuit is non-linear in that its output depends upon the sequence of signals fed to its input nodes. In the case of a circuit in which each node can take either of two levels, e.g. a binary logic circuit, a test pattern is formed, e.g. by use of a pseudo-random number generator, comprising all possible combinations of bits in parallel to be fed in turn to the input nodes (20, Fig. 1, not shown). Each combination is identified by an ordinal number. A list of the possible single stuck faults is also made (21); this will be twice the number of nodes in the circuit. The parallel bit signal forming the first step of the test pattern is now applied to the computer simulations of the good circuit and each bad circuit in turn (25). The output signals of the good circuit are compared with those of each bad circuit (26). If there is an inequality the pattern step ordinal number and the identity of the relevant bad circuit are stored (28), and this bad circuit takes no further part in subsequent comparisons. The next step of the test pattern is now applied to the good and the remaining bad circuits, the outputs compared, and the step number and identities of any bad circuits resulting in inequality are stored, as before. This procedure is repeated until the identities of all the bad circuits are stored (30). It is now necessary to determine, for each bad circuit, how many of the sequential steps of the test pattern are necessary to locate the fault. A counter is set to indicate the number of possible faults (33, Fig. 1A, not shown). The highest stored step number n is applied to the good circuit simulation and to the bad circuit simulation which was identified by this step (34). If the outputs of the circuits are equal (37) there are applied to the circuits the test pattern steps n-1 followed by n (39), and a further comparison is made (37). This procedure is repeated, the sequence of steps being increased by one in the direction of decreasing ordinal number in each cycle, until there is inequality of output at (for example) the i-th step. This sequence of steps i to n is therefore necessary to identify this particular stuck fault and is stored (40). The counter is now decremented (41) and the next highest stored step number applied to good and relevant bad circuits, as before, to find the steps necessary to identify the fault. This is repeated until sequences of steps have been found for each fault. A sequence may consist of only one step. The sequences of steps represent those few steps of the original test pattern necessary to identify all stuck faults. Further reduction in the number of necessary steps may be possible since some of the step sequences may be able to identify more than one fault. This reduction is obtained as follows. When a step sequence i to n has been formed in respect of a particular fault (40) and the counter decremented (41), this sequence is applied to the good circuit and each bad circuit corresponding to the remaining faults, (51, Fig. 2, not shown). If any bad circuit output disagrees with the good circuit output (52) this means that the corresponding fault also is identified by the sequence. This fault is therefore now associated with this sequence (53) and removed from the list of faults (54). The counter is decremented by the additional number of faults identified by the sequence (55) and the next sequence i to n determined in respect of the fault associated with the next highest stored step, as before (34-40). When this sequence is found, it is again determined whether the sequence will identify any remaining faults, as just described, and so on. The resulting step sequence are the minimum necessary to identify all stuck faults.