baber/WOPTO huggingface dataset:
Patent JP-H02207564-A (JP)
Title: Semiconductor integrated circuit device
Inventor: KAWAMOTO MITSUO
IPC: G11C11/409
Filed: 1989-02-06
Abstract: PURPOSE:To reduce the malfunction of data reading out, circuit operation, etc., by a method wherein the substrate potential is fed to the peripheral part near a sense amplifier circuit. CONSTITUTION:When a word line 30 of one of divided memory cell array 2A is selected, the data in minor potential of a memory cell M are read out of the whole complementary data line 37 of the memory cell array 2A. Next, all of respective sense amplifier circuits of sense up circuit 4A are driven by the sense amplifier driving signals phip transmitted from a timing producing circuit 6 conforming to the control signals from an external device. Through these procedures, the data read out on the complementary line 37 are amplified and later, the data selected by a column select decoder circuit 3A are outputted out of a DRAM 1. When the sense amplifier circuit 4A is driven, the substrate potential VBB in a p type well region 21 is boosted, but a wiring 40 is extended over the region 21 to actively feed the region 21 with the substrate potential VBB so that the region 21 may be instantaneously fed back with the substrate potential VBB. Through these procedures, the inversion of data, the multifunction of data reading out and peripheral circuit operation are reduced, thereby enhancing the electrical reliability.
Patent JP-H07240344-A (JP)
Title: Chip-shaped solid electrolytic capacitor
Inventor: NAITO KAZUMI
IPC: H01G9/012
Filed: 1994-02-25
Abstract: PURPOSE:To relax the deterioration of a chip-shaped solid electrolytic capacitor at the time of resin sealing of the capacitor to improve the yield of the capacitor by a method wherein the width of a conductor layer formation part and the width of a projected part of a lead frame is set in the same size. CONSTITUTION:Anode and dielectric layer formation parts 7 and 8 of a solid electrolytic capacitor element 5 formed by a method, wherein dielectric oxide film layers 2 are respectively formed on the surfaces of an anode base body 1, semiconductor layers 3 are respectively formed on the layers 2 and moreover, conductor layers 4 are respectively formed on the layers 3, are respectively placed and bonded on projected parts 6a and 6b of a lead frame. The width of the part 8 and the width of the part 6b of the lead frame is set in the same size. Thereby, the yield of a chip-shaped solid electrolytic capacitor can be improved.
Patent JP-H06219768-A (JP)
Title: Quartz glass material and its production
Inventor: ITO NORIAKI
IPC: C03C3/06
Filed: 1993-01-26
Abstract: PURPOSE:To provide a quartz glass material having high viscosity and a slight deformation due to heat even in use in a long period of time at a high temperature. CONSTITUTION:A quartz glass material comprises high-purity quartz raw material powder having <=1ppm total content of alkali metals consisting mainly of Na, K and Li, <=10ppm of each metal impurity and one or more uniformly dispersed metal atom components selected from the group composed of Al, Y and La constituting a nucleating agent of crystobalite crystal growth at >=1,400 deg.C.
Patent JP-H10215122-A (JP)
Title: Reception signal amplifier and antenna device for reception provided with the amplifier
Inventor: YANAGISAWA KAZUSUKE
IPC: H03F1/52
Filed: 1997-01-28
Abstract: PROBLEM TO BE SOLVED: To provide an antenna device for reception with the small number of parts for preventing the destruction of an amplifier circuit by electric pulses. SOLUTION: FM signals and AM signals are separated by an FM separation circuit 12 and an AM separation circuit 14 connected to the base end of an antenna element 10. The FM signals are supplied to an FM amplifier circuit 24 and an FM dielectric breakdown prevention element 26. The FM amplifier circuit 24 and the FM dielectric breakdown prevention element 26 are formed on an FM semiconductor chip 28 in the manufacture process of a bipolar transistor. The AM signals are supplied to an AM amplifier circuit 30 and an AM dielectric breakdown prevention element 32 and the AM amplifier circuit 30 and the AM dielectric breakdown prevention element 32 are formed on an AM semiconductor chip 34 in the manufacture process of a junction type field effect transistor.
Patent JP-S63196950-A (JP)
Title: Reset circuit for microprocessor
Inventor: IMAI KIYOSHI
IPC: G06F11/14
Filed: 1987-02-10
Abstract: PURPOSE:To restore a microprocessor to normal operation by detecting the malfunction to cause the initializing operation by a reset synthesizing circuit if a vertical address is not changed three horizontal periods or more. CONSTITUTION:The waveform of a horizontal synchronizing pulse input terminal 1, the a/8 waveform of a frequency divider 29, and input waveforms of FFs 20, 21, and 22 are denoted as (a), (b), (c), (d), and (e) respectively. If the malfunction occurs in the fifth period of the waveform (a), the waveform (a) is in a low level in following periods, and waveforms (c), (d), and (e) go to the low level at the time of the seventh period. Therefore, an output (f) of an AND gate 27 goes to a high level through inverters 23-25 and an output (g) of an OR gate 28, namely, the output of a malfunction detecting circuit 32 goes to the high level. As the result, an output (h) of a NAND gate 30 goes to the low level in the tenth period of the waveform (a), and a supply voltage rise detecting signal terminal 11 is in the normal high level, and an output (i) of an AND gate 31, namely, an output (i) of a reset synthesizing circuit 33 is in the low level only in the tenth period of the waveform (a). Consequently, each circuit is initialized and is restored to the normal operation.
Patent JP-H03233942-A (JP)
Title: Field-effect transistor and its manufacture
Inventor: NAKAJIMA SHIGERU
IPC: H01L21/338
Filed: 1990-02-08
Abstract: PURPOSE:To obtain an FET, whose drain breakdown strength is high, with good reproducibility and with good uniformity by a method wherein a stepped part is formed in an active-layer region of a semiconductor substrate, a gate electrode and a source region adjacent to it are arranged on the lower face of the stepped part and a drain region is arranged on the upper face of the stepped part so as to be away from the gate electrode. CONSTITUTION:A stepped part is formed in advance on a semiconductor substrate 11; after that, an active layer 14 is formed over the upper face and the lower face of the stepped part; a gate electrode 16 is formed on the active layer 14 on the lower face of the stepped part; a source-side high-concentration region 19 is formed in the region of the active layer on the lower face of the stepped part in a self-aligned manner with the gate electrode 16; a drain-side high-concentration region 20 is formed in the region of the active layer on the upper face of the stepped part; electrodes are formed respectively on the individual high- concentration regions. In this manner, the active layer 14 is provided along the step-shaped stepped part; the gate electrode 16 and the source region 19 adjacent to it are arranged on the lower face of the stepped part; only the drain region 20 is arranged on the upper face of the stepped part so as to be away from it. By this arrangement, an FET is formed. Thereby, the field-effect transistor FET whose drain breakdown strength is high in the same manner as that of a so-called recess structure can be obtained with good uniformity and with good reproducibility.
Patent JP-S56123173-A (JP)
Title: Facsimile device
Inventor: MIWA HIROSHI
IPC: H04N1/413
Filed: 1980-03-05
Abstract: PURPOSE:To make it easy to put a high-speed device for a DDX (digital data switching) network to practical use by reading and encoding as one block the information signals of not less than one line while feeding an original in the subscan direction, and by sending codes to a transmission circuit synchronizing with the subscan. CONSTITUTION:Picture signal S1 of lines read by image snesor 8 is stored in line memories 20a and 20b and encoded as one block by encoder 11; and then codes are stored in buffer memories 22a and 22b and then sent out successively from transmitter 13 synchronizing with an X-directional scan. For example, counter 21 and function generator 23 are provided in the course of the transmission and the readout time and displacement speed are calculated to vary the feed speed and acceleration of an original through driving DC motor 24 in a sine wave, etc., so that they will be zero in the beginning and ending of the scanning of one block. Thus, the high- speed operating device for a DDX network can be put to practical use by using a paper feeding mechanism, etc., similar to an in-use machine, without requiring a large-capacity memory.
Patent JP-H02207667-A (JP)
Title: Facsimile transmitter
Inventor: SATO TAKASHI
IPC: H04N1/413
Filed: 1989-02-07
Abstract: PURPOSE:To improve the picture quality of a reproduced message by selecting whether the next message is received by a one-dimensional encoding system or the communication speed of a modulator is made low and executing transmission when the message can not be satisfactorily received by a two-dimensional encoding system. CONSTITUTION:A facsimile transmitter is constituted by providing a procedure signal transmission/reception part 1, control part 2 and encoding part 3 and the procedure signal transmission/reception part 1 executes the reception of an initial identification signal, the transmission of an incoming call instruction, the transmission of in-message procedure, the transmission of a post-message instruction and the reception of a post-message response. The encoding part 3 executes the in-message procedure of the one-dimensional encoding system and two-dimensional encoding system according to the instruction of the control part 2 and sends the procedure signal through the procedure signal transmission/reception part 1 to a line. The two-dimensionally encoded message is received at the first communication speed by the modulator. When a retrain deny signal is received from an opponent side as the post-message response, it is selected whether this message is transmitted by the second communication speed lower than the first communication speed or the message is one- dimensionally encoded. Then, the message is transmitted. Thus, the picture quality of the reproduced message can be improved.
Patent JP-S59154482-A (JP)
Title: Hologram and its preparation
Inventor: YAMAZAKI TETSUJI
IPC: G03H1/18
Filed: 1983-02-23
Abstract: PURPOSE:To obtain a hologram record consisting of >=2 hologram records good in quality with high yield by coating a hologram record with a positive type photoresist, exposing it to an optical hologram pattern, partially exposing it to UV rays through a mask pattern, and developing it. CONSTITUTION:A relief hologram 1 having peaks and valleys 22 is coated with a positive type photoresist 31, exposed to laser beams to record another hologram, and developed to form another relief hologram 2 having other peaks and valleys 32. Then, it is covered with a mask pattern 41 not transmitting light at prescribed parts and exposed to UV rays. The parts of the photoresist decomposed with the UV rays are removed by development, and a hologram 3 can be obtained consisting of parts of the first hologram 23 having the peaks and valleys 22 and as the rest, the second hologram 33 having those 32 overlaid on the first.
Patent JP-S59154843-A (JP)
Title: Loop back control system
Inventor: HASHIMOTO TOYOKAZU
IPC: H04L12/437
Filed: 1983-02-23
Abstract: PURPOSE:To simplify the loop back control by utilizing effectively functions such as clock extraction of each relay station in a loop back control system by a control station provided to a double loop transmission line. CONSTITUTION:Suppose that loop lines 3, 4 are opened at the same time between terminal tations (m) and (n) being relay stations. A control station 1 transmits a clock to the line 3 by superimosing it on a carrier wave. Terminal stations 2-(m-1) receive it so as to be able to receive a indication frame from the control station by extracting a clock therefrom. No clock is received from the terminal station (n) and succeeding due to broken lines. The control station 1 gives a folding indication to the terminal (m). The terminal (m) ties the lines 3 and 4. This operation is attained also to the line 4 similarly, and the lines 4 and 3 are connected at the terminal (n). When the carrier wave transmitted to the line 3 is received from the line 4, the control station 1 recognizes that the loop back is finished.
Patent JP-H07237569-A (JP)
Title: Pasting method for protecting film on car body upper surface
Inventor: NAKAYAMA TAKASHI
IPC: B62D65/00
Filed: 1994-02-28
Abstract: PURPOSE:To attain reduction of a use amount of protecting film and improvement of efficiency of cut removing work, in a method of pasting the protecting film on a car body upper surface for pasting the protecting film on a car body front part upper surface including a bonnet of each car body, car body rear part upper surface including a trunk lid and to a roof upper surface, on a vehicle manufacturing line for conveying a plurality of kinds of the car bodies mixed after completion of painting. CONSTITUTION:Protecting films 16, 17, 18 of shape almost corresponding to each upper surface 13 to 15, having circular arc-shaped end edges 16a, 17a, 18a in accordance with at least one of front/rear end edges of each upper surface 13 to 15, are prepared for each of car body front part upper surface 13, car body rear part upper surface 14 and roof upper surface 15. If at least one of the front/rear end edges of each upper surface 13 to 15, after each protecting film 16 to 18, in a condition that the circular arc-shaped end edges 16a to 18a are mated, is pasted on the corresponding upper surfaces 13 to 15, an unnecessary part of each protecting film 16 to 18 is cut removed.
Patent JP-S55122912-A (JP)
Title: Self-elevation type working-platform vessel
Inventor: NISHIOKA SHIYUUSUKE
IPC: E02B17/00
Filed: 1979-03-13
Abstract: PURPOSE: To place an upper leg on a lower supporting leg and add the former to the latter by performing rotary traverse of the upper leg from its housing position to that of its adding in working-platform vessel having the upper leg and the lower supporting leg.  
     CONSTITUTION: A lower supporting leg 2 is fitted to a working-platform vessel 1 movably up and down by an elevation device 10, while an upper leg 7 is moved in a traversing way on rails from its housing position to that of its adding and is placed on the lower supporting leg 2. Next, the upper leg 7 is added to the lower supporting leg 2. In this way, the lower leg can be lifted and lowered without the aid of a separate barge or crane and irrespective of the upper leg, thus the working-platform vessel being jacked up only by the lower leg. 
     COPYRIGHT: (C)1980,JPO&Japio
Patent JP-S58146824-A (JP)
Title: Apparatus for detecting abnormal temperature rise
Inventor: KUSHIHASHI KEIZOU
IPC: G01K5/48
Filed: 1982-02-25
Abstract: PURPOSE:To detect very easily an abnormal temperature rise, by arranging a shape memorizable alloy wire or plate which transforms to preliminarily memorized shape in the vicinity of a body to be detected for the abnormal temperature rise and projecting this wire or plate. CONSTITUTION:For example, three electric conductor 1 are supported in series with an insulating material 2 and a connecting parts stored in a duct 3 are tightened with bolts etc. so that the conductors are superimposed with one another and moreover, a cover 4 is attached to the upper end lower surfaces to form a bath duct. A shape memorizable alloy plate 6 which is transformed to the formerly memorized shape at the preliminarily set temperature is attached by pins to the upper surface of the cover 4 covering this connecting parts. This shape memorizable alloy plate or wire is arranged so as to project at the time of transformation and hereby, an abnormal temperature rise of a body to be detected for the abnormal temperature rise is found very easily.
Patent JP-H05223722-A (JP)
Title: Odorant sensor
Inventor: YOKOYAMA KENJI
IPC: G01N5/02
Filed: 1992-02-17
Abstract: PURPOSE:To obtain an odorant sensor which can quickly and highly sensitively discriminate an odorous substance. CONSTITUTION:The odorant sensor incorporate at least one head 3 provided with an organic thin film 9 which selectively adsorbs an odorous substance through an electrode on the surface of at least one of a quartz resonator and surface elastic wave element and discriminates the odorous substance from the variation of natural frequency of the head 3. In addition, a means 4 which supplies a gas containing the odorous substance to the organic thin film 9 of the head 3 is provided near the head 3.
Patent JP-S60175142-A (JP)
Title: Digital operation circuit
Inventor: KARIBE HIROHISA
IPC: G06F7/74
Filed: 1984-02-20
Abstract: PURPOSE:To attain multiplication limitated in bit length without increasing the number of processing cycles by adding an effective bit position, bit length specification register and a bit length limitation register to a fixed point multiplying circuit. CONSTITUTION:In this operation, a judging circuit JUD checks the maximum effective bits of a multiplier and the multilicand of a register REG1 for storing the multiplier and a register REG2 for storing the multiplicand. Consequently, it is detected that the maximum effective bit position of the register REG1 storing the multiplier is the 5th bit from the least significant bit (LSB) and that of the register REG2 storing the multiplicand is the 4th bit from the LSB. Consequently, the judging circuit JUD judges that maximum effective bit position of a multiplier ARI is the 8th bit from the LSB. Therefore, the resolution of the prescribed number of bits can be obtaied by shifting only the necessary bits of the multiplied result to a REG3.
Patent JP-H04328196-A (JP)
Title: 2-step process of sour hydrocarbon fraction sweetening
Inventor: ROBAATO AARU FUREIMU
IPC: C10G45/06
Filed: 1992-02-18
Abstract: PURPOSE: To provide a process for sweetening a sour hydrocarbon fraction by selectively hydrogenolyzing tert-mercaptans in this fraction and reacting prim- and sec-mercaptans with an oxidizing agent under specified conditions to industrially advantageously sweeten the mercaptans comprising the fraction.  
     CONSTITUTION: A tert-mercaptan in a sour hydrocarbon fraction containing prim-, see-and tert-mercaptans is hydrogenolyzed in the presence of a selective hydrogenolysis catalyst contg. a Group VIII metal and/or a Group VIB metla in a liqudi phase pref. at 25 to 300°C under 689 to 6,894 KPa. Then the prim- and see-mercaptans are oxidized into disulfides in the presence of a basic component and an oxidation catalyst carrying a metal chelate. 
     COPYRIGHT: (C)1992,JPO
Patent JP-H02131596-A (JP)
Title: Method for discriminating fresh fishes, composition for discriminating fresh fishes and kit therefor
Inventor: KITAMIKADO MANABU
IPC: G01N33/12
Filed: 1988-02-10
Abstract: PURPOSE:To enable simple discrimination by allowing an umbelliferon derivative to react with neutral beta-N-acethylglucosaminidase in the fish blood to determine the enzyme activity. CONSTITUTION:An umbelliferon saccharide derivative such as 4-methyl- umbellififeryl-2-acetamide-2-deoxy-beta-D-glucopyranoside bering an umbelliferyl group is supported on a porous carrier such as filter paper to give a kit for discriminating the fresh fishes. Then, fish blood containing neutral beta-N- acethylgrlucosaminidase is added to the kit to effect the enzyme reactions at 15 to 30 deg.C for about 10 minutes. The resultant reaction mixture is subjected to fluorescent ultraviolet absorption at 360nm to discriminate fresh fishes.
Patent JP-H05267203-A (JP)
Title: Diffusing method for impurity into semiconductor wafer
IPC: H01L21/22
Filed: 1993-02-19
Abstract: PURPOSE:To provide an impurity diffusing method for semiconductor wafers by which impurities are diffused making pressure around all semiconductor wafers, placed in a temperature stabilized region, uniform and specified pressure with a pressure limitation established at the waste-gas exhausting end of a heating container. CONSTITUTION:Concerning a heat treatment method for semiconductor wafers by which impurities are diffused, forming an impurity gas flow in a heating container 3 by taking an impurity gas in from one end 3a of the heating container to specified pressure and exhausting a waste gas from the other end, placing semiconductor wafers 1 in the temperature stabilized region of the inside of the heating container making them cross the flow direction of the impurity gas, and performing heat treatment of these semiconductor wafers 1 in the impurity gas atmosphere, impurities contained in the impurity gas are diffused making the temperature stabilized region a constant gas pressure region.
Patent JP-2000225051-A (JP)
Title: Key box and key holder
Inventor: KANEDA SAKAE
IPC: E05B19/00
Filed: 1999-02-08
Abstract: PROBLEM TO BE SOLVED: To provide a key box and a key holder capable of quickly housing and quickly taking out the key holder. SOLUTION: A key box 7 and a key holder are composed of a combination of a case 7 the key box 7 and the key holder 1, and in the case 7, a main part 9 and an opening/closing part 10 are arranged on the left and right via a hinge 8 in a double spread, and in the main part 9, a forward projecting peripheral wall 13 is formed on the four sides of a main plate part 11, a housing part 15 is set in the peripheral wall 13, and in the housing part 15, a hooking hole 21 and positioning parts 19, 20 for installing the key holder are set in the main plate part 11.  In the key holder 1, an installing hole 4 is formed in a base part 2 having a magnetic substance 3, a key installing suspension ring 5 is installed in the installing hole 4 to be constituted in a state of installing a key on the suspension ring 5, and the key holder 1 is magnetized to the positioning parts 19, 20 of the key box 7 by the magnetic substance.
Patent JP-S62188456-A (JP)
Title: Cmi coding and recoding circuit
Inventor: MATSUMOTO TOSHIKAZU
IPC: H04L25/49
Filed: 1986-02-13
Abstract: PURPOSE:To improve the identification capability by extracting an f0 clock component from an input CM1 code, doubling the result and identifying the CMI signal from the result and decoding the CMI code by the f0 flock. CONSTITUTION:The f0 component is extracted from the input CMI signal by a differentiation circuit 4 and an f0 component extraction circuit 5, a 2f0 component is generated by a multiplier circuit 6 and the CMI signal is identified by the 2f0 component. Then the CMI signal is decoded by the f0 component. The f0 component is extracted at first and then the 2f0 component is generated in this way to obtain a CMI coding/decoding circuit having a high identification capability and not requiring any synchronization protection circuit or the like.