Patent GB-1264714-A (GB)
IPC: H02M3/07
Filed: 1969-09-02
Abstract: 1,264,714. Static converters. D. H. NELSON. 2 Sept., 1969 [9 Sept., 1968], No. 43470/69. Heading H2F. In a static converter, storage capacitors are alternately connected in series and in parallel by first and second transistor switch means respectively (or thyristors) the said switch means being driven cyclically in anti-phase and the capacitors are selectively and alternately charged from a voltage source and discharged to a load, a coupling means including at least one transistor switch driven in synchronism with the second switch means alternately coupling the capacitors to the voltage source and the load.  Circuit arrangements are described and illustrated whereby conversions are accomplished such as: D.C. to D.C., D.C. to A.C., A.C. to D.C., single phase A.C. to three phase, A.C. to A.C. with frequency change and/or phase change. The conversions also involve voltage step-up or step-down and may include D.C. polarity reversal. The transistor switches are driven from an A.C. signal source and in the drawings the symbol like a numeral 8 inclined to the right located near the transistors' bases, indicates that that transistor conducts during the first half cycle of the signal source whereas a symbol inclined to the left indicates conduction in the second half-cycle. As shown, Fig. 1, during the first half cycle T1, T2, T3 conduct, diodes 9, 10 are back biased and C6, C7 are connected in series across the D.C. source voltage V each being charged to V/2. In the next half-cycle T4, T5 and diodes 9, 10 conduct. T1, T2, T3 are off and C6, C7 are connected in parallel through a diode 8 to the load so that the load voltage is V/2. Alternatively T3 may be omitted and diode 9 replaced by a connecting link to the common line without affecting the conversion. In Fig. 1 the output voltage is available during " second " half cycles only, while in a modification thereof, Fig. 8 (not shown), output voltage is available during both half cycles. By charging the capacitors in parallel and discharging them in series, D.C./D.C. with voltage step-up is obtained (Fig. 3, not shown). In Fig. 5 (not shown), which is basically as Fig. 1, the D.C. output polarity is reversed with respect to the input. Fractional step down of voltage (e.g. to 2V/3) is obtained by the circuit, Fig. 7 (not shown), two capacitors being connected in parallel and in series with a third during charging and the third in parallel with the series combination of the other two on discharging. Combinations of the basic circuits of Figs. 1 to 8 are used in the embodiments, Figs. 9 to 16. For instance 3-wire D.C. without voltage change is produced by the circuit, Fig. 10, the + D.C. line and neutral being common to both input and output. The two circuit sections are driven alternately so that C45 and C45a discharge alternately to the -ve D.C. line, giving a voltage output during both half cycles. To produce 3-phase A.C. from D.C., the D.C. input is converted to 3-wire D.C. with voltage step-up (Figs. 12a, 12b, not shown) and applied to three pairs of switching transistors in Fig. 12C. The transistors in a pair operate alternately to feed full square-wave A.C. to a respective phase. The pairs are driven by three signal voltages properly phase displaced and at the desired output frequency. For simple A.C./D.C. conversion a diode replaces the transistor 1 in Fig. 1. In a frequency converter embodiment, Fig. 14 (not shown), single-phase A.C. is converted to 3-wire D.C. which is chopped by transistors driven at the desired output frequency.