Patent SG-11201807496X-A (SG)
Title: Offset compensation for ferroelectric memory cell sensing
Inventor: VIMERCATI DANIELE
IPC: G11C11/22
Filed: 2017-03-10
Abstract: Declarations under Rule .17: 11545 465 DL I 415 1 — 440 T405 410 115 460 475 475- a 1 1 430 110-c 220-6 j -205 -b — R1 2 1 L- 210-b 134. `440-a 405-a -465-a j 415 a 455 410-a 445-a FIG. 4 470 400 1054, Z_ 11 , 0-1/ 4L-1 220-a 205-a- 210-a W O 20 17 / 15 6 444 Al (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (10) International Publication Number (43) International Publication Date WO 2017/156444 Al 14 September 2017 (14.09.2017) WIPO I PCT 111111111111110111011111111111010111110 0111111111111111111111111111111111111110111111 KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). (51) International Patent Classification: G11C 11/22 (2006.01) G11C 7/06 (2006.01) (21) International Application Number: PCT/US2017/021884 (22) International Filing Date: 10 March 2017 (10.03.2017) (84) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/067,838 11 March 2016 (11.03.2016) US (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). (72) Inventor: VIMERCATI, Daniele; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). (74) Agent: KRAFT, Aaron J.; Holland & Hart LLP, P.O. Box 11583, Salt Lake City, Utah 84147 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: with international search report (Art. 21(3)) (54) Title: OFFSET COMPENSATION FOR FERROELECTRIC MEMORY CELL SENSING (57) : Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be con - nected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in con- junction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substan - tially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transist - or. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.