baber/WOPTO huggingface dataset:
Patent JP-H04351427-A (JP)
Title: Charging control circuit
Inventor: KAWAMURA TOSHINORI
IPC: H02J7/00
Filed: 1991-05-28
Abstract: PURPOSE:To reduce the number of terminal of battery pack. CONSTITUTION:A battery pack is provided with a charging control circuit 1 for controlling the charging operation while detecting the residual capacity of battery. The battery pack is also provided with an output circuit for providing a machine body with a signal representing the residual capacity of a battery D at the time of discharging whereas delivering a charger control signal at the time of charging. The output circuit 6 outputs any one of the signals from a control output terminal T3.
Patent JP-H0712334-A (JP)
Title: Intelligent transitional rectifier for ignition device
Inventor: MAAKU EMU REEZAA
IPC: F23N5/18
Filed: 1994-05-11
Abstract: PURPOSE: To provide an ignition controller employing an intelligent transient eliminator imparting an inexpensive technology for controlling a heating furnace appropriately. CONSTITUTION: A transient eliminator 12 is provided in a HVAC unit or a heating furnace 10 which burns a fuel such as natural gas. An ignition control system employing an intelligent transient eliminator provides a secondary relay across a pressure switch 18. The secondary relay is controlled by a signal to an igniter 24 in the heating furnace 10. A secondary switch is tested before energizing the inducer blower in the system.
Patent JP-S5347947-A (JP)
Title: Enclosed switchboard
Inventor: TSUJI AKIRA
IPC: H01H3/00
Filed: 1976-10-13
Abstract: PURPOSE:To simplify the entire mechanism and improve safety and workability by enabling swing opening and closing through the interlocking of a shutter plate with a movable isolated section by the actuation of spring force.
Patent JP-S63285853-A (JP)
Title: Display unit
Inventor: NAKATANI TOSHIBUMI
IPC: H04N5/68
Filed: 1987-05-19
Abstract: PURPOSE:To obtain a constant electric field on a whole display region so as to obtain a picture with no unevenness of color and/or luminance on a whole display screen by disposing a shield panel on the outside of the display part of a supporting means disposed at both ends of the display part corresponding to a screen. CONSTITUTION:A shield panel 11 is disposed on the outside of a supporting means 22 disposed at the end of a display area 23 in parallel with a supporting wall 18 and having a specific distance to the supporting means 22. This shield panel 11 is so disposed that it has the specific height and touches a screen 12 or has the specific distance thereto. The same electric potential is given to the shield panel 11, the screen 12 and the supporting means 22. Accordingly, also in both ends of the display part, an uniform electric field can be obtained in the same way as in the case of the center of the display part. Therefore, electron beams land on the specific position, so that preferable quality of a picture with no unevenness of color and/or luminance can be obtained on the whole display screen.
Patent JP-S61293952-A (JP)
Title: Hydroxybenzoate and production thereof
Inventor: INOUE YASUHIKO
IPC: A61K8/00
Filed: 1985-06-05
Abstract: NEW MATERIAL:A compound expressed by formula I [R is alky, alkoxy or halogen; Rs may be the same or different substituent groups when >=2 R groups are present (n is >=2 and/or qis >=2); m and p are integers 1-5; n and q are 0 or integers 1-4; m+n is <=5 and p+q is <=5]. EXAMPLE:3-Hydroxyphenyl-2,4-dihydroxybenzoate. USE:An ultraviolet light absorber, raw material for hydroxybenzophenone which is an electronic material, light stabilizer for plastics and fibers, sunscreen agent, component stabilizer for dyestuff or perfume, etc. PREPARATION:A hydroxybenzene expressed by formula II (i is an integer 1-5; j is 0 or an integer 1-4; i+j is <=5) is reacted with phosgene in a solvent, e.g. nitrobenzene, at 50-150 deg.C to afford the aimed compound expressed by formula I.
Patent JP-S61281017-A (JP)
Inventor: JIYAN RUPUCHI
IPC: C01F7/0626
Filed: 1986-05-27
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S61280092-A (JP)
Title: Bloch line memory
Inventor: MIYAWAKI MAMORU
IPC: G11C19/08
Filed: 1985-06-05
Abstract: PURPOSE:To upgrade the recording density and transmission rate and to decrease a driving part by providing a magnetic film including a Bloch line provided on the substrate, a means to impress a pair of opposite-directioned magnetic fields approximately perpendicularly to the surface of the substrate, and a means to turn the substrate. CONSTITUTION:Plural pieces of stribe magnetic domains 1 are formed radially from the disc center of rotation. In the vicinity of the tip of each stribe magnetic domain at the outer peripheral part of the disc, a conductor for Bloch line regeneration 4 is wired, while in the vicinity of the tip of the same on the side of the center of rotation, a conductor for Bloch line recording 3 is wired. By turning the disc in an external magnetic field 2, the Bloch line at the magnetic wall in the stribe magnetic domain 1 is made transfer on the nail magnetic wall by one bit at every passing through the pair of perpendicular magnetic fields N and S, and the Bloch line thus is transmitted. Accordingly, with one turn of rotation of the disc, the Bloch line is transferred by 4 bits by the four pairs of the perpendicular magnetic fields N and S.
Patent JP-H01291321-A (JP)
Title: Logic circuit
Inventor: ISAKA FUMIKO
IPC: G06F5/10
Filed: 1988-05-18
Abstract: PURPOSE:To control the number of gates of the circuit and to execute read-out at high speed by constituting the circuit of a 2-port RAM and a binary counter. CONSTITUTION:The title circuit is provided with a 2-port RAM 10 for storing the data by an input signal, and binary counters 9a, 9b for executing an address designation of the data in the 2-port RAM 10 by its input signal. In such a state, count values of the binary counters 9a, 9b are compared by a comparator 12a, and when they are the same, a signal for showing a fact that data of a storage area is empty is outputted to a data empty flag output 6. Also, the output value of an adder circuit 11for bringing a count value of the binary write counter 9a to increment by '1' and a count value of the binary read counter 9b are compared by a comparator 12b, and when they are the same, a signal for showing a fact that the data is full in the storage area is outputted to a data full flag output 7. In such a way, the number of gates of the circuit can be curtailed and read-out can be executed at high speed.
Patent JP-H10312853-A (JP)
Title: Lever type connector
Inventor: FUKAMACHI MAKOTO
IPC: H01R13/629
Filed: 1997-05-13
Abstract: PROBLEM TO BE SOLVED: To position tabs of male terminal metal fittings in a lever type connector. SOLUTION: A movable positioning member 17 which has positoning holes 18 fit to tabs 14 and can move from the tip side to the end side of the tabs 14 along a fitting direction of both connector housings 10, 20 is installed in a fitting recessed part 15 of a male side connector housing 10. By fitting the female side connector housing 20 to the fitting recessed part 15, the movable positioning member 17 moves while the tabs 14 are inserted in the positioning holes 18. Therefore, the tabs 14 are always held at specified positions by the positoning holes 18 in the fitting process.
Patent JP-H11317158-A (JP)
Title: Charged particle track calculating method and recording medium recording charged particle track calculation processing program
Inventor: MATSUTANI SHIGEKI
IPC: G21K1/00
Filed: 1998-05-01
Abstract: PROBLEM TO BE SOLVED: To provide a charged particle track calculating method using a computer capable of automatically making the time variable with respect to a system having a different scale and also with respect to a system having a stagnation point, and capable of performing track calculation of an electron accurately in a short period of time. SOLUTION: In a charged particle track calculating method using a computer for calculating the position of a charged particle after an elapse of an infinitesimal time under a given electric field, the position of a charged particle after the elapse of an infinitesimal time is calculated by solving a Newton's equation where the infinitesimal time is changed every moment according to the magnitude of the electric field. Also, in this calculating method, the infinitesimal time is changed every moment according to the position of a charged particle.
Patent JP-S61878-A (JP)
Title: Label attaching circuit
Inventor: IMAMURA MAKOTO
IPC: G06K9/00
Filed: 1984-06-14
Abstract: PURPOSE:To attain the label attachment to binary pictures in an 8-coupling mode and also to read easily the contents of a label counter, etc. out of a CPU, by providing paired area counters and label memories, etc. CONSTITUTION:When the binary picture signals are applied to an input terminal 20, a mask pattern is produced via a 1-line memory 21 and a shift register 22 for production of mask. Then paired area counters 34 and 37 and label memories 35 and 36 function alternately for upper and lower lines every time the mask pattern is shifted by a line. Then a label attachment output is delivered. While the data on the label memory for upper line is delivered to the label memory for lower line according to the form of the mask pattern in the first half of a scan clock via a pair counter 41, a data memory 42, etc. Thus, the label attachment is possible in an 8-coupling mode for binary pictures. At the same time, the contents of the label counters 31 and 33, etc. can be read easily out of a CPU44 via a programmable counter 43, etc.
Patent JP-S611425-A (JP)
Title: Manufacture of forming metallic mold
Inventor: HANZAWA HIDEYUKI
IPC: B21D37/20
Filed: 1984-06-14
Abstract: PURPOSE:To obtain a metallic mold which can be manufactured easily with high accuracy by forming the metallic mold of the fixed side and the movable side by a pair of metallic mold bodies formed by cutting the first block, and a pair of cavity members formed by cutting the second block. CONSTITUTION:A ferrule 5 is formed by using a fixed side metallic mold 30 which has a guide pin inserting hole 31, and into which a cavity member 34 provided with a core pin 36 has been inserted and fixed, and a movable side metallic mold 40 into which a cavity member 45 having a forming material injecting hole 47, and guide pin 44 have been inserted and fixed. In this case, metallic mold bodies 33, 43 are brought to cutting work simultaneously as one body from the first metallic bock and cut and separated at right angles, and also the cavity members 34, 45 are manufactured in the same way from the second metallic block, and thereafter, the core pin 36 is installed. In this way, forming metallic mold having high dimension accuracy can be manufactured easily. This metallic mold is used for forming a ferrule of an optical fiber plastic connector.
Patent JP-S6015821-A (JP)
Title: Magnetic recording medium
Inventor: MIYATA ICHIJI
IPC: G11B5/73
Filed: 1983-07-05
Abstract: PURPOSE:To obtain a magnetic recording medium with which the strength and toughness of a base film are improved and which has much improved mechanical strength by using a base film consisting of a polyethylene terephthalate having a specified number-average mol. wt. and weight-average mol. wt. CONSTITUTION:A magnetic layer is formed on a base film consisting of a polyethylene terephthalate having <=30,000 number-average mol. wt. and >=65,000 weight-average mol. wt. For example, the magnetic paint is applied and dried on a base film of 15mu thickness consisting of a polyethylene terephthalate having 37,000 number-average mol. wt. and 90,000 weight-average mol. wt. so as to have 5mu dry thickness and after the coating is subjected to a surface treatment, the film is cut to a prescribed width and a video tape is thus manufactured. One- sided elongation and soft deformation are hardly observed or not observed at all with such video tape and the tape has excellent mechanical strength.
Patent JP-S61281664-A (JP)
Title: Data telephone terminal testing device
Inventor: KATAOKA NAOHITO
IPC: H04L69/40
Filed: 1985-06-06
Abstract: PURPOSE:To respond to the test call of call types of data telephone terminals by analyzing the ID information of the terminal received from a data telephone terminal, discriminating the type of the communicating mode of the data telephone terminal and setting automatically the communicating mode for applying to this. CONSTITUTION:By adding a dial tone sending part DTS, a PB signal receiver PBREC to receive ID information, an ID information memory part IDMEN to store the ID information of all subscriber terminals, a communicating mode changeover control part MCCONT to set the communicating speed changeover part, the ID information sent from a data telephone terminal is analyzed and the communicating applicable to the data telephone terminal is automatically set. Thus, it is not necessary to give the subscriber number classified by the terminal type, one data telephone terminal test device can test all types of the data telephone terminal, and therefore, the facilities at the station side can be made into the necessary minimum, and the reduction of the service due to the inclination of the originating terminal type and the complication of the user to select the testing device.
Patent JP-H10304483-A (JP)
Title: Bit pattern insertion and detection system using time division switch
Inventor: DOI TAKASHI
IPC: H04Q11/04
Filed: 1997-04-25
Abstract: PROBLEM TO BE SOLVED: To simplify a circuit configuration by storing a bit pattern for verifying a transmission line to a specific address of a data memory, reading the address to insert the verification bit pattern to the transmission line, allowing an opposite station to read a signal from the transmission line at a bit pattern comparator circuit from a time division switch and verifying the transmission line through the comparison of the bit patterns. SOLUTION: A serial bit signal 211 received from a transmission line is serial/parallel converted and written in a data memory 201 as parallel data 221. In the case of a normal operation, the data are read in an output timing to a transmission line. However, in addition to an output to the transmission line, an output timing to bit pattern detection circuits 241, 242 is provided and the content of the data memory 201 is read in the timing and the read bit pattern 231 is outputted to the bit pattern detection circuit, where the bit pattern is detected. After the execution of adjustment of a signal speed, the circuit setting for each object signal kind is not required for the insertion/detection.
Patent JP-H0419048-A (JP)
Title: Id system
Inventor: ISHIKAWA ISAO
IPC: B23Q41/00
Filed: 1990-05-15
Abstract: PURPOSE:To reduce the power consumption of a CPU at the time of writing so as to use this power for the writing energy to an EPROM by placing the CPU in a sleeping mode at the writing time to the EPROM, and resetting the CPU into normal action after the termination of writing. CONSTITUTION:When the indication of writing data is given to the memory 9 of a responder 2 from an interrogator 1, a transmitter-receiver 7 detects this signal to feed it into a CPU 8, and the CPU 8 sends out a data write command to the memory 9 and then is placed in a sleeping mode. Upon receiving this data write command, the memory 9 formed of an EPROM performs the automatic data write processing of writing data held therein automatically and sends out a write termination signal to the CPU 8 upon terminating automatic writing. The CPU 8 supplied with the write termination signal performs interrupt action so as to be returned to the normal acting state from the sleeping state, and normal action is performed thereafter.
Patent JP-S5247360-A (JP)
Title: Switch circuit
Inventor: KOJIMA MASANORI
IPC: H03K5/01
Filed: 1975-10-13
Abstract: PURPOSE: In case the unipolar and single-throw switch which is used for calculatin unit, etc. is turned on, a medium that holds the voltage supplied through the above switch is added, In this way, the malfunction of load equipment caused by chattering at switch operation time can be effectively prevented. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-H06268055-A (JP)
Title: Forming recessed part oxidation insulation
Inventor: KENTO JIEI KUUPAA
IPC: H01L21/31
Filed: 1993-04-28
Abstract: PURPOSE: To provide a method needing only one mask for forming insulation oxide which does not become larger than the size previously determined by lithograph-system and has the same size as the determined size. CONSTITUTION: A buffer layer 14 is formed on a substrate 12. An oxide resistance layer 16 is formed on the buffer layer 16 and etched. A disposable side wall spacer 30 is formed adjacently to the side wall 28 of the oxide resistance layer, and a trench region 36 is defined. The trench region 36 is etched and a trench is formed. The disposable sidewall spacer 30 is eliminated, and a conformal layer of oxidizable material is stuck on the trench side wall 40 and the trench bottom surface 38. The conformal layer is oxidized to form insulation layer in an insulating region 26 of the substrate 12.
Patent JP-H0640701-A (JP)
Title: Hydrogen separation type steam reforming reactor
Inventor: KOBAYASHI KAZUTO
IPC: B01J8/02
Filed: 1992-05-15
Abstract: PURPOSE:To obtain a hydrogen separation type steam reforming reactor excel lent in catalytic efficiency. CONSTITUTION:In the reactor 1, hydrocarbon or oxygen-contg. hydrocarbon 5 is supplied as the source material to produce hydrogen by steam reforming reaction. This steam reforming reactor is a hydrogen separation type in which a hydrogen separation membrane 3 is housed in a steam reforming reaction catalyst layer 2 so that the reaction is effected while hydrogen 8 is selectively separated by the pressure difference. Inert heatconducting particles 4a are disposed in the entrance area of the catalyst layer 2, while a reforming catalyst 4b and a hydrogen separation membrane 3 are disposed in the downstream side of the particles 4a to heat the reaction gas.
Patent JP-H09306869-A (JP)
Title: Plasma cvd method and semiconductor device having metal film formed by the same
Inventor: MIYAMOTO TAKAAKI
IPC: C23C16/44
Filed: 1996-05-17
Abstract: PROBLEM TO BE SOLVED: To provide a plasma of forming a Ti or other metal film good in surface morphology with reduced residual halogen content and a high-reliability semiconductor device having a metal film formed thereby. SOLUTION: The plasma CVD is applied at a total pressure of a mixed gas contg. TiCl4 or another metal halide and H2 , which is less than the point at which any of the emission strength ratios H β/H α, Hγ/Hα, Hδ/Hα of a hydrogen atom beam spectrum turns to decrease as the total pressure gradually increase. This allows a plasma condition rich in high-exciting energy hydrogen active species to be adopted and hence the formed metal film is uniformly adsorbed to a substrate being treated to result in forming of a flat and less- halogen-content metal film.
Patent JP-S5247922-A (JP)
Title: Aerosol of insecticide
Inventor: KATSUTA YOSHIO
IPC: C09K3/30
Filed: 1975-10-13
Abstract: PURPOSE: To make a non-flon aerosol of insecticide without any explosion and combustion hazards by compounding a solution of insecticide with a liquefied petroleum gas propellant having a specific vapor pressure and by the suitable combination of nozzle sizes in the vapor tap and the valve. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-H07333702-A (JP)
Title: Packing structure for waterproof box
Inventor: EZURE MICHIAKI
IPC: H04N5/225
Filed: 1994-06-06
Abstract: PURPOSE:To make a small-sized box having waterproofing and dewproofing functions and improve packing assembly workability by forming specified fitting shapes between a packing made of an elastic material and the box. CONSTITUTION:Fitting shapes 1a, 2a are formed in a cover 1 and a packing 2, respectively, to prevent the packing 2 from coming out of the packing installing groove 1b. That is, projected fitting shapes 1a, 2a are formed in the cover 1 and the packing 2, respectively, and the cover and the packing are fitted mutually. Or, a recessed fitting shape 1a is formed in the cover 1 and a projected fitting shape 2a is formed in the packing 2 and then the cover and the packing are fitted mutually. Or, a projected fitting shape 1a is formed in the cover 1 and a recessed fitting shape 2a is formed in the packing 2 and they are fitted mutually. Consequently, even the fitting shapes are fine, high holding force can be obtained, so that the box can be made compact. Since water-proofness can be kept only by forming the fitting shapes, the workability is improved.
Patent JP-S612866-A (JP)
Inventor: NISHIMOTO TAKASHI
IPC: A61M1/10
Filed: 1984-06-18
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S5647757-A (JP)
Title: Ultrasonic probe driver
Inventor: SUZUKI KAZUMICHI
IPC: G01N29/04
Filed: 1979-09-28
Abstract: PURPOSE: To permit an ultrasonic probe driver to be more compact and lighter and to increase the degree of accuracy in positioning the probes by using permanent magnet wheels, and light, sound wave or microwave.  
     CONSTITUTION: A head 21 having a plurality of probes 1, a ball roller 19 and a light source 20; and a case 17 having a magnet-driving wheel 15, magnet wheels 16, and motors 26 and 30 are linked together by means of a shaft 18. Thus, when the motor 26 causes the megnet-driving wheel 15 to rotate and the motor 30 causes the head 21 to rotate through the shaft 18, the probes 1 axially and circumferentially move in an inner hole 3 in a rotor 2 of a turbine or generator. This permits an ultrasonic defect-location for the whole surface of the inner hole 3, eliminating the need for any track, so that the apparatus can be more compact and lighter. Moreover, by emitting a narrow beam from the light source 20 and receiving it by a photo sensor 23 located on the circumference of a cylinder 22, the position of the head 21 in this direction and consequently the positions of the probes 1 can be detected independently of play, slippage and the like in the driving unit. Therefore, the probes 1 are positioned with higher accuracy. 
     COPYRIGHT: (C)1981,JPO&Japio
Patent JP-H06339262-A (JP)
Title: High power-factor control circuit
Inventor: ABE NOBORU
IPC: H02M7/12
Filed: 1993-05-26
Abstract: PURPOSE:To improve a delay of a transient response characteristic by a method wherein zero voltage of an input power supply is detected and at that timing, a voltage signal of an error amplifier circuit is sample-held and is pulse-width- modulated and voltage is controlled by means of a converter. CONSTITUTION:A signal of a sample and hold circuit 12 is connected to a converter 2 through a PWM (pulse width modulating circuit). A terminal voltage of a load 3 is detected by a voltage detector 7 and a signal Vs which is obtained by amplifying an error of a reference voltage 11 by means of an amplifier 10 is kept constant except when the voltage of a power supply 1 is zero by means of the sample and hold circuit 12. The signal Ia whose value is kept constant by means of the sample and hold circuit 12 is pulse-width-modulated by the PWM 4 and a converter 2 is operated on the pulse-width-modulated signal. Therefore, a pulse width of the signal is kept constant during a zero- voltage period of the power supply 1 (during a half cycle). By this method, a delay of a transient response characteristic can be improved.