Patent GB-667794-A (GB)
Title: Improvements in or relating to calculating machines
IPC: H03K5/15
Filed: 1949-09-05
Abstract: 667,794. Digital electric calculating-apparatus. BRITISH TABULATING MACHINE CO., Ltd. Sept. 5, 1949 [Sept. 3, 1948], No. 22936/49. Class 106 (i). Binary electronic calculating- apparatus comprises an impulse time delay circuit adapted to change from a non-effective to an effective condition in response to an input impulse, means for applying timing impulses to the delay circuit, the circuit being adapted to produce an output impulse on receiving a timing impulse only when it is in effective condition, and means for placing the circuit in non-effective condition after each timing impulse. The described embodiment consists of a binary, series-type, electronic multiplying machine having networks of impedances and rectifiers connected to the control electrodes of a number of electronic tubes from a plurality of voltage supplies of different potentials in order to secure the required delay, the operating and timing impulses being applied to the control electrodes. The multiplicand is translated into series-mode voltage impulse form and supplied simultaneously to a plurality of coincidence circuits corresponding to the different digital positions of the multiplier, each coincidence circuit being responsive to a digit of the multiplier. Through the action of the coincidence circuits all the digits of the multiplicand are multiplied by each digit of the multiplier individually with each resulting partial product appearing in coded impulse form. The partial products are then applied to a series chain of adding circuits, known as adding boxes, the several parts of the chain corresponding to the columnar positions of the partial products. The resulting product in series-mode impulse form may be translated into another form for recording purposes. A record reading and recording machine of the type described in Specification 442,534, [Group VIII] (which is referred to), may be employed. In the time code employed in the device described, a particular period of time is assigned to each digital position in the binary number to be represented. The first time period following a starting impulse corresponds to the lowest denomination of the binary number, the second time period to the next higher denomination, and so on. A voltage impulse occurring in a time period represents a binary 1, and the absence of an impulse represents a binary 0. The operation of the machine is described with reference to the example set out in Fig. 6 in which a binary multiplicand equal to 23 is multiplied by 13 to give a binary product equal to 299. Impulses from card sensing brushes or other entry devices pass through individual voltage dividers and, in the case of the multiplicand, are applied to a translator (see below) which, receiving the multiplicand in the form of a binary number over a plurality of selectively energized circuits, generates time-coded voltage impulses corresponding to that number, transmitting them in serial form as indicated diagrammatically in Fig. 7. Voltages on the lines 195b (1 ... 8) from the multiplier sensing brushes or other entry devices, are applied through voltage dividers to coincidence circuits 190b (1 ... 8) which permit or block ,the passage of the time-coded pulse representation of the multiplicand according to the respective values of the multiplier digits. The resulting partial products pass to adding boxes AB (1 ... 8) which are arranged to accept simultaneously any two binary numbers in coded impulse form and compute and deliver the sum of these two numbers in the same impulse form but delayed by exactly one time period. Each sum is passed on towards the right, being delayed by one time period during each adding operation, thus simulating the staggering of the partial products in the process of multiplication, Fig. 6, so that a train of impulses representing the product in binary form, but with three column shifts to the left, passes to the product translator. The multiplicand translator receives the multiplicand in the form of a binary number represented as a plurality of selectively energized circuits and generates time-coded voltage impulses corresponding to that number. It employs a sixteen-stage electronic commutator, part of which (65 to 73) is shown in Fig. 2f. A positive starting impulse delivered through a coaxial line 89 every sixteen microseconds, is applied to the control grid of a pentode 82 through a condenser 88 causing the valve to become conductive with a consequent drop in voltage at its anode, which is connected through a resistor 84 and choke 85 to a. +110 v. line. A coupling condenser 90 discharges, but its terminal remote from the pentode 82 is held at about - 27 v. by virtue of a connection through a crystal diode 94 to a bias line B1. When, at the end of the positive pulse on the control grid, the valve cuts off and the voltage at the anode rises, a positive pulse passes through the condenser 90 and a crystal diode 91 to the grid of a triode 83. A connection through a crystal diode 93 to a bias line B2 limits the maximum voltage of this pulse to - 6 v. approx. A condenser 95 becomes charged and holds the voltage of the triode grid at the level of the line B2. The anode of each triode 83 is connected through a resistor 98 to the + 110 v. line while the cathode is connected to a - 110 v. line through a resistor 99 and also to the control grid of the pentode 82 of the next stage in a cathode follower circuit. A positive rectangular, low impedance, voltage impulse, approximately <SP>1</SP>/ 3  microsecond in duration, is supplied through a line S1 from the synchronizer, once each microsecond; its magnitude is such that if the grid of the triode 83 is at the voltage of bias line B1 prior to the synchronous impulse, the impulse produced at the cathode of the triode 83 will not raise the voltage of the control grid of the pentode 82-of the next stage above cut-off, but if the grid is at the level of bias line B2 prior to the synchronous impulse, the voltage impulse produced causes the next higher pentode to become conductive. As a synchronous impulse ends, a negative clamp pulse is delivered from a line K1 through a crystal diode 96 and resistor 97, reducing the charge on the condenser 95 and returning the grid of the triode 83 to the level of the bias line Bl. Thus a properly timed positive impulse on the grid of the pentode 82 in any given stage of the commutator causes a voltage pedestal to be established on the grid of its associated triode 83 at the termination of the impulse. The pedestal provides for the effective transmission of a synchronous impulse to cause the pentode 82 of the succeeding stage to become conductive and act, in turn, in the manner just described, thus providing a chain of delay stages whose delay is determined by the frequency of the synchronous impulses. The starting impulse becomes a commutating impulse passing along from stage to stage at a rate of one microsecond per stage, the triodes 83 of successive stages delivering effective output impulses successively at microsecond intervals. The first twelve stages are arranged to correspond to the twelve binary orders of the multiplicand. Switching circuits 81a (1 ... 12) responsive individually to the voltages on the data entry wires 64a (1 ... 12) determine whether or not the impulses supplied by the respective commutator stages are to be transmitted to the multiplicand bus-bar M1. When any one of the entry wires 64a (1 ... 12) is at its more positive voltage, representing a binary 1, the diodes 102, 104 leading to the bus-bar M1 are essentially direct-coupled to the cathode of the triode 83. When an entry wire is at its more negative value the coupling is substantially a condenser coupling, the voltage level of the bus-bar M1 being such that the diodes 102, 104 act essentially as open switches preventing the passage of the commutator impulse to the bus-bar. A clamp pulse acting through a diode 105, Fig. 2g, and resistor 106 restores the voltage level of the bus-bar at the end of each positive impulse transmitted. The bus-bar M1 supplies the coded impulses to a cathode-follower circuit 109, the output of which passes through a coaxial line 111 to the coincidence circuits. The synchronizer which supplies the starting, synchronous, and clamping impulses comprises a known crystal oscillator circuit 115, Fig. 2g, providing a one megacycle frequency output which is fed through a H.F. transformer 126 to a counting-down circuit 127. The first valve 128 of this circuit translates the alternating voltage into a series of negative impulses which are applied to the cathode of a second valve 129 which is arranged in a blocking oscillator circuit including a timing condenser 145 whereby the valve 129 becomes conductive on every fourth impulse from the valve 128. The voltage impulses then produced across a resistor 141 are transferred through a second timing condenser 148 to the grid of a valve 130 in a second blocking oscillator circuit, every fourth impulse at the resistor 141 causing the valve 130 to become conductive (i.e.. every sixteen microseconds). This output is fed by a coaxial line 89 to the first stage 65 of the commutator, Fig. 2f. The one megacycle alternating voltage output from the crystal oscillator 115, Fig. 2g, is also fed via coaxial lines 124, 158 to the grids of twin triodes 159, 160, a variable resistor 171, condenser 172 and inductor 173, permitting phase adjustment at the grid of the triode 159. The output from the cathode of this valve is applied to the control grid of a pentode 174, the bias condition of which is such that a negative voltage impulse appears at the anode once each microsecond, and this is applied to the control grid of a normally conductive pentode 180 driving it below cut-off. In this way, positive, substantially rectangular synchronous pulses 1/3 microsecond wide, are fed to the line S1. In a similar manner the output of the triode 160 controls