baber/WOPTO huggingface dataset:
Patent TW-408420-B (TW)
Title: A method to measure if the connecting via in the metal wiring layer is aligned correctly
Inventor: LUO YUNG-TSUEN
IPC: G03F7/20
Filed: 1998-08-14
Granted: 2000-10-11
Abstract: This invention relates to a method to measure if the connecting via in the metal wiring layer is aligned correctly. This invention is mainly to form the connecting via after exposure, developing and etching on the IMD, then use the IMD as mask to etch the metal wiring layer below and remove said IMD. Then use SEM in reality to measure the left via trace of said IMD after etching, to verify if the connecting via is aligned with the metal wiring correctly or misalign value if there is any mis-aligned.
Patent TW-436706-B (TW)
Title: Latch circuit including means for converting voltage level and flip-flop circuit including the same
Inventor: HAMADA MOTOTSUGU
IPC: H03K3/356
Filed: 1998-08-19
Granted: 2001-05-28
Abstract: The slave latch circuit SL of the flip-flop circuit provided with a master latch circuit ML and the slave latch circuit SL has a voltage level conversion circuit 20. Consequently, it is able to reduce the number of the required elements, decrease the power consumption and increase the operation speed.
Patent TW-387145-B (TW)
Title: Method manufacturing bottom electrode of DRAM capacitor
Inventor: WANG CHIUAN-FU
IPC: H01L27/108
Filed: 1998-09-04
Granted: 2000-04-11
Abstract: A manufacturing method of bottom electrode in capacitance on DRAM is proposed. We formed dielectric layer, etching end layer and first isolation layer in turn. Then pattern the three layers to expose the source/drains form an opening. Formed an electric conduction layer under first isolation layer, and filled the opening. Under the opening of first isolation layer formed a second isolation layer with obtruding area. Then formed a mask gap on the side wall with obtruding area. Using the mask gap as a mask to change second isolation layer to recess isolation layer, then use the recess isolation layer as mask to remove part of electric conduction layer until exposing first isolation layer. Using mask gap as mask to remove part of recess isolation layer, changing it to be an isolation pillar, then remove the mask gap, formed conductor gap at the pillar side wall. Remove the isolation pillar and first isolation layer off to produce bottom electrode of the capacitor.
Patent TW-386277-B (TW)
Title: A method for manufacturing the high voltage mixed-mode component
Inventor: JANG GUANG-YE
IPC: H01L21/70
Filed: 1998-10-02
Granted: 2000-04-01
Abstract: A method for manufacturing the high voltage mixed-mode component. The method includes the steps of first providing a substrate that has a component isolating area and a first active area and a second active area thereon. Then, a first oxide layer is formed on the first active area and the second active area and the thickness of the first oxide layer on the second active area is thicker than that on the first active area. A first conductive layer is formed on the substrate to cover the first oxide layer and the component isolating area. The second oxide layer is formed on the first conductive layer and then defined to expose the conductive layer in order to form the third oxide layer on the first conductive layer. The second conductive layer is formed on the substrate and covers the third oxide layer and the first conductive layer. Defining the second conductive layer in order to expose part of the third oxide layer, and then define the first conductive layer. A low voltage transistor gate and a high voltage transistor gate are formed on the first active area and second active area, respectively, and a capacitor is formed on the component isolating area.
Patent TW-404893-B (TW)
Title: A method for constructing a fluid jet print head, a printhead for ejecting fluid using a semiconductor substrate, and a multi-density level mask
Inventor: CHEN CHIEN-HUA
IPC: B41J2/14
Filed: 1998-10-22
Granted: 2000-09-11
Abstract: A process for creating and an apparatus employing shaped orifices in a semiconductor substrate (20). A layer of slow cross-linking material (34) is applied on the semiconductor substrate (20). An orifice image (42) and a fluid-well image (43) is transferred to the layer of slow cross-linking material (34). That portion of the layer of slow cross-linking material (34) where the orifice image (42) is located is then developed along with that portion of the layer of slow cross-linking material (34) where the fluid well image (43) is located to define an orifice opening in the semiconductor substrate (20).
Patent TW-428214-B (TW)
Title: Semiconductor device, method making the same, and electronic device using the same
Inventor: OHSAWA KENJI
IPC: H01L23/12
Filed: 1998-11-23
Granted: 2001-04-01
Abstract: In a semiconductor device, a plurality of wiring films are formed on a front surface of a base comprising an insulting resin and having electrode-forming holes, the surfaces of the wiring films and the surface of the base being positioned on the same plane and at least parts of the wiring films overlapping with the electrode-forming holes; a conductive material is embedded into the electrode-forming holes to form external electrodes on the back surface, away from the wiring films, of the base; a semiconductor element is positioned on the front surface of the base with an insulating film therebetween, the back surface of the semiconductor element being bonded to said front surface of the base; wires bond the electrodes of the semiconductor element to the corresponding wiring films; and a resin seals the wiring films and the wires.
Patent TW-390038-B (TW)
Title: Method for fabricating poly-Si thin film transistors
Inventor: YE CHING-FA
IPC: H01L29/786
Filed: 1998-12-28
Granted: 2000-05-11
Abstract: This invention proposes a simple method to fabricate self-aligned offset T-gate structure and self-aligned inverse-T gate LDD structure by anodicoxidation. These structures are mainly applied to Al-gate poly-Si TFTs. Utilizing different anodic oxidation rate of Al and other conductive materials (such as Ta,Cr or N+ a-Si) in specific electrolytes, different anodic oxide thickness can be obtained simultaneously. Putting Al in the lower layer with other materials in the upper one and anodizing in the same electrolyte, we can fabricate offset T-gate structure. Inverse-T gate structure can be formed with upper and lower layer materials interchanged. Offset T-gate structure has lower leakage current and excellent drive current ability whereas inverse-T gate LDD one has the merits of high-speed operation, higher transconductance and higher reliability. Because of the advantages mentioned above with low resistivity of Al, these technologies are very potential for future AMLCDs applications.
Patent TW-449815-B (TW)
Title: Method of removing photoresist
Inventor: JENG LUNG-YI
IPC: H01L21/30
Filed: 1999-02-22
Granted: 2001-08-11
Abstract: A method of removing photoresist is disclosed, wherein the procedure of removing photoresist layer is proceeded by ashing after completing the etching procedure and venting with oxygen. The etching machine is Tegal-903, for example. The temperature controlling effect of a general etching machine is better than that of an asher. A stable photoresist etching rate can be obtained by ashing and removing the photoresist layer with oxygen-containing plasma, so as to prevent the flat film under the photoresist layer from being damaged due to over-etching or incomplete removal of the photoresist which is difficult to be completely removed by the subsequent solvent.
Patent TW-412811-B (TW)
Title: Method for manufacturing diode having ceramic substrate
Inventor: SHIU SHENG-SHIUNG
IPC: H01L21/56
Filed: 1999-02-26
Granted: 2000-11-21
Abstract: The present invention relates to a method for manufacturing the diode having a ceramic substrate and, more particularly, for the diode manufactured by using ceramic combined with dies and conductive metal. The present manufacturing process comprises a step to define cutting grooves in the substrate thereby forming hundreds of units. Each unit on the substrate is spread with conductive paste to form a conductive wire, or is plated with a conductive wire. A plurality of dies are attached to the ceramic substrate. The ceramic substrate is spread with photo-sensitive green painting. After exposure, developing and removing the mold, the diode contact points are formed. Alternatively, the ceramic substrate is spread with capping material. After polishing or in chemical solution, the diode contact points are formed. The conductive paste is applied to the top of the diode for connecting to the edge of each unit. The upper surface of each unit is covered with a protection layer and printed with a mark. The substrate is divided into a plurality of bars, each having two edges spread with conductors thereby forming terminals. Each bar is further divided into a plurality of pieces. The terminal is encapsulated by plating nickel and tin-lead. The novel diode product according to the invention has high reliability, low cost and can be efficiently manufactured.
Patent TW-542755-B (TW)
Title: Decorative roll-patterned metal strip or sheet and process for making the same
Inventor: ESCHAUZIER FRANS R
IPC: B21B1/22
Filed: 1999-03-24
Granted: 2003-07-21
Abstract: A decorative roll-patterned metal strip or sheet, preferably aluminium strip or sheet, having: a thickness of about 0.05-1.0 mm, preferably about 0.1-0.8 mm, with a surface having a plurality of indentations of a depth of about 0.001-0.05 mm, preferably about 0.02-0.035 mm, and optionally having a layer of a paint of a thickness of about 3-30 microns, preferably about 10-15 microns, on the surface and within its indentations, the ratio of the depth of the indentations to the thickness of the strip or sheet being in the range of about 1:5 to about 1:100.
Patent TW-421952-B (TW)
Title: Paging system of post-processed Chinese/English character paging
Inventor: LIU MICHAEL
IPC: H04L7/00
Filed: 1999-03-26
Granted: 2001-02-11
Abstract: The present invention relates to a paging system for post-processed Chinese/English character paging which stored the voice recording and relative information of the Chinese/English character paging from the caller in the pre-processed voice mail server. By transmitting the recording of the Chinese/English character to be paged and the information of the pager such as pager number and sequential number through the server to a OAP server over the network, the previous recording is distributed and played to the operator so that the operator can transmit the inputted corresponding Chinese/English characters to the one to be paged. The invention can make the paging operation faster and increase the efficiency of paging system.
Patent TW-391932-B (TW)
Title: Automotive deck lid bumper
Inventor: ANTONUCCI JEFFREY L
IPC: E05F5/02
Filed: 1999-05-04
Granted: 2000-06-01
Abstract: A deck lid bumper having a stud with a head and a shaft, the head adapted to bump against the deck upon closure of the deck against the bumper, the receptacle adapted to receive the  shaft of the stud, the receptacle having means to secure the receptacle in a frame. A frictional surface is provided between the shaft of the stud and the receptacle sufficient to support the stud in a desired position within the receptacle and a lock is provided to lock the shaft portion of the stud into the receptacle by rotating the head of the stud with respect to the receptacle.
Patent TW-408500-B (TW)
Title: The manufacture method of thin film transistor-liquid crystal display
Inventor: PAN TAI-JI
IPC: G02F1/133
Filed: 1999-05-11
Granted: 2000-10-11
Abstract: A method of forming thin-film transistor (TFT) on the glass substrate. Firstly, patterning the first metal layer sited on the glass substrate to define the gate structure. Next, form the insulated layer to cover the first metal layer and glass substrate and form the silicon layer on said insulated layer, then form the doped silicon layer on the upper surface of the silicon layer. Then, form the complex layer on the doped silicon layer and the insulated layer, wherein said complex layer comprises the contact layer as the top layer, and the buffer layer as the bottom layer, and the second metal layer is sited between said contact layer and the buffer layer. Then, etch said composite layer to define the source/drain structure wherein the etching selectivity of said buffer layer relative to said doped silicon layer is larger than 1. After removing part of the doped silicon layer exposed by the composite layer, form the passivation layer on the composite layer and the insulated layer wherein the etching selectivity of passivation layer relative to the contact layer is larger than 1.
Patent TW-451523-B (TW)
Title: Device bay connector
Inventor: JUNTWAIT ERIC
IPC: H01R4/24
Filed: 1999-06-22
Granted: 2001-08-21
Abstract: An electrical connector comprises a dielectric housing having a front face and a rear face opposite the front face. A mating portion extends from the rear face for mating with a complementary connector. A first contact section is integrally formed on the front face for connecting with a first connector. A second contact section is integrally formed on the front face for connecting with a second connector and includes at least a contact pin extending beyond the front face. An alignment plate having an opening for insertion of the contact pin is assembled to the front face for securely positioning the contact pin.
Patent TW-441135-B (TW)
Title: Solar battery unit and solar battery device
Inventor: ITOH KATSUHIRO
IPC: H02S20/00
Filed: 1999-06-30
Granted: 2001-06-16
Abstract: In the present invention, the solar battery units 2 and 3 are formed in the shape of a void column, wherein at least one part of the exterior, circumferential surfaces is prescribed as a light receiving surface 10. Simple installation is made possible either by direct securing to, or by simple placement on the place of installation. A pleasant outer appearance can be procured by concealing the wiring cables therein. Further, due to its capability of being positioned vertically or horizontally, states of installation can be selected according to the conditions of the place of installation, and if it is directly secured to the place of installation, it will permits the installation to be irrespective of the inclination or the height of the place of installation. Composition of the solar battery apparatus 1 by connecting the solar battery units 2 and 3 in the longitudinal direction facilitates installation even in a small or narrow space.
Patent TW-452779-B (TW)
Title: Optical disk device
Inventor: ASADA AKIHIRO
IPC: G11B7/00
Filed: 1999-07-29
Granted: 2001-09-01
Abstract: With the capacity of the recording media becoming larger (the density is higher), in addition to the recording driving current waveform of the semiconductor laser will become multi-valued and the frequency will become higher, the level of the reproducing signal will be decreased. Therefore, the effect of the crosstalk of the reproducing circuit by the recording circuit system has to be reduced, so that the worsening of the reliability of recording and reproducing can be prevented. The present invention is an optical disk device to supply the signal to control the semiconductor laser driving circuit of the optical pickup head through a flexible cable for a signal processing circuit, so that the semiconductor laser driving circuit can generate the driving current waveform of the semiconductor laser based on said two-valued signal and said timing signal supplied by said signal processing circuit through said flexible cable. The signal processing circuit will supply said timing signal during recording the information, and will stop supplying said timing signal during reproducing the information.
Patent TW-464684-B (TW)
Title: Decahydronaphthalene derivative, the liquid crystal composition and liquid crystal display component comprising said derivative, and the producing process thereof
Inventor: OGAWA SHINJI
IPC: C07C255/55
Filed: 1999-08-24
Granted: 2001-11-21
Abstract: Decahydronaphthalene derivative as shown by following formula (I), liquid crystal composition comprises the same and liquid crystal component using the same. As shown in the examples, the novel compound decahydronaphthalene derivatives of present invention can be easily produced industrially. The effect of enlarging temperature range of nematic phase can be obtained by adding small amount into mother liquid crystal and various properties for liquid crystal materials can also be improved. Besides, the solubility with mother liquid crystals which are common used as nematic liquids is also excellent. Therefore, it can be suited to various liquid crystal display component which is requested as broad operative temperature range, and is very useful as liquid crystal material.
Patent TW-493354-B (TW)
Title: CDMA transmission of packet-switched data
Inventor: NEVO RON
IPC: H04L12/56
Filed: 2001-02-19
Granted: 2002-07-01
Abstract: A method for conveying packet data from a CDMA mobile station to a GSM network, including communicating with a GSM service node to establish a data link from the mobile station to the network via a radio communications base station. The packet data are conveyed between the mobile station and the base station over a CDMA air interface and are then transferred over the link between the base station and the network.
Patent TW-442535-B (TW)
Title: Circuit substrate composition with low dielectric constant
Inventor: LIAO WEI-HAN
IPC: C08L63/00
Filed: 1999-10-04
Granted: 2001-06-23
Abstract: The present invention discloses a circuit substrate composition with a low dielectric constant, which comprises: (a) 20 to 99.9 weight percent of a functionalized syndiotactic polystyrene with micro-foaming functions; (b) 0.01 to 80 weight percent of an epoxy mixture; and (c) less than 50 weight percent of a cross-linking agent. A prepreg of a functionalized syndiotactic polystyrene and an epoxy mixture according to the present invention, after immersion in a fiber glass cloth, has a dielectric constant that can be lowered to 3.1 at 1 GHz, and can increase the anti-solvent property of a circuit substrate.
Patent TW-452728-B (TW)
Title: Method for dynamically maintaining function modules of applications
Inventor: CHEN TONG S
IPC: G06F7/00
Filed: 1999-11-11
Granted: 2001-09-01
Abstract: This invention is a method for dynamically maintaining function modules of applications, which only needs to modify contents of function definition files including the name, definition, corresponding exe file of the function module and the name and definition of the sub function to achieve the function module that is needed when inserting, modifying or deleting application functions in an original application. With the present method, the application program is extensible, and quite easy to edit without performing additional complex modifications and compilations.
Patent TW-432666-B (TW)
Title: Electrostatic discharge protection device of field oxide transistor with gate control
Inventor: LIN GENG-LI
IPC: H01L23/60
Filed: 1999-11-23
Granted: 2001-05-01
Abstract: An electrostatic discharge protection device at least comprises: a field implantation region located in a substrate; a shallow trench isolation region on the field implantation region and a gate oxide layer located on the shallow trench isolation region; a source/drain region located below the gate oxide layer and the two sides of the shallow trench isolation region; a gate on the gate oxide layer; and a spacer located on the sidewalls of the gate. The electrostatic discharge protection device according to the present invention can be changed according to the following: (1) the distance between the shallow trench isolation region and the lightly doped drain region being zero; (2) removing the lightly doped drain region; (3) adding a N-well region located below the field implantation region, the lightly doped drain region and the source/drain region; (4) adding a deep N-well region located below the N-well region. The device according to the present invention has a deeper current path thereby increasing the dissipation path of the heat generated during the electrostatic discharge so that the device can withstand a higher electrostatic discharge voltage in a smaller layout area.
Patent TW-I258472-B (TW)
Title: Heterodiazinone derivatives
Inventor: ITO KOICHI
IPC: C07D249/12
Filed: 2000-02-15
Granted: 2006-07-21
Abstract: The present invention provides a novel compound having an excellent 2-amino-3-hydroxy-5-methyl-4-isoxazole propionic acid (AMPA) receptor antagonistic action, particularly a therapeutic, preventing and ameliorating action useful for cerebral ischemia, cerebrospinal injuries, Alzheimer's disease, Parkinson's disease, amyotrophic lateral sclerosis, Huntington's chorea, epilepsy, pain, spastic paralysis, multiple sclerosis etc. That is, the present invention provides a heterodiazinon compound represented by the following formula (I), a pharmacologically acceptable salt thereof or hydrates thereof, in which A represents an oxygen atom, a sulfur atom or a group represented by the formula NR3 (in which R3 represents hydrogen atom or a lower alkyl group); R1 and R2 are the same as or different from each other and each represents an optionally substituted aryl group, an optionally substituted heteroaryl group, an optionally substituted aralkyl group, an optionally substituted heteroaryl alkyl group, an optionally substituted aryl alkenyl group, an optionally substituted heteroaryl alkenyl group, an optionally substituted piperidyl group, an optionally substituted piperazinyl group; a morpholinyl group, an optionally substituted lower cycloalkyl group, a tetrahydrofuranyl group, a tetrahydropyranyl group, an adamantyl group, an optionally substituted amino group or an optionally substituted amide group; and R4 and R5 are the same as or different from each other and each represents hydrogen atom, hydroxy, a halogen atom, nitrile group, nitro group, a lower alkyl group, an aryl group or a heteroaryl group, provided that the compounds represented by the following formula (II), (in which R11 and R12 are the same as or different from each other and each represents hydrogen atom, fluorine, chlorine, bromine, iodine, a C1-C2 fluoroalkyl group, a C1-C2 chloroalkyl group, a C1-C2 bromoalkyl group, a C1-C6 alkyl group, a C3-C6 cycloalkyl group, a C7-C9 aralkyl group, phenyl group, a C1-C6 alkoxy group, a C1-C6 alkylthio group, a C1-C6 alkylsulfinyl group, a C7-C9 aralkoxy group, phenoxy group, phenylthio group, phenylsulfonyl group, alkali metal carboxylate C2-C5 alkoxycarbonyl group or a group represented by the formula -N(R15)R16 (in which R15 and R16 are the same as or different from each other and each represents hydrogen atom or a C1-C2 alkyl group); and R13 and R14 are the same as or different from each other and each represents a C1-4 alkylsulfonyl group, nitro group, a group represented by the formula -OCHnX3-n (in which X represents fluorine, chlorine, bromine or iodine; and n is any of integers 1 to 3) or a group having the same meanings as the definitions of R11 and R12) are excluded.