Patent GB-1235750-A (GB)
Title: Data processing apparatus
IPC: G01S7/28
Filed: 1968-12-30
Abstract: 1,235,750. Digital data-shift register. THOMSON INFORMATIQUE ET VISUALISA. TION. 30 Dec., 1968 ]29 Dec., 1967], No- 61773/68. Heading G4C. [Also in Divisions H3-H5] Specification describes a digital pulse radar receiver in which successive returns are stored in small volume integrated circuit shift registers which are read out in parallel for parasitic element rejection. The data store holding the shift registers may comprise a control circuit B1, Fig. 3, and a storage section B2. The analogue return is converted into N digitized quanta h, Fig. 2, during an effective time T 1 , the remainder of the pulse period being the dead time T 2 . The digitized return is fed to a first of n static shift registers R1 shifted during the effective time by the quantizing clock pulses h, the time T 1  being defined at gate circuit E by a counter F, counting N of the clock pulses and a decoder D. After n returns all the shift registers are filled and the returns are simultaneously read out from the registers. By shifting the register R1 a number (N + m) of pulses, Fig. 5, and the registers R 2  . . . R n  a number N of pulses, the circuit receiving the paralleled outputs of the registers can process the stored returns in quanta in advance of the return in the next recurrence period. To use dynamic shift registers, i.e. those which continue shifting when the shift pulses are removed e.g. cascaded bi-stables, means must be provided to circulate the data during the dead time T 2  or an auxiliary register (V), Fig. 6 (not shown), must be provided at the output of each N-bit dynamic register (R). Each dynamic register may comprise Z sub registers P 1  . . . P 2 , Fig. 7, with N/Z bit capacity and each sub register may comprise, Fig. 8, the dynamic shift means P 10 , fed via gate P 13  by the digitized return during the effective time T 1 , whilst during the dead time T 2 , the output of the shift means is recirculated to its input via gate P 12 . The just described circuit necessitates an accurate knowledge of the repetition period of the radar. If T 1  and T 2  are fixed, however, the actual radar P.R.P. T, Fig. 9, may vary such that consecutive sync pulses (outer pulses) may be spaced from the nominal sync pulse (beginning of T 1  and end of T 2 ) by a possible error up to Œ T 3 . To overcome this the circuit of Fig. 10 may be used in which the sub registers P 1 -P 2  are as in Figs. 7 and 8. The blind time T 3  is defined by the output of a counter F 3  counting pulses h 2  and started by the sync pulse b. Said counter output triggers a bi-stable G 1  to give a signal enabling gate E 3  to pass clock pulses h 1  to the T 1  counter F 1  when N of these pulses have been counted, F 1  produces a pulse which resets bi-stable G 1  then disabling gate E 3  and also triggers bi-stable G 2 . T 2  counter F 2  is started by the " end of T 1  " output of decoder D and gives a pulse when T 2  is reached, which via gate E 4 , open for the period T 1  + T 2  + T 3  by bi-stable G3, resets bi-stable G2. The bistable thus produces a T 2  defining pulse which enables gate E 2 , feeding shift clock pulses h 2  to the register R via OR circuit H. Gate E 1  is enabled by the output of decoder D during T 1  to pass the shift clock pulses h 1 . Thus T 1  and T 2  are defined and shifting produced during these periods independant of the non-constant pulse repetition periods.