Patent GB-1026889-A (GB)
Title: Computer control
IPC: G06F15/80
Filed: 1963-12-03
Abstract: 1,026,889. Electric digital calculators. WESTINGHOUSE ELECTRIC CORPORATION. Dec. 3, 1963 [Dec. 4, 1962], No. 47681/63. Heading G4A. A computer comprises a plurality of processing elements under simultaneous control of central control means and means responsive to internal conditions within said processing elements for selectively altering any of the control signals from the central control means to thereby allow a processing element to be in a different mode of operation from other processing elements of said plurality. The main embodiment is a parallel network type computer based on that of Specification 1,026,888 which is referred to. Like the latter it comprises a rectangular array of identical processing elements (one shown in Figs. 6A- 6D, not shown) all receiving identical control signals from the central control unit and each including (a) two memory frames 20, 30 (Fig. 6A, not shown) addressed by word selection units and bit counters in the central control unit (b) frame selections means 40 (not shown and utilizing STROKE i.e. NAND gates) to write each of the read-out bits into the same or the other memory frame, or to write a bit S1 (not shown) from a logic and arithmetic unit 38 (Fig. 6C, not shown) into either memory frame while rewriting the bit from the other memory frame back in the same place, as commanded by control bits CC1, CC2 (not shown) from the central control unit; (c) routing means 45 (Fig. 6D, not shown) for passing a bit from memory frame 20 (not shown) to operation selection means 47 (not shown) or to one of the four nearest-neighbour processing elements in the array or for passing a bit received from one of the neighbours to operation selection means; (d) operation selection means 47 (not shown) for producing a bit equal to that from the routing means or its complement and a bit equal to a bit from memory frame 30 (not shown) or its complement or setting either equal to zero irrespective; (e) the logic and arithmetic unit producing a bit from the bits produced by the operation selection means and incorporating a carry flip-flop. Features additional to the previous patent are provided as follows. Each processing element is set (methods below) in one of four modes by suitably setting two mode flip-flops in a mode control unit 42 (Fig. 6B, not shown). Any particular operation will be performed only by those processing elements in a selected mode or modes, the central control unit providing four control bits those corresponding to a selected mode being 1. In each processing element, STROKE gates in the mode control unit compare these control bits with the states of the mode flip-flops and only if the mode of the processing element is one of the selected modes will a bit EX (not shown) produced be 1. Bit EX (not shown) is fed back to the frame selection means: if EX = 1, the latter responds to control bits CC1, CC2 (not shown), but if EX = 0, it writes every bit read out of the memory frames back again irrespective of these control bits. When EX = 1, and under control of the central control unit, the states of the mode flip-flops may be stored in respective memory frames or the mode flip-flops may be set either in accordance with bits read from the memory frames or in accordance with four control bits from the central control unit, one of which is set = 1, the latter only provided a bit from the carry flip-flop equals 1. The value of this bit may be determined in accordance with data from the memory frames by routing (and operating on) the latter as in logic and arithmetic operations. In this way, the bit may equal 1 if a particular bit from one of the memory frames is 1 (or 0), or if a word is 0. The solution of a partial differential equation (Laplace) is described. Modifications mentioned.-Counter or register means may be provided to respond to a predetermined internal condition (like the state of the carry flip-flop) by switching to the next of a predetermined sequence of modes. The EX bit (not shown), instead of modifying the effect of CC1 and CC2 (not shown), may control reading and writing of bits in the memory frames, or the logic and arithmetic unit or routing means. There may be a plurality of control units, different modes corresponding to obedience to different control units.