Patent GB-989740-A (GB)
Title: Improvements in or relating to digital voltmeters
IPC: H03M1/00
Filed: 1961-12-18
Abstract: 989,740. Selective signalling. GENERAL ELECTRIC CO. Ltd., and J. N. HAILE. Dec. 10, 1962 [Dec. 18, 1961], No. 45368/61. Heading G4H. Electric voltage measuring equipment of the type in which clock-pulses are counted until a ramp voltage equals the unknown voltage is characterized in that a store is provided whereby the result of one digitising cycle may be indicated while a further cycle is taking place. In order to indicate the polarity of the voltage on the display device the voltage of the ramp signal varies from a value of one polarity through earth potential to an equal value of the other polarity. The comparator arrangement comprises first and second circuits to each of which the ramp signal is supplied, the signal the value of which represents the voltage of the input signal being supplied only to the first comparator circuit, and the arrangement being such that the first comparator circuit gives an indication when the voltages of the two signals supplied thereto are equal in value and the second comparator circuit gives an indication when the value of the ramp signal supplied thereto is equal to earth potential, the time interval between the giving of these two indications defining the duration of said gate pulse and the order in which these two indications are given defining the polarity of the input signal. The signal the value of which represents the voltage of the input signal may be derived from the input signal by a voltage attenuator circuit having associated with it an automatic range changing circuit, the automatic range changing circuit operating to sense the magnitude of the output signal supplied by the attenuator circuit to the comparator arrangement and, when the magnitude of the voltage of this output signal is greater than or less than one or other of two predetermined voltages operating to increase or decrease the value of attenuation so that the magnitude of the output signal voltage is maintained within the range bounded by the predetermined voltages. Each such change alters the magnitude of the output signal by a factor of ten and, where the number shown by the display device is a decimal number, the automatic range changing circuit controls the position of a decimal point appearing on the display device. The means for counting the number of clock pulses passed by the gate means comprises a number of decade counters and the storage means comprise two-condition bi-stable trigger circuits. The means operable at a later time for deriving signals from the storage means may include decade to decimal converter circuits which operate so that the number shown on the display device is a decimal number. Fig. 1 shows the equipment in block diagram from which accepts signals at input terminal 13 ranging from -1000 volts to +1000 volts and displays the measured voltage as a five digit decimal number on a display device 32. The equipment may be set to read the input voltage continuously, i.e. at half second intervals, or singly at any chosen instant. The input 13 is connected to a ten-way multi-bank wafer switch 14a..... 14f each bank having a central rotatable contact cooperating with contacts numbered 1 to 10, the rotatable contacts being ganged together. Contacts 1..... 4 correspond to four voltage ranges i.e. 0-1v, 0-10v, 0-100v, 0-1000v. When the rotatable contacts are on contacts 5 the voltage range is selected by an automatic range changing circuit 19 described with reference to Fig. 3 (not shown) this circuit causing a decimal point to be displayed in an appropriate position on the device 32 and controlling an attenuator 16 (Fig. 2, not shown) whereby the attenuator output voltage is kept within the range 0-1 volt. The signal from the ramp signal generator 21 increases linearly with respect to time and is supplied to the comparator circuits 20, 22 where it is compared with the signal from impedance converter 18 and with earth potential. The output signals from circuits 20, 22 are in antiphase and supplied to summing amplifier 29, gate waveform generator 30 and sign selector circuit 31 described with reference to Fig. 4 (not shown). The time gate 33 receives a gating signal from the switch bank 14d and a clock pulse signal via banks 14e, 14f from the clock pulse generator 46. Each pulse in the gating signal opens the gate 33 to allow clock pulses to pass to decade counters 36, the gate 33 being described with reference to Fig. 7 (not shown). Five storage stages 38 are interposed between the five counters 36 and the decade to decimal converters 39, the stages 38 enabling each reading to be displayed on the device 32 for the whole half second available when the equipment is operating in the continuous mode.