Patent GB-1530405-A (GB)
Title: Loop data highway communication system
IPC: H04L12/43
Filed: 1976-03-16
Abstract: 1530405 Data transmission in loop systems OHKURA ELECTRIC CO Ltd 16 March 1976 [24 March 1975(2) 25 Aug 1975] 10444/76 Heading H4P In a data communication system in which a control station and other stations are connected in a unidirectional loop, the other stations transmit information in a second frame and receive information in a first and the central station can transfer information from the first to the second. Details of the system are given including, synchronization delay adjustment, priority, answer back and of bypassing faulty stations. Transmission is by bi-phase signals and each station is arranged to pass or alternatively to block i.e. remove and insert, highway signals. The central station (102) originates timing signals, adjusts loop delay and transmits specific control signals. The station may comprise a receiver 301 and transmitter 304 serially connected in the highway with 302 controlling loop delay under control of synchronizing master controller 305. An interface 303 controlled and synchronized by 306 is connected via further interfaces 307 to devices 106. The central station alternatively may comprise a local station plus components 302, 305, 306. A local station, Fig. 4 (not shown), comprises a receiver (401), a sync. controller (402), interface (403), transmitter (404) and interfaces (405). The sync. controller includes a phase locked loop controlled by highway signals producing bi-phase clock signals of 20 MHz and bit clock signals of I MHz by division. The master sync. controller 305 shown in Fig. 7 has a crystal controlled 4 MHz oscillator 701 divided by 2 providing the bi-phase clock and further divided by 2 to form 1 MHz bit clock which is applied to a block length counter 703, which on reset triggers block sync. generator 702 consisting of a shift register. Byte counter 704 issues a signal each 9 bit byte to the byte register (602) in the delay controller described in connection with Fig. 6 (not shown). Sync. detector 705 detects block sync. pattern in deserialized highway signals also resets 704. The sync. signal is 9 bits and is distinguished by its special pattern which does not comply with biphase encoding rules. Information blocks are despatched from the central station continually and comprise at least a sync. signal, followed by a first and second frame, each frame size being identical and may each have 16 time slots including receiver address RAA, transmitter address TAA, information DTA, answer back, etc. Information in frame A is taken out and placed into frame B with adjustment of designations on transfer, e.g. TAA becomes TAB, etc. A portion of the information slot may be used for address expansion, retransmission flag, etc.; the information slot may include a parity bit. Certain stations may have transmission priority in an ascending order, i.e. one station may have first priority another second, etc. this being designated by an appropriate address in a block. At least some stations may have a bypass, operable in fault conditions, such as is illustrated in Fig. 11 (not shown). The bypass may comprise a paralleled receiver and transmitter operable through a changeover gate arrangement (411, 413) switched by a fault signal, the bypass and normal transmitters being mutually connected to the highway through a hybrid transformer.