Patent GB-1052596-A (GB)
IPC: G06Q10/04
Abstract: 1,052,596. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 16, 1965 [June 30, 1964], No. 25380/65. Heading G4A. In a computer, information selected from input stores by address signals is processed in an arithmetic unit and the result stored in a result store location selected by the same address signals, which are then variable in accordance with the results. The invention is a special-purpose computer for solving problems such as: what way of dividing a piece of material of length L into pieces of one or more predetermined lengths li having corresponding prices pi will maximize the return R (i.e. total price)? Let ni be the number of pieces of length li in the final answer, and let primes indicate intermediate values of nj and R in the iterative algorithm used. L<1> means an intermediate value of length not allocated to lengths li, called remainder. Input registers are provided for li and pi, arranged in order of decreasing price per unit length, and interim result storage is provided in the form of a counter for each n<1>i, a register for L<1> (initially holding L) and an accumulator for R<1>. The input registers and the n<1>i counters can be addressed simultaneously by a ring counter which can be advanced by one and set directly to any position. The values of n<1>i and R<1> can be gated to optimum result storage which contains at any time the best values (called ni and R) for ni, and R yet found and will eventually hold the final answer. A first set of n<1>i is obtained by repeatedly subtracting the highest order li (i.e. that with highest price per unit length) from the value in the L<1> register (initially L) and simultaneously incrementing the corresponding n<1>i counter by one and passing the result of the subtraction into the L<1> register, until one of these subtractions gives a negative result when the n<1>i counter is not incremented, and the L<1> register is left unmodified. The successive subtraction is then done with the remaining li in turn, in the same way. Following each successful subtraction the corresponding pi is added into the R<1> accumulator. The system now tests whether decreasing the lowest-order non-zero n<1>i (n<1>P say) by one and allocating the current L<1> together with the free length resulting from the decrease, to the next lower order li (viz. lp+1) would, result in an improvement, i.e. whether If an improvement would not result, n<1>p is zeroized and the test repeated (i.e. using what is now the lowest-order non-zero n<1>i), after updating R<1> and L<1>. If an improvement would result, the value of n<1>p is actually decremented by one, L<1> and R<1> are updated accordingly, and the new L<1> is allocated among the lower li, similarly to the allocation to obtain the first set of n<1>i initially, and the testing above is repeated, and so on. When all n<1>i are zero, the process is finished. Adders, subtractors and multipliers are provided in the obvious way for the above operations, except that incrementing and decrementing by one and resetting to zero the n<1>i counters is done by energizing one of three inputs to the appropriate counter, and subtracting a number from the R<1> accumulator is done by adding in the complement.