Patent GB-1164475-A (GB)
Title: Improvements in or relating to Central Processor
IPC: G06F12/08
Filed: 1966-11-21
Abstract: 1,164,475. Programme look-ahead. BURROUGHS CORP. 21 Nov., 1966 [26 Nov., 1965], No. 52077/66. Heading G4A. In a digital electronic data processing system provided with preprocessing facilities of the look-ahead type, preprocessing of certain instructions may be inhibited. In particular, preprocessing of conditional jump and jump on test of data instructions are held up until all data handling instructions are executed. Preprocessing may also be inhibited in response to a clear instruction or an interrupt signal. The invention is described as applied to a multiprogramming modular computer system comprising a memory 122, a communication unit 100 and a processor 101-126. The processor comprises an instruction look-ahead unit 101 for fetching instructions from memory, a syllable determination unit 102 for unpacking instructions (instructions of 1, 2, 3 or 4 six-bit syllables are stored in 52-bit word locations each accommodating 8 syllables, 3 flag bits and 1 parity bit), an advance processing unit 104 for fetching data and performing address computations in advance of the data computations, a final instruction queue unit 108 comprising a circular buffer with accommodation for 4 instructions, a temporary store 114 for storing data corresponding to the instructions in unit 108, a final station 110 for executing the data handling instructions from unit 108, an operand stack unit 116 comprising a plurality of registers operating on a last-in-first-out basis and associated with arithmetic and logic circuits for performing operations in the Polish Notation Code, a programme counter 106, various registers 124, 126 and an associative store 19 for storing index words, programme reference information such as indirect addresses and programme bound limits and result words waiting to be stored in memory 122 by unit 100. The units are autonomous in operation and the system is under the overall supervision of an executive programme. Processor details.-Instruction look-ahead 101 comprises twelve registers each of 52-bits capacity which are operated as a circular buffer under the control of respective load and unload counters, loading taking place four words at a time and unloading one word at a time. Unit 101 also has storage for the previous jump data in case such jump is repeated. Syllable determination unit 102 unpacks the words into instructions the various formats of which are illustrated in Figs. 8a-8k (not shown). Advance unit 104 (Fig. 6, not shown) includes a plurality of registers for storing information from which addresses may be calculated. In general an address may be formed by adding (using a three input adder) the contents of a base register, a register holding the results of a previous indexing calculation and an instruction address field register. A check is made that calculated addresses fall within permitted bounds. Addresses of operands are passed from unit 104 to communication unit 100 which, after any higher priority demands have been met, fetches the relevant operands from memory and stores them in temporary store 114 at positions corresponding to the relevant data handling instructions, which instructions are passed unamended by advance unit 104 into the final queue 108. If however a calculated address corresponds to the address of a word presently stored in associative memory 19 (e.g. a recently calculated result word waiting to be written into memory 122), then the memory access request is suppressed and the more up-to-date word is accessed from store 19, thus avoiding errors. Whenever advance unit 104 decodes a conditional jump or a jump on test of data or a clear final queue instruction, further operations in the unit are suspended until the final queue 108 is empty. Final queue 108 and temporary store 114 comprise registers accommodating four instructions and four 52-bit operands respectively and operate as circular buffers under the control of respective read and load counters. Final station 110 (Fig. 2, not shown) performs the data handling operations of the system and has provision for the normal arithmetic and logic operations, binary to decimal conversion, handling numbers in floating point notation, comparing according to a variety of criteria, shifting (up to 48-bit positions left or right), imply logic operations and double precision operations. Stack 116 has a capacity of 14 words but has provision for extending into memory 122. The top two words are stored in registers directly connected to the arithmetic and logic circuits of final station 110. The contents of associative store 19 (28 words and corresponding addresses) are constantly being changed, with the most recently accessed index and reference words being held in store 19 and transfers to memory (or cancellations in case of reference words which are not altered by processing) taking place when the corresponding part of store 19 becomes full. The programme reference words contain control information for jumps between segments, indirect addresses and data for use by executive. Index words, programme reference words and data words to be stored are all held in separate queues within store 19. Communication unit 100 (Fig. 11, not shown) checks for parity in data transfer operations, monitors input/output line interrupt requests (512 channels each with channel control words and parameter or data word are provided) and grants requests according to a system of priorities. The use of integrated circuits and/or tunnel diodes together with thin film memories and disc stores is referred to.