Patent SG-11201407361P-A (SG)
Title: Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer
Inventor: SCHWARZENBACH WALTER
IPC: H01L21/66
Filed: 2013-05-01
Abstract: (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 28 November 2013 (28.11.2013) WIPOIPCT (10) International Publication Number WO 2013/175278 A1 (51) International Patent Classification: H01L 21/66 (2006.01) (21) International Application Number: (22) International Filing Date: (25) Filing Language: (26) Publication Language: PCT/IB2013/000857 1 May 2013 (01.05.2013) English English (30) Priority Data: 1254841 25 May 2012 (25.05.2012) FR (71) Applicant: SOITEC [FR/FR]; Chemin des Franques - Pare Technologique des Fontaines, F-38190 BERNIN (FR). (72) Inventors: SCHWARZENBACH, Walter; 19 CHEMIN DU MOLLARD, F-38330 SAINT NAZAIRE LES EYMES (FR). DURET, Carine; 18 av du General Cham- pon, F-38000 GRENOBLE (FR). BOEDT, Francois; 3 Allee des Frenes, F-38240 MEYLAN (FR). (81) Designated States (unless otherwise indicated, for every kind of national protection available)'. AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available)'. ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) — of inventorship (Rule 4.17(iv)) Published: — with international search report (Art. 21(3)) (54) Title: PROCESS FOR TREATING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE FOR IMPROVING THICK­ NESS UNIFORMITY OF THE SEMICONDUCTOR LAYER FIG. 5 30-, 20- 10- 0- ry -15 A -10 A r -5 A A oo i> CJ i> i-H cn i-H o CJ o & et +5 A o e mean (A) +10 A +15 A (57) Abstract: The invention relates to a process for treating structure of semiconductor-on-insulator type a successively comprising a support substrate (1), a dielectric layer (2) and a semiconductor layer (3) having a thickness of less than or equal to 100 nm, said semiconductor layer (3) being covered with a sacrificial oxide layer (4), comprising: measuring, at a plurality of points distributed over the surface of the, structure, the thickness of the sacrificial oxide layer (4) and of the semiconductor layer (3), so as to produce a mapping of the thickness of the semiconductor layer (3) and to determine, from said measurements, the average thickness of the semiconductor layer (3), selective etching of the sacrificial oxide layer (4) so as to expose the semiconductor layer (3), and carrying out chemical a etching of the semiconductor layer (3), the application, temperature and/or duration conditions of which are adjusted as a function of said mapping and/or of the mean thickness of the semiconductor layer (3), so as to thin, at least locally, said semi - conductor layer (3) by a thickness identified as being an overthickness at the end of the measurement step.