Patent KR-100251932-B1 (KR)
Title: Memory testing method
Inventor: SEO CHANG-WOO
IPC: G11C29/00
Filed: 1997-12-26
Granted: 2000-05-01
Abstract: PURPOSE: A test method of a memory is provided to detect all of the fails of not only a single port memory but also a dual port memory. CONSTITUTION: A test apparatus of the method includes a tester(200) performing a test according to the test method of the memory, and the first port connection part(202) and the second port connection part(204) connecting the tester with the memory. The test apparatus can be connected to a single port memory through the first port connection part or to a dual port memory through the first or the second port connection part.The method includes the steps of: writing the first value to a memory cell corresponding to each address as increasing the address from an initial address to a final address; reading the first value from the memory cell and writing the second value to the memory cell; reading the second value from the memory cell as to the single port memory and writing the first value to the memory, and reading the first value from the memory cell through the first port as to the dual port memory and writing the first value through the first port, and reading the second value through the second port and writing the second value through the second port to the memory; reading the first value from the memory cell corresponding to each address as decreasing the address from the final address to the initial address, and writing the second value to the memory cell; reading the second value from the memory cell and writing the first value to the memory cell; reading the first value from the memory cell corresponding to each address as decreasing the address from the final address to the initial address as to the single port memory, and writing a toggle value to the memory cell, and reading the first value through the first port from the memory cell corresponding to each address as increasing the address from the initial address to the final address as to the dual port memory, and writing the toggle value to the memory cell through the first port; reading the toggle value through the first port from the memory cell corresponding to the one-increased address than each address as increasing the address from the initial address to the final address as to the dual port memory, and reading the second value through the second port from the memory cell corresponding to each address while reading the toggle value through the first port, and writing the second value to the memory cell through the second port; reading the second value through the first port from the memory cell corresponding to one-increased address than each address as increasing the address from the initial address to the final address as to the dual port memory, and reading the second value through the second port from the memory cell corresponding to each address while reading the second value through the first port, and writing the first value through the second port to the memory cell; reading the first value from the memory cell corresponding to the address as increasing the address as to the dual port memory, and writing the second value to the memory cell through the second port, and reading the first value from the memory cell through the first port while reading and writing the value from/to the memory through the second port, and writing the first value to the memory cell; and reading the second value from the memory cell corresponding to the address as decreasing the address from the final address to the initial address as to the dual port memory.