Patent GB-1182621-A (GB)
Title: Data Processor
IPC: G06F9/355
Filed: 1967-02-14
Abstract: 1,182,621. Data processors. BURROUGHS CORP. 14 Feb., 1967 [14 Feb., 1966 (2)], No. 6187/67. Heading G4A. A data processing system uses a portion of an instruction word to select a register to select a memory division. Fig. 1 shows a processor in which a data output multiplex unit 104 can route a word from any of the registers shown connected to its input, or the OR of the words in any two of these registers, to memory or an I/O module or a parallel adder 103, and may ones-complement the word in the last ease e.g. for subtraction. Also the multiplex unit output is displayed, and may be held at all zeros to permit the adder to be used for simple data transfer via its other input or this latter input may be inhibited to permit data transfer via the first. A data input register 100 receives an instruction, data, index or indirect address word from memory or an I/O module and supplies it to the appropriate other unit(s) as shown. In the case of an instruction word, the operation code and modifier bits are also sent direct to an operation register as shown. A memory address multiplex unit 115 supplies a memory address to memory control from any of various units shown. These units include an address field register 116 and programme counter 117, in which each flip-flop is set through a respective OR gate to which the flip-flop output is fed back via an AND gate so that the OR gate output represents the flipflop state until an input arrives to change the state when it represents the new state. It is the OR gate output which is used to supply the memory address multiplex unit 115, thus saving a cycle during memory addressing when the flip-flop states have to be changed since the OR gates provide the new states before the flip-flops change to them. Other units are fed from the flip-flops. The address field register 116 can receive a memory module selecting 3-bit address portion for either a primary or a secondary selection register 119a, 119b (further such registers may be provided) according to the value of a "module" bit in the current instruction, the address field register also receiving the address of a word within the selected module direct from the instruction. An instruction is provided which causes part of a data word to be loaded into the programme counter 117 and part into the selection registers 119a, 119b, the previous contents of counter 117 and registers 119a, 119b being saved in memory. If an index word called into use has a particular bit at 1, three other bits of it are loaded into the module selecting portion of the address field register 116. Part of any indirect address word called into use replaces the current contents of the address field register 116. The instructions are one-address instructions and when reached in the programme may have up to three indexing operations performed followed by an unlimited number of indirect address operations each succeeded by up to three indexing operations. For indexing, an index location register 118 provides the high order 13 bits of the memory address of the required index word, the other 2 bits being provided by the instruction, index or indirect address word in the data input register 100, indexing only being effected if at least one of these 2 bits is at 1. If both bits are 0, they in conjunction with the contents of the index location register 118 may be used to address in memory a word giving (a) a programme-portion iteration count; (b) the address of the results of a successful test of a block of memory words; (c) the number of shifts necessary in a normalizing instruction; (d) the address of temporary storage used in a shift operation between memory locations; (e) an upper or lower limit to test a string of words against. The adder 103 output can be inserted into an A register 107 directly or shifted to the right one bit or ANDed in with the previous contents, or the A register 107 can be shifted left one bit. Since the A register 107 can feed the adder 103 via the data output multiplex unit 104 the "shifted right feature allows the contents of the A register 107 to be shifted right by passage through the adder 103 thus permitting addition and shift together in multiplication. The C register 108 shown is like the A register 107 except that shifting right is done at the register without passage through the adder 103. The adder 103 is a parallel binary adder using both ripple carry and group carries (carry look-ahead) and uses NAND (or NOR) circuits shown as AND and OR circuits since some signals within the adder are in inverse form. The adder can provide the EXCL-OR of its inputs to a register check circuit 105 for detecting equality. The A and C registers 107, 108 can be used as separate "accumulators" for the adder 103 or may be combined for double precision add, subtract, multiply or divide. Other processors may share the memory, provision being made for inhibiting the memory address multiplex unit 115 of each processor. The address field register 116 can be used as a counter of sequential addresses in block testing or of iterative steps in multiplication or division. The address field register 116 can also be used to modify the command supplied to a command decoder 121 by the operation register 109. Outside the processor each word has a parity bit, used in a check at 101 and generated to attach to a word leaving the processor at 110. The instruction fetch phase for one instruction overlaps the execution phase for the previous instruction. On restart after a halt, different timing steps are used initially so that the next instruction is fetched without attempting to execute the previous instruction (again). When a memory access is requested, supply of clock pulses to the processor is inhibited until the memory is ready, a memory busy signal being obtained by ORing outputs of a chain of clock-driven flip-flops forming a counter. Separate such arrangements may be provided for different memories or different types of access. Overall timing is from an external clock via an I/O control module. Specification 1,182,622 is referred to and has the same disclosure.