Patent GB-1335031-A (GB)
Title: Data processors
IPC: G06F9/46
Filed: 1970-11-03
Abstract: 1335031 Multiprocessor system HONEYWELL INFORMATION SYSTEMS Inc 3 Nov 1970 [3 Nov 1969] 52303/70 Heading G4A  A multiprogrammable, multiprocessor data processing system includes at least one central processor, at least one input/output processor, a store for storing central processor and input/ output processor programmes, and a multiprocessor controller which in response to an interrupt signal from a processor which modifies the relative priorities of the programmes when such modification is such that currently running programme is not the highest priority accepts control of the current programme and provides control of another programme to the processor in accordance with the modified priority. As described three central 12, 14, and 16, and three input/output 18, 20 and 22 processors are provided each connected to a multiprocessor controller 24 which is arranged to ensure that all the processors are fully occupied processing one of their associated programmes at all times. Any one of the central or input/output programmes may, during its execution, require access to a particular input/output or central programme respectively; this is achieved by interrupting the processor associated with the required programme and adjusting the priorities (activity states) of the appropriate programme(s). The activity states of all the programmes are indicated by a number of activity state indicators in the multiprocessor controller 24. When an interrupt occurs a programme, either a central or an input/output programme, may be upgraded or downgraded or one programme may be upgraded and another downgraded. The processors are conditioned to execute their highest activity state programme so that none of the processors is ever left idle. If more than one programme is in the highest activity state the one having the highest priority (determined in an arbitrary manner by the location of status words in the store) is executed. Several types of interrupt are possible. In the first which may originate in either a central or an input/output processor, an order requesting upgrading and/or downgrading of particular programmes is generated. In the second an input/output processor requests the service of a particular device controller which is used to control, e.g. print out devices, magnetic tapes, &c., the device controller indicating that it is not available. A third interrupt originates in an input/output processor and indicates that a particular device controller has completed servicing an input/output programme. The fourth interrupt originates in an external source such as one which is provided to monitor, e.g. an industrial process. Priority buses 57 are provided for resolving conflicts between the multiprocessor controller and two or more device controllers which have simultaneously requested the services of an input/output processor. Four activity states are possible. In the first, STOPPED, the programme is inactive, in the second, ENABLED, the programme is inactive but can be made active, in the third, SEQUENCING, the programme is active and may be called, and in the fourth, COMMITTED, the programme is active and has been requested by an interrupt. The programmes are normally executed by examining a portion of the called programme which contains the address of the instruction required. This address is then incremented for each successive instruction until an interrupt is called. When the activity states of the appropriate programmes have been modified a comparison is effective to determine which programme is to be executed. The Specification describes the central and input/output processors and the instruction formats used therein in some detail.