Patent GB-1350165-A (GB)
Title: Display baseline stabilization circuit
IPC: G01R13/30
Filed: 1972-07-31
Abstract: 1350165 Cathode-ray tube displays TEKTRONIX Inc 31 July 1972 [30 July 1971] 35662/72 Heading H4T  The base line references of a plurality of input signals successively displayed on a cathode-ray tube are automatically maintained at the same vertical position. The invention is described as employed in a system for detecting impedance discontinuities in a transmission line 14 (Fig. 1) under different termination conditions set by switch 30 the arrangement utilizing a known sampling system 10 which samples successive input and reflected test pulses (G), (see also Figs. 2 and 3) at different instants during a plurality of single horizontal sweeps of the display tube 18 and employs the samples to produce a vertical deflection of such sweep to reproduce the entire pulse. In the operation of the system, a trigger pulse (H) triggers a test pulse generator 12 comprising a tunnel diode 32, connected as a bi-stable device, from its quiescent low voltage state (which determines the vertical position of the base line reference) to a high voltage state comprising a step voltage (G) and, in known manner, the sampling system 10 operates under the control of strobe pulses (J) and sampling memory gate pulses (K) to store successive samples of the inputs to sampling gate 28 (diminished by the feed-back via resistors 54, 58) in capacitor 52 the charge on which effects vertical deflection of the horizontal trace produced by ramp generator 68. Each trigger pulse is produced on amplitude coincidence between a fast ramp (F) and an adjustable reference from potentiometer 122 and each test pulse is terminated by a pulse over conductor 76 before the commencement of each fast ramp. At the end of each horizontal trace generator 68 produces a sweep hold-off output (B), which via a correction period generator 78, produces a pulse (C) the latter operating switch 106 to replace the input from ramp generator 68 to comparator 64 by a fixed reference (zero) voltage so that the sample time pulses (I) now occur at fixed intervals i.e. at the zero crossing of the fast ramp generator 32 (F). Additionally, the pulses (C) condition AND gate 80 to pass pulses (D) from memory gate driver 48 to a correction gate 86 to switch it from the position shown and also operate a switch 82 from the position shown. The samples are now taken before the occurrence of the trigger pulses (H), the test pulses (G) due to the previous triggers having being terminated by the output of ramp gate oscillator 60 over conductor 76, and the sample values, which now represent the quiescent level, are transmitted via gate 86 to a difference amplifier 84 in which they are compared with a reference voltage-OV and then via base line correction memory 24 (waveform (L)) and summer 90 to the output of the sampling gate 28 for subtraction from the input to the gate. Thus the output level (the quiescent level) is subtracted from the input level (also the quiescent level) and all base references (switch 30 in any position) therefore have zero voltage level. At the end of correction period pulse 98 (Fig. 2) the circuit reverts to the connections shown and by adjustment of the manual OFF-SET potentiometer the actual vertical position of the base reference lines may be positioned as required.