Patent GB-1512106-A (GB)
Title: Automatic gear change control device in an electromobile
IPC: B60K1/00
Filed: 1975-09-15
Abstract: 1512106 Change-speed control AGENCY OF INDUSTRIAL SCIENCE & TECHNOLOGY 15 Sept 1975 [14 Sept 1974] 37869/75 Heading F2D Gear shift on a battery electric vehicle is automatically controlled in response to output speed and motor torque in accordance with a shift pattern in which for each ratio there is an allowable shift range according to the relationship between the permitted maximum torque and speed of the motor, wherey a ratio is automatically selected in which the total losses in the motor system are minimized. Basis for the minimum loss control are Figs. 3, 4 and 5. Fig. 3, for given maximum motor torque and speed, represents load torque against vehicle speed for three gear ratios, giving three envelopes I, II and III in which the respective ratio can be effective, and including overlap areas in which two or more ratios I, II; II, III or I, II and III, can be effective. For Fig. 4, relations are developed from the equation of total losses (e.g. ohmic, iron, friction and windage), in which, for a given required condition of output speed and output torque, the losses would be less in one ratio than those in an adjacent ratio, such relations being represented by linear boundary lines l 1 , l 2  and l 2 , l 3  between first and second, and second and third ratios respectively. Thus, above the line l 1 , l 2 , losses would be less for a particular condition in ratio I, than in ratio II, whereas for another condition losses would be less below the line in ratio II. Superimposing Fig. 4 on 3 produces the shift pattern shown in Fig. 5, in which, for given conditions there are three individual envelopes, shown in full lines, in each of which a single ratio I, II or III results in minimum loss. The full lines may commence away from the origin, Fig. 8, not shown, and may include hysteresis, Fig. 10, not shown. An electronic circuit producing this ratio shift pattern, with coincidental electric or electro-hydraulic control of a main clutch, and the ratio shift itself, ratio synchronizing by motor speed control for both accelerating and braking, and motor current limit, is shown in Figs. 2 and 6. In Fig. 2 the motor 1 is energized by a battery 9 through a thyristor chopper motor drive, circuit 8, and also included are a motor control circuit 10 for forward, reverse, heavy load, braking and current control; a motor current limiter 11 responding to an armature current detector 12; a command circuit 13 producing motor mode and speed instructions according to accelerator and brake signals 14, 15 and a ratio synchronizer 16; and a logic circuit 17 (detailed in Fig. 6, below), controlling through a drive circuit 7, speed-ratio selection in the gear 2 with coincidental clutch release, and the ratio synchronizing circuit 16. The speed-ratio and clutch control logic circuit, Fig. 6, has input parameters constituted by armature current Im, representing motor torque, and converted to output torque # by signals Ib, IIb, IIIb of established speed ratio in analogue gates 21, 22, 23 and an adder 24; together with vehicle speed V. Comparators 25, 26 receive the output torque signal and signals from function generators 27, 28 which latter, from vehicle speed V, compute the minimum loss boundary lines l 1 , l 2  and l 2 , l 3  of Fig. 5. The comparators 25, 26 issue "1" signals if output torque is smaller than the l 2 , l 3  or l 1 , l 2  value respectively, and two further comparators 29, 30 issue "1" signals if vehicle speed V exceeds V 2 , V 3  and V 1 , V 2  (Fig. 5) respectively, the paired signals issuing to OR gates 31, 32. If an output "1" appears either (a) from comparator 25 at A, or (b) from comparator 29 at C it indicates that third ratio III should be effective for either (a) to minimize losses or (b) due to excessive vehicle speed, and the OR gate 31 issues a "1" signal at IIIa for shift to third ratio. Similarly on output "1" from the OR gate 32 indicates that the operational area includes ratios II and III (Fig. 5), and, to subtract III, output IIIa is fed through an inverter 33 to an AND gate 34 along with the II, III output from the gate 32. If ratio III is not commanded output IIIa is at "0", so that output from the gate 34 will be at "1" for a command IIa for second ratio. A similar inverter 35 and AND gate 36 precludes ratios II and III to issue a "1" at Ia if first ratio is required. Differential circuits 37, 38, 39 generate pulses IIP 1  &c. at the leading edges of the signals IIIa, IIa and Ia, for issue to AND circuits 40, 41, 42, the other inputs of which are derived from the terminal Q of a bi-stable 54 in a synchronizing circuit (below), so that the AND circuits 40 ... 42 have zero output whilst the synchronizing circuit is effective, but issue the pulses IIP 1 , &c., whilst the synchronizing terminal Q is at "0", to differential circuits 44, 45, 46, which issue pulses IIP 2 , &c. at the trailing edges of the pulses IIP 1 , for setting bistables 47, 48, 49 which issue signals IIIb, IIb, Ib to AND gates 50, 51, 52 which, when enabled, issue ratio shift and clutch command signals IIIc, IIc, Ic the sequence for a shift being as follows, assuming that the vehicle is running in ratio I and upshift to ratio II has been required by the Im and V input parameters. Initially the synchronizing circuit is inoperative with the terminal Q of the bi-stable 54 at "0", and Q at "1", opening the gate 41 to the second ratio pulse IIP 1  (which appears when the Ia signal goes to "0" and IIa to "1"), the gate 41 then issuing the pulse to an OR gate 43 which re-sets the previously effective ratio I bi-stable 49, producing "0" on lines Ib, Ic to release the main clutch and neutralize the transmission. The pulse IIP 2  now sets the ratio II bi-stable 48 to issue a "1" on the line IIb to the gate 51 which, however, is now closed by the IIP 2  pulse, through an OR gate 53, setting the synchronizing bi-stable 54 for "0" on Q and issue of a constant synchronizing signal ff on Q. All ratio shift and clutch action is now suspended and, following a timed delay ffd introduced by a timing mono-stable 55 and AND circuit 56 after which the latter issues a synchronizing command signal fv to control motor speed, by means not described, to suit the new ratio. At the end of a timed synchronizing interval a signal fve (from a source not described) re-sets both the bi- and mono-stables 54, 55, erasing the synchronising signal fv and issuing a signal at Q of 54 to re-open the gates 41 and 51, enabling the latter to issue the IIc signal for shift to ratio II followed by re-engagement of the main clutch. Pulse wave forms at various parts of the circuit are given in Fig. 7, not shown.