Patent SG-11201900403P-A (SG)
Title: Circuits and methods providing mutual capacitance in vertical electrical connections
Inventor: PATHMANATHAN PRIYATHARSHAN
IPC: H05K1/16
Filed: 2017-08-08
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 08 March 2018 (08.03.2018) WIPO I PCT (10) International Publication Number WO 2018/044514 A1 (51) International Patent Classification: H05K1/02 (2006.01) H01L 23/498 (2006.01) H0SK1/11 (2006.01) H05K1/16 (2006.01) (21) International Application Number: (22) International Filing Date: (25) Filing Language: (26) Publication Language: PCT/US2017/045888 08 August 2017 (08.08.2017) English English (30) Priority Data: 15/255,412 02 September 2016 (02.09.2016) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (72) Inventors: PATHMANATHAN, Priyatharshan; 5775 Morehouse Drive, San Diego, California 92121 (US). PA- TEL, Devarshi; 5775 Morehouse Drive, San Diego, Cali­ fornia 92121 (US). NORTHGRAVE, Dennis Allen; 5775 Morehouse Drive, San Diego, California 92121 (US). ROBERTS, Kyle; 5775 Morehouse Drive, San Diego, Cal­ ifornia 92121-1714 (US). (74) Agent: KELTON, Thomas W. et al.; HAYNES AND BOONE, LLP, 2323 Victory Avenue, Suite 700, Dallas, Texas 75219 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available)'. AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available)'. ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). (54) Title: CIRCUITS AND METHODS PROVIDING MUTUAL CAPACITANCE IN VERTICAL ELECTRICAL CONNECTIONS 100 •t i-H •t •t © 00 i-H o CJ O £ FIG 1 (57) : An electrical device including a structure having a plural­ ity of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers, a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the vertical electrical connection, wherein the first capacitive structure is dis­ posed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer, and a second vertical electri­ cal connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer. [Continued on next page] WO 2018/044514 A1 llll II II11 III III II II llllI I Hill II III Declarations under Rule 4.17: — as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(H)) — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(Hi)) Published: — with international search report (Art. 21(3))