Patent GB-1087575-A (GB)
Title: Communications accumulation and distribution
IPC: G06F9/30
Filed: 1964-09-18
Abstract: 1,087,575. Digital electric computer. RADIO CORPORATION OF AMERICA. Sept. 18, 1964 [Oct. 4, 1963], No. 38208/64. Heading G4A. A digital computer system for transferring data between a plurality of input and output lines and a corresponding plurality of message storage zones in a message storage memory comprises a procedure memory having addresses (identifying respective input and output lines) for corresponding procedure word storage locations, means to address cyclically all of said procedure word locations, a procedure register connected to receive information read from said procedure memory, means using the contents of said procedure register to address a line and a word location in said message storage memory and to condition a character signal path between the addressed line and the addressed location in said message storage memory, and means to modify and update the contents of said procedure register and write it back into said procedure memory. Ingoing charactere.-As described, with reference to input lines, an address from stage LA<SP>1</SP> passes to Memory Address Register (MAR) 22 to address a word location in Procedure Memory (PM) 10 which corresponds to the line buffer to be serviced. Also the address from LA<SP>1</SP> passes via line 73 to enable the specified line buffer. The addressed word in PM10 is read via Memory Register (MR) 24 to the Procedure Register 50, the portion LA then holding the address of the next line buffer to be serviced, MA holding the address in Memory 12 where the line information presently being serviced is to be stored and TALLY containing the information necessary to transfer the data from the input line. The TALLY contents then pass via line 65 to enable AND gate 18, also to AND gate 28 to determine the portion of the code conversion word to be used for the input character to be received, and via line 63 to COMMAND LOGIC 64 which then permits subsequent passage of a code connected character from CONVERSION REGISTER 30. The input character passes via gates 18, 20 to MAR 22 where the character constitutes the address of a code conversion and instruction word in the code conversion zone of MEMORY 10, the particular code to be used being selected by gate 28 under the instruction of the TALLY contents, the code being suitable for use in a Communications Data Processor (not shown). The word transferred includes the code converted character which is directed to stages CHAR of Register 30 land a machine instruction which is directed to INSTR, which is then passed to COMMAND LOGIC to produce the required result. The character in stages CHAR may then be forwarded to MEMORY 12. Outgoing characters.-The procedure is the same as above up to the information being transferred to the PROC. REG. 50. The TALLY stages then enable gate 44 and condition gate 28. The character in MEMORY 12 addressed by MA is then read out via gates 40, 42, 44, 20 to MAR 22, the character supplied being in the code used by the Communications Data Processor and constituting the address of a conversion word in the Conversion zone of MEMORY 10. The addressed conversion word is then directed to gate 28 and the character in the code specified for the particular output line buffer is passed to the CONV. REG. 30, the INSTR portion being passed to COMMAND LOGIC 64. The CHAR portion may then be passed along output line 16. Error detection and updating of control information.-If an invalid or unassigned character is received at Register 30 then stages INSTR has a machine instruction indicating that the character is invalid or unassigned. This instruction is passed to COMMAND LOGIC where it is decoded and produces a signal to reset stages CHAR and also to insert a predetermined error-indicating character into the stages CHAR, and to insert an error-indicating bit in stages TALLY. The procedure word is later returned to PROCEDURE MEMORY 10. After a predetermined number of characters has been transferred, the machine will examine the error indicating bit and may request re-transinsion, or include an error indicating character in the transmitted message. The stages TALLY and MA may be updated under the control of LOGIC 64 after transmission of each character to indicate the fact that an additional character of the message has been accumulated and to change the storage address for the next character, the updated procedure word being directed via gates 84, 86 to MEMORY REGISTER 24 from which the word is rewritten into MEMORY 10 in the same storage location that it previously occupied. Computer interrupt.-During specified time periods MEMORIES 10, 12 can be accessed by the Communications Data Processor via computer interrupt logic and gates (Fig. 1A, not shown) for the purpose of using or changing the procedure and conversion words or for the purpose of transferring message words to or from the CDP.