Patent GB-1470667-A (GB)
Title: Time-spacetime type time-division switching system
IPC: H04Q11/06
Filed: 1974-04-05
Abstract: 1470667 Automatic exchange systems P VOYER J-M PITIE O LOUVET and A ROCHE 5 April 1974 [6 April 1973] 15296/74 Heading H4K In a time-space-time PCM, TDM system, the transfer of PCM words from an incoming buffer store on to an incoming superhighway and the transfer of PCM words from an outgoing superhighway to an associated outgoing buffer store is controlled by a single control store, the system being characterized by a complicated arrangement of partial serial and parallel superhighways. The application is to a "four wire" system in which a first time slot is used on the superhighways for one direction of communication and the following time slot is used for the reverse connection. Referring to Fig. 4, which is not an embodiment of the invention but which is included for explanatory purposes, each of 512 time channels of a group of 16 incoming serial 32 channel highways 1p0-1p15 has a permanent storage location of an incoming buffer store 3p allocated thereto, the associated outgoing buffer store 13p and highways 2p0-2p15 being similarly arranged. For a connection between a time channel i of highway pair 1pk, 2pk and a channel j of highway pair 1qm, 2qm a search is performed for a free time slot #x on superhighway 12p which gives access via a gate 15pq of the space switching stage to superhighway 11q, the time slot #(x+1) being automatically allocated to the reverse connection via superhighways 12q, 11p and gate 15qp. In control store 9p the address of the storage location 3pki in buffer store 3p associated with the incoming channel i of highway 1pk, and identical to the address of storage location 13pki in buffer store associated with the outgoing channel i of highway 2pk, 13p, is stored in partial stores 90p, 91p (Fig. 5, not shown) under the designation #x. Similarly the address of location 3qmj of buffer store 3q (identical to that of location 13qmj of buffer store 13q) is stored in partial stores 90q, 91q of control store 9q under the designation #(x+1). In operation partial control stores 90p, 90q supply addresses to the incoming buffer stores 3p, 3q in the designation order #0, #1 ... #x, #(x+1) ... #511, #512 whereas partial buffer stores 91p, 91q supply the addresses in the designation order #1, #0, ... #(x+1), #x ... #511, #510. Hence during slot #x the address of location 3 pki is supplied to buffer store 3p by partial control store 90p, the address of location 13qmj is supplied to buffer store 13q by partial store 91q and crosspoint 15pq is operated in known manner to complete the connection. During slot #(x + 1) the reverse connection is similarly made. In each embodiment, Fig. 7 (and Figs. 6, 8, 9, not shown), each 512 slot parallel bit superhighways, e.g. 12p is demultiplexed into 8 highways 212(p0-p8) each having 64 time slots in which PCM words are serially transmitted, the demultiplexing being performed such that the channels of highway 212pn (n=0 to 8) carry the information of parallel bit slots #(0+n), #(8+n) ... #(504+n), in serial form. On the other side of the space switch the highways 211po-211pn are remultiplexed on to a 512 slot superhighway 11p. If it is arranged during the remultiplexing for adjacent time slots to be interchanged such that slots #x, #(x+1) of a superhighway 12(0-31) are placed in the order #(x+1), #x, on a superhighway 11(0-31), the control stores 9(0-31) can be simplified in that they now simultaneously supply the same address to both associated buffer stores. Alternatively instead of reversing the order of adjacent pairs of slots # during the remultiplexing, the remultiplexine is performed in the natural order, a delay of 2# being introduced for the even numbered highways 211pn and hence for the even time slots #, during remultiplexing and a delay of # being introduced in the path between the control store 9p and the outgoing buffer store. For a detailed explanation of these embodiments reference should be made to the Specification. Alternative arrangements of the space switches of Fig. 7 are described with respect to Figs. 8 and 9 (not shown).