Patent GB-1302547-A (GB)
IPC: G06F13/18
Filed: 1969-07-25
Abstract: 1302547 Data processing; data storage MARCONI CO Ltd 23 April 1970 [25 July 1969] 37442/69 Headings G4A and G4C A data processing arrangement comprises a plurality of processors each including a CPU and a store, the store having an input section into which information is received and a working section into which information is transferred from the input section by the CPU for programmed processing, means being provided to effect independently of the CPUs the transfer of information from the store of one processor to the input section of the store of another processor whilst the CPUs of the two processors are not accessing their respective stores. An executive processor may communicate with each of a plurality of peripheral processors in the above way. Fig. 1 shows the executive processor, having a store 1 with input, output and working sections. A word has 10 bits, viz. a control bit, 8 data bits and a parity bit. When a peripheral processor wants to send data to the executive processor it sends a control bit of 1 and two data bits specifying the interrupt priority, over a respective highway 9 to an interrupt unit 13 which sets the priority bits into marker toggles 14. A scanner 15 passes the address of the requesting peripheral with the highest priority, and the priority, to an autonomous I/O controller 10. Marker toggles 2 associated with the input section of store 1 indicate which data blocks are empty and the priorities of the occupied ones for transfer to the working section under CPU control. I/O controller 10 is informed of the address of the next empty block by a scanner 17 and the highest priority for transfer to the working section by a scanner 16, in response to the toggles 2. Marker toggles 3 associated with the output section of store 1 specify the priorities for output from the output section, a scanner 18 informing the I/O controller 10. If the input request from the peripheral is of highest priority, the I/O controller 10 provides the peripheral's address to a decoder 20 which controls a crosspoint switch array 8 to connect up the appropriate highway 9, and sends a control bit of 1 to the peripheral which sends its data to the store input section via highway 9 and a serialto-parallel converter 6. The transfer can be interrupted by the executive CPU if it wishes to access store 1, the peripheral being told to wait. Output from the output section to a peripheral is via a parallel-to-serial converter 7 and highway 9, an address register 19 supplying the peripheral address via I/O controller 10 to decoder 20 to connect up the highway 9. If the peripheral is not ready, the next data block for output is selected. During both input and output, every Nth word (counter 12) is a header word which is decoded at 11 to tell the I/O controller 10 whether the message has ended or not. These transfers are parity-checked with retransmission (once) on error. Transfer from the input section of store 1 to the working section uses the block (to be transferred) address supplied by I/O controller 10 on output 21. Fig. 2 shows a peripheral processor (which is telephone exchange T.D.M. equipment), with autonomous I/O controller 36, store 28, CPU 29, read-only control store 30, store addressing circuits 34, 35, a serial-to-parallel/parallel-toserial converter 33 between highway 9 and store 28 (for transfer in both directions), and another such converter 25 between store 28 and a cyclic buffer store 24 which via an input/output register 23 receives T.D.M. signals from an input 22 and controls T.D.M. functions such as dial tone and call-hold over an output 21. Buffer store 24 has 32 slots communicating in both directions with respective data blocks in a section 27 of store 28. These blocks have respective marker toggles 45 indicating whether empty and if not also the priority and destination of the signals stored. The controller 36 interrupts the CPU 29 at regular intervals to permit transfer from buffer 24 to section 27. Section 27 can receive data from the executive processor via a section 32 of the same store 28 and can supply data to the executive processor. Data in section 27 can be processed by CPU 29.