baber/WOPTO huggingface dataset:
Patent JP-H06146175-A (JP)
Title: Leathery sheet good in fouling resistance
Inventor: AKAZAWA TOSHIYUKI
IPC: C08G18/65
Filed: 1992-10-30
Abstract: PURPOSE:To obtain a leathery sheet excellent in fouling resistance by impregnating an entangled nonwoven fabric with a polyurethane resin prepared by reacting specific components at a specified blending ratio and excellent in mechanical characteristics, durability, processing suitability, etc. CONSTITUTION:This leathery sheet is obtained by reacting (A) an intermediate diol, having terminal OH groups and prepared by reacting (A1) a fluorine- containing diol obtained by radically polymerizing a perfluoroalkyl ester of (meth)acrylic acid in the presence of a compound containing hydroxyl groups and one thiol group with (A2) a polymer diol, selected from polyesters, polycarbonates and lactones, etc., and having 500-3000 number-average molecular weight and (A3) an organic diisocyanate in a quantitative relationship so as to provide 0.5-0.99 equiv. ratio of NCO/OH and (B) a low-molecular diol and (C) diphenylmethane-4,4'-diisocyanate, impregnating an entangled nonwoven fabric composed of ultrafine fiber bundles having preferably <=0.1d size with the resultant polyurethane resin and coagulating the polyurethane resin. This sheet is soft and excellent in fouling resistance and durability.
Patent JP-S62154005-A (JP)
Title: Programmable controller
Inventor: TOYOOKA KATSUJI
IPC: G05B19/05
Filed: 1985-12-27
Abstract: PURPOSE:To substantially facilitate program preparation work and program modification at the time of changing an action sequence by controlling a device at every step. CONSTITUTION:A content (k) instructing the next unit step (shifting step) is programmed in the end of a unit step (n). If shift conditions written in the unit step (n) hold, a flag equivalent to the (k) in a step flag memory part is turned on, and the program in the unit step (k) is executed. If programming is made with k=m given as flow chart shows, the operation is shifted by jumping to a unit step (m). Whereas programming is done with k=n' given, the operation jogs to a unit step n'. A flag on a par with (n) in the step flag memory part is turned off, and the execution of the control of the unit step (n) is completed.
Patent JP-H05129826-A (JP)
Title: Plane antenna
Inventor: KURODA SHINICHI
IPC: H01Q9/04
Filed: 1991-11-08
Abstract: PURPOSE:To miniaturize an entire communication equipment by arranging a conductive enclosure in the opening of a ringular radiator so that the upper face can be positioned on the same plane as the radiator, and connecting the conductive enclosure and a ground conductor. CONSTITUTION:Concerning a planar antenna 20c, a rectangular ground conductor 21 and a rectangularly ringular radiator 23 are coaxially laminated through a dielectric layer 22 of a low loss. In this case, the ground conductor 21 and the dielectric layer 22 are respectively ringularly formed as well, and the dimension of an opening in the dielectric layer 22 is set smaller than that of an opening 23i in the radiator 23. Then, a dielectric enclosure 25 is inserted to the opening of this dielectric layer 22 so that an upper face 25t can be positioned on the same plane as the radiator 23, and suitably connected to the ground conductor 21. Therefore, the inside of the enclosure 25 is electro-magnetically shielded from a radiating system. Further, the bottom of this enclosure 25 is opened, and an RF circuit is integrated into the inside space.
Patent JP-H09114575-A (JP)
Title: Tablet
Inventor: TAGUCHI KATSUHIKO
IPC: H04N5/00
Filed: 1995-10-17
Abstract: PROBLEM TO BE SOLVED: To eliminate the need for a transmission circuit for radio transmission by transmitting cursor control data to an equipment to be controlled in accordance with a transmission format through the use of the control data transmission means of a remote control transmitter remotely controlling the operation of the equipment to be controlled by wireless. SOLUTION: A cursor control data generation circuit 22 compares pressure position data of inputted x and y coordinates with that inputted just before and forms cursor control data of three byte from the difference. Then until data of three byte are all inputted, cursor control data is temporarily stored in a data register 24 and after then outputted to a control circuit 13 to be transformed to transmission data. This transmission data is in accordance with the transmission format of a remote control transmitter executing the operation control of TV. Then the control circuit 13 outputs PPM-modulated transmission data to an output circuit 25. In addition a PPM modulation signal is subjected to secondary modulation to control a driving transistor 28.
Patent JP-H06278168-A (JP)
Title: Injection mold
Inventor: KATAOKA HIROSHI
IPC: B29C33/40
Filed: 1993-11-24
Abstract: PURPOSE:To mold economically without raising temperature of a mold by setting drafts of a face coated with a heat insulating layer to above a predetermined value, in an injection mold whose wall face is coated with a heat insulating layer consisting of heat insulating polymer. CONSTITUTION:In an injection mold, a mold cavity 3 for housing body is formed by a fixed mold 1 and a moving mold 2. Synthetic resin is injected into the mold cavity 3 through a spool 6, a runner 7, and a gate 8 so as to mold a housing body by injection molding. The housing body molded by injection is ejected from the mold by an ejector pin 4 and the molded piece is provided with ribs 9 and bosses as occasion demands. The wall face of the mold which forms the mold cavity 3 is coated with a heat insulating layer 5 consisting of heat insulating polymer. Drafts A and B of the face coated with the heat insulating layer 5 are 1/mold shrinkage factor or more.
Patent JP-H06150663-A (JP)
Title: Storage circuit
Inventor: KAWAMATA NOBORU
IPC: G11C11/401
Filed: 1992-10-30
Abstract: PURPOSE:To start writing in a built-in storage circuit capable of reading and writing sequential file access within a display driving circuit, etc., without the waiting time. CONSTITUTION:A flip-flop group constituting an address selecting shift register 5 is composed of a flip-flop 1 with a set terminal and flip-flops 2-4 with reset terminals. A writing demand signal 15 is inputted to the flip-flop with a set terminal as a setting signal and to the flip-flops 2-4 with reset terminals as a resetting signal.
Patent JP-H05128785-A (JP)
Title: Hub locking mechanism for tape cassette
Inventor: KONDO SHINICHI
IPC: G11B23/087
Filed: 1991-11-08
Abstract: PURPOSE:To easily and surely lock reel hubs and to prevent the slackening of a magnetic tape by providing the hub locking mechanism. CONSTITUTION:The hub locking mechanism 11 is constructed by projecting locking members 13, 14 to the flank of a bar-shaped base plate 51. The locking members 13, 14 engage with gear-shaped locking member engaging parts 12 provided on the reel hubs 3, 4 and lock the reel hubs 3, 4 non-rotatably when the base plate 51 held fitted to groove parts 34, 45 is slid in one way by operating an operating member 15. A projection 53 for a stopper simultaneously fits to a projecting fitting part 43 and maintains the hub locking state. The locking members are disengaged when the operating member 15 is slide in an opposite direction. As a result, the unnecessary slackening of the magnetic tape is surely prevented.
Patent JP-H01134973-A (JP)
Title: Manufacture of vertical semiconductor device
Inventor: INOUE YASUAKI
IPC: H01L29/78
Filed: 1987-11-19
Abstract: PURPOSE:To produce a vertical transistor wherein one gate controls a plurality of channels by a method wherein one gate is surrounded by a plurality of channels so arranged as to cover the whole wafer surface. CONSTITUTION:Four transistors, each consisting of a drain 3, a source 4, and a channel 5, are arranged, facing the four corners of a quadrangle gate electrode 6, respectively. Such a configuration allows one and the same gate electrode 6 to govern a plurality of transistor channels simultaneously. This ensures an efficient use of a given area and enables the production of a plurality of FETs capable of operating at one and the same gate voltage.
Patent JP-H05136115-A (JP)
Title: Method for preserving semiconductor substrate
Inventor: YAJIMA MIKIKO
IPC: H01L21/304
Filed: 1991-11-11
Abstract: PURPOSE:To eliminate the contamination of semiconductor wafers due to a molecular organic matter by maintaining the wafers in the atmosphere of an organic solvent so that the surfaces of the wafers can hold hydrophilic properties until the wafers are fed to the succeeding process after the wafers are subjected to a substrate washing process. CONSTITUTION:This method for preserving semiconductor substrates is used for maintaining semiconductor wafers in the atmosphere of an organic solvent until the wafers are fed to the succeeding manufacturing process after the wafers are subjected to a substrate washing process. Namely, by immediately placing the semiconductor wafers which have been treated with H2SO4, H2O2 and HNO3 and washed with water in the atmosphere of an organic solvent or the vapor of the organic solvent, contamination of the wafers by the adhesion of a molecular organic matter is eliminated. Therefore, since the water repellency of the wafers caused by a molecular organic contaminant can be eliminated, the occurrence of hazes, water marks, etc., caused by the water repellency can be eliminated and the manufacturing yield of semiconductor elements can be improved.
Patent JP-H08140275-A (JP)
Title: Portable electronic device
Inventor: FUJIKI SHIRO
IPC: H02J7/00
Filed: 1994-11-04
Abstract: PURPOSE: To find the exchange period of a battery by identifying the kind of the power source connected to the body of electronic device, and displaying the contents of the discrimination by a display at the same time. CONSTITUTION: Information by kinds on a power source 1 is stored in advance in the ROM 5 of CPU 3. And when the body 2 of electronic device and the power source 1 are connected with each other, the controller 4 of the CPU 3 discriminates the standard. Furthermore, a display 6 displays the information on the identification.
Patent JP-H07129639-A (JP)
Title: Net list dividing device
Inventor: TANISHITA HISATO
IPC: G06F17/50
Filed: 1993-10-29
Abstract: PURPOSE:To divide the entire net list relating to a designed digital device into appropriate sizes by a designer through an interactive method. CONSTITUTION:A block diagram display control means 61 displays the block diagram of the digital device constituted of the images of symbols, nets and input/output terminals at a CRT 64 based on the entire net list 51 relating to the designed digital device. A group selection control means 62 supports an operation in which a user divides the block diagram displayed at the CRT 64 by using a mouse 66 and an extraction means 63 extracts net lists 52-1 to 52-n belonging to the respective groups divided and obtained under the support by the group selection control means 62 from the entire net list 51.
Patent JP-S62154671-A (JP)
Title: Inp solar cell
Inventor: ITO YOSHIO
IPC: H01L31/06
Filed: 1985-12-26
Abstract: PURPOSE:To obtain a solar cell which assures high efficiency and resistivity to radioactive rays by using an n-type InP having excellent resistivity to radio active rays as a substrate layer and forming an i-layer between the p<+> layer and n-layer. CONSTITUTION:A solar cell is composed of an anti-reflection film 1, a front surface electrode 1, a p<+> layer 3, i layer 4, an n layer 5, and a rear surface electrode 6. Since minority carrier generated by optical pumping is moved by an internal field generated by such p<+>-i-n structure, the minority carrier diffusion length is virtually increased, providing expectation of improvement of efficiency. Namely, it is characterized in that the i-layer is provided between the p<+> layer and n layer, the collecting efficiency of the optically pumped is enhanced by the internal field in the i-layer thereby realizing high efficiency, an n type InP having excellent resistivity to radioactive rays is used as the substrate layer and radioactive ray resistivity is enhanced by optimization of the thickness of i-layer.
Patent JP-2001117753-A (JP)
Title: Fifo control circuit
Inventor: HAGIWARA MISAO
IPC: G06F5/06
Filed: 1999-10-15
Abstract: PROBLEM TO BE SOLVED: To quickly access an FIFO memory without mutually synchronizing writing side and reading side systems for the FIFO memory. SOLUTION: Each of access control units 6 to 16 stores token signals in a state shifting token signals one by one to the rear in each input of a write signal WRB, cancels token signals one by one from the rear in each input of a read signal RDB and maintains the state shifting the token signals to the rear. When the access control unit 10 stores no token signal and the access control unit 12 stores token signals, data of three words are stored in a memory 4, a threshold signal STS-THR is outputted from a 1st logic circuit 42 and reported to a data writing side system not shown in the diagram.
Patent JP-H07129802-A (JP)
Title: Data setting registration device for time recorder
Inventor: HORIIKE MASAKI
IPC: G07C1/06
Filed: 1993-10-29
Abstract: PURPOSE:To specify a setting item to be registered in the memory of time recorder only by pushing at attending and leaving operation button provided to the recorder and to take a general view of the names of various setting items in a list. CONSTITUTION:This device consists of a time recorder 1 which is provided with plural operation buttons 3-8 regarding working time conditions in a lateral array in front of a card insertion slot 2 and a setting card T on which the names of various setting items or the names of actual values regarding the setting items are stated in a lateral array corresponding to the operation buttons 3-8, and, when this setting card T is inserted into the card insertion slot 2 and the names in the lateral array are positioned right above the card insertion slot 2, the meanings of the respective operation buttons 3-8 are replaced with the contents of the respective names.
Patent JP-H03154096-A (JP)
Title: Method and device for generating pattern
Inventor: KIMITA TSUNEAKI
IPC: H04N1/40
Filed: 1989-11-13
Abstract: PURPOSE:To display a font which can enlarge and reduce a vector font, etc., by a grey scale without increasing a memory by generating the corresponding multilevel data in accordance with density in a prescribed area of a bit map. CONSTITUTION:In accordance with an instruction from an input means 1, a generating device 2 generates a binary bit map font from vector data from a storage device 3, and stores it in a RAM 4. In a generating device 5, based on bit map data in the RAM 4, a grey scale font is generated. In a dividing part 6, the bit map data is divided in accordance with a level of a grey scale, density of each divided area is decided by a detecting part 7, and the detected density is sent to a data output part 8.
Patent JP-H03156286-A (JP)
Title: Processing method for dust and waste heat generating from ore discharge section of sintering machine
Inventor: NAKAJIMA RYUICHI
IPC: F27B21/12
Filed: 1989-11-13
Abstract: PURPOSE:To inexpensively process dust of sintered ore and to efficiently recover waste heat by collecting the dust by a sintered layer by sucking through the layer charged in a pallet by an air box provided under the pallet, and recovering the waste heat. CONSTITUTION:Sintered ore charged and baked in a pallet 1 is sequentially dropped from the downstream end of the pallet 1, pulverized by a crasher 7, and dust of the ore pulverized in a hood 11 is generated. The air in the hood 11 is sucked to a main duct 12 through a sintered layer charged in the pallet 1 by an air box 2 provided under the pallet 1 in the hood 11, and the dust pulverized by the crasher 7 in the hood 11 is sucked together with the air through the layer by the box 2. The dust is collected by the layer upon passing of the layer. The remaining dust which is not collected is removed through the duct 12. The waste heat of an ore discharger is sucked together with the air through the layer by the box 2, and recovered through the duct 12.
Patent JP-2001116629-A (JP)
Title: Automatic extraction method for measured temperature data and device therefor
Inventor: KODAMA YOSHITO
IPC: G01K13/12
Filed: 1999-10-18
Abstract: PROBLEM TO BE SOLVED: To provide an automatic extraction method for measured temperature data and device therefor capable of automatically extracting only data to be adopted from sequentially measured data and transferring the extracted data to a printer or data processor when measuring a temperature of an individual article and statistically processing the measured data. SOLUTION: This device detects insertion of a temperature sensor 1s into a temperature measurement target 5 from a change ΔT of a detection temperature Tn when inserting the temperature sensor 1s into the temperature measurement target 5 to measure a typical temperature Tmax inside the target 5, manually or automatically samples the detection temperature Tn to extract the adoption data Tmax from the sampling data Ts, decides the adoption data Tmax when detecting departure of the temperature sensor 1s from the temperature measurement target 5 according to the change ΔT of the detection temperature Tn, and outputs the adoption data Tmax to a printer 7 or a data processor 8.
Patent JP-S63146817-A (JP)
Title: Antifungal agent for external use
Inventor: FURUKAWA MIKIO
IPC: A61P31/04
Filed: 1986-12-11
Abstract: PURPOSE:To obtain an antifungal agent for external use, containing griseofulvin having excellent antifungal action and griseofulvin dissolvent, e.g. benzyl nicotinate, etc., as an active ingredient and having high percutaneous absorbability without side effects. CONSTITUTION:An antifungal agent for external use obtained by containing griseofulvin expressed by the formula and one or two or more griseofulvin dissolvents selected from the group consisting of benzyl nicotinate, ethyl nicotinate, menthol, camphor, methyl salicylate, glycol salicylate, crotamiton, diphenhydramine and benzyl alcohol as an active ingredient. The griseofulvin is preferably blended in an amount of 0.01-20wt% and the minimum amount required of the griseofulvin dissolvents is 5-30pts.wt. based on 1pts.wt. griseofulvin. An absorption adjuvant, e.g. dimethyl sulfoxide, etc., can be contained in addition to the above-mentioned active ingredient.
Patent JP-H05133603-A (JP)
Title: Water heater
Inventor: NIIMURA NORIO
IPC: F24H1/10
Filed: 1991-11-12
Abstract: PURPOSE:To keep users from dangers such as scald, etc., even in the case in which hot water supply is made, after supplying hot water at temperature exceeding safe, specified temperature, at the same temperature by forgetting that the high temperature hot water supply is made previously and mistaking it for hot water supply at specified temperature. CONSTITUTION:A control circuit 3 controls to open a water valve 9 and gas solenoid valve 6 by the valve opening signal from a kitchen shower 1. And, a heat exchanger 7 is heated by a burner 4 and hot water is supplied from the kitchen shower 1. The control circuit 3 sets so as to keep always the temperature of supply hot water at safe, specified temperature. Only when a temperature setting device 11 sets temperature that is higher than specified temperature, the control circuit 3 controls heating so as to supply hot water by high temperature setting by the signal of a temperature sensor S, but when the high temperature hot water supply is over and signal to close the valves is received, the high temperature setting is removed and the temperature returns to the setting of specified temperature.
Patent JP-S62152099-A (JP)
Inventor: HASHIMOTO KOICHI
IPC: G07D5/02
Filed: 1985-12-25
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H07146301-A (JP)
Title: Integrated spm sensor
Inventor: KAMIYA NOBUTAKA
IPC: H01L21/66
Filed: 1993-11-25
Abstract: PURPOSE:To provide an integrated SPM sensor having a small area around the tip of its cantilever. CONSTITUTION:A cantilever section 124 has a short strip-like body with a triangular chip and is constituted by laminating a lever structure body section 114 composed of a silicon layer, piezoresistance section 116, insulating layer 118, and electrode section 120. The layer 118 covers the entire body of the section 116 except part of the section 116 around a probe section 119 and the side face of the front end of the section 114. The electrode section 120 covers the entire surface of the layer 118 and probe section 119 and is electrically connected with the section 116 through a contact section 123. The cantilever section 124 is fixed to a supporting section formed of a silicon substrate 110 provided with insulating layers 112 and 111 on its upper and lower surfaces, respectively.
Patent JP-2001116507-A (JP)
Title: Angle detecting apparatus
Inventor: NAKAMURA MORITOSHI
IPC: B60K26/02
Filed: 1999-10-18
Abstract: PROBLEM TO BE SOLVED: To provide an angle detecting apparatus at a low cost in which posi tion adjusting work in a stage of fixing is easy, a rotation angle of a lever to be detected like a pedal arm can be precisely detected, and unit constitution is unnecessary. SOLUTION: This detecting apparatus is equipped with a support shaft 4 fixed to a frame 3, a lever 2 to be detected which is pivotally fixed to the support shaft 4, an angle sensor 5 which has a pivoting part 5a engaged with the lever 2 and driven pivotally and can detect a rotating angle of the lever 2, a bracket 7 which mounts the sensor 5 and is fixed to the support shaft 4 pivotally, and an adjusting means of screws 8, 9, etc., capable of changing the fixing attitude of the bracket 7 to the support shaft 4. The bracket 7 set in a specified fixing attitude by the adjusting means is fixed to the frame 3. Thereby the interval between the angle sensor 5 mounted on the bracket 7 and the support shaft 4 can be previously regulated with high precision.  By adjusting the fixing attitude of the bracket 7 to the support shaft 4, the pivoting part 5a of the angle sensor 5 can be arranged at a desired initial position.
Patent JP-H06151724-A (JP)
Title: Semiconductor device and manufacture thereof
Inventor: TAKECHI EIJI
IPC: H01L27/06
Filed: 1992-11-05
Abstract: PURPOSE:To reduce the number of masks in the process of manufacture of a semiconductor device where a high breakdown strength transistor and a low breakdown strength transistor are mounted, and to improve its latch-up resisting property. CONSTITUTION:The first wells 21 and 22 and the second well 23 are formed on a semiconductor substrate 1, a part of the second well 23 is overlapped on the first well 21, a low breakdown strength transistor is formed on the regions 22 and 23 of the first and the second wells, and a high breakdown strength transistor is formed on the regions 24 and 25 other than the above- mentioned regions.
Patent JP-H05137113-A (JP)
Title: Digital vtr
Inventor: YANAGIHARA HISAFUMI
IPC: H04N21/434
Filed: 1991-11-12
Abstract: PURPOSE:To prevent deterioration of a picture quality in the case an HD signal of high definition is divided and synthesized. CONSTITUTION:A low frequency signal of an HD signal from a thinning-out circuit 5 is supplied to a recording head 12 through, for instance, a discrete cosine converting circuit 7, a quantizing circuit 8, a variable length encoding circuit 9, and an encoder circuit 11. A signal from this quantizing circuit 8 is supplied to a subtracting circuit 18 through a reverse quantizing circuit 17, and also, a signal from the converting circuit 7 is supplied to the subtracting circuit 18. In such a way, a difference signal of a signal obtained by restoring a compressed signal, and the original signal is formed. This difference signal is supplied to an adding circuit 16 through a run-length encoding circuit 20 and a variable length encoding circuit 21. Also, a high frequency signal of the HD signal from a thinning-out circuit 6 is supplied to the adding circuit 16 through a run-length encoding circuit 14 and a variable length encoding circuit 15, and a signal from this adding circuit 16 is supplied to a recording head 23 through an encoder circuit 22.