Patent GB-1030428-A (GB)
Title: An electronic computer for use in laying out cloth
Inventor: PAVLENKO JURY STEPANOVICH
IPC: G06Q10/00
Filed: 1963-06-21
Abstract: 1,030,428. Electronic computers. KIEVSKI GOSUDARSTVENNY UNIVERSITET T. G. SHEVCHENKO. June 21, 1963, No. 24856/63. Heading G4A. A computer designed to solve diophantine equations is used to calculate the numbers of pieces of cloth, of each of a number of given strip lengths, which should be cut from a roll of given length in order to produce the least remnant, i.e. the least waste. In order to find integers A1, A2, A3 and LR (where LR=length of the remanent) which satisfy the equation where L is the length of the roll and 11, 12, 13 are the given strip lengths and LR is the smallest integer to satisfy this relation, LR is initially given a value zero and all possible values of A1, A2, A3 are tried, and if no solution is found the cycle is repeated with the value of LR increased by one at each stage. As described, L, 11, 12, 13 are entered into storage registers through a push-button keyboard and a start button is depressed causing clock pulses V (Fig. 2, not shown) to be generated. The first pulse is gated at 29 and emerges at A to gate the length L to a sumrnator; this pulse also trips a trigger 19 which closes the gate 29 and opens a gate 30 which passes the second pulse, which is in turn gated at 31 to emerge at b. The pulse b trips a trigger 20 and also gates the value of LR (zero for the first cycle) to the summator. The tripped trigger 20 closes the gate 31 and enables one input of each of three AND gates 21, 22, 23. A pair of triggers 17, 18 are initially set so they enable the other two inputs of the AND gate 21 which thus responds to open a gate 32. The third clock pulse V passes through this gate and through a normally open gate 33 to a counter 12 and also to a line 34 where it gates the value 11 to the summator. The fourth, fifth &c. clock pulses V are treated in the same way and the summator (not shown) sums the 11's to form a product A1 11 until this exceeds the value L. When this happens a signal S<1> is generated and this closes the gate 33 and causes the next clock pulse to be gated at 24 to an output 36, passing to an external circuit (Fig. 3, not shown) and producing a signal 39 which combines with a clock pulse V and the signal S<1> to open a gate 40 which trips the trigger 17 so that the gate 21 closes and the gate 22 opens. The next pulse V passes through the now open gates 41, 42 to be recorded on the counter 13 and also to pass out on a line 43 to gate the value 12 to the summator. The counter 13 is set so as to be full when it contains a single pulse at this stage, and thus it produces an output which trips the trigger 17 back to its original state; it also steps a control counter 15 which is in turn controlled via a delay line 37 so that the counter 13 is set to receive two pulses during the next cycle. Thus, in consecutive cycles, first the summator produces the product A1 I1; then it produces the product A1 11+12 up to A1 11+A2 12. This continues until a sufficiently large value of A2 is tried so that A2 12 is greater than L; at this stage signal S<1> is again produced and gate 42 closes. The next clock pulse V is then gated at 25 to produce a signal 44 which is passed to the external circuit (Fig. 3, not shown). A further signal 45 is produced which acts in the same way as the signal 39 to include the final stage 14, thus the summator forms all sums Al 12+ A2 12+A3 13. If no solution is found the whole of the above is repeated with LR= 1, 2 &c.