baber/WOPTO huggingface dataset:
Patent TW-472295-B (TW)
Title: Foreign matter removing method, film forming method, semiconductor device and film forming device
Inventor: MORITA KIYOYUKI
IPC: C23C16/448
Filed: 2000-01-27
Granted: 2002-01-11
Abstract: The present invention provides a method for removing foreign matters in the CVD film under low temperature, and a film forming method to form high quality of oxide layer, nitride layer and nitride oxide layer on the surface of the processing object. The method includes the following steps: placing the silicon liner 11 into the container 17; supplying metal organic composite and carbon dioxide in super-critical state into the container 17; forming BST layer 14 on the platinum layer 13; and, removing the carbon-containing composite generated during forming the BST layer 14. The method employs high solubility and low viscosity properties of carbon dioxide in super-critical state to effectively remove the carbon-containing composite in the BST layer 14 and using the water in super-critical state or sub-critical stage for oxidation and nitridation processing at low temperature to form the oxide layer and the nitride layer.
Patent TW-548079-B (TW)
Title: A mixed herbicidal composition for use in paddy fields
Inventor: GOTO TOSHIO
IPC: A01N47/38
Filed: 2000-02-01
Granted: 2003-08-21
Abstract: The instant invention relates to a mixed composition comprising as herbicidal active components (a) 1 part by weight of 1-(2-chlorophenyl)-4-(N-cyclohexyl-N-ethylcarbamoyl)-5(4H)-tetrazolinone and (b) 0.125-0.5 parts by weight of methyl alpha-(4,6-dimethoxypyrimidin-2-yl-carbamoylsulphamoyl-o-toluate or 0.06-0.2 parts by weight of ethyl 5-(4,6-dimethoxypyrimidin-2-ylcarbamoylsulphamoyl)-1-methylpyrazole-4-carboxylate. The invention further relates to the use of this composition as a selective herbicidal mixture for combating weeds in paddy fields.
Patent TW-494391-B (TW)
Title: Optical information recording and reproducing apparatus
Inventor: AKAGI NORITAKA
IPC: G11B7/095
Filed: 2000-02-25
Granted: 2002-07-11
Abstract: In order to correct an offset and a variation of the amplitude of a tracking error signal caused by a positional displacement of an object lens from the center of an optical pickup, an offset amount and an amplitude value of the tracking error signal with respect to the displacement value of the object lens from the canter of the optical pickup are investigated in advance, and the displacement value of the object lens is estimated by an object lens displacement observer on the basis of a tracking correction signal. An offset detection section and an amplitude detection section detect the offset amount and the amplitude value of the tracking error signal, respectively, and on the basis of the offset amount and the amplitude value investigated in advance, the tracking error signal is corrected by an offset correction circuit and an amplitude correction circuit so that the offset amount and the amplitude value of the tracking error signal become equal to those when displacement value of the object lens is zero. Furthermore, the offset of a tilt error signal depending on a moving direction of the optical pickup is detected and recorded in advance, and when a rotation direction detecting section detects the moving direction of the optical pickup, the tilt error signal is corrected based on the recorded offset.
Patent TW-455960-B (TW)
Title: Semiconductor device and mounting structure of a semiconductor device
Inventor: IMAI KAZUNARI
IPC: H05K3/34
Filed: 2000-03-22
Granted: 2001-09-21
Abstract: A mounting structure is provided for mounting a semiconductor device having an electrode on a mounting substrate having a conductive pad. A metallic bump electrically connects the electrode of the semiconductor device to the conductive pad. A first eutectic solder is used for soldering between the metallic bump and the electrode of the semiconductor device. A second eutectic solder is used for soldering between the metallic bump and the conductive pad of the substrate. A melting point of the metallic bump is higher than those of the eutectic solders and a resistance to fatigue of the first eutectic solder is higher than that of the second eutectic solder. The first eutectic solder is composed of a Sn component of 63% by mass, a Pb component of 34.3% by mass, an In component of 1% by mass, a Sb component of 0.7% by mass, and an Ag component of 1% by mass.
Patent TW-447165-B (TW)
Title: Nitrite additives for nonaqueous electrolyte rechargeable electrochemical cells
Inventor: GAN HONG
IPC: H01M/
Filed: 2000-04-17
Granted: 2001-07-21
Abstract: A lithium ion electrochemical cell having high charge/discharge capacity, long cycle life and exhibiting a reduced first cycle irreversible capacity, is described. The stated benefits are realized by the addition of at least one nitrite additive to an electrolyte comprising an alkali metal salt dissolved in a solvent mixture that includes ethylene carbonate, dimethyl carbonate, ethylmethyl carbonate and diethyl carbonate. The preferred additive is an alkyl nitrite compound.
Patent TW-441031-B (TW)
Title: Input/output control circuit
Inventor: LI KUEN-HAN
IPC: H01L21/8238
Filed: 2000-04-20
Granted: 2001-06-16
Abstract: An input/output control circuit having tolerance of different input voltages is disclosed, the present invention can still make the circuit operate normally even when different operating voltages are inputted, e.g. 2.5V, 3.3V and 5V. Also, when the input voltage is 5V, it can turn off the PMOS transistor in n-well at the same time by using a gate control circuit and a n-well control circuit, so that the function of allowing 5V input can be achieved.
Patent TW-520630-B (TW)
Title: A printed circuit board and a method of manufacturing therefor
Inventor: PARK KEON-YANG
IPC: H05K3/46
Filed: 2000-05-02
Granted: 2003-02-11
Abstract: A printed circuit board and a manufacturing method therefor are disclosed, in which the manufacturing process is simple, the productivity is improved, and the manufacturing cost is curtailed. The method for manufacturing the printed circuit board includes the following steps. A first insulating layer is formed with a first metal layer formed on one face thereof, and then the first metal layer is etched to form a circuit. A second insulating layer is stacked on one face of the first insulating layer, with a second metal layer formed on the second insulating layer. The second metal layer is etched by applying a photo lithography process to form a circuit and to form at least a first open region. A third insulating layer is stacked on the second insulating layer, with a third metal layer formed on the third insulating layer. The third metal layer is etched by applying a photo lithography process to form a circuit and to form at least a second open region above the first open region. The first open region of the second insulating layer and the second open region of the third insulating layer are etched by using a CO2 laser to form a via hole. The via hole is coated with a metal to connect the circuit of the second insulating layer and the circuit of the third insulating layer together.
Patent TW-469393-B (TW)
Title: Method and system for name analysis
Inventor: CHEN CHIH-MIN
IPC: G06Q50/10
Filed: 2000-05-17
Granted: 2001-12-21
Abstract: A method for name analysis includes an analysis procedure, a screening procedure, a user requirement input procedure and an output procedure. The analysis procedure targets at a name to analyze; the screening procedure stores the name satisfying a pre-defined conditions into a name database; the user requirement input procedure accepts at least one condition of the user input; the output procedure targets at the user input conditions to find out the desirable names satisfying the condition from the name database, and use a pre-defined way to output to the user as naming references. The invention also discloses a name analysis system based on this method.
Patent TW-459139-B (TW)
Title: IC cooling system
Inventor: TABATA FUMIO
IPC: H01L21/66
Filed: 2000-05-26
Granted: 2001-10-11
Abstract: An integrated circuit cooling system capable of reducing the number of components for radiating heat, of controlling the generation of stress or bending so as to efficiently cooling the integrated circuit. The integrated circuit cooling system comprises an integrated circuit, a heat exchanger support pole, a fixed spacer, a spring, a cooling block, cooling pipes, and screws. A heat conductive material is applied onto the upper surface of a package portion of the integrated circuit, and another heat conductive material is applied onto an insertion hole for the heat exchanger support pole provided in the cooling block at the portion where it contacts the heat exchanger support pole. The cooling block is fixed to a printed board by the fixed spacer. The spring is attached to the cooling block by two screws and screw holes provided on the upper surface of the cooling block and the heat exchanger support pole is fixed to the cooling block so as to press the upper surface of the heat exchanger support pole downward by a resilience force thereof.
Patent TW-476628-B (TW)
Title: Hook fastener member with less damage to loops
Inventor: HIGASHINAKA YUKITOSHI
IPC: A44B18/00
Filed: 2000-07-29
Granted: 2002-02-21
Abstract: A flexible hook fastener member having a hook density of 80 to 200 per cm<SP>2</SP> and causing little damage to cooperating loop fastening elements. The loops for forming hook fastening elements are produced by thin monofilaments having a fineness of 100 to 200 deniers. The monofilament for forming the hook fastening elements are in reverse phase relation to the adjacent ground warps with respect to the ground wefts.
Patent TW-508515-B (TW)
Title: A system for event registration management
Inventor: FOO ROSALIND
IPC: G07B15/00
Filed: 2000-09-20
Granted: 2002-11-01
Abstract: A network-enabled system for providing event registration management services to event organizers and attendees is provided. The system comprises a network server for processing documents retrievable and viewable via a network by event organizers and attendees for providing information thereto and retrieving information therefrom, and an application server for generating the documents and providing the control logic for providing information to and retrieving information from the event organizers and attendees. The system also comprises a database server for storing and managing the information as data in a database, the data comprising data regarding details of an event including time and venue thereof, and registration fee therefor, the event being organized by an event organizer and the details for informing an event attendee regarding the event, data regarding information for preparing registration documents for registering the event attendee for the event, and data regarding registration information in response to the registration documents, the registration information for registering the event attendee and paying the registration fee. The application server uses the data regarding the preparation information for dynamically generating the documents by which the event organizer retrieves the registration information from the event attendee.
Patent TW-584589-B (TW)
Title: Water flow guide for pelletizer
Inventor: MARTIN JOHN W
IPC: B29C48/92
Filed: 2000-11-07
Granted: 2004-04-21
Abstract: A water flow guide stationarily mounted in the water box of an underwater pelletizer to selectively direct the pressurized water flowing through the water box in order to more efficiently cool and rigidify the extruded polymer strands and enable the rotary cutter blades to more effectively shear the strands into pellets and to convey the sheared pellets away from the die face and rotary cutter blades of the pelletizer to the water box outlet. The water flow guide provides an accurately guided pressurized water flow which enables pelletization of polymers of various diameters and a wide range of specific gravity and rheological characteristics.
Patent TW-480330-B (TW)
Title: Sensor for the detection of a predetermined filling of a container
Inventor: MANNHART EUGEN DR
IPC: G01F23/26
Filed: 2000-11-01
Granted: 2002-03-21
Abstract: A sensor for the detection of a predetermined level of a container has three capacitive electrodes (5-7) which form a first and a second capacitor (8, 9). The three capacitive electrodes (5-7) are arranged in three planes running parallel to each other. A drill hole (13) running through the three capacitive electrodes (5-7) accepts the container. The first capacitor (8) is preferably part of a first RC element and the second capacitor (9) part of a second RC element whereby the two RC elements have differing time constants. Measurement of the relative change of the two time constants enables operation of the sensor without any adjustment. The sensor is used for example with the assembly of a semiconductor chips in order to indicate that a syringe (1) filled with adhesive (2) is almost empty.
Patent TW-506210-B (TW)
Title: Image data compression method and demodulation method
Inventor: KOJIMA SHOUICHI
IPC: H04N1/41
Filed: 2000-12-19
Granted: 2002-10-11
Abstract: The image data compression method and the demodulation method are disclosed in which the degradation of the image quality caused by compressing and demodulating can be suppressed. The image data compression method and the demodulation method with large compressed rate also disclosed by the present invention. In the image data compression method and the demodulation method of the present invention, extracting the image elements contained in the digital image which read from the paper page (S02), data compressing each extracted image element (51 to 53) by using the compression method which corresponding to the image element (S03 to S05), and storing and receiving each image element data (54 to 56).
Patent TW-473964-B (TW)
Title: Semiconductor package structure with embedded heat dissipation bump
Inventor: HUANG CHUNG-PING
IPC: H01L23/36
Filed: 2001-02-08
Granted: 2002-01-21
Abstract: A semiconductor package structure with embedded heat dissipation bump is disclosed, which can provide a good heat dissipation efficiency and make the package size lighter and smaller. The leadframe of the semiconductor package structure comprises an outer lead, an inner lead and a ladder-type soldering finger. The assembly process includes: placing the chip under the inner leads and sticking it on the solder fingers, electrically connecting the chip to the solder fingers via solder line, sticking a heat dissipation bump on the front face of the inner lead by heat conductive glue that is electrically insulated, and proceeding a package gluing step to pack the chip, inner leads, solder lines and heat dissipation bumps. This package structure can dissipate the heat that is generated by the chip operation to the surrounding environment via the heat dissipation bump. Besides, because the heat dissipation bump is embedded, instead of externally connected, the package can be lighter and smaller.
Patent TW-527614-B (TW)
Title: Spacer assembly for flat panel display, method for manufacturing spacer assembly, method for manufacturing flat panel display, flat panel display and metal mold for use in manufacturing spacer assembly
Inventor: TAKENAKA SHIGEO
IPC: H01J31/12
Filed: 2001-03-23
Granted: 2003-04-11
Abstract: The spacer assembly of the present invention has first and second spacers standing on first and second surfaces of a plate-like grid to be integral with them. First and second molds each with a plurality of through holes are arranged on the first and second surfaces of the grid to be in tight contact with them. After that, the through holes of the molds are filled with a glass paste containing an ultraviolet-curing binder, and the glass paste is cured by irradiation with ultraviolet rays. Furthermore, while the molds are held in a tight contact state, the glass paste is sintered at a predetermined temperature. Thus, the first and second spacers are integrally formed on the grid surfaces. The first spacer has an aspect ratio of 2.5 to 3.
Patent TW-504699-B (TW)
Title: Semiconductor memory device
Inventor: HOSODA MASAHIRO
IPC: G11C29/12
Filed: 2001-04-04
Granted: 2002-10-01
Abstract: A semiconductor memory device includes an inner circuit. The inner circuit includes a command user interface, a logical circuit and a pad. Based upon an externally input fixing command, the command user interface outputs signals A and B with H or L level. Upon receipt of the signal A of H level and the signal B of L level, the logical circuit outputs a fixed logical signal of H level independent of the signal received from the pad, and upon receipt of the signal A of L level and the signal B of H level, outputs a fixed logical signal of L level independent of the signal received from the pad. Thus, it becomes possible to carry out a high-quality testing operation even when the number of the test pins of a test device is smaller than the number of address pins or data pins of a semiconductor memory device.
Patent TW-475887-B (TW)
Title: Leg portions supporting wear
Inventor: FUJII TAKAKO
IPC: A41D1/08
Filed: 2001-04-16
Granted: 2002-02-11
Abstract: A leg portions supporting wear which has flexibility and thigh portions worn tightly to the body and supporting leg portion, and which has a stretchable portion (A) comparatively strong in tightening force, wherein the stretchable portion 2 substantially covers collateral ligaments 3 on the inner sides of knee joints of the human body, has a length at least 1/4 that of a thigh portion at portions above the knee joints, and is provided along at least one type of muscles selected from a muscle group consisting of sartorius muscles 6, semi-tendon-like muscles 21, semi-membranous muscles and thin muscles 23. The leg portions supporting wear efficiently protects knees, stably retains knee joints, does not impair a freedom of motion of knee joints, is comfortable to wear, prevents or reduces knee pains, and is effective for preventing damages to inner-side collateral ligaments to be caused by sports.
Patent TW-512284-B (TW)
Title: Graphic processing method using depth auxiliary and computer readable record medium for storing programs
Inventor: LIN TSUNG-WEI
IPC: G06T15/40
Filed: 2001-05-24
Granted: 2002-12-01
Abstract: Provided is a graphic processing method using depth auxiliary executed in the computer system with a display device, which is especially for dealing with situations of inter-overlapping among graphic or image objects. For graphic objects, it is able to separately allocate the corresponding depth parameter to pixels inside the graphic object through 3D transformation procedure. Image objects are allocated a fixed depth parameter. It follows depth parameter allocated to display each object on the display device in order when rendering the above-mentioned graphic and image objects. It follows corresponding depth parameter to each pixel to select a visible object in each object among overlapping areas of objects. At last, it deals with intersection surfaces of overlapping areas among the above-mentioned objects to make them even and smooth.
Patent TW-588225-B (TW)
Title: Method of calibration of a lithographic apparatus, mask for use in calibration of lithographic apparatus, lithographic apparatus, device manufacturing method, device manufactured thereby
Inventor: BASELMANS JOHANNES JACOBUS MAT
IPC: G03F7/20
Filed: 2001-06-06
Granted: 2004-05-21
Abstract: An alignment marker for use in calibration of a lithographic projection apparatus has focus- and dose-sensitive parts, each of which comprises an area having a plurality of dots against a contrasting background forming part of a periodic line structure. A method of calibrating a lithographic projection apparatus comprising: a radiation system for providing a projection beam of radiation; a support structure for supporting patterning means, the patterning means serving to pattern the projection beam according to a desired pattern; a substrate table for holding a substrate; a projection system for imaging the patterned beam onto a target portion of the substrate, the method comprising, the step of: imaging at least one alignment marker provided in said patterning means onto a radiation-sensitive layer on a substrate held by said substrate table, characterized in that: said alignment marker(s) comprise(s) a focus-sensitive part and a dose-sensitive part, said focus- and dose-sensitive parts each having a plurality of dots on a contrasting background, said pluralities of dots being arranged asymmetrically.
Patent TW-541428-B (TW)
Title: Electrical characteristic detection method of silicon based liquid crystal panel
Inventor: BU LIN-KAI
IPC: G01R31/26
Filed: 2001-06-14
Granted: 2003-07-11
Abstract: There is provided an electrical characteristic detection method of silicon based liquid crystal panel, which comprises: first, enabling a scan line, detecting the resistance between a data line and the adjacent data line, and displaying that the two adjacent pixels on the scan line are short-circuited when the measured result is a low resistance smaller than a predefined resistance; in addition, enabling a scan line and inputting a signal from a data line; next, enabling another adjacent scan line and inputting another signal from the data line; then, inputting the original signal from the data line; and finally, enabling the scan line, wherein two adjacent pixels on the same data line are short-circuited if there is a voltage drift on the data line.
Patent TW-501275-B (TW)
Title: Method for making SOI MOSFETS
Inventor: OH JEONG-HEE
IPC: H01L29/786
Filed: 2001-06-15
Granted: 2002-09-01
Abstract: Disclosed is a method for making an SOI MOSFET, which is capable of improving threshold voltage variations and a parasitic bipolar effect generated in the formation of fully depleted (FD) SOI semiconductor integrated circuits using a recess channel. The method involves the steps of forming a buried oxide film and an active silicon film over a silicon-on-insulator substrate, forming a channel at a recess channel, forming dummy spacers at opposite side walls of the etched active silicon film, forming a gate between the dummy spacers, forming a photoresist film on the gate and the active silicon film, forming lightly doped drain regions, removing the dummy spacers, forming lightly doped ion regions, respectively, forming spacers at opposite side walls of the recess channel region, respectively, removing the photoresist film, forming a source region and a drain region, forming source/drain electrodes and a gate electrode on the resultant structure.
Patent TW-556323-B (TW)
Title: Recess type gate and its formation method of flash memory
Inventor: TZENG HUNG-HUEI
IPC: H01L21/8246
Filed: 2001-07-27
Granted: 2003-10-01
Abstract: A recess type gate and its formation method of flash memory are provided. The structure at least consists of a substrate on which the trenched are already formed, a first dielectric layer that is formed on the substrate. A protruding part is formed in the said trenches and protrudes from the substrate surface. The recesses are formed among the protruding parts. A first conduction layer is formed on the first dielectric layer and in the recess to be a floating gate. A second dielectric layer is formed on the first conduction layer and then a second conduction layer is formed on the second conduction layer to be a control gate.
Patent TW-I249577-B (TW)
Title: Method for amplifying nucleic acid sequence
Inventor: SAGAWA HIROAKI
IPC: C12Q1/68
Filed: 2001-08-23
Granted: 2006-02-21
Abstract: This invention provides a convenient and effective method for amplifying a nucleic acid sequence characterized by effecting a DNA synthesis reaction in the presence of chimeric oligonucleotide primers; a method for supplying a large amount of DNA amplification fragments; an effective method for amplifying a nucleic acid sequence by combining the above method with another nucleic acid sequence amplification method; a method for detecting a nucleic acid sequence for detecting or quantitating a microorganism such as a virus, a bacterium, a fungus or a yeast; and a method for detecting a DNA amplification fragment obtained by the above method in situ.