Patent GB-741420-A (GB)
Title: Improvements in or relating to electric adding and subtracting devices
IPC: G06F7/504
Filed: 1952-04-17
Abstract: 741,420. Digital electric calculating-apparatus. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. April 17, 1952 [April 17, 1951], No. 9744/52. Class 106 (1). In an electric device for adding and/or subtracting binary numbers represented by seriesmode pulse trains A, B, the pulse trains are applied to input terminals 5, 6 of a single " half-adder " (i.e. a circuit having an anticoincidence or " ou " circuit 3, and a coincidence or " et " add-carry circuit 4 and/or a subtractcarry circuit 32), and the " ou " output pulses at 7 and " et " or subtract-carry output pulses at 8 or 21 are fed back through delay means 15 and 19, 20 respectively to the input terminals where they arrive out of phase with the input trains. In the adding and subtracting device shown in Fig. 1, the trains A, B are applied simultaneously through coupling and re-shaping circuits 11, 13 to terminals 5, 6 to produce a partial result train C, Fig. 2, at terminal 7 which is delayed by #/2 in delay line 15 (where # is the digit period of the pulse trains) and fed back through gate 18, which is opened by timing pulses T2, Fig. 2, applied at 100, to terminal 5, simultaneously with the application of a delayed carry train R from gate 25, also controlled by pulses T2, to terminal 6. The halfadder then produces sum or difference pulses S which are passed through delay 15 and a gate 29, opened by pulses T1, Fig. 2, to output channel 30. During addition, gate 33 is opened by a potential from sign-control trigger circuit 37 (e.g. of the Eccles-Jordan type), so that the carry train Ra, Fig. 2, is formed from the " et " pulses at 8 which are delayed by 6 in delay line 19 and applied either directly or through a further delay line 20 of 6/2 to gate 25. During subtraction, gate 34 is open and the carry train Rs is formed from the C and S pulses at 7 which are passed through gate 32 to the delay feedback channel 19, 20, 25 provided there is no corresponding pulse sent to inhibiting lead 53 from the A and C train respectively. The half-adder may be similar to those described in Specification 741,418, e.g. it may comprise a bi-stable trigger circuit (Fig. 4, not shown) which counts the input pulses applied with appropriate phase shifts, the pulse period being divided into six intervals defined by timing impulses relatively shifted by #/6 and applied to pentode gates. Modified adding and subtracting devices are described and shown in which two pairs of pulse trains (relatively shifted by 6/2) are added and/or subtracted during a pulse period which is divided into intervals of #/4, the result trains being fed back to the input terminal through minor cycle delays; in which different forms of subtractcarry circuit are provided; and in which the train B is delayed by #/2 relative to A, the delay 19 being correspondingly shortened from # to #/2. In other modifications, the A-train is delayed relative to the B-train and, during subtraction, the device is controlled so as to act alternately as an adder and a subtractor during the first and second half-digit-periods respectively, so as to correspond in operation to the adding and subtracting devices described in Specification 741,418. This may be achieved by applying pulses T1, T2 to gates 33, 34; as shown in Fig. 12, however, the control by trigger 37 is retained and, during subtraction, the gate 34 passes pulses T2 from 71 to an auxiliary gate 69 connected to the output of subtract-carry gate 32 which passes a C-pulse wherever there is no corresponding pulse in the A train. At the beginning of each digit period (pulse T1), the B and R (carry) trains are added and the addcarry pulses are fed back through delay 68 of 0 to gate 25 and input 6. At the time of pulses T2, the A train, delayed by 6/2 in 67, and the C train from gate 18 are added or subtracted and the carry pulses fed back through delay 19<SP>1</SP> of #/2 either via 33 or via 32 and 69. In a further modification, the half-adder is similar to an adding and subtracting device described in Specification 707,784 and comprises triode pairs having a rectifier switching network in their anode circuits.