baber/WOPTO huggingface dataset:
Patent JP-H0345281-A (JP)
Title: Pinball game machine
Inventor: NIIYAMA KICHIHEI
IPC: A63F7/02
Filed: 1989-07-12
Abstract: PURPOSE:To prevent a player from being given with disadvantage by surely detecting the shortage of balls in a ball leading trough by axially installing a plurality of stepping levers in the ball leading trough for leading balls from a storage tank and allowing a ball shortage detecting switch to operate and send out a ball shortage detection signal even if a certain stepping lever turns. CONSTITUTION:When a ball which drops from a ball drop port 17 of a storage tank 9 is deflected by a certain reason, and one between the first and the second stepping levers 46 and 47 turns in the rising direction on the upstream side, even if the first or second stepping lever 46 or 47 swings, a ball shortage detecting operating member 56 swings, since the first and second operating pieces 58 and 60 are set close to a receiving part 54 from above. And a ball shortage detecting switch 62 operates to send out a ball shortage signal. Therefore, even if the ball is deflected in a ball leading trough 10, the ball shortage detecting switch 62 surely sends out the ball shortage signal, and a ball supplying device operates to supply balls, and the motor of a winning ball processing mechanism stops operation, and the operation of a winning ball discharge mechanism is suspended temporarily.
Patent JP-H0936308-A (JP)
Title: Semiconductor device and its manufacture
Inventor: NAGANO YOSHIHISA
IPC: H01L27/04
Filed: 1995-07-14
Abstract: PROBLEM TO BE SOLVED: To solve the dispersion of electric characteristics and the disconnection of metal wiring which are caused by unevenness of the surface of a capacitor insulating film, and obtain a semiconductor device excellent in reliability at a high yield. SOLUTION: On the upper surface of an interlayer insulating film 1 covering the surface of a supporting substrate on which a semiconductor integrated circuit is formed, the following are formed in order; a lower electrode 2 for a capacitance element, a first dielectric film 7, a second dielectric film 8 thicker than the step-difference of unevenness of the first dielectric film 7, and a thin film 9 having an etching rate equivalent to the second dielectric film 8. By dry-etching, the thin film 9 and a part of the second dielectric film 8 are etched back, and a capacitor insulating film 10 is formed, on which an upper electrode 4 for a capacitance element is formed. The upper electrode 4 for a capacitance element and the capacitor insulating film 10 are selectively etched. The lower electrode 2 for a capacitance element is selectively etched and a capacitance element is formed.  A protective insulating film 5 for the capacitance element is formed, an aperture is made, and a metal wiring 6 is formed.
Patent JP-S6425946-A (JP)
Title: Steel plate having excellent workability and toughness as well as having good hardenability and its production
Inventor: MORITA MASAHIKO
IPC: C22C38/00
Filed: 1987-07-20
Abstract: PURPOSE:To produce a steel plate having excellent workability and toughness and having good hardenability by successively subjecting the steel contg. specific ratios of C, Si, Mn, Al, P, S and N to hot rolling and annealing under specific conditions. CONSTITUTION:The steel contg., by weight, 0.40-0.80% C, 0.2-1.50% Si, 0.20-1.50% Mn, 0.001-0.150% Al, <=0.018% P, <=0.010% S and <=0.0050% N as the fundamental components is hot rolled in the range of 800-500 deg.C finish rolling temp. and is rolled round a coil. Said hot rolled steel strip is then annealed for 1-200hr in the temp. range of 500-750 deg.C to form the soft material of <=60kgf/mm<2> TS having the structure consisting mainly of a ferrite phase and graphite phase. By this method, the steel plate suitable as the material for a pawl of an agricultural machine for cultivation is produced.
Patent JP-H0230278-A (JP)
Title: Signal processing unit
Inventor: SEKIYA MASATAKA
IPC: H04N5/262
Filed: 1988-07-20
Abstract: PURPOSE:To realize the simultaneous operation of data write and readout by writing a video signal by one horizontal scanning share via a buffer memory in the lump, transferring the signal to a memory capable of readout at random through the address setting and storing the signal therein. CONSTITUTION:A storage circuit 11 writes an output of a serial/parallel converter 7 and an ADC 5 serially by a command of a memory controller 6, and reads a data written already at random on the other hand. A luminance signal among a data read from the storage circuit 11 is converted into a serial data by a serial/parallel converter 15 and given to a DAC 28 via a Y inversion circuit 25 and solarization circuit 27. Moreover, a chrominance signal is converted into an analog signal by a DAC 28. Signals 41, 42, 44 are respectively signals commanding the mirror state, the zoom state and the mosaic state and each function is processed in an independent block by the state command signal, the combination of modes is attained and the mixture mode is realized.
Patent JP-2000010434-A (JP)
Title: Image forming device and heating device
Inventor: NASHIDA YASUMASA
IPC: G03G15/20
Filed: 1998-06-25
Abstract: PROBLEM TO BE SOLVED: To shorten development period and to improve safety by unnecessitating the designing and working of a through-hole for a ceramic heater. SOLUTION: Relating to an image forming device using an electrophotographic processing technique; the circuit breakers 106 and 107 of a heater power source line such as a relay are provided at both lines of power supply lines on a hot side 110 and a cold side 111 for a thermal fixing ceramic heater 101, and both circuit breakers 106 and 107 are controlled by a controller (CPU) 112, and also a conductive pattern 114 which is in parallel with the heater pattern 102 of the ceramic heater is printed on the mounting surface (secondary signal circuit surface) of the temperature detecting element(thermistor) 113 of the ceramic heater, and the conductive pattern 114 is connected with the secondary side coil of the circuit breakers 106 and 107.  Even in the case that heater crack is caused at worst, the power source line of the circuit breakers 106 and 107 are made in an opened state by the heater crack, and the contact of the circuit breakers 106 and 107 is made in the opened state, so that the safety is sufficiently secured.
Patent JP-H0342790-A (JP)
Title: Work dictionary collating device
Inventor: JIYOUSHIYOUMATSU TAKESHI
IPC: G06K9/72
Filed: 1989-07-11
Abstract: PURPOSE:To save the capacity of a dictionary and processing time by converting a read character string into a word string, a position code and a key word, and in addition, registering beforehand the character string to be collated in a dictionary part, and collating respective parts by a collating means. CONSTITUTION:The read character string is converted into the key word, the word string and the position code by a key word position detecting means 1. Dwelling place information to be a retrieved is registered previously in the dictionary part 22 of a first collating means 2 by the combination of the word string, the key word and the position code. In the key work collating part 31 of a second collating means 3, the key word of the read character string and the key word registered in the dwelling place information are collated with each other, and when coincidence is confirmed, in a position code collating part 32, it is verified whether the position code of the read character string is included in the position code registered in the dwelling place information or not, and when it is confirmed that it is included, the collated dwelling place information or a representative code is outputted to a classifier 5.
Patent JP-S6334650-A (JP)
Title: Program performance measuring system
Inventor: AZUMA KENJI
IPC: G06F11/34
Filed: 1986-07-29
Abstract: PURPOSE:To measure a measuring point by changing it dynamically, by executing measurement by saving the measurement execution unit of a program to be measured, and providing a means which counts a processing time. CONSTITUTION:When an execution unit in the program 5 to be measured is designated by its relative address from an input/output device 1, through the use of a measurement start point, and a measurement end point, a measurement control means 7 performs the mapping of the relative address, and an actual address, and also, saves the execution unit to a measurement start processing means 8, and a measurement end processing means 9, and embeds a branch instruction to the means 8 and 9 in a vacant area. When the program 5 is executed, and it arrives at the measurement start point, control is delivered to the means 8, and the execution unit existing at the measurement start point is executed, and simultaneously, a count processing means starts counting. On completing the execution unit, the counting by the means 6 is stopped by the means 9, and a processing is returned to the program 5. The count value of the means 6 is outputted to the input/output device 1 by an output processing means 10.
Patent JP-S5968004-A (JP)
Title: Fail-safe method of on-vehicle computer
Inventor: HIRAO YOSHIKAZU
IPC: G06F11/00
Filed: 1982-10-12
Abstract: PURPOSE:To initialize a computer, to simplify a circuit and to improve reliability by detecting the execution of a stop instruction by status information from the computer and causing top priority interruption according to the detection result. CONSTITUTION:The on-vehicle computer unit 9 consists of a CPU10, storage device 11, and input/output device 12, and the CPU10 and devices 11 and 12 are connected mutually by buses 13, 14, and 15. This CPU10 is provided with status terminals S0 and S1 for reporting the state to the outside. An NOR circuit 16 is connected to those status terminals S0 and S1 and the output of the circuit 16 is connected to the top priority interruption terminal TRAP of the CPU10. Then, the computer unit 9 itself malfunctions due to an external noise, etc., to execute the stop instruction, the H level of the output of the circuit 16 is detected and the top priority interruption to the CPU10 is caused to initialize the computer unit 9.
Patent JP-H0344580-A (JP)
Title: Bias test board for semiconductor device
Inventor: TOMOTA YOSHIYUKI
IPC: G01R31/26
Filed: 1989-07-12
Abstract: PURPOSE:To enable execution of a bias test being more accurate and having high flexibility by changing a bias level for each terminal by changing a connection pattern board prepared separately. CONSTITUTION:A plurality of sockets 11 for semiconductor devices, sockets 12 for connection patterns and guide pins 18 are formed on a multilayer base 14. A connecting point of each terminal (1) of each of the sockets 11 for semiconductor devices is connected, for instance, to a terminal in a first line of the sockets 12, a connecting point of each terminal (2) to a terminal in a second line of the sockets 12, and a connecting point of each terminal (3) to a terminal in a fourth line of the sockets 12, respectively. Since a bias level of each terminal can be changed by changing a connection pattern board 15 prepared separately, a bias test being more accurate and having high flexibility can be executed in a programmable manner.
Patent JP-H095425-A (JP)
Title: Reception sensitivity suppression control circuit
Inventor: IGARASHI OSAMU
IPC: G01S13/74
Filed: 1995-06-22
Abstract: PURPOSE: To provide a reception sensitivity suppression control circuit with a simple structure without using an external ROM in the base station of a secondary radar discriminating an aircraft. CONSTITUTION: This reception sensitivity suppression control circuit suppresses the reception signal according to the lapse of time with a sensitivity suppression start signal used as reference in the base station of a secondary radar system. The control circuit is provided with a first counter 9 counting up clock signals with the sensitivity suppression start signal used as reference, a distance clock generation section 10 generating multiple distance clocks having different periods from the output of the first counter 9, a distance timing generation section 11 generating multiple different distance timings from the output of the first counter 9, a clock selector 12 selecting the prescribed distance clock as the control clock from multiple distance clocks based on the distance timing,  and a second counter 13 counting down from the sensitivity suppression initial value based on the control clock to obtain the suppression signal.
Patent JP-H11354128-A (JP)
Title: Sealed lead-acid battery
Inventor: NEMOTO SEIJI
IPC: H01M4/68
Filed: 1998-06-11
Abstract: PROBLEM TO BE SOLVED: To provide a maintenance-free lead-acid battery excelling in a charge/ discharge cycle life, by using a positive-electrode grid made of a lead-antimony alloy, forming cross-sections of all minor bridges of the positive-electrode grid into circular shapes, and thereby suppressing antimony elution to the minimum. SOLUTION: A lead-antimony alloy is used for a positive-electrode grid of a storage battery. All minor bridges of the positive-electrode grid have a circular cross-section shape, and the surface area of the grid is small. An electrolyte is solated by adding fine silica to the electrolyte. Early capacity deterioration of a positive electrode plate, dropping-off of an active material, and elongation of the grid, can be prevented by using the lead-antimony alloy for the positive-electrode grid. The fine silica added to the electrolyte captures antimony and prevents an increase of water decomposition, and therefore properties of being maintenance-free and water supplementation-free, characterizing a sealed lead-acid battery, are not damaged. Because the amount of liquid decreased is small, long life performance is obtained.
Patent JP-S6238599-A (JP)
Title: Semiconductor memory device
Inventor: TOYAMA TAKESHI
IPC: G11C29/00
Filed: 1985-08-13
Abstract: PURPOSE:To analyze the defect of a memory part by providing an instruction memory part control part selectively outputting a signal which activates and deactivates an instruction memory part outputting a standby memory selecting signal. CONSTITUTION:When a WE signal and a write power source potential point 12 are set to a level H and a high potential, respectively, data is written in the variable threshold nonvolatile memory 810 of an instruction memory part control part 8. Then, since an RD signal from the part 8 is made at the level H, the instruction memory part 7 is deactivated to make its R/CCAM signal at the level H. Moreover the standby decoder selecting transistor 404 of a replacement control part 4 becomes conductive, and the output node 401 of the replacement control part 4 comes to a level L. Accordingly a standby memory part 2 is not selected, but a decoder carries out a decoding action. Thus, if all addresses of a memory part 1 are inspected in such a state, the defective cells of the memory part 1 can be investigated.
Patent JP-H0630299-A (JP)
Title: Pedestal level adding device
Inventor: SHIMURA KENJI
IPC: H04N5/16
Filed: 1992-07-07
Abstract: PURPOSE:To improve accuracy for adding pedestal level data to a video signal being one of digital processing in the case of digitally processing the video signal in an NTSC system or the like. CONSTITUTION:After pedestal level clamp processing at a clamp circuit 32, an analog video signal 31 is converted into a digital signal by an A/D conversion circuit 33. A pedestal level extraction circuit 1 extracts only the pedestal level data from the output of this A/D conversion circuit 33. Even when the A/D converted output is fluctuated, these extracted data follows up the fluctuation. Therefore, when these extracted data are added to the video signal after digital processing at a digital processing part 34 similar to the conventional one by a pedestal level adding circuit 36 similar to the conventional configuration, exact pedestal level addition can be provided.
Patent JP-S6158000-A (JP)
Inventor: TAGUCHI SATORU
IPC: G10L19/04
Filed: 1984-08-29
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S5971151-A (JP)
Title: Rapid traverse/rewinding mechanism
Inventor: ITOU MASAO
IPC: G11B15/44
Filed: 1982-10-15
Abstract: PURPOSE:To attain surely the switching operation, etc. with a simple constitution, by utilizing a motor torque for the switching operation in rapid traverse/ rewinding. CONSTITUTION:A taper pressing piece 50 at this side provided to a switching plate 47 presses a stopper 16 according to the movement of the switching plate 47 and the locking of an interleaved gear 13 is released. Then, a cam follower 22 locked around the center of a restoring section of a driving cam 20 is shifted toward the minimum diameter section of the cam 20 by a force of a spring 31 driving a power plate 21. With the cam follower 22 shifted, the cam 20 and the gear 13 provided incorporatedly are turned slightly. A notch 14 is released from the front of a reverse driving gear 12 with the slight turning of the gear 13 to mesh with the gear 12 and the gear 13. As a result, the power plate 21 starts moving toward the this side of a tape player with the operation of the cam follower 22 following the outer circumference of the cam 20.
Patent JP-H0349891-A (JP)
Title: Shaft action supervisory device
Inventor: FURUKAWA HIROSHI
IPC: B25J19/06
Filed: 1989-07-12
Abstract: PURPOSE:To reduce impact, received by a drive shaft in each limit point in a movable area, while substantially spreading a work area as wide as possible by providing a control part which stops supply of power to a motor further actuates an action means when an output value of speed detectors exceeds a permissible value set corresponding to each fixed point. CONSTITUTION:By speed detectors set up to each fixed point K0, K1, K2, K3, a rotary speed of a shaft, which passes the fixed points K0, K1, K2, K3 in an outer direction, is measured. Next by a control part, when an output value of each speed detector exceeds a permissible value in accordance with the fixed points K0, K1, K2, K3, supply of power to a motor, which drives the shaft, is stopped further with a brake applied to the shaft. In this way, a work area (H)0, (H)1, (H)2, (H)3 of each rotary speed of the shaft is spread, further impact, received by the shaft in each limit point in a movable area, is moderated to zero or extremely low, and damage of a mechanism, contained with the shaft, can be prevented.
Patent JP-2000013633-A (JP)
Title: High-voltage circuit
Inventor: YOSHIKAWA YOICHI
IPC: H04N3/185
Filed: 1998-06-26
Abstract: PROBLEM TO BE SOLVED: To prevent oscillating current due to an LC from generating after a damper period by using a flyback pulse as a switch signal and performing on/off of a resonant capacitor about a high-voltage stabilization circuit of a primary current control system of a FBT(flyback transformer) which varies on time of a high-voltage output transistor and stabilizes high voltage. SOLUTION: Between a resonant capacitor 5 and grounds, anode of a diode 14 is inserted to the resonant capacitor connected with the diode 14, a collector is inserted to a bipolar type PNP transistor 15 that is connected to the resonant capacitor in the same way and the transistor 15 is a high-voltage stabilization circuit of a primary current control system which is provided with a switching circuit that performs on/off operations with a flyback pulse that is obtained from a tertiary winding of an FBT.
Patent JP-S6346003-A (JP)
Inventor: SUTEIIBUN UIRIAMU BERU
IPC: G01S7/02
Filed: 1987-07-21
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6353036-A (JP)
Inventor: YOHAN EMIRU AITERU
IPC: B41F21/05
Filed: 1987-07-21
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6074555-A (JP)
Title: Semiconductor device
Inventor: SUNAMI HIDEO
IPC: H01L21/822
Filed: 1983-09-30
Abstract: PURPOSE:To increase density by dividing a groove dug to a semiconductor substrate into two or more and forming them in a semiconductor device with a capacitor array consisting of a capacitor using a side wall section in the groove as an electrode surface. CONSTITUTION:One transistor type dynamic random access memory (dRAM) has a capacitor region mainly using side walls in grooves 1 dug to a Si substrate 10, and leakage currents IL flow through the deep section of the Si substrate 10. When groove width WM is made small, leakage currents IL reduce because potential among the grooves is elevated by the potential of the peripheral Si substrate 10. When one grooves are divided into two so as not to vary the side wall areas of the grooves, leakage currents can be reduced remarkably without minimizing the capacitance of a capacitor, distances among the grooves can be shortened, and the integrity of the dRAM can further be increased.
Patent JP-S5969677-A (JP)
Inventor: HOSHINO HIROSHI
IPC: F25D3/10
Filed: 1982-10-14
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6074236-A (JP)
Title: High-voltage treatment method of cathode ray tube
Inventor: YOSHIGI SHIYOUJI
IPC: H01J9/44
Filed: 1983-09-30
Abstract: PURPOSE:To reduce the continuous discharge between the internal surface of the neck and the low-voltage applied electrode by repeating the applying and earthing processes, such as application of high-voltage earthing application of high- voltage earthing, when the voltage is to be applied to the high-voltage applied electrode for cleanup of the electrodes. CONSTITUTION:During the first half of the high-voltage application to the high- voltage applied electrode, the processes of application of high-voltage floating  application of high-voltage floating are repeated. In the second half of the treatment wherein the applied voltage becomes higher and discharge can easily occure between the low-voltage applied electrode and the internal surface of the neck, the processes of application of high-voltage earthing application of high- voltage earthing are carried out repeatedly. In this case, the period of application of high-voltage is within 5sec and the period for earth potential application is 2-3sec. In this manner, the continuous discharge between the internal surface of the neck and low voltage applied electrode can be reduced. Furthermore, the separation of the glass of the internal surface of the neck can be reduced and a cathode ray tube with high voltage is obtained.
Patent JP-S57104208-A (JP)
Title: Degaussing coil
Inventor: FUKUOKA AKIRA
IPC: H01F13/00
Filed: 1980-12-22
Abstract: PURPOSE:To make continuous degaussing possible by a method wherein a coil winding or a bobbin is shaped so that the strength of a magnetic field is gradually decreased from one end to the other end in the direction of the coil axis and a magnetic component is passed through the coil from its one end to the other end in the decreasing direction of the magnetic field. CONSTITUTION:A degaussing coil 10 is, for example, wound around a bobbin of which the cross section is constant along the coil axis so that the number of turns of the coil winding 12 is gradually reduced from end A to end B. With this structure, when a constant alternating current is applied to the coil winding 12, the distribution of a magnetic field as gradually decreasing from end A to end B along the coil axis line can be obtained. Therefore, degaussing can be continuously implemented by conveying a magnetic component therein from end A to end B. Further, even if a bobbin is of a cone shape instead of a bobbin with the constant cross section and the winding is wound in the constant thickness, a similar effect can be gained.