Patent EP-0372865-A2 (EP)
Inventor: SUZUKI MASATO
IPC: G06F12/08
Filed: 1989-12-01
Abstract: A cache device supplies a given word length of a variable-length instruction code and an instruction fetch device. The cache device realizes an instruction cache (3) capable of supplying only the desired word length of an instruction code designated by an arbitrary address irrespective of the instruction alignment. The cache device also realizes a branch history table (4) capable of reading the branch destination address of the branch instruction which is positioned nearest to the read address in the word length supplied by the instruction cache with the read address as the origin. The instruction fetch device is capable of always reading an instruction code of the desired word length and performing only the prediction of a branch of that branch instruction which is to be executed first irrespective of the position and number of branch instructions included in the instruction code read. The cache device realizing the instruction cache selects one of the entries whose stored address or part thereof coincides with the read address and at least one another entry holding the storage contents contiguous to the storage contents stored in the first-mentioned entry and it includes storage contents selecting means   (312-315) so that the storage contents stored in the selected at least one or more entries are selected by every storage unit of the storage contents in corre­spondence to the read address. The cache device realiz­ing the branch history table selects one of the entries whose stored identifying information coincides with that identifying information which identifies the subject storage contents of a reading operation and at least one another entry falling within a given range determined by the stored identifying information and it includes storage contents selecting means (322) to select from the selected at least one or more entries the one whose stored identifying information differs in a minimum amount from the identifying information for identifying the subject storage contents of the reading operation and the storage contents stored in this entry are outputted. Also, the instruction fetch device includes instruction storage means (3) formed by the cache device realizing the instruction cache and the instruction storage means is searched by the value of address holding means (1) to output an instruction string of a predetermined word length stored therein. At the same time, if the outputted instruction string includes no branch instruction whose branch has been taken in the past, address incrementing means (5) generates an address of an instruction string which is to be outputted next from the instruction storage means, whereas if the outputted instruction string includes   any branch instruction whose branch has been taken in the past, branch predicting means (4) formed by the cache device realizing the branch history table is searched by the value of the read address holding means thereby outputting the branch destination address of the branch instruction which is nearest to the read address and included in the instruction string read from the instruction storage means.