Patent GB-1162109-A (GB)
Title: Semi Conductor Data and Storage Devices and Data Stores Employing Such Devices
Inventor: GARDNER PETER ALAN EDWARD
IPC: H03K3/012
Filed: 1966-12-22
Abstract: 1,162,109. Electric digital data storage. INTERNATIONAL BUSINESS MACHINES CORP. 22 Dec., 1966, No. 57536/66. Heading G4C. [Also in Division H3] A data store incorporates transistor bi-stable circuits of the type in which the collector and base electrodes of two transistors are crosscoupled and the circuits use transistors having two emitter electrodes or equivalent assemblies of transistors, the current in the conducting transistor normally passing through one emitter 6 or 7, designated the control emitter, so that the state of the circuit may be ascertained by diverting the current to the other emitter (7 or 9) designated the output emitter. Thus, by raising the potential of a control emitter, current, if flowing to the transistor, is diverted to the associated output emitter and may be detected in a sense circuit connected thereto (not shown). Writing may be effected by simultaneously raising the potential of a control emitter so as to divert the current to the output emitter and lowering the potential of the output emitter of the transistor so that it conducts. At the same time the potential of the other output emitter may be raised. Writing may alternatively be effected by applying to a control emitter a pulse that first goes negative and then positive (Fig. 3, not shown). The negative portion causes the corresponding transistor to conduct and the positive portion temporarily diverts the current to the output emitter without changing the state unless a positive pulse is also applied to the associated output emitter. The circuit is made more sensitive to writing if the potential of the supply line is simultaneously lowered or removed. The bi-stable circuits are arranged in a matrix as shown in Fig. 6, the control emitters being connected to word lines 7 and 9 and the output emitters being connected to sense column lines 6 and 8. In a contents addressable store, matching may be effected by applying the address to the word lines or alternatively by applying the complement of the address to the sense lines. Data may be transferred from one position to another in the same column. For example, a " 1 " from A 1  is transferred in inverse sense by applying a read pulse to the A 1  word line 7 to provide a write pulse in the sense line 8 which will write a " 0 " into B 1  or C 1  according to which is sensitized by lowering its supply voltage. Data may also be shifted to the right or left. Thus if a read-out pulse is applied to the upper line 7, the state of A 2  would be indicated on sense line 8. If simultaneously the lower line 7 is energized to re-set C 1  to " 0 " and gate 10 is opened, C 1  will receive the data from A 2 . Transfer to the left or right may be effected if gate 10 is as shown in Fig. 7. A data pulse being transferred causes transistor 15 to conduct, cutting off 16 and whichever of 11 or 12 was previously rendered conducting by left or right shift control signals. The rise of collector voltage at the corresponding collector provides the write pulse. Logic transfer of data may alternatively be effected. Thus if A 1  andB 1  are read out simultaneously into sense line 8 and C 1  is sensitized by lowering its collector supply voltage, then C 1  will be changed to the " 1 " state if A 1  and B 1  were both " 0." Alternatively if A 1  and B 1  are read out into sense line 6 and C 1  sensitized then a " 1 " will be written into C 1  if A 1  or B 1  is "0." Again, if A 1  and B 1  are opposite and are read into sense lines 6 and 8 simultaneously then C 1  if sensitized will become " 0 " if both are " 0 " and " 1 " if both are 1." If the sense bias lines 6 are connected diagonally instead of vertically then diagonal shifting may be effected without external gating (Fig. 8, not shown). In this case the complement is shifted.