Patent GB-1265013-A (GB)
IPC: G06F12/16
Filed: 1969-04-24
Abstract: 1,265,013. Electric digital data storage: computers. INTERNATIONAL BUSINESS MACHINES CORP. 24 April, 1969, No. 20902/69. Headings G4A and G4C. Error detecting circuitry checks data transfer between two registers to provide an error signal only in the absence of a bit of one value in any order of the second register when the same order of the first register contains a bit of the one value. In Fig. 1 two associative stores 1, 2 storing the same information have a selector trigger 4 (to indicate match) for each word location 3, and each have two input/output registers 12, 13 for store 1 and 15, 16 for store 2. Register 13 can also feed and be fed by a bus 23, register 16 can be fed by bus 23, register 12 can be fed by a bus 24, and register 15 can feed and be fed by bus 24, via drivers 26, 30 and receivers 25, 26, 28, 29. One or more further pairs of associative stores may be connected to the buses 23, 24 as may non-associative stores, and the buses communicate with each other via a buffer which may be in the main memory of a computer system using the invention or may be a single separate register.  Error features.-During simultaneous associative search in stores 1 and 2 using the same search argument from registers 12, 15 or 13, 16, comparators 6 produce an error signal if different selector triggers 4 are set by the two stores. After read, comparators 18 produce an error signal if input/output registers 12 and 15, or 13 and 16, have unequal contents (only one pair of registers is loaded from the store). Following this, to transfer out the read information and prepare for the next associative search, registers 13, 15 are gated (by actuating drivers 26, 30) to buses 23, 24 respectively, the buses being gated (by actuating receivers 27, 28) to registers 16, 12 almost immediately afterwards. An error signal is now produced unless there is a 1 in register 12 for each 1 in register 15 and a 1 in register 16 for each 1 in register 13 (this form of check being used since other stores may be using the buses simultaneously so a simple equal/unequal check cannot be used). Parity circuits 31, 33 connected in series, generate the parity of the data being supplied to registers 12, 16 from the buses 24, 23 (see above) and this parity is compared (not shown) with parity generated for the data on the buses by two parity circuits (not shown) connected to the respective buses and in series with each other, an error signal being produced on inequality. The buses 23, 24 are now gated (by actuating receivers 25, 29) to the registers 13, 15. An error signal is produced if registers 12 and 15, or 13 and 16, are now unequal as determined by comparators 18. After a write operation, all the receivers are actuated to load registers 12, 13, 15, 16 from the buses for the next associative search, parity checking, and an inequality check by 18, being done as above. After associative interrogation, an extra check on the drivers 26, 30 is done by inhibiting all drivers (of all pairs of stores linked to the buses) and generating the parity of the data on the buses, an error signal being produced if it is non-zero. Detection of any error causes retry (repetitive) of the storage cycle giving the error. If this is unsuccessful and the error can be attributed to data errors, an incorrect word is replaced by its duplicate from the other store 1 or 2 followed by retry. If still unsuccessful, or if the error cannot be attributed to data errors, lines 42, 43 are de-energized to isolate the pair of stores from the buses. If the error signal came from mismatched selector triggers 4, the selector triggers are reset (their states having been saved in a diagnostic column of each store 1, 2), then set in turn by a " next " operation which causes a 1 to shift down each column of triggers 4. If the is do not arrive at the bottoms of the columns simultaneously (even after retires) the the stores are isolated from the buses. If they do arrive simultaneously a read operation is performed and if comparators 18 (which should be comparing zeroes) detect inequality, the selector triggers 4 are not resetting properly, so the stores are isolated from the buses. If this does not happen, the " next " operation is good, and is used repeatedly to read out successive bits of the diagnostic columns for comparison at 18, inequality causing the rest of the words corresponding to the unequal diagnostic column bits to be read out for parity checks (by means not shown). If both words have correct parity, the stores are isolated, but if only one is correct, the incorrect word is replaced by the correct one via the two buses. Fig. 6 (not shown) shows two stages of a parity circuit having a stage for each bit position of a word whose parity is to be generated. A typical stage comprises a transistor tree controlled by a parity input in true and complement form from the preceding stage, and by the corresponding bit of the word, to produce a parity output in true and complement form to the next stage. The circuit can also be used for checking parity. Fig. 7 (not shown) shows one stage of a comparator, having outputs indicating (A and not B), (B and not A) respectively, where A, B are the bits being compared. Both outputs are sensed for the inequality comparison and only one for the ones comparison above.