Patent GB-1334583-A (GB)
Title: Vacuum chuck assemblies
IPC: B24B37/27
Filed: 1971-06-23
Abstract: 1334583 Vacuum workholders; polishing SIGNETICS CORP 23 June 1971 [1 July 1970] 29468/71 Heading B3D [Also in Division H1] A vacuum chuck assembly for use with a grinding machine in an apparatus for treatment of a semi-conductor wafer, the grinding machine including a source of vacuum for connection to the chuck assembly, comprises a body 22, Figs. 1 and 2, which is formed with a bore 24 for connection to the source of vacuum and which has a surface carrying a plurality of vacuum chucks 31, the body and chucks being formed with holes 33, 34 establishing communication with the bore in the body so that, in use, a vacuum is supplied to the chucks whereby wafers may be held in place on the chucks while grinding operations are carried out on the wafers. The body 22 may be of stainless steel and the bore 24 has a thread 23 for a swivel-type connection to a vacuum source and communicates with radial channels 26  in a cover-plate 28, in turn, communicating with annular channels 27 in the body. A plurality of chucks 31 of ceramic material formed with annular grooves 32 are brazed to the body, and the holes 33, 34 in the chucks and body connect the annular grooves to the channels 26, 27 and bore 24. A wafer is placed on each chuck and held thereon by vacuum supplied to the bore 24. Thereafter, the wafers are ground so that their surfaces are flat and parallel. After grinding, the wafers are mounted on individual mounting blocks 36, Fig. 3, using an hydraulic press 37. The blocks are mounted on a plate 38 which can be both heated and cooled. A guideplate 41 is urged upwardly by springs 48 and has holes 49 for locating the wafers 52 and wax 51 which is melted when the plate 38 is heated. A layer 53 of felt is placed over the wafers and the pressure-plate 54 of the press lowered so that the wafers are pressed on to the blocks 36, the plate 38 being cooled so that the wax solidifies. The blocks with the wafers mounted thereon are then placed in a jig 58, Fig. 4, having a body 59 formed with an annular recess 61 closed by a flexible diaphragm 67 secured to the body by a plate 69 having openings 73 for receiving the mounting blocks which are held in the openings by magnets 68 secured to the diaphragm. A handle 101 enables the jig to be lifted and acts as a spigot for locating the jig in a polishing machine 74, Fig. 5, the handle fitting into a bore 107 in an adjustable weight which presses the wafers against a polishing plate 77 rotated by a belt drive 81 from a motor 83. A plurality of jigs are disposed about the axis of the plate 77 and are rotated about their own axes by a friction drive 87 driven by a belt 91 from a motor 93, the jigs being located by idler assemblies 96. The apparatus described is for producing dielectrically isolated semi-conductor devices using wafers of single crystal silicon which may be purchased already polished on one surface or may be ground and polished on one surface in a conventional machine and then cleaned. Thereafter, the wafers are oxidized to form a silicon dioxide layer over their surfaces to protect the polished surfaces when placed on the vacuum chucks 31, the other surfaces being ground to remove their layer of silicon dioxide and to be flat and parallel to the already polished surfaces. The wafers are then removed from the chucks, the oxide removed in an etch, and, after cleaning, are re-oxidized and masked for isolation moats etched into the silicon dioxide layers and the wafers. Further re-oxidizing forms a continuous layer over the polished surfaces and moats. A support structure of polycrystalline silicon is then formed upon the surfaces having the moats and the opposite sides placed on the chucks so that the polycrystalline surfaces can be ground flat and aparallel, the wafers then being turned over so that the single surface can be ground. The wafers are then mounted on the blocks 36 and inserted in the jig 58 for polishing in the machine 74, until, upon inspection, the silicon dioxide layer for forming the isolation is exposed and dielectrically isolated islands are produced formed in the original single crystal silicon and carried within the supporting polycrystalline silicon, the bottom of the islands having the first prepared polished surfaces. The islands have a thickness of 20 to 30 microns and the wafers an overall thickness of 8 mils. Integrated circuits are then produced on the islands.