Patent GB-925392-A (GB)
Title: Parallel coded digit adder
IPC: G06F7/50
Filed: 1962-03-01
Abstract: 925,392. Parallel adders. NATIONAL CASH REGISTER CO. March 1, 1962 [April 4, 1961], No. 7986/62. Class 106 (1). In a parallel adder for the addition of two pure binary or binary coded -decimal numbers applied in parallel, one of the numbers to be added is first recorded into a different code, the output sum being recoded to the original code if this is necessary. The circuit described employs the method of Specification 845,466, in which one of the numbers to be added is converted to an " excess 6 " code, by extending the method to parallel instead of serial operation. The circuit may be employed to add or to subtract and the numbers supplied may be in pure binary or in binary coded decimal form, these operations being controlled by signals Ac, Dc, from a computer (not shown). The circuit may also deal with six-bit characters under the control of a further signal from the computer. As shown, Fig. 1, three-decimal digit numbers F, G, each decimal digit being in binary coded form, are applied to decimal units 1-3, the sum output appearing as binary coded decimal digits J 1 -J 4 , J 5 -J 8 , J 9 -J 12 . Fig. 2 shows in detail one of the threedecimal units and comprises a conversion control circuit CC-1 (Fig. 5, not shown), four binary adders B-1 to B-4 and a reconversion control circuit RC-1 (Fig. 6, not shown). In the operation of the circuit of Fig. 2, signals F 1 -F 4 , G 1 -G 4  representing two decimal digits are applied to the circuit and signals Ac, Dc are applied from the computer control to indicate that the addition of decimal digits is required, these signals being effective to cause the control circuit CC-1 to change the signals F 1 -F 4  to signals H<SP>1</SP> 1 -H<SP>1</SP> 4 , representing the complement of the " excess 6 " form of F 1 -F 4 . The signals G 1 -G 4  and H<SP>1</SP> 1 -H<SP>1</SP> 4  are applied to the binary adders B-1 to B-4 to form output sum signals Ja<SP>1</SP> 1 -Ja<SP>1</SP> 4  any carry signals produced appearing on outputs K 1 - K 4 . If a K 4  output is not produced the reconversion control circuit RC-1 is caused to translate the signals Ja<SP>1</SP> 1 -Ja<SP>1</SP> 4  to signals J<SP>1</SP> 1 -J<SP>1</SP> 4  representing the required sum by subtracting 6. In a modification (Fig. 10, not shown), the carry signal is supplied from all the binary adders of a decimal unit simultaneously to the next unit. Binary adder, Fig. 3. This is effective to add the signals Gi, Hi<SP>1</SP> and a carry Ki-1 to produce an output Ja<SP>1</SP> 1  and a carry Ki (dashes represent complementary signals). The signals Gi, Hi<SP>1</SP> are applied to transistors 21, 22 which, together with resistors 25 and clamping diodes 27, constitute an " exclusive or" gate. The potential at a junction 23 is applied to transistors 29, 30 which constitute another " exclusive or " gate to produce the output Ja<SP>1</SP>. The potential at the junction 23 is applied together with the previous carry Ki-1 to a transistor 31 which functions as an " and " gate and whose output is applied together with the output of the transistor 22 to produce the carry output Ki. In a modification (Fig. 9, not shown), the transistors 31, 29 are replaced by a single transistor.