Patent GB-810656-A (GB)
Title: Electronic multipliers
IPC: G06F7/52
Filed: 1955-12-19
Abstract: 810,656. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 19, 1955 [Dec. 24, 1954], No. 36311/55. Class 106 (1). An electronic product generator for producing every single-digit multiple of a multiplicand comprises input control means, Fig. 4, for entering certain predetermined multiples of the multiplicand into a number of registers A-E, read-out means 401 for manifesting certain single-digit multiples of the numbers in said registers, and transfer gate means 404 for applying some of the single-digit multiples either additively or subtractive to the said registers to modify the contents thereof whereby the readout means then manifests every single-digit product of the multiplicand. The device described has three phases of operation: a " readin " phase, a " transfer " phase, and a " compute " phase, Fig. 4a, each phase lasting for one 16-point cycle. On the application of a start pulse a " read-in " phase is commenced during which the input control means causes the multiplicand to be entered into each of registers A and B, twice the multiplicand to be entered into each of registers C and D and ten times the multiplicand to be entered into register E. At the end of the read-in phase a transfer phase automatically commences during which the multiples 2, 2, 5 and - 1 of the multiplicand are added to the registers B, C, D and E respectively, this being shown in the transfer column of Fig. 4a, and being effected by the transfer gates 404, there being three gates for each different multiple transferred, as each register is assumed to be of three decimal denominations. At the end of this phase the registers A-E hold the multiples 1, 3, 4, 7 and 9 respectively of the multiplicand (see compute column, Fig. 4a) and no further operation of the apparatus occurs until a " compute " signal is applied, whereupon in the following cycle the output gates 405, each gate actually having three parallel output leads, produce differentially timed pulses representative of all the single-digit multiples of the multiplicand. A second compute cycle can be initiated by applying a second compute signal to the device, and thus the apparatus could be used as the basis of a multiplier that operates by summing partial products. Registers and multiplying read-out devices.- Each decimal denomination of the registers A-E comprises either four or six or ten triggers representing decimal numbers on either a " 1, 2, 4, 8 " code, or a bi-quinary code or a one-out-of-ten code respectively and the multiplying read-out devices each comprise an arrangement of gates conditioned by the triggers of the associated register and so arranged that when ten input leads are successively pulsed by a commutator one differentially timed output pulse is produced representing the digit in the corresponding denomination of the required multiple. The times five multiplying circuit for two denominations each comprising ten triggers only one of which is on, is shown in Figs. 2a, 2b. The registers are so connected that the on trigger causes current to flow through the emitter of an associated transistor, the result being that in the units denomination, if an even digit is registered current flows through a resistor 156 completely cutting-off a pentode 158 so that when a positive pulse is applied from the commutator to the suppressor grid no output pulse is produced, whereas if an odd digit is registered current flows through a resistor 164 priming the pentode 158 so that on receipt of a pulse from the commutator it fires and produces an output pulse representing the digit five, and in the tens denomination, if an even digit is registered a triode 180 is made non-conductive thereby priming the pentodes 1-4 by raising the potentials of their screen grids so that one of these pentodes which has the potential of its suppressor grid raised by the digit in the units denomination fires, when pulsed by the commutator, and produces a differentially timed pulse at tens output terminal 170 whereas if an odd digit is registered one of the pentodes 5-9 fires. Input to each denomination of a register is effected simultaneously by applying the appropriate number of pulses to the input terminals 10 any carry being stored until a carry propagation period. Control unit and transfer gates.-The control unit comprises an arrangement of hard-valve triggers and thermionic gates and requires driving by an external primary pulse source. Upon the first primary pulse after the start signal, the commutator is started to advance through its ten positions and the units and tens denominations of the multiplicand are applied as differentially timed pulses coming for example from a record card to terminals 500 and 501 respectively, and as a result the input control emits on leads 533 and 537 (both leads being several leads in parallel) pulses representing twice the multiplicand and the multiplicand respectively, which are entered in registers A-C as described above, the ten-multiple for register E being produced by a denominational shift. The transfer gates 404 convert the differentially timed pulses from the read-out units 401 into groups of pulses equal in number to the digit represented, except that the gates associated with register E produce pulses in number equal to the tens complement of the differentially timed pulses. Specifications 595,553, 595,593, [Group XXIII], and 599,553, [Group VII], are referred to.