Patent GB-1463693-A (GB)
Title: T ransfer function identifier system
IPC: G05B23/02
Filed: 1974-06-18
Abstract: 1463693 Generating transfer functions; counting apparatus; digital stores SOC NATIONAL D'ETUDE ET DE CONSTRUCTION DE MOTEURS D'AVIATION 18 June 1974 [18 June 1973] 26890/74 Headings G4C G4D and G4G The nature of a physical system 1, Fig. 1, is investigated with the aid of a model 2 having a transfer function with variable coefficients of the same kind as that of the (object) system, the model being adapted to accept the same inputs as the object system and also inputs for the variation of the said coefficients, the outputs of model and object system being fed to an error detector 3 which controls the coefficients in accordance with a law which tends to minimize the error. In accordance with the invention, input and output data from the object system is digitally coded and stored in a storage element 5 in real time, the stored signals being read out cyclically at a higher rate than they are read into the store. Fig. 4 shows a circuit for the model which can be adapted by means of switches to provide different transfer functions. Thus, if A represents attenuation, B = 1/# 0  represents a time constant and C represents gain, a second order model may be represented by or where p represents differentiation (phase lead) and 1/p represents integration. The circuit comprises a differentiation stage and two integrator stages, amplifiers and inverter amplifiers, having the gains shown, together with an amplifier inverter 6 of unity gain. The switch 7 enables the input and output to be interchanged in order to obtain the inverse of the function set forth above, and the sign of the error may be changed by the switch 9. The switch 8 enables phase lead to be included or left out and the switch 10 enables the function to be commuted between first and second order. Suitable ranges and increments of A, B, C are given. The Specification also gives suitable algorithms, e.g. (# denotes error), for generating A, B, C from #, ##, e, #s m  and #s m , together with coefficients # A , # B , # C , ##, ### chosen such that the expression is minimized by the algorithms. A circuit for generating A, B and C comprises a differentiator 19, multipliers 20, 21, 22 and integrators 23, 24, 25, Fig. 10. Fig. 7 shows an acquisition and compression circuit for values of e 0  and s 0 . These values are sampled alternatively at a clock rate of 1 MHz by a circuit K which supplies pulses in a number proportional to each sample to respective compression circuits II, III each comprising a chain of dividers. Control voltages applied to the chain enable the compression ratio to be multiplied by factors of 10, and control voltages u select a compression ratio of 1, 2 or 5. The clock pulse is also applied to a compression circuit I during a period determined by circuit K which compares e 0 , s 0  with an increasing reference voltage. The circuits cease to receive pulses when the output of the comparator reaches zero, upon which the OR gate q 2  furnishes a command E to the 12-bit counters C4, C5 where the mean values of e 0  and s 0  are respectively accumulated. The command causes the counters to empty into respective stores M2, M3, Fig. 10, which in turn supply circulatory random-access stores Me, Ms each in the form of twelve shift registers. The command E is fed to a 10-bit counter C1 which resets M2, M3 to zero after advancing one step. A further 10-bit counter C3 operates synchronously into stores Me, Ms and each time the counters C1, C3 indicate the same address, the comparator CA produces a command for the recording of the contents of M2, M3 in circulatory stores Me, Ms. A 10-bit counter C2 is advanced at a rate which is a submultiple of the rate of clock H and causes transfer of the contents of stores Me, Ms into buffer stores M4, M5 whenever the addresses recorded in C2, C3 are identical, as determined by a comparator CB. If the two addresses recorded by counters C1, C2 are identical at the time of read-out of Me, Ms, the latter are not completely full. This fact is detected by a comparator D which resets counter C2 to zero. Complete filling of Me, Ms is indicated by the overflow store M1 of counter C1 connected to OR gate P1 which enables advancing of counter C2. Alternatively, if the stores Me, Ms are sufficiently full (as determined by an operator) the counter C1 may be tapped by a switch and an enabling signal fed through gate P1 to the counter C2. At the end of each cycle comparator D issues a pulse in response to which the monostable S generates a pulse of length #. The pulse may be used to freeze values A, B, C for a time # or may activate a feedback amplifier 30 for the same time interval. The amplifier is designed to inject a signal G# into the input and to minimize # as quickly as possible.