Patent GB-892434-A (GB)
Title: Improvements in or relating to data processing machines
IPC: G06F3/02
Filed: 1958-05-15
Abstract: 892,434. Digital electric calculating apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 15, 1958 [May 17, 1957 (4)], No. 15599/58. Class 106 (1). A data processing machine comprises multiorder storage means providing successive digit storage positions interconnected to permit shift of digits stored in each position to the next, means adapted to select successive numeric digits for entry into storage in said storage means, translating means responsive to each digit selection for translating each successive selected digit to temporary storage in the highest-order digit storage position of said storage means, and means adapted thereafter to shift each previously stored digit automatically to the next-higher-order storage position and the temporarily stored digit to storage in the lowest order digit storage position of said storage means. A keyboard controlled business machine is described. Accumulator.-The accumulator comprises five triggers, 1, 2, 4, 8 and carry, Fig. 6b, connected so as to count in the binary scale, a " carry " from any counting stage (which occurs when that stage is turned off)-for example from stage 2- being transmitted to the next higher adjacent stage by a loop such as cathode follower 6-15, or circuit 6-18, cathode follower 6-21, and inverter 6-23, and carried from the " carry stage " being transmitted back to stage 1. A basic addition cycle, during which two binary-coded decimal digits are added together, comprises three periods, an A-period in which the first digit is entered into the accumulator, a B period in which the second digit is added into the accumulator and a C period in which the sum is read out of the accumulator and stored elsewhere, any decimal carry resulting from this addition remaining in the accumulator to be dealt with in a subsequent addition cycle. During the A period the four bits of the first decimal digit are read out of the core matrix via amplifier 6-38, Fig. 6a, and gate 6-40, write trigger 6-45, cathode follower 6-67, and gate 6-69 to cathode follower 6-74, from where they are distributed by gates 6-75, 6-76, 6-77 and 6-78, Fig. 6b, by 1, 2, 4, and 8-bit pulses, see Figs. 5a, 5b, to the appropriate triggers of the accumulator. Each output pulse produced by the core matrix is produced by a read pulse, Fig. 5a, and causes the write trigger 6-45, Fig. 6a, to be set on. This trigger is then turned off by the following write pulse. Thus the actual input pulses to the accumulator triggers do not extend outside the period from one read pulse to the next write pulse. Also during the A period, during the 2-bit portion thereof, a " set " pulse, see Fig. 5a, is applied via a gate 6-82, Fig. 6b, to the turn off input of the carry trigger which if it is on, representing a decimal carry from the preceding addition cycle, turns off and adds ninety to the trigger 1. During the B period the bits of the second digit are entered in a similar manner, these bits passing through a gate 6-68 instead of the gate 6-69. Also during the B period a " set " pulse is entered into trigger 2 of the accumulator via a gate 6-85 at 1-bit time and also into trigger 4 of the accumulator via a gate 6-86 at 2-bit time. This results in the addition of 6 to the accumulator. Thus at the end of the B period, if the carry trigger is on it will be storing a decimal carry and the number registered in the other four triggers will be the decimal sum digit but if, at the end of the B period, the carry trigger is not on then the number registered in the other four triggers will be 6 more than the decimal sum digit. This 6 is effectively subtracted during the C period, by the addition of 10, as the number in the accumulator is being transferred bit-by-bit, lowest bit first, via gates 6-55, 6-56, 6-57, 6-58, associated cathode followers, inverter 6-64 and the write trigger 6-45 to the core matrix. During 1-bit time of the C period, the bit in trigger 1 is stored and also, if the carry trigger is on, a set pulse is entered into trigger 2 via a gate 6-88, thus correcting the 2-bit before it is stored. During 2-bit times the bit in trigger 2 is stored and if the carry trigger is on a set pulse is entered into trigger 8 via a gate 6-89 to thereby correct the 8-bit. During the 4- and 8-bit times the bits in triggers 4 and 8 are stored. The digit entered into the adder during the B period can be entered negatively by changing over a relay contact 246-2, Fig. 6a, to effect subtraction. Data store.-The data store comprises a rectangular array of magnetic cores, Fig. 7a, divided into a four-column buffer storage unit and seven other four-column storage units, only storage unit No. 1 being shown. A particular storage unit is selected by relays R322, Fig. 7d, &c., and cores within a selected storage unit are selected by an X matrix, Fig. 7b, and a Y matrix, Fig. 7c. The X matrix is driven by a ring of three triggers 7-10 to 7-12, Fig. 7c, and a ring of four triggers 7-16 to 7-19, both rings being advanced by Osc 2 pulses, see Figs. 5a and 5b, and is characterized in that the row and column windings are wound in opposition to each other. In operation, by using inverse outputs from the row ring of triggers 7-10 to 7-12, and direct outputs from the column ring of triggers 7-16 to 7-19 to control gates 7-30 to 7-32, and 7-37 to 7-40, a read pulse applied to a cathode follower 7-41, Fig. 7c, causes simultaneously two rows and one column to be pulsed, the result being that that core in the pulsed column not in a pulsed row is set " on " to half-read out the similarly numbered row of the main storage matrix. This is immediately followed by a pulsing of every row of the X matrix effected by a write pulse applied to a cathode follower 7-95, Fig. 7c, which resets the core that was turned " on " to produce an output pulse of opposite polarity to that first produced which half restores in the main matrix (unless it is inhibited) the bit that has just been read out. The Y matrix, Fig. 7e, operates in a similar manner to the X matrix except that it is driven directly by A, B and C timing pulses and 1, 2, 4 and 8-bit pulses instead of by two rings of triggers. The inhibit winding of the store, Fig. 7c, is controlled normally by a write trigger 6-45, Fig. 6a, in which each bit read out of the store is temporarily stored. If this trigger is " on " storing a " 1 " just read out of the main storage matrix, a control lead 6-46, Figs. 6a, 7c, is at a low potential and the inhibit winding is not energized at the time of a following write pulse (which resets the X and Y matrices) so that a " 1 " is restored in the matrix store. The inhibit winding is also subject to the overriding control of an A-read signal during an A-period during which it is energized at every write pulse so that data read from the matrix during an A-period is not restored to the matrix. Operation of the store during addition.-Each addition cycle comprises three periods, an A period during which a digit is read (and erased) from the buffer store and entered into the accumulator, a B period during which a digit is read from (and restored in) a selected storage unit and added into the accumulator, and a C period during which the accumulated sum is stored in the buffer store. The whole operation is serial by bit and twelve addition cycles are performed successively to effect the addition of two ten-digit decimal numbers. At the commencement of a series of addition cycles triggers 7-10 and 7-16, Fig. 7c, are set on, whereupon the first read pulses, at 1-bit time, selects cores X1 and Y1 of the X and Y matrices (see also Figs. 5a, 5b) to read out core position I of the buffer store, Fig. 7a (a relay 295 being energized), which position corresponds to the 1-bit of the lowest order digit in the store. The output pulse (if one was stored) is amplified, Fig. 6a, and temporarily stored in a write trigger (from where it is transferred to the accumulator) and when the X and Y matrices are reset by the following write pulse, which would normally cause a 1 to be re-written back in core I of the buffer store, the inhibit winding is energized by an A-read signal which prevents this. Thus the bit in core I is read out and the core is left storing zero. When the next read pulse occurs (at 2-bit time) the row and column rings of triggers, Fig. 7c, will each have received three oscillator 2 (see Figs. 5a, 5b) pulses since the last read pulse so that core X4 will be set on, to select, in conjunction with the core Y2 which is also set on, a core of the buffer store which will correspond to the 2-bit of the lowest order digit in the store. This process continues, the 4-bit being read out by cores X7 and Y3 in combination and the 8-bit (also marked with I in Fig. 7a) being read out by cores X10 and Y4 in combination. During the B-period four bits are read out of and restored in the corresponding core positions of a selected storage unit by core pairs X1 and Y5, X4 and Y6, X7 and Y7 and X10 and Y8. During the C-period the accumulated sum in the accumulator is transferred bit-by-bit to the write trigger 6-45, Fig. 6a, and thence, by the selective action of core pairs X1 and Y9, X4 and Y10, X7 and Y11 and X10 and Y12 to the lowest order digit position of the buffer store. At the end of the C-period the last write pulse to occur turns off a trigger 7-21, Fig. 7c, which, with a column shift relay R291 energized, is turned on again by the next set pulse. This results in one of the oscillator 2 pulses being blocked (see Fig. 5b) from the row and column rings of triggers, whereupon in the immediately following cycle cores of the X matrix are set on in the order X12, X3, X6 and X9 for each period A, B and C, which results in the processing of the second order digits that are to be added. Further cycles follow in a similar manner. Entry of data into buffer store from keyboard.- The manual entry of a number into the computor buffer store is by a ten-key keyboard, the highest order di