Patent GB-1428505-A (GB)
Title: Permutation network
IPC: G06F12/02
Filed: 1973-08-21
Abstract: 1428505 Data processors GOODYEAR AEROSPACE CORP 21 Aug 1973 [25 Sept 1972] 39375/73 Heading G4A A shift network for transferring signals on 2<SP>n</SP> input lines on to 2<SP>n</SP> output lines with an altered order includes one or more rows of data selectors. Each data selector in a given row z has the same number of input channels, one of which is selected under the control of a binary select signal and passed to the output channel of the selector. The input lines are arranged in groups of k 0  lines. The lines of a group are each connected to each of k 0  selectors forming a group of selectors in the first row, such that a line is connected to a different one of the k 0  channel inputs on each selector. The outputs channels of the 2<SP>n</SP> selectors in the first row are connected to the input channels of the next row, if any, the output channels being arranged in groups and each being connected to different input channels of the corresponding group of selectors, and so on from row to row. The network may be used to pass data between an interface and a multi-dimensional access store in such a manner that the data always appears in the interface in the same order. For example the store may comprise 2<SP>n</SP> modules each containing 2<SP>n</SP> bits such that each module contains a different bit of each of 2<SP>n</SP> words. It may be accessed in bit-oriented mode, word-oriented mode, or mixed-oriented mode. Data to be written in to the store or read from the store appears in the interface in a consistent order. Each module is notionally designated by a unique n-bit number M. A bit from a position P (also designated by an n-bit number) in the interface is written in to module P#X, where# denotes modulo-2 addition and X is the n-bit address of the word or bit to be accessed, dependent upon the access mode. During readout a bit from module M is placed in a position P in the interface such that P=M#X. Fig. 3a shows a shift network for use with such a store comprising two rows of data selectors S. The upper row receives a bit on each of 4 input lines L0-L3 The lines are notionally indexed by 2-bit numbers 00-11 (l1, l0) and the address consists of two bits (xl, x0). The output L<SP>1</SP>0 of unit S0, for example, is that on input line (l1, l0+x0), i.e. the data output on L<SP>1</SP>0 is the same as the data on input L1 or L0 dependent on the value of x0. The output L<SP>11</SP>0 of unit S<SP>1</SP>0 is that of line (l1+x1, l0+x0). Thus if X is 01 the data bit on L<SP>1</SP>0 is that on L1, as is that on L<SP>11</SP>0. In general, L<SP>11</SP>=L#+X, so that the network provides the required re-ordering of the data read from or to be written in to the store. The same re-ordering can be obtained by a network (Fig. 4, not shown) using only a single row of selectors. Networks of large size are constructed of several smaller-sized networks. For example if n= 8 there are 2<SP>8</SP> input lines each indexed by an 8-bit vector L, and if the network is constructed of networks with 4 input lines (e.g. as in Fig. 4, not shown) the network would require 4 rows with 2<SP>6</SP> networks in each row. The networks may be designed to produce cyclic shift of the data. For example, with a network having 2<SP>n</SP> input lines n shifts can be obtained, each shift being a power of 2, namely 2<SP>0</SP>, 2<SP>1</SP> ... 2<SP>n-1</SP>. Other shifts may then be obtained by making two or more passes through the network (Figs. 7-10, not shown). For example a shift of 5 may be obtained by a first pass shifting the data one position and a second pass shifting the data 4 positions. In such networks, the units S of any one row r may not all be fed with the same bit state of bit xr of the address, some may be fed only when xr is 1 and others only when it is 0.