Patent GB-908272-A (GB)
Title: Digital computing method and apparatus utilizing algebraic-binary number representation
IPC: G06F7/48
Filed: 1959-12-21
Abstract: 908,272. Electric calculating-apparatus. COSTE, L. E. Dec. 21, 1959 [Dec. 27, 1958], No. 43418/59. Class 106 (1). Computation is carried out using " algebraic binary " (AB) notation, i.e. in which numbers are represented by series a na n-  1 - - - a o  where a r  = 1, 0, or #1 and the value of the number so represented = #<SP>n</SP> a r  2<SP>r</SP>. In this notation the r = o representation is not unique, and logical circuitry is shown for obtaining a representation in which no two digits in adjacent binary orders are alike (this is " rectified algebraic binary," RAB). A procedure for doing this involves converting each " isolated " 1 (i.e. a 1 flanked by 0's, 010) in the binary notation into 110, and each sequence of 1's into 10 ... 01 (this produces a form of RAB called " normal algebraic binary," NAB). Arithmetic operations are carried out on the positive and negative parts separately; for example the binary number 101001111001 becomes NAB 1111010001011, with positive part 1010010000010 and negative part #10#100000#100#1 It will be noted that these parts have no successive non-zero digits, so that if two such numbers are added the separate addition of the parts produces no repeated carries, thus allowing more rapid operation in the parallel mode cornputor the logical circuitry for parts of which is shown in Figs. 2-6 and 12-21 (not shown). Accumulator.-Fig. 1 shows schematically a number of units (logical circuitry in Figs. 2-6, not shown) forming an accumulator with add (ADD) and subtract (SST) command lines, and which receives input binary numbers (parallel mode) at A and B. The two coders TBA convert these binary numbers into positive and negative parts of NAB numbers and pass these via sign selectors IS (enabling subtraction if desired) to adders ADP, ADN for the positive and negative parts respectively. The part sums on UP, UN are passed to a unit SP which suppresses any pair 1, I in the same binary order, so that the output at EP, EN represents the AB sum (or difference, according as ADD or SST is energized). In order that further accumulation may be effected without repeated carry, this is converted by transcriber TR to RAB form, whence it may be routed back to ADP, ADN to be added to a further input at B. An alternative arrangement described with references to Figs. 6-9 (not shown) accepts for addition two input numbers in binary code and forms a sum-without-carries, and a set of carries which are not promulgated; the former is converted into NAB form and a suppressor unit (similar to SP, Fig. 1) suppresses 1, 1 pairs in it and the set of carries, the positive and negative parts of the resultant sum representing the result in a form suitable for further accumulation. Multiplication.-Fig. 10 shows a multiplication matrix receiving two numbers A and B to be multiplied in binary parallel form (m + 1 bits each) on lines AO-AM and BO-BM. And " gates at the intersections provide partial product bits, the binary order of which is given by the horizontal line on which they are located. The product is obtained by adding the partial product bits, taking account of their binary orders, and regarding them as m + 1 binary numbers each (except the last, N m+1  consisting of two " columns " of intersections (it will be observed that of each pair of neighbouring columns N 1 , N 2 , &c., one provides output bits of even binary order, and the other bits of odd order, so that together they may be regarded as providing a single binary number). The final product may be obtained using an adder of the Fig. 1 type and presenting the N numbers successively for accumulation, or a faster addition may be effected by the arrangement of Fig. 11. In this Figure, designed to deal with the output from a 32 Î 32 (m + 1 = 32) matrix as in Fig. 10, eight adders ADD 1-8 receive at t 2  the partial product numbers N 1 ,N 2 ; N 5 , N 6 , &c., and at t 5  N 3 , N 4  N 7 , N 8  &c. At t 4  these adders provide algebraic binary output sums of the first input numbers and these are passed to further " adders " and " totalisers " TOT (logical circuitry in Fig. 8, not shown) until at clock pulse t 21  TOT 10 gives an algebraic binary output representing the sum of the column? N1, N 2 , N 5 , N 6 , N 9 , &c. This is delayed three clock periods and presented, simultaneously with the second sum (of the other columns) which has been built up three clock periods later, to the final adder PTA2, TOT 11 to produce the product. Other logical circuits for determining the sign of an algebraic binary number, for converting such a number to ordinary binary, for simplifying such a number (reducing the number of non- zero bits), and for shifting and converting from parallel to series-mode form and vice versa, are given. A safety code, in which a separate signal line is used to carry signals representing binary 0, is described together with a check circuit for error detection.