Patent GB-1061546-A (GB)
Title: Instruction and operand processing
IPC: G06F9/355
Filed: 1965-06-09
Abstract: 1,061,546. Programming arrangements for computers. GENERAL PRECISION Inc. June 9, 1965 [Aug. 28, 1964], No. 24437/65. Heading G4A. A computer, with a core memory (24, Fig. 1, not shown) utilizes double-instruction words selected sequentially by a counter (12), each instruction including an operand address portion. Each new instruction word is placed in a memory data register (24b). The first instruction is fed into an instruction register (16) and subsequently into an address register (19) and order register (18) when the second instruction is fed into the instruction register (16). A pair of bits in each instruction designates which, if either, of a pair of index registers A, B should modify the operand address portion of the instruction word in the instruction register during circulation through an adder (17). An additional F register augments the operand address in the address register (19) to designate which field in the memory is to be addressed. Each instruction includes a bit which indicates if the F register should be ignored although setting of a flip-flop over-rides the bit indication and all the operand addresses are augmented. The instruction words are selected by an instruction counter (12) which establishes the sequential addresses of instruction words and is incremented at the end of each instruction by circulation through an incrementer (14). During a sub-routine the count is stored in a register C. The A and B index registers may be decremented on programmed commands or replaced by a number in the C register or replaced by a segment of an address in an instruction. A bit counter (20) steps once for each clock pulse and the state of flip-flops in a phase control circuit (22) establishes the operational phase of the computer. The phases for executing A and B instructions and for holding may last for more than one word time, but all other phases last for a single word time. For multiplication and division the number of word times is fixed and entered into the address register (19) which operates as a word counter and is decremented from the initial count at each word time. A branch instruction (BWF) indicated by a set flip-flop (Cm1 causes the computer to change its instruction by addition of the five most significant bits of the instruction counter (12) to the address specified if the sign of the C register is positive or zero. A " Branch 2 " command (BR2) requiring two word times for execution contains a complete fourteen-bit address in the instruction word to which the programme should branch if the branch condition derived from the condition of the A register, tally index register or discrete input, is met. A return address instruction )RBA) locates a word in the memory (24) which is strobed into the C register and thence into the instruction counter. A programme may be interrupted during the last word of an A or B execute operation by setting a flip-flop from the input-output section and the present contents of the instruction counter 12 are stored in the C register. External data may be entered directly into the memory (24). The counter is lightweight and may be used in aircraft.