Patent GB-1506616-A (GB)
Title: Video display apparatus
IPC: G09G3/28
Filed: 1975-06-24
Abstract: 1506616 Video display panel SONY CORP 24 June 1975 [28 June 1974] 26752/75 Heading H4F X-Y matrix type display panel 11 control arrangement comprises "write in" memory circuits W 1 -W k  for the column lines Y 1 -Y k  of the display panel, each circuit including six flip-flop circuits F AI -F FI  into which the binary coded (i.e. six bits) video signal samples from coder 22 and level detector 21 are sequential fed under the control of clock pulses C w  from oscillator 23 which is triggered by the horizontal sync start pulses S II  i.e. the "write in" memory circuits W I -W K  are loaded with each line of video signal samples by shifting each bit along the lateral shift registers W A -W F  formed by the flip-flop circuits F AI -F FK , the lower order bits of each video sample being stored in flipflops F AI -F AK . These bits are transferred, under the  control of three read pulse pairs C R1 -C R3  from oscillator 26, sequentially into "read-out" memory circuits R I -R K  each including two flip-flops and each having only one input, the outputs from the two flip-flops of each read-out memory circuit R I -R K  being fed via resistors R H  and R G  to the Y column line driving transistors T YI -Y YK , the X row lines being driven line sequentially via driving transistors T x1 , T x2 .... In a first mode of operation with the resistors R G  and R H  having different values the lower order bit signals stored in flip-flops F AI  -F AK  and F BI -F BK  are first transferred to flip-flops F GI -F GK  and F HI -F HK . When F GI  and F HI  are in state "0" the transistor T YI  9s non-conductive; when F GI  is in state "1" and F HI , in state "0" a current having an amplitude corresponding to level "1" flows in transistor T YI ; when F GI  is in state "0" AND F HI  in state "1" a current level of "2" flows; and when F GI  and F HI  are in state "1" a current level of "3" flows. In the example described the video signal is divided into 64 levels (i.e. 6-bit binary code) the read pulses C R1 -C R3  being so timed that the period of time for which the two lower order bit signals are held in read-out memory circuits R I -R K  relative to the period for which the next two bit signals and the two higher order bit signals being in the ratio 1:4:16. Thus 64 brightness levels may be displayed, each being the integrated value of the discharging currents.  In a second mode of operation the resistance values R G  and R H  are equal so that the discharging current when F G1  is in state "1" is the same as when F H1  is in state "1". In this mode in addition to the three pairs of read pulses C R1 -C R3  (Fig. 5D, not shown), read pulses C Q1 -CQ 3  are provided timed mid-way between the pulse pairs C R1 -C R3  so that 64 brightness levels may be displayed using only current levels of 0, 1 and 2 the state of flip-flops F G1 , and F H1  being determined by the bits stored in F A1  and F B1 , then F B1  and F C1 , then F C1  and F D1 ,... F E1 , and F F1 , rather than F A1  and F B1 , F C1  and F D1 , and F E1  and F F1  but with current levels 0, 1, 2 and 3 as in the first mode of operation.