Patent GB-1108801-A (GB)
Title: Improvements in or relating to electronic data processing systems
IPC: G06F13/26
Filed: 1965-03-16
Abstract: 1,108,801. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORPORATION. 16 March, 1965 [6 April, 1964], No. 10969/65. Heading G4A. Simultaneous interrupt requests in a storedprogramme computer result in the interrupt of highest priority being executed and information relating to the other requests and the interrupted programme being stored. Scheduling of problem programmes, and of sub-routines, entered on occurrence of an interrupt, is controlled by a monitor programme which provides a programme status word (PSW) for the problem programme and for each type of interrupt sub-routine to hold information needed for correct resumption of previous operation after an interrupt sub-routine has been executed. At any time, one PSW is " active " and controls processing. The active PSW is constantly up-dated. Five types of interrupt are possible, viz. as a result of (a) a machine malfunction, (b) a programme error, (c) a request from an input/ output (I/O) device for servicing, (d) an external request, i.e. from a timer, the console or real time data channels, (e) a monitor call, caused by a programmed macro-instruction and used when a PSW is to be replaced or altered by the programme. A PSW has fields specifying (a) whether and which external and I/O interrupts are to be allowed (" system mask " field), (b) areas of storage accessible to current problem programmes, (c) whether detection of a machine malfunction is to cause the corresponding interrupt, (d) whether the machine should execute instructions normally or wait until an interrupt occurs before doing so, (e) whether the machine is in the problem or monitor state (in the latter only privileged functions can be executed and others will cause an error indication), (f) cause of interrupt, (g) length of current macroinstruction, (h) machine conditions, (i) whether detection of a programme error is to cause the corresponding interrupt, (j) address of next macro-instruction in the current programme. Predetermined storage locations are provided for ten PSW's to hold those not at present active. Five of these locations (" new " locations) are provided for the five interrupt subroutine PSW's respectively and the other five (" old " locations) can be considered to be respectively associated with the first five. Assuming that a problem is being executed and a single interrupt occurs, then the currently active PSW is stored in the " old " location associated with that particular type of interrupt and the PSW in the associated " new " location is read out to be the active PSW. If a further interrupt of higher priority occurs while this sub-routine is being executed, the PSW of the latter is stored in the " old " location associated with the second interrupt and the PSW in the associated " new " location becomes the active PSW, and so on. When a sub-routine has been executed, its PSW is returned to its " new " location and the PSW in the associated " old " location becomes the active PSW. A plurality of simultaneously occurring interrupts are taken in order of increasing priority and the PSW's stored according to the above scheme. The interrupt to be considered last (that of highest priority) is then executed, and after execution accesses the PSW of the interrupt of next highest priority to act as the next active PSW. Thus the interrupt sub-routines are executed in order of decreasing priority. It is important to ensure that a given interrupt sub-routine is not itself interrupted by an interrupt of the same type, or over-writing will occur in the corresponding " old " location and errors will result. This sort of interrupt can be prevented by suitable use of the " system mask " field of the PSW. The priority sequence may also be altered by suitable use of this field. The computer is micro-programme-controlled, and the interrupt becomes effective immediately in the case of types (a) and (b)-see above-and at the end of the current micro-instruction sequence (i.e. macro-instruction) in the other cases.