Patent GB-1482063-A (GB)
Title: Electronic timepiece
IPC: G04G5/04
Filed: 1975-11-27
Abstract: 1482063 Electronic timepieces DAINI SEIKOSHA KK 27 Nov 1975 [11 Dec 1974] 48854/75 Heading G3T In a seconds setting arrangement of an electronic timepiece, to advance the seconds indication a higher than normal frequency display drive signal is applied, and to retard it the display drive is stopped until the correct time is indicated whereupon it is automatically restarted. The timepiece includes a crystal controlled oscillator followed by a frequency divider 2 producing a 1HZ output at 2a which in normal operation is passed by a gate circuit 3 to a display driver 16, e.g. a motor 18 driving hands or alternatively an electro-optical display, and to thirty's counters 19, 20 which operate synchronously. The counter 20 is an up/down counter which normally operates in the up-counting mode as determined by a mode selecting signal applied to its terminal 20c by a control circuit 22. To reset the seconds indication to zero so as to synchronize with the correct time, a switch 24 is manually operated to set a flip-flop 25 when the seconds indication is between 0 and 29 seconds, if the seconds indication is in advance of the correct time; the switch 24 is operated between 30 and 59 seconds if the seconds indication is in retard. Assuming a 5 seconds retard, the switch 24 is operated when the indication is 55 seconds. The counters 19, 20 will contain counts relating to the second 30 seconds of a respective minute and a high level signal will be produced by a discriminating circuit 21. The circuit 21 output signal signifies which half-minute the counter 19 is counting, in response to a carry signal from counter 19 and is applied to the control circuit 22 to select the proper mode for counter 20. The operation of switch 24 closes AND gates 4, 11 thus preventing passage of the 1HZ signal to the display driver and to counters 19, 20. However an output at 32 HZ from a terminal 2b of the divider is permitted to pass via AND gates 5, 6 and OR gate 7 to the display driver, and counter 20 is in the up-counting mode. Five pulses of the 32 HZ are applied to counter 20 in 5/32 seconds so the count therein becomes 30. Thereupon an output from the counter terminal 20a causes a reset circuit 28 to reset counter 19, discriminator 21 and flip-flop 25 so that normal operation is resumed; the count in counter 19 is reset from 25 to zero and that of counter 20 is zeroed, and the seconds display is driven from 55 to zero by the five pulses in 5/32 seconds. Assuming that the seconds indication is 5 seconds in advance, the switch 24 is operated when the indication is 5. The content of counters 19, 20 will be 5. The 1HZ signal to the display driver and to counter 19 is blocked but will be fed via gate circuit 10 to counter 20, the latter being switched to the down-counting mode. Five pulses of the 1HZ signal cause the count in counter 20 to become zero. Consequently an output at terminal 20b causes the resetting of the flip-flop 25 and the count in counter 19 (i.e. 5) is written into counter 20 by a pre-setting circuit 32. Counter 20 is switched to the up-counting mode and normal operation is automatically resumed, five seconds after the 1HZ signal was blocked.