Patent GB-1308711-A (GB)
Title: Combination switch units and integrated circuits
IPC: H01L23/29
Filed: 1970-03-11
Abstract: 1308711 Matrix semi-conductor store ENERGY CONVERSION DEVICES Inc 11 March 1970 [13 March 1969 22 Dec 1969] 11652/70 Heading G4C [Also in Division H1] A voltage memory matrix 2 (Fig. 1) comprises plural mutually perpendicular conductors X 1 , X 2 &c. and Y 1 , Y 2 &c. without direct crossover contact but interconnected at intersection points by memory 4 in series with isolating diode 6; the information being stored thereat in binary form denoted by memory state; e.g. high or low resistance 0 or 1. Switching connecting voltage sources between selected crossover points to set, reset, or readout is performed by connecting each X conductor to a set of 3 parallel switches 8, 8<SP>1</SP>, 8<SP>11</SP> returned to set, reset, and readout lines 11, 11<SP>1</SP>, 11<SP>11</SP> respectively connected over resistor 12 to + V 2 , over resistor 22 to + V, and to + V, over resistor 28 in parallel with readout sensor 31. Similarly each Y conductor is connected to a set of 3 parallel switches 10, 10<SP>1</SP>, 10<SP>11</SP> returned to earth line 30, and the switches may be electronic or contact with selective control means not shown. Memories 4 are set from 0 to 1 by applying voltage between X, Y conductors exceeding a threshold of polarity to pass diode 6 to trigger it into a low resistance condition, which is held until reset by applying voltage for a short duration to produce a pulse of reset current exceeding a predetermined value. Readout is produced by applying voltage between X, Y conductors less than threshold to produce corresponding readout current over resistor 28 when memory is in low resistance condition to operate the sensing means, and substantially zero current when memory is in high resistance condition (Figs. 2A, 2B, not shown). High/low resistance switching in the memories is instantaneous. The matrix (Figs. 5, 6A, 6B) comprises a substrate of N conductivity silicon whose portion 32a has doped P + parallel regions Y 1 , Y 2 &c. formed by masking techniques to form low resistance Y axis current paths. An overlying epitaxial layer 32b of N conductivity material is grown thereon embedding the Y axis conducting regions; the portions of the epitaxial layer overlying these being lightly doped to form P conductivity regions 6a transecting the epitaxial layer to contact the appropriate Y conductor and to form anodes of isolating PN diodes 6<SP>1</SP>, integrated with the conductors and isolated by adjourning N conductivity regions 6c, while the cathode 6b are formed by selectively lightly doping with N conductivity material the upper face of the epitaxial layer over an area adjacent each matrix crossover point. An insulated film 34 with openings 34 a registering with the cathode regions of the substrate is formed, e.g. by air oxidation of silicon and each cathode region 6b is contacted by a deposited strip of, e.g. aluminium on layer 34 extending into opening 34a and below the associated memory 4. The latter may comprise an electrode 4a of amorphous refractory conductive material, e.g. molybdenum, tungsten, niobium, tantalum and oxides, carbides, sulphides of refractory metals, deposited from vapour on a cool substrate. A layer of, e.g. alumina or silicon oxide 4b is deposited on each, e.g. molybdenum layer 4a to overly its edges, and is pierced at 4c to expose a small portion of 4a for application of a layer 4d of memory semiconductor material by sputtering or vacuum deposition; the hole being filled with refractory conductive material, e.g. molybdenum and an upper electrode layer 4e of, e.g. molybdenum is deposited and overlain by a deposited layer of X axis conductor material, e.g. aluminum. A second layer 4b<SP>1</SP> of insulant is deposited over layer 4b prior to deposit of the X layers X 1 , X 2 , X 3 ...X 6 which have enlarged end portions, e.g. 40-2, 40-4, 40-6 for external connection at alternate ends. Each Y axis conductor is connectable by etching window 42 in layer 34 to expose P region 6a of epitaxial layer 32b and depositing aluminium therein to alloy with the  P-type region.  In a modification a matrix has a semi-conductor substrate of which a portion is of P conductivity material overlain by an epitaxial layer of N material grown on the P material. Y axis conductors are doped N + regions on the upper surface of the substrate, while portions of the epitaxial layer are doped to P+ conductivity extending there through to contact the underlying substrated layer, leaving isolated channels in the epitaxial layer above each Y axis conductor electrically connected to the same, as cathodes of the isolating diodes. The P + doped regions insulate the conductor regions are from another, the memory devices and the X axis conductors are positioned directly over the anode regions, and the insulating layer holes may be filled with aluminium. Insulation layer 46<SP>1</SP> (Fig. 6A) is omitted from the memory devices.  In a further modification (Figs. 9 to 11) a memory matrix 2<SP>11</SP> comprises a P type semiconductor substrate 32<SP>11</SP> covered by insulant layer 34<SP>11</SP> with PNP transistor isolating elements 6<SP>11</SP> at each crossover point; the Y axis conductors Y 1 <SP>11</SP>, Y 2 <SP>1</SP>, Y 3  &c. being formed at the substrate surface. A common collector region of P type material is formed by the substrate body into which N type base forming islands 6a<SP>111</SP> are inserted by opposite conductivity type doping, and P type emitter forming islands 6b<SP>11</SP> are located at the substrate surface within the base forming regions 6a<SP>11</SP>. Insulant layer 34<SP>11</SP> has an opening 34a<SP>11</SP> above each transistor 6<SP>11</SP> exposing the upper emitter face and an opening 34b<SP>11</SP> opposite each transistor forming portion of the substrate overlying exposing the base forming region 6a<SP>11</SP>. A conductive strip 47 on insulant 34<SP>1</SP> connects the exposed base to the associated X conductor, and a conductive strip 37<SP>11</SP> for each crossover point connects the associated emitter region 6b<SP>11</SP> exposed by opening 34a<SP>11</SP> to the upper molybdenum layer 4e<SP>11</SP> of the associated memory device 4<SP>11</SP> at each crossover point. Each device is superposed on opening 34c<SP>11</SP> overlying the associated Y axis conductor, e.g. Y 1 <SP>11</SP>, the opening being filled with a layer of aluminium underlying molybdenum memory electrode 4a. The enlarged end portions of conductors X 1 11, X 2 <SP>11</SP> &c. are exposed at openings 52 for external connection, while a conductive coating 54 is applied to a side edge of the substrate for common collector connection to a D.C. source 56 (Fig. 12). In a read and write circuit for the matrix (Fig. 12) the base and emitter of each transistor 6<SP>11</SP> are series connected between X and Y conducductors at the associated crossover point; the respective X conductors being selectively switchable at 51-1, 51-2 &c. to a D.C. negative source. The respective Y conductors are connected to individual mechanical or electronic switching 55-1, 55<SP>1</SP>-1, 55<SP>11</SP>-1 etc.; respective resistors 60-1, 60<SP>1</SP>-1, 60<SP>11</SP>-1 &c. and common line 61 to a positive D.C. source, while the common collectors are all returned to D.C. negative source. For setting, appropriate switches are operated to interconnect appropriate selected X and Y conductors to the D.C. sources to initiate current flow through the transistor baseemitter and set resistor 60-11 to 60-n at the selected crossover point to drive the memory device 4<SP>11</SP> from high resistance to low resistance when amplified collector current flows in the transistor. For reset, appropriate switching is operated to connect the voltage sources so that reset current flows determined by reset resistors 60<SP>1</SP>-1, 60<SP>1</SP>-n &c. For readout the appropriate switch means are selectively operated to couple the voltage sources over readout resistors 60<SP>11</SP>- 1 to 60<SP>11</SP>-n as described. The effects of oxidation of aluminium overlain by other electrode layers, e.g. 37<SP>1</SP> is eliminated. In a further modification (Figs. 13, 13A, 14) an integrated memory matrix 70 on substrate 72 covered by insulant layer 82 has apertures 86 exposing the isolating element disposed laterally of each memory device 78; the lower electrode layer 88 of, e.g. molybdenum being deposited directly on layer 82 and extending adjacently of aperture 86, while a layer 96 of, e.g. aluminium is deposited on an extension 88a of layer 88 and extends into the aperture. Substrate 72 contains spaced N type conductivity regions mutually insulated by P type regions, and plural P type anode region 72c forming individual PN junction diodes extending below apertures 86 for contact by aluminium layers. Transistors may as described replace diodes. Plural X axis conductors are produced in the substrate by doped N+ conductivity narrow regions 74-1, 74-2 &c. and Y axis conductors by deposited aluminium strips 76-1, 76-2 &c. overlying molybdenum or similar strips 81-1, 81-2 &c. deposited on insulant layer 82. The strips, have enlarged terminal portions 76-1<SP>1</SP>, 76-2<SP>1</SP>, 81-1<SP>1</SP>, 81-2<SP>1</SP>, for external connection, and the insulant layer 82 has apertures 84-1, 84-2, 84-3 for connection to the X axis conductors. A further modification (Figs. 15, 15A, 16) comprises a P type substrate 112 within which are doped plural parallel spaced N type regions 112a overlying plural spaced X axis conductors 114-1, 114-2 &c. of N+ material. Plural memory devices are formed on the substrate in rows and columns, and within it on N type strips 112a are formed P type anode regions 112b of PN junction diodes. An insulant layer 123, e.g. silicon oxide and plural apertures 124 are etched to register with anode regions 112b. Plural parallel spaced Y axis conductor strips 116-1, 116-2 &c. of aluminium are deposited over correspond