Patent GB-1453450-A (GB)
Title: Low power electronic calculator system
IPC: G06F11/22
Filed: 1973-12-14
Abstract: 1453450 An integrated circuit electronic calculator TEXAS INSTRUMENTS Inc 14 Dec 1973 [24 Sept 1973 (6)] 58044/73 Heading G4A  An integrated circuit electronic calculator includes a read-only memory, the cells of which are arranged in rows (defined by X lines in the form of conductive strips) and columns (defined by Y lines in the form of elongated regions) on a semi-conductor chip, groups of the Y lines each having a group output line and a single ground line. In response to an address, a X select decoder energizes one of the X lines and a Y select decoder connects one of the Y lines in each group to the ground line and an adjacent Y line to the output line of the group. As described the calculator is pocket size and battery powered having a moulded plastic casing with decimal keys, function keys for the rules of arithmetic and a segmented light emitter diode, discharge panel or fluorescent type of display, the main electronic system being implemented on a single MOS/LSI chip containing about 5,000 transistors in a standard 28 pin package. It incorporates an on-chip oscillator and clock generator and test circuitry. Semi-conductor chip (Fig. 2).-This includes 3 working registers A, B, C (contents of register A being displayed) and two 11 bit flag registers 26, 27 in a memory 20 sequentially addressed by a state counter 21, an arithmetic unit 22 including a bit parallel digit serial adder, carry/ borrow circuit and BCD corrector and the readonly memory unit 30 containing 320 11 bit instruction words read into a register 31. System timing.-Each instruction time (D time) is divided into 11 state times S 0 -S 10  in each of which 4 phase displaced signals # 1 -# 4  are derived from a basic clock. The state times which correspond to the number of digits in a word are derived from the # 1 -# 4  clock in counter 21. Data is always read from memory 20 at #1 and written at #3. The digit times are used for keyboard and display span, there being 10 digit times D 1 -D 10 . Display.-Data from register A is coded into segment signals on 7 lines (SA-SG, Fig. 4A, not shown) with decimal point information on a further line (SP), the segment signal being fed to cathodes (A-G) in a light emitter diode unit or a gas discharge panel. The scanning signals (D1-D9) are connected to anodes (50) which comprise transparent metal film covering the cathodes in the discharge panel or anodes common to all digit segments in a light emitter diode display. Instruction set.-If class bits I 10 , I 9  of instruction word I 0 -I 10  are 00 or 01, the remaining 8 bits represent an address. For register instructions the class bits are 1, 1, bits I 4 -I 8  represent an OP code and bits I 0 -I 3  represent a mask field. If bits I 10 -I 7  are 1000 or 1001 bits I 0 -I 8  represent a jump address. If bits I 8 -I 10  are 101 a flag instruction is represented by bits I 4 -I 7  and a mask by bits I 0 -I 4 . Read only memory (Figs. 6R, 6S, 6T, 6U).- The memory comprises 3,520 memory cells 300 defined by the presence or absence of a gate or thin oxide at a X, Y intersection, X lines 301 being metallization strips and Y lines being P diffusions. One ground line 303 and one group line 304 are provided for each group of five Y lines 302, there being 11 such groups. Each 3 bit Y address is decoded by decoder 39 to select one of the five Y lines in each of the groups. Each 6 bit X address is used to select one of 64 X lines. At each digit time just prior to S3# 4  all lines 314 from the X decoder 36 are charged to "0" or V GG , all lines 312 from the X address register 36 are at "1" or V SS , all the X lines 301 are at "1" or V SS  and all the Y lines 302 are at 0 or V DD . At S3# 4  line 316 goes to 1 or V SS  to isolate lines 314 from V GG , lines 312 are from V SS , and lines 302 from V DD . At S4# 1  the X and Y addresses are applied to lines 312, 307 so that all except one line 304 are connected to V SS , the selected one remaining charged to V GG  so that the gate of the associated selected device is at 0 or V GG  and in each group of Y lines 302 all except one discharges, the remaining one being at V DD . At S4# 2  line 320 goes to V GG  so that the line 302 associated with the selected device 321 goes to V GG  or zero. This turns on the gates 300 in each of the 11 sections for the selected X line to provide an 11 bit output signal on line 304 for loading into the instruction register 31, which comprises an 11 stage shift register, I 0 -I 10 , stages I 1 -I 5  providing the next X address to input A1-A5 of the X register 36 and stages I 6 -I 8  providing inputs A6-A8 of the Y address register 37 when a JUMP signal occurs on line 335.