Patent GB-1104279-A (GB)
Title: Pulse generator for time division multiplex system
IPC: H03K3/53
Filed: 1966-03-04
Abstract: 1,104,279. Multiplex pulse signalling. INTERNATIONAL STANDARD ELECTRIC CORPORATION. 4 March, 1966 [11 March, 1965], No. 9545/66. Heading H4L. A time division multiplex pulse communication system includes a combination of high-speed and low-speed channels and the invention relates to pulse generating means which are provided at the receiver for demultiplexing the composite signal. The system described includes 25 channels per frame (high-speed channels C) at least one of which is subdivided to provide medium speed (class B) channels. 24 Class B channels are provided for each class C channel at least one of these channels being subdivided to provide thirty-two low-speed (class A) channels per class B channel. The synchronizing signal for the B channels is arranged to be a blank at every 24th class C framing pulse, i.e. at the start of each class B frame except for the class C framing pulse which occurs at the start of each class A frame. High-speed class C channels.-As shown, the incoming signal from a source 101 is supplied via amplifier 111 to filter and shaper 112 to derive the master clock rate (1.44 Mc/s.). The signal from amplifier 111 is also retimed by AND gate 113, controlled by the timing signals developed at 112, and supplied to the class A line gates 114 and the class B gates 115, 115a. Assuming that the system is synchronized, a blocking oscillator 116 will fire at each synchronizing period, both the search " bi-stable trigger 117 and " counter control " bi-stable trigger 118 being in the " O " state. A tapped delay line 119 produces from the output of blocking oscillator 116 gating pulses for the class C channels which are applied to gates 114. The channel 12 gate pulse is supplied via AND gate 103 (opened by the " 0 " output from triggers 117, 118), to OR gate 121 and is returned at AND gate 122 to retrigger blocking oscillator 116 and start a new pulse into the delay line. When the first pulse in delay line 119 reaches tap 123 disposed between the taps for channels 12 and 13, INHIBIT gate 124 controlled by the clock pulses from 112, passes a pulse to set trigger 118 to its " 1 " state. This closes AND gate 125 and the output of delay line 119 for channel 13 is blocked. At this time the second pulse from oscillator 102 appears at the beginning of delay line 119, and the output of tap 1 together with the " 1 " output of trigger 118 gates channel 13 via gate 114c. When this pulse appears at tap 12 it cannot now pass via AND gate 103 but is applied via tap 123 and gate 124 to reset trigger 118 to " 0 " which enables gate 125. Thus when the pulse reaches tap 13 a pulse is fed back via OR gate 121 to trigger blocking oscillator 102 for the start of the next cycle. Synchronous error detection for class C channels. The output of gate 125 occurs in the class C framing pulse time and is compared in an INHIBIT gate 126 with the incoming signal and the clock pulses from 112. Whenever a pulse is present in the signal the gate 126 is blocked but if a pulse from gate 125 does not coincide with a pulse in the signal an error pulse is fed into integrator 127. Integrator 127 ensures that a predetermined plurality of error pulses are required before the " search " flipflop 117 is set to " 1 " so that the search will not be initiated when the synchronizing signal for the B channels occurs. Assuming that the required number of errors has been detected, trigger 117 being in its " 1 " state, gate 120 is disabled to block any pulse from delay line 119. When the unwanted pulse reaches tap 123 trigger 118 is changed over to " 1 " so that gate 125 is disabled. The outputs of triggers 117, 118 enable gate 128 to pass the incoming signal via OR gate 121 and AND gate 122 to trigger the blocking oscillator 102 and start a new cycle. The output of AND gate 128 also resets triggers 117, 118. When a pulse appears again at tap 13 the comparison at gate 126 is repeated and when a sufficient number of errors have been detected at 127 the search cycle starts again and is repeated until the synchronizing signal is located. Low-speed class B channels.-As described the first two class C channels of each frame are gated out by AND gates 115, 115a with trigger 118 in its " 0 " state to form the class B channels. Assuming that the system is synchronized, at the start of a class B frame triggers 129, 130 are in the " 0 " state and a pulse from oscillator 131 is supplied to delay line 132 controlling the channel gates in conjunction with trigger 129. When the pulse reaches tap 12 a gate 133 is enabled to supply a pulse via OR gate 134 and AND gate 135 to retrigger oscillator 131. The first pulse reaches tap 136 and via gate 137 sets " count " trigger 129 in its " 1 " state. The second pulse now reaches tap 1 and when it reaches tap 12 supplies a pulse via gates 138, 134. 135 to start the next cycle. The output of gate 138 is also supplied to the INHIBIT gate 139 which with the output of INHIBIT gate 126, clock pulses from 112, and the class C frame pulse from gate 125 determines whether the class B frame pulses are at the correct time. Since the class B synchronizing signal is recognized by the absence of a class C synchronizing pulse at the start of a class B frame except where this coincides with the start of a class A frame, pulses at the output of gate 126 define the class B frame pulse and with correct synchronism there will be no output from gate 139. Synchronous error detection for class B channels.-When a synchronous error occurs a pulse is fed to an integrator 140 which sets trigger 130 to its " 1 " state after a predetermined number of errors. When the pulse from oscillator 131 initiated by the pulse from gate 138 reaches tap 136, trigger 129 is set to " 1 " and gate 141 enabled so that the next error pulse from gate 126 triggers oscillator 131. Triggers 129, 130 are reset to " 0 " by the output of gate 146 and a normal counting cycle is established again. Low speed class A channels.-The output of gate 138 together with that of gate 125 provides via AND gate 142 a framing pulse for the A channels controlling via INHIBIT gate 149 the class A pulse generator consisting of a binary counter 144 to 148. Class B channels 1 and 2 are gated out by AND gates 143, 143a to form the class A channels. If the counter is synchronized the pulse appearing at the output of gate 139 will appear one bit after the counter has reached its full count. This count is taken from matrix 150 (which is connected to the counter and controls the channel gates) by AND gate 151 and used to inhibit the frame pulses at gate 149. The output of gate 151 also enables AND gate 152 so that the counter will wait for the next pulse from gate 139 to return the counter to zero. The pulse from gate 139 will appear as a frame pulse while the counter is synchronized but if synchronism is lost the counter will wait at a full count until a pulse appears from gate 139.