Patent GB-1014824-A (GB)
Title: Stored programme system
IPC: G11B20/16
Filed: 1962-07-17
Abstract: 1,014,824. Digital computers. SPERRY RAND CORPORATION. Julv 17. 1962 [Sept. 13, 1961], No. 27324/62. Heading G4A. A computer in which the performance of an instruction normally requires two machine cycles, an " acquisition " cycle and an " execution " cycle, is capable of performing sequential instructions in overlapped relationship thereby making a fuller use of the arithmetic unit. The computer has two separate memories each capable of storing instruction and data words, the two memories being capable of being referenced simultaneously. If an instruction word requires an operand from the memory from which the instruction word was acquired, the overlapping feature is inhibited during the performance of this instruction. Word formats.-The computer word length is 25 bits, which includes one parity bit. An instruction word consists of a 6-bit operation code portion, a 4-bit index address portion j and a 14-bit memory address portion S which after possible modification by indexing is designated T. Data words are represented in fractional binary notation, negative numbers being represented by the 2's complement of positive numbers. Timing.-A machine cycle consists of a 5Ás period, a normal instruction requiring two such cycles for its performance the first cycle being for the acquisition of the instruction and for an indexing operation and the second cycle (the " execution " cycle) being for the acquisition of the operand and the execution of the operation code. Normally, the execution cycle of a current instruction coincides with the acquisition cycle of the next instruction. General arrangement.-The general arrangement of the computer is shown in Figs. la, 1b, the letters A, C, I/O, M or E external to various components indicating that the corresponding components belong to the arithmetic, control, input-output, memory or error units respectively. (1) Control section (a) Programme address counter P.-This contains the 14-bit address of the next instruction and is normally stepped by one, but a SKIP instruction causes stepping by two and a JUMP instruction forces a new address into the counter. (b) Instruction register.-An instruction read from either the permanent memory or the variable memory is transferred to a register U whence it is transferred with index-modification if necessary to a register U*, stages 0-5 of which supply the command translation circuit, stages U* 10-23 holding the T number indicating the operand address. (c) Command translator circuits.-These sense the six highest order bits of the instruction register and translate each of the 35 possible operation codes to a set of command enables. (d) Subcommand and memory access control. -The first function of this circuit is to control the computer during repeat, skip or extended sequence (e.g. divide, multiply) instructions. The second function is to control the memory access circuits of both the permanent and variable memories. (e) Interrupt and data transfer control.-The interrupt facility provided enables the acceptance of interrupt signals from both external and internal units. Interrupt signals are assigned a priority. On occurrence of an interrupt signal, all other interrupt requests are inhibited for six instruction times so that an interrupt programme can be performed. At the end of this time a further interruption request can be processed or the original programme can be resumed. In the case of I/O data transfer, the six instruction time inhibition does not occur. (f) Main pulse distributer.-This produces the computer clock pulses, sixteen pulses MP0-MP15 being required for a machine cycle. (g) R memory access and control.-These circuits proved for the R reference (index) memory an output register R, input OR gates, a counter for adding unity, if required, to the number entered. (2) Memory.-This comprises three independent units: the reference (index) or R memory; a variable memory, and a permanent memory. (a) The R (index) memory is a small, destructive read out ferrite core memory capable of storing fifteen 14-bit words and is addressed by stages 6-9 of the U* instruction register. (b) The variable memory is a medium size destructive read out magnetic core store combining 2048 locations capable of storing a 24-bit word and is associated with an inputoutput register O and a memory address register V. A parity bit is generated when a word is sent to register O for storage. This parity bit is stored with the word and checked on read-out. The address register V also has a parity checking arrangement. (c) The permanent memory is large non- destructive read out store using permanent magnets arranged on cards, capable of storing 10,240 24-bit words and used for storing instruction and constants. A twistor matrix is used to sense the presence or absence of a magnet for the bits of the word addressed. An address register V and an output register Z are provided. The permanent memory has parity checking arrangements similar to the variable memory. (d) Twistor input switch.-This receives data from certain external units and makes it immediately available. It comprises 48 locations for 24-bit words and employs the same address and output registers and parity check arrangement as the permanent memory. (3) Arithmetic unit.-This unit performs the operation of addition, subtraction, multiplication, division, square rooting, shifting and masking and comprises arithmetic registers X, Q, A, sequence control circuits ASC and a shift register K, the registers Q, A, K being double rank registers. The arithmetic unit is described in Specifications 960,951 and 1,014,825. (4) Input-output.-The input-output section functions as a buffer for the exchange of data between the computer and the external equipment, communication being effected on two channels, channel 1 communicating with " critical " external units and channel 2 with " non- critical " external units. Function registers F1, F2 receive the function codes from the control section, translate them and provide control signals for the data transfer. A register D serves as a buffer during transfer involving a typewriter or tape units, means being provided for converting a 24-bit computer word to 6-bit characters for the tape or typewriter. (5) Error circuits.-Means are provided for detecting programme-generated and hardwaregenerated errors. The various registers and memories are described in detail in the Specification (Figs. 2-44, not shown). Principal operations involving overlap. (1) Normal overlap.-When different ones of the memories V, W are referenced successively for instruction and operands, the " acquisition " cycle of the next instruction coincides with the " execution " cycle of the present instruction. (2) Overlap inhibition.-If the next instruction is required from the same memory as the current operand, the overlap feature is inhibited for one machine cycle. (3) Extended sequence.-For certain operations, such as multiply, divide, square root and shift, the execution time takes more than one cycle. In such cases the programme unit is cleared of the initiating instruction word and instructions are withdrawn from the memories, these instructions being performed if they do not require access to the arithmetic unit. (4) Instruction jump.-In a jump instruction in which the jump is made in programme sequencing from the address in the programme counter to an address in the instruction word itself, the programme counter is inhibited for one machine cycle. (5) Instruction skip.-In a skip instruction, the programme counter is stepped by two instead of by one. (6) Data transfer.-When an instruction calls for input-output data transfer on channel 1 or on channel 2, the T address portion of the instruction is transferred to the register F1 or F2 to control the direction of transfer and the particular unit involved via the associated C1 or C2 register. An indication that the C1 or C2 register is ready to receive or transmit data causes an input-output data transfer instruction to be transferred to the instruction register thereby interrupting the main programme for one machine cycle so that the variable memory V can be referenced at a location determined by an address in the R memory. Transfer of data words under the control of an instruction in the F1 or F2 register is interspersed with the acquisition and execution of main programme instructions, the number of words transferred being determined by data in the R memory. (7) Interrupt.-The computer programme is interrupted for the performance of a subroutine either by a programmed " interrupt " instruction or on the occurrence of certain conditions such as an error signal. (8) Repeat.-A repeat instruction causes the instruction next following it to be executed a number of times specified by the contents of an address location in the R memory. (9) Illegal values.-If, during any sequence of computer operations an " illegal " (i.e. improper) address is sensed in the programme register P or an " illegal " operation code in the instruction register U, the overlap operation is modified. In the former case, the " illegal " address is held in the register P and the error circuits inform the operator that an error has occurred, the register P then being capable of being cleared manually. In the latter case, the address from which the instruction was obtained is referenced a second time and if there is no error, normal operation is resumed. If an error is again detected, appropriate action (not described in the Specification) is taken.