Patent GB-980453-A (GB)
Title: Improvements in or relating to relay arrangements
Inventor: PILLING HAROLD WILLIAM CLIFF
IPC: G06G7/28
Filed: 1960-11-24
Abstract: 980, 453. Electric analogue computers. GENERAL ELECTRIC CO. Ltd. Nov. 24, 1961 [Nov. 24, 1960], No. 40437/60. Heading G4G. [Also in Divisions H2 and H3] An inverse-with-definite-minimum-time-lag overcurrent relay arrangement A comprises static means 4, Fig. 1, for producing an output signal whose magnitude bears a predetermined inverse relationship to the magnitude of the current in a protected supply line 1, a timing circuit 5 responsive to the magnitude of the output signal and providing a delay related to that magnitude, a trigger unit 6 to render the circuit 5 effective at a predetermined current in the supply line and relay means operated by the timing means. In the system shown in Fig. 1 this relay arrangement A may be rendered directional by an arrangement B and an instantaneous overcurrent relay 62 may be provided. The arrangement A includes a current transformer 2 and an input unit 3, Fig. 2, the latter comprising an auxiliary transformer 8, rectifiers 9, 10, smoothing capacitor 12 and inductance 13, and an adjustable shunt circuit 14. The circuit 14 comprises a transistor 17 and resistors 15, 16 and since the current flowing through the resistor 16 varies with the load current I 2  of the means 4, the transistor shunts a fixed proportion of the current from the transformer 8. The static means 4, Fig. 3 comprises a transistor 22 acting as constant current shunt, a non-linear resistance arrangement having resistors 18, 19 and diodes 20 which successively become conducting as the input voltage from the input unit rises so as to reduce the rate of increase of the voltage at a point 21 relative to that of the input voltage. The voltage at point 21 is applied to the base of a transistor 25 so that the output voltage taken from the collector becomes less negative as the voltage at 21 increases i.e. this output voltage varies inver sely with the line cur - rent. The trigger unit 6,Fig.4 has a stable state in which atransistor 28 is cut off, a transistor 29 is conducting and a negative signal is provided by the collector voltage of the transistor 28. When the input voltage to the base of transistor 28 derived from the resistance arrangement 18.. 20 and dependent on the magnitude of the line current, exceeds the emitter voltage, transistor 28 conducts, transistor 29 is cut off and the collector voltage signal is about zero. The time delay circuit comprises a transistor 42, Fig. 5 which is normally conducting and a transistor 43 which is cut off, the trigger unit 6 applying a negative potential through a diode 56 to prevent the charging of a capacitor 52 which is connected to the collector of transistor 25 of the means 4. When an overload occurs, the trigger unit 6 functions to reverse bias the diode 56 and the capacitor 52 charges to a potential sufficient to cut off the transistor 42 and cause the transistor 43 to conduct to energize a relay coil 44, the charging time being reduced as the transistor 25 collector potential is reduced to increase in line current so providing an inverse time delay. In a modified arrangement, Fig. 6 (not shown) a constant current charging circuit including a transistor is connected between the transistor 25 and the capacitor 52. The directional arrangement B comprises a transistorised current input circuit 64 for producing two antiphase sets of half cycle impulses, Fig. 7 (not shown) and a voltage input circuit 65 energized from a voltage transformer 63. This circuit 65 includes opposed parallel diodes which clip the input voltage to a low amplitude square wave which is then differentiated by a transistor arrangement to produce short pulses on alternate half cycles, Fig. 8 (not shown). The half cycle impulses V 1 , V 2  and the short pulses V 3  are applied to a pair of AND units 82, 83. Fig. 10 and the outputs from the AND units individually form one input to NOR units 86, 87, each NOR unit receiving its second input from the other NOR unit. When say V 1  and V 3  are coincident there is an output from AND unit 82 and no output from unit 83. Hence there is no output from NOR unit 86 and an output is obtained from unit 87. The outputs from the NOR units are used to control the unit 5. Each AND unit includes a pair of diodes and the NOR units together form a transistorised bi-stable flipflop circuit, Fig. 11 (not shown).