Patent GB-1435791-A (GB)
Title: Electronic timekeeping system
IPC: G04G99/00
Filed: 1973-05-14
Abstract: 1435791 Electronic watches TEXAS INSTRUMENTS Inc 14 May 1973 [19 June 1972(7)] 22797/73 Heading G3T [Also in Divisions G4 and H3] A battery powered electronic timepiece with digital liquid crystal display comprises a current regulator means for producing constant current from the battery source, a crystal controlled oscillator 18 Fig. 2 followed by an integrated circuit frequency dividing chain of bipolar toggle flip-flops (ripple counter) 20 which produces 1Hz clockpulses and is driven by said constant current. These pulses are applied to synchronize all counters 22, i.e. seconds counter 22a 22b, minutes counter 22c 22d, hours counter 22e and date counter 22f 22g. The counters increment in response to each clockpulse only when enabled by a signal from the previous counter. Output signals from the counters are fed via respective de-coder circuits 24 to drive circuitry 26 the output of which controls the liquid crystal display 12. Individual time setting switches are provided for seconds, minutes, hours, date. The hours can be set without incrementing the date. A twelve or twenty-four hour mode can be selected and an AM/PM indicator 36 is provided. Toggle Flip-Flop Divider 20, Fig. 10A. The frequency divider or ripple counter 20 comprises fifteen toggle flip-flops (as detailed) Fig. 10A each comprising a bipolar master/slave floating master D.C. coupled flip-flop utilizing Schattky transistors and diodes T 4 , T 5 , D 1 , D 2 . Transistors T 1 , T 2  are the masters while T 3 , T 4 , T 5 , T 6  are the slaves. In operation, with T6 biased ON and receiving collector current from one of the emitters of Schottky transistor T 4 , no base drive is available for T3 and its collector is high. Assuming no clockpulse applied to a terminal T7, the master will move toward supply potential V cc  and will be clamped to ground via the Schattky diode D 1  and the collector of T 6 . This causes T 2  to turn ON diverting base current from T 1  to ground. When a clockpulse is applied to terminal T 7  to switch the flipflop, current is transferred from one emitter to the other of transistor T2 and flows out via the clock line. When terminal T 7  approaches ground potential the base current of Ts flows out via an emitter and saturated transistor T 2  to ground. With no base drive, T6 turns OFF its collector going high so that two high potentials will be applied to the emitters of T4 and its base drive flows out of its collector to the base of T 3  turning it ON. The flip-flop is now in its stable state. If the clock signal now turns OFF, the master is switched to its opposite state and is clamped to ground via D 2  and collector of T3. When the clock signal again goes low, current passes from an emitter of T 4  via T 1  and terminal T 7  so that T 3  is deprived of base current and turns OFF. There are thus two high potentials on emitters of Ts so that base current for T 5  now flows into T 6  and turns it ON again, completing one toggle cycle. The divide by 24 logic Fig. 21, (not shown), uses toggle, RS Fig. 11, (not shown) J-K flip-flops Fig. 12, (not shown). The divide by 31 logic Fig. 24 (not shown), has a divide by 10 and a divide by 4 counter comprising RS flip-flops. D.C./D.C. Converter - Fig. 32a. High voltage (15V) square waveform for activating the liquid crystal, is produced by a converter from the 1 volt battery supply. A transistor Q and a transformer T form a blocking oscillator. A.C. voltage produced in winding W 1  is peak to peak doubled by a voltage doubler circuit C 1 , D 1 , D 2  the output voltage of which is stored in C 2 . Oscillator/Amplifier. Fig. 5. This oscillator comprises an amplifier Q 2  Q 3 . A constant current source Q 6  eliminates requirement for large ohmic value resistors. Bias stabilization for the oscillator is provided by feedback from the collector of Q 3  via a transistor Q 1  strapped as a diode. The total collector current from source Q 6  to the oscillator is determined by feedback from the collector of Q 5 . When current is first turned ON only Q 7  conducts so that the collector potential of Q5 rises until a Schottky diode D1 and Q4 conduct, turning ON Q6 sufficient to maintain D 1  Q 4  slightly conductive at the most positive peaks of the oscillator output. Thereby stable bias operation is maintained. Current regulators 16a, 16b (Fig. 2) and Fig. 31 (not shown), are connected to the logic circuitry to ensure a constant current source regardless of variations in the supply battery voltage or load.