Patent GB-1490715-A (GB)
Title: Methods of forming a conductive pattern on a supporting body
IPC: H01L29/73
Filed: 1974-12-06
Abstract: 1490715 Semiconductor devices; printed circuits PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 6 Dec 1974 [10 Dec 1973] 52864/74 Headings HlK and H1R A method of manufacturing an electrical device including a pattern of conductors on a substrate comprises providing an auxiliary layer on the substrate with apertures corresponding to part of the pattern, depositing a layer of conductive material over the auxiliary layer and apertures, selectively removing at least the upper surface of the auxiliary layer together with the part of the conductive layers on top of it, leaving a first part of the pattern of conductors, providing a second auxiliary layer on the substrate and conductive pattern and repeating the process to form a second part of the pattern. The conductor pattern may be the base and emitter metallization of a transistor and the method allows inter-conductor spacings of less than 1 micron. As shown in Fig. 5, the transistor comprises an, e.g. n-type collector zone 5, a diffuser or implanted base zone 6 having a highly doped contact zone 6A and a less highly doped zone 6B in which emitter zone 7 is formed by diffusion or implantation. Over the substrate partially coated with insulation 8, e.g. silicon oxide or nitride an auxiliary layer is deposited which preferably as shown consists of two layers 9A, 9B. Layer 9A may be Al, Cu, Mg or Ag and layer 9B Cr, Ti, Pd, Mo, W, Ta, Ni or Au. Using a photoresist mask 10, apertures are etched in the auxiliary layer in two stages. In a first stage, apertures are etched in layer 9A, and in a second apertures are etched in 9B with undercutting, layer 9B optionally functioning as the etching mask for the second stage. The assembly is coated by vapour deposition or the like with a conductive layer different from the auxiliary layer and which as shown in Fig. 1 consists of a layer 3A which adheres well to the substrate, e.g. Ti, Cr, Rh, Zr, Ta, W, Mo and a layer 3B chosen for its conductivity, e.g. Pt, Rh, Co, Mo, W. By etching away the remainder of the auxiliary layer 9A, 9B with concomitant removal of the conductive layer on top of it, a first part of the conductive pattern is left, which provides the base metallization. A second auxiliary layer, comprising layers 11A, 11B (Fig. 9) deposited as before and apertures formed therein over the emitter regions. A further conductive layer is applied by vapour deposition or the like, comprising as shown in Fig. 9 layer 4A, e.g. Ti, Cr, Rh, Zr, Ta, W, Co, Mo, layer 4B, e.g. Pt, Rh, Co or Mo and layer 4C of gold. The second auxiliary layer is now etched away with concomitant removal of the conductive layer a top of it to leave a second part of the conductive pattern providing the emitter metallization. Since this is formed separately from the base metallization it may be thicker or otherwise formed to provide for greater required current-carrying capacity. In modifications the first and second parts of the conductive pattern may partially overlap, without intervening insulation (Figs 10, 11, not shown) or with intervening insulation such as glass (Figs 12 to 14 and 18, not shown) the latter embodiment being used in forming charge coupled shift registers. In a further embodiment (Figs 15 to 17, not shown) only the top layer of a two component auxiliary layer is completely removed, the bottom layer, in this case tungsten or polycrystalline silicon forming part of the conductive pattern, in particular the collector connection. The auxiliary layer need not be metal or conductive, e.g. it may be a photoresist and an effect similar to undercutting may be achieved by applying the activating radiation at an angle.