Patent GB-863669-A (GB)
Title: Improvements in or relating to synchronising arrangements for electric pulse code modulation systems
Inventor: CATTERMOLE KENNETH WILLIAM
IPC: H04N5/213
Filed: 1959-09-08
Abstract: 863,669. Pulse code modulation systems. STANDARD TELEPHONES & CABLES Ltd. Sept. 8, 1959, No. 30617/59. Class 40(5) In a multi-channel pulse code modulation system employing a code of n digits, of the type in which a synchronizing combination of digits is transmitted over a particular channel set aside as a synchronizing channel, the receiver comprises means operative upon non-reception of the synchronizing combination to cause different successions of n digits to be selected from those received until a synchronizing combination is detected. The system described has 24 channels, channel 24 being the synchronizing channel, and uses a 7 digit, unit-disparity code, i.e. each combination comprises either three or four digit pulses. The combinations 1111000 and 0101111 are used alternately for synchronizing and are referred to as the A and B combinations. Each transmitted code combination comprises eight digits, the eighth being used for supervisory or control signals in the corresponding channel, and being ignored by the decoder. Alternate frames A and B differ in that in the A frames the eighth digit conveys one supervisory signal and in the B frames conveys a different supervisory signal over the same channel. At the receiver, Fig. 1, the incoming pulses are supplied via a conductor 31 to a seriesparallel converter 32 and also to a clock pulse generator 35 which via a gate 36, which is open only when the receiver is in synchronizm, synchronizes a digit counter 34 controlling the converter 32. Each signal code combination comprising digits 1 to 7 is converted at 38 into a corresponding amplitude modulated pulse and delivered over a conductor 40 to a channel distributer 41. In response to the A and B synchronising signals, short pulses are supplied via conductors 42, 43, respectively to a supervisory signal distributer 44 which also receives the supervisory signals corresponding to digit eight. The supervisory signals are passed via conductors 45, 46, to the channel distributer 41. A ring counter 47 provides pulses to the twentythree conductors 48 to control the channel distributer 41, and through the twenty-fourth conductor to operate an electronic switch passing the channel A or channel B supervisory signals to the respective conductor 45 or 46 in alternate frames. The counter 47 is controlled in conventional manner by a clock pulse generator 51 which is synchronized by the digit one pulses supplied through a normally open gate 53. When the receiver is correctly synchronized either the A or B synchronizing combination is recognised by the decoder 38 during every channel 24 period and a search control pulse is supplied over conductor 54 to a search control unit 55, which also receives the digit eight output pulse from the counter 34, and the channel 24 distributer pulse. When synchronizm is lost, no pulses are delivered over conductor 54 and the unit 55 supplies a pulse which shuts the gate 53 and stops the pulse generator 51. At the same time the unit 55 supplies a pulse via conductor 57 to reset the counter 47 in its channel one position. Meanwhile in response to each digit eight timing pulse from the counter 34 the unit 55 delivers a pulse of duration equal to three code elements to shut the gate 36 so that the counter 34 fails to count three pulses in each cycle. The counting cycle is then eleven instead of eight clock pulses and in this way every possible selection of eight successive digits will be tried until one of the synchronizing combinations is selected by the decoder 38, and normal functioning is resumed. The decoder may be of the type using bistable magnetic cores, two additional cores being provided carrying digit windings corresponding to the A and B synchronizing signals which provide a pulse to control the unit 55 in response to either signal, and operate a flip-flop one way or the other only if the system is in synchronizm, to switch the supervising pulses to the corresponding conductors 45 or 46. The search control unit 55, Fig. 3, comprises a pulse generator 70 which in response to a digit eight pulse from the counter 34 produces an inhibiting pulse (three digit periods) controlling via a gate 71 the gate 36. The search control pulse over conductor 54 is supplied via a gate 74 to a pulse generator 75 which normally produces a positive potential at its output, but in response to each search control pulse produces a rectangular negative-going pulse. In the absence of a negative pulse from the generator 75 a two-condition amplifier 76 is in the "search" position and produces a positive potential on the conductor 57 to reset the channel counter 47 and provide one input to the gate 72 the other input being supplied from the pulse generator 75. Thus the gate 71 will be open to allow the pulse from the generator 70 to close the gate 36 for three digit periods. Under these conditions a negative potential is produced at the output 78 of the amplifier 76 which shuts the gate 53 and stops the pulse generator 51. The positive potential on the conductor 57 through the gate 79 holds open the gate 74 to permit any search control pulse which may arrive, to control the generator 75. When a search control pulse is received the pulse from the generator 75 changes the amplifier 76 to the "lock" condition and its output potentials are interchanged. The gate 53 is opened and the pulses from the generator 70 blocked. The two-condition amplifier 76, Fig. 4 (not shown) comprises a pair of transistors connected as a long-tailed pair coupled via Zener diodes to a similarly connected pair of transistors. When no search control pulses are being received a capacitor in the input circuit is charged and holds the amplifier in the "search" position. When a search control pulse is received the capacitor is discharged rapidly through a further transistor and the amplifier assumes the "lock" position and is held in this position if the pulses are regularly received. The time constant of the capacitor circuit may be arranged so that several search control pulses may be missed before the capacitor is recharged to initiate the search. In a modification, Figs. 6 and 7 (not shown), the amplifier 76 is replaced by several bistable devices in cascade and the capacitor charging circuit is dispensed with.