Patent IE-802121-L (IE)
Title: Mos switching circuit
IPC: H03M7/12
Filed: 1980-10-13
Abstract: 1. MOS switching circuit for converting the code of an n-position binary number (n > 3) into the code of the associated, at least two-place decimal number with the aid of MOS-gates which are controlled by the respective binary position signals or the complement thereof, corresponding to the binary positions of the binary number, characterized by the following features : - for the ten digits in the units place (DE1 ... DE0) of the decimal numbers (D1 ... D32) there is provided each time one NOR-matrix (1 ... 10) with s times z transistors arranged in a row- and column-wise manner (s = number of columns, z = number of rows), - in each NOR-matrix (1 ... 10) the controlled current paths of the transistors of each row, hence the row transistors, are arranged in parallel with one another, and the controlled current paths of the transistors of each column, hence the column transistors, are arranged in series with one another, with the one end of each series arrangement being applied to the zero point of the circuit, and with the other end thereof, via a load transistor (LM1 ... LM10) which is common to all columns per NOR-matrix (1 ... 10), being applied to the supply voltage (+UB ), - the number of columns s of the respective NOR-matrix (1 ... 10) equals n, - the number of rows z is in the utmost equal to the number (d) of the decimal decades (DK) contained in the decimal number range (DB) as represented by the n-position binary numbers (B1 ... B32), - to each row of the ten NOR-matrices (1 ... 10) there is assigned one of the binary numbers (B1 ... B32) in such a way that in each NOR-matrix the binary numbers (B1, B11, B21, B31, etc.) are combined with the same decimal units digit (DE1 ... DE0), i.e. in such a way that the row as applied to the zero point of the circuit belongs to the binary number (B1 ... B10) with this decimal units digit from the lowest decimal decade (DK1), that the row which is the next higher one in direction towards the common load transistor (LM1) belongs to the binary number (B11 ... B20) with the same decimal units digit from the next higher decimal decade (DK2), and so on up to the row applied to the load transistor (LM1) which belongs to the binary number (B31, B32) with the same decimal units digit from the highest decimal decade (DK4), - to the gate electrodes of the row transistors in a row belonging to one individual binary number (B1 ... B32) there are to be applied the position signals (A, B, C, D, E) of this binary number or else the complement thereof (~A, ~B, ~C, ~D, ~E) so that in this way all row transistors of this particular row are switched to the non-conducting state, - moreover, there is provided a multiple-NOR-gate (11) having p columns (S1 ... S4), with p being equal to the number (d) of the decimal decades (DK1 ... DK4) as contained in the decimal number range (DB) of the binary numbers (B1 ... B32), - to each column (S1 ... S4) there is equidirectionally assigned one decimal decade (DK1 ... DK4) (S1 = DK1, etc.), and this particular column consists of transistors (TS ...) arranged parallel in relation to one another with their controlled current paths, arranged between one common load transistor (LS1 ... LS4) and the zero point of the circuit, - the gate electrode of respectively one transistor (TS11 ... TS91) of the first column (S1) is applied to the output of the rows of the first nine NOR-matrices (1 ... 9) associated with the first nine binary numbers (B1 ... B9), - the gate electrode of respectively one transistor (TS02 ... TS92) of the second column (S2) is applied to the output of the rows of the ten NOR-matrices (1 ... 10) as associated with the following ten binary numbers (B10 ... B19), - the gate electrode of respectively one transistor (TS03 ... TS93) of the third column (S3) is applied to the output of the rows of the ten NOR-matrices (1 ... 10) associated with the ten following binary numbers (B20 ... B29), etc., - the gate electrode of respectively one transistor (TS04 ... TS24) of the last column (S4) is applied to the output of the rows of the ten NOR-matrices (1 ... 10) associated with the remaining binary numbers (B30 ... B32), - the output of the first column (S1) is applied via a first inverter (IN1) to the first input of a first decade-NOR-gate (N1) to the second input of which there is applied the output of the second column (S2), - this output is applied via a second inverter (IN2) to the first input of a second decade-NOR-gate (N2), to the second input of which there is applied the output of the third column (S3), - this output is applied via a third inverter (IN3) to the first input of a third decade-NOR-gate (N3), to the second input of which there is applied the output of the fourth column (S4), etc., up to reaching the highest decimal decade, - at the output of the rows of the NOR-matrices (1 ... 10) associated with the highest decimal decade (DK4 or DK3) there is to be taken off the signal for the digits (DE0 ... DE9) of the decimal units position (DE), and at the output of the decade-NOR-gate (N1 ... N3) there is to be taken off the signal for the digits (DZ1 ... DZ3) of the decimal-tens position (DZ), and - all of the employed transistors are of the same conductivity type (n-channel or p-channel) as well as of the same control type depletion or enhancement type).
[EP0027541A1]