Patent SG-11201811065S-A (SG)
Title: Memory cell imprint avoidance
Inventor: CALDERONI ALESSANDRO
IPC: G11C11/22
Filed: 2017-06-02
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property 1111111011110111010101111101011111001111111111111101H11111111111111111111110111111 Organization International Bureau (10) International Publication Number (43) International Publication Date ......0\"\" WO 2017/222786 Al 28 December 2017 (28.12.2017) WIP0 I PCT (51) International Patent Classification: DESCHI, Ferdinando; 8000 South Federal Way, Boise, Gl1C 11/22 (2006.01) Idaho 83716-9632 (US). (21) International Application Number: (74) Agent: HARRIS, Philip W.; Holland & Hart LLP, P.O. PCT/US2017/035758 Box 11583, Salt Lake City, Utah 84147 (US). (22) International Filing Date: (81) Designated States (unless otherwise indicated, for every 02 June 2017 (02.06.2017) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (25) Filing Language: English CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (26) Publication Language: English DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, (30) Priority Data: KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, 15/188,886 21 June 2016 (21.06.2016) US MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, 8000 South Federal Way, Boise, Idaho 83716-9632 (US). SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (72) Inventors: CALDERONI, Alessandro; 8000 South Federal Way, Boise, Idaho 83716-9632 (US). RA- (84) Designated States (unless otherwise indicated, for every MASWAMY, Durai Vishak Nirmal; 8000 South Federal kind of regional protection available): ARIPO (BW, GH, Way, Boise, Idaho 83716-9632 (US). PRALL, Kirk; 8000 GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, South Federal Way, Boise, Idaho 83716-9632 (US). BE- UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, (54) Title: MEMORY CELL IMPRINT AVOIDANCE 430 Non-Volatile Latch Indicator,' 435 , . >i FCC 3 ,i Component f 440 115-b \ 405 (—I J-225-a DL, tm 105-b ‘._ ssvt., l a 415-a )420- . , ......... 420-b l a 415-b Memory _.-b_ 110-bT Cell 425-a{ 425-a{ } 4 b pt N210-a > a \-- 1 125-b 4- 1 410 ,-1 FIG. 4 \----- 400 .4 (57) : Methods, systems, and devices for operating a ferroelectric memory cell or cells are described, A cell may be written GO N with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has ei stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently ei ----. stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based IN ,_ 1 on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period. 0 ei C [Continued on next page] WO 2017/222786 Al IMEDIMOMMIDIRMEMODIOHOHOMEINOME#011# TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(H)) — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))