Patent GB-799705-A (GB)
Title: Improvements in or relating to electronic digital computing machines
Inventor: ROBINSON ARTHUR ALEXANDER
IPC: G06F5/01
Filed: 1953-11-20
Abstract: 799,705. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Nov. 15, 1954 [Nov. 20, 1953], No. 32297/53. Class 106 (1). In an electronic digital computer arranged for operation, at least in part, in the serial mode, shifting arrangements for altering the numerical value of a number word under control of an instruction word comprise a storage device having separate immediately accessible storage locations, one for each digit of the number to be dealt with, digit storage address selecting means including cyclic counting means whereby each storage location can be rendered accessible in turn in a predetermined order and overriding setting means by which any desired address location may be set at a given instant, whereby the whole or part of a number can be written into the storage device with one timing relationship to the timing cycle or rhythm of the computer and can be read out with a different timing relationship. General. The machine illustrated in Fig. 1 is similar to that described in Specification 742,522 employing C.R.T. binary digital stores and comprising a 16-tube main store S, a staticizor unit STU, a two-line control unit C and a fourline accumulator A, controlled by waveforms (including those shown in Fig. 10 (b)-(i) and Fig. 11 (a)-(g)) generated in unit WGU. In the present machine, a shift tube ST and associated counter SC are employed to shift the 80-digit word in A, the extent and direction of shift being either determined by a number given in the address portion of a " shift " instruction, or such as to place the word correctly relative to a fixed binary point (" standardize " instruction) ; such shifting operations involve the extension of a " bar " beyond the normal 4, 5 or 7 beats (see Fig. 11). An instruction word, Fig. 10 (k), is similar to that of Specification 742,522, comprising six line-selecting l digits, and four tube-selecting e digits, but only five function digits f. The machine circuits consist primarily of bi-stable trigger circuits, and "and" gates responsive to coincidence of negative inputs. The function digit combinations applied to the " and gates, such as G203, Fig. 2, are indicated in the drawings (the symbol # indicating that the digit may be " 0 " or " 1 "). Accumulator. The four lines of accumulator tube 200, Fig. 2, are normally scanned in succession under control of Y-shift circuit AYG connected to serially-connected trigger circuits AYC0, AYC1 which are switched by pulses P21, the triggers being reset to select the first (least significant) line by a pulse from gate G205 or G200. The information regeneration circuit including amplifier 205, read unit 206 and write unit 209, is completed through gate and adder 212, e.g. similar to the adder described in Specification 693,424, or through gate G201, according to whether or not the function code is 10###. The sign digit (in the most significant position) is registered on trigger 240. Shift operation. The shift instruction comprises function code 11010 and a number N in positions l 0 -l 5 , e 6 -e 9 , Fig. 10 (k), indicating the degree of shift. If N is positive (" 0 " in position e 9  ) the accumulator word is shifted left, and if N is negative (represented in complementary form) the word is shifted right and the N most significant digits are made the same as the original most significant or sign digit. Normally 79 # N # - 80, in which case the sign of N will be indicated by the digit in position e 7 . The instruction digits will be set up, as usual, on the staticizor during beat S2, and during the following beat A2, the digits in positions l 0 -l 5 , e 6 -e 7  will be transferred through gates G510-G517, Fig. 5, controlled by the output of G502, to trigger circuits Z0-Z7 which are serially connected to form the shift counter SC. The outputs of Z0-Z6 control X- and Y- shift circuits 415, 416, Fig. 4, whereby the counter setting selects one of 80 digit positions in one of 5 lines in the shift tube 400 which has the usual amplifier read unit 406 and write unit 409 associated therewith, but not regeneration loop. A trigger circuit SF also is set during beat A2 through gate G400 and its output SF, Fig. 11 (k<SP>1</SP>), allows trigger S1G to be set through G401, and triggers AYC0, AYC1 to be reset through G200, Fig. 2, at the beginning of the next beat A3. Assuming that a left shift is required, when Z7 registers " 0," the output of S1G, Fig. 11 (i<SP>1</SP>), together with the output of gate G403, Fig. 4, will open gate G402 to allow the accumulator word on line 101, Figs. 2 and 4, to be written in tube 400 during beats A3, S3, B4 and S5, Fig. 11. At the same time the shift counter will be stepped on by dash pulses, Fig. 10 (b), applied to gate G503, Fig. 5 (the shift B0 waveform, Fig. 11 (ml), being negative after beat A2) whereby the shift tube digit positions are sequentially selected. When the shift counter registers 79 (corresponding to the 80th digit position) an 80-digit detector 505 (shown in Fig. 17) emits a pulse which resets Z0-Z6, Fig. 5, and SF, Fig. 4. Gates G403 and G404 are then both closed, and thus the higher digits of the accumulator word cannot pass through G402, and 0's are therefore written in positions 0 to (N-1) of tube 400. At the end of beat S5, when the four lines of accumulator tube 200, Fig. 2, have been scanned, an output from AYC1 resets S1G whose " 0 " output then triggers a circuit SOG (see Fig. 11 (j<SP>1</SP>)) through a slow differentiating network. The differentiated output of SOG resets counter triggers Z0-Z7, and the positive INV SOG waveform applied to the erase input terminal of read unit 406, allow the digits stored on tube 400 to be read out in the order 0-79 during beats S6, S7, B8, S9 whereby the shifted word is fed back over lead 102, Figs. 4 and 2, to the accumulator. At the end of S9, AYC1 resets SOG and the operation is completed. The prepulse-generating circuit (Fig. 9, not shown) is inhibited by S1G whereby the next prepulse, Fig. 11 (a<SP>1</SP>), does not occur until the end of S6, beats S7, B8, S9 overlapping beats Sl, A1 and S2 of the next bar. For a right shift, trigger Z7 registers " 1 " and opens gate G504 during beat A2, whereby 80 (binary 1010000) is added into the shift counter which then registers 80-N. During beats A3, S3, B4, S5, gate G406, Fig. 4, is opened by gate G405 to allow the accumulator sign digit to be repeatedly written into the shift tube, until trigger SF is reset by the 80-digit detector when gate G404 opens G402 and allows the higher digits of the accumulator word to be written in positions 0 to (79-N). The remainder of the operation is similar to that for left shift. If N < - - 80, a circuit comprising gates G408, G407, Fig. 4, causes waveform EX(-) to go negative, and if N > 79, a circuit comprising gates G410, G409 causes INV EX(+) to go positive. In either case, gates G402, G502, Figs. 4 and 5, will remain closed, but if EX(-) is negative, gate G406 is open to fill the shift tube 400 with all 0's or all 1's depending on the accumulator sign digit. The contents of tube 400 are transferred to the accumulator tube as in the normal shift operation. Standardize operation. For the standardize instruction, comprising function code 11011, the accumulator word is shifted so that its most significant digit (" 1 " for positive, " 0 " for negative numbers) is in the 3rd position from the left, and the number corresponding to the required shift is recorded, the operations requiring two successive bars, Fig. 11. At the beginning of beat A2 of the first bar, waveform STAND, Fig. 11 (l<SP>2</SP>) generated by a circuit comprising gates G519, G518, Fig. 5, goes negative and allows triggers ZO-Z7 to be set to their " 1 " condition through gate G500. During beats A2, A3, S3, B4, the shift counter is stopped by dash pulses through G503 and the waveform STAND opens gate G509 to cause the accumulator word to be passed over lead 100, Figs. 2 and 5, to a non-equivalence detecting circuit 502. The word is passed both directly and through a onedigit delay 503 or " shuffle " circuit whereby consecutive digits are compared. For a change from " 0 " to " 1 " or vice versa, the circuit 502 produces an output pulse which resets ZO-Z7 to " 1's." Thus, at the end of B4, the registration of the counter will correspond to the number of digits above the most significant digit position M in the accumulator word. Since the counter starts at - 1, the registration will be 79 - (M +1) - 1 = 77 - M the required number of shifts. If the accumulator word is all 0's the circuit 502 never emits a pulse and 79 will be set up on the counter, and if the word is all 1's, 502 emits a pulse during period P 0  of A2 and 78 is set up whereby 1's are retained only in the two left-most positions of the word. At the beginning of S3, SF is triggered, Fig. 11 (k2), through gate G413, Fig. 4, and a new prepulse is formed, Fig. 11 (a2), to start the second bar, but the addition of " 1 " to the control instruction in C, Fig. 1, is inhibited by the positive INV SF waveform. During A2 of the second bar, the shift number on Z0-Z6 is dynamicized by gates G420-G426 and passed through G412 to the main store at the address given by the l and e digits of the standardize instruction. At the beginning of A3, trigger SIG is set (see Fig. 11 (i<SP>2</SP>)) and a shift operation then proceeds in accordance with the number registered on the shift counter, as described previously Specification 705,477, [Group XL (b)], also is referred to.