Patent SG-11201811095U-A (SG)
Title: Multi-level storage in ferroelectric memory
Inventor: KAWAMURA CHRISTOPHER JOHN
IPC: G11C11/22
Filed: 2017-06-06
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property C.--.` MD HIM 011101011M 01 110 1 01011101111110011111011111011110111 011 Organization International Bureau (10) International Publication Number 03 (43) International Publication Date .....•\"\"- WO 2018/005019 Al 04 January 2018 (04.01.2018) W I PO I PCT (51) International Patent Classification: MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, G11C 11/22 (2006.01) PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, (21) International Application Number: SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, PCT/US2017/036148 TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (22) International Filing Date: (84) Designated States (unless otherwise indicated, for every 06 June 2017 (06.06.2017) kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, (25) Filing Language: English UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, (26) Publication Language: English TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, (30) Priority Data: MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, 15/194,178 27 June 2016 (27.06.2016) US TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). Declarations under Rule 4.17: (72) Inventor: KAWAMURA, Christopher John; 8000 S. — as to applicant's entitlement to apply for and be granted a Federal Way, Boise, Idaho 83716-9632 (US). patent (Rule 4.17(ii)) — as to the applicant's entitlement to claim the priority of the (74) Agent: HARRIS, Philip W.; Holland & Hart LLP, P.O. earlier application (Rule 4.17(iii)) Box 11583, Salt Lake City, Utah 84147 (US). — Published: (81) Designated States (unless otherwise indicated, for every — with international search report (Art. 21(3)) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, = HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, (54) Title: MULTI-LEVEL STORAGE IN FERROELECTRIC MEMORY (57) : Methods, systems, and devices for operating a ferroelectric access- memory cell or cells are described. In some examples, multi-level 1 '-' '-' 1 . 43 + ing, sensing, and other operations for ferroelectric memory may be based on I '-' sensing multiple charges, including a first charge associated with a dielec- tric of the memory cell and a second charge associated with a polarization - - _--1 p.o \ the In 7— of memory cell. some cases, multi-level accessing, sensing, and other EQ B L , 0 _, I_ L operations may be based on transferring a first charge associated with a di- electric of the memory cell to a sense amplifier, isolating the sense amplifier, activating the sense amplifier, transferring a second charge associated with a polarization of the memory cell to the sense amplifier, and activating the sense amplifier a second time. . 3 d e) — — I — —I , _ i _ _ _ P I I I ll r 460 A65 4 7 0 4, , 4 8O 485 '-' '—' I '--' '' it a., I I I it Il 0 1 950 Il • L. - 435-6 r 1 GNFb .. --- 'i ' , SA_NODE 13 1 • I _.J © / kr) „ © © 0 -- tt '---7-1 z___, SA NUPE Ai I I lli_ I L _LI] I 10 \... GC Il \.---- © FIG. 4A 400-a N C