Patent JP-S56120287-A (JP)
Title: Communication exchanger with control command memory such as telephone exchange circuit device
Inventor: RAINHARUTO FURANKU
IPC: H04Q3/54
Filed: 1981-01-29
Abstract: 1. Circuit arrangement for telecommunications exchanges, in particular telephone exchanges, in which storage elements (h1, h2, ... hm), which serve individually to store control instructions which are to be executed with a time delay, can be operated on the basis of storage element addresses (at c1 ... cn) both by means of a drive write arrangement (G1) which serves to write control instructions (at h13, ... h33, ... h53) and also by means of a drive read arrangement (A1, E1) which serves to read stored control instructions (at h13, ... h33, ... h53), and in which exchanges, likewise with the assistance of the drive write arrangement (G1), each of the storage elements (h1, h2, ... hm) can store, in addition to the particular control instruction, a pointer address (at h12v, ... h32v, ... h52v) by means of each of which a further storage element (h1, h2, ... hm) can be addressed, by which means, with the assistance of an address stored in a storage unit (c1, ... cn), of one of the storage elements (h1, ... hm) and with the assistance of the pointer address (at h12v, ... h32v, ... h52v) stored in each of the storage elements (h1, ... hm), this storage unit (c1, ... cn) can in each case be combined with storage elements (h1, ... hm) to form a chain in which the storage element address stored in the storage unit (c1, ... cn) and each of the addresses stored in the storage elements (h1, ... hm) points to the following storage elements (h1, ... hm) in the chain, and in which exchanges, when a control instruction (at h13, ... h33, ... h53) is stored in a storage element (h1, ... hm) which is newly selected for this purpose and, in association with the nominal time of the execution of this control instruction, is to be assigned to a specific storage unit (c1, ... cn), on the one hand in the relevant storage unit (c1, ... cn) the storage element address stored therein is read out and erased in said storage unit and stored, as a pointer address, in the newly selected storage element (h1, ... hm), and on the other hand the storage element address is stored in the relevant storage unit (c1, ... cn), and in which exchanges a clock-pulse controlled counter arrangement (T, U) is provided, and with the assistance of the count of this counter arrangement reached at any given time the storage device (c1, ... cn) indicates in which of the storage elements (h1, ... hm) drive read procedures are due and are correspondingly initiated, characterized in that a plurality of storage units (c1, ... cn) is provided in an ordered sequence, that similarly a plurality of chains of storage elements (e.g. h1, h4, hm and h2, h5) which are independent of one another are formed in that any one of the storage units (e.g. c2 and c5) is only ever logiclinked, by means of the stored pointer addresses (at h12, ... h52v), to the stored control instructions (at h12, ... h53) which are to be executed simultaneously or approximately simultaneously, and that the drive read arrangement (A1, E1) indicates the count of the counter arrangement (T, U) in that for this purpose it is set successively to the individual storage units (c1, ...cn) in sequence, with the assistance of the storage element address (e.g. of h1), to be read from the storage unit (e.g. c2) designated by the setting of the drive read arrangement (A1, E1) to drive the chain of only those storage elements (e.g. h1, h4, hm) which are assigned to the storage unit which has been reached (e.g. c2), by means of address logic-linking with the assistance of the pointer addresses.