Patent GB-1216352-A (GB)
Title: Improvements in or relating to echo suppression systems
Inventor: MAY CARL JEROME JR
IPC: H04B3/20
Filed: 1969-06-23
Abstract: 1,216,352. Echo suppressor system. WESTERN ELECTRIC CO. Inc. 23 June, 1969 [21 June, 1968], No. 31568/69. Heading H4R. In an echo suppressor the signal level on an incoming line is determined and compared with a signal representing the previous condition of the line in order to obtain a signal representing the activity status of the line. In addition the signal level on the outgoing line is compared with the signal level on the incoming line, and with signals representing previous activity state of the line, to obtain a further signal representing the activity status of the outgoing line. If the incoming line is determined to be active and the outgoing line idle a signal suppressor is inserted in the outgoing line. As described, the signal levels and activity states are coded in binary number form and the comparison equipment works in time division multiplex to a number of lines. Preferred arrangement, Fig. 1.-Each outgoing line, LE, and each incoming line, L#, is provided with a threshold detector, 1 and 2, which provides a signal on one or more of its output lines according as the signal level on the line exceeds one or more predetermined threshold values. The threshold detector output lines are fed to sampling circuits, 3 and 4, which simultaneously sample the input and output lines of one line pair from a number of line pairs, of which only the one pair LE1 and L#1 are shown, associated with a single sampling circuit. The signals from the incoming line, L# 1, from sampling circuit 4 are fed to a state detector 9 which is also fed with information on the previous state of the line from the status store 11. The information in the status store and the state determined is recorded as a three bit binary number and the sequence of states stored is indicated in Fig. 4B, from which it can be seen that the higher the level of detected signal and the longer the detected signal remains, the longer is the line assumed to be active after the signal in the line has ceased. The signal level on the incoming line is also compared with that on the outgoing line in the signal level comparator 5, connected to the sampling circuits 3 and 4. If the signal level on the outgoing line exceeds that on the incoming line the signal line AE is energized, if the reverse condition obtains then the line AE is energized. This present activity state is compared with the previous activity state, stored as a two-digit binary number in the even status store 10 and the resulting signal is fed to the suppression signal logic 12 and also used to up-date the status recorded in the store 10, the sequence of states being as indicated in Fig. 4C, from which it can be seen that the line active state is held for a longer period if the active state has existed for a significant period of time. The suppression signal logic compares the incoming and outgoing line activity states and produces a suppression activation signal when the incoming line is determined as active and the outgoing line determined idle. This signal, via the line address matrix, inserts a suppressor in series in the appropriate one of the line pairs for which the signal has been generated. The sampling of the respective lines and the insertion of the suppressor in the appropriate line corresponding to that being sampled is controlled by the line address generator 15 driven by the clock 16. A divider 14 reduces the clock frequency so that the line status stores are only incremented at appropriate periods. Logic circuits are described with respect to Figs. 2 and 3 (not shown) for the state detectors and timing units of the incoming and outgoing lines, called respectively odd and even in the Specification. The status stores operate in a similar manner to that described in a line activity determining equipment for a TASI system of Specification 1,216,351.