Patent GB-1040614-A (GB)
Title: Improvements in or relating to code translation systems
IPC: H03M1/00
Filed: 1963-06-21
Abstract: 1,040,614. Analogue to digital converters. WESTERN ELECTRIC CO. Inc. June 21, 1963 [July 2, 1962; July 16, 1962], No. 24761/63. Heading G4H. A circuit for use in analogue-to-digital conversion and vice versa consists of an amplifier 50, Fig. 6 (not shown), having parallel feed-back connections, one through resistor 53 and diode 54 and the other through resistor 55 and diode 56, the diodes being oppositely poled so that only one conducts at any time. An analogueto-digital converter consists of a series of units 26, 28, 30, 32, Fig. 4 (not shown), including this circuit, each of which gives the result of subtracting a value of 8 volts from twice the input voltage, to give a " 1 " digit if the result is positive and a " 0 " digit if negative and pass a residue voltage to the next stage. The digits then represent in reflected binary code the input voltage. If the input voltage is 4À6 the process is as follows. The value is doubled to give 9À2 and 8 is subtracted to give a residue of 1À2 and a " 1 " digit. The residue is doubled to give 2À4 and 8 is subtracted to give a residue of 5À6 and a " 0 " digit (since the residue is negative). The - 5-6 is doubled and made positive to give 11À2 and eight is subtracted to give a residue of 3À2 and a " 1 " digit and so on. In the circuit of Fig. 6 there are three output terminals 58, 59, 60, giving signals EA, ED, and EB, Figs. 7, 8 and 9 (not shown). The output ED is taken as positive or negative, " 1 " or "0." The output EA is inverted at 60, Fig. 10 (not shown), and combined with EB at 65. A reference voltage is applied at 66 to shift the resulting curve so that its apex is above the origin as shown in Fig. 3 (not shown). Because of this response characteristic, the unit serves to produce a residue equal to the input multiplied by 2 less 8. At very high speeds the difference in time taken for the signals to arrive at point 65 over the two different paths may be high enough to prevent proper working. The circuit of Fig. 11 (not shown), overcomes the difficulty by having two parallel series of coding units, one receiving the current to be coded at 88 and the other, the inverse current at 89. Cross connections take the signals EA and EB to adding points 51 as required and no inverter stage 60 (Fig. 10) is necessary. Decoding.-The binary digits are shifted into a register 130, Fig. 15 (not shown), and are gated out in parallel on leads 125, 126 and 127, each controlling a decoding stage 117, 119 and 120. Each stage receives an input, either a reference voltage r or the output of the preceding stage and has the characteristic of Fig. 14 (not shown). The operation of each stage is to produce half the input voltage if the digit is " 0 " and to produce 8 volts minus half the input voltage if the digit is " 1." Where the digit is " 1 " the slope is -¢ and where it is " 0 " it is +¢. If the binary digits are 11 and the reference voltage is 4 volts, the first stage produces an output of 2 volts on the upward sloping part of the graph of Fig. 16 (not shown). This is applied to the second stage which having a " 1 " input is working on the downwardly sloping line and gives 7 volts. This is applied to the third stage to produce 4.5 volts. The circuit of each stage is shown in Fig. 17 in which 140 is an amplifier with feed-back paths through oppositely-poled diodes 144, 148 and resistors 143, 147. The outputs 1 and 2 are complementary, Fig. 18 (not shown), and to avoid the necessity of inverting one of them, two series of stages are used with cross-connections similar to those of Fig. 11, operating in phase opposition.