Patent GB-1458450-A (GB)
Title: Keyed agc circuit
IPC: H04N5/53
Filed: 1974-03-04
Abstract: 1458450 Television automatic gain control RCA CORPORATION 4 March 1974 [5 March 1973] 9688/74 Heading H3T A television A.G.C. circuit comprises a circuit sensitive to composite video signals for translating signals beyond a given threshold level and coupled to a peak detector having a timeconstant suitable for sync. pulses of different duration. Keying means responds to recurrent pulses and to the peak detector for providing a variable current determined by the peak de. tector, and output means, e.g. a filter, responds to the keying means to develop an A.G.C. voltage determined by this variable current. A first embodiment wherein an increase in A.G.C. bias results in a decrease of gain and the output from video amplifier 34, Fig. 1 is as shown in Fig. 2. In the synchronous mode, if the gain is too low transistor 40 remains saturated, so there is no voltage across capacitor 44; thus transistors 50, 51 are conductive and so the base of transistor 47 is substantially earthed, so that keying pulses from source 57 have no effect. The current amplifier formed by diode 52 and transistor 49 then discharges capacitor 53 to increase gain, diode 33 being cut off. When gain increases sufficiently, the sync. pulses tips at the base of transistor 40 bring it out of saturation on each sync. pulse, and it acts as an amplifier; the resulting positive-going pulses at the collector charge capacitor 44 via diode 43, and this charge is held for the full keying pulse interval because diode 33 is reverse biased and the base current in transistor 51 is in a direction sustaining the charge. The charging timeconstant of capacitor 44 is small compared with the period of the shortest sync. pulses (i.e. the equalizing pulses). The voltage across capacitor 44 causes a reduction in the conductivity of transistors 50, 51 so that transistor 47 becomes forward biased during keying intervals, so that its emitter supplies a charging current to capacitor 53 offsetting the discharge current via transistor 49 and so maintains the charge and the gain constant. At the end of keying pulse intervals transistors 47, 50, 51 are no longer on: diode 33 is then forward biased and capacitor 44 quickly discharges into capacitor 53. When the signal gain is too high, transistor 40 is turned off and capacitor 44 charges towards A + potential; transistors 50, 51 are thus biased to cutoff and during keying pulses transistor 47 has maximum effect in charging capacitor 53. At the end of keying pulse periods capacitor 44 again discharges rapidly into capacitor 53 via diode 33. Noise suppression.-Noise pulses are of no effect outside keying pulse periods. If occurring in such a period, differentiating circuit 5, 58 supplies pulses corresponding to the positive edges which are peak detected by transistor 59 to produce at its emitter positive voltages which are applied via emitter-follower 60 to the base of transistor 63 which then applies negativegoing pulses to capacitor 44 to balance out the positive noise pulses arriving via transistor 40. Out of lock mode of operation.-When the signal gain is too low transistor 40 is always saturated so that transistors 50, 51 are biased conductive, cutting off transistor 47: capacitor 53 then discharges during keying periods until the gain is sufficient for lock to occur. If, on the other hand signal gain is too high, capacitor 44 charges up during the sync. pulse periods: in the periods in which keying pulses are supplied from source 57 transistor 47 supplies charging current to capacitor 53, decreasing the gain. In the absence of keying pulses capacitor 44 again quickly discharges via diode 33 into capacitor 53. In a modification the collector of transistor 50 may be connected directly to earth and capacitor 53 discharged by coupling a resistor across it in place of transistor 49 and diode 52. Arrangements in which a decrease in A.G.C. bias causes a decrease in gain.-Composite video signals are applied via terminal 78, Fig. 3a, and resistor 65 to the base of transistor 68 which feeds a peak detector comprising diode 69 and capacitor 70. A source of keying pulses is coupled via terminal 80 to the collector of transistor 72, while diode 74 forms with transistor 75 a current mirror for charging the A.G.C. capacitor (not shown) via terminal 76. Resistor 65 and capacitor 67 form a low-pass filter restricting band width for thermal and impulsive noise. When the sync. pulses in the input signal fall below a threshold value transistor 68 comes out of saturation and charges capacitor 70: when keying pulses are present, the charge on capacitor 70 causes transistor 72 to be conductive so that a current flows in transistor 75 to discharge the A.G.C. capacitor. When the keying pulses are absent, the charge on capacitor 70 is rapidly removed via the base-emitter junction of transistor 72 and diode 74. The A.G.C. capacitor is coupled to a positive voltage supply via a polential divider network (not shown) for charging purposes. The Specification also discloses a modification in which capacitors 67, 70 are replaced by a single capacitor (81) connected between the bases of transistors 68, 72 (Fig. 3b, not shown). In a further embodiment composite video signals are applied via terminal 78, Fig. 3c to level shifting transistor 100, the bandwidth being restricted by means of resistor 101 and capacitor 107. Transistor 105 is so biased that with a negative-going signal of amplitude less than a given positive threshold value, it comes out of saturation, and the voltage at its collector is peak detected by means of diode 106 and capacitor 107. Thus with gain too high or approximately correct capacitor 107 charges to a voltage representative of the least possible excursion of the signal, i.e. in the in-sync. mode, the tips of the horizontal sync. pulses. In the presence of keying pulses at terminal 80 transistor 108 is turned off and the voltage on capacitor 107 determines the base current of transistor 109; the current allowed is minimal, maintaining the charge on capacitor 107. Once the keying current goes, capacitor 107 quickly discharges through transistor 108. When transistor 109 is conductive transistor 110 is rendered conductive and the current through diode 112 causes transistor 118 to conduct and discharge the A.G.C. capacitor (not shown) connected to terminal 76. When gain is too high and transistor 105 is turned off, transistor 116 conducts, turning off transistor 120. When the keying pulse is present and signals at the base of transistor 105 are insufficient to bring it out of saturation, i.e. the sync. voltage excursions are too small or keying occurs during video portions of signals, transistor 120 has its base clamped to the voltage across Zener diode 114: a predetermined charging current then flows through resistor 121 to terminal 76, increasing the charge on the A.G.C. capacitor and hence the gain. When the system is out of lock, i.e. synch. pulses do not appear at terminal 78, transistor 122 and resistor 123 form a low gain simple A.G.C. circuit to reduce A.G.C. "beat".