Patent GB-1217491-A (GB)
Title: Improvements in or relating to automatic gain control circuits
Inventor: GRAY DAVID
IPC: H04B1/30
Filed: 1966-12-28
Abstract: 1,217,491. Automatic gain control. PLESSEY CO. Ltd. 5 Feb., 1968 [28 Dec., 1966], No. 58030/66. Heading H3T. An automatic gain control (A.G.C.) circuit comprises two gain control generator circuits connected in parallel, one having a rapid rise time and a short hang time and the other having a relatively long rise time and a hang time controllable independence upon an input signal applied to the system wherein only the first A.G.C. circuit is responsive to transient noise bursts and control of the hang time of the second circuit enables the system to provide a control voltage which follows fading input signals. (The " hang time " is the time during which the A.G.C. signal continues to be generated at its original level after a reduction in the mean signal level.) The arrangement is primarily intended for single sideband receivers and may operate from I.F. or audio signals. The Specification describes what is stated to be a known arrangement in which transformer T, Fig. 1, feeds signal E<SP>1</SP> to diodes D1, D3 which charge respectively small and large capacitors C1, C2. A lesser signal E is fed from a tapping on the transformer to diodes D2, D4, resistor R1 being connected in series with diode D4, the diodes charging respectively small and large capacitors C3, C4. The D.C. voltages developed across capacitors C3 and C4 are combined, via resistors R4, R5 and diodes D5, D6 and applied to the gate of field-effect transistor FET, from the source of which the AGC voltage is obtained. Capacitors C1, C2 are connected across the base to collector paths of transistors TR1, TR2 respectively which are biased negatively from terminal 2 via resistors R2, R3 respectively, and capacitors C3, C4 across the corresponding collector to emitter circuits. The arrangement is such that on increasing signal, E<SP>1</SP> being greater than E, the voltages to which the capacitors charge up are such that transistors TR1, TR2 remain non-conducting: the rate of rise of A.G.C. voltage is determined by the short time-constant circuit comprising capacitor C3. If the input signal subsequently becomes reduced, diodes D1-D4 are rendered non- conductive and the charges retained on capacitors C3, C4 maintain the A.G.C. voltage constant. Capacitors C1, C2, however, start discharging and when the charge on the smaller capacitor C1 has fallen sufficiently transistor TR1 becomes conductive and discharges capacitor C3; after a further period capacitor C4 is likewise discharged through transistor TR2. The arrangement is such that for short bursts of signal, only the circuit comprising capacitors C1, C3 is operative, the longer time-constant circuit comprising capacitors C2, C4 only coming into operation on sustained signals. In an embodiment of the invention audio input signal I, Fig. 3, is fed to an A.C. amplifier A1 which produces two outputs at terminals X, Y. That at X is fed to the collectot circuit of a biassing transistor TR3 which is directly connected to the bases of transistors TR4, TR5 which respectively form short and long time constant A.G.C. generators: if the input signal increases the voltages on their bases increase and switch both into a conducting state, to charge capacitors C6, C7 respectively. The time constants are so arranged that capacitor C6 charges much faster than capacitor C7 and therefore operates D.C. amplifier A2 by turning on a transistor TR6, resulting in an increased A.G.C. voltage V. After a time delay capacitor C7 will be sufficiently charged to turn on a further transistor T7, so taking control of the A.G.C. output V. Output Y from A.C. amplifier A1 is fed to input transistor TR8 of a triggering circuit formed by transistors TR8, TR9, TR10, the output of which is fed to the bases of transistors TR11 and TR12. Triggering pulses applied to transistor TR11 cause it to fluctuate, being conducting and non-conducting states: in the conducting state diode D7 is forward biased and turns on transistor TR13, whereby capacitor C7 is discharged at a controlled rate. Triggering pulses applied to transistor TR12 cause it to conduct and charge capacitor C8, whereby transistor TR14 is biased conductive and holds transistor TR15 non-conductive; when triggering pulses cease, however, due to the charge on capacitor C8, the capacitor C7 retains its last charge for a period, before transistor TR14 stops being conductive and so turns on transistor TR15 to allow capacitor C7 to discharge. In the event of a fading input signal I, the bias voltage applied to transistors TR4, TR5 is gradually reduced, whereby they become biased non-conductive; in consequence the charging current applied to capacitor C7 begins to decay. Furthermore, due to the triggering pulses applied to transistor TR11, capacitor C7 is discharging at a constant rate, therefore transistor TR7 of D.C. amplifier A2 is gradually cut off, resulting in a reduction in the A.G.C. output V which will increase the receiver gain in accordance with the rate at which the input signal fades. Since transistor TR4 is gradually cut off capacitor C6 rapidly discharges leaving capacitor C7 to control the A.G.C. output. Should input signal I suddenly disappear, however, transistors TR4, TR5 are biased non-conductive so that capacitor C7 no longer charges; since the input signal has fallen below the threshold voltage of triggering circuit TR8-TR1O the triggering pulse output ceases, so that transistor TR13 is held in its non- conductive state and does not allow capacitor C7 to discharge through it: the output voltage V is accordingly held constant. As the output from the triggering circuit stops, transistor TR12 is cut off and capacitor C8 begins to discharge: transistor TR14 will remain in a conducting state for a period of e.g. one second, after which it becomes non-conducting, biasing transistor TR15 to its conductive state and so discharging capacitor C7, whereby the A.G.C. output voltage V decreases correspondingly.