Patent GB-1091937-A (GB)
Title: Digital computer
IPC: G06F9/42
Filed: 1965-12-03
Abstract: 1,091,937. Data processors. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 3, 1965 [Dec. 30, 1964], No. 51340/65. Addition to 1,007,415. Heading G4A. In a digital computer, means are provided for storing the address of a parameter relating to a sub-routine of a nest of sub-routines, in an address characteristic of the position of the sub-routine in the nest and the position of the parameter with respect to other parameters in the sub-routine call instruction. A multi-character instruction, placed in an instruction register and normally decoded character by character selected under control of a ring, may contain a sub-routine call consisting of, in order, a special start character (º), a two-character name which is the beginning address of the sub-routine, followed by one or more two-character parameters for use in the sub-routine each preceded by a special character (,), the sub-routine call ending with a special end character (Â). Each parameter is either the address of an operand, or a special character (call " par ") followed by a number. The instruction decoder recognizes the special characters and initiates gated chains of singleshots to control operations relating to calling sub-routines. Sub-routines may call other subroutines, forming a hierarchy of sub-routine levels limited only by storage constraints. As a sub-routine call is decoded, its parameters, if they are operand addresses, are stored in addresses specified by the concatenation of a level counter specifying the sub-routine level in the hierarchy and a parameter counter specifying the ordinal number of the parameter in the call. If a parameter is of the form " par n " n is placed in the parameter counter the previous count being saved in a register and the level counter is temporarily decremented to reach the next higher level, the operand address corresponding to " par n " then being accessed at the address specified by the counters and, after restoration of the counters, stored under their control. When the end character of the call is reached, the current instruction address, from an instruction address register and the current ring position are placed in a push-down store as the return address, together with the contents of a sub-routine end address register which, if the call is within another sub-routine, will be holding the end address of that subroutine. Then the sub-routine beginning address moved from the call to a sub-routine address register is used to access the sub-routine and pass it to the instruction register instruction by instruction under control of the instruction address register. The sub-routine starts with its own end address which is stored in the subroutine end address register and compared with the instruction address register during subroutine execution to indicate when the subroutine has been completed. (Alternatively this can be done using a special mark at the end of the sub-routine). After execution, the pushdown store permits return to the next higher level by loading the instruction address register and the sub-routine end address register and setting the instruction register ring, the level counter also being decremented. Sub-routines contain dummy parameters to be replaced by parameters specified in the call, the dummy parameters being of the form " par n " (see above), so when the sub-routine is executed, the corresponding operand address is obtained as in the decoding of calls (see above). A parameter may be an arithmetic expression or a sub-routine call, the latter allowing recursive definition of sub-routines. A sub-routine may be used in a loop which is iterated until a specified condition is satisfied. Sub-routines can be stored in read-write storage or read-only (e.g. a microprogramming read-only store). The invention is described as an addition to the system of Specification 1,007,415. Reference has been directed by the Comptroller to Specification 997,104.