Patent GB-1495729-A (GB)
Title: Apparatus and method for handling exceptions in a data processing system
IPC: G06F11/00
Filed: 1974-12-02
Abstract: 1495729 Data processing COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL 2 Dec 1974 [30 Nov 1973 13 Nov 1974] 52129/74 Heading G4A A data processing system in which error indicating means supply to control means information relating to errors detected by an error analyser, the control means detects the mode of the errors and executes an error program in dependence on the mode. The basic system comprises a central processing unit (101, Fig. 1, not shown) operative in a native mode, emulation mode, concurrent native and emulation modes and diagnostic mode, peripheral sub-systems (103) and a main memory system (102) (capacitive MOS). Secondary storage (drum or disc) is used to provide a virtual memory facility. The central processing unit includes general, base and scientific registers and a control unit including a control store comprising a program for read only memory and a random access store for micro control and an address control unit including an associative store holding the base address of the eight most recently used segments and their segment numbers, this store being updated at each request. Control store words are 84 bits wide, 3 bits for a sequence-type field, 23 bits for branching and/micro operations, 14 bits for constant generations/designation, 8 bits for data, 32 bits for micro operations and 4 bits for checking. Multilevel nesting sub-routine facilities are provided.  The job and process numbers J, P of the currently running process are held in the system base. The address in boundary address register 1202 (Fig. 12) is used to access a J table word in system base 1215 which in conjunction with the J number is used to access the J table 1216 to provide a P table pointer which is then used together with the P number to access P table 1217 to derive a pointer to the absolute address for a process control block 1206, relating to the current process, each process having its own block. An exception occurs if the J or P number is greater than the size of the J or P table (defined by a section of the J or P pointers). The process control block pointer in the P table includes a first bit (bit 0) which is set to zero when the control block is absent, an exception occurring in this case. Unless bits 1-7 are zero an illegal P table entry exception occurs. Since processes vary in size and demand the main memory, memory space is dynamically allocated, addresses used by a process being logical rather than absolute. Each process has access to up to 2068 memory segments, defined in two segment table arrays, one containing the address of all segments of a maximum of 2<SP>22</SP> bytes and one containing the address of segments of maximum of 2<SP>16</SP> bytes, the absolute addresses of the two arrays being held in a process control block for the associated process. The high order bits of the segment table number field STN in a base register 1201 in the CPU are then used to access one of these words, e.g. ASW1 in the address process control block to derive a segment table word array pointer for the segment table word array 1208. This is used in conjunction with the segment table number to access one of eight segments tables 1210, the segment table entry STE in register 1210 being used to derive a particular segment descriptor which in turn is used to access a user segment 1211. A system segment 1214 is accessed using a G table word in the system base to access a G table, segment G0 of which is used for storing the addresses of queues of processes awaiting processing, exceptions occurring if the G number exceeds the size of the G table, if an indirect address bit is set or if a segment is absent. Semaphores are used for transmitting messages when a system exception occurs and the system base includes 9 locations for pointers to these semaphores. A tenth location contains the name of a semaphore used when a channel exception occurs. The system base also includes a pointer IPQW to the head of processes ready queue 12 13. The boundary address register specifies the lowest address in main memory accessible by software, an exception occurring if an address is outside the prescribed space. To protect segments shared by several processes a ring system is utilized whereby procedure and data segments are grouped into 4 ring classes 0-3 each ring representing a level of system privilege, the inner-most (ring 0) having the highest privilege. At each instruction access to data is granted or denied by comparing the ring number of the data with the ring number accompanying the procedure being executed. To pass from one procedure to another a stack frame in a stack segment is used, a T register locating the top of the stack for the currently active process (all processes having a virtual T register in their process control block). Each stack frame comprises a work area for storing variables, a save area for saving the contents of registers and a communications area for passing parameters between procedures, each procedure called creating a stack frame. Different stack segments are used for procedures executing in different rings, each process control block containing 3 stack words which point to the start of the stack for rings 0, 1, 2 associated with the process. When a process is in its running state (as opposed to its ready, wait or suspended state), the CPU is supplied with an address space (segment table) and a starting address. A dispatcher uses a set of queues to manipulate processes in the ready or waiting states. Each process control block (Fig. 4, not shown) includes a priority byte which is used for choosing the process to be run among all the ready processes and for forming queues, for a given priority level a first-infirst-out rule applying. When the process at the head of the ready queue has priority over the currently running process, a roll-out operation is effected with the data stored in temporary registers of the CPU being transferred to the process block of the out-going process. This is followed by a roll-in of data from the process control block of the new process. In a state byte positions are assigned to indicate that the process is active, suspended, waiting in the ready queue, waiting on a semaphore, that an interrupt has occurred or that the process is operating in emulation mode. A further byte contains the local name of the semaphore to which the process control block of a waiting or suspended process is linked and the class and type of interrupt like exceptions which caused the process to enter the suspended state after an exception. An exception word in the process control block contains a pointer to an exception class which defines the action to be taken following a process exception. An instruction word defines a segment number and the segment relative address to define the next instruction to be executed. A central exception mechanism may be activated either by a machine error in the central processing unit or main memory detected by parity checking or by an exception occurring. The CPU may be either executing the process instruction (i.e. either in process or transitory mode) or executing an internal operation (i.e. either in system mode or transitory mode). Transitory mode exceptions have priority over system mode exceptions which in turn have priority over process mode exceptions. When an exception is detected a branch is made which results in a hardware gate being tested, this gate being locked if the processor is in its transitory mode which causes the processor to go to its system incident state for diagnosis. If it is not locked the number loaded into a register in the arithmetic unit when an exception occurs is fetched and used to access an area of main memory reserved for a table of exceptions to obtain a class number identifying the group to which the exception belongs and the type number identifying the particular exception in the group, these being entered in a scratch pad memory. Errors other than machine errors are either functional (these occurring if a segment of main memory is accessed when it is in virtual memory) or illegal. Next a handler flip-flop is tested to see if it is set (indicating that the exception has occurred during the handling of an exception). If reset it is set and a check is made as to whether a system mode flip-flop is set (i.e. if there is a system exception). If it is not set (i.e. if there is a process exception) a branch is made and either the exception is ignored if it is masked or a process exception class table word is fetched from the current process control block and the table accessed by the exception class number to select the appropriate solution, there being a separate program for each class exception, tag bits determining whether a trap type or interrupt type mechanism is to be utilised to derive a 4 word exception report which indicates inter alia whether the message is an input/output one, whether the process has been suspended, the name of the process if it has to be interrupted, the exception class and type number and the cause of the exception (e.g. missing segment), this report being stored in the stack memory. If the system mode flip-flop is set (it being set if the exception handler flip-flop is set) the hardware gate is set and a system exception word in the system base is accessed to decide the proper exception action. Machine errors are of two types, CPU or main memory. The main memory corrects certain errors automatically but multiple bit errors cause the appropriate class of exception to be reported. The machine error mechanism masks other machine errors and then checks whether the operation can be re-tried (i.e. whether the instructions has altered the contents of registers/memory). If it has, or if it is re-tried unsuccessfully, the machine enters a machine error state and the system branches to the program used when an arror occur