Patent GB-1499010-A (GB)
Title: Transmission of digital information signals together with a preceding address signal
IPC: H04L12/54
Filed: 1975-09-30
Abstract: 1499010 Message packet switching SIEMENS AG 30 Sept 1975 [30 Sept 1974 30 April 1975 22 May 1975] 39989/75 Heading H4P A message packet switching system comprises storing information signals until a determined number constituting a message block 1 has been received, e.g. from a terminal, and in response to detection of the number applying such a block together with a preceding address signal to a switching device which establishes a connection only during passage of the block. The system allows the reception of data of different rates. A switching device may be a space multiplex exchange and the information block and address signals may be placed into separate stores. The switching devices may comprise a plurality of interconnected exchanges through which information blocks are routed, each exchange storing routing information designating the next exchange in sequence. Alternatively the information may contain addresses indicating individual exchanges on the route, each exchange erasing its own address. An address block may include a "clear down" signal. A receiver, at the remote end, which is not available for any reason can emit an erasing signal to the exchange to which it is connected. Terminal Tn, which may include a subset, is connected through hybrid circuit Gs to a transmitting store comprising Reg 1, 2 and a receiving store Reg 3; Reg 2, 3 may have a capacity of 492 bits and Reg 1 may store 8 sync. bits, 8 address bits, I parity bit and 3 information designating bits. A dialled address is passed through switch Sl  and OR gate GO1 into Reg 1, which when full causes switch S1 to reverse allowing information bits to be passed into Reg 2, which when a full detection signal is produced, gives a 1 signal on e input of control circuit Stl. This clocks on its output a the contents of Reg 1 both on a recirculating path including OR gate GO1 and also through GO2 on to a transmitting path into exchange setting device Es. Es checks whether external address path is free and an internal path through exchange Kf is available and if so establishes connection through Kf. When content of St1 has been clocked, output b provides a 1 to monostable circuit MF thus setting a bi-stable circuit in control St2 causing through a, Reg 2 to be clocked out through GO2. When all information bits have been clocked through exchange Kf, the path is released until the next address from Reg 1 is received. Information bits from Kf are received at a remote terminal into a register corresponding to Reg 3, which when a complete block has been received supplies a 1 to input e of St3 setting flipflop FF which closes S2 allowing n pulses from clock generator TGo, as recorded by counter C, to clock out the content of Reg 3 through hybrid circuit Gs to the local terminal. Register St1 stages are then reset for reception of another address by PR. It is possible to arrange transmission and reception consecutively in the same cycle. In Fig. 2 (not shown) messages pass serially through a plurality of exchanges each having an internal control store, e.g. Ccl, Fig. 3 (not shown), co-operating with an address store Es1 through a control store Sp1; signals from the local terminal are therefore received into Ccl and information blocks are not released until a path through exchange Kf1 has been established. The arrangement may work in either of two modes; store Spl may have a number of positions which are addressed and the appropriate setting up information emitted therefrom together with the designation of the next exchange in the chain, or alternatively the local terminal itself may provide a list of exchanges through which information blocks should pass. Each exchange sets up a connection for duration of signals only until they are passed, e.g. into Cc2 et seq.