Patent TW-201916038-A (TW)
Title: Semiconductor integrated circuit capable of reducing the time for writing even through it has large-scale resistive change element arrays
Inventor: HO YING-HAO
IPC: G11C13/00
Filed: 2017-12-29
Abstract: In one embodiment of the present invention, there is provided a semiconductor integrated circuit capable of reducing the time for writing even through it has large-scale resistive change element arrays. The semiconductor integrated circuit according to this embodiment comprises: m first wirings (m ≥ 1); n second wirings (n ≥ 1) three-dimensionally intersecting with the first wirings, respectively; k third wirings (k ≥ 1) three-dimensionally intersecting with the first wirings, respectively; m first current limit circuits arranged corresponding to the first wirings and connected to the corresponding first wirings; n second current limit circuits arranged corresponding to the second wirings and connected to the corresponding second wirings; k third current limit circuits arranged corresponding to the third wirings and connected to the corresponding third wirings; m first drivers arranged corresponding to the first current limit circuits and connected to the corresponding first current limit circuits; n second drivers arranged corresponding to the second current limit circuits and connected to the corresponding second current limit circuits; k third drivers arranged corresponding to the third current limit circuits and connected to the corresponding third current limit circuits; a first array; and a second array. The first array includes: m fourth wirings arranged corresponding to the first wirings; n fifth wirings arranged corresponding to the second wirings and configured to three-dimensionally intersect with the fourth wirings, respectively; m first transistors arranged corresponding to the first wirings, wherein one of the source and drain is connected to the corresponding first wiring, and the other of the source and drain is connected to the corresponding fourth wiring; n second transistors arranged corresponding to the second wirings, wherein one of the source and drain is connected to the corresponding second wiring, and the other of the source and drain is connected to the corresponding fifth wiring; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, wherein a first terminal is connected to the corresponding fourth wiring and a second terminal is connected to the corresponding fifth wiring. The second array includes: m sixth wirings arranged corresponding to the first wirings; k seventh wirings arranged corresponding to the third wirings and configured to three-dimensionally intersect with the sixth wirings, respectively; m third transistors arranged corresponding to the first wirings, wherein one of the source and drain is connected to the corresponding first wiring, and the other of the source and drain is connected to the corresponding sixth wiring; k fourth transistors arranged corresponding to the third wirings, wherein one of the source and drain is connected to the corresponding third wiring, and the other of the source and drain is connected to the corresponding seventh wiring; and second resistive change elements arranged in intersecting areas of the sixth wirings and the seventh wirings, respectively, wherein a third terminal is connected to the corresponding sixth wiring and a fourth terminal is connected to the corresponding seventh wiring.