Patent GB-1403386-A (GB)
Title: Data recorder
IPC: G11B15/52
Filed: 1972-08-04
Abstract: 1403386 Control of stepping motors MATSUSHITA ELECTRIC INDUSTRIAL CO Ltd 4 Aug 1972 [7 Aug 1971 20 Dec 1971 24 Dec 1971 (3)] 36575/72 Heading H2J [Also in Division G5] In a data recorder comprising a stepping motor (106) Fig. 1 (not shown) driving capstan (107) in use engaging the magnetic tape in a known cassette (101) for the recording and playback of digital data, the stepping of the motor M, Fig. 2 is controlled during playback by the recorded data itself, and during record by a read command input to terminal RCM allowing the recording of a data word with from ten, to sixteen or more bits on to the tape. D.C. reel motors (108, 109, Fig. 1) are provided. Recording.-A start pulse STA, sets flip-flop FFI enabling oscillator OSC, initially with pulse period (t 1 ) Fig. 3a (not shown), whose output is divided by scale of three counter C 1  and via binary counters C 2 , C 3  and C 4  with respective decoders D 1 , D 2 , D 3  causes the progressive energization of windings MC 1 -MC 4  of the stepping motor in the pattern of waveforms (D 3 -a, b, c and d) Fig. 3b (not shown). The presence of a signal at e of decoder D 3  causes the oscillator pulse period to double, by changing the emitter resistance of a unijunction transistor therein, such a signal being present when only windings MA 1 , MA 2  are energized and enabling smooth acceleration of the capstan, see Fig. 6b (not shown). When counter C 2  attains a count of six, a record enabling pulse signal WCL is provided enabling data recording in synchronism therewith via inputs WD 1 , WD 2  to recording heads H 1 , H 2 , ten pulses WCL being delivered. However, provided a data length control signal VLW is present, flip-flop FF 3  is set via AND gate G 19 , allowing continuing production of pulses WCL. In the absence of such a signal VLW, when C 2  attains the count of sixteen, counter C 3  commences to count, decoder D 2  causing, via terminal b, the slowing of oscillator frequency, via terminal c the reversing of counter C 4  for one received pulse and via terminal a the resetting of flip-flop FF 1 , and counters C 1 , C 2 , C 3 , the reading of the data word being complete. A similar stopping sequence takes place upon removal of signal VLW when more than ten bits are to be read in. The reversing of the counter C 4  produces a smooth, overrun free deceleration of the motor M; Fig. 6b (not shown), Playback.-A start pulse STA sets flip-flop FF 1  and hence the oscillator OSC is enabled, the presence of a write command signal RCM enabling transmission of data from heads H 1 , H, to outputs RD 1 , RD 2 . The data signals, via OR gate G 7  also reset flip-flop FF 2  releasing the reset of counter C 3 , which is reset by the data via OR gate G 9 . When data reception ceases, counter C 3 , now counting pulses from a of C 4 , reaches the count of two whence via c of decoder D 2  it makes counter C 4  count down for smooth stopping, as for reproducing above, and subsequently, at the count of three, via a of D 2  resets the system, the reading of a data word being complete. Stopping requires a lesser tape distance than for the corresponding function in record, so that no recorded data is passed over without being read.