Patent GB-1060928-A (GB)
Title: Transponder system
IPC: G01S13/78
Filed: 1965-11-08
Abstract: 1,060,928. Radio responders; transistor pulse circuits. BENDIX CORPORATION. Nov. 8, 1965 [Nov. 12, 1964], No. 47270/65. Headings H3T and H4L. The invention relates to an aircraft responder, wherein data, e.g. altitude and identity are stored in parallel by bit format in separate binary stores and one of the stores is read out under the control of a local oscillator clock to provide a reply signal in serial by bit format, said one read out store being determined by the type of interrogation code received by the responder. The interrogation pulse pair (P 1 ) and (P 3 ) for an identity reply is shown in Fig. 1A (not shown) and for an altitude reply is shown in Fig. 1B (not shown). These pulses are radiated on a main lobe (M) and side lobes (S), Fig. 2 (not shown). A side lobe suppression pulse (P 2 ) is transmitted in both cases, 2 Ás after pulse (P 1 ), on an omni-directional lobe (P 2 ). Interrogation is at 1030 Mc/s. and the response is at 1090 Mc/s. The interrogation signal is received at the responder by antenna 10 and is converted to an IF signal (60 Mc/s.) in receiver 15. After IF amplification (17) and video amplification (18) the signal is fed to a circuit 20 which determines whether pulses (P 1 ) and (P 3 ) have been received on the main lobe (M) or on one of the side lobes (S). If they have been received on the main lobe, their amplitudes will be greater than that of pulse P 2 , and if received on the side lobes, their amplitudes will be less. Circuit 20 comprises a two-stage transistor Schmitt trigger 22 having a first stage with a low output impedance feeding a capacitor 21, and a high impedance inverting network 23 applying the charge on capacitor 21 as a negative bias to the input of the trigger circuit. Pulse (P 1 ) triggers the trigger circuit to produce an output pulse therefrom and a charge across capacitor 21, which in turn produces a corresponding following negative bias at the input of the trigger circuit. This bias is such that for the side lobe reception case (P 2 >P 1 , P 3 ), pulse P 3  overcomes the bias and again triggers the trigger circuit to produce a corresponding 2 Ás spaced pulse output therefrom, whilst for the main lobe reception case (P 2 >P 1 , P 3 ) the pulse P 2  is not able to trigger the trigger circuit. Due to leakage of the charge on the capacitor, the bias has fallen when pulse (P 3 ) arrives, such that it triggers the trigger circuit and produces an output therefrom for both cases. Pulses (P 1 ), (P 2 ) and (P 3 ) are thus all reproduced at the output of circuit 20 for the side lobe reception case whilst only pulses (P 1 ) and (P 3 ) are reproduced for the main lobe reception case. A circuit comprising means 26 to 31 now reject all pulses having widths outside the range 0À4 Ás to 1À2 Ás. Means 28 only passes that portion of a pulse remaining after 0À4 Ás, which passed portion triggers a monovibrator 29 to produce a pulse of 0À8 Ás width which inhibits gate 27 for the period from 0À4 Ás to 1À2 Ás. Thus, a pulse of width 0À4 Ás causes no inhibitation of gate 27, and the pulse is passed via said gate to inhibit gate 30. Differentiator 26 produces a spike just prior to the trailing edge of the pulse which, however, is not passed by gate 30 to trigger monovibrator 31 due to the inhibitation of gate 30. With a pulse of width 1À2 Ás, gate 27 is no longer inhibited when differentiator 26 produces its spike. Gate 30 is therefore inhibited at the appearance of said spike and monovibrator 31 is not triggered. With a pulse of width between 0À4 Ás and 1À2 Ás, gate 27 is inhibited and gate 30 thus uninhibited during the spike output of differentiator 26. Monovibrator 31 is thus triggered and passes a pulse to a decoder and side lobe reception suppression circuit. This circuit comprises a delay line of total delay 21 Ás and with taps at 2 Ás and 8 Ás. Side lobe reception produces at the input to the circuit two pulses P 1 <SP>1</SP> and P 2 <SP>1</SP> separated by 2 Ás. The undelayed output of monovibrator 31 and the output from the 2 Ás tap on the delay line are therefore fed to an AND gate 33 which produces an output if pulses P 1 <SP>1</SP> and P 2 <SP>1</SP> are present. This output is used to inhibit gates 35 and 36 and stop any response to the interrogation. The undelayed output and the output from the 8 Ás tap are fed to gate 36 which thus produces an output when the interrogation is as shown in Fig. 1A. Similarly, the undelayed output and the 21 Ás delayed output are fed to gate 35 which produces an output when the interrogation is as shown in Fig. 1B. The outputs of gates 35 and 36 are combined in an OR gate 39 to produce a signal which triggers a monovibrator 40 to produce a pulse of duration longer than the required reply. This pulse enables an oscillator 41(689À655 kc./s.). whose output is converted to a pulse train by pulse former 42. The local oscillator clock pulses are thus produced and are fed to a binary counter 43. The altitude and identity data are stored in parallel binary form in respective N stage binary stores 45 and 46. The output of each stage of store 45 is fed to one input of a respective AND gate 45À1 to 45ÀN. The other inputs of the gates are fed by the outputs of respective AND gates 44À1 to 44ÀN, each of these latter gates being fed with a particular combination of the outputs of the stages of counter 43. The output of store 46 is similarly treated and the arrangement is such that each gate 45À1 &c. is opened in succession, and each stage in the stores is read out in turn, to produce on lines 47 and 48, the stored altitude and identity data in serial binary form. The outputs of gates 35 and 36 are also fed to respective altitude and identification monovibrators 37 and 38. To produce a pulse of width equal to the reply time. The outputs of 37 and 38 are respectively fed to AND gates 49 and 50 which have lines 47 and 48 respectively connected to their other inputs. The altitude or identity data is thus fed via OR gate 50 to a transmitter comprising driver stage 58, switching transistor 59 controlling oscillator valve 60, and output amplifier valve 63. Loose coupling is used at 62 and 64 to reduce interstage reaction. The outputs of monovibrators 37 and 38 are also fed, respectively to differentiators 53 and 54, to produce a spike coincident with the end of the reply time and used for resetting counter 43, and together, via OR gate 57, to means 19 causing the disabling of video amplifier 18 during the reply, and to an integrator/counter 56 which on a minimum number of replies being counted, sends a pulse diabling IF amplifier 17.