Patent GB-1407891-A (GB)
Title: Asynchronous time division multiplexer and demultiplexer
IPC: H04J3/07
Filed: 1973-04-12
Abstract: 1407891 Multiplex pulse code signalling INTERNATIONAL STANDARD ELECTRIC CORP 12 April 1973 [17 April 1972] 17539/73 Heading H4L A system for combining a plurality of asynchronous time division multiplex PCM signals into a synchronous time division multiplexed data stream employs a " stuff only "technique, i.e. bit speeds are such that it is not required that bits be subtracted from the data stream, and includes a stuff control circuit common to all the asynchronous data streams and an asynchronous time division demultiplexer which has a common destuffing control circuit. Data format.-The synchronous data stream, Fig. 1, comprises superframes A each superframe consisting of 64 midframes B and each midframe consisting of 15 subframes C. In each midframe, the odd-numbered subframes have 9 bits and the even-numbered have 8 bits, the first eight bits of each subframe being assigned, a bit at a time to the four or eight data groups since the system may be used in a 48 or 96 channel anode with four groups (48 PCM channels) or eight groups (96 PCM channels) respectively. The ninth bit in the odd-numbered subframes is assigned to the " overhead channel ", i.e. supervisory, synchronizing etc., signals (but not stuff bits) providing eight bits per midframe for this purpose. The overhead channel includes a stuff control and signalling channel C, digital voice orderwire (DVOW) channel V, digital data orderwire (DDOW) channel D, short sync. code S0(0) and S1(1) for synchronizing the midframe, a long sync. code L and (for 96-channel mode only) unused bits. The long sync. code is a 64-bit pseudo-random code which defines a superframe of 64 midframes. In one superframe, 8 words of 8 bits each are transmitted in the control channel C, the first 7 bits being a control code between transmit and receive circuits of a group and the 8th bit being used for signalling associated alternately with the DVOW and DDOW channels. The control words are 1111111 for a " stuff " message and 0000000 for a " no stuff " message and the signalling code 1 for ring and 0 for idle. The last short sync. bits of each superframe is deleted thus increasing the nominal rate of each group channel and making the " stuff only " method possible. General arrangement of multiplexer and demultiplexer.-Multiplexer 1, Fig. 4, accepts up to eight 6 or 12 PCM channel groups in the 96 channel mode or four such groups in the 48 channel mode, the four groups being scanned twice in each subframe and each group input being supplied to a transmit group module 3. Modules 3 recover the timing and store the data in a 4-bit buffer and the data is read out by timing signals generated by a transmit common module 4 controlled by clock signal generator 12. A common stuff control in module 4 periodically samples the state of each buffer to determine when stuffing is required and the stuffed synchronous data provides a multiplexed data stream into module 4. When stuffing is required, the same bit is read out of the buffer twice in succession. Multiplexing of framing or sync. bits, control bits, digital voice orderwire from coder 5, and digital data orderwire and data signalling from module 6 is also carried out in module 4 and the resulting digital supergroup is transmitted via a cable modulator and orderwire insertion module 7a where D.C. power and analogue voice orderwire from amplifiers 7 are added. A signalling generator 8 is coupled to amplifiers 7 to provide an indication when analogue voice orderwire is present. A group frame recovery and alarm module 9 checks each group data input on a time-shared basis and also the received group data outputs sequentially to operate group frame alarms at 10 giving a visual indication and audible alarm 11 if no acceptable frame sync. pattern is detectable. A functional alarm from module 4 and a traffic alarm from module 6 also go to the alarm summary module 10. During an alarm signal a dummy pattern from module 9 is substituted at the input to the clock recovery circuit and buffer in module 3 and this is shown by indicator 24. The received digital supergroup signal is supplied to module 17 where it is demodulated, separated into its components and the timing recovered. The analogue voice orderwire signal is supplied via amplifiers 7 to handset 15 and the associated signalling signal is coupled via detector 17a to logic circuit 18 which controls an audible alarm 11. Logic circuit 18 also receives the digital data orderwire and digital voice orderwire signalling signal from module 4 to actuate the alarm. The digital supergroup from module 17 is supplied to a common receive module 19 which, after framing has been checked at 20 which includes search logic for the short and long sync. signals, Fig. 11B (not shown) sends timing and destuff control signals to eight receive group modules 21, which include buffer stores, to demultiplex the asynchronous PCM pulse groups. Module 19 also supplies digital voice orderwire signals to PCM decoder 22 and digital data orderwire signals to module 23. When framing is not verified for the received data, module 9 actuates the group alarms. Modules 21 are controlled by a digital phase-locked timing source 24a to remove the jitter caused by destuffing.