Patent GB-950455-A (GB)
Title: Automatic test apparatus
Inventor: AVIS DONALD WILLIAM
IPC: G07C3/00
Filed: 1959-07-06
Abstract: 950,455. Sequential test apparatus. PYE Ltd. July 4,1960 [July 6, 1959], No. 23131/59. Heading G1U. [Also in Divisions G3 and H3] Relates to an apparatus for the automatic sequential testing of a plurality of characteristics of a manufactured article, comprising one or more separate comparator networks for each characteristic to be tested, each of which networks produces an electric current or voltage serving as a reference representing one limit value of the characteristic and wherein each characteristic, represented as a current or voltage, is compared in the appropriate comparator network or networks with the limit value or values of current or voltage. Means are provided in the apparatus for sensing the difference between the limit value or values of current or voltage and the current or voltage representing a value of the characteristic, for each characteristic to be tested, and for indicating whether each characteristic is within or outside the allowable limit or limits. In one form of basic comparator network (Fig. 1(a)) used in the apparatus according to the invention a voltage (representing a characteristic to be tested) is compared with a limit voltage preset on potentiometer P1. A sensing circuit SE1 determines the magnitude and polarity of the difference, and causes relays to operate and effect indicators if the characteristic voltage is not in its correct range relative to the limit voltage. A modified sensing circuit (Fig. 1(b) not shown) is described for use when the characteristic is represented as a current. The sensing circuit is as described Specification 950,456. In the overall test apparatus (Fig. 2) the article under test, which might be for example a cathode ray tube, internal combustion engine or camera is located on the test bed X and the required test inputs (some of which may be power supplies) are applied by the input transducers T1-T4. The voltages or currents representing the characteristics under test are produced by the output transducers T5-T8. These outputs are applied to the master switch SA1 which arranges the necessary combinations of the transducer outputs to give the correct representation of each characteristic under test and sequentially compares each voltage or current representing a characteristic with the series of reference units L1-L10. Each reference unit contains four reference limits, so that each characteristic can be tested against two pairs of limits, one pair set to wide extremes of allowable variation of the characteristic,the other pair to somewhat narrower extremes. The switch SA1 arranges that the comparison takes place through the appropriate one of four sensing circuits Sa-Sd, the outputs from which are applied through section SC1 of the master selector switch to memory storage devices M1-M10, which consist of self locking relays connected to control three colour indicator lamps E1-E10. An indication may thus be given of whether the characteristic under test is well within the proper limits (say by a green light) outside them (red) or near them (yellow). D1-D2 represent timer circuits for controlling the duration for which the master selector switch remains in any one position for testing any one characteristic. Other parts of the master selector switch, controlling other parts of the apparatus, are indicated at SB1,SB2,SC2,SC3,SD1,SD2 and SD3. In operation, the apparatus is started from the stand by safe position where indicator lamps E11 and E12 are illuminated by operating button K2. This applies a pulse from the solenoid control unit to the solenoid MS which moves the master switch to position 1. E11 and E12 are extinguished, and the timer circuit D1 (see Division H3) starts to operate. At the end of a timing period the test result information, which has been temporarily stored in memory M10, is used to illuminate the appropriate indicator lamp, and may also be fed to a printer if desired. The timer also tramits a signal back to E11 which is illuminated to indicate that the test is complete, and button K2 may then be pressed to initiate the second test. Alternatively this may be initiated automatically. The procedure continues until all tests are completed, and lamp E12 is again illuminated. At the end of a test sequence the memories are cleared and the test bed left safe to handle. Incorporated in the apparatus may be a servo system SS which can adjust the input conditions applied via the transducers T1-T4 so that standard conditions may be maintained in testing some characteristic of a series of devices, even though some other parameter which varies between individual devices may upset the measurement. In a preliminary test the output from the transducers T5-T8 are compared with an expected standard set of voltages taken from units RV1-RV4 through switch portion SD2. Any difference is applied to the balance detector BD, and used to control the servo system SS (see Division G3), the output of which is applied to analogue memory AM before being used to control the inputs to the devices under test applied through transducers T1-T4. After this preliminary operation, the analogue memory will retain the information for use in subsequent tests requiring the standard input conditions. A supply unit PS3 under the control of the switch section SB1 may be used to alter the supply conditions for specific tests. Stabilized power supplies for use in the apparatus are described (see Division G3).