Patent GB-1502675-A (GB)
Title: Apparatus for handling errors in a central processor
IPC: G06F11/14
Filed: 1975-04-25
Abstract: 1502675 Digital computers COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL 25 April 1975 [25 April 1974] 17396/75 Heading G4A A multi-programmed data processing system capable of containing processes which are in the course of execution, in the ready state, in the waiting state, or in the suspended state, comprises at least one CPU and at least one central memory, means for detecting errors, and error handling apparatus, the CPU containing a plurality of functional units and hardware operative to store the characteristics of a detected error and to perform retry operations, the outcome of the retry operations being reported to a microprogramme block operative to call up a central exception mechanism capable of interrogating the software. Functional units of the CPU set respective bits of an error register in the event of machine (hardware errors being detected therein, and some of the functional units are connected via an error bus to a further register to indicate the type of error (in the case of some functional units having more than one type). The presence of a set bit in the error register may be ignored, may freeze the CPU, may generate a request for an isolated test routine or may generate a trap request. A microprogramme trap for machine errors involves masking off (other) machine errors, and retrying the instruction provided it has not progressed too far (i.e. modified main memory or general registers) and provided (in the case of process mode) a retry bit respective to the process is set. (The system can exist in a process mode, carrying out instructions of a process, or a system mode, carrying out control operations for the system, or a critical transitory mode in which process or message queues are being manipulated or where there is a danger that other data involving the overall status of the system may be destroyed by an exception). Retry is repeated until successful, or until a current retry count (incremented at each retry) reaches an initial retry count (both counts read from memory) when after a delay of about 3 milliseconds, a second round of retries is tried similarly. (Of course, the mask on machine errors is removed during each retry to permit success or otherwise to be determined.) If the second round is completed, i.e. no success, or if the original instruction producing the error had progressed too far to permit retry, a "machine error" bit in a control mask register is set (if already set, a system check is called for), and a register in the ALU is loaded with class and type numbers identifying a machine condition exception. Then a microprogrammed "central exception mechanism" (which may also receive other exception indications directly) takes over control of the CPU (provided it is not in the critical transitory mode, as indicated by a "hardware gate" bit in the control mask register), the ALU register referred to is used to address an entry in an exception table in main memory, this entry being placed in a particular address in an auxiliary store to notify the software of the nature of the exception.