Patent GB-1535999-A (GB)
Title: Apparatus for controlling the video display of a standard television receiver
IPC: G06T13/20
Filed: 1976-03-11
Abstract: 1535999 Generating dynamic displays ALPEX COMPUTER CORP 11 March 1976 [12 March 1975] 09766/76 Heading H4T A display control system for a c.r.t., in particular for displaying games, messages or results of calculations, comprises a television receiver and a random access memory having storage positions each corresponding to a different image element of the display tube, means for writing into the RAM data corresponding to given images and means for reading out the data at a scanning rate equal to that at which the display tube is scanned. The RAM 32 has binary memory positions correlated exactly with the bars or dots forming the tube image and may therefore be regarded as a digital representation of the image. In the "display" mode, the data in the RAM 32 is read out under control of horizontal and vertical counters 58, 60 through address multiplexers 64. The counters 58, 60 are driven by a clock 62 synchronized with a master clock 52 which drives a TV sync generator 50. Thus, the data read out through READ gate 54 may be multiplexed with the sync. pulses in the generator 56 to yield a signal suitable for coupling to the antenna terminals of the TV set. In the write mode, control of the RAM 32 passes to a microprocessor (MPR) 40 which is programmed in known manner by a read-only memory 42A. The WRITE process may take place only during line and frame flyback periods to avoid interference with the display. The display in general consists of fixed image "devices" such as boundaries, goalposts and controllable image devices such as players, balls. Data is written into the RAM 32 in the form of blocks which may consist of up to eight vertically-stacked eight-bit data bytes. Thus, a ball may comprise three three-bit bytes and a player may consist of a line of binary ones within an 8 x 8 matrix. The address of each block may be the coordinates of one of its elements, e.g. the extreme top left element. The configuration and address of each device is stored within ROM 42A upon selection by the operator of a desired game. Additional data also stored upon operator selection includes speed of ball, orientation of player (stored as a coded angle), size of pitch, duration of game. During an initialization routine, the computer 40 pulls the device data from ROM 42A and transfers them sequentially to RAM 32 at respective initial addresses, whereupon the entire display appears on the tube display with the selected time being decremented at 1 sec. intervals. The computer 40 thereafter follows a routine in which it scans sequentially such of the operator's controls as have been selected for the chosen game. During a scanning cycle, an 8-bit byte is generated indicating the position of the various controls, the presence of a binary "one" in any position indicating an increment or decrement by a fixed amount of the address of a player, goalie, etc., or the increment or decrement of an angular code representing the orientation of a player. The ball remains in motion during the game, its speed and direction being determined by X and Y increments of its address during each scanning cycle. The computer 40 obtains current (or initial) addresses, angular codes, speed codes, boundary positions from RAM 42B, computes (where necessary) new addresses, codes and checks boundary limits including goals. Coincidence of ball and boundary addresses causes appropriate change in the speed code to be calculated to represent a deflection, or to increment the score. When the displayed device is of a dynamic character, a "display" routine must first erase the current image by writing 0's into the corresponding data block at its current address. The new address is stored in RAM 42B. When data is to be written into RAM 32, a command is produced on lines D 0 -D 3  of the I/O bus of the computer which is used to set a 4-stage counter 90. Fig. 8, forming part of the RAM control 72, Fig. 3. The counter counts up to 15 from 0 or some higher number determined by the input on lines D 0 -D 3 . Thus, this input determines the number of changes of the LSB and hence the number of bits to be written into (or read from) RAM 32. The LSB is coupled to one input of AND gate 92 the other input of which is derived from the set output of flipflop 94 which receives a RAM WRITE signal from command latch 70, Fig. 3. The gate 92 is opened upon receipt of alternate clock pulses (from clock B) when the BUSY line from flip-flop 94 is high. The output of gate 92 may also be used to increment the address latch 66. If it is desired to write only during flyback periods, a composite blanking signal is fed to NAND gate 98 which also receives an input from flip-flop 96 the latter being set by the microprocessor when appropriate. The output of gate 98 places the address MUX 64 under control of the microprocessor. Normally, data is read from RAM 32 in the absence of a WRITE SIGNAL from control 74. A third flip-flop 102 may be set by a RAM-READ pulse from the microprocessor to transmit an enabling pulse through OR gate 103 and AND gate 104 whereby the microprocessor may read the data stored in RAM 32. The other input to gate 104 is a pulse from the MPU enquiring as to the READ/WRITE status of the RAM which will be represented at the output of the gate. The specification contains a detailed sample MPU routine for playing a hockey game.