Patent GB-1535590-A (GB)
Title: Multiplication apparatus
IPC: G06G7/16
Filed: 1976-04-01
Abstract: 1535590 Multipliers HITACHI Ltd 1 April 1976 [4 April 1975] 13332/76 Heading G4G A multiplication apparatus for an indefinite number of factors comprises a logarithmic circuit for establishing a time interval proportional to the log of the amplitude of each factor in turn, adding together all such time intervals and feeding the aggregate signal to an antilogarithmic circuit which establishes a signal whose amplitude corresponds to the desired product. Both the log and antilog circuits may consist of a capacitance charged through a resistance at a constant arbitrary voltage and means which responds whenever the voltage on the capacitor reaches the value of one of the factors, or of the product. Thus, supposing a circuit RC to be subject to a constant source voltage E, the time taken for the voltage across the capacitance to rise to the value V x  of an input signal is given by:- where t 0  = RC log E (see Fig. 1B). If #t 1 , #t 2 , ... #t n  are the time intervals corresponding to the input variables (factors) V x1 , V x2 , ... V xn , the sum of the intervals is represented by If this signal is fed as a variable to a circuit RαCα subject to a constant charging voltage Eα, we have:- where V y  is the sought product. A time interval t y α is established by subtracting #tα from t 0 α = RαCα log Eα. Thus, when the capacitor Cα has been charged for a time t y α it acquires a terminal voltage (Eα-V y ) which is then subtracted from the voltage Eα. In practice Eα=E, the supply voltage. As shown, the inputs V ai  representing the factors are fed in turn through switches S 1  to a circuit 30, 31, 32, 33 the output of which is the difference voltage (E - V ai ). A comparator 5 detects the time at which the terminal voltage on capacitor 43 charged at the supply voltage E, reaches this value, and changes from "high" output to "low" output. A comparator 60 detects zero level of capacitor 43 and triggers a univibrator 61 which delivers a pulse of length t 0 . A logic circuit 70, 71, 72 establishes the difference #t between the time intervals delivered by the comparator 5 and the univibrator 61. The inverted output of the univibrator is used to control a switching transistor 42 for the capacitor 43 and also a circuit 21 for selecting the input switches S t . Both these elements are also under control of a "start" signal on lead 80a from a control unit 8. The latter also provides clock signals which are fed through logic circuit 100, 101, 102 to an up-down counter 110. A flip-flop 90 responds to the first and the (n + 1)th switching signals from switch control unit 21 such that the Q output is at "high" level during the switching of the inputs and at low level from the end of the switching period to the next "start" signal. A flip-flop 92 changes from "low" output to "high" output at the end of the switching period and reverts to low whenever the counter 110 counts down to zero. The logic circuit 100, 101, 102 controlled by NAND gate 72 and flip-flop 92 causes the counter to count up during the time when the intervals #t are being accumulated and to count down to zero immediately thereafter. The period of countdown thus represents ##t. A univibrator 120 controlled by flip-flop 90 establishes the time interval t 0 α whilst a flip-flop 93 establishes a time period extending from the end of the count-down to the incidence of the next "start" signal. A NAND gate 130 provides an output signal whenever both the outputs of univibrator 120 and flip-flop 93 are a "high" level, and this signal represents t y α. In order to obtain zero output whenever one of the input factors is zero, a comparator 301 is used to detect this state of affairs. A flip-flop 302 is controlled by the zero-detector 301 and the counter 110, such that the Q output changes to "high" level and closes NOR gate 131 whenever a factor is zero. The output circuit comprises a JK flip-flop 140 having outputs Q and Q which change from "low" to "high" and vice versa at each "start" pulse on lead 80a.