Patent GB-1108130-A (GB)
Title: Data store
IPC: G06F11/08
Filed: 1966-06-24
Abstract: 1,108,130. Memory store. INTERNATIONAL STANDARD ELECTRIC CORPORATION. 24 June, 1966 [25 June, 1965], No. 28286/66. Headings G4A and G4C. A memory comprises N elementary cells, each cell being able to store the sum of elementary bits of information applied to it during a writing period and to supply during a reading period a signal proportional to the sum of the bits of information received, means to select, at random during the reading or writing period, k cells among the N cells, each set of k cells constituting an address, means operating during writing to add in each cell selected information to that already stored there, means operating during the reading period and to which the output signals of the k cells are applied to sum the signals received from the k selected cells, and a threshold circuit provided for comparing the sum of the output signals with a threshold and for determining whether the stored piece of information in the k cells is a 1 or a 0 according to whether the sum is greater or smaller than the threshold. In one embodiment capacitors 20 are used as elementary cells, an address in a register 19 causes enabling signals to be produced on k, e.g. 300 of the N, e.g. 4000 output lines from a diode matrix 13 and a 1 on the write circuit 11 causes the appropriate AND gates 15 to enable constant current generators 16 to supply a current for a fixed period to the appropriate capacitors. A different address enables another 300 capacitors at random which may have some capacitors in common with other addresses. On readout a current proportional to the charge stored in each capacitor is supplied by circuit 18 and the currents from the k capacitors, each of which may store a different charge is summed in circuit 14 and compared with a threshold value in circuit 22 which sets a bi-stable circuit to indicate whether a " 1 " or a" 0 " is stored. In a second embodiment the N cells are situated on the circumference of a magnetic drum and data is stored in binary form in five parallel tracks 31a-35a, a new signal being added to the sum of the signal already stored in binary form, on a generatrix of the drum, and the new binary member being written back, e.g. if the cell under read heads 31-35 has received 5 inputs and a new one arrives a number 00101 is read out and a new number 00110 read back. Track 36a stores N " 1 "s to serve as a clock and synchronizing device and track 37a stores a single pulse to serve as a resetting signal for the other tracks. In operation data indicating that a particular item is in stock may be stored in the 300 cells constituting one address, data for 150 items may be supplied to the store using addresses picked at random so that some of the individual cells store data from more than one item. It can be shown that a threshold value can be calculated such that if the sum of the signals received from the 300 capacitors of one address is higher than the threshold value, or if the sum of the signals is less than the threshold value then the probability that a " 1 " was recorded in that address, i.e. that that particular item is in stock is 1 or 0 with an error of 0À5%.