Patent GB-1495780-A (GB)
Title: Coin checking and collecting arrangement
IPC: H04M17/02
Filed: 1975-07-01
Abstract: 1495780 Coin checking device INTERNATIONAL STANDARD ELECTRIC CORP 1 July 1975 [3 July 1974] 27683/75 Heading G4V [Also in Division H4] A coin checking device for a coin controlled station, e.g. a telephone station, has at least one coin channel communicating with a coin receptacle and coin collecting means which when operated enable a coin to reach the coin receptacle via the channel and to be collected therein, in which the device is able to check the passage of a coin in the coin channel and includes measuring means to measure the passage time of a coin along a predetermined location of the coin channel subsequent to the operation of the coin collecting means, and control means which are coupled to the measuring means and which are operated when the measured passage time is larger than a predetermined time to prevent use of the station. The circuitry shown includes a delay arrangement DZA, Fig. 1, a D.C. source DSC, a pulse shaper PSC, a fee translator FTC1, Fig. 1, FTC2, Fig. 3, coin collecting means comprising a coin collecting relay circuit CRC, Fig. 2, and a coin collecting logic circuit CLC, a coin collecting circuit CCC, Fig. 3, an antifraud circuit AFC, Fig. 4, and a warning circuit WCC, Fig. 3. The measuring means mainly comprises circuit CCC, signal gnerator AS2, monostable circuits MS3, MS9, MS10 and AND-gate Q9 to measure the passage time of a coin along a predetermined location of each coin channel after the operation of a coin collecting relay, and control means mainly including monostable circuit MS8, winding DLW2 and diode d1 which when operated prevents a coin controlled station from being used when the measured passage time exceeds a preset time of 70 milliseconds. These measuring means include a signal generator AS2, coin detecting means such as light emitting diode LED1 and photo-transistor FT1, comprises means such as monostable circuits MS9, MS10 and AND-gate G9, and gating means transistors T11-T14 controlled by the coin detecting means and by the signal generator and having an output coupled to the comparison means which are themselves coupled to the above control means. These gating means enable a signal train generated by the signal generator to be applied to the comparison means while the coin detecting means are detecting the passage of a coin, whilst the comparison means compare the duration of this signal train with 70 milliseconds and activate their output when this duration exceeds 70 milliseconds. The device also includes registering means mainly including monostable circuit MS3, bi-stable circuit BS4, and AND-gate G8 to register the operation of the coin collecting means, relay circuit CRC and logic circuit CLC, in bi-stable circuit BS4 and, to cancel this registration when the coin detecting means such as LED1-FT1 detect a coin passage. These registering means are coupled to the control means MS8, DLW2, d1 which are operated after the registering means have registered an operation of the coin collecting means and when after 250 milliseconds determined by MS3 this registration has not been cancelled by the coin detecting means. A trap is mounted in each coin channel to prevent coins which pass the trap from being withdrawn.