Patent GB-1135724-A (GB)
Title: Data processing
IPC: H03K19/173
Filed: 1967-04-25
Abstract: 1,135,724. Logic; adders. RADIO CORPORATION OF AMERICA. 25 April, 1967 [5 May, 1966], No. 18915/67. Headings G4A and G4H. An N-universal logic citcuit includes at least one asymmetric threshold gate having n (#6) inputs to which N (#n) digital arguments are applied, inputs not receiving arguments (if any) receiving 0 and/or 1 constant values, the gate output representing any positive threshold function among the N arguments. An asymmetric threshold gate is one in which not all the inputs are assigned the same weight. A block is N-universal if it can be used to realise any positive N-dimensional threshold function, by applying the arguments of the function, and possibly constant values, to the inputs suitably. A function of x arguments has dimension x if it is self-dual, i.e. if the value of the function for each possible set of values of the arguments is the complement of the value obtained if the values of the arguments in the set are complemented. If the function is not self-dual, it has dimension (x - 1). A 4-input, 4-universal gate is shown in Fig. 2, the inputs a, b, c, d being weighted 2, 1, 1, 1. Fig. 3 shows a 6-input, 5-universal gate with weights 3, 2, 2, 2, 1, 1, two other such gates also being possible, with weights 4, 3, 3, 2, 2, 1 and 3, 3, 2, 2, 2, 1 respectively. An 8-input, 6-universal gate has weights 5, 3, 3, 2, 2, 2, 1, 1. A 10-input, 7-universal gate has weights 13, 12, 9, 8, 7, 6, 5, 4, 3, 2. Each gate produces an output when the sum of the weights of those inputs which have 1, as distinct from 0, applied thereto, exceeds half the maximum possible sum. An inverse output may be provided instead of or as well as this. Thus the gates of the invention are like majority, minority or majority-minority gates respectively, but with " inputs " connected together at the gates to produce the weighting and reduce the effective number of inputs, the numbers of inputs listed above being this effective number. Fig. 7 shows a half-adder using two of the 4-universal gates of Fig. 2. Fig. 8 shows a storage circuit. Fig. 10 shows a full adder using the 5-universal gates of Fig. 3 to add two 4-bit binary operands x 3 , x 2 , x 1 , x, and y 3 , y 2 , y 1  Y 0  and a carry C i  and produce a 5-bit binary sum z 4 , z 3 , z 2 , z 1 , z 0  and a decimal carry C 0 . However the other 5- universal gates mentioned may be used instead. An equivalent conventional adder circuit using simple majority-minority gates is shown in Fig. 9 (not shown). Fig. 11b shows a 6-universal gate used as a combination flip-flop and calculator of a 3-argument majority function, usable for a binary carry calculation in a multiplier. With T 1  = T 2  = 0, w acquires the Boolean value w(xy + xz + yz) where w is its previous value. If T 1  and T 2  are now changed to 1, w acquires the value xy + xz + yz, i.e. the majority of x, y, z, which is maintained stored by putting T 1  = 0, T 2  = 1. An equivalent simple majority gate is also shown (Fig. 11a not shown). Fig. 12b shows the 10-input, 7-universal gate mentioned, used to determine if a 6-bit binary number exceeds the value 27. The gates may utilize transistors and resistors, or diodes. Boolean equations are given, in the Specification for some of the gates mentioned.