Patent GB-868309-A (GB)
Title: Improvements in or relating to electric frequency divider circuits
Inventor: CHITTLEBURGH WILLIAM FRANCIS S
IPC: H03K23/58
Filed: 1958-01-24
Abstract: 868,309. Electronic counting apparatus. STANDARD TELEPHONES & CABLES Ltd. Jan. 23, 1959 [Jan. 24, 1958], No. 2456/58. Class 106 (1). A frequency-divider circuit comprises a plurality of binary counting stages connected in cascade, and means for applying outputs from the last counting-stage to control the operation of one or more of the counting stages so as to cause the dividing factor of the circuit to differ by unity from an integral power of two. As shown, Fig. 1, a frequency divider for positive input pulses comprises n+1 binary stages Sl - S(n+1) each of which may comprise crossconnected transistors. Initially all the stages have a side " A " ON and side " B " OFF, a stage being switched by applying a positive pulse to the ON side or a negative pulse to the OFF side. Before counting commences, the stage S(n+1) applies potentials over lines 3, 4 to block a gate Gland open a gate G2 so that the first input on lead 1 switches the stage S(n+1) over a line 2 to provide a negative change in the output voltage on a line 5 and reverse the gates G1, G2, subsequent input pulses passing to the stage S1. Binary counting then proceeds in the stages S1-Sn until the 2nth pulse which switches the stage S(n+1) to produce a positive output voltage and reverse the gates Gl, G2, the next input pulse producing the same effect as the initial pulse. The output waveform is differentiated, only the positive pulses thereby produced being selected to produce division of the original train by a factor 2<SP>n</SP>+1. Connections may be made as required from the line 2 .to intermediate counting stages such as S(p+1), S(q+1), these stages being switched by the first input pulse, which also switches the stage S(n+1) so that when the subsequent counting takes place, the stages S(p+1), S(q+1) are effectively prevented from dividing by 2, the total count being reduced by 2<SP>p</SP>+2<SP>q</SP> to provide a division factor of 2<SP>n</SP> 2<SP>p</SP> - 2<SP>q</SP>+1. Further intermediate connections may be made if desired. To effect division by an even number, the conductor 2 may be disconnected from the stage S(n+1) and connected to one or more of the intermediate stages, the dividing factor then being 2<SP>n</SP>-2<SP>p</SP>-2<SP>q</SP>- ... In a modification, Fig. 3, the input is a series of alternately positive and negative pulses, the positive (or negative) pulses occurring at a frequency F, and the output is a wave or train of pulses of frequency F/N, where N=2n-1. Gates G1, G2 are controlled by the " A " and " B " outputs of the final counting stage Sn. Initially, all the stages have the " A " side conducting, and gate G1 is open. The first positive pulse switches the; stage S0 to generate a pulse which switches the stage S1, counting of the positive input pulses continuing until the 2<SP>n-1</SP>th positive pulse causes the stage S(n - 1) to be switched, thereby causing the stage Sn to be switched and a negative voltage change on the output lead 13 to.be produced. The conditions of the gates G1, G2 are now interchanged and 2<SP>n-1</SP> negative input pulses are counted. During this total period 2<SP>n-</SP><SP>1</SP> positive input pulses are effectively counted to give the required division factor. Intermediate feedback connections via gates Gp1, Gp2 &c. may be provided to give division by a factor of the form 2<SP>n</SP>-2<SP>p</SP>- ... - 1. Division by a factor 2<SP>m</SP>N, where N is odd, may be obtained by preceding or following the circuit of Fig. 3 with m ordinary binary stages. The binary stages of Figs. 1 and 3 may comprise transistors cross-connected in known manner, and circuits corresponding to Figs. 1 and 3 are described in detail (Figs. 5 and 6, not shown).