Patent GB-1409119-A (GB)
Title: Adaptive gate video gray level measurement tracker
IPC: G01S3/782
Filed: 1972-11-20
Abstract: 1409119 Optical tracking WESTINGHOUSE ELECTRIC CORP 20 Nov 1972 [6 Dec 1971] 53483/72 Heading H4D In tracking a target using a television system, one of a number of target constituent regions of different gray levels is selected as representative of said target, and is defined by a track rectangle, the centres of whose sides are all located upon the perimeter of the region, as seen in a T.V. display. A measurement window is defined at the centre of the track rectangle, and the video gray level therein is determined by amplitude searching with a processor. The coordinates of the centre of the track window define a track point, and the target is tracked by obtaining sample distribution measurements of gray levels to again define the selected region by a track rectangle, and determining the coordinates of its centre, so indicating target translation. As described, four tracking gates T1 to T4, Fig. 1, are set up about a measurement window M1 and are cross-coupled using as the reference axis for one pair the average of the rectangular co-ordinates of the other pair. The tracking gates coincide before acquisition of a target, but when this is effected, as by changing the line of sight of the T.V. system until the selected region appears in the window M1, error signals are generated causing the gates to move outwardly until they are positioned on the perimeter of said region. The video gray level is determined by an amplitude search, and is then tracked to compensate for any changes which may occur. In a circuit for gray level measurement input video is applied through a low-pass filter 1, Fig. 2, to an input of a tri-level comparator 2, which has three outputs. A control voltage E c  is applied by a zero order hold circuit 3 for two frame times, and is determined from a sampling of the output of an integrator 11. Small voltages Œd are also applied to the comparator 2, which provides logical "1" outputs as follows where V is the voltage corresponding to the applied video gray level.  Outputs a, b and c of tri-level comparator 2 are connected to sweep logic circuit 4 which functions to gate input video coincident accumulator 5 from either output b or c in each T.V. frame time. The line average value is coupled to the analog accumulator which sums the average line voltages over a frame time. The accumulator output is sampled once per frame and coupled to each of zero hold circuits 6 and 7. Zero order hold circuits 6 and 7 are keyed such that each retains its sample value for two partially exclusive frame times. Thus, zero order hold circuit 6 is keyed to receive the accumulation of output b in frames 1, 3, 5, et seq., and zero order hold circuit 7 receives the accumulation of output c in frames 2, 4, 6 et seq. The outputs of zero order hold circuits 6 and 7 are applied to differencing amplifier 8 and to analog OR circuit 9. In the absence of a stop sweep command, switch 10 is activated to its closed position and connects negative voltage -E to integrator 11 to produce a positive going sweep. If a stop sweep command does not occur before the sweep maximum value is exceeded, sweep level comparator 12 is switched and applies positive voltage +E to the input of integrator 11 by activating switches 13 and 14 to their closed positions. This causes positive voltage +E to be applied to the input of integrator 11 and sweep level comparator 12. Application of the positive voltage to the input of integrator 11 causes a negative integrator output voltage. The sweep level comparator 12 remains in its switched state until the sum of the positive input voltage produced by connecting +E thereto and the negative output voltage supplied by integrator 11 is less than zero. When this condition is reached sweep level comparator 12 switches again to open switches 13 and 14 and thus disconnect the positive voltage +E from the inputs of level comparator 12 and integrator 11. This causes a negative voltage to again be applied to the input of integrator 11, whereby the integrator sweeps positively. If during the sweep cycle the output of analog OR circuit 9 exceeds a preset threshold level, indicative that the sweep voltage is near the nominal control level, a stop sweep command is generated by threshold control circuit 15 which causes switch 10 to be activated to the open position thereby removing negative voltage -E from the input of the integrator 11. Integrator 11 thus stores the value it attained prior to removal of the sweep input voltage.  The error voltage produced by the differencing amplifier 8 is also applied to the input of integrator 11 and functions as a correction signal to correct the integrator output voltage until the difference between the outputs of zero order hold circuits 6 and 7 averages out to zero. When the difference signal between zero order hold outputs 6 and 7 averages out to zero, the error control voltage from differencing amplifier 8 of course is also zero. The gray level loop is then closed in a track condition. The stop sweep command is also coupled to the track circuits to initiate the track acquisition cycle.  On the average, the tracking gate is superimposed on the target such that half of its area is occupied by the gray level region.  Four similar but distinct tracking circuits are employed in the positioning of the tracking gates. The video input is binary as produced by the gray level processor and the process is equivalent to an area measure of error in which the tracking gate is convolved with a binary pattern target of limited area extent. The tracking circuits are conventional and may for example comprise analog range trackers employed in pulse-type radar systems. The tracker system provides an analog bipolar voltage of the gate centroid coordinates for coupling to any external camera positioning system (not shown) such as an external gimballed servo system, with zero voltage in each channel corresponding to the line of sight of the T.V. system. Fig. 5 is a block diagram of a horizontal tracking loop circuit wherein gray level video is applied to video gating circuit 20. The gray level video is gated by horizontal gate generator 21 and applied to a time discriminator 22. The described discriminator is illustrative of only one particular manner of practising the invention, and other discriminators may be substituted therefor. The pulse inputs to the time discriminator are both 0-1 logic level shifts which key switches in a bridge circuit of the time discriminator as shown in Fig. 6. The video and video switches 23 and 24 are respectively interposed between the positive (+E) and negative (-E) power supply sources and equal resistors R1 and R2. The series connection of resistors R1 and R2 is connected to one plate of capacitor C, the other plate being connected to ground. Fig. 7 (not shown) is a series of graphs illustrating the operation of the circuit of Fig. 6 under the assumed video and video inputs. When the transition is centred in the horizontal gate, the discriminator output voltage Eg at termination of the gate is zero. The output is sampled at the end of each line and coupled to analog accumulator 25, Fig. 5. The discriminator capacitor C is then discharged to zero at the end of each line so that the analog accumulator 25 accumulates the sum of the average error per line. At the end of each T.V. frame time, the analog accumulator 25 output is sampled and stored in a zero order hold circuit 26 and the analog accumulator 25 is then reset to zero. The output of the zero order hold circuit 26 is representative of the track error and the resultant error voltage is coupled to track integrator circuit 27. The horizontal gate signal is generated by a trigger signal derived by comparator 28 which compares the output of track integrator circuit 27 with the horizontal sweep. The horizontal signal gate is set so that zero error on the average is provided at the output of the hold circuit 26 which causes the tracking loop to close. In-another embodiment, the amplitude search means constitutes a gray level measurement system, Fig. 8 (not shown), for providing rapid acquisition of target gray level and optimization of gray level slice width of the selected target region, which includes means to provide four clutter windows, Fig. 9 (not shown), each respectively positioned adjacent a tracking window to measure the gray levels in the area immediately outside the selected target region. The gray level of the clutter window which is closest to the gray level of the selected target region is arranged to dominate the other gray level clutter measurements. The measurement window at the centre of the four tracking windows develops a nominal video level for the selected target region and means are provided for varying gray level thresholds in binary steps during the active scan time of the television system and making computations during the vertical blanking times to produce upper and lower threshold levels about the nominal gray level to determine the optimum gray level slice width which satisfies the condition that the clutter gray level closest thereto may be distinguished from the gray levels in the optimum gray level slice width.