Patent GB-1479939-A (GB)
Title: Programme-controlled data switching systems
IPC: H04Q3/545
Filed: 1974-07-26
Abstract: 1479939 Data switching system SIEMENS AG 26 July 1974 [25 Sept 1973] 33092/74 Heading G4H The invention relates to a programmecontrolled data switching system including connection circuits SA each of which, for identification of a line L connected thereto, is assigned a specific number 000-511. Each circuit SA includes a storage device into which an item of information occurring on the respective line can be transferred, and an element for producing a request signal a000-a511 upon such a transfer. For identification of each connection circuit which produces such a request signal, identification devices E00-E63, A0-A7, 50 are provided arranged in stages, each stage corresponding to a position or digit of the code used to characterize the connection circuits, the circuits SA and the stages being interconnected by request lines a via which the request signals are forwarded through the stages for processing and by resetting lines b via which resetting signals are conducted to terminate processed request signals. For coding and intermediately storing identification results produced by the identification devices as a result of the processing of the request signals there are provided coding elements CE, CA, CS and registers RE, RA, RS in respect of each stage of identification devices. As described, the identity of one of 512 lines is expressed in octal code, circuits SA, E and A being arranged in groups of eight. The request signal producing element may be a bi-stable, a second bistable being controlled by the resetting signal. Each circuit E, A contains a priority gating circuit so that the codes for lines L carrying information are produced in the order 000, ..., 511. The information may take the form of a polarity change on a line L. In the embodiment of Fig. 1, circuits SA are controlled by pulse trains T1 (interrogation) and T2 (transfer), and each stage contains a common mixer, coder and store M, C, R at the outputs of which appear the octal code for a selected circuit SA. Selection of, e.g. SA 000 results in request signals a000, a000, a0 via E00 and A0 to the last stage SO, and signals on leads c000, c00,c0 which are decoded at CE, CA, CS. The final output A from SO is applied to a central unit, and a resetting input B gives rise to resetting signals b0, b00, b000. In the embodiment of Fig. 4, each circuit E, A and circuit SO includes its own coder CE, CA, CS, decoder DE, DA, DS and stores RE, KE; RA, KA; RS, KS. Here each stage is controlled by a respective pulse train T2-T4 enabled or blocked by control signals AGSA, AGE, AGA (Figs. 7 and 8, not shown). Information on, e.g., line 000 gives rise to request and reset signals a000, &c. and b000 &c. as before, (stores KE, KA, KS), signals a000-a007 being encoded at CE of E00 to produce a signal which is stored in RE and decoded by DE to produce b000. The signal in RE is transferred as ce00 to store RE0 associated with AO, thence as signal ce0 to a store RE11 associated with SO to give the units digit ce. The request signal a00 is encoded at CA of AO and passed as a signal ca0 to a store RA1 associated with SO to give the tens digit ca. Finally, request signal a0 is encoded at CS to give the hundreds digit cs. Decoders DA, DS decode ca, cs to produce the resetting signals b0 b00.