Patent GB-1431832-A (GB)
Title: Converter apparatus
IPC: H02M7/155
Filed: 1973-03-28
Abstract: 1431832 Controlling rectifiers; control of DC motors WESTINGHOUSE ELECTRIC CORP 28 March 1973 [28 March 1972] 14919/73 Headings H2F and H2J In a converter for exchanging power between an A.C. supply 14 and a D.C. load 12, the conduction angle of controlled rectifiers is determined by means of a phase controller 40 including a phase locked oscillator 42 in dependence upon the error between a reference signal 32 and a feedback signal (such as IU) responsive to a predetermined converter parameter, and has means constraining the conduction angle between first and second end stops, said means in - volving sampling substantially sinusoidal timing waveforms derived at 46 from the A.C. supply 14 and applying said sampled timing waveforms to first and second threshold devices so as to provide first and second end stop signals. General.-The converter may include two three phase bridges comprising thyristors (SCR1 ... SCR6<SP>1</SP>), in anti-parallel so as to determine the direction of current in the field or armature winding of a D.C. motor 12. Current transformers 22 ... 26 and a rectifier 28 provide a unidirectional signal IU proportional to load current. The signal RB is arranged to have a magnitude and polarity indicative of that of the desired load current and is fed to a switching amplifier 34 (detailed in Fig. 2, not shown) arranged to convert this into a signal RU which is substantially unipolar. The desired and actual current signals RU and IU are compared in an error amplifier 38 which provides a signal Vc which controls the phase of a locked oscillator 42, pulses from which are distributed by means of a ring counter and gate drivers 44 to the respective thyristors in the converters 16, 18. A JK flip-flop in a selector 36 provides signals QoQo which determine which of converters 16, 18 are to be operative and hence the direction of current in load 12. Control of conduction angle by phase-locked oscillator.-Fig. 7 shows the phase - locked oscillator in which a capacitor 168 is charged via resistor 162 and periodically discharged by a programmable unijunction transistor PUT160; the resulting pulses are expanded at 170, inverted at 172 and distributed by ring counter 190 to respective gate drivers (Fig. 12, not shown) each comprising an amplifying transistor and clipping zener diodes, the output of which is transformer-coupled to the gates of the respective thyristors. When the error voltage Vc is zero, the oscillator 160 operates at six times the supply frequency but the frequency is changed in response to the error signal Vc being fed to the gate of PUT160 so as to increase or decrease the conduction angle accordingly. End stops.-The signals from the ring counter 190 (Fig. 7) are fed via NAND gates 202 ... 212 to an auctioneering circuit 214 where one pulse at a time samples the sinusoidal timing waveforms TW derived from the A.C. supply. When the error Vc is zero, clock pulses from PUT160 are timed to coincide with the peaks of the timing waveform TW, the auctioneering circuit 214 thus providing a continuous train of such peaks so forming a composite end stop signal CES which is passed via emitter follower 312 to turn on transistor 326 and turn off transistors 324 and 346. When it is desired to increase the load voltage, the error Vc becomes negative at the gate of PUT160, thus increasing the oscillator frequency. The control pulses A ....C from ring counter 190 thus advance with respect to the timing waveforms TW and the segments of the timing waveforms TW, selected by the auctioneering circuit 214 are progressively advanced down the slopes of the sine waves. When the resulting CES waveform becomes sufficiently negative to pass below a threshold set by variable resistor 334, transistor 326 turns off and 324 and 346 turn on, giving an increase at the gate of PUT160 which delays production of the next pulse. A further pulse is fed to the gate of PUT160 by means of the CES waveform via transistors 312, 326, 324 and 346 so that the frequency of pulses from 160 is held at its nominal value until the error voltage Vc is again reduced. When reversing polarity of output from the converters, a signal BS is arranged to turn on transistor 346 irrespective of the level of error Vc so that the PUT160 is inhibited from pulsing and the CES signal follows the waveform it was selecting until it reaches a threshold adjustable by variable resistor 406, when transistor 400 is turned off so as to trigger a JK flip-flop 410 which allows capacitor 422 to charge. If the CES is maintained below the threshold for more than 100Ás, transistors 414 and 430 will turn on, forcing a pulse from PUT160 which advances the ring counter 190 by one step. A further clock pulse is forced by the selection of the next signal of the timing waveform TW so that the frequency of pulses from PUT160 is normal.  Reversal of polarity of converter outputs.-The output polarity is changed by reversing the state of a JK flip-flop in selector 36 whenever both the load current is zero and the signal RU is either zero or negative. This may be achieved as in Fig. 2 (not shown) by having a gate responsive to these two signals. In Figs. 3 and 4 (not shown) the change-over is achieved by a pulse ESP derived from transistor 430 when the inverting end stop is reached. A bias signal IB may be fed to the error amplifier 38 so as to reduce the dead time when reversing polarity.  Modifications.-The converters 16, 18 may alternatively take the form of single phase bridges or half wave, three-phase circuits in which case the oscillator 160 would operate at two and three times the supply frequency respectively. A single set of gate drivers 44 may be provided, being switched from converter 16 to converter 18 as desired.