Patent GB-1189452-A (GB)
Title: A Device for Binary-Decimal Conversion
Inventor: CHINAL JEAN PIERRE EUGENE
IPC: H03M7/12
Filed: 1967-04-09
Abstract: 1,189,452. Binary-decimal converters. J. P. E. CHINAL. 9 April, 1967, No. 51454/66. Heading G4A. The invention is a binary-decimal converter of a type utilizing division. In a binary to binary-coded-decimal converter, the input binary number entered serially or in parallel into an input register is transferred in parallel to a main shift register, then divided by 2 by a shift, the result S being shifted out and gated to an adder-residuator in such a way as to obtain a pseudo-quotient (for a division by 5) X n+   1 X n  . . . X o  according to X k  = Sk + Xk - 2 + Rk - 1 (modulo 2) which is entered back in the main shift register, and a " carry over " word R n+   1 R n  . . . R o  according to R k  = Maj (Xk, X k -   2 , R k  - 1) (or R k  could be obtained utilizing S k  and not utilizing X k ), each " carry over " bit R k  being saved in a flip-flop for use in deriving the next bits X k+  1' R k+  1À In the above, S k  is a particular bit of the result S mentioned &c. This first type of operation is called " residuation." The four bits R n + 1 X n+  1 X n S<SP>1</SP> 0  where S<SP>1</SP>o was the low order bit shifted out (remainder) of the division by 2 are entered into an output shift register as one binary-coded-decimal digit, or the first 3 of these bits may be logically combined (recoded) so that the decimal digit is in 8421 form. Four correction bits, equal to 0000 if R n+   1  = 0 and being derived from X n+  1 and X n  otherwise, are entered into a 4-bit correction shift register. The main and correction shift registers are shifted out (the contents of the latter being used repetitively) and gated to the adder-residuator in such a way that the pseudoquotient and correction are added to obtain the quotient which is returned to the main shift register for use in a similar way to find the next output decimal digit, and so on. The shift registers could be of electronic triggers or magnetic elements or utilize a drum track. An auxiliary register of 2 bit positions could be used to hold the pseudo-quotient bits needed for calculating the following values of X k , R k,  the quantity S being retained in the main shift register, a subsequent subtraction of the remainder of the division by 5 giving the starting point for calculating the next output decimal digit. A plurality of auxiliary registers may be used in connection with respective target radices into each of which the input binary member is to be converted. End of the conversion is signalled when an all-zero quotient is reached. In modifications, the remainder R of the division of S by 5 is obtained, followed by S-R by subtraction, the residuator then determining the quotient S - R/5, the modifications variously using a subtractor, an adder and/or an extra adder-residuator with further registers and in some cases using less passes through the main shift register. Serial-parallel and purely parallel modifications use n adder-residuators or n adder-residuators per decimal order respectively, the parallel modifications having parallel adders for adding in the corrections. A binary-decimal converter as above may be used to convert data being sent from one arithmetic unit to another.