Patent ES-392443-A1 (ES)
Title: An input-output channel (i/o) willing to cooperate with the central treatment unit and the main memory of an electronic data processing system. (Machine-translation by Google Translate, not legally binding)
IPC: G06F13/12
Filed: 1971-06-19
Abstract: An I/O channel comprises a CPU interface unit and an I/O interface unit which operate concurrently and independently, the CPU interface unit to receive control data from the CPU, and the I/O interface unit to transfer data between I/O units and a main store in accordance with control data supplied by the CPU interface unit, whereby control data for a future data transfer is assembled in the CPU interface unit while a data transfer is taking place under the control of the I/O interface unit. The control data goes from CPU to CPU interface unit via a storage data register of the main store, there being one such register for each I/O channel (if more than one), but the storage address register of the main store is common to all I/O channels. The CPU interface unit has a data store and a data control store, and the I/O interface unit has an interface store, an address store, a count store and a buffer store, all these stores being associative stores with 3-state cells (though 2- state cells could be used), a primary and a secondary selector trigger per word location, the primaries and secondaries of a given store being connected as respective shift registers and with two input/output registers per store, Specifications 1,186,703 and 1,231,908 being referred to for details. Various fields of the input/output registers of the same and different stores are interconnected so that stores control themselves and each other, the I/O units and the main store address and data registers, using table-look-up operations. The data control store controls the data store. The data store receives from a channel control word the (main store) data address, data count, flags and command code, and also holds unit control words, and is connected to the I/O interface unit, including the address, buffer and count stores. The interface store controls itself, the other stores of the I/O interface unit and the main store, exchanges signals with I/O units as in Specification 1,264,095 (referred to), and maintains a count of the number of bytes in the buffer store. The count store holds a count of the number of bytes to be transferred between I/O unit and main store, and decrements it as transfer proceeds. The address store holds the main store address and increments it or decrements it as transfer proceeds. The buffer store acts as a buffer between I/O unit and main store, the primary and secondary selector triggers being connected as respective cyclic shift registers and indicating the next position available for storing a byte and the next position to be read out respectively. On input, each byte is stored twice in a respective word location of the buffer store, read-out to the main store being from either of the copies, avoiding the need for a crossover path (since the byte could be either byte of a main store half-word). On output, one byte is stored in each word of the buffer store, using the two possible positions alternately in successive word locations, or a stored bit in each byte may indicate which position is used. Fields of the two input/output registers of the address store are interconnected, as are fields of those of the count store. The address store includes a shift table. On input, the signals sent between the interface store and I/O-unit include "service in " and "service out" but time can be saved, in a modification, by using " service in " to set a service latch thus producing " service out " directly and setting an interlock latch which signals the appearance of " service in " to the interface store. The service latch is reset when " service in " drops but cannot be set again until the interlock latch has been reset by a signal from the interlock store provided for gating the byte from the I/O unit into the buffer store. The buffer store can be replaced by two stores which, on input, store input bytes alternately, each byte being duplicated in its respective word location in its respective buffer store, read-out to the main store being of one byte copy from each store simultaneously (or of a single byte from one store). The data control store in the CPU interface unit could alternatively be an associative read-only store. The buffer store could be a conventionally addressed store, the interface store holding and updating the addresses of the first and last bytes in the buffer store.