Patent GB-1377126-A (GB)
Title: Charge couple circuits
IPC: G11C19/28
Filed: 1972-01-05
Abstract: 1377126 Charge coupled devices RCA CORPORATION 5 Jan 1972 [14 Jan 1971] 20043/74 Divided out of 1377121 Heading H1K A charge coupled device is read out by means of a floating region arranged to receive transferred charge and having an output connection and a drain region coupled by an insulated control electrode to the floating region so that the latter can be selectively discharged. Fig. 5, illustrates how the output of a first shift register (upper part of the figure) is coupled to the input of a second register (lower part of the figure). The output end of the register comprises a floating region F and a drain region D which is connected to a negative supply. A gate electrode 14-(n + 1) is provided on the insulation between the floating and the drain regions. The floating region F is connected to a control electrode 16-0 at the input of an adjacent register which is provided with a second control electrode 17 and a source region S2 connected to a negative supply. The shift system uses a three phase supply and during the second phase #2 pulse the gate electrode 14-(n+1) is made negative to drain away any charge on the floating region which thus takes the potential of the drain region D. During the #3 pulse the potential well is moved to the last storage electrode 14-n which overlaps the floating region F and during the #1 pulse the stored charge, if any, is transferred to the floating region F and is used to control the input to the second register the second control electrode 17 also being pulsed during this interval. A stored charge ("1" state) in the first register produces a less negative control potential and results in no injection of charge ("0" state) in the second register, whereas the absence of stored charge ("0" state) in the first register allows the floating region to remain at a high negative potential and results in the injection of charge ("1" state) into the first potential well of the second register. The complements of the bits leaving the first register are thus entered in the second register. The coupling arrangement may also be used with four phase drive pulses, Figs. 8 and 9 (not shown). In a modification, Figs. 10 and 12 (not shown), the second control electrode at the input of the second shift register is omitted and the last drive electrode of the first register overlaps floating region to a large extent to produce capacitative coupling. A three level voltage supply is applied to this electrode to control the charge injection in the second register. The devices may be realized with alternate polysilicon and Al electrodes, control pulses may be applied to the source region, and two phase operation may be utilized, Figs. 13 to 21 (not shown). If desired an inverter, which may be an integrated MOS device may be arranged in the connection between the floating region of the first register and the input to the second register so that bits are transferred without inversion, Fig. 22 (not shown). In a modified system shift registers are arranged in pairs with corresponding stages carrying complementary bits. The floating regions at the ends of a first pair of shift registers are discharged by a pair of interconnected gates and a single drain region and are also connected to the inputs of a second pair of registers and to a pair of MOS transistors cross-coupled to form a bi-stable acting as a balanced detector, Figs. 23 and 24 (not shown).  The output of the last register of a system may be provided with two floating electrodes the first of which is connected to the input of the first register of the system and control and external input arrangements are provided so that the information may be recirculated or fresh information may be inserted as desired. The second floating region is connected to the input of a further shift register, transfer being permitted, or inhibited as desired by a control electrode, Fig. 25 (not shown). Mention is also made of the use of so called "Bucket Brigade" storage regions and of selfscanning-phesonsor arrays.