baber/WOPTO huggingface dataset:
Patent TW-425487-B (TW)
Title: Apparatus and method of controlling pan/tilt camera
Inventor: KIM WOON-YONG
IPC: G01S3/786
Filed: 2000-05-16
Granted: 2001-03-11
Abstract: Disclosed are apparatus and method of controlling a Pan/Tilt camera by rotating the camera directly to the positional coordinate of a target so that the pan/tilt camera may track and selectively photograph a face portion of the object intellectually. The controlling method comprises the steps of calculating a rotatory direction and a rotatory angle of the camera by using a central point of a camera screen and a central point of the target captured in the camera screen; and driving the pan motor and the tilt motor according to the timer interrupt signal having a regular cycle and rotating the camera on the basis of a predetermined rotating speed and the calculated rotatory direction and rotatory angle. Therefore, the apparatus and method make processing of software and the rotatory speed of the camera for tracking the target captured in the camera screen faster.
Patent TW-509941-B (TW)
Title: Semiconductor integrated circuit
Inventor: NAMEKAWA TOSHIMASA
IPC: H01L21/82
Filed: 2000-05-25
Granted: 2002-11-11
Abstract: A semiconductor integrated circuit comprises a first internal power supply circuit for producing a first internal supply voltage, a clamp circuit for short-circuiting an output node of the first internal power supply circuit and a first external power supply node, a power-on sensing circuit for, upon detecting a second external supply voltage having reached a specified value, producing a first control signal, a second internal power supply circuit responsive to the second external supply voltage for producing a second internal supply voltage, and a potential detecting circuit for, upon detecting the second internal supply voltage having reached a specified value, producing a second control signal. The clamp circuit is enabled by the first control signal from the power-on sensing circuit to short-circuit the first internal power supply node and the first external power supply node and disabled by the second control signal from the potential detecting circuit from short-circuiting, thereby allowing the first internal power supply circuit to produce the first internal supply voltage.
Patent TW-463197-B (TW)
Title: Method and system for driving a solenoid
Inventor: PATTANTYUS TAMAS I
IPC: H01H47/32
Filed: 2000-07-07
Granted: 2001-11-11
Abstract: A system and method for a pulse width modulated (PWM) solenoid driver with a reduced rate of power consumption. The system for driving a solenoid includes a solenoid, a current set-point for establishing a desired current flow through the solenoid, and a step-down regulator circuit for controlling the current through the solenoid based on the difference between the desired current flow and the actual current flow through the solenoid. The step-down regulator circuit has a low internal resistance of not greater than approximately 1 ohm which contributes to the reduced rate of power consumption for the PWM solenoid driver.
Patent TW-466735-B (TW)
Title: Method for forming multilevel metal interconnections with low dielectric constant insulating layers in a semiconductor device
Inventor: KIM II-GOO
IPC: H01L21/768
Filed: 2000-08-15
Granted: 2001-12-01
Abstract: A method for forming metal interconnections in a semiconductor device, comprises the steps of depositing a first insulating layer having a low dielectric constant as a lower insulating interlayer over a semiconductor substrate provided with a lower metal interconnection layer, depositing a second insulating layer having a low dielectric constant and a faster etching speed than the first insulating layer as an upper insulating interlayer over the lower insulating interlayer, etching the upper and lower insulating interlayers according to a first photoresist pattern formed on the upper insulating interlayer so as to produce contact holes exposing the lower metal interconnection layer, removing the photoresist pattern, and etching the upper insulating interlayer with selectivity to the lower insulating interlayer according to a second photoresist pattern formed over the upper insulating interlayer so as to produce trenches for forming an upper metal interconnection layer.
Patent TW-498108-B (TW)
Title: Structure and manufacture method of vacuum vapor electroplating full-scale laser transfer adhesive decoration
Inventor: CHENG DUNG-GUEI
IPC: C23C14/00
Filed: 2000-08-19
Granted: 2002-08-11
Abstract: This invention relates to the structure and manufacture method vacuum vapor electroplating full-scale laser transfer adhesive decoration, especially to the one whose required pattern only appears on the laser transfer adhesive decoration when adhering on an object; which mainly comprising: a plastic sheet is coated with a releasing layer processed by vacuum vapor electroplating and the releasing layer is then covered by a vacuum vapor electroplating metal layer through vacuum electroplating; next, a resin protection layer with a required pattern is formed on the coating metal layer by printing the required pattern on the resin and a corrosive alkaline solution is employed to etch away the vacuum vapor electroplating layer which is not protected by the resin protection layer; the corrosive solution is washed away by clean water and the article is left to dry; a self-adhesive layer of the same size as the pattern is printed onto the resin protection layer and a releasing paper is placed onto the self-adhesive layer to complete the manufacture of the present invention.
Patent TW-541671-B (TW)
Title: Semiconductor chip package method
Inventor: LIN CHUN-HUNG
IPC: H01L23/28
Filed: 2000-08-21
Granted: 2003-07-11
Abstract: A semiconductor chip package method comprises following steps: using an adhesive layer to adhere a semiconductor chip onto a substrate (or lead frame); performing a degassing process on the adhesive layer; curing the adhesive layer electrically connecting the semiconductor chip with the substrate (or lead frame); and using a molding compound to encapsulate the chip and a portion of the surface of the substrate. The invented semiconductor chip package method is characterized that a degassing step is used to assist discharging or removing air bubbles or voids in the adhesive layer. Therefore, during the curing process of the adhesive layer, occurrence probability of void is greatly reduced, which can improve the reliability.
Patent TW-430739-B (TW)
Title: Ear thermometer probe cover and method for producing the same
Inventor: HUANG YOU-CHIAN
IPC: G01K1/08
Filed: 2000-08-31
Granted: 2001-04-21
Abstract: The present invention provides an ear thermometer probe cover and a method for producing the same. The method comprises: (a) forming a film capable of being penetrated by an infrared light; (b) forming a sleeve having a closed end and an open end, the periphery of the sleeve, from the open end to the closed end, forming a plurality of excessive materials and the closed end forming a planar window; (c) thermally compressing the plurality of excessive materials to form a plurality of protruded plates; (d) cutting the plurality of protruded plates to form a plurality of cuts; (e) turning over the sleeve so that the plurality of cuts are located on the inside of the sleeve and the sleeve has a smooth outside; and (f) joining the open end of the sleeve with an annular base.
Patent TW-457562-B (TW)
Title: Plasma apparatus and plasma CVD film formation method
Inventor: TAKECHI KAZUE
IPC: H01L21/205
Filed: 2000-09-08
Granted: 2001-10-01
Abstract: A gas supply duct line 9 for supplying hydrogen gas, rare gas, etc. to the surface of a substrate 7, is provided separately from a first electrode 2 serving as a first plasma source for supplying such material gases as silane such that it can also generate a plasma. Thus, a high quality non-single-crystal silicon film can be formed even at a low substrate temperature with energy provided to the film deposition surface by supplying active hydrogen radicals, ions and rare gas radicals and ion, etc. to the neighborhood of the substrate surface.
Patent TW-I283680-B (TW)
Title: New oxabispidine compounds useful in the treatment of cardiac arrhythmias
Inventor: BJOERE ANNIKA
IPC: C07D295/26
Filed: 2000-10-06
Granted: 2007-07-11
Abstract: There is provided compounds of formula I, wherein R1, R2, R3, R4, R41 to R46, A, B and G have meanings given in the description, which are useful in the prophylaxis and in the treatment of arrhythmias, in particular atrial and ventricular arrhythmias.
Patent TW-473741-B (TW)
Title: Cable entry panel having wear-resisting layer for double twist bunching machine
Inventor: WENG WEN-BIN
IPC: H01B13/00
Filed: 2001-03-21
Granted: 2002-01-21
Abstract: The present invention provides a cable entry panel having wear-resisting layer for double twist bunching machine, which is employed to bunch a plurality of wires or long fibers. The cable entry panel includes: a panel main body; and at least a guiding ring, which is located on the panel main body. The present invention is characterized in that the panel main body has a wear-resisting layer, which is at least located on the surface of the longitudinal range of the panel main body defined by the guiding ring. Thus a plurality of wires or long fibers may pass through the guiding ring along the wear-resisting layer. The composition of the wear-resisting layer may be carbon fiber, silicon carbide fiber, glass fiber, aluminum oxide fiber, ceramic, or fiber cloth containing metal silk or metal mesh. Due to the wear-resisting layer of the cable entry panel in the present invention, wearing through of the cable entry panel may be avoided while the plurality of wires or long fibers passing through the cable entry panel. Therefore, the yield of the wire bundles or long fiber bundles may be increased by employing higher rotating speed.
Patent TW-472126-B (TW)
Title: Temperature control device and temperature control method for high-temperature exhaust gas
Inventor: TATEISHI MASATAKA
IPC: B01D51/10
Filed: 2001-03-23
Granted: 2002-01-11
Abstract: In a temperature control device comprising a temperature control tower for controlling a blown high-temperature exhaust gas to a proper temperature and discharging the temperature-controlled exhaust gas to the subsequent step side, the temperature control tower comprises a cooling water spray means for spraying cooling water to about the center of the gas flow of the high-temperature exhaust gas and a cooling gas injection means for injecting, cooling gas along the inner wall of the temperature control tower.
Patent TW-480156-B (TW)
Title: Apparatus and method for form-frying snack food product
Inventor: FORTI STEPHEN N
IPC: A23L5/10
Filed: 2001-04-23
Granted: 2002-03-21
Abstract: Apparatus and method for cooking snack food pieces features a drum-type fryer which transports individual, diecut piece preforms through hot oil contained within a cooking tank defined between the periphery of the drum and a housing in which the drum is contained. Vacuum transfer and feed rollers transfer the individual piece preforms from a diecutting roller assembly onto the drum for cooking, and a similar roller transfers the cooked snack food pieces from the drum to a take-away conveyor for subsequent, downstream processing. The pieces are retained by suction against molding surfaces of frying mold elements distributed over the periphery of the frying drum.
Patent TW-495886-B (TW)
Title: Method of suppressing boron outgas in oxidation process of sacrifice oxide layer for trench-type power transistor
Inventor: CHEN JEN-TE
IPC: H01L21/336
Filed: 2001-05-02
Granted: 2002-07-21
Abstract: The present invention provides a kind of method for suppressing boron out-gassing in oxidation process of sacrifice oxide layer for trench-type power transistor. In the invented method, nitrogen is continuously guided into the oven tube during the entire oxidation process; and this step is also conducted even in the main oxidation step (that is the step where the temperature is increased to the oxidation temperature and oxygen flow rate is set to the maximum value). High flow rate of nitrogen is guided into the oven tube in three steps, including the preparation step of rising temperature, rising temperature step, and environment stabilization step, before the main oxidation step, such that the ambient of the oven tube is made close to the saturation vapor pressure of boron.
Patent TW-558826-B (TW)
Title: Semiconductor fuse device and its manufacturing method
Inventor: YU TA-LEE
IPC: H01L23/58
Filed: 2001-05-08
Granted: 2003-10-21
Abstract: The present invention is related to a semiconductor fuse device and its manufacturing method. The invention includes the first, the second fuse layers, and the first, the second conducting wire layers. The first fuse layer has a doped region that has a gap. The second fuse layer covers on the first fuse layer such that a discontinuous region is selectively formed on top of the doped region gap of the first fuse layer for selectively providing an electrical connection. The first and the second conducting layers are located on both ends, respectively, of the second fuse layer and are electrically connected to the second fuse layer.
Patent TW-501074-B (TW)
Title: System, method and computer program product for representing object relationships in a multidimensional space
Inventor: AGRAFIOTIS DIMITRIS K
IPC: G06F15/18
Filed: 2001-05-08
Granted: 2002-09-01
Abstract: A method and computer product is presented for mapping n-dimensional input patterns into an m-dimensional space so as to preserve relationships that may exist in the n-dimensional space. A subset of the input patterns is chosen and mapped into the m-dimensional space using an iterative nonlinear mapping process. A set of locally defined neural networks is created, then trained in accordance with the mapping produced by the iterative process. Additional input patterns not in the subset are mapped into the m-dimensional space by using one of the local neural networks. In an alternative embodiment, the local neural networks are only used after training and use of a global neural network. The global neural network is trained in accordance with the mapping produced by the iterative process. Input patterns are initially projected into the m-dimensional space using the global neural network. Local neural networks are then used to refine the results of the global network.
Patent TW-501127-B (TW)
Title: Optical recording medium
Inventor: ARIOKA HIROYUKI
IPC: G11B7/2575
Filed: 2001-06-08
Granted: 2002-09-01
Abstract: The objective of this invention is to prevent the deformation of a light transmitting substrate or grooves due to excess heat of a laser beam when multilevel recording with five or more levels is performed in a recording layer by changing either the irradiation time or the irradiation power or both of the laser beam. The optical recording medium (10) has a recording layer (12) essentially comprising a dye and a light reflection film (18) formed on a light transmitting substrate (14). Virtual recording cells (40) are assumed in the grooves (16) of the recording layer (12), and in each virtual recording cell (40), recording marks (48A) to (48G) having different sizes in five or more levels are formed by modulating either the irradiation time or the irradiation power or both of a laser beam in five or more levels according to the information to be recorded so that the reflectance for light in the virtual recording cell (40) is modulated into multilevels and that the reflection level of the readout laser beam for reproducing is modulated into five or more levels. The light transmitting substrate (14) consists of a plastic material having a glass transition temperature (Tg) of 160 DEG C or less. The light reflection film (18) consists of a metal having a coefficient of thermal conductivity of 300 k/W*m<SP>-1</SP>*K<SP>-1</SP> or more and a film thickness of 50 nm or more.
Patent TW-508880-B (TW)
Title: Techniques for enhancing gain in a quasi-optic grid array
Inventor: ROSENBERG JAMES J
IPC: H01Q15/24
Filed: 2001-06-13
Granted: 2002-11-01
Abstract: The present invention discloses active unit cell topologies for quasi-optic grid array structures that make use of combinations of one of several broadband or frequency-selective positive (or regenerative) feedback networks, as well as multiple transistor configurations in order to enhance the gain of the grid array amplifier. These new topologies yield higher gain, extending the utility of the grid array amplifier to both new applications requiring higher gain, as well as to higher frequencies where the intrinsic gain of the active devices is lower. They also offer greater flexibility in impedance matching, improving the bandwidth and manufacturability of the design.
Patent TW-591653-B (TW)
Title: Method of manufacturing an optically scannable information carrier
Inventor: VAN SANTEN HELMAR
IPC: G11B7/12
Filed: 2001-06-14
Granted: 2004-06-11
Abstract: The invention relates to a method of manufacturing a master mold (1), which is used to manufacture an optical information disc, such as a CD or DVD. According to the method, a substrate (3) is provided with a photosensitive layer (5), which is subsequently irradiated by means of a radiation beam (7), which is focused to a scanning spot (11) on said layer by means of an optical lens system (9). A liquid, such as water, is supplied into a gap (53) present between the photosensitive layer and an auxiliary lens (59) of the lens system facing said layer. As a result, the size of the scanning spot is decreased and the information density of the information disc to be manufactured is increased. According to the invention, the liquid is supplied via a supply opening (69) which is positioned immediately adjacent the auxiliary lens (59), in a direction which, viewed from the scanning spot (11), is contrary to a direction (Z) wherein the substrate (3) is moved with respect to the lens system (9). Thus, the liquid supplied via the supply opening is transported immediately and exclusively into said gap (53), so that the amount of liquid to be supplied to fill the gap is limited. The supply opening is formed in a wall portion (65), which extends in an imaginary plane in which also a side wall (63) of the auxiliary lens (59) facing the photosensitive layer is present. As a result, a homogeneous Couette flow of liquid without air inclusions is obtained in the gap. This Couette flow does not cause any undesirable mechanical vibrations of the lens system. The invention further relates to a method of manufacturing an optical information disc, according to which method a master mold (1) is manufactured in a first step, and the information disc is manufactured in a second step by means of a replica process using said master mold. The invention further relates to a device (25) for the manufacture of a master mold by means of a method according to the invention.
Patent TW-544376-B (TW)
Title: Shot peening processing method and processed article thereof, peening material and the use thereof
Inventor: KUROSAKI JUNKOU
IPC: B24C1/10
Filed: 2001-07-31
Granted: 2003-08-01
Abstract: The present invention provides a shot peening processing method capable of giving high residual compressive stress even to metallic material having high hardness, and easily decreasing the surface roughness of a processed article, and also provides the processed article by using the shot peening processing. Namely, the present invention is a shot peening processing method using peening material which is 900 to 1,100 in Vickers hardness Hv and not more than 200,000 Mpa in Young's modulus and provides an article processed by means of the shot peening processing method. The processed article has a maximum residual compressive stress of at least 1600 MPa and a surface roughness below 5 mum.
Patent TW-518644-B (TW)
Title: Tester for semiconductor integrated circuits and method for testing semiconductor integrated circuits
Inventor: MORI HISAYA
IPC: H03M1/10
Filed: 2001-09-11
Granted: 2003-01-21
Abstract: To provide a tester for semiconductor integrated circuits that can test an A/D converter circuit and a D/A converter circuit in a mixed signal type semiconductor integrated circuit comprising an A/D converter circuit and a D/A converter circuit at high accuracy and at high speed. A test assisting device is provided in the vicinity of a testing circuit board on which a semiconductor integrated circuit to be tested is mounted. The test assisting device comprises a data circuit to supply analog test signals to the A/D converter circuit of the semiconductor integrated circuit to be tested, and digital test signals to the D/A converter circuit thereof, a measured data memory to store test outputs from the semiconductor integrated circuit to be tested, and an analyzer portion to analyze data stored in the measured data memory.
Patent TW-572825-B (TW)
Title: Method of forming articles of a composite material and said composite material
Inventor: SHIAU DENG-PO
IPC: B32B27/00
Filed: 2001-09-19
Granted: 2004-01-21
Abstract: The invention provides a method of forming articles of a composite material and said composite material. The method comprises: preparing a substrate, forming the composite material by hot press, cutting the substrate to a desired size, and forming the article by cold press. The method is carried out by bedding a film layer of TPU on two base surfaces of a base cloth layer, followed by covering a bonding layer on one of the film layer, hot pressing with a temperature of 120 to 180 DEG C and a pressure of 2 to 10 kg/cm<2> for 60 to 250 sec so as to bond the bonding layer on one of the base surface through the film layer closely to from a composite material, and followed by cutting the composite material to a desired size and forming the article of the composite material by cold press with a temperature of 100 to 130 DEG C and a pressure of 2 to 10 kg/cm<2> for 60 to 80 sec. The invention can form articles of the composite material having smooth faces and better bond strength by those steps mentioned above.
Patent TW-550954-B (TW)
Title: Circuit and method for adjusting width of fly-back pulse in video signal processing unit realized in one chip
Inventor: LEE JAE-HOON
IPC: H04N5/445
Filed: 2001-09-28
Granted: 2003-09-01
Abstract: A fly-back pulse width adjustment circuit and a method for adjusting the width of a fly-back pulse which are applied to a video signal processing unit realized as one chip are provided. The fly-back pulse width adjustment circuit is built into a video signal processing unit including a video amplifier, an on screen display unit, and a horizontal/vertical synchronous signal processing unit within the video signal processing unit realized as one chip. Moreover the fly-back pulse width adjustment circuit includes a pulse shaping unit which shapes the fly-back pulse received from the outside via an input terminal and then applies the shaped fly-back pulse to the horizontal/vertical synchronous signal processing unit, and a pulse-width adjustment unit which adjusts the width of the shaped fly-back pulse in response to a predetermined control signal, generates the horizontal blank signal having a different occurrence time from the result of the adjustment in response to a selection signal, and applies the horizontal blank signal to the video amplifier and the on screen display unit. The fly-back pulse width adjustment circuit which is provided as external components of a chip is designed to have a simple structure, and consequently it is possible to build the fly-back pulse width adjustment circuit into a video signal processing unit realized as one chip. Moreover, the width of a fly-back pulse can be adjusted by control of a microcontroller or a microcomputer, thereby applying the fly-back pulse width adjustment circuit to various monitors. In addition, the fly-back pulse width adjustment circuit can input the fly-back pulse via one terminal without an external circuit. Therefore it is easy to manufacture a printed circuit substrate with use of the fly-back pulse width adjustment circuit.