Patent GB-1059671-A (GB)
Title: Improvements in or relating to telecommunication systems
IPC: H04Q3/54
Filed: 1963-08-13
Abstract: 1,059,671. Automatic exchange systems. SIEMENS & HALSKE A.G. Aug. 13, 1963 [Aug. 13, 1962], No. 31941/63. Heading H4K. A telecommunications exchange has a central control system including a store having a plurality of storage cells for storing information relating to the states of subscribers' lines, exchange lines and connections, said cells being sampled cyclically by an information transfer control unit; information to be transferred to another exchange is collected from the store as soon as it is formed therein, but where the information is. to be employed within the exchange, the address of the storage cell which contains the information is fed to a connection setting-up control unit, which when ready samples the said storage cell and collects information therefrom, instigates the control operation appropriate to the information and then feeds information indicative of the control operation to said cell. Construction of stores.-Such a store (e.g. 4W) consists of a three-dimensional array of saturable cores, the x, y co-ordinates defining a cell having a number of cores to provide a multi-bit store associated with each pair of x, y coordinates. The z-co-ordinate defines the bit in question, and for each bit a read-out/write-in circuit (e.g. 4ZW) is provided. The co-ordinates of the cell for read-out or write-in are determined by the circuit 4TW, which enables the cell either in accordance with identities fed in at the bottom or from a scanner 4AW enabled from circuit 4Q. Use of store during setting up of connection.- A particular cell in general contains information (stored in the middle portion of a horizontal row) together with an address indicating where the information is to be directed (stored in the right hand three portions). The address 000 is associated with the circuit 4E which is the setting control circuit for the communication switching network. When the scanner 4AW encounters a cell containing this 000 address gates 4G1 . . . 4G4 become unblocked, and pass the address of the cell concerned to the control circuit 4E for retention until it is ready to use it (the circuit 4E may be engaged in another setting operation at this time). When the circuit 4E is ready it emits this address to the circuit 4TW to cause the interrogation of this cell, the gate 4M2 enabling gates 4K1 . . . 4K6 to pass the relevant stored information to 4E which evaluates the information, and instigates the setting of a call through the switching network, and passes the address of the cell to 4TW and the relevant information to the appropriate 4ZW circuits (over leads not shown) together with the address to which the information is to be directed. Alternatively some other empty cell in 4W may be used. When the cell is subsequently scanned by 4AW the information is read out. This may be for instance an instruction for operating relays (shown for convenience as cells) 4BR associated with a chosen intra exchange link circuit, or the line circuit of an outgoing interexchange line. The identity of this circuit is received by control circuit 4TR which directs the instruction received by 4ZR to the appropriate cell. The use of buffer stores is mentioned for the case where information has to be collected prior to transmission over an interexchange line, e.g. where digits have to be transmitted either as pulses or in multi-frequency code. Receipt of information from line circuits.-The line circuits are provided with saturable cores to indicate loop closure. The cores are grouped together in a store 4I. This store may likewise contain similar cores pertaining to incoming exchange lines. When an off-hook condition is noted during the scanning of these cores, the address of the subscriber or incoming line is transferred to a free cell in 4F. When during scanning by 4AW an empty cell in 4W is obtained gate 4M1 removes an inhibit from 4TW, stops 4AW from scanning and signals 4AF to commence scanning for a cell containing an address, and when one is found the address is read out and inserted in the six left-hand cores of the cell in 4W. Scanning of 4AW is now restarted and, when the address is read out of 4ZW, the core in 4I is sampled for the presence of a dialling pulse and, if present, this is signalled to 4D. Simultaneously the number of dial pulses registered to date is read out from 4W to 4P and addition takes place in 4P, the result being fed back to 4W. When the end of the train occurs 4TW by means not shown signals store 4U to accept the total from 4W. Store 4U then emits signals over 4u 1 , 4u 2 , 4u 3  indicative of fault conditions (e.g. if the value of the counted digit is too high) or of any priority conditions indicated by the digit. Arrangements may be provided to time the duration of a loop break to discriminate between dialled impulses and clear down. As shown a store 5F comprises cells 5BS for indicating the looped or open condition of associated lines and cells 5BF for indicating the free-or-engaged condition of the line. A " monitor " store 5U is also provided. The address generators 5AF, 5AU are arranged to scan alternately. On the first scan of a cell whose line has just gone offhook the 5ZS output enables gates 5K1 . . . 5K6 to insert the address in 5BH and also to change over the corresponding cell in 5BF to mark the line busy. On subsequent scans 5G1 is inhibited preventing the address from again being inserted in 5BH. When 5AU subsequently starts scanning, and when it encounters an empty cell it causes the address in 5BH to be inserted in the left-hand side of the empty cell. On subsequent scans the address is fed to 5TS, 5TF to read out the corresponding cells 5BS, 5BF. On the first sample with the loop closed 5G2 passes a signal which is stored in 5U. When the loop opens, inverter 5I passes a signal to 5TU to delete any previously stored information in the cell and pulses the adding circuit 5D, the result then being inserted in 5U. On subsequent samplings whilst the loop is open, the adding circuit 5D adds 1 and feeds the result back to 5U. Normally on a dial impulse only four or five such samplings will occur before the loop closes. When the loop closes 5G2 opens to store a 1 in an appropriate core in the 5U cell in question and circuit 5D is zeroized. The store is then interrogated over leads 5n to see if a dialling impulse has been stored, such interrogation clearing the information out of the store preparatory to receiving the next impulse. If the subscriber clears down, the count reaches 6 whereupon gate 5K7 conducts to pulse 5TU, 5TF to clear out the appropriate cells in 5U and 5F. Timing of operations.-Charts, Figs. 2, 3 (not shown), are provided to indicate when the control circuits 4Q, 5Q may enable the various scanners so that interference between insertion and extraction of information from the stores does not occur. In the first case a simple sequence is used, consisting of interrogation of line circuit by the free or engaged store; interrogation of free or engaged store by monitor, interrogation of monitor by the intermediate store, working between intermediate store and setting control circuit. Some overlap between the beginning of one cycle and the end of the previous cycle is permissible. Other intervals in the cycle may be allotted special functions, e.g. testing that the various control units are functioning correctly. In the second case interleaving of the periods allotted to the various functions is effected whereby operations may be speeded up.