baber/WOPTO huggingface dataset:
Patent TW-448222-B (TW)
Title: Thermally reworkable anisotropic conductive adhesive composition and process for attaching a component to a substrate by using the same
Inventor: IYER SHRIDHAR RATNASWAMY
IPC: C09J201/06
Filed: 1997-12-24
Granted: 2001-08-01
Abstract: The present invention discloses a thermally reworkable anisotropic conductive adhesive composition which comprises: (a) a thermally reworkable cross-linked resin produced by reacting, as cross-linking agent, one or more dienophiles having a functionality greater than one wherein the dienophile functionality is a cyclic derivative of maleic acid and one or more 2,5-dialkyl substituted furan-containing polymers, obtained by furanizing a copolymer of carbon monoxide and an olefinically unsaturated compound which contains 1,4-dicarbonyl entities in its polymer chains, wherein the 2,5-dialkyl substituted furan groups in the 2,5-dialkyl substituted furan-containing polymer and the dienophiles are combined in a molar ratio of from 10:1 to 1:5, and (b) one or more electrically conductive materials present in an effective amount ot provide a conducting medium in only one direction, which amount is in the range of from 5 to 60% by volume of the anisotropic conductive adhesive composition. The present invention further provides a process for attaching a component to a substrate. The process comprises: (a) providing a substrate; (b) dispensing on a portion of said substrate a thermally reworkable anisotropic conductive adhesive composition as recited in the above, and (c) attaching a component having conductive pads on the surface of the thermally reworkable anisotropic conductive adhesive composition dispensed on the substrate while the adhesive is a liquid under conditions effective to provide electrically conductive paths between the conductive pads on the component and the substrate while maintaining an electrically insulating property in the transverse direction, thereby bonding said component to said substrate, and providing an assembly.
Patent TW-417284-B (TW)
Title: Semiconductor integrated circuit device and flash EEPROM
Inventor: ATSUMI SHIGERU
IPC: H01L27/115
Filed: 1998-02-05
Granted: 2001-01-01
Abstract: To provide a semiconductor integrated circuit device wherein a plurality of transistors different in gate oxide film thickness from one another are integrated into one chip without degrading transistor characteristics. A plurality of external terminals (output terminals) on a semiconductor substrate where a plurality of two or more transistors different in gate oxide film thickness from one another, are connected with an internal circuit through an interface circuit. Transistors other than the transistor having the thinnest gate oxide film are used for the transistors P7, N7 connected directly to the external terminal. A thick-film gate oxide film transistor is used for a node in contact with an external power supply and requiring a high withstand voltage, and a thin-film gate oxide film transistor is used for a transistor not in contact with any external power supply, as mentioned above. Since only voltages that can be controlled by internal voltage drop are applied to the thin- film gate oxide film transistor. As a result, the degree of freedom in device/ circuit designing is significantly enhanced.
Patent TW-437266-B (TW)
Title: Method and apparatus for eliminating reflected energy due to stage mismatch in nonlinear magnetic compression modules
Inventor: PARTLO WILLIAM N
IPC: H01S5/042
Filed: 1998-02-18
Granted: 2001-05-28
Abstract: A high voltage pulse power generating circuit capable of eliminating secondary pulses due to stage mismatch in the stages of its magnetic pulse compressor circuit is disclosed. The pulse generating circuit source comprises a high voltage charge storing element which is periodically discharged into a nonlinear magnetic compressor circuit. A mismatch correction circuit coupled to each stage of the compressor circuit discharges the reflected energy due to stage mismatch and thus eliminates the reflected energy from being launched back into the load. In a preferred embodiment, the pulse power generating circuit of the present invention utilizes a diode and a resistor that is coupled to each stage of the magnetic pulse compressor circuit. Various embodiments are disclosed.
Patent TW-351782-B (TW)
Title: Electronic timepiece supplied by a generator driven by a mechanical power source
Inventor: FARINE PIERRE-ANDRE
IPC: G04C3/00
Filed: 1998-04-01
Granted: 1999-02-01
Abstract: A timepiece includes: an electromechanical converter comprising at least a permanent magnetic rotor and at least a coil coupled with the permanent magnetic rotor so reacted to generate a first electric energy; a mechanical power source mechanically coupled with the rotor so as to apply a first torque onto the rotor and force it to rotate at the specified direction at a preset revolution, the rotor is disposed at an angle to facilitate reciprocate movement; a time data display means linked with the rotor and the mechanical power source; an enslaving circuit including a signal generating and comparing means, the signal value is a typical representation of the difference of the actual angle from its desired angle of the rotor, the difference is an indication that the rotor regularly reciprocates at a specified speed, and the brake means responds to the signal, when the angular difference caused by the actual angle of the rotor exceeds the desired angle, the brake means will apply a brake torque onto the rotor to recover the rotor to the desired speed; the enslaving circuit further includes a control means in response to the comparing signal, this signal represents a lag occurred that the actual angle of the rotor is way behind the desire angle, the lag amount is in excess of the desired amount, the control means will exercise a second driving torque onto the rotor to gain the desire speed faster than the present speed the rotor reciprocates.
Patent TW-479150-B (TW)
Title: Reinforced substrate and flat panel display employing the same
Inventor: YOO MIN-SUN
IPC: G09F9/30
Filed: 1998-04-10
Granted: 2002-03-11
Abstract: A reinforced substrate for use in at least one of two substrates forming a flat panel display together with a display generating material filled between the two substrates, has a reinforcing structure for preventing bending of a substrate installed on one surface of the substrate. According to one embodiment, the reinforcing structure includes an array of hollow polygonal pillars formed of transparent glass or plastic. According to another embodiment, the reinforcing structure is made of transparent glass or plastic, and further includes a conductive film which is coated on one end surface of the hollow polygonal pillars and is then grounded to block electromagnetic waves generated inside the flat panel display. According to a still another embodiment, the reinforcing structure is made of conductive metal, and one end of the arrayed hollow polygonal pillars is grounded to block electromagnetic waves generated inside the flat panel display.
Patent TW-429551-B (TW)
Title: Formation of high speed and high coupling ratio flash memory with textured tunneling oxide
Inventor: WU SHIE-LIN
IPC: H01L21/8247
Filed: 1998-06-04
Granted: 2001-04-11
Abstract: This invention comprises the following steps: patterning the gate structure and form a polysilicon oxide on the sidewalls of the gate and then forming a silicon nitride spacer; forming the source/drain and removing the spacer to expose a part of source/drain; third, forming an undoped amorphous silicon layer on the surfaces of the gate, oxide and exposed source/drain; proceeding a dry oxidation to transform the amorphous silicon layer to a textured tunneling oxide between the amorphous silicon layer and the substrate; forming a polysilicon spacer and then forming another polysilicon on the gate; etching the polysilicon layer to define the floating gate; and finally, forming a dielectric layer on the floating gate and then forming a conductive layer on the dielectric layer for being used as a control gate.
Patent TW-373295-B (TW)
Title: Method for forming via hole in integrated circuit
Inventor: LIOU RUEY-HSIN
IPC: H01L21/76
Filed: 1998-06-26
Granted: 1999-11-01
Abstract: This invention discloses a kind of method for forming via hole in integrated circuit. Prior to making via hole wet etch step, using an additional argon implantation (Ar implantation) step to treat dielectric layer surface, then it can increase subsequent lateral wet etch speed, to improve via hole profile, making upper opening of the via hole to have better width in shape, it shall be advantageous to subsequent metal layer settling for step coverage property, and effectively reducing via hole resist value and its RC time delay.
Patent TW-455815-B (TW)
Title: Database for facilitating software installation and testing for a build-to-order computer system
Inventor: AMBERG RICHARD D
IPC: G06F9/445
Filed: 1998-07-27
Granted: 2001-09-21
Abstract: An apparatus for installing software onto a computer system includes a step table and a component table. The step table contains a set of software installation steps shared among different components of substantially all computer systems being manufactured. The component table contains a set of substantially all possible components that are included within computer systems being manufactured. The computer system corresponds to a family of computer systems and the apparatus further includes a family relation table, a family relation table and a family component relation table. The family relation table identifies the relationship between a set of software installation steps and each family of computer system being manufactured. The family component relation table identifies the relationship between the family of computer systems and the set of components. The family step relation table identifies the relation between a component and a set of software installation steps appropriate for the corresponding component.
Patent TW-430899-B (TW)
Title: Method of manufacturing cathode of plasma etching apparatus, and cathode manufactured thereby
Inventor: KIM JIN-SUNG
IPC: H01L21/306
Filed: 1998-09-30
Granted: 2001-04-21
Abstract: There are provided a method of manufacturing a cathode of plasma etching apparatus and a cathode manufactured thereby for making the inside of the holes formed on the cathode and the surface thereof as hard surface so as to prevent the particle generation. The method of manufacturing a cathode of a plasma etching apparatus comprises the steps of: (a) forming a plurality of holes on a silicon substrate of cathode of the plasma etching apparatus for inducing gas into the etching chamber therethrough; (b) carrying out a physical-surface treatment for the surface of the silicon substrate using slurry; and (c) carrying out a chemical-surface treatment for removing protrusions inside the holes formed on the silicon substrate, and on the surface of the silicon substrate using KOH.
Patent TW-523505-B (TW)
Title: Process improvement to produce low color trimethylolpropane
Inventor: SUPPLEE CAROLYN
IPC: C07C31/22
Filed: 1998-10-07
Granted: 2003-03-11
Abstract: Disclosed is a process for acquiring crude trimethylolpropane (TMP) of low reacted color. TMP is generally prepared by the condensation of n-butyraldehyde and formaldehyde in an alkali solution. The mixture is then concentrated and placed through an extractor. It has been found that a high concentration of low color TMP is present in the extractor and may by obtained by taking a slip stream of hot organic/water/TMP from the extractor and allowing the mixture to cool and phase separate. Upon separation of the phases, TMP generally having an acid wash color of about or less than 5 GU is recovered from the water phase. Disclosed is use of a single and multistage extractor.
Patent TW-409259-B (TW)
Title: Memory array with reduced charging current
Inventor: BROX MARTIN
IPC: G11C11/41
Filed: 1998-10-27
Granted: 2000-10-21
Abstract: The spacing of the bit lines and/or the master bit lines (MBLs) of a memory array is skewed to decrease the charging current required to precharge the bit-lines and or the master bit lines. In one embodiment of the invention, an integrated circuit (IC) includes an array of memory cells arranged in rows and columns, with a pair of bit lines (BLTi and BLCi) per column of memory cells with BLTi carrying the cell data and BLCi its complement. The bit lines are disposed within a first level of the IC and run generally parallel to each other wherein there is a certain capacitance, CINT, between each two paired bit lines (BLTi and BLCi) and a capacitance, CEXT, between the bit lines of adjacent columns. The bit lines are coupled to selected MBLs with the MBLs being paired so that one MBL of a pair (MBLT) carries bit line data and the other MBL of a pair (MBLC) carries the complement of that bit line data. The MBLs are formed on a second level of the IC and run generally parallel to each other wherein there is a capacitance (MCINT) between the two paired master bit lines and a capacitance (MCEXT) between the master bit lines of a pair and the adjacent master bit lines. The spacing between the bit lines is skewed in order to decrease CINT relative to CEXT, and/or the spacing between the MBLs is skewed in order to decrease MCINT relative to MCEXT.
Patent TW-410413-B (TW)
Title: Semi-conductor mounting apparatus with a chip gripper travelling back and forth
Inventor: SCHINDLER SAMUEL
IPC: H01L21/00
Filed: 1998-11-23
Granted: 2000-11-01
Abstract: A ""pick-and-place"" apparatus of this type has a first pivoted lever (10) driven in alternating directions of pivoting, the drive shaft (4) of which is mounted centrally between a first location (A) and a second location (B). In the end positions (Ea, Eb), which delimit the pivoting range (<PHI>), the pivoted lever (1) always faces towards one location (A) or the other location (B). A second pivoted lever (12) is mounted at the end of the first lever (10) and driven in the opposite direction thereto and with a predetermined gear ration (n) thereto, for example, resulting from a fixed toothed wheel (5) by means of a toothed belt (6) and a further toothed wheel (7). The chip gripper (20) is connected to the end of the second lever (12). The gear ration (n) and the lengths (h1, h2) of the two levers (10, 12) are matched to each other such that in both end positions (Ea, Eb), the two levers are in an extended position with respect to one another and the chip gripper (20) is over the one location (A) or the other location (B). The pivot planes of the levers (10, 12) can be perpendicular or parallel to the planes of the chip carrier (32) and/or of the substrate (38) upon which the chips (30) are mounted.
Patent TW-430790-B (TW)
Title: Method and device for writing optical record carriers
Inventor: SPRUIT JOHANNES H M
IPC: G11B7/126
Filed: 1998-12-22
Granted: 2001-04-21
Abstract: A method is described for optimizing recording conditions for writing information on an optical record carrier. The information is written on the record carrier in the form of optically detectable marks, each mark being written by a pulse series of radiation. A series of test patterns is written on the record carrier (1) for the optimization. A jitter detector (11) measures both the leading-edge and trailing-edge jitter of the read signal. The leading-edge jitter is used to optimize the value of a parameter influencing only the leading part of a pulse series. The trailing-edge jitter is used to optimize a parameter influencing only the trailing part of the pulse series.
Patent TW-451005-B (TW)
Title: Process for assembling a funicular element in a shed forming device in weaving loom of Jacquard type, shed forming device on weaving loom of Jacquard type, and weaving loom of jacquard type comprising the above shed forming device
Inventor: BOURGEAUX PIERRE
IPC: D03C13/00
Filed: 1998-12-23
Granted: 2001-08-21
Abstract: This invention relates to a process for mounting a funicular element in a shed forming device of a weaving loom of Jacquard type, wherein it consists in fixing at least one end of the funicular element on a pulley adapted to receive this funicular element wound over at least one turn and driven in rotation by an electrical rotary actuator, and in disposing means for removable connection between the funicular element and the actuator. The device comprises means for removably connecting the end of the funicular element on the pulley.
Patent TW-426908-B (TW)
Title: Method of SOG coating
Inventor: WU JR-DA
IPC: H01L21/304
Filed: 1999-01-11
Granted: 2001-03-21
Abstract: The present invention relates to a method of SOG coating, and particularly to a method of SOG coating that can greatly reduce the working hours and reduce the operation cost of SOG. The method comprises: reducing the rotation speed of a wafer rotation machine to between 2000 rpm and 300 rpm so as to reduce the amount of SOG thrown out by the centrifugal force, and quickly fill up the gap between the metal wires by the SOG, thereby obtaining the thickness and the planarity required by the production. Furthermore, there is only one SOG coating process required so that the working hours can be greatly reduced and the operation cost of the SOG can be saved.
Patent TW-409330-B (TW)
Title: Repairable multi-chip module package
Inventor: HAN TZUNG-LI
IPC: H01L23/12
Filed: 1999-03-20
Granted: 2000-10-21
Abstract: A fabrication method and structure of repairable multi-chip module package are provided. Firstly, the package substrate having the welding pad and the welding pad is utilized for repairing. Several chips are pasted on the substrate and disposed on the same side with the welding pad and the welding pad for repairing. The substrate is electrically connected with the wiring lines. Then, the substrate and the chip are tested. When the error block is found, the wiring lines are removed in the error block. Then, the chip is stacked on the error chip. Then, the repairing wiring lines are used to connect the replaced chip and the welding pad for repairing. Then, the re-testing of the electrical performance and function is proceeded toward the substrate, the chip and the replaced chip. When the detected result is normal, the fabrication of the finished package is proceed after sealing. Once the error block is found, the repairing steps are repeated.
Patent TW-466289-B (TW)
Title: Construction method of an environmental permeable concrete pavement
Inventor: CHEN RUEI-WEN
IPC: E01C7/14
Filed: 1999-06-17
Granted: 2001-12-01
Abstract: A construction method of an environmental permeable concrete pavement includes following processes: (1) sand layer pavement; (2) inserting hollow column-like water guiding pipe into unit frame; (3) placement of the frame inserted with water guiding pipe on top of the sand layer; (4) concrete grouting; (5) pavement unit composition; (6) detachment of water guiding pipe cap after concrete sets. Through processes mentioned above, a permeable concrete pavement is built with little chance of water silt for water guiding pipe will lead water running into and being absorbed by sand layer.
Patent TW-408430-B (TW)
Title: The manufacture method of the DRAM
Inventor: CHEN JUNG-YI
IPC: H01L27/108
Filed: 1999-07-01
Granted: 2000-10-11
Abstract: A kind of manufacture method of DRAM, which is to integrate the shallow trench isolation (STI) structure and the storage node process into DRAM, and catering to the structure of BOC to make the capacitor layout on part of the STI structure to utilize the depth of the trench to increase the surface area of the storage node. And in the process of fabricating the capacitor, form the stacked plug used to connect the bit-line and form the stacked type plug used in the inner-lining on the circuit region; then, cover a layer of insulated layer on the capacitor and form the opening that exposes the stack type plug on the insulated layer; then, form the bit-line and the inner- lining on the insulated layer, and is electrically coupling with the stacked plug and the electrical-conductive layer in contact with the source/drain region.
Patent TW-I245165-B (TW)
Title: Photosensitive siloxane resin composition and patterning method using it
Inventor: RARK JUNG-MOON
IPC: G02F1/13
Filed: 1999-07-05
Granted: 2005-12-11
Abstract: The present invention relates to a photosensitive resin composition which is useful in patterning of a substrate plate of a reflective type thin film transistor-liquid crystal display (TFT-LCD) or an insulated layer between layers, and a patterning method using this composition. In this photosensitive resin composition for manufacturing TFT+LCD, a photosensitive resin composition comprising a polyphenol based supporting binder selected from a siloxane based polymer binder, polyhydroxystyrene or polystyrene-hydroxystyrene, a photo acid generator, and a cross-linking agent has characteristics including good transmissivity, heat resistance, insulation, and flatness resulting in advantages such as reduction of power consumption and the manufacturing process of LCDs.
Patent TW-411597-B (TW)
Title: Method of manufacturing dual damascene structure
Inventor: LIU MING-HUEI
IPC: H01L23/50
Filed: 1999-07-09
Granted: 2000-11-11
Abstract: A method of manufacturing a dual damascene structure is provided. The manufacturing method includes the steps of sequentially forming a first etching stop layer, a first oxide layer, a second etching stop layer and a second oxide layer on a semiconductor substrate. A selectively etching process is performed on the second oxide layer, the second etching stop layer and the first oxide layer to expose the surface of the first etching stop layer to form a contact hole. A liner layer is formed on sidewalls and bottom of the contact hole. A selectively etching process is performed on the second oxide layer and the liner layer to expose the surface of the second etching stop layer to form a trench. Further, the liner layer located in the contact hole and the first etching stop layer are removed to form the dual damascene structure. The foregoing manufacturing method can protect the integrity of the contact hole and increase product reliability.
Patent TW-450887-B (TW)
Title: Automatic calibrating method subjecting parison configuration of a blow molding machine to follow servo-circuit control parameters
Inventor: HUANG JI-JEN
IPC: B29C49/78
Filed: 1999-07-23
Granted: 2001-08-21
Abstract: This invention is related to an automatic calibrating method subjecting parison configuration of a blow molding machine to follow servo-circuit control parameters, which is a user-interactively, automatic calibrating method. The user may first conduct necessary system configuration. Based on the user's configuration, the control program then searches for parameter ranges suitable to the servo circuit. Based on the performance index selected by the user, the proportional, integral, and derivative gains for wall thickness in the control circuit are automatically adjusted in the suitable parameter ranges. Upon adjustment, in the process of extruding molten plastic material of the blow molding machine, the servo circuit controls the opening sizes of the extruding cylinder based on the parison wall thickness distribution as previously configured, for controlling the parison wall thickness, such that the wall thickness of the product made by blow molding is evenly distributed, so as to effectively reduce material consumption, and to enhance product strength.