Patent GB-1352676-A (GB)
Title: Process control computers
IPC: G06F19/00
Filed: 1970-05-04
Abstract: 1352676 Process control computer APV CO Ltd 26 April 1971 [4 May 1970 16 Nov 1970] 21361/70 and 54461/70 Heading G4A A process control computer includes a memory, a number of function circuits, data control unit connected to the memory and a number of registers at least some of which are directly accessible by external devices, the data control unit being arranged to cause the function circuits to perform arithmetic or other operations on data stored in the directly accessible registers and non-arithmetic operations on data stored in the memory. The computer may control, e.g., a food processing plant or a welding system and consists of an array of registers R 0 -R 37  which are formed together with respective decoders either singly or in groups on plug-in printed circuit cards. Data is supplied from within the computer to the registers in series along a common bus B<SP>1</SP>, the registers being selected by an address fed by means of a bus AD1 to the decoders. Data is fed out of the registers in a similar fashion via a bus B when addressed via bus AD2. The registers R 0 -R 3  and R 35 -R 37  have no external connections but the remaining registers are connected via A-D converters and 16-bit parallel data lines directly to transducers monitoring the process. Function circuits, also provided on plug-in printed circuit cards, are provided and are selected as required by a further addressing bus. A number of function operations are provided, e.g. program jumps, addition, comparison, memory fetch, binary- B.C.D. and vice versa conversions. The register IAR is incremented by timing signals, and accesses the memory which may be a core store, the accessed word being of 16 bits and being fed to the OP register. The first four bits specify the function and are fed to a function address latch which via the addressing bus selects the required function. The remaining 12 bits define the registers to be employed in performing the function, bits 5-6 defining one of four A registers, bits 7-11 defining a B register, and bits 12-16 defining a B<SP>1</SP> register. The B<SP>1</SP> register may be the same as the A or B register. The selected function is then performed on the contents of resistors A and B and the result fed to the B<SP>1</SP> register. Each processing cycle is of 20 Ásecs. in duration and is split into two halfcycles of 4 and 16 Ásecs. respectively. The function may be a jump instruction which is accessed from memory, the instruction at which the main sequence was interrupted being stored in a register and transferred to the appropriate point in the main memory following the subroutine for re-entry into the main sequence. The first four bits of the instruction specify the selection of the jump function and the remaining 12 bits the address to be jumped to. A number of jump sequences may be nested. The system may be loaded manually and a display is provided, the loading and display being in octal, binary, or decimal as required. In the event of a power failure a number of capacitors provide sufficient power for the machine to enter a save routine in which the volatile register contents are transferred to specified locations in the non-volatile main memory.