Patent GB-1170160-A (GB)
Title: Code Checking Systems
Inventor: KATSURAGI SUMIO
IPC: G06F11/10
Filed: 1967-10-26
Abstract: 1,170,160. Character recognition; error detection and correction. TOKYO SHIBAURA ELECTRIC CO. Ltd. 26 Oct., 1967 [31 Oct., 1966], No. 48728/67. Headings G4A and G4R. In a code checking system, a series of characters is converted into a series of digits, erroneous digits or digits corresponding to rejected characters being corrected/replaced in accordance with one or more weighted sum check digits, the sums being modulo a prime number. Generating check digits.-Three check digits follow the series of characters. Each is the 11- complement of a modulo-11 weighted sum of the digit equivalents of the preceding characters. The weights for the three sums are respectively: To obtain the first check digit, each character, as a 1-out-of-11 marking, sets a stage of an 11-stage shift register which is then shifted down until the set state is shifted out. An 11- stage end-around shift register is shifted concurrently an equal number of steps to give the check digit at the end of the character series. Generally, a check digit can be obtained by accumulating the products of characters (or rather the equivalent digits) times weights, the multiplication and addition both giving results mod-11. Checking and correcting.-A character recognition system reads a series of characters to produce a series of 4-bit digit equivalents at A1 (Fig. 4, right) an ambiguous (rejected) character being represented by 1100. Detecting gate 104 passes each digit to B4, replacing 1100 by 0000, and causes the weights of sums II and III corresponding to the position of the first code 1100 encountered to be stored at 118, 120 respectively, and the weights of sums II and III corresponding to the position of the second code 1100 encountered to be stored at 119, 121 respectively. The weights are generated in synchronism with digit arrival by generators 102, 103 for sums II, III respectively. The weighted sums, including the check digits, are recalculated by adder 107 (for I), multiplier 105 and adder 108 (for II) and multiplier 106 and adder 109 (for III). The results are combined as shown, complementary gates giving the 11-complement, and reciprocal gates giving a reciprocal (except that if the input is 0 so is the output). If there are one or two rejected characters, the true value(s) of the rejected character(s) appear(s) at B32 or B32, B34 respectively, provided the inputs B15, B16 to comparator 129 are equal. If these inputs are unequal, a further error exists, an uncorrectable situation being indicated. An uncorrectable situation is also indicated by 116 if more than two rejected characters are present. An error detector circuit (not shown) permits a single error (in the absence of rejected characters) to be corrected, comparing B8, B9, B10 (see Fig. 4) to zero to determine the number of errors. In the single error case, the size of the error is given by B8, the sum II weight corresponding to the position in error is given by the 11- complement of the product of B9 and the reciprocal of B8, while the corresponding sum III weight is given similarly except using B10 in place of B9. The size of the error is added into the appropriate digit in the series under control (to indicate the correct instant) of comparison of its weights and the weights of successive digits in the series indicated by generators driven in synchronism with digit arrival. The true values of rejected characters are also added into the series at the appropriate place in correctable cases. The invention is also applicable to a typewriter.