Patent SG-11201804841V-A (SG)
Title: Hardware integrity check
Inventor: FORLER EDOUARD
IPC: G06F21/57
Filed: 2016-12-13
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -, Organization 1111111101111011101010111110101111101110101101010111111101101111101111011111 International Bureau ... .... ..Yd jd (10) International Publication Number (43) .......,,,i International Publication Date WO 2017/102766 Al 22 June 2017(22.06.2017) WIPO I PCT (51) International Patent Classification: (74) Agent: KORENBERG, Alexander Tal; Kilburn & Strode GO6F 21/57 (2013.01) LLP, 20 Red Lion Street, London WC14 4PJ (GB). (21) International Application Number: (81) Designated States (unless otherwise indicated, for every PCT/EP2016/080859 kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, (22) International Filing Date: BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, 13 December 2016 (13.12.2016) DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, (25) Filing Language: English HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, (26) Publication Language: English MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, (30) Priority Data: NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, 1522244.1 16 December 2015 (16.12.2015) GB RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, (71) Applicant: NAGRAVISION SA [CH/CH]; 22-24 Route ZA, ZM, ZW. de Geneve, 1033 Cheseaux-sur-Lausanne (CH). (84) Designated States (unless otherwise indicated, for every (72) Inventors: FORLER, Edouard; c/o Nagravision SA, 22- kind of regional protection available): ARIPO (BW, GH, 24 Route de Geneve, 1033 Cheseaux-sur-Lausanne (CH). GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, BORGEAUD, Jonathan; c/o Nagravision SA, 22-24 TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, Route de Geneve, 1033 Cheseaux-sur-Lausanne (CH). TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, SELTZER, Steven; c/o Nagravision SA, 22-24 Route de DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, — Geneve, 1033 Cheseaux-sur-Lausanne (CH). LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, [Continued on next page] (54) Title: HARDWARE INTEGRITY CHECK (57) : A data processing device is disclosed, which comprises a plurality of data processing hardware components, such as one or more of a microprocessor, a central processing unit, a system on chip hardware component, a conditional ac- = = = 202 cess hardware component, a descrambler hardware component, a graphics hard- = ...-1 ware component, a video hardware component and a field programmable gate ar- ray hardware component. A first hardware component of the plurality of data pro _ = Send challenge to cessing hardware components is configured to send a challenge to at least one re- - = devices maining hardware component of the plurality of data processing hardware com- ponents. Each remaining hardware component is configured to receive a respective challenge and to process the challenge to produce one or more respective re- sponses. The device is configured to use one or more responses to verify device in- tegrity. 204 V = = = . Receive response --- 1 _ from devices V Use response to 206 verify system 1-1 integrity N ei Fig. 2 © ,-1 IN ,-1 © ei O WO 2017/102766 Al MIDEDIM000101011101010M0101101010111IONO1110VOIMIE SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, Published: GW, KM, ML, MR, NE, SN, TD, TG). — with international search report (Art. 21(3))