Patent GB-1410816-A (GB)
Title: Digital devices
IPC: H03G3/00
Filed: 1972-12-21
Abstract: 1410816 Attenuation devices WESTERN ELECTRIC CO Inc 21 Dec 1972 [22 Dec 1971] 59019/72 Heading G4A Attenuation is performed directly on a non- linear segmented code signal L 1  V 1  wherein the code consists of a first group of m characteristic digits e 1  ... e m  defining the segment L 1  and a second group of n mantissa digits e m+1  ... em+n defining the step V 1  in the segment by (1) applying the m digits to a counter 12 (Fig. 5) delay network and multiply 34 to generate a first signal z<SP>-L1</SP>(1+2<SP>n+1</SP>((2<SP>K</SP>-A(2)) where z is an operator representing multiplication by 2 and a one clock interval delay, K is the number of clock intervals delay in the multiplier process and A(z) represents the attenuation factor, (2) supplying the m digits to a shift register 17 and multiplier 38 to derive a second signal A(2)(2<SP>v</SP> 1 (2)+2<SP>n+1</SP>+1) and (3) adding the first and second signals derived at steps (1) and (2) to derive a signal S(z) which controls the pulses of the counter and stepping of the shift register to stop the operation when digits L 2  V 2  representing the attenuated signal are stored therein. In the embodiment of Fig. 5 in which m = 3 and n = 4 counter 12 containing the value L 1  is pulsed, starting at time t -7 , from a clock 26 so that, at a time represented by -L 1 , AND gate 31 is enabled to deliver a signal hence representing z<SP>-L1</SP> to (1) a delay 51 (of K clock intervals) and a delay 52 (of K + n + 1 intervals) to derive at the output of an OR gate 53 a signal representing z<SP>-L1</SP>l + 2<SP>n+1</SP>)z<SP>K</SP> and (2) OR gate 56 and via a delay 54 (of n + 1 clock intervals) to the same gate 56 to derive a signal representing z<SP>-L1</SP>(1+2<SP>n+1</SP>). The latter signal is fed via a multiplier 34 multiplying by A(z) to a full subtractor 36 which receives at its other input the output of OR gate 53 so that the first signal is derived at the output of the subtractor. Shift register 17 has a capacity of eight bits and receives on leads 18-22 the mantissa digits e 4 -e 7 . Additionally "1" bits are fed on leads 23, 24 so that the contents of the registers are representative of z[V 1 (z) + 2<SP>n+1</SP>+1]. Starting at time t 0  the shift register is stepped by clock pulses fed via gates 37 so that its contents are serially multiplied in multiplier 38 by A(z) and added to the output of subtracter 36 to derive the signal S(z) which is fed back to the shift register 17 and a gate 41. As the register continues to shift the first and second cells hold the information zS(z), z<SP>2</SP>S(z), gate 41 being enabled when S(z), zS(z) and z<SP>2</SP>S(z) are all zero to stop the shifting of the register. Counter 12 is then stepped down until time t K+n+1+#max  (i.e. t K+5+#max ) where # max is the maximum possible change in the segment between the values L 1  V 1  and L 2  V 2 . The counter and shift register then hold the required digits L 2 , V 2 . In the 6 decibel attenuator of Fig. 6A (not shown) in which A(z) = 1, the output resulting from incrementing counter (12) is applied to AND gate (62) enabled at time to only and to AND (63) the outputs from which are combined in an OR gate (64) to derive a signal representing z<SP>-L1</SP>(1+z<SP>+n1</SP>). This is combined in a full adder (39) with the output of the shift register (17) the resultant signal being fed back into the register and to an AND gate (41) which as in the embodiment of Fig. 5 controls the pulsing of the counter 12 and shift register 17.