Patent GB-989945-A (GB)
Title: Improvements in data processing systems
Inventor: WRIGHT ESMOND PHILIP GOODWIN
IPC: H04Q3/545
Filed: 1961-06-23
Abstract: 989,945. Automatic exchange systems. STANDARD TELEPHONES & CABLES Ltd. June 23, 1961, No. 31167/56. Heading H4K. Data handling equipment, particularly for use in a telephone exchange, includes a plurality of data-processing equipments, each with its own store, a number of groups of individual holding stores, a number of user circuits from which intelligence items are passed to stores in the data processing equipments, first transfer equipment for transferring items between stores in the data processing equipments and corresponding holding stores, and second transfer equipment for transferring items between stores in the data processing equipments such that a number of items can be received and processed in interleaved staggered relation, the items undergoing successive operations at intervals and being stored in the holding stores between operations, the transfer of items between the user circuits and the data processing equipments and the subsequent extraction of processed items from the data processing equipments being controlled by related repetitive cycles of pulses. General description, Fig. 6. The crossing vertical and horizontal lines represent the column and row wires of a matrix of ferromagnetic cells, the existence of a cell being indicated by a transverse line at a cross point. To each of the trunks 1<SP>1</SP> to N<SP>1</SP> there is allocated a pair of rows of cells 1R to NR, each such pair constituting an individual register for the corresponding trunk. The columns of cells are divided into sets, each associated with a respective common set of storage cells indicated by the blocks A to J, these blocks constituting common data processing equipment. The set of columns associated with block J has each of its cells threaded by both of the row wires of the relevant pair. PG is a generator producing pulses during periods of time t1 to t8, of which those in t1 and t5 are read pulses, those in t4 and t8 are half-write pulses, and the remainder control various gates. The access selector AS passes in turn the read/write pulses in t1 and t4 to the upper row of a register and then those in t5 and t8 to the lower row of that register, this being repeated for the other registers in turn. The trunks 11 to N<SP>1</SP> are cyclically scanned by means in block A to test for the open or closed loop condition, each trunk being associated with block A for the periods t1 to t8, during which time the state of the trunk is recorded in the cell in the upper row of its register which forms part of one of the columns associated with block A. On the next association the stored state is compared with the present state of the trunk. If these are the same, the block B determines by means of an adder the number of consecutive times that the states are the same and causes this number to be stored by the set of columns with which it is associated. If there is a change of state the adder is restored to zero. The time between successive associations of a trunk is 16 m.sec. and the adder counts up to any predetermined number of such periods. If the open condition persists for more than 32 m. secs. it is accepted as an impulse, which is noted by block D and stored in the associated set of columns. An open condition persisting for 160 m.secs. is recognized as a disconnect signal. Similarly, a closed condition persisting for less than 48 m.secs. is recognized as an inter-impulse period, and a longer one as an inter-digital pause. When an inter-digital pause is detected by B, the number of pulses counted by and stored by D is the digit, and this is transferred to E. During each association thereafter the digit is transferred from block to block in co-operation with the cells in the upper row until it reaches block J where it is transferred to the cells of the lower row and is then transferred from block to block until it reaches block E. Succeeding digits follow the same route, the second digit finishing in block F, and the third in block G. Block C counts the digits received and calls in a translator, if required, when three digits have been received, these digits (stored in blocks E to G) being then transferred to the translator. Detailed description.-The pulse generator PG and the access selector may be of well known kinds and are not shown in detail. A bar shown across a timing control in the drawings indicates a delay in operation of the control until the end of the time interval concerned. The scanning device 11C (Fig. 1), a counter having N stages, is stepped after each pulse t8 so that each stage is used for one complete cycle of timing pulses and generates an output 11C1, 11C2 ... accordingly. Each output in turn causes the common equipment, as represented by trigger 11F, to be associated with each user circuit in turn via individual AND gates 1G9 and a common OR gate 1G10. 11X indicates the condition of the calling loop of user (line) No. 1 and may be constituted by a signal or absence of signal from the corresponding line relay. Since each individual register is associated with the common data processing equipment in the same manner, only the associations of one register (No. 1) with the common equipment is described. In time t1 of the first association provision is made to transfer from the individual register all data stored in the first row. If any of the cores of this row is in the " 1 " condition, the trigger associaated with the column will be set to " 1." Thus, if the core threaded by L12 is in the " 1 " condition, it will operate the reading amplifier RA12 and trigger 12F via gates 1G4 and 1G6, this happening while 11F is not set, having been restored to 11f0 after t8 of the preceding cycle. In t1 the condition of the incoming calling circuit loop 11X is examined by 11F; if the loop is open, 11X is zero and 11F is not set in t1, but in t4. 11f0 opens gate 1 G and a half-write pulse is applied via 1G2 and 12W to L12 to write a " 1 " into the first register (upper row). Thus an open-circuited loop results in 11F being at " 0 " and is recorded by a " 1 " being stored in the associated upper row core of the register in column L12. Subsequent associations, while the loop is open, occur with 12F set to " 1 " and 11F set to " 0. " When, on some later association (the (n+1) association) the loop is found closed the signal on 11X sets 11F to " 1 " and with 12F also at " 1 " Ihe trigger 14F remains set to " 0." Also the absence of 11f0 from 1G1 prevents the writing during t4 of a " 1 " in column L12 for this line and the closed condition of the calling line is stored as a " 0 " in the upper register row. In the (n+2) and (n+3) associations 11F is set to " 1 " in t1 and restored to " 0 " after t4 so that again "0" is stored in the upper register. However, when 11F is set to " 1," 12F remains at " 0 " and the resulting condition 14f causes counter 2C to step to 1 and then to 2. 2C is restored to its rest position R after t4, and after t8, but its last condition is stored in the register in each case and is subsequently read out in t1, or t5, of the next cycle. Conditions continue as described until dialling commences and 2C may be used to cause release of the register if dialling does not commence. On the first association after dialling commences (xth association) 11F remains at " 0 " and 12F at " 0 " so 14F remains in condition " 0 " so that neither 2G21 or 2G1 can open; the counter C2 is not stepped and the condition of C2 is not stored. 12W writes a " 1 " at t4 in the upper register row of L12 (no loop). On the (x + 1) association 11F is " 0 " but 12F is " 1 " so 14F goes to " 1 " (via 1G19) and steps C2 to position 1. The nominal length of a dial break is 67 ms. which is slightly more than four cycles of 16 ms. each; during the (x+2) association 2C steps to 2 and during the (x+3) association to 3. When the impulse ceases (between the (x+3) and (x+5) associations) 11F again goes to " 1 " and 14F remains at " 0 " so that 25F is set to "1" via 2G22. This applies a pulse via 4G21 to the counter 4C which thus records the receipt of an impulse. Impulse counting continues, the settings of 4C being successively stored in the upper cores of the columns corresponding to the positions of 4C attained during each t4 and read out again in the next cycle during t1. During the inter-impulse pause of 33 ms., at the (x+5) and (x+6) associations counter 2C will be stepped but on the (x+7) association the loop will again be found open for the second impulse and 2C will remain in position R. During the remainder of the reception of the first digit 4C will count the impulses received. During the seven associations after the first digit ends the loop remains closed (11F set to " 1 ") and the number of associations counted by 2C will reach at least six (2C6). A pulse is then applied to 3C (via 3G21 and 3G22) after t2 and 3C thus counts the number of digits received. Figure 5 shows five horizontal transfer equipments for progressing digits and a vertical transfer means, and provides five registers 51 to 55 each of which may comprise 10 column circuit triggers. For register 51 these are 511F to 510F, of which only 512F is shown, each associated with a corresponding position of 4C and a column of the matrix of Fig. 5. Assuming the first digit received to be 2, then with 2C in position 2C6 and 11F in condition " 1," trigger 512F is set in t2 via 51G1, provided 511-510 were all at " 0," thus storing the first digit 2. 4C is reset to R via RG22 and RG23. In t3 of the same cycle the digit 2 stored in 512F is transferred to 522F, if the 52 register is empty, via 52G1. If 52 is not empty the digit 2 is stored in column 512L at t4 and will be re-entered in 512F in t1 of the next association. When the digit is eventually transferred to register 52, trigger 512F will be reset in t3 via 51G2 since all the 52 ... f0 controls will by then be at zero. In t4 the digit 2 in 522F is written in a cell in column 522L, and in t1 of the