Patent GB-1400561-A (GB)
Title: Signal converter apparatus for two level binary signals
IPC: G06K7/016
Filed: 1972-06-09
Abstract: 1400561 Signal conversion R O BARNES 9 June 1972 [1 July 1971 23 March 1972] 26984/72 Headings G4H and G4M A demodulator (Figs. 3, 3A) converts a series binary input signal of two-level non-synchronous binary input bits having a non-uniform bit repetition frequency (e.g. biphase mark, space or level signals 14, 16, 18, Fig. 2) into a series binary output signal in a different code (e.g. a non-return-to-zero signal 70, 72 or 74) by a process which includes the derivation from each input bit of a timing reference signal which is compared with the width of the succeeding input bit to determine whether it is a binary 1 or 0, the amplitude of the signal being automatically corrected for each bit to compensate for changes in the input bit width.  Signals of varying bit width may arise as the outputs of binary information readers (Fig. 1, not shown) used in a supermarket checkout system, the readers being used to read data from coded strips on goods or credit cards, changes in the speed of relative movement between reader and record giving rise to different bit rates.  In the embodiment of Fig. 3, a biphase input A is converted to pulses C and D representing positive- and negative-going transitions (see Fig. 4), which are then combined into a pulse train E. The first two E pulses (corresponding to a preamble bit, Fig. 2) are gated through 118 to an OR-gate 130 to form the first two of a sequence of pulses I: they are inverted and applied to a gate 140 to block pulses from an oscillator 142, so that a time reference counter 80 stops counting. The I pulses also go via 144 to bit and word-end counters 82, 84 to cause the transfer thereto of the complement of the count in 80 (there is, however, no output from 82 and 84 since their final stage flip-flops are maintained zero). Pulses I also go to a circuit 132 to produce delayed pulses I<SP>1</SP> which reset counter 80 to zero and generate further delayed pulses I<SP>11</SP> which reset flip-flops 88, 96 in a discriminator circuit 86. Pulses I<SP>11</SP> also go via 146 to cause flip-flops 122, 126 in an input memory circuit 124 to terminate a "counter reset" signal J and allow counters 80-84 to begin counting. The abovementioned signals and apparatus also combine to produce "in process" and "begin" signals K, L.  Between the first two I<SP>1</SP> pulses counter 80 counts pulses at a frequency ¥f 0  to produce a signal whose value is shown symbolically as Q 0 <SP>1</SP> which reaches a maximum 214 corresponding to the time width of the preamble bit. The complement of 214 is transferred to counters 82, 84 by the second I pulse for comparison with the width of the next bit of signal A: 82 and 84 output signals M 0 <SP>1</SP>, N 0 <SP>1</SP> which start firstly at zero, and subsequently at the level of the transferred count corresponding to the width of the preceding bit (so as to compensate for a varying bit rate if this should occur).  Signal K enables gate 120 to pass post-preamble E pulses as G pulses (data transition) to gate 148 which is enabled by a signal R from a circuit 86 to give a bit sync signal H corresponding to the transitions 232 at the beginning and end of each bit. Signal H provides further signals I, I<SP>1</SP>, I<SP>11</SP>. When output value M 0 <SP>1</SP> (218) exceeds output value Q 0 <SP>1</SP> (214) a bit counter output signal M<SP>11</SP> appears at the output of 82 and causes flipflops 88, 98 to produce signal R, this signal being terminated by the successive reset pulses I<SP>11</SP> which reset 88 to close gate 148 so that signal G is blocked until the next M<SP>11</SP> output-thus data transition pulses 228<SP>1</SP> are blocked and counter 80 counts during the entire time period between the beginning and end of each bit. Signal R is inverted to give a signal T which enables a gate 94 between R-pulses: thus only data transition pulses U (228<SP>1</SP>) pass through 94, these then triggering a flip-flop 96 whose output provides return-to-zero signals S or (via another flip-flop 98) NRZ signals V. Finally, a long termination pulse causes end counter 84 to produce an end pulse Y which causes the production of signal J and the termination of signal K. A similar demodulator circuit is described for dealing with pulse width modulated signals having varying bit widths (Figs. 5-6, not shown).