Patent GB-646050-A (GB)
Title: Improvements in or relating to electric pulse code modulation systems of communication
Inventor: EARP CHARLES WILLIAM
IPC: H03M1/00
Filed: 1948-02-20
Abstract: 646,050. Multiplex pulse code signalling; valve circuits. STANDARD TELEPHONES & CABLES, Ltd. Feb. 20, 1948, No. 5013. [Classes 40 (v) and 40 (vi)] A pulse code modulator for the simple addition binary code comprises a periodically operating counter which builds up a step wave, means for stopping the counter when the difference of potential of the step wave and the signal wave reaches a specified value, and means for deriving from the counter a distribution of potentials characteristic of the signal amplitude. The invention is described as applied to a multichannel communication system using a single pulse code modulator for all the channels. A five-unit code is used, each unit comprising a pulse or the absence of a pulse, the channel code groups being interlaced in time. In the embodiment described, a master pulse generator 1, Fig. 1, feeds a scale-of-two pulse counter 3 through a trigger gate circuit 2. The counter builds up a step wave, from the incoming pulses, which is combined with the signal voltage from one channel and applied to a comparator 4. When the difference between the signal and the step wave voltage reaches the specified value, the comparator produces a pulse which cuts off the gate circuit 2 and thus stops the counter 3, which remains with some stages normal and others operated. At the end of a complete counting period, a pulse from conductor 6 restores all the stages of the counter to normal. Each of the operated stages which returns to normal in so doing generates a code pulse which is fed over a corresponding conductor to a code gate circuit 7 which is also supplied with a gating pulse over conductor 8. The code pulses are fed in any desired order in time to the output terminal 9. The pulse in conductor 6 after a delay in network 10 opens the trigger gate 2 again to start a new counting operation. The pulse generator 1 also feeds a frequency divider 11 producing channel frequency pulses which are fed to a pulse distributer delay network 12. The signal from the first channel is applied from conductor 15 to a signal gate circuit 14 which is opened by a pulse from a tapping on network 12 shaped in circuit 13, and the resulting signal sample is fed to comparator 4 over the common conductor 16. The other channels have their own signal gate circuits controlled by pulses from successive tappings on network 12, and a synchronizing pulse is derived through shaping circuit 21 from the last tapping. The pulses for controlling the trigger gate, counter and code gate are derived from the common conductor 18 connected to appropriate tappings on network 12 through rectifiers 17. They are further timed and shaped by circuits 10, 19, 20. Counter and comparator circuits, Fig. 3.- The counter circuit comprises five identical stages 22... 26, each containing a multivibrator double triode 27 which is stable in both conditions. The left-hand grid is connected to the grid of a constant current pentode 38 and fed with positive pulses to be counted through condenser 39 from terminal 40. The pulses are also fed through condenser 41 to the right-hand grid. The unoperated condition of each stage is that in which the left-hand triode is cut-off and each two pulses on terminal 40 produce one pulse on output terminal 42. The pentode 38 becomes conducting when the multivibrator is in the operated condition, and the pentode currents are adjusted by screen potentiometer 51 to have values proportional to the numbers 1, 2, 4, 8 and 16 respectively. The current through the common anode resistance 58 therefore rises in equal unit steps as the pulses are counted. The resistance 58 is also the anode resistance of pentode 56 in the comparator circuit, the signal to be coded being applied to its control grid from transformer 61. When the anode voltage of valve 56 falls below that of a comparison source 64, rectifier 65 conducts to apply a negative pulse to the grid of valve 67. The pulse output from 67 is differentiated in circuit 69, 70, 71 and the remaining negative difference pulse is applied through terminal 72 to cut off the trigger gate 2, Fig. 1, and thus stop the counter. The code pulses are produced simultaneously at the appropriate output terminals 43 of stages 22 ... 26 as follows. The restoring pulse from delay network 19, Fig. 1, is fed to terminal 54 connected to terminals 49 on the counter stages and thence to the righthand grid of valve 27 in each stage. Those stages which are in the operated condition at the end of the counting cycle are thereby restored to the unoperated condition and in so doing generate a pulse which is fed to terminal 43 after differentiation and clipping in circuit 44, 45, 46 and at the time when the code gate is opened. Trigger gate circuit, Fig. 4.-The pulses from the master pulse generator are fed to terminal 80 connected to the control grid of gate valve 76. The two-position multivibrator 74 normally has its left-hand triode cut off and its anode potential is suitable to render 76 capable of conduction being connected to the suppressor grid of that valve. To cut off the gate the multivibrator is reversed by a positive pulse at terminal 75 from terminal 72 of the comparator, Fig. 3. The gate is opened again by a pulse applied to terminal 89. This pulse is differentiated in circuit 91, 93, the resulting negative pulse is suppressed by rectifier 92, and the positive pulse fed to the grid of the right-hand triode of multivibrator 74 to reverse it to the normal condition. Code gate circuit, Fig. 5.-The code gate circuit comprises five valves such as 94, the five inputs from terminals 43, Fig. 3, being applied to their control grids 95. The valves are normally cut off by cathode bias which is overcome by a gating pulse applied through terminal 105 and condensers 106 to their cathodes. This allows the code pulses to pass to tappings on the delay network 96 for delivery to the output terminal 100 at any desired time intervals and in any desired order. Specifications 535,860, 644,935, 646,051 and 646,936, [Group XVII], are referred to.