Patent GB-983188-A (GB)
Title: Improvements in means for displaying symbols
Inventor: STEVENS MICHAEL CHARLES
IPC: G09G1/12
Filed: 1962-06-15
Abstract: 983,188. Cathode-ray tube circuits; transistor amplifiers and non-sinusoidal waveform generators. A. C. COSSOR Ltd. June 13, 1963 [June 15, 1962], No. 23186/62. Headings H3T and H4T. In an arrangement for tracing Alpha- Numeric characters on the screen of a cathoderay tube a sine and a cosine waveform of the same frequency are generated and applied through separate gate circuits to the x-deflection means of the tube and through other separate gate circuits to the y-deflection means of the tube, the gating pulses being locked in phase to the sine and cosine waveforms and applied selectively to open the gate circuits so as to cause the electron beam to trace the desired symbol on the screen of the tube. A + sine and - sine wave are generated (Fig. 6) when a symbol is to be written, a negativegoing trigger pulse being applied at terminal TP6 to trigger the main bi-stable into the " set " state and when the field of L collapses the tuned circuit oscillates for two cycles after which a trigger pulse (the trailing edge of the pulse at terminal P8 in Fig. 12, referred to later) is applied to terminal T1 to reset the main bi-stable. The + sine waveform is fed in at TP7 (Fig. 7) through a capacitive input circuit and a - cosine output is obtained through resistor R23. This output contains a small unwanted sine component which is cancelled by injecting a - sine wave from terminal TP8 (Fig. 6). The corrected output, from the waveforms through C6 and R22, is applied to a summing amplifier including transistors VT10 and VT11 to which is added a step waveform derived from Fig. 6 and applied at T2 so as to produce at terminal TP9 a + cosine output (Fig. 4, not shown). An inverter including transistors VT12 and VT13 supplies a - cosine output at a terminal TP10. The gating pulses are generated by passing a + sine waveform from TP7 in Fig. 6 through a buffer amplifier VT14 to a high gain amplifier VT15 and VT16 (Fig. 8) in which both bottoming and cut-off occurs and the output at terminal b is a + sine square-wave in phase with the + sine input. Transistor VT17 acts as in inverter and provides an output of a - sine squarewave at a terminal a. The - cosine square-wave and + cosine square-wave are derived from a circuit identical with that of Fig. 8 using a - cosine wave input. A bi-stable circuit comprising transistors VT18 and VT19 (Fig. 8) generates at terminals e and f half frequency square-waves as shown at (c) and (d) in Fig. 9, the corresponding + sine and - sine squarewaves being shown at (a) and (b) respectively. The bi-stable is triggered into the " set " state by the leading edge of the step wave at terminal T2 in Fig. 6. Fig. 10 shows the circuit of a logical element of a diode matrix for producing a gating pulse in the third quarter cycle position. On the left is shown the waveforms applied to the three inputs and on the right is shown the waveform of the output pulse 31 which is in the third quarter cycle since that is the only occasion during the two cycles of oscillation when the base of VT27 is not held positive with respect to its emitter. By providing suitable inputs to the three diodes of Fig. 10 an output pulse may be obtained in any one of the eight quarter cycle intervals and a complete diode matrix is shown in Fig. 12. On the right are shown the waveforms applied to the various inputs and above are shown the output waveforms obtained at terminals P1, P2, P3 &c., the eight subdivisions also being marked on these waveforms. Figs. 17 and 18 show how the symbol 2 is formed. Fig. 17(a) shows the required x-deflection voltage, this being a - cosine wave and no summing amplifier is required, the waveform being applied directly to the x-deflection means of the cathode-ray tube. Fig. 17(c) shows the required y-deflection waveform and in Fig. 18 is shown the appropriate summing amplifier, the waveforms applied being indicated on the left i.e. + sine wave to terminal 52 and a - sine wave to terminal 53. The parts of the waveforms that are not shorted out, and are therefore effective, are shown in full lines and the remainder of the waveforms in broken lines. The terminals P5, P6, P7 and P8 are connected respectively to corresponding referenced terminals in Fig. 12 and deliver gating pulses in the 5th, 6th, 7th and 8th quarter-cycle positions respectively. During the first four quarter cycles the waveforms at 52 and 53 are shorted out so that a fixed voltage is applied to the y-deflection means. During this time the - cosine wave of Fig. 17(a) executes one cycle and the scanning spot travels from point A in Fig. 17(b) to point B and back to point A. During the fifth quarter cycle the - sine wave applied at 53 is delivered to terminal 45, thus the spot is caused to travel clockwise through a quarter circle from A to C in Fig. 17(b). During the sixth, seventh, eighth quarter-cycles the + sine wave applied at 52 is passed to the terminal 45, thus the spot travels anticlockwise through three quarters at a circle from point C to point D in Fig. 17(b). The Specification includes figures of the deflection waveforms and summing amplifiers for the symbols 3, 4, 5 and 6 and an alternative circuit to the shorting switch for gating the inputs from the diode matrix of Fig. 12 to the symbol summing amplifier making use of diode AND gates (Fig. 35, not shown). All the symbols produced have the same bright-up interval (two cycles of the sine wave) and all curves consist of an integral number of quarter cycles.