Patent GB-1143356-A (GB)
Title: Improvements in information processing systems
IPC: G06J1/00
Filed: 1966-10-21
Abstract: 1,143,356. Hybrid computers. ADAGE Inc. 21 Oct., 1966 [22 Oct., 1965], No. 47416/66 Heading G4A. A hybrid computer comprises one or more sets of analogue components in a hybrid computing array 21, Fig. 1, each set being connectable into a selected one of a number of networks between a set of inputs and an output in accordance with digital signals stored in a control register CR, and also includes a digital computer having a plurality of source registers, one of which is an output register OR of array 21, a plurality of destination registers, one or more of which are input registers VR, CR of array 21, and means 3, 13 for connecting a selected source register to a selected destination register in response to a programmed command. The digital computer also includes means 9, 11 for performing logical operations, detailed below, on digital data being transferred from a source register to a destination register. The hybrid array 21, Fig. 19 comprises two sets of analogue computing elements ACE1, ACE2, each of which is described and claimed in Specification 1,143,355. Briefly, each ACE unit sums the analogue signals on those of its inputs which are selected by bits 8-13 or 16-21 of the instruction stored in register D5R, and multiplies or divides this sum, in accordance with whether bit 14 or 22 from D5R is 0 or 1, by a number represented by bits 15-29 (including a sign bit) from value register D9R or D8R. One of the analogue inputs to the ACE units is from a digital-to-analogue converter DAC supplied with bits 0-14 from D9R or D8R. Two of the other inputs to the ACE units are analogue values x i , yj selected from x 1 -x 7  and y 1 -y 7  by register D6R. A further unit CMP forms the algebraic sum of those of its inputs which are selected by D5R and a digital input from value register D7R. The analogue output of CMP is converted to digital form at ADC and stored in S5R which acts as source register S5. SAH is controlled by D6R to either sample or hold the analogue output of CMP and supply it to any one of loads L0-L5. Examples of functions which may be computed by array 21 are given in the Specification. Instruction register IR is loaded from a memory data register MD at a preset time in a machine cycle. Each instruction comprises 15 bits, the first two signifying a normal or special instruction, and the duration of the machine cycle being selected in dependence on which of the four possible types of instruction is indicated by these bits. Bits 2-5 and 6-8 respectively designate the source and destination involved in performing the instruction. Bits 9, 10 and 11, 12 specify the rotation and transfer functions, and bits 13, 14 specify "increment contents of selected member by 1" and an "indirect address control" respectively. In a special instruction bits 6-10 are interpreted as a special operation code used for all conditional instructions and all instructions which charge a location counter in the memory system DME other than by normal sequential addressing. Source, registers.-These comprise the memory data register MD (SO), the source register of an arithmetic unit AR (S1) buffer register BR(S2), output register OR (S5) and sources S4, S8. Buffer register BR is coupled to external devices XD such as input/output units, via gates 15 controlled by system control unit SCU and interface control register I.C. (source S3), the latter being loaded from a keyboard or by selection of destination D3. Source S4 comprises a group of sense lines 17 which may be connected through gates 15 to report the status of devices XD or to report the status of elements of the hybrid array 21, e.g. the sign and overflow conditions of the computing networks ACE, CMP and ADC, Fig. 19. Source S8 is selected in response to the programme interrupt condition described below. Destination registers.-D2, D3 and D5-D9 are the registers indicated in Fig. 1. DO is the memory data register MD, and this register also acts as the immediate destination for destination code D4, however, in this case D4 forms the command "load IR from MD" and the ultimate destination is thus IR. The destination register of arithmetic unit AR is selected by all of destination codes D1, D13-D15. With D13, a single precision range number (i.e. 14 bits + sign bit) is added to the contents of AR. With D14 an extended range number (i.e. 29 bits + sign bit) is added to the contents of AR. With D15, the resultant transfer to AR is the exclusive OR function of the contents of AR and the contents of the selected source. Memory system.-There are three basic operations and five types of memory cycle. The read-restore operation is one in which a memory address register reads data from the core memory into the memory data register MD, the data being subsequently restored to the core memory. In the read-index-store operation, the contents of the memory address register are indexed by 1, transferred to MD and later stored in the core memory. In the clear-write operation, data from a selected source is transferred, via MD, to an address in the core memory specified by the address register. The "memory data load" cycle is one in which MD is loaded from a selected source and no transfer with the core memory takes place. In the "jump" cycle, no transfer with the core memory takes place and bits 15-29 (the address portion) of MD are loaded into a memory location counter LC. In the "jump to sub-routine" cycle the address bits from MD are loaded into the memory address register, the contents of the core memory at this address are transferred to MD (bits 0-14) and the contents of the location counter LC are transferred to bits 15-29 of MD. The contents of MD are then transferred to the core memory at the address specified in the memory address register, and this address, incremented by 1 is transferred to LC. In a "random addressing" cycle the address bits of MD are transferred to MAR, and in a "sequential addressing" cycle, the contents of LC are transferred to MAR and LC is incremented by 1. Rotation control.-When the rotation control bits are not both zero, gates in unit 9 are enabled to transfer each bit of the 30 bit word supplied thereto by 1, 6 or 15 bits to the left, i.e. so that bit 0 becomes bit 29, 24 or 15. Transfer logic.-If the transfer bits are not both zero, one of three logical operations is performed on each of the 30 bits in a word by 30 sets of gates enabled by the transfer bits. The functions are (1) copy '1" bits into destination register, ignoring 0's. (2) copy 0 bits into destination register, ignoring 1's, and (3) complementing. The data channel 3-11 is claimed in Specification 1,143,360. Programme interrupt system.-When an external device XD requires servicing, it sets a corresponding request storage flip-flop at a predetermined point in a machine cycle when SCU samples the status of the request storage flip-flops. When one or more of the request storage flip-flops has been set, a "fetch priority instruction" signal is generated and this forces S8 to be selected whereupon the external instruction source XIS corresponding to the set request storage flip-flop with highest priority is gated to the memory data register. When servicing is initiated, a corresponding service flip-flop is set and the request flip-flop is reset. The generation of an unassigned special instruction code may be used to produce a service request from XDO of highest priority, and the instruction gated out from XISO may cause the machine to execute an error sub-routine. The programme interrupt and priority systems are the subject of Specifications 1,143,358, and 1,143,359.