Patent GB-786469-A (GB)
Title: Improvements in or relating to intelligence storage equipment
Inventor: WEIR DONALD ADAMS
IPC: G11C29/00
Filed: 1955-12-30
Abstract: 786,469. Electric digital-data-storage apparatus. STANDARD TELEPHONES & CABLES, Ltd. Dec. 30, 1955, No. 37419/55. Class 106 (1). [Also in Group XXXIX] The storage cores of a magnetic memory matrix are scanned in turn and subjected to routine testing without disturbing the normal reading and recording operations on any one or more of the cores or destroying recorded information. It is suggested that routine testing may also be applied to a ferro-electric storage matrix. General arrangement. A clock pulse generator CPG, Fig. 1A, is connected to a pulse shaper PS and delay lines D1, D2 so that each clock pulse produces a set t of three staggered pulses t1, t2, t3. The last pulse t3 drives a three-stage distributer CCA, Fig. 1B, which develops outputs CCA1, CCA2, CCA3 in turn. The matrix scanning and the reading, recording and test operations are carried out as follows :- (1) Step by step scanning of the cores for test purposes is controlled by cycles of three sets of t pulses; (2) The normal reading and recording operations on any one or more cores take place during the first set of t pulses; (3) During the second set of t pulses the magnetic state of a core selected by scanning is read for test purposes. If no output is obtained the state of the core is reversed; (4) The core under test is read for a second time during the third set of t pulses and restored to its initial magnetic state. The two read-out pulses obtained respectively during the second and third sets of t pulses are compared. For a satisfactory test one read-out pulse only should be effective, the other being substantially zero. If this condition is not met scanning is stopped and an alarm given, Matrix scanning. Column and row distributers EC, MC, Fig. 1C, comprising m and n stages respectively control the step by step scanning of an mxn magnetic memory matrix, the distributer EC being advanced each time CCA3 and t3 are applied simultaneously to a gate G1 having a normally applied input MA. The number of simultaneous inputs necessary to open the gate is denoted by the figure in the circle. Each time EC completes a full operating cycle the distributer MC is advanced by a signal ECm applied to gate G2. The outputs from EC and MC control column and row multi-stable registers Y, X, Fig. 1D, which in contradistinction to the distributers may have more than one unit operated at a time. Automatic cancellation of operated units take place in the registers when further units are operated. Normal reading and recording operation. Each register unit is controlled by two gates such as G3, G15 and G5, G16. Normal reading operations are carried out by selective energization of leads SY1-SYm, SX1+SXn, and the associated gates G3, G5 open when distributer CCA steps to stage CCA1. As soon as pulse t1 in the first t pulse set is received, gates G7, G9, Fig. 2, selected by the operated register units pass a positive current pulse to row and column windings of the matrix memory over mixing gates G11, G12 and drive the chosen core or cores located at the intersection of energized circuits to the magnetic state representing a recorded " 0 ". If the interrogated core is in the magnetic state representing a recorded " 1," an induced read-out pulse arises at terminal 01 which is applied over an amplifier AMP to an output terminal M0. The induced pulse is also applied to a delay circuit D3 which brings it into the time position of pulse t2 so that it acts with inputs t2 and CCA1 to open a gate RCG. This gate includes a controlling input SC which is only energized for normal reading or recording operations. As a result an input circuit IC generates a negative t2 pulse which is applied to the interrogated core of the matrix over gates G8, G10, G11, G12 and restores it to its original state 1, the gates G8, G10 being individually controlled by the operated register units. If the interrogated core is initially in state 0, no effective output pulse is produced. Restoration is not necessary in this case and gate RCG remains closed and IC inoperative. Alteration of recorded state. Gate RCG has additional inputs W1, W0 If W1 is energized in the time position t2 of CCA1, RCG opens and a negative pulse from IC records state 1 in the interrogated core. If W0 is energized, RCG is inhibited and the interrogated core remains in the 0 state following the read-out operation. Test operation. The normal reading control acts in the registers over gates G3, G5 only during the period CCA1, the remaining periods CCA2, CCA3 being allotted to testing. In the latter periods, selected gates G15, G16, Fig. 1D, are opened and a unit in each register operated according to the stage reached in matrix scanning by the distributers EC, MC. The distributer CCA is stepped to CCA2 by the pulse t3 in the first t pulse set. The next t1 pulse (second t pulse set) opens a column and a row gate G7, G9 and coincident positive pulses are applied to the selected matrix core. Tested core initially in state 1. A core in this condition is driven to state 0 by the positive pulses and a read-out pulse is obtained over the amplifier AMP. From the amplifier the pulse is applied over the delay circuit D3 to an inverter INV1, and gates G17 and RMG are inhibited in the time position of pulse t2 so that IC is unable to restore the read-out information in the core under test. The readout pulse is also applied to a delay circuit D4 which holds the pulse back for the time period of a t pulse set so that it arrives at a comparative circuit G18 in the time position t1 of CCA3. Occurrence of the t1 pulse in CCA3 causes a further read-out operation on the selected core to take place over gates G7, G9, this time without effect as the core is in state 0. Restoration of tested core to state 1. The condition of absence of read-out signal when the selected core is read for the second time in the time position t1 of CCA3 is reversed by INV1 and appears as a pulse at gate G17 in time position t2 after delay by D3. Both G17 and RMG open and operate IC which produces a negative t2 pulse and changes the state of the core under test over gates G8, G10 to its original state 1 condition in the manner previously described. Tested core initially in state 0. In this case no read-out pulse is produced at the stage when gates G7, G9 are opened by the second t1 pulse. The absence of read-out signal is reversed by inverter INV1 and causes IC to produce a negative t2 pulse which changes the core to state 1. The absent output is also applied over a delay line D4 and an inverter INV2 and appears as a pulse in the next t1 position at a gate G19. Restoration of tested core to state 0. The second reading operation in the time position t1 of CCA3 restores the core to its initial zero state and produces an effective output pulse. Detection of faulty core circuits. A core is read twice by a test operation and if operating satisfactorily should produce one read-out pulse only, either at the first reading when initially in state 1 or at the second reading if in state 0. The first read-out signal is delayed by D4 and arrives in time position t1 of CCA3 at gates G18, G19 at the same time as a directly applied second read-out pulse. If the first and second test read-out operations both produce an effective output then G18 is opened. If, on the other hand, both outputs are zero, gate G19 is opened by simultaneous effective pulses produced by inverters INV2, INV3 in association with delay circuit D4. Either gate when opened energizes a part MB of a bi-stable device MA, MB. Part MA is then disabled and causes gates G1, G2, Fig. 1C, to close and terminate the scanning operation by disabling the distributers EC, MC. Relay AL also falls back and operates an alarm bell and lamp circuit. Specification 760,048 is referred to.