Patent GB-1370870-A (GB)
Title: Data storage device
IPC: G11C16/04
Filed: 1973-06-19
Abstract: 1370870 Digital data storage circuits NCR CORP 19 June 1973 [28 June 1972] 28938/73 Heading H3T [Also in Division G4] The invention relates to a digital data storage element of the type comprising a storage F.E.T. 16 arranged to store digital data in capacitance associated with its gate, a "write" field effect transistor having its source connected to the gate of the storage transistor and a "read out" transistor 14 connected in series with the drainsource path of the storage transistor. According to the invention the "read out" transistor has a non-volatile controllable threshold which is set in accordance with the data stored, if the power supply to the circuit fails. Thus if the data stored at the gate of the storage transistor discharges during the failure, the state before the failure may be recovered. In the circuit shown, writing is effected by operating a "select" switch 44 and connecting the drain of the "write" transistor 12 to one or other of the 0 and 1 voltage sources via switch 25 whereby the capacitance at the gate of transistor 16 is set to a charged or uncharged state. Read out is effected by connecting switch arm 42 to the voltage source 32 whereby transistor 14 becomes conducting. A read out amplifier 41 has its two inputs connected to - 18 volts supplies 29 and 30. Accordingly, if during read out, the charge at the gate of transistor 16 is zero the transistor does not conduct, the input voltages of the read out amplifier are equal and a zero voltage is provided on line 19. If however a "1" is stored at the gate of transistor 16, both transistors 16 and 14 are now conductive, the voltage at terminal 21 of the read out amplifier is earthed and the unbalance of the input produces an output on line 19. Refreshing of the data may be effected by closing switches 25, 34 and 42 whereby the sense amplifier restores the state of charge to its true 0 or 1 value. If failure of the supply 18 occurs it is detected by a circuit 20 which moves switch 42 to connect with the - 30 volt supply 35 (which may be a storage capacitor). If transistor 16 is storing a "1" it is conducting and accordingly the supply 35 will raise the threshold of the transistor 14 to a high value in a non-volatile manner. When the supply is restored the switch 42 is connected to a - 8 volt supply 37. As the "1" is stored as a high threshold value in transistor 14, the - 8 volt supply is insufficient to make transistor 14 conduct and accordingly if switches 25 and 44 are made the charge at the base of 16 is set to zero. This may be reset to "1" by repeating the failure and recovery cycles. A positive supply 34 may be selected to reset the threshold of transistor 14 to its normal low value.  Fig. 2 (not shown) illustrates four such circuits in a matrix arrangement. The "write" transistors in a row are enabled simultaneously by applying appropriate voltage to the gates and the signal to be read in is applied simultaneously to the drains of the write transistors in a column. A common read out amplifier is used for the elements of a column, the read out transistors being enabled row-wise.