Patent GB-1490333-A (GB)
Title: Testing pcm equipment
IPC: H03M1/00
Filed: 1974-11-15
Abstract: 1490333 Testing electrical apparatus POST OFFICE 15 Nov 1974 [15 Aug 1973] 38535/73 Heading G1U In testing the sampling and encoding element of a PCM transmission equipment, a test signal is injected into a selected channel input and coded values corresponding thereto from the channel output are stored in bi-stable memory stages under the control of digit and channel timing pulses derived from the PCM equipment itself. The test equipment forms a rack mounting piece of equipment which is substituted for normal input signalling unit of the selected channel and connected to the PCM transmission equipment via 9 connections viz. encoded signal output TT3'; master clock output MCP'; 'digit 8' pulse output DGP8'; sample channel x pulse SAP(x) - x being the channel under test; synch. unit input pulse MUP'; encodes inputs TT1', TT2'; and two power supply leads +12V and E Fig. 2. The test signal is derived either from an external 300-3,400 Hz oscillator and calibrated attenuator whose output is applies to jack socket JP2, or the internal 2,000Hz oscillator based on MN2 and TR1 may be used with an external attenuator between JP1 and JP2. This internal oscillator is driven by 'multi-frame' synch. pulses from the PCM equipment and thus is arranged such that the channel samples occur selectively at the test signal positive or negative maxima. Using the external source, no such synchronism occurs, but a gate GS15 detects the nodes and indicates the fact by a lamp LD8. Storage of PCM output signals. The encoder output pulses pass via terminal TT3' and Schmitt trigger ST to a gating arrangement GS17-19 which allows for coding either in "straight" or "folded" binary by means of a selector switch SW5. From the gate GS16, the serial code pulses are gated into bi-stable memories BS1-BS8 under the control of pulses from a shift register SR1 via gates GS1-GS8 which also receive master clock pulses from the PCM equipment via terminal MCP' and monostable MN1. The sample pulse corresponding to the channel under test arrives at terminal SAP(x) and along with the 'digit 8' pulse from the PCM equipment provides a pulse from bi-stable BS9 defining the channel x time period. These drive a shift register SR2 whose outputs thus shifts at every channel x pulse, i.e. once per frame. The shift register SR2 is reset from the PCM equipment so that the four shift pulses are synchronized with the 'multi-frame' period. By choosing the first or third frame in that period by means of SS2, master clock pulses are passed to the storage gates GS1-GS8 only in the selected frame. Thus stores BS1-BS8 receive in parallel form the eight digits representing the code in channel x in the selected frame. Lamps LD1-LD7 are used to indicate the polarity of the sample and its value. Various tests may be carried out using the apparatus. a) The overload limit may be detected by varying the calibrated alternator at the test signal input until maximum value codes are displayed. b) The coding law of the encoder may be detected by recording the sample code for various levels of input. c) In checking the transmission line fed from the PCM equipment, a specified level test signal is encoded and sent down the line, the received code being checked at the receive end. By using the present test equipment, the outgoing code can be displayed and checked. d) The encode "offset", i.e. the code transmitted for zero input signal can be determined. e) Some degree of noise monitoring is possible by observing the polarity indicating lamp LD1 under zero input level conditions. Random flickering thereof indicates a noise level substantially equal to the offset level. When the unsynchronized external generator is used, the modification of Fig. 8 (not shown) may be employed. This automatically determines the peak level of the test signal as the samples range over its full period.