Patent GB-777286-A (GB)
Title: Calculating means
IPC: G06F11/10
Filed: 1955-03-25
Abstract: 777,286. Digital electric calculating-apparatus. STANDARD TELEPHONES & CABLES, Ltd. March 25, 1955 [April 2, 1954], No. 8854/55. Class 106 (1). i=n A function F## b i  a i  (mod i=o  p) is calculated for a set of numerical symbols a i  (o#i#n) of radix z, where b i  is one of a group of integral coefficients such that b i ## b i+1  (mod. #), and # and # predetermined different integers (#>1 and ##z), by setting a pstable-state device from one contion to another under control of the n+1 symbols a i  in turn, so that Fi##(Fi-  1+ ai) (mod. p) where F i , Fi -  1  are successive conditions of the device. The apparatus described is used for detecting errors in transcription of n-digit decimal numbers, each number having a check or " proof " digit associated therewith, and the successive conditions of the device are #a 0 ,#(#a 0+ a 1 ) giving the function F (b i =#<SP>n+1-i</SP>). The integer # can be chosen to produce a group of p - 1 different coefficients b i  when, provided n+1 # # - 1, a single transposition between any pair of digits a i  can be detected. The apparatus shown, in which #=2 and #=11 comprises 11-stage counting chains CT1, CT2, e.g. similar to the circuit described in Specification 663,574, [Group XL (c)], bistable devices BS1-BS4, e.g. Eccles-Jordan trigger circuits, and gates such as G5 and G6, the white and black arrows indicating that a control signal opens and closes a gate respectively. The digits a i  are entered into CT2 by operating keys KO, K9 ... K1, and the conditions F i  are registered in CT1. When a digit key is shifted, the potential at terminal P3 as well as firing the corresponding counter stage, sets BS1-BS3 to the "1" condition, BS2 being reset when the key is released, thereby opening gates G1, G2 through normally open gate G6. Gate G2 allows CT2 to operate, like CT1, as a ring counter, and G1 allows pulses from source P2 to operate frequency divider BS4 whose output at P1 steps on both counters together until CT1 reach " 0 " when its output resets BS1 which closes gate G3 and opens G4 and G5; CT2 has then stepped from F i-1  to (F i-1 +ai) (mod. 11). CT2 is then stepped on by pulses at P1 while CT1 is stepped, at twice the frequency, by pulses from P2 applied through Gland G4; when CT1 reaches Fi=2 (F i-1  + A i ) (mod. 11), CT2 reaches " 0 " and its output closes gate G6 via G5. Gates G 1, G2 are then closed and the circuit is ready to receive the next digit. When a whole number (including the proof digit) has been entered, CT1 should register " 0 ". When a " shift " key is then operated and closes contacts S, S<SP>1</SP>, CT1 should produce an O.K. signal at the corresponding terminal, via G7 (opened by BS3) and S. If CT1 is not in the " 0 " condition, it will be driven to " 0 " by pulses at P2 applied via G8 and S<SP>1</SP>, and BS3 will be reset to " 0 " to indicate an error. The apparatus may be used to compute the proof digit, the operative stage of CT1, after a number has been entered, causing a corresponding lamp L to be lit. Where, as shown, only ten symbols are used for the proof digit, numbers requiring a proof digit of " 0 " must be avoided (" 0 " being used for " 10 "); a list of such numbers is given in the Specification. Electromechanical circuits may be used. Reference is made to verifying recorded numbers.