Patent GB-789429-A (GB)
Title: Improvements in electric circuits employing transistors
IPC: G11C19/28
Filed: 1956-04-18
Abstract: 789,429. Electric digital storage apparatus. WESTERN ELECTRIC CO., Inc. April 18, 1956 [April 20, 1955], No. 11791/56. Class 106 (1). [Also in Group XL (c)] A circuit for minimizing the effects of collector saturation (see Group XL (c)) is described as applied to a shift register, Fig. 1, in which information from a source 10 such as a magnetic drum is applied to stages 11 to which shift pulses from source 20 are also applied, the output being fed to a parallel information load circuit 15. Each stage 11 comprises a crosscoupled trigger pair 22, 23 feeding amplifiers 39, 40 and a diode gate 50 to provide output to the next stage and over leads 16, 17 to the load 15. Assuming transistor 22 to be conducting the collector potential is low so that isolating diode 38 conducts to lower the base potential of transistor 39 which also conducts. Due to flow of current in the emitter-collector path of transistor 39 the potential on lead 16 approaches that of the supply 41. Transistor 23 is cut-off so that the collector potential is relatively high and diode 38 is also cut-off and the emitter potential of amplifier transistor 40 rises until the associated diode 46 conducts to feed out a potential on line 17 near that of bias supply 42. The shift pulses 54 are applied to the anode of a diode biased slightly negative and are arranged to have a maximum value lying between the potentials of the sources 41, 42 so that only one diode 50 is conductive during any given shift pulse so that in this case a pulse would be fed over the line 1 to the next stage indicating that a 1 has been stored. Assuming a 1 has been stored in the previous stage then a pulse 55 is fed over isolating resistor 33 to the base of transistor 23 but since this transistor is already non-conducting the pulse is ineffective. If an 0 has been stored in the previous stage then a pulse 32 is fed to the base of transistor 22 thereby reducing the collector current and since the transistor is not saturated a pulse is fed to the base of transistor 23 with an amplitude greater than that fed to the transistor 22. The circuit 22, 23 reverses its state and as the collector potential of transistor 22 rises diode 38 is biased off with the base potential of transistor 39 tending towards the supply potential 42. The emitter potential rises and the lead 16 assumes a potential near that of supply 42 since diode 46 conducts. The transistor 39 is operated in the saturated condition in order to provide an adequate output to the load and when the transistor cuts off minority carriers remain in the base and drain off through resistor 43. A delay occurs in the progression of the information due to the turn-off times of transistors 39, 40 and the time constant of the gate diodes 50. Resistors may be included between the collector of transistor 22 and the diode 38 to reduce the effect of variations in the transistors 22, 23 when fully conducting. In a modification, Fig. 3 (not shown), transistors of opposite conductivity type are used. In a further modification, Fig. 4 (not shown), the amplifier transistor 39 is connected in a common base connection and may be a point contact type. In a further modification, Fig. 5 (not, shown), the amplifier transistor 39 is operated in the common emitter connection.