Patent GB-1045286-A (GB)
Title: Electrical digital computing engines
Inventor: STONE DAVID
IPC: G06F9/22
Filed: 1963-07-15
Abstract: 1,045,286. Digital electric calculating apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. July 15, 1964 [July 15, 1963], No. 27906/63. Heading G4A. A digital computer comprises a store having a block of "special" locations which are such that when a word is transferred thereto, various logical functions of the word are available for read-out therefrom, and calculations can be effected by transfers to and from the special locations. Thus in the special locations of Fig. 2 (not shown), if a binary word X is written into the top row of cores, row 0, the arrangement of windings is such that the following words can be read from the stated rows: from row 1, the complement X of X; from row 2, X shifted one place left; from row 3, X shifted two places to the left; from row 5, the word having the digits of X in the reverse order; from row 6, the logical sum of all the digits of X; from row 7, X shifted one place right. The computer described, Fig. 3 (not shown), comprises a store 20, instruction register 24, number register 22 and control unit 28 containing a bi-stable circuit 30 set by the sign digit when a number is read from store 20. Instruction words are of 25 digits comprising two function digits, three special location address digits, ten operand address digits and ten next instruction address digits. Instruction words are of four types: in type A the contents of the operand address location are transferred without clearing to the special location; in type B the same transfer is effected with clearing of the operand address location; in type C the special locations are cleared and the contents of the specified location transferred to the operand address location; in type D the specified special location is tested for negative contents and if negative the next instruction is taken from the operand address, but if positive or zero sequencing is normal. Each instruction is executed in a single " bar " of nine " beats " at each of which certain of the gates 1-13, Fig. 3, are opened. Addition of two operands X and Y may be effected by a permanently available microprogram of sixteen instructions, sum and carry digits being formed by transfers between ordinary and special storage locations using logical sum and complementing only, based on the formulµ The addition is performed in a plurality of cycles and is terminated when a test of the carry digits formed in a cycle discloses that they are all zero so that no further additions of carries are required. Subtraction may be performed similarly. In a second embodiment Figs. 4, 5 (not shown), the D-type of instruction is modified in that if a test results in a negative sign, the next instruction is taken from the next instruction modified by the replacement of its three least significant digits by the three digits in the special location part of the instruction word. Further, there are additional special locations providing logical functions of two operands so that the number of microprogram steps required for addition or subtraction is reduced. Reference is made to a computer having an address counter so that programming may be simplified.