Patent GB-1420676-A (GB)
Title: Semiconductor devices
IPC: H01L27/06
Filed: 1973-04-11
Abstract: 1420676 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 11 April 1973 [14 April 1972] 17308/73 Heading H1K A monocrystalline semi-conductor body of Si (Figs. 1, 2) comprises a P-type region 3, 12 adjoining a surface 2 and an N-type region 4 adjoining surface 2 to form a PN junction 5 between the regions. P-type source and drain regions 6, 7 adjoining the surface are formed in region 4, and a gate electrode, e.g. of polycrystalline Si overlies an insulant, e.g. SiO 2  layer 9 therebetween. An insulant pattern 10 of, e.g. SiO 2  at least partly inset into the surface bounds region 4 and adjoins PN junction 5 and the source and drain regions 6, 7. Region 4 comprises part of an epitaxial N-type layer 11 overlying P-type substrate region 3 and is surrounded by local P-type region 12 extending from surface 2 through the thickness of epitaxial layer 11 and adjoining and bounded by the inset oxide pattern 10 bounded by line (12). N-type source and drain regions 14, 15 are provided in zone 12 adjoining surface 2 and inset pattern 10 as part of a complementary P-type FET with a gate 16 of polycrystalline Si intermediate the source and drain zones overlying a SiO 2  layer 17. A layer 13 of SiO 2  overlies the semi-conductor body, which is windowed for connection of Al layers 24 to 29 to zones 6, 7, 14, 15 respectively. A poly crystalline Si layer 30 on inset oxide pattern 10 interconnects other parts of the circuit (not shown) and insulatedly traverses Al layer 26. In fabrication, an N-type Si layer 11 is epitaxially grown on a P-type Si substrate 3 and is thermally oxidized to an insulant layer on which are overlain layers of Si 3 N 4  and pyrolytic SiO 2  The latter layer is photolitho etched into a mesh defining a pattern through which the nitride layer is etched with H 3 PO 4  and the oxide layers with buffered HF. The exposed Si is then etched (Fig. 4, not shown) and thermally oxidized in wet O 2  to form an inset oxide pattern 10 flush with the surface, after which the nitride and oxide layers are locally removed by masking and etching from layer 11. B is indiffused thermally from the nitride over the oxide pattern 10 as mesh, and an oxide layer 34 is formed at surface overlying a P-type region 12 (Fig. 6). Alternatively ion implantation may be used; oxide layer 34 is removed, and the B is thermally driven in to substrate 3 in vacuo and also cut diffused through the surface with pattern 10 as mask whereby a surface layer 35, (Fig. 7), is formed having a B concentration increasing from the surface inwardly to line 36. The residual layers 31, 32 are removed and a further oxide layer is thermally formed on which a poly crystalline Si layer is deposited thermally from SiH 4 , strongly P-doped by diffusion, and covered with a layer of pyrolytic or thermal oxide (Fig. 8, not shown). Gate electrodes 8, 16 of the FETs and interconnection 30 are formed photolithographically from the polycrystal and oxide layers (Fig. 9, not shown). The oxide layer under the polycrystal at the surface of region 4 is etched off but retained under gate 8 and on the surface part 41 (Fig. 1), after which P-type source and drain regions are B in diffused or ion implanted over gate 8 and oxide layer 10 as mask. Thereafter a SiO 2  layer 40 is deposited (Fig. 10) and etched off part of zone 12 (Fig. 11, not shown) after which N-type source and drain regions 14, 15 are P in diffused or ion implanted over gate 16 and oxide 10 into layer 13, which has high B concentration around line 36 to prevent channel formation along inset oxide 10 between the epitaxial layer and legions 14, 15. An overlying oxide layer 13 is applied to the assembly (Fig. 12) after removal of the remainder of layer 40 and windowed by etching over a mask, after which Al is deposited in a required pattern by photolithography and etching to produce the final structure of Figs. 1, 2; Al layer 24 contacting regions 6 and 41 to short circuit region 4; the channel 12 of the FET 14, 15, 16 being contacted through substrate 3. The device is finally annealed in H 2  + N 2  One or more FETs may be combined additionally with one or more bipolar transistors; the inset oxide pattern bounding a further N- type epitaxial region in turn bounded by a further local P-type region extending from the surface to the substrate and forming therewith a PN junction adjoining the oxide pattern. Further P-type regions are formed in the further N-type region to define emitter and collector zones of a bilateral transistor of which the N- type region is the base. A highly doped buried N-type layer underlying the N-type epitaxial region prevents parasitic effects between the substrate and the emitter and collector zones, while other highly doped N-type zones separating the latter zones and the inset pattern serve as contact diffusions, and further reduce parasitic action. Polycrystal field electrodes separated by oxide from the surface are connected by Al base contact layers to the further N-type epitaxial region to discourage parasitic surface channels. The substrate is connected to an Al contact layer over a highly doped P-type zone in a contact window of the oxide layer (Fig. 13, not shown). In a modification (Fig. 14, not shown) the emitter and collector zones of the bilateral transistor adjoin the inset oxide pattern and the latter extends down to the buried N-type layer. In modification (Fig. 15, not shown) a P-type surface base zone bounded by the inset oxide pattern is formed in the further part of the N- type epitaxial layer, within which a further N- type surface emitter zone is formed, to constitute an isolated PN vertical transistor. In other modifications (Figs. 16, 17, 18, not shown) one or more vertical transistors with common collector or emitter may be provided; the further part of the N-type epitaxial layer being divided into two islands by the inset oxide. Semi-conductors other than Si may be used, conductors other than polycrystal Si may be used for the gate and field electrodes; metals other than Al may be used for conductors and insulants other than SiO 2 , e.g. Si 3 N 4 , Al 2 O 3  or composites thereof may be used. All conductivity types may be inverted, and dopants other than P and B may be used. The FETs may be of tetrode type with more than one insulated gate, and other bipolar elements, e.g. thyristors may be incorporated. Variations of the doping and masking procedures are described.