Patent GB-1415858-A (GB)
Title: Time division multiplex switching networks
IPC: H04J3/00
Filed: 1972-11-28
Abstract: 1415858 Automatic exchange systems WESTERN ELECTRIC CO 28 Nov 1972 [27 Dec 1971] 54866/72 Heading H4K In a TDM switching network each incoming highway is coupled to a plurality of time slot interchangers such that every time channel on the highway enters a different interchanger and is there switched to a desired output time slot. In practice the coupling is effected with the aid of a series/parallel converter which takes the same numbered slot from a plurality of incoming highways and inserts these slots in series into an interchanger allocated exclusively to the slot. Fig. 1 shows the case where L "highways" TSI 1 -I to TSI 1 -L each carrying M time channels are connected via converter SP 1  to M interchangers TSI 1 I to TSI 2 -M each of which contains L same numbered time slots, i.e. one per incoming highway. The channels, after time switching, are then coupled to the L output "highways" TSI 2 I to TSI 3 L via converter SP 2  which operates in inverse manner to SPI. The network may use single-wall magnetic domain, charge-coupled or bucket-brigade devices. Three-stage network Fig. 1 comprises a time slot interchanger TSI 1 -I to TSI 1 -L in respect of each of the L incoming highways and similarly an interchanger TSI 3 -I to TSI 3 -L for each of the L outgoing highways 12. Each of the incoming highways carries N channels. The interchangers provide an output for TSI 1  or an input for TS 3  of M channels, where M is chosen in accordance with the desired degree of blocking. In one of the examples there are 48 incoming and outgoing highways each of which carries 48 'channels. Provision is then made of 96 intermediate time slots, e.g. interchangers TSI 2 , so that a non-blocking network catering for 2304 connections is obtained. The central stage comprises M interchangers TSI 2  which are accessed from stage TSI 1  by a parallel/serial converter S-PI and which access stage TSI 3  via a serial/ parallel converter SP 2 . The converter SP1 takes the parallel L outputs from stage TSI 1  during a particular time slot say N and inserts them in serial fashion into the Nth interchanger TSI 2 -N. The converter SP2 operates in complementary fashion. The converters may utilize a two-dimensional magnetic domain shift register of the type disclosed in U.S.A. Specification 3,723,985 which permits a single device to perform the necessary storage and shift functions. If a discrete component converter is used then two such devices are required, one being written-in by TSI, while the other is being read-out to TSI 2  during one frame and vice versa during the next frame. Fig. 2 depicts the concept of a discrete component register wherein signals from the L interchangers TSI 1  are fed in parallel during successive time slots of one frame from the left into the rows of a bottom-left-to-top-right shifting register whereafter during the next frame the left input to this register is inhibited and its columns are then read-out bottom-right-to-topleft into respective ones of the M interchangers TSI 2 . The interchangers may be of the magnetic domain type described in Specification 1,415,859. Path finding.-It is assumed that a processor, e.g. of the stored programme type is acquainted with the calling and called party identities expressed as time slot numbers on a particular incoming 11 and outgoing 12 highways. It therefore remains to find a common free time slot at the output of TSI 1  and the input of TSI 3  which slot also defines the interchanger to be used in TSI 2 . Every busy connection is signified by the presence of a busy "1" bit in a particular bit position of its time slots as discussed in more detail in Specification 1,415,859. Consequently by examining in logic 23 the busy bit positions of the channels leaving the interchanger TSI 1  to which the caller is connected and similarly in logic 27 for the channels entering the interchanger TSI 3  to which the called party is connected and then by comparing, as at 26, the two sets of busy bits, a common free time slot can be found. This information is written into the recirculating memories that control the operations of the interchangers TSI 1  and TSI 3  together with, respectively, the calling and the called time slot identities. The control information written into TSI 2 's memories comprises the identities of the calling and called highways expressed as time slot numbers in a frame L time slots long. Further details of the manner of write-in to the memories can be obtained from Specification 1,415,859. The connection is released when the busy bit is removed following hang-up by the calling party. The absence of the busy bit is noted by each of the interchangers' circulating memories in turn and these therefore release themselves from the connection one after the other. Five stage network, Fig. 3.-This comprises 48 groups of incoming highways each of which groups consists of 48 highways carrying 48 channels. Each group has a parallel serial converter SP1 whose 96 outputs are crossconnected to 96 second stage interchanger groups having 48 interchangers per group. As with the first stage interchangers, the second stage interchangers each provide a 96 time slot output so as to provide a non-blocking arrangement. It should be clear from the Figure that the second, third and fourth stages constitute a plurality-in fact 96-of three stage networks akin to that of Fig. 1 and that the stage 4/5 interconnections are a mirror image of the stage 1/2 interconnections. A suggested analogy for the network is that it comprises 96 parallel planes each carrying a Fig. 1 type network and 48 parallel input planer and 48 parallel output planer each carrying a group of 48 incoming and outgoing highways respectively and a converter SP1 and SP4 respectively, the input and output planes being orthogonal to the central planes and having access to all of them. Path finding is effected by matching a slot leaving TSI, with a slot entering TSI 5  as described above and then performing a further match for the stages TSI 2 , TSI 4  so that eventually a unique path is obtained. Network growth is accommodated by providing all the central planes and adding input and output planes as required, or, by providing half the number of central planes and multipling input and output planes thereto until half the final number of terminations is reached (final number is 110592 in the example given) whereupon the remaining central planes are provided and the multipling on half the input and output planes is rearranged. Modified 5 stage network (Fig. 4) having a low but finite blocking probability (10<SP>-10</SP>). In this example a reduction in interchanger complexity is obtained by reducing their size from a 48 to 96 time slot capacity down to a 48 to 60 slot capacity. The inevitable resultant blocking factor is then reduced by using a revised trunking scheme. This involves cross-connecting second and third stage switches on both sides of the intervening parallel/serial converter SP2 and also by cross-connecting the third and fourth stages. The resultant lack of symmetry is more clearly seen in Fig. 4A and of course more complex path finding techniques (which are not disclosed are required. Growth, it is suggested, is accommodated as for the Fig. 3 embodiment. Simplified interchanger / converter group.- Fig. 5A depicts the previously described groups where L highways carrying A channels are connected to interchangers that provide 2B output channels. In order to reduce the processing speed (but not its complexity) and also the hardware requirements, the arrangement of Fig. 5B is proposed.