Patent GB-816861-A (GB)
Title: Apparatus for conversion between binary and decimal notations
IPC: H03M7/12
Filed: 1955-12-20
Abstract: 816,861. Digital electric calculating apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 20, 1955 [Dec. 31, 1954], No. 36439/55. Class 106 (1). In a binary-decimal code converter decimal to binary conversion is effected by repeatedly halving the decimal number, ignoring all remainders, and inserting a one in the appropriate denomination of a binary register each time the result is odd, and binary to decimal conversion is effected by producing in succession all the powers of two, starting with the highest within the converter's capacity and producing the remaining powers by successive halvings, and entering those powers of two corresponding to ones in the binary representation into a decimal accumulator. Each conversion takes eight cycles or steps, the converter accommodating eight binary denominations, and each cycle comprises 16 multivibrator points counted by a timing control circuit. At the end of each cycle a primary commutator consisting of a chain of eight hard valve triggers is advanced one step. During each cycle three operations occur common to both conversions: (1) at point 1 half the number in a register A, ignoring any remainder, is transferred to a register B, (this being effected by a multiplication by five combined with a decimal shift) both registers A and B being decimal registers in which one out of ten hard valve triggers is on in each denomination, (2) at point 12 register A is cleared, and (3) at point 15 the number in register B is transferred to register A and register B is cleared. For a decimal to binary conversion the decimal representation of a number is inserted by a full keyboard into register A, registers A and B having both been previously cleared, and a start key is depressed, whereupon when the timing control circuits next reach the beginning of a cycle the first state of the primary commutator is set on and the conversion commences. (The timing control circuits are free running but both the primary commutator and a secondary commutator, being open-ended, have all their stages off except when they are set on to control a conversion.) During each cycle, in addition to the three operations mentioned above a further operation is performed simultaneously with operation (1): if the number in register A is odd a one bit is inserted into a denomination of the binary register corresponding to the number of the cycle being performed. This results, after eight cycles, in a binary representation in the binary register of the number that was initially in register A. For a binary to decimal conversion the binary representation of a number is inserted into the binary register (by means not described), the start key is depressed, and as before, the conversion commences. At point O of the first cycle the number 128 (28) is inserted into the A register, and thereafter, in every cycle in which a one appears in the corresponding denomination of the binary register and simultaneously with operation (1) mentioned above the secondary commutator is caused to commence a cycle of operation resulting in the entry of the number in register A into the decimal accumulator. This is achieved by entering into each binarycoded decimal denomination of the accumulator pulses equal in number to the digit being transferred, inter-denominational carry occurring during the eleventh and last step of the secondary commutator. Thus finally after eight cycles the decimal accumulator contains a binary coded decimal representation of the number in the binary register.