Patent GB-1207201-A (GB)
Title: Selective calling system
Inventor: SHARMA ROSHAN LAL
IPC: H04W88/02
Filed: 1968-04-23
Abstract: 1,207,201. Selective calling systems. COLLINS RADIO CO. 23 April, 1968, No. 19140/68. Heading G4H. A selective calling system comprises a first means for generating a redundant address code and means for receiving it, the first means comprising a shift register having N stages each with an input for presetting it, an Exclusive Or gate responsive to the states of certain ones of the stages and means for connecting the output of the Or gate to the input of the first shift register stage. A redundant address code is a series of marks and spaces which is an expanded form of a shorter group. Thus an address may have three bits but is sent as a group of seven bits, four of the bits being redundant and serving to enable groups to pass as correct which have developed erroneous bits. In the form described, the shift register 100 comprises three stages 101, 102, 103 and the contents are shifted by pulses from source 115. The first and third stages are connected to the Exclusive Or gate 104 which produces a "1" when the inputs are different and a "0" when they are the same, the output passing to the input of the first stage via a gate 110. If the initial setting of the register is 101, seven shift pulses will cause a pattern 1100101 to pass from the final stage 103 via switch 118 to a modulator 111 to be transmitted from antenna 113. The switch 118 is moved to the other contact to transmit a message from source 119. The complete address comprises in all fourteen bits, of which the first seven (110101) are "an address recognition code" common to all receivers and serving to alert them. The initial setting "101" is entered initially by three switches in unit 119 which are momentarily connected to the shift register stages by switches 134 and Or gate 123-125. When the sequence of seven bits has been transmitted, it is also entered in a shift register 140. An And gate connected to the seven stages responds to the presence of the address recognition code to energize a unit 120 closing switches 121 to transfer the setting of switches in unit 122 to the register 100. The register then produces a new sequence of seven bits which is the address and calls a particular receiver. Receiver.-At the receiver (Fig. 3, not shown) the transmitted signals are demodulated and the bits of the address recognition code are entered in a seven-stage shift register and are recognized by an And gate. When the gate responds, which it does in all receivers, the signal starts a local code generator having a threestage shift register and an And gate similar to that of the transmitter. This receives seven shift pulses and the seven generated bits are compared with the incoming address bits by an And gate. The output of the And gate passes to a counter so that coincidences are counted up to seven. If the counter reaches six the address is accepted as correct and a gate is opened to pass the message following. In another form the address code is transmitted in parallel, no address recognition code then being necessary. The address bits are generated as described with reference to Fig. 1 and entered in turn in a shift register. At a count of seven, the stages of the shift register are connected in parallel to a modulator and the seven bits are sent simultaneously. At the receiver the received bits are entered in parallel into a shift register and then shifted out to be compared with the locally generated code as described above.