Patent GB-1158889-A (GB)
Title: Data Processing System
IPC: G06F15/16
Filed: 1968-07-03
Abstract: 1,158,889. Multi-processor computers. INTERNATIONAL BUSINESS MACHINES CORP. 3 July, 1968 [14 July, 1967], No. 31752/68. Addition to 1,150,110. Heading G4A. In a multi-processor computing system, each processor has an associated interaction controller capable of executing instruction sequences specified by the processor and specified by other such controllers, the controllers intercommunicating directly with each other over a common bus, and each controller includes count-off means for determining which of the controllers are working on the same job. The invention differs primarily from the parent regarding passing control of the bus between controllers, and in the provision of "count-off" means for determining which and how many of the controllers are working on the same job. Each controller has a "wait" flip-flop which it sets when it requires access to the bus, a "bus available" flip-flop, an equal-unequal compare unit, a unique 8-bit seizure code (having 4 ones and 4 zeros) and a unique index number. The index number has two octal digits each represented by an 8-bit byte consisting of (n+1) ones followed by (7-n) zeros, where n is the value of the octal digit. If a plurality of controllers apply bytes to the bus simultaneously, the bus effectively ORs corresponding bits, so that if two or more seizure codes are applied simultaneously the bus signal will not be equal to any of them, and if two or more index digits are applied simultaneously the bus signal will be equal to the largest. Passing control of the bus.-When a controller has finished with the bus, it releases it by applying a "release bus" code to the bus followed by the first digit of its index number. Each controller waiting for access to the bus compares the first digit of its own index number with the disjunction (i.e. OR function of corresponding bits) of this digit and the digit on the bus. Than the releasing controller sends the first digit of its own index number again and each waiting controller compares this with its own first index digit. Then the releasing controller sends its second index digit and each waiting controller compares its own second index digit with the disjunction of this digit and the digit on the bus. From the results of these comparisons, each waiting controller classifies itself as being in a first class (i.e. having a lower index number than the releasing controller) or a second class (higher number). Each waiting controller of the first class now applies its first index digit to the bus and compares its first index digit with the bus. If unequal, it sets its "bus available" flipflop to 0 (since this means there is a waiting controller in the first class with a higher index number) but if equal the controller applies its second index digit to the bus and compares its second index digit with the bus. If equal, the controller has control of the bus. If unequal, it sets its "bus available" flip-flop to 0. Thus if there are any waiting controllers in the first class, the one with the highest index number obtains control of the bus. Concurrently with each waiting controller of the first class applying its first index digit to the bus, the other controllers (waiting and non-waiting) compare the bus with all-zeros. If unequal, indicating there is at least one first class waiting controller, the "bus available" flip-flop is set to 0. If equal, the following operations occur. Up to this point a waiting controller was one which was waiting when operations began. Henceforth it is one which was waiting at this point. Each waiting controller applies its first index digit to the bus and compares the bus with its first index digit, while each non-waiting controller compares the bus with all-zeros. Equality and non-equality in a non-waiting controller cause the "bus available" flip-flop to be set to 1 and 0 respectively, while inequality in a waiting controller sets the "bus available" flip-flop to 0. Any waiting controller having equality applies its second index digit to the bus and compares the bus with its second index digit. If equal, the controller has control of the bus. If unequal, the "bus available" flip-flop is set to 0. Thus, summarizing, when a controller releases the bus, the initially waiting controller having the highest index number which is less than that of the releasing controller, if any, acquires control of the bus, otherwise the controller waiting at the intermediate time which has the highest index number acquires control. It may be that no controller has control of the bus at a particular time. In this case each "bus available" flip-flop will be at 0 and any controller which enters the waiting state can attempt to seize the bus, as follows. It applies its seizure code to the bus and compares the bus with its seizure code. Equality indicates it is the only controller attempting to gain control of the bus, and it gains control forthwith. Inequality causes it to apply its first index digit to the bus and compare the bus with its first index digit. Inequality sets the "bus available" flip-flop to 0. Equality causes it to apply its second index digit to the bus and compare the bus with its second index digit. Equality indicates it has control of the bus, and inequality sets the "bus available" flip-flop to 0. Thus in the event of concurrent seizure attempts the controller with the highest index number is successful. Count-off.-To perform this sequence, the controller (transmitter) having control of the bus applies a "job code" to the bus followed by a job number (specifying the job the controller is working on). Every other controller (receivers) compares this job number with its own and if unequal drops out of the sequence. The transmitter sends a "count off" code. Two cycles are now repeated until the transmitter, comparing the bus with all-zeros in the first of the cycles, detects equality, in which case the sequence terminates. Inequality increments a counter to provide the "count." In the first cycle, each receiver applies its first index digit to the bus and compares the bus with its first index digit. In the case of inequality, the receiver, in the second cycle, does nothing, but in the case of equality, it applies its second index digit to the bus and compares the bus with its second index digit. Equality causes it to drop out of the sequence, and inequality causes it to participate in the next repetition of the "two cycles". Thus the count in the transmitter finally specifies the number of controllers working on the same job as the transmitter, by specifying the number of repetitions of the "two cycles" required to eliminate the participitating controllers one at a time. Other features.-The maximum of a set of index numbers was found above, but use of complements would enable the minimum to be found. Each controller can interrupt its associated processor. A controller instruction may cause it (the controller) to ignore subsequent instructions in the instruction sequence it is executing until another instruction countermanding the order is encountered. Use of techniques described above permits an instruction to cause counting of the number of controllers meeting chosen criteria and to select one of them. A controller instruction may cause its associated processor to execute an instruction appearing on the bus (linking controllers), the processor then proceeding with its own programme where it left off (unless e.g. the instruction was a branch instruction).