Patent GB-865353-A (GB)
Title: Improvements in or relating to pulse generators
IPC: H04L7/027
Filed: 1959-12-02
Abstract: 865,353. Pulse signalling; transistor blocking oscillator circuits. WESTERN ELECTRIC CO. Inc. Dec. 2, 1959 [Dec. 11, 1958], No. 40901/59. Classes 40(5) and 40(6) Relates to a regenerative repeater employed in a pulse transmission system wherein the input signal consists of "on" and "off" pulses combined in preassigned phase relation with a timing wave, and comprising means for deriving a second timing wave from the input signal, means jointly responsive to the input pulse train and to the second timing wave for generating an output pulse train corresponding to the input pulse train, and means for combining at least a part of the second timing wave with the output pulse train. As shown, the input signal is supplied via a transformer T1 and equaliser circuit including inductors L1, L2, which compensate for the transmission line characteristics, to an amplifier comprising transistors Q1, Q2, Q3, the amplifier being provided with negative feedback comprising resistors R17, R18, R19, R20 and capacitors C7, C8, C9, in order to stabilise the gain and provide a low output impedance. The output of the amplifier is supplied to a circuit L1, C16, C17, which is tuned to the pulse repetition rate, and the resulting sinusoidal timing wave is amplified by the transistors Q5, Q6 of the clock amplifier, which is provided with negative feedback via a resistor R30 in order that the resulting low input impedance can be connected in series with L1. The output of transistor Q3 is also supplied via a diode clamp CR1, the clamping level being determined by a diode CR5 and resistor R25, to a diode CR2 and the application of a negative pulse from transistor Q3 back-biases diodes CR1, CR2. Under this condition resistor 23 draws current either from the base of transistor Q4 or from the collector of transistor Q6 via diode CR3. The positive excursions of the timing wave from transistor Q6 are clamped by diode CR4 to the clamp potential. When the clock signal is positive current flows through diode CR3, resistor R24, and resistor R23 to the negative source -E1 and no current will be drawn from the base of the transistor Q4. The transistor Q4 is connected through transformer T2 as a blocking oscillator with a natural period considerably longer than a normal pulse interval. When the clock signal goes negative diodes CR4 and CR3 are backbiased and current is drawn by resistor 23 from the base of transistor Q4, and the oscillator is triggered. Thus the presence of both a negative input pulse at the start and a negative excursion of the timing wave causes current in the collector and base circuits of the transistor Q4 to build up until the transistor reaches saturation, and an output pulse is supplied to the transformer T3 until the clock voltage again goes positive. A compensating network C14, R26, assists in maintaining the pulse amplitude constant and circuit L5, R27, compensates for the output cable characteristics. The timing signal from the collector of transistor Q6 is supplied to the lower terminal of the primary winding of the transformer T3 whereby it is superimposed in the correct phase on the pulse train. In a modification, Fig. 3 (not shown) the timing wave is taken from the emitter of transistor Q6 and is connected via a diode and at a reduced amplitude to the upper terminal of the primary winding of transformer T3. In this arrangement timing information is provided only in the intervals where no signal pulses appear.