Patent EP-4167278-A3 (EP)
Title: Methods and apparatuses with reduced defects in interconnecting bumps between a semiconductor die and a substrate (a package substrate or another die)
Inventor: MANEPALLI RAHUL N
IPC: H01L23/538
Filed: 2022-09-22
Abstract: Example methods and apparatuses reduce the likelihood of defects forming in bumps (114, 116, 118, 808, 810) associated with first level interconnects between semiconductor dies (106, 108, 802) and substrates (package substrates (110, 804) or other dies) associated with shifting in plated tin (1802, 2506) upon stripping and swelling of a dry film resist (1002, 1102, 2406), wicking of tin (1802, 2506) upon tin (solder) reflow following removal of the dry film resist (1002, 1102, 2406) (which both could lead to unintended bridging of bumps) and a lack of co-planarity across different bumps due to warpage and/or other factors, by fabricating dummy bumps (702, 812) adjacent operational bridge bumps (604, 810), fabricating bumps (1806+1808+1802) with bases (1806+1808) with non-circular shapes (e.g., polygonal shapes such as octagonal or hexagonal, wherein the shape may correspond to a packing geometry of the bumps), and/or fabricating bumps (2502+2504+2506) with diameters or widths and heights that differ spatially across the area (e.g., between ring-shaped regions (2712)) over which the bumps (2502+2504+2506) are distributed. Such potential defects are reduced in a manner that enables the bumps to be fabricated with a smaller size and/or smaller spacing to meet the ongoing needs of scaling down the overall size of electronic components. In an embodiment, the bumps (114) of the first level interconnects include two different types of bumps corresponding to core bumps (116, 808) (i.e., bumps on the dies (106, 108, 802) through which electrical signals pass between the dies (106, 108, 802) and the package substrate (110, 804) and then to components external to the IC package (100)) and bridge bumps (118, 810) (i.e., bumps on the dies (106, 108, 802) through which electrical signals pass between different ones of the dies (106, 108, 802) within the package (100), via an interconnect bridge (126) embedded in the package substrate (110)), wherein the core bumps (116, 808) are typically larger than the bridge bumps (118, 810). An array of dummy bridge bumps (702, 812) may be positioned adjacent the outer edge or perimeter of the operational bridge bumps (604, 810) so as to at least partially fill in open spaces (608) adjacent an outer edge or perimeter of the array of operational bridge bumps (604, 810) and thus limit bump shifting upon resist swelling in the remaining open space to the dummy bridge bumps (702, 812), thereby protecting the operational bridge bumps (604, 810), as well as to improve plating uniformity (e.g., the relative bump thickness variation (rBTV)) across the operational bridge bumps (604, 810). The operational bridge bumps (604, 810) and the dummy bridge bumps (702, 812) may have the same or different size and shape. The dummy bridge bumps (812) may have a shorter height so that they do not form a connection that extends a full distance between the die (802) and the package substrate (804).