Patent GB-1238021-A (GB)
IPC: H04Q11/04
Filed: 1967-09-07
Abstract: 1,238,021. Multiplex pulse signalling. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. 9 Sept., 1968 [7 Sept., 1967], No. 40894/67. Heading H4L. In a time division multiplex arrangement, a plurality of low bit rate time division multiplex systems in each of which information is conveyed by means of discrete pulses, are supermultiplexed in an exchange for manipulation in the exchange at a higher bit rate. General description. As shown, n low speed systems LS1 to LSn are to be super-multiplexed on a high speed highway HS for manipulation within an exchange EE. In each of the low speed channels the sampling rate is 8 kc/s and there are 8 bits per channel and 24 channels so What the bit rate is 1À536 Mb./s. requiring a bit rate of n x 1À536 Mb./s. for the high speed channel. Each low speed channel is coupled to a transfer arrangement SMI to SMn which each include a pair of 8-bit shift registers R1/1, R2/1 &c., and provide time compression of information transferred from a low speed to the high speed channel or time expansion for the reverse operation. The two shift registers are arranged to operate at two reading speeds (the high and low bit rates) alternately. In Fig. 2, pulses CL1  to CL24 define the low speed channels and pulses CH1 to CH24n define the high speed channels. The third, fourth and fifth lines of pulses show the allocation of the high speed channels to the arrangements SM1 to SMn. Thus, high speed channels 1, n + 1, 2n + 1, 23n +1 are allotted to SM1 (pulses Pa/1 Pb/1) and so on. Pulses P1 and P2 correspond to alternate channels of a low speed system, and are derived from each of the low speed systems. Clock pulses LSCe are derived from the normal clock pulses LSC and occur at the end of each bit interval in a low speed system, similar clock pulses LSCc occurring at the centre of each such interval. High speed clock pulses HSCe and HSCc (not shown) are derived similarly. Operation. It is assumed that each of the shift registers R1/1 to R1/n is storing information received over the "GO" path from channel 24 of the corresponding low speed system via gates GLG1/1, GLG1/2 &c., during the P2 pulse period and written into the shift registers by clock pulses LSCc as gated by pulse P2 at gate LG1/1 &c. In the following P1 pulse period, gates GLG2 are opened so that information in channel 1 of each low speed system is passed from the "GO" path to the corresponding shift register R2/1 &c. and written in by pulses LSCc via gates LG2. During the pulse P1 period control pulses Pa/1 to Pa/n for channels ch1 to chn of the high speed system HS occur so that information is read out of registers R1/1 to R1/n in succession via gates HG1/1<SP>1</SP> &c. and bi-stables B1/1 &c. during this period and supplied via corresponding gates GHGa to the high speed highway HS and exchange EE. During the pulse period Pa/1 information will be applied over the "RETURN" of the high speed highway HS and written into shift-register R1/1 via gate RHGa/1 under the control of clock pulses HSCc via gate HG1/1 so that after eight pulses HSCc information has been returned to the shift register R1/1. Similar operations take place during pulse periods Pa/2 &c. for shift registers R1/2 &c. In the following P2 pulse period, gates LG1/1, LG1/1<SP>1</SP> and RLG1/1 in SM1 and corresponding gates in SM2 &C are opened so that information is read out of registers R1 by the slow speed clock pulses LSCe to the respective low speed highways. Also during period P2 gates GLCI are opened so that information on the "GO" path of the low speed highways is being written into registers R1, and control pulses Pb/1 to Pb/n occurring in succession causes information to be read out of registers R2 to the high speed highway HS. This cycle is repeated for subsequent pulses P1, P2. The phasing of pulses P1, P2 may be adjusted to correct for any difference in the "GO" and "RETURN" paths of the low speed systems.