Patent SG-11201804490V-A (SG)
Title: Wide band gap device integrated circuit architecture on engineered substrate
Inventor: ODNOBLYUDOV VLADIMIR
IPC: H01L21/20
Filed: 2016-12-01
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -' Organization International Bureau ires.. 00) (43) International Publication Date ..... ..sr ,„,„.1 8 June 2017 (08.06.2017) W I P0 1 PCT (10) WO International 111111111111311111111111111111111111111111111111111111111111111111111111111111111111111111 2017/096032 Publication Number Al (51) International Patent Classification: AO, AT, AU, AZ, BA, HO1L 21/20 (2006.01) C30B 29/36 (2006.01) BZ, CA, CH, CL, CN, CO4B 35/00 (2006.01) C3OB 33/10 (2006.01) DO, DZ, EC, EE, EG, C3OB 29/06 (2006.01) F21K 99/00 (2016.01) HN, HR, HU, ID, IL, IN, KW, KZ, LA, LC, LK, (21) International Application Number: MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, PCT/US2016/064405 OM, PA, PE, PG, PH, (22) International Filing Date: SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, 1 December 2016 (01.12.2016) TN, TR, TT, TZ, UA, ZW. (25) Filing Language: English (84) Designated States (unless (26) Publication Language: English kind of regional protection (30) Priority Data: GM, KE, LR, LS, MW, 62/263,462 4 December 2015 (04.12.2015) US TZ, UG, ZM, ZW), Eurasian TJ, TM), European (AL, (71) Applicant: QUORA TECHNOLOGY, INC. [US/US]; DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, 2306 Waslsh Avenue, Santa Clara, California 95051 (US). LV, MC, MK, MT, NL, (72) Inventors: ODNOBLYUDOV, Vladimir; 2306 Walsh SM, TR), OAPI (BF, Avenue, Santa Clara, California 95051 (US). BASCERI, GW, KM, ML, MR, NE, Cem; 2306 Walsh Avenue, Santa Clara, California 95051 Published: (US). BB, BG, BH, BN, BR, BW, BY, CO, CR, CU, CZ, DE, DJ, DK, DM, ES, FI, GB, GD, GE, GH, GM, GT, IR, IS, JP, KE, KG, KN, KP, KR, LR, LS, LU, LY, MA, MD, ME, PL, PT, QA, RO, RS, RU, RW, SA, UG, US, UZ, VC, VN, ZA, ZM, otherwise indicated, for every available): ARIPO (BW, GH, MZ, NA, RW, SD, SL, ST, SZ, (AM, AZ, BY, KG, KZ, RU, AT, BE, BG, CH, CY, CZ, DE, NO, PL, PT, RO, RS, SE, SI, SK, BJ, CF, CG, CI, CM, GA, GN, GQ, SN, TD, TG). — with international search report (Art 21(3)) (74) Agents: LARGENT, Craig C. et al.; Kilpatrick Townsend before the expiration of the time limit for amending the & Stockton LLP, Mailstop: IP Docketing - 22, 1100 claims and to be republished in the event of receipt of Peachtree Street, Suite 2800, Atlanta, Georgia 30309 (US). amendments (Rule 48.2(h)) (81) Designated States (unless otherwise indicated, for every kind of national available): AE, AG, AL, AM, protection (54) Title: WIDE BAND GAP DEVICE INTEGRATED CIRCUIT ARCHITECTURE ON ENGINEERED SUBSTRATE 58N 2u0 — Thei ,-1\"32N ',WE' 2 :- - -1.6 ) ), E_p #N) = J,, V^,N = V ELECTRODE '2 ' I It (K :E\",•, —‹ B d2 / 6,;e) Lit z. v;LE 1 ), / I ?OFFER I R 32 , 11 .4t en en o C ) (57) : Disclosed herein are wide C ---. plurality of groups of epitaxial layers formed 1 L .-- epitaxial layers have a coefficient of theimal ..::::; internal interconnects, and electrodes configure N different WBG devices into a WBG integrated 0 location density and an overall thickness size and thick WBG epitaxial layers allow a large 5- strate. band of greater male, t;IAME I eF1 ( FIG. 2 gap integrated circuits, such as gallium nitride on an engineered substrate, and methods of making expansion (CTE) substantially matching the CTE each group of epitaxial layers into a WBG device. circuit. The CTE matching allows the foiination than 10 microns on a six-inch or larger engineered number of high density WBG integrated circuits (GaN) integrated circuits, including a the WBG integrated circuits. The of the engineered substrate. Mesas, External interconnects connect of epitaxial layers with reduced dis - substrate. The large substrate to be fabricated on a single sub -