Patent GB-1396923-A (GB)
Title: Data communication system
IPC: H04Q9/14
Filed: 1972-05-31
Abstract: 1396923 Data transmission system RECEPTORS 31 May 1972 [3 June 1971] 25543/72 Heading G4H In a system for communicating digital data between dispersed stations via a common channel, the address signal sequence of M bits comprises 2<SP>n</SP> subsequences of N bit unique addresses and each station responds to one unique address and has means for applying a data signal representing a multibit data word to the channel in response to its address. Address generation and structure.-The address sequence is a cyclic sequence of M = 2<SP>n</SP> bits. Each address is a subsequence of N bits (4 as described) and each new address is generated, as shown in Fig. 2A by moving one digit to the left in the main sequence, including a new digit at the left hand end and dropping one from the right. The sequence of addresses is generated in a four stage shift register. The outputs of the first three stages are connected to the input of the succeeding stage and the complement of the output stage is normally connected to the input of stage 1. To create the stages (8) and (16) which do not follow the above conditions, logic circuit 42 detects stages (7) and (15) and switches the output of stage 4 to the input of stage 1 via gates 46, 48. The register is shifted by slow clock pulses. Pulse coding format.-These are shown in Fig. 3. Each address bit is generated for period TA (a). This period is considered to be made up of four timing bits T r , (b) each having a "1" period (t 0 ) and a " 0 " period (t 1  and t 2 ); t 0 , t 1  and t 2  being equal. The waveform for each address bit period T A  is made up by combining parts of the " timing bit 1 " waveform (b) and the " timing bit 0 " waveform (c) giving a waveform (d) for " 1 " address bits and a waveform (e) for " 0 " address bits. Both these waveforms have four characteristic rise or fall positions P 1 , P 2 , P 3  and P 4 . The address sequence (f) is thus generated for the address bit sequence 101. Timing waveform (g) is generated from address sequence (f) by setting a monostable multivibrator of period MV, where <SP>2</SP>/ 3  T t  < MV 1  < T t  by level transitions in waveform (f). Waveform (h) is obtained by clocking (f) into a delay time flip flop with synchronism from pulses of line (g) and address bit synchronizing pulses (i) are generated from (h) by using the transitions to set a monostable multivibrator of period MV 2  given by ¥ T A  < MV 2  < T A . The data signals which are in the form shown in line (j) and comprise four data bits per address period TA are added to the addresss signal during the last third (t 2 ) of each timing bit period T r . Station construction.-Each remote station can either receive or transmit data. The incoming signal (k) which is the same to all stations, is amplified at 150 and fed to edge detectors 152, 154 which, together with monostable 158 generate timing pulses (g) or (I). The detected negative edge of these pulses are supplied by detector 160 to flip-flop 162 as timing pulses and together with data waveform k, edge detectors 164, 166 and monostable 170 generate address bit sync. waveform n. The positive going edges of (n) are detected at 172 and are used to shift four bit register 174 which is constructed as shown in Fig. 2B. Decode circuit 176 detects correspondence between the reading in register 174 and the address of the station and produces an output on line 178 when this occurs. Timing synchronizing pulses (l) from monostable circuit 158 are also fed to the circuit comprising phase detector 184, voltage controlled multivibrator 186 and 3-stage ring counter 188. The phase loop locks on to the pulses (l) and the counter produces 3 outputs o, p, q corresponding to pulses at times t 0 , t 1  and t 2  respectively. When operating in the send mode, the data to be sent has been loaded into the four stages of shift register 200 and is added to the address signal f entering through gate 218 during the periods determined by output q of counter 188. When operating in the receive mode, the data bits are loaded serially into register 200 but are read only by the actuation of gate 204 when the station is being addressed.