Patent DE-602006001828-D1 (DE)
Inventor: LICITRA CHRISTOPHE
IPC: H01L29/786
Filed: 2006-11-17
Abstract: The production of a microelectronic device with a double grid structure for a transistor comprises forming a stack, an anisotropic etching of the stack by masking on a first structure having a channel formed from an etched semi conductor zone and motifs of a first and second grid, and an isotropic etching of at least a part of the first and second motif towards a channel. The grids are formed by the first and second layer of etched grid material. The production of a microelectronic device with a double grid structure for a transistor comprises forming a stack, an anisotropic etching of the stack by masking on a first structure having a channel formed from an etched semi conductor zone and motifs of a first and second grid, isotropic etching of at least a part of the first and second motif towards a channel, and forming a first and second metallic contact. The grids are formed by the first and second layer of etched grid material. The first metallic contact is linked with a third motif without contact with a fourth motif on a second structure. The second metallic contact is linked with a fourth motif without contact with the third motif on a second structure. The stack comprises a first layer of grid material, a first dielectric grid layer lying on the first layer of grid material, a semi conductor zone lying on the first dielectric grid layer, a second dielectric grid layer lying on the semi conductor zone and on the first dielectric grid layer, and a second layer of grid material lying on the second dielectric grid layer. The first and second layer of the grid materials are formed on the first and second stack with a number of sub-layers of different materials. The first stack is different from the second stack, where the first stack having different material. The first and second layer of grid material comprises a poly-silicon-germanium and sub-layer with a base of metallic material. The isotropic etching comprises dry etching of the poly-silicon-germanium with plasma, and dry etching of the sub-layers with a base of metallic material. The etched semi conductor zone contains silicon. After the isotropic etching, insulating spacers are formed on both sides of the motifs of the grids. After the isotropic etching, the first and the second zones are formed, which are in contact with the channel. The first zone is useful as a source region and the second zone is useful as a part of drain region. The formed first and second zone comprises epitaxial growth of semi conductor blocks on sides of the channel blocks. The semiconductor blocks are made up of a semiconductor base material, which is different from the semiconductor blocks or channel. The formation of the first and second zone comprises depositing a layer on a support, forming cavities in the layer on both sides of the first structure, and depositing metallic materials in the cavities to form a first metallic block and at least a second metallic block on both sides of the channel. The formation of the stack comprises depositing the first layer of dielectric grid on a semiconductor layer lying on an insulating layer that covers the first support, depositing the first layer of grid material on the first layer of dielectric grid, sticking the second support on the first layer of grid material, removing the first support and the part of the insulating layer, etching the semi conductor layer to form the semi conductor zone, depositing the second layer of dielectric grid on the semi conductor zone and the insulating layer, and depositing the second layer of grid material on the second layer of dielectric grid. The anisotropic etching comprises forming a second structure in a stack zone in which the second layer of dielectric grid lying on the first layer of dielectric grid. The second structure comprises third motif formed from the first layer of etched grid material and fourth motif formed from the second layer of etched grid material. The third and fourth motifs are separated by the dielectric grid layers. An independent claim is included for a microelectronic device.