Patent FR-2833114-A1 (FR)
Title: Multiband power amplifier implemented as an integrated circuit chip, comprises two transistors of final output stage whose elementary transistors are laid out in a mixed configuration
Inventor: YAMAMOTO KAZUYA
IPC: H03F3/72
Filed: 2002-12-04
Abstract: The multiband, in particular biband, power amplifier in the form of an integrated circuit (900,902) for use in frequency bands of systems such as DCS and GSM comprises a final output stage with two power transistors (Trd3,Trg3) constituted of elementary transistors (Tr) which are laid out in a mixed configuration in a rectangular region (PW3) of a semiconductor chip (999) where the power transistors of the final output stage are formed.  The first output transistor (Trd3) comprises a multiplicity of cells of elementary transistors (D) for transmitting a signal in the first frequency band, and the second output transistor (Trg3) comprises a multiplicity of cells of elementary transistors (G) for transmitting a signal in the second frequency band. The two output transistors comprise at least a part having a second cell of elementary transistor (G) formed between two first cells of elementary transistors (D) aligned in a given direction. An inductor (Lcc) and a capacitor (Ccc) in series are connected between the output node of the first transistor and the output node of the second transistor so to form with the parasitic capacitance of interconnections a parallel resonant circuit in order to ensure the interband insulation. The mixed layout of elementary transistors of respective bands avoids the concentration of electric current under the effect of heat generation. The first and second cells of elementary transistors (D,G) are laid out in alternation in at least one first direction and a second direction which is perpendicular to the first direction, or are laid out in groups which are mutually surrounded in alternation. The multiplicity of first cells of elementary transistors and the multiplicity of second cells of elementary transistors comprises each two conduction nodes and a control node. The first output transistor (Trd3) comprises a multiplicity of first interconnection conductors extending in the first direction and interconnecting electrically the first conduction nodes of the multiplicity of first cells of elementary transistors (D), a multiplicity of second interconnection conductors extending in the second direction and interconnecting electrically the conduction nodes of the first cells, and a fourth interconnection conductor extending in the second direction and connecting electrically the first interconnection conductors to form the output node of the first transistor. The second transistor (Trg3) comprises the fifth interconnection conductors extending in the first direction and laid out in the second direction in alternation with the first interconnection conductors and interconnecting electrically the first conduction nodes of the second cells, two multiplicities of interconnection conductors, and the eights interconnection conductor extending in the second direction and interconnecting the fifth conductors to form the output node of the second transistor. The transistors are preferentially of type the heterojunction bipolar transistor (HBT).