Patent GB-1211189-A (GB)
Title: Monitors
IPC: G06F11/36
Filed: 1969-05-19
Abstract: 1,211,189. Monitoring computers. INTERNATIONAL BUSINESS MACHINES CORP. 19 May, 1969 [10 June, 1968], No. 25384/69. Heading G4A. A monitor, for monitoring the operation of a computer, comprises means to select parts of data from the computer and compare them with stored comparators, the storage also holding the results of comparison operations and, in the event of no match in the comparison, receiving the selected parts as further comparators. As described, the storage is an associative memory 32 (in which the comparisons are performed) and supplementary storage 50, the former having an input/interrogation register 42, a mask register 43 and an output register 38, and the supplementary storage 50 having input and output registers 44, 40 respectively. Setting of match triggers, in word logic 48, in response to an interrogation, permits not only access to locations in the associative memory but also to corresponding locations in the supplementary storage. The monitored computer 30, which may be a System 360, supplies information via a monitor register 56 to an A register 54 which can also receive constants from a programme control unit 52, data from input/output 58, a time from a clock 60 and output from the associative memory and supplementary storage output registers. The A register can supply data via a cross-point switch 34 and an adder 46 to the input/output 58 and the input registers 42, 44 of the associative memory and supplementary storage. The connecting lines each represent a one-byte-wide bus and the dots are programmable sets of gates so that individual bytes may be selected and routed to desired byte positions. Themonitor is controlled by programme contuel unit 52, using associative memory instructions and supplementary storage instructions. An associative memory instruction specifies an associative, memory operation, a mask, two routing specifications (each of which gives the first-byte locations of source and sink fields and the number of bytes-Fig. 1 shows the addresses of the possible source byte locations by numbering on the lines), and two next-instruction addresses for conditional branching according to whether there is a match indicated from the most recent associative interrogation. A supplementary storage instruction specifies lengths of up to four fields to be processed in the accessed word and the respective operations to be performed on each. The instruction also specifies the first-byte location of the first field, the fields being contiguous, and the next instruction. Any one or none of the following operations can be performed on a field: (a) increment, (b) add clock to field, (c) put the lesser (or greater) of the clock reading and the old field value in the field, (d) OR the interface byte to the field. Basically, the associative memory holds data describing the state of the monitored computer, and the supplementary storage collects related statistics e.g. times, counts and condition codes. Uses of the monitor described in detail are: (a) determining how long the monitored computer spends in executing instructions from different areas of its store, by using the high-order portion of each instruction address to interrogate the associative memory, storing the portion in a free location if no match and incrementing a count in the corresponding location of the supplementary storage if match, (b) as (a) but the counts are broken down according to which channel is active by using the channel number as well as the address portion in each interrogation, (c) as (a) but also determining the number of transitions between different areas using the high-order portions of the current instruction address and of the preceding instruction address together in each interrogation, (d) determining which combinations of system states occur, how many times each occurs and how much time is spent in each state, by using the combination of states to interrogate at each instruction strobe or change of state, storing the combination if no match, and updating time and usage counts in the supplementary storage if match, (e) determining path lengths between branches by interrogating on branch operation codes and a " branch taken " bit, incrementing a running count if no match, and, if match, interrogating on the code, bit and count, a match on this causing a frequency field of the matched word to be incremented and the running count to be zeroed, (f) determining instruction mixes preceding branches by interrogating on operation codes, (g) determining how often sequences of events occurred, (h) determining the block structure of a programme, blocks being delineated by conditional branches, but blocks overlapping other blocks being segmented, the algorithm involving interrogations on " entry ", " exit " and " destination " instruction address fields.