Patent GB-1092290-A (GB)
Title: Information store
IPC: G11C7/02
Filed: 1965-06-23
Abstract: 1,092,290. Circuits employing bi-stable magnetic elements. INTERNATIONAL BUSIINESS MACHINES CORPORATION. June 23, 1965 [June 30, 1964], No. 26488/65. Heading H3B. In a two-core per bit store in which each magnetic storage element of a pair is electromagnetically coupled to a different branch of a sensing circuit and is associated with a driving circuit, the drive and sense circuits are so coupled that noise signals induced in the different branches of the sense circuit are of the same polarity whereas output signals induced in the different branches of the sense circuit during read out are of opposite polarity. The storage elements of Fig. 1 may be discrete spots or regions within a uniaxial anisotropic thin film. In order to store information a word pulse is passed down a word line 9, 10 . . . n parallel to the easy axis M coincident with a bit pulse on bit lines 5, 6. Since the bit pulse will be of one polarity in line 5 and of the opposite polarity in line 6 the two storage elements, e.g. 1, 2 will be magnetized along opposite directions along the easy axis representing the storage of one binary bit. If the polarities of the bit pulses from bit source 17 are reversed the second binary bit is stored in elements 1, 2. To read out, a word or read pulse is supplied to the appropriate word line 9, 10 &c., in the case of elements 1, 2 line 9, so that the magnetizations of elements 1, 2 are rotated to the right along the hard axis inducing first and second sense signals of opposite polarity in the sense lines 13, 14. These sense signals are passed to a differential transformer 21, Fig. 2 (not shown), the output from which is either positive or negative determined by whether a " 1 " or " 0 " is stored. Noise due to capacitive coupling between the word lines and sense lines is obviated since the spurious noise signals coupled into sense lines 13, 14 will be of a common polarity and hence will be cancelled by differential transformer 21. Inductive coupling between bit and sense lines is also eliminated. Since the bit pulses in bit lines 5, 6 are of opposite polarity the resultant field of the two opposing fields created by the pulses will tend to cancel so that the effect of the pulses on an adjacent pair of bit lines is minimized. However, noise signals induced in the half sense lines such as 13, 14 due to bit signal propagation in the bit lines 5, 6 are of opposite polarity and are added by the differential transformer and appear with the desired full sense signal. To eliminate this a second identical memory A is employed. Simultaneously with the half bit pulses from source 17 to lines 5 and 6 of array A an identical set of pulses are applied to lines 5<SP>1</SP>, 6<SP>1</SP> of array B. This induces spurious noise signals on lines 131, 141 identical to those on 13, 14 of array A which after addition in differential transformer 21<SP>1</SP> are present in full sense line 22<SP>1</SP>. Since the two signals are of the same polarity on lines 22, 22<SP>1</SP> they cancel out in 23. The system of Fig. 10 comprises a unipolar pulsing technique and uses " dispersion locking" " wherein remanence along the hard axis represents a " 0 " while remanence along the easy axis represents a " 1." Switching from the hard axis to the easy axis is accomplished by concurrent fields applied one along the easy axis and one along the hard axis, whereas switching from the easy to hard axis is accomplished by a hard axis field. To store a " 0 " in bit place 101, 102 a word pulse is applied to the word line 109 rotating the magnetization of elements 101, 102, along the hard axis to the right transverse to M. To store a " 1 " coincident bit and word pulses are applied to line 105 and hence 106, and word line 109, resulting in the magnetization of 101, 102 being in opposite directions. In order to read, a pulse is applied to word line 109. If a " 0 " is stored there is no induced signal in sense lines 113, 114, whereas for a " 1 " opposite polarity signals are induced in the sense lines. Capacitive coupled noise signals are eliminated as explained above and a second array B identical to A acts as a noise generator to eliminate inductively coupled signals.