baber/WOPTO huggingface dataset:
Patent JP-S60189268-A (JP)
Title: Semiconductor device
Inventor: INADA TSUGUO
IPC: H01L21/338
Filed: 1984-03-08
Abstract: PURPOSE:To obtain a heterojunction FET, which is never made to deteriorate its characteristics even though a high-temperature manufacturing process is performed by a method wherein a spacer layer consisting of two layers of an N type impurity diffusion blocking layer and a high-resistance aluminum arsenide gallium layer is made to interpose between a gallium arsenide channel layer and an N type aluminum arsenide gallium layer. CONSTITUTION:The semiconductor element is formed by forming successively each semiconductor layer in the following order on a semiinsulative GaAs substrate 1 by a molecular beam crystal growth method and so forth: a nondoped I-type GaAs layer 12, a nondoped I-type AlxGa1-xAs layer 13, a nondoped I-type GaAs layer 14, an N type AlxGa1-xAs layer 15 doped with silicon and an N type GaAs layer 16 doped with silicon. Impurities are introduced in the source and drain regions of the semiconductor substrate in high concentration in a depth to reach sufficiently into the I-type GaAs layer 12. Then, a source electrode 18 and a electrode 19 are arranged by a conventional technique, and moreover, a recess is formed and a gate electrode 20 is arranged in the recess.
Patent JP-H09238349-A (JP)
Title: Image transmitter
Inventor: ARIMA YUJI
IPC: H04N19/423
Filed: 1996-03-01
Abstract: PROBLEM TO BE SOLVED: To reduce the connection time of a communication line and to improve the transmission efficiency by using a moving image detection circuit to detect a moving image for each frame and sending multiplex data to the communication line only when a moving image is detected. SOLUTION: A motion detection circuit 103 compares moving image data 101 of this frame with moving image data of a preceding frame stored in a frame memory 114 to detect a motion with a small overlap error. Then a moving image detection circuit 115 detects it that a total sum of absolute values of moving positions for each frame exceeds a set value, image variable length data from a variable length data coding circuit 107 and audio variable length data from an audio coding circuit 198 are multiplexed by a multiplexer circuit 109 and the multiplexed data are sent to a communication line via a transmission circuit 110. Furthermore, when no motion is detected within a prescribed time, the moving image detection circuit 115 interrupts the transmission circuit 110. Thus, the connection time of the communication line is reduced and efficient transmission is attained.
Patent JP-H06234518-A (JP)
Title: Flaky barium sulfate and its production
Inventor: YAMAZAKI NOBUYUKI
IPC: C08K7/08
Filed: 1993-02-08
Abstract: PURPOSE:To industrially and efficiently obtain a flaky barium sulfate provided with a particle property suitable for applications such as to pigments and cosmetics. CONSTITUTION:The crystal particle of the barium sulfate has >=5 aspect ratio, >=2mum average particle diameter in planar shape and is free from any exceptional projecting or recessed part on the peripheral part of the planar face, and the flaky barium sulfate is provided with the property revealing streamline by streamline evaluating method when the crystal particle is made into a water based slurry. The flaky barium sulfate is produced by adding a barium salt solution to a sulfate solution simultaneously in such a concn. and vol. ratio that the concn. of a formed slurry of barium sulfate is made <=5wt.%, and the quantity of sulfate ion excessive to Ba ion in the system is set to 0.1-3g/l based on sulfate ion through the reaction process in this barium sulfate forming reaction by the barium salt solution and the sulfate solution.
Patent JP-S62206094-A (JP)
Inventor: AZUMA ASAO
IPC: D07B3/10
Filed: 1986-02-28
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H10225689-A (JP)
Title: Production of electrolytic sterilized water or aseptic water
Inventor: MATSUO YUKIAKI
IPC: C02F1/46
Filed: 1998-02-10
Abstract: PROBLEM TO BE SOLVED: To provide a method of producing treated water in which water can be sterilized or made aseptic and also be neutralized at a room temperature and left as it flows and further with simple equipment. SOLUTION: In an electrolyzer 1, a space between an anode 3 and a cathode 5 is divided into an anode chamber 10 and a cathode chamber 9 by a diaphragm 8. Adding liquid in which an ionizing inorganic material is dissolved is added to treating water, which is adjusted to prescribed electrical conductivity and as water to be treated, is injected into both the anode chamber and the cathode chamber to perform electrolysis, or is injected into the anode chamber only and water drained from the anode chamber is circulated to the cathode chamber to perform electrolysis. Then, acidic water and alkaline water are taken out from the anode chamber and the cathode chamber respectively, or neutral, aseptic water is taken out from the cathode chamber.
Patent JP-S57161030-A (JP)
Title: Improving method for watt loss of thin strip of amorphous magnetic alloy
Inventor: SATOU SHIYUN
IPC: C22F1/00
Filed: 1981-03-28
Abstract: PURPOSE:To reduce watt loss and to utilize a thin strip of an amorphous magnetic alloy to iron cores for power transformers, etc. by introducing linear strains to said strip, and annealing the strip thereby segmenting the magnetic domains of the strain introduced parts finely. CONSTITUTION:Linear strains are introduced into the direction of a thin strip of an amorphous magnetic alloy having an angle to its longitudinal direction by means of grooved rolls or the like. With the strain introduced side of the strip on an outer side, the strip is wound toroidally to form iron cores or the like, after which the iron cores are subjected to stress relief annealing in a magnetic field. By this annealing, the 180 deg. magnetic domains in the strain introduced parts are finely segmented, and the watt loss is improved. By this method, the thin strip of the amorphous magnetic alloy of extremely small watt loss is used for the rolled iron cores, etc. of power transformers.
Patent JP-S62202283-A (JP)
Title: Japanese language processing system
Inventor: IGARASHI JIICHI
IPC: G10L15/00
Filed: 1986-03-01
Abstract: PURPOSE:To save memory basing on the common operation of a program and the common operation of a word dictionary, etc., by using a morpheme analyzing function as an independent sub-routine, and using it even for the after- treatment of an OCR character recognition and a voice recognition besides a KANA (Japanese syllabary)/KANJI (Chinese character) conversion. CONSTITUTION:By a keyboard 10, one of seven modes of a KANA/KANJI conversion (keyboard input), a KANA/KANJI conversion (OCR input), a KANA/ KANJI conversion (voice input), a partial KANA/KANJI conversion (OCR input), a KANJI/KANA conversion (OCR input), an OCR character recognition (OCR input) and a voice recognition (voice input) is designated, and thereafter, a necessary parameter is set by the mode. The mode designated by a processing device 13 is decided, and the processing is executed for every mode based upon the program of a ROM 14, a KANA/KANJI conversion processing, an OCR character recognition processing, a voice recognition processing, a correcting processing and morpheme analyses 141-145. By executing the KANA/KANJI converting processing, etc., with the analysis 141 as the independent sub-routine, the common operation of the program and the common operation of the word dictionary, etc., can be executed.
Patent JP-S55139683-A (JP)
Title: Sense amplifying circuit for core memory
Inventor: HOSHINO KOUTAROU
IPC: G11C11/02
Filed: 1979-04-12
Abstract: PURPOSE:To simplify a circuit and to reduce power consumption by putting an sense amplifier into operation only for a core memory read by making use of the read current of a core memory for an electric power supply for the sense amplifier. CONSTITUTION:In reading a core memory, when switching transistors 14A and 14B are supplied with timing signals TMA and TMB, read current IR flows through core stack 13 and shunt resistance 17. Therefore, a voltage drop across resistance 17 develops an output voltage across the secondary side of pulse transformer 12. This voltage applies power voltage -Vcc across sense amplifier 1 via Zener diode 11 to put sense amplifier 1 into normal operation. In writing, since neither timing signal voltage TMA nor TMB is applied, current IR never flows through power voltage generating circuit 10. Therefore, amplifier 1 will not operate. Consequently, the circuit can be simplified and its power consumption can also be reduced.
Patent JP-S60190962-A (JP)
Inventor: MORINAKA YOSHIHIRO
IPC: A61H3/02
Filed: 1984-03-10
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S57160301-A (JP)
Title: Power conversion system of ac electric motor vehicle
Inventor: KINOSHITA SHIGENORI
IPC: H02M7/12
Filed: 1981-03-27
Abstract: PURPOSE:To reduce split secondary winding numbers, by combining a transformer having a plurality of secondary windings and a semiconductor converter, and by changing voltage of windings connected to unit converters which is phase controlled at high and low regions of converter output voltage. CONSTITUTION:An AC power source 1 is connected to a primary winding of a transformer 3 via a reactor 2. A secondary winding of the transformer 3 is divided in five. Each of windings 31, 32, 33, 34, 37 is connected to each of unit converters 41, 42, 43, 44, 47 constituting a thyristor converter 4. The converters 41, 42, 43, 44, 47 are connected in series. A load 6 is connected to them via a smoothing reactor 5 at a DC output. The secondary winding ratio of transformer 3 is set lower for the windings 31, 32 in voltage ratio and higher for the winding 37. The converters 41, 42, 43, 44, 47 are controlled sequently in phase in correspondence with composite output voltage of the converter 4. The converters 41, 42, 43, 44, 47 are controlled to constant margine angle at regenerative operation for inverse conversion. This reduces the split secondary winding numbers of transformer 3 and realizes more stable regenerative operation without increasing the maximum high-frequency current at the power supply.
Patent JP-S60189331-A (JP)
Title: Superwide band high balance signal discriminating circuit
Inventor: NIITANI TOSHIMITSU
IPC: H04B1/58
Filed: 1984-03-08
Abstract: PURPOSE:To execute a simultaneous call by a loudspeaker of an interphone, a high voice telephone, etc. by providing a voltage feedback circuit between the collector and the base, and fetching a receiving signal, in an output transistor of a parallel circuit having a transmitting and receiving line in a load. CONSTITUTION:A signal inputted to a common base of transistors (TR)TR1, TR2 connected in parallel is supplied to a transmitting and receiving line T1 through TRs TR3, TR4. The base of the TRTR3 is connected to a collector resistance R2, therefore, a shunted receiving signal is small, and accordingly, an output resistance R01 containing a negative feedback circuit is small. However, the base of the output TRTR4 is connected to an emitter resistance R3. As for this emitter inputting circuit, an input resistance of the inputting circuit is very small, therefore, the shunted receiving signal current is large. Therefore, as for a receiving signal circuit current I1 and I2, I1 is larger than I2, and a receiving signal can be fetched between neutralizing points A and B.
Patent JP-H11242731-A (JP)
Title: Device for detecting moving object and device for detecting number of people waiting for elevator
Inventor: NOMURA SATOSHI
IPC: G06M11/00
Filed: 1998-02-26
Abstract: PROBLEM TO BE SOLVED: To reduce the degradation of moving object detecting precision due to the difference of the light and shade of the background picture of a monitor area. SOLUTION: Picture data in which any moving object is absent in a monitor area in an image pickup device 1 are stored in a background picture memory 4. Also, picture data in which any moving object is present in the monitor area are stored in a present picture memory 3. Difference in the both picture is binarized by a difference binarizing means 5 with a threshold set by a threshold setting and adjusting means 6. The above means 6 adjusts the binarization threshold according to the pixel lightness of the background picture data.
Patent JP-H05239571-A (JP)
Title: Production of ti-al intermetallic compound
Inventor: KIN BOKUJIYUN
IPC: C22C1/04
Filed: 1992-03-02
Abstract: PURPOSE:To produce a Ti-Al intermetallic compound excellent in oxidation resistance at high temp. as well as in ductility at ordinary temp. by performing prescribed homogenizing treatment. CONSTITUTION:A Ti type material and an Al type material are mixed, deaerated, and subjected to vacuum sealing. The resulting sealed powder mixture is subjected to plastic deformation at a temp. not higher than the reaction synthesis temp. to undergo reaction sintering. Further, after the reaction synthesis, homogenizing heat treatment is done in a nonoxidizing atmosphere for >=0.2hr at a temp. in the range between 1170 and <1400 deg.C where Ti3Al is allowed to disappear. By this method, the Ti-Al intermetallic compound having a composition consisting of 40-50 atomic % and the balance essentially Ti can be produced.
Patent JP-H02228250-A (JP)
Title: High voltage generating circuit
Inventor: TSUZUKI HIROYOSHI
IPC: G03G15/00
Filed: 1989-02-28
Abstract: PURPOSE:To eliminate the possibility of damage of a high pressure generating circuit when the operation of a PWM control circuit is abnormal by a method wherein the high pressure generating circuit is made inert when the output of a driving and controlling circuit for the high pressure generating circuit is abnormal. CONSTITUTION:Two times of leading edge of a clock pulse CK are found and the output of a PWM output condition detecting circuit 16 is kept in 'LOW' level during each period (t1), (t2), in which the output of a PWM control circuit 12 is in 'HIGH' level. However, the leading edge of the clock pulse CK is more than three times and the output of the circuit becomes 'HIGH' level during a period (t3). Accordingly, a transistor 17 is put ON and the transistor 6 of a high pressure generating circuit A is retained in the condition of non- conduction whereby the high pressure generating circuit A may be brought into inert condition.
Patent JP-S62203122-A (JP)
Title: Plane display device
Inventor: INAO KATSUZO
IPC: G02F1/313
Filed: 1986-03-04
Abstract: PURPOSE:To obtain sharp picture elements, to increase a response speed, and to facilitate coloring by impressing a voltage between an upper and a lower electrode and leaking light from a light guide nearby the intersection part between the upper electrode and the light guide by an interference filter func tion. CONSTITUTION:Light is made incident on a specific light guide, e.g. (i) from alight source 24 which generates light with large brightness, e.g. laser light or LED light and guided to between the specific transparent electrode (j) and a lower electrode 16; and then an electric field is produced at the intersection part between the light guide (i) and upper transparent electrode (j) and the refractive indexes of division parts j1, j2, j3...jp, and j1 and j2, j2 and j3...jp-1 and jp vary alternately to constitute a multilayered film filter. A light wave with wavelength lambda is therefore reflected upward to obtain a picture element of a matrix i.j as one element of an image.
Patent JP-H01219473-A (JP)
Title: Refrigerator
Inventor: ARAKAWA TOSHIKAZU
IPC: F25D29/00
Filed: 1988-02-26
Abstract: PURPOSE:To permit the accurate control of temperature at all times regardless of the arrangement of foods, by a method wherein a second sensor is provided so as to be proximated to an inner box or a partitioning wall, opposed to the right or left side surface of the partitioning wall while a cold air leakage port is provided near the second sensor of a cold air discharging passage, formed on the partitioning wall. CONSTITUTION:A second sensor 22 is pinched by the rear end 25b of a rail 25, fixed to an inner box 1c, and the inner box 1c. The second sensor 22 is provided with a lead wire 22a and a connector 22b. A cold air leakage port 28 is provided at the left side of a cold air discharging passage 20 on a partitioning wall 9. A temperature in a second low-temperature chamber 6 has a given relation between the temperature of cold air, discharged out of the cold air leakage port 28, in such a constitution, therefore, this temperature is detected by the second sensor 22 to control a second damper opening and closing device 13 and keep the temperature in the second low-temperature chamber 6 at a predetermined temperature.
Patent JP-S61204659-A (JP)
Title: Developing device
Inventor: WATANABE MICHIOKI
IPC: G03G15/01
Filed: 1985-03-07
Abstract: PURPOSE:To prevent a surface potential from dropping and to obtain images of good quality by providing a developing bias cutting means and then cutting a developing bias associatively with the removal of the magnetic brush of the developer of a developing device which is not used for development. CONSTITUTION:When the 2nd developing device is selected and a developer magnetic brush 1352 is formed on the surface of the 2nd developing roller 1312, the 1st contact 190 is broken and the 2nd contact 191 is made; and the developing bias is applied to only the 2nd developing roller 1312. Further, when the 1st developing device is selected and a developer magnetic brush 1351 is formed on the surface of the 1st developing roller 1311, the 1st contact 190 is made and the 2nd contact 191 is broken; and the developing bias is applied to only the 1st developing roller 1311. Thus, while one selected developing device is in operation, the developing bias to the other developing device is cut to prevent a drop in surface potential due to the contacting the unused developing device with a photosensitive drum 13.
Patent JP-H06258056-A (JP)
Title: Profile recognition system for semiconductor wafer
Inventor: NISHIDA TETSURO
IPC: H01L21/66
Filed: 1993-03-05
Abstract: PURPOSE:To allow stabilized and accurate recognition of profile by providing a filter for polarizing the illuminating light and shading the illuminating light reflected directly to the imaging unit side. CONSTITUTION:An illuminator is provided with a first polarization filter 7 whereas an imaging unit 3 is provided with a second polarization filter 8 and the polarizing direction of the filter 7 is set in parallel with the paper plane. Illuminating light P is reflected by a circuit pattern formed on a semiconductor wafer 100 toward the imaging unit 3 and the polarizing direction after reflection is set at a specific angle depending on the surface condition of the water 100. Consequently, the filter 8 having the polarizing direction perpendicular to the specific angle substantially shades the light P. On the other hand, illuminating light R reflected by an adhesive tape 102 15 reflected randomly and half of the randomly reflected light is shaded by the filter 8 while the remainder transmits through the filter 8. Consequently, the image of the tape 102 is brighter than the wafer 100. Since the light reflected on the wafer 100 toward the unit 3 is substantially shaded, the image does not become brighter even if the reflectance of the wafer 100 varies. Consequently, high contrast is ensured constantly between both images thus allowing accurate recognition of profile.
Patent JP-H04220157-A (JP)
Title: Controlling device for pouring molten material into mold and its method
Inventor: OREGU FUISHIYUMAN
IPC: B22D5/00
Filed: 1991-02-19
Abstract: PURPOSE: To provide a pouring method for molten metal into a sand mold capable of calculating the behavior of the molten metal from a sprue cap to a gate system, 'learning' the behavior of the sprue cap 12 and gate system, calculating the molten metal flow in the mold and changing a pouring condition while taking the amt. of the molten metal flowing from a tundish into the sprue cap during pouring and an apparatus therefor. CONSTITUTION: The molten metal 20 is poured from the tundish 30 into the sprue cap 12 of the sand mold 20 in a controlled state by a stopper 40. A camera is so arranged as to monitor the molten metal 20a in the upper opening of the sprue cap 12 and in the sprue cap 12 and the molten metal 20b emerging from an orifice 35.
Patent JP-S62205062-A (JP)
Title: Imidazole derivative
Inventor: OGAWA MASAKI
IPC: A61P31/04
Filed: 1986-03-03
Abstract: NEW MATERIAL:The imidazole derivative of formula I (R1 is H, halogen or acyl; R2 is H, alkyl or alkenyl) or its acid addition salt. EXAMPLE:1-[1-(2-Buthyloxynaphthyl)vinyl]imidazole. USE:Pharmaceuticals, agricultural chemicals, preservatives, etc. It has excellent antimicrobial activity against bacteria, yeasts and phytopathogens. PREPARATION:A compound of formula I wherein R2 is H can be produced by reacting the naphthol derivative of formula II with N,N'-thionyldiimidazole of formula III in a solvent at room temperature or ice cooling or under heating. The obtained compound can be converted to another compound of formula I wherein R'2 is R2 by reacting with an alkylation or alkenylation agent of formula R'2X (R'2 is alkyl or alkenyl; X is halogen, benzenesulfonyloxy, p- toluenesulfoxy, etc.) in a solvent in the presence of an alkali at room temperature or under heating.
Patent JP-S55138132-A (JP)
Title: Signal processor
Inventor: SHIGAKI SEIICHIROU
IPC: G06F13/12
Filed: 1979-04-13
Abstract: PURPOSE: To bring excellent signal processing to effect by letting a digital signal processor, using a stored program, operate at its original processing speed without reference to whether a control data write instruction exists to send control data to a processing circuit according to the existence of the write instruction.  
     CONSTITUTION: Memory 8, when write command signal w p  is not supplied to terminal W/R, outputs control data stored at read address (ar) from address output terminal AO of processing circuit 9 to terminal CI of circuit 9. On the other hand, when signal w p  is supplied to terminal W/R, control data (dw) from terminal 2 is written at an address assigned by address (ar) while data (dw) are output, and circuit 9 processes input signal Si from terminal SIP on the basis of data (dw) and outputs the processing result data to terminal 5. Consequently, circuit 9 operates at its original processing speed without reference to whether signal w p  control data write instruction (w) exists and also inputs control data (dw) to the processing circuit according to the existence of write insturction (w), performing excellent signal processing. 
     COPYRIGHT: (C)1980,JPO&Japio
Patent JP-S58162067-A (JP)
Title: Manufacture of insulated gate field effect transistor
Inventor: SUZUKI TOSHIYUKI
IPC: H01L29/78
Filed: 1982-03-23
Abstract: PURPOSE:To obtain an insulated gate field effect transistor having no negative resistance, excellent breakdown resistance and less irregular ON resistance. CONSTITUTION:A drain mask region 13 formed to surround a drain region 2 and a gate electrode 6 are simultaneously formed in a pattern, and a source region 3 and a buried earth layer 10 are formed with the secound mask material 16 and the electrode 6 as masks. The mutual position relationship among the end of the gate side of the source region 3, the end of the gates side of the buried earth layer 11, the drain region 2 and the offset gate region 4 can be unitarily determined by the gate electrode 6 formed in a pattern simultaneously and the drain mask region 13. Accordingly, this buried earth layer 10 can completely cover the directly under the source region 3, and an offset gate IGFET having no negative resistance and excellent breakdown resistance can be obtained. The gate channel length and the irregularity in the offset gate length can depend only upon the machining accuracy at the patterning time of the gate electrode and the drain mask without addition of matching error, thereby reducing the irregularity of the ON resistance.