Patent GB-1116869-A (GB)
Title: Digital electric memory addressing apparatus
Inventor: ASHBAUGH JAMES P
IPC: G06F12/06
Filed: 1966-09-20
Abstract: 1,116,869. Memory addressing apparatus. SPERRY RAND CORPORATION. 20 Sept., 1966 [5 Oct., 1965], No. 41862/66. Headings G4A and G4C. Digital electric memory addressing control apparatus for use with a memory having a plurality of independently addressable storage registers for storing data and instruction words and having an instruction storage register with at least a portion thereof adapted for storing a base relative memory address to be accessed in the memory is characterized by a register for storing at least two selectively alterable base relative address constants. and a memory area divider pointer address constant, a first adder for forming the sum of one of the base relative address constants and the programmed base relative address constant, a second adder for forming the sum of the second base relative address constant and the programmed base relative address, and a comparator coupled to the register for evaluating the base relative address pointer constant so as to enable the selection of one of the sums as an alternate absolute memory address to be accessed in the memory. In the embodiment described, each independently addressable memory section is divided into a plurality of blocks (e.g. 64 or 100 8 ), each block having 512 (1000 8 ) locations (000 8 -777 8 ). Any block containing data from one programme cannot contain data from another programme. Thus, in searching for an empty block only the block number need be specified and the base relative address need not include the three least significant digits of each address. The apparatus can use two independently addressable sections, one containing instructions (I), the other data (D) so that the next instruction can be accessed while the data is being operated on so as to shorten the time taken to complete the programme. An Internal Function Register 40 (Fig. 7) contains a BI register holding the base relative address for I words, a BD register holding the base relative address for D words and a BS register holding the memory address divider constant. An instruction word is loaded into the instruction register, the address portion u of which comprises a part uh of nine bits defining the address of the location within the block as three octal digits and a part uh of seven bits defining the block. The part uh is added simultaneously in FULL ADDERS 1 and 2 to BI and BD respectively. The lower significant digits ul are appended to the number and if specified by the instruction the contents of an index register B are simultaneously added to the number there formed in FULL ADDERS 3 and 4 respectively and the original number u is added to the contents of the index register B in FULL ADDER 5. The output of FULL ADDER 5 is compared with the value BS and enables the I gates if BS is greater than or equal to the contents of ADDER 5 or the D gates otherwise. The resulting address is checked to make sure that data is not being written into an area already containing data and then applied to the translation unit, which may be a diode matrix, to enable the appropriate memory location. Memory lock-out units.-When data and instructions are written into the memory they are generally placed at opposite ends of the memory locations. For instance, a programme having 10,000 8  I words and 5000, D words will fill blocks 354-364 8  and 014-020 8  and in a storage limits register 140 these limits for the I and D words will be entered. The next programme may have 30,000 8  I words and 20,000 8  D words. These can go in blocks 021-051 8  and 334-353 8  respectively, the larger number of words filling the portion of the memory storing the least number of words. The storage limits register is adjusted accordingly. B.S. register.-When words are entered in the memory a base address is fixed and the number of blocks to be filled is determined for the instructions. The number of blocks to be filled is the number in the B.I. Register and is subtracted from the one less than the address of the first block to receive data, and the resulting number is the base address for the data. Thus, if the relative address #BS the address refers to an instruction, if > BS it refers to data. Relocation of programme.-It is possible to relocate programme words merely by shifting data or instructions a particular number of blocks and adjusting the base relative address constants to refer to the new location. It is possible that if an interrupt occurs the programme in operation before the interrupt may be relocated before it can be continued, so the circuit shown in Fig. 11 is used to store the relative address of the next instruction to be performed. The compare circuit sets or resets a transistor flip-flop 240 depending on its output. The flip-flop enables appropriate gates to cause the BI, or BD values to be subtracted from the actual address obtained by the circuit shown in Fig. 7 and stores the resulting relative programme address. It is stated that all operations are performed in the parallel mode, that the computer can perform add, subtract, divide and multiply operations in fixed or floating point numbers, that shift operations can be performed and that normally consecutive instructions are obtained by adding one to the address of the previous instruction. Thr memory comprises high-speed ferrite cores.