Patent GB-1061781-A (GB)
Title: Analogue dividing and multiplying apparatus
Inventor: BROWNING SHANE CAIRNES
IPC: G06G7/161
Filed: 1962-07-10
Abstract: 1,061,781. Electro-analogue calculating. ENGLISH ELECTRIC CO. Ltd. Oct. 10, 1963 [July 10, 1962], No. 26481/62. Heading G4G. In an analogue dividing apparatus a controlled voltage is varied between first and second levels at a rate dependent upon a signal representing a divisor, while the difference between the first and second levels is varied in dependence upon a signal, representing a dividend. The variation of the controlled voltage is repeatedly initiated in response to each of a train of trigger signals. The apparatus produces a pulse train of constant repetition rate and amplitude, the durations of successive pulses corresponding to the time taken for the controlled voltage to change between the first and second levels. The average value of these pulses is therfore dependent upon the ratio of the dividend and divisor. In a circuit in accordance with the invention a dividend signal X is applied to an input 16, while a divisor signal Z is applied at an input 17. The circuit also includes provision for multiplying the quotient by a quantity Y, applied to an input 20. Trigger signals at a constant repetition rate are applied to an input 18. With the apparatus in a quiescent state at the end of each operating cycle, the anode of the pentode 10 carries no current, the current through the valve being taken by the screen 10d. The anode 10a will be at the potential of the X input, while the screen is at the potential of a steady bias applied to the input 18. The application of a trigger pulse to the input 18 causes the voltage on the suppressor grid 10e to rise momentarily so diverting the valve current to the anode. The fall in anode voltage reverse biases the diode 22 and is fed via the condenser 23 to the grid 10b, thus giving a uniform rate of fall of anode potential, while the screen grid immediately rises to an upper value fixed by the supply at 14. The anode potential fall continues until the valve bottoms, at which point the anode current is transferred back to the screen grid, so that the screen grid potential falls again, while the anode potential returns to the X input level. The time during which the anode potential is falling is directly proportional to X (the voltage from which it starts) and inversely proportional to Z, since the divisor potential Z is applied to the control grid 10b of the pentode and the rate of fall of the anode potential will be proportional to Z. Thus the width of the voltage pulses appearing at the screen grid is proportional to X/Z. The cathode follower 11 enables variations in the pentode bottoming voltage with the input voltage at 17 to be compensated by feeding this voltage to the suppressor grid 10e. The output pulse train from the screen 10d of the pentode dividing stage is fed via the cathode follower 12, whose cathode is normally held at zero volts under quiescent conditions, to the triode 13, where it is amplitude modulated at the input by a signal Y. The pulse train produced at the cathode of the triode 13 thus has an average value proportional to X/Z.Y. A D.C. output signal proportional to this product is obtained through the smoothing circuit 44. A potentiometer 43 enables zero adjustment to be effected.