baber/WOPTO huggingface dataset:
Patent TW-333682-B (TW)
Title: The method for producing multi-crown capacitor of DRAM memory cell
Inventor: WU SHYE-LIN
IPC: H01L21/70
Filed: 1997-05-09
Granted: 1998-06-11
Abstract: A method for producing IC capacitor, it includes: Form 1st dielectric layer on semiconductor substrate. Form contact hole inside 1st dielectric. Form 1st conductive on 1st dielectric layer to fill back the contact hole. Form 2nd dielectric on 1st conductive layer. Form Si layer on 2nd dielectric layer. Etch Si layer to separate Si layer to form HSG-Si. Use HSG-Si as etching mask to etch 2nd dielectric to form pillars dielectric. Use pillars dielectric as etching mask to etch 1st conductive layer, and during the etching step, the HSG-Si will be removed. Form 2nd conductive layer on top of 1st conductive layer and pillars dielectric. Use anisotropically etching to etch 2nd conductive layer, to form conductive sidewall spacers at sidewall of pillar dielectric. Remove pillars dielectric to form multi-crown structure. Form 3rd dielectric on multi-crown structure. Form 3rd conductive layer on 3rd dielectric layer.
Patent TW-505525-B (TW)
Title: Pharmaceutical compositions based on diclofenac
Inventor: REINER ALBERTO
IPC: A61P19/02
Filed: 1997-05-16
Granted: 2002-10-11
Abstract: New pharmaceutical compositions for oral use containing diclofenac together with alkali metal carbonates and bicarbonates and particular flavouring substances are described. These compositions are entirely palatable and free from any unpleasant taste or other side effects.
Patent TW-366366-B (TW)
Title: An alloy, in particular for use in the manufacture of frames for eyeglasses, jewelry and the like
Inventor: FACKERT JUERGEN
IPC: A44C27/00
Filed: 1997-06-11
Granted: 1999-08-11
Abstract: A high-temperature nickel-free alloy, in particular for spectacle frames, jewelry, etc. with the following composition in percentages by weight: Zn 3.0-7.0%, Mn 8.0-13.0%, Fe 0.5-3.5%, Al 4.5-8.0%, Cu the remainder.
Patent TW-349994-B (TW)
Title: Surface activator composition
Inventor: ISHII YASUO
IPC: C11D1/16
Filed: 1997-11-25
Granted: 1999-01-11
Abstract: A sort of surface activator composition, having the following formula (1) compound and water showing an average molecule of under 1200, in total with respect of water and compound given in (1), at a mixture ratio of (1) in over 5% and less than 50% by weight, RO-(EO)x-(PO)y-(EO)x^-H (1) where R stands straight chain or branched alkyl or olefin in 12-15 of carbon numbers, EO for epoxy ethanol, PO for epoxy propanol, x,x^ average adding mol of over 1 on the epoxy ethanol, y for adding mol of 0.5-6 on the epoxy poropanol, and (EO)x, (PO)y, (EO)x^ for bonding in this order.
Patent TW-357505-B (TW)
Title: Method and apparatus for bandwidth reuse in a communication network
Inventor: LU XIAOLIN
IPC: H04J1/00
Filed: 1997-12-01
Granted: 1999-05-01
Abstract: A method and apparatus for bandwidth reuse in a communication network, including the following steps: transmission in the first bandwidth the first downward transmission data; transmission in the second bandwidth the second downward transmission data; transmission of the data being transmitted in the first downward and in the first bandwidth to a first destination; transmission of the data being transmitted in the second downward and in the second bandwidth to a second destination; and in a bandwidth section for downward transmission yet not the first bandwidth section, for transmission the first upward transmission data from the first destination.
Patent TW-373367-B (TW)
Title: Surface acoustic wave filter
Inventor: KADOTA MICHIO
IPC: H01L41/08
Filed: 1998-01-13
Granted: 1999-11-01
Abstract: A transversal-coupled resonator type surface acoustic wave filter includes a piezoelectric substrate and first and second interdigital transducers. The piezoelectric substrate has a pair of substrate edges which are substantially parallel to each other and reflect a shear horizontal type surface wave excited and propagated on a surface of the piezoelectric substrate in a direction perpendicular to the substrate edges. The first and second interdigital transducers have the same resonance characteristics and are provided on the piezoelectric substrate. Each of the first and second interdigital transducers includes a pair of outermost electrode fingers which are arranged to be flush with the substrate edges of the piezoelectric substrate, respectively and a pair of adjacent electrode fingers which are adjacent to the pair of the outermost electrode fingers, respectively. A distance D' from one of the substrate edges of the piezoelectric substrate to a center of the corresponding adjacent electrode fingers satisfies the following inequalities: lambda/2 < D' ≤ (lambda/2) + (5 lambda/16), where lambda is a wavelength of the shear horizontal type surface acoustic wave excited on the piezoelectric substrate.
Patent TW-392334-B (TW)
Title: Low power, high accuracy clock circuit and method for integrated circuits
Inventor: GRUNDVIG JEFFREY PAUL
IPC: G06F1/04
Filed: 1998-02-09
Granted: 2000-06-01
Abstract: A clock circuit for providing an integrated circuit with a high accuracy, crystal oscillator clock which interfaces to an ""off-chip"" crystal to provide a high accuracy clock signal while an internal, low power oscillator provides a low power clock source. Either clock may be selected to drive a programmable processor under program control. When high accuracy and stability are required, the crystal oscillator may be chosen as the processor clock, and when lower power is desired, the low power oscillator may be chosen as the processor clock while the high accuracy clock is disabled. The high accuracy oscillator is used to clock a first timer circuit, while the low power oscillator is used to clock a second timer circuit. The second timer circuit output, in turn, is synchronized to the processor clock so that the programmable processor can utilize the second timer circuit even when the processor clock is asynchronous to the second timer circuit. When the high accuracy oscillator has been selected as the timing source to the programmable processor and to the first timer circuit, and the low power oscillator is clocking the second timer circuit, the programmable processor under program control can effectively measure the frequency of the ""on-chip"" low power oscillator in terms of the frequency of the high accuracy clock. Accordingly, when the high accuracy clock is disabled, the programmable processor can use the low power oscillator more accurately.
Patent TW-405220-B (TW)
Title: Soi/bulk hybrid substrate and method of forming the same
Inventor: JASO MARK A
IPC: H01L21/762
Filed: 1998-04-21
Granted: 2000-09-11
Abstract: A semiconductor device having areas that are semiconductor on insulator (""SOI"") and areas that are bulk, single crystalline semiconductive areas provided in which conductive spacers may be formed to electrically connect the SOI areas to ground in order to overcome floating body effects that can occur with SOI. Additionally, insulative spacers may be formed on the surface of the conductive spacers to electrically isolate the SOI regions from the bulk regions. A novel method for making both of these products is provided in which the epitaxially grown, single crystalline bulk regions need not beselectively grown, because a sacrincial polishing layer is deposited, is also provided.
Patent TW-368607-B (TW)
Title: Look-up table apparatus for radar pulse Doppler filter set
Inventor: Cai ming-fa
IPC: G01S7/00
Filed: 1998-05-15
Granted: 1999-09-01
Abstract: For an advanced radar system, because the detecting distance becomes further and target speed become faster, in order to meet the system specification requirement, the apparatus employs a lot of signal processing method to enhance the performance of radar. Those operations are all highly sophisticated and with large data amount and need real time processing capability. So, the invention designed a parallel processing structure for pulse Doppler filter set of special look-up table apparatus and to provide serial parallel operation and recursive operation for the two-dimensional operation of pulse compression and limited pulse responsive filter. All the structure is simple and with regularity that the apparatus can be produced as ASIC which can greatly save the number of logical gates, reduce the hardware volume and the cost.
Patent TW-370477-B (TW)
Title: Immersion spout for a continuous slab-casting mould
Inventor: SCHEMEIT HANS JURGEN
IPC: B22D11/10
Filed: 1998-05-26
Granted: 1999-09-21
Abstract: The invention relates to an immersion spout of a metallurgical vessel which is connected upstream of a continuous-casting mould, which immersion spout is designed to be a one-pieced structural member and comprises, in the outlet region, a slot-shaped pouring opening, the length of which is a multiple of the width thereof. In this regard, the immersion spout (21) has a cylindrical shape comprising a circular R, oval (r and c) or bone-shaped (p and q) cross-sectional form, and the slot-shaped pouring opening (22) is designed to be a through slot (23) which extends in the bottom (28) and the side wall (29) of the cylindrical part of the immersion spout (21). The invention also relates to a method for manufacturing an immersion spout of this kind.
Patent TW-494125-B (TW)
Title: Preparation of fluorinated polymers
Inventor: PARKER HSING-YEH
IPC: C08F220/24
Filed: 1998-06-22
Granted: 2002-07-11
Abstract: Disclosed is a method for preparing fluorinated emulsion polymers that reduces or eliminates the need for fluorinated surfactants comprising the steps of: (a) providing a reaction mixture comprising water, surfactant, monomer mixture comprising at least one fluorinated monomer, at least one non-fluorinated monomer having high water solubility, and optionally at least one non-fluorinated monomer having low water solubility, macromolecular organic compound having a hydrophobic cavity; and (b) polymerizing said monomer mixture.
Patent TW-436704-B (TW)
Title: Multi-bit current-mode communication system
Inventor: KIRSCH HOWARD C
IPC: G06F13/38
Filed: 1998-06-23
Granted: 2001-05-28
Abstract: The present invention relates to a current-mode data communication system having a transmission device that can transmit two digital data bits simultaneously. The two digital data bits are converted into a current-mode signal that includes the first and the second positive currents and the first and the second negative currents and is transmitted through a 2-bit current-mode data bus. The current-mode data communication system also includes a receiver that is connected with the 2-bit current-mode data bus to receive the current-mode signal and can convert the current-mode signal into a non-corrected signal representing the two original digital data bits. The output of the receiver is connected with the data correcting circuit to convert the non-corrected signal back to the two digital data bits originally transmitted and represented by the signal.
Patent TW-376354-B (TW)
Title: Alignment method for chemical mechanical polishing
Inventor: LIAO WEN-SHIANG
IPC: H01L21/304
Filed: 1998-07-13
Granted: 1999-12-11
Abstract: The method comprises uses a zero-layer photomask to form an original alignment mark pattern on a wafer, depositing a plurality of dielectric layers on the wafer, performing a chemical mechanical polishing to planarize the topmost dielectric layer, coating a photoresist and using the zero-layer photomask again to define on the planarized dielectric layer by photolithography, etching the photoresist defined by the zero-layer photomask to make an etching mask and etching the dielectric layer to a depth identical to the original step height difference, removing the photoresist after completion of the etching, defining a second photoresist on the dielectric layer, using the photoresist as the etching mask and clearing out the dielectric material on the original alignment mark by etching the dielectric layer using an etching process thereby reexposing the duplicated original alignment mark. The etching process of the second photoresist can also be used as an etching mask to form a connection hole or a plug hole on the dielectric layer of a multi-interconnect in devices.
Patent TW-580500-B (TW)
Title: Nucleoside compounds, and pharmaceutical composition comprising same for use in the prophylaxis or treatment of viral infections
Inventor: ZHOU XIAO-XIONG
IPC: A61K31/00
Filed: 1998-08-14
Granted: 2004-03-21
Abstract: Compounds of the formula I or corresonding monohydroxyl nucleoside derivatives wherein: R1 is hydrogen, hydroxy, amino or carboxy; optionally having esterified/amide bonded thereon; a C4-C22 saturated or unsaturated, optionally substituted fatty acid or alcohol, or an aliphatic L-amino acid; R2 is the residue of an aliphatic L-amino acid; L1 is a trifunctional linker group; L2 is absent or a difunctional linker group; and pharmaceutically acceptable salts thereof have favourable pharmacological properties and are antivirally active.
Patent TW-406521-B (TW)
Title: High conductance plasma containment structure
Inventor: WALKO II JOSEPH PHILIP
IPC: H05H1/16
Filed: 1998-09-22
Granted: 2000-09-21
Abstract: Plasma containment is achieved within a region by a containment plate while gas is allowed to flow through this region by openings in the plate. The openings in the plate are larger in two of the cross-sectional dimensions parallel to the plate surface than the thickness of the dark space or plasma sheath. This plasma containment plate allows high conductance for conditions including those of long molecular mean free path and thick material deposits on the interior chamber of the plasma reactor.
Patent TW-406403-B (TW)
Title: Method for manufacturing the bottom electrode of a cylindrical-type capacitor
Inventor: LIN SZ-MIN
IPC: H01L27/108
Filed: 1998-10-14
Granted: 2000-09-21
Abstract: A method for manufacturing the bottom electrode of a cylindrical-type capacitor is disclosed, which comprises the steps of providing a semiconductor substrate; forming the insulated layer and the contact opening on the substrate; forming the electric-conductive layer on the contact opening and the insulated layer; proceeding the photolithography process; defining and forming the photo-resist layer on the electric-conductive layer; forming a silicide photo-resist layer spacer on the electric-conductive layer and the photo-resist layer as the mask for next process; using the spacer as the mask to etch the electric-conductive layer and the photo-resist layer; using the length of a time period to control the depth of etching; and forming the bottom electrode a cylindrical-type capacitor on the insulated layer.
Patent TW-407291-B (TW)
Title: The simulation of the post-exposure bake process of the chemically amplified resist
Inventor: LI TZUNG-LUNG
IPC: H01L21/00
Filed: 1998-11-06
Granted: 2000-10-01
Abstract: A method of the simulated post-exposure bake process of the chemically amplified resists, wherein said chemically amplified resist has the photoacids and the protected unit cell, and said method at least comprises the following steps: firstly, input the initial parameter of the bake process after the exposure, to display the temperature-time process of the bake process after said exposure. Next, input reaction constant and diffusion coefficient to display said chemically amplified resists, wherein said reaction constant is a function of temperature, and said diffusion coefficient is the function of the protected unit cell concentration. Then, calculate the protected unit cell concentration of said chemically amplified resists, wherein said calculation procedure uses an implicit scheme; and, calculate the photoacids material concentration of said chemically amplified resists, wherein said calculation procedure uses the above-mentioned implicit scheme and said diffusion coefficient.
Patent TW-455622-B (TW)
Title: Thermosetting resin composition
Inventor: SAITO TERUO
IPC: C09D163/00
Filed: 1998-12-08
Granted: 2001-09-21
Abstract: A thermosetting resin composition which is useful for the formation of a solder resist or an insulating interlayer in a multilayer printed circuit board is disclosed. This composition contains (A) a cyanate ester compound possessed of not less than two cyanate groups in its molecule, (B) an epoxy compound possessed of not less than two epoxy groups in its molecule, (C) a metal salt of an aliphatic carboxylic acid, and (D) an organic solvent. The metal salt of an aliphatic carboxylic acid functions as a catalyst for the reaction of the cyanate ester compound with the epoxy compound.
Patent TW-415079-B (TW)
Title: Circuit for standby current reduction
Inventor: SON JOO-HIUK
IPC: H03K19/00
Filed: 1999-01-15
Granted: 2000-12-11
Abstract: Circuit for reducing a standby current, is disclosed, including a PMOS transistor connected to a power supply voltage terminal, an NMOS transistor connected to a ground voltage terminal, and a switching device between the PMOS transistor and the NMOS transistor for cutting off a leakage current flowing to the NMOS transistor through the PMOS transistor, whereby minimizing a leakage current and shortening a time period for going from a standby state to an active state.
Patent TW-383255-B (TW)
Title: In-tube non-axis boring and polishing method and apparatus thereof
Inventor: CHEN CHING-HE
IPC: B24B5/40
Filed: 1999-02-25
Granted: 2000-03-01
Abstract: The invention provides a kind of in-tube non-axis boring and polishing method and apparatus thereof especially as a method for making the same direction of boring polishing tracks and fluid flow direction. The method is to mount the pipefitting in axial holes of a plurality of magnetic-excited conduit in advance and install a boring-polishing shuttle in the pipefitting. Therefore, when the conductive coils around each magnetic-excited conduit are conducted sequentially, it can generate magnetic field and attract the boring-polishing shuttle and guide the shuttle into the generated magnetic field range of each magnetic-excited conduit so that the boring-polishing shuttle can move in a straight line in the conduit and contact the inner wall of conduit along axial direction with the boring-polishing surface. Therefore, the invention can generate boring-polishing tracks in the same direction with the fluid flow and without obstructing the fluid flow for uniform boring and polishing processes to get an uniform and shining wall surface and increase the efficiency.
Patent TW-487714-B (TW)
Title: Process for coating substrates having polar surfaces with polyurethane latexes
Inventor: TABOR RICK L
IPC: C08G18/00
Filed: 1999-03-31
Granted: 2002-05-21
Abstract: Claimed is a substrate having a polar surface and, adherent thereto, a polyurethane polymer which was applied as a latex. The latexes of the present invention are chain extended in water with aminoethyl ethanolamine and are prepared and applied in the substantial absence of organic solvents. The prepolymers used to prepare the latexes are substantially free ionic groups on the polymer backbone. The process for preparing the latex coated substrate of present invention comprising: (A) the polyurethane latex is prepared from a polyurethane prepolymer which has a polymer backbone substantially free of ionic groups and is prepared from a prepolymer formulation which includes polyols having an average ethylene oxide content of less than 80 weight percent, (B) the prepolymer is chain extended with an AEEA chain extender, and (C) the prepolymer and latex are prepared in the substantial absence of an organic solvent.
Patent TW-429371-B (TW)
Title: Magnetic recording medium and reproducing method for information stored in magnetic recording medium
Inventor: SUZUKI MASAYASU
IPC: B42D15/10
Filed: 1999-06-10
Granted: 2001-04-11
Abstract: There are provided a magnetic recording medium and reproducing method for information stored in magnetic recording medium, capable of easily imparting non-addable nor erasurable forgery preventive information and is capable of preventing the unauthorized use by duplication or fraudulent alteration of magnetic information. A magnetic recording medium 10 is adopted, in which a first magnetic layer 2 consisting of first magnetic powder having a magnetic line of force of 250 to 4000 ersteds and a second magnetic layer 3 consisting of second magnetic powder having a magnetic line of force smaller than ersteds are at least formed on a base 1 constituted of a nonmagnetic material and in which plural protruding parts 6 each having two apexes 5, 5 constituted by accumulating second magnetic powder are formed on one surface 4 of the second magnetic layer 3 along the reading direction of the magnetic recording.
Patent TW-570908-B (TW)
Title: Flow field plate used in the form of a fuel cell
Inventor: MERCURI ROBERT ANGELO
IPC: H01M8/02
Filed: 1999-07-08
Granted: 2004-01-11
Abstract: Flexible graphite sheet having embedded ceramic fibers extending from its surfaces into the sheet to increase the permeability of the sheet to resin which is grooved by mechanical deformation into a shape useful as a flow field plate in fuel cells, having a thin sheet of flexible graphite affixed to the grooved sheet to provide support therefor.
Patent TW-401498-B (TW)
Title: Resistance valve
Inventor: IMADA YOSHIO
IPC: F16N25/00
Filed: 1999-07-09
Granted: 2000-08-11
Abstract: The present invention provides a resistance valve which uses the unidirectional pressure to distribute correctly the fluid lubricant in constant volume or with the specific proportion to the parts of the machine where the lubrication is needed. The structure comprises forming female thread 11 on inner peripheryl of the main portion in the holes of path component and forming male thread 12, matching up with the said female thread, on outer periphery of the main portion of resistance level 2; cutting off the thread peak of either one of said female thread or male thread according to specific height and using the cut portion of the thread peak as fluid path 3.
Patent TW-418535-B (TW)
Title: MOSFET with gate side air-spacer
Inventor: LIN CHUNG-RUNG
IPC: H01L29/772
Filed: 1999-07-09
Granted: 2001-01-11
Abstract: The present invention comprises forming a silicon nitride layer and an oxide layer on a substrate; forming a silicon nitride sidewall spacer; forming an ion doped region by implanting ions with an ion implantation process; forming a gate oxide layer on the exposed substrate; depositing a doped polysilicon layer on the gate oxide layer and the silicon oxide layer; removing the polysilicon layer to the surface of the silicon oxide layer; removing the silicon oxide layer, the silicon nitride layer and the silicon nitride sidewall spacer; forming a lightly doped ion doped region by an ion implantation process; forming a sidewall spacer to form a gate side air-spacer between the gate and the sidewall spacer; using the sidewall spacer and the gate structure as the mask to perform an ion implantation to form a drain and a source; and forming a self-aligned silicide.