baber/WOPTO huggingface dataset:
Patent TW-510786-B (TW)
Title: Wet tissue warmer and tissue lifting plate
Inventor: NAKAMURA KEIICHI
IPC: A47K10/42
Filed: 2000-12-05
Granted: 2002-11-21
Abstract: A wet tissue warmer includes: a case (2) having an open end (2a), a lid (3) removably put on the case (2) so as to cover the open end (2a) of the case (2) and internally provided with a heater, and a lifting plate (9) placed in the case (2) and biased upward. When the lid (3) is closed, a wet tissue package (A) mounted on the lifting plate (9) is kept in contact with the lid (3) to heat the wet tissue package (A). Lifting plate locking devices (11) are disposed in the case (2). The lifting plate (9) is locked at the present position by the lifting plate locking devices (11) when the lid (3) is opened.
Patent TW-503574-B (TW)
Title: Packaging structure of image sensor and its packaging method of the same
Inventor: PENG GUO-FENG
IPC: H01L27/148
Filed: 2000-12-14
Granted: 2002-09-21
Abstract: nable the image sensor chip to receive image signals via the transparent layer and convert the image signals into electrical signals for being transferred to the printed circuit board via the soft circuit board.
Patent TW-579555-B (TW)
Title: Semiconductor chip package and packaging of integrated circuit chip in electronic apparatus
Inventor: MOK LAWRENCE SHUNGWEI
IPC: H01L23/12
Filed: 2001-01-31
Granted: 2004-03-11
Abstract: A chip packaging structural principle is provided wherein a direct fused attachment thermal path from the surface of the chip to a cover is constructed. The thermal path location on the surface of the chip is provided with a fusion member. The thermal path location on the cover has attached thereto in a low thermal impedance connection, the cover contacting end of a high thermal conductivity path member with a length such that when the cover is in position over the chip, the chip contacting end of the high thermal conductivity member is in contact with the chip contact fusion member on the surface of the chip. A low temperature excursion and dwell then operates to fuse the fusion member and the chip contacting end of the high thermal conductivity member providing thereby a low thermal impedance direct from the surface of the chip to the cover. As many fusion members for thermal paths as desired may be deposited. The high thermal conductivity members can be a convenient shape such as posts or balls and are selected for favorable conductivity. The material for the fusion member is selected for properties that give good bonding at low temperatures. Stress due to heat generation in die chip is alleviated by positioning of the thermal paths and through the use of a stress stabilizing member between the chip and the cover.
Patent TW-520461-B (TW)
Title: A liquid crystal display device
Inventor: TOWLER MICHAEL JOHN
IPC: G02F1/139
Filed: 2001-02-07
Granted: 2003-02-11
Abstract: A liquid crystal display device comprises: a layer of a chiral liquid crystal material disposed between first and second substrates; and means for applying a voltage across the liquid crystal layer. A first region of the liquid crystal layer is an active region for display and a second region of the liquid crystal layer is a nucleation region for generating a desired liquid crystal state in the first region when a voltage is applied across the liquid crystal layer. The ratio of the thickness d of the liquid crystal layer to the pitch p of the liquid crystal material has a first value (d/p)A in the first region of the liquid crystal layer and has a second value (d/p)N different from the first value in the second region of the liquid crystal layer. The value (d/p)N of the ratio of the thickness d of the liquid crystal layer to the pitch p of the liquid crystal material in the second region of the liquid crystal layer is selected such that, when no voltage is applied across the liquid crystal layer, the liquid crystal state stable in the second region of the liquid crystal layer is topologically equivalent to the desired liquid crystal state.
Patent TW-471047-B (TW)
Title: Thin film transistor having surrounding main gate and sub-gate and the manufacturing method thereof
Inventor: LIN HUNG-JR
IPC: H01L21/28
Filed: 2001-02-23
Granted: 2002-01-01
Abstract: A thin film transistor having surrounding main gate and sub-gate and the manufacturing method thereof are disclosed. The driving force of the surrounding main gate of this thin-film transistor is more greatly increased than that of well-known single-gate thin film transistor. In addition, voltage is applied to the sub-gate of this thin-film transistor to sense and form an electrical junction, which can replace the traditional source/drain extension region equivalently. Therefore, the disadvantage of attenuating driving force resulted from the leakage current of TFT using well-known LDD (lightly doped drain) structure can be improved.
Patent TW-487979-B (TW)
Title: Method for forming multi-thickness gate oxide layer by using oxygen plasma doping
Inventor: CHEN WEI-WEN
IPC: H01L21/283
Filed: 2001-02-26
Granted: 2002-05-21
Abstract: The present invention discloses a novel method for producing semiconductor device, which comprises: providing a semiconductor substrate; forming and defining a photoresist layer thereon; using the photoresist layer as a mask to perform a pulse-type plasma doping to form a doped region and an undoped region on the surface of the semiconductor substrate; after removing the photoresist layer, performing a thermal oxidation process to form a thick gate oxide layer in the doped region and a thin gate oxide layer in the undoped region; and using a conventional process to form a gate on the thick gate oxide layer and a gate on the thin gate oxide layer, respectively.
Patent TW-498636-B (TW)
Title: Method and system for channel estimation using multi-slot averaged interpolation
Inventor: ROE SOOYEON
IPC: H04B7/005
Filed: 2001-03-23
Granted: 2002-08-11
Abstract: A method of multi-slot averaged linear interpolation (MALI) to estimate channel transfer characteristics at a receiver in a wireless network. The method and system are particularly well suited to use in wideband CDMA transmission systems. The steps of the method include calculating an instantaneous channel estimation from each slot in a transmitted signal, combining the instantaneous channel estimations for adjacent slot groups, and linearly interpolating between multi-slot averages to provide each symbol within a slot an accurate estimate of transfer characteristics for that symbol.
Patent TW-513875-B (TW)
Title: Sending full-content data to a second data processing system while viewing reduced-content data on a first data processing system
Inventor: DUTTA RABINDRANATH
IPC: G06F12/00
Filed: 2001-03-30
Granted: 2002-12-11
Abstract: A system, method, and computer program product which allows a user to view and navigate reduced-content web pages on a wireless connection. Upon the user's selection of specific web pages, the pages are then delivered to the user by a less expensive connection, as in a conventional wired internet connection. The delivery is accomplished by several methods, according to different embodiments, including by an electronic mail message, by ""push"" delivery to an internet-connected data processing system, and by providing a set of hyperlinks to the wired internet connection which reference the selected pages, among other methods. The user is thereby able to view, on a second internet-connected data processing system, the data selected when using the wireless internet-connected data processing system.
Patent TW-486742-B (TW)
Title: Gate etch process for 12 inch wafers
Inventor: GREWAL VIRINDER
IPC: H01L21/28
Filed: 2001-04-02
Granted: 2002-05-11
Abstract: A method for fabricating a stacked gate array on a semiconductor 12 inch wafer uses a reaction chamber with an upper inductive means and a lower capacitive means. For etching 12 inch wafers the etching parameters are adjusted to values optimized for etching an 8 inch wafer. In particular the power of the upper inductive means is set to a value between 50 and 600 Watts.
Patent TW-504638-B (TW)
Title: Optical mouse with a simplified design
Inventor: WANG CHING-WEN
IPC: G06F3/0354
Filed: 2001-04-26
Granted: 2002-10-01
Abstract: An optical mouse has a monolithic bottom housing, a lens set component and a circuit board for control circuitry. The bottom housing has an opening and a light source mount. The lens set component is disposed over the opening. The circuit board has a light source and a light sensor, which are mounted on the circuit board. The circuit board is fixed within the bottom housing over the lens set component, and helps to secure the lens set component within the bottom housing. The light source sets within the light source mount. The light source mount helps to fix the angular orientation of the light source within the bottom housing so that light from the light source is directed through the opening onto the surface on which the optical mouse slides. Light reflecting from the surface passes through the lens set component to the light sensor.
Patent TW-538388-B (TW)
Title: Manufacturing method of dynamic transparency
Inventor: LING SHIOU-JEN
IPC: G09B5/02
Filed: 2001-05-17
Granted: 2003-06-21
Abstract: The present invention provides a manufacturing method of dynamic transparency which comprises a dynamic sheet and a static sheet. The dynamic sheet is a transparency manufactured to have a density degree of including fourteen vertical parallel lines in one centimeter. The static sheet is a transparency with pictures and drew thereon inclined lines substantially with several different kinds of angles with respect to the vertical lines or vertical lines with a density degree different from that of the dynamic sheet. The dynamic sheet is covered on the static sheet. When the dynamic sheet is pulled on the static sheet, the cross points formed by the vertical lines and the inclined lines of the static sheet cause an illusion of flowing ripple in vision, thereby achieving the effect of simulating dynamics. The present invention can be used to produce color transparency with a computer graphic software, so as to increase the affinity of the picture. Furthermore, it is able to present animation-screen which not only attracts the attention of students but also makes the tuition vivid, thereby increasing the teaching effect and providing an outstanding design.
Patent TW-I235175-B (TW)
Title: Refrigerating machine oil composition
Inventor: SHIMOMURA YUJI
IPC: C10M171/00
Filed: 2001-07-23
Granted: 2005-07-01
Abstract: The refrigerating machine oil composition of the invention contains alicylic multi-carboxylic acid ester compounds obtained by the following compounds (a) to (c): (a) an alicylic multi-carboxylic acid with an alicyclic ring and 2 or more carboxyl groups and at least 2 of the said carboxyl groups binding to adjacent carbon atoms of the said alicyclic ring or its derivatives, (b) a compound containing 2 or more hydroxyl groups or its derivatives, (c) a compound containing 1 hydroxyl group or its derivatives. When they are used with HFC refrigerant and nature refrigerants of carbon dioxide or hydrocarbon, it could be balanced to satisfy all of lubrication, refrigerant-solubility, heat-hydrolysis stability and electricity-insulation.
Patent TW-584992-B (TW)
Title: Parallel interference cancellation receiver for multiuser detection of CDMA signals
Inventor: REZNIK ALEXANDER
IPC: H04B1/00
Filed: 2001-08-27
Granted: 2004-04-21
Abstract: A parallel interference cancellation receiver that reduces impulse response interference using a model of the received signal similar to that used in block linear equalizers. Block linear equalizers comprise decorrelating receivers, zero-forcing receivers, minimum mean square error receivers and the like. The invention comprises an interference computation processor feedback loop for correcting the output of a direct interference canceller. The m iterative process removes interferers from the output symbols of a matched-filter. The PIC receiver uses received signal models of the various block linear equalizers that do not assume that each subchannel consists of several distinct paths. The receiver estimates the impulse response characteristic of each subchannel as a whole.
Patent TW-513506-B (TW)
Title: Double floor structure
Inventor: SHIMIZU SHOHACHI
IPC: E04F15/00
Filed: 2001-08-29
Granted: 2002-12-11
Abstract: To provide a double floor structure capable of being disposed by preventing a floor panel being lifted upward. The double floor structure is composed of a plurality of floor joist members 12, disposed in parallel with one another at intervals on a foundation floor 11 within a building, and the plural first and second floor panels 13a and 13b erected and supported on the respective members 12. The engaging pieces 20 of the panels 13a and 13b disposed in the second erection position are engaged with the supporting protrusions 17 of the members 12 so as to enable the upward movement of the panels 13a and 13b to be regulated, and wedges 22 permit the lateral movement of the panels 13a and 13b to be regulated.
Patent TW-540181-B (TW)
Title: Method for the preparation of cathode active material and method for the preparation of non-aqueous electrolyte
Inventor: HOSOYA MAMORU
IPC: H01M4/136
Filed: 2001-09-21
Granted: 2003-07-01
Abstract: A non-aqueous electrolyte cell having superior electronic conductivity and superior cell characteristics. A cathode active material used for the cell is a composite material of a compound having the formula LixFePO4, where 0 < x <= 1.0, and a carbon material, wherein the specific surface area as found by the Bullnauer Emmet Teller formula is not less than 10.3 m<2>/g.
Patent TW-496813-B (TW)
Title: Infrared end-point detection system
Inventor: GOTKIS YEHIEL
IPC: B24B37/013
Filed: 2001-10-12
Granted: 2002-08-01
Abstract: A chemical mechanical planarization system and methods for implementing infrared detection of process state and substrate surface composition are provided. In one example, the chemical mechanical planarization system includes a substrate chuck to hold and rotate a substrate, a preparation head mounted on a preparation carrier, and a conditioning head mounted on a conditioning carrier. The preparation head is configured to be applied against the substrate, overlapping at least a portion of the substrate of an area smaller than the entire surface area of the substrate. The system further includes an infrared sensor positioned over the substrate to sense infrared emissions from the surface of the substrate. Several examples of infrared sensors are provided including single point, scanning, and array infrared sensors. In another example, a method of determining process state and surface composition of a substrate using infrared sensing is provided. During chemical mechanical planarization, an infrared sensor is positioned to sense infrared emissions from the surface of a substrate, and to analyze the infrared emissions to determine process state and to generate a topographical detail of the substrate.
Patent TW-533413-B (TW)
Title: Asynchronous hidden refresh of semiconductor memory
Inventor: CHEN WENLIANG
IPC: G11C8/02
Filed: 2001-11-09
Granted: 2003-05-21
Abstract: Improved semiconductor integrated circuit random access memory (RAM) features pin-compatible replacement of SRAM devices, while providing low power and high density characteristics of DRAM devices. The refresh operations of a DRAM array are hidden so as to faithfully emulate an SRAM-type interface. The new refresh strategy is based on prohibiting the start of a refresh operation during certain periods but otherwise continuously refreshing the array, rather than affirmatively scheduling refresh at certain times as in the prior art. Short refresh operations are initiated frequently, driven by an internal clock that generates periodic refresh requests, except when a read or write operation is actually accessing the memory array. By isolating the DRAM memory array from I/O structures, external memory accesses are essentially interleaved with refresh operations, rather than temporally segregating them as in prior art.
Patent TW-531655-B (TW)
Title: Peripheral component connection interface burn-in card
Inventor: JAN YI-SHIN
IPC: G01R31/28
Filed: 2001-11-30
Granted: 2003-05-11
Abstract: The present invention provides a peripheral component connection interface burn-in card. The burn-in card of the present invention is composed of a burn-in test circuit and a burn-in process and result display circuit. With the burn-in test program provided by the burn-in test circuit, the I/O devices in the motherboard are sequentially checked to determine their access statuses. After each check, a reset pulse is sent, so as to achieve the purpose of complete burn in. The present invention also applies a display circuit to display the burn-in time and whether there is a crash in the burn-in process. With the present invention, the test person can directly look at the operating status of the burn-in test and the progress of performing the burn-in test.
Patent TW-533559-B (TW)
Title: Chip package structure and its manufacturing process
Inventor: LIN MAU-SHIUNG
IPC: H01L23/28
Filed: 2001-12-17
Granted: 2003-05-21
Abstract: A chip package structure and its manufacturing process are disclosed in the present invention. In the invention, a chip is bonded to a glass substrate, and a laminated circuit layer having an external circuit is formed on the chip and the glass substrate. Part of the external circuit is electrically connected to metal pad of the chip and is extended to the region except that above the active surface of the chip for fanning out the metal pad of the chip to the region except that above the active surface of the chip. In addition, the active surface of the chip even has an internal circuit and plural active devices such that signal can be transmitted from an active device to the external circuit via the internal circuit and is transmitted from the external circuit to the other active device via the internal circuit. Furthermore, it is capable of integrating the chips having the same function or different functions in a packaging body so as to make the chips electrically connect with each other through the external circuit.
Patent TW-521315-B (TW)
Title: Method for fabricating a semiconductor epitaxial wafer having doped carbon
Inventor: PYI SEUNG-HO
IPC: C30B15/04
Filed: 2001-12-31
Granted: 2003-02-21
Abstract: A method for fabricating a semiconductor epitaxial wafer having doped carbon comprises: mixing a carbon block and a silicon block and melting them together; growing a carbon-doped cast nugget from the molten carbon-containing silicon; polishing the carbon-doped cast nugget to form a flat surface and a dent; slicing the carbon-doped cast nugget into pieces of silicon wafers; polishing the carbon-doped silicon wafers; and growing an epitaxial silicon layer on the surface of the polished carbon-doped silicon wafer.
Patent TW-I244477-B (TW)
Title: Compositions comprising higher diamondoids and processes for their separation
Inventor: DAHL JEREMY E
IPC: C07C4/00
Filed: 2002-01-18
Granted: 2005-12-01
Abstract: Higher diamondoids ranging from tetramantanes through undecamantanes are disclosed in isolated and enriched forms. Methods for obtaining these higher diamondoids are disclosed, as well.
Patent TW-550457-B (TW)
Title: Method and system for circular addressing with efficient memory usage
Inventor: CHOU HONG-CHI
IPC: G06F5/10
Filed: 2002-01-24
Granted: 2003-09-01
Abstract: An apparatus generates addresses for circular address buffers in a memory, in which a higher boundary of a circular buffer is implied from the current address. This approach is applied alone, and in combination with circular buffers which rely on an implied lower boundary to improve memory usage and flexibility in the design of circular buffers for integrated circuits. The dual mode address generator comprises inputs that receive a current address A, an address offset M, a buffer length L and a control signal; and logic configured to compute a first memory address for a buffer with an implied lower boundary and a second memory address for a buffer with an implied higher boundary in response to A, M, and L. One of the first and second memory addresses is provided in response to the control signal. The first memory address corresponds the current address A plus the address offset M for a first circular buffer having an implied lower address boundary X and including addresses X through (X+L); and the second memory address corresponds the current address A plus the address offset M for a second circular buffer having an implied higher address boundary Y and comprising addresses Y through (Y-L).
Patent TW-593564-B (TW)
Title: New benzoindole styryl compounds and its use for a high density optical recording medium
Inventor: WANG SHIN-SHIN
IPC: G11B7/24
Filed: 2002-04-19
Granted: 2004-06-21
Abstract: The invention discloses new benzoindole styryl compounds and its use for a high density optical recording medium. The invention uses the dyes of the new benzoindole styryl compounds to form the recording layer of high density recording medium. The new benzoindole styryl compounds are easy to compound and purify, so they are cheaper when comparing to the compounds generally used in high density optical recording medium. The benzoindole styryl compounds has a lot of absorption for the light wavelength in the range of 500 nanometer to 700 nanometer. The benzoindole styryl compounds have highly absorption for the light wavelength in the range of 500 nanometer to 700 nanometer and also have high sensitivity and chemical stability for light and heat. The new benzoindole styryl compounds form a high density optical recording medium which can match up with the short-wavelength laser bean that high density optical recording medium uses and have the advantage of stable quality.
Patent TW-582143-B (TW)
Title: Wireless clock synchronization
Inventor: BEKRITSKY BENJAMIN J
IPC: H04M1/72415
Filed: 2002-05-17
Granted: 2004-04-01
Abstract: A system and method for synchronizing internal clocks of receiving stations of a locating system are described. A beacon transmits reference data packets at a known position. A first arrival time is compared to a second arrival time to determine a correlated arrival time data. The first arrival time is a time of reception of the reference data packets by a first receiving station, and the second arrival time is a time of reception of the reference data packets by a second receiving station. A linear polynomial fit is computed as a function of the correlated arrival time data and the first and second arrival times. Times of arrival of data packets at the first and second receiving stations is synchronized as a function of the linear polynomial fit.
Patent TW-592780-B (TW)
Title: Improved sulfur-bearing residue treatment system
Inventor: CARLSON CURTIS INGSTAD JR
IPC: C07C69/54
Filed: 2002-06-07
Granted: 2004-06-21
Abstract: A sulfur-bearing residue treatment system is provided for the recovery of valuable organic components and the reduction of capital costs and operating costs. The treatment system involves the use of a stripping vessel in conjunction with a heating apparatus. All elements of the treatment system may be coupled together to form one integral piece of equipment.