Patent GB-845344-A (GB)
Abstract: 845,344. Multiplex pulse code modulation systems. WESTERN ELECTRIC CO. Inc. Dec. 18, 1958 [Dec. 24, 1957(2)], No. 40842/58. Class 40(5). Relates to a pulse code modulation time division multiplex system in which the distributor is provided with means for inserting synchronizing or other signal pulses in a predertermined manner between encoded samples, the encoding of the message samples being periodically delayed for the duration of one time slot and the synchronizing or other additional pulse being inserted in this slot. As shown the output of a pulse generator 10 at a repetition rate n is applied to series connected delay circuits 11 to 16, each producing a time delay equal to 1/n. The outputs of the delay circuits 11 to 15, and the output of the delay circuit 16 via a normally disabled AND gate 17, are applied via diodes 18 to 23 respectively to an inhibit terminal of the generator 10, the arrangement being such that when AND gate 17 is enabled, one out of every seven pulses from the generator 10 is applied to the delay circuits, and generator 10 and delay circuits 11 to 16 each supplies a train of pulses to its respective lead 25 to 30. The time interval between the pulses in each train is 7/n, the pulse trains are progressively displaced by a time interval 1/n, Fig. 2, and seven different output trains are produced. When the AND gate 17 is disabled, one out of every six pulses appears at the output of the generator 10, the time interval between the pulses in each train is 6/n, the pulse trains are progressively displaced by 1/n, and there are six different trains, since the pulses at the output of the delay line 16 and generator 10 coincide in time. Thus AND gate 17, when enabled, adds an extra inhibit pulse to the inhibit terminal of the generator 10 and delays the appearance of timing pulses on leads 25 to 30 by one time slot. The AND gate 17 is controlled by a flip-flop 33 receiving inputs from the delay circuit 11 and a counter 32 which in turn is energized from the delay circuit 12. The counter 32 produces one output pulse for twenty-four input pulses. A further output of the flip-flop 33 controls a counter 34 which produces one output pulse for two input pulses and together with the other output of the flip-flop controls a normally disabled AND circuit 35 which with the switch 36 as shown receives an input from the delay circuit 16. The timing pulses on leads 25 to 30 control an encoder 39 controlling both the sampling of messages and the encoding of the samples. Alternate marks and spaces constituting framing information are provided by the AND gate 35 and inserted via an OR gate 38 in the time slot in the output of the encoder 39 made available by the delay introduced by enabling the AND gate 17. In operation, when the counter 32 has counted twenty-four pulses it causes flip-flop 33 to change state and apply enabling voltages to AND gates 17 and 35 but the counter circuit 34 requires two input pulses to produce an output pulse and the gate 35 remains disabled and a space is introduced into the time slot, made available by the operation of gate 17 to provide the framing information. The pulse at the output of the delay circuit 11 as a result of the delayed 25th pulse from the generator 10 returns the flip-flop 33 to its initial state until at the 48th pulse from the generator 10 both gates 17 and 35 are enabled and framing information in the form of a mark is introduced into the time slot made available. In the case of an encoder which introduces a delay, compensation may be effected by including a delay circuit between the gates 35 and 38, or alternatively a suitable delay may be introduced by supplying the input to the gate 35 via switch 36b from a delay circuit other than the circuit 16. In a modification a delay circuit having a delay equal to one time slot is connected between the lead 24 and the pulse generator 10 and the gate 17 is connected between the delay circuits 15 and 16, the output of the generator 10 being connected via a diode to the lead 24. The system may be arranged to delay the encoding of message samples for several time slots, a particular framing pattern being inserted in the empty time slots. The delay circuits and pulse generator, Figs. 4 and 5 (not shown) include a transistor blocking oscillator similar to that shown in Specification 811,958 the output circuits being suitably modified. Specification 785,568 also is referred to.