Patent GB-1357598-A (GB)
Title: Arithmetic unit
IPC: G06F7/52
Filed: 1971-11-09
Abstract: 1357598 Digital arithmetic units INSTITUT MATEMATIKI SIBIRSKOGO OTDELENIA AKADEMII NAUK SSSR 9 Nov 1971 52017/71 Heading G4A A serial by digit arithmetic unit for performing the four rules of arithmetic is described. The unit operates in binary-decimal code. The two operands are placed respectively in registers 1, 12 under the control of a numeral entry keyboard 14. The arithmetic function is selected by a keyboard 15 which feeds a control unit 10 connected to a sequence controller 4. The controller enables the various input and output gates of the arithmetic unit 1, multiplier 2, and adding unit 3 in the order necessary to perform the function called for. The controller comprises reversible counters 19-21 and respective decoders 22-24. Addition.-Considering the least significant digit of an operand to be the zero order digit, the next significant digit to be the first order, and so on, addition is performed as follows. The zero order digits of the addends are added in known manner in adder 38 in the adding unit. The resulting zero order digit is stored in the zero order position of result register 13 and the carry, if any, stored in adder 38. The first order digits are next added, together with the carry, if any, to provide the first order result digit, and so on. Subtraction.-The minuend is first added as described above to the inverse of the subtrahend but the result is not recorded. If there is a carry in the highest order position of the result the minuend is greater than the subtrahend. The operand which has thus been discovered to be the smaller is now inverted and added to the other operand, the result being recorded in result register 13. Multiplication.-Each order of the result is obtained by the addition of partial products, together with the carry, if any, from previous additions. Each partial product consists of the product of one digit from both operands, the sum of the orders of the digits selected being equal to the order of the result digit being calculated. Division.-The divisor is multiplied, as above, by factors 1 to 9 in succession, and as each order is calculated the resulting values are subtracted from the corresponding part of the dividend by adding them in turn to the inverted dividend. The presence or absence of a carry after each addition indicates whether or not the dividend is greater than the multiple of the divisor. When it is not the factor of the preceding multiple is placed in the highest order of the result register. To obtain the next lower order of the result the divisor is now multiplied in turn by factors in which the most significant digit or digits is the number currently in the result register and the next lower significant digit is, in turn, 1 to 9. These multiples are subtracted from the corresponding part of the dividend as before, and so on, to provide successively lower order digits of the result. The circuit described includes gates 17, 18 controlling input to the operand registers 11, 12, gates 5, 6, 7 controlling input to the arithmetic unit 1, gates 8 feeding the outputs of the arithmetic unit 1 to result register 13, input gates 25, 28, 31 of the multiplier 2, input gates 26, 29, 32, 34, 35 and output gate 41 of the adding unit 3, and selectively operable inverters 36, 37.