Patent GB-1163981-A (GB)
Title: Improvements in or relating to Time Division Communication Systems
IPC: H04L5/22
Filed: 1966-11-29
Abstract: 1,163,981. Multiplex pulse code signalling; telegraphy. WESTERN ELECTRIC CO. Inc. 29 Nov., 1966 [14 Dec., 1965], No. 53384/66. Headings H4L and H4P. In a time division multiplex signalling system comprising a plurality of input ports for receiving coded signals, means are provided for applying the coded signals to a common path from the plurality of input ports, and means responsive to the application to the common path of a coded signal from one input port initiate the application to the common path of a coded signal from another of the input ports. At the receiver means responsive to the application of a coded signal to an output port cause the application of the next coded signal received over the common path to another output port. General description.-Incoming signals in the form of a start-stop code containing a parity bit are applied via leads 101 to 104 to input ports or buffers 105 to 108 which store the signals until they are read out sequentially to a common bus 120 under the control of a circuit 124 and clock generator 121 which may control a slave clock at the remote end in known manner. When the read-out from buffer 108 finishes a signal from terminal STS is applied to the control circuit 124 which at the next clock pulse applies a framing bit to the bus 120. The framing bit consists of alternate mark and space. At the end of the framing signal the control circuit 124 applies an enabling signal to terminal STP of input buffer 105 so that it accepts clock pulses via terminal CL-1 to read-out one data character and a flag bit indicating the condition of the parity element through the data output lead. If no code character has been received on line 101 a signal indicating the condition of line 101 is sent. After these signals have been applied to bus 120 the buffer 105 applies a signal via terminal STS to terminal STP of buffer 106 which reads out the character stored therein in the same way, this process being repeated until a framing signal from buffer 108 initiates the next cycle. When all the buffers have concluded their read-out they apply an enabling potential to control circuit 124 to show that none of the buffers are operating and to permit circuit 124 to apply the framing signal to bus 120. At the receiver the framing signal is detected by control circuit 125 which provides an enabling signal on terminal STP of output buffer 115 which accordingly counts and registers the character applied to bus 120 from buffer 105. When the character plus the flag bit have been registered, the buffer 115 provides an enabling signal via terminal STS to terminal STP of buffer 116 which registers the data from buffer 106. Similarly, each of the output buffers counts and registers the bits from the corresponding input buffer until the output buffer 118 concludes its registration and applies a signal via terminal STS to enable the control circuit 125 to read bus 120 to detect the framing signal, which, assuming the framing signal is correct, initiates a new cycle. If at this stage control circuit 125 detects an incorrect framing signal indicating loss of synchronization, after two successive incorrect framing bits have been detected it applies a disabling potential to terminals DD-1 to DD-N to prevent registration of any of the data bits and also via terminal D1S disables the counter of buffer 115. Control circuit 125 then examines successive bits from bus 120 until a correct framing signal is detected, whereupon the disabling potential is removed from terminal D1S so that buffer 115 commences to count the incoming bits, the disabling potential on terminals DD being retained. After buffer 115 has counted the required number of bits the remaining buffers are enabled to count as before but without registering, each of the output lines being maintained in the signal condition occurring when synchronization was lost. At the end of the cycle the circuit 125 again examines the bit appearing on bus 120 and if it is a correct framing bit another counting cycle is initiated, bit registration still being prevented. After this cycle, if a correct framing bit is detected, it is presumed that the system is synchronized, the disabling potentials are removed from the terminals DD and normal operation resumed. Input buffer stages.-The store in each input buffer includes a first shift register into which signals are inserted at the signalling rate of the incoming transmission line which is connected via gate circuits to a second shift register reading out at the transmission rate of the common bus. During this process the start and stop bits are removed, the parity bit is examined and a new flag bit is inserted which depends upon the incoming signal, the condition of the input line and the parity bit. The logic circuits for detecting these various conditions and initiating the appropriate flag signal are described, Figs. 2, 3 (not shown). Receiving end output buffer stages.-These operate in converse manner to the input buffer stages to reconstitute the signals in their original form with start, stop and parity bits and to distribute them to the respective output channels at the appropriate signalling rate, Figs. 5, 6 (not shown).