Patent GB-961947-A (GB)
Title: Core array temperature responsive apparatus
IPC: G11C11/06
Filed: 1960-10-06
Abstract: 961, 947. Electric selective signalling systems; temperature alarms. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 6, 1960 [Oct. 9, 1959], No. 34257/60. Headings G4H and G4N. [Also in Division H3]. The approach of overheating of a group of magnetic storage cores due to an excessive rate of repetitive driving is signalled by the change of output voltage from an associated test core which is changed from one stable state to the other whenever any of the cores in the group are switched . The outcome of an excessive driving rate is to narrow the hysteresis characteristic of the storage cores to such an extent that erroneous storage or read-out occurs, while at the same time the output voltage from core switching is increased. The latter effect is used to indicate overheating of the test core which is excessively driven compared with the individual storage cores. In an application to a three-co-ordinate data store comprising a stack of two-co-ordinate matric planes, each plane comprises magnetic storage cores 62, Fig. 6b associated with row and column drivers Y1-Y4, X1-X4, an inhibiting driver Z, and a common read-out wire 64 connected to an amplifier 66. In addition a test plane is provided which is identical to Fig. 6b except that the inhibiting circuit is omitted and the amplifier 66 is connected to a voltage-sensitive device 68. The writing operation is effected in the usual manner by simultaneously pulsing a selected X and Y driver in each plane to write a binary word, and at the same time selectively energising those inhibit drivers which are associated with planes in which a binary zero is to be registered. As the inhibit circuit is omitted from the test plane, test core switching occurs for each and every writing operation and more rapid heating therefore takes place. This is indicated by a rise in the read-out potential at the voltage-sensitive device 68. In a modification, Fig. 6c, a separate test plane is replaced by test cores 70, 72 in each plane which are associated with respective matrix column and row conductors. As the number of winding turns on the test cores are double those on the storage cores, test core switching in a row and a column occurs each time a single storage core is switched. The test cores have separate read-out circuits 74, 76, and overheating is signalled when the test output voltages in the row and the column both increase, the signal being obtained from an AND gate 82 having inputs from voltage-sensitive devices 78, 80. Modifications are described to increase the variation of test-core voltage output when the core becomes overheated. In one arrangement, Fig. 5a (not shown), a test core is larger than a storage core and due to its greater volume-to-surface area becomes overheated more rapidly. In other arrangements Figs. 4a-4c (not shown) more rapid heating of the test cores is obtained by coating each core with a thermal insulating material, or either encasing a test core array in a frame of heat-insulating plates, or embedding the array in a heatinsulating body. Again, the test cores may have a lower Curie temperature than the storage cores. A three-co-ordinate array with a separate test plane may also be modified by having double the number of storage-core row and column turns on the test cores, and having a continuous inhibiting current equal to the effect of one turn, the switched test cores being then overdriven to an extent such as to increase in temperature more rapidly. Another method is to employ the double-wound test cores as previously described but without the provision of an inhibiting current. Instead, test core material requiring twice the coercive force of the storage cores for a reversal of remanent state is used. In an application to a two-co-ordinate store, Fig. 7a, a test core 102 is provided for each column of storage cores 100, a test core being switched with a storage core by direct column energisation and by indirect row energisation over a row OR gate 104. A modification is shown in Fig. 7b in which test core energisation is provided by doubled column windings only. Another application is to a decimal to binary translator comprising coding cores 117-120, Fig. 8, in which a test core 121 is switched by the most frequently occurring decimal digit, in this case zero. A modification of the test core arrangement of Figs. 7a and 7b is shown in Fig. 9a in which each test core 132 is duplicated, the additional core 134 being temperature controlled within a thermally insulating container 141. The test output conductor 136 passes through the two cores in opposite senses so that normally a null output is obtained. When however the two test cores are repeatedly switched, the higher temperature rise of core 134 produces a resultant output voltage which is detected by a signalling device 140. In a modification the core 134 is maintained at a constant temperature so that the temperature rise of core 132 produces the output signal. In a further modification core 134 is maintained at a constant intermediate elevated temperature. Thus when core 132 is cool an output of one polarity is produced and when the core 132 has reached a permissive higher temperature the output polarity reverses. Specification 836,198 is referred to.