Patent GB-826613-A (GB)
Title: Improvements in or relating to electronic digital computers
Inventor: GILLIES DONALD BRUCE
IPC: G06F9/355
Filed: 1955-01-24
Abstract: 826,613. Electronic digital calculators. NATIONAL RESEARCH DEVELOPMENT COR. PORATION. Dec. 2, 1955 [Jan. 24, 1955], No. 2086/55. Class 106 (1). In a serial mode-type electronic digital computer an order word comprises two separate address-defining digit groups, one of which groups controls switches to connect a selected one of a plurality of single word immediate access type storage registers to a mill and the other digit group connects a further selected one of said registers to the mill. The two register contents are transmitted to the mill simultaneously, and the mill output is fed to a selected' one of the registers determined by a chosen one of said digit groups. General arrangements-Figs. 1, 2. Order and number words are transferred in known manner from the main low-speed magnetic drum store 1 to the high-speed computing store 10 which consists of a group 2 of seven accumulatorregisters, four further groups. 4 each of eight storage registers and a group 3 of other address registers for auxiliary, e.g. constant representing signals. An order word, Fig. 2 (c), consists of A and B orders, each similarly divided in time order into M, F, X, N digit groups. The three M digits define the address in the accumulator register group 2 of store 10 of any required modifier word to be used for altering the subsequent N or X digits only, or both the N and X digits of the same order as described in Specification 826,612. The six F digits define the function to be performed by the machine. The three X digits select the particular accumulator register in group 2 to be associated with the mill 5 and the seven N digits define the address in the store 10 where one operand is to be obtained or delivered. A " stop-go " digit in interval 38 of an order word provides for an optional stop of the machine operation before. obeying the first or A order of the word. Each minor cycle or beat of the machine, for signalling a number word, Fig. 2 (b), is of 42 digit intervals length, Fig. 2 (a). A normal operation cycle of the machine comprises A and B periods during which the A, B orders respectively are obeyed, followed by a C period during which the next order word is selected and fed into the control system. The A, B periods each have a minimum length of two beats (D, E beats), but other intervening beat periods may be interposed between the D, E beats dependent upon the operation. The C period occupies one beat. A beat counter, Fig. 3 (not shown), controls the machine rhythm by providing waveforms corresponding to the various D, E beats and other auxiliary U, X waveforms which are applied to various points of the machine. In addition to the high-speed computer store 10 shown in detail in Fig. 6, the mill, Fig. 7, and the control system, Fig. 4, separate staticisor circuits, Fig. 5 (not shown), similar to those described in Specification 789,207, are provided in respect of the M, F, X, N digits of an order, and function, when set up by the corresponding order digits, to provide static output waveforms designated S, F, G, N which are also fed to appropriate control points, Figs. 4, 6, 7 of the machine. Operation.-A control address number signal indicative of the address of the last used order word is continuously circulating in a control number register A01, Fig. 4, consisting of a " 42-digit interval delay line " (as defined in the Specification) and its regenerative loop. During the E beat of the B period the X20 waveform causes this number to be read out through a " double entry gated delay " A21 to one input of an adder ADR1 and at digit time 32 allows a single pulse to be fed through a double-entry gated delay A61 to the other adder input whereby the control address number increased by unity flows down the control line of unit delays A24 ... A48. It also flows from unit delay A28 through the 35 interval delay line A14 and a mixer A12 to the opposite entry gate of delay line A01 where it arrives at the beginning of the following beat, i.e. the D beat of the next C period. As the two entry gates of the register A01 are both reversed at this time by the U15, U16 waveforms, the original word is erased from the register A01 and the new word from mixer A12, i.e. the previous control address number increased by unity entered in its place. In this manner the order addresses are normally rendered operative sequentially. The unit delays A24 . . . A48 provide appropriate outputs I0, I1 . . . I17 which are fed to various points of the machine including the N digit staticisors which are set up at digit 40 time, i.e. at the end of the E beat of the B period, according to the new control address number. A corresponding combination of two N waveforms is thereby made available by the N digit staticisors to open the gate such as Y58 or Y302, Fig. 6, of the selected one of the thirty-two registers 4, only two of which, 64 and 95, are shown in Fig. 6. The next required order word, which has been circulating in the 42-digit delay line Y78, of the selected register 64, for example, is thereby released, i.e. at the start of the D beat of the C period, through a gate Y96 with one digit interval delay over the bus Y40 and a " double-entry unit delay " A41, Fig. 4, to the input 67 of the adder ADR1. Any modifier word specified by the M digits is applied during the same beat to the adder input 68 as described in Specification 826,612. The adding circuit output, i.e. the whole modified order word, flows along the unit delays A24 ... A48 and through delay A14 direct to the double entry gate A21 where it arrives as the next beat, the A period D beat, commences. The initial half of the order wordthe B orderis lost from the control instruction line during the C period as the return path thereof to the double-entry gated delay A41 is blocked at the appropriate time. Thus at digit interval time 40 of the C period D beat, only the A order of the order word is present in the control line A24 ... A48 and the N digit staticisors are released and then reset according to the new address number specified by the N digits of the A order of the selected order word. At digit interval time 41 in the same beat, the X digit and F digit staticisors are set up to produce corresponding combinations of F, G, S, waveforms. The M digit staticisors are also similarly set up at digit times 24, 25 of the same D beat of the C order, to produce further S waveforms. The F digit staticisors remain set up for both D, E beats of the A period but the other staticisors are reset after one beat or less. The setting of the N digit staticisors select one of the accumulator registers ACR 1... ACR7, Fig. 6, or one of the thirty-two registers 64 ... 95, or one of the auxiliary address registers such as 30, 33, 35 (sources of constants) by opening a corresponding gate S17, S13, S11, Q70, Y58, Y302 or one of the unit delays V6, V7, H50. The operand number word signal so selected is fed to the mill, Fig. 7, directly over bus Y40 or via a double entry gate V54 and bus Y41 according to the order. Similarly, the setting of the X digit staticisors selects the operative accumulator register ACR1 ... ACR7 by opening one of the gates S57, S53, S51 ... Q81 whereby the selected register operand signal, circulating in the 42 interval delay line S47, S43 . . ., is passed via double entry gated delays V36, V57 and bus-bar Y44 to the mill. The setting of the F digit staticisors determines whether the two operand inputs to the mill are fed to the inputs 64, 65, of the computing circuit CPC, or vice versa, and also determine the operation effected, the resultrepresenting signal at the output 66 passing via a 35 interval delay B55, and unit delay B56 over bus-bar Y2 back to the high-speed computing store where it enters via unit delay V51 to bus Y35 timed so that the least significant digit coincides with the first digit interval O of the next following beat E of the A period. In the meantime the order word circulating through delays A14, A21 has re-entered the control instruction line A24 . . . A28 one beat time later, and the N digit staticisors, which were reset at digit time 40 in the preceding D beat are set up again, under control of the F digit staticisors to route the result signal to its selected address by opening one of gates S17, S13, S11, Q70, Y58, Y302. This address is that accumulator register ACR1 ... &c. from which one of the operand signals was taken under control of the N digit staticisors. At digit time 20 of this E beat the gate A21, Fig. 4, is closed and A41 opened whereby the B order, which is at this time in the control instruction line A24 ... A48, is directed back into the line and circulates therein in synchronism with the timings previously applicable to the A order. In the following two D, E beats, similar operations to those occurring during the A period are effected under control of the N, X, F, X digits of the B order, after which a new order word is selected in the following C period as above described. Specifications 789,207, 789,208, 789,209, 796,404 and 826,614 also are referred to.