baber/WOPTO huggingface dataset:
Patent JP-H0964104-A (JP)
Title: Apparatus and method of mounting chip
Inventor: SATO SEIICHI
IPC: H01L21/60
Filed: 1995-08-24
Abstract: PROBLEM TO BE SOLVED: To increase the speed of the mounting of chips, and to mount the chips in multikinds on a substrate. SOLUTION: Three heads 70 are installed around the center rod 51 of a head section 50. The heads 70 are rotated horizontally around the center rod 51. When the heads 70 are turned horizontally, the heads 70 are revolved at 180 deg. in the vertical direction by a first bevel gear 61 and a second bevel gear 62. Nozzles 73 for the heads 70 pick up a flip chip P on wafer sheets 2b, and are rotated horizontally at 180 deg. and transfer the flip chip P towards a shifting head 31, but to the nozzles 73 are turned at 180 deg. in the vertical direction on its midway of the transfer of the flip chip P and the flip chips P are turned upside down. The shifting head 31 receives the flip chip P from the heads 70, and mounts the flip chip P on a substrate. The heads 70 and the shifting head 31 have nozzles optimum for the corresponding chips in response to the kinds of the chips.
Patent JP-S6195127-A (JP)
Title: Concrete formwork process
Inventor: OKUMURA YOSHIO
IPC: E02D29/02
Filed: 1984-10-15
Abstract: PURPOSE:To eliminate the needs for the separation of both sheathing boards by a method in which a prefabricated sheathing board for surface side and a metal net sheathing board for the back side are erectely set at a fixed interval by means of a separator, formworks are assembled for retaining wall, etc., and concrete is placed between the formworks. CONSTITUTION:A formwork structure for a rentaining wall, etc., consists of a surface sheathing board 1, a metal net sheathing board 2 at a given interval in the face of the board 1, a waling 6 to hold both the sheathing boards 1, and 2 at a fixed interval, and a structural brace 10 and a vertical stud 11 on the metal net sheathing board 2l side. The sheathing board 1 is a fabricated on serving as a finishing material for the outer wall of concrete structure, and the sheathing board 2 uses a metal lath with ribs. Concrete is placed between the formworks constructed and hardened, and the braces 10 and studs 11 are removed to construct a concrete structure. A retaining wall, etc., can thus be constructed without the needs for separation of the sheathing boards.
Patent JP-H0265132-A (JP)
Title: Dry etching method
Inventor: KADOMURA SHINGO
IPC: H01L21/302
Filed: 1988-08-30
Abstract: PURPOSE:To make a fine groove or hole with a high aspect ratio excellently in shape controllability by adding rare gas into halogen gas to etch silicon substance in advance. CONSTITUTION:When forming a fine groove 2 with a high aspect ratio in a single crystal silicon substrate 1, Cl2/N2 gas, in other words, the mixture gas that Xe is further added to the one that nitrogen gas is mixed to chlorine gas is used as etching gas. The etching condition shall be the condition that the energy of entering ions are small. In this case, even if it is low energy condition with the sputtering effect by Xe, the bottom etching is restrained and the groove 2 can be made excellently in shape controllability.
Patent JP-S60108883-A (JP)
Inventor: ASAI NOBUTERU
IPC: G09G1/06
Filed: 1983-11-18
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S59106062-A (JP)
Title: Address selecting circuit
Inventor: ARAI HARUO
IPC: G06F12/06
Filed: 1982-12-10
Abstract: PURPOSE:To reduce a required number of kinds of print board package, by providing exclusive OR gates on a package in accordance with respective bits of a peculiar identification code and discriminating the selection of packages by outputs of exclusive OR gates. CONSTITUTION:When an address (a)=x4xx (hexadecimal) is transmitted from a microprocessor MPU1, (0) is transmitted to input terminals A8, A9, and All of packages 60, 80, and 100, and (1) is transmitted to a terminal A10. The address is inputted to the first terminals of exclusive OR gates 24-27, 33-36, and 41- 44. Conditions of exclusive OR gates are satisfied in the packag 60 and a selecting signal (g) of logical (1) is outputted from a gate 18 to start a decoder 19, and a specific circuit 5 to be selected is selected by the address (a) other than the identification code inputted from a terminal A. However, conditions of exclusive OR gates 33-36 and 41-44 are not satisfied in packages 80 and 100, and consequently, decoders 21 and 23 are not started, and circuits 7 and 9 to be selected are not selected.
Patent JP-H0539600-A (JP)
Title: Method for electrolytic descaling of stainless steel in neutral salt
Inventor: UDA YUNOSUKE
IPC: C25F1/06
Filed: 1991-08-02
Abstract: PURPOSE:To control an electrolytic soln. to high concn. as well as to realize recycling use of this electrolytic soln. to effectively use the source and to reduce the cost, and moreover, to realize effective descaling. CONSTITUTION:When a stainless steel is descaled by electrolysis in a neutral salt soln., hexavalent chromium dissolved in a sodium sulfate soln. used as the electrolytic soln. is reduced by using a sodium metabisulfite soln. The electrolytic soln. is neutralized and filtered, and then the filtrate is recovered to be used as the electrolytic soln. above described. The hexavalent chromium in the electrolytic soln. is reduced to chromium with sodium metabisulfite soln., and then the electrolytic soln. is neutralized with sodium hydroxide. Thus, the tervalent chromium is precipitated and removed as chromium hydroxide.
Patent JP-S59105390-A (JP)
Title: Atomic beam tube
Inventor: KOBAYASHI TETSUYA
IPC: H03L7/26
Filed: 1982-12-09
Abstract: PURPOSE:To eliminate the possibility of the loss of a proper layout due to sintering, reduce the manufacturing cost, and obtain an atomic beam tube strong to oscillation impact by enabling to perform the accurate positional adjustments of an atomic beam source and a detector after sintering. CONSTITUTION:A microwave hollow resonator 6 is so fixed to a fixed part 12 that the microwave input part agrees with the microwave introduction part 9 of a vacuum sealed tube 1, and in the same manner a C magnetic field generation device 13 and a shield case 5 are fixed respectively by means of four screws. An A polarization magnet 4 and a B polarization magnet 7 are installed respectively to brackets 14 and 15 by means of snaps 16, 17 and screws 18, 19, and the brackets 14 and 15 are screwed respectively to fixing parts 20 and 21. The atomic beam source 2 is placed on a fixing part 23 after fixing on a bracket 22, and a cap scre 24 is screwed at the tip of a fixing bellow device 25. The position of the atomic beam source is moved by a moving bellow device 26 also after vacuum sealing, which is then fixed by means of the fixing bellow device 25 and the cap screws 24. The detector 8 also can be moved and fixed after vacuum sealing by means of a bracket 27, a fixing bellow device 28, cap screws 29, and a moving bellow device 30.
Patent JP-S6274332-A (JP)
Inventor: KAWAMATA MASAJI
IPC: G01N23/04
Filed: 1985-09-30
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0265412-A (JP)
Title: Digital/analog converter
Inventor: FUNAMOTO TARO
IPC: H03M1/08
Filed: 1988-08-31
Abstract: PURPOSE:To cancel an error caused in a limiter and to decrease the distortion by adding an error caused in the limiter to a quantized error at an input of a large amplitude and giving the result to a prediction filter. CONSTITUTION:The converter is provided with a limiter 3 applying amplitude limit to an output data of a quantizer 2 quantizing an output data of an adder circuit 1 again giving a negative number of a prediction quantized error to a quantized digital input signal data X, a prediction filter 5 using an output data of a subtraction means 4 taking a difference between the input data of the quantizer 2 and the output data of the limiter 4 as the input data and predicting the succeeding quantized error and giving an output, and an analog low pass filter 7 eliminating a high frequency component from the output signal of a PWM converter 6 using the output data of the limiter 3 as the input data and outputting it as an analog output signal. Thus, the distortion of the digital analog conversion at the input of a large amplitude is decreased.
Patent JP-H1165194-A (JP)
Title: Image forming device
Inventor: TAKAGI OSAMU
IPC: G03G15/01
Filed: 1997-08-11
Abstract: PROBLEM TO BE SOLVED: To provide an image forming device capable of integrating the device constituting image forming means, shortening a pitch between mutual image carriers to the utmost, obtaining shortening in the lengthwise direction of the whole device by virtue thereof and contributing to a cost reduction. SOLUTION: This image forming device is constituted so as to form an image of multiple colors by arranging plural image forming means in a series, for forming the image of a specific color by performing respective processing with regard to photoreceptor drums 1a and 1b in order of electrification, exposure, development, transfer, cleaning and discharge, making a paper sheet P successively pass through them and successively transferring the visual image of a specific color. In this case, the device is provided with an image forming units S integrating a developing device 4 of a specified color and a cleaning device 6 on the upstream side by one.
Patent JP-H05227027-A (JP)
Title: Dc offset removing circuit for a/d converter
Inventor: IWANAGA KENICHI
IPC: H04B3/14
Filed: 1992-08-14
Abstract: PURPOSE:To remove a DC offset component included-in an output from an A/D converter by using a cyclic digital filter constituted of two adders, a code converter, a delay circuit, and a branch circuit for an offset removing circuit. CONSTITUTION:A code word string x(kT) is added to an offset code word string c(kT) by the 1st adder 20 in each code word and a code word string y(kT) is outputted. A code converter 24 adds parallel 10 bits to the MSB upper side of the string y(kT) and applies the bit-added string to the 2nd adder 25 as a binary code word string m(kT) and the adder 25 outputs a binary code word string r(kT). The output of the adder 25 is delayed equally to a sampling time T by the delay circuit 26 as the code word string r(kT). An output from the circuit 26 is supplied to the adder 25 and also supplied to the adder 20 as the code word string c(kT) through the branch circuit 28.
Patent JP-S6277323-A (JP)
Title: Anticancer agent
Inventor: HAYASHI NARIYUKI
IPC: A61K31/365
Filed: 1985-09-30
Abstract: PURPOSE:An anticancer agent, consisting essentially of a metal dyestuff complex, sodium fluoresceine, etc., having selectivity and capable of emitting fluorescence by irradiated light and destroying cancerous cells by induction of photochemical reaction. CONSTITUTION:An anticancer agent consisting essentially of a metal dyestuff complex having fluorescent property and photochemical reactivity and further selectivity for DNA base of cancerous cells and sodium fluoresceine having very high fluorescence yield for light irradiation within a specific wavelength range and high selectivity for cancerous cells and adenosine triphosphate capable of facilitating incorporation of the metal dyestuff complex and sodium fluoresceine into the cancerous cells. The above-mentioned complex is capable of inhibiting the DNA synthesis, producing a large amount of radicals by irradiation with light and destroying the cancerous cells. The sodium fluoresceine is capable of readily emitting fluorescence and causing swelling of cells having effect on cell destruction.
Patent JP-H10277917-A (JP)
Title: Spiral vortex barrel machine with gap adjusting function and a retreating layer forming method and gap adjusting method
Inventor: KOBAYASHI FUMIAKI
IPC: B24B31/12
Filed: 1997-08-11
Abstract: PROBLEM TO BE SOLVED: To provide an expansion escape space of lining layer between the inner surface of metal wall and the outer surface of lining layer in an fixed reservoir. SOLUTION: A retreating layer is formed over the desired area between a lining layer 3 and the inner surface of metal wall in a fixed reservoir 4 in a spiral vortex barrel machine 13 consisting of a cylindrical fixed reservoir 4 and a rotating reservoir 12 which is installed to close the lower part of the fixed reservoir 4.  For forming the lining layer 3 in the fixed reservoir 4 of the spiral vortex barrel consisting of the cylindrical fixed reservoir 4 and a rotating reservoir 12, a break away means is applied on the lining layer over vertically prescribed area at the position corresponding to the minor gap S of the fixed reservoir 4 and the rotating reservoir on inner surface of metal wall in the fixed reservoir and then the lining layer 3 is formed on the inner surface of metal wall in the fixed reservoir and a shelter layer is formed in the part where a break away means is applied.
Patent JP-2001044326-A (JP)
Title: Semiconductor device and manufacture thereof
Inventor: KAWAGUCHI YASUMASA
IPC: H01L23/12
Filed: 1999-07-30
Abstract: PROBLEM TO BE SOLVED: To protect a semiconductor device against disconnections due to warpage of a sealing body. SOLUTION: A group of inner terminals 14 and a group of outer terminals 15 are each formed on the upper and lower surfaces of a base 11 of a BGA/IC 31, where the inner terminals 14 and the outer terminals 15 are connected electrically together with electrical wirings 17. A semiconductor pellet 26 bonded to the top surface of the base 11 is connected electrically to the inner terminals 14 with wires 28. Solder bumps 21 are provided protruding to the outer terminals 15, which are out of the outer terminals provided on the under surface of the base 11 and located in an intermediate region, and pins 18 which are higher than the solder bumps 21 are provided, protruding to the outer terminals arranged on the outer peripheral part of the under surface of the base 11.  At this point, since the pins 18 are anchored to through-holes provided to the a mounting board, the base 11 is prevented from warping due to heat released at mounting of a mounting board. Therefore, connection terminals can be protected against breakage due to solder bumps.
Patent JP-H0555842-A (JP)
Title: Semiconductor device
Inventor: KONDO MASANORI
IPC: H03F3/343
Filed: 1991-08-28
Abstract: PURPOSE:To improve the generality of a semiconductor device including an operational amplifier by allowing a user to set up several characteristics for the operational amplifier built in the semiconductor device by means of a program. CONSTITUTION:The operational amplifier is provided with plural constant current sources 109, 110, plural PMOS switches 111, 112 for turning on/off the constant current sources 109, 110 and plural constant current source selecting registers 113, 114 for applying signals to the switches 111, 112. When '1' and '0' are written in the registers 113, 114, the switches 111, 112 are turned on and off and the level of a current supplied to an output stage is changed. Thereby the reduction of the current to the output stage suppresses the power consumption of the operational amplifier, and when the current is increased, the response speed or driving capacity of the amplifier can be improved.
Patent JP-H01301952-A (JP)
Title: Fuel injection pump
Inventor: ISHIKAWA HIDEAKI
IPC: F02M41/14
Filed: 1988-08-30
Abstract: PURPOSE:To enable a fuel injection pump to make high speed rotation regardless of its multi-cylinder type with small size and weight by installing individual ejected fuel passages independently from each other for the sake of plungers housed in cylinders arranged radially from a pintle as the center. CONSTITUTION:Plungers 10a to 10d pushed onto the inner wheel of a cam ring 21 in the state of the cam ring 21 eccentric to a rotor 4 make sliding motion inside cylinder holes 9a to 9d when the rotor 4 makes rotation. And when the plungers 10a to 10d are positioned on respective fuel intake grooves, fuel is absorbed therein and on respective fuel discharge grooves, fuel is ejected therefrom. Hereat, individually independent fuel discharge grooves and fuel discharge passages are provided for respective plungers 10a to 10d. Since each cylinder can be provided with one plunger out of 10a to 10d, high speed rotation is possible regardless of a multi-cylinder type. In addition, small size, light weight and small number of parts can be realized by installing plungers 10a to 10d in radial cylinder holes 9a to 9d arranged radially from a pintle 8 as the center.
Patent JP-H05106169-A (JP)
Title: Sizing agent composition
Inventor: IDE KAZUTOSHI
IPC: C09J137/00
Filed: 1991-08-28
Abstract: PURPOSE:To provide a sizing agent composition containing a specific component, capable of finishing clothes, sheet, etc., in a state having particularly high stiffness, comfortable to the skin and easily removable by washing. CONSTITUTION:The objective sizing agent composition capable of finishing clothes, sheet, etc., in a state stiff and comfortable to the skin compared with conventional sizing agent is produced by mixing (A) a copolymer emulsion of a lower fatty acid vinyl ester (preferably vinyl acetate, etc.) and an unsaturated carboxylic acid [preferably (meth)acrylic acid, etc.] and (B) a copolymer emulsion of a lower fatty acid vinyl ester and N-vinyl-2-pyrrolidone at a weight ratio (A:B) of 10:90 to 90:10. Addition of a cationic polymer such as cationic cellulose is preferable in order to improve the adsorptivity to the fiber at high bath ratio. The sizing agent can easily be removed by washing. The agent is suitable especially for the starching of bed sheet, etc.
Patent JP-H0555826-A (JP)
Title: Receiver
Inventor: SHIGA NOBUO
IPC: H01Q21/24
Filed: 1991-08-28
Abstract: PURPOSE:To attain compactness and high performance in a receiver provided with a plane antenna and receiving circuit connected thereto. CONSTITUTION:A silicone substrate 1 obtained by forming a half-insulating compound semiconductor layer 5 on a part of a surface by crystal growth is used as a substrate, a plane antenna 2 consisting of one or plural antenna elements 4 is formed on the surface of the substrate 1 except the area on which the layer 5 is formed and a receiving circuit 3 to be connected to the antenna 2 is formed on the layer 5. Since the antenna 2 and the circuit 3 are mounted on the same substrate, the size and weight of the whole receiver can be reduced, and since the antenna 2 is formed on the substrate 1 having a comparatively small dielectric constant epsilon, band width can be extended. Although the monolithic formation of a high frequency receiving circuit on a silicone substrate is generally difficult, such difficulty can be removed in this invention forming the receiving circuit 3 on the half-insulating compound semiconductor layer 5.
Patent JP-H1063755-A (JP)
Title: Voltage adding circuit
Inventor: KIMURA KATSUHARU
IPC: H01L27/04
Filed: 1996-08-19
Abstract: PROBLEM TO BE SOLVED: To provide a voltage adding circuit reduced in voltage and improved in frequency characteristic. SOLUTION: The voltage adding circuit has a 1st differential pair equipped with a 1st and a 2nd transistors Q1 and Q2, and a 2nd differential pair equipped with a 3rd transistor Q3 and a 4th transistor Q4 which are connected to each other with a diode. Then, one of the 1st and the 2nd transistor Q1 and Q2 and the 3rd transistor Q3 are commonly connected to each other and forming an output terminal, and a current source having a current value equivalent to the driving current of the 1st and the 2nd differential pairs is provided as common load.
Patent JP-H1164450-A (JP)
Title: Semiconductor-testing device
Inventor: SASAKI HISAMI
IPC: G01R31/28
Filed: 1997-08-12
Abstract: PROBLEM TO BE SOLVED: To easily diagnose a GO/NO-GO of a tester bus via a plurality of units by latching address data on an AD bus that returns to the reception terminal of a bus controller using a data latch register. SOLUTION: First, a selector 34 sets a mode-switching register 36 in advance so that a signal at the side of an OR gate 32 can be outputted. Address data and a write control signal are outputted at the same clock timing from the transmission of a bus controller onto an ADO bus. Therefore, a write control signal received at the reception terminal side of the bus controller is supplied to a data latch register 62 via an OR gate 32 and a selector 34. As a result, the address data on the ADO bus at the reception terminal side are latched. A GO/NO-GO can be judged by allowing a CPU to read the data. If the data is not matched with the value of an address register 52 that is a transmission terminal side, it can be easily judged that some sort of transmission failure has occurred at the AND transmission line of a tester bus.
Patent JP-H0882490-A (JP)
Title: Heat exchanger
Inventor: GOTO KOICHI
IPC: F28C1/00
Filed: 1994-09-12
Abstract: PURPOSE: To lessen the quantity of a second liquid, such as refrigerant, which flows into a first liquid used as heat source, etc., in a direct contact type heat exchanger. CONSTITUTION: A heat exchanger is composed of a stagnant part 4 into which a first liquid 1 having a first specific gravity and a first temperature flows and out of which it flows out, a second liquid-injecting part 6a from which a second liquid 7 being insoluble in the first liquid 1 and having a second specific gravity greater than the first specific gravity and a second temperature differing from the first temperature is injected from above the stagnant part 4, at least one plate-shaped member 10a which is disposed in the stagnant part 4 with the longitudinal direction set from the second liquid-injecting part 6a to the bottom of the stagnant part 4 and designed to make the second liquid 7 flow, injected from the second liquid-injecting part 6, on the surface, and a second liquid-recovering part 8 for recovering the second liquid 7 from under the stagnant part 4.
Patent JP-H1158587-A (JP)
Title: Antioxidizing packaging film
Inventor: KOMATSU HIROYUKI
IPC: H05K3/38
Filed: 1997-08-12
Abstract: PROBLEM TO BE SOLVED: To provide an antioxidizing packaging film preservable for a long period by hermetically sealably packaging an object. SOLUTION: The packaging film comprises a laminated film obtained by forming a diamond-like carbon film having hydrogen concentration of 50 atomic % or less and oxygen concentration of 2 to 20 atomic % on at least one side surface of a plastic film. Since barrier properties of the oxygen and steam are excellent, if it is used as a packaging film for a disposable body warmer, metal powder, sputtering target, or printed circuit board, it can be preserved for a long period.
Patent JP-H0555096-A (JP)
Title: Device for positioning tab terminal
Inventor: ASO HIROYUKI
IPC: H01G13/00
Filed: 1991-08-28
Abstract: PURPOSE:To provide a device for positioning a tab terminal, in which a flat part can be safely positioned without damage in the device for positioning the terminal to horizontally position the flat part of the terminal to be connected to an electrode foil of an aluminum electrolytic capacitor. CONSTITUTION:The device for positioning a tab terminal, comprises a rotary chuck 5 for holding a CP wire 1 of a tab terminal 3, a conveying chuck 4 for supporting the wire 1, a light source 7 opposed through a flat part 6 of the terminal 3, and a photosensor 8, and detects the amount of a shade of the float part of the sensor 8 to rotatably control the chuck 5, thereby horizontally positioning the flat part 6.