Patent GB-1361849-A (GB)
Title: Digital data cyphering technique
IPC: H04L9/00
Filed: 1971-10-20
Abstract: 1361849 Digital transmission; ciphering systems DATOTEK Inc 20 Oct 1971 [15 April 1971] 48722/71 Heading H4P A ciphering system has a device comprising a non-linear cyclic sequential stepping circuit actuable by input signals to provide a count which is stepped forwardly, e.g. by pseudo random means, to provide a ciphered output signal. The system may have a means for comparing clear text signals with corresponding ciphered signals and generate an alarm from lack of correspondence for a determined number of signals. The comparison device may include a counter also an arrangement for preventing transmission and/or recording unless such correspondence is achieved. The system may also include an arrangement for inhibiting operation if the frequency of clock signals is increased beyond a determined value in order to restrict unauthorized computer analysis of the ciphered signals. In a main mode of operation a terminal, e.g. teleprinter, develops clear text recorded on punch tape which is then ciphered and again recorded on tape, the cipher being set manually by an operator. The ciphered tape is then transported physically, or transmitted by line, to a distant receiver for the reverse process to take place, a corresponding cipher being also set up at the receiver. If the ciphered and clear texts do not correspond an alarm is operated and operation is arrested. The arrangement operates by moving a character random numbers r of places in a telegraph alphabet, i.e. in Table 1 (not shown), if r = 4 an "H" will be sent out as "L", but forbidden characters are not included, i.e. for r = 4 count will be 5. The next and immediate subsequent characters will be moved different numbers of places in a pseudo random sequence. Random code generator 44, Fig. 5, which may comprise a pseudo random source, i.e. interconnected non-linear feedback shift registers, is initially set by insertion of manually selected numbers, e.g. set by thumbwheel switches (not shown) after which the register outputs are modulo 2 added, the output being received by register 152 clocked through NOR 154 controlled by NOR 156. Five SHIFT pulses may be provided for each data word, hence each key word generated by 44 may have 32 combinations which are converted into binary equivalent. Conversion circuit 158 receives each of three "forbidden" combinations and converts into specified ones of the remaining 29. Additional "forbidden" words may be included by adding additional circuits. Outputs from 152, 158 pass through OR 182, NAND 184 to flip-flop 186 which is part of a synchronous up (decode)-down (code) counter 188. A count limit signal is developed in NAND 206. When a "forbidden" word is detected an inhibit signal INHCT, see Fig. 6, is applied to gate 190 thus causing an additional count, i.e. 4 increased to 5. Plain text PT is applied through register 250, Fig. 6, to non-linear sequential stepping circuit which may comprise a synchronous counter 256. Gate 268 detects a figures character which is converted into a line feed signal. In operation a word is placed into counter 256 which is clocked until a limit signal (42) has been reached when it is shifted to 8-bit register 284. When coding data in register 250 is in plain text and in counter 256 in cipher but conversely when decoding on reception. Clear/cipher characters Q, K, LTRS are entered through a teleprinter keyboard and are detected by gates 306, 310. Outputs from counter 256 are detected via inverters 330-334 and NOR gates 336, 340 and NOR 342 which generates INHCNT signal applied to gate 190, Fig. 5. If a figures character is fed into register 250 this is changed into an LF signal. If the frequency of clock signals is changed by unauthorized replacement by a higher frequency crystal, a detection circuit including a monostable multivibrator (138), Fig. 3 (not shown), will become continuously fired at double design frequency hence a signal RKisnot provided to circuit (42) and a detector (50) will place the circuit in an alarm state. A further arrangement described with reference to Fig. 8 (not shown), prevents clear text from being transmitted when the arrangement is in a cipher mode. Before transmission, 25 bits are checked and if correct the system is allowed to operate in cipher. Other formats e.g. 8 bit code may be employed.