Patent GB-1137786-A (GB)
Title: Data processing systems
IPC: G06F13/18
Filed: 1967-06-21
Abstract: 1,137,786. Data processing systems. INTERNATIONAL BUSINESS MACHINES CORP. 21 June, 1967 [25 June, 1966], No. 28527/67. Heading G4A. In a data processing system, decoding of an instruction by a central processing unit causes sequential accessing from main storage of first and second control informations which specify the addresses of a control item and a data item, a special purpose peripheral processor performing an arithmetic operation specified by the control item on the data item. Switching units associated with groups of input/output peripheral units time-share a data-and-control bus connected to a first channel unit. Peripheral processors time-share a data-and-control bus connected to a second channel unit. A central processing unit instruction can provide addresses to select a channel unit and specify one of the peripheral devices associated with it, the channel unit obtaining from main storage a channel command word through the agency of a channel address word. The channel command word specifies a peripheral operation, an initial main storage address to take part in any data transfer, and a count field for message length, and can call for another channel command word for use next. The peripheral device involved recognises its address (from the original instruction) and sends its address to the channel unit for a check comparison, Subject to this and satisfactory device status, operation proceeds. A channel unit essentially as in Specification 1,062,225 is described. Peripheral processor.-A peripheral processor described calculates sums of products employable to form cross-correlation and auto-correlation functions, the operands F y  and S n+y-1  representing filter and sample data respectively. The processor generates from one to six of these sums at a time, six registers for sample operands and one (backed by a buffer register) for a filter operand being provided. Overlapping groups of two and three bits in the filter register are decoded to select the amount of shift to be given to a sample operand from one of the sample registers before accumulation in one of six result registers using a carry-save adder and a carry-lookahead adder. A local store, fed from the central processing unit under control of channel command words as described above, holds the sample and filter operands prior to their transfer to the respective registers and also holds the sums of products from the result registers until transfer to the main storage under control of channel command words. Various address registers (providing addresses for addressing the local storage) are preloaded from the main storage and subsequently can be incremented by two or by the contents of a programme-settable further register. Length registers controlling numbers of iterations are also preloaded from the main storage and can be decremented by one, repetitively to zero. The formation of sums of products is checked by comparison of before and after modulo-3 residues. The peripheral processor converts negative data from the main storage (as indicated by a sign bit) to twos-complement form so that the sum of products process may be done on both positive and negative operands.