Patent GB-794078-A (GB)
Title: Improvements in or relating to electrical equalizer circuits
IPC: H04L25/03
Filed: 1956-04-18
Abstract: 794,078. Equalizing networks. WESTERN ELECTRIC CO., Inc. April 18, 1956 [April 22, 1955], No. 11792/56. Class 40 (8). An equalizing circuit comprises an unbalanced delay line and means for deriving a main signal from the centre of the line and impressing it upon a summing circuit, the summing circuit being connected to spaced points on both halves of the delay line whence a series of leading and lagging voltages are derived. The input signal is applied to terminals 1, 2 of the unbalanced delay line 16, 18 which is terminated in a matching impedance 5. The main signal is taken off at the centre of the delay line by a hybrid circuit 6 and applied through an alternating pad 7 and an unbalanced-to-balanced transformer 19 to a summing network 8 and thence through a transformer 20 to signal output terminals 3, 4. The remaining part of the input signal is applied to the second half 18 of the delay line which is conjugated by the hybrid with the pad 7. The delay line comprises an even number of matched delay networks 10 to 15 which may have lumped elements or may comprise coaxial cables. Each network has a linear phase-shift which increases by an integral multiple (including unity) of 180 degrees over the band, the phase-frequency characteristics being equal in pairs, e.g. networks 10 and 15 have the same characteristics. Three leading voltages are derived from points 36, 42, 48 on the first half 16 of the delay line and are applied through attenuating pads 37, 41, 46 to variable tapping points 30, 31, 32 on shunt resistors 24, 25, 26 of the summing circuit, these tapping points being also connected through dropping resistors 39, 43, 47 to points 38, 44, 49 on the second half 18 of the delay line whence three lagging voltages are derived. The pads 37, 41, 46 afford impedance transformation and are selected in relation to the resistors 39, 43, 47 to provide pairs of leading and lagging voltages of the same magnitude. Assuming that the networks 10 to 15 each have a phase-shift varying linearly from zero to 180 degrees over the band the equalizer will provide fundamental, second and third harmonic, cosine-shaped pure loss or pure delay characteristics which can be controlled independently by the variable tapping points 30, 31, 32. If it is desired to obtain pure delay equalization shapes the hybrid network 6 is so constructed and the terminals 50, 51 so connected that the input signal is reversed in phase as it passes from the first to the second half of the delay line. To obtain pure loss shapes the phase reversal is eliminated by reversing the connections to terminals 50, 51 or by altering the hybrid circuit. The circuit also provides another type of equalization for which purpose tapping points on shunt resistors 21, 22, 23 are connected through dropping resistors either to the leading voltage points 36, 42, 48 (as shown) or to the lagging voltage points 38, 44, 49. Adjustment of the tapping points controls three harmonically related, cosine-shaped, loss characteristics and three associated harmonically related, cosineshaped, minimum-phase delay characteristics. If the connections are made to points 36, 42, 48 the associated delay will be negative, i.e. it will be the negative of the delay produced by a minimum-phase circuit producing the same loss. This embodiment is preferred when the circuit is associated with a fixed delay equalizer. Where there is no fixed delay equalizer connections are preferably made to points 38, 44, 49 to obtain positive delay. If the pairs of voltages at tapping points 30, 31, 32 provide pure delay equalization, the combined characteristics are first adjusted to minimize loss distortion. The tapping points 30, 31, 32 are then adjusted to minimize delay distortion. If the tapping points 30, 31, 32 provide pure loss adjustment the phase distortion is dealt with first and the loss distortion afterwards. The circuit may include any number of pairs of delay networks.