Patent GB-1321911-A (GB)
Title: Multiprogrammed digital computer having store-protection means
IPC: G06F12/14
Filed: 1970-06-10
Abstract: 1321911 Store protection KOMBINAT ROBOTRON VEB 10 June 1970 28136/70 Heading G4A A multiprogrammed digital data processing system includes a plurality of units including processing units, channels, and the like, a main memory to which said units may have access, a plurality of store protection devices operative to prevent units with which they are associated from making unauthorized main memory accesses, there being more units than store protection devices, and allocating means adapted to allocate respective ones of said store protection devices to individual units requesting access to said main memory until all said protection devices are allocated to respective ones of the units, and, when all said store protection devices are so allocated and a further unit makes a request for access to said main memory, to withdraw the store protection device allocated to the unit which has made fewest access requests within a predetermined period from that unit and to allocate the withdrawn protection device to said further unit. As described there are three protection devices which are allocated to the requesting units 49- 56 by a device which includes a set 20-27, 28-35, and 36-43 of flip-flops for each protection device, there being one flip-flop for each unit 49-56 within each set. Each unit is connected to its associated flip-flop in each set via two AND gates, only the gates 70-75 associated with unit 49 being shown. The access request lines from each unit feed an OR gate 47 and a counter is provided for counting the number of protection devices allocated to units at any time. Initially all the flip-flops are reset and signal #48A (from the counter) is high indicating that not all the protection devices are allocated. The signals 11F, 12F, and 13F from AND gates 60, 61, and 62 are also high since all flip-flops are reset. However the outputs of OR gates 63 and 64 are low since no flip-flops are set so that of the AND gates 71, 73, and 75 only 71 is enabled (and likewise all the corresponding gates for flip-flops 21-27). Thus when a unit 49-56 makes an access request the corresponding flipflop 20-27 is set and the first protection device is allocated (by means not described) to the requesting unit. AND gate 60 is thus blocked and OR gate 63 enabled so that AND 71 is blocked and AND 73 enabled. The next access request thus sets the corresponding one of flipflops 28-35 and so on. When all the protection devices have been allocated signal 48A goes high and all the gates 71, 73, and 75 are blocked by 48A. When a further unit makes a request for memory access OR 47 conducts and a set of three AND gates are enabled. These AND gates are connected to three comparators which compare the contents of respective pairs of three counters which count the number of access requests made by units having a protection device allocated to them. The AND gate corresponding to the protection device associated with the smallest count conducts and that protection device is withdrawn from its unit by means of signals 20-27/A, 28-35/A, 36-43/A which reset the corresponding set of flip-flops 20-27, 28-35, 36-43. The corresponding AND gate 70, 72, or 74 is enabled and the further requesting unit sets its associated flip-flop via the enabled gate 70, 72, 74.