baber/WOPTO huggingface dataset:
Patent TW-425625-B (TW)
Title: Method of producing semiconductor wafer
Inventor: KATAOKA MAKOTO
IPC: B24B37/04
Filed: 1998-11-17
Granted: 2001-03-11
Abstract: The object of the present invention is to provide a method of producing a semiconductor wafer, which can prevent the breakage of the wafer due to one series of operation of grinding the back surface of the semiconductor wafer, and which can reduce the working time. The present invention also provides a method of producing a semiconductor wafer wherein an adhesive tape is applied on the surface of the semiconductor wafer and, after grinding the back surface of the semiconductor wafer using a grinding machine, the adhesive tape is peeled off. The present further provides a method for manufacturing semiconductor wafer, which is characterized in using an adhesive tape having heat contractibility as the adhesive tape, grinding the back surface of the semiconductor wafer and heating the adhesive tape in the grinding machine, thereby peeling off the adhesive tape from the surface of the semiconductor wafer in the grinding machine.
Patent TW-554132-B (TW)
Title: Process for reconditioning oil and apparatus for removing volatiles from engine oil
Inventor: DEPAUL MICHAEL T
IPC: B01D35/30
Filed: 1999-01-13
Granted: 2003-09-21
Abstract: Apparatus and methods for improved in-line contaminant removal from engine lubricating oil are provided which employ gravity to achieve a desired flow rate of oil. The invention is adapted for use with an existing engine oil lubrication system and continuously processes a side stream that after processing, is returned to the engine oil. During processing, the oil is first filtered and then drained and deposited upon the upper central surface portions of a heated dome whereon the oil forms a thin film from which relatively low boiling volatile impurities (especially water) are rapidly separated in a gaseous state. The gas is vented through a pressure relief valve to the manifold while the recovered reconditioned oil is collected and recycled.
Patent TW-439342-B (TW)
Title: An external charging/discharging device
Inventor: LI YING-WEI
IPC: H01M10/44
Filed: 1999-02-01
Granted: 2001-06-07
Abstract: An external charging/discharging device which can directly charge the battery set, or charge the battery set after discharging, so that users can proceed the charging/discharging of the battery set to increase the accuracy of the internal detection device of the battery and the lifetime of the battery set.
Patent TW-414975-B (TW)
Title: Method of forming SiON layer
Inventor: YAU LIANG-JI
IPC: H01L21/322
Filed: 1999-03-30
Granted: 2000-12-11
Abstract: A method of forming a SiON layer with anti-reflection effect and low leakage current is provided. The anti-reflection SiON layer has a leakage current smaller than 1.0 pA/cm2 at about 10 Volts. The method comprises depositing a SiON film on a semiconductor substrate by plasma enhanced chemical vapor deposition process (PECVD). The anti-reflection SiON layer having suitable n and k constants and low leakage current is formed in the ratio of SiH4 to N2O under 2.5 and the radio frequency (RF) power over 120W as an etching stop layer or a CMP stop layer for a dielectric layer in subsequent process.
Patent TW-512137-B (TW)
Title: Low-temperature crystallization of ceramic films by high-pressure processing
Inventor: LIU TZUNG-SHIN
IPC: H01L21/316
Filed: 1999-05-03
Granted: 2002-12-01
Abstract: A process is disclosed for reducing the crystallization temperature of amorphous or partially crystallized ceramic films by providing a higher pressure under which the crystallization of the amorphous or partially crystallized ceramic films can be significantly enhanced. The present invention not only improves quality, performance and reliability of the ceramic films, but also reduces the cost for production. By lowering the crystallization temperature, the cost for thermal energy consumed during the crystallization process is greatly reduced. In addition, the interaction or interdiffusion occurring between films and substrates is significantly suppressed or essentially prevented, avoiding the off-stoichiometry and malfunction of thin films, which usually occur in the conventional high-temperature crystallization processes. The process of present invention also decreases the grain size of formed films, thus reducing the roughness of films and producing relatively smooth, good quality films. This process made possible the fabrication of ceramic films with larger area at substantially lower temperatures without using other excitation energy such as laser, ion beam or electron beam, and is applicable to very large scale integrated circuit technologies. The present invention finds broad applications including manufacturing electronic and optical devices such as ferroelectric memories, capacitors, actuators, piezoelectric transducers, pyroelectric sensors, gas sensors, electro-optic displays, electro-optic switching, non-liner optical devices, and reflective/antireflective coating, etc.
Patent TW-522350-B (TW)
Title: Systems for dynamic smartcard synchronization and personalization
Inventor: HOHLE WILLIAM
IPC: G06Q20/40
Filed: 1999-05-05
Granted: 2003-03-01
Abstract: A system generally for personalizing and synchronizing smartcard data in the context of a distributed transaction system is disclosed. A dynamic smartcard synchronization system comprises access points configured to initiate a transaction in conjunction with a smartcard, an enterprise data collection unit, and a card object database update system. An exemplary dynamic synchronization system (DSS) preferably comprises various smartcard access points, a secure support client serve, a card object database update system (CODUS), one or more enterprise data synchronization interfaces (EDSI), an update logic system, one or more enterprise data collection units (EDCUs), and one or more smartcard access points configured to interoperab1y accept and interface with smartcards. In an exemplary embodiment, DSS comprises a personalization system and an account maintenance system configured to communicate with CODUS. Persona1iztion of multi-function smartcards is accomplished using a security server configured to generate and/or retrieve cryptographic key information from multiple enterprise key systems during the final phase of the smartcard issuance process.
Patent TW-445412-B (TW)
Title: Method and apparatus for power mode transition in a multi-thread processor
Inventor: TOLL BRET L
IPC: G06F1/32
Filed: 1999-05-21
Granted: 2001-07-11
Abstract: A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.
Patent TW-509725-B (TW)
Title: High strength zirconium alloys containing bismuth and niobium
Inventor: VAN SWAM LEONARD F P
IPC: G21C3/06
Filed: 1999-06-08
Granted: 2002-11-11
Abstract: High strength zirconium alloys with improved strength and creep resistance having 1.5 to 6 weight percent bismuth, and niobium.
Patent TW-407321-B (TW)
Title: Manufacture method of the copper barrier layer in the integrated circuit
Inventor: LIOU CHUNG-SHI
IPC: H01L21/3205
Filed: 1999-06-10
Granted: 2000-10-01
Abstract: This invention discloses a manufacture method of the copper barrier layer in the integrated circuit. The manufacture method is provided to form the barrier layer for manufacturing copper trench by sequentially utilizing a PVD process and a CVD process before depositing copper layer. The physical vapor phase deposition barrier layer provides a better adhesion force, and the chemical vapor phase deposition barrier layer provides better step coverage ability, so that the stack-type multi-layer barrier layer structure manufactured by this invention has the characteristics of solid, being not easy to peel off, being able to prevent the short circuit problem caused by the spike phenomena in the copper silicon interface, and having a lower and uniformly distributed resistance.
Patent TW-465159-B (TW)
Title: Surface mount electrical device with multiple PTC elements
Inventor: SWENSEN ROBERT G
IPC: H02H9/02
Filed: 1999-08-05
Granted: 2001-11-21
Abstract: A surface-mountable electrical circuit protection device comprising first and second laminar PTC elements, each having first and second surfaces. The PTC elements are electrically connected in parallel. A first electrode is attached to the first of the first PTC element and a second electrode is attached to the second surface of the second PTC element. A third electrode, having an electrical resistance is positioned between the first and second laminar PTC elements. The third electrode is connected to the second surface of the first PTC element and the first surface of the second PTC element and has a main portion and a sub-portion. The main portion of the third electrode is separated from the sub-portion by an element having a higher electrical resistance than the electrical resistance of the third electrode. A first electrically conductive end termination wraps around a first end of the device and is in electrical contact with the first and second electrodes. A second electrically conductive end termination wraps around a second end of the device and is in electrical contact with the third electrode. The stacked configuration of the PTC elements allows for an increased electrical rating without increasing the overall footprint, i.e., length and width, of the device.
Patent TW-390982-B (TW)
Title: Time output apparatus and time correction method
Inventor: KAWAI EIJI
IPC: G04C9/04
Filed: 1999-08-25
Granted: 2000-05-21
Abstract: An automatic time difference correction apparatus includes an RTC (Real Time Clock) circuit which outputs standard time information that indicates an absolute standard time, a time difference table 3 which holds time difference information that indicates the time difference between the absolute standard time and the time at a certain position corresponding to positional information that indicates that position, a GPS (Global Positioning System) decoder which acquires current-position information that indicates the current position a GPS receiver an antenna, a comparator which obtains time difference information corresponding to the current position by comparing the positional information and the current-position information and a computing element which calculates the time at the current position based on the time difference information corresponding to the current position and the standard time information.
Patent TW-I230284-B (TW)
Title: Insulated-gate transistor signal input device and array substrate
Inventor: ANDO KOTARO
IPC: H03K5/08
Filed: 1999-09-22
Granted: 2005-04-01
Abstract: An insulated-gate transistor signal input device includes an insulating substrate, a first line formed on the insulating substrate to receive a signal externally supplied, an insulating-gate transistor signal processing circuit formed on the insulating substrate to process the signal supplied from the first line, a second line formed on the insulating substrate to input a signal obtained from the insulating-gate transistor signal processing circuit to a load circuit formed on the insulating substrate. The insulated-gate transistor signal input device further includes a first protection diode circuit connected to the first line to remove electrostatic charge from the first line, and a second protection diode circuit connected to the second line to remove surge voltages from the second line.
Patent TW-437200-B (TW)
Title: A variable sleep mode for mobile stations in a mobile communications network
Inventor: WILLARS PER
IPC: H04L12/56
Filed: 1999-10-16
Granted: 2001-05-28
Abstract: A sleep cycle of a mobile station may be optimally varied depending upon one or more conditions relating to the mobile station's operation. Based on one or more of those conditions, a variable wake up parameter is determined and used to establish times when the mobile station automatically leaves a lower power mode and enters a higher power mode to listen for a page. The mobile station's variable wake up parameter is provided to a radio access network and to one or more core networks to permit coordination of communications and services with the mobile station.
Patent TW-436445-B (TW)
Title: Shock absorbing system for bicycle
Inventor: MARTIN DANIEL JOSH
IPC: B62K25/04
Filed: 1999-10-26
Granted: 2001-05-28
Abstract: Disclosed is a shock absorbing system for bicycle, which the shock absorbing system apparatus is positioned at an appropriate location of an upper tube of a frame body, causing the rear fork tube and the middle tube to be connected and positioned at an appropriate location of the shock absorbing system, so as to eliminate assembly of revolving shaft structure after installation. Due to the revolving shaft point and the shock absorber which carry out the shock absorbing efficacy are located at the same action point, the structure of the entire frame body can be precisely simplified. Owing to the shock absorbing efficacy carried out by the shock absorbing system, the rider is free from the feeling of tossing and discomfort.
Patent TW-479119-B (TW)
Title: Planar light source illumination system and the manufacturing method thereof
Inventor: WEN CHI-JAIN
IPC: F21S6/00
Filed: 1999-11-11
Granted: 2002-03-11
Abstract: A planar light source illumination system having diffractive grating structure and the manufacturing method thereof are disclosed. The light source illumination system of the present invention comprises a light-emitting device, light source reflection mask and light guide plate having light re-directional device. The light re-directional device of the light guide plate has a diffractive grating structure. The diffractive grating utilizes the condition satisfying Bragg condition to deflect the light in the light guide plate into the direction toward the display, so that it can provide the display with uniform planar light source. The planar front light source or the back light source system can be accomplished based on the component devices and manufacturing method of the system of the present invention. One of the preferred embodiments of the present invention utilizes a phase-diffractive grating as the light re-directional device of this light source illumination system, so that the light illumination system of the present invention has a high light re-directional efficiency and transmittance, and reduces the degradation of the image quality.
Patent TW-451139-B (TW)
Title: A cache memory system
Inventor: KUNG SHAO-TSU
IPC: G06F12/08
Filed: 1999-12-03
Granted: 2001-08-21
Abstract: A cache memory system of a computer. The computer comprises a processor, an address bus for transmitting a data address which can access one storage cell in the main memory, and a data bus for transmitting data. The data address contained in the address bus comprises a low-order portion defined as a cache line address and a high-order portion defined as a block address. The cache memory system comprises a cache data memory having a plurality of cache lines for storing data, a first cache tag memory having a plurality of tag cells for storing block addresses of data stored in the corresponding cache lines of the cache data memory, a second cache tag memory having a plurality of tag cells for storing block addresses of the cache lines of the cache data memory currently transmitted from the address bus. When the processor accesses the cache memory system, if the block address of the data address has cache misses with both the first and second block addresses, the second block address will be replaced with the block address of the data address. If the block address of the data address has a cache miss with the first block address but has a cache hit with the second block address, the data stored in the corresponding cache line of the cache data memory will be replaced.
Patent TW-436615-B (TW)
Title: Decal with multiple concealing features that selectively display or conceal temperature sensors according to ambient temperature
Inventor: LIMBURG RANDY MARTIN
IPC: G01K11/16
Filed: 1999-12-28
Granted: 2001-05-28
Abstract: A decal has multiple temperature sensors that individually appear within certain concealing features of the decal in accordance with different prescribed temperatures, otherwise blending into the concealing features and thereby disappearing into the design. The decal may depict an image of an animal, fish, flower, abstract form, or another design, such as a photograph, cartoon, sketch, or other representation. The image includes multiple separate concealing features, such as spots, fins, flower petals, abstract shapes, or other components of the decal's image. These features may have one color in common, or different concealing features may have different colors. The feature color(s) contrasts with one or more background colors in the design, which serve to visually separate the concealing features. The temperature sensors are scattered throughout the design in a visually pleasing manner. Importantly, the sensors are placed within the concealing features, where the non-activated color of each temperature sensor matches its surrounding concealing feature. Thus, non-activated sensors become completely camouflaged within their surrounding feature color(s). The temperature sensors comprise a formulation that reacts to changes in temperature by changing color, and may comprise a thermochromic liquid crystal (TLC) material, for instance. Each temperature sensor is activated by a different ambient temperature range.
Patent TW-440980-B (TW)
Title: Package with an innovation substrate having an embedding capacitor to reduce the signal noise
Inventor: WU CHUNG-JU
IPC: H01L21/60
Filed: 2000-01-28
Granted: 2001-06-16
Abstract: The package of the present invention comprises a substrate which has a grounding ring and a power ring formed on the upper surface of the substrate; a chip configured on the substrate; a golden wire used to connect the chip with the substrate; an encapsulation covering over the chip and the substrate for protecting the chip and the conductive wires; a conductor ball grid formed on the lower surface of the substrate for transmitting the signal; and, at least a capacitor to be formed on the substrate for eliminating the coupled noise. The inventive design is to only reserve the pad of de-coupled capacitor for connecting to the power ring and the grounding ring while making layout on the substrate surface.
Patent TW-I262214-B (TW)
Title: Process for determination of microbial contamination
Inventor: BURI MATTHIAS
IPC: C12Q1/04
Filed: 2000-01-29
Granted: 2006-09-21
Abstract: The present invention discloses a process for quantitative and/or qualitative determination of the microbial contamination of suspensions, emulsions or dispersions containing minerals and/or pigments and/or fillers and/or fiber materials wherein following the addition of one or more substances which can be degraded by microorganisms, mixing and optionally subsequent incubation a sample of the suspensions, emulsions or dispersions is centrifuged to separate the microorganisms from the minerals and/or fillers and/or pigments and/or fiber material and the number and/or size and/or type of the microorganisms is determined in the aqueous supernatant phase after one or more incubations.
Patent TW-457168-B (TW)
Title: Chemical mechanical polishing processes and components
Inventor: JIN RAYMOND R
IPC: B24B37/04
Filed: 2000-07-21
Granted: 2001-10-01
Abstract: A substrate is chemical mechanical polished first with a single layer hard polishing pad and a high-selectivity slurry until a first endpoint is reached, and then with a soft polishing pad and a low-selectivity slurry until a second endpoint is reached. Dishing is reduced when low-selectivity slurry is used at the second polishing step. Low within-wafer-non-uniformity is achieved by using a single layer hard pad at low pressure at the first polishing step.
Patent TW-477794-B (TW)
Title: Biodegradable copolymer and preparation process thereof
Inventor: TSAI JING-JIUN
IPC: C08F16/06
Filed: 2000-03-24
Granted: 2002-03-01
Abstract: The present invention relates to a new biodegradable copolymer of starch and polyvinyl alcohol, which is characterized in using a maleic anhydride as an interface modifier and exhibits excellent cross-link between starch and polyvinyl alcohol, and therefore results in a biodegradable copolymer with good physical properties. The present invention also relates to a method for producing the new biodegradable copolymer.
Patent TW-478055-B (TW)
Title: Method for polishing
Inventor: KONDO SEIICHI
IPC: H01L21/321
Filed: 2000-04-08
Granted: 2002-03-01
Abstract: This invention provides a method for polishing. The problem to be solved is how to provide a polishing method which can inhibit occurrence of scratch, peeling, dishing or erosion and also realize a high speed polishing treatment. The solution is to use a slurry comprising an oxidizing substance, a substance for dissolving the oxidized substances in water, a thickening agent, and water.
Patent TW-526436-B (TW)
Title: Design database for integrated circuit device and design method for integrated circuit device
Inventor: OTA MITSUHO
IPC: G06F17/50
Filed: 2000-04-28
Granted: 2003-04-01
Abstract: The present invention provides a design database stored with integrated circuit devices under the optimized inspection scheme, and a design method for optimized inspection scheme. After receiving the design request, the optimized means for fault inspection scheme 800 will select the RT-level VC (RT-VC) and fault inspection method from the VCDB 100, wherein the design request includes the request for system LSI (area, pin number, inspection time, prior constraint weighting information), and VC information. The optimized means for fault inspection scheme 800 execute the optimized operation considering all kinds of parameters, and create the optimized fault inspection scheme and a chip fault inspection control circuit. The VCDB 100 stores a plurality of VCs with same function but different inspection schemes, and weights the parameters influencing the inspection cost, and finally selects the inspection scheme making the total inspection cost minimized.
Patent TW-I258500-B (TW)
Title: Chemical mechanical polishing slurry composition
Inventor: LIOU RU-SHI
IPC: C09K13/00
Filed: 2000-06-07
Granted: 2006-07-21
Abstract: This invention provides a chemical mechanical polishing slurry composition, which roughly includes: (a) gamma phase aluminum oxide abrasive particle, (b) alpha phase aluminum oxide abrasive particle and (c) silicon dioxide abrasive particle. The novel slurry can raise the polishing rate toward the metal layer to achieve the purpose of time-saving in the process and is advantageous to the mass production.
Patent TW-479190-B (TW)
Title: Cursor input system composed of camera
Inventor: JUANG DA-CHANG
IPC: H04N1/58
Filed: 2000-07-27
Granted: 2002-03-11
Abstract: The present invention is a cursor input system composed of a camera, which comprises a pen-shape moveable light emitting device with LED at the pen point which can emit at least two types of colored light according to the movement of user operation; and, a camera connecting to a computer device for capturing the light from the moveable light emitting device and determining the color of the light and converting the captured moving trace for the spots of the moveable light emitting device to XY coordinates so as to provide the computer device with cursor input function that the user can conveniently proceed with the cursor input and the hand-writing input.