baber/WOPTO huggingface dataset:
Patent TW-464859-B (TW)
Title: Magneto resistor sensor with diode short for a non-volatile random access ferromagnetic memory
Inventor: LIENAU RICHARD M
IPC: G11C11/15
Filed: 2000-03-04
Granted: 2001-11-21
Abstract: A non-volatile RAM device is disclosed which utilizes a plurality of ferromagnetic bits (8) each surrounded by a write coil (15) for directing the remnant polarity thereof is disclosed. The direction of magnetic remnance in each bit (8) is dictated by the direction of a current induced into write coil (15). Further, a magneto sensor (9) comprising a magneto resistor (18) coupled to a diode (26) is placed approximate each bit (8). The magneto resistor (18) is coupled to a sense line (20), and receives current at a first point of attachment, and returns current at a second point of attachment. The current passing across magneto resistor (18) is biased in a direction either right or left of the original current flow direction. If current is biased toward the anode end of diode (26) then it is complimentary to the preferred flow direction of diode (26), and flows easily there across. The ultimate effect is that the serial resistance of magneto resistor (18) is reduced, allowing a greater amount of current to pass into the sense line (20). When current is biased toward the cathode end of diode (26), then it is contrary to the preferred flow direction of the diode (26), and does not flow easily there across. The ultimate effect is that the serial resistance of magneto resistor (18) is increased, allowing a smaller amount of current to pass into sense line (20). The presence and amount of current found in the sense line (20) between the bit (8) and the detector (14) determines whether a digital value of ""1"" or ""0"" is stored in the magnetic bit (8). A method for storing binary data is also disclosed.
Patent TW-559750-B (TW)
Title: Composite substrate, thin film EL element using it, and method of producing the same
Inventor: NAGANO KATSUTO
IPC: H05B33/02
Filed: 2000-04-07
Granted: 2003-11-01
Abstract: The purpose of the thin-film EL device of the present invention is to provide a composite substrate that can be simply produced without causing irregularities in an insulation layer surface ascribable to the influence of an electrode layer and without requiring grinding process or sol-gel process and that, when applied to thin film light emitting elements, provides high display quality; a thin-film EL device using the substrate; and a production method for the device. To achieve the purpose, the composite substrate comprises a substrate, an electrode layer embedded in this substrate and formed such that it is flush with the surface of the substrate, and an insulation layer formed on the composite surface between the substrate and the electrode layer, and formed on the composite substrate are a light emitting layer, an insulation layer and an electrode layer, thereby forming a thin film EL element.
Patent TW-539645-B (TW)
Title: Method for making fullerenes water and apparatus therefor
Inventor: HIRATA YOSHIHIRO
IPC: C01B31/02
Filed: 2000-04-28
Granted: 2003-07-01
Abstract: A method and an apparatus for producing healthy drinking water containing fullerenes, which is excellent as healthy water, are provided. In high-pressure water, by burning a mixed gas of oxygen and hydrogen and burning carbon using the combustion gas generated, water containing fullerenes, which include water molecules and are floating in water, is produced. The water containing fullerenes obtained is useful as healthy drinking water.
Patent TW-448544-B (TW)
Title: Method to generate a memory-cells arrangement
Inventor: HOFMANN FRANZ
IPC: H01L21/8242
Filed: 2000-05-18
Granted: 2001-08-01
Abstract: A conductive structure (L, L') is generated in a recess (V, V'), so that it is adjacent on a part of the second edge (F2, F2') of the recess (V, V') on the substrate (1, 2) and is separated from the substrate (1, 2) through another isolations (I1, I1') generated in the recess (V, V'). Thus at first the isolations (I1, I1') are generated, so that they can separate the conductive structure (L, L') fully from substrate (1, 2). The part, which is arranged above the conductive structure (L, L'), of the first edge (F1, F1'), which is opposite to the second edge (F2, F2'), of the recess (V, V') is implanted through an inclined implantation with oxygen. An isolation-structure (I2, I2') is generated through a thermal oxidation, which on the first edge (F1, F1') covers from above the isolation (I1, I1'), but on the second edge (F2, F2') does not cover the isolation (I1, I1'). Thus the part, which is arranged on the second edge (F2, F2'), of the isolation (I1, I1') can be removed through un-masked etchings and can be replaced by conductive material, so that the conductive structure (L, L') can be enlarged and adjacent on the substrate (1, 2).
Patent TW-478003-B (TW)
Title: Semiconductor thin film and liquid crystal display apparatus using the same, and method of fabricating the same
Inventor: SHINAGAWA YOUMEI
IPC: H01L31/036
Filed: 2000-07-13
Granted: 2002-03-01
Abstract: A crystalline semiconductor having an even surface and a large crystal grain size is formed on an economical glass substrate using a laser crystallizing technology. A series of processes of forming an insulation film on a glass substrate; forming a semiconductor film in the first layer; crystallizing the semiconductor film in the first layer by irradiating laser light stepwise from weak energy laser light to strong energy laser light; forming a semiconductor film in the second layer having a film thickness thinner than that of the semiconductor film in the first layer; performing laser crystallization of the semiconductor thin film in the second layer irradiating laser light stepwise from weak energy laser light to strong energy laser light are continuously performed without exposing the workpiece to the atmosphere. According to the above-described processes, a high-quality polycrystalline semiconductor having an even surface and a large crystal grain size can be fabricated.
Patent TW-464705-B (TW)
Title: Method for producing synthetic cotton water pressed cross-woven environmental cloth
Inventor: SU CHING-RUNG
IPC: D04H1/44
Filed: 2000-07-21
Granted: 2001-11-21
Abstract: The present invention relates to a method for producing a synthetic cotton water pressed cross-woven environmental cloth, which is pressed and stabbed by water jet and guided to make them entangled and cross-woven. The method mainly comprises opening and blending the cotton into a fluffy cotton to enable uniformly distributing cotton on mesh conveyor; pressing and wetting the cotton into a dense state with front low pressure water; injecting distributed cotton through the mesh with high pressure water jet by a plate nozzle; providing a turning wheel with cone grooves driven synchronously under the mesh to make the water jet return in two direction, enable the cotton filament to be entangled irregularly up and down to cross-woven as a unity; evaporating the water with upper and lower heated turning circular plates alternately while trimming the burr of the fabric and shaping; drying the fabric in an oven, so as to obtain a fabric which is smooth, soft, without burr, and finely cross entangled after the cold and hot interchanging process. This invented method uses an improved technique to produce a fabric with a better quality. The fabric produced according to the present invention has a high density and a high hygroscopic property. After being used, the fabric can be recycled without the concern of environmental contamination.
Patent TW-457717-B (TW)
Title: Integrated circuit having running indicator
Inventor: WANG BILY
IPC: H01L29/00
Filed: 2000-07-26
Granted: 2001-10-01
Abstract: The present invention discloses an integrated circuit having a running indicator, wherein a light emitting diode is connected in series in the power input/output path of the integrated circuit product as the running indicator. When the integrated circuit product is running, the running indicator will be turned on, and when the integrated circuit product is out of order, the running indicator will extinguish. Thereby it is convenient for repairing during the malfunction.
Patent TW-456036-B (TW)
Title: Method of making integrated circuit capacitor including tapered plug
Inventor: CHAUDHRY SAMIR
IPC: H01L21/02
Filed: 2000-10-07
Granted: 2001-09-21
Abstract: A method of making a capacitor includes the steps of forming an interconnection line above a substrate, depositing a first dielectric layer on the interconnection line, and etching a via in the first dielectric layer. The via has a tapered width which increases in a direction toward the substrate. Further, the method includes filling the via with a conductive metal to form a metal plug, and etching a trench in the first dielectric layer around an upper portion of the metal plug. The metal plug has a tapered width which secures it into the dielectric layer. A second dielectric layer is deposited adjacent the metal plug and an upper electrode is deposited on the second dielectric layer. Preferably, a lower electrode is deposited to line the trench and contact the metal plug.
Patent TW-477817-B (TW)
Title: Metal smelting method and apparatus therefor
Inventor: IWASAKI KATSUHIRO
IPC: C21B11/00
Filed: 2000-09-06
Granted: 2002-03-01
Abstract: The present invention provides a method wherein smelting reduction of metal oxides and/or metal hydroxides such as iron ores are carried out to produce a molten metal at a low cost and high productivity. To attain it, at least metal oxides and/or metal hydroxides such as iron ores and carbonaceous materials are previously mixed, mixed and agglomerated, or mixed and molded to form a mixture. The mixture is pre-reduced in a rotary hearth furnace type or a rotary kiln type pre-reduction furnace to obtain an average metallization degree of metal oxides and/or metal hydroxides, which is 5-55%. The pre-reduced mixture is charged into a smelting furnace for refining. The charged mixture is smelted and finally reduced by using the carbonaceous material as reducing agent and by using, as heat source, combustion heat of the carbonaceous material and combustion heat of carbon monoxide which is generated in the smelting furnace. As a result, molten metal such as molten iron is produced while maintaining a good energy balance and achieving a high productivity.
Patent TW-I248546-B (TW)
Title: Thin film transistor and method for fabricating same
Inventor: TANABE HIROSHI
IPC: H01L21/20
Filed: 2000-09-15
Granted: 2006-02-01
Abstract: In a thin film transistor provided with a metallic layer with a light-shading property and a Si layer formed on an insulating layer, a dent for locally thinning the insulating layer is formed on a portion corresponding to a drain region. When the Si layer is recrystallized by means of a laser light irradiation, the dent serves as a crystalline nucleus formation region in order to recrystallize a particular portion earlier than other portions. Recrystallization of melted Si starts from a periphery of a bottom surface of the dent, hence a Si layer formed of a single crystal or uniformed crystal grains which serves as an active region of the TFT can be obtained.
Patent TW-550892-B (TW)
Title: Network coupler
Inventor: WENDT MATTHIAS
IPC: H01F27/28
Filed: 2000-10-04
Granted: 2003-09-01
Abstract: For a network coupler for network users in a network comprising at least two lines, a simultaneous data and energy transfer is ensured in that the network coupler is formed in such a way that it is suitable for data transfer via the two lines (1, 2) of the network and for coupling out energy from the two lines (1, 2) of the network to which a terminal of a voltage source is coupled, in that the network coupler symmetrically couples energy into and/or out of the two lines (1, 2), in that the network coupler couples the data symmetrically, differentially and inductively or capacitively into and/or out of the two lines (1, 2), and in that the network coupler symmetrically terminates the two lines (1, 2).
Patent TW-502519-B (TW)
Title: Packet transmission in a UMTS network
Inventor: SODERSTROM RAUL
IPC: H04L12/56
Filed: 2000-10-07
Granted: 2002-09-11
Abstract: A method of scheduling packets for transmission over the air interface of a UMTS terrestrial radio access network (UTRAN) in the case where a pair of radio network controllers (RNCs) are acting as separate serving and controlling (drift) RNCs for a mobile terminal. The method comprises sending from the controlling RNC to the serving RNC, allocated scheduling priorities together with packet sizes accepted for transmission with those priorities by the controlling RNC. Subsequently the serving RNC send to the controlling RNC, packets of sizes accepted by the serving RNC together with respective allocated priorities.
Patent TW-495829-B (TW)
Title: Semiconductor wafer having a dot mark with a peculiar shape and method of forming the dot mark
Inventor: MORI AKIRA
IPC: H01L21/205
Filed: 2000-12-07
Granted: 2002-07-21
Abstract: The present invention provides a kind of semiconductor wafer having a dot mark with a peculiar shape, which is excellent in optical visibility and indicates the azimuth of the crystal axis, and forming method of the dot mark. In the method of the invention, a fine protruded dot-like mark (M') is formed on part of a semiconductor wafer surface. A growth layer is grown by epitaxial treatment on the entire surface of a semiconductor wafer including the dot mark (M') so as to form a dot mark (M) of the present invention. During this growth process, the dot-like mark (M') is changed into a polygon pyramid shape including a clear ridge line indicating the same azimuth of the crystal axis as that of the wafer. This ridge line is optically read out so that the azimuth of the crystal axis of the wafer can be specified.
Patent TW-476726-B (TW)
Title: Packaging bags with zippers and inner plaits and its manufacture
Inventor: DAIUCHI TOSHIKATSU
IPC: B65D30/16
Filed: 2000-12-29
Granted: 2002-02-21
Abstract: This invention is related to a packaging bag with zippers and inner plaits and its fabricating method. This invention does not increase the component number or complicate the manufacturing process when the bag may still be zipped and folded so as to reduce the cost Further, the inner plaits do not interfere with the unzipping operation and the bag may be easily unzipped; neither does air leak from the inner plait edges. This invention also provides a method for fabricating such a packing bag by an efficient process.
Patent TW-514499-B (TW)
Title: Nail structure of soccer boots
Inventor: LIAU TSUNG-NENG
IPC: A43C15/16
Filed: 2001-01-11
Granted: 2002-12-21
Abstract: The present invention relates to a nail structure of soccer boots, particularly a screw-on object where a spacer is used to divide the object into a screw on one end and a connection rod on the other end. An insertion part on the end of the connection rod is connected to the head of a constriction structure by compression or screwing and can perform a stretching movement. A buffer is installed between the spacer and the head to obtain a buffer performance when a wearer of the soccer boots is walking or running in order to absorb a portion of the force exerted on his or her feet.
Patent TW-507074-B (TW)
Title: Estimation method for metal impurity concentration in silicon wafer
Inventor: MIZUNO MICHIHIKO
IPC: G01N33/20
Filed: 2001-01-20
Granted: 2002-10-21
Abstract: The present invention discloses an estimation method for the metal impurity concentration in silicon wafer for chemical analysis on the metal impurity in the dense sulfuric acid, which is characterized in, when dripping the dense sulfuric acid onto the surface of silicon wafer, to extract the metal impurity melted in the silicon wafer into the dense sulfuric acid. For the high precision estimation for the metal in the silicon blocks, except for improving the sensitivity of the analyzer itself, the method according to the present invention can solve the problem of extracting the metal contained inside the silicon toward the surface and recycling.
Patent TW-473936-B (TW)
Title: Manufacturing method for SDRAM
Inventor: SHIU SHR-YING
IPC: H01L21/8244
Filed: 2001-02-06
Granted: 2002-01-21
Abstract: A manufacturing method for SDRAM, which includes the following steps: forming a stacking gate on the substrate and forming a light doped source region and a light doped drain region in the substrate; next, forming a thin spacer on the sidewall at the source side of the stacking gate, in which the thin spacer will not completely cover the lightly doped source region to expose part of the lightly doped source region; then, forming a thick spacer on the sidewall at the drain side of the stacking gate; using the thin spacer and the thick spacer as an implantation mask for the ion implantation process to form the heavy doped source region and the heavy doped drain region in the substrate; then, conducting a self-aligned metal silicide process to form a metal silicide layer on the source region, drain region and stacking gate.
Patent TW-594823-B (TW)
Title: Exhausting method and apparatus for flat display panel
Inventor: PARK SUN-WOO
IPC: H01J11/12
Filed: 2001-02-07
Granted: 2004-06-21
Abstract: Disclosed is an exhausting apparatus and method for a flat display panel with high exhausting efficiency assisted by the pressure difference between the interior and the exterior of the panel. Spacing between upper and lower panels will be widened to facilitate the exhausting procedure once the pressure of the interior panel is higher than the pressure setting of the container to a specific value. The method is capable of shortening exhaust time and decreasing the possibility of exhaust residues within the flat display panel to improve the optical and electrical characteristics of the flat display panel.
Patent TW-505994-B (TW)
Title: Semiconductor memory device having self-aligned contacts and method of fabricating the same
Inventor: AHN TAE-HYUK
IPC: H01L27/108
Filed: 2001-02-20
Granted: 2002-10-11
Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.
Patent TW-476839-B (TW)
Title: Radial turbine of an exhaust gas turbocharger
Inventor: MEIER RETO
IPC: F02C7/30
Filed: 2001-02-22
Granted: 2002-02-21
Abstract: The object of the invention is to clearly reduce damaging deposits in the radial turbine of an exhaust gas turbocharger, with little technical complication and without loss of efficiency. For this purpose, at least one through-opening (21) is arranged in the upstream region of the bulkhead (18), which through-opening (21) connects the flow duct (10) to the clearance (19) via the hollow space (20). In this arrangement, a partial flow (24) with a first pressure p1 is branched off from a main flow (23), of the working medium (11) of the radial turbine (1), which main flow (23) is admitted to the flow duct (10). The partial flow (24) is introduced into the clearance (19) formed between the bulkhead (18) and the turbine rotor (7) and is subsequently released into a region of the flow duct (10) provided with a second pressure p2, the pressure p1 being greater than the pressure p2.
Patent TW-581833-B (TW)
Title: Partially oriented poly(trimethylene terephthalate) yarn
Inventor: HOWELL JAMES M
IPC: D02G1/02
Filed: 2001-03-02
Granted: 2004-04-01
Abstract: A partially oriented yarn made from a polyester polymer, wherein said polymer comprises at least 85 mole % poly(trimethylene terephthalate) wherein at least 85 mole % of repeating units consist of trimethylene units, and wherein said polymer has an intrinsic viscosity of at least 0.70 dl/g and the partially oriented yarn has an elongation to break of at least 110%. In addition, processes for spinning a partially oriented yarn and for continuous draw-texturing a partially oriented feed yarn.
Patent TW-527228-B (TW)
Title: Electrostatically assisted coating method and apparatus with focused electrode field
Inventor: LOUKS JOHN WEAVER
IPC: B05D1/30
Filed: 2001-03-19
Granted: 2003-04-11
Abstract: A system for applying a fluid coating onto a substrate includes forming a fluid wetting line by introducing a stream of fluid onto a first side of the substrate along a laterally disposed fluid-web contact area. An electrical force is created on the fluid from an effective electrical field originating from a location on the second side of the substrate and at a location substantially at and downstream of the fluid contact area. The electrical field can be generated in a highly effective manner relative to the coating fluid by a sharply defined electrode on the second side of the substrate. Ultrasonics combined with electrostatic fields further enhances coating process conditions and coating uniformity.
Patent TW-518826-B (TW)
Title: Circuit-arrangement to receive at least two digital signals
Inventor: NIKUTTA WOLFGANG
IPC: H03K5/00
Filed: 2001-04-03
Granted: 2003-01-21
Abstract: A circuit-arrangement (1) has a calibration-circuit (2), which is connected with terminals (11, 12) for two digital signals (E1, E2) and has the output (13, 14) for two digital output-signals (A1, A2), which are derived respectively from one of the digital signals (E1, E2). Through the calibration-circuit (2), a time control of the switch-edge of one of the output-signals (A1, A2) is carried out according to a control-value (R). A comparison-signal (V) is generated with a comparison-circuit (3), which indicates that one of the output-signals (A1, A2) has a switch-edge earlier than other output-signal. The calibration-circuit (2) has a control-input (21), through which the control-value (R), which is stored in a memory-circuit (4), can be adjusted according to the states of the comparison-signal (V) of the comparison-circuit (3). Through the circuit-arrangement (1), it is possible to compensate the unexpected propagation-time difference between the digital signals (E1, E2).