Patent GB-1077084-A (GB)
Title: Improvements in or relating to data readout apparatus
IPC: G06K7/016
Filed: 1964-07-08
Abstract: 1,077,084. Sensing records. HONEYWELL Inc. July 8, 1964 [July 8, 1963], No. 28244/64. Heading G4M. In a system for reading binary information from a storage medium, timing pulses are obtained from pulses derived from the sensing of transitions on the medium which are representative of information. As described, the information is--printed on coupons, transitions from black to white or vice-versa occurring at the middle of a bit area being indicative of the binary information. Clock generation, Fig. 5.-Two information tracks on the coupon are sensed simultaneously. Positive and negative transistions of track A produce the combined signal AP+AN. These transistions may occur in the middle of a bit period (denoting information), or at the limits of a bit period (not information significant), depending on the information. Track B transition signals BP+BN are similarly derived. OSMV 64 and OSMV 72 cause a pulse C to be produced whenever a transition in one track occurs within 1/8 of a bit period of a transition in the other track, this tolerance compensating for variations in the time of firing of triggers in the scanning circuit caused by variations in the output amplitudes of the associated scanning cells. The first E pulse from gate 76 is produced by passing a start pulse from buffer 80 to 1 bit delay 82, the D output pulse therefrom opening gate 76 when the first information C pulse arrives. The timing of the start pulse is normally such that only information significant C pulses are passed by gate 76, i.e. those occurring in the middle of a bit period. Each E pulse is thereafter applied to delay 82, and the D pulses have a duration such that an E pulse is only produced if a C pulse follows the preceding C pulse within a given tolerance of one bit interval. This guards against spurious marks being regarded as information. The E pulses are delayed one bit period at 84 and are then applied to a clock terminal 87. If information transitions on both tracks are obliterated, a C pulse will not occur at the proper time and the corresponding E pulse will not be produced. Pulse absence detector PAD 120 sets FF 88 and opens gate 90 if there is a gap of 1¢ bit periods between E pulses. The last-produced E pulse, having been delayed by 2 bit periods through 84, 92, then passes through gates 94, 90 and supplies the missing clock pulse at terminal 87, as well as entering a 12-bit counter 96. The absence of further C pulses results in the continued recirculation of clock pulses until counter 96 reaches 12, gate 94 is closed and no further substitute clock pulses are generated. The reading operation is also stopped by the output of counter 96. When only a few C pulses are missing, gate 78 is opened by a substitute clock pulse and the set output of FF 88 to restore operation to normal when the next information C pulse occurs. The information pulses are gated to output terminals by clock pulses after being stored for a ¢ bit period in FF 122, the output for track B not being shown. Generation of control signals. Sure start and stop.-A start mark is printed in front of the information on a coupon and extends over two bit areas, being unbroken black in one track and white in the other track. This start mark is recognized by a gating circuit, Fig. 7 (not shown) which only produces a Sure Start signal if the signals derived from the mark conform to strict time limits. The Sure Stop mark is the inverse of the start mark and is recognized by a similar circuit. Self start.-If a Sure Start signal is not generated, self starting is attempted from information sensed from the two tracks. A gating circuit, Fig. 9 (not shown) examines signals derived from the tracks and produces Self Start pulses in synchronism with transitions in either track provided these conform with a prescribed set of logical conditions. One track run.-It is possible that one of the tracks is badly mutilated, but the other track is readable, i.e. transitions are detected on the readable track. In such a case, provided a Sure or Self Start has been achieved, the presence of readable transistions is detected by a gating circuit, Fig. 11 (not shown) to provide a One Track Run pulse to replace the missing C pulse, Fig. 5, whenever a transistion occurs in the middle of a bit period. When transitions are missing, substitute clock pulses are generated as described in connection with Fig. 5. Error signals.-The self-start pulses should be in phase with the clock pulses so that flipflop 144, Fig. 13 should remain set. If a phase error occurs, flip-flop 144 is reset and reading is stopped. When an erroneous transistion occurs during a clock pulse, flip-flop 140 will be set and then reset within the same clock pulse interval so that when the next pulse from OS 136 occurs FF 154 will be set to indicate the error. If a transition has been obliterated, FF 140 will not be set during the clock pulse interval and FF 154 will again be set. Reader control.-The arrival of the leading edge of a coupon at the sensing station is sensed photo-electrically and produces a coupon present pulse CP, Fig. 3, the trailing edge of which causes FF 23 to be set. A Sure or Self Start signal then sets FF 21 and resets FF 23. Sensing of the stop mark produces a Sure Stop signal to reset FF 21, but if this signal is not produced, the output CRB of OSMV 29 automatically resets FF 21 before the next coupon arrives. If the transport system jams, no CP pulses are produced and the system is disabled. The system will only accept a limited number of blank coupons. As before, the trailing edge of a CP pulse sets FF 23, but no start signal is produced and FF 23 is not reset by TCR, gate 28 then being enabled to pass a pulse derived from the CP pulse by OSMV 25 to produce false coupon read signal FCR to replace the missing TCR at buffer 37. The signal CCR informs associated equipment that reading has been attempted. On arrival of a second blank coupon, FF 23 is still set when the CP pulse starts, and a pulse is supplied to. counter 32, then FCR is produced as before. A third blank coupon causes a second pulse to be entered in counter 32 to produce a Scanner Error Interlock signal SEI to reset FF 21 and shut down the reading operation. FF 21 may also be reset by the 12-bit counter of Fig. 5, detection of a phase error or by a manually selectable controlled reset signal.