Patent GB-1161238-A (GB)
Title: Gain Control Circuit.
IPC: G06J1/00
Filed: 1966-10-03
Abstract: 1,161,238. Automatic gain control; seismic exploration. TEXAS INSTRUMENTS Inc. 3 Oct., 1966 [24 Oct., 1965], No. 44049/66. Headings H4D and H4R. In an automatic gain control system for processing the signals from a seismometer an impedance network is controlled by digital signals applied to the network from a digital register. The digital signals may be recorded with the output from the network to indicate the gain of the channel. The contents of the digital register may be controlled as a function of time or with signal level. The impedance network may comprise a number of resistors 50-52, Fig. 2, whose values are in binary progression connected in the signal path between terminal 32  and amplifier 26 via switches 47-49 operated by the stages of a binary counter 43. Fig. 3 shows a system in which the gain of a network 23 in the signal channel between a seismometer 20 and a recorder 29 is controlled as a function of time by feeding pulses from pulse generators 64 to 66 into the binary counter 60 controlling the attenuation of the network. Initially clock 67 is set to a reference, or zero value, from which its digital output is steadily increased with time. When the clock output reaches the count set in t 0  store 71 an output is obtained from the digital comparator 68 to set flip-flop 76, enable gate 79 and feed pulses from generator 64 into the binary counter 60. The counter 60 is then stepped at the rate corresponding to the frequency of generator f 1  and produces a corresponding rate of change of gain of network 23. When the digital output of clock 67 reaches the value set in store 72 coincidence gate 69 is operated which sets flip-flop 77 and resets flipflop 76 so that pulses are fed through gate 80 from generator 65 instead of gate 79 from generator 64, and the count of counter 60, and therefore the gain of network 23, is changed at a rate corresponding to the frequency of generator f 2 . The process continues with the different generators being switched in in sequence until the count stored in the counter 60 equals a value set in the final gain store 84, at this stage comparator 85 is operated and, via inverter 91, disables gate 83 and prevents any further pulses being fed to the counter 60. The output of inverter 91 is also applied via a further inverter 87 to reset the operated one of the flip-flops 76 to 78 to put them in their initial condition. The Figure shows how both the attenuated signal and the state of counter 60 are applied via respective gates 27 and 25 to the recorder 29 when a multiplexer 28 selects that channel from a number of similar channels not shown. The signal is recorded after passage through the analogue to digital converter 30. Alternative methods of deriving the variable pulse rate signal to feed to the binary counter are described. In one method an analogue signal varying with time is arranged to frequency modulate a pulse stream, Fig. 9 (not shown), while in a second method a pulse generator 100, Fig. 5, feeds a number of serially connected beam switching tubes 101 to 103 which are each connected, via a diode matrix 104 to 106, to a set of and gates 137 to 146, 149 to 158 and 161 to 170. The diode matrices are such that for each 10 pulses fed to the respective beam switching tube, 9 pulses are fed to gate 137, 8 to 138, 7 to 137 ... 0 to 146. The other inputs of the and gates 137 &c. are fed from the beam switching tubes 108 to 110 which are stepped by the output of a memory 135 such that in the initial condition the pulses at the output 86 are derived via gates 137, 149 and 161 and for each 1000 pulses fed from generator 100, 999 appear at terminal 86, 900 from gate 137, 90 from 149 and 9 from 161. Successive pulses from the memory reduce the number of pulses at the output by 1 in a 1000, so providing a fine control of the pulse rate in a manner determined by the pulses in the memory 135. If desired the gain of the impedance network may be controlled by the output signal via an analogue to digital converter to maintain the output level constant as the input signal decays.