Patent GB-1185812-A (GB)
Title: Frequency Synthesizer
IPC: H03L7/20
Filed: 1968-01-12
Abstract: 1,185,812. Frequency synthesizers. C.I.TCOMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 12 Jan., 1968 [12 Jan., 1967; 30 Oct., 1967 (2)], No. 1898/68. Heading H3A. A frequency synthesizer comprises a number of oscillators OS, Fig. 1, turnable to different ranges spanning, for example, one octave, and a frequency divider unit OP which can be set to one of five division ratios thereby extending the range of the output frequency Fs to five octaves, tuning within each range of an oscillator being accomplished by scanning the oscillator through its range and counting each time the frequency passes through a harmonic of a reference frequency until the oscillator reaches the frequency of a desired harmonic when the scanning is stopped and a phase lock loop is completed. In Fig. 1 the system is designed to cover the range 2À5-80 Mc/s. in steps of 0À1 Mc/s., harmonics of this step frequency being derived from a reference oscillator Fo by a harmonics generator GH1. The desired frequency is recorded in a register BC connected to a coincidence detector MD1 coupled to a counter MC, which is also coupled to a second coincidence detector MD2 connected to a second register MM in which is recorded the limits of the twenty sub-ranges provided by the four oscillators in OS and the five possible division ratios (1, 2, 4, 8 and 16) of the divider OP. Initially clock pulses from generator H are fed to the counter MC, and each time the count passes one of the limits recorded in MM a pulse is fed by detector MD2 to the logic circuit LO until the count is stopped when it reaches coincidence with the desired number recorded in register BC. In this way the logic circuit LO is enabled to select the required one of the four oscillators in OS (over lines a, b and m) and the required division ratio of OP (over lines e, f and n). The frequency of the selected oscillator is scanned by generator GE and is mixed with the output of harmonics generator GH1 in mixers MO1 and MO2; the latter produces a pulse each time the oscillator frequency reaches a harmonic frequency, and the pulses are fed to the counter MC through switches Y and 302 until the count is equal to the desired count when the logic circuit changes over the switch N to complete a phase locking loop using the output of MO1 and the phase discriminator ##. The output frequency Fs is now fed to the counter MC which acts as a frequency divider with ratio set by BC, and the output of the counter is compared with a reference oscillation in unit 303. If they do not agree, the output frequency is incorrect, the selection process is repeated, and an alarm 306 is energized by relay 305; operation of the alarm is delayed by a monostable 304 to allow several unsuccessful selection processes to take place before an alarm is given. Detailed circuit. Figs. 2-4 (not shown).-The frequency divider corresponding to OP (Fig. 1) is a four stage binary counter (60, Fig. 2) with AND gates (50) connected to each stage so that the division ratio may be 1, 2, 4, 8 or 16 according to which AND gate is opened by a control signal. A similar counter and gate stage (80, 70) is connected between the mixer MO2 (units 14-17, Fig. 2) and the counter MC and is operated by the same control signal. The last two stages of this second counter are controlled by the logic circuit to take account of the remainder when, for example, a frequency of 70 Mc/s. is divided by 16 to derive a frequency of 4À3 Mc/s. The four steps in selecting a frequency are controlled by a five-bank four-position switch (160, Fig. 3). In the first position clock pulses are counted to select the required oscillator and division ratio. In the second position a wide band harmonic generator GH2, Fig. 1 (19, Fig. 2), is connected to the mixers so that the first pulses from mixer M02 indicate that the frequency is equal to the lowest frequency of the selected range. In position 3 the narrow step harmonic generator GH1 is used and harmonics are counted, and in the final position the phase lock is completed. The sweep generator (Fig. 5, not shown) comprises a capacitor charged through two parallel circuits, one including a transistor. When the harmonic below that desired is reached the transistor is cut off to slow down the sweep rate, and the next pulse from mixer MO2 unblocks the phase discriminator to allow it to control the frequency. The system can be arranged to produce a different output frequency from that inserted in the register BC, e.g. differing by a desired intermediate frequency, by correcting the limits recorded in register MM. Modified circuit. Figs. 7-9 (not shown).- Clock pulses fed to the counter corresponding to MC (220, Fig. 9) are also fed to a counteradder (230). If the required frequency is between 40 and 80 Mc/s. the most significant digit in the counter-adder is 4, 5, 6 or 7 and indicates which of the four oscillators is to be used. If it is not, the count is repeated 2n times until the most significant digit in the counter-adder is one of these numbers. This digit then indicates the required oscillator, and the number of counts indicates the required division ratio.