Patent GB-1414183-A (GB)
Title: Charge coupled devices
IPC: H01L21/339
Filed: 1972-10-24
Abstract: 1414183 Charge transfer devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 24 Oct 1972 [27 Oct 1971] 48980/72 Heading H1K A device in which packets of charge carriers can be transferred along a semi-conductor layer between two locations by means of clock voltages applied to an array of electrodes associated therewith is so constructed that the carriers are confined within the layer during transfer and the thickness and doping of the layer are such that a depletion layer extending throughout its thickness and in which no avalanching occurs can be generated by the clock voltages. The shift register shown in Fig. 1 comprises a P type silicon substrate carrying an N type epitaxial layer divided into islands 2, 19, 28 by an inset oxide layer extending into the substrate. Charge transfer takes place along island 2, which is isolated from the substrate by reverse biasing its junction therewith, under the control of clock voltages applied via conductors 13, 14, 15 common to three groups of transfer electrodes 4, 5, 6 respectively which extend the full width of the island over a layer of silicon dioxide, electrodes 6 being connected to conductor 15 via underpasses constituted by the N+ doped surface regions of islands 19. Operation is as follows: Initially the magnitude and phasing of the clock voltages are such that the island 2 is fully depleted of electrons except under the electrodes 4. An input signal voltage applied to electrodes 33 determines the potential of the area underlying N+ inclusion 34 and a pulse voltage on gate electrode 35 allows sufficient electrons to flow to the area beneath adjacent electrode 4 to raise its potential to the same level. Then the clock voltages change to bring the undepleted regions beneath electrodes 5 causing transfer of the charge packet from beneath electrode 4 and so on until it reaches the area beneath N type inclusion 25 where it is held by the depletion layer under electrode 20. There being a reference voltage on electrode 24 the amount of charge in the packet determines the potential of inclusion 25 and hence of the gate 27 of a deep depletion IGFET in island 28, thereby providing an output signal at the drain. Electrode 20 is then pulsed to enable the charge to be drained away via N+ region 22. In a modification the lower face of the N type layer is provided with a corresponding set of transfer electrodes. In another arrangement (Fig. 9) there are four groups of transfer electrodes supplied from two clock voltage sources 97, 98 connected directly to electrodes 93, 95 respectively and via fixed bias sources to electrodes 92, 94. In a more compact arrangement there are two groups of electrodes on each face of the layer the electrodes on one face being displaced by half the pitch distance between electrodes on the opposite face in relation to those electrodes but overlapping them. Each group of electrodes is supplied by a different clock voltage source, the voltages being such that at a given moment only limited regions beneath one group of electrodes are undepeleted and their sequence such that the undepeleted region moves alternately from one face of the wafer to the other. In yet another arrangement with three groups of electrodes disposed on each face of the layer the electrodes on one face are mutually parallel and perpendicular to those on the opposite face. By application of clock voltages to the electrodes on the two faces the charges can be transferred in mutually perpendicular directions. Use of other semi-conductors, e.g. germanium and A III B V  compounds, reversal of the conductivity types of the regions and the use of silicon nitride or aluminium oxide or combinations of layers of different materials instead of silicon to underlie the transfer and gate electrodes are suggested. An alternative way of introducing electrodes into the layer is to produce electron-hole pairs therein by irradiation, the holes draining away into the substrate on account of the bias voltage. The described shift registers, which have the advantage that the charges are transferred through the interior of the layer where the carrier mobility is higher rather than along the surface, may be incorporated in a wafer ineluding other integrated circuit components.