baber/WOPTO huggingface dataset:
Patent TW-517464-B (TW)
Title: 1-from-N decoder-circuit
Inventor: FISCHER HELMUT DR
IPC: G11C8/10
Filed: 2001-09-21
Granted: 2003-01-11
Abstract: A decoder-circuit (2) to control a sample selected from a set of N-output-lines (40) independent from an M-bit address and in response to a switch-signal (AES) contains k≥2 parallel pre-decoders (11, 12, 13), each of which decodes a related segment of the M-bit-address through activation of just one sample of its outputs (a1 to a8, b1 to b8, or c1 to c4). An end-decoder contains for each of the N output-lines (40) a special control-branch (32) with a group of k controllable switches (T1-T3) in series between the related output-line (40) and a control-potential (L). Each switch-group in the end-decoder can be switched on by just one related sub-set of the pre-decoder-outputs, which contain just one output from each pre-decoder. On the outputs (a1-a8) of one of the pre-decoders is connected a device (70), which responses to the switch-in-signal (AES), in order to release the outputs only during the appearance of the switch-in-signal (AES) for the coupling with the related switches (T1, T2, T3) in the control-branch (32).
Patent TW-I242722-B (TW)
Title: Data communication system and method, and recording medium
Inventor: EBIHARA HITOSHI
IPC: G06F15/167
Filed: 2001-10-09
Granted: 2005-11-01
Abstract: The present invention provides data communication technology for improving the efficiency of cooperation of two or more information processing units (GSM) for more sophisticated processing. According to the present invention, there are provided four GSMs, a sub-MG (merger) for merging data output from the GSMs, and a main MG for merging data output from the four sub-MGs. Data output from the GSMs are stored in parallel in a register on a unit length basis. Then the data stored in the register are serially read on the unit length basis to form serial data. When the serial data contain altered data, auxiliary data for identifying which data have been altered or modified are added to a predetermined portion of the serial data. Then the serial data with the auxiliary data added thereto are output to the main MG. On the other hand, parallel data to be output from a main SYNC to each GSM are copied, and the copies of the same parallel data are propagated over all the GSMs at the same time.
Patent TW-532013-B (TW)
Title: Method of and system for wireless network access through server platform integration
Inventor: SUMNER TERENCE EDWARD
IPC: H04L12/54
Filed: 2001-10-22
Granted: 2003-05-11
Abstract: A method, system, and apparatus for incorporating a database-enabled server into a wireless network. The method includes the steps of receiving, at the wireless gateway, a communication message from a first communication network, the communication message including address information associated with a subscriber; storing, by the wireless gateway, the communication message, the communication message being stored in association with the subscriber; and selectively sending, with the wireless gateway using the wireless communication network, at least a portion of the communication message to a wireless device.
Patent TW-536735-B (TW)
Title: Optical condenser system, optical illumination system provided with the same, and exposure system
Inventor: SUENAGA YUTAKA
IPC: G02B19/00
Filed: 2001-12-14
Granted: 2003-06-11
Abstract: There is provided an optical condenser system that can secure required optical characteristics using a simple constitution composed of a small number of lenses. This optical condenser system is constituted, so that its front-side focal plane and first surface (8) coincide with each other and its rear-side focal plane and second surface (10) coincide with each other and condenses and guides the light from the first surface to the second surface. This system has a first lens group G1, containing a negative lens the concave surface of which is directed toward the first surface, a second lens group G2 containing a positive lens, and a third lens group G3, all of which are positioned in this order from the first surface side. The first lens group G1 has at least one lens surface formed into an aspheric surface.
Patent TW-I283509-B (TW)
Title: Method in connection with an inverter
Inventor: TARKIAINEN ANTTI
IPC: H02P21/22
Filed: 2002-03-14
Granted: 2007-07-01
Abstract: The invention relates to a method in connection with an inverter, the inverter comprising a direct voltage intermediate circuit, an optimum switching table and output power switches. The method comprises steps where phase current (iA, iC) of the inverter are converted to a synchronous dq coordinate system in order to achieve vector components (id, iq), the synchronous current vector components (id, iq) are low pass filtered in order to achieve current vector components (id, lpf, iq, lpf), a current reference (iq, ref) is generated in the direction of the q axis, a current reference (iq, ref) is generated, a torque reference (te, ref) is generated, an absolute value reference (|Psi|, ref) of a flux linkage is generated from the currents and switching commands are formed on the basis of the torque reference (te, ref)and the flux reference (|Psi|, ref) using the optimum switching table (5).
Patent TW-570818-B (TW)
Title: Air purifier
Inventor: OIKAWA TAKUMI
IPC: A61L9/00
Filed: 2002-03-15
Granted: 2004-01-11
Abstract: To provide an air purifier with which discharging sounds are reduced and the generation of noise can be prevented as well. An air blowing fan 12, an optical catalyst module 14 and an ozone decomposing catalyst filter 16 are arranged on an air blowing pass 13 and air cleaning is performed by reforming discharging with pulses having rising width for 10 musec and discharging frequency of 10 kpps.
Patent TW-I227401-B (TW)
Title: Method and system for establishing a temporary, dedicated pipeline in a processor apparatus for processing data being received by said processing apparatus
Inventor: SUZUOKI MASAKAZU
IPC: G06F15/167
Filed: 2002-03-22
Granted: 2005-02-01
Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
Patent TW-I236580-B (TW)
Title: Method and apparatus for generating and synchronizing multiple clocks
Inventor: WANG CHARLES L
IPC: H03L7/06
Filed: 2002-05-21
Granted: 2005-07-21
Abstract: Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.
Patent TW-563347-B (TW)
Title: Compensation light souce to compensate the optical attenuation caused by optical path and the design method thereof
Inventor: LEE KUAN-YU
IPC: H04N1/40
Filed: 2002-06-13
Granted: 2003-11-21
Abstract: A compensation light source to compensate the optical attenuation caused by optical path and the design method thereof are disclosed. Firstly, choose the predetermined light source with different tube diameters to irradiate the same gray scale chart, and generate the corresponding scanning light. Collect the scanned light and focus/form the image on the photosensitive device, the pixels of the photosensitive device generates several sensing voltages corresponding to each predetermined light source, and the tube diameters of the predetermined light source have a correspondence relationship data with the sensing voltages of the predetermined light source. By using the correspondence relationship data and the sensing voltages of the predetermined light source selected, a compensation light source is designed and the detection operation is proceeded.
Patent TW-563017-B (TW)
Title: Device and method for executing single-step interrupt debugging in first stage of computer booting through PCMCIA interface
Inventor: TSAI JIUN-NAN
IPC: G06F13/10
Filed: 2002-06-25
Granted: 2003-11-21
Abstract: The present invention provides a device and method for executing single-step interrupt debugging in first stage of computer booting through PCMCIA interface, which inserts a bus period single-step interrupt debugging device into the PCMCIA slot of the computer device, and extracting the debug-related messages in the first stage of booting computer device with the bus period single-step interrupt debugging device. The extracted debug-related message can be transmitted and displayed through a signal transmission and display circuit. The signal transmission and display control device is connected with a debug message collecting device for collecting the debug-related messages and signals sent by the bus period single-step interrupt debugging device. The PCI/PCMCIA interface controller of the computer further includes a mode switching control circuit for switching the PCMCIA slot operating between the normal PCMCIA mode or debugging mode.
Patent TW-563255-B (TW)
Title: Semiconductor device and manufacturing method thereof
Inventor: NAKAJIMA HIROOMI
IPC: H01L21/322
Filed: 2002-10-22
Granted: 2003-11-21
Abstract: An active layer is formed on an imbedding oxide film. A gettering layer is formed in the active layer and is located around an element isolating insulation film. The gettering layer is to trap heavy metal diffused from the element isolating insulation film to the active layer. The method prevents characteristic deterioration of the device.
Patent TW-I234774-B (TW)
Title: Optical recording medium and optical recording medium evaluation method
Inventor: YAMAGA KENJI
IPC: G11B7/26
Filed: 2002-10-22
Granted: 2005-06-21
Abstract: To effectively use a conventional mechanical precision measuring instrument to measure the eccentricity of a high density optical disc. This optical disc 2 for DVD has a fine projection and recess pattern (a first projections and recesses: pits and/or grooves) 4 complying with the standard format in the information recording area 6 and is also provided with an eccentricity measuring fine projection and recess pattern (a second projections and recesses) 8 complying with the CD format which is less in density than the format with which the DVD optical disc 2 complies in the area other than the information recording area 6. With the fine projection and recess pattern 8 for mechanical check, the eccentricity (mechanical precision) of the optical disc 2 for the DVD can be measured by using a mechanical precision measuring instrument for a conventional CD family without modifying.
Patent TW-I231927-B (TW)
Title: D/A converter for current-driven type source driving circuit in active-type matrix OLED
Inventor: SUEN WEN-TANG
IPC: H03M1/74
Filed: 2002-11-27
Granted: 2005-05-01
Abstract: A D/A converter for current-driven type source driving circuit in active-type matrix OLED is disclosed, which can generate data current with different gray levels. The D/A converter comprises the following devices: a column decoder to convert the input digital control signal (Dx) into a set of column selection signals (Cj) through a decoding program; a row decoder to convert the input digital control signal (Dx) into a set of row selection signals (Ri) through a decoding program; a current cell array having current cells arranged in column and row, and each current cell has a local current source and a local decoder, wherein the local current source can be selected from at least three currents with different magnitudes, and the local decoder can execute the decoding program to the column selection signal and row selection signal of the input current cell, so as to determine whether to conduct the local current of the current cell or not. After summing all output currents of the conducting current cells, the data current having the selected gray levels can be formed.
Patent TW-I240638-B (TW)
Title: A film-coated solid-dosage form pharmaceutical composition
Inventor: BAKER ROBERT WILLIAM
IPC: A61P25/06
Filed: 2002-12-03
Granted: 2005-10-01
Abstract: The present invention relates to a pharmaceutical composition for oral administration capable of rapid disintegration and dispersion within the gastrointestinal tract comprising a 5HT1 receptor agonist as active ingredient, in particular a composition in solid-dosage form that is intended to be swallowed, and methods of treatment of cephalic pain, especially migraine, using such composition.
Patent TW-I234239-B (TW)
Title: Method of fabricating mask ROM
Inventor: KIM SEOK-SU
IPC: H01L29/423
Filed: 2002-12-17
Granted: 2005-06-11
Abstract: A method of fabricating a mask ROM excellent in gap-filling force in a salicide-forming process. The method comprises the steps of: preparing a substrate defined by a memory cell array region and a peripheral region; forming a device isolation film between the memory cell array region and the peripheral region; forming a gate-forming material layer on the entire surface of the substrate having the device isolation film; covering the memory cell array region and selectively etching the gate-forming material layer in the peripheral region to form a first gate; forming an insulation spacer in a lateral portion of the gate in the peripheral region; injecting ion to the substrate in the peripheral region to form a source/drain region using the gate and the insulation spacer as a mask; forming salicide on the gate-forming material layer of the memory cell array region and the gate and in the source/drain region of the peripheral region; covering the peripheral region and selectively etching the gate-forming material layer in the memory cell array region to form a second gate; and forming a protective film on the resultant substrate.
Patent TW-I228407-B (TW)
Title: Surgical knife
Inventor: CHEN GA-LANE
IPC: A61B17/32
Filed: 2002-12-31
Granted: 2005-03-01
Abstract: A surgical knife includes a main body and a cutting portion. The cutting portion are shaped as a line. The shape of the cutting portion can be linear or spiral. A diameter of the cutting portion is in the range from 10 nm to 1000 nm. A length thereof is in the range from 1 cm to 50 cm. The surgical knife is generally made from a carbon nanotube, a bundle of carbon nanotubes or carbon nanowire. Alternatively, the surgical knife can be made of silicon nitride, boron carbon nitride, silicon carbide or gallium nitride. The size of the surgical knife is much smaller than the dimension of blood vessels and nerves, the surgery with employing it will be bloodless and painless.
Patent TW-568973-B (TW)
Title: Method for producing patterned fabric mimicking muntjac leather
Inventor: SU YUE-JU
IPC: D06N3/00
Filed: 2003-02-20
Granted: 2004-01-01
Abstract: A method for producing a patterned fabric mimicking muntjac leather comprises knitting or sewing a monocolored or multi-colored pattern on a fabric base cloth; using a yarn-twisting treatment to combine the tightly knitted yarns with the yarns of the base cloth to form an integral laminated fabric; applying a fine grinding fibrillation treatment on the surface of the base cloth to form short uniform piles on the surface of the fabric formed by yarn-twisting of the knitted yarn and the base cloth, thereby achieving a complete cover on the knitted or sewn pattern to form a fabric mimicking muntjac leather and having properties including no pile-detaching, natural pattern, smooth and excellent visibility, wear resistance, and durability.
Patent TW-I227430-B (TW)
Title: System for enterprise innovation and incubation development and method thereof
Inventor: LI JR-RUEI
Filed: 2003-02-27
Granted: 2005-02-01
Abstract: A system for enterprise innovation and incubation development and method thereof particularly specifies a computer aided system for innovation company to cultivate the person to be incubated for innovation and new product development. The computer aided system comprises a registration log-in system, an innovation management system, a creativity database management system, a In6-based innovation evaluation system, a contracting system, an incubation development management system, an incubation performance management and merit system and residual value reorganization system. The integrated system and method can be utilized for innovation company to cultivate innovator for innovation and new product development, services and enterprise incubation.
Patent TW-I271822-B (TW)
Title: Memory manufacturing process with bitline isolation
Inventor: RAMSBEY MARK T
IPC: H01L27/115
Filed: 2003-03-27
Granted: 2007-01-21
Abstract: A method of manufacturing an integrated circuit is provided with a semiconductor substrate (506) having a core region (502) and a periphery region (504). A charge-trapping dielectric layer (510) is deposited in the core region (502), and a gate dielectric layer (522) is deposited in the periphery region (504). Bitlines (518) are formed in the semiconductor substrate (506) in the core region (502) and not in the periphery region (504). A wordline-gate layer (524) is formed and implanted with dopant in the core region (502) and not in the periphery region (504). A wordline (528) and gate (530) are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate (506) around the gate (530), and the gate (530) is implanted with a gate doping implantation in the periphery region (504) and not in the core region (502).
Patent TW-I227179-B (TW)
Title: Program-controlled dicing of a substrate using a pulsed laser
Inventor: BOYLE ADRIAN
IPC: B23K26/06
Filed: 2003-04-18
Granted: 2005-02-01
Abstract: A substrate 30 is diced using a program-controlled pulsed laser beam 35 apparatus having an associated memory for storing a laser cutting strategy file. The file contains selected combinations of pulse rate Deltat, pulse energy density E and pulse spatial overlap to machine a single layer or different types of material in different layers 31, 32, 33, 34 of the substrate while restricting damage to the layers and maximizing machining rate to produce die having predetermined die strength and yield. The file also contains data relating to the number of scans necessary using a selected combination to cut through a corresponding layer. The substrate is diced using the selected combinations. Gas handling equipment for inert or active gas may be provided for preventing or inducing chemical reactions at the substrate prior to, during or after dicing.
Patent TW-I250296-B (TW)
Title: Battery capacity calculation method
Inventor: YAMAZAKI KAZUO
IPC: H01M10/48
Filed: 2003-05-05
Granted: 2006-03-01
Abstract: The present invention relates to a battery capacity calculation method, which includes: a reference discharge curve calculation step for obtaining a discharge curve as a reference, a correction voltage calculation step for correcting the battery measurement voltage (V1) by a battery resistance component so as to obtain a corrected voltage (V), and a capacity calculation step for calculating the battery discharge capacity from the discharge curve serving as the reference by using the corrected voltage (V). The capacity calculation step has a deterioration index calculation step for calculating a capacity deterioration index (S) as a capacity reduction ratio attributed to battery deterioration. The discharge capacity calculated from the discharge curve as the reference by using the corrected voltage (V) is further multiplied by the capacity deterioration index (S), thereby calculating a discharge capacity.
Patent TW-I280134-B (TW)
Title: Accelerating agent for elimination of dioxins
Inventor: SHINODA TADASHI
IPC: A23L33/135
Filed: 2003-05-30
Granted: 2007-05-01
Abstract: An accelerating agent for elimination of dioxins which comprises, as an active ingredient, a microorganism having an activity of accelerating elimination of dioxins in the body to the outside of the body.
Patent TW-I242307-B (TW)
Title: Jointer device
Inventor: SHINABE MUNEHIRO
IPC: H01P5/18
Filed: 2003-07-03
Granted: 2005-10-21
Abstract: A jointer device with larger jointability is disclosed, to do this, the jointer device is consisted of a first and a second dielectric substrate (141), (142) each having parallel first and second surface; a ground conductor (103) formed on the second surface of the first dielectric substrate (141); and two jointing line conductors (120), (121) that are closely adjacent provided on the second surface of the second dielectric substrate (142) for electromagnetic jointing each other; in which the arrangement and the connection of plural via conductors (150 to 163), (170 to 183) on the two jointing line conductors (120), (121) may increase the electromagnetic jointability each other, and the areas opposite to the two jointing line conductors (120), (121) are enlarged so as to increase static-electric capacity.
Patent TW-I228302-B (TW)
Title: Composite stack package
Inventor: CHANG CHIN-CHIANG
IPC: H01L23/28
Filed: 2003-08-28
Granted: 2005-02-21
Abstract: A composite stack package including a substrate, a first die, a second die, and an encapsulation layer is disclosed. A cavity is configured within the substrate. The first die is disposed in the cavity and is electrically connected to the substrate by a number of gold wires. The second die with a number of bumps is disposed over the first die. The encapsulation layer encapsulates the first die, the second die, and the gold wires and exposes the bumps of the second die. The density of output/input can be increased by means of stacking the second die over the first die.
Patent TW-I263911-B (TW)
Title: System and method of generating simulated diffraction signals for two-dimensional structures, and computer-readable medium thereof
Inventor: BISCHOFF JOERG
IPC: G06F17/10
Filed: 2003-10-16
Granted: 2006-10-11
Abstract: One or more simulated diffraction signals for use in determining the profile of a structure formed on a semiconductor wafer can be generated, where the profile varies in more than one dimension. Intermediate calculations are generated for variations in a hypothetical profile of the structure in a first dimension and a second dimension, where each intermediate calculation corresponds to a portion of the hypothetical profile of the structure. The generated intermediate calculations are then stored and used in generating one or more simulated diffraction signals for one or more hypothetical profiles of the structure.