Patent GB-1388486-A (GB)
Title: Semiconductor device manufacture
IPC: H01L29/00
Filed: 1972-03-30
Abstract: 1388486 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 30 March 1972 [3 April 1971] 15022/72 Heading H1K An integrated semi-conductor device comprises a P-type semi-conductor body 1 incorporating a transistor having N-type regions 2 and 4, 5 separated by a P-type region 3; an inset pattern 6, 7, 8 of insulant material extending from surface 9. A portion 10 extends inwardly from the surface 9 and is peripherally bounded by inset pattern 6, 7. It wholly contains N-type region 2 and P-type region 3, and partly contains N-type regions 4, 5 adjoining region 3 and inset pattern 6, 7; the region 3 being separated from surface 9 by region 2. The inset pattern 6, 7, 8 is embedded in an adjacent zone 11, 12, 13 having a concentration of P- dopant less than the concentration of N- dopant in the N-type regions 4, 5 but high enough to prevent electrical connections between N-regions within P-region 3 or P-body 1, at the area of zone 11, 12, 13; e.g. between regions 2 and 4, 5. Part 18 of adjacent zone 11 operates as a channel stopper with respect to a circuit element (not shown) in an adjacent bounded portion of the body. The P-dopant concentration in zone 11, 12, 13 is less than the N-dopant concentration in region 2 adjoining the inset pattern 6, 7 over part of its periphery, while regions 2, 3 are contacted over surface 9 at the bounded portion 19 and region 4, 5 is contacted over the same surface at the bounded portion 14. Another portion 15 adjoining surface 9 is bounded by part 8 of the inset pattern embedded in adjacent zone 13, which is heavily doped for P-conductivity in its part 16 contacting the surface 9, over which the substrate 1 is contacted through P-type low ohmic zone 17. In a modification (Fig. 2) a semi-conductor body 25 containing a transistor comprises an inset pattern 26, 27 embedded in an adjacent zone 29, 30; and a bounding portion 28 containing N-type regions 21, 22, 23 of the transistor and P-type region 24 of the same. The latter region adjoins the inset pattern 26 over part only of its periphery so that N-type region 22, 23 may be contacted by low ohmic N-type contact zone 31; the semi-conductor body 25 also being contacted at the major surface 32 as before. In manufacture a P-type Si semi-conductor body 1 (Fig. 7) is substrate for N-type epitaxial. As doped layer 4 in which a low ohmic N type region 5 is formed by local deposition of As prior to epitaxy and subsequent in-diffusion. Oxidation resistant mesh layers 71, 72 of Si3N4 overlain by SiO2 and apertured at 74 are deposited on surface 73, and the Si body is etched over the mask to form recesses 76 which are then thermally doped with B to pattern 75 from Bo vapour. The doping pattern is oxidized thermally in steam through the mask to obtain inset pattern 6, 7, 8 (Fig. 8) and P type adjoining zones 11, 12, 13. Masking layers 71, 72 are removed, and regions 2, 3, 17 are diffused in with respectively P and Bo. Regions 4, 5 are contacted by deep diffusion of P. Contact zones for the. circuit element regions and the semiconductor body are formed to extend to the major surface. The modified device of Fig. 2 is similarly manufactured with channel stoppers between the circuit elements in adjacent bounding portions 28 or between regions 21, 23 of a circuit element. The inset pattern 6, 7, 8 (Fig. 8) may alternatively be formed after provision of the masking layers 71, 72 and before forming the doping pattern 75; after which Ga or Al is thermally diffused using masking layer 71, 72 (Fig. 7); respectively from AlSi and GaSi alloys in H2 or vacuum. P-type zones 11, 12, 13 (Fig. 8) are then formed adjacent the inset pattern; by diffusion of Ga or Al, preferably after removal of mask 71, 72, so that the first conductivity type regions, are formed first and then the second conductivity type regions. The masking layer may be Al2O3 and the circuit element may be, e.g. a PNPN transistor, while oxidation may be carried out in two steps with the formed oxide layer removed after the first step. The inset pattern may only be partially inset in the semiconductor body.