Patent GB-1352937-A (GB)
Title: System for correcting time-base errors in a repetitive signal
IPC: H04N5/95
Filed: 1971-04-19
Abstract: 1352937 APC systems AMPEX CORP 19 April 1971 [1 April 1970] 25668/71 Heading H3A A variable delay system for adjusting the phase relationship between two signals, e.g. video signals, having corresponding periodic synchronizing components from sources 11, 12 comprises a phase comparator 17, a plurality of delay elements 71-76 (see Fig. 4) adapted to be connected in different serial combinations for selectively delaying one of the signals, switching devices 81-85; 91-96 effective to apply the signal to be delayed as well as for changing the serial combination in accordance with the magnitude of the measured phase relationship during a predetermined portion of the periodic synchronizing component of the signal to be delayed, the delay elements being suitably bypassed or inserted in the serial combination so that at the instant of changing, the output signal emerges having been delayed by the requisite amount. The periodic synchronizing component may in the case of a video signal correspond to the horizontal synchronizing pulse with its front porch interval. The phase comparator 17 output has a range undergoing a transition from maximum to minimum level or vice versa when the signals undergo relative phase changes between maximum out of coincidence and coincidence conditions and a period of one of the signals is skipped or repeated as required in order to resynchronize the two signals when the phase difference exceeds the above range. In operation, an information signal including synch pulses from a video source 11 (see Fig. 3) is applied to a digital phase comparator 17 via a sync. pulse stripper 43 along with reference pulses from source 12. The information signal, usually at the line frequency of TV transmission, is also applied via a fixed 1 line delay 13 to a switched segmented delay 14 including a binary ordered delay line network 31 and a tapped delay line network 32. To counteract amplitude variations in the delay networks, a frequency modulator 33 and a frequency demodulator 34 are introduced at suitable points in the signal path. Further as different sections of the delay network 14 involve different frequency responses a frequency doubler 36 and a frequency divider 37 are introduced in the signal path. The digital phase comparator 17 produces an error signal in the form of a binary coded word suitable for setting the value of delay introduced by network 14 as to provide coarse phase correction. A finer phase correction is obtained by comparing the delayed output of 14 with the reference pulse in an analogue phase comparator 18 for controlling an electronic variable delay line 16. The digital phase comparator 17 comprises a pulse time quantizer and analogue error generator 41 for quantizing, i.e. regenerating the information sync. and reference pulses at predetermined instants, a pulse time comparator 48 for comparing the phases of the quantized pulses to produce a binary error word, an analogue to digital corrector 51 for determining the error between the actual phase difference and the phase difference of the quantized pulses and effective to apply a correcting signal to the comparator 48 when the error exceeds a given threshold value. The phase comparator 48 comprises (see Fig. 4) a time word generator 123 responsive to clock pulses from a generator 118 to develop a recycling binary time word, registers 126, 127 for separately storing the time words occurring at the appearances of the reference and information synchronizing pulses respectively and a subtractor 128 for providing a binary difference word as the phase comparator 17 output. The system also includes a timing control arrangement involving delays 182, 183 and registers 146-148 for operating the switching devices 81-113 in accordance with the phase comparator 17 output and at periodic switching times determined by the reference pulses. For relatively small phase changes, devices 81-85 are conditioned to be switched at a time preceding the switching of devices 91-96 by an amount corresponding to the smallest binary delay step and this switching is timed to occur during the front porch of the blanking period as not to distort the sync., burst and information pulses. In the case of large abrupt changes in phase, the step change in delay distorts one line of information but the following line is properly synchronized. The embodiment of Fig. 11 (not shown) includes a delay networks with large capacity as to permit frequency and phase synchronization from the frame or field level down to the line level. The arrangements indicated in Figs. 6-10 (not shown) involve part of the delay lines 71-85 and individual components of the phase comparator 17.