Patent GB-1111839-A (GB)
Title: Improvements in or relating to electric signal handing systems
IPC: G11C27/02
Filed: 1966-02-11
Abstract: 1,111,839. Multiplex amplifier; transistor amplifying circuits. HONEYWELL Inc. 11 Feb., 1966 [19 Feb., 1965], No. 6067/66. Headings H3T and H4R. [Also in Division G3] Amplifier system, e.g. for use in a control system, comprises a single amplifier associated with a number of signal channels by sequential switching, with memory devices associated with each signal channel which are sequentially connected to the output of the amplifier and from which a feedback path is connected to its associated input channel. One or more switching positions may provide stabilizing arrangements by shorting or open circuiting the amplifier input and providing a balancing signal from an associated memory device to the amplifier input. In the system of Fig. 1 during a first time interval switches 20a and 20b are closed, to earth one input of a differential D.C. amplifier 2 and to connect its output to a memory device 22. A signal dependent on the voltage drift of the amplifier 2 is thus fed from the memory unit to the other input 6 of the amplifier 2. Subsequently, during a second time interval switch 26 is closed so that a signal is fed to memory unit 28, and from there as feedback to the amplifier input, in accordance with the current drift of the amplifier, i.e. with the input of the amplifier open circuit at 15 and 20, to provide current drift compensation. During the following time interval switches 36a, 36b and 15, are operated to provide, in the case of 36a and 15, capacitance transfer of the value of the output of a transducer, e.g. a thermocouple, connected at terminals 32 to the input of the amplifier 2, whose output is connected, via switch 36b, to the memory unit 48. The output of the memory unit is recorded at 50 and also applied, via an attenuator 31, as feedback to the amplifier input to provide the appropriate amplifier characteristic. During the succeeding time interval the output of memory 48, which is sustained even though switch 36b is now open, is applied to an " error " unit 54 where it is compared with a desired value and the error signal is applied via a reset adjust 56 and switch 62a, which together with switches 62b and 15, is closed for the duration ofthis time interval, to the input of the amplifier 2, the output of which, via switch 62b, memory unit 64, and amplifier 66, is applied to the utilization device 67, e.g. a valve actuator which controls the process the result of which is being monitored by the transducer connected to terminals 32. In addition the output of memory unit 64 is applied via a proportional band adjustment, and rate unit 70 to a summing junction 60 to provide feedback over the amplifier to provide the appropriate type or rate of control of the actuator 67. Further signal sources may be connected as at 73 to be sequentially switched to the amplifier 2 by operation of switch 73a, switch 73b also being operated to connect the output of the amplifier to a memory unit, not shown, the output from which feeds a feedback attenuator 69 to provide the appropriate amplifier characteristic. Common amplifier, Fig. 2, comprises a pair of series connected differential amplifier modules, Fig. 3 (not shown) each comprising a pair of transistors in long tailed pair configuration with a third, current stabilizing, transistor in their common emitter connection, the differential outputs being fed via emitter followers and conventional common emitter amplifier stages with emitter coupling. The output of the amplifier 2 is fed via emitter followers, 82 and 100, Fig. 2, with the emitter loads bypassed by the collector emitter path of a transistor whose base is fed with the emitter follower input signal so that cutting off of the emitter followers on fast falling edges is prevented by conduction of the auxiliary transistors. A memory amplifier for unit 64 in Fig. 1 is described with reference to Fig. 4 (not shown) and comprises an electrometer valve (202) first stage, and two cascaded transistor stages using transistors of opposite conductivity type (204 and 206) with temperature stabilization provided by D.C. negative feedback.