baber/WOPTO huggingface dataset:
Patent TW-453049-B (TW)
Title: Real time algorithms and architectures for coding images compressed by DWT-based techniques
Inventor: ACHARYA TINKU
IPC: H04N7/32
Filed: 1999-08-03
Granted: 2001-09-01
Abstract: What is disclosed is a method that allows a fixed length codeword and flag to serve as a structure for encoding large run lengths, a sequence of such structures representing the number of zeroes between two non-zero values in a data set to be encoded. Also disclosed is an adaptive encoding technique that determines an encoding method suitable with the entropy characteristics of the data to be encoded. An architecture is disclosed which allows the size of the fixed length to be varied, if needed. This architecture includes a plurality of logic networks coupled to a single counter, each of which may be enabled depending on the desired codeword size.
Patent TW-421871-B (TW)
Title: Semiconductor device
Inventor: ITO FUJIO
IPC: H01L23/28
Filed: 1999-07-23
Granted: 2001-02-11
Abstract: The present invention relates to a semiconductor device with radiator fins; and, the lead at the front of internal lead connected with the semiconductor chip with width w and board thickness t as w<t; fixing the internal lead with the radiator fins and arranging the swinging lead along with the radiator fins fixed and supported by the internal lead; and, the lead at the front of internal lead connected with the semiconductor chip with lead interval p, width w and board depth t as w<t and p<=1.2t ; fixing the internal lead with the radiator fins that the radiator fins are configured between the semiconductor chip loading area and interconnection and the heat conduction path of the radiator fins are configured with holes in radial shape. Related to a semiconductor device wherein a semiconductor chip is fixed to the heat-radiation plate which is sealed with a sealing material, a plate thickness (t') at the front end of the inner lead is thinner than the thickness (t) at the other parts with the inner lead fixed to the heat-radiation plate.
Patent TW-432810-B (TW)
Title: Heavy-duty audio equipment
Inventor: SMITH ROGER Q
IPC: H01M50/247
Filed: 1999-09-07
Granted: 2001-05-01
Abstract: In accordance with the present invention, an improved audio equipment is employed. The audio equipment includes a housing, audio circuitry installed within the housing, and a first protective bar flexibly connected to the housing. The audio equipment may also include a handle attached to the first protective bar, a second protective bar flexibly connected to the housing, and/or a connector assembly flexibly connecting the first protective bar to the housing. The connector assembly may include a flexible gasket preferably disposed between the first protective bar and the housing. Also disclosed herein is a method for manufacturing an audio equipment.
Patent TW-469480-B (TW)
Title: Processing system
Inventor: TATEYAMA KIYOHISA
IPC: H01L21/00
Filed: 1999-09-27
Granted: 2001-12-21
Abstract: A main transport passage is linearly disposed substantially at the center of a processing system. Auxiliary transport passages are disposed on two sides of the main transport passage and are used sequentially from one end of the main transport passage as auxiliary transport passages for peeling and cleaning processes, auxiliary transport passages for film-forming processes, auxiliary transport passages for etching processes, and auxiliary transport passages for coating and developing processes. The auxiliary transport passages are substantially perpendicular to the main transport passage. Processing devices required for various processes are arranged along the auxiliary transport passages. As such, the processing system has less spatial equipment and high efficiency, and the processing ability thereof can be increased in a stepwise manner.
Patent TW-472261-B (TW)
Title: Static random access memory and semiconductor device using MOS transistors having channel region electrically connected with gate
Inventor: SATO YUICHI
IPC: G11C11/412
Filed: 1999-09-30
Granted: 2002-01-11
Abstract: In an SRAM, memory cells are each constructed of four NMOS transistors and two PMOS transistors 25 and 26. The four NMOS transistors are each constructed of DTMOS in which the channel region is electrically connected to the gate. In each NMOS transistor, a threshold voltage Vth is lower in an ON stage than in an OFF stage. The threshold voltage Vth in the OFF stage is equivalent to that of an ordinary NMOS transistor in which the channel region is not electrically connected to the gate. Read and write circuits of the SRAM also include MOS transistors formed of DTMOS in which the channel region is electrically connected to the gate.
Patent TW-513316-B (TW)
Title: Humectant skin cosmetic containing acrylic acid-based polymer
Inventor: NAGASAWA MAKI
Filed: 1999-11-01
Granted: 2002-12-11
Abstract: The present invention relates to a skin cosmetic, which comprises: (A) an acrylic acid-based polymer; (B) a polysaccharide excluding mucopolysaccharides; and (C) water. Such a cosmetic is capable of persistently feeding moisture to stratum corneum after a long time.
Patent TW-436892-B (TW)
Title: Substrate processing apparatus
Inventor: TAKAHASHI NOBUYUKI
IPC: H01L21/00
Filed: 1999-11-02
Granted: 2001-05-28
Abstract: To provide a practical substrate processing apparatus that does not occupy more area as the number of chambers increases. Four load lock chambers 2 and eight process chambers 101, 102, 103, 104, 105, 106, 17 {sic} and 108 are hermetically connected around the outside of a central separation chamber 3 via gate valves 5 both types of chamber being stacked up in two places and each chamber is capable of being evacuated by its respective vacuum pump system 301, 201 and 100. A transfer mechanism 42 inside separation chamber 3 removes a substrate 9 from a load lock chamber 2, transports it to each of the process chambers 101, 102, 103, 104, 105, 106, 17 {sic} and 108 in a prescribed sequence and thereafter returns it to load lock chamber 2. Each load lock chamber 2 has inside it a substrate holder 22 which always holds a single substrate 9 in the same position.
Patent TW-457224-B (TW)
Title: Method of processing green part for multilayer ceramic process and hollow frame suitable for such a method
Inventor: YUE JIA-WEI
IPC: C04B38/00
Filed: 1999-11-06
Granted: 2001-10-01
Abstract: The present invention provides a method for processing a green part for a multilayer ceramic production process and a hollow frame suitable for such a method. According to the present invention, a hollow frame made of a specific material is used to improve the processing technique of a green part production process (from blanking to lamination), thereby setting up an optimum process condition, and increasing the stability and yield of the RF module, high frequency inductance, and high frequency filter, etc.
Patent TW-440650-B (TW)
Title: Key with built-in transponder
Inventor: SUZUKI MICHIYUKI
IPC: B60R25/24
Filed: 1999-11-17
Granted: 2001-06-16
Abstract: The present invention provides a key with built-in transponder, which has the advantages of easy to be assembled, reduced parts numbers and low production costs. The key with built-in transponder comprises a key plate (1) formed with a insert portion (1e) in the lower part and a wider base portion (1a) in the upper part, a holder (2) in the shape of a thin and flat receiver with an opening (2c) at the lower end and formed therein a wide first receiver portion (2a) and a narrow second receiver portion (2b) separated by a separating wall (2g) biased from the middle, and a transponder (3). Thereby, in the condition that the transponder (3) is received in said second receiver portion (2b), said base portion (1a) of the key plate (1) can be pressed into said first receiver portion (2a) and seal the second receiver portion (2b).
Patent TW-446644-B (TW)
Title: Method and structure for precise temperature measurement of ink-jet printhead heating element
Inventor: CHANG CHARLES C
IPC: B41J2/05
Filed: 2000-01-29
Granted: 2001-07-21
Abstract: The present invention relates to a method and a structure for precise temperature measurement of ink-jet printhead heating element mainly by adding an extra metal layer or semiconductor layer on the ink-jet chip equipped with a driving element. The printhead structure consists of an ink-jet heating element, a transistor driving element, and a temperature sensing resistance layer. The ink-jet heating element includes a heating resistor to heat up the ink. The transistor driving element is used for driving a transistor so as to control the heating of the ink-jet heating element. The temperature sensing resistance layer is located between the transistor driving element and the ink-jet heating element. Located below or nearby the heating resistor, the temperature sensing resistor is connected to the transistor on one end and the electrode contact connected to the printer on the other end. Through the temperature sensing resistance layer, the ink-jet heating element is connected with the transistor driving element.
Patent TW-460909-B (TW)
Title: Method of manufacturing semiconductor device
Inventor: YOSHITAKA HIKARU
IPC: H01L21/311
Filed: 2000-03-08
Granted: 2001-10-21
Abstract: An inorganic insulation film 103 constituted by SiC is formed on a fluorocarbon film 102 utilizing chemical vapor deposition in which SiF4 and C2H4 are used as source gases. By means of using SiF4 and C2H4 not containing hydrogen (H) as source gases, the phenomenon of capturing H into the inorganic insulation film 103 to form a hard mask 113 is prohibited. As such, the H that diffuses outwardly from the inorganic insulation film 103 is coupled with the fluorine (F) in the fluorocarbon film 102 to form HF. The HF prohibits decay of the inorganic insulation film 103. Therefore, deterioration of the bonding between the hard mask 113 constituted by the inorganic insulation film 103 and the other layer, such as the fluorocarbon film 102, can be prohibited.
Patent TW-434114-B (TW)
Title: Apparatus for polishing wafers
Inventor: NUMOTO MINORU
IPC: B24B37/30
Filed: 2000-03-14
Granted: 2001-05-16
Abstract: An apparatus 1 for polishing wafers in which a first pushing means 50 for imparting a pushing force to a carrier 20 is arranged along the outer peripheral portion under the lower surface of a head body 40, and a second pushing means 60 for imparting a pushing force to a retainer ring 30 is arranged at a central portion under the lower surface of the head body. The first and second pushing means are formed of air bags 51 and 61.
Patent TW-469553-B (TW)
Title: Semiconductor factory automation system and method for controlling automatic guide vehicle
Inventor: KO MYUNG-JAI
IPC: G05D1/02
Filed: 2000-06-21
Granted: 2001-12-21
Abstract: A method for controlling an automatic guide vehicle (AGV) in a semiconductor factory automation (FA) system, includes the steps of: (a) receiving operating mode information of a process equipment changed by an operator; (b) storing the operating mode information of the process equipment changed in a real-time database; (c) carrying out a predetermined semiconductor process at an operating mode having a full automation mode and sending a process completion signal after the predetermined semiconductor process has been completed, wherein the predetermined semiconductor process is applied to a lot of semiconductor wafers; (d) creating a queue in response to the process completion signal; (e) checking the operating mode information of the process equipment stored in the real-time database in response to the queue; (f) inactivating the AGV by interrupting a transmission of the queue to the AGV if the operating mode information of the process equipment stored in the real-time database is not the full automation mode; and (g) activating the AGV to unload the lot of semiconductor wafers from the process equipment in response to the queue if the operating mode information of the process equipment stored in the real-time database is the full automation mode. The method in accordance with the present invention can effectively control the AGV by checking operating mode information stored in a real-time database in order to inactivate the AGV in a semiconductor FA system, when an operating mode is changed from a full automation mode to another mode by a system operator.
Patent TW-455963-B (TW)
Title: Semiconductor device and assembly method of the same
Inventor: SUGIURA RIKIO
IPC: H01L21/301
Filed: 2000-07-10
Granted: 2001-09-21
Abstract: The object of the present invention is to prevent a copper pad from being oxidized after bonding from wafer to die. To achieve the object, the assembly method comprises: an anti-oxidation tape pasting process where an anti-oxidation tape 2 is pasted on the surface of a wafer 1 where pads are formed of copper or copper alloy; a dicing process where a anti-oxidation dicing tape is pasted on the backside of the wafer 1 to form grooves 4 for the wafer 1; and a die bonding process where the semiconductor chip 5 with the anti-oxidation tape 2 is bonded to the lead frame 6 or the like.
Patent TW-504712-B (TW)
Title: Manganese-zinc (Mn-Zn) based ferrite
Inventor: TAKAGAWA KENYA
IPC: C04B35/38
Filed: 2000-08-30
Granted: 2002-10-01
Abstract: MnZn ferrite comprises a main component comprising iron oxide 52.5 to 54.0 mol % in terms of Fe2O3, zinc oxide 7.7 to 10.8 mol % in terms of ZnO, and manganese oxide of the remaining, and sub-components of silicon oxide 60 to 140 ppm in terms of SiO2 and calcium oxide 350 to 700 ppm in terms of CaO, and further contains nickel oxide 4500 ppm or lower (not including 0) in terms of NiO.
Patent TW-552682-B (TW)
Title: Improved NROM floating gate in flash memory and manufacturing method thereof
Inventor: JANG GUO-HUA
IPC: H01L21/8247
Filed: 2000-11-07
Granted: 2003-09-11
Abstract: The present invention discloses an improved NROM floating gate in flash memory and manufacturing method thereof. Silicon-oxy-nitride is used by the present invention to replace the floating gate formed of silicon nitride in the well-known NROM flash memory. By using the present invention, the endurance and reliability of NROM is improved, the retention for charges to remain in the floating gate is increased. Furthermore, the present invention discloses a manufacturing method of NROM in flash memory. By using the manufacturing method of the present invention, the processing steps of manufacturing NROM in the prior art can be reduced effectively, and the defects resulted from cleaning the chip can be eliminated to thereby increase the yield rate of NROM.
Patent TW-483031-B (TW)
Title: Thin film forming device and thin film removing device
Inventor: YAHIRO SHUNICHI
IPC: H01L21/00
Filed: 2000-11-09
Granted: 2002-04-11
Abstract: This invention provides a thin film forming device and thin film removing device. The thin film forming device is provided with a resist liquid coating part for forming the thin film of a resist liquid by rotating a substrate while applying the resist liquid on the surface of the substrate, a thin film removing head for removing the unnecessary thin film covering the peripheral part of the substrate by spraying a solvent to the peripheral part of the substrate, a moving structure for driving the thin film removing head along the peripheral part of the substrate a storing part for storing a section A speed for a section A and a section B speed for a section B by dividing the moving range into the section A and the section B and a control part for operating the driving part of the thin film removing part at the section A speed in the section A and at the section B speed in the section b by taking out the section A speed and the section B speed from the storing part. The generation of residue of a resist film on four corners of a substrate is prevented through the setting by the more simplified procedure.
Patent TW-500959-B (TW)
Title: Insulating substrate for forming conductive thin film and liquid crystal display device using the substrate
Inventor: TERAKADO MASAMICHI
IPC: G02F1/1368
Filed: 2000-11-15
Granted: 2002-09-01
Abstract: This invention provides an insulating substrate for forming conductive thin film and liquid crystal display device using the substrate to enhance adhesion of a wiring film to a substrate for the purpose of enhancing reliability of wiring and to enhance resist adhesion for the purpose of enhancing accuracy of wiring patterns. An insulating substrate 101 is cleaned with oxygen plasma and stabilized by treatment with nitrogen plasma to form a clean treated layer 102. Then a conductive thin film having three-layered structure consisting of a nitride layer 103 of a conductive metal, a nitride layer 104 of a conductive metal, and a nitride layer 105 of a conductive metal is formed by a sputtering method.
Patent TW-594681-B (TW)
Title: Overshoot control for a hard disk drive write head
Inventor: TETERUD PATRICK M
IPC: G11B5/02
Filed: 2001-02-07
Granted: 2004-06-21
Abstract: An improved write drive circuit which includes a discharge circuit added to the base of the bottom transistors of the H-bridge to prevent excessive overshoot and ringing while allowing for higher data rates. The discharge circuit is turned on after the head voltage or current reaches an overshoot condition. In preferred embodiments, the discharge circuit includes variable discharge capability by selecting one or more parallel drive transistors or varying a variable delay in the discharge circuit or any combination of both variables. Both can be controlled by a word written to the disk drive pre-amp over the serial control port.
Patent TW-536432-B (TW)
Title: Method and system for processing a sheet member, and various devices relating to such system
Inventor: KOYAMA JUNICHI
IPC: B21D5/02
Filed: 2001-01-16
Granted: 2003-06-11
Abstract: The present invention is to efficiently and precisely conduct bending by measuring an actual plate thickness and a material attribute in punching before bending and reflecting the measured information to bending. In a blank working process before bending a work W, respective blank materials, which are extended based on a nominal thickness and a nominal material constant of the work W, are punched, based on the various data of a ram stroke, pressure, etc., detected in punching, an actual plate thickness distribution and material constant distribution of the work W are calculated.
Patent TW-503398-B (TW)
Title: Semiconductor device and semiconductor device testing method
Inventor: FUJIOKA SHINYA
IPC: H01L27/04
Filed: 2001-01-17
Granted: 2002-09-21
Abstract: A semiconductor device which has a test mode for testing the semiconductor device, is provided with a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.
Patent TW-567700-B (TW)
Title: Method of registration a user on a directory server of an internet type network and/or of localization of a user on this network, and chip card for using such method
Inventor: URIEN PASCAL
IPC: G06K19/00
Filed: 2001-02-09
Granted: 2003-12-21
Abstract: The present invention relates to a method of registration of a user on a directory server and/or localization of a user on an internet (RI) type network, by interrogation of a directory sever (SAi), so as to determine the address ""IP"" associated with this user. For doing this, to use a chip card (2a) storing the applications (Al) associated with each of the registration and/or localization protocol (""PL""). The subscriber profiles can be stored in a chip card (2a), several different protocols can be stored, and transforming the chip card (2a) into the data-based multi-directory. The chip card (2a) is given the ""WEB"" client/server and ""CGI"" functions, so as be able to initialize the transmission according to Internet protocol between the directory server (SAi) and the chip card (2a), and activate the applications (Al) stored is the chip card (2a), for the processing of the registration and/or localization protocols (""PL""). The present invention also relates to the associated chip card.
Patent TW-483173-B (TW)
Title: Thin film transistor array structure
Inventor: YOU JIAN-SHENG
IPC: G02F1/1343
Filed: 2001-02-19
Granted: 2002-04-11
Abstract: A thin film transistor array structure is disclosed, wherein the capacitive coupling effect between the source electrode and the data line is kept constant on each part of the liquid crystal display panel, said structure is mainly forming electrodes on both sides of the pixel electrode close to the data line, this electrode and data line are located on the same photomask, thereby the distance between the electrode and data line is kept constant, then connect this electrode and the pixel electrode, and the edge of the pixel electrode does not exceed the range of electrode, the capacitive coupling effect between the pixel electrode and the data line is identical to the capacitive coupling effect between said electrode and data line, and the capacitive coupling effect between the electrode and the data line is kept constant, therefore, even if the position of the pixel electrode is deviated to vary the distance between it and the data line, the capacitive coupling effect between the pixel electrode and the data line is still kept constant, so as to avoid the alignment error of the pixel electrode in the process, which results in the variation of the optical characteristics among different pixels.
Patent TW-496045-B (TW)
Title: Correction of received signal and interference estimates
Inventor: HE NING
IPC: H04B17/00
Filed: 2001-02-23
Granted: 2002-07-21
Abstract: An apparatus and method are described in which a corrected signal to interference ratio (SIR) is determined in a cellular telephone receiver. First, the estimated signal strength at the receiver is measured, then the estimated interference level is measured. Before calculating the SIR value to be corrected, the independent components, namely the signal strength and the interference values are first corrected in accordance with the given algorithm. Thereafter, the SIR corrected value is obtained by applying as a ratio the corrected signal strength and the corrected interference values.
Patent TW-538088-B (TW)
Title: Chemical amplification resist compositions
Inventor: TAKEDA TAKANOBU
IPC: G03F7/039
Filed: 2001-03-08
Granted: 2003-06-21
Abstract: A chemical amplification positive resist composition comprising a polymeric mixture of a polyhydroxystyrene derivative having a Mw of 1000-500,000 and a copolymer of hydroxystyrene and (meth)acrylate having a Mw of 1000-500,000, as a base resin, has improved dry etching resistance, high sensitivity, high resolution, and process adaptability, and is suppressed in the slimming of pattern films after development with aqueous base.
Patent TW-521436-B (TW)
Title: Integrated circuit device with MIM capacitance circuit and method of manufacturing the same
Inventor: WAKABAYASHI MASARU
IPC: H01L21/02
Filed: 2001-03-22
Granted: 2003-02-21
Abstract: A first conductive layer of metal silicide, a silicon layer, an insulating layer, and a second conductive layer of metal or metal silicide are deposited in the order named on a surface of a semiconductor substrate. Thereafter, the second conductive layer and the insulating layer are patterned to expose the silicon layer. The exposed silicon layer and the first conductive layer are patterned, thereby forming an MIM capacitance circuit.