Patent GB-1445031-A (GB)
Title: Broadcast receivers
IPC: H03J7/28
Filed: 1974-01-03
Abstract: 1445031 Radio receiver tuning; AFC; muting circuits SONY CORP 3 Jan 1974 [9 Jan 1973] 00281/74 Headings H3Q H3A and H3T A broadcast receiver comprises a tuner 1 having a variable frequency local oscillator, a divider 9, 18 consisting of a dividing means 9 and a counter 18 the dividing means 9 operating to divide a signal derived from the local oscillator in response to the contents of the counter 18, a comparator 10 for comparing the divided signal derived from the divider with a reference signal 13, 14 to produce a control signal controlling the tuner 1 and a muting circuit 4 operating to prevent a lower frequency signal derived from the tuner 1 being delivered to an output 5 during time intervals during which the contents of the counter 18 is changed by a pulse from a pulse generator 20. In the FM receiver shown the output from the local oscillator 1 is mixed in a mixer 7 with an output from a frequency doubler supplied from a crystal oscillator 11. The mixed output is supplied via a ¢ divider 8 to a divider 9 which has its divide ratio set by station selection counter which is driven by pulses from a control circuit 20. A frequency and phase comparator 10 co-operate with the divider 9 and station selection counter 18 which are disclosed in detail (Fig. 2, not shown) and the output of a Schmitt trigger 14 fed by a reference signal generator 13 to provide a phase locked loop controlling the local oscillator to the channel selected. The divider 9 includes decimal counters (15a, 15b) and a binary counter (15c) the outputs from which are fed to a discriminator (16). When these outputs are a predetermined number as detected by the discriminator (16) a gate circuit (17) is opened through which the contents of counters (18a, 18b) which form the station selection counter 18, in accordance with the respective figures of counter 18 are set in the counters (15a, 15b and 15c). The contents of the station select counter 18 is applied to binary-decimal decoders 21a and 21b disclosed in detail (Figs. 4 and 5, not shown) the decimal output from which is applied to a non-volatile memory 29 and to a panel display device 47 including neon lamps (P0, Fig 10 not shown) arranged in rows and columns (Fig. 9, not shown). The memory 29 comprises two memorymembers (29a, 29b, Fig. 5, not shown) each provided with non-volatile memory elements such as MAOS FET elements (Fig. 6, not shown) which memorizes the channel whilst the panel display device 47 displays this channel. When a push button switch (S0-S99) of an associated neon lamp (P0-P99) of the display device is operated a stop signal is applied to a pulse generator of the control circuit 20 to stop the supply of station select pulses to the station select counter when the channel corresponding to the operated switch is obtained. When the phase locked loop is operated or the station select pulse is applied for searching of the desired broadcast wave a circuit 76 (Fig. 11, not shown) operates the muting circuit 4, such as a FET T, Fig. 31, to turn it off and prevent output from a stereo multiplexer 5 during searching. A capacitor (66) delays turn on of the FET T in the muting circuit 4 at the end of the station select pulse. The muting circuit 4 may be connected between the stereo multiplexer 5 and the output. A non-volatile memory 56 using MAOS FET (Q 1 -Q 9 , Fig. 11, not shown) memorizes the content of the counter 18 every time its content changes so that when the power source is cut-off on turning the power source on the broadcast wave which was previously received is tuned to. Instead of using non-volatile elements for the memory 56 a separate electric power source may be provided for the memory 56. The control circuit 20 is disclosed in detail (Fig. 16, not shown) and includes flip-flop and gating circuits controlling a station select pulse generator (100) providing 3 kHz output and a second station select pulse generator (101) providing 17 kHz output. The control circuit 20 also has a detector circuit (104) which provides an output when the IF amplifier 2 produces a sufficient IF output at tuning. The receiver is controlled by button switches (91, 96, Fig. 14, not shown) provided on a front panel around the display device 47 to provide Search, Next, Auto, Program, In and Reset operation. For Search operation the received frequency is switched from a certain frequency to another frequency. When the Next operationa button switch (92) is operated the frequency is changed sequentially by one station. For the Auto operation the memory 29 is made operative and all of the stations capable of being received are displayed on the panel display 47. For the Program operation the memory 30 is made operative and the stations which are programmed are displayed on the panel display 47. When the In button switch (95) is operated during the reception of a certain frequency signal, the received frequency signal is stored in the memory 30 to achieve the programme. When the Reset button switch (96) is operated during the Auto mode a received band between 88À1 and 107À9 MHz is swept and a received frequency of sufficient signal strength is automatically written into the memory 29. Then the mode is changed to Search mode and the stored frequency is displayed on the panel display 47. When the Reset button switch (96) is operated during the Program mode the content stored in the memory 30 is erased.