Patent GB-1250528-A (GB)
IPC: H03K5/156
Filed: 1968-11-01
Abstract: 1,250,528. Electronic circuits, digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 1 Nov., 1968 [6 Nov., 1967], No. 51901/68. Headings H3T and H4P. In a binary pulse repeater which in response to the input pulses provides synchronizing pulses, data signals indicative of the binary values and regenerated pulses derived in response to the synchronizing and data signals, the data signals are provided by an operational amplifier arranged to rectify the input pulses and a further operational amplifier receives the rectified and input pulses and provides intermediate pulses from which the synchronizing pulses are derived. Bipolar digital data signals Ve (Fig. 4a) have their negative going portions inverted and a mean D.C. level inserted so as to provide signals Vs and these are then squared to produce Vso. From the squared signal is produced a clock train- Vh and, by differentiation, sampling signals Vr. Also from the input signals is produced a polarity indicating signal, SIGN. The input signal Ve, the squared signal VSO the sampling signal Vh, and the SIGN signal are applied to NOR gates 10, 10<SP>1</SP> (Fig. 3) and the clock signal is applied to control circuits 8, 8<SP>1</SP> to control two bi-stable circuits 7 and 7<SP>1</SP> such that coincidence of all three signals switches the corresponding bi-stable circuit to provide a zero voltage at I or J and thus an output pulse at V1 (see also Fig. 4a) corresponding in polarity to the input signal. Notwithstanding the early termination of the trigger circuit the bi-stable circuit is held by circuits 8, 8<SP>1</SP> until the end of the clock pulse and cross-coupling between the bi-stable circuit prevents simultaneous operation. The SIGN information is produced from the input signal Ve by an amplifier C (Fig. 1) having feedback through diodes. Inversion of the negative polarity portion of the signals Ve and insertion of the mean D.C. component is also effected by the circuit of Fig. 1. The signal Ve is applied through resistors R1 and R5 to the two inputs of amplifier A. During positive going signals diode Di1 is conducting so that point K is at virtual earth and only the input to the amplifier via R1 is effective. During the negative half cycle diode Di2 conducts to provide an effective earth at the lower end of R6 so that the positive input of amplifier A receives a signal dependent upon the ratio of R5 and R6 which chosen to over-ride the input through R1. Accordingly the signal is effectively full wave rectified and the output of amplifier A is of one polarity independently of the polarity of the input signal. A D.C. component equal to half the peak amplitude of the output of the amplifier is applied at terminal E and is produced by a peak rectifier D3, C1 and smoothing and attenuating circuits R3, R4, C2. Negative feedback is provided through R2 and diode D2 which compensates for the voltage drop in D3 when conducting and the diode D1 on which provides continuity when D2 is not conducting. The squaring circuit for the full wave rectified and D.C. restored signal Vs comprises a current switching circuit T1, T2 (Fig. 2) and a diode-connected transistor T<SP>1</SP>2 which clamps one limit of the output of T2. The clock pulse generator (Fig. 2) receives the full wave rectified and D.C. restored signal Vs and passes it to a ringing circuit L1C4 the output of which is squared by T4, T5, D5 and D6. The sampling signal Vh is obtained from this via T6 and T7 and an inductive differentiator including a blocking capacitor C5 and a diode D7 which removes positive peaks at the trailing edge of the differentiated clock pulses. The gating and bi-stable circuits of Fig. 3 are shown in Fig. 4. Considering only the upper part of this circuit, current through R15 and R16 provides bias to hold T14 off and thus T15 on so that points I and J are are the same potential. Concurrence in negative sign of the SIGN signal, the squared signal Vso and the sampling signal Vr at the input of a NOR gate T8, 11 causes the R15 current to be diverted to T11 and a concurrent clock pulse at Vh causes T13 to conduct. The base current of T14 is thereby removed and a bi-stable circuit T14, T15 changes state producing a zero output at I and a pulse of one polarity at output VL. The termination of the sampling pulse causes T11 to conduct again but the current through T3 is sufficient to hold the bi-stable circuit latched until the clock pulse terminates and T13 is thus cut off, whereupon the bi-stable circuit restores to terminate the output pulse. When the SIGN signal is of opposite polarity the lower part of the circuit operates to produce an output pulse of opposite polarity, cross coupling between the two bistable circuits preventing the two bi-stable circuits being in the same state.