Patent GB-1482688-A (GB)
Title: Storage configuration comprising a main store and a buffer store
IPC: G06F12/0864
Filed: 1974-12-18
Abstract: 1482688 Digital storage systems; testing digital stores PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 18 Dec 1974 [21 Dec 1973] 54P26/74 Heading G4A A digital data processing system comprises a relatively slow and large capacity main store MS, Fig. 2, e.g. a magnetic core store, a relatively fast and small buffer store BS, e.g. an integrated semi-conductor store, an incoming word address A from an address register AR being compared in a comparison device V with word block addresses ab0-ab3 stored in an address register AS of the buffer store BS; if a comparison is found one of the word blocks wb0-wb3 stored in BS is selected by lines l0-l3 for use by a processor P via an I/O register BSR of the buffer store; if a comparison is not found a signal on a line l4 causes the word block WB with the desired address to be accessed in the main store MS by a selection unit SE and used by the processor P via an I/O register MSR; at the same time that word block and its address are respectively stored in the buffer store BS and in the address store AS. The invention resides in the additional features of a control unit C (bounded by broken lines), wherein an address generator AG generates successive addresses 00, 01, 10 and 11 on lines a0, al, these successive addresses being converted to complete addresses A<SP>1</SP> by having prefixed thereto a series of "0"s and being passed via an enabled gate PS to the address store AS, the address blocks ab0-ab3 being successively selected by signals on lines da representative of the decoded output of address generator AG (via a decoder AD) and being loaded with the complete addresses 00 ... 00, 00 ... 01, 00 ... 10 and 00 ... 11 so that the buffer store BS may operate as a normal store when it is addressed via the address store AS. The decoder AD may be omitted if a decision unit BI, which determines into which block of the address store AS an incoming address from the main store MS shall be overwritten, is set to its starting position by a command RC. The decision as to which word block shall be overwritten may be made on the basis of "first-in, first-out", "last-recently used" or "frequency of use"; and the word block overwritten in buffer store BS and its address in AS may be transferred to the main store. Indexing of the addresses may be effected by prefixing with other than "0" bits. In a modification (not illustrated nor described in detail), the buffer store BS and address store AS are replaced by an associative store. A plurality of processors P and/or a plurality of main stores MS and buffer stores BS may be provided (Fig. 1, not shown). Testing of the buffer store BS may be carried out by disabling the decoder AD by means of a-signal nad, successively generating the addresses A<SP>1</SP> and writing 1 bits into all the word blocks of BS, generating the addresses A<SP>1</SP> again and reading the word blocks from BS; the outputs from BS should all be 1 bits and are detected as such by an AND gate N(EN). The test is then repeated with 0 bits obtained via an inverting circuit INVPS, the read-out contents of buffer store BS being inverted before being fed to AND gate N(EN). The address store AS may also be tested by storing the successive addresses A<SP>1</SP> therein and interrogating them for correspondence to the read-out values by means of the comparison device V; this test is also repeated with inverted addresses. In Fig. 4, the main store MS, buffer store BS and address store AS are each divided into groups of (word or address) blocks, an incoming address having a part c which determines which group of blocks shall be accessed. The groups are selected by group detectors GDM (for MS) and GD (for AS, BS) in turn fed with addresses from respective address registers DAR, AR.