Patent GB-807882-A (GB)
Title: Improvements in electronic calculating circuits and devices
IPC: G06F7/52
Filed: 1955-11-17
Abstract: 807,882. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 17, 1955 [Nov. 22, 1954], No. 32939/55. Class 106 (1). Electronic multiplying and dividing apparatus comprises first and second shifting register storage means, a product generator adapted to receive an input representing a first number and to manifest a series of outputs each representing a different multiple of said first number, a plurality of selecting devices each operable on receipt of an input representing a second number of select that output of the product generator representing the multiple of said first number by said second number, and switching means for performing multiplication and division and for entering the result of such calculation in the storage means. The main embodiment, Figs. 20A-20N, arranged as shown in Fig. 20P, can multiply or divide two thirteendigit decimal numbers registered in two shifting registers, Figs. 20M and 20N, each decimal-digit being registered on the binary scale and being transferred serially over four parallel leads (this being indicated in the drawing by a bracketed four adjacent to the data paths), and comprises basically a multiplier unit to which switching means have been added to enable division to be performed. The result of a division or multiplication operation is entered into one or both, respectively, of the two registers. Multiplication.-Three decimal denominations of the multiplier unit forming the basis of the main embodiment are shown in Figs. 16A and 16B, arranged as in Fig. 16C, and an example of its operation multiplying 523 by 154 is shown in Figs. 16D, and 15A-15E. The unit comprises a product generator which receives serially on four parallel leads the binary coded decimal digits of the multiplicand (523)-lowest denomination first-and which after a four-digit delay provides simultaneously on nine sets of four leads serial signals representing the nine multiples of the multiplicand with the digits 1-9, three binary-to-decimal converters 597, one per denomination, which receive the staticized binary coded multiplier digits (154) and which as a result energizes one or none of nine output leads causing an associated selector switch 591 to select the corresponding multiple of the multiplicand and to pass it to its output terminals 195, and three serial adders 594-596, one per denomination (excepting the highest denomination where the adder is replaced by a one-digit delay), which have an internal delay of one digit. In operation the staticized multiplier digits are applied to the binary-to-decimal converters, the multiplicand is entered serially into the product generator, and after a delay of five-digit periods the product digits-lowest denomination first-emerge from the adder in the units denomination. This is shown in Fig. 16D, where time intervals 6-10 correspond respectively to Figs. 15A-15E. In the main embodiment, Figs. 20A-20N, which is controlled for multiplication by signals (Fig. 10E not shown) produced by a control unit (Figs. 10A-10C, not shown) stimulated by a single multiply signal, the multiplier, staticized in register 1, is applied to the binary-to-decimal converters 830-842, and the multiplicand, staticized in register 2, is shifted " rightwards " out of register 2 and entered into the product generator. Shift of the multiplicand from register 2 to the product generator continues and after 8 digit-periods the digits of the product begin to emerge from adder 801M and are passed via switch 799, Fig. 20N, to the thirteenth position of register 2 where, as the multiplicand digits are shifted out, they are shifted in. This continues until the first twelve lowest order digits of the product have been shifted into register 2, which occurs 20 digit-periods after the start of multiplication, whereupon subsequent product digits are switched to digit position 13 of register 1 and shifted in concurrently with the outward shift of the multiplier formerly staticized therein. The fact that the multiplier digits are no longer applied to the appropriate binary-to-decimal converters is of no significance because by this time all the product generator's outputs will be zero. During the 32nd digit period, i.e. the period when the 25th product digit is entered into register 1, thus filling register 1, the output of adder 851, Fig. 20A, is examined by the control unit via terminal 102P to ascertain whether or not the 26th product digit is zero. If the 26th product digit is zero, shift of register 1 is stopped resulting in the 13 highest ordered digits of the product being in register 1 and the remaining 12 digits in register 2, otherwise, if the 26th product digit is not zero, one further shift of both registers 1 and 2 is made, the digit being shifted out of register I being shifted into register 2, resulting in the 13 highest ordered digits of the product being in register 1 and the remaining 13 being in register 2. No means are described for locating the decimal point and it is stated that this is left to the operator. An example multiplying 4,976,542,286,321 by 5,463,819,710,709 is described (Figs. 21A-21D arranged as in Fig. 21E, not shown). A second multiplier unit is described (Fig. 18, not shown) similar to that shown in Figs. 16A and 16B except that the multiplicand is entered serially by bit as well as serially by digit, and thus the product generator and the adders are appropriately modified. Two further multiplier units are also described, both using simplified product generators only producing the products 1M, 2M, 4M and 8M, the first (Figs. 17A-17C arranged as in Fig. 17D, not shown) operating serially-by-digit and parallelby-bit, similarly to that shown in Figs. 16A and 16B, and the second, Figs. 19A, 19B, arranged as in Fig. 19C operating serially both by bit and digit. In this embodiment three adders 711, 715 and 718, Fig. 19A, together with their associated delays, constitute the product generator. The numbers in rectangular boxes indicate numbers that pass by in multiplying 523 by 154. Division.-An example of ordinary long division is shown in Fig. 22A. In the apparatus described this division is performed in the following steps: first the dividend is complemented on nines, Fig. 22B, and has added to it the largest integral multiple of the divisor that does not result in a carry from the highest denomination; this addition gives a first partial dividend and the multiple of the divisor added gives the first quotient digit: secondly the first partial dividend is shifted one digit to the left and has added to it the largest multiple of the divisor that does not result in a carry from the highest denomination thus giving the second quotient digit and a second partial dividend: this process is repeated until the quotient is determined. The determination of the largest multiple of the divisor that can be added to the nines complement of the dividend is determined by a quotient generator, Fig. 20E: each of the adders 841-849, Figs. 20A, 20E, 20C, is fed with the nines complement of the dividend via its associated 4-pole 2-position switch, and also with a corresponding one of the multiples 1-9 of the divisor and thus simultaneously nine different additions are performed; the sum outputs 102 of the adders go to the next lower 4-pole 2-position switches which block them and the carry outputs 61C go to the quotient generator which is such that it produces an output on one of nine leads indicating the " number " of the lowest adder from which no carry occurs and thus the highest multiple of the divisor, i.e. the quotient digit, can be determined by sampling the output of the quotient generator at the time when carry from the highest denomination would occur. A complete division operation, which is controlled bypulses (Figs. 11F, 11G, not shown) produced by a division control circuit (Figs. 11A-11D arranged as in Fig. 11E not shown) is as follows: (a) the dividend and divisor are entered into registers 1 and 2 respectively, Figs. 23A, 23B, 23F, 23G arranged as in Fig. 23M; (b) during the first cycle of 16 digit periods the divisor in register 2 is shifted cyclically and applied to the product generator and after a 5-digit period the dividend is shifted out of register 1 into a nines complement generator and thence into a circulating storage loop comprising a 4-pole 2-position switch 886, Fig. 20J, a 1-digit delay DC887, a 4-pole 2-position switch 860M, the adder 801M and a 15-digit delay 888. Thus as the digits of the nines complement of the dividend emerge from adder 801M and enter adders 841-849, so also do the digits of the nine products of the divisor, the individual products 1 to 9 being selected by the 4-pole 9- position selector switches 811-819 and their associated binary to decimal converters. Cyclical shift of the divisor register continues for 13-digit periods until the divisor has made a complete cycle and then stops until the beginning of the second 16-digit-period cycle, when it recommences. Shift of the dividend continues for 13 digit-periods until the register is empty, which happens in the second period of the second cycle. During the fifth digit period of the second cycle when the highest ordered digit of the nines complement of the dividend is being added to the multiples of the divisor, the output of the quotient generator is sampled by applying a single shift-lift pulse to register 1, thus entering the first quotient digit, and since the first position of register 1 controls the switch 860M, on the next cycle of the nines complement around the storage loop it has added to it the corresponding multiple of the divisor. In a similar manner a second quotient digit is determined, entered into the register 1 and used to control the addition of a further multiple of the divisor to the number circulating in the storage loop-the partial dividends in the storage loop automa