Patent GB-900611-A (GB)
Title: Improvements in receivers for use in phase-shift signalling systems and in systems incorporating such receivers
IPC: H04L27/20
Filed: 1959-02-17
Abstract: 900,611. Pulse signalling. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 17, 1959 [Feb. 18, 1958], No. 5477/59. Class 40 (5). In a data transmission system of the type in which input signal pulses phase-shift a subcarrier in accordance with the information to be transmitted and transmission is effected via a single side-band suppressed carrier channel, a pilot signal is transmitted and utilized at the receiver to generate a synchronizing signal. As shown in Fig. 5, at the transmitter a master clock unit 14 generates synchronizing signals M.C.S., Fig. 6, at a frequency of 800 pulses/sec., and through a filter 20 selecting the third harmonic, provides a sub-carrier SCS at a frequency of 2400 c/s., which is amplified at 21 and supplied via a cathode follower 22 to a phasemodulator 28. An input signal IF from a device 12 is supplied at a rate of 1600 bits/sec., controlled by a clocking signal ICS as by selecting the second harmonic of the master clocksignal. The signal IF is supplied to the modulator 28 whereby the subcarrier is modulated so that if a " 1 " is transmitted the subcarrier H is in phase with SCS and if a " 0 " is transmitted it is in antiphase. The pilot signal PS at a frequency of 800 c/s., is supplied from the master clock unit 14 through a filter 36 and cathode follower 37 and is supplied to a summing unit 16 together with the phase-modulated subcarrier H to be transmitted via a single sideband suppressed carrier communication channel (not shown). At the receiver, Figs. 7a, 7b, the received signals H<SP>1</SP>, Fig. 9, which may have been given a frequency spectrum shift due to the transmission channel characteristics, are amplified at 90 and supplied to a sub-carrier regenerating circuit including a 1 bit delay unit 50. The output of the circuit 50 and the information signal output I.O.S. from the terminals 106, 107, are supplied to a balanced modulator 51 which operates in a similar manner to that at the transmitter to reconstitute the subcarrier SCS<SP>1</SP>. The output of the modulator 51 is supplied via a filter 52, amplifier 53, and squaring circuit 54 to supply a square wave (SCS<SP>1</SP>)<SP>2</SP> to the signal detector 43 and clock pulse generator 41. A signal RCS is generated by the clock pulse generator, a filter 70 selecting the pilot signal from the incoming signals which is supplied via an amplifier 71 to a balanced modulator 72 which receives as its other input the squared sub-carrier wave (SCS<SP>1</SP>)<SP>2</SP>. The modulator 72 produces an output signal corresponding to the bit rate of the system, i.e. 1600 c/s., the difference frequency between the 800 c/s. pilot signal and the 2400 c/s. subcarrier signal, which is selected by a filter 73 and phase-adjusted at 74 to provide an input RCS to a squaring circuit 80. The squared signal (RCS)<SP>2</SP> is supplied to a control unit 81 which provides triggering pulses for a blocking oscillator 82 which supplies squelch pulses S.P.S. to the squelch circuit 93 of the signal detector circuit 43. The blocking oscillator 82 also controls output gates 100, 101, by means of gating pulses GPS supplied through a delay circuit 83. The phase-modulated subcarrier H<SP>1</SP> from the amplifier 90 is supplied to a demodulator 91 which receives as its other input the square-wave (SCS<SP>1</SP>)<SP>2</SP> and provides an output DMS which is integrated at 92 to provide an output IS, the capacitor 92C being discharged at the end of each bit period by the squelch unit 93. The output signal IPS from the integrator is amplified at 94 and controls a flip-flop 99 through the coincidence gates 100, 101, the resulting output signal I.O.S. appearing at the output terminals 106, 107.