Patent GB-1262223-A (GB)
Title: Improvements in or relating to location systems
Inventor: GIBSON RODNEY WILLIAM
IPC: G01S5/14
Filed: 1970-06-26
Abstract: 1,262,223. Radio position finders. MULLARD Ltd. 26 June, 1970, No. 31133/70. Heading H4D. In a location system for determining the position of a mobile station by measuring the arrival times of signals passing between the mobile station and at least three fixed stations, the position of said mobile station arid the time or times of origin of said signal or signals are first assumed and subsequently iteratively corrected to a required degree of accuracy. Radio signals are generally used, but the system is also applicable to light or sound signals. If there are three fixed stations 1, 2, 3, Fig. 2 with respective rectangular co-ordinates (x 1 , y 1 ), (x 2 , y 2 ), (x 3 , y 3 ) and a mobile station at A from which a signal, conveniently a pulse of very short duration (e.g. one micro-second), is received at respective times t 1 , t 2 , t 3 , then it may be assumed that the mobile station is at B, with co-ordinates (x, y), and that the signal was sent at time t<SP>1</SP>. The distance G 1  of the point B from the fixed station 1 is given by, and, assuming for convenience that the signal propagation velocity is unity, the nominal distance T, is given by,  An error factor F 1  is given by, and similarly error factors F 2 , F 3  are derived for the fixed stations 2, 3. Corrections are iteratively applied so as to reduce each error factor in turn, whereby the assumed position of the mobile station is brought nearer and nearer to the true position. Instead of the usual correction of F/2T an approximation such as F/2W is used, where W is given by rounding up T to the nearest integral power of 2. The directions of movement of the assumed position of the mobile station may be made parallel to imaginary lines joining the fixed stations. A system for performing the required computations when there are four fixed stations comprises a subtractor SUB, Fig. 3, having inputs t 1  to t 4  and t<SP>1</SP> and outputs T 1  to T 4 , a first digital multiplexer MX1 with inputs x, y, and T 1  to T 4 , and a second digital multiplexer MX2 with inputs selected from a read-only memory ROM in which the known coordinates x 1  to x 4  and y 1  to y 4  are stored. The system also comprises a first shift register SR1 which recirculates via a digital adder DA, second and third shift registers SR2, SR3, a shift control SH, a sign control logic unit SC, a digital multiplexer DM, a digital accumulator ACC, a "true/ complement/zero" logic unit TC, a decoder DEC and a sequence controller SEQ. The multiplexer MX1 steps in synchronism with the register SR1 so that, at the beginning of a cycle, its contents are arranged as shown in Fig. 3. The register SR1 is stepped by the controller SEQ so that each of the contents appears at the output stage at the appropriate time. In similar fashion, the multiplexer MX2 is stepped so that the appropriate fixed information from the memory ROM is fed into the shift register SR2; the outputs of both registers being combined to produce the terms required in the error factor equations. The fixed station co-ordinates are stored in the memory ROM as negative binary numbers, i.e. - x 1 , - y 1  etc., so that the terms (x - x 1 ) etc. are produced by addition in the adder DA. With the register SR1 in the position shown, x is fed into the adder DA from the register SR1 and - x 1  is fed from the register SR2. The term (x - x 1 ) appears at the output of the adder DA. The digital multiplier DM operates on the said output to produce the term (x - x 1 )<SP>2</SP>, which is fed into the accumulator ACC. The register SR2, the adder DA and the multiplier DM are then cleared. The register SR1 and the multiplexer MX2 are then stepped by the controller SEQ to the y and y 1  positions respectively; the term - y 1  being stored in the register SB2. The adder DA produces (y - y 1 ) which is squared in the multiplier DM and added to the existing information in the accumulator ACC to produce The register SR2, the adder DA and the multiplier DM are now cleared and the register SR1 is stepped to the T 1  position. In the ease of the T terms, the adding function of the adder DA is not required since no term is required from the register SR2. This is effected by retaining the register SR2 at zero so that the adder DA produces the term (T-O) which is squared in multiplier DM to produce +T<SP>2</SP>. It can happen in the course of applying corrections that a T value may become negative in sign, this fact being recorded by an appropriate sign digit stored in the most significant digit position of the relevant T information in the register SR1. The sign digit is fed via the sign control logic unit SC to the multiplier DM and is used to cause the T<SP>2</SP> term in the multiplier to be subtracted from (if T is positive) or added to (if T is negative) the value (x - x 1 )<SP>2</SP> + (y - y 1 )<SP>2</SP> already stored in the accumulator ACC. The value for F 1  is therefore now stored in the accumulator. The F values are divided by a scaling factor W to produce the correction factors and the x and y values are modified by components respectively denoted u and v to produce corrections to the coordinates (x, y). The approximation for W used in this particular embodiment is W = 2<SP>n</SP> x (T rounded off to next lower integer power of 2). This is achieved by the W shift control logic SH which governs the transfer of the F value from the accumulator ACC to the register SR2. The T value in the register SR1 is duplicated in the register SR3 under control of the controller SEQ. The F 1  value is shifted from the accumulator ACC via the true/complement/zero logic unit TC into the register SR2 together with and at the same rate as the T value in the register SR3. When the most significant non-zero digit in the register SR3 reaches the last stage of this register, the shift pulses to the register SR2 from the shift control SH are inhibited. The effect of this is that the final position of the F value in the register SR2 is controlled by the value of T as given by the bracketed term in the above equation for W. The 2<SP>n</SP> term in this equation is implemented by the controller SEQ which produces the appropriate number of additional shift pulses so that the position of the F value in the register SR2 accords with the desired value of n. The desired value of n may be changed during the progressive computation, e.g., the sequence controller SEQ may be arranged so as to vary the value of n after a predetermined number of iterations.  If the controller SEQ is arranged to produce the preferred cycle of operations in which a correction to the assumed time t<SP>1</SP> is first made in respect of the first station error correction (F 1 ¸W now stored in the register SR2), each of the T values is stepped in turn to appear at the output of the register SR1 while the contents of the register SR2 are held static. In this way, each of the four T values has the correction added to it when it passes via the adder DA back into the register SR1; thus, in effect, applying a correction to assumed time t<SP>1</SP> dependent upon the error in the assumed position with respect to station 1. Alternatively, if the method being used is to correct the assumed position with respect to station 1, the sequence controller is arranged to control the operation of the equipment in regard to station 1 in the same manner as will now be described for station 2. The value F 2  is computed and stored in the accumulator ACC in the same manner as described for F 1 ; except of course that the terms x, x 2 , y, y 2  and T2 are selected by the register SR1 and the multiplexer MX2. In this case, the assumed position is to be corrected and this involves resolving the correction magnitude F 2 ¸W into its components (F 2 ¸W) Î u along the OX axis and (F 2 ¸W) x v along the OY axis and adding these to the x and y terms respectively. The direction components are effected by multiplying the F 2  value by + 1, - 1, or 0 in the logic unit TC which either passes the F 2  digits unchanged (multiply by +1), inverts them (multiply by - 1), or suppresses them (multiply by 0). The decoder DEC uses signals from the sequence controller SEQ to select the appropriate function corresponding to the appropriate u or v value. In the manner, a correction for either the T values or for the x and y values can be produced in the register SR2. A shift pulse from the sequence controller then causes the sum of the existing value and the correction to be reentered into the register SR1. The process is repeated for F 3  and F 4  and the whole cycle then repeated; so applying successive corrections to the assumed position to cause it to converge in steps on the true position until the desired accuracy has been achieved.  During the cycling, the values of x and y are progressively corrected and, at the end of the complete operation, the corrected values of x and y are taken from an output OP in turn for use by indicating equipment such as a map plotter or display unit.