Patent GB-1401098-A (GB)
Title: Data storage systems
IPC: G11C19/28
Filed: 1973-09-10
Abstract: 1401098 Digital data storage INTERNATIONAL BUSINESS MACHINES CORP 10 Sept 1973 [15 Nov 1972] 42405/73 Heading G4C A multi-dimensional shift register array includes feedback loops to allow re-ordering of the stored information, e.g. to maintain the most recently accessed information nearest to the access position which itself incorporates a shift register. In a first embodiment, each of a plurality of matrices as shown in Fig. 2 stores a single address or data bit for each word stored, words having a common sector address being stored in the same row of the matrices. Each matrix has a single access cell X, and if the sector address of the word currently in the access position is different from that of an access request, a sector comparator SCU, Fig. 5, causes a signal to be applied to a DOWN input of a shift control unit so that data is shifted down through the rows of cells Z and recirculated over loops L1 until the words with the required sector address are in the bottom row X, Y. If the word address of the word in the access position is not that of the access request, a word comparator WCU causes a signal to be applied to the LEFT input of the shift control unit whereupon the bottom row of each matrix is shifted left and recirculated over loop L3 until the required word is in the access position X and is available for a read/write operation. While that operation takes place, the data stored in cells Y, Z is reordered by shifting cells 7 right over loop L4 (excluding X) so that the data which was previously nearer the X position than the accessed data is finally shifted one place to the right. Similarly the rows are shifted upwards over loop L2 so that the rows which were nearer the bottom row than the row containing the accessed word are effectively shifted upwards by one row. The re-ordering is controlled by a pair of counters C1, C2 which register the number of down and left shifts required to access a word and which are counted down for each up or right shift. When re-ordering is completed (the two shift operations may take place simultaneously), a ready signal is produced to notify the requesting unit that another request may be made. In a modified embodiment, Fig. 7 (not shown), the shift up loop for all columns except that containing cell X includes all cells of the column. This arrangement allows words to migrate between rows. To access a word, shift down is effected until the required word is detected in the bottom row X, Y by full address comparison for each word position. Left shift then occurs until the required word is detected in the access position X, against by full address comparison. Re-ordering of cells Y, Z then takes place, the accessed word remains in cells X, the other words which were in the same row as the accessed word are returned to the pre-access row position but re-ordered by the right shift operation, words which were previously in the left-hand column and below the accessed word are shifted up one row, and the remaining words are returned to their original positions. Modifications.-Instead of using counters to determine the number of shifts required for the accessing and re-ordering operations, a directory may be interrogated with the address of the required word to look up the amount of shift required. The addresses of words may be changed as they migrate from row to row in the Fig. 7 embodiment, the position of words being kept track of by an old-to-new address directory. Words with odd and even addresses may be stored towards opposite ends of the registers to reduce access time as described in Specification 1398204. The system may be extended to an n dimensional array. Check bits relating to the data and address bits may be included in the stored words. The registers may be implemented in FET or magnetic bubble form.