Patent GB-1003329-A (GB)
Title: Cascade multipliers and squarers
IPC: G06G7/28
Filed: 1962-11-06
Abstract: 1,003,329. Electric analogue calculating. A. NATHAM. Oct. 17, 1963 [Nov. 6, 1962; Nov. 13, 1962], Nos. 41963/62 and 42808/62. Heading G4G. A cascade multiplier or squarer for the production of an output signal representing the product of two signals, or the square of a signal, incorporates a first stage which produces from inputs consisting of the two signals to be multiplied, or the signal to be squared and its inverse, a converted signal corresponding with a first approximation of the required output signal by a process which includes the operations of: choice of a maximum or minimum signal from a set of signals, signal amplitude shift and change of sign. The multiplier or squarer also incorporates a generating arrangement responding to the converted signal for producing a further signal which is such that when linearly combined with the converted signal an improved approxim ation to the required output signal is produced, and an adding arrangement for carrying out this combination and producing the output signal. It is shown in the Specification that a product z =1/Mxy, where M is a positive constant and x and y are variables may be derived from the series z=¢u 1  +(¢)<SP>2</SP>u 2 + . .. (¢)<SP>N</SP>u n +z n <SP>1</SP> where u 1 =max (min (x, y), min (- x, - y)) u 2  = max (min (u 1 , v 1 <SP>1</SP>), min (- u 1 , - v 1 <SP>1</SP>)) vl<SP>1</SP>=v 1  - i<SP>M</SP> v 1 =max (x, y, - x, -y) and generally u i <SP>+</SP>1=max (min (u i , v 1 <SP>1</SP>) min (- u 1 , - v 1 <SP>1</SP>)) v i + 1 =max (u i , v 1 <SP>1</SP>, - u i , - v 1 <SP>1</SP>) v<SP>1</SP> i + 1 =v i + 1  - M/2 i + 1  and Z n <SP>1</SP>=u n v n <SP>1</SP> Thus a first approximation to z will be ¢u 1  and a second (improved) approximation according to the invention will be ¢u 1 +u 2 . A suitable circuit (Fig. 2) for determining u 1  involves diode arrangements such that at the junctions 2 and 4 signals corresponding to the minimum of x and y and the minimum of - x and - y respectively are produced and then at the junction 3 the maximum of these two signals is derived. Similar diode circuits for evaluating - u 1 , v 1  and - v 1  are illustrated in the Specification (Figs. 3-5, not shown). An arrangement according to the invention (Fig. 7) incorporates four such circuits A, B, C, D, which from inputs x, y, - x, -y determine the quantities u 1 , - u 1 , v 1  -v 1  these quantities appearing on the lines 9, 10, 11, 12. To the signals representing v 1  and - v 1  constant currents are added or subtracted, derived from the current generators 15 and 16, so that signals representing v 1 <SP>1</SP> and - v 1 <SP>1</SP> are derived at the points 17 and 18. The signals u 1 , - u 1 , v 1 <SP>1</SP> and - v 1 <SP>1</SP> are fed via impedance converters 19 to a set of lines 20-23, which are used to supply inputs to a second similar arrangement of circuits A, B, C, D. Similarly, outputs u 2 , - u 2 , v 2 <SP>1</SP> and - v 2 <SP>1</SP> are fed to the lines 24, 27 from which inputs are fed to a multiplier 28 to give an output z 2 <SP>1</SP>. Signals related to u 1 , u 2  and z 2 <SP>1</SP> are fed to the sign changing adder 31 to produce an output signal related to the required quantity z. Other possible arrangements are indicated in the Specification (Figs. 8 and 9, not shown), and reference is made to a time sharing arrangement whereby signals such as u 1  are stored and also fed back as an input to the same circuitry, the output (e.g. u 2 ) then being added to the quantity in the store and also fed back again. Squaring arrangements (Figs. 10 and 11, not shown), using modifications of the multiplying arrangements, are referred to. Specification 939,486 is referred to.