Patent GB-957503-A (GB)
Title: Improvements in or relating to pulse code modulation systems
Inventor: DAVIS JOHN CHRISTOPHER HAMMOND
IPC: H03M1/00
Filed: 1959-11-13
Abstract: 957,503. Pulse code modulation systems. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. Nov. 14, 1960 [Nov. 13, 1959], No. 38629/59. Heading H4L. In a pulse code modulation system logic circuits are employed for giving an amplitude compression effect in conjunction with an encoder including a comparator. The system described involves ten binary digits plus a sign digit which are converted into a code of six binary digits plus a sign digit. The arrangement is as follows. Starting from the most significant digit the number of consecutive 0's up to the 6th place is counted and this number translated into a 3-digit binary code. If the number of 0's does not exceed 6 the next digit necessarily a 1, is not transmitted and the next three digits are transmitted unchanged, any remainder being neglected. If the number of initial 0's is 7 or more the number 7 is transmitted corresponding to the first 7 0's and the remaining three digits are transmitted unchanged. At the receiver the process is reversed and to compensate for the error introduced by neglecting the final digits they are replaced by the digit 1 followed by the necessary number of 0's to make up the 10-digit number. Initially the signal is coded linearly, Fig. 1, the input signal being supplied via terminal S to a comparator CM where the signal current is balanced against the combined currents flowing through resistors R, 2R, 4R &c. and its polarity is determined. The connection of these resistors is controlled by toggles TG1, TG2, TG3 &c. which are controlled by timing waves T1, T2, T3 &c. applied in succession. Switches SP1, SP2 &c. and SN1, SN2 &c. connect up either a positive or negative current source +V or- V according to the value of the sign digit which controls the toggle TGS. The last timing pulse T16 resets all the toggles including TGS. During T1 the comparator CM detects whether the signal applied at S is positive or negative, and if positive a potential appears on lead L2 and if negative on lead L1. Energization of lead L1 causes the sign toggle TGS to be set via gate G1, but if L2 is energized the sign toggle remains in its reset position. The position of the sign toggle remains unaltered during the remainder of the coding cycle so that if the signal is positive only the switches SN1 &c. are effective and if negative only the switches SP1 &c. are effective. At the end of T1 toggle TG1 is set and assuming that the signal is negative, TG1 and TGS together operate switch SP1 via gate G7 and current flows through resistor R. The comparator now decides whether the current through R is greater or less than the amount required. If less, the lead L1 is energized but has no effect on the output lead TR since gates G3 and G4 are blocked. Hence toggle TG1 will not be reset via gates G5 and G6 by the next timing pulse T2 and current in resistor R is left flowing. If the current through resistor R is greater than the amount required L2 is energized and via gate G2, a pulse is applied to output line TR, and toggle TG1 is reset by timing pulse T2 to disconnect resistor R. Pulse T2 also sets toggle TG2 associated with resistor 2R and the process is repeated until all the toggles are set in accordance with the incoming signal. The input to the code translator, Fig. 2, may be obtained from the setting of the toggles or may be derived from the coded output pulses on the lead TR. In the translator a binary counter CN8 is reset to 000 and a shift register SR is reset to its initial position by the timing pulse T16. The timing pulse T1, i.e. the first pulse, applied via inverter I2 inhibits gates G20, G21, and prevents the sign information from reaching toggle TG11. Potentials following the sign digit indicating 0's are prevented by inverter I3 from opening gate G21 and operating toggle TG11, and under these conditions the potential derived from the inverter I4 allows the gate G22 to open and permit incoming 0's to operate the counter CN8 which stores its output for eventual read-out. If seven 0's are counted the gate G24 is opened and via inverter I4 the gate G22 is closed, thus blocking any further input to the counter CN8. The output of gate G24 also permits the shift register SR to be operated by timing pulses and the next three digits operate toggles TG12, TG13, TG14, via gates G26, G27, G28 respectively. If there are less than seven 0's the first 1 sets the toggle T11 via inverter I3 and the gate G22 is closed. Thus the shift register is made operative and the next three digits are set up on toggles TG12, TG13, TG14. Further transmission is controlled by timing pulses T7 to T12 controlling gates G29 to G34. At the receiver, Fig. 3, timing waves T7 to T12 are supplied to gates G40 to G45 and the incoming signals are supplied via the gates to set the toggles TG21 to TG26. The sign digit is stored in another toggle (not shown) which together with the outputs on terminals 1 to 10 controls ten pairs of switches providing currents of both polarities in a similar manner to the encoding arrangement. Toggles TG21, TG22, TG23 register the number of 0's, the output at E1 corresponding to no 0's and so on up to E8 which corresponds to seven 0's. With no 0's the first digit of the 10-digit code is 1 and digits 2, 3, 4 correspond to digits 4, 5, 6 of the 6-digit code. Digit 5 of the 10-digit code is a 1 and the remaining digits are 0's. Thus the output of E1 is supplied to terminal 1, the fourth digit, if a 1, via gate G43 sets toggle TG24 and the output of TG24 coincides with the output of E1 at gate G47 and is supplied via gate G51 to terminal 2. Similarly the fifth digit operates toggle TG25 if it is a 1 and the output from E1 in coincidence with the output from TG25 via gates G48 and G52 is supplied to terminal 3. The sixth digit, if a 1, operates TG26 and an output is supplied in a similar manner to terminal 4. The output from E1 is also supplied to gate G54 and so to terminal 5, this representing the digit introduced to compensate for the coding approximation. No potential is supplied to the remaining terminals which thus represent 0's. If there is an output at E8, representing seven 0's, the output from E8 coincides at gates G61, G62, G63 with the outputs from gates TG24, TG25, TG26 respectively to supply the appropriate potentials via gates G57, G58, G59 to lines 8, 9, 10. For other digital inputs the logic circuits operate in a similar manner. Alternative means for correcting for D.C. drift in the comparator CM during the synchronizing periods are described, Figs. 4 and 5 (not shown).