Patent GB-1173528-A (GB)
Title: Processor Intercommunication Control.
Inventor: THORNTON JAMES EDWARD
IPC: G06F13/24
Filed: 1967-06-16
Abstract: 1,173,528. Multiprocessor computer systems. CONTROL DATA CORP. 16 June, 1967 [20 July, 1966], No. 27970/67. Heading G4A. A computer system which includes a central memory and at least two central data processors operatively associated therewith, each processor having at least one central register associated therewith, comprises means associated with one of said central data processors for indicating at least two conditions of said one of said central data processors; means associated with another of said data processors for sensing said indicating means and for generating a first signal when said one processor is in one condition and for generating a second signal when said one processor is in another condition; and means associated with said processor for exchanging the contents of a portion of said central memory in response to said first signal. An arrangement is described (Fig. 1) comprising a central memory 10, two central data processors 12 and 14 and three peripheral data processors 16, 18 and 20, all the processors having access, if required, to the memory 10 and the processors 12 and 14 being allocated programme tasks according to a system of priorities by a monitor programme stored in memory 10 and performed when required on either of processors 12 or 14 as available. Each processor 12 and 14 includes a status flip-flop 28, 30 respectively which incidates by its set and reset conditions respectively that the corresponding processor is performing the monitor or another programme. The Specification describes instructions for switching the processors 12 and 14 between the monitor and other programmes according to the conditions of these flip-flops. Instruction 1.-For use in cases where one processor (say processor 12) is performing the monitor programme and monitor decides a high priority task is to be performed but said one processor 12 is already performing an equally high priority task. Then processor 12 senses (line 51) the state of flip-flop 30 and if set (processor 14 in monitor) merely proceeds with the next instruction, but if reset (processor 14 not in monitor) the processor 14 is transferred to monitor as follows. An interrupt signal is issued on line 60 whereby, at the end of the current instruction cycle, the contents of various control registers (not shown) associated with register 14 are exchanged with the contents of a portion of central memory 10 defined by the address in memory address register 48, said memory portion having been preloaded with the required control data for the transfer of control. The flip-flop 30 is set (line 54) to indicate that processor 14 is now in monitor. Buffer registers to facilitate the exchange are provided (not shown). The control registers which are exchanged include programme address register, instruction register, memory address registers, constants registers, index registers and the monitor address register 46 or 48. Instruction 2.-Enables control of the processor processing this instruction to be switched from monitor to another task and vice versa whatever the state of its status flip-flop 28 or 30. Thus, in the case of processor 12, on decoding such an instruction, the flip-flop 28 would be changed in state and the control registers associated with this processor exchanged with the contents of the portion of memory 10 at the address defined by memory address register 46. Instruction 3.-This is similar to instruction 1 but enables a peripheral processor to interrupt a central processor 12 or 14. Decoding circuitry is diagrammatically illustrated in Figs. 2-4 (not shown). Memory 10 preferably comprises ferrite cores and the peripheral processors may process input and output data relating for example to magnetic tape drives or card processors.