Patent GB-931270-A (GB)
Title: Improvements in or relating to automatic telecommunication exchanges
IPC: H04Q3/52
Filed: 1960-02-23
Abstract: 931,270. Automatic exchange systems. PHILIPS ELECTRICAL INDUSTRIES Ltd. Feb. 23, 1960 [Feb. 26, 1959], No. 6333/60. Class 40 (4). A subscriber's line is associated with two magnetic cores, each of said cores belonging to one of two matrices of such cores. The first core is arranged to be in the 0 or 1 state according as the subscriber is on- or off-hook. The second is arranged to be in the 0 or 1 state according to the state of connection of the line in the exchange, i.e. according as a connection is not or is made to the line. From the relative states of the cores the exchange control apparatus can determine whether the subscriber is quite free (0, 0), off-hook and requesting a connection (1, 0), engaged in a connection (1, 1) or has just been called but has not yet answered (0, 1). The results of such tests are used in the control of a switching network not described in detail. The circuits of the detailed embodiment employ so-called "cocking gates " symbolized as shown in Fig. 5. These are bi-stable circuits which are cocked into one state by an input on the lower lead, and subsequently triggered by an input to the left-hand lead whereupon they revert to their former state and emit a pulse on the right-hand lead in so doing. Preferably they are magnetic core circuits with a back-coupled transistor in the output circuit. Call incoming from subscriber.-Fig. 15 illustrates the subscriber's line test matrix. Each subscriber is designated by a triad of three digits j, k, l (j = 1 ... 3, k = 1 ... 5, l = 1 or 2). The cores are arranged as a three-dimensional matrix, the two layers corresponding to l = 1, 2 being shown side by side. Each core carries a subscriber's test wire 24 which is energized to set the core if the line is off-hook. Ring counters 31 ... 33 and 36 ... 40 are pulsed from a source 30 and in a cycle of 15 pulses test each core of each layer, a core being momentarily reset by coincidence of pulses in the appropriate horizontal and vertical leads. Each pulse duration is divided into five periods t 1  ... t 5  and as the counters are stepped during period t 1  read-out from both layers takes place at time t 1  on leads Z = 1, l = 2 the pulses being gated to the trigger inputs of cocking gates 44, 45. Assuming the former is cocked then if an output exists on l = 1 gate 44 is reset and emits a pulse on l<SP>1</SP> = 1 and cocks 46. If there is no output on l = 1 44 is triggered to cock 46 and produce an output on l<SP>1</SP> = 1 at time t 3 . At t 4 , 46 is triggered to cock 45 so that in the next pulse duration a similar test is applied to the output on l = 2. Thus all the cores are tested in 30 pulse periods and pulses are emitted on l<SP>1</SP> = 1 or l<SP>1</SP> = 2 at times t 1  or t 2  according as the subscriber is or is not off-hook. In the second matrix, Fig. 16, one gate from 54 ... 56 and one gate from 61 ... 65 is cocked at time t 1  from the j and k ring counters of Fig. 15. If an output exists on l<SP>1</SP> = 1 say, at time t 1 , this cocks 91 and when this is triggered at t 2  it opens gate 71 to enable all the vertical half-write windings of the layer corresponding to l = 1. The cocked gate from 61 ... 65 is triggered at time t 2  to put a half-write pulse on the appropriate horizontal. Likewise the cocked gate from 54 ... 56 is triggered at t 2  to permit the application of a half-write pulse to the appropriate verticals of both layers of the matrix and gate 71 selects the layer l = 1. Thus for the appropriate core two half-write pulses are applied, and if the core is in the 0 state, it is now set to the 1 state with a consequent output on winding 60. The windings 60 of all cores may feed a common circuit for control of subsequent switching, or may be connected together in groups according to the class of service of the subscriber's line. Provision may also be made for reading out the condition of the loop circuit of any selected subscriber and also for effecting alterations in the setting of any or all of the cores in the subscriber's memory, either in the process of setting up a call or in a checking process in which comparison is made against other registration in the system. To read out the state of any core in the loop test circuit, Fig. 17, it is first necessary to disable the sources 30, 43, 48, 49. A long pulse is then applied to terminal 27 at time t 3 . This sets all the cores in the triggered state. Leads j* = 1 ...3, k* = 1 ... 5, l* = 1 or 2 one lead in each group are then pulsed at time t 5  cock one particular gate in each of the groups 31 ... 33, 36 ... 40, 44 or 45. The pulse sources are then re-enabled. At the following t 1  instant this combination of gates is triggered to read out the relevant core (not shown) as in the case of Fig. 15. Gates 44 ... 47 operate as described previously, and a pulse exists on l<SP>1</SP> = 1 or l<SP>1</SP> = 2 at time t 1  if the relevant core is set. Coincident between such a pulse and the source pulse t 1  cocks 51, which is then triggered at t 4  to produce a pulse which triggers gate 50 previously cocked by the pulse on lead 27. Gate 50 thus produces an output at t 4  if in response to questioning from the control equipment the answer concerning a particular core is " set." If the core was not set then gate 50 produces an output at t 5 . Gate 93 is arranged to produce an output at t 2  to terminal 90 in response to the read out of any set core in any circumstance. After the determination has been made terminal 28 is pulsed to cock the gates indicating the subscriber j = 1, k = 1, l = 1 and normal scanning recommences. To adjust a particular core in a subscriber's memory, Fig. 18, the scanning is stopped as above and one lead out of each of the groups j** = 1 ... 3, k** = 1 ... 5, l** 1, 2 is energized to cock one gate in each of groups 54 ... 56, 61 ... 65, 91 or 92, so designating the core in question. At the same time lead 88 is not or is pulsed according as a 1 or a 0 is to be written into the core, the latter case causing switch 87 to change-over from the positive source 73<SP>1</SP> to the negative source 73<SP>11</SP>. At instant t 2  the cocked gates are triggered to open gates such as 57, 66 and a layer designating gate 71 to permit source 73<SP>1</SP> or 73<SP>11</SP> to supply half-write pulses to both the horizontal and vertical windings of the selected cores (not shown) so setting the core as required to 1 or 0. The terminal 90 also requires pulsing at this time to enable at gate 89 all the horizontal half-write circuits. The provision of this gate and lead enables a large memory having a single control circuit to serve a plurality of subscribers' loop test circuits. A further winging, not shown, threading all cores, may be provided forsimultaneouslyzeroizing all the cores. Specifications 835,534, 849,873, 925,706 and 925,707 are referred to.