baber/WOPTO huggingface dataset:
Patent TW-446563-B (TW)
Title: Low static conditioning shampoo
Inventor: PATEL AMRIT M
IPC: C11D3/20
Filed: 1996-02-28
Granted: 2001-07-21
Abstract: The present invention provides an effective conditioning shampoo composition which is free of conditioning amounts of silicone conditioning agents. It comprises: (A) about 5% to about 40% of a detersive surfactant mixture of an anionic detergent and an amphoteric surfactant, the weight ratio of the anionic detergent to the amphoteric surfactant being in the range of about 10:1 to 0.8:1; (B) about 0.05% to about 6% of a conditioning agent selected from the group consisting of 0.05% to 5% of a complex of essentially equimolar amounts of a C8-C18 (EtO)1-10 carboxylic acid, and a C8-C18 alkyl (EtO)0-10 dimethyl amine; 0.05% to 1.0% of a polyquaternary compound selected from the group consisting of a quaternized cellulosic polymer and a mixture of the quaternized cellulosic polymer with a non-cellulosic quaternary conditioning polymer; and mixtures of the foregoing; (C) 0.1% to 1% of a static control mixture of a quaternary ammonium salt having the formula R9, R10, R11, R12 N<SP>+</SP>X<SP>-</SP> wherein R9 is a C14-C18 alkyl, R10 and R11 are each a C1-C4 alkyl, R12 is C1-C4 alkyl or benzyl and X<SP>-</SP> is a salt forming cation selected from the group consisting of chloride, bromide, methosulfate and ethosulfate; and a di-quaternary ammonium salt having the formula (R13)2R14R15N<SP>+</SP>X<SP>-</SP> wherein R13 is a C14-C18 alkyl or alkylene group and R14 and R15 are each a C1-C4 alkyl group or a (CH2CH2O)nH group with at least one of R14 and R15 being a (CH2CH2O)nH group, n is an integer from 2 to 20 and X is a cation as set forth above, the weight ratio of the monoalkyl quaternary salt to dialkyl quaternary salt being from about 1:4 to 4:1; and (D) an aqueous medium. These compositions exhibit enhanced antistatic properties as compared to the same compositions containing either the monoalkyl quaternary salt or the dialkyl quaternary salt as the sole antistatic ingredient.
Patent TW-307899-B (TW)
Title: Semiconductor apparatus and manufacturing method thereof
Inventor: EIMORI TAKANAO
IPC: H01L27/108
Filed: 1996-05-01
Granted: 1997-06-11
Abstract: A semiconductor apparatus comprises of: (1) semiconductor substrate; (2) insulating coating overlaid on main surface of the semiconductor substrate; (3) conductive portion with contact allocated beside the above semiconductor substrate main surface on the insulating coating; (4) SiN coating allocated on the above insulating coating, used to overlay the above semiconductor substrate main surface and the above conductive portion; (5) conductive path, arriving contact part of the above conductive portion after penetrating the above insulating coating and the above SiN coating.
Patent TW-458958-B (TW)
Title: Compound with growth hormone releasing properties
Inventor: JOHANSEN NILS LANGELAND
IPC: C07K5/083
Filed: 1996-06-28
Granted: 2001-10-11
Abstract: Compounds of the formula A-B-C-D(E)<p> are used to stimulate the release of growth hormone from the pituitary. A compound of general formula I A-B-C-D-(-E)p, wherein p is 0 or 1; A is hydrogen or R1-(CH2)q-(X)r-(CH2)s-CO-, wherein q is 0 or 1; r is 0 or 1; s is 0; R1 is piperidino or N(R2)-R3, wherein each of R2 and R3 is independently hydrogen or lower alkyl; and X, when r is 1, is -C(R16)(R17)-, wherein each of R16 and R17 is independently lower alkyl; B is (G)t-(H)u wherein each of t and u independently is 0 or 1; G and H are amino acid residues selected from the group consisting of natural L-amino acids or their corresponding D-isomers such as His or Ala, or non-natural amino acids such as amino-isobutyric acid, 3-aminomethylbenzoic acid, nipecotic acid or iso-nipecotic acid; C is a D-amino acid of formula -NH-CH((CH2)W-R4)-CO- wherein W is 1, and R4 is selected from the group consisting of D, when p is 1, is a D-amino acid of formula -NR20-CH((CH2)k-R5)-CO- or, when p is 0, D is -NR20-CH((CH2)k-R5)-CH2-R6 or -NR20-CH((CH2)m-R5)-COR6, wherein k is 1; I is 1; m is 1; R20 is selected from the group consisting of lower alkyl; R5 is selected from the group consisting of each of which is optionally substituted with halogen, and R6 is -OH or -N(R7)-R8, wherein each of R7 and R8 is independently hydrogen or lower alkyl; E, when p is 1, is -NH-CH(R10)-(CH2)v-R9, wherein v is 0 or an integer selected from the group; 1, 2, 3, 4; R9 is hydrogen, morpholino, -N(R11)-R12, wherein n is 0, and R19 is hydrogen or lower alkyl, each of R11 and R12 is independently hydrogen or lower alkyl, and R10, when p is 1, is selected from the group consisting of H or -CO-R13, wherein R13 is -N(R14)-R15, wherein each of R14 and R15 is hydrogen; all amide bonds within formula I with the exception of the bond between C and D may independently be replaced by -Y-NR18-, wherein Y is -CO-, and R18 is hydrogen, lower alkyl; or a pharmaceutically acceptable salt thereof; and with the exception of the compounds, (3-aminomethylbenzoyl)-D-2Nal-N-Me-D-Phe-Lys-NH2, H-Aib-His-D-2Nal-N-Me-D-Phe-Lys-NH2, H-Aib-His-N-Me-D-2Nal-N-Me-D-Phe-Lys-NH2, 3-(H-Aib-His-D-2Nal-N-Me-D-Phe-NH)-1-morpholinopropane, 2-(H-Aib-His-D-2Nal-N-Me-D-Phe-NH)-(1-methyl-2-pyrrolidinyl)ethane, ((3R)-piperidinecarbonyl)-N-Me-D-2Nal-N-Me-D-Phe-Lys-NH2, 3-((3-aminomethylbenzoyl)-D-2Nal-N-Me-D-Phe-NH)1-morpholinopropane, 2-(H-Aib-His-N-Me-D-2Nal-N-Me-D-Phe-NH)-(1-methyl-2-pyrrolidinyl)ethane, 2-(((3R)-piperidinecarbonyl)-N-Me-D-2Nal-N-Me-D-Phe-NH)-(1-methyl-2-pyrrolidinyl)ethane, 2-((3-aminomethylbenzoyl)-N-Me-D-2Nal-N-Me-D-Phe-NH)-(1-methyl-2-pyrrolidinyl)ethane, 3-(H-Aib-His-N-Me-D-2Nal-N-Me-D-Phe-NH)-1-morpholinopropane, 3-(((3R)-piperidinecarbonyl)-N-Me-D-2Nal-N-Me-D-Phe-NH)-1-morpholinopropane, 3-((3-aminomethylbenzoyl)-N-Me-D-2Nal-N-Me-D-Phe-NH)-1-morpholinopropane, 2-((3-aminomethylbenzoyl)-D-2Nal-N-Me-D-Phe-NH)-(1-methyl-2-pyrrolidinyl)ethane, 2-(((3R)piperidinecarbonyl)-D-2Nal-N-Me-D-Phe-NH)-(1-methyl-2-pyrrolidinyl)ethane.
Patent TW-304289-B (TW)
Title: Manufacturing method of semiconductor memory device with capacitor
Inventor: JAW FANG-CHINQ
IPC: H01L21/70
Filed: 1996-08-16
Granted: 1997-05-01
Abstract: A manufacturing method of semiconductor memory device with capacitor, in which the semiconductor includes one substrate, one transfer transistor formed on the substrate, and one storage electrode electrically coupled to one of drain and source of the transfer transistor, comprises of: (1) on the substrata forming one first insulator, overlaying the transfer transistor; (2) forming one first conductive layer, passing at least the first insulator, electrically coupled with one of the drain and source of the transfer transistor; (3) on the first conductive layer forming one insulating pillar with one concave opening; (4) forming one second conductive layer overlaying only partial region of the concave bottom; (5) patterning the first, second conductive layer, forming one opening;(6) on the opening sidewall forming one third conductive layer, in which the first, third conductive layer constitute one tree-type conductive layer, and the second conductive layer constitutes one tree-type conducting layer, and the first, second, third conductive layer constitute one storage electrode of the storage capacitor; (7) removing the insulating pillar; (8) on exposed surface of the first, second and third conductive layer, forming one dielectric; and (9) on the dielectric surface forming one fourth conductive layer to constitute one opposed electrode of the storage capacitor.
Patent TW-494441-B (TW)
Title: Emitter material for cathode ray tube and a method for manufacturing the same
Inventor: OZAWA TETSURO
IPC: H01J9/42
Filed: 1996-09-14
Granted: 2002-07-11
Abstract: An emitter material for a CRT comprises a mixed crystal or a solid solution of at least two kinds of alkaline earth metal carbonate, in which at least one alkaline earth metal carbonate is dispersed or separated in the mixed crystal or solid solution. The alkaline earth metal carbonate, which is a material for an emitter 4 for the CRT, is coated onto the base metal 3 and thermally decomposed in a vacuum to from an emitter of an alkaline earth metal. This emitter, which is proper for a larger screen size, high brightness and high resolution CRT, can be provided with enough life characteristics even under the operating condition of the emission current density of 2A/cm<SP>2</SP>.
Patent TW-354376-B (TW)
Title: An optic cable laying method and self supporting type optic cable
Inventor: ISHIKAWA HIROKI
IPC: G02B6/44
Filed: 1996-10-24
Granted: 1999-03-11
Abstract: A self-supporting type optical cable comprising a supporting wire portion, a long body portion 2, and an outer jacket 3 common to the two portions, wherein the supporting wire portion 1 and the long body portion 2 are integrated with each other through a neck portion of the outer jacket 3. The outer jacket 5 of the long body portion 2 forms a nearly cylindrical section so that optical outside wires 4 are loosely accommodated in the inner space 2a of the long body portion 2. In a downstream portion with respect to a drawing-down point, the outer jacket 3 is cut and opened so that an optic outside wire is selected and cut. At the drawing-down point, the outer jacket 3 is cut partially and the cut side of the optical outside wire 14 is selected to be drawn out. The optic outside wire 14 thus drawn out is laid to a subscriber^s house directly and connected to an interior cable. The partially cut portion of the shall 3 is blocked to be repaired so that rainwater or foreign matter does not invade.
Patent TW-315464-B (TW)
Title: Polysilicon fuse with peripheral isolated by at least two metal layers
Inventor: UEN GWO-LIANG
IPC: G11C11/40
Filed: 1997-01-03
Granted: 1997-09-11
Abstract: A polysilicon fuse, formed on one substrate, comprises of: (1) one field oxide located on the substrate; (2) one polysilicon segment located on the field oxide; (3) one dielectric located on the polysilicon segment; (4) one localized SOG layer located on the dielectric; (5) the localized SOG layer contains one top surface, one bottom surface and one ambient surface, in which the bottom surface contacts with the dielectric, and the localized SOG layer is separated by at least one first metal and one second metal layer surrounding around, in which the first metal layer contacts with the dielectric.
Patent TW-339476-B (TW)
Title: Semiconductor component having a devided floating gate
Inventor: RONALE KAKOSCHKE
IPC: H01L27/115
Filed: 1997-04-07
Granted: 1998-09-01
Abstract: A sort of semiconductor having the following: - first conductor-type first (14, embedded channel) and the second mixture area (12), where the first conductor-type is provided in the base (11) of the second conductor-type semiconductor, - a path area (15) located in the base of the semiconductor between the 2 mixture areas (12, 14), - a tunnel dielectric medium (18), which is partially covering the surface of the first mixture area, - a port gate dielectric (17) covering the surface of the path area (15) and the edge (14^) of the first mixture area (14), - a tunnel port electrode (19) on the tunnel dielectric, - a path port electrode (20) on the tunnel dielectric, where the tunel port gate electrode (19) and the path port gate electrode (20) having at least the surface facing the tunnel dielectric and the port gate dielectric being divided by an insulation structure (22).
Patent TW-402630-B (TW)
Title: Transparent electroconductive film, low reflection transparent electroconductive film and display device
Inventor: TAKAMIYA NAOKI
IPC: H01J29/86
Filed: 1997-06-06
Granted: 2000-08-21
Abstract: A transparent electroconductive film according to the present invention has a transparent electroconductive layer containing a total of at least 10% by weight of at least two types of metals. Consequently, the transparent electroconductive film has high transparency, tonability and electroconductivity, provides exceptional charge prevention and electromagnetic shielding effects, allows adjustment of the tone of transmitted images and is highly durable with regard to saline resistance, acid resistance, oxidation resistance and ultraviolet resistance. A low reflection transparent electroconductive film according to the present invention is additionally provided with at least one transparent thin film 2 having a refractive index  different from the refractive index of the transparent electroconductive layer 1 above and/or below the transparent electroconductive layer. This transparent electroconductive film is capable of being produced economically, and has exceptional reflection prevention effects in addition to the above-mentioned properties. A display device according to the present invention has the low reflection transparent electroconductive film formed on the display screen thereof. This display device has high transparency, tonability and electroconductivity, provides exceptional reflection prevention effects as well as charge prevention and electromagnetic shielding effects, allows adjustment of the tone of transmitted images and is highly durable with regard to saline resistance, acid resistance, oxidation resistance and ultraviolet resistance.
Patent TW-341688-B (TW)
Title: Prioritization of background display during animation
Inventor: SCOTT A MORGAN
IPC: G09G5/36
Filed: 1997-06-11
Granted: 1998-10-01
Abstract: A multiplex operation type data processing system, the data processing system displaying an animated image generated by a first procedure and overlapped on at least another image generated by a second procedure, the data processing system comprising: means for determining whether the animated image will cause a region of the another image which is previously hidden becoming visible; and means for designating a first priority to the first procedure, and the first priority being relatively lower than a second priority designated to the second procedure; in which the data processing system executes the second procedure in a priority relatively higher than that of the first procedure so that the another image can be displayed when the animated image exposes the another image.
Patent TW-348312-B (TW)
Title: Process for producing semiconductor integrated circuit device
Inventor: HASHIMOTO NAOTAKA
IPC: H01L27/10
Filed: 1997-07-19
Granted: 1998-12-21
Abstract: A process for producing a semiconductor integrated circuit device, which is characterized in comprising the following steps: (a) forming a first MISFET in a first region and a second MISFET in a second region of the main face of a semiconductor substrate; (b) forming a connection hole on the upper part of either of the source or drain of the first MISFET; (c) stacking a first conductive film on the upper part of the connection hole in the first region which has a film thickness larger than the step difference between the upper part of the gate of the first MISFET and its gate oxide film; and stacking a first conductive film on the upper part of the source/drain of the second MISFET which has a film thickness larger than the step difference between the upper part of the gate of the second MISFET and its gate oxide film; (d) generally equalizing the step difference of the first region and the step difference of the second region by processing the first conductive film; (e) stacking a second conductive film on the upper part of the first conductive film; (f) using the photoresist film of the upper part of the second conductive film as a mask and patterning the second conductive film of the first region into a desired shape, while removing the second conductive film of the second region.
Patent TW-357490-B (TW)
Title: Radio receiver
Inventor: HEGELER WILHELM
IPC: H04H40/45
Filed: 1997-09-01
Granted: 1999-05-01
Abstract: A sort of radio receiver, in particular, for automobiles, having a memory for saving the emission frequency and the code representing the program being transmitted on the emission frequency, having the code a partial code, a country code (42), a program code (46) and an area code (44), being the country code used for the country that emits the program, the area code (44) for the space of the program being transmitted at the emission frequency, being the code representing the emission frequency saved in the memory, with an identification device (8) for identification of the code, inclluding: sending based on a control signal the emission frequency of a program, of which the code in the memory following the code of the program being physically selected; in the first operation status, selection of only specific emission effects, being relevant codes interm of partial code (42)(46) different from the physically adjusted emitter and in the second operation status, selection of relevant codes interm of partial code (42)(46) and/or area code (44) different physically from the selected emission frequency.
Patent TW-350177-B (TW)
Title: Hybrid ATM adaptation layer
Inventor: WESTBERG LARS
IPC: H04Q11/04
Filed: 1997-08-21
Granted: 1999-01-11
Abstract: A sort of hybrid ATM adaptation layer, including the following steps: receiving from at least one communication application the hybrid data, which includes a number of data transfer formats; insertion of the data having the first data transfer format into at least one data package; insertion of data having the second data transfer format into at least one data package; multiplying the data package to a single data flow; and transfering of the data package through a common communication frequency to the receiving station, where the data package including a common data transfer protocol.
Patent TW-353047-B (TW)
Title: Improved injection molding apparatus, injection nozzle valve gating apparatus, combination of an injection molding equipment, and method of injection molding articles in a mold
Inventor: DISIMONE JOHN
IPC: B29C45/26
Filed: 1997-11-04
Granted: 1999-02-21
Abstract: An improved injection molding apparatus for forming articles including an aperture therethrough, the apparatus including a first mold half having a first bore; a second mold half having a second bore substantially aligned with the first bore, in which the first mold half and the second mold half form a mold cavity space in the mold closed position, the mold cavity space having a thickness T1 adjacent the first bore, the improvement comprising a slidable mold injection nozzle located inside the first bore having a molding position and a post molding position, the nozzle including an inlet in fluid communication with a molten material supply means; an outlet including a nozzle tip, the nozzle tip having a gating portion and being in communication with the mold cavity space when the nozzle is in the molding position; and an unobstructed nozzle melt channel between the inlet and the outlet to guide the flowing molten material from the supply means towards the mold cavity space in tubular flow up to the outlet; independently movable sliding valve gating means located in the second bore and having a molding position therein and a post molding sealing position in the first bore, the valve gating means including mold core means to form a hole in the article to be molded, means for converting the flow of molten material from tubular to radial in the mold closed position, and nozzle channel sealing means to prevent leakage of molten material in the mold opened position; a circular mold gate of an adaptable thickness T2, the mold gate being formed in the mold closed position between the gating portion of the nozzle tip and the valve gating means, the mold gate having no mechanical obstructions, whereby the maximum thickness T2 of the gate is substantially equal to the thickness T1 of the mold cavity space; first motive means to slide the mold injection nozzle inside the first bore between the molding and the post molding positions; and second motive means to slide the valve gating means at least partially from the molding position inside the second bore to the post molding sealing position inside the first bore.
Patent TW-358234-B (TW)
Title: Semiconductor device package having twice bent tie bar and a small die pad
Inventor: JEUNG DO-SU
IPC: H01L23/50
Filed: 1997-11-11
Granted: 1999-05-11
Abstract: A semiconductor device package composed of a die pad to which a semiconductor chip is attached, a plurality of inner leads which are electrically connected to the semiconductor chip, tie bars for supporting the die pad, a package body for the encapsulating the semiconductor chip, the die pad, and the inner leads, and a plurality of outer leads which are integral with the inner leads and exposed from the package body, wherein the die pad has a smaller size than that of the semiconductor chip and the tie bar is twice bet, that is, having a downward and an upward bent part.
Patent TW-360771-B (TW)
Title: Vacuum rotary dryer
Inventor: MATSUMOTO TAKASHI
IPC: F26B11/04
Filed: 1997-12-05
Granted: 1999-06-11
Abstract: To provide a vacuum rotary drier capable of charging the solid into a rotary drum and transferring the solid from the rotary drum without touching the solid by hand. A gas passing pipe 46 and a solid charging/discharging pipe 56 are fitted to a rotary drum 23. The solid charging/discharging pipe 56 is connected to a solid feed source, and the solid to be dried is fed into the rotary drum 23 by evacuating the rotary drum through the gas passing pipe 46 through an evacuation device 53. After the solid is dried in the drum, the solid charging/discharging pipe 56 is connected to a solid sucking and carrying device, and the gas passing pipe 46 is opened to the atmosphere. A turning part 56b provided on the solid charging/discharging pipe 56 is turned so as to be advanced into the solid with the rotary drum in an inclined condition, and the solid is sucked from the tip of the turning part, and carried out. In the final condition, the tip of the turning part 56b is arranged opposite to a lowest part of the rotary drum to carry out most of the solid in the rotary drum.
Patent TW-358065-B (TW)
Title: Method of making high purity copper sputtering targets
Inventor: KARDOKUS JANINE K
IPC: C21D1/74
Filed: 1997-12-24
Granted: 1999-05-11
Abstract: A method of making high purity copper sputtering targets, including: provision of a plurality of pure copper pieces, having each a bonding face; cleaning the bonding face; stacking the pieces by binding the adjacent pieces; fixing the stacked piece at a fixed position to form an assembly; heating in the inert environment and forging the assembly, for reduction of thickness of the stacking; and annealing the forged assembly for generation of a diffusion bonded unitary structure.
Patent TW-368775-B (TW)
Title: Low cost high efficiency power converter
Inventor: POON FRANKI N K
IPC: H02M5/22
Filed: 1998-02-03
Granted: 1999-09-01
Abstract: A switch mode power converter achieving high efficiency through zero voltage switching (ZVS) by using an auxiliary switch, a capacitor, an auxiliary winding and an inductor. The technique can be applied to a boost, buck-boost, buck, isolated forward or isolated flyback converter. The auxiliary switch is turned on before the main power switch turns on, and the capacitor provides voltage to energize the inductor and force current to flow into the auxiliary winding. The current is transformed by the main winding and discharges the capacitance across main power switch to zero volts before the main switch turns on. Hence ZVS is obtained and can greatly reduce the switching loss of the main power switch.