Patent GB-793446-A (GB)
Title: Punched-card relay calculating perforating machine
IPC: G06F7/44
Filed: 1954-11-12
Abstract: 793,446. Digital electric calculating-apparatus. ARITMA NARODNI PODNIK, and SVOBODA, A. Nov. 12, 1954 [Nov. 16, 1953], No. 32831/54. Class 106 (1). A punched-card calculating machine comprises the combination of a mechanical part for feeding and sensing the punched cards and punching data therein, and an electric part including electromagnetic relay calculating-circuits operating according to the code 8, 4, - 2, - 1, and a relay control device which, during multiplication, expresses the multiplier digits in the code 4 1 with a carry for the digits 5 to 9. General. The multiplying and dividing machine described receives factors x, y from a punched card 1, Fig. 1, and punches the calculation result on the card by mechanism 18. Only the electromagnetic relay calculating circuits are described in detail, these circuits being controlled by timing pulses, Fig. 8, generated in synchronism with the rotation of the main shaft of the machine; relay-energizing timing pulses marked by a circle in Fig. 1, e.g. S, are associated with holding pulses marked by a square, e.g. s, the relay contacts only being sensed or pulsed during the holding period. Each machine cycle is divided into twelve periods corresponding to the positions of telephone-type selectors 6, 7 which supply the digits stored in memory 4, or "fixed commands " stored in 5, to a controlling decoder 10 (Fig. 2, not shown), comprising a pair of relay networks, alternately operative (i.e. the relays of one network are being selectively energized while pulses are applied to contacts of the other), under control of switching pulse L, to direct pulses F, G to memories 2, 3, 11, 12 for passing the values stored therein in positive or negative (complementary) form, to the right-hand input of an adding circuit 8 which together with a memory 9 forms an accumulator as described in Specification 787,185. The memories 2, 3 translate values received from a card into the accumulator code 8, 4, - 2, - 1, and memories 11, 12 are used to store four times and two times the amount in 3. The value stored in 9 is applied to the left-hand input of circuit 8, entry into 8 being controlled by pulses A and the subsequent addition by pulses S. The value in 9 may be shifted one digit by energizing relay F by a pulse from 10, and may be read out by energizing relay H. During multiplication, the product is built up in 9 and passed via 17, where it is translated back into the card code, to the punching mechanism 18. Division is controlled by a relay chain 13, the quotient digits being built up by decoders 14, 15 whose outputs are passed to 17 by selector 16 (operating at half the speed of 6, 7). In Fig. 1, the dashed, dotted and full line connections correpond to multiplication only, division only and both operations respectively. Multiplication. The multiplicand x and multiplier y are passed to memories 3, 4 respectively and the multiplication is performed during a single cycle of selector 6. During the first three selector steps, the " commands " from 5 causes decoder 10 to control the accumulator to compute 4x which is passed to memory 11. During the next seven steps (4-10), the decoder 10 is controlled by the multiplier digits in 4 in turn, beginning with the least significant, to direct the pulses F and G to memories 3, 11 to enter Œ x and Œ4x selectively (see Fig. 3) into the accumulator, pulses F causing a right shift after each multiplier digit has been dealt with. For a multiplier digit greater than " 4," decoder 10 adds " 1 " in the next higher denomination (see the right-hand two columns in Fig. 3). During the eleventh selector step, pulse F causes a final transfer of x to the accumulator if such a " 1 " is registered in 10, and pulse G causes a " round-off " value of " 5 " to be entered in the appropriate digit position. The following pulse F, during the twelfth step, energizes relay H, so that the product is read out under control of the following pulse A, held in 17 by pulse K, and punched under control of Mg (see Fig. 8). Division. The dividend x and divisor y are passed to memories 2, 3 respectively, and the division is performed in two machine cycles under control of selectors 6, 7 respectively which are switched by relay Z (see lower half of Fig. 8). During the first four selector steps, decoder 10 is controlled by 5 via selector 6 to compute 2y and 4y and pass them to memories 12, 11 respectively, and x is entered in the accumulator. During the following eighteen steps (5-22), nine cycles of division are performed under control of relay chain 13 which is started by pulse D (see Fig. 8) and stepped on by each succeeding pulse A and S as long as holding pulse v operates. During each division cycle, the chain directs a pulse to memories 11, 12 and 3 to cause Œ4y, Œ2y, Œ2y and Œy successively to be entered in the accumulator. The pulse is obtained from " carry " line 64 or " no carry " line 63 of the accumulator, one or the other of which receives a pulse S according to whether the previous entry produced an endaround carry or not, the chain causing the next entry to be negative or positive respectively. The first entry (4y) during the first division cycle is negative, controlled by pulse D, and the sign of the first entries during each subsequent cycles is determined by the effect of the last entry (y) of the preceding cycle; left shift of the remainder in the accumulator between cycles is controlled by pulses F which are produced only during every other period for division. The signs of the entries are registered on relays of alternately operating sign decoders 14, 15 selected for read out by switching relay Y; each quotient digit is read out to coder 17 in the code 8, 4, - 2, - 1 by a pulse G, obtained from 10 every other period, and is held by pulse d1 or d2 and punched under control of Mg1 or Mg2. The last (9th) quotient digit is read out during the 23rd step, and during the final (24th) step, the remainder is read out from the accumulator to memory 11 but not held.