Patent GB-1262502-A (GB)
Title: Improvements in or relating to semiconductor devices and methods of making them
Inventor: GLINSKI VINCENT JOHN
IPC: H01L27/07
Filed: 1969-01-29
Abstract: 1,262,502. Semi-conductor devices. WESTERN ELECTRIC CO. Inc. 29 Jan., 1969 [5 Feb., 1968; 23 Dec., 1968], No. 45599/71. Divided out of 1,262,501. Heading H1K. A semi-conductor circuit element such as the bipolar transistor shown is isolated laterally from the remainder of the wafer, which may contain other transistors-or-circuit elements such as diodes, resistors or capacitors, by a field-effecttype pinching off of a normally conductive channel in a.layer 242 due to reverse biasing of two PN-junctions parallel to the wafer surface and on either side of the layer 242. The unshaded portions of Fig. 23 represent the depletion regions associated with the various junctions under reverse bias. The structure is formed by epitaxial deposition of an N-type layer 242 on a P-type Si substrate and subsequent formation by epitaxy, duffusion or ion implantation of a P-type layer on the layer 242. Localized N+ type regions 246, 247, the latter surrounding the former, are formed by selective diffusion or ion implantation, :a passivating layer, e.g. of silicon oxide or nitride, aluminium oxide, zirconium oxide or comprising multiple layers, is formed and electrodes are provided as shown. The N-type layer 242 is of relatively high resistivity, so when the parallel junctions are reverse biased the depletion regions extend mainly into the layer 242 and pinch it off in a zone surrounding the collector region of the transistor. In other embodiments the pinch-off effect occurs in an N-type channel between the P-type substrate and a P-type region (144), Fig. 14 (not shown), diffused or ion implanted into an N-type epitaxial layer (142). The P-type region (144) in this case surrounds a portion of the layer (142) which constitutes the collector region of the transistor, the base, emitter and collector contact regions being provided by selective diffusion or ion implantation within the surrounded portion. A silicon oxide mask may be used to define the diffused regions, a mask of gold or platinum being used if ion implantation is employed. Embodiments are described in which an N-type epitaxial layer (47), Fig. 10 (not shown), is formed on a P-type substrate (40) and an annular N+ type zone (48) is selectively diffused or implanted therein to form a collector contact region extending down towards or into a buried N+ type zone which lies between the P-type substrate and the N-type epitaxial layer (47). A P-type dopant is then diffused or implanted non-selectively into the entire surface of the epitaxial layer so that the surface of the N + collector contact zone (48) is not converted to P-type conductivity due to its high N-type impurity content, but the remainder of a surface layer of the N-type layer (47) is converted. A P-type base region is thus formed inside the annular N+ type region (48), and a surrounding P-type surface layer (50) is also thus provided. An N+ emitter region is diffused or implanted into the base region. Field-effect isolation of the transistor is then provided by reverse biasing of the two back-toback junctions between the substrate (40) and the epitaxial layer (47) and between the layer (47) and the P-type surface layer (50) so that the remaining N-type channel through the layer (47) is pinched off. Boron, phosphorus, arsenic and antimony are referred to as suitable dopants for the various regions. Contact thereto may be made by means of a beam-lead technique.