Patent GB-906678-A (GB)
Title: Precision infinite memory integrator
IPC: G11C27/02
Filed: 1961-02-27
Abstract: 906,678. Electric analogue calculating systems. BENDIX CORPORATION. Feb. 27, 1961 [March 1, 1960], No. 7110/61. Class 37. In an electrical analogue integrator system which includes a transfluxor and means for connecting the output winding of the transfluxor to the control winding in a feedback loop, the loop includes summing and switching means operated by a timing arrangement. The integrand signal (e.g. an amplitude modulated A.C. signal) E 1  is applied via a transformer 10, with centre-tapped secondary, to a switch 11, which is controlled by signals on the lines 43, 44 to pass signals E 1 a (corresponding to -E 1 ) and E 1 b (corresponding to +E 1 ) during alternate periods of time. The output from the switch passes to an amplifier 12, where it is combined with the output from a differential amplifier 35. This amplifier 35 receives at its inputs the integrated outputs E a  and E b , from the respective circuit branches A and B, and hence produces an output E a -E b . The output from 12 passes through a demodulator 13 and a lag network 14 and is then applied to the gates 15A and 15B, which are arranged to open alternately at times related to those of operation of the switch 11. The D.C. error signal E 4  passed through either gate 15a or 15b will be related to (-E1 + E a  - Eb) or (+ E 1  + E a  - E b ) respectively and is converted by means of a gating circuit 17 into pulse trains E 5 a or E 5 b corresponding in polarity and amplitude to the phase and amplitude of the error signal. The gating circuit operates by applying pulses from a source (not shown) across opposite apices of a diode bridge, which are normally held at potentials which prevent the error signal from passing, in such a way as to permit the signal to pass. The pulse train passes by way of a transistor amplifier 19 to the control winding 23 of the transfluxor 21A or 21B where it controls the coupling between the output winding 27 and the supply winding 25, and hence the size of the output on 27. The distorted output is rectified and remodulated to constitute the output signals E a  and Eb. Thus during one alternate set of active periods feedback system A operates to make: Since Eb is the output value stored in transfluxor 21B of the other branch from the preceding active period, E a - E b  represents increment #E a  in the output signal, i.e. #E a  = E 1  or approximately E a  = # # E 1  dt, where f is the frequency of the active periods. A better approximation to the desired integral is obtained by combining both outputs E a  and Eb by means of an electronic switch 34 to give a final output E 2 . To eliminate spurious effects caused by transients occurring at the switch over from circuit A to circuit B, guard periods of length To are intercalated between successive active periods. The timing pulses for the system are produced from a pulse source, not shown, as a train P 1  and, by means of a delay line 36 (length To), an or-gate 37, flip flops 38, 39 and and-gates 41, 42, are made to produce all the necessary timing waveforms (see Fig. 2). At the start of an integrating operation both transfluxors have their cores blocked in opposite states by means of a pulse on the reset windings 48. The transfluxors may be set at intermediate magnetisation states to enable the system to accept input signals of any phase and polarity (Fig. 3, not shown). Specifications 858,208, 858,209 and 906,299 are referred to.