Patent GB-906192-A (GB)
Title: Improvements relating to automatic telecommunication switching systems
Inventor: WARMAN BLOOMFIELD JAMES
IPC: H04Q3/00
Filed: 1959-01-05
Abstract: 906,192. Automatic exchange systems. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. Dec. 31, 1959 [Jan. 5, 1959], No. 403/59. Class 40 (4). Incoming lines are each provided with a bi-stable device, such as a magnetic core having a rectangular hysteresis loop, which is set by incoming digital impulses, the cores being secured and reset by a device which at the same time steps a counter for registering the digit. As described 200 junction lines are served by 50 registers. Incoming digital pulses on a junction J set the core C over winding WS and when the junction scanner JS reaches the junction it resets the core to produce output pulses from windings WO1, WO2. The latter sets the bi-stable device SS which stops junction scanner JS and starts a register scanner RS. Meanwhile the output pulse from winding WO1 lengthened at PL is applied via gate GX to enable output gates G1 . . . Gn to pass the coded identity of the junction (in the form of markings on combinations of 2 out of n leads) to the input gates. IG1 ... n of all registers. The register scanner enables all such sets of gates in turn provided they are not disabled by a busy marking from gate GB. Thus the first free register accepts the junction identity and registers it in the store IS whose outputs mark the register busy at GB and also cause corresponding combinations of gates OG1 ... n to produce outputs. All of the gates CG1 . . . n (which are comparison gates arranged to give an output provided they receive identical inputs) of the junction concerned thus produce an output (being enabled by the output from PL) so that the n-gate GO also produces an output. This is gated at HG to the digit store DS. The output from GO also resets bi-stable circuit SS to stop the register scanner and restart the junction scanner. Shortly afterwards a delayed output from DL1 sets bi-stable circuit X to close GX so that subsequent digital pulses cannot seize another register. On each subsequent digital pulse, however, operations take place otherwise as before and gates CG1 ... CGn are enabled by PL so that when the register scanner RS reaches the register having that junction's identity stored in IS, the gates OG1 ... OGn emit pulses which pass through CG1 ... n to the n-gate GO and thence via HG to the digit store DS. The monostable circuit B set to its unstable state on the first impulse is held in this position during impulsing and is sufficiently slow in releasing that it does not do so until all the digits have been received. It then resets X. In a modification, Fig. 2 (not shown), a free register is preselected and the junction scanner runs continuously. On the first impulse, the resetting of the core by the scanner opens gates to emit the junction identity which is registered on a store in the preselected register. The stored identity is compared in the register with that emitted by the junction circuit on this occasion and on the receipt of future impulses to operate an n-gate (this time located in the register) which pulses the digit store. The bistable circuit C may be arranged to emit a pulse both at the beginning and end of each impulse. The digit store is then fed via bi-stable circuit operating as a ¸ 2 circuit. The core may be arranged to give an output pulse both at the make and the break of the loop. The input to the digit store would then be preceded by a flip-flop acting as a divide-bytwo circuit. The odd or even states of the flipflop if persisting for more than prescribed periods may then be used to determine inter-train pauses for digit distribution purposes; or for clear down or switch-through detection, signifying that the register may be cleared. Specification 868,629 is referred to.