Patent WO-2022018634-A1 (WO)
Title: Capacitive feedthrough for hybrid hermetic modules for space applications
Inventor: RANIERI PAOLO
IPC: H03H1/00
Filed: 2021-07-20
Abstract: The present invention concerns a capacitive feedthrough (1) hermetically sealable to a hybrid module for space applications, comprising a multilayer ceramic structure that has: two opposite external faces including a top face (10) and bottom face (20); and metallized external closed side walls (31, 32, 33, 34) vertically extending between said opposite external faces (10, 20) around the multilayer ceramic structure. The multilayer ceramic structure includes: on the top face (10), a metallized top central region (11) designed to receive an input electrical signal to be filtered, a dielectric top region (12) extending around the metallized top central region (11), and a metallized top peripheral region (13) extending around the dielectric top region (12) up to joining the metallized external closed side walls (31, 32, 33, 34) to act therewith as electrical ground, wherein the dielectric top region (12) is designed to ensure electrical insulation between the input electrical signal and the electrical ground; and, on the bottom face (20), a metallized bottom central region (21) designed to provide an output filtered electrical signal, a dielectric bottom region (22) extending around the metallized bottom central region (21), and a metallized bottom peripheral region (23) extending around the dielectric bottom region (22) up to joining the metallized external closed side walls (31, 32, 33, 34) to act therewith as electrical ground, wherein the dielectric bottom region (22) is designed to ensure electrical insulation between the output filtered electrical signal and the electrical ground. The multilayer ceramic structure further including ceramic layers (41, 42, 43, 44, 45, 46, 47, 48), first metallized layers (51, 53, 55, 57) and one or more second metallized layers (52, 54, 56) stacked on one another such that: each first metallized layer (51, 53, 55, 57) is interposed between two respective ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) arranged immediately on and below said first metallized layer (51, 53, 55, 57); each/the second metallized layer (52, 54, 56) is interposed between two respective ceramic layers (42, 43, 44, 45, 46, 47) arranged immediately on and below said second metallized layer (52, 54, 56); the first and second metallized layers (51, 52, 53, 54, 55, 56, 57) are vertically alternated such that each/the second metallized layer (52, 54, 56) has a respective upper first metallized layer (53, 55, 57) arranged above said second metallized layer (52, 54, 56), and a respective lower first metallized layer (51, 53, 55) arranged below said second metallized layer (52, 54, 56); and two ceramic layers (41, 48) are respectively arranged immediately below the top face (10) and immediately above the bottom face (11). The first metallized layers (51, 53, 55, 57) are joined to the metallized external closed side walls (31, 32, 33, 34), whereby said first metallized layers (51, 53, 55, 57), said metallized external closed side walls (31, 32, 33, 34) and said metallized top and bottom peripheral regions (13, 23) form an electrical ground structure. Each/the second metallized layer (52, 54, 56) is separated from the metallized external closed side walls (31, 32, 33, 34) by a respective first dielectric gap designed to ensure electrical insulation between said second metallized layer (52, 54, 56) and the electrical ground structure. Each/the second metallized layer (52, 54, 56) is connected to: an upper second metallized layer (52, 54, 56), or the metallized top central region (11), by means of a respective first electrically conductive via (62, 63, 64) that vertically extends between said second metallized layer (52, 54, 56) and said upper second metallized layer (52, 54, 56) the metallized top central region (11) through upper ceramic layers (43, 44, 45, 46, 47, 48) and the respective upper first metallized layer (53, 55, 57), wherein said respective first electrically conductive via (62, 63, 64) is separated from said respective upper first metallized layer (53, 55, 57) by a respective second dielectric gap extending around said respective first electrically conductive via (62, 63, 64), thereby forming a respective first capacitor; and a lower second metallized layer (52, 54, 56), or the metallized bottom central region (21), by means of a respective second electrically conductive via (61, 62, 63) that vertically extends between said second metallized layer (52, 54, 56) and said lower second metallized layer (52, 54, 56) the metallized bottom central region (21) through lower ceramic layers (41, 42, 43, 44, 45, 46) and the respective lower first metallized layer (51, 53, 55), wherein said respective second electrically conductive via (61, 62, 63) is separated from said respective lower first metallized layer (51, 53, 55) by a respective third dielectric gap extending around said respective second electrically conductive via (61, 62, 63), thereby forming a respective second capacitor. The metallized top and bottom central regions (11, 21) and the second metallized layer(s) (52, 54, 56) along with the respective electrically conductive vias (61, 62, 63, 64) and the respective capacitors form a capacitive feedthrough structure configured to receive the input electrical signal at/on the metallized top central region (11) and to provide the output filtered electrical signal at/on the metallized bottom central region (21), whereby filtering of the input electrical signal is carried out by the capacitors. The metallized top and bottom central regions (11, 21) are planar regions with no apertures.