Patent GB-1495825-A (GB)
Title: Signal synchronization in a satellite communication syste
IPC: H04B7/185
Filed: 1975-02-26
Abstract: 1495825 TDMA communication systems FUJITSU Ltd 26 Feb 1975 [26 Feb 1974] 8107/75 Heading H4M In a system in which mutually remote stations communicate by way of a satellite operating in time division multiplex, and in which a succession of synchronization signal bursts are transmitted from an individual remote station, that part of a burst which falls within a synchronization time window at the satellite being retransmitted to the station, the synchronization control circuitry at the station comprises (a) a synchronization signal generator which generates the succession of bursts; (b) a signal detector which detects the respective proportions of the bursts of the succession which are retransmitted by the satellite; (c) a phase error measurement arrangement which in dependence on the respective proportions of the synchronization bursts which are detected provides measures of phase error between the times of reception of the bursts of the succession at the satellite and the timing of the synchronization time window; (d) a phase correction decision arrangement which operates to designate a phase correction for the transmitted burst so as to reduce such phase errors, in dependence upon the respective measures treated cumulatively to reduce the possibility of error due to erroneous recognition of noise as part of the retransmitted burst and (e) a transmission phase control which controls the phase of succeeding synchronizing signal bursts in comparison with earlier bursts, in dependence on the phase correction last selected by the phase correction decision arrangement. The system is for use at the earth stations of an SDMA/TDMA satellite communication system. A standard clock signal from a generator I (Fig. 6) passes to a variable divider 2 which provides frame timing. At a given frame time a sync burst is produced by a circuit 3 and transmitted through a modulator 4 to the satellite 5. The burst comprises a pseudo noise, phase shift keyed signal and includes a preamble word for carrier acquisition and bit timing, a station identification code and measurement bits. As much of the burst as is received by the sync window at the satellite is retransmitted, detected by demodulator 6 and passed via a station identification circuit 7 to a phase error decision circuit 8 where a measurement of the phase difference between the station burst and the satellite window is derived. This is used to control the timing of pulses 10 from a phase control circuit 9 so as to adjust the divider 2 and hence the timing of the sync bursts from the circuit 3. The sync burst returned from the satellite and received at the grand station is applied via a line 11  (Fig. 7) to a unique word detector 17 which detects a unique word in the burst preamble, whose output controls a timing generator 17 and thus the timing of the ground station. The measurement bits in the received sync burst are applied to a shift register 12 whose content is continuously compared with the output of a pattern generator to which indicates the transmitted pattern. Coincidences for each given bit position in the measurement word detected by exclusive OR circuits 14, are applied to counters 16, which count coincidences for l sync bursts, whereat they are reset. The counts are applied to comparators 21 and counts in excess of a predetermined comparator input m are considered to correctly indicate a detected bit and are applied to the phase error decision circuit 25. This counts the number of received measurement bits. From this count is derived the phase error of the transmitted burst relative to the satellite window and this is quantized. Detailed logic circuitry is described for assessing how many measurement bits have been detected in the received sync burst, as indicated by the comparators 21, and for using the pulse outputs representing this assessment to control the generation of control impulses (Fig. 9, not shown). The phase error signal so produced is subtracted from a previously corrected value for the required transmission time phase held in memory 28 to generate a new value, which is retuned to the memory and also to a divide ratio controller 29. A detailed explanation of how the timing signals provided by the standard clock are adjusted in phase by the controller 29 is provided (Fig. 10, not shown), the divider being controlled by an N + 1 counter which can be reset at N and N - 1 counts depending on the signals supplied from the subtractor 27.