Patent GB-1390830-A (GB)
Title: Caracter representation systems
IPC: G09G1/10
Filed: 1973-02-13
Abstract: 1390830 Cathode-ray tube displays SIEMENS AG 13 Feb 1973 [24 March 1972] 6903/73 Heading H4T In a character display system a fixed word store, when addressed by input commands, supplies character segment data specifying particular ones of a finite number of directions in which segments are to be drawn to digital-toanalogue converters controlling X, Y coordinate deflections of a writing element, e.g. the beam of a cathode-ray display tube and additionally, supplies such data to an adder the output from which is fed to a register from which, when desired, it is fed back to the input of the adder. Thus, by adding a particular data word to itself or to another data word a further data word specifying a direction determined by the direction of the last segment trace is produced. By this means sixteen discrete directions (see Fig. 4), can be produced by employing only seven different input data code words. Fig. 1 shows the general scheme in which data, specifying characters to be displayed, derived from an input source 11 (e.g. a computer), which may be remotely located, is supplied via an image repetition store 12 to a character generator 13 from which deflection quantities are derived and supplied to the deflection coils of a cathode-ray display tube 19 via respective D/A converters 15X, 15Y and respective amplifier 16X, 16Y. Additionally a beam intensity control output is supplied to the tube via a control amplifier 14. Fig. 2 shows the arrangement of the character generator 13 which includes an address selection stage 21 receiving data in the seven-bit ASCII code I-VII from the image repetition store 12 and via switch position 35a supplies these bits together with bits VIII, IX and X, as a ten-bit word I-X to an address counter 22 and thence to a fixed word store 23. The latter which is organized as shown in Fig. 3, and contains 1024 words each of 12-bits comprises; a storage zone 23c containing the addresses of alpha-numeric character segment data and control data, a total of 128 words; a storage zone 23d containing the addresses of segment data of graphic characters and control data, a total of 128 words; a storage zone 23e containing segment data for alphanumeric characters (3 x 128 words) and a storage zone 23f containing segment data for graphic characters and control data (3 x 128 words). In operation, when alpha-numeric characters are to be displayed the ten-bit word I-X, with the bits I-VII indicative of the desired character in the ASCII code and the bits VIII=0, IX=0 and X=0 (see line 2, Fig. 3), addresses storage zone 23c which outputs a twelve bit word XI-XXII specifying the address of segment data and control data to a register 24 which, in response to the control data bits XXI-XXII, operates a switch control stage 26 to cause the bits XI-XX to be transferred via contacts 25c and 35b to the address counter 22 and thus to address storage zone 23e. The latter then outputs a second twelve-bit word of which the bits XI-XVIII specify the first segment, in terms of X-Y deflection of the desired character, the bit XIX, the beam blank-unblank requirements (the bit XX a function not specified and not relevant to the present invention), whilst the bits XXI and XXII which specify control data cause switch control stage to produce a bit XXIV which causes the address counter 22 to be advanced by "one" on the occurrence of the next timing pulse. The segment bits XI-XVIII are then effective via a control stage 28 and the D/A converters 15X, 15Y to produce the required beam deflection and the bit XIX is operative via a control stage 30 and amplifier 14 to control the beam blank-unblank requirements in accordance with the b output from a decoder 32. When the first segment has been traced control stage 28 emits a "1" from output d and assuming the character consists of more than one segment (otherwise address counter 22 would not have been advanced by "1"), the control bits XXI = 0 and XXII = 0 and the new address in counter 22 addresses the store 23 which provides segment and control data for the second segment of the character. The operation continues in this manner until the last segment has been traced this being signalled XXI=0, XXII=1 and XXIII=1 at which point the control bits XXI and XXII cause the switch positions 25a and 35a to be set in preparation for new input data from the image repetition store 12. When it is desired to display graphic characters (i.e. mathematical curves and equivalent traces), a distinctive seven-bit input word together with bits VIII = 0, IX = 0 and X = 0 is fed via address counter 22 into the store 23 which then emits a twelve-bit word XI-XXII having bits XXI = 1 and XXII=1. The latter bits then switch position 25d so that bits XI-XV pass to a decoder 32 supplying the bit XXV="1" to a trigger stage 33 which changes bit VIII from "0" to "1". This results in a new address word (line 3, Fig. 3), which now addresses storage zone 23d from which the address of the first segment of the graphic character is read out and stored in register 24. The control bits XXI = 1 and XXII = 0 in the latter address word set switch positions 25c and 35b which causes the bits XI-XX of this word to be transferred via address counter 22 to zone 23f in the store 23. The latter then outputs the data of the first segment of the graphic character and the operation continues in the same manner as for alpha-numeric character display. When the latter type of display is again required a distinctive address word I-X is input and addresses storage zone 23d from which a 12-bit output control word XI-XXII is derived, the bits XXI = 1 and XXII=1 setting switch position 25d to cause bits XI-XV to produce via decoder 32 the bit XXV=0 which changes trigger 32 back to its "0" state so that bit VIII is again "0", the value required for alphanumeric display. By giving the bits IX and X a value other than "0", i.e. a "1", further storage zones of the store assigned to a further class of characters may be addressed. Fig. 4 shows the (sixteen) different directions in which the beam may be deflected each direction being designated by a four digit "syllable" employing the bits XI-XIV in the group XI-XVIII supplied to control stage 28. The latter (see Fig. 5), includes a switching stage 35 (described below in connection with Fig. 6), and a decoder 40 which decodes the bits XI-XIV and supplies two four bit output words to the respective D/A converters 15X, 15Y and to respective up-down counters 49X, 49Y in which the counts are increased or decreased by one or two steps in accordance with the inputs. Such counts represent the binary co-ordinates of the end points of the last segment to be traced and are supplied via respective outputs f to the D/A converters 15X and 15Y. By supplying a signal to input 51 both counters are counted down and a "runback" effect to the start point of the first character segment is produced (e.g. the upper left-hand corner of the screen), and by supplying a signal to input 52 counter 49X alone is reset and a "run-back" to the start of a particular line is produced. The length of each segment is specified by the bits XV-XVIII (in the group XI-XVIII) which are stored in a counter register 54. When the count in the latter is other than zero a NOT gate 56 supplies a "1" output which maintains gates 36 to 39 and 41 to 48 conductive whilst counter register is being counted down until its count becomes zero at which point gate 56 emits a "0" and the other gates become non-conductive to terminate the tracing of the segment. Fig. 6 shows the switching stage 35 which comprises an adder 57, registers 58 and 59, AND gates 60-63 and an OR gate 64. The output of adder 57, (which forms the input to gates 36 to 39 of Fig. 5), is supplied to the register 59 which stores the input "syllable" only when a "1" is supplied to input a from input 66 the stored "syllable" being erased (i.e. all "0"s are stored), when a "1" is supplied to input b via inputs 51 or 65 and OR gate 64. A "1" input at 66, in addition to causing storage, also renders AND gates 60-63 conductive whilst an "0" at this input prevents storage. Three operational modes are possible. In the first mode an "0" is supplied to input 66 and thus the "syllable" XI-XIV is transferred, unmodified, to the decoder 40 (Fig. 5), so that the beam of the tube traces a segment having co-ordinates related to the X and Y co-ordinate axes of Fig. 4. In the second mode, an "0" is supplied to input 65 and a "1" to input 66 so that register 59 stores the input "syllable" from register 58 and supplies them via the gates 60-63 to the input of adder 57. Thus, the beam of the tube which has already traced a segment corresponding to the "syllable" (i.e. in the direction specified by the "syllable"), now traces a segment corresponding to that specified by the digital sum of the two inputs to adder 57, in this case a digital value equal to twice the initial input to the adder. In this manner, by repeated addition of a "syllable" to itself segments having the directions shown in Fig. 4 may be successively traced in clock-wise order, such segments being related to the direction of a preceding segment and not to the X and Y axes. In the third mode "0" signals are supplied to inputs 65 and 66 so that gates 60-63 are blocked and any previously stored signals in register 59 are not modified by the output of register 58. Thus, operation in the first mode results. When operation in this mode has been completed a "1" may be supplied to input 66 so that the previously stored signals in register 59 are added to the signals in adder 57 which now produces a signal specifying a direction dependent on the direction of the previously stored signals. In this manner, by the supply of suitable inputs to 51, 65 and 66 operation may be switched between the various modes resulting in a reduction of the number of code words required for the selection of characters to be traced. Thus, i