Patent GB-1057382-A (GB)
Title: Data processing system
IPC: G06F9/22
Filed: 1963-09-23
Abstract: 1,057,382. Digital computers. SPERRY RAND CORPORATION. Sept. 23, 1963 [Oct. 1, 1962], No. 37325/63. Heading G4A. A data processing system is characterized in that instructions are carried out by means of microinstruction words (called " control words " or " subcommands ") which are erasably stored in the computer memory. General arrangement.-The computer described comprises a magnetic thin film highspeed memory 10 for storing operands, instructions and control words and having a capacity of 1024 24-bit words. Associated with the memory are an address decoder (translator) 12 which can receive inputs from a programme address counter (PAZ) 16 a control word address counter (SAC) 22 and an operand referencing counter (SAZ) 26; a memory exchange (Z-register) 34; and a control word register (C-register) 32. A programme control register (PCR-register) 54 and associated translator is employed to interpret instructions. The arithmetic section employs subtractive logic and includes an X-register 70 which serves as a buffer or can hold an addend; an accumulator (A-register) 74 and associated borrow tree 72 which can be as described in Specification 967,045; a shift matrix 104 and associated register 106 for shifting words. The computer includes also a search memory 120 adapted to supply the address of a word when the word sought is applied as an input, the address being temporarily stored in a register 122. An instruction word is a 24-bit word having one of the formats shown in Fig. 2. A control word is a 24-bit word, each bit of which, when a " 1," causes the execution of a corresponding microinstruc - tion, as shown in Fig. 4. The address portion of an instruction specifies the memory address of the first control word of a control word sequence for performing that instruction. Certain of these sequences may be for " housekeeping " purposes, such as the acquisition of the next instruction in a sequence. General operation.-Initially the operator closes a switch which clears all the machine registers and inserts a " 1 " in the lowest order of the C-register 32. The operator then inerts manually the address of the first instruction into the PAZ-register 16 and subsequently depresses a " run " button to initiate machine operation. Since bit O of the C-register is set to " 1," subcommand O, Fig. 4, is executed, thereby effectively clearing the SAC-register 22, and initiating an automatic sequence of subcommands to retrieve the first instruction. This is effected by a sequence of three subcommands, the first having control word bit 6 (C<6>) set, the second having bits C<7> and C<11> set and the third having bit C set, these subcommands being accessed under the control of the SAC-register 22, which is incremented by unity after each subcommand is performed. Subcommand C causes the upper four bits in the Z-register 34, i.e. the N designator, Fig. 2, of the instruction, to be transferred to the SAC-register 22 to serve as a subcommand address initiating a subcommand sequence for executing the instruction. A normal instruction is as shown in line 1 of Fig. 2, the F and T portions designating the computer components from and to which respectively a transfer of data is to take place. In a stop-jump type of instruction, line 4 of Fig. 2, a stop or jump takes place, according to the state of manuallyoperable stop buttons and jump buttons on the computer console, the instruction employing subcommand C<23>, Fig. 4, in its execution. In a shift type of instruction, line 2 of Fig. 2, a word located in a register specified by the F- designator is transferred to the shift matrix 104 where it undergoes a shift by a number of places determined by the shift count (SK) designator of the instruction word, the N- designator specifying the starting address for a sequence of two subcommands for executing the instruction, the first having bit C<16> set and the second having bits C<8> and C<18> set. A subcommand sequence is described in the Specification for a " search " instruction in which the search memory 120 is tested to see if it contains a given word, the address of the word, if found, being transferred to the register 122 and thence via the Z-register 34 to the memory 10. Logic module.-The computer employs NOR logic circuits (Fig. 5, not shown), including transistors. Circuit details.-The Specification describes in detail the memory access circuits and the 24 stages of the C-register 32 which control the various subcommands shown in Fig. 4. Timing arrangements.-The main memory is under the control of a timing chain comprising six flip-flops (Figs. 22a-22d, not shown), driven by a two-phase clock, the timing chain providing signals to control transfer between the memory and various registers in the computer. The normal memory timing cycle is interrupted and replaced by a special timing sequence when subcommand C<3 >= increment programme address register PAZ is effective (Fig. 15, not shown).