baber/WOPTO huggingface dataset:
Patent JP-H08121482-A (JP)
Title: Air bearing
Inventor: YAMAMURA MOTOHISA
IPC: F16C32/06
Filed: 1994-10-18
Abstract: PURPOSE: To reduce the clearance between a rotary shaft and an air jet member, even in the case where a temperature rises by rotation of the rotary shaft at a high speed. CONSTITUTION: When a rotary shaft 36 is rotated at a high speed to generate heat, a temperature rises in the rotary shaft 36, bearing bases 17, 18 and air ejecting member 31, 32 to perform thermal expansion, but since the air ejecting members 31, 32 with a coefficient of thermal expansion smaller than the rotary shaft 36 is fixedly inserted to the bearing bases 17, 18 with a coefficient of thermal expansion larger than the rotary shaft 36, the air ejecting members 31, 32 are largely expanded by receiving an influence of the bearing bases 17, 18, to make expansion (enlarging internal diameter) of the air ejecting members 31, 32 approach expansion (enlarging external diameter) of the rotary shaft 36.
Patent JP-S63132510-A (JP)
Title: Programmable gain-controlled amplifier
Inventor: TANIGUCHI AKIRA
IPC: H03G3/12
Filed: 1986-11-25
Abstract: PURPOSE:To eliminate the need to arrange many high-accuracy resistors and to reduce the cost of a programmable gain-controlled amplifier by controlling the gain of the amplifier according to a duty ratio which is set variably by a pulse width/voltage converting circuit. CONSTITUTION:The pulse width/voltage converting circuit 6 is provided with two analog switches S1 and S2, a filter for smoothing consisting of a resistance R2 and a capacitor C2, and a duty ratio varying circuit 7 as a means for varying and setting the duty ratio T1/T2 of a pulse (e) to a necessary value. The duty ratio varying circuit 7 is connected directly to the analog switch S1 and also connected to the other analog switch S2 through an inverter 8. The output E0 of the programmable gain-controlled amplifier is controlled by the pulse width/voltage converting circuit 6 to a value corresponding to the duty ratio T1/T2 to perform control to desired gain.
Patent JP-S63133861-A (JP)
Title: Stepping motor
Inventor: HATANAKA TAKESHI
IPC: H02K37/08
Filed: 1986-11-25
Abstract: PURPOSE:To increase the volumetric ratio of a coil, by concentrating flux, generated in cylindrical driving coils, into an inner cylindrical stator magnetic pole and an outer stator magnetic pole to arrange the flux in the areas of plural radii of curvature. CONSTITUTION:A stepping motor 10 is equipped with a frame 12, a stator 14 and a rotor 26. A housing 16 is fixed to the yoke 15 of the stator 14 and the output shaft 22 of the rotor 26 is supported through bearings 18, 20. Cylindrical driving coils 28-32 of first-third phase are arranged in the stator 14 concentrically with different radii of curvature while inner and outer cylindrical stator magnetic poles 34-44 of first-third phase are arranged inside and outside of the coils. A plurality of arc-shaped magnetic pole teeth 34p-44p, a plurality of troughs 34c-44c and a plurality of slits 34s-44s are formed on said magnetic poles 34-44. Cylindrical magnetism interrupting members 46-50 and magnetism interrupting rings 52-56 are arranged to prevent the leakage of magnetism whereby the electromagnetic energy converting efficiency of the motor may be improved.
Patent JP-H0591935-A (JP)
Title: Seat device
Inventor: SAITO MITSUHIRO
IPC: A47C7/46
Filed: 1991-09-30
Abstract: PURPOSE:To set the hardness of a seat cushion with a switch operation by calculating drive data of a drive means according to the input from an operating switch or a detecting signal from a body pressure sensor group when the hardness of a cushion member is set by vertically moving a spring with the drive means. CONSTITUTION:A plurality of springs 21 supporting from below a cushion member of a seat cushion 2 are vertically moved by drive means disposed respectively below the respective springs 21 to set the hardness of the cushion member to a level determined by the height of the moved spring 21. Drive data for the drive means are calculated by a CPU 201 on the basis of the input of a switch 100 or the input of a body pressure sensor SEC on the cushion surface. Thus, the hardness of the seat cushion can be set to a desired level by a simple switch operation. Also, even in traveling, the hardness of the seat cushion can be adjusted to be adapted to a change in position and fatigue can be prevented.
Patent JP-H01120905-A (JP)
Title: Supporting method for planar antenna
Inventor: IYAMA HIROYUKI
IPC: H01Q3/08
Filed: 1987-11-04
Abstract: PURPOSE:To eliminate the need for changing the conductor pattern depending on the direction of the wall or roof of a building with the title antenna installed therein by devising a tilt beam antenna which is turned within the plane of the antenna around one point in the plane. CONSTITUTION:The planar tilt beam antenna 1 has a conductor layer and a dielectric layer used for a microwave, the layers are processed to a desired shape and laminated and incorporated and its directivity is determined only one direction not coincident with a perpendicular line with respect to the plane of the planar antenna in any of the conductor layer and dielectric layer or both. In order to device the tilt beam antenna 1 such that it can be turned within a plane of the antenna 1 around one point on the plane, several points of the ridge of a disk structure 3 supporting the antenna 1 are fixed to a fixed frame 4a through a ball bearing, etc., so that the disk structure 3 can be turned or a shaft is fitted to the center of the structure and the structure is fixed to a supporting base 4b. In this case, the shaft 5 is fitted to the fixed frame 4a or the supporting base 4b so as to vary the elevating angle of the antenna.
Patent JP-H10102276-A (JP)
Title: Lead and lead-tin alloy plating bath
Inventor: UCHIYAMA NAOKI
IPC: C25D3/56
Filed: 1996-09-30
Abstract: PROBLEM TO BE SOLVED: To obtain a high Pb-Sn alloy plating bath giving a smooth surface by adding a specified arom. compd., a nonionic or cationic surfactant and a leveling agent to an aq. soln. of specified Pb and Sn compds. SOLUTION: An arom. compd. such as 4,4'-dihydroxydiphenyl sulfide, a nonionic or cationic surfactant such as styrenated phenol and a leveling agent such as cyclohexylamine salt of 2-mercaptobenzothiazole are added to a Pb or high Pb-Sn alloy plating bath contg. lead alkanesulfonate such as lead methanesulfonate and/or lead alkanolsulfonate such as lead isethionate and alkanesulfonic acid such as methanesulfonic acid and/or alkanolsulfonic acid such as isethionic acid or further contg. tin alkanesulfonate and/or tin alkanolsulfonate to obtain the objective Pb or high Pb-Sn alloy plating bath contg. <50ppb radioisotopes as impurities, having <0.1CPH/cm2 count number of α-corpuscles emitted from Pb and giving a smooth surface.
Patent JP-S62140290-A (JP)
Title: Magnetic bubble memory element
Inventor: SUZUKI TETSUAKI
IPC: G11C11/14
Filed: 1985-12-13
Abstract: PURPOSE:To increase the lower-limit margin of a bias magnetic field and to expands an operation margin by increasing the distance between tips of leg parts of opposite transfer patterns in a minor loop. CONSTITUTION:When the distance between tips of opposite leg parts at the part composed of a transfer pattern 11 with a minimum transfer period lambda0 in the pattern of the straight part of the minor loop is denoted as l0, magnetic bubble transfer lines 10a and 10b are so constituted that the distance ln between the tips of opposite leg parts at the part composed of a basic transfer pattern 12' with a period lambdan larger than the period l0 is larger than lambda0. Then, the distance ln between opposite patterns 12' is large at the position of the pattern 12', so magnetic bubbles become hard to move to reduce the generation of transfer errors, thereby expanding the margin of the lower limit value of the bias magnetic field.
Patent JP-H02126650-A (JP)
Title: Manufacture of dielectric isolation semiconductor device
Inventor: TANZAWA KATSUJIRO
IPC: H01L27/12
Filed: 1988-11-07
Abstract: PURPOSE:To effectively prevent the bottom of an element isolation groove from being side-etched and to obtain a semiconductor device whose isolation breakdown strength is high and whose reliability is high by a method wherein a silicon nitride film is used as an etching mask of the element isolation groove. CONSTITUTION:A silicon nitride film 25 (a second film) of 0.3mum is formed, by a CVD method, on the surface of an active layer of a united substrate; it is patterned and used as an etching mask; an anisotropic etching operation is executed by using an alkaline solution; a V-shaped groove 26, for element isolation use, reaching an oxide film 23 is formed. Then, a p<+> type layer 242 with a depth of about 3mum is formed on side faces of the V-shaped groove 26. Boron glass 27 formed on the side faces of the V-shaped groove 26 is etched and removed by using dilute hydrofluoric acid in such a way that an element- isolation dielectric film (a first insulating film) 23 is not excellent. The silicon nitride film 25 used as the mask is etched and removed by using hot phosphoric acid. Then, a thermal oxidation operation is executed; an oxide film (a third insulating film) 28 of 1mum is formed on the side faces of the V-shaped groove on the surface of the active layer.
Patent JP-2001102331-A (JP)
Title: High flatness back surface matted wafer and its manufacturing method and/or front surface grinding back surface lapping device used for manufacturing method
Inventor: TANAKA KEIICHI
IPC: B24B37/00
Filed: 1999-09-30
Abstract: PROBLEM TO BE SOLVED: To obtain a back surface matted wafer, where the front surface is highly flat and the selectivity of back surface glossiness is large, its manufacturing method, and a front surface grinding back surface lapping device used for the manufacturing method. SOLUTION: Slice damage is removed coarsely by low-accuracy etching. The front surface of wafer is subjected to low-damage grinding, and at the same time the back surface of the wafer is subjected to low-damage lapping. The front surface of the wafer has high planarity for reducing the machining damage of the front and rear surface. In a succeeding high-accuracy acid etching, the amount of etching is reduced. An etchant to be used can be appropriately selected, the high planarity is maintained, and at the same time, glossiness of the back surface can be freely selected. A grinding whetstone ranging from #1500 to #4000 is used, the depth of damage is set to approximately 2 μm, and at the same time, grinding is made without damaging the front surface. In back surface lapping, alkaline-family lapping liquid containing an FO abrasive grain ranging from #1500 to #4000 is used.  The back surface can be lapped with low damage and at the same time high throughput. Also, the front surface after etching is subjected to mirror polishing.
Patent JP-H10126511-A (JP)
Title: Intercom equipment
Inventor: SEKIJIMA KENOU
IPC: H04M3/54
Filed: 1996-10-22
Abstract: PROBLEM TO BE SOLVED: To obtain the equipment that connects an entrance slave set and an external line terminal equipment at a transfer destination by sending an external line number registered in an automatic speech section to the external line terminal equipment via a speech network and a channel control circuit from a dialer. SOLUTION: When a ten-key 9 is operated to enter an intercom transfer command registered in a CPU 20, a dialer 8 detects a PB signal and provides an output to a DTMF circuit 10 via a speech network 5. The DTMF circuit 10 converts the received PB signal into data and provides an output of the data to a PB signal reception pin P10 of the CPU 20. Then a password confirmation section provided to the CPU 20 detects it to close an intercom transfer switch. When the intercom transfer switch is closed, a reference level is given to an external transfer mode use LED lighting pin P2. Thus, an external line transfer mode use LED 14 denoting it that the intercom transfer is set is lighted.
Patent JP-2001101843-A (JP)
Title: Recorder and recording method
Inventor: ICHII YUTAKA
IPC: G11B27/10
Filed: 1999-09-30
Abstract: PROBLEM TO BE SOLVED: To enable video and voice information to be selected and reproduced simply when plural video and voice information are recored on a disk. SOLUTION: When a video recording button 17 is pushed, a video signal from an imaging device 10 and a voice signal from a voice input means 11 are outputted as compressed signals from a video and voice signal processing circuit 12. At this time, the compressed signals before the button 17 is pushed again are recorded on a disk 25 as the compressed signals of the portion of a cut and a still picture and TOC information corresponding to the compressed signals of the portion of a cut an the screen information of table of contents constituted so as to be able to reproduce only a desired cut when plural cuts are recorded on the disk 25 in addition to the compressed signals.
Patent JP-2001100015-A (JP)
Title: Diffracting optical element and optical system composed of same diffracting optical element
Inventor: SATO HIDEKI
IPC: G02B5/18
Filed: 1999-09-30
Abstract: PROBLEM TO BE SOLVED: To provide a diffracting optical element which can form a polygonal shape capable of maintaining high diffraction efficiency by a small number of straight lines when forming the polygonal shape similar to an ideal shape of a relief type diffracting optical element and can effectively suppress a flare, etc., when built in an optical system and the optical system composed of the diffracting optical element. SOLUTION: The diffracting optical element has a laminate structure wherein at least two or more layers of diffraction gratings are stacked; and the sectional phase of the diffraction grating is a relief type shape derived from a shape shift function by the polygonal shape obtained by connecting one or more straight lines in order and the sectional shapes of the diffraction gratings which are put one over another are similar.
Patent JP-H03142640-A (JP)
Title: Conversion system for file record form
Inventor: MISAWA KENTARO
IPC: G06F3/06
Filed: 1989-10-30
Abstract: PURPOSE:To store data among files of different data forms by providing four data conversion means. CONSTITUTION:A data store means 401 stores a data train which includes a file form recording medium 402, the data records 403 - 405, a file length recording means 406. A form conversion means 101 reads the data train out of a data store means 201 and deletes a data termination code 209 to divide the data train into data 202 - 205 based on the line feed codes 206 - 208. Then, the data 202 - 205 are allocated to the data records 303 - 306 of a data store means 301, and the lengths of data 202 - 205 are stored in the record length store means 307 - 310. A form conversion means 101 reads the data train out of a data store means 201 and deletes the code 209. Then the means 101 divides the data train by the length of the record 403 and stores the decomposed data in the records 403 - 405 of the means 401. Thus, the data can be stored among files of different data forms.
Patent JP-2000111321-A (JP)
Title: Method of and device for correcting luminance of stereo image
Inventor: KAWAI YOSHIHIRO
IPC: G06T7/00
Filed: 1998-10-01
Abstract: PROBLEM TO BE SOLVED: To correct luminance of stereo image from the correspondent relations of characteristic quantities of image. SOLUTION: Stereo images are input and the edges of each image are detected (S1). Segments are extracted (S2) and characteristic quantities of each segment are obtained (S3). Correspondence of segments between stereo images is obtained (S4), and from the corresponding part, shielding profile is eliminated (S5). From the correspondent relation of luminance obtained by this process, a luminance correction equation is obtained (S6) and luminance of stereo images is corrected (S7). Then this process is repeated until the luminance correspondence agrees between stereo images to correct luminance of stereo images.
Patent JP-H01120958-A (JP)
Title: Communication record managing system
Inventor: HIBINO HIROKATSU
IPC: H04B17/00
Filed: 1987-11-05
Abstract: PURPOSE:To display again communication recording automatically without the operation of an operator by updating the communication recording by the data transmission/reception between a recording/updating means (program) and a display means (program) so as to update the display of communication recording. CONSTITUTION:In case of data transmission, a transmission data read section 11 reads a transmission data from an auxiliary storage 5 and a transmission section 12 sends a data to a MODEM 13 to complete the transmission. In case of reception, when a reception data is sent from a MODEM 13 to a reception section 14, a reception data registration section 15 records the received data in an auxiliary storage 5. When the transmission or reception is finished, the result of communication (success or failure of communication, etc.) is given to a recording generation section 16 to generate a recording file. A display program 20 reads a buffer Q at a prescribed time interval, a record updating discrimination section 21 discriminates whether or not the recording is updated and when the read data exists (revision of recording), the communication recording is displayed again.
Patent JP-H05121740-A (JP)
Title: Method of simulating semiconductor device
Inventor: AMAKAWA HIROTAKA
IPC: H01L21/00
Filed: 1991-10-25
Abstract: PURPOSE:To calculate accurately the impurity distribution in a region, whose diffusion coefficient is small, in the vicinity of the interface of the region and another region whose diffusion coefficient is large and considerably different from the coefficient of the small diffusion coefficient region, even if the mesh of the small diffusion coefficient region is rough in the vicinity of the interface. CONSTITUTION:First and second regions having small and large diffusion coefficients respectively forms an interface. Digitizing meshes are used for one-dimensional simulation of the process of manufacturing a semiconductor device. If the mesh of the area of the first region is rough in the vicinity of the interface, the amount of transportation of an impurity at the interface between the regions is given using an analytical formula. In the case where after a diffusion process is performed, an ion-implantation is performed and a diffusion process is further performed, another value of the amount of the transportation of the impurity found applying the analytical formula to the increment of the impurity concentration at the interface due to the ion-implantation is added to the former amount of transportation of the impurity, and the sum is used as the simulated amount of transportation of the impurity. Accordingly, even in the case where the meshes in an oxide film is rough, the boron concentration in the surface of a substrate can be calculated accurately. The boron concentration in the surface of the substrate of (a) is calculated abnormally low by a conventional method.
Patent JP-S61155346-A (JP)
Inventor: DEIBITSUDO JIYON MOOGANZU JIYU
IPC: B01J27/12
Filed: 1985-12-11
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H03142541-A (JP)
Title: High speed memory access system
Inventor: HIRAUMA KOICHI
IPC: G06F12/00
Filed: 1989-10-27
Abstract: PURPOSE:To improve the bus access performance of a CPU by switching smoothly a normal mode with an advanced mode and making best use of the address first-out effect of the advanced mode. CONSTITUTION:A CPU 1 contains an ADAEN terminal as conventional and is set in a normal mode and an advanced mode with the ADAEN terminal set at H and L levels respectively. In a conventional mode switching system, the DRAMCS signal of an address decoder 2 is used directly as an ADAEN signal. In this system, however, the DRAMCS signal is inputted to the ADAEN terminal via a mode control circuit 7. The circuit 7 consists of a flip-flop 71, an AND gate 72, and an inverter 73. The DRAMCS signal of the decoder 2 is inverted by an inverter 73 and then 'D' inputted to the flip-flop 71 after an AND secured between the inverted input of the inverter 73 and the inverted input of a BCYST signal of the CPU 1 via the gate 72. Then the 'Q' output of the flip-flop 71 is inputted to the ADAEN terminal of the CPU 1.
Patent JP-H06130660-A (JP)
Title: Positive photoresist composition
Inventor: SHIMIZU NAOTO
IPC: G03F7/023
Filed: 1992-10-20
Abstract: PURPOSE:To obtain a positive photoresist compsn. excellent in both of resolution and heat resistance. CONSTITUTION:This positive photoresist compsn. contains an alkali-soluble novolac resin and 1,2-naphthoquinone diazide compd. The alkali-soluble novolac resin consists of a novolac resin (I) and low mol.wt. compd. (II). The novolac resin (I) contains 10-30wt.% binuclear compd. obtd. by additional condensation reaction of phenols and formaldehyde. The compd. (II) contains >50wt.% 2- to 4-nuclear compd. obtd. by additional condensation reaction of formaldehyde and phenols except for the phenols used to obtain the resin (I). Further, the alkali-soluble novolac resin contains 10-50wt.% binuclear compd.
Patent JP-H10126558-A (JP)
Title: Image forming system, image input device and image output device
Inventor: KANANO SATOSHI
IPC: H04N1/00
Filed: 1996-10-23
Abstract: PROBLEM TO BE SOLVED: To allow the image input device to set all output conditions of image data set by the image output device by allowing the image output device to send a setting program to the image input device and allowing the image input device to set the output conditions of image data based on the setting program. SOLUTION: The image input devices 10, 10a and the image output devices 20, 20a...20e are interconnected via a communication line 40, and upon the receipt of image data from the image input device 10 or 10a, any of the image output devices 20, 20a...20e outputs the image data on recording paper or on a public line. The image input device 10 sets output conditions of image data based on status information and a user interface program sent from each of the image output devices 20, 20a...20e. Thus, the image input device 10 or 10a sets all output conditions of image data attained by any of the image output devices 20, 20a...20e.
Patent JP-S63137566-A (JP)
Title: Sealing method for ladle of refinary furnace
Inventor: FURUNO YOSHIKATSU
IPC: B22D41/015
Filed: 1986-11-27
Abstract: PURPOSE:To prevent the infiltration of an air from the gap between the upper end face of a ladle and a water cooling cover and the flow-out of a molten steel, to maintain the molten steel in good quality, to stabilize the yield thereof and to reduce the breakdown of a ladle by spreading fireclay refractories all over the upper end face of the ladle and placing a water cooling cover thereon. CONSTITUTION:Fireclay refractory block plates 6 are spreaded all over the upper end face of the ladle 2 in which a molten steel 1 is poured and a water cooling cover 3 is placed thereon. The block plate 6 is crushed with the tare of the water cooling cover 3 to eliminate the gap between the both. Consequently the air infiltration from this gap and the flow-out of the molten steel 1 are prevented to maintain the molten steel in good quality, the yield thereof is stabilized and the damage on the upper end face of the ladle 2 is reduced as well.