Patent GB-1477511-A (GB)
Title: Methods of manufacturing semiconductor devices
IPC: H01L21/28
Filed: 1974-05-21
Abstract: 1477511 Semiconductor devices MULLARD Ltd 21 May 1974 22583/74 Heading H1K A narrow low resistivity strip of uniform width is formed in a layer of high resistivity polycrystalline semiconductor deposited on an insulating layer at the surface of a semiconductor wafer, by providing a masking layer on it, removing part of the polycrystalline layer so that an edge of it is exposed adjacent an edge of the masking layer, and diffusing a dopant or dopants laterally into said edge of the polycrystalline layer to form a low resistivity strip lying entirely beneath the masking layer. In one embodiment the strip is formed beneath nitride masking by diffusion of boron, and the high resistivity polysilicon removed by etching with a specified selective etchant after the masking has been stripped off. In another embodiment boron and phosphorous are successively diffused to define a P type strip between their diffusion fronts, and the polysilicon bounding the strip similarly removed by selective etching. In either case the required part of the boron doped strip may then be oxide coated and the rest removed by etching. The residual strip may define the gate of an of an IGFET the source and drain of which are formed by implantation of boron through the oxide flanking gate. Fig. 7 shows a pair of load resistors constituted by IGFETs with a common drain region 59 to which their gates 61 and 62 are shorted. In manufacture a thick oxide film is formed on the high resistivity substrate, removed and replaced by thin oxide within the area bounded by the dashed line, the thin oxide removed within the dotted line, polycrystalline silicon deposited overall and removed, except within the area bounded by the chain line, by etching using thin oxide or nitride masking which is retained on the remaining silicon, photoresist applied and removed except within the area bounded by the line of crosses, residual thin oxide removed by etching, the remaining resist removed, and boron diffused to form the source and drain regions and dope the edges of polysilicon region 69 to form the gates and the uncovered area of it extending on to the drain region. Oxide 63 is then deposited overall and apertured over electrode regions 57, 58, 59 for contacting. Alternatively where the structure is combined with other components in a monolith an electrode region (Fig. 11) may be extended as shown to provide an interconnection with a similar region of another IGFET which may be crossed by a track such as 73 fabricated from the overall polysilicon layer. In the area bounded by line of crosses 76 the oxide on the track and beneath the polysilicon are retained during the boron diffusion so that conductive strips 77, 78 are formed by lateral diffusion, and the electrode regions 74, 75 and track doped. After removal of the thin oxide from and laterally of track inside line 76 the undoped polysilicon between strips 77, 78 is removed by selective etching and boron diffused in to form shallower extensions of regions 74, 75 and a region between strips 77, 78 the depletion regions of which overlap to provide conductive continuity. Specification 1477512 is referred to.