Patent GB-1271722-A (GB)
Title: Telephone switching systems
Inventor: LUCAS PIERRE
IPC: H04Q3/545
Filed: 1969-04-21
Abstract: 1,271,722. Automatic exchange systems. P. LUCAS, and M. ROUZIER. 21 April, 1969 [19 April, 1968], No. 20288/69. Heading H4K. A multi-stage switching network, using relay cross-point matrices and operated from a control circuit 1, comprises inlets 71 and outlets 77, connections being set up in response to a marker 44 from a marked inlet 71 to a selected junctor in a junctor group 14 over cross-point relays selected by route markers 31, 32, 33 in switching stages 21, 22, 23; such connection being extended at the same time to a wanted outlet 77 over stages 24, 25, 26 by operating cross-point relays selected by markers 34, 35, 36; the inlets, outlets, and junctors being served by respective identifiers 61, 67, 64 which operate in response to current surge occurring in the establishment of a connection or in response to current surge produced at a selected inlet or outlet by identification markers 41, 47. The inlets, outlets, junctors and interstage links are supervised for purposes of route selection and path checking by testers 51 to 57 which interrogate magnetic cores threaded by the hold wires of the network. Further cores threaded by the hold wires are employed by the identifiers 61, 64, 67, to detect current surges. To effect a connection the control circuit 1, Fig. 4, receives from a computer 2 the addresses of the terminals 71 and 77 between which connection is to be established. These addresses are stored in register 107 while a register 106 cycles over the addresses of free junctors in stage 14 providing possible paths and each defining a set of addresses gating the testers 52, 53 and 55, 56, to see if the associated links are free. If the testers signal a free route from a terminal to a junctor the associated cross-point relays are marked from the routing markers and marker 44 connects battery from the junctor to set the connection up. The current surge in the hold wire is detected by identifiers 61 and 67 and the resulting terminal identities are checked against the identities in register 107. If no path is connected, no code is received in this checking phase, if a double connection is made the identifiers produce a code with more binary ones than should be present, and in either case a fault is identified. When a connection is fully established from terminal to junctor and junctor to terminal, the identification markers are activated one after the other to pulse the hold wires at each terminal and the identity of the junctor detected twice by identifier 64 is checked against the identity of the junctor in register 106. Finally, all the testers 51 to 57 are actuated to test the busy condition of each component link of the path. If the phase control circuit 101 advances the phase register 102 and order register 103 thus far successfully, the control circuit is cleared. To effect release of a connection from the identity of a terminal 77, the marker 47 is directed to pulse the terminal and thereby obtain the identity of the associated junctor in group 14. Marker 44 is then instructed to pulse the junctor so as to obtain the identity of the associated terminal 71 which terminal is then pulsed by marker 41 to re-obtain the identity of the junctor as a check. If this sequence of operations proves self-consistent, the disconnection marker 144 is instructed to release the connection from the junctor and the testers 51 to 57 are recruited to confirm that the path is released. The identities of matrices subject to congestion are recorded in a register 104 and the identities of matrices for which links become free are set up in register 108. If the contents of registers 104, 108 show a match, the corresponding matrix is removed from the congested record and is included in subsequent route search sequences. A connection from a terminal 71 to a first terminal 77 may be transferred to a second terminal 77 in a process called external lines change. This involves establishing all the conditions of release but postponing release by marker 144 until a route search has established the existence of a free path to the second terminal 77, whereupon the transfer is effected. The markers, testers, identifiers, and control units are provided in duplicate, the markers testers and identifiers of a number of network frames being addressed selectively over a common bus system, Fig. 5 (not shown).