Patent SG-11201808969X-A (SG)
Title: Barrier layer for interconnects in 3d integrated device
Inventor: SOARES EDWARD R
IPC: H01L25/065
Filed: 2017-03-14
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property :::` , Organization 111111101111 0 111010101111101011111 0 011111111111111111111111111111111111111 0111111 International Bureau (10) International Publication Number 03 (43) International Publication Date ......°' WO 2017/200632 Al 23 November 2017 (23.11.2017) WIPO I PCT (51) (21) (22) (25) Filing Language: (26) (30) (71) International Patent Classification: HOlL 23/485 (2006.01) HOlL 25/065 HOlL 21/60 (2006.01) International Application Number: International Filing Date: 14 March 2017 (14.03.2017) Publication Language: Priority Data: 15/156,087 16 May 2016 (16.05.2016) PCT/US2017/022284 (72) Inventors: SOARES, Edward R.; 1181 Onstott Road, (2006.01) Lompoc, California 93436 (US). DRAB, John J.; 2324 Sonora Drive, Santa Barbara, California 93105 (US). (74) Agent: WOLF, Richard A.; RENNER, OTTO, BOISSELLE & SKLAR LLP, 1621 Euclid Avenue, 19th Floor, Cleveland, Ohio 44115 (US). (81) Designated States (unless otherwise indicated, for every English kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, English CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, US HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, [US/US]; MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, Massachusetts PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, Applicant: RAYTHEON COMPANY 870 WINTER STREET, WALTHAM, 02451-1449 (US). Title: BARRIER LAYER FOR INTERCONNECTS 16 2 16 : An electronic device integration preparing a first electronic device by forming an electrically conductive trace overlying electrically conductive trace, forming one or overlying the trace and/or at least partially surrounding the one or more interconnects. of an intermetallic compound between the trace and interconnect structures, the trace and interconnect. The integration method may further include the steps a second electronic device, direct bonding a third electronic device to the second electronic and functional testing of the vertically integrated electronic device may be conducted (54) = cz formation 0 between IN treatment IN 3D INTEGRATED DEVICE 10 14 = _ = = = = r E A 12 18 18 12 14 10 The integration method may include the steps a substrate, forming a barrier layer overlying on the barrier layer, and forming a bonding The barrier layer is configured to prevent while still enabling electrical communication of direct bonding the first electronic device device, and so on. A high-temperature after each stack sequence. __I: = 'BMW FERMI INESE = 28 1 24 24 = = = REIBUTTNEMMIS = t Ai v ----.. : lir = = = = Fig. 2A method and integrated electronic device. more electrically conductive interconnects = , -1 (57) . .41 4 of ei the f .r1 layer --.., \" to Il 0 ei O [Continued on next page] WO 2017/200632 Al MIDEDIMOMOIDEIRMEM001010111011011001011MEMOIMIE GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))