Patent GB-1342463-A (GB)
Title: Device for testing the operation of integrated circuit units
IPC: G01R1/04
Filed: 1972-06-08
Abstract: 1342463 Logic circuit testing apparatus HONEYWELL INFORMATION SYSTEMS ITALIA SpA 8 June 1972 [9 June 1971] 26889/72 Heading G1U A logic circuit testing arrangement includes a reference circuit nominally identical to the circuit under test, means for commoning the inputs of the two circuits, means for connecting a corresponding output pair of outputs from the two circuits to a comparator, means for storing those disagreement signals from the comparator that exceed a minimum duration (in order to prevent transients causing spurious operation) and for actuating an alarm indicator. The output signals of the circuit under test may also be examined to ensure that they lie either below or above preset thresholds and in the preferred embodiment a plurality of comparators are employed so that every pair of corresponding outputs from the circuit under test and the reference circuit can be compared simultaneously, any disagreement signals sufficiently long actuating a common alarm indicator. The arrangement is shown in principle in Fig. 1. A circuit under test, 1, illustrated as a NOR gate, and a reference circuit 11, have their inputs 2, 3, commoned and their outputs C, C<SP>1</SP> connected to a comparator 14 consisting of inverters 13, 15, AND gates 16, 17 and a NOR gate 18. The output signal from the comparator is fed in parallel via inverters 8, 9, to a further NAND gate 19, one path including a short delay line 6, so that a "1" output is only produced by the NAND gate 19 if the comparator output signal f exceeds a minimum duration. The output signal from the NAND gate 19 is fed via a further NAND gate 21 to a bistable circuit 29, comprising cross-coupled NAND gates 23, 24 and an inverter 22, which, when set 'ON' energises a lamp 25. In the preferred embodiment, which is designed to test a circuit having a multiplicity of outputs, each pair of corresponding outputs from the circuit under test and the reference circuit are compared in a circuit such as 20, and their resulting output signals are effectively mixed by NAND gate 21, so that a disagreement signal from any comparator sets the bistable 'ON' and energises the lamp 25. The input and output signals of the circuit under test are also examined, each by a pair of threshold circuits such as 87, Fig. 5, to ensure that they lie outside a range determined by the largest voltage level that a 'O' can be, and the smallest level that a '1' can be. Each threshold circuit as shown comprises a differential amplifier one input of which is determined by a Zener stabilised reference voltage. If any voltage lies in the prohibited range a bistable 135 is set 'ON' to energise a lamp 128. The correct functioning of the warning lamps 125 and 128 may be verified by depression of buttons 30 and 130 respectively. The preferred embodiment is arranged as in Fig. 6, in which a multi-way connector 42, 43, can be clipped on to the circuit to be tested, the reference circuit 49, mounted on a suitable plug can be inserted into a socket 45, and the comparators are mounted in a box 44, only the warning lamps and test buttons being visible. Various modifications are described including an R-C integrating circuit and a thre shold circuit Figs. 3, 3a, 3b (not shown), which may be used, in place of delay line 6, &c, to determine when a comparator output is long enough (thereby preventing spurious operator by short transients), a tapped delay line Fig. 9 (not shown), for use in place of delay line 6, so that a tap appropriate to the circuit under test can be chosen, and a modified lamp testing circuit Fig. 1a, (not shown). The Specification also outlines Figs. 8 and 10 (not shown), various possible basic units, such as gates and inverters, which may constitute reference circuits, and various ways of connecting such circuits to the plug 48, Fig. 6.