Patent GB-1394894-A (GB)
Title: Synchronising unit for a time-division switching centre
Inventor: JACOB J
IPC: H04J3/12
Filed: 1972-06-30
Abstract: 1394894 Multiplex pulse code signalling SOC LANNIONNAISE D'ELECTRONIQUE and COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT ALCATEL 30 June 1972 [30 June 1971] 30702/72 Heading H4L A received multiplex signal has frame, speech channels and data signalling channels all synchronized by separate, independent but sequential processes. The multiframe Fig. 3A has 32 frames, each frame Fig. 2 has 32 time channels and each channel (I t 0 to I t 31 Figs. 6a, 6b, 6c, not shown) contains binary digits 1 to 8. The frames and multiframes are synchronized in a synchronizing unit 11, Fig. 1 (not shown) which generates (in 11) frame codes and multiframe codes to correspond with those contained in certain time channels of the received signal, and modifies these locally generated codes until they coincide in time with the received ones. Time channel I t 0 of every even frame contains the frame code; time channel I t 16 of the first frame TR0 of each multiframe Fig. 3a contains the multiframe code; time channel I t 16 of the remaining frames of each multiframe contains channel-by-channel signalling data (1-15, Figs. 3a, 3c) and further signalling data (16-31, Fig. 3a, 1-31, Fig. 3b). The Fig. 3a signal links a switching centre to a distant connection unit; Fig. 3b links two switching centres; Fig. 3c links a switching centre to a distant digital terminal. The synchronizing unit (11) and associated time connection network (18) are at the input to a time switching centre (20) which comprises a marker (20) which processes tests on new calls, using data supplied in the signalling channels; a local time base (23); and multirecorders (21A-21B) which process channel-by-channel data when connected to a concentrator. Inputs to the sync unit (11) are connection units (6, 7) for near and distant subscribers lines (12); junctors (8) for inter-exchange circuits (3); p.c.m. multiplex lines (10c for an electromechanical centre (4); and p.c.m. multiplex lines (10D) for a distant time centre 5. Frame and multiframe locking, Fig. 4.-The received time channels I t a 15, &c. Fig. 6A, are clocked into a register 101 by the distant clock W<SP>a</SP> and a decoder 103 provides the frame lock word at 104, and the multiframe lock word at 140. (a) Frame locking. Gates 106, 107 respectively indicate VTR, VTR if a frame lock word has been recognized, these gates being controlled by a "search" signal I to <SP>a</SP>W a8 <SP>a</SP> from a decoder 129 (at lower right). The VTR, VTR signals together with a further output of decoder 129, TRP (even frame), and with outputs PV i , ES i  of the last of three cascaded bi-stables 123, 124, 125 control logic gates 112-122 which in turn govern setting and resetting of the same bi-stables 123-5. Of the various combinations of the states of the three bi-stables, three represent a state of search (PV i  = 1); and three (ES i =1) represent synchronization of a counter 128 driven by the bi-stables and controlling the decoder 129. The bi-stables progress through the three states of search which represent the recognition of no, one, and two locking words until PV i  and ES i  change over and synchronization is established, the search signal I to /aW 8 /a ceasing. The other two states of synchronization represent loss of one and two locking words respectively. As soon as one word has been recognized during search, gate 127 blocks, and the ACT 1 changes. ACT 1 is used (top right) to ensure that loss of frame sync causes loss of multiframe sync. (b) Multiframe locking. Another counter and decoder 149, 151 responding to two cascade bi-stables 144, 145, have associated logic gates 142, 147 and inverters 141, 143. In response to the multiframe locking word at 140, and to outputs from the frame sync decoder 129, this circuit progresses through three conditions of sync, one loss of lock, and search. Speech channel synchronizing (Fig. 5a, not shown).-This is achieved by effectively reducing the last time channel I t <SP>1</SP>31 of the locally generated frame (Fig. 6a 4th line), and either reducing the ensuing first time channel I t <SP>1</SP>0 or lengthening it (Fig. 6B) according to whether the distant clock is fast or slow. The circuit basically consists of two stores (206, 207) respectively storing the first 15 time channels (1-15) and the last 15 (17-31), one being read while the other is receiving write-in, under the control of gates (208, 209, 230, 231). The circuit is controlled by a write address signal I ti  from 128, Fig. 4 (received at 214), and a read address counter (241); together with various ones of locally generated clock signals W 1 -W 8  corresponding to the binary digits 1-8 of the locally generated time channels I t 10-31. A register (236) reads out the stores (206, 207) alternately under control of A, B outputs of a bi-stable (252). Channel-by-channel multiplex synchronizing (Fig. 7, not shown).-The I t 16 time channels of Figs. 3A, 3C which contain channel-by-channel signalling and are received from a distant digital terminal are synchronized (in Fig. 7) by a circuit (280, Fig. 12, not shown) which passes data only when the 8 bits of the 16th time channel are the same in two successive multiframes. The data is transmitted by 284 (Fig. 10, not shown) to a multirecorder (286). Channel-bychannel data received (at 287) from a time switching centre is received in (285. Fig. 11, not shown) and transmitted by 281 (Fig. 13, not shown) to a distant connection unit (278). Satellite "signalling data" synchronizing (Fig. 8, not shown).-The signalling data time channels of frames 16-31, Fig. 3A, and all frames Fig. 3B are received from a distant connection unit at 289 (Fig. 9B, not shown) in a register (61), and transferred to an active store (71). An order memory (78) selectively passes signalling data (from 71) to the control logic element (279, Fig. 8, not shown). A transmitter (289, Fig. 14, not shown) passes the received signalling data to a multiplex synchronizing module (not shown). Signalling data from the control logic unit (279) is transmitted to a distant connection unit (by 290+Fig. 9A) in which alternately a static memory (39) transmits orders, and an active memory (34) receives data, as controlled by an order signal (35).