Patent GB-1451673-A (GB)
Title: Memory systems
IPC: G11C11/4091
Filed: 1974-05-15
Abstract: 1451673 Data storage systems TELETYPE CORP 15 May 1974 [17 May 1973] 21431/74 Heading G4C [Also in Division H3] A storage system includes a refreshing circuit and a memory cell containing a capacitor whose potential indicates the stored bit state. The refreshing circuit has two terminals respectively connected to first and second equal capacitors (which may be the distributed capacity of conductors connected to the terminals). The memory capacitor is connectable in parallel with the first capacitor. In response to a clockpulse train the circuit applies ground potential and a potential -V alternately to both terminals. When it applies -V to the parallel combination of the memory and first capacitors the first capacitor is charged towards -V at a rate slower or faster than that of the second capacitor, dependent upon the stored bit state. The circuit restores the potential on the memory capacitor to its initial bit state in accordance with the differential charging rate. The embodiment disclosed comprises a matrix array of memory cells, a cell being addressed by applying -V to an appropriate X and Y conductor. Each row of cells is centrally divided by a refreshing circuit whose terminals are connected to respective halves of the X conductor Fig. 1 (not shown). For example, Fig. 3 shows four cells 12 associated with a row conductor X1 and refreshing circuit 16'. The clockpulses are applied at 19 and first cause distributed capacitors 33, 34 to discharge to ground. Subsequently a memory capacitor e.g. 42 is selected by energizing column conductor Y2 and placed in parallel with capacitor 34. All other cells in this column will also be selected When circuit 16' applies -V to its terminals 1, 2 capacitor 34 charges at a greater rate than capacitor 33 if memory capacitor 42 has a potential about -V (representing a 0-bit) or at a lesser rate if 42 is at ground potential (representing a 1-bit). Accordingly transistor 66 or transistor 67, respectively, in the circuit 16' is turned on when its threshold is reached and hence transistor 67 or 66 is turned off so that capacitors 42 and 34 will continue to charge to -V or will discharge to ground, respectively, thus being refreshed. Refreshing of other cells in the selected column occurs similarly and simultaneously. Refreshing takes place similarly for any other selected column, but for cells to the right of the refreshing circuit 16' the bit state represented by the memory capacitor potential is the inverse of that for cells to the left, i.e. ground potential represents a 0-bit. During read-out the potential appearing on capacitor 33 of the selected row conductor represents the bit state of the cell selected by the Y conductor. During write-in -V is applied to the X conductor if the bit to be stored is a 1-bit, and ground if a 0-bit. Irrespective of the present potential on the selected cell capacitor the charging rate of the capacitors 33, 34 will differ in such a sense that the appropriate potential is impressed on the memory capacitor, i.e. -V to represent a 0-bit if the cell is to the left of circuit 16' and to represent a 1-bit if the cell is to the right, or ground to represent a 1-bit to the left and a 0-bit to the right.