Patent GB-742869-A (GB)
Title: Impulse-circulation electronic calculator
IPC: G06F3/08
Filed: 1952-10-03
Abstract: 742,869. Digital electric calculating-apparatus. COMPAGNIE DES MACHINES BULL. Oct. 3, 1952 [Oct. 4, 1951], No. 24852/52. Class 106 (1). A cyclically operating computer, performing multiplication or division by the repeating method, comprises three serial circulating pulse memories M1, M2, M3, consisting of electric delay lines, a serial adder-subtractor D with two inputs which receive pulses, coded in fourdigit notation, from memories M2 and M3, and with an output connected to memory M2, a comparator E connected at least to one of the memories and adapted to compare a digit therefrom with another digit of the same denomination, step-selecting means controlling the mutual connections of the memories, addersubtractor and comparator during each arithmetical step, and manually-operable means for setting the apparatus to perform either multiplication or division, the formation of each partial result in memory M2 coinciding with the elimination of a number previously lodged therein, and the act of stepping on to the next operation being initiated by a signal to the comparator to the step-selecting means after one or several digit comparisons. In the described embodiment each memory comprises five decimal-digit compartments, and electronic switching gates between various compartments provide for transferring sections of data from normal circulation in a memory loop to other units in order to perform the required arithmetic operations. Each decimal compartment can accommodate up to four binary digits representing 1, 2, 4 and 8, respectively. The memory loops are built up from delay units and regenerators of the type described in Specification 711,240, [Group XXXIX]. Data may be introduced from record cards or from the setting of totalizer wheels. The operation of the machine is described by an example of division: 1,057,012 ¸951=1111 (remainder 451). The dividend is entered into memory loops M1, and M2 and the divisor into M3; the quotient is built up in M1 as the contracting divided passes into M2. The points of introduction of the impulses representing the data into the memories are situated at the left-hand end of each loop. The four digits of the first group 7012 of the dividend are passed successively into the memory loop M1, commencing with the digit 2 and finishing with the digit 7, and then the memory M2 receives successively the three digits of the second group 105, commencing with the digit 5. The memory M3 successively receives the three digits of the divisor 951, commencing with the digit 1. The directions of circulation in the loops are indicated by arrows. The comparator, which is of the type described in Specification 730,297, determines whether the divisor is greater or less than the aligned digits of the dividend. It receives during one complete passage through the loop the impulses representing the divisor 0951 and the corresponding second group 0105 of the dividend, and emits an impulse through its output end E2 as soon as it has compared these two numbers, because the group 0105 is lower than the divisor. This impulse is emitted when the digits occupy the positions indicated in diagram I, and actuates means which modify the connections to those shown in diagram II, in the course of which the digit 7 passes from loop MI into loop M2. The same impulse is set into circulation in a shift counting device G the object of which is to stop the division when the four quotient digits have been formed, that is to say, when the first group of the dividend has been transferred from the memory Ml into the memory M2. After re-arrangement in accordance with diagram III, the arithmetic unit D, which comprises two binary adder/ subtractors of the type described in Specification 717,869, performs a subtraction, and a quotient digit " 1 " is lodged in the memory loop M1. The comparator now finds that the difference 0106-951 is negative and initiates another shifting operation. Operations continue in this manner until the shift counting device detects passage of the lowest digit of the dividend from memory M1 to M2, the end of the division being brought about by the impulse emitted by the comparator E when the remainder becomes lower than the divisor. The performance of multiplication by the computer is also described.