baber/WOPTO huggingface dataset:
Patent TW-409485-B (TW)
Title: The circuit apparatus of the halogen lamp used by semiconductor machine
Inventor: RAU RUEI-JIUN
IPC: H01L21/00
Filed: 1999-01-26
Granted: 2000-10-21
Abstract: A circuit apparatus which prolongs the life of the halogen lamp by controlling voltage. Said circuit apparatus comprises mainly the wafer carrier of the semiconductor after develop inspection (ADI) as the start switch of said circuit apparatus, a micro-switch apparatus, and a halogen lamp. When the wafer carrier is ready for testing the wafer, start said apparatus to provide sufficient voltage. The micro-switch apparatus is triggered by the motion of the wafer carrier. A sufficient voltage is supplied from the power supply to the lamp for maintaining a suitable brightness during the operation, and the supplied voltage is weakened under the standby status, the brightness of the lamp is also weakened to prolong the life of said lamp.
Patent TW-I233432-B (TW)
Title: Method of making transparent glass-ceramics with high temperature dimensional stability
Inventor: LAPP JOSEF CHAUNCEY
IPC: C03C10/06
Filed: 1999-02-25
Granted: 2005-06-01
Abstract: A glass-ceramic material which exhibits extremely low (e.g. less than 100 ppm) shrinkage, when exposed to 900 DEG C for 6 hours, and methods for making such glass-ceramics. The glass-ceramic is cerammed at a sufficiently high temperature and then cooling in a controlled manner, preferably to below the strain point of the resultant material. Using this technique, glass-ceramic materials were fabricated which exhibited dimensional shrinkage comparable to and in some cases even less than that achieved by fused silica substrates, when exposed to high temperature poly-Si processing temperature (e.g. 900 DEG C for 6 hours).
Patent TW-582040-B (TW)
Title: Embedded type memory self-tester
Inventor: WU CHENG-WEN
IPC: G11C29/00
Filed: 1999-03-05
Granted: 2004-04-01
Abstract: An embedded type memory self-tester is disclosed, which is an integrated circuit structure embedded in the memory chip, and obtained by the same processing way as that of the memory. It can perform various ways of test to various types of memories in accordance with various control commands and detection ways under the same speed as the operation speed of memory, so that the memory operation is more efficient.
Patent TW-454071-B (TW)
Title: Differential gear
Inventor: MIMURA KENJI
IPC: F16H48/38
Filed: 1999-06-09
Granted: 2001-09-11
Abstract: A differential gear which can always obtain a stable differential limiting force even in low-speed rotation. A plurality of rollers are provided between a raceway surface integrally rotating with an input-side rotating body and a raceway surface integrally rotating with an output-side rotating body. A tilt angle of the axes of rolling of the rollers with respect to the axis of rotation of the raceway surfaces is made smaller than 20 DEC, and a tilt angle of the axes of rolling of the rollers with respect to a plane including the axis of rotation of the raceway surfaces is made larger than 25 DEG and smaller than 90 DEG. Thereby, a stable frictional force can be produced between the rollers and the raceway surfaces, and a differential limiting force without producing a stick-slip even in low-speed rotation can be obtained.
Patent TW-428217-B (TW)
Title: Method for fabricating a non-volatile memory cell
Inventor: SHIU SUNG-MU
IPC: H01L21/8247
Filed: 1999-09-08
Granted: 2001-04-01
Abstract: A method for fabricating non-volatile memory cells for a substrate includes the following steps: forming an isolation structure to define an active region on the substrate; forming a channel oxide layer on the active region; sequentially forming a conducting layer and a silicon nitride layer on the channel oxide layer and the isolation structure; defining the polysilicon layer and the silicon nitride layer to form a floating gate on the active region and to form an opening exposing a portion of the isolation structure; conformally forming an etching protection layer which extends from the isolation structure inside the opening up to the silicon nitride layer; comprehensively forming an oxide layer to fill up the opening; planarizing the oxide layer until reaching the surface of the silicon nitride layer so that the remainder of the oxide layer is left within the opening; removing the silicon nitride layer; forming conducting spacers on the sidewalls of the remainder of the oxide layer and on the conducting layer; removing the remainder of the oxide layer; conformally forming an isolation layer; forming another conducting layer on the isolation layer for being used as a control gate; and forming source/drain regions.
Patent TW-406155-B (TW)
Title: Structure supporting apparatus
Inventor: NISHI YOSHIO
IPC: B66F19/00
Filed: 1999-09-18
Granted: 2000-09-21
Abstract: The present invention provides a structure supporting apparatus which can simply and accurately lift the upper structure to the right position corresponding to the lower structure not necessary to equip a stopper, capable of being directly used as a supporting member under such condition to achieve the object of improving the operation. The composition is to move relatively the upper compressed member with the lower compressed member in overlapping condition to vary the thickness of the upper compressed member and the lower compressed member in the overlapping direction. The driving device for moving the said lower compressed member is composed of the reducing gear mechanism, also acting as intermediate gear element, transmitting the input power from the driving shaft to the screw.
Patent TW-448356-B (TW)
Title: Signal processing apparatus
Inventor: UEDA YASUSHI
IPC: G06F11/36
Filed: 1999-10-19
Granted: 2001-08-01
Abstract: The invention relates to a signal processing apparatus comprising plural memories in an LSI and plural memory access blocks for accessing these memories, in which the cause can be analyzed easily in the event of a fault. The signal processing apparatus 100 comprises a first arbitration block 150 for arbitrating the access right of a third memory access block 130 to a first built-in memory 160, a second arbitration block 180 for arbitrating to store the memory access history of the third memory access block 130 in a second built-in memory 190 which is not the same memory as the first built-in memory 160 executing the access of the third memory access block 130, and a trace control block 170 for controlling.
Patent TW-419774-B (TW)
Title: Positional allignment method for transport system
Inventor: NISHINAKAYAMA YASUHIKO
IPC: H01L21/68
Filed: 1999-10-26
Granted: 2001-01-21
Abstract: This invention is directed to a transport position alignment method for a transport system for performing positional alignment of a retaining portion 48 with respect to a reference position. Respective temporary position coordinates corresponding to a determined position on a rotary reference table 60, i.e., orient teaching reference position, and a determined position of a cassette type container supported on a container supporting table, i.e., container teaching reference position, are inputted into a control portion 72 in advance. Under the control of temporary position coordinates according to the orient teaching reference position, an object W to be transported, which is retained by the retaining portion 48 in a correctly aligned position, is transported to the rotary reference table 60 for transfer. A position posture detecting portion 62 is utilized to detect the amount and direction of the eccentricity of the object W to be transported on the rotary reference table 60. According to the detected eccentricity amount and direction, the temporary position coordinates corresponding to the orient reference position are corrected as appropriate position coordinates. Further, under the control of temporary position coordinates of the container teaching reference position, the object W to be transported, which has been correctly aligned with the container teaching reference position, is transported to the rotary reference table for transfer. The position posture detecting portion 62 is utilized to detect the amount and direction of the eccentricity of the object W to be transported on the rotary reference table 60. According to the detected eccentricity amount and direction, the temporary position coordinates corresponding to the container teaching reference position are corrected as appropriate position coordinates.
Patent TW-592011-B (TW)
Title: Post-treatment for copper on printed circuit boards
Inventor: MCGRATH PETER T
IPC: H05K3/22
Filed: 1999-11-29
Granted: 2004-06-11
Abstract: A post-treatment method for copper on printed circuit boards is disclosed. The method comprises forming a cupric-based organometallic conversion coating on a copper surface of a printed circuit board, and then converting the cupric-based organometallic conversion coating to a cuprous-based organometallic conversion coating. The resulting cuprous-based organometallic conversion coating is desirable in that it improves copper to dielectric bond integrity.
Patent TW-525293-B (TW)
Title: Method to fabricate a wavy deep trench
Inventor: LEE SZETSEN STEVEN
IPC: H01L27/108
Filed: 1999-12-06
Granted: 2003-03-21
Abstract: The present invention provides a wavy deep trench and the method to fabricate the same. The wavy deep trench of the present invention is disposed on the surface of a substrate, which comprises a bottom edge and a sidewall, the sidewall is between the bottom edge and the substrate surface. The sidewall comprises a first sidewall with positive slope and a second sidewall with negative slope, the first sidewall and the second sidewall appears on the sidewall alternatively.
Patent TW-445565-B (TW)
Title: Connectors for an electrostatic chuck and combination thereof
Inventor: SHAMOUILIAN SHAMOUIL
IPC: H01R13/05
Filed: 1999-12-09
Granted: 2001-07-11
Abstract: A semiconductor wafer chuck for retaining a semiconductor wafer during semiconductor wafer processing in a semiconductor wafer processing system including a connector connecting DC chucking voltage and RF biasing power to an electrode embedded in the body of the chuck. The connector for the chuck includes two or more members joined by resilient banana connections. The connector may be adapted for use as a high temperature connector for an electrostatic chuck operated at an elevated temperature and such connector includes a thermal impedance for reducing the heat transferred from the chuck to the bottom of the connector.
Patent TW-434796-B (TW)
Title: Method for forming shallow trench structure on the semiconductor substrate
Inventor: TSAI YOU-SUNG
IPC: H01L21/76
Filed: 2000-02-18
Granted: 2001-05-16
Abstract: A method for forming shallow trench structure on the semiconductor substrate is hereby disclosed, which comprises: first, forming a silicon-oxy-nitride layer on the semiconductor substrate, and forming silicon nitride layer on the silicon-oxy-nitride layer; using the etching agent which contains carbon fluoride (CxFy) to etch the semiconductor substrate in-situ, whereby an opening pattern is formed on the silicon nitride layer and silicon-oxy-nitride layer, and some portion of the upper surface of the semiconductor substrate is exposed; and using the silicon nitride layer and silicon-oxy-nitride layer as the hard mask in the in-situ etching process to form a shallow trench structure on the exposed portion of semiconductor substrate.
Patent TW-462938-B (TW)
Title: Flexible storage bag
Inventor: CERONE DANIEL RAYMOND
IPC: B65D33/18
Filed: 2000-05-20
Granted: 2001-11-11
Abstract: The present invention provides a flexible storage bag having an opening and a closure system for the opening, wherein the closure system provides a high contrast color indication when complete closure of the closure system has been achieved. The closure system may be a mechanical interlocking seal or an adhesive-based closure system. The high contrast color indication may be a change from colorless to colored, from white to black, and/or from translucent to opaque.
Patent TW-516962-B (TW)
Title: A human TNFR1-IgG1 preparation
Inventor: ETCHEVERRY TINA
IPC: C07K16/18
Filed: 1996-06-05
Granted: 2003-01-11
Abstract: The present invention relates to novel process for the preparation of glycoproteins by mammalian cell culture wherein the sialic acid content of the glycoprotein produced is controlled over a broad range of values by manipulating the cell culture environment. The invention provides for processes in which the sialic acid content of the glycoprotein is modified by changes in cell culture parameters which affect cell specific productivity. Preferred embodiments of the invention include cell culture processes in the osmolality of the cell culture is controlled as well as the concentration of a transcription enhancer during the production phase of the cell culture. The invention further provides for novel preparations of soluble type 1 tumor necrosis factor immunoglobulin G1 and their uses in the treatment of inflammatory or immune related disorders.
Patent TW-495878-B (TW)
Title: Semiconductor device
Inventor: TANIGUCHI YASUHIRO
IPC: H01L29/10
Filed: 2000-06-19
Granted: 2002-07-21
Abstract: This semiconductor device on the first conductive type semiconductor layer comprises: gate insulation film, gate electrode, first conductive type channel, second conductive type buried layer, first conductive type halo layer and second conductive type source and regions of a field effect transistor (FET). Above-mentioned each buried layer and halo layer uses the source region as emitting region. The halo layer beside the source region is the base region. When depletion or second conductive type conversion happen on the FET and the Vbe is the activation voltage difference between base and emitter of the parasitic bipolar transistor that is composed by connecting the halo layer beside the drain region, the buried layer and drain region: The feature is the doping concentration that lets the FET be ""OFF"" condition while parasitic bipolar is ""OFF"" (lower than Vbe), and the FET be ""ON"" condition while the parasitic bipolar is ""ON"" (higher than Vbe).
Patent TW-501086-B (TW)
Title: Liquid crystal display panel signal processor
Inventor: YANG JEFFREY
IPC: G02F1/133
Filed: 2000-07-15
Granted: 2002-09-01
Abstract: A liquid crystal display (LCD) panel signal processor is disclosed in the present invention. The invention is suitable for use in a LCD panel that has gate drivers and source drivers. The invention includes the followings: an input interface for receiving plural kinds of image signals; and a micro-processing apparatus, which outputs the first control signal to control the input interface to select the first kind of image signal from the image signal stated above, converts the first kind of image signal into a digital image signal having the output format, and sends a notification signal to inform a panel controller about the output format. The panel controller receives digital image signals based on the output format, and generates the gate driver signal and the source driver signal, which are then output to the gate driver and the source driver, respectively.
Patent TW-473852-B (TW)
Title: A single-operation method of cleaning semiconductors after final polishing
Inventor: YALAMANCHILI M RAO
IPC: H01L21/306
Filed: 2000-10-12
Granted: 2002-01-21
Abstract: A process for cleaning a final polished semiconductor wafer in a single operation (i.e., following final polishing, a process or action is directed at the wafer which includes drying the wafer only once, thereby yielding a polished wafer surface substantially free of contaminants). The process comprising contacting the polished wafer with an aqueous solution comprising an oxidizing agent to oxidize organic carbon on the surface of the polished wafer. After oxidizing the organic carbon, immersing the polished wafer in an megasonically agitated alkaline cleaning solution to reduce the surface concentration of contaminant particles exceeding 0.2 μm in diameter. Withdrawing the polished wafer from the alkaline cleaning solution and rinsing it with deionized water. After rinsing, immersing the polished wafer in an acidic cleaning solution to reduce the surface concentration of contaminant metal atoms. Withdrawing the polished wafer from the acidic cleaning solution and immersing it in an ozonated aqueous bath. Withdrawing the polished wafer from the aqueous bath and drying the wafer. The process is further characterized by the absence of a step in which the surface of the polished wafer is dried between oxidizing organic carbon on the surface and immersing the wafer in the ozonated aqueous bath.
Patent TW-468096-B (TW)
Title: Case for an instrument of small volume including a manually removable back cover
Inventor: RUFFIEUX PATRICK
IPC: H05K5/03
Filed: 2000-10-30
Granted: 2001-12-11
Abstract: The watch case includes a middle part (2) and a removable back cover (3). The back cover (3) is held under the middle part by means of at least one rail (5), this rail having a first portion (7) arranged to be slid into a groove (9) made in the middle part (2) and a second portion (11) arranged to cap an edge (13) of the back cover (3). Without using tools, the user can remove the rail, take off the back cover and change the battery or batteries powering the movement.
Patent TW-523434-B (TW)
Title: Method and device for the production of light-metal pellets
Inventor: BOEHNKE CHRISTIAN
IPC: B22D11/126
Filed: 2000-11-24
Granted: 2003-03-11
Abstract: The invention relates to a method for the production of light-metal pellets, in which a light-metal melt is introduced into a gap between two cooling bodies and in which the light-metal melt is divided into pellets of pre-determined size, before complete solidification thereof, either by means of weakened lines or complete separation. According to the invention, a device is disclosed for carrying out the method, in which the cooling bodies comprise troughs on the surfaces thereof which face each other, of such a kind that the light-metal melt situated between the two cooling bodies may be formed into pellets in the shape defined by said troughs.
Patent TW-490716-B (TW)
Title: Apparatus, method and product therefrom, for aligning die to interconnect metal on flex substrate
Inventor: SAIA RICHARD JOSEPH
IPC: H05K3/00
Filed: 2000-12-11
Granted: 2002-06-11
Abstract: A method and process sequence for accurately aligning (14) die (108) to interconnect metal (112) on flex substrate (100) such as polyimide flex is described. A mask (102) for via formation is first patterned (12) in a metal layer on the bottom surface of the flex substrate (100). Die attach means (104) such as die attach adhesive is then applied (13) to the top side of flex substrate (100). The bond pads (106) on die are locally, adaptively aligned (14) to the patterned metal via mask (102) on the flex (100) with high accuracy. Vias (110) down to the die bond pads (106) are then created (15) by either plasma etching or excimer laser ablation through the existing aligned metal mask (102) on the flex substrate (100), and interconnect metal (112) is then deposited (16), patterned and etched (17). As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using ""adaptive lithography"". Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost. The method is compatible with the projected designs of the next generation die which will have bond pads on the order of 40um in size.
Patent TW-587275-B (TW)
Title: Exposure method and exposure apparatus
Inventor: NISHI KENJI
IPC: G03F7/20
Filed: 2000-12-20
Granted: 2004-05-11
Abstract: In the invented exposure method and exposure apparatus, the effect of vibration is not transmitted to each other when using two movable stages. On both sides of the Y-direction of the wafer base (13), the X-axis sliding members (19A, 20A) are disposed to move freely in the X-direction. On the X-axis sliding members (19A, 20A), Y-axis sliding member (16A) is disposed to move freely in the Y-direction. Along the Y-axis sliding member (16A), the first wafer stage (WST1) is disposed to move freely in the Y-direction (scanning direction). The second Y-axis member (16B) is disposed in parallel to the X-axis sliding members (19B, 20B); and the second wafer stage (WST2) is disposed to move freely along the Y-axis sliding member (16B). When conducting exposure on the first wafer stage (WST1), wafer exchange or wafer calibration is performed on the second wafer stage (WST2).
Patent TW-459096-B (TW)
Title: Fire-proof suspended door device and installation structure of vertical strip set in the opening of storage space of door
Inventor: MUKAIDE YOSHIHIDE
IPC: A62C2/06
Filed: 2000-12-22
Granted: 2001-10-11
Abstract: This invention aims to provide a door storage space by using building wall. There is a door bottom member, settled at the suspended door bottom, designated to fit into the vertical stop strip, which is set at the opening of the door storage space, when the suspended door closes to prevent any fire expanding. The vertical strip will not be an obstacle when the suspended door is suspended on the upper guiding rail. The main solution of this invention is to install the vertical strip 4 at the door storage space opening by screwing bolts, and to remove the vertical strip 4 temporarily while doing the door suspending on the upper guiding rail.
Patent TW-584917-B (TW)
Title: Method of forming interconnect
Inventor: HATTORI TSUKASA
IPC: H01L23/522
Filed: 2000-12-27
Granted: 2004-04-21
Abstract: An interconnect forming method includes the steps of: (a) forming a through hole in an insulating film over a substrate; (b) depositing a photosensitive masking material over the insulating film as well as inside the hole; (c) patterning the material, thereby forming a mask pattern, which has an opening located over the hole and is used to define a trench; (d) etching the insulating film to a predetermined depth using the mask pattern, thereby defining a trench pattern, linked to the hole, in an upper part of the insulating film; (e) filling in the hole and the trench pattern with a conductive material; and (f) before the trench pattern is defined, defining the mask pattern so that no remaining part of the material, which has been filled in the hole, will reach a level higher than the bottom of the trench pattern.
Patent TW-554610-B (TW)
Title: Electronic volume circuit
Inventor: NORO MASAO
IPC: H03G3/12
Filed: 2001-02-01
Granted: 2003-09-21
Abstract: An electronic volume circuit is provided, which can be driven by a single power source and can therefore be formed by an LSI that can be fabricated in a simple manner using an oxide film and a junction process for a single power source. A first amplifying circuit attenuates the amplitude of a bipolar input signal and converts the attenuated input signal to a unipolar signal, and a variable resistor device controls the degree of attenuation of the first amplifying circuit based on an externally supplied signal.