Patent EP-3739624-A1 (EP)
Title: Semiconductor arrangement with a compressible contact element encapsulated between two carriers and corresponding manufacturing method
Inventor: FÜRGUT EDWARD
IPC: H01L23/538
Filed: 2019-05-13
Abstract: A semiconductor arrangement and a method for forming a semiconductor arrangement are disclosed. The semiconductor arrangement includes: a first arrangement (1A) and a second arrangement (1B) each comprising a first surface (11A, 11B), a second surface (12A, 12B), and an electrode (21A, 21B) formed on the first surface (11A, 11B), wherein the first arrangement (1A) and the second arrangement (1B) are spaced apart from each other in a first direction (x) and arranged such that the first surface (11A) of the first arrangement (1A) faces the first surface (11B) of the second arrangement (1B), and wherein at least one of the first arrangement (1A) and the second arrangement (1B) comprises a semiconductor body (103A, 103B); a connector (3) electrically connecting the electrode (21A) of the first arrangement (1A) and the electrode (21B) of the second arrangement (1B), wherein the connector (3) is compressible in the first direction (x); and an encapsulant (4) filling a space between the first arrangement (1A) and the second arrangement (1B) and embedding the connector (3). The connector (3) may include a base section (30), one or more first legs (31A) extending from the base section (30) towards the electrode (21A) of the first arrangement (1A) and one or more second legs (31B) extending from the base section (30) towards the electrode (21B) of the second arrangement (1B). A pressure contact may be formed between the connector (3) and the electrode (21A, 21B) of at least one of the first arrangement (1A) and the second arrangement (1B) or alternatively the connector (3) may be fixed (e.g. soldered or welded) at the electrode (21A, 21B) of at least one of the first arrangement (1A) and the second arrangement (1B) by an electrically conducting compound. The encapsulant (4) may be a mold compound. The second surface (12A, 12B) of each of the first arrangement (1A) and the second arrangement (1B) may be at least partially not covered by the encapsulant (4) to allow for efficient cooling of the first and second arrangement (1A, 1B). A contact pin (104A, 104B) may protrude from the encapsulant (4), wherein the connector (3) is electrically connected to the contact pin (104A, 104B). The connector (3) may comprise a terminal section (33) that protrudes from the encapsulant (4). One semiconductor arrangement may include a plurality of connectors (3), wherein the connectors (3) may be arranged such that terminal sections (33.1-33.3) of several connectors protrude from the encapsulant (4) on one side, wherein these terminal sections (33.1-33.3) are arranged next to each other in a lateral direction along the one side and two (or more) terminal sections (33.1-33.6) may be arranged next to each other in the vertical direction (x), wherein the terminal sections that are arranged next to each other in the vertical direction may be aligned relative to each other or offset in the lateral direction. At least one of the first arrangement (1A) and the second arrangement (1B) may comprise a carrier (101A, 101B) forming the second surface (12A, 12B) and a semiconductor body (103A, 103B) arranged on the carrier (101A, 101B), wherein a surface of the semiconductor body (103A, 103B) facing away from the carrier (101A, 101B) forms the first surface (11A, 11B). T he carrier (101A, 101B) may be part of a leadframe. The carriers (101A, 101B) may each include a respective leg (102A, 102B) that adjoin each other and are therefore electrically connected, wherein both legs (102A, 102B) may protrude from the encapsulant or one of the legs (102A, 102B) is cut off and ends inside the encapsulant (4) where it is connected to the other one of the legs (102A, 102B), wherein the other one of the legs (102A, 102B) protrudes from the encapsulant (4). The carrier (101A, 101B) may also be a substrate (110A) comprising: an insulating carrier (111A, 111B), a first metallization (112A, 112B) formed on a first surface of the insulating carrier (111A, 111B) and a second metallization (113A, 113B) formed on a second surface of the insulating carrier (111A, 111B), wherein the second metallization (113A, 113B) forms the second surface (12A, 12B) of the respective arrangement (1A, 1B), and wherein the semiconductor body (103A, 103B) is formed on the first metallization (112A, 112B). The method for forming the semiconductor arrangement may comprise: placing the semiconductor arrangement in a first section (51) of a mold (50), closing the mold (5) by placing a second section (53) of the mold (50) on top of the first section (51); and filling a space (53) inside the mold (50) by the encapsulant (4), wherein closing the mold (50) comprises compressing the connector (3) arranged between the electrode (21A) of the first arrangement (1A) and the electrode (21B) of the second arrangement (1B) in the first direction (x).