baber/WOPTO huggingface dataset:
Patent JP-S5792168-A (JP)
Title: Manufacture of al alloy with superior brightness and strength
Inventor: INABA TAKASHI
IPC: C22C21/06
Filed: 1980-11-28
Abstract: PURPOSE: To manufacture an Al alloy with superior brightness and strength while using Al of ordinary purity by adding Si and Fe to Al besides Mg and Cu and carrying out heat treatment under specified conditions.  
     CONSTITUTION: An Al alloy contg. 0.05W0.5% Cu, 0.1W0.5% Mg, 0.01W0.4% Si and ≤0.6% Fe is heat-treated by heating at ≥100°C/min heating rate, holding at ≤450°C for ≤10min, and cooling at ≤100°C/hr cooling rate. Si reduces a drawing edge and reduces an edge in 45° direction increased by adding Fe, yet >0.4% Si makes the Al alloy easy to color by anodic oxidation and deteriorates the formability. <0.01% Si loses its effect. Fe provides strength, yet >0.6% Fe produces crystallizd and precipitated substances in large quantitites, so the brightness is lost. The addition of Fe enables the use of Al of ordinary purity. Since the heat treatment is carried out at such a high temp. for such a short time, a previously produced precipitate is partially resolubilized, and no precipitation is caused at each temp. up to the arrival temp., resulting in superior brightness. In addition, the grains are not grown and are made fine to increase the strength furthermore. 
     COPYRIGHT: (C)1982,JPO&Japio
Patent JP-S6251098-A (JP)
Title: Dynamic type semiconductor memory device
Inventor: OGURA ISAO
IPC: G11C11/409
Filed: 1986-07-18
Abstract: PURPOSE:To omit a dummy cell and its clock system and simplify a circuit constitution by making lower a precharge potential of a digit line than a high level potential applied to the digit line and higher than a low level potential. CONSTITUTION:Electric potentials of digit lines A, B sensed by a sense amplifier 50 are fed back, boosted to the digit lines A, B of '1' to enhanced the electric potential of the digit line. This high voltage may be about 1.8 times a power source voltage VDD externally applied. A circuit 53 decoding a word line 60 can be constituted by an ordinary address decoder circuit. A clock phiD is a boosting clock, connected to the word line 60 through a decode transistor 71 and '1' level of the word line is made about 1.8 times the power source voltage VDD. A circuit forming the clock phiD is a boosting clock generating circuit 52.
Patent JP-S6325978-A (JP)
Title: Semiconductor integrated circuit device
Inventor: KOMORI KAZUHIRO
IPC: H01L21/8247
Filed: 1986-07-18
Abstract: PURPOSE:To make it possible to improve the integration density and the electric reliability of an EEPROM, by forming the floating electrode and the control gate electrode of a field effect transistor for information memory and the gate electrode and the word line of a switching field effect transistor by overlapping and cutting. CONSTITUTION:A floating gate electrode 6A and a control gate electrode 8A provided thereon in a field effect transistor Qm for information memory are formed by overlapping and cutting. A word line 8B, which is formed with the same conductor layer for the control gate electrode 8A, is formed on a gate electrode 6B of a switching field effect transistor Qs. The gate electrode 6B of the switching field effect transistor Qs is formed with the same conductor layer for said floating gate electrode 6A by overlapping with said word line 8B and by cutting both parts. Thus the size of mask aligning allowance in manufacturing processes is reduced. The integration density is improved. The etching conditions are made approximately uniform. Deterioration in dielectric strength of the gate insulating film and the like are reduced, and the electric reliability can be improved.
Patent JP-S6411367-A (JP)
Title: Gate turn-off thyristor
Inventor: SHIRAISHI TAKASHI
IPC: H01L29/745
Filed: 1987-07-06
Abstract: PURPOSE:To improve a turn-off gain, to particularly improve an anode current in an N-type base layer at the time or turning OFF, i.e., the exhausting efficiency of a tail current, and to improve switching characteristic by providing a lattice-like P-type buried layer in an N-type base layer, applying a negative reverse bias to a gate electrode at the time of turning OFF, and simultaneously applying a negative bias also to the P-type buried layer. CONSTITUTION:A lattice-like P-type buried layer 27 substantially parallel to the main face of a substrate is formed in an N-type base layer 21. A negative gate turn OFF voltage VRG to a cathode electrode 31 is applied to a gate electrode 32. Since a negative bias VRG is also applied to the layer 27 at this time, a depletion layer 37 formed in a junction with the layer 21 increases fts spread, the mobility of carrier is interrupted by forming the barrier of a high resistance layer, and remaining carrier exhausting efficiency from the gate electrode is remarkably improved. Since an anode current, i.e., a tail current flowing in the layer 21 is interrupted on the way by the layer 37, the exhausting efficiency of the tail current is improved, a junction between a gate P-type base layer 22 and the layer 21 is reversely biased to be turned OFF.
Patent JP-S6325737-A (JP)
Title: Generating circuit for error correction code
Inventor: KADOKAWA YUICHI
IPC: G06F11/10
Filed: 1986-07-18
Abstract: PURPOSE:To simplify the constitution of a generating circuit for error correction codes by adding medium values between data words and error correction codes to store them in a register and calculating the error correction codes based on the output of the register and position data on the correction series of the data words. CONSTITUTION:The recording data RD and the output of an alpha multiplication table 14 are supplied to an adder 11 which defines 2 as a divisor. The result of addition is stored in a P or Q parity register 12 or 13 and the output of this register is applied to the table 14. Furthermore the table 14 contains the word position data DP in the correction series of the data RD as well as a selection signal PQ which shows a parity word P or Q that is calculated in the processing cycle of the data DP. The signal PQ is applied directly to the register 13 as well as the register 12 via an inverter 15 respectively. Then the words P and Q are calculated at L and H levels of the signal PQ respectively.
Patent JP-S5980944-A (JP)
Title: Forming method of multilayer film
Inventor: NITSUTA TAKEHISA
IPC: H01L21/3213
Filed: 1983-09-14
Abstract: PURPOSE:To prevent the disconnection of a multilayer wiring layer and the defective insulation of an insulating layer while improving the degree of integration of the multilayer wiring layer by interposing a layer etched by only an etching method of a different kind between an upper layer and a lower layer and selectively etching only the upper layer. CONSTITUTION:A passivation SiO2 layer 7 is etched selectively and a contact is formed, Al is evaporated, and a first Al wiring layer 8 is formed through selective etching. An inter-layer insulating SiO2 layer 10 is formed to the upper surface of an Si3N4 insulating layer 9, and a through-hole 11 is formed on an Al wiring layer 8 on a buried-layer electrode extracting region 6 through fluoric acid group selective etching. The passivation SiO2 layer is not etched by the stopper action of the Si3N4 insulating layer 9 at that time. The Si3N4 insulating layer 9 is etched selectively through a plasma etching method, and a deep through-hole 11 is formed at the same position. When an Al layer 13 is etched selectively by a phosphoric acid group and a second Al wiring layer 13a connected to the first Al wiring layer 8 is formed, a W/Ti layer 12 performs stopper action.
Patent JP-S5959315-A (JP)
Title: Timing gear cutting method
Inventor: OGUMA TOMIO
IPC: B23F15/00
Filed: 1982-09-29
Abstract: PURPOSE:To shorten the gear cutting and key groove machining process and stabilize the quantity by machining a pair of timing gears with high timing precision invariably by use of the same arbor and maintaining the relative angle relationship between key grooves and teeth constant at all times. CONSTITUTION:A gear blank 1 is in a state that a shaft hole 2 is provided on a hub 9 and key grooves 3 machined in advance. Next, in order to get the timing 90 deg. out of phase for the rotor of a two-lobe root-type compressor, alpha=90 deg., n= 0, Z=40 are set for simplicity. According to an equation theta=alpha+180/Z+360n/Z, theta=94.5 deg. is obtained. A pair of key grooves 5, 5' having angular positions displaced each other by this angle are machined on an arbor 4. Next, a pair of blanks 1 is coupled with the arbor 4 at a preset angle theta with individual key grooves 3 being engaged with key grooves 5, 5' of the arbor 4 by use of keys 8 respectively. Then, the arbor 4 is fitted to a gear cutting device and machined for gear cutting, and gears 10, 10' are removed and fitted to shafts 15, 15 of a compressor.
Patent JP-S6146104-A (JP)
Title: Operating apparatus of carrier in line
Inventor: YASUOKA NORIHISA
IPC: B61B12/06
Filed: 1984-08-11
Abstract: PURPOSE:To prevent carriers from colliding each other due to an abnormal operation by stopping the following carrier when the following carrier enters into the same section trolley wire where the preceding carrier is stopped. CONSTITUTION:When a drive motor 34 is started to allow the first carrier A to abnormally start so that a current collector 14A overrides a section poit 5a into the second section trolley wire 4b, a circuit W of the first powe supply trolley wire 1, a current collector 11A, a control relay 20, a current collector 14A, the second section trolley wire 4b, a current collector 14B, the control relay 20, a current collector 12B and the second power supply trolley wire 2 is formed. When the relay 20 is energized, a relay for operating the drive motor is deenergized to stop the motor 34, and the first carrier A automatically stops driving.
Patent JP-H0217579-A (JP)
Title: Individual collating device
Inventor: YAHAGI HIRONORI
IPC: G06T7/00
Filed: 1988-07-05
Abstract: PURPOSE:To improve the precision of fingerprint register and collation by providing a sweat gland eliminating means which eliminates sweat glands after converting a fingerprint picture to narrow lines. CONSTITUTION:The picture from a picture input system 11 is stored in a picture storage circuit 12 and is binarized by a binarizing and narrow line converting circuit 13 and is converted to narrow lines of rising lines and falling lines. Feature points are extracted by a feature extracting circuit 14 and are stored in a feature point storage device 15. Branch points are retrieved from the picture converted to narrow lines by a branch point retrieving circuit 16, and a perpendicular bisector is drawn between two arbitrary branch points by a perpendicular bisector calculating circuit 17. When the perpendicular bisector crosses two narrow lines in the range of a certain number of picture elements, branch points are regarded as sweat glands by a sweat gland discriminating circuit 18 and the processing is performed which eliminates these two branch points form feature points, and results are outputted to a feature point storage device 15.
Patent JP-S6324370-A (JP)
Title: Image data rotating system
Inventor: KUMAKURA YASUO
IPC: G06T3/60
Filed: 1986-07-16
Abstract: PURPOSE:To process image data at optional ratio of magnification or reduction by setting reduction ratio calculated from angle of rotation to a magnification and reduction control register and generating clock signals that control a vector generator by the data. CONSTITUTION:A DDA (digital differential analyzer) clock generating circuit 4 is connected to a magnification and reduction pattern register 1 and a magnification and reduction control register 2 of the system. A pattern of optional ratio of magnification and reduction is set to the register 1, and repetition width of magnification and reduction pattern of image data calculated from angle of rotation is set to the control register 2. The generating circuit 4 is controlled by output from the register 1 and control register 2, and clock signals generated by the generating circuit 4 is applied to a spectrum generator 3, and image data are processed at optical ratio of magnification or reduction.
Patent JP-H1113192-A (JP)
Title: Vibration isolation floor structure
Inventor: MURAI TATSURO
IPC: E04B5/43
Filed: 1997-06-25
Abstract: PROBLEM TO BE SOLVED: To provide a vibration isolation floor structure in which a difference in level does not occur between adjacent floor panels. SOLUTION: Adjacent floor panels 10, 11 are spaced through a liquid sealing damper 17 at a regular interval separately and attached to building casing 12, 13, and a buffer plate 20 for absorbing a difference in level due to vertical movement of each floor panels 10, 11 is set between the floor panels 10, 11. The buffer plate 20 is a plate body of substantially the same thickness as the surface plates 10b, 11b of the floor panels 10, 11, attached between the surface plates 10b, 11b of the floor panels 10, 11, and both the side edges of the buffer plate 20 are supported at the panel frames 10a, 11b of both the floor panels 10, 11 respectively.
Patent JP-S6150780-A (JP)
Inventor: OOKA AKIHIRO
IPC: B25H1/14
Filed: 1984-08-11
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6413591-A (JP)
Title: Display device
Inventor: TSUJIOKA SHIGEO
IPC: G09G1/02
Filed: 1987-07-08
Abstract: PURPOSE: To prevent output mode switching by detecting that the output mode switching to a dual-port memory with logical operation is specified and inhibiting the output mode switching of the dual-port memory. CONSTITUTION: For example, when a microprocessor 100 specifies a function for output mode switching owing to an error of software, an output mode switching code is sent out as a function code to a signal line 170 and a function setting actuation signal is sent out to a signal line 200. In this case, a mode switching detecting circuit 130 detects this output mode switching code and a selector 120 operates so as to select an input 3. A function code other then the output mode switching is inputted to the input 3 of the selector 120, so the selector 120 stops the output mode switching code. Consequently, the dual- port RAM 110 with logical operation is not switched in output mode from a 4-bit output mode to a 1-bit output mode.
Patent JP-H0612152-A (JP)
Title: Electric power source division control system between cmos circuits
Inventor: MATSUO TOMOAKI
IPC: G06F1/32
Filed: 1992-06-26
Abstract: PURPOSE:To suppress an increase in irreducible hardware quantity and prevent a latch-up phenomenon with low-power-consumption circuit constitution when a CMOS circuit is divided and supplied with electric power as to the electric power source division control system which divides and controls the electric power between the CMOS circuits. CONSTITUTION:This system is equipped with a signal output circuit 2 which is provided with a signal output timing control part 21 and a signal-input side circuit 1 which inputs the signal from this signal-output side circuit 2 through a signal line where a pull-down resistance R is connected; and a signal output timing control part 21 places the output of the signal-output side circuit 2 to the signal line in a floating state corresponding to a power-OFF indication and powers OFF the signal-input side circuit 1 while the signal holding the signal level at an L level through the pull-down resistance R is inputted to the signal-input side circuit 1.
Patent JP-H09328695-A (JP)
Title: Electroviscous fluid
Inventor: ODA HIROHARU
IPC: C10M107/24
Filed: 1996-06-10
Abstract: PROBLEM TO BE SOLVED: To obtain an electroviscous fluid capable of exhibiting large electroviscous effect in low power consumption, excellent in stability and useful as an actuator for clutches, dampers, etc., by dispersing specific polyether acrylate-based polymer particles into an electrical insulating liquid. SOLUTION: This electroviscous fluid is obtained by dispersing (A) particles of a polymer containing polyether acrylate monomers represented by formula I [R<1> is H or methyl; R<2> is a 6-30C alkyl; Z is a 2-4C alkylene; A is 0, OCO or a group of the formula OPh (Ph is phenylene); (n) is 2-50], formula II, formula III (R is a 1-5C alkyl) or formula IV as a polymerization component and having 5-50wt.% content of polyether unit (OZ)n of the component A1 based on the weight of the polymer into (B) an electrical insulating liquid (e.g. silicone oil or fluorocarbon oil).
Patent JP-2000002199-A (JP)
Title: Bell-mouth for propeller fan
Inventor: KOYAMA KIYOSHI
IPC: F04D29/56
Filed: 1998-06-16
Abstract: PROBLEM TO BE SOLVED: To prevent interfering with a heat-exchanger at the time of assembling in to outdoor unit. SOLUTION: Flanges 2 and 3 having a rectangular outside shape are extended outward from the two ends of a cylindrical body 1 to form an air passage R, and a thin wall portion 4 stretching in the vertical direction is provided in the part of the flange 2 positioned to the left and right at assembling to an outdoor unit and located inside the outdoor unit, and it is arranged so that the flange 2 can be bent by this thin wall portion 4.
Patent JP-H0724717-A (JP)
Title: Method and device for polishing optical fiber multi-core block connector
Inventor: SAITO HIROMITSU
IPC: G02B6/40
Filed: 1993-07-08
Abstract: PURPOSE:To provide an end surface polishing method for optical fiber multi-core block connector whereby low-loss connection can be made and also re-polishing can be made easily. CONSTITUTION:A close-fit pin 6 is inserted into a close-fit hole 3 of an optical connector 1, and a part at the rear of the optical connector is fixed to a polishing jig 7. In this case, the axis of the close-fit pin 6 is fixed at right angle to the upper surface of a polishing machine 10. Next the polishing machine 10 is moved in the direction at right angle to the axis of the close-fit pin 6 and, at the same time, a proper pressure is applied to the end surface 1a of the optical connector 1 to polish the end surface 1a.
Patent JP-H067871-A (JP)
Title: Manufacture of heat exchanger
Inventor: GO NOBUAKI
IPC: F28F9/02
Filed: 1992-06-26
Abstract: PURPOSE:To save labor in operation by suppressing the bulge of a core part, which consists of tubes and fins, by utilizing the spring back action of side members. CONSTITUTION:In the case of manufacturing a heat exchanger assembly 9, by using curved side members 4, 4, arranging them outside of the outermost fin 2, and holding by fitting to both ends with the engaging part 3d such as recessed parts and holes which are provided on the periphery of both headers 3, the bulge of the core part that consists of the tubes 1 and the fins 2 is suppressed through the spring back action of the side members 4, 4. Then, brazing is generally performed on this assembly 9 to join and integrate the whole body. Thus, the attaching and detaching of tools and bands for suppressing the bulge of the core part may be omitted, and the improvement in productivity and the reduction in cost of the heat exchanger are attained.
Patent JP-H0458752-A (JP)
Title: Rotary yoke type brushless motor subjected to noise reduction
Inventor: YAMAGUCHI TADAO
IPC: H02K5/24
Filed: 1990-06-27
Abstract: PURPOSE:To suppress noise by arranging a high density metallic member closely to the free end of stator, i.e., a through-hole. CONSTITUTION:A stator has a central through-hole 11a and comprises a thick film fine pattern board printed with a plurality of armature coils and the stator 11 is secured to a stator holding section 9a having outer circumference molded integrally with a bracket 9. The through-hole 11a is set as a pattern for arranging the routing lead of armature coil at the inside of the inner diameter 2b of a magnet 2, and a high density metallic member 12 comprising a brass ring is bonded through an acrylic bond in a space delimited by a magnet case 2a, the magnet 2 and the step part 4a of a rotor holder 4.
Patent JP-2000357035-A (JP)
Title: Audio system
Inventor: NARISAWA SADAYUKI
IPC: G06F3/0484
Filed: 1999-06-15
Abstract: PROBLEM TO BE SOLVED: To provide an audio system capable of easily performing setting operation while miniaturizing an audio device capable of a lot of kinds of setting. SOLUTION: A display control part 142 of a PC 14 displays the setting state of items, which can be set by an audio device 100, according to a control program read out of a CD-ROM by a reader 143 and functions these items as a GUI. When any setting is performed from the GUI, these set contents are sent through an interface 141 to the audio device 100. On the basis of the received set contents, the audio device 100 applies processing to an audio signal.
Patent JP-S6147365-A (JP)
Inventor: KIMOTO KATAYOSHI
IPC: B65D83/06
Filed: 1984-08-13
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6328270-A (JP)
Title: Capacitance-diode voltage multiplying circuit
Inventor: TAKAMURA YOSHIO
IPC: H02M7/06
Filed: 1986-07-18
Abstract: PURPOSE:To cut down the rush current when AC input voltage is of rectangular waves and to strive for high efficiency, by inserting and connecting the resistance in series to all the diodes. CONSTITUTION:By combining and connecting multiple capacitors C1-C8 and diodes D1-D8, a capacitance-diode voltage multiplying circuit is formed in which DC multiplied voltage is produced from AC input voltage. To diodes D1-D8 resistances R1-R8 are inserted and connected in series respectively. When the resistance value of these resistances R1-R8 grows larger to some extent, the output voltage increases and that the output voltage changes according to the resistance value.
Patent JP-H04367989-A (JP)
Title: Input/output circuit of microcomputer
Inventor: MORIMI YOICHI
IPC: G06F15/78
Filed: 1991-06-14
Abstract: PURPOSE:To effectively utilize a memory for storing an address of an address signal by controlling a direction register and an output latch by the same address signal. CONSTITUTION:After resetting, an RS flip-flop 7 is reset, and a 2-input AND circuit 8 becomes active. When an address signal An is designated, a direction register 3 is designated, an input buffer 6 becomes active and data is transferred to a data bus 1 from an input/output terminal 5. When the direction register 3 is designated, the RS flip-flop 7 is set through a delaying circuit 10, and a 2-input AND 1 circuit 9 becomes active. Thereafter, when the same address signal An is designated, an output latch 2 is designated, and data from the data bus 1 is latched to the output latch 2. Thereafter, the output buffer 4 becomes active by the direction register 3, and the data latched to the output latch 2 is transferred to the input/output terminal 5.
Patent JP-2000355492-A (JP)
Title: Canvas roof for head guard and canvas roof device
Inventor: TOKUDA HARUMI
IPC: B66F9/075
Filed: 1999-06-16
Abstract: PROBLEM TO BE SOLVED: To prevent gathering of rainwater by respectively arranging a plurality of shape memory linear material extending in the longitudinal and lateral directions in a main body sheet part for covering an upper surface part of a head guard, and restoring the main body sheet part from deformation by a temperature and humidity. SOLUTION: Shape memory glass fibers 13a as shape memory linear material are fully embedded in large numbers at prescribed intervals in the lateral direction by the sheet length in the longitudinal direction inside a main body sheet part 11. Shape memory glass fibers 13b are fully embedded in large numbers at prescribed intervals in the longitudinal direction by a sheet width in the lateral direction. Thus, even if rainwater gathers in a lattice part in a lattice- shaped upper surface part 2, the rainwater can be dropped from the main body sheet part 11 in rainy weather by a shape restoring function of the shape memory glass fibers 13a, 13b. Thus, the gathered rainwater does not drop even if a vehicle is operate after the rain, so that an operator can safely perform work without caring about the rainwater.