baber/WOPTO huggingface dataset:
Patent JP-S60213123-A (JP)
Title: Non-instantaneous interruption switching circuit of clock
Inventor: KAWAMURA KAZUTOSHI
IPC: G06F1/04
Filed: 1984-04-06
Abstract: PURPOSE:To prevent an output clock from instantaneous interruption even if any one input clock is interrupted at a high level or a low level by combining plural AND circuits and NAND circuits to constitute OR and exclusive OR circuits. CONSTITUTION:If one input clock, e.g. CLKB, is interrupted at the high level, high level clock interruption of one period is generated in an output clock CLKY from a NAND circuit IC5. However, the output clocks CLKA', CLKB' of NAND circuits IC3, IC4 are inconsistent each other during said period, so that the output of an exclusive OR circuit IC7 is in the high level, the output of an AND circuit IC8 is turned to the low level and the output of a NAND circuit IC9 is turned to the low level. Consequently, the output of an AND circuit IC6 is inverted and an output clock CLKZ is prevented from clock interruption at the high level.
Patent JP-S59194577-A (JP)
Title: Image pickup device
Inventor: TAKAHASHI SUSUMU
IPC: H04N5/21
Filed: 1983-04-19
Abstract: PURPOSE:To improve an apparent aperture by vibrating a parallel plane plate arranged in an optical path in an image pickup device using a solid-state image pickup element. CONSTITUTION:Incident light is image formed on the solid-state image pickup element 8 by an image formation optical system 6 through the parallel plane plate 7. At that time, the parallel plane plate 7 is driven by a driver 9 and vibrated around the horizontal direction on a surface vertical to an optical axis at every frame period. On the other hand, the solid-state image pickup element 8 is controlled at its reading and signal amplified by a signal processing circuit 10 and outputs a video signal. Thus, the apparent aperture rate is improved so that a point on an object varies an image formation point on the solid state-image pickup element.
Patent JP-S58186242-A (JP)
Title: Adaptive predicting encoder
Inventor: KAWAYAUCHI NOBORU
IPC: H03M3/04
Filed: 1982-04-26
Abstract: PURPOSE:To prevent the generation of noise, by selecting an input connected with a code representing the minimum quantizing step by a data selector, during a prescribed time until the encoding of an ADPCM encoding section is functioned normally after powering. CONSTITUTION:Although the integration voltage of an integration circuit of a timer 14 is OV just after application of power supply, the integration voltage is increased with a current flowing to a capacitor C from an input of a resistor R and a Schmitt trigger inverter gate 15 with the lapse of time. While the integration voltage is lower than the input threshold voltage of the inverter gate 15, the logical level of an output (r) of the inverter gate 15 goes to ''1'', and when the integration voltage exceeds the threshold voltage, the logical level of the output (r) is switched to ''0''. The data selector 12 selects an input (m) to which the code representing the minimum quantizing step is connected to output said input when the output (r) logical level of the timer 14 is ''1'', and when the logical level of the output (r) is ''0'', the input to which an output data (d) of the ADPCM encoding section 11 is connected is selected and outputted.
Patent JP-H11262449-A (JP)
Title: Rice cooking device for business
Inventor: MIHIRA KEIICHI
IPC: B23K26/12
Filed: 1998-03-18
Abstract: PROBLEM TO BE SOLVED: To easily finish tasty cooked rice according to uses without sticking a seasoning to the bottom of a rice cooking pot and having many films made by providing a seasoning supply means supplying the seasoning to the rice cooking pot. SOLUTION: A rice cooking device 1 is provided with a rice storing part 2 on the upper part, a rice washing part 3 on the lower side and a rice cooking part 4 on the lower side of the rice washing part 3. The rice cooking part 4 is provided with an electric or gas type rice cooking pot 7 on a frame 4A capable of sliding on a horizontal surface in the front and rear directions and a pot cover 7D for an inner pot 7C is provided so as to be freely opened and closed by a cover opening and closing means. In this case, the rice cooking part 4 is provided with a seasoning supply means 9 supplying a seasoning 9A to rice cooking pot 7.  This seasoning supply means 9 has a container 10 storing the seasoning 9A having flowability of water in which rice cooking oil and table salt are dissolved and is provided with a passage 11 feeding the seasoning 9A from this container 10 to the rice cooking pot 7. On the container 10 or the passage 11, a sensor detecting the opening and closing operation of a shutter 12 is provided. By the detection signal of this sensor, a solenoid valve 14 is opened and closed.
Patent JP-S58185354-A (JP)
Title: Oil film removing wiper
Inventor: YONEMORI KOMAO
IPC: B60S1/18
Filed: 1982-04-23
Abstract: PURPOSE:To apply soapy water and remove an oil film, by mounting another wiper to a conventional wiper to form the wiper to a twin wiper. CONSTITUTION:An auxiliary wiper B is mounted to a conventional wiper A and their wiping parts (a) and (b) are parallelly arranged. In case of removing an oil film, only the wiper A is firstly moved, if the wipers A and B are separated with a large opening, soapy water is sprayed to a glass surface, after confirmation of the soapy water between the parts (a) and (b), the wiper B is moved.
Patent JP-H07283698-A (JP)
Title: Dynamic flip flop circuit with asynchronous clear
Inventor: USHIO TOMOHIRO
IPC: H03K3/356
Filed: 1994-04-07
Abstract: PURPOSE:To provide a dynamic flip-flop circuit with asynchronous clear of a simple configuration which is compatible to a breadboard for which a TTL is used. CONSTITUTION:Between a data input terminal 1 and a data output terminal 6, an MOS transistor 2, a NAND gate 3, a MOS transistor 4 and an inverter 5 are serially connected, and the outputs of the NAND gate 3 and the inverter 5 are made clear according to a clear signal CL by the NAND gate 3 and a MOS transistor 7. By a MOS transistor 8, the signal to be transferred from the MOS transistor 2 to the NAND gate 3 is interrupted according to the clear signal. By a MOS transistor 9, the data held in the capacity on the side of the input of the NAND gate 3 is made clear.
Patent JP-H10253320-A (JP)
Title: Apparatus for measuring amount of position dislocation
Inventor: SUZUKI TAKAHIKO
IPC: H01L21/027
Filed: 1997-03-06
Abstract: PROBLEM TO BE SOLVED: To restrict influence of grains and measure with high accuracy, by providing a photodetecting element which is arranged in a direction at right angle to a plurality of patterns and selected to have a slit with thereby a ratio of an image to a pupil diameter of an objective lens is set to be not larger than a specific value and a slit length whereby the ratio is set to be not smaller than a specific value. SOLUTION: An incident-light optical system introduces an illumination light from a light source to an objective lens through an opening aperture having a cross slit, thereby illuminating a sample with an incident light. The cross slit is selected to have a slit width whereby a ratio σ of an image to a diameter of a pupil 1a of the objective lens is set to be 0.3 and a slit length whereby the ratio is set to be not smaller than 0.6. A contrast of a detection signal from a pattern to a detection direction is improved. Moreover, since the ratio σis larger than 0.6 along the detection direction, a contrast of grains can be reduced. A noise level of the detection signal due to the grains is restricted. The detection signal shows accordingly a favorable peak value.
Patent JP-S62232422-A (JP)
Title: Polyisocyanate preparation and its use for producing polyurethane plastic
Inventor: MUELLER HANNS P
IPC: C08G18/10
Filed: 1987-03-25
Abstract: The present invention is directed to polyisocyanate compositions containing (a) at least one organic polyisocyanate and (b) at least one dissolved catalyst corresponding to the general formula   <IMAGE> wherein R1 and R2 may be identical or different and denote hydrogen or a methyl group, provided that R1 and R2 do not both stand for a methyl group, R3, R4 and R5 denote identical or different organic groups which are inert in isocyanate addition reactions and k, m and n represent identical or different integers with values from 1 to 5. The present invention also relates to the use of the polyisocyanate compositions as the polyisocyanate component for the production of polyisocyanate polyaddition products, especially moisture cure coating compositions or adhesives.
Patent JP-S60213012-A (JP)
Title: Small sized flyback transformer
Inventor: MORIMOTO SADAO
IPC: H01F38/42
Filed: 1984-04-06
Abstract: PURPOSE:To facilitate positioning of a rectifying part, and to contrive to enhance yield and to reduce the man-hour of work when a small sized flyback transformer is to be manufactured by a method wherein a printed substrate is held by projections provided to the edge surface of the flange of a bobbin. CONSTITUTION:Projections 11 are provided to the edge surface of the flange 12a of the bobbin 12 of a transformer part, and a printed substrate 10 is held by the projections 11 thereof. Diodes 4, capacitors 5 and an anode lead wire 6 are assembled to the printed substrate 10 by performing the prescribed wiring to construct a rectifying part. By engaging a high voltage coil 1 with a low voltage coil 2, and by fixing according to a core 3, a transformer part is constructed, and the printed substrate 10 is equipped to the high voltage coil 1 of the transformer part thereof to be connected according to solder. The insulating distance between the printed substrate 10 equipped to the transformer part and the core 3 of the transformer part is made to a distance enabled to hold sufficient insulation.
Patent JP-S61228716-A (JP)
Title: Input stage filter tuning device for tuner
Inventor: YAMADA TADASHI
IPC: H03J5/00
Filed: 1985-04-02
Abstract: PURPOSE:To omit the adjustment for initial value setting for an RF tuning voltage by providing a comparator detecting an IFAGC voltage and comparing it with an optional reference potential fed through a D/A converter circuit from a microcomputer and inputting the output of the comparator to the microcomputer. CONSTITUTION:The comparator 34 comparing an analog voltage obtained from the 2nd D/A converting circuit 35 with the IFAGC voltage is provided. Further, a means 17 calculating a sensor value i=(h+j)/2 is provided, where h-j is the 1st digital information during an output of the comparator 34 is turned on when a voltage given to a varactor diode of an input stage filter 5 is swept by the 1st digital information controlling the 1st D/A converting circuit 18 every time the digital information controlling the 1st D/A converting circuit 18 is incremented or decremented by one step each after channel selection is applied and the local oscillation frequency is made stable. Then the digital information corresponding to the value (i) is converted into an analog voltage by the D/A converter 18 and fed to the varactor diode of the input stage filter 5 of the tuner so as to fix it.
Patent JP-H11248899-A (JP)
Title: Electron beam irradiation device
Inventor: SUGITA TATSUNOBU
IPC: G21K5/00
Filed: 1998-03-03
Abstract: PROBLEM TO BE SOLVED: To detect even in the case only one filament is blown out. SOLUTION: A current measuring meter 42 and a voltage measuring meter 40 are provided in the secondary winding 26b side of a filament transformer 26 to measure the filament current If flowing in the secondary winding 26b and the filament voltage Vf across the filament 6. The voltage Vf and the current If measured with them are transmitted to a ground potential part by way of a transmission circuit 44 and supplied to a controller 52. The controller 52 has a filament current controller 54 and a comparator 56. The filament current controller 54 controls a voltage controller 32 so that the filament current If given from the transmission circuit 44 becomes constant and controls the primary voltage V1 supplying to an insulation transformer 24.  The comparator 56 compares the filament voltage Vf given by the transmission circuit 44 with the specific reference voltage R, and outputs a breaking detection signal S when the former Vf is larger than the latter R.
Patent JP-H01242294-A (JP)
Title: Semiconductor memory apparatus
Inventor: TAKAYANAGI HIROSHI
IPC: G11C11/401
Filed: 1988-03-25
Abstract: PURPOSE:To reduce the density of pattern wiring and a pattern length, by separately arranging memory signal driving parts to both ends of a memory IC and wiring the memory terminals of the memory IC serially and connecting both terminals thereof to each memory signal driving parts. CONSTITUTION:The address buffer IC 7 and damping resistor 14 on the side of a port 1 and the address buffer IC 8 and damping resistor 15 on the side of a port 2 are arranged to both ends of a memory array part 2, and the mem ory address signal bus 5 from the port 1 and the memory address signal bus 6 from the port 2 are separated to perform wiring. Therefore, the pattern wiring density and wiring length of this part are reduced. By arranging memory address buffer circuits 19, 20 and damping resistors 23, 24 to both ends of a memory IC, the memory signal wiring 25 of the memory IC part can be connected seri ally with respect to the memory IC and the memory signal wiring of the mem ory IC part also becomes easy.
Patent JP-H06297281-A (JP)
Title: Method of replacing cutter on machine tool and machine tool for cutting workpiece
Inventor: PABERU BURATSUEKU
IPC: B23Q3/155
Filed: 1994-04-07
Abstract: PURPOSE: To prepare a tool for next use by taking action in a short time from cutting to cutting and in a configurationally and control-technologically simple manner. CONSTITUTION: A machine tool has a table 17 for tightening and fixing a workpiece, a board 24 provided with at least one main spindle and a tool magazine 12. Tool replacement is accomplished at a first outer periphery portion of the tool magazine. For formation of at least one first void space located right adjacent to a position of storing a tool to be used next in the tool magazine, the tool is removed out of the tool magazine and the tool is temporarily stored in a range of a second outer periphery portion so that tool replacement can be accomplished directly by the main spindle. In this case, the used tool is put into the first void space of the tool magazine and a tool to be used next, adjacent thereto, is removed out of the tool magazine. Then, a second void space produced thereby receives the tool, temporarily stored, again.
Patent JP-S57184255-A (JP)
Title: Solar cell
Inventor: YOSHIDA MASAHIRO
IPC: H01L27/142
Filed: 1981-05-08
Abstract: PURPOSE:To protect the solar cell from opposite-direction voltage by isolating one part of the P-N junction solar cell section formed onto a semi-insulating substrate and forming a protective diode. CONSTITUTION:An N type GaAs layer 2 and a P type GaAs layer 3 are laminated successively onto the semi-insulating GaAs substrate 1 and the solar cell is formed while one part is isolated, thus shaping the protective diode consisting of layers 6, 7. The P type layer 3 and the N type layer 6 are connected electrically by an electrode 5 through an insulating film 4, the P type layer 7 and the N type layer 2 are connected electrically by an electrode 8, and the solar cell and the protective diode are connected. Accordingly, the solar cell can be protected from the opposite-direction voltage by simple constitution.
Patent JP-S60213847-A (JP)
Title: Hydraulic destruction test of frp joint for high-temperature solution
Inventor: HIGASHIKUBO KAORU
IPC: G01N3/00
Filed: 1984-04-06
Abstract: PURPOSE:To enable actual measurement of a correct bursting pressure by forcing a high temperature solution into an FRP joint after an attachment is mounted to a connecting jig as extended from a pump. CONSTITUTION:A hydraulic test jig is mounted on an FRP joint A in which an FRP layer 2 is fastened integral outside a core 1 as heat resistant vinyl chloride cheese joint. Under such a condition as illustrated, two sealing jigs 3 and 3 and one connecting jig 4 are fastened on three-way sockets of the FRP joint A while a threaded part 6 is provided at the end of a liquid inflow path 5 of the connecting jig 4 and an attachment 7 extended from a pump is screwed securely into the threaded part 6. A high temperature liquid is fed being pressurized and thereby, a high temperature liquid with a specified pressure is forced into the FRP joint A from the liquid inflow path 5 to measure a liquid pressure which will cause destruction.
Patent JP-S63233725-A (JP)
Inventor: HINO MORIO
IPC: A01G9/00
Filed: 1987-03-23
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S62227636-A (JP)
Inventor: HIDA KOJI
IPC: B32B3/12
Filed: 1986-03-28
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H04363353-A (JP)
Title: Guanamine resin molding material
Inventor: HASHIMOTO YOICHI
IPC: C08L61/26
Filed: 1991-04-02
Abstract: PURPOSE:To obtain a guanamine resin molding material, capable of providing molded products excellent in transparency while maintaining water resistance and suitable as wiring tools, electric appliances, etc. CONSTITUTION:A guanamine resin molding material is obtained by adding guanamine resin and/or solid guanamine resin to the solid guanamine resin subjected to treatment at a high temperature of 120-170 deg.C for 0.5-5hr at (3:7) to (7:3) ratio and further blending 100 pts.wt. above-mentioned resin with 0.01-3 pts.wt. curing agent (e.g. hexamine), 0.05-5 pts.wt. mold release agent (e.g. a fatty acid or a metallic salt of the fatty acid) and, as necessary, a filler or a colorant.
Patent JP-S62129711-A (JP)
Title: Method and apparatus for measuring configurational error of object
Inventor: ONO AKIRA
IPC: G01B11/30
Filed: 1986-03-28
Abstract: PURPOSE:To make it possible to measure the configurational error of object having a complicated shape, by simple constitution such that Moire interference fringes by imaginary object free from a calculated configurational error and actual object are respectively displayed at the same time. CONSTITUTION:When a reference mirror 12 is moved by a driving controller 14, the relative phase of reflected interference beams from a measuring mirror 16 and a mirror 12 successively changes by pi/2 and an interference fringe due to interference beams is displayed on a TV monitor 24 through an image sensor/ monitor 11 and a memory/data processor 15. A reading circuit 23 is also controlled through the controller 14 and the Moire interference fringe to imaginary matter free from a configurational error written in a recording apparatus 22 at every phase difference preliminarily calculated by an operation circuit 21 to correspond is simultaneously displayed on the monitor 24. By this simple constitution wherein it is unnecessary to form a hologram of an object interference fringe by display, the configurational error of complicated object of which the interference fringe intensity distribution does not form sine function is measured.
Patent JP-S61230479-A (JP)
Title: Processor for composite video signal waveform of television
Inventor: YAGI MOTOI
IPC: H04N5/93
Filed: 1985-04-04
Abstract: PURPOSE:To eliminate the occurrence of a flicker on a screen by a waveform process to coincide the level of a video signal in a reproducing signal that is delayed with the level of the video signal in the reproducing signal that is not delayed without receiving the influence by temperature and the like. CONSTITUTION:The peak level of the video signal in the reproducing signal that is delayed by H/2 at a delay circuit 25 and the peak level of the video signal in the reproducing signal that is not delayed are inputted respectively to the input terminals of a pair of operational amplifiers 29 and 30 which are easy to be balanced and also, the output of each operational amplifier is inputted to a differential amplifire 31 and an error voltage is obtained byh comparing those. Based upon the error voltage, these are coincided with the level of the video signal of both signals and also the pedestal levels of both reproducing signals are coincided by a pedestal level circuit 37 and furthermore, the sync chip levels of both reproducing signals are fixed at a fixed potential by an NPN transistor Tr 3. Thus, the composite video signal from which possibility of occurrence of flickering by the flicker is eliminated is obtained.
Patent JP-H07234891-A (JP)
Title: Sequence cad system
Inventor: KAYAMA SUSUMU
IPC: G06F17/50
Filed: 1994-03-14
Abstract: PURPOSE:To improve the design efficiency at the time of drawing preparation, to facilitate assembly or construction and to facilitate the maintenance of an equipment by adding attribute symbols containing the name of equipment, capacity, etc., to symbols stored in a symbol file. CONSTITUTION:This system is provided with an input part 10, output part 20, work area 30, CPU 40 as a control part for performing retrieval, control and arithmetic, file part 50 and auxiliary storage part 60. Then, a format file 52 at the file part 50 stores various kinds of formats of an output drawing such as the size of the drawing, vertical writing, horizontal writing and the kind of a frame. On the other hand, a symbol file 54 stores various kinds of symbols to be used for an electric circuit diagram. Namely, the attribute symbol containing the equipment name, capacity and contact symbol is added to the symbol stored in the symbol file 54. Then, the CPU 40 calls the symbols from the symbol file 54 and performs control according to its attribute symbol.
Patent JP-S61229341-A (JP)
Title: Semiconductor integrated circuit
Inventor: AIZAWA HISAMITSU
IPC: H01L27/02
Filed: 1985-04-03
Abstract: PURPOSE:To array all the cell blocks without any unavailable region by a method wherein, in the arrangement structure of cell block according to a building block system, the number of the parallel arrangement stages of the polycell-structure arrays of each cell block is properly modified and the configurations of the respective cell blocks are prescribed. CONSTITUTION:When blocks B1-B9, in each of which plural pieces of polycell- structure arrays C1-C5 are arrayed in parallel to one another across each wiring region L, are arrayed, the number of the parallel stages of the polycell- structure arrays belonging to each block is properly modified and the configurations of the respective blocks are prescribed. For example, when a block 8 and a block 9 are arranged, the numbers of the parallel stages of the polycell-structure arrays of the blocks 8 and 9 are respectively modified for eliminating an unavailable region I2 to generate on the boundaries of both of the blocks 8 and 9 and a block 5 and the configurations of the blocks 8 and 9 are modified so as to fill the above-mentioned unavailable region. Hereby the unavailable region to generate between each blocks is activated and the utilization efficiency of the substrate can be improved.
Patent JP-H06281388-A (JP)
Title: Plate for plate type heat exchanger
Inventor: KIYOSE TERUHISA
IPC: F28F19/01
Filed: 1993-03-29
Abstract: PURPOSE:To prevent adherence of scale to a liquid contact part by precisely finishing a surface of the contact part such as a heat transfer surface by electrolytically polishing, chemically polishing, electrolytically plating, etc., after a plate is pressed completely. CONSTITUTION:A plate 11 has a heat transfer surface 12, a channel hole 13, a gasket 15 mounting gasket groove 14, and is formed by pressing a flat plate made of stainless steel, etc. The pressed plate 11 is electrolytically polished as precise finishing protruding ends of an uneven part due to damage formed on a surface of the plate 11 at the time of pressing is concentrically polished to smooth a surface of a liquid contact part of the surface 12. Thus, adherence of scale to the surface of the contact part of the surface 12 of the plate 11 can be prevented.