Patent GB-828539-A (GB)
Title: Improvements in or relating to data processing equipment
Inventor: WRIGHT ESMOND PHILIP GOODWIN
IPC: H04L12/54
Filed: 1956-08-28
Abstract: 828,539. Automatic exchange systems. STANDARD TELEPHONES & CABLES Ltd. Aug. 16, 1957 [Aug. 28, 1956], No. 26230/56. Class 40 (4). In a system in which 2- digit and 3-digit code prefixes are used, the reception of the first two digits causes the ready out of the information stored in a corresponding row of a matrix store forming part of a translator. If the two digits constitute a code prefix, the information read out is a multi-digit translation; if they do not constitute a code prefix, the information read out is a single digit, which, in combination with the third dialled digit, causes the read out of a further row corresponding to that combination, from which row the required multi-digit translation is obtained. The storage matrix is of the ferro-magnetic type and includes two groups of columns, of which the first consists of a number of sets TA ... TM (Fig. 6), one per digit for the maximum number, say six, of digits in a translation, and a set TI having as many columns as are needed to store one digit, all the columns sharing the same row wires. Each set of columns, as described, consists of ten columns, and in each row there is stored either a multidigit translation in the sections TA-TM, or a single digit in section TI, a row in any set storing a digit by one of its cells being operated to the " 1 " state and the other nine to the " 0 " state. Each column wire is associated with a circuit such as is shown in Fig. 4, and for each set of columns there is provided a pattern shift register RA, RM, RI (Fig. 6). A calling subscriber SUB (Fig. 5) is connected in well-known manner via a line-finder LF to a speech channel SC which is associated by a register finder RF with a free register REG (Figs. 5, 6). Dial tone is reverted and the first three digits dialled are repeated by IR via distributer DS to digit stores R1, R2, R3, respectively, these stores being pattern shift registers which record a digit by leaving operated the corresponding one of a chain of ten binary register elements. After the second digit has been received, DS steps to position 3, whereupon pulses PL (Fig. 2) produced by generator PLG (Fig. 1) are applied via bank DSB (Fig. 5) to the gates OG1, OG2, OG3 associated with R1, R2, R3 respectively. The output of PLG is also applied via a divideby-ten circuit DT (Fig. 1) to a three-stage counter TC which provides pulses t1, t2, t3 (Fig. 2), in its three stages respectively. When the next t1 pulse occurs, OG1 and OG2 both open because the bi-stable trigger circuit IFF (Fig. 6) is in its rest (" 0 ") condition, and ten PL pulses are applied to R1 and R2, thus transferring the first two dialled digits via gates OG4, OG5, respectively, to the pattern shift registers X and Y, which are similar to R1, R2, R3 in type. The registers X and Y control the cells of the access selector XY (Fig. 6), each of which is individual to one row of the storage matrix. Each cell (see Fig. 3) has five windings, an input winding 1 fed from pulse generator RWG which produces a read/ half-write pulse output RW (Fig. 2), an output winding 2 connected to the LG gate (Fig. 6) of the corresponding row, a column winding 3, a row winding 4, and a bias winding 5 which normally saturates the cell negatively. The row and column windings are fed via gates such as 3G1 from the corresponding X and Y register elements. These gates are also fed by pulse t2 and by an output RWA from RWG consisting of a pulse whose duration equals that of a read/half-write pulse RW. On the next t2 pulse the cell corresponding to the first two dialled digits is unsaturated by the current flowing in its row and column windings and operates as a pulse transformer to pass the waveform RW applied to its input winding 1 to its output winding 2 to open the LG gate (Fig. 6) corresponding to the " wanted " row and pass the read half-write pulse to that row. The read pulse causes pulses to appear on those column wires corresponding to the cells of that row in which " 1 " is stored. Each column wire is associated with a gate 4G1 (Fig. 4), fed by pulses RWA and, if the column wire corresponds to a cell of the row which was at " 1," the resulting pulse passes via 4G1 to the amplifier A1 and thence to the appropriate portion of the registers RA-RM or RI. The output from A1 is also applied via gate 4G2 controlled by pulses coincident with the second portion of the read/half-write pulses RW, so that a half-write pulse is applied via A2 to the column wires from which " 1 " was read. This, in conjunction with the half-write portion of the pulse RW applied to the row wire, causes " 1 " to be re-written into the appropriate cells. If the first two digits dialled constitute a code prefix, the translation will thus be read out and entered in RA-RM. On the next t3 pulse, with RA off-normal and RI normal (indicating that a translation has been recorded in response to the first two dialled digits), gate FG (Fig. 6) will not be opened and no further action takes place in the translator. If the first two dialled digits do not constitute a code prefix, the row selected contains one digit only stored in TI, which digit is transferred to RI. Pulse t3 therefore passes via gate FG and operates the trigger circuit IFF to state " 1." Consequently the next t1 pulse opens IG and OG3 instead of OG1 and OG2 and ten pulses from the PL leads transfer the digits in RI and R3 to X and Y, respectively. On the next t2 pulse the cell of XY corresponding to these two digits is rendered unsaturated and the row corresponding thereto is read out as before, the translation corresponding to the three-digit prefix being transferred to RA-RM. After reception of the third dialled digit the stepping of DS to position 4 resets IFF to its normal " 0 " condition. The production of an output pulse from any cell of XY automatically resets the registers X and Y to zero by means not shown. Specifications 719,288, 749,796 and 750,636 are referred to.