Patent GB-842860-A (GB)
Title: Improvements in or relating to electromagnetic storage and switching arrangements
Inventor: HOFFMAN GEORGE RICHARD
IPC: H03K25/00
Filed: 1956-04-10
Abstract: 842,860. Circuits of bi-stable magnetic elemerits. NATIONAL RESEARCH DEVELOPMENT CORPORATION. April 5, 1957 [April 10, 1956], No. 10906/56. Class 40 (9). A binary counter comprises a core 1 of rectangular hysteresis characteristic material having an input coil 2, an output coil 4 and a regenerative coil 8, the output and regenerative coils being respectively connected to the base and collector electrodes of a transistor 5 which conducts and energizes the regenerative coil only when the core flux changes its remanent state in a particular sense. In one arrangement, Fig. 2A, the transistor base is positively biased by a source 10, and the input coil is energized from a source 30 by composite current pulses each representing a binary digit and consisting of a positive and a negative component. In operation, when the core is initially in magnetic state " 1," the positive component of the first composite pulse drives the core to state " 0," and the consequential induced output pulse in coil 4 renders the transistor conductive. The regenerative coil 8 is therefore energized, and since the coil is arranged to drive the core to state " 0," the subsequent negative component of the input pulse is prevented from having effect in restoring the core. At the same time the regenerative current establishes an output pulse at terminals 21, 22. The positive component of the next composite pulse is without effect, but the negative component restores the core to state " 1 " without producing an output at 21, 22 as the induced voltage in coil 4 is in a direction which inhibits transistor operation. This operational cycle is repeated for subsequent pairs of composite pulses. In a modification, each binary digit is represented by a unidirectional input pulse which is converted into a composite pulse by a reactance in the circuit of coil 2. In one arrangement, Fig. 6A, this conversion is effected by a condenser 23 and associated resistors 24, 25, the binary counter shown comprising an intermediate stage in a chain of identical units. Alternatively, as shown in Fig. 9, the condenser 23 and resistor 25 may be associated with a centretapped input coil 2. In a further arrangement, Fig. 8, pulse conversion is effected by an inductor 26 in association with resistor 25. An alternative form of counter directly responsive to unidirectional input pulses each representing a binary digit is shown in Fig. 3. In this arrangement a second coil 11 is permanently biased to state " 1 " by current in a winding 18, and the first input pulse changes core 11 to state " 0 " and leaves core 1 in state " 1." An output pulse is therefore induced only in winding 14 and the transistor is rendered conductive so that an effective output is produced by regenerative current and core 1 set to state " 0." The core 11 is then automatically reset to state " 1 " by the bias. The next input pulse changes both cores to state " 1," but fails to produce an output pulse as the induced voltages in windings 4 and 14 act in opposition.