Patent GB-1309101-A (GB)
Title: Laser recording system
IPC: G11B7/12
Filed: 1970-03-17
Abstract: 1309101 Laser memory CHASE MANHATTAN CAPITAL CORP and UNITED CALIFORNIA BANK 17 March 1970 [17 March 1969] 12900/70 Headings G4A G4C and G4M A data processing system and laser memory unit of the type in which a modulated laser beam selectively ablates the surface of an energyabsorbing strip 33 and variable intensity light reflected from the strip during read-out is sensed and decoded, comprises an optical head 30/31 for focusing the beam on to and receiving reflected light from the strip during recording and readout, data sensing means 47 including a track analyser 46 which splits the reflected beam into two and, in response to sum and difference signals corresponding to the two beams, supplies servo correcting signals to the optical head to ensure accurate track registration, a means for detecting detects in the strip prior to recording and errors in the data being recorded, the detecting means being operative during recording to generate and record signals indicative of the presence of defects or errors, and logic-control means responsive to these signals also during recording for re-recording previously recorded erroneous data. Laser memory; general.-The output from, e.g. an argon II ionic laser, is modulated by a Pockell cell modulator 11, passed through track widening optics to change its cross-section to rectangular, and a beam splitter 14. Part of the beam is passed to an intensity monitor sensor which passes feedback signals to the Pockell modulator to control the intensity of the beam, and the remainder is passed to an angled galvonometer mirror 30 and a cylindrical object lens 31 which direct it on to recording strip 33 mounted on a rotating drum 32. The optical head assembly 30/31 is mounted on a carriage which translates the beam across the periphery of the drum 32 under the control of the sequence control unit 18 via the control circuits 40, 41. During recording the beam intensity is selectively maintained at a level sufficient to burn the storage strip 33 whereas a lower intensity is used during readout. A number of strips 33 are stored in a rack and an automatic device is provided for selectively loading strips on to the drum 32 (see record strip selection). Clocking signals from the unit 55 serve as timing signals to control the operation of the system, the timing signals being interleaved with the data being recorded in the record mode, and being generated, during the read mode, by an optical tachometer 56 in response to rotation of the drum 32. A manual control panel is provided to control and/or test the system. Optical head 30/32 control.-The mirror 30 is driven by a sawtooth waveform synchronized to the rotation of the drum and the translation of the carriage carrying the head assembly so that a circular track is scanned. The reflected beam during readout and recording is split into two by a prism and detectors and amplifiers produce a difference signal which is fed back to the mirror drive circuit to ensure accurate track registration, a sum signal also being produced to serve as the readout signal. Delay units or temporary memories are included in the circuit between the two beam detectors and the difference amplifier. The difference signal is passed to an analogue gate which is connected to the mirror drive circuit and is open during the record mode and closed during the read mode. A delayed sum is also generated to provide fedback control for the carriage drive circuits. Drum speed control.-The drum 32 is driven by a printed circuit motor 34 which is locked on to an accurate reference frequency produced by a crystal controlled oscillator. An optical tachometer is also connected to the motor shaft to produce a pulse train which is fedback and compared with the reference frequency, remedial action being taken to vary the speed of the motor, if necessary The system is operated under the control of the sequence control unit 18 which determines the required speed of the motor, e.g. for read, record or loading modes. The pulses from the tachometer are also used to increment a counter which is reset by a "home" pulse on a second track on the tachometer thereby producing position information signals. Stored data format.-Each data track on the drum 32 commences with a timing sector which consists of a series of timing pulses for synchronization purposes. A diagnostic pattern consisting of combinations of "0's" and "1's" and a track identification word respectively follow the timing sector. The track identification word is repeated and data follows. The data is divided into 16 data bit, two byte, segments each consisting of 8 data bits, a timing bit, 8 data bits, a timing bit and an error bit which indicates whether any of the bits in that segment are erroneous. After every 128, 16-bit data segments a 16-bit check sum in the same configuration as the data segments but representing error information is recorded. Alternatively cyclic check characters of any known code may be generated and used instead of or as well as the check sum. Track skew correction.-When a recording strip is loaded on the drum the abutting ends of the strip may not be precisely aligned and track registration may be lost. To compensate for this a read calibration mode is initiated and the optical head and carriage mechanisms are positioned to read a selected track. When a "home' pulse from the optical tachometer 56 is detected the system attempts to acquire a track within a specified period. Failure is indicated to the control panel 63 and the system initiates a further attempt on the occurrence of the next home pulse. If a track is acquired and synchronization between the recorded clock signals and the tachometer signals is achieved the track identification word and clock signals recorded on the first portion of the track are transferred to the data format control 20. This transfer occurs each time a "home" pulse is detected and the track identification words received are compared to test for track registration. If registration has not occurred correction data is fed to the track position servo control 42 or the carriage position control 40 as appropriate, the correction data being acquired from the difference between the track identification signals transferred to the format control 20 and used to control the system in operation. Axial offset, i.e. symmetrical displacement of the complete strip on the drum, is treated in the same fashion with the desired track identification being compared with that actually read out. Format control subsystem.-The format control system 20, Fig. 17, provides control of reading, recording, error detecting &c. operatio is. The buffer 250 and the data holding shift registers 260 provide intermediate storage for information being transferred to and from the laser memory. During recording input data is passed to the shift registers 261, 262 from where it is gated into a common serial bus to be passed to the character composing registers 271, 272. Logic 303 maintains a constant monitoring of the input data, each bit recorded being compared with the corresponding input bit and rerecording is initiated if an error is detected. On detecting an error the error bit at the end of the segment is recorded as a "1" and the whole segment is re-recorded. The parallel adder 281 and accumulators 282, 283 are used to compute the check sum segment by adding all the valid "1's" contained in each string of data segments. The error bits and timing pulses are interleaved with the input data by the counter 292 which halts for one count after 8 data bits and two counts after the next 8 data bits. The timing and error bits are loaded in theses space to produce the format described above. Media verification signals, i.e. signals indicative of faults in the recording strip 33, are obtained from the sum signal derived from the split beams produced in the data sensing means. These signals are also used to set the error bit as above. During reading the data is transferred from the verify register 263 to one of the shift registers 261, 262 if the error bit recovered from the data segment by circuit 301 prior to its accumulation in register 263 indicates an error free segment. If transfer occurs and the relevant shift register 261 or 262 becomes full, transfer is continued to the other register and a flag indicating that data transfer from the filled register may occur is set. If an error is detected the register 263 is cleared and the next segment is read out. The adder 281 and accumulators 282, 283 are used to compute the check sum segment, as before, which is compared with the check sum segment read from the memory to give additional verification. A serial-parallel interface is also described (Fig. 18, not shown) for converting theiinput data to serial and the retrieved data to parallel. Recorder Control subsystem.-The recorder control system 60, Fig. 20, is interfaced with the format control system and provides high-speed programme control of all the functions performed by the laser memory. The system includes an arithmetic section 460 used for modifying operands or the operand address of an instruction for controlling index addressing operations on the core memory 490. Holding registers 471 provide for operand, instruction &c. storage and are used to eliminate unnecessary addressing of the core store for operands &c. which are being used in any operation in order to increase processing speeds. The programme address register 481 holds current instruction addresses and is normally incremented by 1 or 2, but may be fed with a jump instruction from an addressed location in the store. After each instruction is accessed it is examined by the address control logic to determine its type and the appropriate operands are addressed by the holding registers 471. A control unit 500 includes an instruction register and instruction decoder 502 which decodes the instruction and ac