Patent GB-1010291-A (GB)
Title: Multiplying device
Inventor: DAVIES BEAUMONT JOHN
IPC: G06F7/68
Filed: 1960-10-26
Abstract: 1,010,291. Electric digital multipliers. G. RICHARDS & CO. Ltd. Oct. 25, 1961 [Oct. 26, 1960], No. 36793/60. Heading G4A. [Also in Division H3] In a multiplication circuit, the multiplier is set up in radix n (where n is not a power of 2) in binary coded form in a register comprising a plurality of radix n stages and a number equal to the multiplicand of cycles of pulses is applied to a multi-stage binary coded radix n counter, the register stages being arranged to control the passage to an output of pulses formed by the transistion of the counter binary stages from one of their stable states to the other. As described, the multiplier register 34 employs a binary coded decimal code in which the binary stages have the significance 5, 1, 2, 1, but other binary coded decimal codes may be used. For each desired addition of the multiplier a cycle of 100 pulses is applied at 11 to a binary coded decimal counter 12 having two decimal stages each comprising four binary stages 13-16 with feedback from the stage 16 to the stages 14, 15 so that the counter counts in the 2, 4, 2, 1 decimal code and the numbers of transistions from " 0 " to "1 " of the stages 13-16 are 5, 2, 1, 1 respectively. The outputs of the register stages 35-38 are connected together with the counter binary stage outputs 16, 14, 15, 13 respectively to AND gates 27, 25, 26, 24 respectively (see Division H3) and the outputs of the binary stages of the units decimal digit in the register 34 are similarly connected to AND gates 28-31 in the outputs to the binary stages of the tens decimal digit stage in the counter 12. The outputs of all the AND gates 24-31 are connected via an OR gate 22 to an output 23. When 100 pulses are applied to the counter at 11, a number of pulses equal to the multiplier set up in the register 34 appears at 23. A number of 100-pulse cycles equal to the value of the multiplicand is applied at 11 to produce a total of pulses representative of the product at 23. Application to control system, Fig. 3.-The circuit arrangement of Fig. 1 may be modified by using the same counter 12, Fig. 3, to supply two sets of AND gates 75 controlled by registers 78, 79. The outputs from the gates 75 are fed to two co-ordinate control systems 76, 77 which may be of the kind described in Specification 966,379 for the control of a machine tool. The systems 76, 77 control the and y co-ordinates of a moving point. To generate a straight line, numbers whose ratio represents the slope of the line are placed in the registers 78, 79 so that pulses in the desired ratio will be fed to the control systems 76, 77. To generate a circle, switches between the gates 75 and registers 78, 79 are closed. If pulses representing ## are applied to the counter 12, the registers 78, 79 which contain the slope ratio numbers proportional to cos #, sin #, where tan # is the slope, of the curve generated are supplied with pulses from the AND gates 75 representing ## sin #, i.e. - #(cos #) and ## cos #, i.e. #(sin #). Thus if the register 79 counts forward and the register 78 counts backward, the pulses supplied to the control system 76, 77 cause a circle to be generated. In order to make the controlled point move with constant velocity, the frequency of the input pulses to the counter 12 can be varied. Target counters 81, 82 which count backwards are preset in accordance with the desired coordinate difference between the start and finish of the generated curve or line. The counters 81, 82 can be used to cause deceleration of the generated point towards the end of the operation. The counter 12 can also be used to supply further circuits adapted to modify the generated results for a circle to avoid errors due to the cutter radius in a machine tool.