Patent EP-2363818-A2 (EP)
Inventor: BIANCHI RAUL ANDRES
IPC: H01L21/336
Filed: 2003-01-09
Abstract: The device for modelling an integrated circuit comprising at least one insulated-gate field-effect transistor, comprises the means for elaborating (MLB) a parameter representative of the mechanical constraints applied onto the active zone (ZA) of the transistor, and the processing means (MT) which are adapted to determine at least some electrical parameters (P) of the transistor by taking into account the constraint parameter The elaborating means (MLB) are adapted to define a useful active zone (ZAU) equal to a part or all of the active zone (ZA) of the transistor, and the constraint parameter is a geometrical parameter (a e q) representative of a distance counted in the direction of the length of the transistor channel and separating the transistor gate from the edge of the useful active zone. The processing means (MT) determine the electrical parameter (P) on the basis of a relation which involves the value of the electrical parameter determined for a reference distance, for example the minimum distance (a m i n) required of the active zone, the value of the constant parameter, the value of the reference distance, and a coefficient associated with the electrical parameter and dependent on the width (W) and the length (L) of the transistor channel. The processing means (MT) are adapted to compute the electrical parameter on the basis of the constraint parameter and by use of a basic simulation model (BSIM). The method for modelling an integrated circuit comprising at least one insulated-gate field-effect transistor is implemented by the device as claimed. The reference distance is the minimum distance (a m i n) required of the active zone, the electrical parameter (P) is defined by a relation comprising the value of the electrical parameter determined for the minimum distance, the coefficient associated with the parameter, the constraint parameter and the minimum distance. The device also comprises several reference transistors having different reference values (Wref,Lref) for the width and the length of the transistor channel, and different values for the constraint parameter. The processing means comprise the measuring means adapted to measure the value of the electrical parameter for each reference transistor, the first computing means adapted to compute the reference coefficient for each couple of the reference values (Wref, Lref), and the second computing means adapted to compute the coefficient on the basis of different reference coefficients. The electrical parameter (P) is, for example, the mobility of carriers at weak field and ambient temperature, the threshold voltage, and the drain/source resistance. Independent claims are also included for a method for implementing an integrated circuit comprising at least one insulated-gate field-effect transistor, and an integrated circuit comprising at least one insulated-gate field-effect transistor. The transistor is of type n-MOS when the constraint distance is greater than two times the minimum distance, or of type p-MOS when the constraint distance is less than two times the minimum distance.