Patent GB-1206663-A (GB)
Title: Improvements in transfer-storage stages for shift registers and like arrangements
IPC: G11C19/28
Filed: 1968-04-18
Abstract: 1,206,663. Digital electric shift register. SOC. INDUSTRIELLE BULL-GENERAL ELEC. TRIC. 18 April, 1968 [26 April, 1967], No. 18489/68. Heading G4C. A signal transfer-storage stage of the type comprising a transfer section having a binary signal input terminal and a storage section having at least one binary signal output, each of these sections being composed of a bi-stable circuit and these sections being interconnected and operative under control of a train of recurrent signals, is characterized by a first logical gate and a second logical gate, each of which comprises a logical inverting-circuit having a number of inputs and at least one output, a first input and an output of these gates being connected to effect the transfer of the state of the transfer bi-stable circuit, another input of each of the two gates being provided to receive a first systematically applied pulsed signal, and a third input of each of the two gates being provided to receive either a predetermined constant voltage level or a second pulsed signal applied after the first pulsed signal. The arrangement is as shown in Fig. 7, 10 being the transfer section, 12 the storage section and EI-3, EI-4 being the gates. The transfer section 10 is composed of NAND gate EI-1 AND gates ENI-1, ENI-2 and NOR gate OI-1. Using positive levels to represent " 1 " and negative levels to represent " 0 " a negative timing pulse T1 inhibits gate ENI-1 to put a " 0 " signal on line LI. An input signal D, from a preceding stage of a shift register enables or inhibits AND gate ENI-2 depending on whether the input signal is " 1 " or " 0 ". The gate receives a " 1 " from the inverted timing pulse. A " 1 " signal renders the output #M of NOR gate OI-1 negative. This output is fed to NAND gate EI-1 to produce a positive output M. Thus a " 1 " input produces a " 1 " at M and a " 0 " at #M. Similarly a " 0 " at D produces a " 0 " at M and a " 1 " at M. When the T1 signal is removed AND gate ENI-1 in the cross-coupling circuit helps to maintain the data stored. During the pulse T1 NAND gates EI-3, EI-4 are inhibited by the signal on inputs e2 and both have " 1 "s at their outputs. These fed to NAND gates EI-5, EI-6 for forming the storage flip-flop cause no alteration in the data. When T1 is removed NAND gates EI-3, EI-4 pass the signals stored in the transfer section to the storage section, since inputs e1 receive the signal, e2 receives the positive level of the timing pulse and, in one embodiment e3 receives a permanent positive voltage. In a second embodiment inputs e3 are connected to a source of pulses T2 occurring after the pulses T1 so that flip-flop 10 stores the data at the first pulse and gate 11 is enabled to pass the signal at the second pulse. The pulses must last for a sufficient time to account for time delays created by the NAND gates, e.g. if pulse D is applied at time t1 and T1 at t2, #T1 occurs at t3 and assuming the AND gates have no time delay L2 occurs at t3, M at t4 and M at t5, so T1 must last at least until t5 (see Fig. 3). The AND gate ENI-2 may be replaced by a plurality of AND gates each having a plurality of inputs so that a predetermined logical condition must occur before the gate can be enabled. Inputs SU and RU are used for setting and resetting the flip-flops respectively.