Patent GB-1184006-A (GB)
Title: Stored Program Electronic Data Processing System
IPC: G06F12/08
Filed: 1968-10-16
Abstract: 1,184,006. Data storage; computers. INTERNATIONAL BUSINESS MACHINES CORP. 16 Oct., 1968 [19 Oct., 1967], No. 49073/68. Headings G4A and G4C. In a stored-programme data processing system having main and backing storage, accessing of an operand is inhibited if it extends over more than one block (page) of storage until the whole operand is stored in the main storage. An instruction specifies the logical address (segment, page and byte) of the first byte of at least one operand, and the number of bytes in the operand. The logical address of the first byte is sent to a dynamic address translation unit from the (or one of the) processor(s) and the segment and page portions are used to interrogate an associative store. If a match is found (this implies that the page containing the first byte is in main storage), the page portion of the actual physical address is read from the associative store and appended to the byte portion of the logical address to address main storage, unless the instruction is of a type which could give rise to trouble if the operand crossed a page boundary. In the latter case, the segment and page portions of the ending logical address (i.e. end of operand) are obtained by adding portions of the logical address and other portions of the instruction, the sum being saved in a sum register. If a high-order carry is produced in the addition, it indicates the operand crosses a page boundary (it is assumed that no operand occupies parts of more than two pages, i.e. crosses more than one page boundary). In the absence of a carry the associative store &c. is used to address the first byte as before. In the presence of a carry, the segment and page portions of the ending logical address (from the sum register) are used to interrogate the associative store and if a match is found (implying the ending page is in main storage), addressing of the first byte in main storage proceeds as before. If either of the interrogations of the associative store mentioned produces no match, the segment portion of the appropriate logical address is compared with the length of a segment table. If this indicates the segment table contains an entry for this logical address the segment portion of the logical address is added to the segment table origin address to address main storage thus obtaining an entry in the segment table. This specifies the origin address of a page table and the page table length. The latter is compared with the page portion of the logical address and if the result indicates the page table contains an entry for this logical address, the page portion of the logical address is added to the page table original address to address main storage thus obtaining an entry in the page table. This gives a physical page address which is inserted into the associative store together with the segment and page portions of the logical address, replacing the oldest entry. Interrogation of the associative store as before now gives a match and operations proceed as before. If either of the comparisons with a table length indicated the absence of an appropriate entry in the table, the processor is signalled to transfer the page from backing storage to main storage and update the tables, and after this is done, interrogation of the associative store &c. follow as before. (If the processor chooses to postpone these transfer and update operations, the dynamic address translation unit can be used for dealing with other instructions in the interim in the same way.) The processor sends in turn the addresses of the remaining bytes of the operand which are each used to interrogate the associative store as before, giving a match. Calculation of the ending address &c. is not done again, the associative store providing the page portion of the physical address, the byte portion being the byte portion of the logical address as before.