baber/WOPTO huggingface dataset:
Patent JP-H01163924-A (JP)
Title: Lightening insulator
Inventor: NAKAYAMA TETSUYA
IPC: H01T1/15
Filed: 1987-12-19
Abstract: PURPOSE:To reduce the thickness of an insulating pipe and to make a lightening insulator in a compact size by melting and breaking pressure release plugs and releasing the pressure rapidly when a current limit element is made into a conductive condition and an arc is generated. CONSTITUTION:At an enclosed space R of an insulating pipe 1, a current limit element 6 with the nonstraightness of voltage current property is accommodated with a specific interval to the inner periphery surface. And between insulating pleats 1a and 1a of the insulator pipe 1, pressure release holes 1c are formed, and at the pressure release holes 1c, rubber pressure release plugs 15 are geared airtight and connected with an adhesive. Since an insulating gas is enclosed in the space R between the insulator pipe 1 and the element 6, a high voltage arc breaks or melts the pressure release plugs 15 rapidly and the arc is released outward, even when a lightening surge current is applied to the element 6, and a high temperature and high voltage arc is generated. Consequently, the thickness of the insulator pipe 1 main body can be reduced.
Patent JP-H10164442-A (JP)
Title: Correlated double sampling circuit
Inventor: TAZAWA HITOSHI
IPC: H04N5/335
Filed: 1996-12-02
Abstract: PROBLEM TO BE SOLVED: To realize a correlated double sampling(CDS) over a broad band with good noise elimination characteristic. SOLUTION: A current differential DC amplifier 6 is interposed to an input side of a correlated double sampling section 7 that samples a reference level and an image signal level of an output signal Vo of a solid-state image-pickup element 8 respectively and eliminates a noise component of a reset noise or the like by subtracting both the levels. Since a DC coupling is adopted, determination of noise superimposed on the output signal Vo is made quickly and the correlated double signal sampling section 7 has a high noise elimination effect, even when a drive frequency of the solid-state image-pickup element 8 is high. The gain is adjusted by a variable resistor Rc and a DC level of an output node ND depends on a reference voltage source Vref and hardly fluctuates.  Moreover, the correlated double sampling circuit is configured by a cascode amplifying circuit consisting of TRs Q3 , Q4 and applicable over a wide frequency band.
Patent JP-2001142852-A (JP)
Title: Synchronism and communication control device for high- speed parallel computation
Inventor: SEKIGUCHI TOMOTSUGU
IPC: G06F3/00
Filed: 1999-11-12
Abstract: PROBLEM TO BE SOLVED: To provide a synchronism and communication control device for high-speed parallel computation, which enables the scalability to be improved and synchronism and communication processing of low latency to be performed. SOLUTION: It is made to have a structure capable of easily extending a synchronism/communication network, by packaging a new synchronizing mechanism, by merging a synchronizing signal and a communication signal and making synchronizing processing and communication processing into hardware, synchronism and communication processing of low latency is performed. Since synchronizing processing is made to be a hardware and the synchronizing signal is directly sent to a network, the network is switched for synchronizing processing and data processing. In synchronizing processing, the number of synchronizing codes is reduced, the kinds of synchronizing codes are reduced and a synchronizing mechanism for improving debugging efficiency is packaged. Data transfer is limited to the packet of a small data amount, a packet size is fixed and each of transactions is processed by the hardware.  All functions for synchronism and communication processing are settled within one chip and the length of a transmission cable is shortened.
Patent JP-H08181203-A (JP)
Title: Manufacture of soi substrate
Inventor: MAEDA MITSUHIDE
IPC: H01L21/76
Filed: 1994-12-26
Abstract: PURPOSE: To facilitate inter-element isolation in the lateral direction, and to improve an integration by a method wherein an isolation trench reaching an inter-substrate oxide film from the main surface of a silicon substrate is formed, oxide films are formed on the side faces of the isolation trench, the inside of the trench is filled with polycrystalline silicon and the single crystal of silicon is grown on the main surface of the substrate. CONSTITUTION: Trenches 12 reaching an inter-substrate oxide film 9 are made on a silicon substrate 10, and a surface is oxidized to form oxide films 13 on the bases and side faces of the trenches 12 and the surface of the substrate 10. The oxide films 13 are left only on the side faces of the trenches 12 through dry etching, and silicon is grown in an epitaxial manner and silicon is grown on the surface of the substrate 10 and polycrystalline silicon 14 on the oxide films 9 on the bottom sections of the trenches 12 and the oxide films 13 on the side faces. Oxygen is driven into the polycrystalline silicon 14, and oxide films 17 are formed through heat treatment. Accordingly, inter-element isolation in the lateral direction is executed easily and surely, thus improving an integration degree.
Patent JP-H01289785-A (JP)
Title: Rear arm of motorcycle
Inventor: SUZUKI YASUHITO
IPC: B62K25/10
Filed: 1987-12-18
Abstract: PURPOSE:To prevent sticking of a large amount of mud splashed over from the ground by having a rear arm comprising two arm parts projected backward from a box-shaped base end which is provided with a through-hole, for use in a connecting member, the inner face of which has a cylindrical wall face formed. CONSTITUTION:In a motorcycle, a rear arm 4 supporting a rear wheel is pivotally supported by a supporting shaft 5 at the rear part of a body frame 2 in a free oscillation, and is also connected via a linkage mechanism 6 and a shock absorber 7 which are installed at the lower part thereof to the upper part of the body frame 2. In this case, the rear arm comprises a base end 4a formed in a box shape and two right and left supporting arms 4b extended backward therefrom to insert a wheel shaft through transmissive holes 4c in the tips of the supporting arms 4b for supporting a rear wheel. Also, in the base end 4a of the rear arm 4 is formed a circular communicating hole 4e which penetrates from top to bottom at the position in between two right and left supporting arms 4b to rigidly fit in this hole a cylindrical covering member 4f made of a synthetic resin for locating extensively a shock absorber 7 therein.
Patent JP-2001138528-A (JP)
Title: Ink jet recording head
Inventor: YAMAMOTO KOJI
IPC: B41J2/055
Filed: 1999-11-12
Abstract: PROBLEM TO BE SOLVED: To provide an ink jet recording head high in reliability by easily reducing the stress generated at the bonded interface of a nozzle plate and a base plate after bonding. SOLUTION: When a center plate 301 made of stainless steel and a nozzle plate 303 made of nickel are bonded by using a thermosetting adhesive 501, a square slit part 302 is provided at the bonded interface of the center plate 301. By this constitution, the shearing stress generated in the bonded interface end part is absorbed and relaxed from a difference in the coefficient of thermal expansion and stress relaxation of about 20-30% can be realized.
Patent JP-H11217144-A (JP)
Title: Image forming device and sheet conveying device
Inventor: MAETANI MASAMI
IPC: G03G15/00
Filed: 1998-11-12
Abstract: PROBLEM TO BE SOLVED: To prevent the reverse rotation of a sheet from being impeded caused by an accumulated sheet, and excessive load from being applied to a normal and reverse rotating roller pair, by providing a slit-like opening provided on an outer cover in the approximately horizontal direction and an inclined path for communicating the slit-like opening and the lower part of a reversing paths with one another. SOLUTION: An image forming device provided with stacking means 2a to 2f for staking sheets S for image forming, an outer cover 42 for surrounding the peripheries of the sheet stacking means 2a to 2f, and approximately vertical reversing paths 29, 40 arranged on each one sides of the sheet stacking means 2a to 2f and for reversing the sheet is provided with a slit-like opening 42a provided on the outer cover 42 in the approximately horizontal direction and an inclined path for communicating the slit-like opening 42a and the lower part of the reversing paths 29, 40 to one another.
Patent JP-H03183025-A (JP)
Title: Optical disk device
Inventor: KAYANUMA KINJI
IPC: G11B7/0045
Filed: 1989-12-11
Abstract: PURPOSE:To obtain an optical disk device with high recording density by providing a recording circuit, a reproducing circuit, a reference waveform generating circuit and a recording waveform control circuit. CONSTITUTION:In a variable recording waveform generating circuit 1, a train with pulse width corresponding to recorded data is outputted by a pulsing circuit 7, and a recording waveform is generated through a delay element 8, a multiplier 9 and an adder 10. A recording circuit 2 makes a recording pit onto a recording medium 3. It is transmitted from a reproducing circuit 4 to a timing detection circuit 16 of a reference waveform generating circuit 6 and the recorded data are taken out from a data buffer 14 synchronously with a reproducing signal. Further, the waveform of the data is shaped by a filter 15 and a reference waveform is obtained. In a recording waveform control circuit 5, the reference waveform is delayed 8 and difference from the reproducing signal is calculated by an adder 13. Then, the difference and the delayed reference waveform are multiplied 12 and added to an integration value set by an integration circuit 11 in advance. An integration period is controlled by the timing detection circuit 16 and a reproducing waveform is applied so as to be extremely similar to the reference waveform. Thus, when the recording waveform is compensated by such a feedback system, optimum recording power and waveform can be obtained and high recording density can be obtained.
Patent JP-H09136303-A (JP)
Title: Stapler
Inventor: YAMANUSHI SATOSHI
IPC: B27F7/17
Filed: 1995-11-16
Abstract: PROBLEM TO BE SOLVED: To surely allow a bundle of sheets to enter a binding position and to discharge the bundle of sheets after binding in a short time by the constitution in which a head unit and a clinch unit can move freely forward/backward to/from the transfer route of the bundle of sheets while both units being separated. SOLUTION: An apparatus is equipped with an anvil 110 which is supported to be able to move between a waiting position separated from a head unit 18 and an actuation position brought close to the head unit 18 from the waiting position and a clinch driving mechanism 130 which transfers a head 74 and the anvil 110 to the waiting position when a bundle of sheets comes between the head unit 18 and a clinch unit to guide the bundle of sheets to a staple position and transfers them to an actuation position in a state in which the bundle of sheets is brought to the staple position to hold the bundle of sheets between the head unit 18 and the clinch unit.
Patent JP-H02166904-A (JP)
Title: Compound frequency synthesizer
Inventor: YAMAZAKI TOYOE
IPC: H03B21/00
Filed: 1988-12-21
Abstract: PURPOSE:To improve a phase-to-noise characteristic and to accelerate response speed by setting the frequency step of a second frequency synthesizer at the sum of the frequency step of an output frequency and that of a first frequency synthesizer. CONSTITUTION:The first frequency synthesizer 1 with the frequency step fs1 is provided with a reference oscillator 5, and the second frequency synthesizer 2 with the frequency step fs2 is provided with a reference oscillator 6. At this time, the frequency step fs2 of the second frequency synthesizer 2 is set at the sum (fs2=fs1 +DELTAf) of the frequency step DELTAf requested in output and the frequency step fs1 of the first frequency synthesizer 1. Thereby, it is possible to set the loop gain of a phase locked loop and a phase comparison frequency at the frequency synthesizer 2 at high levels, and to improve the noise suppression characteristic and the stability of the loop, and to accelerate the response speed.
Patent JP-H08177210-A (JP)
Title: Tile
Inventor: ISHII AKIRA
IPC: E04F13/08
Filed: 1994-12-26
Abstract: PURPOSE: To arrange the sides of adjoining tiles in parallel during various joint plans and to improve alignment of joints. CONSTITUTION: A tile 3 is a square having sizes substantially equal to each other and two protrusions 4 and 5 are formed on each of the sides. The protrusion parts 4 and 5 are both formed in a trapezoidal shape in plan-view. On each side of the tile, the protrusion parts 4 and 5 are positioned on the opposite side to each other on both side of the intermediate point. Distances (a) and (b) from the nearmost apexes of the protrusion parts 4 and 5 are substantially equal to those of other sides. The widths of the protrusion parts 4 and 5 are also substantially equal to each other. Arrangement of the protrusion parts 4 and 5 are arranged point-symmetrical with respect to the central point, of the main plate surface of the tile 3.  When the protrusion parts 4 and 5 of one side are projected on a mating side, the projected protrusion parts 4 and 5 are not overlapped with the protrusion parts 4 and 5 of a mating side.
Patent JP-H04196723-A (JP)
Title: Pwm controller
Inventor: ISOBE YOSHINORI
IPC: H02P7/29
Filed: 1990-11-28
Abstract: PURPOSE:To prevent a malfunction at a high speed clock by forming a PWM output signal with a 2nd control data extracted from a latch means in response to a data set signal, a counting output data from a down--counter and the data set signal. CONSTITUTION:A data set signal line 13 is connected to the control signal input terminal of a waveform shaping circuit 5, and a part of signals of a data latch 6 is inputted to the circuit 5 through a signal line 14. Thus, the circuit 5 generates a PWM output in response to the signal on signal line 11-15 and outputs the PWM signal to a PWM signal output terminal 17 through a signal line 16. A signal line 13 is connected to a down-counter 3, an up-down control circuit 1 and a data set signal input terminal of the data latch circuit 6, and the circuit 6 receives a control data for a CPU 7 via a signal bus 18 and transmits it to the circuits 5, 1 through data buses 14, 19. Thus, no malfunction is caused at a high speed clock.
Patent JP-H11160829-A (JP)
Title: Treatment of silver halide photographic sensitive material
Inventor: TSUKADA KAZUYA
IPC: G03C5/29
Filed: 1997-11-25
Abstract: PROBLEM TO BE SOLVED: To provide a treating method by which contamination of residual colors and irregular drying are not caused even when a photosensitive material is treated with a boric acid-free developer. SOLUTION: This photographic material contains at least one kind of compd. selected from org. acids or their salts having 0.8 to 4.0 chelate stability const. for calcium. The developer and the fixing liquid in the treating process do not substantially contain boric acid or its salt. It is preferable that the photographic material contains planer silver halide particles having >=20 mol.% silver chloride content and contains a specified carbocyanine. The developer contains a reduction and the treatment is carried out with <=200 ml replenishing amt. for the treating liquid for <=30 sec treating time.
Patent JP-H11163917-A (JP)
Title: Electronic mail equipment
Inventor: MAENO TAKAHIRO
IPC: H04L12/58
Filed: 1997-11-25
Abstract: PROBLEM TO BE SOLVED: To set the mail address of a transfer destination even in the case that a mail user does not know the details of n electronic mail equipment to be used in another place by replacing information on the place or the area of science list with an electronic mail address corresponding to the received schedule list. SOLUTION: When a reservation request mail which is forwarded from a mailing list server 103b is received, servers 103c and 103d which can receive a reservation inspect the schedule list of a text and judge presence or absence of an entry including the area to be assigned. When the requested reservation can be received, a reservation address is extracted and added to the entry. Then, the generated new entry is added to a reservation list and also reservation return mail with the new entry as the text is transmitted to a return address. A mailer 102a extracts the entry in the text at the time of receiving the reservation return mail and replaces the applying entry in the schechule list with it.
Patent JP-H09155217-A (JP)
Title: Garbage treating device
Inventor: KUSAKABE TAKESHI
IPC: E03C1/266
Filed: 1995-12-12
Abstract: PROBLEM TO BE SOLVED: To separate water and general waste water and to activate the switch of a garbage pulverizing section by the operation of the cap of a waste water and garbage feed section. SOLUTION: This garbage treating machine has a draining cage 6 in the upper part and the garbage pulverizing section in the lower part. The waste water and garbage feed section 2 is provided with the freely attachable and detachable cap 3 in the upper part. This draining cage 6 is provided with a water pass hole 9 and valve 8 for opening and closing this water pass hole 9. The waste water and garbage feed section 2 is provided with a reed switch 11 for making and breaking the power source of the garbage polarizing section 12. The make and break of the valve 8 and the make and break of the reed switch 11 are executed by the rotating operation of the cap 3.  The switching of the water passages and the make and break of the switch are executed by the same operation and, therefore, the neglect in switching of the water passages does not arise and the fail-proof sepn. of the garbage from the general living waste water is assured.
Patent JP-2001136897-A (JP)
Title: Method for producing dough for cake
Inventor: FUJISHIMA NOBORU
IPC: A23G3/50
Filed: 1999-11-12
Abstract: PROBLEM TO BE SOLVED: To produce a dough for a cake excellent in taste. SOLUTION: The dough for the cake is produced by formulating a highly branched cyclodextrin.
Patent JP-S63171549-A (JP)
Inventor: TEYUNISU ROBERUTO FUAN HEERUSU
IPC: G01R33/32
Filed: 1987-12-22
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H09155687-A (JP)
Title: Frame for fixing mask
Inventor: SAKAMOTO SUSUMU
IPC: G03F1/66
Filed: 1995-12-12
Abstract: PROBLEM TO BE SOLVED: To provide a frame for fixing a mask to suppress expansion and contraction of a mask fixing frame or a member for fixing a mask due to the temperature of related environment during manufacture of a mask or during the use of a mask. SOLUTION: A heating medium circulation passage comprising flow passages 18a and 18b to circulate a given temperature heating medium along the peripheral edge part of a mesh 16; and a coupling hole 24 is arranged in a pipe 18 of which a frame 10 for fixing a mask consists. Thereby, during exposure and when the temperature of environment in which a plate 12 is placed is changed, by properly setting the temperature of a heating medium circulating through the heating medium circulation passage, the temperature of the frame 10 for fixing a mask is kept at a constant value and the occurrence of expansion and contraction due to an environment temperature difference is suppressed. This constitution suppresses the occurrence of a fact that a tension exerted on a mesh 16 is brought into an improper state due to expansion of the frame 10 for fixing a mask, and lowering of pattern precision.
Patent JP-2000201102-A (JP)
Title: Estimation of channel for space time block coding transmission antenna diversity of wcdma
Inventor: DABAK ANAND G
IPC: H04B1/707
Filed: 1999-10-07
Abstract: PROBLEM TO BE SOLVED: To supply the diversity of at least 2L over the time and a space and to improve the estimation of a channel by providing a correction circuit which generates the 1st and 2nd symbol estimation value in response to plural pieces of estimation signals and input signals, respectively. SOLUTION: A phase correction circuit 350 receives the input signals Rjm and Rjn on the lines 324 and 326 corresponding to the symbol time included in the same time slot as a pilot symbol that is used for estimation value of a channel. The circuit 350 also receives the channel estimation value of Rayleigh fading parameters αj1* and αj2 corresponding to the 1st and 2nd antennas on the lead wires 302 and 306, respectively. The conjugate complex numbers of the input signals are generated on the lead wires 310 and 332 by the circuits 308 and 330, respectively. These input signals and complex numbers are multiplied by the parameters and added together to generate the symbol estimation value specific to the paths on the output lead wires 318 and 322.  Then these generated symbol estimation value are applied to a rake combinational circuit to produce a net soft symbol or a pilot symbol signal.
Patent JP-H07290812-A (JP)
Title: Printing method
Inventor: HILL GEORGE ROLAND
IPC: H05K3/46
Filed: 1994-12-26
Abstract: PURPOSE: To obtain a printed matter with matched layers easily and with high accuracy by removing an unnecessary part by a force acting upon a printed layer so that the peripheral edges of the printed layer mutually coincide with each other. CONSTITUTION: A masking material 4 is printed on the surfaces of a substrate material 2 and regions 12, 14, 16 are exposed in such a state as required by a final printing design on the substrate material 2 while maintaining a specified geometrical relationship. The substrate material 2 and the surface of a mask 4 and some areas of the surfaces of the desired final designs 12, 14 are covered with an ink layer 6, and only the region 16 is covered with another ink layer 18. In addition, above this ink layer 18, two layers of ink, three layers of ink and a one layer of ink are formed in the regions 12, 14, 16, in such a state that these layers are correctly matched. This layer matching is achieved by removing the masking material 4 and ink right above the former.
Patent JP-H11159036-A (JP)
Title: Work execution structure body of plate glass
Inventor: WAKUI SATOSHI
IPC: E04B2/90
Filed: 1997-11-25
Abstract: PROBLEM TO BE SOLVED: To restrain damage of rib plate glass by an earthquake by fixing a displacement tuning member inserted into upper and lower end parts of butting parts of adjacent face plate glass, to fixing frames. SOLUTION: A displacement tuning member 9 is arranged in an upper and part and a lower end part of butting parts of adjacent face plate glass 1, and the member 9 is fixed to fixing frames 6 and 7. Next, when a building frame 5 inclines so that the fixing frame 6 is displaced to the left C side and the fixing frame 7 is relatively displaced to the right D side by an earthquake, since interlayer displacement is caused between the fixing frames 6 and 7, almost equal interlayer displacement is also caused between upper and lower parts of rib plate glass 3. Next, an upper end part of a right D side edge part of the glass 1 is displaced to the left C side by being pressed by the member 9, and a lower end part of the left C side edge part of the glass 1 is displaced to the right D side by being pressed by the member 9, and almost equal interlayer displacement is caused. Since large bending stress caused by a difference in a displacement quantity between the glass 1 and 3 does not act on upper and lower part vicinity parts of the glass 3, damage of the glass 3 can be restrained.
Patent JP-H11164335-A (JP)
Title: Matrix switch method and device therefor
Inventor: SUZAKI TETSUYUKI
IPC: H04J3/06
Filed: 1997-11-25
Abstract: PROBLEM TO BE SOLVED: To exchange plural parallel input data at a high speed. SOLUTION: In the case that input data 41 are exchanged so that the data are given to a D flip-flop 2N by an N:N switch 3A via a clock extract section 11, a clock signal 11C from the clock extract section 11 is controlled to be given to the D flip-flop 2N by an N:N switch 3B. Thus, in the D flip-flop 2N, the timing of the input data 41 is recovered by a trailing of the clock signal 11C from the clock extract section 11 and the result is outputted as output data 5N.