Patent GB-878937-A (GB)
Title: Improvements relating to pulse generating circuit-arrangements
Inventor: ROBINSON NIGEL DAVID
IPC: G06F7/68
Filed: 1957-01-16
Abstract: 878,937. Pulse generator circuits. ELECTRIC & MUSICAL INDUSTRIES Ltd. Jan. 15, 1958 [Jan. 16, 1957], No. 1575/57. Class 40(6) In an arrangement for generating a group of pulse trains from a master pulse train a number of pulse trains each having a different frequency ratio to the master train are generated and are then applied to gates the outputs from which constitutes the required trains, spurious pulses being cancelled by inhibiting the gates during predetermined intervals. Fig. 2 shows a pulse generating circuit comprising a series of trigger circuits 4, 6, 8, each of which are successively triggered to their alternate states by a narrow pulse input and which also comprises "end of pulse gates" 5, 7, which each generate a narrow pulse train output corresponding to the end of each pulse of a train of broad input pulses. Thus on applying a train of narrow pulses "a" to the binary trigger 4 pulse trains 1, 2, 3, Fig. 3, are generated at output leads 1, 2, 3. Each pulse train, for example the train 1, is slightly phase displaced with respect to the train "a" due to the finite triggering time of the trigger circuit. The pulse trains 1, 2, 3 are then applied to a number of logical gating circuits 9, 10, . . . 16 which operate to produce an output in accordance with a predetermined relationship between the associated inputs. Thus, for example, gate 9 produces an output pulse train b0, Fig. 3 only in response to inputs "not 1", "not 2", and "not 3". Fig. 4a shows a pulse generator according to the invention in which the logical gates comprise a diode matrix to the input leads 17, 19 and 21 of which the pulse trains 1, 2, 3 are applied and the corresponding complementary or "not" train being applied to inputs 18, 20, 22. The required output pulse trains b0, b1 . . . b7, Fig. 3 are derived from the output leads 32, 33 . . . 39 Fig. 4a. The diode logical gating circuit operating for example to produce output b0 only on coincidence of the three states "not 1", "not 2", and "not 3", the associated diodes under these conditions being nonconducting to produce an output at line 32. The unwanted short pulses which appear in the pulse trains b0, b2, b4, b6, Fig. 3, are inhibited by applying a "not a" input to each of the gates 9, 10 . . . 16, Fig. 2, derived for example by applying the a pulse train to the tube V, Fig. 4a, the output from which is applied to supplementary diodes connected to each of the output leads 32, 33 . . . 39. In a modification shown in Fig. 5 pulse trains 1, 2, 3 are derived from bistable trigger circuits 4, 6, 8 and gates 5, 7 as described with reference to Fig. 2. The pulse output 1 is also applied to a series combination of a "beginning of pulse gate" 41, trigger 42, 'beginning of pulse gate" 43, trigger 44. The outputpulse trains 1, 2, 2<SP>1</SP>, 3, 3<SP>1</SP>, are then applied to logical gating circuits 9, 10 . . . 16, and produce output pulse trains b0, b1 . . . b7, as shown in Fig. 3. In this embodiment the unwanted short pulses do not appear in the pulse trains b0, b2, b4, b6.