Patent GB-1354527-A (GB)
Title: Semiconductor devices
IPC: H01L27/07
Filed: 1971-06-17
Abstract: 1354527 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 17 June 1971 [20 June 1970] 28441/71 Heading H1K A semi-conductor integrated circuit (Figs. 1, 2) comprises a wafer 1 incorporating transistors T 1 , T 2  having zones 4, 5, 6, and 7, 8, 9 mutually separated by insulation zone 2 and each comprising groups of three alternate conductivity zones of which zones 6, 9 underlie zones 5, 8 which underlie zones 4, 7; the pairs being of respectively similar conductivity types. Zone 5 also comprises part 10 between zones 14 and 6 and a coherent cup shaped part 2 surrounding zone 6, together co-operating with zone 9 of T 2  to form a surrounding insulant PN junction 11 for transistor T 1 . Transistor T 2  also comprises three successive zones of alternate conductivity types with dopant concentration in the centre zone exceeding that in the surrounding outer zone. The control zone forms an insulating PN junction round the transistor with the collector zone. The substrate operates as a common collector (or emitter) for plural transistors of a given type and further insulated transistors may be used. Transistor T 2  is of transversal bipolar type with first emitter zone 7 surrounded by second base zone 8; the collector being zone 9. T 1  is also bipolar with emitter (or collector) zone 4, base zone 10, 2 and collector (or emitter) zone 6 respectively. It may also be an FET with annular zone 4 as gate, and the source and drain formed by the parts of 10, 2 situated inside and outside the annulus, while zone 6 forms a second gate. Zone 10 may alternatively be in two parts coherent over a channel, permitting zone 4 to laterally overlap zone 10 and cohere with zone 6. In bipolar transistor T 1  zone 6 is separated from the substrate by base zone 10, 2 so that stray transistor action is avoided. The insulant PN junction 11 forms a simple diode which is reversed biased automatically, and the base-collector junction of T 1  comprises parts 12, 13 to form a diode in parallel with the base-collector junction 12 to prevent bottoming (Fig. 3 not shown). The collector zone 9 of T 2  is a substrate 9a of a one conductivity type on which is superimposed an epitaxial layer of a similar conductivity type; the cup shaped zone 2 having a surface zone 2a of opposed conductivity type surrounding part 6 of epitaxial layer 9b at the surface and extending to a region 2b of opposed conductivity type at the boundary of layers 9a, 9b; the zone 2a forming a circumferential wall of the cup of which buried region 2b is the bottom, and part 6 of the epitaxial layer within the cup is the collector of T 1 . The resistivity of substrate 9a is lower ohmically than the epitaxial layer 9b, and collector zone 6 may have a control zone 14, while substrate 9a is connectible to another remaining circuit element over a conductive track through an aperture of the insulant layer to contact zone 15. The collector of T 1  has a buried part 16 to reduce its series resistance and the remaining semi-conductor zones are connectible to other circuit elements over conductive tracks through the surface insulating layer 17. In a modification (Figs. 4 to 6, not shown) of differing geometry the cup shaped insulant part of the base zone is connected to the collector zone over a conductive track extending through an aperture of a surface insulant layer; so as to form a Schottky diode junction between the base and collector zones. In a further modification (Fig. 7) a substrate 40 has a two part composite epitaxial layer 41, 42 on a substrate 40 containing emitter zone 44, base zone 45, 46 and collector zone 47 of a first self insulating transistor separated by insulating PN junction 48 from a second similar transistor having emitter zone 49, base zone 50 and collector zone 40 to 43. A further insulated complementary transistor is provided having emitter zone 51, base zone 52, and collector zone 53; the latter being cup shaped to form an insulant PN junction 48 with collector zone 40 to 43. Cup shaped zones 46, 53 are coherent to connect the transistors in cascade (Fig. 8, not shown). Collector zones 47 and 40 to 43 have buried parts 54 and 43 to reduce collector series resistance, and contact zones 55, 56 are provided in collector zone 47 and base zone 52. In manufacture the substrate 40 is of N silicon masked with an oxide layer having apertures etched over photoresist. This is thermally doped with B to form the buried insulation zone after which the N epitaxial layer 41 is grown, and into this As or Sb is thermally doped to form the buried parts 43, 54 during which the buried B zone diffuses into layer 41. Further B is thermally diffused from the surface into regions surrounding part of the epitaxial layer to define the walls of the cup shaped region 46, and regions 45, 50, 51 are formed by further surface thermal diffusion of B. Emitter zones 44, 49 and control zones 55, 56 are formed by thermal diffusion of P and thermal annealing, while diffusion of B from the buried zone continues until a closed cup shaped P conductivity zone 46 is formed at the upper surface of the epitaxial layer. B or As doping may be used in the buried part covered by zone 54 and A1 or P doping at the edge of the buried part. The several surface zones may be contacted through etched apertures of the surface insulant layer by vapour deposited A1 etched to pattern, and the device may be encapsulated. Alternatively doping may be by ion implantation from the surface. The substrate may be Ge or A<SP>III</SP>B<SP>v</SP> and the insulant of Si 3 N 4 , Al 2 O 3  or combination thereof with SiO 2 , while the conductive layers may be of Mo or composite TiPtAu. The contact zones are replaceable by PtSi contacts. Diodes may be provided by introducing additional cathode zones relative to the insulant zones as anodes. The devices of Figs. 1 and 2, 4, 5 and 6 may be produced by similar methods. In a further modification a multitransistor gate circuit (Figs. 9 to 13, not shown) is constructed using a semi-conductor body 70 on a low ohmic substrate overlain by an epitaxial layer of similar conductivity type and higher resistivity defining a common collector zone for the transistors. Plural parallel signal input transistors having distinct base and emitter zones receive input signals over metallic tracks applying a surface insulant layer which are connected through apertures to the several base zones. The emitter zones are connected in common over a further metallic track to the base zone of the gate input transistor whose emitter zone is surrounded by a cup shaped insulant region forming a PN junction with the common collector zone. The collector zone of this transistor is provided with a control zone and is surrounded by coherent base zones extending parallel to the surface; the zone being partially or completely annular, with a projection extending to form a resistive connection for the base zone, which may have other similar resistive connections; the latter being connected to metal tracks over apertures of the insulant layer. Similar insulant zones and resistive connections connected to overlying metal layers are formed for subsequent transistors of the gate and the transistors may have buried low ohmic zones thereunder extending along the layer interface to reduce collector series resistance. Specification 1,349,101 is referred to.