Patent GB-1024427-A (GB)
Title: Improvements in or relating to automatic frequency control
Inventor: DEARNLEY JOHN DEAN
IPC: H03L7/113
Filed: 1962-03-29
Abstract: 1,024,427. Automatic frequency control systems. PLESSEY CO. Ltd. March 29, 196<SP>3</SP> [March 29, 1962; May 1, 1962], Nos. 12086/62 and 16569/62. Heading H3A. An electrical oscillation generator comprises a standard frequency source; a slave oscillator of frequency variable over a required range; means for producing from the outputs of the standard frequency source and the slave oscillator corresponding pulse trains so related to the output frequencies of the standard frequency source and the slave oscillator respectively that their repetition frequencies are identical when the output frequencies are in a required relationship with each other; a frequency control circuit responsive to the two pulse trains and arranged to vary the frequency of the slave oscillator in such a manner that the difference in the repetition frequencies of the two pulse trains tends to zero; and a phase control circuit for fine tuning. The standard frequency source may comprise a crystal-controlled master oscillator (not shown) feeding a digital frequency divider (not shown) operating at a fixed division ratio to produce pulses on the line 3, Fig. 2, at a rate equal to a sub-multiple of the master oscillator frequency. A slave oscillator 4 is adapted to operate at various multiples of the frequency of the pulses on line 3 and feeds a digital divider 6 of adjustable division ratio, the arrangement being such that the frequency of pulses in line 7 is the same as that of pulses in line 3 when the oscillator is correctly tuned. The two sets of pulses are fed to identical units 11 and 12 which produce widened pulses on lines 11a and 12a, and delayed pulses on lines 11b and 12b leading to a bi-stable device 13. A pulse on line 11b puts device 13 into one condition, thereby opening gate 14, closing gate 15, and conditioning counter 17 to count in a forward direction; whilst a pulse on line 12b reverses the condition of device 13 to open gate 15 and close gate 14, and conditions counter 17 to count in a reverse direction. If the pulses are of the same frequency each pulse arriving on line 11b or 12b will find its respective gate closed; if there is a difference in the two frequencies, two pulses will sometimes appear on one line between successive pulses on the other line, and the second pulse will pass through the gate opened by the first pulse to the reversible binary counter 17, each step of which varies by one unit the reactance of a switched reactor set 18 forming part of the tuning circuit of oscillator 4. Spurious pulses may appear if pulses on lines 11b and 12b succeed each other too closely, and in such a case a coincidence detector 19 detects coincidence of the widened pulses on lines 11a and 12a and closes the inhibit gate 21. Each stage of binary counter 17 may be associated with a capacitor of appropriate size and may be adapted to switch the capacitor into circuit by rendering conductive a transistor placed in series with the capacitor, Fig. 3 (not shown). The most significant stage of the counter may be adapted to switch an extra inductance into the tuning circuit, Fig. 4 (not shown). Automatic phase control.-The pulses on line 3 of Fig. 2 are also fed to a sawtooth generator 51, Fig. 5, the output of which is sampled in units 52 at instants determined by the pulses from divider unit 6. If the two pulse trains are in phase the output of unit 52 is a unidirectional voltage of constant level. If the pulse trains differ slightly in frequency the output is a sawtooth waveform of " staircase " profile, and this signal is applied to a variable reactance device 50 to adjust the frequency of oscillator 4. A low-pass filter 54 is normally included in the circuit to reject components corresponding to the pulse repetition frequencies. This filter restricts the response to large phase differences and it is by-passed by a gate 55 during the period immediately following frequency locking by the circuit of Fig. 2. The gate is opened by unit 56 when the counter 17 of Fig. 2 remains in the same state for an appreciable period, and is closed again by unit 57 when the binary gate 13 of Fig. 2 shows that phase lock has been achieved, as shown by the mark/space ratio of the signal in line 17a or 17b of Fig. 2 remaining constant. A gate 59 in the automatic gain control loop of oscillator 4 is also opened by unit 57, so that the loop only comes into operation after the correct operating frequency has been set up.