Patent GB-965537-A (GB)
Title: Improvements in or relating to data processing systems
IPC: G06F9/355
Filed: 1960-11-18
Abstract: 965, 537. Instruction modifications. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 18, 1960 [Dec. 9, 1959], No. 39680/60. Heading G4A. For the operation of indexing or modifying an instruction, in which index values are added to the operand address of an instruction, index values are held in a number of buffer registers together with the address in memory from which they originate, which addresses are compared with the index address of the instruction and on equality being found indexing is carried out; if equality is not found, the least recently acquired index value in the buffers is replaced by the index value at the index address in memory specified by the instruction and indexing is then carried out. The sum of the index value and operand address may define one of the buffers, in which case the index value held in this buffer acts as the operand or will be replaced by the operand. The intructions are one-address type and are taken from store under the control of an instruction counter 701 (Fig. 3). The buffer registers 208 contain besides the index value V and the index address IA and S bit which indicates that the value held in the buffer is different from that held in memory at the index address and a J bit which if 1 indicates that the information in the buffer is that least recently acquired. The operation is under the control of sequencing signals (Figs. 2 and 4) which vary according to the result of the comparison and the operation required. A Y pulse gates the contents of instruction counter to one input of adder 250 and a "1" through circuit 703 to the other input. The incremented address is gated to register 262 and back to the counter by a Y<SP>1</SP> pulse which also generates an M pulse. This gates register 262 to memory and is followed by an M<SP>1</SP> pulse which gates the instruction from memory to instruction register 206 and generates an A pulse. As soon as the index address is in the instruction register a comparison is made with the index addresses in the buffers by means of exclusive-or circuits such as 202. Equality produces no output from circuit 202 and this is inverted to give a (comparison) signal. The figure shows only the k th buffer and it will be assumed that equality is not found, that this buffer contains the least recently acquired index value (J k  = 2) and that the index value in the buffer is not the same as that at the index address in memory (S k  = 1). The sequence of operations will contain all other sequences as sub-sequences. 1. Since #S k  = 1 and J k  = 1 the index value V k  must be stored in memory at the index address IA k  so that it is not lost. Signals J k . #S K  and A open gate 226 to pass V k  to register 256 through adder 250 and gate 254, opened by A<SP>1</SP>. The combination J k . #S k , C (no comparison) and A' generate an S pulse to which with J k . #S k  gates IA k  to address register 262. The S<SP>1</SP> pulse sets #S k  = 0 after suitable delay. The S<SP>1</SP> pulse triggers an N pulse which gates the contents of register 256 and 262 to memory. The N<SP>1</SP> pulse triggers an A pulse. 2. The index value at the index address in memory specified by the instruction word must now be read into the buffer register. Since now #S k  = 0, the A pulse performs no function as it acts only in conjunction with J k . #S k  but the A<SP>1</SP> pulse under the new conditions triggers pulses B and B<SP>1</SP> which gate the IA of the instruction to register 262 through adder 250. The B<SP>1</SP> pulse triggers pulses M and M<SP>1</SP>, enters the IA into the index buffer register through gate 296 and also sets J k  to 0 and J k   +   1  to 1. The M pulse gates the new index value to the index buffer register. A comparison now exists and inverter 212 issues a C signal. The M<SP>1</SP> pulse triggers an A pulse. 3. There being now a comparison the index value to the buffer register issuing the comparison signal is added to the IA of the instruction. The A pulse again does no work but the A<SP>1</SP> pulse with the C signal triggers a D pulse. This gates the operand address of the instructions through gate 200 to adder 250, and the conjunction with an NI signal and the C signal gates the V k  to the adder through gate 226. The sum is sent to register 262 by the D<SP>1</SP> signal. A comparison is now made of the sum with the addresses IA k  in the buffer registers by means of exclusive-or circuits such as 266 to produce a signal K if equality is detected. If there is no comparison and the instruction is not of the store type (transfer operand to memory) the operand at the address specified by the sum is sent to register 256 and the operation proceeded with. If there is no comparison and the instruction is of the store type the operand is first transferred from e.g. the arithmetic unit to register 256 and is then stored at the address specified by the sum. If there is a comparison and the instruction is not of a store type the index value in the buffer producing the comparison is gated to register 256 and this treated as the operand. If in this case the instruction is a store instruction the operand is stored as an index value in the buffer producing the comparison signal. If the instruction is an index modification instruction the address finally in register 262 is sent to the buffer producing the C comparison signalat the same time #S k  is set to 1. The instruction may be one in which no indexing is required in which case the IA in the instruction register is sent to address register 262 and immediately compared with the IA's of the index buffers to produce a K or K signal.