Patent GB-1397007-A (GB)
Title: Data storage systems
IPC: G11C11/406
Filed: 1973-09-21
Abstract: 1397007 Memory systems INTERNATIONAL BUSINESS MACHINES CORP 21 Sept 1973 [18 Oct 1972 (2)] 44319/73 Heading G4C In a memory system of the type in which the memory cells need restoring periodically, a priority order is established for the restoration. In the embodiment of Fig. 1 (not shown) in which accessing a column of capacitor FET storage cells is assumed to cause restoration, the cells retaining the information for M memory cycles, a priority memory (38) stores the addresses of memory cells restored during the previous M cycles together with an indication from a cyclic counter 42 (of capacity M) of when restoration was effected. During each memory cycle a determination is first made of whether access is requested. If it is not locations H in the memory (38) are examined to see if any address occurs only once (i.e. has been refreshed only once in the last M cycles). If so, if the address of the current count H(C) in the counter (42) falls into this category the associated cells are restored; otherwise H(C) is incremented until such an address is found. If no address occurs only once then the cells associated with the address H(C) are restored. If access is requested a check is first made that the address associated with the count H(C) is also stored in another location in the memory (38). If it is not then access is inhibited and the cells associated with this address are restored unless the current access request is for these cells, in which case access is allowed. In a second embodiment (Fig. 2, not shown) it is assumed that access does not restore the information. A memory array (46) contains a bit position for each group of simultaneously restored cells, a " 1 " being stored if restoration is effected. A pointer (50) stores the address of the next group of cells requiring restoration. If access is not requested the cells indicated by the pointer are restored. If access is requested, a check is made of the number of non regeneration cycles in the last M cycles. If this number is equal to the difference between M and the number N of groups of cells a determination is made of whether restoration was effected M cycles previously. If it was then restoration is necessary and access in inhibited but if it was not then access is allowed. In the embodiment of Fig. 5, an address for access is supplied on line 56 to memory 54 which contains " age " data on the segments. The age of the least recently restored address is compared in comparator 62 with the maximum permitted address age and if it is less than it the input address is fed to drive circuits 30, 40 and age memory 54 is updated in respect of the soaccessed segment. If however the least recently restored address is such as to require restoration and is not the address currently being accessed comparator 62 generates a memory busy signal on line 70 and a signal on line 68 to address generator 66 which supplies the address requiring restoration to the word drive circuits 30. If no address for access is supplied the oldest restored address is selected. Preferably the address age memory 54 comprises a modulo M counter for each segment in the memory array, the counters being incremented at each memory cycle and reset when the associated segment is restored, detectors detecting when any of the counters reaches a counter M. In the embodiment of Figs. 9A, 9B (not shown) a word line address store (122) of capacity C words each of W bits (where C is the number of cycles for which data may be stored without deterioration in the N segments of the memory) has N of its word lines assigned to one of the C cycles of a counter (118). When an address for access is fed in on a bus (140) it is decoded to find the associated word line in the store (122) so that at the end of the cycle updating may be effected. The address (if any) associated with the current cycle is compared in a comparator (136) with the input address and if they are equal the address is fed via a gate (170) to the memory. If they are not but no refresh is required, the address is fed via a further gate (175). If however refresh is required a third gate (168) is enabled to feed the address from the store (122) to the memory (or if the comparator has indicated equality between the input address and the assigned address the input address is fed for access). If no access is required a gate (204) is enabled to feed an address from a look ahead register (200) receiving from store (122) the address of the next word line needing restoration.