Patent GB-819567-A (GB)
Title: Switching circuitry
IPC: H03K17/00
Filed: 1957-08-09
Abstract: 819,567. Electric digital-data-storage apparatus. NATIONAL CASH REGISTER CO. Aug. 9, 1957 [Aug. 21, 1956], No. 25193/57. Class 106 (1). Switching circuitry for selectively connecting any one of a plurality of signal sources to a common output circuit through individual switching devices, includes a source selecting device and a feedback circuit connected from the output circuit through the selecting device to the selected switching device, for maintaining on the output circuit a constant mean D.C. potential on which is superimposed the signals received from the selected signal source. The switching circuitry shown in Fig. 1 selects one of ten heads, such as 12, 39 for reading binary information from a corresponding channel of a magnetic drum 11 forming the memory of a computer. The selection is effected by a register comprising four bi-stable flip-flops whose outputs U 1 , U<SP>1</SP>1 to U 4 , U 4 1 are applied through triode driver and inverter circuits, such as 61, and diode clamping circuits, such as 1, 39a, to a diode matrix 32 to cause one of its output lines 33-42 to be marked with a relatively high potential. The lower clamping diodes such as 39a are connected to a potential of 100 v. and the upper clamping diodes 1-8 are connected via line 30 to an error-correcting circuit 27. Line 30 and the marked matrix output line are nominally at 125 v. The latter conditions a corresponding preamplifier and gate circuit such as 18 to allow playback signals from a corresponding head to pass via common junction 20 and line 23 to a pulse forming circuit 22 (Fig. 2, not shown) whose outputs are applied to opposite triggering inputs of a bi-stable memory flip-flop circuit 24. According to the invention, the signal on line 23, and a D.C. reference signal from junction 21 are applied via lines 23a, 28 to circuit 27 which controls the potential on line 30 and thus acts as a feedback circuit for stabilizing the mean D.C. potential on line 23; this potential might otherwise vary, when switching from one channel to another, owing to the clamping and matrix diodes having different characteristics from one another. The circuit 18 comprises an amplifier 43 and gate tube 45, Fig. 3, connected in series with common resistors 70 and 73, Fig. 1, across a voltage supply. If a relatively positive potential is supplied via line 33 to the grid of the tube 45, the circuit will be conditioned to respond to the playback signals on lines 16, 17. The signals on 16 (see Fig. 5) then appear, amplified and inverted, on line 23 which is held at a mean D.C. level of 175 v. This level is maintained by applying the potential at the cathode of tube 45, as a reference signal, to line 28. This signal is passed through gas tube 60, Fig. 4, cathode follower 50 and control tube 52 to the grid of driver and inverter tube 53 whose anode is connected to line 30. Thus, suppose e.g. that when the circuitry is switched to head 15, the matrix output on line 33 tends to rise to 126 v. (instead of 125 v.), Fig. 5, thus tending to produce an abrupt fall 145 in the D.C. level on 23. This rise will appear on line 28, Figs. 3 and 4, thus producing a fall on line 30 and thus a corresponding fall on line 33. The line 33 is thus held at a mean level of 125 v. as shown. However, in order to hold the anode of tube 45, and thus the cathode of 43, at a steady D.C. potential in spite of A.C. variations in the playback signals, the signals on lines 23, 23a, after attenuation in A.C. control tube 51, also are applied via tubes 52 and 53 to line 30 so as to reproduce on line 33 signals 156 which counteract the playback signals at 17. Adjustment of the maintained D.C. level may be effected by potential divider 120.