Patent GB-858275-A (GB)
Title: Improvements in or relating to alternating current receivers
Inventor: HARRIS LIONEL ROY FRANK
IPC: H04Q1/457
Filed: 1956-01-04
Abstract: 858,275. Alternating current signal receivers. POSTMASTER-GENERAL. Jan. 4, 1957 [Jan. 4, 1956], No. 354/56. Class 40 (4). An alternating current signal receiver comprises means for deriving time space pulses from each signal received by the receiver, the time interval between successive ones of said pulses being dependent upon the frequency of said signal, and means for timing said intervals and producing an output when said time interval corresponds with a predetermined time interval. Signal consisting of a single frequency.-As shown, Figs. 1 and 2, the A.C. signal 1 is caused to amplitude modulate a pulse train supplied over lead PL1 and the modulated pulses fed to a common highway H1. The pulses 2 are then applied to a comparator-amplifier which passes those exceeding a level S to produce an output 3 which is fed via a delay line DL1 to a gate SG1 which is inhibited by the directly applied pulses. The delay line has a delay equal to the pulse interval, so that all pulses of a sequence received from the delay line are suppressed, except the last, 4, which resets the counter C 1  which is stepped by timing pulses 5 coincident with those on PL1. If, say, the frequency of the PL1 pulses is 10 kc/s. and the frequency of the A.C. signal is 1250 c/s then the output 4 from SG1 must occur either on the eighth or ninth count. Accordingly the counter is arranged to provide an output on the eighth and ninth counts which at SG2 gates the pulse 4 to a counter C 2  arranged to produce an output on lead L2 after a prescribed number of such pulses has been received. As shown in thick lines a spurious pulse (due to noise say) is caused to reset the counter C 2 . On noisy lines a further counter C 3  may be provided (dotted connections) for counting the spurious pulses, resetting of C 2  only taking place after a predetermined number of such spurious pulses have been received. The pulses on lead PL1 may be one of a series of interleaved pulse trains, which may, or may not, be permanently associated with specific A.C. signals. The counter C 1  may be arranged to count pulses in all positions simultaneously and detect different pulse counts for different pulse positions. Fig. 3 illustrates such a counter comprising circulating storage systems P1, P2 ... P16 whose delay lines have a delay equal to the pulse interval of any train. Timing pulses for all pulse trains are provided via gate SG10, and resetting pulses in any pulse position are applied to lead 4. The first pulse in any position is inserted in P1. The second pulse in that position is stored in P2 since CG1 is open and suppresses the pulse in P1. The next pulse is inserted in P1. The next is inserted in P4 and deletes the pulse in P2 and P1 and so on, the count being registered in binary form. If the count is allowed to reach 31, the output of CG10 prevents the application of further pulses of that train by gate SG10. The counter is arranged to produce outputs (in the appropriate pulse position) on L3, L4, L5 for counts of 15 or 16, 10 or 11, 7 or 8, corresponding to signalling frequencies of 650, 950, 1300 c/s. If the A.C. signals are permanently associated with particular pulse positions (e.g. the A.C. signal always causes an L5 output at the pulse position on lead PL2) the dotted connections are used and the pulses on lead 4 are gated at CG16 to the counter C 2  which operates as described for Fig. 1, when a prescribed count has been reached to open gate CG18 to pass the appropriate pulse to lead L2<SP>1</SP> and to reset the counter C 2 . In the case where pulse positions are not specifically associated with different frequencies the chain-dotted connections are used and when an output is received, say, from lead L5 it is stored in the circulating delay line MD1, whose output is then used to gate further pulses on L5 (at CG14) into the counter C 2 . When the counter has completed its count it enables gates CG18 ... CG20 at the appropriate pulse position and as this pulse is stored in MD1 it is emitted at CG18 to lead L2<SP>1</SP>. Leads L2<SP>1</SP> . . . L2<SP>111</SP> are now associated with specific frequencies and the pulse position identifies the source. Signal consisting of two frequencies.-A signal comprising a pair of frequencies of approximately equal amplitude is recognized by detecting the semi-sum and semi-difference frequencies. In Fig. 5, graph 1 illustrates the combined waveform of two frequencies f 1 , f 2  and shows it as a signal of ¢ (f 1 +f 2 ) whose amplitude varies at a frequency of ¢ (# 1 -# 2 ). When this signal modulates a pulse train PL1 (Fig. 4), it produces pulses as shown in graph 2 which after passing through the comparator amplifier have the form of graph 3. Pulses will then be obtained from gate SG1 as shown in Fig. 4 at intervals corresponding to a frequency of ¢ (f 1 +f 2 ) so that the counter C 1  may be set to produce an output for the corresponding count on lead L1 so as to gate out the corresponding pulses from gate SG1 to give an indication of the presence of frequency ¢ (f 1 +f 2 ) as described for Fig. 1. However, at the end of every half-cycle of ¢  (# 1 -# 2 ) the phase of the ¢ (# 1 +# 2 ) current changes so that the pulses obtained from SG1, as shown in graphs 4 or 9 are at that point so positioned as not to be suppressed in gate SG4 by the output from counter C 1 . These pulses operate on a counter C 4  and its associated equipment which is arranged in a manner similar to the circuit of C 1  to produce an output when the pulses fed to it indicate a frequency of ¢ (# 1 -# 2 ). Detection of lines having a v.f. calling signal.- A ring counter RC applies a pulse train on lead L12, in turn to incoming modulators. When a signal is detected the corresponding pulse on lead PL7 is gated at CG22 to operate a trigger TC associated with the calling line. If the lines are quiet then the output of gate SG1 may be connected over lead L8 to provide the PL7 pulse if it is not necessary to identify the frequency. If, however, the frequency must be identified the output of SG2 connected over L9 may be used. Alternatively the output from the counter C 2  connected over L10 may be used. To ensure that detection of a V.F. signal occurring at the end of a stepping pulse for counter RC, does not cause the tripping of the trigger TC belonging to the incoming line next to be tested arrangements may be made in the respective cases as follows: the first pulse after the stepping pulse may be inhibited in lead L8; the stepping pulse may be arranged to set the counter C 1  to a number higher than that for which it produces an output; the stepping pulse may reset the counter C 2 . In the case of quiet lines in which a sample detection of the crossing of the threshold value is required, the counter RC may be stepped by the pulse train on L12, the delay line DL1 having a delay equal to n times that of the pulse cycle. In the case where the unmodulated amplitudes of the pulses is variable different comparison levels may be used. Thus, as shown in Fig. 7, four comparison circuits C 1  ... C 4  use successively higher levels of comparison. Pulses are applied to either neither- or both of leads PL101, PL102 to permit the outputs from one only of the comparators C 1  ... C 4  to be passed by gates G9 ... G11, CG23 in accordance with the known amplitudes of the pulses received in the various pulse positions. If these amplitudes are not predetermined the lower part of the equipment may be used (full lines only) to . make the standard depend upon the amplitude of the previous pulse of the train. If a pulse exceeds the C 4  level it is passed to delay lines DL4 and DL5; if it exceeds only the C 3  level it is passed to DL4 only; if it exceeds only the C 2  level it is passed to DL5 only. The outputs of these delay lines, applied to gates G9, G10, G11, CG23 permit these gates to pass only the output of the highest numbered comparator which produced an output for the previous pulse. Instead the highest amplitude pulse may be made to set the standard for a number of successive pulses by the inclusion of the dotted line circuits and components which convert delay lines DL4, DL5 into closed circulating systems which indicate the highest comparison level yet used and maintain that comparison level despite a subsequent fall in incoming amplitude level. The pulses in these lines are deleted at relatively long intervals by pulses on lead PL 103. Economy in delay lines may be effected by using the techniques of Specification 796,223 in which some delay lines are common to more than one group of sources, prescribed times being allotted for interchange of information between the delay line and the individual groups. Specifications 781,561 and 858,276 also are referred to.