Patent GB-1322284-A (GB)
Title: Multi-loop multiplexed data communication system
IPC: H04M9/02
Filed: 1971-11-03
Abstract: 1322284 Digital transmission; stations on a loop INTERNATIONAL BUSINESS MACHINES CORP 3 Nov 1971 [31 Dec 1970] 51033/71 Heading H4P In a system of the type where a looped channel connects all stations which each receive all data in a cycle, the loop being controlled by a system controller, a first loop is employed connected to transmitters and a second loop is connected to the receivers. During a portion of the data cycle or frame the loops are serially connected and during the remaining portion are substantially parallel. Synchronizing may be incorporated into the frames or a separate sync. loop may be employed. Each frame is divided into time slots preferably with some allocated one to each transmitter and some non-assigned. The means serially connecting the loops preferably includes a delay which may be variable or a constant amount greater than the propagation delay in the first loop; such delay is unnecessary with a separate sync. channel. In one arrangement the assigned time slots are allocated to transmission between controller, transmitters and receivers, and the unassigned slots to communication between transmitters and receivers of the stations. The system controller 3 has a register 16 recording operation of all devices 10 which may by any type of terminal or processing unit and which communicate through interface units 20 to respective loops. A non assigned register 17 records the use to which non-assigned time slots are put before being controlled by a further unit 18 through a block 19. If a separate sync. channel 21 is used, this is connected to clock output units 24, 25 which also has an output to a delay monitor 28, also receiving return sync. signals after propagation round channel 21 which is applied initially to counter 29, 30. When the two inputs to monitor 28 differ beyond a specified threshold a variable delay e.g. a tapped delay line is adjusted. Delay 33 may be alternatively in the form of a shift register. Data from the loop is passed through amplifier 34 through AND gate 36 enabled by counter 30 only during assigned slot time which is passed to unit 19. During non-assigned time gate 40 is enabled hence data in this time is delayed by 33 and is clocked out through gate 44 to loop 5 and the appropriate receivers. Assigned data from unit 19 may be in the same frames the switching being performed by appropriate gating of 44, 49 which are enabled alternatively. Loops 4, 5 are effectively in parallel during assigned time and are in series during non-assigned time. Where a sync. channel is employed for both loops, bit, byte and frame synchronization can be supplied hence delay 33 and monitor 28 are not necessary hence loop 4 return may be connected directly into counter 29, 30; a slight disadvantage of this arrangement is that if the propagation time should vary, information may "miss" one unassigned slot and have to be placed. placed in the next. Where a separate sync. channel is not provided clock 24 is directly connected to loop 4 and only byte and frame synchronization is furnished, loop 4 return being connected also to counter 29, 30. Transmitting and receiving interfaces are described in connection with Fig. 6 (not shown) the units being controlled by counter (57) cooperating with a comparator (59) containing addresses of assigned and non-assigned slots, hence when identity with an incoming signal is achieved appropriate gates are enabled to pass the data to a terminal and similarly to pass data out during the appropriate slot time. When a non-assigned time slot is required a request is sent to unit 18 which allocates a slot as soon as one is available and advises both the prospective transmitting and receiving stations of its number hence during the appropriate slot times of the next and succeeding frames, data is passed out to both loops to the receiving station. Any station can be transmitting and receiving during the same frame time in different slots. The specification contemplates the provision of a fixed delay slightly greater and the total loop propagation delay which may be obtained from the difference between in going and out going sync. pulse counts. It is stated that voice switching may be employed by connecting telephone search directly to loops 4, 5 or alternatively by means of PCM a-d and d-a convertors or PAM but this may involve a separate pair of cables incorporating amplifiers. Dependent on the constants of the system resonant transfer may be feasible. A coded address may be used instead of sync. bits.