Patent GB-716246-A (GB)
Title: Improvements in electric circuits for producing or combining coded impulse trains
IPC: G06F7/52
Filed: 1951-05-03
Abstract: 716,246. Digital electric calculating apparatus. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. May 3, 1951 [May 3, 1950], No. 10459/51. Class 106 (1) A circuit for encoding or combining binary expressions to form a series-mode pulse train, comprises (i) a registering device having a plurality of elements (10, 11, 12, 13, Fig. 1) adapted to register respectively the digits of the binary expression, (ii) an input channel (14) common to all the elements for applying a read-out signal thereto, (iii) a delay-line channel (1) having a plurality of tappings, (2, 3, 4, 5) spaced at electrically equidistant intervals, the delay time between each two adjacent tappings being equal to a pulse period in the pulse train, the number of elements and the number of delay-line tappings being equal to the maximum number of terms of the binary quantity to be registered, and each of the delay-line tappings being connected to the output side of one of the elements (10, 11, 12, 13) so that representations of successive digits appear at adjacent tappings, (iv) a pulse-analysing channel connected to each delay-line tapping excepting the one furthest from the output terminal of the delay-line channel, and including means (17, 18, 19) for detecting pulses of amplitude greater than unity, (v) a pulse-reducing channel (21, 23, 25) connected from each pulse-analysing channel back to the delay-line tapping to which the same pulse analysing channel is connected, and (vi) a pulseincreasing channel (20, 22, 24) connected from each pulse-analysing channel to the delay-line channel at a point corresponding, in time, to the point where a pulse of the order next higher than that of the pulse analysed is applied to the delayline channel, the detecting means (17, 18, 19) in each pulse-analysing channel being adapted, in response to the detection of a pulse of amplitude greater than unity, to cause the associated pulsereducing channel to apply to the delay-line channel a pulse of opposite polarity and of doubleunity amplitude and to cause the associated pulseincreasing channel to apply to the delay-line channel a pulse of the same polarity and of unity amplitude. When used as an encoding circuit or dynamicizer a binary number is first registered on switches 10 ... 13, Fig. 1, and then a pulse is applied at the input terminal 15 ; by virtue of the one-digit delay devices 6, 7, 8 arranged between the outputs of the switches 10 ... 13, a series-mode pulse train representing the registered binary number is built up and emerges from the output terminal 9. If, instead of a single pulse, another binary series-mode pulse train is applied at the input terminal 15, then multiplication of the two numbers can be performed. Whenever a pulse greater than unity is built up in the delay channel 1 the appropriate amplitude detector 17 ... 18 (say 17) responds and a device 20 produces a "carry" pulse to the next binary order (at the other side of the one-digit delay device 6) while a device 21 produces a two-digit, negative-going, cancelling pulse which reduces the detected pulse by an amount equivalent to the carry. This process continues until the corrected pulse train representing the product emerges completely from the output terminal 9. In one embodiment the register elements 10, 11, 12, 13, Fig. 3, are multi-grid valves with control grids connected to the input channel 14 and second grids 33 ... 36 selectively biased according to the digits of the statically registered factor. The amplitude detector valves 17 ... 19 are normally biased to cut off but when a pulse greater than unity appears on the grid of (say) valve 17 a negative-going cancelling pulse is derived from the anode and fed back to the delay channel 1 via a resistor 21. A negative-going pulse is passed also via a resistor 20 to a shortcircuited delay line 42 which causes a positive pulse to follow the negative pulse to the delay channel at 41. The negative pulse arrives too early in the digit period to be effective and only the positive carry pulse is superposed on the pro-- duct impulse train. Other embodiments are described including an arrangement for handling series-mode trains in which the digits arrive in descending order of magnitude. Specifications 679,390 and 716,172 are referred to.