Patent GB-1280550-A (GB)
Title: Error detection and correction system
IPC: H03M13/15
Filed: 1969-11-26
Abstract: 1280550 Error correction INTERNATIONAL BUSINESS MACHINES CORP 26 Nov 1969 [28 Feb 1969] 57759/69 Heading G4A The specification describes error correction using the Golay (23, 12) code embodied in the Bose-Chaudhuri code. A 12 data bit, 11 check bit word is loaded into a storage register and an 11 bit check word is generated in a check word generator (Fig. 2). The contents t 1 -t 11  of the generator represent bit positions 1-11 of the 23 bit word. The check word generator is connected to a decoder, Fig. 3, which is arranged to generate an output X 3 = 1 when lines t 1 -t 11  are all 0, X 2  = 1 when t 1  = 1 and t 2 -t 11  are all 0 or contain one other 1, and X 1  = 1 when the unique " Golay " error pattern indicating two errors 11 bits apart in the 23 bit word occurs on t 1 -t 11 . The first bit, t 1 , of the check word is complemented on the assumption that the first bit of the 23 bit word is in error and the contents t 1 -t 11  are circulated right to left twenty three times the arrangement of the check word generator, which includes exclusive-OR gates 11, 12, 13, 14, 15 and 16, being such that 23 shifts returns the contents t 1 -t 11  to their original state. Any outputs X 1 -X 3  which occur during the shifting are utilized to detect and correct errors as described below. The contents of the check word generator are now circulated one place and the procedure described above, beginning with the complementing of bit t 1 , is repeated. The process is continued, i.e. repeated 23 times, until error correction of the 23 bit word is complete, a fact denoted by an X 3  output (check word all 0s) from the decoder. Error correction.-If no errors are present in the original 23 bit word, complementing the first bit of the check word introduces an error. The error in the first bit will be detected by an output on line X 2  at times 0 and 23 (corresponding to no shifts and 23 shifts). This combination is used to cause the first bit of the check word to be recomplemented, the input word remaining unchanged. If the first bit is an error the complementing of the first stage of the check word causes the check word to become all zeros. An output on line X 3  at time 0 is thus used to cause the first bit of the 23 bit word which is stored in the separate register during the process, to be complemented. If one error exists in bit positions 2-11, the check word will be all zeros except for a 1 in the corresponding position. In complementing the first bit of the check word a second error is added which gives rise to an output on line X 2  at time 0. After 23 shifts the same pattern is detected and a further X 2  output occurs at time 23. These, outputs are used to recomplement the first bit of the 23 bit word. If an error exists in bit position 12 of the 23 bit word, the complementing of the first bit of the check word produces an output X 1 , signifying two errors 11 bits apart. This output occurs at times 0 and 23 and is used to recomplement the first bit of the check word. If an error exists in bit 13 of the 23 bit word the complementing of the first bit of the check word introduces a further error. The two errors will not however be recognized until 12 shifts have been made since only errors 11 or less bits apart can be detected. The unique double error pattern then appears and this is used to recomplement the first bit of the check word. Similarly if one error exists in bit positions 14-23 an output on line X 2  will occur after 13-22 shifts respectively. These outputs are used to recomplement the first bit of the check word. If two errors exist in the 23 bit word, one in the first bit position, the number or errors is reduced when the first bit of the check word is complemented. An X 2  output will then occur at times other than 0 and 23 and this is used to complement the first bit of the 23 bit word. If two errors exist in bit position 2-23 of the 23 bit word an additional error is generated when the first bit of the check word is complemented. No error pattern will be generated at any time as the decoder is not responsive to three errors and the first bit of the check word is recomplemented. Similarly if three errors exist, a fourth is added and no error is recognized. If three errors exist, one in the first bit position of the 23 bit word, complementing the first bit of the check word produces an X 1  output at some time during the shifting. Such X 1  signals are distinguished from fallacious X 1  signals, i.e. signals resulting from the creation of two errors by the complementing of the first bit of the 23 bit word, by the times at which they occur. Inhibit circuitry is described with reference to Fig. 4 (not shown) which comprises a number of latches responsive to the X 1 -X 3  outputs at particular times and which directs a pulse which occurs at the end of the 23 shifts in each cycle either to the check word generator to recomplement the first bit of the check word or to the register storing the 23 bit word where it is used to complement the appropriate bit, e.g. during the first 23 shift cycle the first bit, during the second 23 shift cycle the second bit, and so on. Since the 23 bit word contains 11 check bits the correction may be terminated when all 12 data bits have been treated.