Patent GB-953957-A (GB)
Title: System for registering and displaying signals
IPC: G08B26/00
Filed: 1962-06-15
Abstract: 953,957. Selective electric signalling. STANDARD TELEPHONES & CABLES Ltd. June 15, 1962 [June 16, 1961], No. 23124/62. Addition to 952,290. Heading G4H. An apparatus for monitoring a plurality of two-state units, e.g. circuit breakers, in an electric railway power supply system, arranged in groups, some of which are at remote stations, scans a number of receivers, one monitoring each station until it finds one with its output up indicating that one of its units has changed condition, and then stops while it records in a magnetic store:- the station, the group within the station, its number within the group, its new condition and the time of the change so that this information can be printed out when a teleprinter becomes available. As shown a scanner DP scans the station receivers and sends a binary-coded signal to a decoder DCP which brings up an output on one of fifteen lines fl1...fl15 corresponding one to each station. A receiver AT associated with the station at which the scanner has stopped applies an enabling signal to one of sixteen leads fg and one of sixteen leads f0 to enable two relays RD corresponding to the number of groups in the station and the number of the unit within the groups respectively. The actuated relays close corresponding contacts RD1-RD15 to connect the output of the decoder DCP to a pair of circuits CG, CO, which circuits each include four triggers which bring up a parallel four-bit output indicating the group and unit numbers respectively. These outputs are serialized in circuits CG1, CO1 and passed to a parallel-to-series converter TPS. A clock driven by one-a-minute pulses i has four counters UM, DM, UH, DH, each producing a four-bit series output giving in binary form the units of minutes, tens and minutes, units of hours and tens of hours respectively. These signals are decoded at DCH and displayed in decimal form on a panel AF. A decoder DC1 sends a pulse down each of its eight outputs fl 22 in sequence so as to scan the parallel to-series converter TPS so that each of its inputs comprising four serialised binary-coded bits is displayed in turn as four parallel bits, one each on leads fl 23 which comprise the inhibit wires of a conventional core storage MT. A pair of decoders DC2, DC3 select the respective locations for the information recorded under the control of a clock generator CTI which also controls the decoder DC1. A similar clock CTL controls the read out and both clocks operate a totaliser TO which indicates the number of complete sets of information recorded in the store. The information is read out character by character as required by the teleprinter. The character is fed in parallel form to a circuit RL where it is stored and read bit by bit as required to a teleprinter control circuit. The control circuit comprises a bit counter BT which pulses at the read-in rate of the teleprinter and a character counter which steps once every five bits to step a decoder DCS to perform the various functions of the control circuit. The teleprinter works on the international five-bit code and thus circuits TP, TG, TO, TPO, TDH, TUH, TDM, TUM have to be provided to translate the four-bit binary information into teleprinter code. Circuits PC, PL, PE, PH, PM generate number leaders, letter leaders, spaces, the letter H to indicate hours and a prime to denote minutes. Some of the stations may have their groups arranged in a number of portions in which case the corresponding apparatus AT<SP>1</SP> at the central station has two circuits FT, FG' which give the portion number and the number of the groups within that portion respectively. As these numbers are small they are combined in a circuit CG' which produces a four-bit parallel output that functions as the output from the circuit CG.