Patent GB-907100-A (GB)
Title: Improvements in or relating to data processing systems
Inventor: WRIGHT ESMOND PHILIP GOODWIN
IPC: H04L12/54
Filed: 1958-02-06
Abstract: 907,100. Code telegraphy. STANDARD TELEPHONES & CABLES Ltd. Feb. 2, 1959 [Feb. 6, 1958], No. 3993/58. Class 40 (3). A processing arrangement for examining electrically recorded data applicable to electronic computers, or telegraph systems with electronic storage, comprises a number of stores individually and specifically associated with each one of a number of signal channels so that signals on the channels are continuously transferred to the respective associated stores and are effective to feed a constantly-changing constant length signal combination, constituted at any moment by the last received sequence of signals of said constant length on a channel, into each said store during signal transmission on the respective signal channels, means for examining the current contents of each of said stores for the detection of at least one signal combination, and means for providing a signal relating to a corresponding signal channel when a predetermined signal combination is detected in a store. In the diagrammatic arrangement, Fig. 1, the signals received on a channel, such as 101, are passed to a line store 11L comprising individual storage devices LS, which under control of a counter 23C are connected in turn to a stepping register operating to transfer the signal received on a line to a store forming part of the processing arrangement 11P, and comprising eight stepping pattern-registers from which eight characters from the fifty channels are recorded in fifty sequential sections of a drum track 11D, each section carrying or registering forty telegraph elements. The counter 23C for associating each line 101 in turn with the processor 11P for 1 m sec. is driven by a first auxiliary counter 21C, Fig. 2, which is stepped through a character cycle by check pulses 11p generated by each element position on the drum track and a second counter 22C which is stepped through a cycle corresponding to the eight characters on a section of the drum track allocated to a channel by the clock pulses lip and pulses 21c5 derived from the counter 21C at the end of each character. The positional arrangement of the reading heads 11R and writing head 11W in respect of the speed of the drum track 11D is such that when no new signal has been received over a line, the elements of the eight signals are rewritten by the device 11W in the exact positions from which they were extracted by the reading device 11R. If a new character or signal has been received on a line, the signal at the r.h. end of the associated track section is deleted, the remaining signals are moved one character position to the right and the newlyreceived signal is inserted in the vacant position during the cycle corresponding to the cycle of the next channel. The operation for the insertion of a new character in a channel position of the drum track is under the control of a two condition device 21F which is triggered to its 21F1 condition at the end of the 8-character cycle of a channel 1 . . . n . . . 50 if a pulse has been received on that channel, denoted by 23C1 . . . 23Cn . . . 23C50 and a trigger associated with a channel has been operated in response to the reception of a character and produces an output on an associated output or conductors 201a(1) . . . 201a(n) . . . 201a(50). If 21F is triggered to its " 1 " condition, a pulse at 21f1 is applied over terminal 201b in conjunction with a pulse from the corresponding element of counter 23C to restore the trigger associated with the incoming line to a condition to respond to the subsequent new signal on that line. The reading circuit for inserting the eight characters from the channel section of the drum track into the 8-character store of the processor 11P and the subsequent reinsertion of these characters without change or with the insertion of a newly received character on the line in question are described in connection with Figs. 3, 4 (not shown). The detector, as shown in Fig. 5, is responsive to even code elements (2nd and 4th) and odd code elements (1st, 3rd and 5th) of the odd and even characters and the detection operation is carried out by twocondition devices 51F, 52F associated with characters 1 to 4 and 5 to 8 respectively. The devices are triggered by pulses 32S1, 32S3, 32S5, 33S2, 33S4 . . . 35S2, 35S4 and 36S1, 36S3, 36S5, 37S2, 37S4 . . . 21S2, 21S4 in combination with pulses 22c6 and 22c1 from the character register 22C. If 51F, 52F are both triggered to condition 1, a pulse from 22c2 and a pulse 23c3 corresponding to the channel subsequent to that having the characters satisfying the predetermined conditions, open gate G501 passing a pulse to terminal 501 which through counter 23C is associated with the desired channel. Specification 762,094 is referred to.