Patent GB-1297525-A (GB)
IPC: G11C8/04
Filed: 1969-12-12
Abstract: 1297525 Read only memory GENERAL INSTRUMENT CORP 12 Dec 1969 [16 Jan 1969] 60825/69 Heading G4A A matrix read only memory comprises field effect transistors (FET's) at each row/column intersection, selected FET's being operative in order to store one logic level and the remainder being inoperative so as to store another logic level, the transistors in each column having their gates connected to respective row select lines and their source/drain paths connected in parallel between an output node (e.g. In) and a voltage source + V the arrangement being that data is read out by charging the output nodes of each column 1n-64n to a negative potential, connecting the nodes of all non-selected columns to a source of positive potential 1r-64r ( + V) to discharge them, and applying a negative potential to the gate of a selected FET in the selected column so that the output node is connected to the positive potential and discharged only if the FET is operative. The memory is constructed on a semi-conductor chip, the thickness of an insulating layer overlying the gate electrode determining whether the transistor is operative. Fig. 5 shows the selector circuiting for the first eight columns of a sixty-four column thirty-two row memory, the connections for the first row A1 and first column B1 only being shown in detail. The output nodes n are charged through transistor Qn when it is switched on by a timing pulse Q2x. The output node n is connected to a reference node r through two gates Cn and Rn connected in parallel. Gate Cn comprises six FET's which receive one of the sixty-four possible permutations of six column select signals b1-b6 and b1-b6 derived from the column select signals B1-B6 by double and single inversion respectively and gate Rn comprises the thirty-two data storing transistors of the column. If column B1 is to be selected all the transistors in gate Cn will be held off, the corresponding circuits in all other columns being provided with at least one negative b signal to connect the nodes n and r together. The node r is previously charged to +V volts via transistor Qr which is switched on by the timing pulse 3. The selected output node n therefore remains negatively charged while the remainder discharge through their gate C. If the row A1 is selected, by the circuit 18, the transistor QR1 in gate Rn will be enabled and the node n will discharge or not-discharge via this transistor to the node r depending on whether the transistor QR1 is operative or inoperative. The state of the node on the selected column at the end of this operation therefore determines whether a "1" or a "0" logic level was stored by the transistor QR1 at the intersection of the row Al and column B1. The state of the node n is investigated by the output circuitry 22 which comprises an eight input NOR gate On which receives input signals from the output nodes of the eight columns, the connection between the first column node only being shown. A single bit output is therefore provided at terminal 55. Output "words" of two, four or eight bits may however be provided. To obtain a two bit output only five of the six column input signals B1-B6 are used and a corresponding transistor from QC1-QC6 is disabled so that two data storing transistors at the intersections of two columns and one row are selected, the output of the NOR gate On being divided into two, one from transistors Q01-Q04 and one from transistors Q05-Q08. For an eight bit output word three column inputs and corresponding transistors are not used and the output NOR gate On arranged to provide eight output signals. A number of memories may be combined to form a larger module, the unused column selected signals being used to select particular memory chips. To prevent unwanted transistor action between the layers of semi-conductor in the chip from which the memory is constructed a number of blocking regions are included which are connected to a -V volts supply. These art as transistors and collect stray positive carriers. The simultaneous and rapid discharge of 63 unselected nodes presents a possible cause of variation in the uniquely negative row decode signal. This is prevented by initially precharging the column nodes n during #2x time (see Fig. 6, not shown) which is effective to compensate for the positive feed through the data devices as a result of column discharging.-