Patent GB-1296067-A (GB)
IPC: G11C11/4094
Filed: 1970-01-23
Abstract: 1296067 Data storage GENERAL INSTRUMENT CORP 23 Jan 1970 [21 March 1969] 3470/70 Heading G4C [Also in Division H3] Stored data on for example a capacitor 26 is fed to a terminal 24 by a switch which may be a F.E.T. Q1, the terminal 24 being connected to an amplifier 18 whose output B is connectible both to an output terminal D via Q3, Q4 and via Q7 back to the terminal 24, thereby to "refresh" the data read from Cs26. In a matrix of such storage cells Cs the row select lines 16 go to the gates of all the F.E.T.'s Q1 in the desired row, while the column select signal goes to the gate of the Q3 in the desired row to connect the amplifier output to the output terminal D. When writing, the data at C is fed through Q3 to the storage cell Cs26 via Q1 ; the refresh amplifier 18 being rendered inoperative for that particular cell of a selected row, by F.E.T.'s Q20, Q21 which respond to "write" and "column select" signals to earth a point in the amplifier. There is one amplifier for each column (Fig. 2, not shown). In operation, with a three-phase clock source (Fig. 3, not shown), the terminal 24 and associated line 14 which has an appreciable capacitance to earth are charged negatively to V EE  by Q2 during #1 time; Q1 conducts in #2 and #3 time so that the voltage on line 14 is changed according to the stored charge on Cs26, and adopts one of two values (typical voltages are specified) such that Q9 in the amplifier 18 is more, or less, conductive. The resultant voltages at F, G control Q11, Q12 to make the voltage at E sufficient to turn Q14 on or off. Reciprocal coupling by Cf speeds operation. Thus, the voltage at B, charged in #1 time to V DD  is either reduced only by the drop across Q13, or it is earthed by Q14, according to the stored data, the latter being restored to its initial value via Q7 to compensate the change produced when Q1 first turned on. The base and emitter of output transistor Q4 are also charged negatively in #1 time by Q6, Q5, these levels being then modified by the amplifier output. Compensation for variations of V DD  and V EE  in the amplifier is effected by a F.E.T. Q10 which controls the potential at G in accordance with the state of conduction of a F.E.T. Q16 whose resistive load Q15 is connected to V EE  and whose gate is fed from a resistive potentiometer Q17, Q18, Q19 across V DD  and earth. Row and column select circuits are described (Figs. 4a, 4b, not shown) which are basically similar, each including a set of parallel F.E.T.'s (Q22, Q23, Q24 &c.) constituting a NOR gate. In #1 time the output (36) of a NOR gate is charged (by Q27) negatively, and only if all F.E.T.'s in the gate remain non-conductive does this negative voltage remain in #2 and #3 time to connect V DD  to the row select output via Q29, Q30, Q31. Four inputs and their complements are fed in different combinations to each of sixteen such NOR gates connected to respective rows. In the data part of the data and write circuit (Fig. 4c, not shown), a print (54) is charged negative in #1 time (by Q41, Q43a) and a data signal modifies the voltage (at 55) according to its binary value. In #2 time the resultant voltage (at 54) is inverted (at Q44) to control a further F.E.T. (Q46) which earths the output (58) when the data is negative. The write part of the circuit is similar (52). In all three circuits (Figs. 4a, 4b, 4c, not shown), the part of the circuit connecting the output to the negative supply V DD  includes a parallel pair of F.E.T.'s (Q30, Q31 for example) controlled by #3 and #2 respectively, and a series F.E.T. (Q29) receiving the controlling voltage from the earlier part of the circuit, the #3 voltage being supplemented by this controlling voltage if the latter is negative by means of a capacitor (C2) between the gates (of Q29, Q30).