Patent GB-1504196-A (GB)
Title: Data storage systems
IPC: G06Q40/00
Filed: 1975-03-25
Abstract: 1504196 Credit card verification; data storage systems SOC INTERNATIONALE POUR L'INNOVATION 25 March 1975 [26 March 1974] 12489/75 Headings G4A G4D and G4H A portable device, e.g. a credit card, ring, &c., includes one or more semi-conductor integrated circuit memories and control circuits, there being means to prohibit data being written into and/or out of sections of the memory denoted as prohibited. General.-The device is coupled optically or by transformer cores to a read-out device, power being supplied through coupling 105, 151. As described, the device is used as a credit card, a memory 40 storing customer identification &c. The contents of memory 40 are read out and compared, 30, with identification data entered on keyboard 31. If and only if these data match the remaining memories are accessed. In the case where the card is used to control a bank note issuing machine the memories contain a number of credit entries, made at the issuing bank, and a number of locations available to store debit entries. A new debit entry is only permitted if the outstanding credit balance is positive, calculated in unit 49 by reading all entries from the card together with the new debit amount entered on keyboard 63. Memory protection.-Several forms of memory protection are described to prevent fraudulent use of the card. Memory 40 is arranged to be read only to prevent alteration of the customer identity. In respect of memories 50, 51 each entry may include a final bit which subsequently prevents the entry being modified. When a debit entry is to be made, all the debit entries are accessed in sequence (to calculate net balance, a debit transaction being prevented if the balance after the transaction is negative) until the first location not having a final marker bit is located. The address is then counted back to the beginning of the (empty) location and the entry is then made, details of the transaction being displayed at 69. In another form the arrangement is similar except that each entry is read out (serially or in parallel), staticized, and examined by a gate to detect empty entries. Writing is only permitted in an empty entry. In a further form writing and/or reading is prohibited within certain zones in the memory, address comparisons inhibiting access when within the prohibited zone. Arrangements involving fusible links are provided to allow initial data to be written into prohibited zones, the link being subsequently fused to prevent further access (read and/or write). Further details.-The memories which may store m,n-bit words may be accessed serially by bit or in parallel by word and are addressed by counters. The reading device is sequenced by counters 46, 47, 48 stepping through a number of states, different operations, e.g. reading the memories, being performed in each state. The arithmetic unit 49, Fig. 3 (not shown), is formed of an up/down counter. Each successive bit of a binary debit or credit is stored in a shift register (17) and gates (14), via switch (9), a number of pulses from an oscillator (15) corresponding to the weight of the bit to an up/down counter (11) whereby the final contents of the counter indicate the net credit. The various memory protection arrangements are described in some detail with reference to Figs. 4-19 (not shown).