Patent GB-1116524-A (GB)
Title: Information storage system
IPC: G11C15/04
Filed: 1965-09-09
Abstract: 1,116,524. Digital electric calculator; electric digital data-storage. WESTERN ELECTRIC CO. Inc. 9 Sept., 1965 [9 Sept., 1964], No. 38506/65. Headings G4A and G4C. An associative memory comprises first and second arrays of cells 40a, 40b, 40c, 41a, each comprising a plurality of registers X, Y for storing data units of multi-unit words, each first array cell 40b being associated with a group of second array cells 41a, means for storing data units in a selected first array cell on a word per cell basis, and means for transferring stored data units simultaneously from the registers of the first array cell to the registers of a plurality of second array cells on a unit per cell basis. Memory unit.-The second array cells (Fig. 2, not shown), may comprise a set of flip-flops XI to XN for storing data and a pair of match flip-flops MA, MB, flip-flop MA indicating whether the cell is active, i.e. matches a specified input pattern, or not, and MB for temporarily storing the result of MA. Data can be stored by two commands, unconditional STORE and conditional STORE. In unconditional STORE data is stored in all cells via gates 210, 211 ... 212, 213 under the control of a STORE signal and an #Im signal and in conditional store data is stored only in active cells, gates 210 ... 213 being enabled by a STORE signal and an active signal from register MA. On a MATCH or comparison instruction the data in each cell is compared with the data in the input register via AND gates 214, 215, 217, 218, each bit stored being compared with the inverse of the corresponding bit of the comparison number and vice versa, the output of all the AND gates being connected to an OR gate 230 and an INVERTER so that on comparison all the AND gates are inhibited and the INVERTER passes a signal m; which in combination with the MATCH command and an Im signal sets register MB, the active signal stored therein being transmitted to MA under the action of a DOWN command. A READ command retrieves the contents of an active cell and places it on the 0 lines. Since all cells share common output lines it is necessary to ensure that only one cell is active before reading. Further commands enable LEFT, RIGHT, and UP and DOWN shift of data. In the memory shown in Fig. 4 the nth row of X registers are connected to form a Y cell with additional registers added, register G acting as the match flip-flops. Cell Y is capable of storing a word and of transmitting it into appropriate register XI-XN of the X cells storing 1 bit per cell, the X cells being connected as described above except that all reading and writing is done via the Y cells. The cells may be identified by content or position, i.e. if a group of cells contain Ym + 2 =1 then all cells are deactivated, the leftmost cell is activated and shifted left until a cell containing Ym +1 is found. This is then activated and all the others deactivated leaving only the one active cell identified. Arithmetic operation.-Addition is performed on two binary numbers in the store by storing the two numbers in different rows of the X cells and performing suitable MATCH and SHIFT operations. Initially the match flip-flops are cleared, then the match flip-flops are set for each column wherein both numbers contain zero, and the " ones " set in the said flip-flops are shifted one position left and stored in one of the vacant X rows (say X 1 ). The match flip-flops are then set for all columns wherein each number contains 1 and the " ones " thus stored are shifted left. A PROPAGATE left command then activates all cells between an activated cell and the nearest left cell containing a one in X 1 . X 1  is then cleared and the pattern from the match flip-flops stored therein. If the two numbers to be added are in X 8  and X 9  then all cells containing X 1  = 0, X 8  = 0, X 9  = 1 are activated, then all cells containing X 1  = 1, X 8  = 0, X 9  = 0 are activated also and then all cells containing X 1  = 1, Xs = 1, X 9  = 1 and the ones stored in the match flip-flop are equivalent to the sum. Subtraction may be performed in a similar manner and multiplication or division by repeated addition or subtraction and shift. Alternatively for accumulative addition wherein the addend need not be saved and the addend is in X 1  and the augend in X 2  then the partial sum may be formed in X 2 , the carries formed and the carries added to the partial sum, the final sum being stored in X 2 . The instructions for the above operation are given as are those for multiplication using a stored carry technique and those for multiplication of two matrices.