Patent GB-1036024-A (GB)
Title: Data processing
IPC: G06F11/10
Filed: 1964-03-18
Abstract: 1,036,024. Electronic computers. RADIO CORPORATION OF AMERICA. March 18, 1964 [March 28, 1963], No. 11503/64. Heading G4A. A data processing system comprises a plurality of input-output buffers and includes a memory having a corresponding plurality of sub-areas each of which stores " instruction bits " indicative of the status of, and operations to be performed on, corresponding input-output data, each buffer producing a " ready " signal when it requires attention for an input-output operation. The arrangement is described as applied to the R.C.A. 301 computer but may be applied to other computers. During short time intervals within the normal machine programme, the instruction bits may be sensed to determine for example if a complete message has been assembled and is ready for processing, so that a sub-routine to effect this processing is initiated only when necessary. As described, the computer 12, Fig. 2 (not shown), handles data in the form of 7-bit characters (6 data bits plus a parity bit) and has n (= 16) peripheral devices, each having an associated character buffer, data input-output being under the control of a control unit 10 connected to the computer 12 which includes a random access magnetic core memory 12a with 7 Ás. cycle time. In operation, a computer programme is interrupted for a period of one memory cycle each four memory cycles (or each x memory cycles where 4 # x # 24) for the purpose of communication with the peripheral devices. In the case of an input device (Fig. 4, not shown) data may be supplied serially by bit to a 7- stage shift register which, when full, transfers its contents to a 7-stage storage register thereby causing a " ready " signal to be produced. The control unit 10 includes a scanner (Fig. 6, not shown) in the form of a binary counter the stage outputs of which are applied to AND gates whose other inputs are the lines carrying the " ready " signals from the peripheral devices. When a buffer producing a " ready " signal is sensed, scanning is halted and the required transfer of a character between the computer memory and the peripheral device takes place. The computer memory includes a large working section for normal programme operation and a plurality of 100-character sections, one for each peripheral device. The memory is addressed by four decimal characters A0, A1, A2, A3 each of which may be in 6-bit binary coded form with the first two bits being 0. When the peripheral device scanner stops at a peripheral device requesting attention, the output of the binary counter in the scanner is decoded to provide a representation of memory address characters A0, A1, corresponding to that device. Instruction characters. Fig. 8 (not shown).- Stored at fixed locations 2 and 03 in each memory section corresponding to a peripheral device are two 6-bit " instruction characters " I1, I2, Fig. 8, the bits of which can indicate the status of input or output data, or operations to be performed. Thus the 2 bit of I1 indicates whether an input or an output operation is required; the I1 2<2> bit indicates whether the parity of a character is to be checked and if this parity is incorrect a predetermined character 101111 replaces the incorrect character and the I2 2<2> bit is made 1 " to serve as an alarm indicator. The I1 2<3> and 2<4> bits may serve to control a test of whether a character is a predetermined character, e.g. end of message character, corresponding bits of I2 being made " 1 " if a successful test is made. The I1 2<5> bit may control a test of whether a character is the " k'th character", i.e. the k'th character of a message being transferred. At appropriate short time intervals within a programme, the I2 bits are sensed to determine for example whether a complete message has been assembled requiring attention by a sub-routine. System operation.-As illustrated in the flow chart of Fig. 3 (not shown), box 14, the peripheral devices are scanned until a device ready for attention is reached when the scanner stops and the memory 158, Fig. 7 (not shown), is addressed by characters A0, A1, 02, 03 to read out the instruction characters I1, I2 for the device into registers 164, 166. If the computer memory is not able to be addressed for some reason, I1 and I2 are returned to their locations (line 20, Fig. 3) after modification if necessary (line 16, Fig. 3) and scanning is resumed. Normally, however, I1 and I2 are read out and any operations required thereby are performed (box 22, Fig. 3) under the control of a control circuit 174, Fig. 7, and either returned after modification at 170, Fig. 7 (box 18, Fig. 3) to the memory 158 or retained to cause the memory addresses A0, A1, 00, 01 to be read out, the characters A2, A3 being read out during the next memory interrupt cycle and stored in the memory address register 154. The transfer of a data character now takes place to or from this address (box 26, Fig. 3), A2, A3 are incremented to provide the address for the next character transfer and are returned to the memory (box 32, Fig. 3). Thereafter I1, I2 are modified if required and returned to the memory. The transfer of a character as described requires five interrupt cycles which, as stated above, are interleaved with normal computing cycles, and subsequently the scanner is advanced to sense the next peripheral device.