Patent GB-1259911-A (GB)
Title: Address translator
IPC: H03M7/00
Filed: 1970-01-05
Abstract: 1,259,911. Data storage; address selection. BURROUGHS CORP. 5 Jan., 1970 [31 Jan., 1969], No. 401/70. Headings G4A and G4C. Digital data stored on a magnetic disc or drum has its address stored as a binary coded or binary coded decimal signal in a data processor 14 and an arithmetic unit 16 converts this signal to separate signals for selecting a transducer 12 and for selecting the angular position of the data on the disc or drum. This is effected by division using repeated subtraction of parameter signals from the address signal. The disc.-A two-sided magnetic disc has three (Fig. 2) annular fields 1 to 3, each field comprising 32 information channels CH0 to CH31. Each channel has three readable tracks, one track being on one side of the disc and two on the other or vice versa alternately for all the channels. Read/write heads are provided for each track. Each field has a number of radial zones, field 1 having three 0 to 2, field 2 having four 0 to 3, and field 3 having five 0 to 4, and in each zone each channel segment comprises 512 word addresses 0 to 511. Every word address (having the same number) in all zones is grouped together; i.e. in field 1 addresses 0 for zones 0 to 2 are together. Ten discs 0 to 9 may be used. Operation.-A 22 bit binary or BCD signal is translated into disc, field, and channel signals which control a head selection matrix 20 to select three heads 12 to simultaneously read/ write the three tracks of a channel, and zone and word signals which select the angular position of the disc. The 22 bit signal passes from a data register of a data processor 14 to a 24 bit disc address register 30 of arithmetic unit 16 under the control of unit 28, and the operation proceeds in five steps under the control of a sequencing counter 32. A gating matrix 38 and a subtract register 34 form a parameter generator for providing parameter signals to be divided into the coded address. Step 1.-The right hand nine bits correspond to the 512 word addresses/channel segment and the binary point is thus moved nine places to the left (i.e. division by 512), thus the nine bits are stored in cells 0 to 8 of register 30, the remainder being in cells 11 to 23. Step 2.-There are 384 channel segments so the remainder is divided by 384 by repeated subtraction using the 1's complement method, a subtractor register 34, a parallel adder 36 and a gating matrix 38. As a result, cells 15 to 23 contain the channel segment bits, and cells 11 to 14 contain bits specifying the disc. Step 3.-As there are 96 channel segments in field 1, 96 is subtracted from the bits in cells 15 to 23. If the subtraction is not possible the address is in field 1 indicated by a bit in cell 9, if it is possible it is in field 2 or 3. Step 4.-There are 128 channel segments in field 2, so by dividing by 128 the address can be traced to field 2 or 3 and this is stored in cells 10 and 11. Step 5.-The remainder from step 4 (knowing the field) is divided by the zone interlace ratio (indicating the number of zones/field). After these five steps register 30 holds from left to right, 3 bits for zone, 4 bits for disc, 2 bits for field, 5 bits for channel and 8 bits for word address, and a control signal notifies disc selection circuit 18 so that read/write can take place. A compare unit 22 compares the zone and word address bits with signals coming from the disc. In this embodiment subtraction is carried out until no longer possible, however subtraction may be carried out until a negative result is found and then one addition is made to compensate. Arithmetic operations are in parallel.