Patent GB-745660-A (GB)
Title: Improvements in analogue computors, for solving differential equations
Inventor: THOMAS ERIC LLOYD
IPC: G06G7/06
Filed: 1953-02-26
Abstract: 745,660. Electric analogue calculating systems. SHORT BROS. & HARLAND, Ltd. Feb. 11, 1954 [Feb. 26, 1953], No. 5410/53. Class 37. An electric analogue computer for solving differential equations expressing the behaviour of physical systems to be investigated comprises an electrical network analogous to the equation to be solved, composed of a number of cooperating computing units each constituted by a D.C. amplifier, an associated function unit comprising three impedances (two resistive and one capacitative), switching circuits operable to selectively connect the impedances and the amplifier in various combinations wherein one impedance is connected in series with the amplifier input and another is connected in a feedback path across the amplifier so that the latter may operate alternatively as an addition circuit, an integrating circuit or a differentiating circuit in accordance with its position in the network corresponding to the equation, switching circuits operable to vary the individual impedance values, and a transient forcing function generator exciting the network to generate a solution function which is displayed on a cathode-ray oscillograph screen or by a pen recorder; there being also provided multiple interconnection panels whereby plural computing units may be connected at will into plural analogue networks representing distinct differential equations, with interconnections therebetween introducing common terms for the simultaneous solution of such equations, and wherein feedback connections may be set up as required between individual computing unit amplifiers situated both within a common analogue network and within distinct analogue networks representing distinct equations. Basic computing circuits.-Fig. 3 shows a computing circuit for solving the differential equation wherein a transient forcing function F(t) = Eo is injected at F1a through a resistance of unity value to the input F1b of an adding highgain amplifier D1 shunted by a unity feedback resistance, whose output F1c is connected at F2a through a unity resistance to the input of an adding highgain amplifier D2 1 shunted by a scaling resistance S3 = -, L whose output F2c is connected at F3a through a unity resistance to the input F3b of an integrating highgain amplifier D3 shunted by a unity capacitance. The output F3c is connected at F4a to a unity resistance in series with the input F4b of a further integrating highgain amplifier D4 whose output at terminal F4c is applied for display to a cathode-ray oscillograph or pen recorder and fed back over resistance S7 = C to terminal F2b, while the output of amplifier D3 at terminal F3c is fed back over resistance S5 = 1/R to the input F1b of amplifier D1. Assuming the output signal at terminal F2c to be + #q, that at F3c is - #q and that at F4c is + q since the integrators possess unity time constants, the total signal at F1c is - Eo + Rq and the signal #q at F2c is 1/L (- Eo + Rq + q/c) so that the equation to be solved is satisfied for the displayed value of + q at F4c, shown in Fig. 16 (a) against a time axis. Fig. 4 shows a modification for solving the simultaneous differential equations representing the longitudinal stability of an aircraft, wherein U = forward velocity, W = vertical velocity, and # = angle of incidence. A computing channel is provided to represent each of the differential equations as shown, the constant coefficients are introduced by scaling resistors associated with the several addition units, and linkages are provided between the computing channels for introducing into each channel the necessary common terms involving functions of the solution values computed by the remaining channels of the system. The forcing function Ft is injected at input terminal F1a, and the solution values of U, W, and # are obtainable by display on an oscillograph or pen recorder of the output signals generated at terminals a, b, and c, as shown in Fig. 16 (a) against a time axis. Function units.-Each amplifying function unit comprises (Fig. 1) a three-terminal network having alternative input terminals Fna, Fnb at opposite ends of generalized variable impedance Z1, a capacitance 105 coupling Fnb to the input of highgain amplifier D whose output is connected to output terminal Fnc, and a generalized variable feedback impedance Z2 interconnecting terminals Fnb, Fnc. Relay contacts 102, 103, and switch 104 are operable from their normal positions as set forth below to short circuit the amplifier output and input, to short circuit the capacitance 105 over resistance 117, and to earth the input terminal Fnb. The generalized impedances are switchable as set forth below so that the function unit may operate additively with Z1 = R1 and Z2 = R2 (Fig. 2b) wherein application of signal V1 to Fna produces an output Vo = R 2 /R 1  V1 at Fnc and application of signals V1, V3, V4 ... to Fnb over respective input resistances R1, R3, R4 ... (not shown) produces an output or as an integrator (Fig. 2a) with Z1 = R1 and Z2 = C wherein application of signal V1 to Fna produces an output Vo = - 1/CR 1  ##V1dt in which CR1 is the integration time constant. When the computer is designed to simulate the response characteristics of a servosystem, the function units may be modified to present other elementary characteristics (Figs. 2c to 2g, not shown), e.g. differentiation, wherein terminals Fna, Fnb are joined by a capacitance and the amplifier is shunted by a resistance, and phase advance wherein Fna, Fnb are joined by a resistance paralleled by a capacitance and the amplifier is again shunted by a resistance. Structurally, each function unit (Fig. 8) comprises a range of seven fixed resistances from which the desired value R1 is selectible by 8-position 2-way ganged switch 34a, 34b; a further range of seven fixed resistances from which the desired value R2 is selectible by 8 position 2-way ganged switch 35a, 35b, and a range of seven fixed capacitances from which the desired value C is selectible by 8 position 2-way ganged switch 36a, 36b together with a 7 position 5-way ganged selector switch 33 having sections 37-41 in which the arm of section 37 is connected to input Fna, that of section 38, to input Fnb, and that of section 39 to Fnc and which is interconnected with the selectible values of R1, R2 and C so as to set up in switch positions 1 to 7 the alternative function unit circuits referred to. Amplifiers.-The associated amplifier (Fig. 9) comprises a pair of balanced phase-splitting cathode coupled pentodes V1, V2 zeroized by potentiometer 42, energized by input grid connection to terminal Fnb in series with capacitance 105 short circuitable by relay contact 104, and directly coupled to balanced cathode coupled pentodes V3, V4. The anode of V3 is earthed over a resistance while that of V4 is directly coupled through triode amplifier V5a and cathode follower triode V5b to the output terminal Fnc and to a biased thyratron pentode V6 striking to energize neon indicator lamp 43 in series with the H.T. supply over terminal 44 when the output voltage exceeds Œ 50 v. on overload. Pentode V7 energizes relay windings 45, 46 on arrival of a control pulse at terminal 47 to apply drift connection and clamping to the amplifier as set forth below. Stability is preserved when selector switch 33 is in position 1 by the insertion by section 41 of a resistance capacitance network between the anodes of V3 and V4 (Fig. 8). Scaling units.-Associated with each amplifier is a double resistive scaling unit capable of introducing a controlled level of feedback between amplifiers of the same or distanct computing channels, representing the coefficient values of common variable terms. Each unit (Fig. 10) comprises a potential divider 57 from input terminal Sna to earth comprising resistances of 1 M#, 100 K#, 10 K#, and 1.1 K# in series, the input and the successive resistance functions being connected respectively over resistances of values 100 K#, zero, 100 K# in parallel with 820 K#, and 100 K# in parallel with 10 M# to sockets 56 which are selectively interconnectible by a 2-pin plug, in alternative positions corresponding to attenua- 1 tion steps of -, 1, 10, and 100, with the terminal 10 Snb over a chain of variable resistances 47, 48, 49 respectively variable in steps of 100 K#, 10 K# and 1 K# by 9-way switches 50, 51, 52. The latter have scales graduated in steps of 1 M#, 100 K#, and 10 K# and by adjustment of the attenuator plug to its several positions, an effective scaling resistance of 1/10, 1, 10, or 100 times that shown on the scales may be inserted between terminals Sna, Snb. Universal computer structure. In apparatus for solving a wide range of simultaneous differential equations according to the principles set forth above, combined amplifier and function units F1 to F18 and associated double scaling units S1 to S36 are removably rack mounted in a cabinet (Figs. 5, 6, 7, not shown) provided with a set-up socket field (Fig. 19) having multipled and correspondingly numbered sockets to which function unit terminals Fna, Fnb, Fnc and scaling unit terminals Sna and Snb are respectively connected. The cabinet also contains a power supply and switching unit, a timing signal generating unit, a cathoderay oscillograph display unit, a Y amplifier unit, a metering panel, and a pen recorder unit; all of which are common to the plural amplifier, function, and scaling units. The set-up field (Fig. 19) comprises a panel 160 having 36 columns of correspondingly numbered sockets 161 to which the terminals F (1-18) a, F (1-18) band F (1-18) c of the plural function units and terminals S (1-36) a and S (1-36) b of the plural scaling units are respectively connected in multiple, and also multipled sockets 162 to which a forcing function signal F(t) is applied as set forth below, while certain sockets 166 are provided with permanent interconnections 167. The sockets are grouped in paired columns to c