baber/WOPTO huggingface dataset:
Patent TW-461199-B (TW)
Title: Receiver, CDMA telecommunications system and method of synchronizing a receiver with a transmitting station of such a system
Inventor: KHALIFA NABIL
IPC: H04B1/707
Filed: 1999-12-29
Granted: 2001-10-21
Abstract: The invention relates to a receiver and a CDMA telecommunications system comprising various transmitting stations. The receiver comprises synchronizing means for synchronization with at least one transmitting station periodically transmitting over a common synchronization channel a cyclic synchronization code formed by pilot signal Cp and a useful signal containing a code Cs,t. The transmission period of the synchronization code via the transmitting station is denoted T. The receiver comprises correlation means for acquiring the phase of the cyclic synchronization code and for determining the code Cs,t, contained in the useful signal at the instant t among a plurality of orthogonal reference codes defined by the system, before the transmission of the next synchronization code at the instant t+T containing a new useful signal Cs,t+T. Application: CDMA telecommunications, more particularly, UMTS, ARIB, IMT-2000 radio telephony etc.
Patent TW-I243287-B (TW)
Title: Lithographic projection apparatus and device manufacturing method using the same
Inventor: KRUIZINGA BORGERT
IPC: G02B5/02
Filed: 2000-02-16
Granted: 2005-11-11
Abstract: In a lithographic projection apparatus, extreme ultraviolet radiation, e.g. of a wavelength of 13 nm, is generated by an undulator 10 in an electron storage ring. The radiation is collected by a first relay mirror 13, and an image of the source waist is formed at an intermediate plane. At the intermediate plane, a first scattering mirror 14 is provided to increase the divergence of the radiation beam in at least one plane. A second relay mirror 15 images the first scattering mirror onto the entrance pupil 18 of the projection system of the lithographic apparatus. A second scattering mirror 16 folds the projection beam onto the mask 17 and further increases the divergence of the radiation beam. The second scattering mirror may be combined with the second relay mirror.
Patent TW-444268-B (TW)
Title: Display panel
Inventor: KAWASAKI KIYOHIRO
IPC: H05K3/36
Filed: 2000-02-23
Granted: 2001-07-01
Abstract: Disclosed is a display panel that provides a semi-conductor integrated circuit chip mounted on the display panel with the necessary signals and power using low resistance. Supply of electronic signals to terminal electrodes of a scan line and a signal line is achieved by means of directly mounting the driving integrated circuit chip on the terminal electrode arranged on an active substrate. Further, electrical connection of the driving integrated circuit chip is achieved by means of forming an opening portion larger than the profile of the above-mentioned integrated circuit chip at an assembly position of the driving integrated circuit chip mounted on the active substrate and its vicinity, and by disposing a printed circuit of a wiring circuit outside an image display zone of the active substrate.
Patent TW-558703-B (TW)
Title: Apparatus for driving dataline of liquid crystal display panel and method of doing the same
Inventor: KOGA KOICHI
IPC: G02F1/133
Filed: 2000-03-02
Granted: 2003-10-21
Abstract: There is provided an apparatus for driving a data line in a liquid crystal display panel, including (a) a data line into which an analog data signal is input, (b) at least one shift register transmitting a shift pulse, and (c) at least one circuit for sampling and holding the analog data signal in accordance with the shift pulse, and transmitting a voltage signal, the data line being comprised of first and second divisional data lines, the analog data signal being input into one of the first and second divisional data lines. In accordance with the apparatus, a data line in a liquid crystal display panel is comprised of first and second divisional data lines. Hence, it would be possible to reduce wiring resistance and capacity of the data line as a whole. In addition, since the number of switches positioned between the divisional data lines and the sampling and holding circuits can be reduced, ensuring reduction of parasitic capacity caused by switches.
Patent TW-457419-B (TW)
Title: Microcomputer, electronic machine and emulation method
Inventor: KUDO MAKOTO
IPC: G06F11/22
Filed: 2000-03-22
Granted: 2001-10-01
Abstract: The present invention relates to microcomputer, electronic machine and emulation method. The purpose of this invention is to obtain a microcomputer, an electronic equipment and an emulation method capable of realizing an optimum evaluation environment while saving the number of terminals. The solving means is shown in the following. An external bus 28 is shared by an external memory 30 and an emulation memory 32. In an emulation mode, an access to an internal ROM 16 of a CPU 12 is switched to an access to the emulation memory 32 through the external bus 28. The ON/OFF operation of the emulation mode is switched by a mode selection terminal or a mode selection register. The memory 32 is controlled by a control signal CNT2 different from a control signal CNT1 for the memory 30. A memory read signal in the CNT2 is activated at timing earlier than that of a memory read signal in the CNT1 such that the checking and decoding of an instruction are completed within one clock cycle. The mode selection terminal, which selects each mode simulated from the emulation memory 32, internal ROM 16 or the external memory 30, or is used in an OPT mode, is installed.
Patent TW-465057-B (TW)
Title: Method of producing semiconductor device comprising insulation layer having improved resistance and semiconductor device produced thereby
Inventor: ITO DAISUKE
IPC: H01L21/60
Filed: 2000-05-06
Granted: 2001-11-21
Abstract: A semiconductor device comprising an insulation film covering a semiconductor chip so as to expose electrodes or pads fabricated in the chip and wiring lines located on the insulation film and connected to the respective electrodes of pads is produced by a method which comprising: providing a semiconductor chip provided with an insulation film covering the chip so as to expose a conductor layer for electrode or pads fabricated in the chip, ion milling the surface of the chip provided with the insulation film by a mixed gas of argon and hydrogen forming a patterned conductor layer for wiring lines on the ion-milled surface of the chip, and dry etching the surface of the chip provided with the insulation film and the patterned conductor layer by nitrogen gas.
Patent TW-463037-B (TW)
Title: Method for displaying skin color information
Inventor: TSUGITA TETSUYA
IPC: A61B5/107
Filed: 2000-05-08
Granted: 2001-11-11
Abstract: The invention is based on the test value for cosmetics. To distinguish the blacken extents of skin and whether the balance is good between makeup skin and non-makeup skin. It tests two different sites of an examinee and input the color test value into the arithmetic unit connected with a display to show the value with color image from the different sites.
Patent TW-505945-B (TW)
Title: Blade and blade assembly for mechanical wafer handling system
Inventor: MINNICK ANDREW
IPC: H01L21/677
Filed: 2000-05-26
Granted: 2002-10-11
Abstract: A blade assembly for a mechanical wafer handling system. The assembly includes an elongated planar member having a central region, wherein the central region has a first array of openings and a second array of openings, the openings of the first array being arranged substantially symmetrically to the openings of the second array on opposing sides of a central longitudinal axis extending along the length of the planar member and passing through a center point of the central region. The openings in the first array are arranged substantially symmetrically with respect to a perpendicular axis extending along the width of the elongated planar member and passing through a center point of the central region. The openings in the second array are also arranged substantially symmetrically with respect to the perpendicular axis. The assembly also includes a wrist with a wrist upper cap and a wrist lower cap. The wrist upper cap has a first and a second wing support on two opposing sides of the upper cap and a first non-supporting narrow ridge extending between the first and second wing supports. The wrist lower cap has a third and a fourth wing support on two opposing sides of the lower cap with a second non-supporting narrow ridge extending between the third and the fourth wing supports. The wrist upper cap is attached to a top surface of the planar member and the wrist lower cap is attached to a bottom surface of the planar member when the blade assembly is assembled.
Patent TW-458791-B (TW)
Title: Intracutaneous microneedle array apparatus
Inventor: YUZHAKOV VADIM VLADIMIROVICH
IPC: A61M37/00
Filed: 2000-06-09
Granted: 2001-10-11
Abstract: Improved microneedle arrays are provided having a sufficiently large separation distance between each of the individual microneedles to ensure penetration of the skin while having a sufficiently small separation distance to provide high transdermal transport rates. A very useful range of separation distances between microneedles is in the range of 100-300 microns, and more preferably in the range of 100-200 microns. The outer diameter and microneedle length is also very important, and in combination with the separation distance will be crucial as to whether or not the microneedles will actually penetrate the stratum corneum of skin. For circular microneedles, a useful outer diameter range is from 20-100 microns, and more preferably in the range of 20-50 microns. For circular microneedles that do not have sharp edges, a useful length for use with interstitial fluids is in the range of 50-200 microns, and more preferably in the range of 100-150 microns; for use with other biological fluids, a useful length is in the range of 200 microns - 3 mm, and more preferably in the range of 200-400 microns. For circular microneedles having sharp side edges, a useful length for use with interstitial fluids is in the range of 50-200 microns, and more preferably in the range of 80-150 microns; for use with other biological fluids, a useful length is again in the range of 200 microns - 3 mm, and more preferably in the range of 200-400 microns. For solid microneedles having a star-shaped profile with sharp edges for its star-shaped blades, a useful length for use with interstitial fluids is in the range of 50-200 microns, and more preferably in the range of 80-150 microns; for use with other biological fluids, a useful length is again in the range of 200 microns - 3 mm, and more preferably in the range of 200-400 microns, while the radius of each of its blades is in the range of 10-50 microns, and more preferably in the range of 10-15 microns.
Patent TW-464484-B (TW)
Title: Manufacture of multicolored zipper pull tab
Inventor: CHERN DANN-MING
IPC: A44B19/42
Filed: 2000-07-05
Granted: 2001-11-21
Abstract: Disclosed is a manufacture of multicolored zipper pull tab. The manufacture comprising the steps of: injection molding trademark pattern blocks and arranging the blocks into slot holes of a preformed insert plate, transferring the trademark pattern blocks to slot holes in a mold by pressing; placing metal hook in a mold unit; mating the upper mold unit with the lower mold unit; injection molding the zipper pull tab body, where the body encases and retains part of the metal hook and part of the trademark pattern blocks therein, and part of the metal hook and trademark pattern blocks are exposed out of the body, wherein the metal hook is to be coupled to the zipper slide and the trademark pattern blocks render a 3-dimensional and multicolored visual effects. By using the process of inserting the trademark pattern blocks of this invention into an insert plate and then transferred into a mold, the lead-time and cost may be reduced, and the production rate may be increased to meet the economic needs.
Patent TW-477981-B (TW)
Title: Input initial stage circuit for semiconductor memory
Inventor: KATSUHISA TAKUJI
IPC: G11C7/22
Filed: 2000-07-15
Granted: 2002-03-01
Abstract: In a semiconductor memory which includes an input initial stage circuit receiving an external clock for generating an internal clock and an internal circuit operating on the basis of the internal clock, the input initial stage circuit comprises a first inverter receiving the external clock for generating the internal clock, a second inverter receiving an output of the first inverter, and a switch transistor having a control electrode receiving a test mode signal and a main current path connected between an output of the second inverter and an input of the first inverter. This switch transistor is turned on in response to the test node signal, so as to connect the output of the second inverter to the input of the first inverter. With this arrangement, even if the external clock applied at the time of a testing has a voltage transition which is slower than a voltage transition of an external clock applied in a normal operation of the semiconductor memory, the input initial stage circuit can generate the internal clock which correctly reflect the change of the input clock.
Patent TW-513615-B (TW)
Title: Photolithography using a super-resolution near-field structure
Inventor: TSENG TZU-FENG
IPC: G03F7/09
Filed: 2000-07-24
Granted: 2002-12-11
Abstract: Photolithography using a super-resolution near-field structure. Firstly, forming the super-resolution near-field structure on semiconductor chips composed of a base and a photo-resist layer, then irradiating the semiconductor chips by a beam of light so as to expose the photo-resist layer by way of the super-resolution near-field structure. Thus, the super-resolution near-field structure can enhance the magnitude of the beam of light and reduce the diameter of the beam of light while the beam of light passes through the super-resolution near-field structure. The super-resolution near-field structure is composed of a first dielectric layer, a second dielectric layer, and an active layer sandwiched between the first dielectric layer and the second dielectric layer. The active layer is made of a material either selected from a group consisting of gallium (Ga), germanium (Ge), arsenic (As), selenium (Se), indium (In), tin (Sn), antimony (Sb), tellurium (Te), and silver (Ag) or selected from a group consisting of gallium oxide (GaOx), germanium oxide (GeOx), arsenic oxide (AsOx), selenium oxide (SeOx), indium oxide (InOx), tin oxide (SnOx), antimony oxide (SbOx), tellurium oxide (TeOx), and silver oxide (AgOx).
Patent TW-445615-B (TW)
Title: Semiconductor package with enhanced heat dissipation function
Inventor: HUANG JIAN-PING
IPC: H01L23/433
Filed: 2000-08-04
Granted: 2001-07-11
Abstract: The present invention discloses a semiconductor package with enhanced heat dissipation function. In the semiconductor package, the encapsulant is filled only on the upper mold of one die and one lead frame. A heat sink with a thickness adaptive to be selected based on the desired specification is adhered to the die pad and the plurality of leads by an adhesive that is heat conductive but not electrical conductive. Because the thickness of the heat sink can be adjusted as desired, it is very suitable for the manufacture of thin products. In addition, the width of the heat sink is able to cover the die pad and the plurality of leads. Therefore, the heat generated by the die can be exhausted to the atmosphere via the heat sink, and also can be conductive to the connected printed circuit board via the plurality of leads of the lead frame.
Patent TW-490563-B (TW)
Title: Regulable test integrated circuit (IC) system for signal noise and its measurement method
Inventor: LEE MIN-LIN
IPC: G01R29/26
Filed: 2000-08-30
Granted: 2002-06-11
Abstract: The present invention provides a regulable test integrated circuit (IC) system, which is designed by using electric analysis, for signal noise and its measurement method to measure various kinds of noise values for digital signals. The invented system includes the followings; a power supply, which is used to provide a measuring voltage for the system; a pulse generator, which is used to provide a measuring frequency required for measuring signal noise; a regulable test IC for signal noise, which is used to provide the regulable measurement of noise signal by using the built-in plural specified structures based on an assigned current specification and the use of frequency supplied by the pulse generator; a digital oscilloscope, which is used to display and record the measured results of the regulable test IC for signal noise; The present invention also provides a kind of method that uses the electric analysis to realize function of system measurement, and the method includes the following steps: loading an object to be measured; setting a measurement voltage and a measurement frequency for measuring the noise value of the object to be measured under the measurement voltage and the measurement frequency; setting a ratio value of the measured signal, in which the object to be measured is connected to the measurement IC based on the ratio value; using a digital oscilloscope to measure the object to be measured; and recording the measured result from the digital oscilloscope.
Patent TW-535391-B (TW)
Title: Communication on hold
Inventor: KERNER YAIR
IPC: H04L29/06
Filed: 2000-09-05
Granted: 2003-06-01
Abstract: A communication session is established between an APCM modem and a DPCM modem. The central office interrupts the communication session by transmitting a call-waiting alert signal to the APCM modem. In response to the alert signal, the APCM modem transmits a caller ID data request to the central office. The APCM modem further transmits an on hold notification to the DPCM modem to prevent the DPCM modem from terminating the communication session as a result of the interruption by the alert signal and/or receipt of the caller ID data by the APCM modem. The DPCM modem is placed on hold while the APCM modem answers the call waiting. Subsequently, the APCM modem initiates a quick connect procedure to re-establish the communication session with the DPCM modem.
Patent TW-471173-B (TW)
Title: Photosensor system and drive control method thereof cross-reference to related applications
Inventor: KOSHIZUKA YASUO
IPC: H04N5/359
Filed: 2000-09-26
Granted: 2002-01-01
Abstract: A photosensor system including a photosensor array having a plurality of photosensors arranged two-dimensionally comprises a driver circuit and a readout circuit for applying signal voltages to each photosensor, and also a control circuit having a function of controlling the voltages applied to each protosensor and adjusting the sensitivity of each photosensor. During an image reading operation and a reading operation for setting the sensitivity of each photosensor, a correction signal is generated, which has an effective voltage that can adjust an effective voltage, applied to each gate electrode of each photosensor, to 0 V, or to a value that minimizes degradation of the characteristics of each photosensor. This correction signal is applied to each gate electrode.
Patent TW-548940-B (TW)
Title: Generation of a mathematically constrained key using a one-way function
Inventor: SPRUNK ERIC J
IPC: H04L9/30
Filed: 2000-11-20
Granted: 2003-08-21
Abstract: A cryptographic key (K2) is generated using a one-way function (325) and testing for a mathematical constraint. At an encoder (200, 200'), such as at a headend, or a manufacturing site, pre-seed data is obtained by subdividing (320) a random bit string into several segments (PRE-P1, ..., PRE-P8, PRE-Q1, ..., PRE-Q8), then independently processing each segment with a one-way function (325) to obtain respective values (P, Q). The values (P, Q) are tested for a mathematical constraint such as primeness (345). If the values do not pass the test, the steps are repeated. If the values do pass, a modulus N (350), and Euler's Totient phi=(P-1)(Q-1) (355) are formed. Segments Pre-K1-1, ..., Pre-K1-16 are also processed through a one way function to form segments K1-1, ..., K1-16, which are assembled to form a value K1. Euclid's Basic Algorithm (360) is used to determine if K1 is relatively prime to phi. If not, a new K1 is formed. If so, a key (K2) is formed from Euclid's Extended Algorithm (365) for encrypting data. At a decoder (260, 260'), the pre-seed data is provided, e.g., via a chip, and processed using the same one-way function (615) as used at the encoder to obtain the modulus N and the key K1 for use in decrypting the encrypted data.
Patent TW-515047-B (TW)
Title: Decoupling capacitors and methods for forming the same
Inventor: BRYANT ANDRES
IPC: H01L27/08
Filed: 2000-11-29
Granted: 2002-12-21
Abstract: A decoupling capacitor and methods for forming the same are provided. In a first aspect, the decoupling capacitor is formed during a process for forming first and second type FETs on a common substrate that comprises a plurality of implant steps for doping channels and diffusions of the first and second type FETs. In a second aspect, a method is provided for forming the novel decoupling capacitor that includes the steps of forming a mandrel layer on a substrate, including forming openings in the mandrel layer and disposing a first type dopant into the substrate through the openings. Thereafter, an epitaxial layer is formed in the openings on the substrate, an insulator layer is formed in the openings on the epitaxial layer and a gate is formed in the openings on the insulator layer. The mandrel layer is removed and the first type dopant is disposed into the substrate abutting the first type dopant in the substrate that was disposed through the openings. During this step the first type dopant is disposed into the gate. The substrate having the first type dopant comprises one terminal of the capacitor and the gate comprises another terminal of the capacitor.
Patent TW-508820-B (TW)
Title: Integrated circuit inductor structure and non-destructive etch depth measurement
Inventor: NORSTROM HANS
IPC: H01F17/00
Filed: 2000-12-26
Granted: 2002-11-01
Abstract: A method for forming an electrical device structure in an integrated circuit comprises providing a substrate (11); forming a passivation layer (13) thereon; forming a plurality of through holes (15) in the passivation layer, the through holes; removing substrate material under the passivation layer by means of isotropic etching, thus forming at least a first cavity (19) in the substrate beneath the plurality of through holes; forming a dielectric layer (23) on top of the passivation layer to plug the through holes, thereby creating a membrane (24); and creating an electrical device (27), such as e.g. an inductor, above the membrane.
Patent TW-510054-B (TW)
Title: Circuit for processing charge detecting signal
Inventor: HARAGUCHI YOSHIZUMI
IPC: H04N5/335
Filed: 2001-01-29
Granted: 2002-11-11
Abstract: The first present invention provides a circuit for processing charge detecting signal transferred to a floating diffusion amplifier from a charge coupled device. The circuit comprises: a first node connected to the floating diffusion amplifier; a first enhancement type field effect transistor being connected in series between a first fixed-voltage supply line for supplying a first fixed voltage and an output terminal, and the first enhancement type field effect transistor having a first gate connected to the first node; and a second enhancement type field effect transistor being connected in series between a second fixed-voltage supply line for supplying a second fixed voltage and the output terminal, wherein the second enhancement type field effect transistor has a second gate supplied with a third fixed voltage which is different in potential from the second fixed voltage.