Patent GB-1277917-A (GB)
Title: Memory using paired digit sense conductors
IPC: G11C7/02
Filed: 1969-08-29
Abstract: 1277917 Magnetic storage arrangement RCA CORPORATION 29 Aug 1969 [6 Sept 1968] 43072/69 Heading H3B In a magnetic storage arrangement, Fig. 1, a pair of digit-sense conductors 8, 10 have a common end 14 connected to a reference potential by a terminating impedance 16, their other ends being coupled to a differential sense amplifier 40 via a centre-tapped resistor 22, 24, and receiving push-pull drive signals from source 38 via transformer 34. Resistor 16 has a value of half the characteristic impedance Z 0  of a conductor, and the centre tapped resistance is of value 2Z 0 . Diode pairs 28, 30 are stated to prevent voltage build-up in the conductor pair, and a grounded conductive plane 17 is placed adjacent magnetic storage elements 12, which may be cores, thin films or plated wires. Because the conductors receive push-pull drive signals, the input to the sense amplifier is not saturated during writing, and currents are not induced in plane 17, so that interference between conductors is minimized and high switching speeds are usable. The arrangement may be used in four different store configurations. Fig. 2 shows a one digit portion of a word organized store having word conductors 46; for each additional digit of a word, a further system like that the one shown is added to conductors 46. Reading in Fig. 2 is by pulsing a given word conductor, output from a switched element passing to sense amplifier 40 which is appropriately strobed. This is followed by writing, which requires a pulse of reverse polarity in the word conductor with a coincident push-pull pulse on the digit-sense pair 8, 10. To write a "0", this latter pulse is omitted. In Fig. 3, a one digit portion of a 2¢D two wire store is shown, in which word conductors x 1 -x 4  each pass through several elements. However the arrangement has only one element per bit, since the drive currents in conductors 8, 10 are always push-pull and pairs of elements such as 12<SP>1</SP> and 12<SP>11</SP> are operable separately. To read element 12<SP>1</SP>, digit conductors 8, 10 are pulsed, and shortly afterwards a pulse is passed through conductor x 1 . To read element 12<SP>11</SP>, one of these pulses is reversed in polarity. Writing is as in Fig. 2, pulse polarity selecting which of a pair of elements is operated, as in reading. Fig. 4, (not shown), relates to a one digit portion of a 3D or coincident current memory, having a set of row conductors added to Fig. 3. Reading is by coincident pulses on row and column conductors while during writing the digit-sense conductor pairs may be used to inhibit if a "0" is required. In Fig. 5, which forms the basis of the invention claimed in Specification 1,277,916, the conductor pairs are used in a two digit portion of a two core per bit word organized store, the two cores of a bit being, for example, those labelled 12<SP>1</SP>. These two cores are linked by a word conductor 46<SP>1</SP>, and are both on digit-sense conductor 8 of the pair 8, 10. The second digit of word conductor 461 is stored in core pair 12<SP>11</SP>. Conductive planes 17 are located adjacent the conductors. To read word lines 46<SP>1</SP>, switch 761 is opened, and driver 74 actuated to pulse line 46<SP>1</SP>. Any output from the two cores 12<SP>1</SP> is passed to sense amplifier 40 since both cores are on the same sense line 8, and similarly any output from cores 12<SP>11</SP> appears at sense amplifier 40<SP>1</SP>. To write, driver 78 is actuated and a coincident pulse is passed on line pairs 8, 10 and 81, 10<SP>1</SP>, the polarity of the latter pulses determining whether a "1" or a "0" is written in cores 12<SP>1</SP>, 12<SP>11</SP>. The second inputs of the differential sense amplifiers are connected to further conductor pairs 48, 50, and 48<SP>1</SP>, 50<SP>1</SP>, so that Fig. 5 is thus a two core per bit equivalent of Fig. 2. The word lines 46 may be terminated as shown by grounded, centre-tapped resistors at their drive ends, or the centre-tap may be unconnected and the mid-point 56 grounded via a suitable impedance, Fig. 6 (not shown).