baber/WOPTO huggingface dataset:
Patent TW-460900-B (TW)
Title: Method of producing a screen for a display device, screen for a display device produced by means of said method and display device provided with said screen
Inventor: HEEMSTRA TEWE HIEPKE
IPC: G02B5/04
Filed: 2000-02-14
Granted: 2001-10-21
Abstract: In cathode ray tubes with a dotted screen structure (20), current requirements make it necessary to have a screen structure (25) with elongated matrix apertures, in order to have a good performance with respect to moire and luminance. This invention discloses a method of producing a screen for a display device that uses a matrix structure with elongated matrix apertures. In the currently used method, a segmented lens with a plurality of facets is applied. A light-refracting means for instance, a prism (40) with a number of light-refracting surfaces (41), (42) is added to each facet (30), forming an undistinguishable part of the segmented lens. This creates a number of virtual light sources (48), (49) which is equal to the number of light-refracting surfaces. By separating these virtual light sources in the frame (mostly vertical) direction, this will lead to the exposure of an elongated matrix aperture, although a mask (5) with substantially round apertures is used. If the light-refracting means (64), (65), (66), (67) comprise prisms with three light-refracting surfaces (70), (71), (72) oriented in the line (mostly horizontal) direction, it is also possible to separate the three virtual light sources over such a distance that their images on the screen are disjunct and separated by a distance corresponding to the distance of the matrix apertures in a triplet. This makes it possible to expose the matrix in only one step, instead of the traditional three steps.
Patent TW-461114-B (TW)
Title: Semiconductor device manufacturing method
Inventor: KUNIKIYO TATSUYA
IPC: H01L29/49
Filed: 2000-05-17
Granted: 2001-10-21
Abstract: After a channel layer (7) containing nitrogen is formed in a channel region (5) in the main surface of a semiconductor substrate (1), a gate insulating film (9) and insulating films (10) are formed as oxide film by a thermal oxidation on the main surface of the semiconductor substrate (1). The insulating films (10) are thicker than the gate insulating film (9) because the oxidation reaction is suppressed in the nitrogen-introduced region. Further, stresses caused by the oxidation are suppressed around the connections between the gate insulating film (9) and the insulating films (10). Accordingly, reduction in leakage current and improvement of gate insulating film reliability are compatibly realized.
Patent TW-I281096-B (TW)
Title: Image forming composition, image recording material comprising the same, and process of image formation
Inventor: FUJIMOTO TAKASHI
IPC: G03F7/027
Filed: 2000-07-07
Granted: 2007-05-11
Abstract: Disclosed is an image forming composition comprising (A) a film-forming resin and (B) an infrared laser beam absorbing substance, an image recording material comprising the same, and a process of image formation using the image recording material.
Patent TW-527391-B (TW)
Title: Polyolefin resin composition
Inventor: HAMADA NAOSHI
IPC: C08L23/04
Filed: 2000-07-10
Granted: 2003-04-11
Abstract: A polyolefin resin composition comprising (A) an ethylene-based polyolefin having a density of 0.865 to 0.980 g/cm<3> and MFR of 0.01 to 50 g/10 min, (B) a phosphorous compound, and (C) at least one heat stabilizer selected from the group consisting of a phenol-based heat stabilizer and a tocopherol-based heat stabilizer. The polyolefin resin composition has excellent heat resistance, moisture resistance and discoloration resistance, and also when used as a packaging material, does not impair the taste of contents to be packaged, such as flavor or odor, and therefore does not impair the taste of the contents.
Patent TW-477127-B (TW)
Title: Low earth orbit distributed gateway communication system
Inventor: WIEDEMAN ROBERT A
IPC: H04B7/185
Filed: 2000-07-18
Granted: 2002-02-21
Abstract: A method for operating a communication system includes steps of: (a) receiving a call for a user terminal at a satellite system gateway, the call origination from another user terminal; (b) examining a database to determine if the called user terminal is located within a coverage area of the satellite system gateway; and (c) if yes, formulating a paging message and transmitting the paging message to the called user terminal via at least on satellite. Upon the called user terminal responding to the page, the method further: (d) establishes the call using satellite system resources, (e) designates one of the calling or called user terminals as a call manager for the duration of the call, and (f) makes a temporary assignment of satellite system resources to the call manager user terminal for use in managing the remainder of the call. The step of establishing the call includes a step of assigning at least and initial channel/circuit pair to each of the user terminals. A call synopsis is transmitted from the call manager user terminal to the gateway at the completion of the call, and the gateway employs the call synopsis when transmitting billing-related information from the gateway to another gateway with which one or both of the user terminals has an affiliation. The other gateway could be a virtual gateway that serves a localized region within the service region of the gateway. At the completion of the call the assigned satellite system resources are relinquished. Also disclosed are methods and apparatus for extending the effective service regions of gateways and diversity technique, wherein gateways are interconnected for providing user terminal traffic and signalling information between themselves at call setup and during a call.
Patent TW-500937-B (TW)
Title: Liquid crystal display
Inventor: KIM DONG-KYU
IPC: G09F9/30
Filed: 2000-07-11
Granted: 2002-09-01
Abstract: A liquid crystal display includes first and second insulating substrates facing to each other, and a liquid crystal sandwiched between the first and second substrates. A plurality of gate lines are formed at the first substrate to transmit scanning signals, and data lines cross over the gate lines to transmit picture signals. Pads are connected to the gate and data lines. Pixels are demarcated by the gate lines and the data lines, and collectively form a display area. The gate lines demarcate the pixels into rows, and the data lines demarcate the pixels into columns. A black matrix defines each pixel, and a pixel electrode is formed at the pixel. A storage capacitor line is formed at the first substrate parallel to the gate line, and overlapped with the pixel electrodes at the first pixel row. Storage capacitors are formed between the pixel electrodes and the previous gate lines as well as between the pixel electrodes and the storage capacitor line. A gate-off voltage or a common electrode voltage is applied to the storage capacitor line. The opening ratio of each pixel at the first pixel row with the storage capacitor formed between the corresponding pixel electrode and the storage capacitor line differs from the opening ratio of the pixels at the other pixel rows. The difference in the opening ratio is made through forming a light interception pattern at each pixel of the first pixel row, or through differentiating opening volumes of the black matrix. In order to prevent leakage of light, light interception patterns may be formed at the region between the display area and the pads.
Patent TW-505836-B (TW)
Title: Adapter automatically controlling power supply for air conditioning apparatus by sensor
Inventor: PARK TAI-UP
IPC: F24F11/00
Filed: 2000-09-21
Granted: 2002-10-11
Abstract: An adapter automatically controlling a power supply for an air conditioning apparatus by a sensor and individually formed outside of a power supply unit and an air conditioning apparatus, including a single or plural output consents switching with an input power plug by a gas detecting control circuit installed in the adapter; a composite gas sensor operating the gas detecting control circuit; and a detection reference value preset volume controlling an operating range of this composite gas sensor.
Patent TW-I235770-B (TW)
Title: Amorphous alloy
Inventor: INOUE AKIHISA
IPC: C22C45/00
Filed: 2000-09-27
Granted: 2005-07-11
Abstract: The present invention relates to a method of manufacturing an amorphous alloy composite material containing ZrC particles dispersed therein. According to the method, carbon particles and Zr pure metal or Zr alloy are added to alloy as a mother phase, the alloy is melted at a temperature of at least the melting point of Zr pure metal or Zr alloy +100 DEG K, Zr is reacted with C during melting, thereby manufacturing ZrC particles. With this operation, mother alloy, which has a glass forming capability and in which the ZrC particles are uniformly dispersed, is manufactured, and amorphous alloy in which ZrC particles are dispersed can be manufactured by adjusting the ZrC particles. It is preferable that carbon particles and ZrC particles used in manufacture of the alloy have a particle size of 100 micrometers or less, respectively.
Patent TW-469508-B (TW)
Title: Coating apparatus and coating method
Inventor: HASHIMOTO HIROSHI
IPC: H01L21/027
Filed: 2000-10-18
Granted: 2001-12-21
Abstract: This invention relates to a coating apparatus for applying a coating to a surface of a substrate. The coating apparatus comprises a rotating cup, which includes an upper end defining an opening for receiving the substrate; a drive member disposed to drive the substrate located in the rotating cup to rotate; an annular cover having an access opening and disposed on the rotating cup; a coating-ejecting nozzle disposed extendible into the access opening of the annular cover so as to give out the coating to the substrate; a small cover for closing the access opening; a displacing arm disposed to displace the small cover over the accessing opening; and a magnetically attractive member disposed to attract and bring the small cover in engagement with the peripheral portion bordering the access opening so as to prevent the splashing of the coating from the beginning to the end of the coating process.
Patent TW-502355-B (TW)
Title: Bonding pad structure to avoid probing damage
Inventor: KER MING-DOU
IPC: H01L23/485
Filed: 2000-12-15
Granted: 2002-09-11
Abstract: A bonding pad structure to avoid probing damage applied to IC or PCB products at least includes comprises a first pad and at least one a second pad. The first pad is coupled with the second pad. The first pad is used for wire bonding and packaging while the second pad is used for probing in IC function testing. Therefore, it avoids the probing damage of the first pad after the IC function testing and further increases the IC reliability while wire bonding and packaging.
Patent TW-518602-B (TW)
Title: Integrated circuit
Inventor: HATAKENAKA MAKOTO
IPC: H01L21/822
Filed: 2000-12-30
Granted: 2003-01-21
Abstract: The subject of the present invention is to provide an integrated circuit that can achieve the unit test of its memory simply and truly. The solving means is described in the following. Whether a DRAM (202) is normal or not is determined according to a 1-bit identity determination result outputted from an identity/nonidentity determination circuit (205). It obviates the need for assigning a plurality of decision terminals to each chip to be tested such that it is possible to simultaneously test the same number of chips as the total number of the decision terminals of a tester which is physically limited. It can improve test efficiency and reduce test cost.
Patent TW-479355-B (TW)
Title: Manufacture method of non-volatile memory with bias optimization
Inventor: JIANG FU-CHENG
IPC: H01L27/11
Filed: 2001-01-19
Granted: 2002-03-11
Abstract: This invention provides a manufacture method of non-volatile memory with bias optimization, which includes following steps: firstly forming oxide-nitride-oxide (ONO) layer structure on a substrate; part of substrate surface is exposed through lithography and etching process on the ONO structure; bit line is formed by ion implantation; P+ region implantation is carried out; bit line oxide is formed on the bit line; polysilicon layer is formed on the bit line oxide and the ONO structure to form a non-volatile memory cell; and the threshold voltage of the non-volatile memory cell is optimized during the manufacturing process, which enables design and program for correctly corresponding to the writing area or erasing area during electrical writing to silicon nitride or electrical erasing from the silicon nitride.
Patent TW-493267-B (TW)
Title: Semiconductor memory device, method for driving the same and method for fabricating the same
Inventor: SHIMADA YASUHIRO
IPC: G11C11/22
Filed: 2001-02-15
Granted: 2002-07-01
Abstract: Data is read out from a ferroelectric film with its remnant polarization associated with one of two possible logical states of the data and with a bias voltage applied to a control gate electrode over the ferroelectric film. The ferroelectric film creates either up or down remnant polarization. So the down remnant polarization may represent data ""1"" while the up or almost zero remnant polarization may represent data ""0"", for example. By regarding the almost zero remnant polarization state as representing data ""0"", a read current value becomes substantially constant in the data ""0"" state. As a result, the read accuracy improves. Also, if imprinting of one particular logical state (e.g., data ""1"") is induced in advance, then the read accuracy further improves.
Patent TW-I238541-B (TW)
Title: Fabrication of semiconductor materials and devices with controlled electrical conductivity
Inventor: KAPOLNEK DAVID
IPC: H01S5/323
Filed: 2001-04-16
Granted: 2005-08-21
Abstract: A method for protecting the surface of a semiconductor material (30, 50) from damage and dopant passivation is described. A barrier layer (32, 52) of dense or reactive material is deposited on the semiconductor material shortly after growth in a growth reactor (10) such as a MOCVD reactor, using the MOCVD source gasses. The barrier layer (32, 52) blocks the diffusion of hydrogen into the material. The reactor (10) can then be cooled in a reactive or non-reactive gas ambience. The semiconductor material can then be removed from the reactor (10) with little or no passivation of the dopant species. The barrier layer (32, 52) can be removed using a variety of etching processes, including wet chemical etching or can be left at the semiconductor material for surface protection. The barrier layer (32, 52) can also be a gettering layer that chemically binds hydrogen trapped in the semiconductor material and/or blocks hydrogen diffusion into the material.
Patent TW-516125-B (TW)
Title: Semiconductor device and apparatus for manufacturing semiconductor device
Inventor: ITATANI HIDEHARU
IPC: H01L21/8242
Filed: 2001-03-15
Granted: 2003-01-01
Abstract: This invention provides a semiconductor manufacturing method and apparatus having an excellent step coverage and capable of manufacturing semiconductor devices at low cost. The apparatus includes a reaction chamber 4 adapted to accommodate a substrate 1, a gas feed port 5 through which a raw material gas is supplied to the reaction chamber 4 for forming ruthenium films or ruthenium oxide films on the substrate 1, and a gas exhaust port 6 through which the raw material gas is exhausted from the reaction chamber. The raw material gas is directed from the gas feed port 5 toward the substrate 1, and subsequently to form ruthenium film or a ruthenium oxide film by means of the thermal CVD method under film-forming conditions different from the said film-forming conditions, the ruthenium film or the ruthenium oxide film having a thickness greater than that of the said ruthenium film or the said ruthenium oxide film.
Patent TW-517342-B (TW)
Title: Silicon on insulator field effect transistors having shared body contacts
Inventor: DAKUTERA WILLIAM R
IPC: H01L21/8244
Filed: 2001-03-22
Granted: 2003-01-11
Abstract: Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.
Patent TW-523784-B (TW)
Title: Substrate processing apparatus and substrate processing method
Inventor: KITANO JUNICHI
IPC: H01L21/00
Filed: 2001-03-29
Granted: 2003-03-11
Abstract: A controller controls the temperature of a hot plate and the degree of vacuum in a tightly closed space to a temperature and a pressure at levels at which a thinner contained in a resist applied to a wafer volatilizes and an acid generator, a quencher, and a polymer chain protecting group practically remain in the resist, for example, during heat processing. More specifically, the controller controls the temperature of the hot plate and the degree of vacuum in the tightly closed space to bring the temperature of the hot plate to about 40 DEG C., and the degree of vacuum in the tightly closed space to approximately 5 Torr. Thereby, the heat processing can be performed for the wafer so that the acid generator is uniformly dispersed in the resist, or the quencher is uniformly formed on the front face of the resist without breakage of the polymer chain protecting group.
Patent TW-479336-B (TW)
Title: Method for preventing wire crossing during under-filling operation
Inventor: YAU JIN-TSAI
IPC: H01L23/28
Filed: 2001-04-10
Granted: 2002-03-11
Abstract: The present invention relates to a semiconductor package, and particularly provides a solution for the wire crossing phenomenon due to wire sweep caused by the molding flow in the under-filling operation. The present invention is characterized in, based on the direction of the molding flow, finding some wires influenced by larger molding flow bump and possible to sweep and cross, and setting up some braking devices (such as objects for supporting) to prevent the wires from crossing the other wires. The present method for preventing wire crossing during under-filling operation is suitable for various shapes of packages, various types of wire arrangements, various kinds of semiconductor device installation positions, various kinds of under-filling molding flow direction (or various kinds of under-filling opening position and direction).
Patent TW-507182-B (TW)
Title: LCD of impulse driving method and driving method thereof
Inventor: KWON SU-HYUN
IPC: G02F1/133
Filed: 2001-04-23
Granted: 2002-10-21
Abstract: There is provided an impulse driven LCD which comprises: a timing controller for outputting normal data, random data for impulse generation, and a first control signal for controlling the output of the normal or random data, and for outputting a second control signal for controlling display of an image signal according to the normal or random data; a scan driver for sequentially outputting first and second scan signals for a 1H period according to application of the second control signal; and a LCD panel for charging the normal data signal to the liquid crystal capacitor according to application of the first scan signal, and for charging the random data signal to the liquid crystal capacitor according to application of the second scan signal.
Patent TW-494504-B (TW)
Title: Semiconductor apparatus and its manufacturing method
Inventor: FUNAKURA KAN
IPC: H01L23/31
Filed: 2001-04-24
Granted: 2002-07-11
Abstract: The present invention proposes a semiconductor apparatus comprising: a semiconductor chip; a wiring substrate having the semiconductor chip mounted thereon; an under-fill resin sheet interposed between the semiconductor chip and the wiring substrate; and a resin sealing body for sealing the semiconductor chip; the under-fill resin sheet and the wiring substrate, wherein the under-fill resin sheet is greater than the semiconductor chip in size, and its end is exposed from at least one side face of the resin sealing body.
Patent TW-584668-B (TW)
Title: Rapid identification of porcine estrogen receptor marker
Inventor: CHANG HSIU-LUAN
IPC: C12Q1/68
Filed: 2001-05-22
Granted: 2004-04-21
Abstract: A method for rapidly identifying porcine estrogen receptor (ESR) marker comprises using published primers to amplify the target DNA fragment by polymerase chain reaction (PCR). The DNA fragment is cloned and then sequenced. The key positions of the sequence are modified to generate three primers which are used to amplify different DNA fragments with different genotypes by PCR to eliminate extra restriction cut reaction. A long one of the primers is to specifically amplify non-prolific allele, a short one of the primers is to specifically amplify prolific allele, and the remaining one is mutual and complimentary to the sequence. After PCR and electrophoresis, the sample with 90 bp band is identified as prolific genotype, the sample with 110 bp band is identified as non-prolific genotype, and the sample with 90 bp and 110 bp bands is identified as hetero-genotype.
Patent TW-524900-B (TW)
Title: Material for bismuth substituted garnet thick film and a manufacturing method thereof
Inventor: SATO TADAKUNI
IPC: C30B19/12
Filed: 2001-06-05
Granted: 2003-03-21
Abstract: A material for a bismuth substituted garnet thick film comprising Gd, Yb, Bi, Fe and Al as the main ingredient grown by a liquid phase growing method on a garnet substrate in which the composition of the garnet thickness is represented by the general formula: Gd3-x-yYbxBiyFe5-zAl2O12 (0 < x ≤ 0.5, 0.85 ≤ y ≤ 1.55 and 0.15 ≤ z ≤ 0.65), and each of boron oxide (B2O3) and lead oxide (PbO) is contained by from 0 to 4.0 wt% (not including 0) in the garnet thick film.
Patent TW-537924-B (TW)
Title: Process for the production of olefins
Inventor: GRIFFITHS DAVID CHARLES
IPC: C07C5/333
Filed: 2001-08-01
Granted: 2003-06-21
Abstract: A process for the production of an olefin comprising partially combusting in a reaction zone a mixture of a hydrocarbon and an oxygen-containing gas in the presence of a catalyst which is capable of supporting combustion beyond the fuel rich limit of flammability to produce the olefin, wherein the superficial feed velocity of said mixture is at least 250 cm s<-1> at standard temperature and operating pressure with the proviso that where the catalyst is an unsupported catalyst, the superficial feed velocity of said mixture is at least 300 cm s<-1> at standard temperature and operating pressure.
Patent TW-574059-B (TW)
Title: Method for recovering high purity salt from waste solution of salting-out of dye
Inventor: WU JEN-FANG
IPC: C25F1/00
Filed: 2001-09-21
Granted: 2004-02-01
Abstract: A method for recovering high purity salt (sodium chloride or potassium chloride crystals) from a waste solution of salting-out of dye without secondary pollution comprises: (1) performing an evaporation concentration treatment in order to crystallize over-saturated inorganic salts, e.g. sodium chloride or potassium chloride etc. contained in a waste solution; (2) adding a salt solution recycled from the subsequent step into the wet crystals obtained by filtration evaporation crystallization to form a suspension, and using an electrolysis oxidation method to oxidize and decompose the dye and intermediates thereof adhered over the surface of the crystals; and (3) filtering and drying crystals and recycling the filtered salt solution.