Patent UA-98694-U (UA)
Title: Shaper single of double pulse code series with programmable time parameters
Inventor: KOROBKOV MYKOLA HRYHOROVYCH
IPC: H03K3/78
Filed: 2014-09-15
Abstract: Shaper single of double pulse code series with programmable time parameters includes: reversible binary counter adjusted to the mode subtraction, which has input supply pulse synchronization input adjustment on mode summation / subtraction, entry permit regime counting, entry permit simultaneous parallel downloads and inputs supply data , asynchronous input settings in the zero state, the output overflow; D-trigger synchronous with asynchronous input settings in the zero state; inverter; the first and second elements OR; the first and second elements I; chain consisting of series connected resistor and capacitor, and the common point of series connected resistor and capacitor connected to the information input of D-flip-flop, with one input of the first and second dvovhodovoho item I; dvovhodovoho first output element and is connected to the input asynchronous installation D-flip-flop in the zero state; a second input of the second element is connected to the output of the first OR element, one of the inputs is connected to the output of D-flip-flop; counter overflow output connected to the input of the inverter; inputs parallel data download counter inputs form programming shaper to set the timing pulses on the output of the shaper; output of the second element is connected to the input settings asynchronous counter in the zero state; counter clock input entry forms generator - supply input periodic sequence of pulses output from the external oscillator; clock input of D-flip-flop forms the input supply pulses start forming the output pulse shaper. Introduced: The first, second and third JK-flip-flops with asynchronous input settings in the zero state; third and fourth elements I; NAND element, with the first JK-flip-flop has two inputs J, and united in, and the second - JK-flip-flop has two inputs K, united by I; inverted output of the first JK-flip-flop is connected to the direct input of the second JK-K flip-flop, and the inverted output of the second JK-flip-flop is connected to the direct input of the first JK-K flip-flop and a second input of the first element I; direct access to the second JK-flip-flop is connected to the input mode permission download counter, a second input of the first element OR, the first inputs of the third and fourth elements I; counter overflow output connected to the inverse inputs J and K of the first JK-flip-flop and the first input NAND element, the second input is connected to a second input of the third element I and an inverted output of the third JK-flip-flop; output inverter connected to a second input of the fourth item I; And the third element output is connected to the inverse inputs J and K of the third JK-flip-flop; out-HI element and is connected to the input mode permits counting counter; direct access to the third JK-flip-flop is connected to the first input of the second OR element, the second input is connected to the output element I; output of the second element or form generator output; JK-clock inputs of flip-flops is connected to the input shaper; asynchronous inputs settings in the zero state JK-flipflops connected to the output of the second element I.