Patent GB-1054784-A (GB)
IPC: G11C7/02
Abstract: 1,054,784. Magnetic data storage apparatus. WESTERN ELECTRIC CO. Inc. Aug. 1, 1963 [Aug. 7, 1962], No. 30554/63. Heading H3B. A two-core-per-bit memory comprises a high magnetic permeability base member 11 having a plurality of posts 12 protruding therefrom and a magnetic member 18 having rectangular hysteresis characteristics positioned on top of the posts to form groups of first and second memory cells, each including a closed flux path 24 through the base member 11, two of the posts 12 and the magnetic member 18. In the memory of Fig. 1 word conductors 13 and bit conductors 15 define a plurality of bit addresses, each address comprising two memory cells, one of the conductors 13 and one of the conductors 15 passing between the posts 12 of each memory cell. A binary word is written in by the application of a positive write signal simultaneously to a selected one of the word conductors and a positive or negative signal to each of the bit conductors 15, depending on the binary value to be written. The magnitude of the write pulses is such that the resulting magnetizing force in each cell exceeds the coercive force of member 18 only when the individual forces of the two signals are additive. Each bit address has only one of its memory cells switched from a reset to a set condition so that when a subsequent negative polarity read-out signal from 14 is applied to the selected one of the word conductors 13, the set memory cell of each bit address is switched back to the reset condition and output signals are induced in the bit conductors 15 1 , 15 2 , 15 3 . The arrangement of the word and bit conductors is such as to eliminate noise signals induced in the conductors 15. Each of the word conductors may alternatively pass twice in the same direction through a selected one of the slots and return by passing once through each slot adjacent to the selected one, Fig. 3 (not shown). Also, separate sense conductors may be used rather than the bit conductors for the sensing of the output signals. In another embodiment, Fig. 4 (not shown), non-destructive read-out of the information is achieved by means of two sheets placed over the posts, the lower sheet having a low coercive force and the upper sheet having a high coercive force. Read-out is accomplished by the application of interrogating signals to word conductors of a magnitude sufficient to cause flux switching in the lower sheet but not the upper sheet. After read-out the magnetic fields of the upper sheet restore the flux in the lower sheet to its previous condition. The conductors may be in the form of printed circuits on both sides of an insulating board provided with apertures corresponding to the posts of the base member. In the embodiment of Fig. 5 (not shown), the two memory cells comprising a bit address are linearly arranged with each cell utilizing a common post and two bit addresses linearly arranged also use a common post. In Fig. 6 the word conductors and bit conductors follow straight line paths between the posts. During the write phase positive write signals are applied to the word conductors 63 simultaneously with write signals applied to bit conductors 65 of positive or negative value depending upon the particular binary value being stored. The write signals are of a magnitude sufficient to establish in the member 18 above the bit addresses remanent magnetic conditions showed by arrows 73, 74, 75, arrow 74 representing a " 1 " and arrow 75 a "0." A subsequent negative read-out pulse applied to the word conductors induces output signal in sensing wires 66. The coincident current operated memory of Fig. 7 (not shown), is similar to that of Fig. 5, except that double word and bit conductors are employed.