Patent GB-960511-A (GB)
Title: Improvements to pulse transmission system
IPC: H04J3/06
Filed: 1962-05-04
Abstract: 960,511. Multiplex pulse code signalling. STANDARD TELEPHONES & CABLES Ltd. May 4, 1962 [May 10, 1961], No. 17214/62. Heading H4L. In a time division multiplex pulse code modulation receiving system in which an incoming trunk carries m transmission channels in time succession, the data concerning each channel being constituted by a p-digit serial binary number, in which each binary number on reception is stored in a data store having a compartment for each channel, and wherein the data on reception may have suffered some displacement in time position of some of its binary elements, each binary number is checked for accuracy of time position and if an inaccuracy in time position is present the insertion of that number into the appropriate compartment of the data store is delayed by an amount determined by the extent of the inaccuracy. The invention relates to the synchronization of signals from a multiplex trunk applied at the input of a P.C.M. telephone exchange in which variation of timing may occur as compared with the timing controlled by the local clock generator, the messages being registered in the data store at the trunk time and correction (if necessary) applied so that they are read out at the exchange time. As described, the analogue signals are sampled 10,000 times per second, i.e. each 100 microseconds, each trunk carries 25 channels, the twenty-fifth being a synchronization code, each channel occupying 4 microseconds, and the amplitude modulated pulses are coded in a 7 digit binary code, an 8th digit being added for checking purposes. A clock 310, Fig. 2, controls the exchange timing and defines channel time slots t1 to t25, each channel time slot being divided into eight digit time slots 1 to 8 and each digit time slot being sub-divided into four basic time slots a, b, c, d. The incoming message signals are designated W1.1 to W1.8 for the first channel W2.1 to W2.8 for the second channel &c. and the corresponding addresses in the data store for the respective channels are V<1>1.1 to V<1>1.8 &c. and they must be selected at the precise time that the corresponding signals appear on the incoming trunk. To select an address in the data store 160, a digit selector advances one position at each basic time slot c and a channel selector advances one position when the digit selector is in position 8 the digits being stored during basic time slot b. Means are provided for correcting for both " slow fluctuations " which produce a variation in the repetition frequency of the message signals and " fast fluctuations " which produce a variation of the time position of a message signal on either side of its mean position. The data store is in the form of a matrix for each trunk having 24 columns and 7 rows. In Fig. 2 a plurality of incoming trunk circuits E 1 to En are shown which are connected sequentially to a common synchronization circuit 200. Taking trunk E1 (reference 100) for example, incoming signals at 10 are applied to pulse regenerator 110 to remove the " fast fluctuations " and which also supplies a timing reference signal on conductor 14 which represents the trunk timing and has a width equal to the width of a basic time slot a, b, c, d as determined by clock 310 and a phase representative of the timing of the signal on lead 13. Selector 331 controls the selection of the trunk which is to be examined as regards digit timing via leads 33 controlled, by AND gates (not shown) represented by arrows 33 and selection 341 controls the selection of the trunk for correcting digit and channel synchronization via leads 34 controlled by AND gates represented by arrows 34. The regenerated signal 13 is supplied to a retiming unit 120 comprising a buffer store 130 in which the signals are stored at the trunk time and read at the exchange time and a variable delay circuit 140. The phase shift due to " slow fluctuations " is measured periodically at block 280 by comparison between clock pulses from generator 310 at the basic repetition frequency, the previous timing information stored at 120 and supplied via lead 17 and the reference signal or present timing information on conductor 14. Fig. 3 shows five consecutive digit time slots subdivided into basic time slots a, b, c, d, the information which may be produced by circuit 280 being represented by A, B, C and D indicating a slow fluctuation and shown as crosses. This information is transmitted via the conductor 15 to read the message signal stored at 130 at the time a, b, c or d respectively five basic time slots after the associated rcference signal. The message signal is read always at time d of the same digit time slot from the delay 140 and written during time b of the next digit time slot in data store 160. Time slots c, d are reserved for reading from the data store. On changing from condition A to condition D or D to A, an error of more than one digit time slot may ocour and this is corrected by similarly delaying or advancing the digit counter controlling the data store 160, this operation being performed during the synchronization code period since this code is not stored. This error infomation when provided by block 280 produces a signal on either of two conductors 12a, or 12r and on conductor 29 which control an error correction unit 210. The synchronization code is set up sequentially for each trunk in block 230 and compared with the incoming signals on lead 11, an output signal being provided on lead 24 when the incoming synchronization code is recognized as agreeing with that set up. A signal 16 is transmitted from the data store 160 to the clock 310 when the address V25.1 is reached and for eight digit time slots a signal is supplied by the clock via OR gate 231 to activate the coincidence detector 230. Synchronism or lack of synchronism must occur three times in succession as registered by a synchronism detector 250 before any further action takes place. If synchronism is registered as lost, conductors 26 and 42r are energized and the address counters blocked temporarily. If within a frame period " coincidence " is detected, the signals 26 and 42r are cancelled and the address counters unblocked. Any error information present on conductors 12a or 12r is transmitted via block 210 to the data store 160 via conductor 22a or 22r, giving a lead or lag of one digit time slot respectively as appropriate, this operation being restricted to the synchronization code period by a signal on lead 25. When channel synchronization has been carried out on a particular trunk the operation is started on the following trunk unless error inforation has in the meantime been stored in block 210 in which case a signal on lead 28 from error correction unit 210 temporarily prevents operation of the selector 34. Details of the logic circuitry are included, Figs. 4 to 8 (not shown). Specification 936,612 is referred to.