Patent GB-1511553-A (GB)
Title: Data processing systems
IPC: G06F11/16
Filed: 1975-05-23
Abstract: 1511553 Checking parallel data processors CSELT-CENTRO STUDI E LABORATORI TELECOMUNICAZIONI SpA 23 May 1975 [3 June 1974] 22854/75 Heading G4A Data being transferred between data memories MD1, MD2, Fig. 1, of a data processing system, and respective computing units CPU1, CPU2 operating in parallel, are checked for identity by means of identical logic units LC1, LC2, each logic unit being connected between a respective computing unit and a respective data memory, and each logic unit comparing its own data with that of the other logic unit. Each logic unit, e.g. LC1, comprises a microprogrammed logic circuit, e.g. LF1, controlling on connections 16, 30 the transfer of data, a microprogrammed logic circuit, e.g. PL1, controlling on connections 31, 32 the parallel operation of the system associated with the computing unit CPU1, and an operating unit, e.g. ED1, for temporarily storing data being transferred. Each operating unit, e.g. ED1, comprises a matrix buffer store B, Fig. 3, for the above data storage, the buffer store B having a plurality of rows addressed by a counter CW for reading and writing operations in the data memory, and by a counter CR for checking operations. Each row of the buffer store is divided into four sections B1-B4, for storing respectively an address in the data memory MD, data to be written into the data memory MD, data read from the data memory MD, and parity check data. Operations within each operating unit, e.g. ED1, are controlled by AND gates P1-P20 enabled by signals from the connections 16, 32 of respective microprogrammed logic circuits, e.g. LF1, LP1. In operation, a comparison circuit CFR checks whether the contents of the counters CR, CW are unequal, and therefore whether there is data in the buffer store B that has not yet been checked, after each reading and writing operation in the data memory. If inequality is found between the contents of the counters CR, CW, the microprogrammed logic circuit LP1 is signalled on a connection 15 to begin a checking procedure, a signal on the connection 31 preventing, inter alia, the logic circuit LP2 from beginning its checking procedure until that of the logic circuit LP1 is completed. The contents of the counter CR and of the particular row of the buffer memory B being checked in the operating unit ED1 are then transferred to the associated operating unit ED2 via a connection 27 where they are temporarily stored, the corresponding quantities for the operating unit ED2 being transferred to the operating unit ED1 via a connection 20. The contents of each section B1-B4 of the particular row of the buffer memory B of the operating unit ED1 are then successively compared in the comparison circuit CFR with those transferred from the operating unit ED2. If identity is found, the inhibiting signal on the connection 31 is removed and the operating unit ED2 then carries out the same check. The counter CW is then advanced by one and the reading or writing operations in the data memory continue. If, on the contrary, the comparison circuit CFR indicates a discrepancy in the data being checked, an alarm signal is sent to the computing units CPU to halt processing. If the discrepancy is recognized during a writing operation, the data memory may be cleared of new (written-in) data by means of a resetting procedure wherein the old (recently-read) data from the data memory is restored, the old data having been stored in the buffer store B.