Patent GB-1298833-A (GB)
Title: Improvements relating to frequency control arrangements
Inventor: FRANKLIN DONALD PETER
IPC: H03L7/14
Filed: 1969-03-13
Abstract: 1298833 Automatic frequency control EMI Ltd 11 March 1970 [13 March 1969] 13266/69 Heading H3A A frequency control arrangement comprises a local oscillator 31, a variable frequency generator, e.g. counter C for varying the output frequency of the oscillator, a binary bidirectional accumulator D arranged to be incremented by the applied signal or a signal derived therefrom and decremented by the generator (or vice versa), the generator being controlled in dependence on the state of accumulator D to maintain a desired relationship between the applied and output signals, and an arrangement 33, 36 for clearing the accumulator when the duration of a fade of the applied signal exceeds a threshold value and an arrangement 34, 35, 37 for switching the accumulation rate to a faster rate on the reappearance of the applied signal and for switching back to the initial rate once the desired relationship is achieved. Input binary data received by a receiver 2 is converted from a "non-return to zero" form to a "return to zero" form, i.e. a series of positive spikes by network A. Network B consisting of a 1 ns. delay 10, inhibit gate 11, OR circuit 12, pulse generator 13, a 8À33 ns. delay converts the input pulses into a crude clock train. To obtain a wider error range, the eighth harmonic of the clock train is modulated at 17 with a signal 959.84 MHz derived from a stable oscillator 31. The lower side-band is filtered off to produce a 320Œ96 kHz signal to be applied as an incremental input to one each of pairs of AND gates 28, 35. In the presence of a signal, a drop-out senser feeds signals via line 47 and bi-stable 34 to keep gates 28 open, but gates 35 closed. Gate 28 feeds a binary bidirectional accumulator D. A divided output of oscillator 31 is fed to a binary counter C. The output of 1st stage B14 is applied directly to an OR gate 29. The outputs of stages B1-B13 and stages S1-S13 of the accumulator are connected to AND gates G1-G13. At any time, only one stage of counter C has a non-carry transition producing a unidirectional pulse. The corresponding AND gate then applies a further pulse to OR gate 29, the output of which is divided down at 30 and fed as a decremental input to the second of the gates 28. In normal operation, the accumulator operates to keep the rates of increment and decrement the same, i.e. to synchronize divider 30 output with the input applied from OR gate 27. With the loss of input signal, drop-out sensor 33 closes the pair of gates 28, the accumulator D remains at its last state and the pulse output from gate 29 will be maintained at the last rate attained. When the loss of signal is over a long interval sensor 33 clears accumulator through reset 36 and sets bi-stable 34 to keep gate 35 open and gate 28 closed so that when the signal reappears, it is carried forward to stage S5. When the decremental rate transiently exceeds the incremental rate, reset 37 trips bistable 34 and the input pulses are applied to stage S1 1 to achieve a finer balance. The output of divider 30 is regularized by further division to 20 Œ 6 kHz and then modulated with the 119À98 MHz signal from oscillator 31 to obtain a clock output signal 120 Œ 0À006 MHz synchronized to the input signal received. To ensure phase tracking as well, a signal from generator 13 is modulated at 48 with a 119À98 MHz signal to obtain an approximately 20 kHz signal for resetting dividers 38-40. An alternative to the above method of phase synchronization is indicated at Fig. 2 (not shown) wherein a phase comparator (52) and a controlled oscillator (49) is used.