Patent GB-1210214-A (GB)
Title: Improvements in or relating to apparatus for synchronising the frequency of a generated signal to a reference frequency
Inventor: ROBSON ALAN
IPC: H03L7/00
Filed: 1967-01-17
Abstract: 1,210,214. Automatic speed control. ELECTRIC & MUSICAL INDUSTRIES Ltd. Jan. 12, 1968 [Jan. 17, 1967], No.2345/67. Heading G3R. The speed of a tape drive motor is controlled by a frequency comparator circuit, a signal whose frequency represents the speed of the motor being applied to terminal 1, whilst a reference signal is applied to terminal 2, the output at terminal 20 supplying a servo for regulating the speed of the motor. A bi-directional shift register has stages 3-6 which are interlinked so that only one stage is in a '1' state when it receives an input pulse, the other stages being in the '0' state. Assuming that the motor is to be started and that stage 3 is in the '1' state, the reference frequency signal is applied to AND gates 7-9 the output of stage 3 being applied through delay circuit 10 to the gate 7. The latter passes a signal through OR gate 17 to stage 4 which changes to the '1' state, causing stage 3 to change to the '0' state. The output from stage 4 is delayed by circuit 11 and then applied to gates 8, 14, the next reference pulse enabling the gate 8 whose output is transferred through gate 18 to the stage 5. The output from the latter is applied through delay circuit 12 to gates 9, 15. If a further reference pulse arrives, gate 9 passes a signal to stage 6 whose output is applied through delay circuit 13 to gate 16. A further output is taken from stage 5, 6, through gate 19 to the terminal 20. Thus, the '1' state shifts from stage 3 to stage 6 where it remains until the motor begins to move and a pulse appears at terminal 1. The gate 16 is then enabled, and a signal passes through gate 18 to stage 5, the '1' state repeatedly shifting between the stages 5 and 6 until two pulses from the shaft are uninterrupted by a reference pulse. The '1' state is then shifted to stage 4 to remove the acceleration signal from terminal 20 and substitute a deceleration signal. Thereafter, the '1' state passes repeatedly between the stages 4 and 5 as successive reference pulses follow successive shaft pulses, the markspace ratio of the output signal from the terminal 20 eventually attaining a value to give precise speed regulation. The delay circuits 10-13 prevent false operation of the system. When the reference frequency is reduced, the '1' state is shifted to the stages 3 and 4 and the output signal drops to zero until two reference pulses are uninterrupted by a shaft pulse. After this, alternate "on" and "off" signals keep the motor running at the new speed by shifting the '1' state between the stages 4 and 5. The stages 3-6 are formed by transistors 50-53, diodes 61-72 and resistors 81-92; the AND gates by transistors 73-78; whilst the collector circuits of transistors 73, 77, and 74, 78, form the gates 17, 18. The gate 19 is constituted by diodes 54, 55, whilst the delay circuits comprise capacitors 93-96. When transistor 50 is conductive, the voltage-drop across resistor 97-98 causes diodes 65, 68, 70, to conduct, thus ensuring that the transistors 51-53 are cut off. When a reference pulse is applied to the emitter of transistor 73, transistor 51 is turned on whilst transistor 50 becomes non-conductive. The remaining transistors 74-78 function in a similar manner.