Patent GB-914829-A (GB)
Title: Analog-to-digital converter
IPC: H03M1/00
Filed: 1961-06-02
Abstract: 914,829. Electric selective signalling systems. BECKMAN INSTRUMENTS Inc. June 2, 1961 [Oct. 13, 1960], No. 19904/61. Class 40(1). A voltage digitizing system of the type in which an unkown voltage is compared with a succession of known voltages, the known voltages being so produced that each differs from its predecessor by a unit increment in its highest denomination until the highest denomination cannot be increased further without exceeding the unknown voltage, and after this each differs from its predecessor by a unit increment in its second highest denomination until this denomination cannot be increased further without exceeding the unknown voltage, and so on for the remaining denominations, is characterizod in that each denomination of the known voltage, after the highest denomination, can be increased by a number of unit increments greater than the radix of the country scale being used. This means that if, in the production of the sequence of known voltages, any denomination is not increased the correct number of steps the error can be corrected by increasing the next denomination by more steps. Thus, if, for example, the unknown voltage is approximately 0.5155, then this would be correctly digitized, as indicated by the full lines in Fig. 1b, by adding increments to the highest denomination of the known voltage until 0.5 is reached, and then adding increments to the next denomination until 0.01 is reached (giving a total of 0.51) and so on. If, however the highest denomination is only increased to 0.4 (dotted lines, Fig. 1b) before increments are added to the next denomination, this error can be rectified by allowing the second denomination to receive eleven increments so that it reaches 0.11 (giving a total of 0.51 as before). An error in the other direction, i.e. if the first denomination were raised erroneously to 0.6, can be corrected subsequently by permitting the next denomination to become negative. In the particular embodiment described each decimal digit is represented by four binary bits (which is of course quite usual) but instead of restricting the count within each decimal denomination to 10, it is allowed to rise to 16, and to allow for the possibility of errors of the second type mentioned above (where 0.6 was notched-up instead of 0.5) without the necessity of using negative increments each denomination, when it is receiving increments, is biased by an amount equal to 0.3 times unit increments in the lower denominations so that, in effect, the six (16-10=6) spare increments in each decimal denomination are shared out as 3 positive and 3 negative increments. Thus as described there are four binary-weighted resistors 50, 51, 52, 53 and a biasing resistor 84, Fig. 3, per denomination, and a digitizing operation proceeds as follows. At time To each biasing resistor is switched into circuit, giving a bias of 0.0333 and the 8-weight resistor of the highest denomination is switched into circuit. The unknown current at 104 and the known current at 14 are then subtracted and if the known current is the larger a signal is produced by a monostable circuit 37. This signal if produced lasts long enough to be gated with clock-pulse T 1  and to cause the 8-weight resistor from circuit. Clock-pulse T 2  also switches the 4- weight resistor into circuit and a further comparison. Similar operations occur for the 2 and the 1-weight resistors. At time T 4  the 8-weight resistor of the next denomination is switched into circuit and simultaneously the biasing resistor 84 of the highest denomination is removed from circuit, leaving a bias of 0.0033, and the 1-weight resistor is removed from or left in circuit in dependence upon the result of the previous comparison. This process continues and at time T 17  the result is transferred to storage flip-flops for recording into conventional binary-coded-decimal form. The switches, shown as relays, could be electronic devices.