Patent GB-983343-A (GB)
Title: Semiconductive oscillator-mixer device
IPC: H03D7/12
Filed: 1963-04-24
Abstract: 983,343. Semi-conductor devices. WESTINGHOUSE ELECTRIC CORPORATION. April 24,1963 [May 11, 1962], No. 16184/63. Heading H1K. [Also in Division H3] A semi-conductor device comprises a doped semi-conductor substrate formed with doped areas to form the functional equivalents of two transistors and associated resistors such that one transistor can act as an oscillator and has its emitter D.C. coupled by a resistor to the base of the second transistor which can act as a mixer. As shown, Figs. 1 and 2, the device comprises a high resistivity N-type substrate 10 in which are formed P-type regions 21 to 27 and lower resistivity N-type regions 31 to 34. Metallic contacts are made to regions 41 to 47 and 61 to 64, the rest of the substrate being covered by an insulating oxide layer. Interconnections 48 to 50 are then formed on top of the insulation. Regions 31 and 21 form the emitter and base of a transistor T1 whose collector is formed by part of substrate 10 and low resistivity region 33 which is formed in a recess in the lower surface of the substrate. Regions 32, 22, 10 and 34 similarly define a second transistor T2. The equivalent circuit of the device is shown in Fig. 4, the reference numbers corresponding to those of the various regions of the device. An external quartz crystal connected between the collector and base of T1 causes it to oscillate, the output being directly coupled to the base of T2 from the centre tap of the emitter resistor. The RF input signal is applied directly to the base of T2 or may be applied to the emitter of T1. T2 acts as a mixer and the output signal is taken from its collector. The device may be manufactured from a single wafer of N-type silicon, doped with arsenic, antimony or phosphorus, by oxidizing the surface, by heating in an ambient of argon containing water vapour, applying a photoresist mask and etching the oxide layer. Boron is then diffused into the wafer to form P-type areas 21 to 27 while the surface is simultaneously re-oxidized by the presence of water vapour. The surface is then re-masked and etched and phosphorus is diffused in to form N-type areas 31 to 34 again simultaneously re-oxidizing the surface. The surface is again masked and etched and metal contacts 41 to 47 and 61 to 64, for example of aluminium, are evaporated on to the surface. The contacts are alloyed to the wafer and interconnections 48 to 50 are applied on top of the oxide layer. Connecting leads are then brazed to contacts 41, 43, 44, 45 and 47 and the device is mounted on a header and hermetically sealed. The various regions may also be fabricated to form a mesa structure and may also be applied by alloying or epitaxial deposition. Resistive region 23 may be made variable by applying a conductive strip across the ends of the structure and cutting this strip in various places to produce the required resistance. Tapping point 44 may also be shifted to vary the bias voltage. The two transistors may be individually tested before applying the interconnections. The substrate may also be germanium, a compound of two Group IV elements such as silicon carbide, a III-V compound such as gallium arsenide, or a II-VI compound such as cadmium sulphide. Specification 908,553 is referred to.