Patent GB-1247583-A (GB)
Title: Improvements relating to semiconductor devices
IPC: H01L23/544
Filed: 1969-01-09
Abstract: 1,247,583. Integrated circuit manufacture. INTERNATIONAL BUSINESS MACHINES CORP. 9 Jan., 1969 [15 Jan., 1968], No. 1378/69. Heading H1K. [Also in Division G1] In the manufacture of a great many integrated circuits in/on an N- epitaxial layer on a P- silicon substrate wafer some of the circuit sites are occupied by test patterns of one of two kinds. At some sites the test pattern is used to check device characteristics and at other sites a different test pattern is used to check metallization characteristics. Each test pattern is provided with as few terminals as possible consistent with the tests to be undertaken. Within a " device " test pattern diffusionformed junction isolation is used to produce islands in which transistors and resistors are formed in numbers and type equivalent to a typical " working " circuit though their interconnections differ. Considering Fig. 3, potential supplies and a voltmeter are connected to the terminals as shown and enable the dynamic characteristics of two NPN transistors 50, 52 to be checked in a " current-switch " circuit. Alternative external connections are used to measure the V BE  of each of these transistors to see how closely matched they are. Resistor values may be checked by measurement of R E  and R c . R c , though not connected to a collector, represents what would be a typical collector resistor in one of the ordinary circuits on the wafer. Resistor isolation tests may be carried out on groups R1 c  and R<SP>1</SP> E  representing an average area of collector and emitter resistors in a typical integrated circuit; resistance measurements here also show up " pipes " resulting from the presence of pin holes in the oxide masking during the isolation diffusion step. R u  is an underpass resistor, in normal circuits acting as a base resistor. A group of further underpass resistors R<SP>1</SP> u  represent the other base resistors of a typical working circuit. Isolation tests are carried out on these since their isolation in working circuits is important. A group of transistors 54-66 represent the remaining transistors in a typical circuit; in the test pattern they are connected in parallel. Using these and the substrate connection 7 (formed on one of the diffused isolating walls), life tests and isolation checks are made on the important island isolation junction which, in a normal circuit, is subjected to the highest voltage. The metal interconnections on the top surface of the body lie on a silicon oxide layer and are themselves covered with glass passivation. The "metallization" pattern (Fig. 4, not shown) uses similar components but is not concerned with their interconnection. It has a large area metallization used to check pin-holes over a large representative area; connections to the N- epitaxial layer and to the P- substrate enable distinction to be made between pin-holes to the types. The pattern also connects to diffused resistors so that sheet resistivity measurements can be made with a four-point probe technique which also allows measurements of contact resistance. The application of resistance measurements to a narrow neck of metallization gives a cheek on the extent of etching used in forming the general interconnections. One terminal on top of the glass passivation has two separate connections through the glass to the metallization pattern to give a contact resistance check for the external connections to the metallization pattern. Collection of data from the test sites gives an estimate of the likely yield of working circuits on the wafer, shows up particular manufacturing faults &c and gives a guide to static and dynamic characteristics of the device in the working circuits.