Patent GB-1351807-A (GB)
Title: Pulse generator for television for generating at least one pulse series having pulses of different duration and repetition period
IPC: H04N9/45
Filed: 1971-04-19
Abstract: 1351807 Television PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 19 April 1971 [14 March 1970 16 May 1970 10 Oct 1970] 23805/71 Heading H4F A generator of television sync., blanking and colour burst gating pulse series P, W, Fig. 1, and S cc , Fig. 10 comprises a clock A having a period t such that each (leading and trailing) pulse edge in each series is substantially coincident with a clock pulse edge, i.e. t equals, or is an integral submultiple of, the highest common factor of the different spacings between (leading and/or trailing) pulse edges in the same or different series. By choosing which divider outputs define the pulse edges it is possible, using the propagation delay of each divider stage, to approximate the required pulse length even more closely. Fig. 1 shows a generator operating according to the CCIR standard which specifies line sync. and blanking pulses of 4À7 and 12À05 ÁS with a front porch of 1À55 ÁS, equalizing pulse of 2À3 ÁS and a raster serration during the vertical sync. pulse of 4À7 ÁS, so that a clock period t of 0À8 (or 0À4, 0À2 &c.) ÁS includes pulse edge spacings of 4À8, 2À4, 12À0 and 1À6 ÁS which are within the tolerances laid down in the standard. Fig. 9 shows the output Q 1  = P of a sync. pulse circuit P over some of a series of nineteen half line periods tH/2 occurring between successive fields, for a clock having t = 0À8 ÁS so that each line period t H  = t 0 -t 80  comprises 80 clock periods. Divider chains DEF and DELM provide outputs at line and field frequency respectively. A generator X is controlled by divider M to give a 20 line period pulse x commencing at period 3, and differentiated pulse x together with outputs of dividers 2 and M cause a generator Y to produce a 7¢ line period pulse y, periods 3-17. A generator Z provides a 2¢ line pulse z, periods 8-12, from outputs of dividers L and M and generator Y, and a further generator I is controlled by dividers D-F and the pulse y to provide an output i of line frequency pulses t 3 -t 13  and additional pulses t 43 -t 53  when y is present during periods 3-17. As described, all the dividers and pulse generators are essentially J-K flip-flops, and the generator P has a plurality of J and K inputs receiving outputs from the dividers and also the pulses i, y, z, such outputs being logically combined to form J and K inputs as shown in Fig. 9. An output T = d1 from the first stage of divider D clocks the flip-flop P. As can be seen, the line sync. pulses S HP , t 9 -t 15  defined by the J 2  input (from divider D) and the clocking input T, the previous negative transition of T being ineffective due to the presence of a logical 0 at K 2 . (Some pulses are shown in dashed lines since they appear in alternate half line periods in successive fields due to interlace.) When the K 2  pulse disappears in periods 3-17, since y is the present, equalizing pulses t 9 -t 12  are produced at double line frequency, (due to the input J 3 =i), since the earlier negative transition of T is now effective. For periods 8-12, where K 3  = z = 0, K = 0 and the raster serrations are defined at t 3  by a differentiated double line frequency i pulse reset input S 2 , and the negative going J input at t 9 . In a similar manner, the flip-flop W receives i and x pulses and outputs of dividers D, E, to give the line t 7 -t 22  (t 47 -t 62  in alternate fields) and field t7 (47) period 3 to t 22  (62) period 43 blanking pulses, Fig. 8 (not shown). In this case a third stage of divider D provides the clock input d 3 , and all the output transitions are controlled thereby. Details of the flip-flop connections are shown in Fig. 2 (not shown), together with a circuit whereby a field synchronizing pulse S VES  resets the dividers L and M to within half a line via a coincidence circuit which ensures that the pulse is not transmitted if synchronism obtains. Synchronism within the half line period is ensured by connecting clock A, dividers D-F and a phase discriminator having a further line frequency input in a phase locked loop. The burst gating pulse S cc  of 2À26 ÁS (ten chrominance subcarrier periods) is developed by J-K flip-flops FF 1  and FF 2 , Fig. 10. Pulse i enables the circuitry, which is clocked by pulses d 1  from the first stage of divider D and by clock pulses a, such that the d 1  and a pulses determine the leading and trailing edges respectively of pulses S CC , at t 16  and t 19 , Fig. 11 (not shown). The duration t 16 -t 19  equals 2À4 ÁS, but, for a typical delay of 70 nS in flip-flop FF 1  and divider D, relative to the clock A, the pulse is shortened by 140 nS to 2À26 ÁS. For the PAL standard, with quarter line offset, pulses S cc  must be blanked for nine line periods around the line sync. period, such blanking period assuming a different position over a cycle of four lines due to the offset. Line frequency pulses f and i are fed to flip-flop FF 4  to produce a half line frequency output, ff 4  which therefore repeats over a cycle of four fields for 625 line interlaced scanning. This output is fed together with other logic signals to a flip-flop FF 3  to develop the required blanking pulse S c  for disabling flip-flop FF 1 , Figs. 12, 13 (not shown). A second embodiment is shown and described, which contains suitable switching of the dividers and pulse generators so that the output conforms to either of the CCIR or RTMA standards. A suitable clock period in this case is also 1/80 of a line period # 795 nS, taking into account the rise times of pulse edges specified in the RTMA standard, and a burst gating pulse generator with separate outputs S CC  and S CR  for each standard is described, Figs. 24-27 (not shown). The clock may be free running and synchronized by the appropriate input V H  to allow for the slightly different line frequencies, or it may provide an output for each standard.