Patent GB-1407320-A (GB)
Title: Method and apparatus for locating predetermined portions of a radio-frequency pulse particularly adapted for leading edge location of loran and similar navigational pulses
IPC: G01S5/10
Filed: 1973-11-05
Abstract: 1407320 Radio navigation INTERNATIONAL NAVIGATION CORP 5 Nov 1973 [8 March 1973] 51236/73 Heading H4D In a LORAN-C receiver it is required to lock on to the end of the third cycle of the carrier in the received ground wave pulse thereby obviating any interference by the much stronger first received sky wave pulse which is normally only received during the fourth or later cycles of the ground wave pulse. To carry out this requirement the LORAN-C waveband is monitored until a signal is received whereupon samples are taken at 30 microsecond intervals proceeding backwards through the received wave. This backward sampling is continued until the sampling goes beyond the beginning of either the sky waves or the ground waves and a signal is no longer received whereupon the sampling is continued at 10 microsecond intervals but in a forwards direction until the beginning of the ground wave is detected. Once the beginning of the groundwave has been detected simple cycle counting or envelope matching can enable the detection and lock on to the end of the third carrier cycle. In the receiver of Figs. 1A and 1B, the waveband of the LORAN-C transmissions is monitored by variable bandwidth RF amplifier 3 which feeds the output to a sample and hold circuit 5 where the ground wave and sky wave signals A (Fig. 2) are sampled by a group of three sampling pulses comprising a phase lock sample trigger pulse preceded (2À5 Ásec.) by cycle selection trigger pulse and followed (2À5 Ásec.) by a found signal detector sample trigger pulse which, if the period of the carrier wave is 10 Ásec. samples the maximum of the carrier wave when the phase lock sample trigger pulse is sampling a cross over in the carrier wave. The sample produced by the found signal detector sample is fed to a limited bandwidth integrator 21 and a threshold detector 23 such that when a signal of an amplitude greater than a predetermined threshold and indicative of a received pulse, detector 23 produces a "yes" pulse which via a gate 25 enabled for a period of 10 seconds by timer 27, is fed to an advance decision logic 33, whereby extra pulses are fed to a divider chain 15 normally receiving the output of variable oscillator 13, whereby the trigger pulses are produced for the next LORAN-C pulses 30 Ásec. earlier. This is repeated until the successively delayed 30 Ásec. samples yield a "no" output from the threshold detector 23. This causes an inverter 37 to enable a retard decision logic 47 whereby pulses are subtracted from those being sent to divider chain 15 and the next sample pulse fed to sample and hold circuit 5 is 10 Ásec. later than normal. This retarded sampling is repeated until threshold detector 23 again gives a "yes" output indicating that the ground wave LORAN pulse has been detected again. To ensure that the phase lock sample trigger is sampling at the cross over points ofthe cycles the samples from said phase lock sample trigger are fed to a phase lock loop circuit 11 to cause the required adjustment of the frequency of the output of oscillator 13. Once the beginning of the ground wave LORAN pulse has been acquired circuitry 55, 57, 59, 51, 53 takes over. Cycle selection enhancement circuitry 55, shown in detail in Fig. 3, differentiates the envelope A of the LORAN pulse in a low Q notch filter to produce a waveform B, which waveform B is added to the inverse C of the envelope waveform to give output waveform D having a cross over point N, which by adjustment of a potentiometer P occurs at the required end of the third cycle. The full waveform D shown in detail in Fig. 5 is sampled in sample and hold 57 by three sampling pulses which under the control of threshold detector 53 vary their positions from pulse to pulse by plus or minus 10 Ásec. until the cross over point N or N3 in Fig. 5 is detected. The receiver has now locked on to the end of the third cycle as required. Analogue to digital converters 7 and 59 enable the various phase locking steps to be performed by digital apparatus.