Patent GB-1184108-A (GB)
Title: Improvements in or relating to Communication Systems
Inventor: INOSE HIROSHI
IPC: H04J3/06
Filed: 1967-05-10
Abstract: 1,184,108. Multiplex pulse code Signalling. WESTERN ELECTRIC GO. Inc. 10 May, 1967 [11 May, 1966], No. 21742/67. Heading H4L. A communication system control centre which is to be established and maintained in synchronism with at least one other remote control centre, includes means for defining a sequence of time slots, means for generating and transmitting a synchronizing signal to the other centre or centres in one of the time slots, means for detecting a synchronizing signal received from the or each other centre. means for comparing the phase of the output signal from the or each detecting means with the phase of the locally generated synchronizing signal and means for utilizing the error signals produced by the phase comparing means to adjust the time slot defining means to establish and maintain synchronism. The invention is described in relation to a pulse code modulation system in which each pulse code is transmitted in a time slot. General description.-In a switching centre A, Fig. 2, which is linked to centres B and C, each frame is divided into twenty-four time slots (S1, S24), Fig. 4 (not shown), each of which contains eight bits (B1 to B8) and a twentyfifth time slot (S s ) containing a single bit. Each bit interval is divided into four phases (#1 to #4) and each bit is expected to occupy the phases (#2 and #3) for each bit interval. The framing signal consists of eight successive binary 1's in time slot (S1) preceded by a binary 0 in time slot (S s ). The centre includes a conventional time division switching network 20 to which is coupled all the incoming and outgoing voice-frequency lines and the incoming and outgoing trunks to other switching centres. A separate frequency synchronization circuit 30 and phase synchronization circuit 40, Fig. 3, is provided to process the signals from each of the centres B, C. Signals from B, for example, are supplied via a fixed delay 31, which adjusts the delay to be approximately an integral multiple of one frame length, to a frame detector 32 which extracts the framing signal pattern and passes a frame marker pulse to a phase comparator 34 where it is compared with a frame marker pulse derived from the locally generated framing pattern provided by local oscillator 52 through counter 53. A bitfrequency extractor 33 generates timing pulses from the incoming signal to control the timing of detector 32. The phase error signal from comparator 34 is added to the phase error signals provided by other comparators at the centre A and supplied via filter 51 to control the frequency of oscillator 52. Counter 53 provides signals corresponding to each phase, time slot and frame which are fed to each of the phasecomparators at A. Under some conditions centres could be pulled into synchronism with a large phase difference existing between them and to prevent this a phase mode selector 54 detects the presence of such an out-of-phase mode by comparing a signal representing the incoming frame timing pattern (the frame marker) received from detector 32 with the locally generated frame marker from counter 53. If a large phase difference is detected in two consecutive frames the phase of the local centre is adjusted to coincide with the phase of the incoming signal from B. To ensure the correct phasing of each bit of the incoming signals, the output of delay 31 is fed via a jitter eliminator 41 and bit shifter 44, which introduces a time delay of twice the expected phase variation between centres, to a frame detector 47 which detects the incoming framing pattern and compares the individual bits with the local framing pattern in a bit shifter control circuit 46 to modify the information stored in bit shifter memory 45. Memory 45 which includes a reversible counter controls the output of bit shifter 44 and receives control signals from jitter eliminator 41 and jitter control 43. If phase jitter larger than a bit width is detected, circuits 41 and 43 transmit signals to bit shifter memory 45 to effect the desired compensation. If the phase difference is less than a bit width, a tapped delay line in jitter eliminator 41 is controlled through a series of logic gates by jitter memory 42. The jitter memory 42 records which gates are operative and compares this with the next delay line output, any phase lag or lead causing the appropriate gates to be operated.