Patent GB-1015651-A (GB)
IPC: G06F3/08
Abstract: 1,015,651. Electric digital computers. SPERRY RAND CORPORATION. June 12, 1963 [June 18, 1962], No. 23326/63. Heading G4A. A serial digital data processor in which operations are under the control of a plugboard has a punched card input and is characterized in that operands may be selected from the processor memory in variable lengths as determined from the plugboard. General arrangement.-The apparatus described, Fig. 15, is a plugboard-controlled processor having a punched-card input and punched or printed output. Arithetic operations are performed in binary coded decimal excess-3 code (called XS3). The input is from " 160 column " cards which are actually 80 column cards in which the upper six rows and lower six rows constitute distinct fields, numerical data being punched in XS3 code. Alternatively, the input can be from ordinary 80 column or from 90 column cards. The computer memory can store data in either XS3 code or 90 column card code. Variable length words are employed in processing operations. The basic computer gates and flip-flops employ transistors (Figs. 1-8, not shown). Memory locations.-The processor memory, Fig. 9a, is a 31 x 31 x 6 matrix of cores having 961 locations and capable of storing 961 6-bit characters. For operation with 160-column cards, locations R1C1-R6C5 are assigned to the card reader, locations R6C6-R10C13 to the printer and locations R10C14-R15C18 to the punch, the remaining locations being working storage. When operating with 80 column or 90 column cards, the memory locations are assigned differently (Figs. 9b, 9c, not shown). Memory address control, Fig. 11. To control variable word length read-out from the memory, it is necessary to plug on the plugboard both the starting and ending address of a word to be read out. In a read-out operation, the starting address is placed in a memory address register MAR, Fig. 11, the ending address being placed in a field counter register. The address in the memory address register MAR then permisses the desired memory location and is compared with the ending address. Assuming there is no coincidence, the starting address is increased or decreased by unity (according as an " ascending " or " descending " operation is being carried out) and the next memory location address. The process continues until the ending address is reached. Plugboard, Figs. 14a-14d. The processor plugboard has the following functional sections: (1) Step output. There are 62 processing steps available, a standard machine employing only 31 of these. For each step there is a column of five hubs, a hub PRO being wired to control arithmetic or logical process to be performed, a pair of hubs OP1 defining a first operand, and a pair of hubs OP2 defining a second operand. (2) Start. A start hub enables processing to begin with any desired step. (3) Step sequence change. This plugboard section comprises one hub for each processing step and enables the normal sequential stepping to be changed. (4) Distributer. There are 160 distributers, each comprising a column of nine hubs, a signal received at the entrance hub being available at four pairs of exit hubs to provide four exits for a step output signal to four operand address hubs. (5) Operand 1 address. This section comprises four rows of 31 hubs to define the storage location of the first operand of a step, a hub row " R " defining a memory row and a hub row " C " defining a memory column. (6) Operand 2 address. This section is similar to the operand 1 address section. (7) Collector. Each collector consists of a column of either seven or ten hubs, a ten hub column providing a pair of exit hubs and four pairs of entrance hubs, thereby enabling a single destination to be signalled by a plurality of sources. (8) Descending transfer. This section comprises eight hubs for controlling, commencing with the most significant digit, an operation such as transfer, zero suppress, zero delete, insert, superimpose, described fully in the Specification. (9) Ascending transfer. This section controls similar operations commencing with the least significant digit. (10) Arith. This section contains three hubs for ADD, SUBTRACT and ADD WITHOUT SIGN operations respectively. (11) No PRO. A " no process " hub is wired if no arithmetic or logical process is required on a particular step. (12) No RC. A " no recomplement " hub suspends automatic recomplementation of a complementary result obtained during an arithmetic step. (13) Form control. This section consists of five hubs arranged to initiate certain paper movements in the output printer. (14) Read-print. This section comprises three hubs; a hub RD for altering the reader section, and hubs for altering the printer section, the execution of a read and/or print operation occurring only when a hub marked EX is signalled. (15) Punch. There are three PUNCH hubs, a HOLD hub H, a CLEAR hub C, and a TEST hub T. The hub H initiating punching and holding the information in punch storage, the hub C initiating punching and clearing the information from punch storage and the hub T preventing the initiation of a new step until punching is completed. (16) Card. This section comprises hubs for controlling 80 column card or 90 column card operation. (17) Comparator. This section contains hubs for a maximum of ten compare circuits, each circuit having a row of eight hubs. Three types of comparison are possible: " numeric " producing three results according as Operand 1>, = , < Operand 2; " arithmetic," determining whether the result of an arithmetic process is positive, negative or zero; and " alphanumeric " determining whether Operand 1 is equal to Operand 2 or not. (18) Address combine. There are 79 " address combines " each consisting of a column of 11 hubs including four pairs of IN hubs, a common (C) hub, and a pair of OUT hubs. An " address combine" column is effective to emit a pulse at its OUT hubs whenever two or more pulses are received at the IN hubs. (19) Address emitter. This section comprises 31 hubs representing row (R) co-ordinates of storage and 31 hubs representing column (C) co-ordinates of storage and when during an operation, a memory location is addressed by an Operand 2, the corresponding address emitter hubs emit signals. These hubs are wired to cause the insertion of characters, to control punching &c. (20) Bit present emit; bit absent emit. This section comprises two rows of six hubs each, representing the six cores of any storage location and can be employed to determine the contents of that location. These hubs are wired via " address combine " hubs to control card punching &c. (21) Manual hold. This section comprises four sets of four hubs corresponding to four control switches on the computer control panel. (22) ISD inhibit selector delay. This hub eliminates the delay that normally occurs at an ON or OFF hub of a programme select (see below). (23) Cycle Clear (CC). This hub emits at the start of the execution of a read cycle. (24) Cycle hold (CH). This hub emits except when hub CC emits. (25) Hold (H). This hub emits as long as power is supplied to the computer. (26) Programme select control. This section comprises 20 sets of hubs, each set consisting of an ON and an OFF hub. A signal - wired to the ON hub of a set creates a continuous signal at the related programme select power hub. (27) Programme select power. These hubs emit when the associated programme select control ON hub is signalled. (28) Selector pick-up. Each " selector " (see below) has a hub in this section which when signalled, causes the associated selector to assume the select position. (29) Selectors. There are 60 selectors, each consisting of four columns of three hubs each, each column being referred to as a " pole." The upper hub of each pole is the " select " (S) hub, the centre hub is the " common " (C) hub and the lower hub is the " non-select " (NS) hub. The function of the selectors is to allow one machine function if the selector is picked up and an alternative machine function if the selector is not picked up. (30) Printer overcapacity (PRO'C). This hub emits during the printing of a line if an overcapacity is sensed. (31) End RD, PU, PR. A signal to any one of these hubs serves to halt the reading, punching or printing operation with which it is associated. (32) Zero suppress, start and end. These hubs are wired to define the start and end of a zero suppress field. (33) Space generate, start and end. These two hubs are used to start and end the entry of spaces in a series of storage locations, and to end such an area. (34) Test location. This section comprises two hubs, each associated with a two-position switch and enables a storage location accessed as part of Operand 2 to be tested for a required character. (35) Test zero, test sentinel. These hubs are employed in conjunction with the test location hubs. (36) Test overflow. This section comprises three pairs of hubs marked YES, IN and NO. If any arithmetic operation causes a result having more digits than there are storage locations in Operand 2, an interconnection between hubs IN and YES is established. (37) Character generator. These hubs generate the 160/80 or 90 column characters with which each is labelled and are effective to insert or superimpose that character. (38) Bit generator. This comprises six hubs representing the six positions of the 160/80 or 90 column card code and can be effective during an insert or superimpose transfer operation. (39) Halt. This stops the processor. (40) Indicator. These hubs are associated with display lights on a display panel and provide a means for indicating the reason for halting. Information flow, Fig. 15. Assuming that information on a 160 column card is being read, this information is entered column-by-column via a memory data register MDR to the reader buffer storage section of the memory. During this transfer, other operations can be carried on in the comput