Patent CH-539890-A (CH)
Inventor: EMILE FERDINAND SALADE ROBERT
IPC: H04Q3/545
Filed: 1968-01-24
Abstract: 1,181,184. Automatic exchange systems. INTERNATIONAL STANDARD ELECTRIC CORP. 11 Jan., 1968 [24 Jan., 1967], No. 1737/68. Heading H4K. [Also in Division G4] A data processing system includes two programme controlled processing units, and a control system associated to both processing units and storing " test " and " restoring " programmes in a memory outside the processing units, the " test " and " restoring " programmes being used after detection of a faulty processing unit to test the faulty processing unit and restore a successfully tested processing unit to operative condition. The processing units control a telecommunication switching network on a load-sharing basis and if one processing unit develops a fault, the other takes over its share of the work. Each processing unit can send information to the other over a respective interprocessor unidirectional channel. The control system includes a set of five bistate devices for each processing unit to control and indicate its state, the five bistates signifying " on-line " (i.e. operative), " copying," " reading," " stop " and " test " respectively. Each processing unit may set any bistate (i.e. of all ten) and the states of all bistates are signalled to both processing units over test leads. The states of each set of five bistates are also signalled to the processing unit associated with the other set, over interrupt leads. Setting of any bistate, in a given set of five, resets the other bistates in the same set, except that setting of the " test " bistate does not reset the " on-line " bistate. The control system also includes a tape memory holding the " test " and " restoring " programmes, and a supervision circuit. Loading and execution of " test " and " restoring " programmes.-If the first processing unit, say, detects that the second is faulty, it sets the " stop " bistate of the second. This stops the second, adjusts the beginning of the tape to the reading position, and via the interrupt lead causes the first processing unit to set the " reading " bistate of the second. This is detected over the interrupt lead by the first processing unit to cause it to take over the work load of the second, and the second responds to the " reading " bistate to read the first " test " sub-programme from the tape into its own memory. An order read from the tape after this sub-programme sets the " test " bistate of the second processing unit so that the second executes the first " test " sub-programme. If this is done successfully the second processing unit sets its " reading " bistate to read the second " test " sub-programme from the tape which is then executed in the same way, and so on. Unsuccessful execution of a " test " subprogramme causes the second processing unit to set its " stop " bistate which has the same effect as before, causing (indirectly) the sequence of " test " sub-programmes to be gone through again, starting with the first. An alarm signal (to maintenance personnel) is given if repetitive execution of " test " sub-programmes continues for too long. After the successful execution of the last " test " sub-programme, the " restoring " programme is read from the tape into the memory of the second processing unit and executed, causing the state of the " on-line " bistate of the first processing unit to be sampled. If this indicates the first processing unit is " on-line," the second sets its own " copying " bistate and information from the memory of the first is transferred over the interprocessor channel into the memory of the second which then sets its own " on-line " bistate. If, on the other hand, the first processing unit was not " on-line," the second sets its own " reading " bistate and receives an operational programme from the tape, after which it sets its " on-line " bistate. Supervision circuit.-When on, a routine test device alternately closes, every 3 minutes, two test lines of the switching network. Closing a test line causes one of the processing units to establish a connection between this line and a junctor which then applies dial tone to the line. If, due to a fault, this dial tone is absent throughout a time period measured by a counter, the routine test device is switched off and then, when neither processing unit is " on-line," the " test " and " restoring " programmes are executed in the two processing units alternately (in each case for a time period measured by a counter), starting with the processing unit which was last in the non-operative (i.e. not " on-line ") condition, until one of the processing units has been restored to " on-line " condition, when the routine test device is switched on again. Manual means are provided to prevent this alternate testing of the two processing units continuing too long. On-line tests.-When the " on-line " and " test " bistates of a processing unit are both set, it performs the following tests: (a) checks whether a 14 ms. clock signal is being received from the other processing unit over the interprocessor channel, (b) sets the " test " bistate of the other processing unit directly and samples its state on the interrupt lead, (c) as (b) except that the setting is done via the interprocessor channel and the other processing unit, (d) sends information over the interprocessor channel to the other processing unit which processes it and sends an answer signal back. Bistates set in the processing unit in accordance with the results of the tests control gates in combination to indicate which portion of the system is faulty, assuming only one is. The processing unit then takes the appropriate action, e.g. rendering the other processing unit non-operative. Reference is made to Specification 1,181,182 for further details of some aspects.