Patent GB-886421-A (GB)
Title: Improvements in or relating to data processing apparatus
IPC: G06F15/00
Filed: 1958-01-24
Abstract: 886,421. Digital electric calculating and sorting apparatus. MINNEAPOLIS-HONEYWELL REGULATOR CO. Jan. 24, 1958 [Jan. 25, 1957], No. 2437/58. Class 106 (1). General.-A data processing machine has an internal store to or from which data may be transferred under the control of a single programme control order, and a portion of the data may be uniquely selected from the data being transferred for combination with the programme control order to direct a further operation of the machine in accordance with the modified control order. This feature of the machine has particular application to sorting- operations. A further feature of the machine is that a single control order may direct the transfer of data from an external source, e.g. a magnetic tape store, to a number of separately accessible storage locations in the internal store through an input buffer store, and simultaneously direct the transfer of data from these storage locations to an external destination through an output buffer store. In the embodiment described, data derived from punched cards and recorded on magnetic tape in one of files 13-19A, Fig. 1, is read at a relatively slow speed on 31 channels into the input buffer store 21 which discharges its contents into the internal store over a single channel at a relatively high speed, and the output buffer 23 simultaneously receives high-speed data from the internal store over a single channel and delivers it on 31 low-speed channels into one of the tape files 13-19A. Input buffer, Fig. 7 comprises an argument section and a data section which may be selectively connected to one of the magnetic tape files, each section being divided into an upper and a lower portion which are each capable of storing 31 complete words, corresponding to one block of 62 words recorded on 31 channels of a tape. A block of data is read serially into the 31 shift register circuits of the buffer section selected, and is later read out in parallel, words being read out alternately from the upper and lower portions into a high-speed register AOWL or DOWL, from which the data is again converted to serial form, provision being made for reversing the bit order if a reverse tape-read was used. The tape " argument " channel carries key information which identifies other information recorded in that particular block, and the argument section of the input buffer may receive data from a plurality of magnetic tapes, one channel at a time, or a complete block from a single tape. The buffer argument section also includes circuitry in the first ten register circuits to enable a selective read-out of any of the first twenty words stored in that section to be made. The number of words read out from the buffer store may be controlled by the programmer. Internal store. Fig. 9.-The serial input derived from high-speed register AOWL or DOWL is converted to parallel form at 156 and stored in local register 157 from which it may be transferred through Z driver 158 to an address in high-speed magnetic core memory 155 selected by X, Y drivers 161, 162. The X driver has four " tens " and ten " units " input lines, and the Y driver has five " tens " and ten " units " input lines from the memory control circuits 159, giving a total of 2,000 addresses in store 155. Word structure and operation checking, Fig. 2. Each word has 52 bit positions of which positions 5-52 are considered to be in groups of four which are assigned transfer weights 1, 2, 4, 8. Bits 1-4 comprise a weight count section which carries a number indicative of the number of " ones " in positions 5-52 in accordance with the transfer weights of those positions. The weight count provides a check to ensure that no errors are made in transferring a word between two locations or performing an operation on the word. The weight count is removed from the word which then undergoes the desired process and is then supplied to a transfer weight adder which generates a new weight count for the processed word, this weight count being compared with the original weight count, modified as necessary according to the type of process involved, and if the two weight counts are identical a check pulse is produced to allow the machine to proceed. Fig. 2 illustrates numeric and alphabetic data words and also order or instruction words used in the machine. The order words each have an operaation code section in which the actual order is represented. Thus order word 1 may mean " take the word stored at address A and the word stored at address B, perform a specified arithmetic operation on them and store the result at address C." Order word 1 may also be used to perform various transfer and extracting functions. Order word 2 is used to transfer B2 words from the input or output buffer, as determined by bits Ba, Bd and the existing machine connections, and store them in B2 sequential locations starting with address A, the next order being obtained by a subsequence call to address C. Order word 3 means " transfer C2 consecutive words starting at address A and store them at consecutive locations starting at address B." Order word 4 is used for shifting a word left or right including or excluding the sign bit by four bits Bh times and also performing or not performing an additional two-bit shift as determined by Bt, the word being selected from address A and the modified word stored at address C. In addition to these words, sentinel words whose bit positions 51, 52 are zeros are employed, for performing special functions in the machine, such as denoting the end of a certain type of data or acting as filler words for the output buffer when a tape write signal is given before the buffer is full. A sentinel word when sensed is stored in a special register to which a sub-sequence call is made at the end of a machine major cycle, the sentinel word then directing a subsequence operation before the next major cycle commences. If no sentinel word is sensed, a " pass " order is stored in the special register. Control console and programming.-Initial programming is accomplished by way of a keyboard and an address selection keyboard, the programme being stored in sequential addresses in the internal store. The console also includes a typewriter from which a printout of data may be obtained at a specified time in the machine operation. The address of the first order to be used is inserted in a sequence register SR, Fig. 18, and this sequence number is changed at the end of each major machine cycle which includes a first minor cycle so that the machine orders are selected in succession. A sub-sequence may be initiated by the setting of certain special functional units, e.g. by the sensing of a sentinel word, while an order is being processed, in which case the contents of SR remain unchanged until the end of the major cycle proper. Minor cycle 1 is the same for all types of order words : sequence register SR sets an address selection circuit which then transfers the order word from the high-speed memory or a special address into control register CR. Special addresses denote circulating registers CR. AR2, AR4, LOP, AR7, the output buffer (one word) and a label register LR (not shown) which stores the source of a word currently being processed. The contents of SR are also supplied to an accumulator ACC in which a one is added to the address of the order word and to the transfer weight. The contents of SR are also supplied to LR. Weight count checks are made throughout minor cycle 1 (and all succeeding cycles) for each data transfer, and if no error is indicated the machine proceeds to cycle 2 (or next cycle). Arithmetic operations: Addition.-Fig. 18 shows the arithmetic unit. In cycle 2 CR supplies the addition order to an operation code register, and sets the address selector to transfer the numerical word at address A to AR1  in cycle 3, and the next order address in ACC is transferred to SR. In cycle 3 the sign of the number transferred from A to AR1 is noted and stored. In cycle 4 CR sets the address selector to address B whereupon the number stored there is transferred to AR2 and its sign is also noted and stored. The two numbers are inserted into ACC, Fig. 26, in cycle 5, the number from address B being complemented before insertion if the signs of the number were found to be different. CR also sets the address selector to address C. In ACC a 6 is added to each decimal digit of the augend, no carry between digits occurring, and the modified augend is added serially to the addend in the main adder, carry digits being supplied as necessary from the main adder carry circuit. When there is no carry between a pair of decimal digits, the negation output of the main adder carry circuit causes a binary coded ten to be added without carry to the appropriate output digit of the main adder. The result of the addition is recirculated. In cycle 6 various control and checking functions are performed, and in cycle 7 the result is moved out of ACC and is checked before being supplied to address C in cycle 8. The machine will then step to cycle 1 or cycle 2 of the next order. Subtraction.-This operation is the same as addition except that in minor cycle 5, either A or B is complemented on being fed into ACC according to their signs. Multiplication.-In this operation the number at A is multiplied by the number at B and the high order product is transferred to C whilst the low order product is stored in LOP. Cycle 2 is similar to the addition process. The multiplicand is transferred from address A into ACC in cycle 3 and in cycle 4 the multiplier is transferred from B into LOP. In cycle 5, one, two, four and seven times the multiplicand are generated as follows. The multiplicand is applied to AR1 and added to itself in ACC; twice the multiplicand thus generated is applied to AR2 and added to itself in ACC; four times the multiplicand thus generated is applied to AR4, and twice the multiplicand an