Patent GB-1332178-A (GB)
Title: System for the display of synthesized graphic symbols
IPC: G09G1/08
Filed: 1970-09-17
Abstract: 1332178 Cathode-ray tube displays THOMSON-CSF VISUALISATION ET TRAITEMENT DES INFORMATIONS 17 Sept 1970 [19 Sept 1969 (2)] 44438/70 Heading H4T [Also in Division G4] A system for presenting visual symbols on a cathode ray tube comprises a memory 4 for storing digitized instructions and a control unit 5 for distributing such instructions between analogue function-generating means 6 and function-modifying means 7 which supply scanning voltages to the CTR. A computer 3, Fig. 2, generates code words of the three-part form shown in Fig. 3, wherein E ijk  is an identification part denoting the ith element of the jth group of the kth figure, N is a characterization part denoting a geometrical law, and LT is a modification part comprising commands determining size (L) and transformations (T). Instructions from memory 4 relating to groups and figures lack the portions N and L of the code since these are determined by the instructions relating to elements. Thus, memory 4 may contain in its register 10 a number of code words F k T fk  indicating one or more transforms to which each figure of the display is to be subjected; a number of code words G jk T gjk  indicating transforms to which groups of any figure F k  are to be subjected; and a number of words of the Fig. 3 type relating to all the elements E i  of each group G j  of any figures F k . The memory 4 may e.g. just read out (when instructed by computer 3) the instructions F 1 T f1  relating to the first figure and these are distributed by a gating network to a set of "figure" registers T 1f  ... T n  f , the address of the figure (in this instance "1") being stored in address register AF. Register AF reports this address to register 10 while gating network 13 upon receiving a switching command from memory 4 energizes a lead Sa to cause a shift in register 10 which then changes from figure to group processing and issues instructions G 11  T g11  relating to the first group of the first figure. When buffer "group" registers T 1 G .. T n G are filled, the address of the group is entered in register AG and the register 10 shifted from group to element processing. Element instructions are gated by gating circuit 13 to "element" registers T 1 E ... T n E and also to registers N, L and AE. When these are full of information relating to the first element, this information is transferred to buffer registers (T 1 E)v ... (T n E) v , (N) v , (L)v and (AE)v to make room for information relating to the second element. The register (AE)v reports to the computer 3 the identity of the element being traced. Registers (N)v and (L)v control analogue function generator 6 and registers (T 1 E)v ... (T n E)v control transform generators 7E, signals from these causing the CTR to scan all the elements of the first group of the first figure. After synthesis of this group, the network 13 responds to another switch signal and instructs register 10 to shift to group selection, i.e. to the second group of the first figure, and so forth. The transform signals relating to groups and figures are fed to transform generators 7G, 7F in cascade with the element transform generators 7E. The address of any element is available to the computer 3 from registers AF, AG and (AE)v and an operator may identify a chosen element to the computer and modify its shape by feeding a new "N" value to the computer. The analogue function generator 6 may comprise a combination of known D/A converters and analogue function generators. Alternatively, as described (Fig. 4), the generator 6 consists of analogue means selectable by digital switching signals to generate any linear or second-degree function. It comprises identical X and Y signal channels which are fed by voltages v x , v y , being the analogue equivalents of the digital values transmitted from "size" register (L)v. The X channel includes an operational amplifier A x  and two integrating amplifiers I 1x  and I 2x , the output of the amplifier I 1x  being connected by a multiplier M 1  and an inverter 27 to the input of the corresponding amplifier I 1y  of the Y channel. Switches 21, 22 open and close periodically in response to clock pulses to allow for establishment of the selected starting conditions determined by voltages v x , v y  at the beginning of each operational time slot. The rest of the switches are operated by digital "shape" signals from register (N)v, as exemplified below. Thus, if switches 25, 26 are changed over to cut out the first integrating stages I 1x , I 1y , the respective outputs X c  and Y c  of integrators I 2x  and I 2y  will be linear Functions of time. If switch 25 is changed over and switch 26 is left as shown, the voltage X c  will be linear as before, and the voltage Y c  will follow a square law as determined by the cascading of the two integrators I 1y  and I 2y . The result is a parabolic trace. If the cross-connections are established by closure of switches 23, 24 and the other switches left as shown, a hyperbolic segment will be generated. For, assuming v ox  (input of integrator I 1x ) is zero at t = 0, and inputs v ox , v ov  satisfy v ox  = A sinh zt; v oz  = A cosh zt, then amplifier I 1x  has an output v ix  = A/z a cosh zt and amplifier I 1v  an output v 1y  = A/z α sinh zt where a is the gain of the amplifiers. If the feedback factor of the amplifiers is #, and the multiplication factors in the cross-connections K 1  and K 2 , the voltages at the inputs of the amplifiers may be expressed in two simultaneous equation which when solved for z yield: so that the system is in equilibrium if K 1  = K 2  = K and z = Kα/(1-α#). At t = 0 (when switches 21, 22 are closed) v ox  must be zero if the sinh function is to develop in the x branch. If the signs of the cross-feed voltages are reversed, a segment of an ellipse will be generated. In order to make the peripheral tracing speed independent of radius, the amplitude A may be made inversely proportional to K, so that the input voltages are increased with decreasing multiplication factors. The final radius still depends on K since this is again introduced by the integrators I 2x , I 2y . The various multipliers used in the junction generator (Fig. 4) and elsewhere in the circuit are of the hybrid type, being, in effect, D/A converters of the kind using a resistance ladder network with shunt branches selectively connected, e.g. by FET switches, to a common input. An analogue multiplicand is applied to this input and the switches selected by binary logic circuits in accordance with a digital command signal representing the multiplier (Fig. 5, not shown). A feature of the multiplying circuit is the equality of all the shunt resistances (R), and of all the series resistances (R/2) of the ladder network. The transform generators 7E, 7F, 7G, for translation and rotation, each comprise a conventional arrangement of multipliers and adders for performing the operation defined by x<SP>1</SP> = x cos # - y sin #; y<SP>1</SP> = x sin 0 + y cos 0, the multipliers being of the hybrid kind, described above, to which digitally encoded signals sin 0, cos 0 are fed. Translation is effected by a third input to the adder circuits (Fig. 6, not shown). In order to explore in greater detail part of the trace 100, Fig. 7, on the CRT screen, a small area may be selected by depressing keys on keyboard 9 (Fig. 1) corresponding to voltages X 1 , X 2 , Y 1 , Y 2 . These (digital) voltages are fed to D/A converters 101, 102, 103, 104, Fig. 8, and the analogue values compared with the sweep voltages x c , y c , which determine the trace, in comparators 201, 202, 203, 204. Each comparator may signal up to two coincidences (corresponding e.g. to points P 1 , P 2 , P 3 , P 4 ) and these coincidence signals are used to control shift registers 301, 302, 303, 304 which yield up to eight marker pulse signals S. The registers are reset after each time slot. The computer 3, upon receipt of the marker pulses, ascertains from address registers (AE) v , AG, AF, the identity of the elements touching the chosen frame and instructs the memory 4 to suppress parts of the trace outside the frame. The chosen part of the trace may then be magnified &c. as desired. It is stated that, instead of a keyboard, the chosen area may be marked out with the aid of the photoelectric stylus described in Specification 1,202,270.