Patent GB-1128407-A (GB)
Title: Improvements in gating the input to an integrator
IPC: H03M1/00
Filed: 1966-04-15
Abstract: 1,128,407. Integrators. SOC. NATIONALE DES PETROLES D'AQUITAINE. 15 April. 1966 [15 April, 1965 (2)], No. 16727/66. Heading G4G. In apparatus for initiating and terminating integration of an electrical signal between predetermined signal levels, the level is measured over periodic fixed time intervals short compared with signal duration and two successive measurement values are compared; the difference therebetween controlling a gate between the signal input and the integrator circuit. In Fig. 1 a signal voltage source 1 energizes a voltage to frequency converter 2 whose pulse output excites gates 3, 4 and 11. Gates 3, 4 are also triggered by circuit 8 responsive to clock 9 also controlling trigger circuit 10 excited by an overflow counter 7 responsive to counters 5, 6 fed from gates 3, 4; the trigger 10 controlling gate 11 connecting the output of converter 2 to an integrating circuit (not shown). In operation, the pulses from converter 2 are gated at 3, 4, according to trigger 8, to counters 5, 6 for successive equal time intervals, and the algebraic difference between the counts operates counter 7 having a fixed capacity. When this is exceeded, an overflow pulse changes over trigger 10 to open gate 11 and allow integration of the signal. Clock 9 zeroizes the counters and restores trigger 10 to rest before arrival of each overflow count, so that on cessation of the input signal no overflow is produced and trigger 10 is inoperative, so that gate 11 is closed between the signal and the integrator. Fig. 2 shows an analogue system wherein a pulsed signal from converter 2 and signal source 1 is applied to gates 3, 4, 12 of which 3, 4 are controlled by trigger circuit 14 excited from clock 13, so that the pulsed signal is applied alternately to R.C. integrating circuits 5, 6 and 7, 8 for equal time intervals, whose outputs are applied to difference amplifier 9 energizing positive and negative threshold trigger circuits 10, 11 controlling gate circuit 12 between the output of converter 2 and the integrator (not shown), so that a sufficient increase of the input signal over successive time intervals operates trigger 10 to open gate 12 and permit integration, while on cessation of the input signal, negative trigger 11 operates and gate 12 is closed to arrest integration. In a modification (Fig. 3) the output of converter 22 is applied to first and second counters 23, 25 interconnected by a memory 24; the counter 25 exciting a trigger circuit 27 and a decoder 26. The outputs of the latter operate a trigger circuit 28 whch actuates a gate 29 together with the output a further gate 32 responsive to the complementary output of trigger 27 and trigger 31. The input pulses are counted by 23, 25 for a given time interval, after which the complementary number of pulses transferred to memory 24 is transferred to counter 25; the operations being synchronized by a clock circuit (not shown). Over the succeeding time interval, the pulses are again counted in 23, 25 and carry the latter to maximum capacity if the number of pulses is the same as that in the preceding interval. If the number is in deficit, there is no overflow of 25, but if in excess the latter overflows and changes over trigger 27 to open gate 28 and connect the pulses from 22. Decoder 26 pulses through this gate to change over bistable element 29 and open gate 30 to the integrator (not shown). Counters 23, 25 are zeroized at the ends of predetermined periods. In a further modification (Fig. 4, not shown) the voltage source delivers signal to a voltage frequency converter and to a R.C. differentiating circuit whose output operates positive and negative threshold triggers. A sufficient increase of voltage operates the +ve trigger to open a gate permitting converter pulses to pass to an integrator, while a sufficient decrease closes the gate. Thereafter a sufficient further decrease of voltage operates the -ve trigger to open a fuuther gate passing converter pulses to the integrator, and on cessation of signal both gates-are closed.