Patent GB-1513054-A (GB)
Title: Circuit for cancelling echo signals
IPC: H04B3/23
Filed: 1975-05-13
Abstract: 1513054 Echo suppressors COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 13 May 1975 [24 May 1974] 20066/76 Heading H4R In an echo suppressor of the echo-cancelling type in which a synthetic echo y(t) is generated in a transversal filter from a signal x(t) in one path and subtracted from the signal yt in the other path, with the multipliers of the transversal filter adjusted in accordance with correlation between a residual echo signal and the signal in the one path, and in which the transversal filter and correlator are implemented digitally, the transversal filter operates on N samples of the signal, each coded into n digits, with N multiplier coefficients, each of which is stored as n + m digits of which only the first n digits are used in the transversal filter multiplier wih the full n + m digits being used in the adaptive control loop, which receives the residual echo signal after multiplication by a factor α, which is close to zero, and the n + m digits being required to represent the residual echo after multiplication by this factor. As described the signal x(t) in one path is sampled and digitized in a to d converter 21 and N successive samples stored in register 20 for multiplication by corresponding filter coefficients C 1  to C N  stored in register 24, and accumulation in adder 26, to provide a synthesized echo sample y(t) which is subtracted from the signal sample z(t) in the other path, which contains an actual echo y(t). The result of the subtraction, during periods of time when only an echo signal y(t) is present on line 13, is an echo error signal e(t). The sign of the error signal is multiplied by the sign of the input signal xt in an exclusive-OR gate 36, while the value of the error, e(t) is multiplied by a constant α=<SP>1</SP>/ 256  at 37 and combined with the appropriate multiplier coefficient from register 24 in a manner decided by the value of the output of gate 36, to increment the multiplier coefficient in the appropriate direction. Fig. 3 shows how the multiplier 25 of the transversal filter operates with an 8 digit input for the signal input x(t) and multiplier coefficients Ci and provides a 16 digit output to the accumulator 26 which, while retaining the 16 digits for accumulation, provides an 8 digit output y(t) for the synthesised echo. Subtractor 27 operates on the 8 track synthesised echo and 8 digit real echo to derive an 8 digit echo error e(t) which is applied via an operation circuit 40 to be combined with the multiplier coefficient in circuit 38. The echo signal #(t) is shifted 8 digit positions to effect a multiplication by a constant α = <SP>1</SP>/ 256  at the input of circuit 38, which operates with multiplier coefficients stored in register 24 as 16 digit numbers, only the 8 most significant digits being supplied to multiplier 25. The operation circuit 40 is fed with signals M and # derived in circuit 39 (Fig. 2) from the signals on the two paths and either blocks the signal e(t) if there is no signal in both paths, allows the signal e(t) to pass normally if there is a signal x(t) but only a low level signal z(t) i.e. probably only an echo of the signal x(t), while if both paths contain signals at high levels, indicating double talking, the value of e(t) is modified to a very low level so that convergence of the multiplier coefficients proceeds but only at a very low rate.