Patent GB-1360930-A (GB)
Title: Memory and addressing system therefor
IPC: G06F12/04
Filed: 1972-06-14
Abstract: 1360930 Addressing systems BURROUGHS CORP 14 June 1972 [28 June 1971] 27840/72 Heading G4C  Data is read out of or read into a random access memory 10 (Fig. 1) under the control of two signals, one of which indicates the boundary between two storage cells in the memory and the second of which indicates on which side of the boundary access is required. As described when a unit (not shown) requires read-out of data from the memory 10, the memory consisting of four modules 10-0, 10-1, 10-2, 10-3, in each of which data is arranged in a plurality of 8 bit locations C 0 -C 7 , ... C 32 -C 39  ... comprising non-destructive readout bi stable elements, each memory module is accessed by its associated control circuit MAC so that 32 bits are entered into read register 40R. The stored data is fed via read rotator and mask network 41, which serves to isolate a desired subfield of the 32 bits and to rotate it to the desired position for entry into register 44 from which it is fed to the requesting unit. Similarly new data is entered from the data register 44 via a write rotator 42 and write register 40 into desired units of the memory 10. The boundary address BBA is stored in a 24 bit address register 30, two bits representing a module, 2<SP>19</SP> bits representing the 8 bit location and 2<SP>3</SP> bits representing the boundary within the location. A transfer vector is stored in a register 35, five bits TW being indicative of the number of bits to be transferred (up to a maximum of 24 bits) and a sixth bit TS indicating which side the boundary is to be accessed. The bit TS together with bits MSM, MSL, representing the module in which the boundary lies, are fed to a distribution gating network 15, together with the 19 bits KLA representing the location in the module and a modified address MKLA derived by incrementing or decrementing respectively the location KLA if TS is "1" or "0" respectively. The network 15 comprises gates such that, for addressing in the direction of higher numbered storage units from a boundary in storage module 10-i, the unamended location address KLA is applied to stores 10-i ... 10-3 and the modified location address KLA + 1 is applied to stores 10-o ... 10-i-1 and, for addressing in the direction of lower numbered stores the unamended location address KLA is applied to stores 10-o ... 10-i and the modified location address KLA-1 is applied to stores 10-i + 1 ... 10-3. This ensures that if, for example, the boundary specified is between storage units C32 and C33, to read out locations C33 to C56, locations 2 of all the modules are addressed but if locations C9-C32 are to be read out location 1 of modules 10-1, 10-2, 10-3 and location 2 of module 10-0 are read out. Network 50 controls the rotation of the read out data (or the data to be read in) so that the least significant bit is stored in the least significant position of register 44. The network receives (1) the signal TS which indicates whether the boundary location represents the least significant bit or the most significant bit, (2) 5 bits MBS of the address signal representing the module and the boundary position within the location and (3) the bits TW representing the length of the data. It is arranged to add the bits TW to the bits MBS when the signal TS is "0" and to pass the bits MBS unchanged when the signal TS is "1", The output for network 50, which represents the amount the data should be rotated, either to the left in read-in or to the right in write operations, is fed to read and write rotation networks 41, 42. The read network 41 (Fig. 5, not shown) may comprise shift registers but preferably includes 24 gating matrices, the output from each of which is connected to one of the 24 inputs of register 44, each matrix having inputs from all the stages of register 40R. The arrangement is such that in dependence on the amount of rotation required, determined by network 50, inputs of the matrices are selectively connected to the stages of register 44, the number of matrices enabled depending on the length of the data, determined by the bits TW. The write network 42 (Fig. 6, not shown) comprises 32 similar gating matrices, each receiving rotation control signals from the network 50 and inputs from the outputs of register 44 and a write mask generator 45W (in dependence on the length of the data to be read). This results in "0" signals from generator 45W being entered in the spare units in register 40W to which the matrix outputs are connected. Write merger network 51 ensures that, during a write in phase, data is read back in unamended from register 40R to all of the 32 read out storage units except those for which new data is entered into register 44.