Patent ES-353793-A1 (ES)
Title: Method of manufacturing a semiconductor device and device manufactured by said method
IPC: H01L21/00
Filed: 1968-05-11
Abstract: The invention relates to a method of making a lamina consisting of a network of silicon oxide containing islands of silicon which extend the full thickness of the lamina and contain circuit elements. The oxide network is formed by selectively oxidizing parts of a silicon layer which forms or previously formed the surface of a thicker semi-conductor body. In one method areas of one face of a silicon wafer are first oxidized to the depth of the lamina and material subsequently removed from the opposite face to the level of the oxide to form the lamina. Alternatively it is formed by first providing the wafer with a support, removing material from the face remote from the support to give the desired lamina thickness and then oxidizing throughout the thickest parts of the remaining layer. A diode matrix is formed starting with a wafer consisting of an epitaxial N layer on an N+ silicon substrate. Silicon nitride is deposited on the N face by the gaseous reaction of silane and ammonia and formed into a mask by photoresist and etching steps. The exposed silicon areas are then oxidized in steam in a two-stage process with an intervening etching step to obtain a layer of the requisite thickness flush with the untreated parts of the silicon surface. After removal of the nitride phosphorous is diffused in to form N+ contact areas, which are then interconnected in rows by parallel strips of aluminium prior to sticking the diffused face to a glass or alumina support with polyvinyl acetate. Next the N + layer is etched electrolytically and the N layer chemically to expose the oxide network, after which gold Schottky contacts are deposited on all the exposed N areas and interconnected by aluminium tracks running transverse to the others, to which aluminium contacts are made via apertures etched through the network. A similar method is used to form an assembly consisting of silicon islands including a transistor and diode respectively (Fig. 9, not shown) save that in this case the silicon substrate is P type, the diode and transistor zones being formed by masked diffusions into the N-epitaxial layers prior to attachment to the support and removal of the substrate, the parts of the N zones to which contact is made being overdoped by ion implantation. In a process for forming complementary transistors in adjacent islands the collector zone of one is formed by diffusion into the N epitaxial layer and tungsten contacts made to both islands before provision of a support consisting of pyrolytically deposited polycrystalline silicon. After etching down to the oxide network as before the emitter of the one transistor and base and emitter of the other are formed by sequential masked diffusions and the transistors appropriately interconnected by deposited metal tracks, before aperturing the network to contact the tungsten contacts. In all cases the contacts and interconnections referred to are formed by overall deposition (e.g. sputtering) of metal followed by form-etching. Other types of device may be formed in the islands, some of which may include several devices, to constitute integrated circuits any capacitors in which may utilize the silica network material as dielectric. The use of molybdenum supports, and A III B V compound substrates for the silicon layer is also suggested.