Patent GB-1016798-A (GB)
Title: Data storage system
IPC: G11C21/00
Filed: 1964-11-23
Abstract: 1,016,798. Electric digital data-storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 23, 1964 [Dec. 31, 1963], No. 47503/64. Heading G4C. A data storage system comprises means for detecting a character of a particular type in a recirculating storage loop and for inserting data into the loop at a location corresponding to that of said character and delaying subsequent previously-stored data in the loop as necessary to avoid interference. Fig. 3 shows a magnetostrictive delay line 10 storing messages consisting of an address character (RA), followed by an " end of message " character (EOM), followed by one or more data characters. At least one blank character (all ZEROS) separates adjacent messages. Read-in.-Flip-flops FF1, FF2, FF3 are set at the beginning of each character time by a clock pulse tx. Flip-flops FF1, FF2 have their reset inputs connected to points in the storage loop 10 separated by a one-character delay DC1, so if two consecutive blank characters occur in the loop, then as the second is about to enter delay DC1, signals P and X are produced (the latter with the aid of an end-ofcharacter clock pulse ty). A blank character stored in a one-character delay loop M is continually compared in exclusive or gate 42 with the output from delay DC1 and resets flip-flop FF3 if unequal. Accordingly, if two consecutive blank characters are detected, AND gate 54 sets flip-flop FF5 to insert one-character delay DC3 into the loop 10 and gate the address character of the message to be stored from a one-character delay loop N via AND gate 30 into the loop 10. Thus the address character is stored in place of the second of the two blank characters, the second blank character and subsequent characters being effectively shifted back one character by insertion of delay DC3. The next pair of adjacent blank characters in the loop 10 is detected by flip-flops FF2, FF2<SP>1</SP> to produce a signal Y as the two characters are in delays DC2, DC3. This signal Y resets FF5 to remove delay DC3 from the loop. Thus one blank character is lost. The address character is next stored in loop M and the first data character in loop N. When FF2 detects a blank character, it sets flip-flop FF4 and when the following character is equal to the address character in loop M, exclusive-or circuit 42 does not reset FF4 with the result that FF4 sets FF5 on occurrence of clock pulse ty. This inserts delay DC3 into the loop 10 as before and gates the contents of loop N into loop 10. FF5 is reset as before on occurrence of two blank characters. The remaining data characters and the end-of-message character are now inserted in loop 10 in the same way, via loop N. Other messages from different sources ("terminal sets ") may then be stored in the same way. Read-out.-An " end-of-message " character, circulating in a one-character loop is compared in exclusive-or circuit 40 with characters in loop 10 to allow FF6 to produce a signal G, on detection of an " end-of-message " character in loop 10. Signal G, if a " read-out message " command from a message-utilizing computer is present, sets FF7 via AND gate 46 to pass the data characters following the " end-of-message " character out of the loop 10. FF7 is reset by signal X1 produced when FF2 detects the blank character following the last data character of the message. Modifications.-Fig. 4 (not shown) shows a modification permitting more than one character to be inserted in loop 10 per cycle thereof, by duplicating loop M &c. of Fig. 3 to search concurrently for several address characters in loop 10, detection of one permitting the contents of a corresponding one-character loop to be inserted into the loop 10, except that lockout means are provided to prevent a second insertion until the delay DC3 has been removed from the loop following a first insertion. It is mentioned that a particular address character could be searched for during read-out, and loop 10 could be replaced by a magnetic tape or a serially-accessed core memory. It is also mentioned that an error signal could be provided during an address character search by loop M (see Read-in) if a complete cycle of loop 10 passed without the address being detected, and a new character automatically gated into loop M.