Patent GB-1321895-A (GB)
Title: Digital storage apparatus
IPC: G11C19/28
Filed: 1970-07-24
Abstract: 1321895 Shift register WESTERN ELECTRIC CO Inc 24 July 1970 [25 July 1969] 35886/70 Headings G4A and G4C [Also in Division H3] A digital store, e.g. a shift register, consists of a number of cascaded stages each including a flip-flop 11 and a coupling device 12 which includes a means for temporarily storing a signal indicative of the state of the associated flipflop, the coupling devices being controlled such that in the normal "holding" state, i.e. when no shift pulse is applied, each coupling device is connected to its associated flip-flop and in the "shift" state each coupling device is disconnected from its associated flip-flop and connected to the flip-flop in the next succeeding stage. Thus the use of two phase "shift" pulses to load the contents of each flip-flop into the associated temporary store and to load the contents of each temporary store into the next succeeding flip-flop is avoided. As described the flip-flops consist of a pair of cross-coupled transistors 13, 14 and the stages are maintained in the holding mode by clamping control line 19 to ground by means of transistor 20. The coupling devices 12 consist of two matched parts each of which consists of a fast recovery (e.g. Schottky-barrier) diode 22 (32), an emitter follower transistor 23 (33) and a further diode 27 (37). In the holding mode the levels of conduction of transistors 23 and 33 depend upon the voltage at nodes 18 and 17, i.e. on the state of the associated flip-flop. Thus the state of each stage is also stored in the associated coupling device. To shift the information transistor 20 is turned off and presents a high impedance to the emitters of the flip-flop transistors causing the voltages at the collectors (nodes 18 and 17) to rise. The time constants of the circuit attached to the anode side of the fast recovery diodes 22 and 32 are greater than those of the circuits on the cathode side so that these diodes become reversed biased and isolate the flip-flops from the coupling devices. As the collector voltages of flip-flop transistors 13A and 14A rise they, and the corresponding base electrodes are clamped via diodes 27 and 37 at voltages dependent on the state of the coupling device transistors. Thus when transistor 20 is turned on again stage N + 1 goes into the holding mode with the state previously stored in stage N. In a modification, Fig. 2 (not shown), the biasing impedances for the base circuits of the emitter-follower transistors 23 and 33 include the collector-emitter circuit of a transistor in series with a resistance. The bases of these additional transistors are connected to a control line which is connected via a further transistor to a positive voltage source. This arrangement enables the flip-flop transistors to settle back into the holding state more quickly. Impedances can be connected in the collector circuit of transistors 23, 33 so that they may become saturated and provide additional charge storage in the form of minority carriers. To minimize power dissipation gateable impedances may be disposed in series with or substituted for resistors 25 and 35, and to increase the speed of operation the base collector junctions of the flip-flop transistors and transistor 20 may be shunted with diodes. The Specification states that FET's may be used.