Patent GB-1490524-A (GB)
Title: Memory apparatus
IPC: G11C11/408
Filed: 1974-10-08
Abstract: 1490524 Matrix stores PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 8 Oct 1974 [11 Oct 1973] 43518/74 Headings G4A and G4C A matrix store M (Fig. 1) comprising elements M ij  includes, for each row i of elements, a first selector line S1r i  connected to a control line a and enabling access to the elements and a second selector line S2r i+1  connected to a control line a which also enables access to the elements of the same row. This results (when column lines K j  are enabled) in a word W i  location being read out (or written into) if row line r; and selector line S1r i  are enabled and a word location W i-1  being assessed if row line r i  and selector line S2r i  are enabled Successive rows preferably contain successive digits to prevent arithmetic operations to be effected. Either switches Sl, S2 may be connected between the elements and the control lines or pairs of AND gates (E1, E2, Fig. 2, not shown) the latter also receiving the signal on the row line conductors. In an alternative embodiment (Fig. 3, not shown) a pair of AND gates is associated with each word. In the embodiment of Fig. 4 (not shown) the word lines (gr i ) are connected to alternate word locations (W;, W i+2 ). In one embodiment (Fig. 5) operating as an arithmetic unit, a digit in binary coded decimal form at input IR1 is successively compared with binary coded decimal digits read from a read only memory 1 under the control of a scanner SR1, at comparison the scanner being stopped. A second digit at input IR2 is then compared with the digits read from a second read only memory ROM2 under the control of a second scanner SR2, the scanner being stopped at equality. To add the scanners SR1, SR2 are then driven in the return and forward directions respectively the operation stopping when scanner SR1 reaches zero. The sum digit is then in register UR and any carry results in a flipflop FF being set by a signal on column kc. This results in a line a of the first read only memory ROM1 being energized so that a subsequent digit, e.g. 5 on input IR1 results in equality with the contents of ROM1 when its scanner is in position 6. Consequently when after entry of a digit at input IR2 and after the scanner SR2 has been moved to indicate this digit, both scanners are again clocked the two new digits are added together with any resultant carry from the first two digits. Subtraction may also be effected by running the scanners when they are simultaneously operative in the same direction. The scanners and read only memories may be manufactured on a single chip. Read only memory (Fig. 6, not shown)- The read only memory comprises pairs of transistors (bipolar or preferably FET) (2, 3; 10, 11) coupled by further transistors (6, 7) to column conductors (Y 1 ) each of the further transistors being enabled by a signal on an associated line (15, 14). Stored information is represented by the presence/absence of connections (16, 17) between the column conductors and the further transistors. The memory may store a microprogram. Fig. 10 (not shown) gives the layout for a read only memory semiconductor chip in which the insulating layers may be silicon oxide or silicon nitride and the conducted paths may be aluminium molybdenum or a semiconductor material with polycrystalline silicon gate electrodes.