Patent GB-1318231-A (GB)
Title: Data-processing systems
Inventor: FABER ULBE
IPC: G06F9/24
Filed: 1970-05-06
Abstract: 1318231 Data processing BURROUGHS CORP 6 May 1970 [19 May 1969] 21803/70 Heading G4A A data processing system which as described uses three instruction levels (macro, micro, and nanoinstructions) includes several registers for data transfer purposes, a logic unit, and a memory storing operational command instructions and sets of control instructions and is arranged so that in response to the retrieval from memory of certain ones of the operational command instructions the corresponding set of control signals is accessed in order to condition the operation of the logic unit or registers, certain ones of the control signals being such that they condition the operation of the registers directly, i.e., without decoding. S (macro) instructions.-Each S instruction consists of two parts indicating respectively a routine to be performed and the addresses of a peripheral or memory unit involved. The first part is applied, via the logic unit to the arithmetic and logic unit (ALU) output shift register and the M memory address register. M (micro) instructions.-The M memory is accessed by the address loaded in the address register, each succeeding instruction being addressed by a portion of its predecessor. A buffer may be provided to store a string of M instructions accessed in response to an S instruction, the instructions in the string being subsequently executed sequentially. Two types of M instruction are used. If the first bit of the instruction is a "1" then the instruction is used to address the N memory. If however the first bit is a "0" then no corresponding N instruction exists. If the first two bits are "01" then a part of the instruction is fed to the logic unit, if the third bit is a "1" then a part of the instruction is transferred to a register from where it controls the shifting of data in the ALU output shift register, and if the first three bits are all zero then the remainder of the instruction is a new M instruction address. The latter feature is used to control sequencing within the M program. Several tests are performed by each M instruction, the outcome determining the way in which that instruction is executed and the sequencing of the next instruction. The instructions are implemented in three time phase periods with type I instructions, i.e., those involving N instructions, occupying all three periods and type II instructions occupying only phase 1 time. The implementation of the M instructions is overlapped where possible, e.g. phase 1 of an instruction is performed during phase 3 of a preceding type I instruction. Depending on the operation being performed phase 2 operations may require more than one clock period, e.g., in the case where an instruction requires a replace operation, i.e. where a different instruction has to be fetched perhaps in response to the result of a condition tests, the current (type I) instruction is held in phase 2 for one clock period to permit phase 1 of the replace operation to be performed. N (nano) instructions.-N instructions, each of which contain several groups of control signals, may be used directly as control signals or may be decoded further. The instructions are addressed and accessed by a type I M instruction and are of three types for implementation in phases 1, 2, and 3 respectively. Phase I operations involve condition testing, M instruction modification, sequencing etc., phase 2 operations involve only logic operations and may take two clock periods, and phase three operations involve data transfer, and counter operations. Examples of N instructions are described in some detail in relation to the circuits, e.g. the logic unit, which they control. Modular adder/logic unit.-An adder is described which is modular in the sense that the format of the N instructions which control it is independent of the number of nodules used, further logic modules together with their associated N instruction decode gates being added in order to handle the required number of parallel bits. The adder incorporates a carry look ahead facility in each of the two embodiments which are described. Further details.-The three memory sections for the S, M, and N instructions may all be of the magnetic thin film type athough the N memory may be a read only device. A multiprocessor system may be constructed by interconnecting several processors, memories, and I/O peripherals via a switching interlock.