Patent ES-347094-A1 (ES)
Title: Selective Signalling System.
IPC: H04L29/12
Filed: 1967-11-13
Abstract: In a signalling system for transmitting coded information from a transmitter to a selected one of a number of receiving stations, the coded information being one or more characters each composed of a group of 8 binary bits, the transmitter has an input member arranged to generate groups of binary bits representing selected characters and to feed them to a data store 58, Fig. 2A, there being a clock pulse source 62 to read the characters serially from the store, a recirculation loop 220 by which the information is rewritten in the store as it is transmitted, and a character store 82, Fig. 2B, connected with the data store to record the number of characters in the data store and to ensure the correct positioning of said characters on transmission. The data store 58 comprises a series of bi-stable stages sufficient to store eight characters each represented by a group of seven bits and a parity bit. The store is loaded by depressing keys on a keyboard 14. When a key is depressed a corresponding lead is energized to set a pattern of bi-stable elements (flip-flops or cores) in the load stage which also comprises 8 elements. When the load stage is set according to the desired pattern an output on lead 86 starts the clock circuit 62 applying staggered pulses on leads 84, 85 to step the character into stage 1 of the store. At the other end of the store is a sync. stage in which is a single pulse. As the clock pulses shift the characters along the store the pulse recirculates in the sync. stage giving an output pulse S1 on lead 90. This is applied to the character store 82 to move a " 1 " bit in the 0 stage into the 1 stage causing the 1 lamp to light indicating that one character has been entered in the data store 58. The sync. pulse also produces an S2 pulse which passes via gates 98 and 56 to stop the clock 62. The keyboard is then operated again to enter the next character the " 1 " in register 82 being stepped for each character entered. A special end character STX is entered from the keyboard, to define the end of the transmission, which may not consist of a full eight characters. Transmission is initiated by a " send " button 18 which sets a flip-flop 50. If the receiving apparatus is not busy, gate 124 is enabled by a signal on lead 128, flip-flop 44 is set and a series of gates 136-138 are opened to set one of the stages of memory register 66 in accordance with the setting of the corresponding stage of character register 82. The memory register is used to keep the data register 58 and the character register 82 synchronized irrespective of message length. The presence of a " 1 " in any stages 1-7 of register 82 will cause a pulse to pass through Or gate 94 to enable And gate 146, to produce a start signal which is applied to start the clock 62. The data in register 58 is thereby shifted towards the right, the S1pulses on lead 90 causing the " 1 " in register 82 to move one step to the right for each eight steps of register 58. The clock runs until the " 1 " reaches stage 7 of the register 82 when a " send ready " lamp 28 lights and gate 120 is enabled to inhibit the keyboard from further operation. Flip-flop 72 is also set by the signal in stage 7 of register 82, via gate 156 which also sets the mark/space flip-flop 164 into the space condition. Flip-flop 72 starts a 200 millisecond delay 168 and enables output gates 170, 172 and 202, whereby a " pretone character is sent before the transmission of the stored characters. The flip-flop 164 drives a tone oscillator 178 to generate different tones for mark and space signals which are sent out on line 184. A relay 190 operated by gate 172 causes a contact to energize mark or space lines 196, 200. Two types of output are therefore provided. Gate 202 drives a keying relay providing energization of outputs 210 or 211. After the 200 millisecond delay the start character is loaded into stage 8 of register 58 and the clock 62 starts to shift the data from stage 8 to the output flip-flop 164 over leads 59, 61 so that the corresponding signals are transmitted. At the end of the start character the " 1 " in the sync. stage will give another pulse on lead 90 to operate flip-flop 78 to turn on the " send " lamp 30. The registers 58 and 82 are shifted until the data is in identical positions in each, this being checked by gates such as 230 connected to the memory register. The data is shifted until the " 1 " in register 82 is in stage 7. The data can then be transmitted. If a full 8 characters have been entered the preliminary shifting is not necessary. After transmission the circuit is cleared before another message can be sent. Receiver.-At the receiver the tone pulses are passed to tone filters, the outputs being rectified, amplified and squared to provide mark and space pulses on separate leads. Signals that are too short or too long are prevented from operating the circuit, and if no signal is received for 250 milliseconds the circuit is reset. The incoming bits are counted by a counter having 8 stages and outputs connected to advance a character register also comprising 8 stages. The characters are compared, as they are received, with locally generated characters which are entered by coding plugs 360 in turn into an eight-stage register 322. Character sequencer 358 energizes the coding plugs in turn. Exclusive Or gate 332 compares incoming bits on lead 334 with the output of character register 322. If the characters do not compare, the gate produces a reject and reset signal. If there is agreement the character stored in the register 322 may be gated to a decoding network providing control signals on one of ten leads.