baber/WOPTO huggingface dataset:
Patent JP-S6111874-A (JP)
Title: Data transfer system between computers
Inventor: KOYAMA MINORU
IPC: G06F13/12
Filed: 1984-06-27
Abstract: PURPOSE:To simplify communication control procedure by extending the address space of a bus of a microprocessor built in a channel device up to the inside of the opposite channel device to which data are to be transferred. CONSTITUTION:After checking that an extended bus 35 is not used for data transfer, a bus controller 31 controls a bus master switching circuit 32 to couple a microprocessor bus 23 with the extended bus 35 and open the extended bus 35 to a microprocessor 21. Then, the microprocessor 21 sends a transfer control signal in a program mode to a channel device 14 through the extended bus 35. Receiving a transfer control signal in a program mode from the microprocessor 21 through the extended bus 35, a bus slave switching control circuit 33 sends a control signal to a bus slave switching circuit 34 to control the coupling of the extended bus 35 with an extended bus 36 in a sub-channel device.
Patent JP-S5758360-A (JP)
Title: Semiconductor device
Inventor: YAMAZAKI SHIYUNPEI
IPC: H01L21/8234
Filed: 1980-09-24
Abstract: PURPOSE:To obtain a gate electrode of semiconductor device being reinforced dynamically by a method wherein the gate electrode is made as the side part thereof to lean against the first region being enabled to constitute the source and drain. CONSTITUTION:A field insulator 2 is buried in the surface of an Si single crystal substrate by the selective oxidation method, and the first region 3 is formed on the surface thereof with an Si semiconductor being doped with an N<+> type impurity by depressurized vapor phase growth. An insulating region 4 is provided on the side circumference and on the upper side of the region 3. The triangular gate electrode 6 being consisted of the first and the second layers consisted of at least two conductors or semiconductors is provided at the corner part between the region 4 and the substrate 1, and the second two regions 13 are provided beneath the electrode 6 and one ends of two electrodes separately from the region 3.
Patent JP-S5922391-A (JP)
Inventor: TAKAHASHI SEIHACHI
IPC: B23K1/00
Filed: 1982-07-29
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H10319367-A (JP)
Title: Liquid crystal display module and portable terminal using the module
Inventor: KAWASAKI NAOTO
IPC: G02F1/133
Filed: 1997-05-23
Abstract: PROBLEM TO BE SOLVED: To eliminate data correction of a pen position by suppressing a noise level occurring from itself when an alternating signal is switched in a liquid crystal display module. SOLUTION: Since thins module is provided with a display off generation circuit 21 making a display off signal active when the alternating signal is switched and outputting it to a COM driver 4 of a liquid crystal panel 2, and since the display off signal is made active when the alternating signal is switched when the noise level occurring from the liquid crystal module 1 itself becomes maximum, a drive voltage applied to the liquid crystal display panel 2 becomes a non-selection level, and becomes a voltage level lower than a regular selection level, and the noise level occurring from the liquid crystal display module 1 itself is reduced.
Patent JP-H0429963-A (JP)
Title: Production of benzophenones
Inventor: KANEKO KAZUO
IPC: C07C229/52
Filed: 1990-05-24
Abstract: PURPOSE:To obtain 2-alkoxy derivative in high purity and in high yield by alkylating a 2-hydroxy-4-dialkylaminobenzophenone-2'-carboxylic acid in the presence of KOH used as a deacidifying agent and then hydrolyzing the alkylated compound. CONSTITUTION:KOH having molar ratio of 2.1, based on 2-hydroxy-4 dialkylaminobenzophenone-2'-carboxylic acid (A), is added to water of 1.2-1.8(wt.) times the compound A, and then the compound A is added thereto to dissolve the compound A in the solution. An alkylating agent having 2.05 molar ratio, based on the compound A, is dropwise added to the solution at 25-35 deg.C to alkylate the compound A. Then NaOH and water is added thereto and the mixture is stirred for several times at about 100 deg.C to hydrolyze the alkylester compound, and then hydrolyzed product is subjected to acid deposition using acetic acid to produce 2-alkoxy-4-dialkylaminobenzophenone-2'-carboxylic acid. The reaction concentration can be increased by using KOH and, as a result, the objective product is obtained in high purity and in high yield.
Patent JP-H0429140-A (JP)
Title: Automatic developing device
Inventor: MATSUMOTO TOSHIYA
IPC: G03D3/00
Filed: 1990-05-24
Abstract: PURPOSE:To stabilize a developing process and to prevent an irregularity in development by providing a means which limits a flow of upper processing liquid as compared with lower liquid between a film conveying means and a heat supply means. CONSTITUTION:A developer partition part 41 is provided as the limiting means nearby the liquid surface of a liquid developer 42 to a developing tank 8 to prevent the liquid developer 42 from moving from a heater 23 to nearby a film conveyance part 13. The liquid developer which is heated by the heater 23 moves as shown by arrows (g) and (h) and stays nearby the liquid surface, but is stopped by the liquid developer partition part 41 and the heated liquid developer 42 does not contact a film directly; and a difference in liquid temperature due to the depth is reduced nearby the film at the film conveyance part 13 and the distribution of the liquid temperature becomes uniform. consequently, the developing processing is stabilized and the development irregularity can be prevented.
Patent JP-S6224146-A (JP)
Title: Enzyme immunoassay of prostaglandin i2 derivative
Inventor: HIRANO MASAHIKO
IPC: C07D307/93
Filed: 1985-06-18
Abstract: PURPOSE:To enable the measurement of a trace prostaglandin (PGI2) derivative in a biological sample at a high sensitivity, by immobilizing an antibody to the PGI2 derivative expressed by a specified formula. CONSTITUTION:An IgG fraction as antibody is immobilized on an immuno plate, particle, test tube or the like as solid phase. The antibody is immobilized easily on the solid phase in a physical adsorption. In the use thereof, the solid phase is washed and a sample containing a PGI2 derivative (A) expressed by a formula and a reference PGI2 derivative (A) are added thereto to carry on an antigen-antibody reaction. Subsequently, an enzyme labelled PGI2 derivative is added to cause a emulating reaction with the PGI2 derivative previously added. After the end of the emulating reaction, the solid phase is washed thoroughly and an enzyme substrate is added to carry on an enzyme reaction. After a fixed reaction time, changes in the absorbance due to the decomposition of the substrate are measured spectroscopically. As a color formation occurs in response to the amount of enzyme bonded to the antibody, the amount of the PGI2 derivative is determined from the value of the absorbance. An assay is done by measuring the amount of the PGI2 derivative in the sample from a calibration curve using the reference PGI2 derivative.
Patent JP-H087050-A (JP)
Title: Card forcedly ejecting mechanism for card reader
Inventor: OGUCHI KATSUAKI
IPC: G06K13/067
Filed: 1994-06-15
Abstract: PURPOSE:To provide a card forcedly ejecting mechanism capable of surely ejecting a card blocked inside of the card transfer passage of a card reader from the card transfer passage. CONSTITUTION:A driving gear 36 is fitted to the driving shaft 17 of a driving roller 6a rotationally driven by a driving motor 25, a clutch gear 38 engaged to the driving gear 36 is provided on a supporting shaft 37 freely slidably supported by a base part 11A, and a forcedly ejecting member 46 in contact with a card C within the passage by being introduced into the card passage 3 and an ejection gear 40 capable of engaging with the clutch gear 38 are provided on a shaft 39 which is freely rotatably supported by the base part 11A, so as to engage the clutch gear 38 by displacing toward the ejection gear 40 by a driving means 41, in the card forcedly ejecting mechanism 10.
Patent JP-H09321043-A (JP)
Title: Method for manufacturing semiconductor device
Inventor: TAKAGI MARIKO
IPC: H01L21/302
Filed: 1996-05-28
Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for which calculation for positioning is not needed and which has dummy patterns for preventing short circuits with wirings and whose surface is flattened by a CMP(chemicalmechanical polishing) method. SOLUTION: A mask is provided with patterns having line width and space of the same order with the smallest line width and space of wirings 2 on its entire surface. Exposure to light is performed through the mask 6 to form resist patterns 9 on a lower level region 4 between the wirings 2. Then etching operation is performed with the resist patterns 9 as mask to form dummy patterns 10 consisting of an interlayer insulating film 3. A further interlayer insulating film 11 is formed on the surface and is flattened by a CMP method.
Patent JP-H05324617-A (JP)
Title: Scale display system
Inventor: NISHIKAWA TORU
IPC: G06F3/153
Filed: 1992-05-26
Abstract: PURPOSE:To easily confirm the position, etc., a character on a screen by displaying a scale in a window provided at the display screen of a wordprocessor. CONSTITUTION:A lateral scale 5a and a longitudinal scale 5b are displayed as the window on the display screen of the wordprocessor. That is, the division interval of the scale is calculated from a display magnification on the screen, and whether the lateral scale display is designated, or the longitudinal scale display is designated is judged. When the lateral scale display is designated, the position of the lateral window is set, the size of the lateral window is set, and the position of the division interval of the lateral scale is set. Then, the window is displayed, and the scale is displayed in the window. Therefore, the lateral and longitudinal scales can be displayed at the arbitrary positions on the screen.
Patent JP-H01300958-A (JP)
Title: Intraocular lens having surface functional film
Inventor: OKAMURA MORIYUKI
IPC: B29D11/00
Filed: 1988-05-31
Abstract: PURPOSE:To enhance durability and abrasion resistance, by forming a close adhesion layer of a plasma polymer having a dense crosslinked structure prior to applying the coating of a functional film of various kind. CONSTITUTION:A coil 2 is provided to the periphery of the small diameter part provided to a chamber 1 and a current is supplied to the coil 2 from an RF power supply 3 to generate charge. The org. monomer introduced from an introducing port 6 is subjected to plasma polymerization reaction to form a polymer on the surface of the intraocular lens L supported in the large diameter part of the chamber 1. As the org. monomer, one or more kind of a compound selected from a group consisting of a hydrocarbon compound, a halogenated hydrocarbon compound, a hetero element-containing hydrocarbon compound and an organometal compound is used. Thereafter, a functional film is formed.
Patent JP-H08331709-A (JP)
Title: Insulating support base and high-voltage receiving apparatus
Inventor: KAWAHARA KOUNOSUKE
IPC: H01F27/04
Filed: 1995-05-31
Abstract: PURPOSE: To facilitate assembling operation by providing a support part nearly vertical to a receiving base and the mounting face of the receiving base, providing a plurality of holes for fixing a conductor in the support part in the direction vertical to the mounting plane and marking with dimensional degrees. CONSTITUTION: A conductor support plane 12 is formed in a plane vertical to a mounting plane 11 having a fixing screw 10 for an insulating support base. It has a conductor receiving plane 13 in a plane parallel to the mounting plane 11, bolt insertion holes 14a, 14b, 14c for supporting a band copper are provided in the conductor support plane 12, and a plurality of divisions 15 for expressing a positional relationship between the band copper and the conductor receiving plane 13 are provided to the band copper and the conductor receiving plane 13. When the plate thickness plane of the band copper is horizontally disposed and the band width plane is vertically disposed and the band copper is disposed in horizontal and parallel to the disposition of a breaker for wiring, the area of the band width plane of the band copper opposite to each other becomes sail. Therefore, the fastening operation of a connection screw is effectively performed and the equipment is miniaturized.
Patent JP-S5834941-A (JP)
Title: Manufacture of semiconductor device
Inventor: KAMEYAMA SHIYUUICHI
IPC: H01L21/76
Filed: 1981-08-27
Abstract: PURPOSE:To form the favorable element isolation region in a semiconductor device by a method wherein the groove parts having the sides deeper than depth of junction and moreover being perpendicular and having the slant bases are provided in the semiconductor layer, and an insulator is accumulated to be buried in the groove parts thereof. CONSTITUTION:When the insulating accumulation layers 111 are to be formed in the groove parts provided in the semiconductor layer 101 to form the element isolation region, the groove parts having the perpendicular or the nearly perpendicular sides of depth D1 shallower than depth D2 of the groove parts to be set, and having the slant type bases, the V-type bases for example, are formed. When the insulating films 111 are accumulated in the groove parts thereof, the favorable shape insulating accumulation layers having no cavity are formed being buried. Moreover when the junction is coming in contact with the sides, by making depth of the perpendicular sides of the groove parts to deeper than depth of junction, reduction of junction depth C at the junction faces is not generated. Accordingly favorable element isolation can be attained.
Patent JP-S63300241-A (JP)
Title: Electrostatic latent image developing toner
Inventor: YAMAGUCHI KIMITOSHI
IPC: G03G9/08
Filed: 1987-05-30
Abstract: PURPOSE:To prevent blocking of a toner fixable at low temperature by coating the surface of each specified particle with a specified F-containing silane compound. CONSTITUTION:The surface of each of the heat-fixable core particles A is coated by buring with smaller particles B in a depth not larger than the particle diameter of B, and further the surfaces of the particles B and those of the composite particles consisting of A and B are coated with the F-containing silane compound represented by formula I in which X is 1-6C alkyl containing F; Y is phenylene or SO3; R is H or 1-5C alkyl or alkoxy; (m) is 0-3; and (n) is 0 or 1. A compound of formula II and the like can be used for said compound of formula I. The particles B are made of an organic polymer higher in softening point and smaller in average particle diameter than the particles A, or the particles B have substantially not a softening point.
Patent JP-H02310591-A (JP)
Title: Character generating device
Inventor: ONOZAWA YUJI
IPC: G06T11/20
Filed: 1989-05-26
Abstract: PURPOSE:To attain plotting in high quality even for small characters by calculating the length of lines by which inside letters are painted over in accordance with coordinate points extracted and sorted by label values. CONSTITUTION:Information on the contours of the characters is read from a font data memory 1 storing the information and coordinate calculation for dots for plotting the contours is performed. Then the information is stored in a contour plotting memory 6. At the same time, calculated coordinate values are provided with labelling values for painting over and labelled coordinate points data is sorted and a distance between the coordinate points is calculated as the number of the dots by an MPU 3. The outputs of a paint-over memory 9 and the contour plotting memory 6 are ORed by a logical circuit 10 and paint-over data is completed. Thus even if the angle of a single dot exists on a contour, painting over is performed without fail and characters of high quality can be speedily plotted.
Patent JP-H09321622-A (JP)
Title: Frequency synthesizer
Inventor: HIRATA KENRO
IPC: H03L7/093
Filed: 1996-05-28
Abstract: PROBLEM TO BE SOLVED: To enable the compensation of a phase error only through digital signal processing and to perform high-precision spurious suppression by shifting the phase of a reference frequency output pulse and compensating the phase error on a sprious generating frequency band. SOLUTION: A reference frequency divider 2 generates the phase shift output pulse of a reference frequency fref to be divided according to a reference frequency dividing number Nref from a phase error compensating means 9. A loop filter 5 converts the output of a charge pump 4 to a voltage value and outputs it to a voltage controlled oscillator 6. A frequency dividing number switching circuit 8 uses the output pulse of a variable frequency divider 7. The compensating means 9 generates the reference frequency dividing number Nref for shifting the phase of a reference frequency output pulse according to the output of phase error data Eθ(n) of the switching circuit 8. As a result, the phase error can be compensated only through digital signal processing and there is no influence from environmental temperature changes, etc.
Patent JP-H01303594-A (JP)
Title: Machine guard system
Inventor: SUZUKI OSAMU
IPC: G08B13/00
Filed: 1988-05-31
Abstract: PURPOSE:To obtain the machine guard system which enables ID card registration and explanation to tenants to be performed simultaneously at one placed by registering an ID number from an ID discriminating device. CONSTITUTION:A mode switch 1c is placed on a registration side, a card with a start ID number used for a tenant A is read and stored on a RAM 1f, and a card with a final ID number used for the tenant A is also read and stored on the RAM 1f. Then the mode switch 1c is put back to a passage mode, the ID numbers are transmitted to a host CPU 4 and stored on the RAM 4c of the host CPU 4, and all the IC numbers of the tenant A are printed out by the host CPU 4. Further, similar registration is performed for a tenant B. Namely, when ID numbers continue, the start and end ID numbers are only registered to register all the ID numbers. Consequently, the registrations of cards and the explanation tenants are performed simultaneously at one place.
Patent JP-H0427291-A (JP)
Title: Color solid-state image pickup device
Inventor: OMAE MASANORI
IPC: H04N9/07
Filed: 1990-05-22
Abstract: PURPOSE:To easily raise the sensitivity by using a vertical adjacent two-picture element mixed and odd column horizontal picture element mixed image pickup signal and a vertical adjacent two-picture element mixed and even column horizontal picture element mixed image pickup signal to perform color separation. CONSTITUTION:The vertical adjacent two-picture element mixed image pickup signal of a first column is added to that of a third column to obtain the vertical adjacent two-picture element mixed and off column horizontal picture element mixed image pickup signal, and the vertical adjacent two-picture element mixed image pickup signal of a second column is added to that of a fourth column to obtain the vertical adjacent two-picture element mixed and even column horizontal picture element mixed image pickup signal. Image pickup signals of the third column and the fourth column are sampled and the difference between them is taken to obtain color difference signals C1H and C2H. A luminance signal YH and two color difference signals C1H and C2H are synthesized to obtain a color composite video signal.
Patent JP-H11331053-A (JP)
Title: Repeater for communication equipment
Inventor: TOKUNAGA MASAHIRO
IPC: H04W16/26
Filed: 1998-05-15
Abstract: PROBLEM TO BE SOLVED: To simultaneously achieve improvement in the accuracy of communication with an external communication station and the facilitation of operation, by performing communication between the external communication station and a base unit while temporarily interposing a repeater. SOLUTION: This communication equipment is loaded in the room of a moving object 10 such as an automobile and in the case of exchanging prescribed information data concerning ETC or the like with an external communication station 11 outside the moving object 10 through radio waves, radio communication is performed while interposing a repeater 12 inside the moving object 10. The repeater 12 is loaded near the front glass of the automobile or the like and a transmission/reception antenna 21 for performing transmission/ reception to both the external communication station 11 and a base unit 13, a signal circulator 22 for processing both reception and transmission signals and an amplifier 23 for amplifying the signal received by the signal circulator 22 and feeding it back to the signal circulator 22 are formed on one printed circuit board.  As the signal circulator 22, a general circulator is used.
Patent JP-H11323730-A (JP)
Title: Production of craped knit or woven fabric
Inventor: SATO JUNYA
IPC: D06M13/368
Filed: 1998-05-15
Abstract: PROBLEM TO BE SOLVED: To provide a method for producing a craped woven or knit fabric, capable of obtaining a high craping property without increasing the number of twisted yarns and without generating fibrillation. SOLUTION: This method for producing a craped knit or woven fabric comprises imparting a compound having two or more functional groups capable of reacting with yarns or a solution or dispersion of the compound to the yarns, thermally treating the yarns, twisting the yarns, weaving or knitting the twisted yarns and subsequently subjecting the woven or knit fabric to a craping treatment. The yarns are cellulose yarns, and the compound having two or more functional groups capable of reacting with yarns is at least one kind of compound among N-methylol compounds, dimethyl urea compounds, aldehydes, acetals, epoxides, active vinylic compounds, aziridinyl compounds, polycarboxylic acids, acid chlorides and isocyanate compounds.
Patent JP-S5923384-A (JP)
Inventor: NAKAMURA KATSUTOSHI
IPC: G06F3/038
Filed: 1982-07-30
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H07320484-A (JP)
Title: Output buffer circuit and boosting method
Inventor: SUKOTSUTO II SUMISU
IPC: G11C17/00
Filed: 1994-05-11
Abstract: PURPOSE: To obtain a CMOS memory integrated circuit with an output buffer having an N channel pull-up output transistor receiving boosted gate voltage and outputting a complete power-supply voltage level. CONSTITUTION: A MOSDRAM memory device contains an output buffer 10 with an N channel output transistor 13, which receives a boosted gate signal and must generate a complete Vdd high logical level signal to an output terminal. Vdd power-supply voltage and the output terminal are connected by the N channel transistor 13. Vdd power-supply voltage is joined with a gate for the output transistor 13 only for a short period of time sufficient for elevating the gate for the output transistor 13 up to a Vdd voltage level by the output buffer 10, and a Vdd power supply is detached. Vdd + power-supply voltage is connected to the gate by the buffer 10, gate voltage is made higher than Vdd power-supply voltage by the threshold value of at least the transistor, and Vdd voltage is acquired at the output terminal.