baber/WOPTO huggingface dataset:
Patent TW-533558-B (TW)
Title: Substrate manufacturing method for forming image sensor package
Inventor: LIN VINCENT
IPC: H01L23/28
Filed: 2000-09-29
Granted: 2003-05-21
Abstract: There is provided a substrate manufacturing method, which comprises the steps of: (a) providing a molding die having an upper mold and a lower mold, in which the lower mold has at least two projections, each having a recess; (b) sealing and clamping the molding die on a leadframe so that a chip supporting member is located in the cavity of the molding die, in which the corner of the chip supporting member is jointed with the recess of one of the at least two projections, thereby ensuring that the surface of the chip supporting member is parallel with the leadframe; (c) injecting thermoplastic material into the mold cavity; (d) curing the thermoplastic material; and (e) opening the molding die to take out the molded product. In accordance with the substrate manufacturing method of the present invention, since the corner of the chip supporting member is fixed by the at least two projections of the lower mold, the chip supporting member is not influenced by injecting the thermoplastic material in step (d), thereby ensuring that the surface of the chip supporting member is parallel with the leadframe.
Patent TW-546936-B (TW)
Title: Data encrypting/decrypting system in client/server structure and the method thereof
Inventor: WENG CHIEN-SEN
IPC: G06F3/0486
Filed: 2000-10-27
Granted: 2003-08-11
Abstract: The present invention provides a data encrypting/decrypting system for the data encrypting and decrypting operations in the client/server structure, and dividing the data into a plurality of channels. The data encrypting/decrypting system comprises: a service system and a client system, wherein the service system is used to transmit the encrypted channel, and the client system is used to receive the encrypted channel. The service system includes the encrypting unit for conducting different encrypting methods according to the plurality of channels. The client system further comprises a channel receiving unit and a plurality of decrypting unit; wherein the channel receiving unit is used to select the channel, and the decrypting unit has to be moved to the top position of the channel receiving unit for conducting the decrypting operation, and the decrypting unit is used to directly present the channels after decoding.
Patent TW-454256-B (TW)
Title: Manufacturing method of the dielectric layer in the semiconductor devices by using etching stop layer
Inventor: YANG CHIH-SHENG
IPC: H01L21/768
Filed: 2000-11-03
Granted: 2001-09-11
Abstract: The present invention provides a manufacturing method of the dielectric layer in the semiconductor devices by using etching stop layer, and the semiconductor structure manufactured by this method. The manufacturing method of the present invention comprises the following steps: provide a semiconductor substrate comprising a convex portion and a concave portion; form a first etch stop layer covering the convex portion and a concave portion; form a dielectric layer covering the top of the first etch stop layer, wherein the thickness of the dielectric layer is substantially less than that of the convex portion; form a second etch stop layer covering the dielectric layer; and proceed a planarization procedure, polish the second etch stop layer and the dielectric layer until the first etch stop layer located on top of the convex portion is exposed. At this time, plural remaining pieces of second etch stop layer will be left on the planarized surface, and on the dielectric layer located in the convex portion.
Patent TW-I222632-B (TW)
Title: Optical disk device
Inventor: KUSUMOTO KUNIMASA
IPC: G11B7/007
Filed: 2001-03-15
Granted: 2004-10-21
Abstract: The optical disk device is disclosed which relates to the loop gain adjustment of the focus/tracking servo of the optical disk device, the loop gain adjustment can be converged normally even in the case that the unrecorded area and the recorded area are coexist and the servo system can be stabilized even in the case that the gain is varied significantly by the variation of the disk state. When the inserted optical disk is detected as the recordable disk by the optical disk type judgement device, the optical pick up 1 seeks the predetermined area for adjusting the loop gain. The gain adjustment value is changed by the gain adjustment device 10 when the gain is varied during operating.
Patent TW-I229264-B (TW)
Title: Method for developing bluetooth software protocol layer
Inventor: YE CHENG-SHIUAN
IPC: H04L12/56
Filed: 2001-04-04
Granted: 2005-03-11
Abstract: The present invention relates to a method using computer software to implement the switch of packet transmission route in bluetooth communication, which is suitable for transmitting a plurality of bluetooth packets between at least two electronic machines respectively having at least a first transmission route and a second transmission route. The first transmission route has at least one bluetooth hardware and a bluetooth physical communication layer transmitting through the 2.4 GHz band. The second transmission route has at least one virtual bluetooth host controller interface system and other physical communication layer. The two electronic machines separately execute source codes, which realize the method with software, to transmit the bluetooth packets via the first transmission route or the second transmission route. The method includes steps of providing a switch transmission route command packet to assign a plurality of routes for bluetooth packet transmission between the two electronic machines; and coding and executing a bluetooth switch source codes to perform the processing of the HCI switch transmission route command packet. The method switches the transmission route between the two electronic machines on demand. Under normal condition, the packets are transmitted through the 2.4 GHz ISM band using the bluetooth hardware of the two electronic machines. When needing to assign the packet to other type of physical communication layer for transmission, the electronic machine transmits the bluetooth packets through other physical communication layer assigned by a virtual host controlling interface system by providing a new HCI command packet and coding and executing a bluetooth switch source codes.
Patent TW-490994-B (TW)
Title: Method of making an emissive layer for an organic light-emitting device
Inventor: LONG MICHAEL EDGAR
IPC: H01L51/30
Filed: 2001-04-09
Granted: 2002-06-11
Abstract: A method of making an electroluminescent device having a substrate, and at least one dopant receiving layer containing a host material which when doped provides an emissive layer, includes providing at least one dopant layer having a dopant disposed over or under the dopant receiving layer; providing an anode and a cathode so that the dopant receiving layer and the dopant layer are disposed between such anode and cathode; and heating the electroluminescent device to cause the dopant to diffuse from the dopant layer into the dopant receiving layer and forming the emissive layer having uniformly dispersed dopant in the host material.
Patent TW-526261-B (TW)
Title: Low emissions F-T fuel/cracked stock blends
Inventor: BERLOWITZ PAUL JOSEPH
IPC: C10L10/12
Filed: 2001-04-18
Granted: 2003-04-01
Abstract: A blend useful as a diesel fuel, as well as a method for its production, comprising a high quality Fischer-Tropsch derived distillate boiling in the range of a diesel fuel blended with a cracked stock boiling in the range of a diesel fuel wherein the final blend contains 10-35 wt% aromatics and 1-20 wt% polyaromatics and produces low regulated emissions levels.
Patent TW-515067-B (TW)
Title: Metal bump having higher pillar and the fabricated device thereof
Inventor: SHIE WEN-LE
IPC: B23K20/00
Filed: 2001-05-31
Granted: 2002-12-21
Abstract: The present invention provides a metal bump having higher pillar and the manufacturing device thereof. The metal bump includes a hard-tube-like solder pin member having a gold bonding wire with an inner diameter passing through the center and inner wall, and the cross section of the inner wall of solder pin is a slightly tapered pillar with a wider bottom portion. The metal bump fabricated according to the shape of the cross section of the solder pin is described as follows. When the end of the metal wire in the solder pin is sintered to be ball-like for forming the shape, the metal surface of the pin pad is varied by using mechanical energy and thermal energy such as ultrasonic vibration energy and pressurizing distortion energy, etc. to bond the metal. Since the cross section of the inner portion of the hard-tube-like solder pin is slightly tapered with wider bottom portion, when the metal wire is filled on the inner wall portion, it is bonded with the pin pad of the die and naturally form a bell-like metal bump. The bottom portion of the bell-like metal bump forms a protruded edge seat due to the inner ring at the bell bottom of the inner wall portion of capillary, which is helpful to stabilize the metal bump. The bell-like metal bump also has a higher pillar. Due to the inner cross-section shape design in accordance with the present invention, the pillar height of the metal bump can be easily and correctly increased, so as to increase the subsequent bonding gap between the chip and the substrate. When mounting solder ball on the metal bump, the present invention is able to prevent the solder ball from contacting with the aluminum pad, which may influence bonding reliability.
Patent TW-535377-B (TW)
Title: Multi-path dynamic routing algorithm
Inventor: WORFOLK PATRICK A
IPC: H04L12/56
Filed: 2001-06-07
Granted: 2003-06-01
Abstract: Disclosed is a routing algorithm that uses a new concept of node metric system for optimizing the throughput of a network, in particular, a shared medium network. The measure of congestion of a path in the network is represented by a path metric which is computed by summing the node metrics of the intermediate nodes on the path. Factors used in computing node metrics include the following: (1) future traffic load from neighboring nodes to the node; and (2) future traffic load from the node to the neighboring nodes.
Patent TW-548920-B (TW)
Title: Web pad module with a rear coupling device of a web pad
Inventor: LO CHAI-CHING
IPC: G06F1/16
Filed: 2001-06-07
Granted: 2003-08-21
Abstract: The present invention provides a web pad module, which includes a portable web pad and a pad base. The web pad has a housing, a processing circuit installed inside the housing for controlling the web pad, a display panel for displaying images, and a first coupling device installed on a rear side of the housing. A first connector is installed in the first coupling device and electrically connected to the processing circuit. A second coupling device is installed on the pad base for detachably coupling with the first coupling device so that the web pad is placed on the pad base. The second coupling device has a second connector corresponding to the first connector. When the first coupling device is coupled to the second coupling device, the first connector is therefore connected to the second connector and signal can be transmitted between the web pad and a peripheral device through the pad base.
Patent TW-556102-B (TW)
Title: Method for database security control mechanism
Inventor: CHEN JIN-SHIAN
IPC: G06F17/30
Filed: 2001-06-15
Granted: 2003-10-01
Abstract: The present invention provides a database security control mechanism, which includes the following steps: first, loading with the user name and the password; checking the user name and the password; then, connecting to the database, which uses the dynamic link library to connect to the database; finally, checking the internal application program and authorizing the access right to complete the database security control mechanism.
Patent TW-521057-B (TW)
Title: Use of transponders for the documentation and the manipulation of waste
Inventor: LANDRE MARTIN
IPC: B65F1/14
Filed: 2001-06-26
Granted: 2003-02-21
Abstract: Use of transponders for the documentation of waste manipulation whereby packages are generated at the collection sites, a material designation is submitted to a databank for every package, a transponder is attached to every package, a transponder identification is read into the databank and the transponder identification is allocated to the material designation, the packages are transported in transport lots, whereby a reading of the transponder occurs during loading and the read data are entered into the databank, at the waste treatment location the transponder and its package are treated and read and the treated packages are registered in the databank.
Patent TW-I239030-B (TW)
Title: Process system for immersion processing wafers or workpieces, and an immersion module
Inventor: HARRIS RANDY
IPC: H01L21/00
Filed: 2001-07-06
Granted: 2005-09-01
Abstract: A process system for processing semiconductor wafers includes a stocker module, and immersion module, and a process module. A process robot moves on a lateral rail to transfer wavers between the modules. The immersion module is separated from the other modules, to avoid transmission of vibration. Immersion tanks are radially positioned within the immersion module, to provide a compact design. An immersion robot moves batches of wafers on an end effector between the immersion tanks. The end effector may be detachable from the immersion robot, so that the immersion robot can move a second batch of wafers, while the first batch of wafers undergoes an immersion process.
Patent TW-515901-B (TW)
Title: Method for increasing process throughput and performance
Inventor: LIN WEN-SHIUNG
IPC: G01R31/01
Filed: 2001-09-12
Granted: 2003-01-01
Abstract: A method for increasing process throughput and performance is provided in the present invention. In the invention, the testing region is divided into the transmission-terminal testing region and the receiving-terminal testing region, which are disposed on both sides of a delivering belt. An upper separation box is used to tightly mask the circuit board to be tested at the receiving-terminal testing region so as to isolate the external interference. A lower separation box is used to mask and separate the signal emission source, which is connected to one side of the upper separation box by using a cable specified for anti-interference. After the cable is connected to the upper separation box, an attenuator is used to attenuate signals so as to weaken the transmitted signals for simulating the emission source that is located at a long distance away. Through the separation box installed at the receiving-terminal testing region, the integrated circuit to be tested is made capable of conducting both the transmission-terminal test and the receiving-terminal test at the same test production line without having interference. Therefore, the platen of testing apparatus (such as the receiving-terminal, the transmission-terminal) can be placed at sequential operation area.
Patent TW-I289573-B (TW)
Title: Whole aromatic polyester and polyester resin composition
Inventor: YOKOTA TOSHIAKI
IPC: C08G63/60
Filed: 2001-09-14
Granted: 2007-11-11
Abstract: The invention is to obtain a whole aromatic polyester having excellent heat resistance, capable of being produced with a conventional polymerization facility and amenable to melt processing. This whole aromatic polyester exhibits optical anisotropy on melting and comprises as indispensable components constituting units expressed by general formulae (I), (II), (III) and (IV) (where Ar1 is 2,6-naphthalene; Ar2 is one or more kinds selected from 1,2-phenylene, 1,3-phenylene and 1,4-phenylene; Ar3 is at least one kind from 1,3-phenylene, 1,4-phenylene or a residue of a compound having two or more phenylene groups linked at para-positions; and Ar4 is 1,4-phenylene), where the structural unit (I) is 40 to 75 mol%, the structural unit (II) is 8.5 to 30 mol%, the structural unit (III) is 8.5 to 30 mol% and the structural unit (IV) is 0.1 to 8 mol% in the total structural units.
Patent TW-559577-B (TW)
Title: A method of producing steel
Inventor: STREZOV LAZAR
IPC: B21B1/46
Filed: 2001-09-28
Granted: 2003-11-01
Abstract: Steel strips and methods for producing steel strips are provided. In an illustrated embodiment, a method includes continuously casting molten low carbon steel into a strip and hot rolling the cast strip within a temperature range such that the strip passes through the Ar3 transformation temperature from austenite to ferrite under strain during rolling, thereby producing a strip having a yield strength above 400 Mpa and an elongation in excess of 30%. The cast steel strip has desired microstructures.
Patent TW-522521-B (TW)
Title: Semiconductor device having an organic material layer and method for making the same
Inventor: FUKASAWA NORIO
IPC: H01L21/301
Filed: 2001-10-05
Granted: 2003-03-01
Abstract: A semiconductor device includes a semiconductor element (22) having a circuit surface (29) on which a projection electrode (23) is formed, a seal resin (24) which seals the circuit surface of the semiconductor element while exposing at least an end part (23A) of the projection electrode, a connect surface that is to face a board when the semiconductor device is implemented on the board, a back surface (31) which is opposite to the connect surface, a side surface (32) arranged between the connect surface and the back surface, and an organic material layer (40) formed on the side surface.
Patent TW-507311-B (TW)
Title: Capacitance prediction method of deep trench capacitor
Inventor: TSAI TZ-JING
IPC: G01R31/27
Filed: 2001-11-06
Granted: 2002-10-21
Abstract: A kind of capacitance prediction method for deep trench capacitor is disclosed in the present invention. In the invention, many trenches arranged in arrays are formed at the memory cell array region of the substrate. Then, a conformal silicon oxide layer is formed on the substrate surface and is followed by forming a photoresist layer on top of the silicon oxide layer so as to fill the photoresist (PR) into the trenches. After that, the height difference between the PR layer at the memory cell array region and the PR layer at the supporting region is measured. The square-root of the height difference value is in proportion to the capacitance value of the capacitor to be formed in the trench.
Patent TW-522640-B (TW)
Title: High performance CPL double-gate latch
Inventor: BERNSTEIN KERRY
IPC: H01L27/12
Filed: 2002-02-08
Granted: 2003-03-01
Abstract: A differential circuit to be used as a latch-up for asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) devices is provided. Specifically, the differential circuit comprises an asymmetric-DGCMOS device having the weak gates tied to input circuitry and strong gates that are used in cross-coupling.
Patent TW-I271131-B (TW)
Title: Pattern fabrication process of circuit substrate
Inventor: KUNG MONSS
IPC: H05K3/14
Filed: 2002-04-23
Granted: 2007-01-11
Abstract: A pattern fabrication process of circuit substrate, which is applicable to the fabrication of circuit substrate having fine circuits and micro vias. The process includes steps of using at least a stamp whose surface is attached with a thin film suppressing metal nucleation characteristic, first contacting the stamp with the substrate surface to imprint the thin film on the substrate during the step that requires to form a patterned metal layer, and then performing a deposition step of the metal layer such that the metal is selectively deposited on the section not covered by the self-assembled monolayer to directly form the patterned metal layer.
Patent TW-586213-B (TW)
Title: Semiconductor integrated circuit and its manufacturing method
Inventor: TAKAURA NORIKATSU
IPC: H01L21/8238
Filed: 2002-06-07
Granted: 2004-05-01
Abstract: The purpose of the present invention is to improve refresh characteristic of a DRAM memory cell and the driving capability of a MISFET that constitutes a logic circuit. By using p-type polycrystalline silicon, a gate electrode 5g of a memory cell region is formed. The gap insulating film 6 on the gate electrode 5g and a sidewall film 7 on the sidewall of the gate electrode 5g are made of silicon oxide films. By polishing the polysilicon on the gate electrodes 5g and a part between the gate electrodes 5g through the use of a CMP method, contact electrodes 12a, 12b are formed. In addition, a sidewall film composed of a lamination film of a silicon oxide film 7 and a polysilicon film is formed on sidewalls of gate electrodes 8f and 9f of a logic circuit region. By using these films as masks, semiconductor regions 8e and 9e are formed. Consequently, boron punch through can be reduced, and the contact electrodes can be formed in a self-alignment manner. In addition, the driving capability of the MISFET constituting the logic circuit can be improved.
Patent TW-567554-B (TW)
Title: All dual damascene oxide etch process steps in one confined plasma chamber
Inventor: CHEN LAWRENCE
IPC: H01L21/768
Filed: 2002-06-28
Granted: 2003-12-21
Abstract: The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost.
Patent TW-I269520-B (TW)
Title: Apparatus for the high voltage testing of insulated conductors and oscillator circuit for use with same
Inventor: CLINTON HENRY H
IPC: H04B3/46
Filed: 2002-07-19
Granted: 2006-12-21
Abstract: An insulation tester (10) and oscillator circuit for use in same includes a transformer (12) including a primary winding (14) and at least one secondary winding (16, 18, 20) to be coupled across an external load such as an electrode (25). First and second bipolar junction transistors (26, 28) are connected in a ""push-pull"" operating mode and coupled to the primary winding (14) of the transformer (12) for producing a high frequency voltage. The primal winding (14) has two ends (29, 31) each respective one of which is coupled to a respective one of the collectors of the first and second bipolar junction transistors (26, 28). First and second field effect transistors (52, 54) are respectively coupled in parallel with the first and second bipolar junction transistors (26, 28). An actuator for activating the first and second field effect transistors (52, 54) to respectively conduct substantially synchronously with the first and second bipolar junction transistors (26, 28) shortly after start-up is provided, whereby the majority of current is shunted through the field effect transistors (52, 54).
Patent TW-I282201-B (TW)
Title: Power converter
Inventor: NAKATSU KINYA
IPC: H01F27/28
Filed: 2002-08-21
Granted: 2007-06-01
Abstract: A low noise, compact and low cost electric power converter employing a compact common mode transformer, and incorporating a line filter can reduce a leakage current, and can maintain predetermined leakage current reduction effect even if installation condition of the electric power converter or a characteristics of a semiconductor switching element is varied. The electric power converter including a capacitor, a first electrode, a second electrode, a first magnetic body, on which the first electrode and the second electrode are wound to form an LC composite element, connecting electrodes electrically connected to respective of both ends of the first and second electrodes, a second magnetic body for interlinking both ends of the first magnetic body, a coil wound around the second magnetic body in the same winding direction as the first and second electrodes wound around the first magnetic body and a resistor for shorting the output of the coil.