Patent GB-884533-A (GB)
Title: Digital differential analysers
Inventor: CORRIN PETER GILBERT
IPC: G06F7/66
Filed: 1959-03-11
Abstract: 884,533. Digital differential analysers. NATIONAL RESEARCH DEVELOPMENT CORPORATION. March 10, 1960 [March 11, 1959], No. 8367/59. Class 106 (1). In a digital differential analyser including remainder stores the contents of which are always positive or zero and integrand (Y) stores, increments ( #Y) are added to the next-to-least significant places in integrand stores or the least significant digit of the algebraic sum of the increments to be added to the integrand store is added to the next-to-least significant place thereof. The increments are derived from the overflow digits of the remainder stores and the error in neglecting the contents of the remainder store is reduced by adding unity to the least significant place of an integrand store for each remainder store which supplies unmodified overflow digits to the integrand store, and subtracting unity for each remainder store which supplies overflow digits reversed in sign. In this way an approximation to the average content of the remainder store is inserted in the integrand store. The remainder stores are maintained positive or zero by expressing e.g. - (0). 0001000 (= - <SP>1</SP>/ 16 ) as - 1 (overflow) + (0) . 1111000 (= + 15/16). DDA using circulating stores (Fig. 2).-The Y or integrand store includes a delay line 3 of capacity ten bits, two unit delays 5, 6 and an adder 4. The remainder store has two paths having in common ten bit delay 7 and unit delay 8 but one path includes gate 10 and unit delay 9 while the other path includes gate 11, adder 12, unit delay 13 and an inhibiting gate 42. There is also a #Y store of capacity three bits including half adder/subtractor 27, three unit delays 23 to 25 and gate 26. It is assumed that the Y register receives from three other remainder registers overflow digits i.e. the #Z outputs of integrators similar to that being described. These appear on inputs ( #Y1) S  to ( #Y3) S  and ( #Y1) M  to ( #Y3) M . The M input defines the magnitude (1 or 0) of the input, the S input the sign (if marked the digit is negative). The system operates to a cycle of clock pulses P1 to P24; the least significant digit contained in a circulating store emerges from the delay line in the store at P1 and P13, the sign digit at times P12, P24. The correction of the Y store to allow for the average contents of the remainder stores is done by gating the contents of a staticizer 39 to adder 4. The value on the staticizer may range from 01.1 (+ 1 ¢) to 10.1 (- 1 ¢) the first digit being a sign digit. The one shot device 43 opens gates 40 to 42 for one cycle and the gates 44 to 46 are opened by the clock pulses shown to combine the correction and Y terms in adder 4, carry on the most significant digit (P12) being suppressed. #X) M  and, if #x is negative, ( #x) S  pulses are then gated at P13¢ to set triggers 35, 36 producing the signal shown. If #x is zero the gate 10 is open and the remainder circulates in the loop including unit delay 9. If #x is + 1 gates 11 and 16 are opened and Y and the remainder are combined in adder 12 during times P14 to P1. An overflow generated at P1  is gated to trigger 18 but is prevented from circulating in the remainder store by the action of P2 on inhibit gate 48. If #x is - 1 the gates 11 and 16 are opened but additionally notequivalent gates 14 and 22 are operated. This together with the addition of unity at P14 complements the contents of the Y store and these are effectively subtracted from the remainder store in adder 12. If an overflow occurs gate 21 is opened at P1 and trigger 20 set to indicate the sign of the overflow, while trigger 18 indicates its magnitude. The #Y inputs are sampled at times P1, P4 and P7 and the M inputs passed to the circuit 27. If the corresponding S input exists trigger 31 is set to cause circuit 27 to act as a half-subtractor. The #Y inputs are summed during the periods P4 to P12. The first two digits are delayed by unit delay 50 and are then combined with the integrand at P14, P15 i.e. starting with the next-to-least significant digit of the integrand. If the third digit is a one, indicating negative, trigger 53 is set and unity is added to the integrand during times P16 to P14. An embodiment using shift registers as the Y and remainder stores is also described (Figs. 3 and 4, not shown). Specification 717,114 is referred to.