Patent GB-1346669-A (GB)
Title: Memory devices
IPC: H03K19/168
Filed: 1971-11-16
Abstract: 1346669 Magnetic storage arrangements WESTERN ELECTRIC CO Inc 16 Nov 1971 [16 Nov 1970] 53031/71 Heading H3B [Also in Division G4] Data bits are moved through a first channel in a storage medium and are compared by mutual interaction with interrogation bits in a second channel to produce a predetermined output if a mismatch occurs. As described the data bits are represented by magnetic domains in a sheet of material provided with a soft magnetic overlay for controlling the propagation of the domains along predetermined paths, but the use of integrated circuits and semi-conductor charge couple or transfer devices is also mentioned. In one embodiment, domains are recirculated in a loop ML1, Fig. 1, the presence of a domain in a particular time slot indicating that a corresponding telephone line was previously in the off-hook condition. The currently scanned states of the lines are supplied in the appropriate time slots to a pair of domain generators GA, GB associated with registers SL1, SL2. The presence of a mismatch between SL1 and ML1 in any particular position is determined at an interaction region IP2 which is such that an unmatched domain continues to advance to a detector 31 or 32 depending on the change of state which the associated line has undergone. A match in the form of a domain in each of registers SL1, ML1 results in the domains being mutually repelled into paths SL1-2 and ML1-1 respectively, the latter domain then recirculating unchanged in register ML1. Pulses are supplied from a processor 10 to a further domain generator GC in accordance with whether or not the data stored in loop ML1 are to be updated in corresponding time slots. If updating is to be inhibited, a domain is generated in register IL1 and repels any corresponding domain in SL2 into an annihilation device EC, whereas if updating is required, a domain in SL2 is allowed to proceed to interaction region IP4 where a domain is caused to be injected into the loop ML1 along path SL2-2 to replace the absence of a domain in the corresponding time slot in ML1-2. Region IP4 also serves to update loop ML1 in the opposite sense when required and region IP5 serves as a junction for reinserting domains from SL2-2 and ML1-1 into the loop ML1. Further loops ML2-ML n  are loaded with domains to provide sequential parallel output codes identifying the corresponding time slots, all the loops ML being driven in synchronism. In a second embodiment, a register 116, Fig. 13, is loaded with domains which are then transferred in parallel to a register 127. Depending on the state of input lines associated with a further register 126, selected domains are transferred to register 126 from register 127, and then the contents of registers 126 and 127 are transferred to respective registers 115, 116 which therefore have complementary contents. After n shifts of the contents of registers 115, 116 into registers 118, 119, a further set of n inputs is entered in complementary registers 115, 116, and after further shifting, interaction takes place in registers 118, 119 between corresponding data bits in the 2 successively entered sets of bits. A persistent condition on a line results in a domain being repelled into register 1-1 or 0-0 in the corresponding time slot. Such domains are subsequently compared with the next expected state of the line by means of recirculating-registers 123, 124. Detection of a change of state in a given time slot results in an output at 121 or 122 and a change of domains between registers 123, 124 in the corresponding time slots by way of a "compressor" or push through register 125. The arrangement can be used for checking correct transmission of data.