Patent GB-983255-A (GB)
Title: Improvements in or relating to pulse code modulation systems
Inventor: INGRAM DEREK GEORGE WOODWARD
IPC: H04J3/17
Filed: 1962-02-20
Abstract: 983,255. Multiplex pulse code signalling. GENERAL ELECTRIC CO. Ltd. Feb. 19, 1963 [Feb. 20, 1962], No. 6544/62. Heading H4L. In a time division multiplex P.C.M. system in which the number of channels available is less than the number of incoming channels means are provided at the transmitting terminal for testing sequentially the incoming channels to provide coded information for transmission which defines the condition of the channel at that time and at the immediately preceding time at which that channel was examined. In the system described there are seventy-five incoming channels supplying twenty-five time division multiplex channels. Each channel group comprises eight pulse positions, the first pulse being used for signalling and synchronizing and the remaining pulses defining the polarity and magnitude of the signal sample. Transmitting terminal. Fig. 1 shows a line 1 corresponding to one of the seventy-five incoming channels, which is connected via an AND gate 2 to a common line 3 feeding the coder 48, Fig. 2. The line 1 is also connected to a trigger 4 which provides an output on lead 5 when an audio signal is present on line 1 and an output on lead 6 when there is no audio signal, corresponding signals being supplied to control a further trigger 9 with outputs 10, 11. AND gates 12 to 16 and an OR gate 17 also are associated with the channel gate 2, and equipment common to all the channel gates includes a clock pulse line 18, a first selector line 19, a second selector line 20, a register gate line 21, a register set line 22, and a shift register 23 having seventy-five stages and controlled by clock pulses, each stage being associated with a corresponding channel gate. When a signal is present on line 1 operation of gate 2 will cause trigger 4 to energize leads 5 and 7. It is assumed that the previous time line 1 was sampled it carried a signal so that trigger 9 will be supplying a signal over lead 10. Thus when the shift register 23 reaches the position corresponding to line 1, the gate 12, which also receives clock pulses from line 18, will ba open to operate channel gate 2. The signal over lead 5 is supplied via OR gate 17 to the gate 16 which also receives a signal from the register 23 so that the line 21 is energized to operate common equipment which prevents clock pulses from being applied to the register 23 until the operations in connection with line 1 have been completed. Towards the end of the interval allotted to these operations a pulse over line 22 causes gate 15 to reset trigger 9 to match the condition of trigger 4 as represented by the signals on lead 7 or 8. In the present case there will be no change in the condition of trigger 9. At the end of the interval allotted to these operations a pulse is supplied to the shaft register 23. If the trigger 9 is supplying a signal over the lead 19, indicating that a signal was present at the previous sampling time of line 1, but leads 6 and 8 are energized indicating that no signal is on the line 1 at the present sampling time, a signal will be supplied via OR gate 17 and AND gate 16 to stop the supply of clock pulses to the shift register 23 as before. The gate 13 will supply a signal to the line 19 which causes common equipment to transmit a code group of pulses indicating that there is no audio signal on line 1 and also prevents the transmission of pulses from the coder 48 in respect of the zero sample voltage. A pulse over line 22 then sets trigger 9 via gate 15 so that its output 11 supplies a signal, and if at the next time interval appropriate to line 1 an audio signal is present, the gate 16 will stop the shift register as before. The gate 14 will supply a signal to the line 20 to cause common equipment to transmit a code group of pulses indicating that during the next cycle a sample voltage may be expected on line 1, and also preventing operation of the coder 48 since the gate 12 will be inoperative. In Fig. 2 blocks 30, 32 represent apparatus as shown in Fig. 1 connected with incoming lines 1 and 32 respectively, the line 18 being supplied with clock pulses at a repetition frequency of 250 kc/s. from a generator 33. Further clock pulse generators 34, 43, supply pulses at repetition frequencies of 12 mc/s. and 2 mc/s. respectively, and a reset clock pulse generator supplies pulses at a repetition frequency of 250 kc/s. The pulse generator 43 controls a fifteen-stage shift register 38 supplying the coded signals to the output line 39. It is assumed that an audio signal is present on the line 1 and was present at its previous sampling period, no signal is present on any of the second to thirtyfirst channels and a signal is present on line 32 but was not present at its previous sampling period. A sample voltage from line 1 will be supplied to the coder 48 and the resultant code group of pulses will be supplied via transfer gates 47 to the output register 38 the first stage of which will register a "0." As there are no signals on lines 19 or 20 there will be no output from gate 42 so that transfer gates 37 are inoperative. After the sample voltage has been obtained clock pulses from the generator 34 are supplied via INHIBIT gate 35 to the shift register 23 so that the second and subsequent channels are tested. An interval of four microseconds is available for obtaining a sample voltage but only one microsecond is used so that during the remaining interval of three microseconds a maximum of thirty-six clock pulses may be applied to the shaft register 23, so that thirty-six channels may be scanned. In practice this number is restricted to thirtytwo. During these clock pulses no signal, will be supplied by the gate 16 and lead 21 will not be energized so that gate 35 will permit clock pulses to pass to operate the shift register 23 until the thirty-second channel position is reached. At this time the lead 21 will be energized and gate 35 inhibited to stop the operation of the shift register 23. The clock pulses from 34 also operate a counter 36 and this will be stopped at a count of thirty-one indicating that the line 32 is the thirty-first channel after the last active incoming channel. At this time the gate 14 supplies a signal via lead 20 and gates 41 and 42 so that a digit " 1 " is inserted in the ninth stage of output register 38. In addition gate 45 is operated so as to insert a digit " 1 " in the fifteenth stage of the register 38. This provides a code in which the digit " 1 " in the ninth stage (which will appear in the first position in the channel group) indicates that the code group which follows relates to a change of state of a channel from active to inactive or vice versa, the digits in the tenth to the fourtheenth stages indicate how many channels have been sampled since the last channel carrying a signal was sampled, and the digit in the fifteenth stage indicates whether that channel has changed from active to inactive or vice versa. The gate 42 also supplies a pulse via a four microseconds delay circuit 46 to the transfer gates 47, thus blocking signals from the coder. In the ease of inactive channels which were also inactive at the previous sampling time for that channel no channel pulse groups are transmitted. Receiving terminal. Incoming signals over line 78 (Fig. 4) which are assumed to be a group of pulses representing a signal sample on a channel which was also active at the previous sampling time, are supplied to a register 72, the first stage of which will register a " 0." A signal is then supplied to operate gates 74 and transfer the digit pulses to a decoder 75 supplying a corresponding amplitude modulated pulse to the common output line 63. The clock generator 69 supplies pulses at a repetition frequency of 12 mc/s. via INHIBIT gates 70, 71 to a seventyfive stage shift register 58, i.e. one stage for each outgoing line. Each outgoing line is associated with a corresponding trigger 61, AND gates 52, 53, 54 and a channel gate 51, Fig. 3, represented by blocks 65, 66 for channels 50, 67 respectively on Fig. 4. The triggers 61 in one condition supply a signal over lead 62, and when there is no signal on lead 62 the shift register 58 will pass on to the next associated outgoing line. Assuming that the trigger 61 associated with outgoing line 50 is supplying a signal over line 62, a signal will be supplied via gate 53 and line 56 to inhibit the gate 70 and block the supply of clock pulses to the shift register 58. The next clock pulse from generator 68 supplies the amplitude modulated pulse from the decoder 75 via the gate 51 to the outgoing line 50. If the received channel code group indicates that a channel on which audio signals were present in the previous sampling time no longer carries audio signals the first stage of the register 72 will correspond to a digit " 1 " and will prevent operation of the transfer gates 74 supplying the decoder 75, and will also block the supply of clock pulses to the shift register 58 through the gate 71. It will also operate transfer gates 76 so that the condition of the second to the sixth stages of the register 72 are transferred to a counter 73 which then supplies a number of clock pulses, equal to the count registered, to the shift register 58 thus energizing the line 60 associated with the outgoing line in respect of which action is required. The seventh stage of the register 72 will register digit " 0 " signifying that the channel under consideration has become inactive. The first stage of register 72 supplies a signal together with a signal representing digit 0 in stage 7 via gates 77 and 52 to cause trigger 61 to change its condition so that no output appears on lead 62. When the received channel group relates to a channel which carried no input signal at the previous sampling time but carries an input signal at the present sampling time the operation is similar but the first and seventh stages of the register supply signals via the gate 77 to cause the