Patent GB-697920-A (GB)
Title: Improvements in or relating to selective signalling systems employing pulse code modulated carrier signals
IPC: H04Q1/446
Filed: 1951-02-02
Abstract: 697,920. Exchange systems. WESTERN ELECTRIC CO., Inc. Feb. 2, 1951 [April 26, 1950], No. 2643/51. Class 40 (iv). [Also in Group XL (b)] Numbers are signalled between exchanges at a rate of 100 digits per second by means of a two-in-five pulse position code and pulses of 1500 c/s. voice frequency. A preparatory signal (comprising a start pulse and a synchronizing pulse) and the coded digits of a called number are transmitted cyclically until a 1800 c/s. stop signal is returned from the called exchange. The start signal consists of a pulse extending through the five positions of one digit cycle and the first position of the next digit cycle. The synchronizing pulse is transmitted in the fifth position of the second digit cycle. Transmission of the coded digits may start before any equipment is seized at the next exchange. The number may include code and numerical digits and the whole number may be transmitted to several exchanges in succession when building up a long-distance connection. Only part of the number is then used at each exchange and only the terminal exchange returns a stop signal. In the system described, a junction 23 Fig. 1, between a toll exchange, and a local cross-bar exchange is selected manually. A free register-sender circuit 16 is connected to the junction by a link 15. Mechanical registers 17 are set by means of an operator's key-set 10, relays 199, 195, Fig. 4, operate and connect the sender to the junction and circuits 18, 19, 20, controlled by the registers, transmit D.C. pulses to an oscillator modulator circuit 21 which passes voice-frequency pulses to the junction through a control circuit 22. As soon as the registers are set, the voice frequency transmitter, in circuit 21, is connected to the trunk 23, the connection constituting a seize signal at the called exchange where a free register-sender circuit 26 is connected by a link 25. The voice-frequency signals are rectified in a detector circuit 28 and a decoding control circuit 29 detects the start and synchronizing signals and controls the commutator and steering circuits 30, 31 to register the digits in gas discharge tube registers 32. When registration is complete and has been checked, a stop signal is returned by a transmitter 33. The detailed description is confined to the register-sender circuits. The left and right triodes of double triodes are identified by suffixes L, R which are not all marked in the drawings. The conducting and non-conducting states of a triode may be denoted by the signs + and -. Figs. 2 to 11 should be arranged as shown in Fig. 15. Register-sender 16, transmission, Figs. 2, 3, 4; when a priming key 77 is operated, D.C. pulses (lines 4 to 8, Fig. 12) are fed cyclically over five conductors CD1-CD5 which are multipled to the banks of register switches TH, H, T, U. The pulses are generated by means of a coding stepper comprising an oscillator VIL operating at 500 c/s. The sinusoidal output of the oscillator (line 1, Fig. 12) is applied to a triode V1R to provide a square wave (line 2, Fig. 12) which is fed from the diode 42 through a differentiating circuit to the grid of a triode V2L. Sharp pulses from V2L (line 3, Fig. 12) drive a ring of five flip-flops V5-V9. Normally the left and right triodes of four of the tubes are respectively conducting and non-conducting (+ - ). The fifth tube is operated ( - +). A single pulse transfers the marking ( - +) to the next tube. The anodes of V5L to V9L are connected to five cathode followers in tubes V2R, V3, V4, which feed the conductors CD1-CD5. The pulses on CD1-CD5 (lines 4 to 8, Fig. 12) define the five pulse positions of a single digit. When V9 is operated ( - +) once in each cycle, a pulse is transmitted over conductor 108 to the grid of tube V19L which drives a ring of six flip-flops V13-V18, described as a digit stepper, to count the digits. As the digit stepper operates, a positive potential (lines 10 to 15, Fig. 12) is applied cyclically to conductors 160-165 to enable the triodes of tubes V10, V11, V12 to gate, in turn, a start signal and a synchronizing pulse and four digits (line 16, Fig. 12). These tubes have a common cathode resistor 140 and the output is amplified by a cathode follower V19R connected by conductor 150 to the oscillator and modulator circuit 21. During the first cycle of the coding stepper, V13 is operated ( - +) and enables VIOL to conduct. As the anode of V10L is permanently connected to battery, the pulse transmitted lasts until V10R is enabled when V14 operates at the beginning of the next cycle of the coding stepper. As the anode of V10R is permanently connected to conductors 121, CD1 and CD5, regardless of the register setting, the pulse is extended to the first position of the second cycle by a pulse on CD1 and the resultant six pulse-position start signal is followed by a synchronizing pulse in the fifth position. As the digit stepper applies enabling potentials to conductors 162-165 coded digits are gated by V11L, V11R, V12L, V12R in accordance with the settings of the register switches, the first pulse of the thousands digit being transmitted through switch bank TH1 and rectifier 113 and the second pulse through switch bank TH2 and rectifier 112. A ring modulator CM normally blocks the transmission of 1500 c/s. from an oscillator CO but transmits current to the junction under the control of pulses fed through a 500 c/s. low-pass filter 166. The 1800 c/s. stop signal is amplified by tube 181 and is rectified to operate relay 194 and to release 195. Register-sender 26, reception, Figs. 5-11; when a free register sender 26 is seized, relays 5801, 5802, 204, 210 operate and the voicefrequency pulses (line 1, Fig. 13) are amplified and rectified in circuit 28 to provide D.C. pulses of constant amplitude on conductor 245 (line 2, Fig. 13). The output of push-pull pentodes 224, 225 is rectified by a full-wave rectifier 229 and the rectified pulses are amplified by cathode followers in tube 231. The constant pulse amplitude is maintained by means of negative feed-back through an amplifier 237 to the suppressor grids of the pentodes. The pulses on conductor 245 are fed to a decoding control circuit 29, Fig. 7, which controls the operation of a commutator circuit 30 and a digit steering circuit 31 and the setting of four registers RA, RB, RC, RD, Figs. 9, 10, in accordance with the code digits 5731 received. In the decoding control circuit, tube SL squares the pulses from conductor 245 (line 3, Fig. 13) and feeds a cathode follower SCFL. Triode SCFR is not enabled to transmit pulses to triodes SFFL, SSGR until a start pulse is detected by tubes STC, STL, described later, and an enabling potential is applied to the grid of SCFR. Triode SSGR then repeats the pulses to gating tubes 308, 309 in the digit steering circuit and the pulses of the four digits are gated over conductors SA, SB, SC, SD for registration. The synchronizing pulse and the enabling potential from the start pulse detector together fire gas tube 271; tube SFF operates (+ - ) and locks until released by a positive potential on conductor 219. The synchronizing pulse, by operating SFF, starts a timing oscillator OSR which generates a 500 c/s. sinusoidal current (line 5, Fig. 13). The oscillations are squared by triodes SQL, SQR (line 6, Fig. 13) and SSGL inverts the pulses (line 7, Fig. 13). When the timing oscillations start, tube C1 operated ( - +), locks to conductor 219, and prepares tube CPG by biasing CPGR to just below cut-off and by biasing CPGL so that a coincidence between a timing pulse from SQ and a digit counting pulse on conductor 305 is necessary to make the tube conduct. The inverted timing pulses from SSGL are differentiated in a circuit including condenser 297 and are amplified in triode CPGR to produce sharp pulses on conductor 303 (line 8, Fig. 13). These pulses drive a ring of five flip-flops SP1-SP5 which feed timing pulses (lines 9-13, Fig. 13) cyclically to the registers over conductors 1301, 1302-1305. When tube SP5 operates (- +) once in every digit cycle, a pulse (line 14, Fig. 13) is transmitted over conductor 1305 to CPGL which, at coincidences with sharp pulses (line 15, Fig. 13) derived by condenser 290, transmits pulses (line 16, Fig. 13) over conductor 296 to the common cathode conductor of a chain of flip-flops A, B, C, D, CR, which count the digits and enable the triodes of tubes 308, 309 to gate the pulses of the digits from conductor 289 to register conductors SA, SB, SC, SD. Each register comprises a string of five gas discharge tubes A1-A5 which are enabled cyclically by the timing pulses on conductors 1301- 1305. The register conductor SA over which the pulses of the thousands digit are gated is commoned to the control grids of the five discharge tubes and the tubes fire in which coincidences occur between timing pulses and digit pulses. Each of the registers RA, RB, RC, RD is set in turn as digit pulses are gated over conductors SA, SB, SC, SD. Relays AR1-AR5 in the anode circuit of the tubes A1-A5 control a marker 34 for the switches in the cross-bar exchange. The firing of two and only two tubes in each register is checked by means of tubes AC, AGC. When a gating potential is applied to triode 308R and conductor 315 to gate the hundreds digit, triode AGC in the thousands register conducts and provides anode potential for tube AC. Triode ACL is biased by a potentiometer including the cathode resistors of A1-A5 and conducts only if more than two tubes fire. Triode ACR is biased by a potentiometer including anode resistors of A1- A5 and conducts only if less than two tubes fire. If a registration is incorrect, one or more of the tubes AC-DC conducts, a potential is developed across resistor 349, triode RT conducts and relays 215, 216 operate and restore the register sender to normal. As no stop signal has been given the registers are re-set by further pulses. The decoding control circuit is