Patent GB-1194957-A (GB)
Title: Method and Apparatus for Controlling the Gain of Binary Gain-Ranging Amplifiers
IPC: H03G3/20
Filed: 1968-08-29
Abstract: 1,194,957. Automatic gain control. MANDREL INDUSTRIES Inc. 29 Aug., 1968 [30 Aug., 1967], No. 41328/68. Heading H4R. In an automatic gain control, in a system requiring changes in gain of an analogue signal amplifier to be effected in synchronism with system timing pulses, the analogue signal is compared with a threshold value to produce a digital output which is supplied to means which produce synchronous changes in gain. In the seismic prospecting system described the changes in gain are synchronized with a recorder which is adapted to record also the changes in gain. The gain control is effected by controlling an attenuating network disposed in a line of signal amplifiers. The attenuating network includes relay contacts arranged in parallel and arranged to effect loss or gain in ratios of 2-n. A sample of the analogue output signal of the last amplifier in the line is supplied to two comparison devices each of which produce a digital output if the magnitude of the analogue signal (either positive or negative) exceeds a predetermined threshold. One comparison device receives a first lower potential in both positive and negative form at respective comparators each of which receives the analogue signal via an adjustable potentiometer. The output of one comparator is inverted and combined with the output of the other. Thus this comparison device produces an output " U " whenever the level of the analogue signal is outside the range defined by the positive and negative potentials. The other comparison device gives a similar output " D " whenever the level of the analogue signal is outside the range defined by the positive and negative forms of a second higher potential. A logic circuit receives the outputs " U " and " D " from the comparison devices and, in synchronism with timing pulses also received, adjusts the gain until the output " U " is received indicating that the peaks of the analogue signal are of magnitude greater than the level set by the lower potential and less than the level set by the higher potential. The logic circuit comprises an array of NAND gates and two bistables which define four states. The circuit is normally in a first state and in response to a stepping signal received say once every 15th cycle of the recording system timing, the logic is advanced to its second state. If the output " U " is received the logic is switched back to its first state until the next stepping signal is received. If the output " U " is not received before the next stepping signal the logic is advanced by the stepping signal to its third state. If while in the first state the output " D " is received the logic steps to the third state immediately or immediately after the stepping signal (if it exists at that time) ceases. In the third state the logic produces a gain change signal which is fed to a counter, which also receives the stepping signals. If the third state was reached in response to the presence of a " D " output then it does not occur simultaneously with a stepping signal and the counter steps down causing, via relays controlled by its outputs, the gain to be decreased. If the third state was reached in response to the occurrence of two stepping signals without an intervening " B " output then the counter simultaneously receives the gain change signal and the stepping signal and counts up to increase the gain. Thus decreases in gain are effected rapidly in not more than two clock pulse periods while increases in gain occur only after two stepping signals i.e. after 30 cycles of the clock.