Patent GB-1302513-A (GB)
IPC: G06F15/80
Filed: 1970-01-20
Abstract: 1302513 Digital computers BURROUGHS CORP 20 Jan 1970 [5 Feb 1969] 2629/70 Heading G4A An electrical sequencing control unit, for use in a parallel digital data processing system (i.e. having a number of processing units operable in parallel), has algorithmic means for determining the presence of parallelism within and between statements of programmes, a matrix means connectible to receive the output of the algorithmic means and a plurality of vector registers coupled to said matrix to apply executed, initiation, in progress and allowable vectors thereto.  By parallelism within a statement of programme is meant the existence of two or more instructions within that statement which may be executed simultaneously, and by parallelism between statements of programme is meant the condition that two or more of those statements may be executed simultaneously. Parallelism within programmes executed by the system is detected during compilation, before programme execution, by a prior art method which results in a grouping of instructions to be executed at each level of the " tree " (i.e. groups of instructions which may be executed in parallel) in a Boolean matrix. The sequencing unit is stated to control the sequencing of these partially ordered instructions. The system (Fig. 1, not shown).-This comprises a plurality of 3-address processing units, a plurality of sequencing units, a resource manager controlling the allocation thereof, high speed storage, random access memories and a memory manager. Also provided are secondary memory input/output devices such as tapes, printers, punches and sorters. The sequencing unit (Fig. 3).-An instruction number from the resource manager enters a register 3-10, is decoded, and sent to an executed (E) register 3-14 and to an in progress (IP) register 3-16. The information in the E register is used to search an IZT flip-flop matrix 3-18 which contains information which is a composite (logical union) of the intersection relation (IT) which indicates the potential data paths from one instruction to the next and the given essential order relationship (ZT) which indicates the conditions of precedence which must be observed between any two instructions. The search result goes to line 3-20 and an initiate (I) register 3-22 receives signals indicating that the instructions are allowable (A), are " not " already executed (E), and are " not " in progress (IP). The contents of the I register go to Instruction Selector Register 3-24 and certain bits of registers 3-22 and 3-16 are set. Operation.-For an operation of n instructions the IZT matrix is n x n and there are the four vector registers, E, IP, A and I. When a programme segment is to be executed, the resource manager chooses a sequencing unit and a set of instructions is sent thereto with sequencing information for use by the 1ZT matrix which causes all the registers to be set to zero. When a processing unit has completed an instruction the result (together with its instruction number) is sent to the sequencing unit where it is decoded and the appropriate bit set in the E and 1P registers. Simultaneously, the 1ZT matrix is searched for an instruction which is allowable as all its predecessors have been executed, which allowable instruction is sent to A. The I register is set the associated operator and two operands are sent to the resource manager and the appropriate registers reset. If there is more than one allowable instruction they are queued in the resource manager. The sequencing unit initiates the fetching and storing of operands through the memory manager which includes an associative memory. This procedure continues until the segment is completed when another segment is fetched by a special instruction.