Patent GB-865691-A (GB)
Title: Digital computer control
IPC: G06F15/00
Filed: 1958-10-20
Abstract: 865,691. Digital electrical calculating apparatus. SPERRY RAND CORPORATION. Oct. 20, 1958 [Nov. 20, 1957], No. 33414/58. Class 106 (1). An instruction word may be either variable or invariable, if invariable, processing means performs operations which are predetermined by the word, if variable, then an operator may either directly or indirectly vary the interpretation of the instruction, as described by means of a plugboard. The general arrangement of the computor described is shown in Fig. 6. An instruction word (IW) comprises eleven decimal digits translated into the excess-3 binary code of which the first two (OP) define whether the word is variable or invariable and the remainder comprise three three-digit addresses U, V, W. An IW from general storage 146 is sent to a holding register 56, thence to a decoder 48, then, if variable to plugboard 52, if invariable directly to the command timing circuits 60. The arithmetic unit (not described in detail) has four storage registers A to D. Also provided are memory address register (MAR) circuits 144, a programme address counter (PAK) 150 and an information transfer counter 154 which during a transfer counts the binary digits of an IW and then sends a resume signal to a clock. The clock (Fig. 5, not shown) provides synchronizing pulses and determines a six-period cycle by means of pulses P-0 to P-5, each period being initiated by a resume signal from, e.g., the information transfer counter or the arithmetic register. On such initiation a pulse TP is emitted by the clock. Any period may be suppressed although TP still issues. The holding register 56 (Fig. 7B) comprises two registers HR-1, HR-2, which may be sections of a magnetic drum, to which input is controlled by a flip-flop 188, the outputs of which are each connected to an input gate of one register and an output gate of the other. A write enable signal is applied to gates 180, 184 and the information, usually an IW, is written from line 152. A read enable signal appears on line 196 and the output is gated either to the decoder or directly to the arithmetic unit on line 468. Reading and writing may thus take place simultaneously. The decoder 48 (Fig. 8A) comprises an IW flip-flop register 220 divided into four sections for the OP, U, V and W parts of an IW. An OP translator 230 emits a D.C. signal on a selected line of a selected channel determined by OP. Additionally if OP contains a binary " 1 " a signal appears on line 236. This is gated (Fig. 7B) by TP-5, the pulse emitted by the clock at the beginning of the fifth period of a cycle to flip-flop 188, switching the holding register. Channel 64 from the OP translator 230 is associated with an invariable instruction, OP being a number in the range 1 to 49, and a particular line of the channel is associated with a specified operation, e.g. multiply, has an OP 43 which causes a signal to issue on line 258, add has an OP 14, the signal issuing on line 256. A variable instruction has an OP in the range 51 to 99 and is signalled on channel 62. Invariable instruction execution. (a) Period 0. Transfer contents of holding register to decoder. This requires an output from AND unit 210 since the output of this unit is fed to AND unit 200 gating the output of the holding register to the decoder, and to line 196 via OR circuit 204 and line 206 providing a read enable signal. The output is provided by flipflop 214 being set to " 1," by a signal appearing on line 212 and pulse P-0 all being fed to AND unit 210. Signal on line 212 will be described later. At the conclusion of the transfer, the information transfer counter emits a resume pulse to the clock which initiates period 1. (b) Period 1. Transfer 1st address to memory address register. The address is assumed to be section U of the IW now in the decoder. By the beginning of period 1 the OP translator 230 has established a signal in channel 64 which is gated by P-1 to line 268 of channel 74 and so to AND unit 288 which when fully enabled passes sync pulses to the address transfer counter which has been set by pulse TP-1 through OR circuit 292. Thus one of the counter stages will contain a binary " 1 " and since each of the " 0 " output lines from the counter is connected to an OR-NOT circuit 296, AND unit 288 is fully enabled by the OR-NOT circuit to pass sync pulses to the address sections of the IW register to cause circular shift of the addresses. Thus the address U is gated through AND unit 274 by the signal on line 268 to memory address register 306 via OR unit 302 and line 304. (c) Period 1. Transfer contents of 1st address to register A (in arithmetic unit 148). The two least significant binary digits of an address determine, if both zero, that a general storage reference is to be made, otherwise reference is to, e.g., the arithmetic registers A to D or the holding register 56. The memory address register is a flip-flop register and the " 1 " output of the two least significant stages is connected to an OR-NOT unit 312 which provides, if the last two bits are zero, a partial enable to AND unit 316. Other signals from detector 328 of coincidence between the memory address register and angular index counter 326 associated with a general storage magnetic drum, and from flip-flop 320 set at " 1 " by a signal on line 322 from the address transfer counter fully enable AND unit 316. Read or write is determined by memory address register translator 338 which for read, as not, issues a signal on line 340 to AND unit 286, which when enabled by other signals on line 284 from OR unit 278 and the " 1 " output of flip-flop 330 gates an operand from general storage to register A of arithmetic unit 148. (d) Period 2. Transfer 2nd address to memory address register. This is similar to the operation described, in (b), save that pulse P-2 is applied to AND unit 348 and a gating signal is sent to AND unit 358 so that the contents of the V-section of IW-register are shifted to the memory address register. (e) Period 2. Transfer contents of second address to arithmetic register B. This is essentially the same as (c). (f) Period 3. Perform operation. As examples addition and multiplication are shown. If the contents of registers A and B are to be added the OP section of the IW is 14, if to be multiplied together, 43. If OP is 14 a signal from decoder 48 (Fig. 7B) issues on line 256, thence through OR circuit 366 to AND unit 368 where it is gated by pulse P-3 to provide an addition enable signal in the arithmetic unit. The sum is stored in register D. If OP is 43 line 258 and AND unit 376 is used to provide a multiplication enable signal. The product is stored in registers C and D, the least significant half in the latter. (g) Period 4. Transfer third address to memory address register. This is similar to (b) and (d) save that the signal on channel 72 is gated through AND unit 380 to line 382. The result is that the W-section of the IW is transferred to memory address register, while a signal is sent through OR circuit 392 to line 398. (h) Period 4. Transfer result of operation to memory (general storage 308). Translation of the address W results in a signal on translator output line 394 partially enabling AND unit 396. Other enables are on lines 398, from OR circuit 392, and 334. Circular shift of one of the arithmetic registers over line 400 to AND unit 396 is started when flip-flop 330 is set to " 1," the output being applied to AND unit 434 through OR circuit 432. When the period is not period 0, a signal appears on line 436 and AND unit 434 is fully enabled. Thus sync pulses are gated through AND unit 444 by means of the signal from AND unit 434 and the signal from OR-NOT circuit 446 connected to the " 0 " lines from information transfer counter 154. This has been set by an end pulse on line 448 from the address transfer counter 290 to a number equalling the largest number of binary digits in any information to be transferred. Thus while a binary digit is being transferred no output appears on at least one " 0 " line in the information transfer counter and a signal issues from OR-NOT circuit 446. (i) Period 5. Switch.holding register. While the OP section of register 220 contains a binary " 1 " a signal is on line 236 and this is gated by TP-5 to switch the holding register as described above. (j) Period 5. Transfer contents of programme address counter to memory address register. The signal on line 236 is also gated by P-5 through AND unit 406 to line 408 and appears as input 408a to OR circuit 278, causing a partial enablement of AND unit 288. Since address transfer counter is set by pulse TP-5 applied to OR circuit 292, the OR-NOT circuit 296 provides the complete enablement and sync pulses are gated to programme address counter 414. Line 408b feeds OR circuit 410 and gates the contents of the programme address counter through AND unit 418 to memory address register. (k) Period 5. Increment programme address counter. At the end of the transfer the end pulse from address transfer counter 290 is gated through AND unit 422 and line 424 to the programme address counter which is incremented one decimal digit. The programme address counter represents a three-digit decimal number with two binary zeros added and thus always refers to general storage. (1) Period 5. Transfer new IW to holding register. After (i) above, a signal appears at output " 1 " of flip-flop 360. This partially enables AND unit 426 to gate an IW from general storage to input line 152 of the holding register, full enablement being provided by pulse P-5. Above has been described the normal cycle followed by the system when an invariable IW is entered-into the holding register. However, alternative operations depending on the addresses contained in the IW may be performed by an invariable instruction e.g. during periods 1 or 2 the contents of the holding register may be transferred to the arithmetic unit by utilizing the " 0 " output of