Patent GB-1425985-A (GB)
Title: Arrangements including semiconductor memory devices
IPC: H01L29/788
Filed: 1973-06-08
Abstract: 1425985 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 8 June 1973 [13 June 1972] 27394/73 Heading H1K In the "write" operation of a semi-conductor memory device in which charges to be stored are injected into an insulating layer from a depletion zone formed temporarily in a semi-conductor body underlying the insulating layer, the voltage drop applied across the depletion zone is less than that at which avalanche breakdown would occur but is more than sufficient to enable carriers injected into the depletion zone to cross into the insulating layer, there being a voltage applied to a gate electrode located over the insulating layer so as to exert upon the carriers in the depletion zone a force tending to move then towards the insulating layer. The depletion zone may be associated with a PN junction terminating under the insulating layer and/or with the insulation/semi-conductor interface itself (as in a depletion-mode IGFET). Carriers to be stored may be injected into the temporary depletion zone from a further PN junction which is temporarily forward-biased or as a result of incident radiation which generates electron-hole pairs. Storage may occur at traps within the insulating layer itself (which is preferably of silicon oxide), at an interface between two superposed insulating layers (e.g. silicon nitride-on-silicon oxide) or on a floating conductive layer (e.g. of doped polycrystalline Si) embedded within the insulating layer. Non- destructive read-out is based upon the effect of the stored charges on the characteristics of the device, and erasure may be effected by irradiation with X-rays or U.V. light, by reverse biasing the junction beneath the insulating layer to the point of avalanche breakdown so that holes (or electrons) are injected into the insulating layer to recombine with the stored electrons (or holes), or by increasing the voltage across the insulating layer, which in this case has been formed of a material having a non- linear resistance/voltage characteristic, to such an extent that it conducts sufficiently to allow the stored charges to drain away. Fig. 2 shows a Si IGFET embodiment in which the depletion zone 17 forms temporarily around N-type source and drain regions 7, 8 and under the gate insulation 5, which encloses a floating polycrystalline Si conductor 12 and carries an Al gate electrode 6. Charge injection to the depletion zone 17 is from a temporarily forward-biased PN junction 9 between an N- type substrate 4 and a P-type epitaxial layer 3 thereon. The stored charges influence the threshold voltage of the device, possibly to such an extent that a depletion-mode device is converted to the enhancement mode, or vice versa. Fig. 7 (not shown) illustrates a further IGFET embodiment in which the depletion zone from which charges are injected to the insulating layer (45) is formed at the insulation/channel interface. In Fig. 6 the storage device is a bipolar transistor having a gate electrode 29 over the emitter-base junction 30. Charge storage is obtained by a temporary reversal of the polarities of the voltages across the emitterbase and base-collector junctions 30, 31 so that charges are injected from the latter into the former and thence, under the influence of a voltage on gate electrode 29, into the insulating layer 25 for storage.