Patent GB-1172494-A (GB)
Title: Improvements in and relating to digital computer systems
IPC: G06F13/10
Filed: 1968-03-27
Abstract: 1,172,494. Computer systems; input-output control. BURROUGHS CORP. 27 March, 1968 [27 March, 1967], No. 14696/68. Heading G4A. In a digital computer system having a main memory with a plurality of input-output channels, any one of a plurality of data lines from remote stations may be connected to a particular one of the channels by a multi-line control means which also addresses a section of an address memory storing an address word for each data line. As shown (Fig. 1), access to a main memory 11 is time shared by a central control unit 12 between a processor 10 and a plurality of peripheral units 13, 18, 61. The processor 10 and a plurality of peripheral units 13, 18 are each connected to the unit 12 by a respective single input-output channel 39, 40; 16, 17; 21, 22 whereas a plurality of other peripheral units 61, which may for example be remote terminals, are all connected by a further single input-output data channel 26, 27, a channel 24, 25 being provided for transmission of commands only to the unit 23. Each of units 13, 18 and the plurality of units 61 has an input-output control 15, 19 and 23 respectively. In operation, whenever a memory access request is granted by central control unit 12, an address from an address memory 46 is transferred to an address register 29, two 4-bit digits of information are transferred between the memory 11 and the requesting unit by way of a register 31 and the address in register 29 is incremented by two and transferred back into the address memory 46. All words are assembled and transmitted 2 digits at a time. A next-instruction-address counter 41 communicates with the register 29. The memory 46 may comprise a number of integrated transistor storage cards. Each of the single peripheral units 13, 18 and the processor 10 has an individual address storage location in a section A of the memory 46. The plurality of units 61 share a common location in section A but each have individual locations in section B addressable only by the multi-line control unit 23. When during execution of a programme, an " initiate inputoutput " command concerning one of the units 61 is decoded by the processor control circuitry 36, the address part of the actual command is passed to the said common location in section A of memory 46 and the function part (defining amongst other things the direction of data transfers and which one of the units 61 is concerned) is transferred two digits at a time to the multi-line input-output control unit 23. Control 23 then causes the address part to be transferred to the location in section B corresponding to the particular peripheral unit 61 concerned, inserts a descriptor word into memory 11 indicating that a data transfer command is in progress and controls the transfer of data between the unit 61 and the memory 11 without further processor interruption, transfers between the memory 11 and the control unit 23 taking place 2-digits at a time as described above. Simultaneous transfers on a time-sharing basis between different peripheral units 61 and the memory 11 may take place. The multi-line control unit 23 (Fig. 4), includes a memory 77 (which may be constructionally similar to memory 46) with a word storage location for each of the units 61, control circuitry 71 for executing the required commands and command receiving registers 62, 63, 65, a scanner 67 for scanning the lines 28 and the corresponding word storage locations in turn. Serial information on the lines 28 is assembled into characters (pairs of digits) in a register 78 associated with the memory 77 before being transmitted to the memory 11. As each line is scanned, so the corresponding word containing the command code and partially assembled data is transferred to the memory register 78. Data transmission in the opposite direction is similar. Completion of a data transfer command is indicated by unit 23 inserting a result descriptor word into memory 11. The units 61 may be of different types, adapters 58 providing a standard interface with the unit 23.