Patent GB-1392599-A (GB)
Title: Semiconductor memory elements
IPC: H01L27/088
Filed: 1971-07-28
Abstract: 1392599 Semiconductor memory elements MULLARD Ltd 30 June 1972 [28 July 1971] 35400/71 Heading H1K The two possible memory states of a semiconductor memory element are determined by the injection of dot electrons or hot holes from respective device portions of a semiconductor substrate 1 through an insulating layer 5 and on to a conductive charge storage layer 4, which may be metal or highly conductive Si. Non- destructive read-out is then preferably effected by employing the storage layer 4 as the gate of an enhancement mode IGFET T 1 , and in the configuration shown the transmission or otherwise to an electrode 8 on drain region 6 of a negative pulse applied to electrode 9 on source region 7 via an accessing IGFET (not shown) indicates the charge state of the layer 4 and hence the memory state of the element. In the embodiment illustrated the enhancement mode IGFET T 1  is also used in the "write 0" operation of the element, the application of a large negative pulse to the source region 7 via the above-mentioned accessing IGFET causing avalanche breakdown of the source-channel junction. When the insulation 5 comprises silica thermally grown in dry oxygen a lower barrier is presented thereby to the hot electrons generated in the breakdown process than to the hot holes, and the hot electrons consequently selectively tunnel through the layer 5 to reach the storage layer 4. The "write 1" operation employs a depletion mode IGFET T 2  having common source region 6 and floating gate 4 with the IGFET T 1 . The IGFET T 2  has a shallow boron-inplanted channel 12 between the borondiffused or inplanted source and drain regions 6, 10. Hot hole injection through the layer 5 into a portion of the storage layer 4 overlapping the drain region 10 is effected by the application of a negative pulse to electrode 11 via a second accessing IGFET (not shown). A large hole current consequently flows through the channel 12 and hot holes are injected through layer 5 to the storage layer 4. This injection may be facilitated by making the pertinent part of the layer 5 of silicon nitride or of nitride-on-silica. A preferrred method for manufacturing the illustrated structure described with reference to Figs. 4-6 (not shown) includes the step of defining the locations of windows in a masking layer for the two regions 6, 7 by under#tching a silicon nitride layer beneath a silica layer. Various other devices for generating the hot carriers to be injected through the insulating layer 5 are described. An IGFET in which the source and drain regions are replaced by Schottky barrier contacts is one possibility, and another is an "inverted" bipolar transistor having its collector at the surface and its emitter region within the semiconductor body. In this case the collector may comprise a Schottky barrier contact or a thin implanted semiconductor layer having spaced higher conductivity collector contact regions thereon. The base region may include highly conductive zones positioned directly beneath the collector contact regions at the emitter-base junction, and a thin relatively highly conductive layer of the base layer may be situated adjacent the basecollector junction.