Patent GB-935174-A (GB)
Title: Improvements in or relating to diversity receiving systems
Inventor: PAINTER PETER LOUIS
IPC: H04B7/08
Filed: 1961-06-23
Abstract: 935,174. Electric analogue calculating. MARCONI'S WIRELESS TELEGRAPH CO. Ltd. April 25, 1962 [June 23, 1961], No. 22825/61. Class 37. [Also in Group XL (c)] In a diversity reception system for frequency modulated signals means are provided for deriving control signals from the incoming signals before amplitude limiting and demodulation, whereby the amplitudes of the respective demodulated signals are controlled to be at least approximately in the ratio of the squares of the input signals before demodulation, and means are provided for combining the amplitude controlled demodulated signals. Space, frequency or polarization diversity may be used. As shown in Fig. 1, diversity signals are supplied to respective mixers 2, 2<SP>1</SP> co-operating with a common local oscillator 3 and I.F. signals are supplied via respective amplifiers 4, 4<SP>1</SP> and limiters 5, 5<SP>1</SP> to discriminators 6, 6<SP>1</SP>, the demodulated signals being supplied via controlled amplifiers 9, 9<SP>1</SP> to a combining circuit R1, R2. I.F. signals are also supplied to a unit 7 which produces an output signal proportional to the difference of the logarithms of the amplitudes of the two I.F. signals and this signal is applied to a differential amplifier 8 which provides two output signals having values in the ratio of the squares of the two I.F. signals supplied to unit 7. These potentials are supplied as signals to control the gain of respective amplifier 9, 9<SP>1</SP> so that their respective outputs are in the ratio of the squares of the amplitudes of the I.F. signals, this being the optimum method of combining diversity signals. Fig. 2 shows the circuits 7, 8, 9, 9<SP>1</SP> for a frequency shift telegraphy system. I.F. signals from one channel are supplied via transformer TR1 to the base of transistor T1 whose output signal is supplied via a transformer TR3 to a diode MR1 so that negative-going I.F. signals are supplied to the base of a PNP transistor T5. These negative going signals are also smoothed by a circuit C13, R7, C17, and operate a meter M indicating signal level. The output of transformer TR3 is supplied via diode MR2 and circuit C14, RV1 to the base of PNP transistor T2 which is connected in known manner to control the emitter current of transistor T1 and provide A.G.C., the arrangement being such that the output signals from the anode of diode MR1 are logarithmically related to the input signals to transistor T1. A small positive bias on the anode of MR1 assists in providing this relationship. The other channel signal is supplied via a transformer TR2 to a similar circuit excepting that diode MR3 is oppositely connected to MR1, is biased from the negative line, and supplies positive going I.F. signals to the base of NPN transistor T6. Output signals from the collectors of transistors T5, T6 are combined so that the signal at the junction of resistors R19, R20 represents the difference of the logarithms of the amplitudes of the two input I.F. signals. Diodes MRS, MR6 and the associated resistance network act as clamps to prevent overdriving of succeeding stages. The difference signal is applied to differential amplifier T7, T11 having a common emitter load consisting of transistor T8, a potentiometer RV3 and resistors R22, R31 being adjusted so that the collector potential of transistors T7, T 11 is midway between that of the negative supply terminal (e.g. -10 volts) and earth, i.e. at - 5 volts. The difference signal is also supplied to a similar differential amplifier T9, T12, T10, but using NPN transistors instead of PNP, the collector potentials of transistors T9, T12 being set at +5 volts. Thus the application of an input signal causes the collector potentials of T7 and T11 and of T9 and T12 to change in opposite directions by equal amounts and the characteristic of the differential amplifiers is so chosen that the collector potentials of each amplifier are in the ratio of the squares of the amplitudes of the I.F. signals applied to transformers TR1, TR2. For example if the signal applied at TR 1 is twice the amplitude of that at TR2 the signal at the junction of R19, R20 will be positive and the collector potentials of transistors T7, T11 will be - 8 and - 2 volts respectively and of transistors T9, T12 will be +2 and +8 volts respectively. The collector outputs of transistors T7 and T11, are supplied to PNP transistors T13, T15 respectively and the collector outputs of transistors T9, T12 are supplied to NPN transistors T16, T14 respectively. The emitter outputs of transistors T13, T14 (- 8 and +8 volts) are supplied as amplitude limiting potentials to a balanced peak limiter comprising PNP transistor T17 and NPN transistor T18, and demodulated signals derived from the I.F. signal supplied to transformer TR1 are applied to the bases of transistors T17, T18. Similarly, the emitter output of transistors T15, T16 (- 2 and + 2 volts) are applied as amplitude limiting potentials to a limiter comprising PNP transistor T19 and NPN transistor T20, the bases of these transistors being supplied with demodulated signals derived from the other I.F. channel. The limiters are arranged so that in the absence of input signals on their bases the transistors are on the point of conduction so that, in the example given, when the input signal is positive-going the collector of T17 remains at - 8 volts while that of T18 reduces to zero potential. Conversely, when the input signals are negative going, the collector of T17 is at zero potential and that of T18 is at +8 volts. Similarly, the collectors of T19 varies between zero and - 2 volts and that of T20 between zero and +2 volts. The output of limiter T17, T18 is connected across a resistance network from whose centre point signals having peaks of Œ4 volts are taken and the output signal from limiter T19, T20 is similarly connected to provide an output signal having an amplitude of Œ1 volt. The two output signals which are in the ratio of the squares of the amplitudes of the corresponding I.F. signals are combined in resistors R49, R50 and the output taken from the junction of the resistors.