Patent GB-1323631-A (GB)
Title: Semiconductor memory device
IPC: H01L27/00
Filed: 1971-07-14
Abstract: 1323631 Data storage NATIONAL CASH REGISTER CO 14 July 1971 [3 Aug 1970] 33045/71 Heading G4C [Also in Division H3] A data storage element comprises a semiconductor body of a first type material provided with two regions of a second type material, an insulator covering an area of the body between the two regions, a control electrode provided on the insulator, and an electron beam source, the arrangement being that the threshold potential required at the control electrode to induce a conductive path between the two regions is variable between two values and the beam is directed at one of the two regions while the control electrode is supplied with a potential intermediate the two threshold values. Storage cells.-Each storage element consists of a field effect transistor formed on an integrated circuit array. The gate voltage (threshold) required for conduction may be varied by the selective application to the gate of an electron beam of variable intensity. Read out of the stored data is made, by means of the electron beam which is directed at the transistor drain, the gate potential being held at a value intermediate the threshold level of the two binary states to be stored. Memory arrangement.-A memory is arranged as a matrix array of "pages" 100, each page being a matrix array of storage elements. To address the memory the electron beam is initially directed at an area 78 on the target. The beam is then scanned along the X direction so as to sequentially cross the fingers 82 each of which is connected to an output pad 88 which, in turn, is connected to the logic circuit which contains a counter. The beam can thus be counted along to the desired page. A similar procedure is adopted in the Y direction and the beam is eventually directed at a receiving area 102 in the upper right hand corner of the required page (see Fig. 9). Each page has a number of horizontal biasing strips 106 connected to a common vertical strip 98 and each having fingers 108, 110 extending vertically, and at the right hand side a vertical indexing strip 114 from which several horizontal indexing strips 116 extend. Each strip has several indexing fingers 120 extending from both its sides. Each finger is connected to an associated MOS field effect storage transistor. Each row of a page contains 135 memory elements of which 128 are used for storage, the remaining 7 being available in case certain ones of the memory elements become defective. The fingers associated with defective or unused elements are disconnected from strip 106 so that only operative elements are counted. From its position on the landing area 102 the beam is scanned downwardly across the strips 116 which are counted in the logic circuit which is connected to pad 92 until the required row is reached. The beam is scanned from right to left crossing the fingers 120 which are counted in the logic circuit and is then positioned for writing or reading, i.e. to strike the gate and drain electrodes of the transistors respectively. When 128 fingers have been counted the beam is then scanned left to right to perform the required read or write operation. A disconnected finger is shown at point 132 and it is clear that disconnected fingers will not be counted. Logic circuit.- The logic circuit comprises a buffer 134 which receives commands (i.e. read or write instructions) address data, and storage data. During the X scan performed during page addressing the fingers 82 are scanned and pulses appear on line 54. These pulses are applied to a monostable circuit 148 the time constant of which is adjusted to a time less than that required to scan two fingers 120 but greater than that required to scan between a finger 120 and the gate 112 or drain 124 regions of the associated transistor. The pulses are counted by counter 150 the output of which is connected to a comparator 152. When the count reaches the required address stored in register 154 the counter is reset and controller 136 informed that the correct page is located. Similar procedures are adopted when addressing within a page. When a row within a page has been addressed and a write operation is required each pulse from monostable 148 is applied to AND gate 166 and delay 168. On the occurrence of each pulse applied to register 140 a signal corresponding to the bit to be written is applied to beam modulator 170, the delay 168 being adjusted to take account of the time required for the beam to scan from a finger 120 to the associated gate electrode. For a read operation the sequence is similar except that the beam is applied to the transistor drains. The clocking and data pulses are supplied to line 54, monostable 148 and to AND gate 172, the other input of which is connected to the monostable output. Since the output of the monostable persists for a time less than that required for the beam to scan two fingers 120 only the data pulses will appear at the output of gate 172 from where they are passed to the buffer 134. The signals from multivibrator 148 are applied to counter 150, which when it reaches a count of 128, informs the controller 136 that the whole row has been accessed.