Patent GB-764523-A (GB)
Title: Improvements in or relating to electronic computers
IPC: G06F9/02
Filed: 1953-07-02
Abstract: 764,523. Digital electric calculating apparatus. COMPAGNIE DES MACHINES BULL. July 2, 1953 [July 2, 1952; July 2, 1952; Aug. 7, 1952; Oct. 23, 1952; Dec. 8, 1952; Jan. 7, 1953], No. 18335/53. Class 106 (1). An electronic cyclically operatiiig computer comprises a programme board having rows of elements emitting pulse trains representing various programme instructions for transmission through a selecting device to order transmitters which receive and re-transmit the instructions in sequence to control the operations of a plurality of circulating memories storing numbers in coded-decimal form, one of these memories including a serial arithmetic unit. The apparatus is similar to that described in Specification 764,522, which is concerned mainly with the positioning of numbers in the circulating memories. Fig. 56 shows the general arrangement of the computer with circulating serial memories S1 ... S4 and a similar memory MO provided with an addersubtractor. CC and CG are comparing devices of a "sequence unit which controls the operations of a number of pulse generators Gz, Gp, Gl, G1, G2 and G3, described as " phase selectors." There is an auxiliary memory MD and a counter-discounter CD. AC represents the accumulator of a tabulating machine with which the computer is associated, M the record card analysing device and AP the printing apparatus of the tabulator. The programme to be performed may comprise up to 64 stages or instructions, and these are set up by plugconnections between a row of sixteen plug sockets 0 to 15 to which coded signals equivalent to. the values of the sockets are periodically supplied, and four rows of 64 double plug sockets AD, TO, OF, OD, each column of which represents a programme instruction. Each instruction comprises four " orders " (represented by a number not greater than 15 in each case) as follows :- AD=Address to which, or from which, a number is to be transferred. OD=Beginning order. This defines the time position in a memory of the units order of the number stored. OF=End order. This defines the time position in the memory of the highest order of. the number. TO=Type of operation to be performed, e.g.:- Referred to No. Type of operation by code: : 5 " Transfer amount standing in tabulating machine accumulator AC to the address specified." IS 6 Transfer amount from storage address specified to memory MO." BO 9 " Compare amount standing in MO with amount in the storage address specified." CN 11 " Subtract amount in the storage address specified from the amount in MO." SN The sequence of the instructions is controlled by a " Line number memory " NL which steps on after each instruction has been obeyed, controlling line-selection pyramids LSP which direct the pre-arranged instructions in succession to " order transmitters " AD, TO, OF and OD. All the memory devices are of the closed loop circuit type comprising one or more electromagnetic delay elements and pulse reshapers. The pulse circulation time of each of the numerical memories covers twelve decimal digit periods, each decimal digit period being divided into four binary periods so as to provide for binary-coded decimal representation. The duration of a binary period is referred to as " a " so that the cycle of a numerical memory amounts to 48a. When a number is read out from a storage memory to the tabulating machine a " Zero Coder " ZC inserts pulses of values " 2 " and " 8 " into those positions in the pulse train representing digit zero to distinguish these digits from the blank spaces to the left of the highest significant digit. More than one amount can be stored in a single memory loop. Order transmitters. Fig. 3 shows some of the connections between pulse generators 1 to 4 an some of the sixteen plug sockets 5 to 15, one of which is shown plugged to the first instruction socket associated with the " type of operation " transmitter TO. The rectangle 19 represents one of the four line-selection pyramids, and the four memory loops M1 to M4 constitute the storage of the order transmitter TO. When the first line is selected by the pyramid 19 a pattern of pulses passes through plug point 16 representing the number of the socket to which the point has been connected and these pulses are passed via gates 27 to 30 to corresponding memory loops M1 to M4. The stored order controls the performance of the first instruction in co-operation with the AD order, which is stored in a similar manner, and the orders OD and OF which are handled somewhat differently, being stored in serial form, each in a single memory loop 75, Fig. 5, of capacity a4. The line-selection pyramid 78 connects the plug socket 77 under consideration to the input circuits of the memory loop and, under control of four gates 81 to 84, &c., the four binary elements of the order are passed into the storage loop from which they exercise the appropriate control during performance of the instruction. Comparators CC and CG are similar in construction to the comparing device described in Specification 740,756. They control the production of various pulse trains for carrying out programme instructions in accordance with the table of Fig. 25 (not shown). Counter - discounter. This comprises two memory loops 54, 55, Fig. 6, of capacity 4a and a1 respectively. Under the control of pulse trains Tp and Tl, which limit the number of pulses applied at a time, a pulse I<SP>1</SP>4 is applied to a regenerator 57 (all such regenerators a1 cause a delay of 0.25a) at intervals of one decimal period. The first pulse passes through a gate 59 and enters the loop 54 to represent a count of " one." It completes the circuit of the loop in time to block ,the entry of the second pulse into the loop at the gate 59, but this second pulse enters the loop 55 and, after passing the regenerator 57 a second time, enters the loop 54 in the second position to represent the count "two." The third pulse is entered directly into the first place in the loop 54 so that two pulses circulate in that loop to represent in binary code a count of " three." The fourth pulse is blocked at its first application to the gate 59 by the arrival of the lowest-order pulse circulating in loop 54, and after one circulation in loop 55 is blocked again at the gate 59 by the second circulating pulse. These actions clear both pulses from the loop 54 and when the pulse circulating in the loop 55 is applied for the third time to the gate 59 it is passed into the loop 54 at a time-position representing a count of " four." Counting proceeds in a similar manner to the maximum capacity of the loop 54 (i.e. 15). The device can be conditioned to operate subtractively. Line-number memory and line-selection pyramids. The line-member memory comprises a chain of one-binary-digit delay loops 86 to 91, Fig. 6, having gates therein controlled by pulse trains Tl and Tl. In one condition of these gates the contents of the loops are blocked against circulation in the loops and, instead, a pulse leaving point 146 (say) in the loop 54 of the counter-discounter will travel through pulse regenerator 91a and the 0.75a delay to a point 91, suffering a delay of one binary-digit period, pulse regenerator 90a and a further 0.75a delay, and so on along the complete chain to re-enter the loop 54 via a gate 150. If this is the first pulse to be entered it will continue along the chain again, reaching the loop 86 as the controlling pulse trains Tl, Tl change the conditions of the gates so that the pulse circulates in the closed loop 86 to register a count of "1." The increase of this amount by unity after each instruction has been carried out is obtained in a similar manner to that described under " counter - discounter " above. The amount registered in the line-number memory controls a network of diode coincidence gates forming a tree circuit which causes one of 64 channels (only channels 0 to 15 are shown in Fig. 7) to be opened to admit pulses representing orders, &c., obtained from the plugged connections described above. These pass the appropriate gate 128, 129, &c., then the group gate 147, 121, &c., and so via gates 122 and 123 to the output 124 which may supply either the TO or AD memory Ml to M4, Fig. 3, or the OD-type memory, Fig. 5.. The arithmetic unit and the arithmetic processes carried out are similar to those described in Specification 742,869. Multiplication. The multiplier is lodged in MO or S1, Fig. 56, and the multiplicand in one of the other memories Sn. Two degrees of multiplication are possible: " reduced multiplication " (TO symbol: MR) and " complete multiplication " (MC). In reduced multiplication the multiplier is stored in MO, and digits of increasing order are erased as the corresponding partial products are formed, the final product. having a maximum of eleven digits, being accumulated in MO. In complete multiplication the multiplier is stored in S1 and progressively fades out as the product, which in this case has a maximum of 23 digits, is stored in S1 and MO. Division. This also can be performed as either a reduced or complete operation. In reduced division (DR) the dividend, having a maximum of 11 digits, is stored in MO, and the divisor is stored in one of the memories Sn; at the end of the operation MO contains the quotient and the remainder, the number of digits in the former being defined by the number stored in OD. The dividend may have up to 23 digits in complete division (DC), the more significant group being stored in MO and the rest in S1. The divisor is stored in one of the other memories Sn, as defined by AD. The quotient (maximum 12 digits) is built up in S1, and the remainder (maximum 11 digits) is left in MO. The performance of some typical instructions including the transfer of amounts between computer memories and an associated tabulating machine accumulator, comparison of magnitudes, the four basic arithmetic operations, and modification of a programme in a