Patent GB-913606-A (GB)
Title: Improvements in or relating to electronic calculating apparatus
Inventor: WENSLEY JOHN HENRY
IPC: G06F7/491
Filed: 1959-04-02
Abstract: 913,606. Electric calculating apparatus. COMPUTER DEVELOPMENTS Ltd. March 15, 1960 [April 2, 1959], No. 11206/59. Class 106 (1). An arithmetic unit capable of addition, subtraction, and multiplication and division by ten and operating in the series-parallel mode with an operating radix of 16 comprises input selection circuits 6 and 7 receiving the binary coded input digits from 30 and 32 and transmitting them to a first adder comprising units 8, 9 and 10 (unit 7 may modify the input digit by shifting and/or complementing it under control of a unit 31),  the uncorrected output from the adder passing to a correction circuit 11, 12 which generates carries and filler digits where necessary, again under control of unit 31 which supplies " radix " and " arithmetic operation " signals over lines 28 and 24, respectively, and a second adder 13, 14 and 15 which adds in these corrections. The Specification describes arithmetic operations on sterling values expressed in pounds, shillings and pence (including tenths and hundredths of pence), the digits being received in parallel from the registers 30, 32 least significant digit first (the weights of the data-carrying lines are given by the second parts of the references, e.g. 1-4 and A-4 carry binary 4 to and from unit 6). Whole pence values are expressed by a single digit, e.g. 11 pence, by signals on lines 1-1, 1-2 and 1-8 during the pence period. Addition.-The control unit 31 conditions units 6 and 7 to pass input signals from 30 and 32 respectively unchanged. The signals of weights 1 and 2 added at 8, and those of weights 4 and 8 at 9, and any carry from 8 is added in by adder 10 (this arrangement of three adding units is the subject of Specification 906,168) to give the binary-coded sum on lines E-1 to E-16. A carry recognition circuit 12 receives these signals and provides an output on line Fa if their value equals or exceeds the radix appropriate to the denomination (signalled over line 28), or if a carry occurred in the previous denomination (signalled over line FaD through delay device 16) and their value equals the radix - 1. The signal on line Fa conditions. the filler generator 12 to produce filler digits appropriate to the radix, and delayed by 16 it produces a carry on line 91 at the next denomination period (an arrangement of gates for units 11 and 12 is shown in Specification 913,605). Subtraction.-The subtrahend passes through 6 unchanged, but unit is conditioned by 31 to pass the 15's complements of minuend digits from 32. If the minuend digit is less than the subtrahend digit, then the sum formed by 8-10 will be at least 16, and the number represented on lines E-1 to E-8 will be one less than the true difference (i.e. will be correct if a borrow from the previous denomination is necessary) ; if it is greater the result will be less than 15, and a filler digit equal to the radix needs to be added to produce a result one less than the true difference and a borrow from the next denomination is necessary ; if it is equal then the result will be 15 and the filler digit will depend on whether or not a borrow was called for in the previous denomination. The apparatus obtains the correction result by producing a " no-borrow " signal on line Fb if E16 is pulsed (this is returned delayed by 17 to 11 and produces a further " no borrow " signal if the input is 15 at the next denomination) which inhibits the production of filler digits by 12, and delayed by 17 passes a borrow signal to line 9-1. Multiplication and division by ten.-The multiplication of a sterling amount received from register 30 by ten requires, in the pounds, digits and decimals of pence digits, a mere shift ; this is effected by delay elements 4, the outputs from which, over lines 18, are selected under control of arithmetic and radix control lines 24 and 28. In other denominations modification of the delayed digits is necessary. This is done using the undelayed inputs over lines 1-1 to 1-8 and modifying them in 7 for addition in 8-10, and generating required filler digits using lines Fc and Fd ; the Specification describes this generation in detail. For division the delay circuits are again used, the output appearing 2 digit periods later than the corresponding input digits.