baber/WOPTO huggingface dataset:
Patent JP-H0239297-A (JP)
Title: Alarm monitor device
Inventor: KIMURA TETSUO
IPC: G08B17/00
Filed: 1988-07-29
Abstract: PURPOSE:To display an alarm at a high speed with a high precision by providing A/D converters of terminals with two high and low resolution modes in an alarm monitor device to which many terminals such as a fire sensor and a gas leakage detector are connected and selecting the high resolution in accordance with the indication from the monitor device at the time of abnormality. CONSTITUTION:When a high resolution mode request signal is outputted from a central monitor board, a switching signal is applied to a resolution switching circuit 10 from a command discriminating circuit 8, and a switch SW2 connected in series to a capacitor C2 is closed to set the capacity of the capacitor C2 to 15-fold capacity of a capacitor C1, and the discharging time is extended about 16 times. Consequently, the counted value of a counter 15 is increased about 16 times, and the resolution is raised by this increase. Thus, an integral A/D converter 9 whose speed is relatively low at the time of normal monitor is switched to the high resolution mode at the time of abnormality, and address polling at a high speed is possible. That is, the time of transmission from a specified terminal is shortened.
Patent JP-H04226548-A (JP)
Title: Elastomeric low-density foamable composition, its manufacture, and article made therefrom
Inventor: RICHIYAADO BURIAN AREN
IPC: C08L53/02
Filed: 1991-07-03
Abstract: PURPOSE: To provide an elastomeric low density foamable compsn., a method for producing the same and a produced article.  
     CONSTITUTION: A low density foamable elastomer compsn. is produced from blends comprised of a major amt. of a block copolymer consisting of an alkenyl aromatic and a conjugated diene and a minor amt. of one or more other thermoplastic resins and an easily volatile foaming agent. Pref., the blends of the foamable compsns. are comprised of a major amt. of triblock copolymer of the A-B-A type and a minor amt. of polystyrene resin and/or polyphenylene ether resin. Processes for preparing such low density foamable compsns. and articles made therefrom are also describled. 
     COPYRIGHT: (C)1992,JPO
Patent JP-H0237297-A (JP)
Title: Control device
Inventor: SAITO OSAMU
IPC: F41G7/22
Filed: 1988-07-28
Abstract: PURPOSE:To improve the target destruction capability of a control device against a target which is turning rapidly or moving at a high rate of speed by providing a limiter circuit which outputs first and second level signals, a steering command bias signal generating circuit which outputs the zero signal and the steering command compensating signal, and an adder which outputs the compensated steering command signal to the steering device. CONSTITUTION:The limiter circuit 17 outputs a low level signal when the target direction command signal outputted by a signal processing section 9 does not exceed a predetermined level, and outputs a high level signal when the predetermined level is exceeded. The steering command bias signal generating circuit 18 outputs the zero signal when the output from the limiter circuit 17 is a low level signal, but, if a high level signal is being outputted, it outputs a steering command compensating signal corresponding to the magnitude of the target direction command signal outputted by the signal processing section 9. An adder 19 adds the steering command signal outputted by the auto pilot 11 and the steering compensation signal from the steering command bias signal circuit to output a compensated steering command signal to the steering device 12. Since the attitude of this control device M is controllable, the attitude angles and the flight path of the control device M is controlled so that the target 1 may be always acquired within the beam scanning angle of the antenna 7 and within the signal transmission and reception of the dome.
Patent JP-H1131862-A (JP)
Title: Method of manufacturing semiconductor solid-state quantum structure
Inventor: NISHI KENICHI
IPC: H01S5/343
Filed: 1997-07-14
Abstract: PROBLEM TO BE SOLVED: To provide a method for easily manufacturing a semiconductor solid- state quantum structure, wherein homogeneity in size and composition is good while density is sufficient as well. SOLUTION: A plurality of regions (resist parts 11) which is, of ruggedness structure, larger than in-surface size of a solid-state quantum structure but smaller than 5 times the in-surface size are formed on a first semiconductor layer (GaAs substrate 10), while a second semiconductor layer (Inx Ga1-x As mixed crystal, etc.), of different lattice constant is laminated, so that a solid- state quantum structure (InAs semiconductor solid quantum structure 13) is manufactured self-alignedly on the plurality of regions (11).
Patent JP-S5890651-A (JP)
Title: Electrophotographic method
Inventor: IRIHARA KOUICHI
IPC: G03G21/08
Filed: 1981-11-24
Abstract: PURPOSE:To eliminate a transfer track, etc., generated when a photoreceptor is used repeatedly by irradiating the surface of a photoreceptor uniformly with discharging light having shorter wavelength than laser light for discharging after the transfer process of a laser printer. CONSTITUTION:The photoreceptor 10 of a laser printer has the two-layer structure of an Se charge transfer layer, Se-Te charge generation layer, and Se charge holding layer on a substrate of Al. A corona discharging device 11 charges the surface of the photoreceptor 10 positively and the photoreceptor is rotated as shown by an arrow and irradiated with an original pattern by using laser light 12 to form an electrostatic latent image. This is treated through the reversal development of a developing device 13 and after transfer to a form is performed, the form is charged positively by a corona discharging device 16 for discharging. Then, a light discharging device 17 is used to supply light having short wavelength than the laser light 12, eliminating the generation of a dark current of the photoreceptor 10. Then, a cleaning device 18 performs cleaning. Thus, a picture free of a transfer trace is obtained repeatedly.
Patent JP-H07145603-A (JP)
Title: Concrete injection device of sleeper spacing
Inventor: AREKUSANDERU FUON BUIRUKEN
IPC: E01B37/00
Filed: 1994-07-19
Abstract: PURPOSE: To improve workability by connecting a finishing machine for injecting concrete and a pump for supplying concrete by a conduit having a fixed length. CONSTITUTION: A concrete finishing machine 4 with travelling cars 26, 28 is disposed onto the edge lane 2 of a foundation HGT while a lattice body 10 comprising ties 8 and rails 12 is laid on a concrete board TRG. A concrete pump 14 is disposed at the rear of the finishing machine 4, and both the machine 4 and the pump 14 are connected by a conduit supporter 18 supporting a pump conduit 16. The travelling cars 26, 28 are made to travel, tie spacings are supplied with concrete flowing into a concrete buffer tank 32 from the conduit 16 by a filling vessel 34, and a surface is molded by a press plate device 40. The effective length of the conduit 16 is adapted to the operating speed of the finishing machine 4 so that the pump 14 feeds concrete sufficiently curable at all turns.  Accordingly, the device can be lightened, the application of powerful load to a subgrade can be avoided, and concrete can be injected into the tie spacings by a simple method.
Patent JP-S6348188-A (JP)
Title: Rotor position detector for synchronous motor
Inventor: YAMAMOTO MASARU
IPC: H02P25/026
Filed: 1986-08-12
Abstract: PURPOSE:Te detect the position of a rotor based on induction voltage induced to respective phase windings, by permitting exciting current to flow to the field windings to generate magnetic flux, on the stop of a synchronous motor. CONSTITUTION:By an exiting current regulating means 1, exciting current I f fluctuated for a time is permitted to flow to a field winding 21, and magnetic flux is generated. On the respective phase windings of a synchronous motor 20, the induction voltage of respectively different degree and direction is generated according to positional relation between the then magnetic flux and the respective phase windings. Accordingly, the induction voltage induced to the respective phase windings is to have a regulating property according to the position of the stopped rotor of the synchronous motor 20. Then, the position of the rotor is detected by an integrating circuit 3, a polarity discriminator 4, a voltage comparator 5, and a logical circuit 6.
Patent JP-H0630664-A (JP)
Title: Nutritive liquor formulation system
Inventor: KIKUCHI HIROSHI
IPC: G05B11/32
Filed: 1992-07-16
Abstract: PURPOSE:To provide system designed to efficiently grow plants without suspending the circulation of a nutritive liquor to raising beds and without the need for preparing additional tanks. CONSTITUTION:The electrical conductivity of a nutritive liquor 8 to be used for plant raising is determined by an electrical conductivity meter 12; when the resultant electrical conductivity value is out of a specified range, an acid- alkali feeder 3, liquid fertilizer feeder 9 and water feeder 4 are selectively actuated respectively for a specified time so that the electrical conductivity value fall within the specified range through a controller 2, and concurrently, electrical conductivity control is performed to check its value at every specified time so that such value does not get out of the specified range; a nutritive liquor is replenished under the above actions.
Patent JP-H0239203-A (JP)
Title: Fuzzy controller
Inventor: OKAMOTO KENJI
IPC: G06F9/44
Filed: 1988-07-28
Abstract: PURPOSE:To increase the arithmetic processing speed of a fuzzy controller by using only hardware to produce the fuzzy controller. CONSTITUTION:An operation is applied to the conditions of a formula consisting of the membership relations Ai and Bi which is used to obtain the control input (y) for control of a control subject as well as the present output value (x) of the control subject. The memories 5 and 6 store the former conditions Ai and the latter conditions Bi of the 1st conditions. While the memories 7 and 8 store the former conditions A2 and the latter conditions B2 of the 2nd conditions respectively. The MIN circuits 13 and 14 compare the data read out of the memories 5, 6 and 7, 8 with each other for each clock and output the smaller value. Then a MAX circuit 15 compares the outputs of both circuits 13 and 14 with each other for each clock and outputs the larger value. A sum total circuit 16 integrates the output of the circuit 15 to obtain the sum total for each frame. A weight sum circuit 17 integrates the product of the output of the circuit 15 and the clock number of obtain the sum total for each frame. Then a division circuit 18 divides the arithmetic result of the circuit 17 by the arithmetic circuit of the circuit 16 to obtain the centroid (y).
Patent JP-S6083745-A (JP)
Title: Production of thin sheet by continuous casting method
Inventor: KADOI JIYUN
IPC: B22D11/12
Filed: 1983-10-12
Abstract: PURPOSE:To produce continuously a thin sheet product having an excellent surface characteristic and fine structure by rolling continuously the thin continuous casting billet which is cast by a twin drum type continuous casting machine under specific conditions. CONSTITUTION:The molten metal 4 in a tundish 5 is allowed to flow down between two internally water-cooled casting rolls 1 and 1' and is drawn out by guide rolls 8 as a thin casting billet 3 under cooling with the casting rolls. The continuous casting billet 3 is rolled without cooling by plural rolling down rolls 2-2'' in a temp. range of 1,050-800 deg.C billet temp. and a thin metallic sheet 7 is continuously produced. The billet is rolled in this case at <=10% draft in one pass in such a way that the total draft is made >=20% by >=2 passes of rolling. The sheet 7 which is smooth without having ruggedness such as rippled surface, has a uniform thickness and has fine structure is thus produced.
Patent JP-H0717450-A (JP)
Title: Traveling condition detecting device
Inventor: OKUZONO NAGAHIKO
IPC: B62M25/00
Filed: 1993-06-30
Abstract: PURPOSE:To provide the data which clarifies relationship between the traveling condition and the force to be required for the traveling. CONSTITUTION:When the start key is operated (S3) after the weight of a bicycle and the weight of a rider are inputted (S1, S2), the traveling speed and the traveling distance are calculated (S4). These calculated traveling speed and the traveling distance are stored (S5), and then displayed (S6). Then, a judgement is made whether the flag F is reset or not (S7), and when the flag F is reset, the present speed V1 calculated in S4 is stored (S8). In addition, the process from S4 is executed again until the specified period of time is elapsed after the flag F is set (S9). Because the flag F has been already in the set condition, the loop of S4-S7 S10 is repeated. When the specified period of time is elapsed, the power is calculated (S12) after the speed V2 calculated in S4 in running the loop is stored (S11).
Patent JP-2000021178-A (JP)
Title: Semiconductor memory apparatus
Inventor: TAKENAKA HIROYUKI
IPC: G11C11/407
Filed: 1998-07-03
Abstract: PROBLEM TO BE SOLVED: To reduce a power consumption without lowering an operation speed by precharging a block selection circuit for selecting a sub memory array of one block prior to an address selection circuit before turning into a non-selection state. SOLUTION: A pulse generation circuit 13 outputs a reset signal for temporarily resetting a precharge to a selected row decoder when the row decoder is changed to a non-selection state. When a /CE signal changes from '1' to '0', address decode circuits 18, 19 and 20 operate thereby supplying decode signals W2, W3 and W4 to pulse generation circuits 41, 42 and 43, whereby signals W2', W3' and W4' are output with a predetermined time delay. In consequence of this, all transistors 15-17 of the row decoder selected by a combination of addresses are turned on and a word line WL rises. In the selection state, a transistor 14 is not turned on and therefore a punch-through current never flows between a power source Vcc and a ground GND even when the transistors 15-17 are turned on.
Patent JP-2000336008-A (JP)
Title: Pest control composition for agriculture and horticulture
Inventor: HOSOKAWA HIROYASU
IPC: A01N43/50
Filed: 1999-07-02
Abstract: PROBLEM TO BE SOLVED: To obtain the subject composition which can simultaneously control pathogenic fungi and insect pests such as mites, can give a larger synergistic effect than only an additive effect obtained by mixing active compounds, and enables the reduction in the amounts of the ingredients to be used, by including chlorfenapyr, an anilinopyrimidine-based agent, an SBI agent, and, etc., as active ingredients. SOLUTION: This pest control composition contains (A) at least one selected from chlorfenapyr and dinocap, and (B) at least one selected from the group consisting of anilinopyrimidine-based agents such as mepanipyrim, pyrimethanil and cyprodinil, SBI agents such as triflumizole, triadimefon, propiconazole, tebuconazole, epoxiconazole, diniconazole, bitertanol, myclobutanil and hexaconazole, and strobilurin-based agents such as kresoxim, azoxystrobin and metominostrobin, as active compounds.
Patent JP-S6433798-A (JP)
Title: Semiconductor integrated circuit
Inventor: IMAI MIZUHO
IPC: G11C17/00
Filed: 1987-07-29
Abstract: PURPOSE:To prevent the generation of a latch-up and the enlargement of a chip by discharging the output node of a CMOS circuit in a condition in which the conductive resistance of a MOS transistor for separation is high after a period to output a higher voltage than a first voltage, and thereafter, lowering the conductive resistance with a control signal. CONSTITUTION:A CMOS circuit 6 is operated by a voltage VC, and it sets an output node 1 to the voltage VC or to a voltage VS. On the other hand, the circuit impresses voltage HV 1 or HV 2, which is higher than the voltage VC, to a node 16 or 15 respectively, boosts them, and takes out the output voltage from an output line COLi. Here, the output of the CMOS circuit 6 is controlled by an inverter 11 between the voltages VC and VS, and given through an output mode 12 to a MOS transistor TR 13. A control signal S3 is applied to the TR 13, and a second voltage, which is higher than the voltage VC, discharges through the node 12 in a condition of a high conductive resistance after the output period. Thereafter, the second voltage is conducted to the MOSTR for separation by the control signal S3, and discharged. Thus, the generation of the latch-up is prevented, and the enlargement of the chip of an integrated circuit is evaded.
Patent JP-H0353347-A (JP)
Title: Debugging system
Inventor: SAIKAI HIROYASU
IPC: G06F11/28
Filed: 1989-07-21
Abstract: PURPOSE:To carry out the steps at a high speed for each function of source levels like each sentence, each line, each function call, etc., by setting a break point at a process part where the steps are produced by a language process program. CONSTITUTION:When the steps of function levels are carried out, a debugger program 2 sends a command to an in-circuit emulator 5 via a communication circuit 4 to set a break point to the head address of a function step execution process part 33 of a target equipment 6. A user decides whether he/she carries out the steps at block levels or not based on the program 2. If so, the program 2 sends a command to the emulator 5 via the circuit 4 to set a break point to the head address of a block step execution process part 34 of the equipment 6. As a result, the response time is shortened to a command for step execution at a source level.
Patent JP-H0739532-A (JP)
Title: Speed examining device for diastolic blood flow
Inventor: TAKASHIMA MITSURU
IPC: A61B5/0295
Filed: 1993-07-30
Abstract: PURPOSE:To detect the speed of diastolic blood flow accurately and precisely with a simple structure irrespective of the diameter of blood vessel. CONSTITUTION:The inflow and discharge of air to and from an air bag 7 is controlled by controlling a pump 38 and discharge valve not shown in the diagram by a pressure control section 37 through the control signals c1 and c2 so that the pressure P by the air bag 7, for example, becomes equal to the diastolic pressure P1. A first peak detector 41 detects the first peak and generates the first peak detection signal DP1 and a second peak detector 42 detects the second peak and generates second peak detection signal DP1. Based upon the generated first peak detection signal DP1 and second peak detection signal DP1, a timer 43 measures the time interval between the first peak and the second peak as the counted value A. The speed of diastolic blood flow in a diastolic blood vessel diameter is computed by taking the reciprocal of such counted value A with a divider 45.
Patent JP-H1134999-A (JP)
Title: Launch type zero gravity generating device
Inventor: SAKAI YOSHIHITO
IPC: G01D21/00
Filed: 1997-07-15
Abstract: PROBLEM TO BE SOLVED: To air-brake an external capsule to decrease lifting down speed, integrate the external capsule with an internal test device table just before braking, and reduce impact at braking, by placing a member which amplifies air resistance during lifting down on a hollow body. SOLUTION: Plural supporting members 26 are stood on a body part 21a above an external capsule 21, two hollow semi-spheres 27 which play an air brake as a member amplifying air resistance are mounted to the supporting members 26 such that its opening is downward. Thus, during lifting down of a capsule 20, a semi-spherical recessed surface which is formed on the lower end 21c of the external capsule 21, and air-braking function of the hollow semi- spheres 27 restrain the lifting down speed. In addition, because an internal test device table 22 floated in the external capsule 21 is softly lifted down and integrally loaded on the bottom of the external capsule 21, impact to inner bottom during braking can be prevented.
Patent JP-H0241631-A (JP)
Title: Battery backup device for dc power
Inventor: INAO KIYOHARU
IPC: H02J9/06
Filed: 1988-07-29
Abstract: PURPOSE:To eliminate the need for a voltage monitor circuit, and to simplify the circuit by installing a backup power supply feeding DC voltage slightly lower than the output voltage of a DC power supplying load with DC voltage and changing over the power supply on service interruption. CONSTITUTION:DC input voltage Vin obtained by rectifying and smoothing a commercial power supply not shown is converted into specified DC voltage Vout by a DC/DC converter and output. DC voltage Vout is divided by resistors R1-R3, and voltages Va, Vb (Va>Vb) are determined. Voltage Va, Vb is compared with reference voltage Vref by error amplifiers (a), (b). A PWMCTL turns a transistor Tr ON-OFF so that an output from the error amplifier (b) is brought to zero at all times. The error amplifier (a) sets the voltage of a backup power supply B at a value slightly lower than output voltage Vout by a controller R by an output obtained by comparing voltages Va and Vref. Accordingly, the power supply is changed over automatically to the backup power supply on the service interruption of the commercial power supply by a simple circuit requiring no voltage monitor circuit.
Patent JP-H1014929-A (JP)
Title: Forceps apparatus
Inventor: JO SHIGETO
IPC: A61B17/28
Filed: 1996-07-02
Abstract: PROBLEM TO BE SOLVED: To secure certainty, safety and moreover, diversity in the treatment with forceps by building a drive shaft up with a hollow member to drive the opening or closing of a dog of forceps provided on an insertion shaft to allow the insertion of the forceps, a medical fluid supplying/discharging device and other treating devices thereinto for compound operation with a simple forceps device. SOLUTION: In first forceps 1 in which a pair of large dogs 3 and 3 as working part mounted on the tip of an insertion shaft 2 comprising a hard pipe through a link mechanism, a hollow drive shaft linked to the link mechanism is provided to open or close the large dogs 3. Second forceps 20 are inserted through the drive shaft and have a pair of small dogs 21 connected to a slide shaft 24 slidably provided within the drive shaft through the link mechanism. To operate the link mechanism, a drive rod is inserted through the slide shaft 24.
Patent JP-2001024004-A (JP)
Title: Led chip mounting structure
Inventor: ISOKAWA SHINJI
IPC: H01L21/52
Filed: 1999-07-05
Abstract: PROBLEM TO BE SOLVED: To prevent a short circuit at the upper surface of an LED chip by forming, in the bonding area of the LED chip of a pattern electrode, a groove to guide the bonded extra silver paste to the outside area of the bonding area. SOLUTION: A groove 3A is formed to an electrode pattern on a substrate 2 in the shape for easily generating the capillary phenomenon, to release an extra paste and to prevent up-diffusion of the silver paste 4 to the surface of a chip 1 leaving the necessary paste only at the back side of the chip 1. Namely, a cross type groove 3A is formed with the etching or pressing work to the bonding area of the chip 1 of the electrode pattern 3 in order to release the extra silver paste to the outside. As a result, the short circuit on the upper surface of the LED chip 1 can be prevented.