Patent GB-938188-A (GB)
Title: Improvements in and relating to electronic computers
IPC: G06F7/495
Filed: 1960-10-12
Abstract: 938,188. Electronic computers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 12, 1960 [Oct. 19, 1959], No. 34961/60. Class 106 (1). An electronic computer comprises a memory, a memory address register, storage means for a plurality of addresses, address modification means and programme timing means for controlling the flow of addresses between the address storage means and the memory address register. General.-The memory 101 (Fig. 1a) comprises 100 x 100 rows of magnetic cores, each row of 12 cores including an even addressed location and the higher adjacent odd addressed location, each location of six cores being capable of storing a four-bit binary-coded decimal digit, a check bit and a " flag " signal which may indicate the beginning or end of a word, a carry &c. The memory address storage 300 MARS consists of eight 22-core registers each capable of holding a five-digit word which may be a memory address or an arithmetical quantity. Modification means 400 include an incrementer 401 capable of altering the address in a particular register. A programme timer 504 determines which particular register shall transfer its contents to the memory address register MAR 201. The contents of the latter control two 10 x 10 matrices 102, 103 to select the corresponding twelve-bit row in the memory, and the resulting pulses from the memory cores pass via amplifiers 601 to buffer registers MBRE, MBRO, an even/odd switch 604 selecting one of the two locations according to whether the units digit of the address is even or odd. Data words of variable length are stored in the memory with two digits in each row, the beginning of a word being signalled by a flag " in high order digit position. An additional " flag " in low order digit position indicates a negative number. Instructions are stored in the memory in twelve-digit form as follows: Q 2  being stored in an even-addressed location and the other digits in adjacent locations. For most instructions the P number is the address of the location at which the units order of the P field is situated, higher position digits being located in lower adjacent addressed locations, the highest order digit being indicated by a " flag " signal. In other cases, the P addressed digit marks the beginning of a record which extends over higher addressed locations, the final digit being marked by a " flag " signal. Starting.-Manual resetting at the console 702 zeroizes all the registers &c. and starts the timing control 800. Instructions and data can then be read into the memory from a punched tape. After the contents of the tape have been stored under the control of the first instruction, the next instruction in the location indicated by 1R1, is set up, under the control of the programme timing means 504, in I-time and executed in E-time. I-time occupies eight machine cycles each of 20 Á secs.; E-time occupies a variable number of cycles depending on the instruction. The address of the first instruction entered from the input tape is set up in MAR, via IR1, by built-in means. During the first cycle of I-time this address, which represents digits 0 1 0 2  of the instruction, is applied to decoding matrices 102, 103, causing the " operation " digits of the instruction to be read out of the main store 101. The evenaddressed location sends its content, O 2 , via MBRE and data register MDR to the tens digit position in the operation register 501, while the odd addressed location sends its content 0 1  via MBRO to the units position in OPR. The digits read out of the store are normally regenerated in the position from w hich they came. Also during the first cycle of I- time, the address in IR-1 is increased by 2 by means of incrementer 401, and this new address is set up in MAR. During the second cycle of I-time the two highest digits P 5 P 4  of the P-number of the instruction are read out of the main store and written into the appropriate orders of e.g. OR-1 (as marked by the programme timer) and the address increased by 2 as before. P 3 P 2  are transferred during the third cycle and, during the fourth cycle switches set by the programme timer ignor the odd memory location, allowing only P 1  to pass into and complete the P-number in OR-1. The incrementer increases the address by 1 only at this stage. During cycles 5 to 7 the Q number is transferred to another register, e.g. OR-2 in a similar manner. The eighth cycle is used to synchronize the programme timer advance pulses and transfer the contents of OR-1 into MAR. During E-time the machine performs the operations determined by the O 2 0 1  digits registered in OPR. A list of operations, and a detailed description of the performance of a particular programme, are given in the Specification. Addition.-This is performed by multiple memory references, a sequence of locations 00300-00399 in the memory being set aside as an add table. Each location contains a result digit, and where a carry is necessary a " flag " signal accompanies the digit. The augend digit forms the units digit of the address and the addend digit forms the tens digit. Thus in adding 3 to 4 location 00334 is addressed and the sum 7 is read out; in adding 7 to 8 location 00378 is found to contain a flagged 5, (5!), indicating a carry and setting carry trigger 403. The 3 in the hundreds position is introduced automatically as the add table is addressed. During I-time, OPR receives the operation digits signifying " ADD " and the decoder 503 - sets up the programme time 504 for addition; OR-1 receives the Q number, the addend field address, OR-2 the P number, the augend field address. The Q number is set up in MAR and the address of the next instruction is registered in IR-1; OR-3 also registers the P number to retain the augend units address should re-complementing be necessary. During E- time for addition four cycles are required at each digit position. 1. Read out (RO) addend digit from memory per OR-1. Decrement by 1 the content of OR-1. 2. RO augend digit from memory per OR-2. 3. RO add table location specified as 00-3 (augend digit) (addend digit plus carry from previous order) to MDR. 4. Write sum into augend digit location in memory per OR-2. Decrement by 1 the content of OR-2. Decrementing OR-1 and OR-2 causes the addition to flow from low order to high order digit positions, until the augend " flag " signals completion. The augend field is arranged to have more digit positions than the addend. On sensing the addend word mark flag step 1 is eliminated from the add sequence. Subtraction is accomplished by 10's complement addition, true/complement switches 404, 408 being 9's complementers and forcing a carry from the next higher digit position to create 10's complement when the relative signs of the operands render this necessary. When there is no carry from a higher order digit on sensing the word mark flag, carry trigger 403 is un-set and recomplementing is necessary. The programme forces add sequences 2, 3, 4 until the word mark appears, using augend/ sum address per OR-3. The difference, in complemented form, is addressed. Working from low order digit positions the 9's complement and a forced carry give the correct difference digits until no carry is possible, when a " flag " is forced as a word end mark. Multiplication is performed digit by digit by means of a multiplication table in locations 00100-00299 in memory, followed by the accumulation of the so-formed partial products in an accumulator area, location 00080-00099 in the memory. The form of addressing the multiplication table in the memory is i.e. for 5 x 7 the location in memory is 00254 and is such that an even addressed location is always read. The odd addressed location contains the tens digit of the product. Thus 00254 and 00255 contain 5, 3 respectively and the product is recognized as 35. During I-time OR-1 is set to the Q number, the multiplier units address, OR-2, OR-3 to the P number, the multiplicand unit address. The accumulator locations are first cleared per PR-1 which is incremented by 2. A digit of the multiplier is read out per OR-1 (which is decremented by 1) to multiplier register MR405 which is used for quick access storage of a single multiplier digit whilst each of the multiplicand digits are presented. The content of MR is doubled by doubler 406 and passed to the units and hundreds position of MAR. Each digit of the multiplicand is in turn directed to the tens position of MAR which then addresses memory. The even addressed location in memory passes its content via MBRE and MDR to digit register units DRU, the odd addressed location content is sent to digit register tens DRT. The accumulator is read out per PR-1 to MDR and its content added, by memory add table, to the contents of DRU, the sum being passed to MDR and stored in the accumulator per PR-2 which is decremented by 1. The next higher order accumulator digit is then read to MDR per PR-3, the contents of DRT are sent to DRU and the accumulator digit from MDR is added to the partial product tens digit, now in DRU, the sum being stored in the accumulator per PR-2. When the multiplicand word end flag is sensed, the next higher multiplier digit enters MR until the multiplier flag is sensed. Specification 909,899 is referred to.