Patent GB-1105812-A (GB)
Title: Data processors
Inventor: ULRICH WERNER
IPC: G06F9/308
Filed: 1965-10-06
Abstract: 1,105,812. Digital electric computers. WESTERN ELECTRIC CO. Inc. 6 Oct., 1965 [7 Oct., 1964], No. 42347/65. Heading G4A. A data processor operating on words (e.g. of 23 bits) and having a masking circuit has means for detecting in an instruction words an abbreviated code having a number of bits fewer than the word (e.g. 6 bits) and means decoding the smaller word to generate a mask word having more than the smaller number of bits (e.g. 23 bits) and means for controlling the use of the generated mask word by the masking circuit in a masking operation. In the computer described using a memory having 2<SP>16</SP> locations an instruction or data or masking word of 23 bits is used. Bits 20 to 22 specifying operation, bits 18, 19 specifying the index register and bits 16, 17 specifying either the destination or source register depending on the operation. Operations are Read (RD), Register to Register (RTR), Write (WRT) which may be masked or not masked, Transfer (XFR) and Abbreviated Mask-Read (ABRD) and Abreviated Mask - Register - to - Register (ABRTR) the latter two of which will be described. ABRD (Figs. 1 and 2, not shown). An instruction word read from a store (10) into an instruction register (16) is applied to a decoderdistributer (30). If bits 22, 21, 20 are 110 then an ABRD cable is enabled and bits 20-16 are transmitted thereon. Bits 15-0 are transmitted on a further line, bits 5-0 to an index adder (32) and bits 15-6 to a translator 44 enabled by the ABRD cable. A read cable (RD) is also enabled by the ABRD command and carries bits 19-16 and #20 supplied from the ABRD cable, a 1 in bit 20 being necessary in the RD cable to enable the masking circuit (19). Bits 19, 18 pass to a register reader (34) to specify which register (A, B or C) is to be used. The index adder then adds the 23 bit word from the register specified to the 6 bit word in the index adder and bits 0-15 of the sum are passed on a cable (33) to a data read circuit (12) which reads a word from store specified by the 16 bit address. This word is then passed through the masking circuit which by then contains the word produced by the translator from the abbreviated code and stored in a masking register 39, is masked, passes to a register selector 35 which under the instructions of bits 17, 16 of the instruction word stores the word in a specified register. Normally the instruction words are obtained from memory by a program address register (36) and an order read circuit (11) the word address being incremented by one after each withdrawal. However a transfer instruction allows a different address to be written into the programme address register. In this operation wherein no masking occurs a XFR line is enable passing bits 15-0 to the index adder. To this word is added a 23 bit word from a register specified by bits 19, 18 and bits 15-0 of the sum pass via a cable (33) to the programme address register to denote the address of the next instruction word. ABRTR. An ABRTR command operates similarly to the ABRD command except that a 23 bit sum word issues from the index adder to the masking circuit, is masked and returned to a register specified by bits 17, 16. Abbreviated masking code (AMC) and decoder (Fig. 3). The AMC is represented by a 10 bits 15-6, comprising two five bit words, the first denoting the most significant bit containing a masking 1 and the second denoting the least significant bit containing a set of adjacent 1's with adjacent 0's at each end e.g. 0000011111000 (for a 13 bit number). The decoder comprises two sets of AND gates H1-22, L0-21 each set being one less in number than the number of bits to a word, and each corresponding to a bit position, one set corresponding to bits 22-1 the other to 21-0. Each gate is enabled when a number corresponding to its bit position is applied to its input and each H gate is connected to an OR gate A21-A1, except H22, a second input to the OR gate coming from the next adjacent more significant H gate such that if one H gate is enabled an input appears at each less significant OR gate. The L gates and corresponding OR gates B are connecting in a similar manner in the opposite (less significant to more significant) direction, and the outputs of OR gates corresponding to the same bit position are ANDED in gates G which also have an enabling pulse from source 62. In operation a pulser 60 resets the mask register on lines S0-22 the pulse also passing through delay 61. Bits 15-11 enable one of H gates and the least significant OR gates G while bits 10-6 enable one of L gates and the more significant OR gates B thus the output on AND gates G and lines S0-22 has 1's in the places between and including the numbers specified by bits 15-6.