Patent GB-1456712-A (GB)
Title: Adaptive braking system for a vehicle
IPC: B60T8/70
Filed: 1974-09-04
Abstract: 1456712 Adaptive braking systems BENDIX CORP 4 Sept 1974 [25 Sept 1973] 38709/74 Heading F2F An adaptive braking system 10 has a solenoid valve 58 which is actuated to initiate brake pressure decay in a number of modes of operation in response to the rotational behaviour of wheels 16, 18 on a common axle; in the primary mode the valve 58 is actuated using a comparison of a wheel deceleration signal with reference levels 46, 52 in comparators 44, 50; in the unbalanced mode the valve 58 is actuated if one of the wheels 16, 18 is rotating at a lower speed than either of the respective reference levels 64, 60; in the secondary mode the valve 58 is actuated when both wheels 16, 18 are rotating at such a low speed that lock is imminent, and the adaptive system also includes circuitry 80 to detect when wheel velocity is substantially synchronous with vehicle speed and then to terminate secondary mode signal and hence the brake pressure decay. As shown, the system 10 has respective wheel speed sensors 12, 14 and a selecting circuit 20 to select the signal representing the speed of the faster rotating wheel, and this signal is supplied to a reference velocity circuit 24 to provide a signal on an output terminal 26 which substantially approximates to vehicle velocity. Such signal is compared with reference velocity signals 30, 37, 30>37 in comparators 28, 34, and when the signal on terminal 26 becomes greater than these signals 30, 37 respective signals are generated on respective terminals 32, 38. The signal representing the faster wheel is differentiated in a differentiator 40 to give a signal proportional to wheel accleration and deceleration and this signal is supplied to comparators 44, 50 having reference levels 46, 52 corresponding to different deceleration levels. Both comparator signals are fed to an AND gate 48 that from comparator 50 being inverted; the AND gate 48 generates a signal fed to an AND gate 54 also connected to terminal 32. The output of AND gate 54 constitutes the primary mode signal which is fed through an OR gate 56 to actuate the solenoid valve 58. The speed signals generated by sensors 12, 14 are fed to respective comparators 62, 59 and if either or both speed signal drops below the respective levels 64, 60, on OR gate 66 will generate an output signal which actuates a timer 68-the timer 68 inhibits the output signal of OR gate 66 after a predetermined period but during this period a signal is transmitted to an AND gate 70 whose other input terminal 71 is connected to terminal 38. The output of AND gate 70 is defined on the unbalanced mode signal and is transmitted to OR gate 56 to actuate valve 58. However, if both comparators 59, 62 generate output signals then an AND gate 72 will also generate an output signal which fires a one-shot 74 connected to an AND gate 76 whose other input is connected to terminal 38. The output of AND gate 76 sets a secondary mode flip-flop 78 whose output is defined as the secondary mode signal and is transmitted to OR-gate 56. The circuitry 80 acts to reset the flip-flop 78 to terminate the brake pressure decay. Thus, the circuitry 80 includes a comparator 82 with a reference accleration value 84 and when the signal from differentiator 42 exceeds value 84 the comparator 82 generates a signal which is fed through an OR gate 86 and an OR gate 88 to the reset terminal of flip-flop 78. Further, the circuitry 80 includes a peak falloff detector 90 which generates an output signal when the acceleration signal has decreased a predetermined amount from a peak value, and a comparator 94 having a reference level 96 proportional to a substantially zero value of the acceleration signal, the comparator 94 generating a signal when the signal from differentiator 42 is above the level 96. Simultaneous signals from detector 90 and comparator 94 causes an AND gate 92 to supply a signal to OR gate 86. Still further, the circuitry 80 has a comparator 106 which generates an output signal whenever the value of the acceleration signal is above a reference level 108 to set a flip-flop 110, the output of the comparator 106 and the flip-flop 110 also being inverted and transmitted to an AND gate 112, having a third input terminal connected to flip-flop 78. AND gate 112 generates an output signal whenever the value of the acceleration signal drops below level 108 after it initially increases to a value higher than level 108, and this output signal actuates a timing mechanism 114 which generates an output signal a predetermined time period after the output signal from AND gate 112 is generated, which is fed to OR gate 88. Another failsafe timer mechanism 116 is provided to ensure that the secondary mode cannot last indefinitely. Fig. 4 shows details of the reference velocity circuit 24. A capacitor 130 has its charge increased as long as the magnitude of the signal from selecting circuit 20 increases when the value of the signal decreases the capacitor 130 discharges through a current source 134 so that the signal generated on the output terminal 127 will decay linearly.