Patent GB-985020-A (GB)
Title: Adaptive recognition systems
IPC: G06V30/194
Filed: 1964-02-06
Abstract: 985,020. Adaptive recognition circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 6, 1964 [Feb. 28, 1963], No. 5013/64. Heading G4R. In an adaptive recognition system a binary input signal is arranged, in a "learning" phase, to set up a representation of the relationship of each of the "1" bits in the input signal with all the other "1" bits, there also being means, used in the "recognition" phase, for producing a signal representative of the relationship between a new input signal and the pattern set up. This signal is then used to obtain a signal indicating the match between the input signal learned and the new input signal. The input signals are in the form of a succession of three groups of ten bits. In convenience the ten bits are given the letters A-J and the groups are represented by words e.g. "DAD" indicating that the first and fourth bit are "1's" and all the rest "0's". The successive words are applied in parallel to the input gates 1m Fig. 1A of a shift register stage 1 having ten storage positions. When gate 1m is opened the first word "DAD" enters stage 1. The output gate is then opened to pass the stored signals to the logic and weighting circuits 4a-4j. In each of these circuits are thirty comparison and latch circuits as shown in Fig. 2. Each consists of a unit as shown in Fig. 3. The two inputs 1a and 1b, with the switch 33a in the "learning" position, are applied to And gate 30. If both are "1's" latch circuit 31 is set. In the recognition phase the switch is in the opposite position and the signal 1b is, in effect, compared with the setting of latch 31 in gate 32. In the first circuit 4a the first bit 1a of the first register stage 1 is compared with all the bits of all three stages, thirty in all. When the first word "DAD" is gated to the circuits 4a-4j the "1" on the first lead 1a is compared with itself in unit 17-1 and the corresponding latch is set. The "1" on the fourth lead 1d is also compared with lead 1a and the corresponding latch is set. The same happens in the fourth circuit 4d where all leads are compared with the fourth lead 1d. When the next word is entered into stage 1, the first word "DAD" shifts to stage 2. The second word may be "HAD" and the comparisons are again made and further latches set up not only in respect of the new word in stage 1 but also in respect of the fact that "DAD" is now in stage 2. Again each bit of stage 1 is compared with each bit of stage 1 and stage 2 and latches set where there are coincident "1's" i.e. in the first and fourth positions. The process is repeated when the third word shifts into stage 1, the second into stage 2 and the first into stage 3. The settings of the 300 latches represents the comparison (both "1's") between each bit of each input signal group with all bits of itself and the other two groups. Recognition. The switches 33 in each of the 300 circuits are changed to the lower position. As the input signal groups are entered into the first stage outputs are obtained from And gates 32 wherever the signals correspond to the learned input signals. As each new word enters a comparison is made and a match signal produced. If the same sequence of signal is entered the match signal remains at unity. If a different sequence is entered the match signal is less than unity. The thirty outputs of each group of circuits 4a-4j are summed at 9a-9j Fig. 1b and the resulting signal applied to a threshold circuits 10a-10j. In addition the total number of "1" bits in the shift register stages 1, 2, 3 are summed at 9k and this value used as a level for the threshold circuits. Where the threshold level is exceeded a "1" passes to an And gate 11a-11j. The ten bits from stage 1 of the shift register are used to control these gates so that a signal can only pass if there is a corresponding "1" bit in the corresponding position of the first stage. The ten outputs are summed at 12. The ten leads from stage 1 are also summed at 14 and the signal from the former divided at 15 by the signal from the latter. The signal on lead 16 gives an indication of the degree of match between the learned input signals and those applied subsequently.