Patent GB-1061060-A (GB)
Title: Semiconductor structure and method
IPC: H01L21/74
Filed: 1964-09-18
Abstract: 1,061,060. Semi - conductor devices. SIGNETICS CORPORATION. Sept. 18, 1964 [Dec. 16, 1963; Jan. 20, 1964], No. 38280/64. Heading HlK. An integrated circuit structure comprises a plurality of semi-conductor bodies disposed in recesses in a support member coated with insulating material. A typical arrangement may be made from a monocrystalline silicon wafer by oxidizing its surface and then forming grooves in it defining isolated mesas, using photolithographic techniques. The oxide layer is reformed in the grooves and a thick mass of insulating material, later to form a support, vapour deposited on the grooved face. Material ' is then etched or lapped from the opposite face of the wafer down to the oxide in the groove bottoms to leave islands in which diodes or transistors may be formed by conventional masking and diffusion techniques. These may be interconnected. Fig. 9, by conductive tracks and passive components such as resistors formed by evaporation on an oxide layer which, if the support layer is polycrystalline silicon, may extend over the whole of the lapped face. A layer of opposite conductivity type at the base of each island can be provided simply by forming such a layer on the wafer at the start of the process. To accurately control the thickness of the islands the edges of the deposited support may be etched away before mounting it in a recess 39 of a lapping machine, Fig. 12 (not shown). Lapping is terminated by diamond stops 42. Alternatively the wafer edges are removed to leave shoulders on the support which are then coated with chromium. In this case lapping terminates when the lapping face contacts the hard chromium. If the support is of a hard material, e.g. alumina or silicon carbide. it may itself act as a stop. In a further modification shoulders are formed on the wafer at the same time as the grooves and the chromium stop layer deposited there before depositing the support. In other methods the semi-conductor portions are separated before the final support layer is deposited. Thus, as described with reference to Figs. 20-24 (not. shown), a plain superficially oxidized wafer has polycrystalline silicon deposited on it. The wafer is then etched using photolithographic techniques to form a series of islands which are re-oxidized. A second polycrystalline layer is deposited between and on the exposed faces of the islands and the first layer removed to leave the-assembly of Fig. 24. In a modification of this the wafer is machined down to stops as previously described before forming the islands. A similar technique may also be performed on a sub-assembly made by forming a layer of opposite conductivity type on one wafer face by diffusion or epitaxial deposition before oxidizing. After deposition of the support on the treated wafer face the wafer is electrolytically etched down to the layer, from which the islands are then formed. Another way of treating the PN wafer is to etch away sections of the layer to leave isolated portions. After re-oxidizing and depositing support material over and between these portions the wafer material is removed down to the layer to complete the isolation. Formation of device structures in isolated sections is preferably done after isolation but it is possible to form them before. This is essential where such structures are to be formed on both faces of the islands as in Fig. 60 (not shown). In this case the buried junctions are formed in the base wafer at the outset while the others are formed by diffusion into the completed structure. In this particular arrangement support 22 is conductive and contacts zones of the device: structures through apertures in the oxide.