Patent GB-1517750-A (GB)
Title: Reframing circuit for a time division multiplex system
IPC: H04J3/06
Filed: 1975-10-30
Abstract: 1517750 TDM reframing circuits WESTERN ELECTRIC CO Inc 30 Oct 1975 [22 Nov 1974] 45079/75 Heading H4M A reframer circuit for a TDM system, in which a plurality of groups of data bits (digroups) are time multiplexed on a common transmission link, each group comprising successive frames, each frame containing bits representing message information for a respective group of channels (themselves in TDM) and a respective bit providing framing information by presenting a succession of values from frame to frame in a recognizable framing pattern, is such that reframing of all multiplexed digroups occurs concurrently. In the reframer, a number of bits from successive frames of each group are applied to a first store (viz 43, Fig. 3) and the value of each of the bits in the first store is compared (comparator 48) with that of a corresponding bit one or more frames later in the respective group to detect possible framing patterns. A record is kept in a second store (45) of corresponding bits which have comparisons which violate the framing pattern and which have not. A shift decoder (49) responds to the outputs of the comparator (48) and the record in the second store to determine for each group whether any shift is necessary to reframe the group. In accordance with this determination, the bits stored for a group in the first store, the record for that group in the second store and the multiplexed bits of that group are shifted (by logic arrangements 44, 46, 51). Multiplexed digroups are received at TDM station where reframing is necessary over a link 11  (Fig. 1) and passed to a data converter 13 which regenerates received bits, converts from bipolar to unipolar format and converts each successive word to digital format. The clock in the received data is recovered at 12 and used to control operation of the converter 13 and of write address 14. Successive frames of the same digroup are alternately written into stores A and B; the write address logic directs the other digroups to other stores. The stores are read out in parallel in accordance with local clock generated at 21 and pass via multiplexer 27, along with read out information from the other store for the other digroups, to a common bus 28. The requests on this bus are passed to a framing detector (20) (Fig. 2 not shown but described in detail in Specification 1,506,759) and to an auxiliary store 47 (Fig. 3), reframe comparator 48, shift decoder 49 and "old data" store logic 44 in the reframer circuit 30. Logic ouputs from the framing detector are applied to the reframer on lines IF/IF (in frame or not in-frame status) and a framing pulse frame signal on line FPF. The "old data" store 43 includes a shared recirculating memory in the logic 44 and successively stores a given number of selected bits (including an assumed reframing bit) of each group - e.g. bits D2-D9 of time slot 23 in a frame having 193 bits arranged in 24 time slots 0-23 - which should contain the framing bit. The reframe comparator 48 compares, for each group, the output of the "old data" store with new data that is e.g. two frames later in time. A "suitability" store 45 including a shared recirculating memory and controlled by logic 46 in response to the frame comparator output records for each group which of the compared data bits have had framing pattern violations and which appear to be possible framing bits. The shift decoder, operating in response to the suitability store output and reframe comparator determines how many digit shifts should be made by the reframer in order to move to the next candidate for a framing bit. Once this number of shifts has been determined, the old data store, the suitability store and the write address logic via the shift address decoder 51 in the receive data stores to which the received multiplex data is initially applied in the retiming and framing detector arrangements at the input (Figs. I and 2 not shown) are shifted by this number in preparation for the next set of comparisons. This operation is repeated until the framing bit is captured. Details of the various logic arrangements used in the reframer are given by reference to Figs. 8-14 (not shown). The reframer continuously monitors all digital groups and carries out a reframing operation in the same time frame on any and all the TDM groups which are out of frame. The auxiliary store 47 holds the D2-D8 bits of the previous time slot TS22 for possible shift into the old data store. The slip compensation unit 52 compensates the reframer for the effects of slip in the received signals and delivers appropriate signals to the old data logic.