baber/WOPTO huggingface dataset:
Patent TW-I282591-B (TW)
Title: Semiconductor device including porous insulating material and manufacturing method therefor
Inventor: FUKUYAMA SHUNICHI
IPC: H01L21/768
Filed: 2002-02-26
Granted: 2007-06-11
Abstract: On a substrate, a first insulating film, a first interlayer insulating film, a second and third insulating films, and a second interlayer insulating film are formed. Wire trenches are formed reaching the upper surface of the third insulating film, and via holes are formed from the bottom of the wire trench to the upper surface of the first insulating film. Formation of the wire trench is performed by etching the second interlayer insulating film under a condition in which the second interlayer insulating film is selectively etched. The third insulating film exposed at the bottoms of the wire trenches and the first insulating film exposed at the bottoms of the via holes are removed by etching under a condition in which the third insulating film is selectively etched. Wires are filled in the via holes and the wire trenches.
Patent TW-550579-B (TW)
Title: On-chip circuits for high speed memory testing with a slow memory tester
Inventor: VOLRATH JOERG
IPC: G11C29/14
Filed: 2002-03-28
Granted: 2003-09-01
Abstract: A memory system (26) on a semiconductor body (10) is tested by testing components (12, 14, 16) formed on the semiconductor body. A programmable clock signal generator (12) receives an external clock signal and selectively generates an output clock signal having a frequency at a predetermined multiple of the received external clock signal. A counter (14) receives the output clock signal from the clock signal generator and generates output signals having a cyclical binary count up to the predetermined multiple of the received external clock signal. Memory locations in a programmable look-up memory (16) store separate commands for testing the memory system. The programmable look-up memory receives each of selective remotely generated binary encoded address signals (21a-21n) to access a separate predetermined look-up memory section (30-37), and the binary output signals from the counter for sequentially accessing separate memory locations within the separate predetermined look-up memory section.
Patent TW-I220115-B (TW)
Title: Method and apparatus of reverse coupling calibration for discharging electrode head of discharging machine
Inventor: HU LUNG-JIANG
IPC: B23H1/00
Filed: 2002-05-29
Granted: 2004-08-11
Abstract: This invention provides a method and apparatus of reverse coupling calibration for discharging electrode head of a discharging machine, characterized in that: a to-be-processed workpiece is positioned on a worktable of the discharging machine, a feedback reference is selected from the to-be-processed workpiece in relation to the discharging electrode head of the discharging machine, and the discharging electrode head is movable through transmission and to be biasingly and rotatably adhered to the to-be-processed workpiece or to rotate in relation to the feedback reference, so as to obtain an optimum processing position for the discharging electrode head in relation to the feedback, whereby the discharging electrode head is able to be locked to gain a calibration effect after the optimum working position for the discharging electrode head has been achieved.
Patent TW-548859-B (TW)
Title: Organic light-emitting display
Inventor: KUO CHIH-MING
IPC: H01J37/32
Filed: 2002-06-03
Granted: 2003-08-21
Abstract: An organic light-emitting display, including a transparent substrate, a transparent anode, an organic light-emitting layer, a cathode and an insulator. In this case, the transparent anode is formed on the transparent substrate. The organic light-emitting layer is formed on the anode. The cathode is formed on the organic light-emitting layer. The insulator is formed on the cathode and permeate-s into the organic light-emitting layer in part.
Patent TW-539831-B (TW)
Title: Air conditioner
Inventor: LEE KAM-GYU
IPC: F24F1/00
Filed: 2002-06-19
Granted: 2003-07-01
Abstract: Air conditioner including a main chassis 100 which forms an outer shape, a heat exchanger 150 in the main chassis 100, for heat exchange of room air with a working fluid, a blower 160 in the main chassis 100 for forced circulation of room air toward the heat exchanger 150; and discharge means in the main chassis 100 movable into/out of the main chassis 100 for discharge of air into a room.
Patent TW-558841-B (TW)
Title: Method of manufacturing semiconductor device and semiconductor device
Inventor: KIMURA MASATOSHI
IPC: H01L31/0352
Filed: 2002-08-13
Granted: 2003-10-21
Abstract: Photolithography is used to form a photoresist (30) having an opening over an end portion of a gate structure (15) and over a region adjacent to the gate structure (15) where a photodiode (18) is to be formed. Next, using the photoresist (30) as an implantation mask, vertical implantation of N-type impurities (31) such as phosphorus is performed at an energy of 300 to 600 keV and a dose of 1E12 to 1E14 ions/cm<2>, thereby forming an N-typeimpurity-introduced region (17) in an upper surface of a P well (11). At this time, the N-type impurities (31) can penetrate through the gate structure (15) to enter into the P well (11), allowing the N-type impurity-introduced region (17) to be also formed under the gate structure (15).
Patent TW-I223082-B (TW)
Title: Method for judging pass or fail of capacitor
Inventor: KAMIYA TAKESHI
IPC: G01R31/12
Filed: 2002-09-05
Granted: 2004-11-01
Abstract: The subject of the present invention is to shorten the examination time for reducing the manufacturing time and manufacturing cost. An electric current iall generated during charging is divided into a plurality of electric current components icap, iline, and ileak mutually different in an electric current change; and an approximation formula showing their current changes with the lapse of time is formed. The judgment reference current component ileak serving as a reference of pass or fail judgment of the capacitor is extracted from a plurality of the electric current components icap, iline, and ileak; and a pass or fail judgment condition is set on the basis of the approximation formula. The judgment reference electric current component ileak contained in the charging current of the capacitor to be judged is compared with the pass or fail judgment condition so as to determine whether the capacitor to be judged is good or defect.
Patent TW-I227268-B (TW)
Title: Polishing composition and polishing method employing it
Inventor: TAKAMI SHINICHIRO
IPC: C09C1/68
Filed: 2002-10-18
Granted: 2005-02-01
Abstract: A polishing composition comprising the following components (a) to (c): (a) colloidal silica; (b) at least one bicarbonate selected from the group consisting of ammonium bicarbonate, lithium bicarbonate, potassium bicarbonate, sodium bicarbonate and a mixture thereof; and (c) water; wherein the concentration of each of the elements included in groups 2A, 3A, 4A, 5A, 6A, 7A, 8A, 1B and 2B, lanthanoid and actinoid, and the concentration of each element of aluminum, gallium, indium, thallium, tin, lead, bismuth, fluorine and chlorine, are at most 100 ppb in the polishing composition, respectively.
Patent TW-582108-B (TW)
Title: Electrostatic discharge protection circuit and its design method
Inventor: YU TA-LEE
IPC: H01L23/60
Filed: 2002-10-24
Granted: 2004-04-01
Abstract: The invented electrostatic discharge (ESD) protection circuit includes the followings: a chip having an input/output device region for receiving the first power and a core device region for receiving the second power, in which the core device region has the bonding pad coupling with the second power; and an NMOS transistor with its source connected to a ground level. The protection circuit is connected between the chip and the bonding pad, and is provided with a PMOS transistor having a gate connected to a ground level, a source connected to the second power, and a drain connected to the gate of the NMOS transistor.
Patent TW-580706-B (TW)
Title: Semiconductor memory
Inventor: SHINOZAKI NAOHARU
IPC: G11C11/406
Filed: 2002-11-07
Granted: 2004-03-21
Abstract: In response to a refresh request generated at a predetermined cycle, a refresh signal is outputted to perform refresh operation. When an access request and a refresh request conflict with each other, the refresh operation is completed. This enables an earlier initiation of access operation, resulting in shortening of the access time. Changing the completion time of the refresh operation in accordance with supply timing of the access request can further shorten the access time. Forming a test circuit for notifying a state of the refresh operation to exterior realizes evaluation of operation margin of the refresh operation in a short time. As a result, it is possible to reduce a developing period for semiconductor memories.
Patent TW-I228054-B (TW)
Title: Selective catalytic reduction of NOx enabled by side stream urea decomposition
Inventor: SUN WILLIAM H
IPC: F01N3/28
Filed: 2002-11-15
Granted: 2005-02-21
Abstract: A process for reducing the concentration of nitrogen oxides in a stream of combustion gases, comprising: providing a side stream of gases at a temperature of at least 140 DEG C; introducing an aqueous solution of urea into said side stream under conditions effective to gasify said aqueous urea; introducing said side stream of gases containing the gases resulting from the gasification of the urea into a primary stream of NOx-containing gases of greater volume than the side stream to create a combined gas stream; and passing the combined gas stream through a NOx-reducing catalyst under conditions effective to reduce the concentration of NOx in the combined gas stream.
Patent TW-I249511-B (TW)
Title: Method for adhering transparent materials, and adhered quartz glass plate and apparatus using the same
Inventor: ONUKI HIDEO
IPC: C03C27/10
Filed: 2002-12-27
Granted: 2006-02-21
Abstract: As a method for adhering, easily at room temperature, materials which are transparent to shorter wavelength ultraviolet rays, such as quartz glass plates, with each other, to provide a transmission through the adhered portion to the short wavelength transmission limit inherent to the quartz glass or the like, there is provided a method in which two materials are adhered by using an alkoxide as an adhesive material and irradiating the portion to be adhered with ultraviolet rays. A large area quartz glass plate can be manufactured by adhering quartz glass plates in the lateral direction. The large area quartz glass plate can be used as a window pane to separate a radiation source portion and a cleaning chamber in an UV as her.
Patent TW-I225813-B (TW)
Title: Polishing pad, process for producing the same, and method of polishing
Inventor: FURUKAWA SHOICHI
IPC: B24D11/00
Filed: 2002-12-27
Granted: 2005-01-01
Abstract: The present invention provides a polishing pad for polishing the surface of a wafer for semiconductor integrated-circuit formation thereon, which has a high polishing rate, attains evenness of polishing, and has a long life. The polishing pad that is suitable for the present invention comprises a nonwoven fabric (base) and a non-porous photocured resin filling the spaces among fibers of the nonwoven fabric. It is obtained by: impregnating the base with a photosensitive resin composition comprising at least one member selected from the group consisting of hydrophilic photopolymerizable polymers or oligomers and hydrophilic photopolymerizable monomers; and then photocuring the composition.
Patent TW-I271246-B (TW)
Title: Electrolytic processing apparatus and method
Inventor: MORI YUZO
IPC: B23H3/08
Filed: 2003-01-07
Granted: 2007-01-21
Abstract: There is provided an electrolytic processing apparatus and method that can effect processing of a substrate with high processing precision and can produce an intended form of processed substrate with high accuracy of form. The electrolytic processing apparatus includes: a holder for holding a substrate; a processing electrode that can come close to the substrate; a feeding electrode for feeding electricity to the substrate; an ion exchanger disposed in the space between the substrate and the processing electrode, or the substrate and the feeding electrode; a fluid supply section for supplying a fluid into the space; a power source for applying a voltage between the processing electrode and the feeding electrode; a drive sections for allowing the substrate and the processing electrode, facing each other, to make a relative movement; and a numerical controller for effecting a numerical control of the drive sections.
Patent TW-I254946-B (TW)
Title: Semiconductor memory apparatus simultaneously accessible via multi-ports
Inventor: OKUYAMA YOSHIAKI
IPC: G11C5/02
Filed: 2003-01-29
Granted: 2006-05-11
Abstract: A dual-port semiconductor memory apparatus constructed by a core circuit and a plurality of ports, different row blocks of which in the same column block of the core circuit are simultaneously accessible. Since each of the ports is provided with a global data bus, different row blocks of the same column block can be accessed via both ports by selectively activating a column line corresponding to a port and another column line corresponding to another port.
Patent TW-579548-B (TW)
Title: Semiconductor device having gate with negative slope and method for manufacturing the same
Inventor: BAE GEUM-JONG
IPC: H01L21/265
Filed: 2003-02-11
Granted: 2004-03-11
Abstract: A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.
Patent TW-I269052-B (TW)
Title: Ionospheric error prediction and correction in satellite positioning systems
Inventor: PANDE ASHUTOSH
IPC: G01S19/07
Filed: 2003-02-13
Granted: 2006-12-21
Abstract: A GPS server capable of receiving information for use in determining ionospheric errors using mathematical formulas and sending ionospheric error correction information to GPS receivers that are in a location capable of receiving the ionospheric error correction information.
Patent TW-I276922-B (TW)
Title: Position detecting method, surface shape estimating method, and exposure apparatus and device manufacturing method using the same
Inventor: MAEDA KOHEI
IPC: G03F7/20
Filed: 2003-03-06
Granted: 2007-03-21
Abstract: A position detecting system including a detecting system for detecting positions, at different points on a surface of a reticle having a predetermined pattern formed thereon, with respect to a direction substantially perpendicular to the reticle surface, wherein the detecting system includes a light projecting portion for directing light from a light source to the reticle surface and a light receiving portion for receiving reflection light from the reticle surface, and wherein the angle of incidence of light from the light projecting portion, being incident on the reticle surface, is not less than 45 degrees.
Patent TW-I263275-B (TW)
Title: Method of passivating of low dielectric materials in wafer processing
Inventor: TOMA DOREL IOAN
IPC: H01L21/306
Filed: 2003-03-11
Granted: 2006-10-01
Abstract: A method of passivating silicon-oxide based low-k materials using a supercritical carbon dioxide passivating solution comprising a silylating agent is disclosed. The silylating agent is preferably an organosilicon compound comprising organo-groups with five carbon atoms such as hexamethyldisilazane (HMDS) and chlorotrimethylsilane (TMCS) and combinations thereof. The silicon oxide-based low-k material, in accordance with embodiments of the invention, is maintained at temperatures in a range of 40 to 200 degrees Celsius, and preferably at a temperature of about 150 degrees Celsius, and at pressures in a range of 1,070 to 9,000 psi, and preferably at a pressure of about 3,000 psi, while being exposed to the supercritical passivating solution. In accordance with further embodiments of the invention, a silicon oxide-based low-k material is simultaneously cleaned and passivated using a supercritical carbon dioxide cleaning solution.
Patent TW-I250147-B (TW)
Title: Method for decomposition of Michael type adduct
Inventor: SHIBUSAWA FUMIO
IPC: C07C51/377
Filed: 2003-03-24
Granted: 2006-03-01
Abstract: A method for the decomposition of a Michael type adduct of an acrylic acid and/or an acrylic ester represented by the following formula [I] or [II] is disclosed, wherein decomposing the Michael type adduct in the presence of at least one copper salt and at least one metal salt selected from the group consisting of an alkali metal salt and an alkaline earth metal salt into an acrylic acid and/or an acrylic ester and/or an alcohol. CH2=CHCOO(-X-COO)n-R1 [I], R2-O(-X-COO)m-R3 [II], (wherein n and m denote an integer in the range of 1-5, R1, R2 and R3 independently denote a hydrogen atom or an alkyl group, and -X- denotes -CH2CH2-or-CH (CH3)-, and -X- may be identical or different when n is 2 or more).
Patent TW-I282285-B (TW)
Title: Sustained release of guaifenesin combination drugs
Inventor: DAVIS ROBERT D
IPC: A61K/
Filed: 2003-04-15
Granted: 2007-06-11
Abstract: The invention relates to a novel pharmaceutical modified release formulation of guaifenesin and optionally a second drug which is preferably selected from dextromethorphan and pseudoephedrine. The formulation may comprise a hydrophilic polymer, preferably a hydroxypropyl methylcellulose, and a water-insoluble polymer, preferably an acrylic resin, in a ratio range of about one-to-one (1:1) to about nine-to-one (9:1), more preferably a range of about three-to-two (3:2) to about six-to-one (6:1), and most preferably in a range of about two-to-one (2:1) to about four-to-one (4:1) by weight. This formulation capable of providing therapeutically effective bioavailability of guaifenesin for at least twelve hours after dosing in a human subject. The invention also relates to a modified release product which has two portions: a first portion having an immediate release formulation of guaifenesin and a second portion having a sustained release formulation of guaifenesin, wherein one or both portions further comprises dextromethorphan. The modified release product has a maximum guaifenesin serum concentration equivalent to that of an immediate release guaifenesin tablet, and is capable of providing therapeutically effective bioavailability of guaifenesin for at least twelve hours after dosing in a human subject.
Patent TW-I230758-B (TW)
Title: Stroke determination method of internal combustion engine and stroke determination device using the method
Inventor: KONDO SEIJI
IPC: F02D45/00
Filed: 2003-04-16
Granted: 2005-04-11
Abstract: To provide a stroke determination method of an internal combustion engine whereby a stroke determination of the engine can accurately be performed without the use of a cam angle sensor and also the engine can precisely be controlled with high correlation with respect to an actual intake air amount after the stroke determination, and a stroke determination device using the method. An intake pressure sensor 21 detects an intake pressure affected by intake air pulsation in an intake passage 6 during operation of an engine 3. An ECU 20 detects a lower limit value of the pulsating intake pressure and turns a detection flag thereof to an ON state. The ECU 20 also detects a TDC (top dead center) signal of the engine 3 from a rotational speed sensor 23. Upon detection of the TDC signal while the lower limit detection flag is in the ON state, the ECU 20 determines that the detection time corresponds to a compression top dead center.
Patent TW-594934-B (TW)
Title: Method of fabricating a semiconductor memory
Inventor: LIU CHIA-CHEN
IPC: H01L21/3205
Filed: 2003-07-09
Granted: 2004-06-21
Abstract: A method of fabricating a semiconductor memory. Conducting line layers, a conductive layer with first type ion doping, a first dielectric layer and a conductive layer with a second type ion doped are sequentially formed on a substrate. The conducting line layers, the conductive layer with a first type ion doping, the first dielectric layer and the conductive layer with a second type ion doping are defined along a first direction, wherein the conducting line layers are defined as a first conducting line. The conductive layer with first type ion doping, the first dielectric layer and the conductive layer with a second type ion doping are defined to form a memory cell. A blanket second dielectric layer is deposited on the substrate, wherein before the deposition of the second dielectric layer, a pre-oxygen sputtering process is exerted to bombard the substrate. The blanket second dielectric layer is polished until exposing the memory cell. A second conducting line, electrically connected to the memory cell, is formed on the second dielectric layer along the second direction, wherein the first direction and the second direction are perpendicular to each other. Thus the semiconductor memory is obtained.
Patent TW-I236107-B (TW)
Title: Semiconductor chip package and method for making the same
Inventor: LAI YI-SHAO
IPC: H01L23/28
Filed: 2003-07-29
Granted: 2005-07-11
Abstract: A semiconductor chip package includes a lead frame, a semiconductor chip and a package body. The lead frame has a plurality of inner leads, a plurality of outer leads and a die pad. The inner leads define a horizontal plane. The semiconductor chip is disposed on the die pad and has a plurality of bonding pads on an active surface thereof. The bonding pads of the semiconductor chip are electrically connected to the inner leads of the lead frame. The package body encapsulates the inner leads and the semiconductor chip. The present invention is characterized in that the die pad is downset to a position within the package body to allow the active surface of the semiconductor chip to be coplanar with the horizontal plane, and the thickness of the package body located above the horizontal plane is substantially equal to the thickness of the package body located below the horizontal plane. The present invention further provides a method for manufacturing the semiconductor chip package.
Patent TW-I222226-B (TW)
Title: Manufacturing method of thin-film transistor
Inventor: WU YING-MING
IPC: H01L29/786
Filed: 2003-08-05
Granted: 2004-10-11
Abstract: A manufacturing method of thin-film transistor is disclosed, which comprises: forming a gate lead structure on a substrate by a first exposing/developing/etching process; forming a source, drain and semiconductor channel by a second exposing/developing/etching process; forming an island-like transistor structure by a third exposing/developing/etching process; forming a passivation layer having a contact hole by a fourth exposing/developing/etching process; and forming a pixel electrode connected to the contact hole by a fifth exposing/developing/etching process.