Patent GB-1023320-A (GB)
Title: Memory system
Inventor: ANDERSON JOHN LEANDER
IPC: G11C15/06
Filed: 1963-09-20
Abstract: 1,023,320. Electric digital data-storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 2, 1964 [Sept. 20, 1963], No. 37028/63. Heading G4C. A memory system comprises a plurality of word registers, a main current source for supplying a main current to an indicating circuit within each of the registers, a diverting circuit for selectively diverting the main current from the registers in response to address signals each defining an individual one of the registers, each indicating circuit having a plurality of current paths switchable from one condition to a second, the condition of any one path being determined by control signals supplied to the circuit and by the information stored in the register containing the path, the diverting circuit being arranged to divert the main current from an indicating circuit whenever all the paths thereof are in the second condition, and a switching circuit for applying the main current diverted from a register to read information into or from the register. The particular embodiment is a cryotron memory which can be addressed by co-ordinate selection, or operated associatively. Single bit storage device 14 (Fig. 4A, not shown)- This includes two cross-connected cryotrons 35, 36 (not shown) which ensure that a current flows in only one of two circuits respectively representing ZERO and ONE. Read-out is produced by energizing leads 49 and 26, the former including the gate conductors of two cryotrons in parallel, the control conductor of one cryotron being in lead 26 and that of the other cryotron being in the ONE circuit. Thus if ONE is stored, a voltage develops across the parallel circuit due to both cryotrons being resistive, but if ZERO is stored no such voltage develops. Switching networks.-Various switching networks used are shown in detail, e.g. Fig. 9A (not shown) shows network 15, comprising a cross-connected pair of cryotrons 71, 72 (not shown) by which current in lead 61 is constrained to follow one of two paths within the network. If line 62 is energized the current from lead 61 follows a path which renders cryotron 65 (not shown) resistive, thereby introducing resistance between leads 20 and 21. If, subsequently, lead 28 is energized the 61 current changes paths and the resistance is removed. Memory arrangement (Figs. 1A, 1B).-Figs. R 1A, 1B show word registers A, B . . . N each having a plurality of single bit storage devices 14. In the quiescent state of the memory, a main current from a source 18 flows through the registers in turn, via switching networks 10, and leads 20 and 21, and not along any alternative pathways all of which are rendered resistive by control unit 77. In each register, the current flows along one pathway interconnecting the leads 20 and 21 in each storage device 14 and also along such a pathway in the switching network 15. A register is selected by X, Y co-ordinate techniques to cause the switching network 10 associated with the register to introduce resistance into the lead 20 therethrough. The main current now by-passes the selected register and travels from terminal 19 (associated with that register) via switching network 11, terminal 23 and switching network 12 to the terminal 19 of the next register. If it is now desired to read data into the selected register, the lead 44 to every bit position where ONE is required is energized. Lead 66 is de-energized so that another superconducting path for the main current is established via leads 24 and 28 of the selected register. Lead 29 is then energized to render the direct connection between terminals 19 and 23 via switching network 11 resistive, thus shifting the main current in the selected register from the latter path to lead 24. This reads in the required data. Unit 77 now returns the memory to the quiescent state. Read-out, following co-ordinate selection, is similar to read-in except that lead 26 takes the place of lead 24, and all leads 49 rather than selected leads 44 are energized. Resetting (the whole register) is also similar to read-in, except that lead 25 takes the place of lead 24, and there are no leads corresponding to leads 44 involved. For a fully associative mode of operation, unit 77 controls switching networks 15 and 12, so that resistance is introduced into the interconnection between leads 20, 21 in each network 15, and each network 12 connects the adjacent terminal 23 to a common ground line 70 by a superconductive link, the connection between the adjacent terminals 23 and 22 being resistive. All the leads 59 are energized except those leading to storage devices 14 which must store a ONE to agree with the association pattern, and all leads 60 are energized except those leading to storage devices 14 which must store a ZERO to agree with the association pattern. (Thus both leads, 59 and 60, are energized for " masked " bits.) Therefore, in the first register which agrees with the association pattern, the main current can no longer flow through a superconducting path between leads 20 and 21 and is therefore shifted from network 10 to network 11 in that register. The main current continues via terminal 23 and network 12 to ground line 70 in which is connected a comparison indicator 75. Read-in, read-out or reset of this first register can now be performed as before, and incidentally produces a current in lead 28 of this register which restores the superconductive connection between leads 20 and 21 in network 15. This results in the next " agreeing " register being conditioned (main current shift from 10 to 11) for operation thereon when the control signal to the networks 13 is restored to the quiescent state after the operation on the first register. The whole memory can be reset in one operation by causing the main current to flow through all the registers in turn, from terminal 19 through leads 25, 28 and then via terminal 23 and network 12 to terminal 19 of the next register.