Patent GB-1201403-A (GB)
Title: Number and symbol display system
IPC: G09G5/00
Filed: 1968-10-29
Abstract: 1,201,403. Numerical displays. SONY CORP. 29 Oct., 1968 [2 Nov., 1967], No. 51142/68. Heading G4H. In a system for displaying a number and symbol (e.g. "-") coded digits are entered into a register 5, Fig. 1A, means are provided for distinguishing special codes representing redundant zeros above the highest significant digit from codes representing significant zeros in the number, and the display device has a plurality of positions each capable of displaying a digit or a symbol, the digit codes being read out from the register and sequentially applied to the display device to be displayed in the appropriate position, detecting means responsive to the code for a redundant zero providing a control signal at a digit time later by a predetermined number of digit times than the most significant digit to cause the symbol to be displayed at the corresponding position of the display device. In the form of Fig. 1A the digits are entered from a keyboard 1, being encoded at 2. After the digits have been entered, the register is filled up with redundant zero codes X from a generator 6. In operation the contents of the register are read out repeatedly and simultaneously re-entered via buffer 4. The word cycle has 7 steps, the seven positions of the display device are enabled synchronously so that the digits are displayed in the corresponding positions. The redundant zeros give no display. The symbol "-" is entered at a position nextbut-one to the highest digit. This is effected by the detector 8 which gives an output on line #C if a redundant zero code is detected and on line C if no such code is detected. The first C signal therefore appears in the fourth position adjacent the highest significant digit at the end of time t4 as shown in Fig. 1B. Gates A1, A2, enabled by the step pulse td set or re-set a flip-flop F1 according to whether the C or #C signals are present. The flip-flop outputs Q1 or #Q1 are delayed by one step time from signals C, C. Gates A3, A4 receiving signals Q1, #Q1 are enabled by step pulse td to set or re-set flip-flop F2. The output Q2 is therefore two step timee later than the highest significant digits and ths combination Q1, #Q2 defines the step t6. The symbol code is applied to the display device from encoder 2 and when it is present the line J is marked. Gate AD receiving Q1, Q2 and J provides a pulse in the fifth step time (t6) to cause the symbol "-" to be displayed. In the sixth position, in another form there is only one flip-flop F1 so that the symbol signal appears in the step following the highest significant digit and is displayed in the position adjacent to it. In a modified form (Fig. 3, not shown) the symbol "-" is displayed in the next-but-one position if there is room, but if the number has six digits, leaving only the seventh position, the symbol is displayed in this position. If the digits entered into the register are the result of a computer operation the redundant zeros will be entered as ordinary zeros as shown in Fig. 7A. To avoid displaying these redundant zeros a circuit is provided which changes all redundant zeros to the redundant zero code X during the first two circulations of the member in the store. For this purpose a counter 24 is arranged to count the digits and redundant zeros. After the first redundant zero (fourth place) which is detected by circuit 23. The counter has a capacity of six and on the seventh digit, which is the redundant zero which started the counter, it enables the redundancy code generator 25 to substitute the redundancy code X for all redtmdant zeros. The symbol "-" is inserted in the position next-but-one to the highest significant digit as before.