Patent GB-1417033-A (GB)
Title: Selecting of a time slot for transmission of pcm words
IPC: H04Q11/04
Filed: 1973-02-08
Abstract: 1417033 Automatic exchange systems TELEFONAKTIEBOLAGET L M ERICSSON 8 Feb 1973 [8 Feb 1972 (5)] 6346/73 Heading H4K In a TDM exchange incorporating a timespace-time network through which PCM channels are switched, preferably in a parallel format, a free time slot through the space switch is determined by examining all the time slots' on a calling incoming link to the switch and all the slots on the corresponding called outgoing link therefrom, and selecting one of the slots which is free on both links. The address of the called channel accompanies each data word through the space switch and is used to open the cross-point gate between the calling and called links. The network may be made non-blocking by providing a plurality of parallel TST networks between the incoming and outgoing highways of the system. General description.- Incoming highways carrying 32 channels of 8-bit serial PCM are multiplexed in sets of 4 to provide 128 channels of 8-bit parallel PCM, termed MUX-2 links. Two such links may be further multiplexed to obtain a 256-channel link without modification of the basic system which uses a 2À048 MHz clock as its pulse source. The channels on a link are written cyclically into associated cells of a time store, which cells are then read out acyclically to a cross-point network and from there are written acyclically into cells of another time store. Finally these cells are read out cyclically and their contents after demultiplexing and parallel/serial conversion are fed to outgoing highways. The network consists of a 256 x 256 cross-point array having one inlet and outlet per MUX-2 link. In a fully equipped exchange the latter links are of the 256 channel-type so that in order to ensure a non-blocking network four separate cross-point arrays must be provided with each link being multipled on four time stores, each of which has access to a different array (Fig. 5, not shown). Each data item extracted from the first time store is prefixed by its destination address which is decoded in the space switch so as to gate open the relevant cross-point. Synch./signalling.-In a 128 channel MUX-2 link the channels 0-4 serve for supervisory and control purposes e.g. path finding. (These channels of course correspond to the first, i.e. synch., channels on each of the four highways which form the MUX-2 link.) Speech or other data in 8-bit PCM format occupies channels 4-63 and 68-127. Signalling in respect of the speech channels is effected on a multiframe basis and uses channels 64-67 each of which includes 4-bit signal data relating to two channels of a same highway. The problem of separating this data if the two channels require routing to different outgoing highways is not considered. Any change of state of a signal word is noted by a computer coupled to the space switch in order to set-up, break-down &c. a connection in respect of the associated channel.  Operation, Fig. 4.-The channels of an incoming link MUX-2 are written cyclically into the cells of a memory SA during the first half of every time slot (#r=framing pulse, # = time slot 0-127 pulses, and #tp1 = first half of each slot). The link is identified by the suffix in-aa while the channels are identified by the symbol ia. During each successive time slot tp an index address memory IA is read so as to determine which cell of memory SA must be read-out during the second half (#tp2) of the slot, Simultaneously a destination address memory AB is cyclically read out so that the destination of a data item can be inserted on to a C in highway during the first half of the time slot being utilized for conveying that data through the space switch C. From the Figure it can be gathered that during slot 4 of a frame (see memory IA) the data word (actually a signal word) in cell 64 of memory SA must be routed to a signal receiver (sir in AB), while during slot 125 the word in cell 126 must be routed to outgoing link ab. The destination word occurring during each first half time slot is decoded in a decoder CA, of which there is one per row of the switching matrix, and used to open a gate, e.g. G5, which will permit the accompanying data word to reach a memory SB that is allocated to the required destination highway MUX-2 out ab. An index address memory IB which is cyclically addressed by the time slots in similar manner to memories IA and AB contains the identity of the cell into which each data word appearing on C out must be written during the second half of a time slot (#tp2 into gate G6). In the case of the considered slot 125, the cell address is also 125 in the example. Finally memory SB is cyclically read out on to the outgoing link MUX-2 during the first half of each time slot. The various outputs of the clock CG which have not been mentioned above serve functions such as multiplexing MUX-1 highways on to MUX-2 links and controlling signalling and path finding exercises. Path finding (Fig. 7).-The incoming and outgoing highways of a same MUX-2 link a are terminated on a box labelled ABal which contains the various memories and gates shown in the A stage and B stage boxes of Fig. 4. This link is coupled to the a row and to the a column of the space switch Cl as already discussed. A last look memory TM retains the condition of each channel. The memory is scanned in synchronism with the multiframe signalling format so that during a signalling channel-as denoted by the prefix address SR-the arriving signal word on row a is gated on to column sik and thence into comparator SIR. If there is any change in condition, i.e. free to calling, the computer DM is informed. Subsequent signal words for this particular calling channel are collated in order to obtain the address of the wanted outgoing channel. Once all the information is registered, the computer conveys the input and output channel addresses to a logic SL1 together with a request to set up a two-way connection therebetween. The logic applies to path finder AU which scans every time slot occurring on the row and the column pertaining to the two multiplexes involved (usually of course the calling and called channels will belong to different multiplexes) via the scanning column ak and scanning row ak respectively. Each slot is examined for absence of a prefix address and a data word. When a slot is discovered free on both the row and the column the logic is informed so that all the data relating to the considered call may be written into memory TM. Additionally, during the signalling word times of the calling and called channels the relevant address and time slot data are inserted into their multiplex control circuits using data insertion row or of the space switch. The logic and path finder are cleared for further use. Release of a connection is effected by writing zero into formerly used memory compartments during the channels' signalling time slots.