Patent GB-1268283-A (GB)
Title: Connect module
Inventor: CRAFT DAVID JOHN
IPC: G06F13/38
Filed: 1970-04-02
Abstract: 1,268,283. Data processing; data stores. INTERNATIONAL BUSINESS MACHINES CORP. 2 April, 1970, No. 15553/70. Headings G4A and G4C. A connect module comprises a plurality of groups of data input-output (I/O) conductors, a respective I/O register connected to each group of I/O conductors, parity generating circuits for generating the parity of data in the I/O registers, a plurality of data highways, and means for connecting any I/O register to any data highway whereby data can be transferred between selected I/O registers. The parity generating circuits are also used in parity checking. The module also contains a multi-row store each row of which can receive the contents of all the I/O registers, or load all the I/O registers. A shift register having a bit position for each row specifies which row or rows are to be accessed when read or write occurs, write being into each of the specified rows, and read being from all of the specified rows simultaneously with ORing of corresponding bits. The shift register can be loaded in parallel from outside the module and shifted in either direction. The module is controlled by microprogramme control signals from outside the module. Transfer in both directions between the I/O registers and the groups of I/O conductors (leading out of the module) is controlled for the different I/O registers independently. Several such modules can be connected for operation in turn or together, or an arrangement of such modules may interface between a main-store data register and the rest of a data processing system so as to provide control and diagnostic microinstructions read from the main store on different groups of conductors since the decoding required is different. A modified module also includes a module function control register which can be loaded from the multi-row store or the I/O registers, to control the module. Inter alia, bits transferred can be selectively inverted. The control register also specifies a direct address, a base address, a mask and the identity of an I/O register. A conditional address is constructed by obtaining each bit from the corresponding position of either this I/O register or of the base address, according to the corresponding bit of the mask. Either the direct or the conditional address is used to address the multi-row store to load the next control word into the control register, and the other address is used to address the multi-row store if a read or write function is called for during the next cycle. A modification (with a smaller multi-row store) has a bit in the control register to select half of the selected I/O register for use in forming the conditional address. Another modification uses control bits to select I/O registers whose contents are ORed to provide bits for the formation of the conditional address. The control register can be preloaded serial-by-bit from outside the module. Another modified module includes an I/O control register for each I/O register, loadable initially only and not when in use. Loading is serial-by-bit, the registers being connected serially as a shift register. Each I/O control register has a respective control line from outside the module to cause the respective I/O register to obey the command(s) in the I/O control register or not. Alternatively, three control registers can be provided for each I/O register, one or none being selected by external control signals to control the I/O register. I/O control registers can also be provided in the embodiment using the module function control register (see above) the latter register specifying for each I/O register separately whether it is to be controlled by a respective field of the module function control register, or by a first or a second further field of the latter register, or by one of the I/O control registers (which being specified). The data highways referred to above can OR corresponding bits of a plurality of I/O registers read out on to them together.