Patent GB-1352052-A (GB)
Title: Systems for processing information
IPC: H03M5/12
Filed: 1971-04-22
Abstract: 1352052 Digital data storage BURROUGHS CORP 22 April 1971 [6 May 1970] 10891/71 Heading G4C A system for processing data prior to its recording, e.g. on a magnetic tape includes a pulse generator 24 generating two interleaved trains of pulses 28A, 30B each having a frequency corresponding to the minimum allowed spacing of recorded transitions, a register 22 adapted to store the data to be recorded, a delay means 32 coupled to receive data serially from the register in response to pulses 30 of one of the pulse trains, a first means 56 responsive to the binary zero output of the delay and the pulses 28 of the other of the two trains to produce a first signal F, and a second means 42 responsive to the binary one output of the delay, the value of the bit at the output of register 22, and the pulses 30 of the said one of the pulse trains to produce a second signal E. General.-The first and second signals are recorded as transitions in opposite senses, e.g. on a magnetic disc 20, the first signal being developed on the occurrence of a binary zero at the delay (flip-flop 32) output and the second signal on the occurrence of a binary one at the delay output and at the output of the register 22, i.e. when the next bit to be recorded is also a binary one. The arrangement results in fewer recorded transitions and hence the recorded information density may be increased. Recording.-Register 22 is a shift register receiving data to be recorded in parallel and supplying the data in serial form to its output 40 in response to the clock pulses 30. The pulse generator 24 produces the two pulse trains Figs. 5A and 5B, the pulses 28 being generated directly from a clock track on the disc 20. Assuming a sequence 011010 (Fig. 5C) is stored in register 22 the system operates as follows. The trailing edge of the second pulse 30 in Fig. 5B, shifts the contents of register 22 one place and loads flip-flop 32 with the first bit, i.e. 0. The second pulse 28 enables AND gate 56 which passes a pulse to toggle flip-flop 62 via OR gate 58. The toggling of flip-flop 62 causes a transition to be recorded by transducer 34. The trailing edge of the next pulse 30 shifts the register 22 one place further and loads flip-flop 32 with the next bit, i.e. 1. The next pulse 28 does not cause gate 56 to pass a pulse since the flip-flop 32 stores a 1. However the next pulse 30 is conducted through gate 42 if the bit at the output of register 22 is a 1 which in this case it is. This pulse via OR gate 58 causes a transition to be recorded. The trailing edge of this same pulse 30 shifts register 22 and loads the flip-flop and the procedure continues. Reading.-Two reading circuits are described Figs. 7 and 9 (not shown) both of which read data recorded as above and also compensate for the fact that the recording does not position the transitions accurately due to head gaps &c. In both cases the reproduced waveform is fed to one input of a differential amplifier directly and to the second input of the differential amplifier via a delay having a period one half that of either one of the clock pulse trains. In one embodiment the amplifier output is clocked into a flip-flop and gates similar to gates 42 and 56 above produce data output signals. In the other embodiment two differential amplifiers are provided, the second amplifier being provided with the delayed input to the first as an input and a double delayed signal as its second input. A logic network connects the amplifier outputs to a clocked flip-flop. Further details.-The data source for recording may be a keyboard, e.g. in an accounting machine, or a magnetic tape. It is stated that the readout system may include capacitors charged according to the reproduced signal, the capacitor charges being compared at clocked intervals to generate data signals, no further details being given.