Patent GB-947529-A (GB)
Title: Improvements in or relating to electrical bistable circuits
IPC: H03K5/13
Filed: 1961-06-15
Abstract: 947,529. Transistor pulse delaying circuits. NIPPON ELECTRIC CO. Ltd. June 15, 1961 [June 21, 1960], No. 21655/61. Heading H3T. [Also in Division G4] A circuit for delaying incoming pulses by one half of a clock-signal period comprises two reciprocally-coupled transistors forming a bistable trigger circuit and means, controlled by a clock signal, for disabling the reciprocal coupling so as to convert the bi-stable trigger circuit into a simple on-off switching circuit in alternate half-clock-signal periods, whereby the reception of an input signal during a half period in which the reciprocal coupling is disabled switches the circuit from one condition to another which second condition is retained during the following half period, despite the discontinuance of the input pulse, due to the restoration of the reciprocal coupling. Negativegoing input signals, Fig. 2c, are applied to input terminal 3 during positive half cycles of sinusoidal clock signals applied to terminals 5 and 6 respectively. Thus, during these halfcycles diodes CR4, CR5 conduct so that the base electrode of transistor Q3 is held at voltage +E3 and the cross-coupling via resistor R6 from the collector of transistor Q2 to the base of transistor Q3 is rendered ineffective while simultaneously diodes CR2, CR3 are cut off and the voltage at point 7 takes up whatever value the input has at terminal 3, conduction being maintained in resistor R2, Zener diode RD1 and rectifier diode CR1 by the applied bias voltage +E4. The Zener diode RD1 adds a fixed positive voltage to that appearing at point 7 so that that applied by emitter-follower Q1 to the base of transistor Q2 is either negative or positive to the voltage, +E3, existing at its emitter electrode, depending on whether a negative-going input pulse is applied at the input terminal or not. Thus, if an input pulse is applied, transistor Q2 is rendered conducting and transistor Q3 non-conducting so that the voltage levels at output terminals 2 and 9, shown respectively in Figs. 2d and 2e change respectively in the negative and positive directions. During the alternate half cycles, diodes CR4, CR5 are non-conductive and diodes CR2, CR3 conductive. The potential at point 7 is consequently held at- E2 irrespective of the value of the input and the cross-coupling via resistor R6 is restored so that the circuit comprising emitter-coupled transistors Q2, Q3 functions as a bi-stable trigger circuit. This circuit consequently now exhibits electrical hysterisis in the input/output characteristic, the voltage now appearing at the base of transistor Q2 having a value within the loop portion of the characteristic curve, Fig. 3 (not shown), so that transistors Q2, Q3 retain whichever conductive state was established in the previous half cycle. It can thus be seen from curves 2d, 2e that the outputs appearing at terminals 2 and 9 are respectively delayed and inverted delayed replicas of the input applied to terminal 3. Diodes CR6, CR7, CR8, CR9 hold the output between - E2 and zero voltage levels. A plurality of such circuits connected in cascade with successive clock signals displaced in phase by 180 degrees functions as a stepping register, Fig. 4 (not shown).