Patent GB-916410-A (GB)
Title: Improvements in program devices
IPC: G06F9/32
Filed: 1959-10-09
Abstract: 916,410. Plugboard computers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 9, 1959 [Oct. 9, 1958], No. 34371/59. Class 106 (1). In a plugboard controlled computer in which operations are initiated under the control of a programme chain of hubs P 1 , P 2 , which are patched to hubs O 1 , O 2  specifying the kind of operation, a hub of the programme chain is energized at a time before the end of the operation initiated by the preceding hub of the chain, but the resulting control signal at the operation hub is not gated to computer control until the end of the operation now going on. At the end of the operation a signal on line DV opens gates such as 4 1  so that the signal from programme control 14 is immediately available to the operation control unit 4. This obviates loss of time due to the time taken for the signal from programme control 14 to travel along the patch cord linking the programme and control hubs. The computer comprises a magnetic core memory 2 storing eight-digit binary-coded decimal cords in location M 1 , M 2 , &c., and an accumulator 3 with a capacity of sixteen decimal digits, eight lower orders in a lower row of magnetic cores and the eight higher orders in an upper row. The machine is controlled by a unit 4 including an adder and the various circuits (described in Specification 916,409 to which reference is made) necessary for the performance of arithmetic and transfer operations. Unit 4 is switched by signals from operation hubs 0 1 , 0 2 , &c. Timing controls.-A generator 1 provides basic timing signals R, A and B and signals #R and A. Memory 2 scanning signals are provided by a chain 7b of latches stepped by the removal of the #R signal. Together with a pair of latches 7a, chain 7b defines an eighteen-interval time cycle T x , To, T 1  to T 16 . From Tx to T 9  line DL from unit 7a is up, at other times line DU. At times T 1  and To line D 1  is up, at times T 2  and T 10  line D 2  is up, and so on. A similar arrangement 9a, 9b of latches provides sixteen accumulator scanning signals on eight lines A 1  to A 9  during times T 1  to T 16 . The combination of a DX signal from unit 7b at time T x , with signal B and not complement signal #C operates latch 10 which issues a signal DV to open the gates 4 1 , 4 2  .... A memory unblocking latch 11 operated by DX, DV and #R signals issues a DM signal which is combined with an A signal to control reading from memory 2 and with a B signal to control writing into memory 2. The combination of, say, a D1 signal from unit 7b with an A.DM signal results in the read-out of the lowest order position of a memory location selected by patching a location hub M 1 , M 2  ... to the programme control hub. A similar arrangement leads to the read out of the accumulator 3. Latch 12 supplies a signal V and is actuated by a signal dv derived when DV goes off. Unit 13 provides a programme advance signal P.R at T 9 . Thus, at T 9  in every time cycle the next programme hub is energized but this is not gated to unit 4 until time T x  of the next time cycle. Operations.-In addition, a number in memory 2 at a location determined by energization of a hub M 1 , M  2  ... is added algebraically to the number in the accumulator, the sum being held in the accumulator. The sign of the accumulator is held in unit 4, that of the addend in memory 2. During times To to T 8  the digits of the addend are sent serially to the adder in unit 4 together with corresponding digits from the accumulator, and the digits of the addend are regenerated in memory 2. At the end of time T 8  latch 11 is turned off and no more transfers between memory and unit 4 can take place. Transfers between accumulator 3 and unit 4 continue until the end of the time cycle. If the operation at time T 16  does not result in a carry when subtraction takes place the  c  signal is suppressed, latch 10 does not go on to provide the DV signal. Another time cycle is gone through, againwithout transfer between memory 2 and unit 4 to enable the accumulator to be complemented. Figs. 15a and 15b (not shown) illustrate a slightly more complicated machine capable of multiplication and division (not described in detail) and of suppressing a programme stage as a result of a previous operation by means of transfer hubs. Specification 916,409 is referred to.