Patent GB-799667-A (GB)
Title: Improvements in digital differential analyzers
IPC: G06F7/66
Filed: 1954-10-21
Abstract: 799,667. Digital electric calculating-apparatus. BENDIX AVIATION CORPORATION. Oct. 21, 1954 [Nov. 6, 1953], No. 30356/54. Class 106 (1). In a digital calculator for integration and differential analysis comprising a set of storage sections, common computer means arranged to coact with each section to perform a fixed sequence of operations whereby in response to first and second input trains of pulses representing increments of an integrand variable (y) and a variable of integration (x) respectively, an output train of pulses is produced such that its effective rate at any time corresponds to the product of a number (y) cumulated from the pulses in the first train with the effective rate of the pulses in the second train, and means whereby the output train can be introduced as the first or second input train for one or more selected storage sections, partial corrective terms corresponding to successive increments of y are cumulated and stored for each section until the occurrence of a pulse representing an increment of x when the computer means algebraically adds the total cumulated value of the corrective terms to y, the cumulation and storage of the corrective terms then being resumed from zero. The computer described is generally similar to that of Specification 748,267 and includes a magnetic drum having in addition to the Y, R and clock pulse channels 14, 16 and 24, Fig. 1, two information precessing Z channels 20, 22 for indicating respectively the existence and polarity of y #x increments, and a further channel 18 containing corrective values corresponding to ¢ #y (where #x, #y represent increments in x, y respectively). Three similar read, erase and record coils, e.g. 26, 28 and 30, are provided for each of the channels 14, 16, 18, 20, 22. Channel 14, 16, 18 are divided into 22 successive integrator member sections I 1 -I 22  each the length of 48 clock pulses P 1 -P 48 , the pulse times and intervals I 2 -I 22  being marked off by clock pulse counters 60, 62 respectively. Simplified embodiment. The computing circuits, shown in simplified form in Fig. 1, comprise, as well as counters 60, 62, three sections described separately below: (i) a y-loop; (ii) a loop for cumulating the corrective terms ¢ #y; (iii) an integraing loop. (i) y-loop. The #y code pulses in positions P 1 -P 22  of a given memory section on channel 14, recirculated via gate 64, are fed to a gate circuit 72. Provided a code pulse coincides with a pulse from channel 20, a unit is added or subtracted in counter and stepping circuit 74 according to whether or not a coincident pulse is also obtained from channel 22. As soon as a bi-stable trigger circuit 66 (called " multivibrator ") has been operated to open gate 69, the number y from 14 is passed, together with #y stepped out of 74, to an adder 70 whose output, representing the new y-nurnber, is fed back to channel 14 via " or " network 68. (ii). Corrective-term-loop. A driver circuit 86 controlled by trigger 66 opens gate 88 after P 22  to allow the number on channel 18 to pass to adder 92 where it is combined with a further partial corrective term ¢ #y obtained by supplying the binary value cumulated in 74 one digit time earlier to 92 than to 70. The output of 92 is recorded on 18 only if gate 93 is open, indicating that a #x increment has not occurred. Such an increment is detected by applying the #x code pulses from channel 16 together with the pulses from channel 20 to a coincident-detecting circuit 95 whose output is used through inverter 94 to inhibit 93. (iii). Integrating-loop. The #x code pulse in one of positions P 1 -P 22  of a memory section on channel 16, recirculated via gate 116, is passed to Ax increment detector 95, as described above, whose output controls an adder 80. The y #x value is passed through gate 90 and is combined with the corrective term, obtained from adder 92, in adder 100 whose output is combined in adder 80 with the y-number obtained from adder 70. The new y #x value is fed back to channel 16 via gate 104 and any overflow pulse in position P 48  is passed through gate 106 to channel 20 the information in position P 1 -P 47  for this channel being recirculated through gate 118. If the overflow represents a positive increment, a pulse is recorded also, through gate circuit 108, on channel 22. Detailed embodiment. In the computing circuits described in detail (Figs. 5-8, not shown), the read coil for each information channel is connected to a bi-stable trigger circuit whose outputs provide direct and inverse indications of the binary information. The adder corresponding to 80 receives directly from channel 14 either y or its inverse according to the sign of the #x increment. The presence of absence of code pulses in positions P 2 , P 3  on channel 18 determines the form of the correction term. Normally, the term ¢# #y is added to or subtracted from y, depending on whether the integrator memory section under control of which the #y increments are obtained occurs later or earlier in the drum scanning cycle. Where two memory sections are employed together to obtain the product of two quantities, a correction term of - ¢ #y is used, i.e. the correction terms are prevented from being cumulated by the inhibition of a gate corresponding to 93, Fig. 1. When a memory section is used to compare two values, no correction term is used. Specification 751,101 also is referred to.