baber/WOPTO huggingface dataset:
Patent JP-S56111188-A (JP)
Title: Semiconductor storage device
Inventor: NAGAO KENICHI
IPC: G11C17/00
Filed: 1980-02-05
Abstract: PURPOSE:To speed up the information readout with a simple constitution, by applying the output of memory section to a sense amplifier via the voltage set means setting a voltage near the threshold value of the sense amplifier at precharge period. CONSTITUTION:FETs 13 and 17 of the memory 11 are respectively ON and OFF with the signal phiT1 at precharge period T1 for precharge and FETs 22 and 24 of a voltage set circuit 25 connecting the memory section 11 and the sense amplifier 16 via a capacitor 20 are both ON. Thus, the node 19 of the circuit 25 is set to somewhat low level than a threshold voltage Vth1 of the amplifier 26 and the output of the amplifier 16 is 0 volt, and the node 19 and the node 15 of the memory section 11 are coupled with the capacitor of a given potential difference. Thus, when the level change of the node 15 of the memory section 11 is started at readout, the voltage of a node 19 is immediately reached to the threshold voltage Vth1, allowing the readout of information by the sense amplifier with a simple constitution in high speed.
Patent JP-S62171971-A (JP)
Inventor: OGURI TAKEFUMI
IPC: C04B38/00
Filed: 1986-01-23
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S5397140-A (JP)
Title: Starting system for engine pump
Inventor: TSUDA YUUJI
IPC: F02D28/00
Filed: 1977-02-07
Abstract: PURPOSE: To ensure reliable and safe starting of the engine in cold districts by operating a tickler for a predetermined period of time with an electronic timer when a preset temperature is not reached by the temperature of the engine body. 
     COPYRIGHT: (C)1978,JPO&Japio
Patent JP-S59140691-A (JP)
Title: Dynamic ram
Inventor: YANAGISAWA KAZUMASA
IPC: G11C11/407
Filed: 1983-01-31
Abstract: PURPOSE:To obtain a dynamic RAM which stabilizes the reference voltage used for decision of an external input signal by providing a coupling capacity which offsets the effect of the fractuating component of the bias voltage of a semiconductor substrate to the output terminal of a reference voltage generating circuit. CONSTITUTION:Sense amplifiers SA are actuated all at once when a row address strobe signal RAS is changed to a low level, and therefore the data line of one side is set at a low level. As a result, the substrate bias voltage Vbb drops owing to the coupling to a semiconductor substrate, and accordingly the reference voltage Vref is also going to drop by said coupling. This state can be offset with a timing signal phipa2 which rises up to a high level and a capacity C3. At the same time, active restore circuits AR are actuated all at once to recover a data line DL of the high level side up to the level of power supply voltage. Thus the voltage Vbb raised up, and at the same time the voltage Vref is also going to rise up by the coupling. This state is offset with a timing signal phiref which is set at a high level and a capacity C4.
Patent JP-H03128457-A (JP)
Title: Method of visualizing reflection charac- teristics
Inventor: SUBUENTO AAGE RUNTO
IPC: G01N29/04
Filed: 1990-01-24
Abstract: PURPOSE: To produce a clear image of echo amplitude by withdrawing the length of a line part generated at a picture element for indicating a position in the direction of projection on the section of ultrasonic pulses that arrive at the position in a video image. CONSTITUTION: At least one ultrasonic probe travels on the surface of an object, at least one short-pulse ultrasonic energy is transmitted with a predetermined time interval, and echo pulses are received from inner heterogeneity. Then, a digital calculation means stores a digital signal containing information regarding the continuous position corresponding to an incidence point and the direction of the center axial line of acoustic beams and information regarding the amplitude of echo pulses and the length of an acoustic path to a reflection point for generating echo pulses from an incidence point when receiving the echo pulses. Then, the digital signal indicates a segment that is superposed on a shadow part image, thus indicating the shadow of a partial plane that passes through an object.
Patent JP-H03216756-A (JP)
Title: Time sharing computer system
Inventor: TSUKADA EIJI
IPC: G06F15/177
Filed: 1990-01-22
Abstract: PURPOSE:To execute with preference a specific command received from a specific terminal by attaining such constitution where a user instructs the executing priority at the time of executing SG (system generation) of a time sharing system. CONSTITUTION:An executing priority control instruction means 106 inputs the commands to each terminal 100 and sets the executing priority of these commands in an SG state of a time sharing computer system 10 which instructs the executing priority control for the process where the commands inputted from the terminals 100 are executed. At the same time, a process control means 107 registers the processes 101a which are executed by the commands received from the terminals 100 into a process state table 104. Then the means 107 executes the processes 10a in the order of higher priorities and decides the swap-out candidates for the processes 101a in the order of smaller priorities. Thus a specific command received from a specific terminal is executed with preference.
Patent JP-S58130003-A (JP)
Inventor: MURAMATSU SHIGEO
IPC: A43B13/38
Filed: 1982-01-29
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H09205555-A (JP)
Title: Image processor and its method
Inventor: EBIYA KENJI
IPC: G06T1/00
Filed: 1996-01-29
Abstract: PROBLEM TO BE SOLVED: To output a full color image at a high speed with small hardware resource even when only a limited color number is expressed by providing a component comparison means comparing colors selected by a selection means and each color component of a color image and an output means or the like providing any of colors selected by the selection means based on the comparison result by the component comparison means. SOLUTION: An object color storage means 104 provides an output of plural object colors represented by an object color number received from an object color selection means 110. A FIFO 128 stores tentatively an image read from an image memory 152 and synchronizes the image read from the image memory 152 with an output from the object color selection means 110 and an object color storage means 104. A component comparison means 112 compares the object color outputted from the object color storage means with each component of input color image data. An output means 114 outputs any component picture element of one of the object colors outputted from the object color storage means 104.
Patent JP-H08204888-A (JP)
Title: Facsimile equipment
Inventor: OOKI HIROHISA
IPC: H04N1/107
Filed: 1995-01-31
Abstract: PURPOSE: To obtain facsimile equipment provided with a cover opening and closing detection sensor with excellent detection accuracy. CONSTITUTION: In the recessed part of the recessed type block 41B on the side of a cover part 3, the transmission type sensor 52 provided with an actuator 51 is incorporated. When the cover part 3 is closed in a (c) direction, the projected part of a projected type block 41A provided on a book scanner part 1 is fitted to the recessed part of the recessed type block 41B of the cover part 3 and the cover part 3 is positioned. At the same time, the actuator 51 provided on the recessed part of the recessed type block 41B is pressed up and the closing state of the cover part 3 is detected by the transmission type sensor 52.
Patent JP-H08204978-A (JP)
Title: Vertical deflection system
Inventor: AKIYAMA YUKIO
IPC: H04N3/16
Filed: 1995-01-31
Abstract: PURPOSE: To suppress amplitude fluctuation in a vertical direction, to reduce the density modulation of a scanning line by a high voltage and to eliminate horizontal stripes by detecting the white signal period of video signals and performing input to a vertical amplitude compensation circuit. CONSTITUTION: The amplitude detection part 9 of a video signal amplitude detection circuit 5 outputs detection output only in the white signal period of input video signals, an output delay part 10 delays the detection output of the circuit 9 for the fixed period of time and the delayed detection output is added to the changeover switch 7 of the vertical amplitude compensation circuit 6. A feedback resistance value at normal time becomes the parallel synthetic resistance value A of a feedback resistor 3 and the feedback resistor 8 for vertical amplitude compensation. Then, the switch 7 is opened only in the period when the detection output is added and the feedback resistance value becomes the value B of only the feedback resistor 3.  Thus, by setting the ratio of the A and the B so as to cancel the vertical amplitude fluctuation by high voltage fluctuation of the white signal period, the horizontal stripes are eliminated.
Patent JP-S63181086-A (JP)
Title: Segment extracting system
Inventor: SASE SHINJI
IPC: G06K9/62
Filed: 1987-01-22
Abstract: PURPOSE:To improve a reading performance by applying direction codes more than the directions of extracted segments to an input picture, transforming them to the direction of the extracted segment, absorbing a large fluctuation to the direction of the extracted segment and executing a partial blurring transformation thereto. CONSTITUTION:The application of the direction code according to a quantizing level is executed by applying the number of the directions more than the directions of the segments required for the extraction to the input picture. At the time of forming a direction picture based thereon, when the direction of the extracted segment coincides with the direction code, it is directly defined to be the direction as it is and when the extracted segment does not coincide with the direction code, the direction code is defined to be both segments in two directions near to the code to form the direction picture. The partial blurring transformation applied only to a preset direction facilitates the extraction of the segment by preparing different masks according to the application, and the direction of the extracted segment and blurring-transforming the direction picture.
Patent JP-S63179758-A (JP)
Title: Drawing image control system of serial dot printer
Inventor: MIHARA OSAMU
IPC: B41J2/51
Filed: 1987-01-22
Abstract: PURPOSE:To effectively use a limited memory, to minimize the stand-by time of the image buffer of an image processing task and to shorten the processing time of a printer, by using the image buffer in a ring form. CONSTITUTION:The data sent from a higher rank host is received and decoded by a receiving task 7 to be delivered to an image processing task 8 in a processed form. On the basis of the data delivered from the receiving task 7, the data is developed on an image buffer 1 from a drawing address 4. When the development of the data of one line on the image buffer 1 is finished, a logical start address 2 and logical finish address 3 are delivered to a printing task 9 which in turn prints the image from the logical start address 2 to the logical finish address 3 to inform the finish of printing to the image processing task 8. In the image processing task 8, the image development of the next data can be performed before the arrival of the information of the finish of printing from the printing task 9.
Patent JP-S57126977-A (JP)
Title: Preparation of chromate treated steel plate
Inventor: NAKAMORI TOSHIO
IPC: C23C22/78
Filed: 1981-01-30
Abstract: PURPOSE:To enhance corrosion resistance by a method wherein a steel plate subjected to hot dipping in a Zn bath containing a specific amount of Al and Pb is subjected to chromate treatment by a chromate treating liquid containing a weak acid after cooled at a specific average cooling speed and burning is carried out corresponding to a Pb content of a plating film. CONSTITUTION:A steel plate is subjected to Zn hot dipping in a Zn bath comprising, on the wt% basis, 0.05-0.3 Al, 0.2 or less Pb and the remainder Zn and inevitable impurities. This steel plate is cooled at an average cooling speed of 20 deg.C/sec or more or, directly before a plating film begins solidification, a liquid containing a cooling medium is injected on the plating surface to cool the same. After cooling, the plated steel is subjected to chromate treatment in a chromate treating liquid containing a weak acid and, when a Pb content of the plating film is 0.1% or less, burning is carried out at 95-150 deg.C and, when 0.1% or more, carried out at 70-120 deg.C.
Patent JP-S60198101-A (JP)
Inventor: AKUSERU SHIYURUTE
IPC: A44B18/00
Filed: 1985-01-29
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S58129330-A (JP)
Title: Method for correcting instrumental error of positive displacement flow meter
Inventor: SHIMOZONO TOSHIAKI
IPC: G01F15/00
Filed: 1982-01-29
Abstract: PURPOSE:To enable to perform an adjustment over a wide flow rate range for  an instrumental error which is needed as flow meter by constituting the flow meter such that a brake is exerted on rotation of a rotor corresponding to instrumental error characteristics which a positive displacement flow meter has. CONSTITUTION:In case a flow meter has instrumental error characteristics not allowable within an instrumental error range necessary as a flow meter, an adjusting screw 25 is screwed in to compress a spring 24, and this causes a brake rod 23 to exert a friction force on a ring 20. As a result, a brake is exerted on a rotor 8 which is increased in a rotation resistance. Thus, in order to turn the rotor 8, a difference in pressure between a flow-in side and a flow- out side of a liquid to be measured increases, and the liquid to be measured leaking through a gap between a main body and the rotor 8 increases. This  enables the instrumental error characteristics of the positive displacement flow  meter to be brought to a instrumental error within a given range necessary as the flow meter over a wide flow rate range.
Patent JP-H09213947-A (JP)
Title: Semiconductor integrated circuit device for driving
Inventor: MIYAKE MINORU
IPC: H01L29/78
Filed: 1996-01-30
Abstract: PROBLEM TO BE SOLVED: To prevent the flowing of a leakage current due to the electric conduction of a parasitic transistor in the constitution circuit of a double diffused type MOS. SOLUTION: An n-type diffusion layer 10 having high concentration is formed among the n<+> type source region 7, n<+> type drain region 6 and p<+> type isolation regions 4 of a double diffused type MOS transistor in a shape that the peripheries of these source region 7 and drain region 6 are surrounded, and the drain region 6 is formed in a high-concentration diffusion layer. Accordingly, the hFE of a parasitic transistor is lowered, wasteful power consumption due to a leakage current is inhibited, and the increase of the potential of a p-type substrate 1 due to the leakage current is suppressed, thereby preventing the malfunction of a circuit.
Patent JP-S59140737-A (JP)
Title: Communication system by analog pulse modulation
Inventor: TSUSHIMA DANJI
IPC: H04B14/02
Filed: 1983-02-01
Abstract: PURPOSE:To improve the efficiency of utilization of a line by increasing a sampling period by R times and reducing the maximum frequency of a signal to be transmitted to 1/R. CONSTITUTION:When sampled values of a signal V(t) sampled at a period TS are transmitted to reconstitute the V(t) on a reception side, >=(n) sampled values are transmitted in a time nTS. The sampling period TS is equal to or larger than gamma0+etaV (where gamma0 is a minimum pulse interval, eta is a modulation constant, and V is a sampled value). Assuming that the equation holds, PPM (pulse position modulation) allows (n) sampled values to be transmitted. The maximum frequency of the signal to be transmitted is 1/2TS. The ratio R of nTS and the mean transmission time for the transmission of the (n) sampled values is nearly 0.74 when gamma0TS=0.1, so the remaining 26% time is allotted for another signal. On the other hand, it is possible to increase the sampling period by R and reduce the maximum frequency of the signal to be sent to 1/R.
Patent JP-H05204484-A (JP)
Title: Portable computer
Inventor: ISHIBASHI YASUHIRO
IPC: G06F1/24
Filed: 1992-01-29
Abstract: PURPOSE:To eliminate illegal use by a third person by judging the correctness of system using from given key information at the time of power supply of a main body of a device and making the normal processing of the whole device when the system using is not correct. CONSTITUTION:When a power source switch 6 becomes on, information of a key module 41 mounted in a key interface part 40 is read-in to confirm whether it is correct or not. When correctness is not confirmed, a power source control processor 2 set a random number decided by a random number generation means in a counter in RAM to start the counter, prepares a reset command after waiting for time corresponding to the set value and sends it to main CPU 11 by way of a power source control interface 28, etc. Thus, system processing is reset and the system comes into the state where a program board is necessary so that substantial processing becomes impossible. Thus, unfair using by the third person can be prevented.
Patent JP-S63186511-A (JP)
Inventor: EBARA TOSHIRO
IPC: H02B13/02
Filed: 1987-01-26
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S60157034-A (JP)
Title: Method for deciding knocking of internal combustion engine
Inventor: ANZAI KATSUSHI
IPC: G01M15/00
Filed: 1984-01-27
Abstract: PURPOSE:To eliminate the possibility of damaging an engine owing to deterioration in fuel consumption or generation of knocking by correcting a peak value or decision level for prescribed time when an intake control valve is opened or closed. CONSTITUTION:An ignition plug 20 attached to an engine body 14 is connected to a distributor 26. The distributor 26 is connected to an igniter 28. The outputs from a sensor 30 for discriminating cylinder and a sensor 32 for the rotating angle of engine are supplied to an electronic control circuit 34. The circuit 34 compares the peak value and decision level of the engine oscillation in the prescribed crank angle range after ignition and decides the generation of knocking. The peak value or decision level is changed in this stage for a prescribed time after an intake control valve 11 is opened from the shut state or a prescribed time after said valve is closed from the open state.
Patent JP-H09330892-A (JP)
Title: Manufacture of semiconductor device
Inventor: MATSUHIRO YASUSHI
IPC: H01L41/311
Filed: 1997-01-28
Abstract: PROBLEM TO BE SOLVED: To avoid becoming worse of processing accuracy of dry etching for a semiconductor wafer. SOLUTION: A prescribed region is etched from a first surface 30a of a silicon substrate 30 so as to form a recessed part 34 and to form a thin thickness part 35 on the bottom part of the recessed part 34. While supplying water vapor for reaction by filling the thermocuring type silicone resin 36 as a medium made of a thermally conductive material inside the recessed part 34, heat curing treatment at 100 deg.C and for 30min is performed. Later, a through hole 39 is formed through the thin thickness part 35 by performing dry etching of a prescribed region from a second surface 30b to the thin thickness part 35 in the silicon substrate 30. At the time of dry etching heat escapes through silicone resin 36 provided inside the ressed part 34. Then, silicone resin 36 is removed.
Patent JP-S59150420-A (JP)
Title: Manufacture of semiconductor device
Inventor: TSUJI TAKAFUMI
IPC: H01L21/28
Filed: 1983-01-31
Abstract: PURPOSE:To prevent the diameter of a contact-hole from being enlarged irregularly near the surface of a substrate and contribute to the prevention of current leakage and improvement of characteristics of the element and the like by a method wherein, after the 1st insulation film is accumulated on the substrate by CVD method, an aperture, which includes a whole region where the contact- hole is to be formed and does not include the boundary between an impurity doped region beneath the region mentioned above and the substrate, is formed in the accumulated film and then the 2nd inslation film is accumulated on the whole surface and the contact-hole is formed in the 2nd insulation film. CONSTITUTION:After a P<+> layer 12 is formed by doping an impurity into a part of the surface of an N type InSb substrate 11, a CVD-SiO2 film (the 1st insulation film) 13 is accumulated on the whole surface. Then, an aperture 14 is formed in the CVD-SiO2 film 13 using a resist (not shown in figures) as a mask. Then, a sputtered SiO2 film (the 2nd inslation film) 15 is accumulated on the whole surface. Then, a resist 16 for forming a contact-hole is formed on the sputtered SiO2 film 15 and the sputtered SiO2 film 15 is selectively etched by the solution of NH4F and HF using the resist 16 as a mask.
Patent JP-S59139540-A (JP)
Title: Ion implantation device
Inventor: NAKANO MOTOO
IPC: H01L21/265
Filed: 1983-01-31
Abstract: PURPOSE:To take out a necessary ion sort and to shorten a beam running distance while aiming at miniaturization of a device by providing a slit behind a deflecting magnetic field, shifting the slit in accordance with the deflecting quantity of an ion beam due to variations in the deflecting magnetic field, and by scanning the beam upon a sample. CONSTITUTION:An ion beam from an ion source 1 is accelerated by accelerating electrodes 3. A deflecting magnetic field is applied perpendicularly to a paper face to an ion beam 2 by an electro-magnet 4, and both mass analysis and scanning are performed. A slit plate 6 is disposed at right behind a deflection control circuit 5 for beam scanning and an electro-magnet 4 and the lengthwise direction of the slit is made perpendicular to the beam deflecting direction due to the electro-magnet 4. A driving device 7 to shift the slit plate 6 to its deflecting direction is provided. A rotary supporting table 9 to mount sample wafers 8 in circular arrangement is disposed right behind the slit plate 6, and is revolved by a motor 10. All the above mentioned mechanism is disposed in a vacuum chamber. Unnecessary ion sorts of different deflecting angles based on the difference in a mass are shielded by the slit plate 6.
Patent JP-S62172428-A (JP)
Title: Extracting system for form feature
Inventor: MAEDA YASUYUKI
IPC: G06F17/30
Filed: 1986-01-24
Abstract: PURPOSE:To efficiently control the collation processing of generation rule data base and generation rule by making an inference section collate only on a part of generation rule in the generation rule data base according to conceptional level of information relating to form feature included in short term memory. CONSTITUTION:A generation rule data base 1 stores generation rule for extracting form feature, classifies generation rule according to the level and kind of objective form feature and controls hierarchically. A generation rule assemblage selecting section 3 examines the level and kind of feature information included in short term memory 2 that holds information relating to form and selects corresponding set of generation rules. A generation rule set inputting section 4 reads the content of selected generation rule set from the generation rule data base 1, and a generation rule condition collating section 5 makes collating operation of conditional parts of read generation rule and the short term memory 2. When there are plural generation rules that satisfy the condition, one of generation rules is selected by a generation rule selecting section 6, and selected generation rule is executed by a generation rule executing section 7 and the short term memory is rewritten Thus, extraction of form feature can be made at high speed.