Patent GB-1447550-A (GB)
Title: Gaming machine
IPC: G06F19/00
Filed: 1973-09-19
Abstract: 1447550 Gaming machines G WACHTLER 19 Sept 1973 [20 Sept 1972] 43895/73 Heading G4V [Also in Division A6] A gaming machine arranged to simulate a game of poker comprises a display unit 15 with one indicating device for each card, a card memory 15 with one memory stage for each card, each stage being capable of being set into two memory conditions from a rest condition, the associated indicating device indicating the respective card has been dealt when the memory stage is in the first memory condition and the second memory condition serving to represent that the card has been returned by the player, a dealing unit 19 for randomly selecting and setting a pre-established number of said memory stages in said first condition, and a card return unit including, for each memory stage, means operable by the player to return a dealt card by switching over the memory stage from its first to second conditions. In the embodiment described thirty two cards are used, the seven to ace of each suit, and arranged in lines of the same suit and columns of the same value on the display unit. Coins inserted in a stake unit 11 are checked, totalled in reversible counter 14 and passed to a store and paying out device 27. One coin is required to initiate a game and for the return of each card. When the minimum credit is established the game may be started by depression of a push-button 37 which enables the dealing unit (Fig. 3, not shown) and resets all of the memory stages, e.g. T7, Fig. 2, to the rest condition. The dealing unit comprises an oscillator (65) which feeds pulses to a five-stage counter (67) each counting state of which is associated with a particular card and to a random pulse generator (69) the output of which is applied after frequency division to AND-gate 75 whose other inputs are selected outputs of counter (67) and outputs of the memory stage T7. AND-gate 75 is therefore only enabled if the counter (67) is at the appropriate counting state, there is an output from random pulse generator (69) and the memory stage is in its rest condition, and when so enabled memory stage T7 is set to its first condition by setting of flip-flop FF1a The corresponding card inidicating lamp 79 is illuminated and a pulse applied to the count input of a reversible counter 83, dealing continuing until the counter 83 registers five. After five cards have been dealt, up to three cards may be returned by depression of corresponding push-buttons 91 each of which closes a switch 93 to set flip-flop FF1b and reset flip-flop FF1a of the associated memory stage. As each card is returned the content of counter 83 is reduced by one and when the content reaches two the enabling signal KRS of the card return unit is removed. A second deal may then be started by depressing push-button 39. Any card returned cannot be reselected since the AND-gate 75 is now blocked by the signal from the memory stage. At the end of the second deal the contents of the memory stages are analysed by logical circuitry (Figs. 4a to 4f, not shown) to determine whether a winning hand has been dealt, the circuitry including a shift register (109) for determining whether the cards lie in two, three or five columns of the display, and gating circuits for detecting a sequence of five cards, three of a kind, four of a kind, any two aces and a flush. When a winning hand is detected a counter (149) is set according to the value of the hand and the content of the counter is then transferred to the counter 14. The sum accumulated in counter 14 may be paid out at any time by depression of push-button 153 which actuates a dispensing slide, each coin as it is dispensed being detected photo-electrically to produce a pulse which is fed back to the subtract input of the counter.