Patent GB-1113431-A (GB)
Title: Improvement relating to radar apparatus
Inventor: VOLES ROGER
IPC: H03M1/00
Filed: 1963-10-30
Abstract: 1,113,431. Pulse radar. ELECTRIC & MUSICAL INDUSTRIES Ltd. 30 Oct., 1964 [30 Oct., 1963], No. 42905/63. Heading H4D. [Also in Division G4] In a pulse radar the amplitude and/or phase of the individual cycles in an echo pulse are digitized into more than two discrete values. Amplitude analogue-to-digital conversion. Figs. 1, 7.-In one embodiment utilizing ten discrete values the echo signal at radio or intermediate frequency is fed at terminal I<SP>1</SP> to a chain of amplifiers A1 . . . A10, the gains of amplifiers A2 . . . A10 being 10/9, 9/8, 8/7 ... 2/1, the amplifiers are connected to threshold devices T1 . . . T10 all having the same threshold level, the threshold devices T2 . . . T10 are connected to taps on a delay line D0 via inhibit gates G2 . . . G10, and the inhibit inputs to the gates are fed from the delay line as shown. In operation the amplitude is indicated by the gate which produces an output and the first gate to produce an output inhibits all subsequent gates. Device T1 is connected directly to the delay line and if it gives an output (corresponding to signal amplitude of at least ten units) all the gates are inhibited. The total delay in the line is equal to that in passing between points C1 and C10. The signal amplitude is given in parallel in normal binary code form by connections to delay lines D1 to D4. Each threshold device may include a tunnel diode. If the required number of amplitude levels is N, there are 2<SP>N</SP> amplifiers in the chain and N delay lines for the binary code are required. In a modification, Fig. 5 (not shown), the radar signal is applied to a delay line taps on which lead to ends of resistors the other ends of which are connected to a line of increasingly-negative reference voltage. Centre taps from the resistors feed zero-sensing circuits (T1 . . . T10) each arranged to produce an output only when its input is zero or negative. The first zero-sensing circuit is fed to the first stage of a shift register the later stages of which are connected via inhibit gates to corresponding zero-sensing circuits. When a zero-sensing circuit produces an output it is applied via the corresponding gate to set the appropriate shift register stage to the " 1 " condition which is shifted along the register in step with the signal in the delay line (the shift register is an alternative form of delay line D0, Fig. 1). If the Nth zero-sensing circuit is the first to produce an output, gates (N + 1) to 10 are inhibited in turn by outputs from stages N to 9 of the shift register. Only one of the gates produces an output in response to one step of the waveform and such gate indicates the voltage of the step. Further delay lines as in Fig. 1 produce the binary signals. Circuits T1 . . . T10 correspond to ascending order of magnitude instead of descending order as in the first embodiment, Fig. 1. A zero-sensing circuit comprises the signal input terminal connected via a diode to an amplifier the output of which is connected to an inverting amplifier via a double-diode limiting circuit fed also from a positive voltage source, Fig. 6 (not shown). In a further amplitude analogue-to-digital converter, Fig. 7, the different bits of the binary word are generated serially; each signal component to be converted is compared successively with a series of reference signals which are reduced by a factor of two for each successive comparison and if a signal component exceeds a particular reference signal the latter is subtracted therefrom before being transmitted to the next comparator. Each comparator corresponds to a binary digit place and an indication that the signal component exceeds the particular reference signal is transmitted along a delay line to an output terminal, the length of each delay line being such that all the digital signals generated by a particular signal component appear at the output terminals simultaneously. Two comparator stages are shown in Fig. 7, only one of which need be described: it has input and output terminals 39, 40 respectively. The input signal is compared by equal resistors 24, 26 with the reference signal, of opposite polarity, from point 27 to switch monostable multivibrator 28 to the " 1 " state if greater. The multivibrator output forms the digit pulse applied to delay line D2 and is also added to the input signal as it emerges from delay line 23 to reduce the latter by the amount of the reference signal. Time interval digitizer, and counting, Fig. 2.- A number of ring counters RC1 . . . in parallel are utilized, the number of monostable stages M in a counter being a prime and the stages being connected by AND gates. The outputs of the stages of counter RC3 are applied to a set of AND gates for sampling by an interrogation signal applied to terminal 2; similar means (not shown) sample the other counters. Clock pulses are fed into terminal 1, and only after thirty (2 x 3 x 5) clock pulses are the MO stages of all counters again in the " 1 " state. The number which can be counted is the lowest common multiple of the stages in the counters and a seven-stage counter may be added. When used for radar echo phase measurement a signal of reference phase synchronized with the transmitted carrier phase starts the clock pulse generator or gates the clock pulses to the counters, or re-sets the counters (all MO stages in the " 1 " state), and the radar I.F. signal interrogates the contents of the counters: a digital signal is derived for each cycle of the I.F. signal and can be averaged over a number of cycles; or the digital signals derived during successive cycles of the I.F. signal may be compared to afford target radial velocity measurement. The digital signals do not form a conventional binary code: the code produced by each counter represents the remainder when the number of pulses applied is divided by the number of stages in the counter. To afford rapid counting each M stage incorporates a tunnel diode associated with a short-circuited delay line, Figs. 3, 4 (neither shown).