Patent GB-803431-A (GB)
Title: Transistor computer
IPC: G06F7/491
Filed: 1955-06-30
Abstract: 803,431. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 30, 1955 [July 1, 1954], No. 18916/55. Class 106 (1).  An electronic computer comprises networks of electronic means including transistors and connected circuits adapted to produce electrical manifestations selectively of different amounts received at an input, and a control circuit including transistors for manipulating said manifestations corresponding to the different amounts to secure arithmetic results based upon the values of the amounts and a selected arithmetical process, said control circuit including at least one cyclically operable electronic commutator arranged to provide a succession of voltage gate outputs and means for varying the number of such outputs delivered in each cycle. The machine described is manually settable to perform either multiplication or division, the two numbers involved being read from a record card and the result being punched into the same record card. The record cards are fed continuously, each card passing from a hopper to just before the reading brushes in a first machine cycle, under the brushes in a second cycle and through the punching station in a third cycle, the calculation being performed while the card is passing from the brushes to the punches. The card reading and punching mechanism is as described in Specifications 656,139 and 588,167, both of which are referred to. Throughout the machine transistors are used in combination with hard valves and crystal diodes to form triggers and gates. Multiplication.-Multiplication is effected by a series of repeated additions of a multiplicand, in accordance with successive multiplier digits alternated with denominational shifts. Each decimal denomination of the multiplier and multiplicand, both read from a record card, is registered on four triggers weighted 1, 2, 4, 8,  Figs. 3a, 3b, each register comprising only two denominations, the product is accumulated in a four-denomination accumulator PR, each denomination being adapted to accumulate in a decimal radix, and the additions are controlled by an A-commutator, comprising a ring of 6 triggers. Consider, for example, a multiplier of 53 and a multiplicand of 79, Fig. 7a. With these numbers registered in their respective registers, multiplication is initiated by a start pulse applied to the A-commutator on a lead 236 (see also Fig. 4), clock pulses being applied to an off lead 240. The commutator then performs successive cycles, Fig. 4, in each of which one addition is effected, until the multiplication is completed. During each cycle pulses are applied to the triggers 8, 4, 2, 1 of each denomination of the multiplicand register over leads 214, 212, 210, 208, the triggers being so constructed (see Fig. 15a) that they also function as gates, which results in the emission, from each denomination via a unit SEQ, of a serial train of pulses representing the digit registered therein, which pulses pass either via gates A and B or via gates C and D, constituting a column shift device, and thence over wires 296 (see Fig. 7a) to the PR accumulator. Simultaneously with the start pulse a pulse is applied on lead 272 to a switch SWI through which it passes to turn " on " a trigger CS4, which in turn opens gates A and B and a stepping pulse circuit, which passes pulses applied to it on a lead 310 (Fig. 7a) to the tens denomination of the multiplier register, which is thereby caused to advance negatively to zero. Thus during the first cycle of the A commutator the digits 7 and 9 pass through the gates A and B respectively and their component bits are distributed to the appropriate triggers of the hundreds and tens counters of the PR accumulator. Interdenominational carries in the PR accumulator are stored in triggers CY and propagated during the last two index points of the cycle. This occurs for the first five cycles, whereupon, the tens denomination of the multiplier register having reached zero, a signal is produced by a zero detector in that order, which together with a timing pulse on lead 276, results in the turning " off of trigger CS4, the turning " on " of a trigger CS3, the stopping of the tens stepping pulse circuit and the starting of a units stepping pulse circuit. Three further addition cycles follow, with gates C and D open, whereupon the units zero detector produces a signal which causes the A commutator to stop. The multiplier register is then standing at zero and the product is in the PR accumulator. The A- commutator includes switches SW1-SW4 and is so arranged that if any one bit does not appear in any denomination of the multiplicand, then the corresponding stage of the commutator is by-passed in each cycle. Division.-Division is performed by repeated subtraction of the divisor from the dividend until a negative partial dividend results, followed by repeated addition of the divisor, shifted one denomination, until a positive partial dividend results, followed by further subtractions and further additions, until the machine's capacity is exhausted. In the described embodiment, Figs. 10a-10e, arranged as in Fig. 11, the dividend, say 2072, Fig. 9, is registered in a dividend accumulator DD, the highest denomination digit always going into the 6th order, the divisor 37 is registered in true form in a divisor add register DRA, and in nines complement form in a divisor subtract register DRS, and the quotient is built up in a quotient register Q. Each addition and subtraction cycle is controlled by an A, and an S-commutator respectively, the carry stages CY1 and CY2 of the A-commutator being shared by the S-commutator. During each addition cycle and during each subtraction cycle except the first cycle of each series of subtraction cycles a stepping pulse is fed to a selected order of the Q register which is conditioned for reverse stepping during addition and for forward stepping for subtraction. In this way the quotient is built up. With the dividend and divisor registered division is started by a pulse on a lead 288 which sets " on " a column shift trigger CS6 which opens gates E, Q, U and K, and at the same time the S-commutator is started. During the first subtraction cycle the dividend subtract register is " scanned " by the S-commutator resulting in serial trains of pulses representing the nines complement of the divisor appearing on tens and units leads 264, which pulses are passed via gates Q and U to the 6th and 7th orders of the DD accumulator; simultaneously pulses representing 9 and 1 are produced by a complement circuit and passed over leads 270 and 268 to the 8th order of the DD accumulator and to the carry stage of the 5th order of the DD accumulator via gates E and K respectively. The net result is, as shown in Fig. 9, that the tens complement of the divisor is added to the dividend. As no carry is produced in the 8th order of the DD accumulator, the amount therein is negative. This fact is recognized by a carry/no-carry control device C/N-C which causes (a) column shift trigger CS5 to go " on " and trigger CS6 to go " off ", (b) the quotient register counters to be conditioned for reverse counting, and (c) the initiation of repeated additions of the divisor under control of the A-commutator. At this stage the Q register is still registering zero, there having been only one subtraction cycle. During the first addition cycle the divisor add register DRA is " scanned " by the A-commutator and the divisor is added to the DD accumulator via gates R and V. At the same time the 5th order counter of the Q register is stepped back one step by a pulse on a lead 312 from a stepping pulse circuit. Further during addition the carry/no-carry control unit is adapted to detect the presence of carries (as opposed to detecting their absence during subtraction)) and as no carry results from the 7th order of the DD accumulator during the first addition cycle, a further addition cycle ensues. Further addition cycles follow, until, during the tenth (see Fig. 9) a carry occurs from the 7th order of the DD accumulator which carry is effective to cause the carry/no-carry control device (a) to turn trigger CS4 " on " and trigger CS5 " off," thereby effecting a column shift, (b) to condition the Q register counters for forward stepping and (c) to initiate a subtraction cycle. The Q register is again registering zero, the 5th order thereof having been stepped backward ten steps, one in each addition cycle. During the six subtraction cycles which follow until no carry is produced from the 6th order of the DD accumulator, the 4th order Q counter is advanced 5 steps. This is followed by four addition cycles, one subtraction cycle and ten addition cycles, as shown in Fig. 9, after which division ceases with the Q register registering 005,400 representing the quotient of 207,200 and 37. The digits 6 and 1 remaining in the DD accumulator at the end of division are of no significance. as in multiplication, if any binary bit does not occur in any order of the divisor the corresponding stages in the A-commutator are skipped. Similar skipping provisions are provided in the S-commutator with the exception, that as a 1 and a 9 are always added during every subtraction cycle no means are provided for skipping the 1 and 8 stages. The MC-DRA register and the DRS register.- Each denomination of the MC-DRA and DRS registers, Fig. 15a, counts negative input pulses applied to a terminal 50 and provides both a static and dynamic indication of the count reached. Each stage of the MC-DRA register comprises a bi-stable-circuit including a transistor T2 connected between the screen and control grids of a pentode V2, as described in Specification 722,516, [Group XL (c)], two transistors T4 and T6 connected as described in Specification 751,595, both of which indicate, by the currents flowing in their collectors, the state of the bistable circuit, a