Patent GB-916392-A (GB)
Title: Transistor circuits
IPC: G11C19/28
Filed: 1960-02-01
Abstract: 916,392. Transistor pulse storage circuits. THOMPSON RAMO WOOLDRIDGE Inc. Feb. 1, 1960 [March 30, 1959], No. 3540/60. Class 40 (6). A circuit for producing a delayed pulse output in dependence upon applied input pulses comprises a transistor whose emitter-collector path is periodically energized by a train of regularly occurring pulses, the input pulses being applied to the base electrode in the intervals between the energizing pulses so effecting minority-carrier storage in the base and causing an output current to flow when the energizing pulses are applied in dependence upon the previous presence or absence of an input pulse. In the circuit of Fig. 1, pulses Ei, Fig. 2, are applied as input to the base electrode of NPN transistor 10 at the commencement of selected digit periods P1, P3. Energizing pulse Ec are applied regularly to the collector of the transistor 10 during an intermediate interval in each of the digit periods. By virtue of chargestorage q following upon the pulses Ei an output pulse dEi is developed only during those digit periods, e.g. P2, during which no input pulse is applied to the transistor. In an alternative circuit, Fig. 3 (not shown), having the load resistor connected to the emitter electrode, a delayed pulse output is obtained only during the digit periods in which an input pulse occurs. In the circuit of Fig. 5, the output dEi has the same form as the input Ei but is delayed by a whole digit period with respect thereto. Energizing pulses Ec, Ec<SP>1</SP> occuring respectively during the first and second halves of each digit period are applied to transistors 28 and 26 respectively. Input pulses Ei are applied to the base electrode of transistor 26 during the first halves of selected digit periods whereby a complementary signal dEi<SP>1</SP> delayed a half-period is produced at the output of transistor 26 and a signal dEi corresponding to the input delayed by a whole period is produced at the output of transistor 28. Pulses Ep and Ep<SP>1</SP> respectively synchronized with pulses Ec and Ec<SP>1</SP> are applied to the emitter circuits of transistors 26, 28 to discharge any remaining stored carriers immediately after the application of each respective energizing pulse. Diode 30 is inserted as shown, to prevent the input pulses Ei from being applied directly to the transistor 28 along the brokenline path shown. Figs. 7 and 9 show modifications of the circuit of Fig. 5, Fig. 7 representing an OR circuit in which an input pulse at either input 47 or 48 produces a corresponding delayed output at 50, and Fig. 9 an AND- circuit in which simultaneous inputs at 78 and 80 are required before a delayed output is produced at 82. Fig. 11 shows a two-state circuit. The application of a pulse a1 Fig. 12, to input 102 results in the generation of a delayed pulse A1 at output 104, this pulse being fed back to the input 102 over diode 117, so maintaining a continuous train of pulses. At this time no output pulses A1<SP>1</SP> are produced at output 106. On applying a second input pulses a1<SP>1</SP> to input 108, pulse dE<SP>1</SP> is produced owing to the resistor in the emitter circuit of transistor 105 and an output pulse A1<SP>1</SP> is likewise produced by transistor 107. At the same time transistor 103 ceases to produce output pulses A1 so that the pulses fed back to transistor 101 cease and pulses dE<SP>1</SP> continue to be produced by transistor 101 so maintaining the supply of pulses A1<SP>1</SP> at output 106 until another input pulse a1 is applied to input 102.