Patent GB-960452-A (GB)
Title: Data transfer apparatus
IPC: G06F3/08
Filed: 1961-04-07
Abstract: 960,452. Digital data-storage. RADIO CORPORATION OF AMERICA. April 7, 1961 [May 3, 1960], No. 12635/61. Heading G4C. In an arrangement for transferring data between a first and second store, each store having M rows and N columns, the data is read from the first store by rows and for each row read from the first store, the columns of the second store are read out successively, up-dated by the corresponding bit in the row read from the first store, the updated data columns being re-entered into the second store. The arrangement also provides for data transfer from the second to the first store. The apparatus described is for transferring data between a first store in the form of an 80 column, 12 row punched card and a second store in the form of a magnetic core matrix memory which stores data in the form of 6-bit characters (plus parity bit). Card to memory transfer. A punched card 14 is sensed photo-electrically at a sensing station 24, photodetectors 24a being effective to transfer the contents of a sensed row on the card to an 80- stage shift register 32. A timing device 26 synchronized with the card feed mechansim causes a master clock circuit 40 to produce 80 sets of clock pulses CP 1 -CP 5  for each row of data sensed. The CP 2  pulses are counted by a counter 44 which resets after a count of 80. The row of data in the shift register 32 is shifted serially therefrom, each bit as it is shifted being applied to a set of 12 AND gates 60, only one of these 12 gates being enabled corresponding to the particular row sensed from the card. The enabled gate 60 passes the bits shifted from the shift register 32 to a corresponding OR gate in a set of 12 OR gates 64 in sychronism with successive pairs of 6-bit characters from the memory 50, which characters correspond to the columns of the data stored on the card or in the memory 50. The pairs of 6-bit characters derived at the output of the OR gates 64 represent the up-dated columns and are returned to the memory 50 via a register 68. This procedure is repeated for each successive row read from the card. Checking arrangements. The data read from the register 68 is applied through parity generators 70 which generate parity bits, one bit for each six data bits, the data and parity bits being entered in the memory 50 at CP 4  clock times. The outputs of the register 68 are applied also to a set of check gates 74 which are connected to a comparator 78 (Fig. 5 not shown), the other input of which is supplied, via a second 80-stage shift register 30 with the data read from successive rows of the card 14 by a second sensing set of photo-cells 24b. If an inequality is detected, an error indication signal is produced. Memory to card transfer. A control flip-flop 20 is changed over to initiate read out from the memory 50 by enabling gates 82 connected to the outputs of the register 68. A timing device 84 in the card punch apparatus actuates the master clock circuit 40 to produce eighty sets of clock pulses CP 1 ..... CP 5  in response to each initiating pulse. Each CP 2  pulse causes read out of a different pair of characters from the memory 50 to the data register 68, the outputs being fed to the gates 82, the row counter 56 supplying an enabling signal to that gate corresponding to the row of data being read. The gates 82 supply a shift register 88 which, when filled with a row of data is supplied with a control pulse to gate the data to a punch driver 92. The punched data is sensed at 96 and compared with the data read from the store 50 in the comparator 78.