Patent GB-1263856-A (GB)
Title: Address translator
Inventor: HYNES DONALD PAUL
IPC: G11B5/02
Filed: 1970-04-30
Abstract: 1,263,856. Digital data storage. BURROUGHS CORP. 30 April, 1970 [23 May, 1969], No. 20809/70. Addition to 1,259,911. Headings G4A and G4C. A modification of the address translator of parent Specification is disclosed. The stores.-Four storage units make up a subsystem, each unit comprising four double-sided rotatable magnetic discs having binary coded decimal address data thereon. Each disc side has 150 tracks thereon comprising three zones of fifty tracks each. Each track is divided into segments, 78 segments/track on the inner zone tracks and 100 segments/track on the tracks of the two outer zones. The BCD address is converted to signals designating a storage unit, a disc face, a track, a zone, and a segment by successively subtracting (by 9's complementing) parameters representing the said signals from the address and counting the number of times each parameter can be subtracted in appropropriate counters 26 to 34. The first parameter is repeatedly subtracted until the remainder is too small, the next parameter is subtracted from the remainder etc. The counter readings select the appropriate head and the remainder of the successive subtractions in register 36 selects the disc angle of the address. Operation (Figs. 3A, 3B, not shown).-A BCD address is passed into shift register 14 and the step generator and control 42 shifts the address to adder 24 a digit at a time. Nothing is added thereto and if the result is measured to be zero by control 42 (i.e. the address was zero) address decoding is complete. If the address is non-zero, control 42 sets ASC 44 to a state corresponding to the parameter "segments per storage unit" which parameter comes from generator 18 (described later). The address (returned to register 14) is shifted out digit by digit and causes ADC 46 to count through a corresponding number of states. The parameter is to be subtracted so control 42 energizes subtract line 42b causing gate 20 to form the 9's complement of the parameter. The adder 24 adds the address and the 9's complement (plus a one for the least significant digit on the ADD 1 line) and the result goes to register 14. If a carry signal was formed on the carry line of the adder, the result of the subtraction was positive, the SU counter is incremented by one, and the cycle is repeated. If there is no carry the result of the subtraction is negative, hence the last subtraction is annulled by one addition of the parameter to the result. SU counter 26 now holds the segment address, ASC 44 is set to a state corresponding to the parameter "Segment per disc face", and the process repeated by successive subtraction from the remainder to increment counter 28. The same procedure is followed for the other parameters. At the end the counters select the head through a known selection matrix and the remainder goes to register 39 where it is compared in unit 38 with signals coming from the disc to determine the precise time for read/write (i.e. angular position). Parameter generator 18 (Fig. 2, not shown).- Different disc file formats, have different parameter types and a parameter printed circuit card is provided for each type. The ASC 44 identifies the parameter to be generated while ADC 46 forms the signals corresponding to the parameter digits. The arithmetic operations could be in parallel and the register 36 could be time shared with other similar apparatus.