Patent GB-1484162-A (GB)
Title: Data processing systems
IPC: G06F13/12
Filed: 1974-11-08
Abstract: 1484162 Data processing systems AMDAHL CORP and FUJITSU Ltd 8 Nov 1974 [19 Nov 1973] 48446/74 Heading G4A A data processing system for transmitting information between storage apparatus and input/ output devices over a plurality of channels comprises a channel unit including a store for information to be transferred, a state memory common to all channels having groups of locations, one for each channel storing a count indicating a remaining transfer length (which specifies the number of bytes of data remaining to be transferred over the channel) and data access control means which controls the decrementing of the count as transfer occurs. Channel control logic (403<SP>1</SP>, Fig. 2, not shown) includes memory addressing and priority allocation for determining which part of the logic is allocated to each channel. It comprises four sections; a state controller (428<SP>1</SP>) which receives an instruction for a specific channel and addresses and modifies one of the N store locations (one for each channel) in channel memory (448), a OP controller (429) for control word processing, a storage unit access logic (430<SP>1</SP>) and an access controller (432<SP>1</SP>) controlling transfer between channel memories (448) and input/ output controllers (411<SP>1</SP>). The channel memory is divided into three parts, (1) a shifting channel state store SCSO, 15 (Fig. 3), (2) a local channel store 406 including a channel buffer store and a sub-channel state store and (3) a sub-channel buffer store 408. The channel unit also comprises registers 404 including a 32-bit address register 464, a 32-bit data register 465, a 32-bit working register 466, a 13-bit local channel address register 467 and a 32-bit local channel fetch data register 468. When data is received into registers 404 through interface logic 407 it passes through data register 438 to local channel store 406 or sub-channel buffer store 408. When data is to be transmitted from registers 404 to the input/output devices it is accessed from the local channel store 406 and latched into local channel fetch data register 468 from which it is fed by a register 440 to the input/output device, one or two bytes at a time. The registers 404 are connected to a channel data manipulator 405, input bus 424 being connected to state registers (476, Fig. 4, not shown) flags (477) and a command register (446). The state registers form part of the input to OP controller (429<SP>1</SP>). Flags indicate when certain functions have occurred and have an input to the controller. The command register latches command words which are recoded and fed to the controller. The bus is also connected to logic (482) which controls and analyses sub-channel information stored in the sub-channel state store by causing access to the latter under the control o an address in device address register (479). This is incremented by a + 8 incrementer (480), a comparator (481) comparing the address of the device specified on the input bus (424) with the address in the register (479). Adder (483) receives an input from buffer byte count select circuitry (474), the latter receiving the low order bits (a 5-bit buffered byte count) of a 16- bit count field from the data access control register (430<SP>1</SP>). The adder receives control information, correct count, back up count, correct data, back up data, increment by 4 or increment by 8, from the OP controller, the output from the adder being fed to data manipulator output register 437 (Fig. 3) in the registers 404. The channel state memory comprises a shift register stage for each channel, the information being stepped along the stages at each clock cycle. The stage SCS2 in the section 430 is examined at each cycle to see if the channel that is currently associated with it has priority. If it has, the actual transfer length TA to be undertaken (1, 2, 3, 4 bytes) is fed as a 2-bit output from priority logic to a staging register (735, Fig. 6, not shown) the latter also receiving the 5-bit old buffered byte count and a 1-bit EX field which indicates whether any of the 11 high order bits of the count field are pre-set. The staging register is connected to an action register (736) controlling logic (739) which includes a comparator for comparing the transfer with the buffered byte count. If the transfer length exceeds this and EX is set, the high order bits are fetched from channel memory and modified. If the buffered byte count is less than or equal to the transfer length and EX is not set the transfer is complete. Operation.-A channel command word obtained from the instruction unit is transmitted under the control of the OP controller to the working register 466 from which it is transmitted via the data manipulator 405 and register 437 to local channel 406. As the command is fed through the data manipulator the 5 low order bits of the count field are additionally loaded into a register (470, Fig. 4, not shown) and the high order bits are OR'ed and used to form the EX signal, the buffered byte count bits and the EX signal being gated into register stage SCS2 when SCS1 contains the appropriate channel number. The data access control means is then ready to commence transfer when the appropriate channel obtains priority, the byte number information being fed to an action register (736, Fig. 6, not shown) for examination by action logic (739). If the low order bits of the buffered byte count are greater or equal to the transfer length a short sequence is effected for 4 byte transfer in which (1) for channel to store transfer, in cycles 1 and 2 the data address is fetched, in cycles 3 and 4 the data is fetched, in cycles 5 and 6 the data address is stored and cycles 7 and 8 are not used and (2) for store to channel transfer, in cycles 1 and 2 the data address is fetched, in cycles 5 and 6 the data address is stored, in cycles 7 and 8 the data is stored and cycles 3 and 4 are not used. The actual length is subtracted from the low order bits of the count field in the data manipulator to give a new low order count. If the low order count is less than the transfer length the sequence is extended by 2 cycles (that it is to 10 cycles) so that the high order bits of the count may be fetched and the modified count restored, all 10 cycles being used. The transfer continues until the low order bits of the byte count are zero and the signal EX is zero.