Patent GB-1490445-A (GB)
Title: Digital automatic gain control circuit
IPC: H03G3/20
Filed: 1975-08-22
Abstract: 1490445 Digital automatic gain control INTERNATIONAL BUSINESS MACHINES CORP 22 Aug 1975 [18 Dec 1974] 34885/75 Heading H4R In a digital automatic gain control system a multiplier 21 forms the product of an uncontrolled digital input signal S 0  and a digital gain control signal | s 1  | to form a gain controlled signal S 1 . The gain control signal [ s 1  | is derived in a loop in which the output of the multiplier 21, i.e. S 1 , is compared with a reference value s 2 , in adder 23, and the resulting error is accumulated in accumulator 28, 29 to form the gain control signal | s 1  | . The sign of the accumulator output s 1  is used, via a control loop and multiplier 24, to control the sign of the reference value s 2  in order that the error signal assumes alternate positive and negative signs during periods when the gain controlled signal S 1  is zero. As described, an analogue signal is sampled and converted, in A. to D. converter 20, to a 16 bit digital form in which the first digit indicates the signal sample sign (1=-ve, 0= + ve) and the remaining digits indicate the most negative or least positive by all "zero" and the least negative or most positive by all "ones". The full adder 22 with its zero second input and sign control performs an effective full wave rectification of the input signal about zero level (16 "zeros"), comparison with the reference s 2  in adder 23 provides the error signal e which is multiplied by a constant -k 2  in multiplier 26, the constant controlling the rate of the gain control. In addition the error signal from multiplier 26 is multiplied, in multiplier 27 with the gain control signal itself to cause the correction factor to be a fixed percentage of the input signal itself so that correction occurs at the same rate regardless of the actual level of the input signal SO. The output of multiplier 27 is applied to the accumulator formed by adder 28 and delay circuit 29 connected in a loop to provide a control signal s 1  which is multiplied by a factor 1-2<SP>-15</SP>, in 2's complement code, and full wave rectified in the full adder 31 to provide the gain control signal | s 1  | . The sign of the output of the multiplier 30 is used, together with inverter 32, to enable one or other of the generators 25-1 and 25-2 which control the sign of the reference signal s 2  so that s 2  = Œk 1 , depending on the sign of the output of the accumulator. This provides that, when the input So drops below the controllable range, i.e. S 0  < k 1  and the accumulator overflows, the accumulator is caused to oscillate directly between maximum positive and negative values without traversing the intermediate values, such as would occur if the loop including generators 25-1 and 25-2 were not included. The multiplier 30 is included to prevent a "-1" signal being applied to the full adder 31 since the corresponding rectified output of + 1 from the full adder is not a possible signal on the two's complement code. The use of the full adder 22 as a rectifier of the gain control output signal will stabilize the signal level so that its average value will be equal to the constant k 1 . By replacement of the full adder with a squaring circuit, Fig. 3B (not shown), the level will be stabilized at the RMS value.