Patent GB-1098329-A (GB)
Title: Data processing device
IPC: G06F9/46
Filed: 1966-06-27
Abstract: 1,098,329. Multi-processor computer: addressing memories. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 27, 1966 [June 30, 1965], No. 28651/66. Headings G4A and G4C. A data processing device has an address generator for concurrently generating a plurality of memory addresses, and a plurality of arithmetic units. General arrangement.-Sixteen arithmetic units each have an adder and a respective 36-bit row in each of an accumulator register (X), a multiplier-quotient register (Y) and a buffer register (Z). Two input rings are provided for selecting one of the odd-numbered and one of the even-numbered rows of the buffer register (Z) respectively. Output rings are provided similarly. Bits can be shifted along a row of the accumulator register (X) or the contents of rows can be shifted to other rows. Particular columns of the accumulator register (X) can be selected for input, output in true or complement form, or resetting. Similar controls could be provided for the multiplier-quotient register (Y) Transfers between these registers are possible. Various control registers are provided, having one bit position for each arithmetic unit. Programme control is common to all the arithmetic units and one of the control registers is used for specifying which of the arithmetic units are to respond to the currently decoded instruction. Obtaining operands from memory.-Sixteen operands for respective arithmetic units are located at addresses α + n8, where n = 0, 1, 2 . . . 15, in a core or thin-film memory. The instruction specified α and #, and two adders (A, B) derive the addresses with even and odd n respectively, successive outputs of the even adder (A) being fed as inputs to both adders to be added to 2# and # respectively. Each address has 18 bits, the low order 4 bits selecting one of 16 memory sections (" boxes ") having separate read-write circuitry and the other bits selecting a word in the selected section. The two addresses generated at a time are passed over respective buses to access memory simultaneously except that access is prevented if the required section is busy, as indicated by a respective " busy " flip-flop. In addition, if the two addresses ralate to the same section, as indicated by a comparison of their low order 4 bits, they are dealt with in turn and address generation is temporarily inhibited. The low order 4 bits of successive addresses on the two buses are stored in respective matrices (A, B) to ensure gating out of or into the memory sections in the correct order. Each matrix has an input and an output ring, each for selecting one 4-bit position therein. Data flows between the accessed memory word and the appropriate row of the buffer register (Z). In the case of a read operation, the read-out word may be an operand or provide an address for accessing the operand. Index registers are also provided. Other address generation schemes for generating 4 or more addresses at a time in a basically similar way but using more adders and one involving subtraction, are described. Restructuring operations.-In an EXPAND operation the contents of the accumulator register (X) are shifted between rows so that those rows whose bits in a control register (having one bit for each row) are zero are left empty. A COMPRESS operation is the reverse, the contents of rows having a zero control register bit being deleted and the contents of the other rows being shifted to close the gaps. In a MASK operation, the contents of those rows of the accumulator register (X) whose bits in a control register are one are replaced by the contents of the corresponding rows of the multiplier-quotient register (Y). In a SUM REDUCTION operation, the sum of those rows of the accumulator register (X) having a one bit in a control register is obtained. After alignment of radix points (see next section), the rows are shifted out together to a " counting network " (tree of AND gates) which thus receives all the bits of a given binary order together and sums them to give a 1-out-of-17 selection which is converted to binary form and passed into a tree accumulator which shifts before the next order arrives. In a SEARCH FOR LARGEST operation, the largest of the contents of those rows of the accumulator register (X) having a one bit in a control register is determined. A SEARCH FOR SMALLEST operation is similar. In these last two operations, " uppermost circuits " are used to detect the highest order one bit in a register. Standard arithmetic operations.-Floating point addition of signed binary numbers is described in detail, using separate exponent and fraction adders in an essentially conventional fashion, in each of the arithmetic units. Circuitry providing the two's complements of 1, 2, 4, 8, 16, 27 for exponent modification is used in common by all the arithmetic units. Radix points of operands may be aligned concurrently (i.e. the exponents made equal with compensating shift of the fractions), the largest exponent being identified and compared with the others to determine the amounts of shift to be given to the respective fractions. All the fractions to be shifted are shifted concurrently. Multiplication is by repeated addition and shift, under control of successive pairs of multiplier bits, multiplier bits 11 causing addition of the two's complement of the multiplicand and incrementing of the multiplier by one. Division is by successive subtraction and shift (of the fractions) after assuring that the fraction of the dividend is less than the fraction of the divisor by any necessary fraction shift and corresponding exponent modification. Subtraction is by complemented addition. Fixed point addition is also possible.