Patent GB-1046426-A (GB)
Title: Cryotron memory
IPC: G11C11/44
Filed: 1963-06-18
Abstract: 1,046,426. Superconductor circuits. GENERAL ELECTRIC CO. June 18, 1963 [July 5, 1962], No. 24214/63. Heading H3B. The basic bit storage circuit of a memory matrix is as shown in Fig. 2 and includes three cryotrons 21, 22, 23 connected as shown. A persistent current loop comprises a branch circuit 20 including the control of cryotron 22 and the gate conductor of cryotron 23. To write a " 1 " i.e. a persistent current in the loop, switch 26 is closed in write line 82 so that current from constant current sources 24 renders the gate of cryotron 23 resistive. A digit current I1 is then applied to the digit line 81 which flows entirely through branch circuit 20 since the gate of cryotron 23 is resistive. The write current and the digit current are turned off so that the gate of cryotron 23 becomes superconductive again and a persistent current is established in the loop circuit. To perform the read operation currents are applied to both the digit line 81 and the read line 83, the read line current rendering the gate of cryotron 21 resistive and since the gate of cryotron 22 is also resistive due to the stored persistent current, a voltage drop due to the resistance encountered by the digit current and indicative of a stored " 1 " is detected by voltage detector 28. To write a " 0 " i.e. no persistent current in the loop circuit, a current is applied to the write line 82 but no current is applied to the digit line 81. The gate of cryotron 23 is rendered resistive and any persistent current in the loop is dissipated. To read a " 0," digit and read currents are applied to the digit 81 and read lines 83 so that the gate of cryotron 21 is rendered resistive and since there is no persistent current in the loop the gate of cryotron 22 is superconductive. The digit current is therefore provided with a non- resistive path so that no voltage drop is registered on the detector 28. Memory matrix.-The memory matrix of Fig. 4 comprises rows and columns of the bit storage circuits of Fig. 2 and also an arrangement of cryotrons to the left of column 51(1) for directing a memory current M to the read or write line of a selected row of storage circuits. To write a word into the upper row of storage circuits selection currents S1 S2, S3 are applied to lines 41, 43, 45, rendering resistive the gates of cryotrons 52-58 and leaving a superconducting path for the memory current M to only the first row of storage circuits 51(1)-51(n). Digit current pulses D1-Dn are applied or not to lines 50(1)-50(n) according to whether a " 1 " or a " 0 " is to be stored. In order that the memory current M flows only through write line 61 a write current pulse W is applied to line 47 rendering read line 60 resistive. To read from the store, e.g. a word stored in the fourth row of the memory selection currents S1, S2 and S3 are applied to selection lines 41, 44, and 46, and a read current R is applied to line 48 rendering cryotron 62 resistive, so that read line 63 of the fourth row is the only row line which remains superconductive. Digit currents D1- Dn are then applied to the digit lines 50(1)- 50(n) and the memory current pulse M is applied to achieve the reading action as described with reference to Fig. 2.