Patent GB-1433070-A (GB)
Title: Amplifiers
IPC: H03G3/10
Filed: 1974-03-06
Abstract: 1433070 Transistor differential amplifier; analogue-to-digital conversion WESTERN ELECTRIC CO Inc 6 March 1974 [12 March 1973] 9992/74 Headings H3T and H3H In an amplifier including first and second transistors 40, 42 connected as a differential amplifier, the base of at least one of the transistors is for receiving an input signal 1, bias current is provided to the collector-emitter paths of the transistors, a biasing circuit 4-18 provides to the collector-emitter paths of the transistors 40, 42 supplemental bias currents I 4 , I 5  which vary together in the same sense in dependance on variations in magnitude of the input signal and a circuit 44-49 maintains the sum of the currents in the collector-emitter paths constant. The differential amplifier 40, 42 is shown in a current folder and coder circuit where a differential switch including Darlington pair transistors 27, 28; 30, 31; 33, 34 and 37, 38 functions to provide "folding" by obtaining single polarity input to a comparator 23 regardless of the polarity of the alternating signal input 1. Switching speed up diodes 29, 32, 36 and 39 also provide paths for transistor leakage currents to prevent coding inaccuracies. The coding of the analog input signal is obtained by comparing the voltages or currents proportional to the input with one of a plurality of reference voltages or currents generated by a weighting network 21. The results of this comparison are then fed to a logic circuit 26 for arrangement as a PCM word. A dynamic bias control circuit includes transistors 11 and 12 which function as a full wave rectifier and in the absence of an input signal transistors 4, 9, 15 and 16 conduct with I 1 =I 2  and I 3  and I 5  slightly less than I 6  and I 7 . A peak magnitude positive input 1 causes transistor 4 to conduct more so I 1  increases and transistor 11 is cut off and transistor 12 is conductive. This causes I 4  and I 5  to decrease to a negligible value. The peak magnitude positive input also increases the conduction of transistor 42 of the differential amplifier so that I 7  increases and I 6  decreases. For small magnitude positive input signals 1 the bias control circuit operates so that the currents I 4  and I 5  flowing through transistors 15 and 16 are proportional to the magnitude of the potential at the emitters of transistors 11 and 12; that is proportional to the magnitude of the input signal 1. As the current balance I 6 +I 7  is maintained constant at I 8  by a transistor 44 supplementing the currents I 9  and I 10  flowing into the weighting and coding network with currents I 4  and I 5  for the small magnitude input signals achieved the following. First the currents through resistors 22 and 25 of each arm of the weighting and coding network are not constrained to be equal to the constant bias I 8  which must be chosen for peak signal conditions. Instead I 9  and I 10  are proportional to only the instantaneous magnitude of the input and weighting network reference signals and hence the I#R error due to resistors 22 and 25 is in the same relative proportion to the magnitude of the small input signal as the proportion of the magnitude of the I#R error in the presence of a large input signal. Second since the currents in the main coding paths I 9  and I 10  are proportional to the input signal the base current of the transistors in the differential switch are reduced proportionally to the reduction in the currents in the main coding path thereby also reducing this error to acceptable levels. Third the insertion of the currents at the collectors of the differential amplifier enables the gain of the differential amplifier transistors to be kept relatively constant as compared to an amplifier arrangement as disclosed in Specification 1,433,069. The longitudinal compensation circuit 20 compensates for large input voltage swing from 1 which cause the current through a transistor 20 to increase to keep the average voltage at the interconnection of the emitter of the transistor 20, the weighting network 21 and the resistor 22 relatively constant for large input voltages. The circuit could be used as an unfolder circuit with the weighting network interchanged with the input source 1 and the comparator 23 replaced by a differential operational amplifier.