Patent AT-E22496-T1 (AT)
Inventor: BOISSARD DANIEL
IPC: G06F11/16
Filed: 1982-09-16
Granted: 1986-10-15
Abstract: 1. A method for synchronizing two microprocessors (100, 200) each one having its program and operating on the basis of microcycles of a common clock (300) defining the duration of their machine cycles, characterized in that it consists : - in providing in each microprocessor (100, 200) a register called synchronisation register (105, 205) which can be activated by the inscription of a first value and inactivated by the inscription of a second value and the contents of which can be read by the other microprocessor (200, 100), - in controlling the microprocessors (100, 200) in such a way that they engage a synchronisation procedure during which one of them called first microprocessor (100) : - performs two successive reading operations of the synchronisation register (205) of the other microprocessor (200), called second microprocessor, these two reading operations being spaced by an integer N1 of microcycles counted by means of machine cycles of the first microprocessor (100), - activates its synchronisation register (105) after an integer N2 of microcycles counted by means of its machine cycles from its first reading operation of the synchronisation register (205) of the second microprocessor (200) onwards, - inactivates its synchronisation register (105) after N3 + 1 microcycles counted by means of its machine cycles from the effective activation of its synchronisation register (105) onwards, - repeats these aforementioned three operations after an integer N4 of microcycles counted by means of its machine cycles from the effective activation of its synchronisation register (105) onwards, as long as the synchronisation register (205) of the second microprocessor (200) does not show a synchronisation state by being constantly activated during the two successive reading operations which it performs, - and, as soon as the synchronisation register (205) of the second microprocessor (200) appears to be constantly activated, which enables the first microprocessor to find its position in the synchronisation procedure with respect to that of the second microprocessor (200) awaits an integer N5 of microcycles counted by means of its machine cycles from the inactivation of its synchronisation register (105) onwards, for regaining the synchronisation state and taking over its program, whereas during this very synchronisation procedure, the other microprocessor, called second microprocessor (200) - activates its synchronisation register (205), - inactivates its synchronisation register (205) after an integer N1 + 1 of microcycles counted by means of its machine cycles from the activation of its synchronisation register (205) onwards, - performs two successive reading operations of the synchronisation register (105) of the first microprocessor (100) after an integer N2 of microcycles counted by means of its machine cycles from the effective activation of its synchronisation register (205), these two reading operations being spaced by an integer N3 of microcycles counted by means of its machine cycles, - repeats these three operations after a number of N6 of microcycles which is different from the number N4 , the absolute value of the difference N6 -N4 being a prime number with respect to N2 + N4 , the microcycles being counted by means of its machine cycles from its first reading operation onwards as long as the synchronisation register (105) of the first microprocessor (100) does not show a synchronisation state through being constantly activated during these two successive reading operations which it performs, - and, as soon as the synchronisation register (105) of the first microprocessor (100) appears to it to be constantly activated, thus enabling the second microprocessor to find its position in the synchronisation procedure with respect to that of the first microprocessor (100), awaits an integer N5 + 1 of microcycles counted by means of its machine cycles from the second reading operation onwards for regaining the synchronisation state and taking over its program.