Patent GB-1188172-A (GB)
Title: Improvements in or relating to Analogue Computers
Inventor: NIBLOCK WILLIAM JOHN
IPC: G06G7/122
Filed: 1967-05-17
Abstract: 1,188,172. Simultaneous equation solving computers. QELEQ Ltd. 2 May, 1968 [17 May, 1967], No. 22844/67. Heading G4G. An analog computer solving a linear programming problem defined by M equations in N variables to optimize an objective function by the method of steepest ascents comprises N electronic intergrates each with (M + 1) inputs; N banks of M potentiometers in parallel fed from the respective integrator outputs M; summing amplifiers each with N inputs respectively connected to the outputs of each of the M potentiometers of the N banks; M error amplifiers energized from the outputs of the summing amplifiers; M banks of N parallel potentiometers energized respectively from the error amplifier outputs, the N outputs of which energize the remaining inputs of the N integrators; limit setting devices connected to at least one of the elements in the group comprising N integrators, M summing amplifiers; and N error amplifiers to constrain the problem solution to predetermined limits, and detector means associated with the limit setting means to indicate attainment of a limit. For determination of the proportions of each of ingredients X 1 , X 2 , X 3 , X 4  in a mixture of constituents of f 1 , f 2 , f 3  whose proportions are specified within lower and upper limits and which are contained in known proportions in the four ingredients, integrators 10, 11, 12, 13 are provided for each ingredient to energize respective banks 14, 15, 16, 17 each of three potentiometers are for each constituent. The output -of the first potentiometer in each bank represents the percentage of the first constituent contributed to the mixture by the respective ingredient, and the outputs are summed in amplifier 18 to produce voltage representing the total quantity of the first constituent f 1  in the mixture. Similarly the outputs of the remaining potentiometers are summed in amplifiers 19, 20 to produce voltages representing the total quantities of the second and third constituents f 1 , f 2  in the mixture. The outputs of amplifiers 18 to 20 are respectively connected to error amplifiers 21, 22, 23 also receiving inputs representing the respective minimum and maximum allowable quantities of the constituents. Diode networks 24, 25, 26 eliminate unwanted error offset signals from the outputs, which respectively energize banks of 4 potentiometers 27, 28, 29 disposed one potentiometer per ingredient. The first potentiometers are set to give voltages representing percentages of f 1 , f 2 , f 3 , in ingredient X 1 , and subsequent potentiometers are set to give voltages representing corresponding percentages in ingredients X 2 , X 3 , X 4 . The outputs of corresponding potentiometers are summed at inputs of integrators 10, 11, 12, 13, which receive voltages V c1 , V c2 , V c3 , V c4  at other inputs representing the costs of the respective ingredients per unit weight. Detectors 36, 37, 38 and 39, 40, 41 for minimum and maximum limits are connected respectively to the inputs of potentiometers banks 27, 28, 29, while outputs of integrators 10 to 13 excite problem variable minimum and maximum limiters 42, 43, 44, 45; 46, 47, 48, 49, and minimum and maximum limit attainment detectors 50, 51, 52, 53, 54, 55, 56, 57. Limit setting devices 30, 33; 31, 34; 32, 35; (Fig. 2, not shown) comprise preset potentiometers switchably supplying voltage together with the output of amplifier 18 to a further amplifier with feedback over series opposed diodes, and problem variable minimum and maximum limit setting means 42, 43, 44, 45 and 46, 47, 48, 49 (Fig. 3, not shown) comprise preset potentiometers switchably supplying first and second double diode OR gates also receiving the output of integrator 10 to 13, which output to potentiometer banks 14 to 17. Limit detectors 36 to 41 and 50 to 57 comprise lamps panels indicating setting and attainment of prescribed limits. Error amplifier outputs are compared at detectors 36, 39; 37, 40; 38, 41 with system zero to indicate excess or defect, and the switchable potentiometers permit insertion or removal of imposed limits, or resetting of such limits during operation. In a modification, the potentiometer groups are arranged in modular assemblies which may be present for coefficients and plugged into the computer circuit.