Patent GB-929557-A (GB)
Title: A calculating system
IPC: G06F7/535
Filed: 1962-04-06
Abstract: 929,557. Digital electric dividers. TELEFUNKEN PATENTVERWERTUNGSGESELLSCHAFT. April 6, 1962 [April 15, 1961], No. 13300/62. Class 106 (1). Digital electric calculating apparatus is arranged to divide two numbers represented in binary form by the " without restoration of remainder method." In this method, the remainder at each stage of the division operation is, if it is negative, shifted to the left by one binary place and the divisor is added (instead of subtracted). In the arrangement described, the method is modified in that the divisor is always subtracted and if a negative remainder appears, the remainder is complemented before the next subtraction operation, a further complementation of the remainder taking place each time its sign changes. The method can also be employed for bases other than binary, e.g. the decimal base. The apparatus described includes a plurality of registers, the division operation being controlled by a microprogramme. Fig. 1 is a flow chart for dividing two binary numbers. Registers MD, AC, MQ and UB employed are shown in Fig. 2. In operation, the two operands are first brought to a standard form in which they are positive and less than unity and the divisor y is larger than the dividend x. The 48-digit divisor y is converted to 2's complement form and entered in the register MD. The dividend which comprises 95 digits is entered into the registers AC and MQ. These operations constitute steps S 1 , S 2  of the programme. In step S 3 , the first digit of the dividend y is tested. If it is " 0," the dividend in registers AC, MQ is shifted to the left and a " 0 " result digit entered into the next-to-last place of the MQ register. If the first dividend digit is a " 1," the contents of the register MD (i.e. the complemented divisor) is added to the contents of the register AC. If the result is negative, it is inverted (step S 7 ) and a bi-stable flip-flop R r , Fig. 2, changed over to indicate that inversion has taken place. Step S 8  controls the entry of the correct result digit into the register MQ. The division operation continues in this manner until 48 steps have taken place when the result appears in the register MQ. If the remainder has been inverted an even number of times (i.e. the flip-flop R r  registers " 0 "), the remainder is correct but if an odd number of inversions has taken place (R r  is "1"), a further inversion is required (steps S 10 , S 11 ) to produce the correct remainder. The register stages comprise transistor Eccles- Jordan circuits (Fig. 5, not shown) having two inputs and two outputs. The programme steps of the division operation are under the control of a chain SK, Fig. 2, of control elements each of which includes a bistable transistor circuit and a two-stage transistor amplifier (Fig. 6, not shown). All the register and control stages are operated in response to clock pulses from a clock pulse source (not shown). A plurality of matrices of diodes and resistors are provided (Fig. 3a, not shown) one for each binary order for interconnecting the various denominational orders of the registers with the control chain SK. A micro-programme matrix, Fig. 8, comprising crossed conductors interconnected by resistors or diodes is provided for the overall control of the division operation. The division method described may be extended to other bases and the Specification contains an example of the division of two decimal numbers.