baber/WOPTO huggingface dataset:
Patent TW-451142-B (TW)
Title: Device with an embedded on-line program processing structure on integrated circuit
Inventor: SUEN JIUN-GUNG
IPC: G06F15/78
Filed: 1998-01-08
Granted: 2001-08-21
Abstract: The present invention provides an integrated circuit architecture with an on-line program processing function, which is able to dynamically change on-line program instruction set and other software stored in the chip. The architecture is based on the micro-controller of the integrated circuit and includes two or more sets of embedded nonvolatile memory arrays for storing instructions containing the on-line program instruction set. With the control program stored in the device, it is able to interactively exchange information required for on-line program processing with a remote end, thereby updating data and software (including the on-line program instruction set). The processor and on-line codes response to the updating command of the on-line program, so as to copy the on-line program instruction set on the first block of memory array to the second block of memory array, execute the on-line program instruction set on the second block of memory array, and complete the program process of the nonvolatile memory cells in the first block of memory array based on the data from an external port.
Patent TW-401684-B (TW)
Title: Generator of clock signals for the synchronization f a system for processing digital data packets
Inventor: CHAUVEL GERARD
IPC: H04N21/43
Filed: 1998-02-10
Granted: 2000-08-11
Abstract: This generator of clock signals for the synchronization of a system for processing digital data packets (10), on the basis of program clock reference values (PCR) transmitted by the packets, comprising counting means (68-a, 74) for storing a clock reference value (PCR) and incremented under the control of a voltage-controlled oscillator (78), and means (68-b, 76) for storing the contents of the counting means (68-a, 74) includes hardware means (64) for decoding a header signal (12) so as to transfer the contents of the counting means (68-a, 74) into the storage means (68-b, 76) and a processing unit (66) decoding a useful signal (14) of the packets so as to decode the said clock value (PCR) and making a correction to the value held in the storage means (68-b, 76) as a function of the position of the said characteristic (28) and the position of the said reference clock value (PCR) and furthermore the calculation of the said voltage so as to produce the said clock signals.
Patent TW-436691-B (TW)
Title: Method for preventing compact disk from malicious copying
Inventor: JANG KAI-SHENG
IPC: G06F12/14
Filed: 1998-02-26
Granted: 2001-05-28
Abstract: The present invention provides a method for preventing CD from malicious copying, which forms the application data by pressing in a mother disk, and also preserves an area on the mother disk stored with a data. Thus, the disk that is copied from the mother disk also has the data remained thereon. The magnitude of the data is used to obtain a characteristic value. Then, the characteristic value is used to generate an encryption key and the corresponding product serial number by an encryption algorithm. When the software in the compact disk is to be installed into the computer, it is first required to input a correct product serial number. After decrypting the key, the characteristic value in the compact disk can be obtained and verified. If the verification is passed to assure that the compact disk is an original copy, the installation can be continued and the characteristic value is encrypted to determine an encryption value for being stored in the computer. When the application software is executed, the encryption value in the computer is verified at random time to avoid a malicious change. At the same time, the value is used to determine whether the compact disk is an original copy. Therefore, with the encryption method of the present invention, the compact disk can not be duplicated thereby effectively preventing the compact disks from being malicious copied.
Patent TW-388723-B (TW)
Title: Automatic dimension and sorting system
Inventor: WANG JIUN-CHIN
IPC: B07C5/06
Filed: 1998-03-23
Granted: 2000-05-01
Abstract: An automatic detecting system for dimensions of an object, obtaining a result to proceed with sorting procedure, comprising: an auto-supplying device, a measuring and procedure-controlling device, a sorting control device, a printing device, and a status display and statistical analysis device. A detected object is sent to a rotatable plate of the measuring and procedure-controlling device from the auto-supplying device. The detected object pauses whenever the rotatable plate rotates for a certain angle, and the outer diameter, thickness and flatness of the object are measured during the pause so that the detected results are printed on the object by the printing device. The detected result is not also used as the sorting criteria for the sorting device such that the object is clamped by a horizontally moveable device and a vertically moveable device from the rotateable plate and placed at a predetermined location thus achieving the purpose of sorting. The status display and statistical analysis device shows the sorted results on a display so that an operator is able to monitor the status on line.
Patent TW-461187-B (TW)
Title: Pincer movement delay circuit for producing output signal different in repetition period from input signal
Inventor: SAEKI TAKANORI
IPC: G11C11/4076
Filed: 1998-03-30
Granted: 2001-10-21
Abstract: A delay circuit has a first delay line (11) propagating an input pulse (CKL10) from stage to stage in one direction, a second delay line (12) propagating the previous input pulse from stage to stage in the opposite direction and a comparator (14) operative compare output potential levels of the stages incorporated in the first delay line with output potential levels of the stages incorporated in the second delay line so as to see any pair of output potentials are consistent in logic level with one another; when the output potentials are consistent with one another, an output timing signal is produced, and the pulse repetition period of the output timing signal is exactly half as long as that of the input pulse signal.
Patent TW-385296-B (TW)
Title: Method and apparatus for applying a protecting film to a semiconductor wafer
Inventor: SAITO HIROSHI
IPC: H01L21/00
Filed: 1998-05-14
Granted: 2000-03-21
Abstract: In an apparatus and method of applying a protecting film to a semiconductor wafer, a semiconductor wafer is placed on top of a table, a protecting film is pressed onto the wafer by a press roller biased toward the table, the table is moved to apply the protecting film to the wafer, a tension roller arranged upstream from the press roller applies a tensile force to the protecting film in a direction opposite the feeding direction of the film, the tensile force of the tension roller is first set at a relatively high value at the beginning of the application of the protecting film to place the protecting film in a stretched state and then at a relatively small value during the application of the protecting film to prevent the portion of the protecting film which has not yet been applied from coming into contact with the wafer, and then, after the protecting film has been applied to the wafer, a cutting blade is used to cut the protecting film to match the shape of the semiconductor wafer by first moving the cutting blade in the Y direction to cut from an angular portion C1 of the orientation flat portion to an angular portion C2, then rotating the table while moving the cutter and the table to align the cutting direction of the cutting blade with the tangential direction of the circumferential portion of the semiconductor wafer, and then rotating the table to cut the protecting film along the circumferential portion of the semiconductor wafer.
Patent TW-531557-B (TW)
Title: Conductive composition
Inventor: NIKAIDOH TAKASHI
IPC: H05K3/24
Filed: 1998-06-06
Granted: 2003-05-11
Abstract: To provide a conductive composition having an improved solderability and being easy to process. A conductive composition is characterized in comprising: a metal particle which is easily alloyed with solder at 28-45 wt%, a metal particle which hardly diffuses in solder at 25-60 wt%, an oxide at 3-7 wt.% for blocking solder from weldering, and a resin at 7-30 wt%.
Patent TW-498096-B (TW)
Title: Stabilizer composition comprising a blocked mercaptan and polymer composition comprising said stabilizer composition
Inventor: DUVALL TOD C
IPC: C07C323/12
Filed: 1998-06-10
Granted: 2002-08-11
Abstract: Both flexible and rigid vinyl chloride polymer compositions comprising a latent mercaptan-containing heat stabilizer are substantially free from the offensive odor typically associated with mercaptans and are protected during processing by the degradation products of the latent (i.e., blocked) mercaptan which include a free mercaptan. The free mercaptan thus released enhances the activity of metallic-based heat stabilizers such as zinc carboxylates and organotin carboxylates and mercaptides in the polymer composition. Other of the blocking moiety which are stabilized by a molecular structure in which the electron deficiency is shared by several groups. The latent mercaptan is selected from the group consisting of a 2-S-(tetrahydropyranyl)-thioalkanol and a carboxylic acid ester thereof.
Patent TW-417236-B (TW)
Title: A global planarization process
Inventor: HSIEH TZUNG-RUE
IPC: H01L21/3105
Filed: 1998-09-01
Granted: 2001-01-01
Abstract: This invention relates to a global planarization process that is used to cover the dielectric layer of the wafer having the metal conduction wire structure and includes the following procedures. A sacrificial layer is formed on this dielectric layer. A mask layer is formed on the sacrificial layer at a temperature lower than 500 DEG C. A first chemical mechanical polishing process is then performed to remove the part of mask layer with higher topography and leave the part of mask layer that has lower topography as the self-aligned mask. An etching process is performed to the sacrificial layer by using the self-aligned mask so as to decrease the height of sacrificial layer having higher topography. A second chemical mechanical polishing process is performed to polish and planarize the self-aligned mask as well as the sacrificial layer such that the effect of global planarization process on a wafer is obtained.
Patent TW-368579-B (TW)
Title: Valving device
Inventor: SUZUKI HIDENAO
IPC: F16K41/10
Filed: 1998-10-15
Granted: 1999-09-01
Abstract: A valving device can operate stably to provide switching or flow rate control actions, even when it is used for controlling thermodynamically unstable gases. The valving device comprises a valve casing having an internal passage for process fluids. A valve body is movable against a valve seat for adjusting opening of the internal passage, and a valve driving mechanism can drive the valve body. A flexible member is provided for separating a fluid handling space including the internal passage from a valve mechanism space for housing the valve driving mechanism. A thermal medium space is formed within the valve mechanism space for receiving a thermal medium for providing heat to the valve body.
Patent TW-407117-B (TW)
Title: Apparatus for strapping packages
Inventor: HUBER HANS
IPC: B65B13/18
Filed: 1998-11-20
Granted: 2000-10-01
Abstract: An apparatus for strapping packages with a band (7) made of weldable plastic comprises a band-supply unit, a band-transporting and tensioning unit, a closure unit, which is provided as a separate unit and has an abutment plate, and a band-guidance unit and has at least one band clamp (15) with a pivotably mounted clamping part (10). The band clamp (15) is formed by a specific recessed section (14) of the abutment plate (5) and the clamping part (10), a curved operative surface (40) being provided on the clamping part, and the band clamp (15) being self-locking. Selecting the clamping angle W for the band (7) between the clamping part (10) and recessed section (14) to be as large as possible means that it is easier to release the band clamp when the band is tensioned. The apparatus makes it possible for strapping bands to be applied, even with high tensioning, without slipping during the closure operation.
Patent TW-550239-B (TW)
Title: Method of preparing high brightness, shorter persistence zinc orthosilicate phosphor
Inventor: RAO RAVILISETTY P
IPC: C09K11/00
Filed: 1998-12-03
Granted: 2003-09-01
Abstract: Improved zinc orthosilicate phosphor particles are produced by thermal decomposition of gels comprising zinc and manganese salt and an organic precursor that provides a source of silicon at a temperature below the temperature of solid state reaction. The phosphor of the present invention has the empirical formula: Zn(2-x)MnxSiO4, wherein 0.005 <= x <= 0.15, and provides a broad emission in a green region when excited by 147 nm and 172 nm radiation. The phosphor obtained by the present method has uniform spherical or needle shape particles having an average particle size in the range 0.1 to 3 microns, is appropriate for thin phosphor screens required for a variety of flat panel display and lamp applications. These phosphors exhibit high brightness and shorter decay when excited with 147 nm and 172 nm radiation than currently available commercial phosphors of this type.
Patent TW-392204-B (TW)
Title: Method of defining lot's priority of wafer
Inventor: LIN GUO-JEN
IPC: H01L21/00
Filed: 1998-12-11
Granted: 2000-06-01
Abstract: The invention provides a method for determining the lot's priority of wafers during the semiconductor fabrication process. A principle of dispatching process is made based on this method. The details of the invention that provides a method of determining the lot's priority of wafers are described as follows. At first, the budge queue time of every process stage that is not preceded for all of the wafer lots is calculated. The delivery interval of wafer lots at different process stage used to produce the same products is then defined. The priority of wafer lot that is at the same delivery interval is established. Based on the delivery interval and the priority value obtained, the priority of all wafer lots is finally determined and the dispatching process is made.
Patent TW-436937-B (TW)
Title: Insulated gate semiconductor device with open gate channel structure
Inventor: YU KE-YU
IPC: H01L21/336
Filed: 1999-01-08
Granted: 2001-05-28
Abstract: The present invention discloses an insulated gate semiconductor device with an open gate channel structure, which is produced by forming a N well on a semiconductor substrate; forming a gate structure on the N well; forming a P well in the N well in the gate structure as a device channel region; forming a N well in the P well below the gate structure as the source of the device; covering an insulation layer on the surface of the polysilicon gate structure and the source region; covering a metal layer on the surface of the insulation layer and contacting with the source. The operation of the device comprises separately using the metal layer and the gate structure to apply a voltage on the source region and the channel region. The open gate channel structure has a larger contact area to the source and drain. Meanwhile, the body region length of the open gate channel structure is determined by the difference in depth between the source region and the body region. Therefore, the use of the open gate channel structure will not increase the area of the semiconductor device, and the contact area of the source to the drain can be increased.
Patent TW-391935-B (TW)
Title: Child seat
Inventor: NAKAGAWA OSAMU
IPC: B60N2/28
Filed: 1999-01-14
Granted: 2000-06-01
Abstract: The subject of this invention is to provide a child seat in which a space between a seat plate and a seat back is not widened even when the seat plate is risen. Referring to Fig. 2, the solution of this invention is: the seat plate 20 comprising a front seat plate 22 and a rear seat plate 24 is supported, by a front link 38 and a rear link 40, to a seat body 16 having the seat back 12 in such a manner that the seat plate 20 is vertically movable. Rear end portions 24a of the rear seat plate 24 are slidably engaged with guide slits 30 formed in the seat back 12. When the seat plate 20 is risen, the rear end portions 24a of the rear seat plate 24 move along the guide slits 30 so that the space between the rear seat plate 24 and the seat back 12 is never widened.
Patent TW-548897-B (TW)
Title: Write-in circuit for a semiconductor memory
Inventor: HASEGAWA KAZUHIRO
IPC: G11C16/06
Filed: 1999-01-20
Granted: 2003-08-21
Abstract: The present invention is for writing into the memory stably. In response to the reference potential Vrf generated by a reference potential generator (21), the oscillation of VCO 22 is controlled to supply the oscillation clock phic and the booster circuit (23). The peak value of the oscillation clock phic is accumulated to generate a high potential Nhv. In response to the write-in clock phis outputted by the write-in control circuit (7), the write-in potential Vd2 is supplied to the source line 4.
Patent TW-448429-B (TW)
Title: Recording/reproduction and/or editing of real time information on/from a disc like record carrier
Inventor: KELLY DECLAN PATRICK
IPC: G11B27/034
Filed: 1999-04-20
Granted: 2001-08-01
Abstract: Various measures are proposed for enabling simultaneous reading and writing of real time information, such as a digital video signal, from/onto a disc-like record carrier. The measures embody a requirement to the size of the blocks of information recorded in fixed sized fragment areas on the record carrier. Further, measures are disclosed to enable reproduction and seamless editing. The seamless editing method requires the generation of one or more bridging blocks to be recorded in fixed size fragment areas on the disk like record carrier.
Patent TW-441096-B (TW)
Title: Fabricating method for the landing pad of dynamic random access memory
Inventor: LINLIU-KUNG
IPC: H01L27/108
Filed: 1999-04-22
Granted: 2001-06-16
Abstract: This invention is about the fabricating method for the landing pad of dynamic random access memory (DRAM). At first, a substrate is provided, in which a peripheral transistor region and a DRAM region are formed on the substrate. Then, the dielectric layer of DRAM region is removed to expose source/drain regions in the DRAM region. Silicon nitride covering layer and silicon nitride spacer of gate are stacked and a polysilicon layer is formed to cover the whole upper surface. After that, a photoresist pattern, which includes plural windows with 0.3 mu m width or even smaller width for each window, is formed such that each window is located on top of the silicon-nitride covering layer. A layer of polymer with about 0.1 mu m thickness is uniformly formed on the whole surface so as to generate smaller polymer window in photoresist window. Therefore, 0.1 mu m opening or even smaller opening can be obtained in this way. Anisotropic polymer etching and polysilicon layer etching are performed sequentially so as to separate polysilicon layer and form the landing pad.
Patent TW-432616-B (TW)
Title: Semiconductoor device and method of manufacturing the same
Inventor: PARK SANG-WOOK
IPC: H01L23/52
Filed: 1999-06-04
Granted: 2001-05-01
Abstract: A semiconductor device which can reduce contact resistance is disclosed. A semiconductor device according to the present invention includes a lower conductor pattern and an upper conduction pattern. The lower conductor pattern is in contact with the upper conductor pattern. The lower conductor pattern includes a first doped polysilicon layer, a first tungsten silicide layer and a cap layer formed sequentially. Here, the cap laye is formed to a doped polysilicon layer containing a small amount of tungsten and has stoichiometrical equivalent ratio x of Si higher than the firt tungsten silicide layer. The upper conductor pattern includes a second doped polysilicon layer and a second tungsten layer formed sequentially. The contact of lower conductor pattern and the upper conductor pattern is substantially formed between the cap layer and the second doped polysilicon layer. Preferably, stoichiometrical equivalent ratio x of Si for the first tungsten silicide layer is 2.3 to 2.5 and stoichiometrical equivalent ratio x of Si for the cap layer is 2.6 to 2.9.
Patent TW-439395-B (TW)
Title: Circuit arrangement
Inventor: JACOBS RONNY ANDREAS ANTONIUS
IPC: H05B41/28
Filed: 1999-06-10
Granted: 2001-06-07
Abstract: The invention relates to a circuit arrangement for igniting and operating an electrodeless discharge lamp provided with a half-bridge commutator having two switching elements each having an emitter electrode and a control electrode and a parasitic capacitance in between, each switching element being alternately switched to a conducting state by means of a resonant control circuit. The resonant control circuit is coupled to an oscillator by way of a transformer. According to the invention, the resonant circuit is provided with capacitor means which form part of the oscillator.
Patent TW-503424-B (TW)
Title: A PDP manufacturing method and an aging process performed on a PDP
Inventor: KADO HIROYUKI
IPC: H01J17/49
Filed: 1999-06-25
Granted: 2002-09-21
Abstract: The object of this invention is to provide a plasma display panel in which an aging process essential to the manufacturing process generates minimal phosphor deterioration, enabling a relatively high luminous efficiency and high quality color production to be produced. To achieve this object, the aging process takes place while gas generated inside the panel is evacuated. Alternatively, after completion of the aging process, the phosphor of the whole panel is heated to restore heat deterioration.
Patent TW-377403-B (TW)
Title: Method of focus adjusting on image capture equipment
Inventor: Liu li-guo
IPC: G03B13/32
Filed: 1999-07-07
Granted: 1999-12-21
Abstract: The present invention relates to a method of adjusting focus of optical imaging equipment. When a CCD camera is activated to captured the specified graphic image, after periodic and directional graphic images form on the imaging equipment such as CRT monitor, it produces video interference stripes on the received image, as the imaging equipment and the CCD camera both have different operating frequencies. The imaging equipment therefor needs to have focus adjusted until a setting with best focus is reached, clearing any video interference stripes that had been present.
Patent TW-486730-B (TW)
Title: Insulated channel field effect transistor with an electric field terminal region
Inventor: KESHAVARZI ALI
IPC: H01L29/786
Filed: 1999-10-02
Granted: 2002-05-11
Abstract: In one embodiment, the invention includes a field effect transistor having a substrate, a source, and a drain. An electric field terminal region is in the substrate. A body is above the electric field terminal region between the source and drain. There is a barrier between the electric field terminal region and the body. In another embodiment, the invention includes a field effect transistor having an insulator layer and a body above the insulator layer between a source and a drain. A substrate is below the insulator layer. A gate is above the body and between the source and drain. An electric field terminal region is included in the substrate. The body may be undoped and the threshold voltage be set by setting the distance between the insulator layer and a gate insulator. The body, substrate, and electric field terminal region may float or one or more of them may be biased.