Patent GB-1278861-A (GB)
Title: Transmit-receive devices
IPC: H04L9/00
Filed: 1970-02-03
Abstract: 1278861 Telegraphy; cyphering LITTON INDUSTRIES Inc 3 Feb 1970 [4 Feb 1969] 5208/70 Heading H4P A telegraphy system transmitting characters comprising a start bit, a plurality of data bits and a stop bit, e.g. a teleprinter system, has scrambler-descrambler devices for selectively cyphering data bits during transmission and for decyphering during reception, with means for automatically switching the cyphering means when required for transmission or reception and for excluding the start and stop bits so that they are sent in "clear". Substantially identical scramblers may be employed at each terminal and the arrangement works in half-duplex, automatic switching between send and receive mode being employed. A pulse shaping circuit may also be incorporated which also provides timing and control signals for the scramblers. Each station is connected to lines 10 and includes a teleprinter 11, pulse shaper 23 and scrambling apparatus 33, the speed of transmission being controlled by a clock oscillator 15.  For transmission, depression of a key in the teleprinter initiates a start pulse which sets a transmit bi-stable circuit 17 holding a receive bi-stable circuit 18 in the off state, also bit rate counter 20 and character counter 21 are enabled through NAND gate 19 which returns the station to a stand by mode at the end of each character. A clock 15 has an output frequency 16 times that of the baud rate of the teleprinter feeding into a counter 20 comprising four JK bi-stable circuits providing division by sixteen hence pulses on conductor 22 are at the baud rate which are fed to the pulse shaper bi-stable circuit 23 and the first stage of character counter 21. Counter 21 also develops timing signals T1 fed to bi-stable circuits 25, 26 and T2 fed to counter 21 which comprises three JK bi-stable circuits combined with gates the counter being advanced once for each counter disc. With a switch (16), Fig. 3 (not shown), in the normal position (marked REGEN), an output of a mode bi-stable circuit 27 is shunted to earth, and during the transmit operation teleprinter signals are transmitted via gate 24 through shaper 23 and then through a gate 30 to line 10. At the same time a receive bi-stable circuit 25 is blocked to prevent the signals passing into the teleprinter. When switch (16) is moved to the "SCRAMBLE" position, cypher unit 33 is activated from circuit 27 and a gate 35 producing a cyphered signal on conductor 36, trough gate 30 and circuit 26. Start and stop pulses are not encoded which is prevented by control 38 operated at a count of 24 to control circuit 27 thus sampling the start bit which is transmitted prior to the cypher unit 33 being enabled. On count 24 means 38 sets circuit 27 which allows a shift register (75) of the cypher unit 33 to be clocked through gate 35 thereby cyphering the data bits of the character signals until a count of 104 is reached when circuit 27 is reset by control 38 and the stop pulse is transmitted with the cypher unit 33 disabled. At a count of 109 circuit 17 is reset from means 38 which inhibits oscillator 15 and resets counters 20, 21 hence the system is reset to stand by condition. On reception of a message functions are controlled by bi-stable circuit 25 which inhibits the transmit circuit 26 and with the switch (16) in the "REGEN" position incoming signals are forwarded directly to the printer through the pulse shaper 23. With switch (16) in the "SCRAMBLE" position, incoming signals are directed into cypher unit 33 prior to feeding into gate 31. The unit 33 remains in synchronism hence send-receive switches are not required. The unit 33 may effect reversal of certain of the mark and space signals in a random manner and is preferably a digital code generator of the self-synchronizing type which comprises a multistage shift register having 18 stages which is fed each time a pulse is applied to the interstage gates. In the examples shown, the 11th and 18th stages of the register may be combined in a modulo-2 adder (76) the output of which may be further added to the regenerated signal in a further adder (77). Although the apparatus works in half-duplex, it may be modified for simplex operation by the omission of some control circuits.