Patent GB-1138640-A (GB)
Title: Variable gain amplifier and circuits using same
IPC: H03M1/00
Filed: 1966-06-17
Abstract: 1,138,640. A/D converters. INTERNATIONAL STANDARD ELECTRIC CORP. 17 June, 1966 [24 June, 1965], No. 27103/66. Heading G4H. The input analogue signal is applied in push-pull to a pair of differential amplifiers Q3, Q4 and Q5, Q6, Fig. 2, which are supplied by a constant current source Q0 via switching transistors Q1, Q2 and provide push-pull outputs O, O<SP>1</SP>, amplitude compression being achieved by selectively switching out amplifier Q3, Q4 to alter the overall gain. With both amplifiers Q3, Q4 and Q5, Q6 operative the system has a high gain, but if the associated coder, described below, determines that the signal thus amplified, i.e. OO<SP>1</SP> lies outside a given range, a control signal C is generated to switch off Q1 to reduce the overall gain. Several amplifier sections could be used to provide several different input/output characteristics under control of several bits of the coder output. The coder comprises a comparator DSC, Fig. 4, n, e.g. 6 circuits SNj, one for each binary digit, and two others, and n-1, e.g. 5 storage flip-flops (not shown) having outputs bj. The output of the amplitude compressor O, O<SP>1</SP> is applied in push-pull to transistors Q7, Q<SP>1</SP>7. During the first digit interval, all the circuits SNj are inactive, control signals b<SP>1</SP>j blocking transistor Q10. A clock pulse #2 enables comparator DSC which sets FF in accordance with the polarity of the input OO<SP>1</SP>. All the storage flip-flops are enabled during the first digit interval and are set in accordance with the state of FF, e.g. to state 1 by a positive input signal. The first storage flip-flop is inhibited for digit intervals 2-6 and therefore retains the sign bit generated in the first digit interval. During the second digit interval SN2 and SN6 are enabled by control signals b<SP>1</SP>2 and b<SP>1</SP>6, and since these circuits have their inputs b2, b6 connected to the 1 output of the first storage flip-flop, transistors Q<SP>19</SP> are conductive to supply weighted currents, each of 1/2, to comparator input O<SP>1</SP>. The summed current I corresponds to the maximum required compressor output for the high-gain range, and since the input signal was assumed to be positive, this current is effectively subtracted from the input. Assuming FF to be set again to the 1 state by DSC, indicating that the required maximum compressor output for the high gain range has been exceeded, the second to sixth storage flip-flops are again set to state 1, the second flip-flop remaining in this state for digit intervals 3-6. This condition is detected by a gating circuit which supplies the control signal c for switching the compressor over to the low gain condition. In addition, transistor Q10 of SN1 is switched on, and in accordance with the sign bit stored in the first storage flip-flop, supplies a reference current through Q9 or Q<SP>1</SP>9 to effectively adjust the low-current end of the low gain range to zero. In the third digit interval, SN2 supplies I/2 through Q9 or Q<SP>1</SP>9 in accordance with the sign bit in the first storage flip-flop, the third to fifth flip-flops are set in accordance with the setting of FF. Subsequent digit generation is similar, reference currents I/4, I/8 and I/16 being supplied by SN3-SN5 in a positive or negative sense through Q9, Q<SP>19</SP> in accordance with the preceding bit. A receiver is described comprising a decoder supplying an expander which is similar to that shown in Fig. 2 but has complementary characteristics, the gain of the expander being controlled by the second digit of the PCM code. A modified version of the Fig. 2 circuit is described, Fig. 9 (not shown) in which the connections between Q3, Q4 and resistors R7, R8 are reversed, whereby, with suitable gains for Q3, Q4 and Q5, Q6, polarity inversion may be effected under control of the sign bit. Such a modified circuit may be fed from a decoder and itself feed an expander as described above.