Patent GB-1190041-A (GB)
Title: A Binary-Decimal Converter
Inventor: CHINAL JEAN PIERRE EUGENE
IPC: H03M7/12
Filed: 1967-05-03
Abstract: 1,190,041. Radix converters. J. P. E. CHINAL. 3 May, 1967, No. 402/67. Heading G4A. A binary-to-decimal converter utilizes multiplication by a number having a repeated pattern of four bits, a fractional portion of the result being used by a matrix to derive the remainder of a division by ten and being partly inserted into a recirculation register for correcting the result in the case of non-zero remainder. The input binary number, in a shift register 1 is multiplied by 3 by being added to itself one-bit-delayed in a serial adder 3, the result being multiplied by Y = 0À00010001 ... 0001 (binary notation) by means of serial adders 4, 5 connected as shown, adder 4 having an input from the 4th bit (from high order) of register 1 and adder 5 having an input T from a trigger supplying appropriate bit sequences and the carry triggers a, b of adders 4, 5 having been appropriately preset. Division by 2 is also accomplished, this being a simple shift. The result, apart from the last 4 bits, is reinserted into register 1 (connection not shown), the next 4 bits being inserted into an output shift register 2 and a correction recirculating shift register 6. The 4 bits together with the output of stage P1 of register 1 are used by a diode matrix L to derive the remainder of a division by ten which the above operations have effectively performed, this remainder being inserted into the register 2 as shown and constituting one decimal digit in a desired binary code of the output number. The contents of register 1 are now corrected (to obtain the quotient of the division by ten) by adding them, with each bit inverted, in adder 3 to corrections, the result being returned to register 1 (connection not shown). If the remainder above was non-zero, one correction is a number obtained by repeating the four bits in register 6 by recirculating this and applying its output to adder 3. A second correction, the value of which depends on whether the remainder is zero or not and on a bit derived in calculating the remainder, is incorporated by direct control of the state of the carry trigger c of adder 3. Subsequent decimal digits are obtained by repeating the above using the new contents of register 1. The adder 5 can be replaced by a subtractor or an adder-subtractor. Instead of multiplying the input binary number by 3 and Y and dividing by 2 as above, it can be multiplied by a number consisting of the bits 1111 repeated, then dividing by 5 and 2, the division by 5 being done by what is essentially a subtractor (it is known that the division will give no remainder), and the division by 2 being a shift. By using an extra adder, the correction relative to one decimal digit and the search for the remainder relative to the next can be done concurrently, thus almost halving the number of circulations of register 1. The system could be multiplexed between a plurality of binary sources, used to feed a decimal display, counter or printer, or used between two arithmetic units working in binary and binary-coded decimal respectively. The whole and fractional portions of a mixed binary number can be converted in turn each as above, also using multiplication by ten for the fractional portion.