Patent GB-1415859-A (GB)
Title: Signal steering circuits
IPC: G11C19/08
Filed: 1972-11-28
Abstract: 1415859 Automatic exchange systems; magnetic storage arrangements WESTERN ELECTRIC CO 28 Nov 1972 [2 Dec 1971] 54867/72 Headings H4K and H3B In a TDM system, time slot interchange is effected with the aid of two shift registers whose stages are coupled to each other via respective gates that are controlled by respective recirculating memories. Input signals relating to all the slots of a single frame are fed to the first register which has sufficient capacity for a full frame and are then gated to the second register which is of similar capacity such that they merge therefrom in the required order. A central processor is responsible for choosing a path through the system and for writing the input and output time slots of a particular connection into the time slot interchanger. The latter is responsible for determining the time slot during which a data word should be transferred between the registers and for entering a corresponding control word into the relevant recirculating memory. The invention is particularly suitable for planar shifting technologies viz those where a signal representative state of matter is shifted in a determined manner in a homogeneous body of material. Of the two examples given, viz. charge-coupled devices and single-wall magnetic domain devices, only embodiments utilizing the latter are described in detail. As can be seen from Fig. 1, input highway 11 is connected to the input of a shift register 19 that has at least as many stages as there are time slots in a frame. Each stage is connected by a gate 22-26 to a particular stage of a second shift register 20 whose output is connected to an output highway 12. A central processor 13 fills memory 18 with the requisite gate opening commands. It will be appreciated that the gates are opened during a frame such that when register 19 contains a full frame (i.e. it has been stepped through the number of slots in a frame) then register 20 also contains a full frame but the time slot order in this register is different from that in 19 and the individual time slots may in fact contain data which was inserted in register 19 during the previous frame. In general, during any one time slot there may be none, one, or more than one gates open in order to transfer data between the registers, and, during any one frame a particular gate need not be opened at all or may be opened a plurality of times. For example, if the order of time channels on the input and output highways is to be inverted then all the gates will be opened simultaneously once and once only during a frame whereas if the order of channels is to remain the same on both highways then a single and same gate is opened during successive time slots. In the case where each time slot contains only single bit words the problem may arise that a bit is lost because it is between stages when the gates are opened. This is an inevitable consequence of stepping the two shift registers synchronously. It is referred to as the "half word" problem. Solutions to the problem therefore consist in stepping the registers alternately or buffering a complete frame from one register and then gating its time slots to the other register during the succeeding frame. In another embodiment which requires that each word contain an even number of bits, the registers 2 are provided with twice the number of stages each effective to store half a time slot word and with separate gates for gating the two so-formed half words.  Magnetic - domain time slot interchanger (Fig. 2).-The two oppositely shifting registers of Fig. 1 are here represented by lines 19<SP>1</SP>, 20<SP>1</SP> along which magnetic domains are propagated, leftwards and rightwards respectively, by a magnetic field rotating counter-clockwise. Each of the gates 22-26 is represented by a coupling path 550-52 which is enabled by the appearance of a magnetic domain on a "lead" 47-49 emanating from a respective recirculating memory 37-39. In operation, the processor writes the input and output time slot identities into coding circuits 56, 53 so that properly timed domains may be injected into closecoupled domain shift registers 40, 41. When the domains interact, e.g. at 58, the domain in register 40 is diverted into recirculating memory 38 while the domain in register 41 containues its passage towards annihilator 63. The domain in memory 38 is effective at F to supply a control signal to gate 23<SP>1</SP>. The control signal consists of as many domains as there are bits, e.g. 10, in a data word which is to be routed through the time slot interchanger. The control domains interact with the data domains in gate 23<SP>1</SP> so as to divert the data domains into register 20<SP>1</SP> while the control domains proceed to annihilator 31. The domain in memory 38 meanwhile reaches register 19<SP>1</SP> so that it in turn can proceed to the annihilator. Each data word contains one bit position which is marked busy throughout a connection. The domain in register 19<SP>1</SP> corresponding to this bit for the call under consideration reacts with the domain leaving memory 38 and in consequence is diverted into the memory so that it can react at F one frame later. The repeated diversion of the busy bit domain due to reaction with the previously diverted bit domain in memory 38 ensures continuity of the connection. At the end of the call the busy bit is marked free so that no new entry is made in the memory which is thereby cleared. It will be appreciated that in a large system removal of the busy bit at the calling end will permit all the various time slot memories to be cleared one after the other without any further demands on the processor. Domain time slot interchanger details (Fig. 3).- The convention used is referred to as an overlay pattern utilizing T and bar type overlays for defining propagation paths. The device may be constructed along the lines discussed in Specification 1,241,235. It will be remembered that circuits 56 and 53 have inserted domains into shift registers 40 and 41 and that these are to interact so as to insert a control domain into memory 38. At a particular point in the propagation process when the rotating field vector H is pointing upwards the domain in register 41 adopts the orientation L1 and that in register 40 the position 41.During each of the next anticlockwise, quarter turns of the field the domain in register 41 adopts successively the orientations L2 to L6 and so on until it is annihilated at the output of the register. In register 40 however, the domain U is repelled by the domain L and so is forced into the path defined by orientations U3, U4A, U5, U6, U7 rather than the path U3, U4 and the unreferenced orientations. The control domain after its diversion via the so-called "lazy T" 66<SP>1</SP> then proceeds along the left arm of memory 38 under the influence of the rotating field until it reaches the fan out circuit 43. This has the function of stretching the single bit control domain so that it lasts for the duration of a full time slot. In practice the latter is constituted by 10 bits so it is necessary to convert the control domain into 10 portions each for co-operating with a respective bit. Specification 1,235,930 and U.S.A. Specification 3,564,518 and 3,713,118 provide examples of suitable fan out circuits. The domains from fan-out 43 proceed along path 48 and adopt the orientations G1-G7 in their passage through the interaction or gating zone 23<SP>1</SP>. It will be noted that orientations G4, G5 coincide, this condition together with G3 being produced by a so-called angular (rather than T) overlay format. A lazy T element 68 causes domains in lower register 19<SP>1</SP> to traverse the orientations D1 to D7 if repelling domains appear from path 48 otherwise they traverse the path D1, D2, D3, G4, G5 &c. in their passage towards a later gating zone. The recirculating memory 38 (or see memory 37 for more clear detail) loses its control domain to the shift register 19 as can be seen from the orientations C1 to C6 and gains a new control domain from the register (providing of course that (a) it already contained a control domain and (b) the busy bit still occurs in the incoming data word) as indicated by the orientations B1-B3A-B6. Modified time slot interchanger Fig. 4 which is capable of changing the bit rate of signals passing therethrough. Input words in parallel or serial bit format are shifted through register 19 and at the end of each frame are simultaneously gated into buffer store 69. During the next frame the words are gated into shift register 20<SP>11</SP> in accordance with the time changes required in an obvious manner (note that register 20<SP>11</SP> shifts in conventional manner from left to right contrary to the Fig. 1 embodiment. If the bit rate is to be doubled, the control memories feeding leads 27 are arranged to circulate or otherwise reproduce their gate control words twice per frame. This has the effect that if the output time slot occurs earlier in a frame than the corresponding input time slot then the shift of a data word from store 69 to register 20<SP>11</SP> can only occur on the second occurrence of the gate control word whereas if the output slot succeeds the input slot the data word is shifted on the first occurrence of the gate control word. In order to overcome the problem and ensure that all data words are correctly in register 20<SP>11</SP> during the second occurrence, i.e. during a period equivalent to half the length of an incoming frame, any words entered during the first occurrence are recirculated via gate 70 during the first half frame.  In another embodiment (Fig. 6, not shown) incoming serial words are entered one at a time into a one word shift register which is emptied parallel fashion into a plurality of time slot interchangers of the types described above. Those changers operate synchronously so as to transfer the plurality of bits of each word