Patent GB-1263305-A (GB)
Title: A system for controlling a plurality of traffic signals
IPC: G08G1/081
Filed: 1969-05-21
Abstract: 1,263,305. Road traffic signals. OMRON TATEISI ELECTRONICS CO. 21 May, 1969 [10 June, 1968], No. 25914/69. Heading G4Q. A system for controlling traffic signals over a wide area divided into a plurality of local areas comprises a master controller having a computer CM, Fig. 1, which receives information of traffic conditions, e.g. traffic volume, traffic density, in each of the local areas. Each local area has a local controller comprising a register CR, Fig. 2. As shown, there are thirty local areas and therefore thirty shift registers CR1 . . . CR30. Each local controller CR is controlled by a pair of signals, viz., a cycle signal and synchronizing signal. The system provides ten different pairs of these signals in the form of pulses of different frequencies. Thus ten different cycle signals are applied to terminals C1 . . . C10, respectively, and ten different synchronizing signals are applied to terminals R1 . . . R10, respectively, these signals being paired, e.g. C1 is paired with R1. To obtain the optimum traffic flow through the wide area the computer CM selects for each local controller in turn the best pair of cycle and synchronizing signals and causes that pair to be supplied to the appropriate register CR. The master controller includes an address register CA and a command signal register CB both controlled by the computer CM. The register CA has ten output lines labelled 1, 1, 2, 2 &c. and stores in binary code the addresses of the thirty registers CR1 . . . CR30. The register CB stores, at any given time in binary code, a particular one of ten different command signals, each command signal corresponding to a particular pair of the ten different pairs of cycle and synchronizing signals. The computer CM causes the addresses to be called in succession and also supplies to the register CB the particular command signal appropriate to the address being called. The ten output lines of the register CA are connected to a diode matrix DM1 having thirty output lines L1 . . . L30 each forming one input to respective AND gates A1 . . . A30. The outputs of gates A1 . . . A30 are connected to shift registers CR1 . . . CR30 corresponding to the thirty local areas. The other inputs of the AND gates A1 .... A30 are taken from a line LC connected to a clock pulse generator (not shown). If, for example, register CA has called out No. 2 local area, an output appears on line L2 and when this coincides with a clock pulse on line LC the command signal stored in register CB is transferred via line LB to register CR2. Local controller CR represents any one of the shift registers CR1 . . . CR30. The eight output lines labelled 1, #1, 2, #2, &c. are connected to a divide matrix DM2 having ten output lines L41 . . . L50. The particular command signal stored in the register CR gives rise to a signal on one of the lines L41 . . . L50 to energize one input of one of AND gates A41 . . . A50 and one input of a corresponding one of AND gates A51 . . A60. The other inputs of the AND gates are energized from the terminals C1 . . . C10, R2 . . . R10 mentioned earlier. Thus if register CR causes a signal to appear on line L42 the cycle signal applied to terminal C2 passes through AND gate A42 and OR element O1 to a terminal SC. Similarly, the synchronizing signal applied to terminal R2 passes through AND gate A52 and OR element 02 to a terminal SR. The signals at terminals SC, SR are applied to counters (Fig. 3, not shown) to produce at four output terminals signals which appear after lapse times equal to 0, 4, 50 and 90% of one cycle length of the synchronizing signal. These signals may be used as described in Specification 1,259,435.