Patent GB-746744-A (GB)
Title: Improvements in and relating to apparatus for synchronising electric oscillations or trains of electric pulses
Inventor: ROBIN HAROLD KILNER
IPC: H03L7/00
Filed: 1949-12-14
Abstract: 746,744. Automatic phase control. NATIONAL RESEARCH DEVELOPMENT COR. PORATION. Dec. 13, 1950 [Dec. 14, 1949; Dec. 30, 1949], Nos. 30279/50 (Divided out of 746,741) and 33405/49. Class 38 (4). Trains of pulses 01, 02, of same frequency, or oscillations from which the pulses are derived, are synchronized despite the phase of one train 02 or oscillation being variable by employing a generator of pulses 03 of constant frequency greater than 01 and 02 to produce the pulses 01 from a frequency reducing pulse counter DR producing one output pulse 01 for every n applied to it and a phase-correcting device cancelling one or-more of the pulses 03, or interlacing one or more additional pulses with the pulses 03, to retard or advance the counter DR in dependence on change of phase of the pulses 02. Phase synchronism is maintained between upper and lower limits determined by the frequency division ratio of the counter. The pulse counter may be a decade ring DR (see Figure) of ten trigger pair valve circuits connected in a ring cascade. An output is taken from one trigger pair circuit and applied at OS to generate a rectangular waveform 01, as described in Specification 746,741, [Group XL (b)], of frequency 90 c/s. to be controlled, relative to incoming pulses 02 at T13 of mean frequency 90 per second and variable phase. The pulses 03 are developed from a tuning fork TF2 of frequency 1800 c/s. which feeds through phase shifters PC4, PC5 trigger pair circuits F29, F30 generating pulse trains of frequency 3600 per second symmetrically staggered. These are applied to gates G17, G18 and through buffers B19, B20 to valve trigger pair circuits F31, F32 which ensure that normally gate G17 is open and gate G18 is closed. A common output of gates G17, G18 feeds the pulse counter DR through circuits F10, F11 each dividing the pulse frequency by two. The pulse waveform 01 to be controlled in phase is fed to a phase-splitter circuit PC3 with outputs in anti-phase alternately opening and closing gates G15, G16 to which the pulses 02 of variable phase are fed in parallel through means K3 producing a delay of <SP>1</SP>/ 360  second. The arrangement is such that either a pulse 02 passes through gate G15 to a second terminal of trigger pair circuit F31 to cause the latter to close the normally open gate G 17 and prevent one pulse 03 from reaching the common output circuit or the pulse 02 passes through gate G16 to a second terminal of the trigger circuit F32 and causes the latter to open the normally closed gate G18 and introduce an extra pulse from circuit F30 into the output. Thus, 39 or 41 pulses in every <SP>1</SP>/ 9o th second, never 40, pass to the counter and the system hunts between the two conditions, about a mean condition having the commencement of each positive half-cycle of waveform 01 coinciding with the input of pulses 02 to the gates G15, G16. The arrangement may be applied to synchronizing the multiplex radio signalling system of Specification 746,741 in which a locally generated 90 c/s. square wave is synchronized with the 90 c/s. modulation on a received carrier wave.