Patent GB-945406-A (GB)
Title: Improvements in or relating to multi-channel communication systems
Inventor: HAKIM SAHIR SABIR
IPC: H04J3/12
Filed: 1961-06-29
Abstract: 945,406. Multiplex pulse code signalling. GENERAL ELECTRIC CO. Ltd. June 27, 1962 [June 29, 1961], No. 23577/61. Heading H4L. Relates to a time division multiplex communication system in which in order to provide additional signalling information, e.g. for supervising, the additional signals are substituted temporarily for the normally transmitted synchronizing signals, means being provided at the transmitting terminal equipment to suppress the synchronizing signals for a short interval immeddiately prior to such substitution. The pulse code modulation telephone system described provides twelve channels using a seven-digit binary code an eighth digit being added at the beginning of each channel code group for synchronizing. The channels are transmitted in succession to form a frame, the first eleven synchronizing digits of each frame being a " 0 " and the twelfth synchronizing digit being a " 1." The additional signalling information is transmitted at a frequency of 444.4 c/s., i.e. once every 18th frame, by making the synchronizing digit of the twelfth channel a " 0 " for one frame, thus suppressing the synchronizing information, and in the immediately following frame the synchronizing digit of each code group is made a " 1 " or " 0 " according to the information to be transmitted. The receiver includes equipment which recognizes that the synchronizing information has been suppressed in one frame and is conditioned to accept and utilize the additional signalling information in the subsequent frame. At the transmitter, Fig. 1, the twelve incoming audio frequency signals are supplied via respective terminals 1 and low-pass filters 3 to a corresponding sampler 4, the samplers being operated in sequence by timing pulses O to C12 derived from a 13.824 mc/s. oscillator 5, frequency divider 6 and channel pulse gates 8. The frequency divider 6 also supplies signals of 444.4 c/s. over lead 10 and signals of 4 kc/s. over leads 12 to an output co-ordinator 11, and signals over a group of five leads 43 to control coder pulse generators 14. The outputs of the samplers 4 are supplied to an amplitude compressor 16 and are converted to modulated pulses in a sampler 17 controlled by pulses from 14. The width modulated pulses are supplied to the AND gate 19 which receives clock pulses from the oscillator 5 so that its output consists of clock pulses gated in dependence on the signal from 17 and these clock pulses set a seven-stage binary counter 21 accordingly. When the count has been completed the pulse generators 14 operate to transfer the count via transfer gates 22 to a shift register 23. A signal over lead 26 to the shift register 23 causes the digits stored to be supplied over lead 27 to the coder pulse generators 14 and the resulting output is supplied via the co-ordinator 11 and an amplifier and shaper 28 to the outgoing line 29. For transmitting the supervisory signals each channel is provided with a terminal 31 energized as required and connected to a sampler 32 controlled by the appropriate timing signals C1 to C12, the outputs from the samplers 32 being supplied to the co-ordinator 11. The oo-ordinator 11, Fig. 2 (not shown), includes gating circuits for signalling information in every 18th frame and removing the synchronizing pulse from the frame immediately prior to the 18th frame. At the receiver, Fig. 4, the incoming pulse signal is supplied via an amplifier 61 to a timing network 62 and after regeneration at 63 is supplied to the decoder 64 together with digit timing signals D1 to D8. The signals are also fed to a bandpass filter 66 supplying a sinusoidal signal at the pulse repetition frequency to a pulse generator 68 controlling the timing network 62 and to a synchronizing arrangement 65 which also receives the pulse code signals from 63. A signal 65 is frequency-divided at 69 and via decoder pulse gates 74 and channel pulse gates 72 provides digit timing pulses D1 to D8 and channel timing pulses C1 to C12. The amplitude modulated pulses from the decoder 64 are supplied via an amplitude expander 75 to the channel separator 76 controlled by pulses C1 to C12 and each separated channel is supplied to a pulse lengthener 77 and low-pass filter 78 to reconstitute the audio-frequency signal. The additional signalling information is selected in the apparatus 65 and passed to signalling separators 83 controlled by pulses C1 to C12 to separate the pulses into their respective channels. In each channel the pulses are lengthened at 84 and operate a relay 85. In the synchronizing arrangement 65 and frequency divider 69, shown in Fig. 5, the sinusoidal timing signal at the pulse repetition frequency from amplifier 67 is supplied to terminal 102 and the regenerated pulse code signal from 63 is supplied to terminal 101. In operation, assuming no additional signalling and correct synchronizing, the output of the inverter 119 which is supplied via a compensating delay line 103 consists of waveform A, Fig. 6. This signal causes pulse generator 120 to supply waveform B at the same pulse repetition frequency to the AND gate 121. The frequency divider 69 comprises bi-stable circuits 110 to 115, the bi-stable circuits 113, 114 being arranged to divide by a factor of three and the remainder by two, controlled through an OR gate 109 and AND gate 106 or 107 by a bistable device 105 operated by the timing signal from terminal 102 via an inverter 104. A second output from the OR gate 109 is supplied via an inverter 116 to an AND gate 117 which also receives appropriate inputs from the frequency divider. The output C from the gate 117 is supplied to AND gate 118 together with appropriate signals from the frequency divider and the output from the gate 118 after inverting at 129 produces a signal F applied to inhibit gate 122 and also applied to differentiator 131. Negative going half-cycles of the differentiated signal F are supplied via an inverter 130 to a gate 133 controlling a pulse generator 134. The pulse code signal on terminal 101 is supplied to AND gate 121, which also receives signal C from gate 117, and its output E is supplied to gates 122 and 137 and to control a pulse generator 135. The incoming signal at 101 includes the' synchronizing signal (waveform) D which shows the first pulse position of channel 12 in a frame the remaining code pulses being omitted for simplicity. With correct synchronism the gate 121 will supply a signal E to the gate 122 but this gate will be inhibited by the signal F, the delay line 103 being included to ensure this condition. During the two frames in each eighteen in which no synchronizing signal is transmitted the first digit in the first of these frames will be " 0 " and thus there will be no signal E from gate 121 and pulse generator 135 will be inoperative and will not inhibit a gate 133 so that a pulse will be supplied by generator 134. This pulse will pass via gate 138 to inhibit the gate 124 for a time such that it will not pass any signal supplied by the inverter 123 during the next frame. The pulse from 134 will also be supplied to the gate 136 for the duration of the next frame during which any incoming signal from 101 will be passed to the terminal 137 for subsequent utilization. If the receiver is not correctly synchronized some of the pulses passed by the gate 121 will be passed by the gate 122 and will be supplied via inverter 123 to the gate 124. Assuming that the gate 124 is open these pulses are supplied to an integrator 125 and detector 126 which co-operate with a reference 127 so that the detector 126 supplies a signal only if three or more pulses have been received during an interval equal to several frames. Thus any further pulse supplied by the gate 124 will pass via the gate 128 to cause the bi-stable device 108 to reverse its condition and cause a different one of the gates 106, 107 to be operative. This shifts the signal derived from the gate 109 and associated bi-stable devices 110 to 115 by one pulse position relative to the incoming signal, this process being repeated until correct synchronism is reached. The delay introduced by detector 126 prevents operation by occasional spurious pulses. The gate 124 normally will not pass signals during the frame in which the additional signals are being received, thus preventing undesired operation of the bi-stable circuit 108 during this frame. However, each time the bi-stable circuit 108 changes over a pulse supplied by differentiating circuit 139 or 140 is passed via gate 141 to cause a pulse generator 142 to supply a signal inhibiting the gate 138. The duration of this signal is such as to allow synchronizing to be completed if the apparatus is already out of synchronism.