Patent DE-10052326-A1 (DE)
Title: Semiconductor remanent memory device with maintained margin between threshold voltages, for use in read-only memory type units
Inventor: KIM DONG-HWAN
IPC: G11C16/06
Filed: 2000-10-18
Abstract: The semiconductor remanent memory device comprises a bit line (BL1), several word lines (WL1-WL16) positioned perpendicular to the bit line, several memory cells (MC-1-MC-4) positioned at intersections of the bit line and the word lines, a storage circuit including two data locking circuits (LT1,LT2), each coupled to a corresponding input/output line, and a data discrimination circuit for serving to the bit line a voltage which is a programming voltage or a stop programming voltage, depending on the logic states of locked data. The discrimination circuit serves to the bit line the programming voltge when at least one of the logic states of locked data indicates the programming of selected memory cell, and the stop programming voltage when the logic states of locked data indicate the programming stop of selected memory cell. The discrimination circuit comprises a NOR gate with inputs receiving the data contained in the locking circuits (LT1,LT2), a switching transistor (MN10) connected between the bit line and the output of NOR gate, where the transistor is gate-controlled by a signal active only during the programming operation. The memory device also comprises a charging transistor (MP1) connected between a supply voltage (Vcc) and the bit line (BL1), which serves as a constant current to the bit line in response to a reference voltage (Vref) during an operation of programming verification; and a storage control circuit serving to an inverter or maintaining the logic states of locked dta as a function of the voltage level on the bit line, in response to locking validation signals. The memory device also comprises another bit line (BL2), and a circuit for the selecton of bit line in response to the bit line selection signals, where the bit line which is not selected is biased by means of the supply voltage by the intermediary of selection circuit, and the selected lline is set to the programming or the stop programming voltage by the intermediary of discrimination circuit. The programming voltage is at the potential of electrical earth, and the stop programming voltage is at the potential of supply voltage. The memory device also comprises two transistors for initialization (MN8,MN9) connected to the locking circuits and used to reset the locking circuits in response to a repositioning signal (PBset), before which the data bits are not loaded to the locking circuits. The data bits in the locking circuits are programmed in the selected memory cells during a set of cycles, e.g. 3, each including the programming operation and the programming verification operation period. The programming of memory device with several states comprises the following operations: the loading of storage circuit with several data bits for the programming in selected memory cell; the determination if at least one data bit indicates the programming operation; and setting the selected bit line to the programming voltage or the stop programming voltage, depending on the indication.