baber/WOPTO huggingface dataset:
Patent TW-I226062-B (TW)
Title: Flexible redundancy for memories
Inventor: ROEHR THOMAS
IPC: G11C29/04
Filed: 2003-04-17
Granted: 2005-01-01
Abstract: An improved redundancy scheme for a memory matrix is disclosed. The memory matrix a plurality of memory cells interconnected in first and second directions. The memory cells are grouped into memory elements. A redundant memory element having a plurality of redundant memory cells is provided. The redundant memory element is segmented into R sections in the first direction, wherein R is a whole number greater to or equal to 2. By segmenting the redundant element into R sections, it can be used to repair defects in up to R different memory elements.
Patent TW-I240818-B (TW)
Title: Display device
Inventor: TSUTSUI YUSUKE
IPC: G09G3/36
Filed: 2003-05-14
Granted: 2005-10-01
Abstract: This invention provides a display device capable of selecting a desired partial display a region to perform a partial display. The device is provided with a masking circuit 210 which provides video signals to each pixel of the partial display region selected in response to display region selection signal DS', and mask the supply of the video signals to each pixel of the background display region. Furthermore, in order to reduce the power consumption, a precharge signal PCD from a precharge circuit 150 provided in liquid crystal panel 100A is used as a background display signal.
Patent TW-I258028-B (TW)
Title: Aligning method under electric field for ferroelectric liquid crystal and liquid crystal display using the same
Inventor: KIM HONG-CHUL
IPC: G02F1/1337
Filed: 2003-07-03
Granted: 2006-07-11
Abstract: A method of aligning a ferroelectric liquid crystal (FLC) material capable of facilitating the restoration of an initial alignment of FLC material as a result of mounting of driving circuits includes simultaneously applying a first voltage to a Vcom terminal formed on a source printed circuit board and applying a second voltage to a GND terminal also formed on the source printed circuit board while the first voltage is also applied to a Vcom terminal formed on a gate printed circuit board and while the second voltage is also applied to a GND terminal formed on the gate printed circuit board.
Patent TW-I244449-B (TW)
Title: Bicycle power supply
Inventor: KITAMURA SATOSHI
IPC: B62J6/12
Filed: 2003-08-13
Granted: 2005-12-01
Abstract: The object of the present invention is to provide a bicycle power supply, which does not cause incorrect operation of small power consumption electrical devices even when large power consumption electrical devices are in operation. The bicycle power supply is to store electrical power from an AC generator (19) mounted on a bicycle and supply the electrical power to a device that drives front and rear chain shifters (26f), (26r) and first controller (35), (55) and comprises rectification circuit (37), charging ON/OFF switch (40), first electricity storage unit (38a), second electricity storage unit (38b) and diode (42). The rectification circuit rectifies the electrical power from the AC generator into direct current. The first electricity storage unit is connected to the charging ON/OFF switch and supplies electrical power to the chain shifters. The second electricity storage unit is connected to the first electricity storage device and supplies electrical power to the controller. The diode allows unidirectional flow of electrical current from the first electricity storage unit to the second electricity storage unit.
Patent TW-I223696-B (TW)
Title: Belt tensioner
Inventor: SERKH ALEXANDER
IPC: F16H7/08
Filed: 2003-09-22
Granted: 2004-11-11
Abstract: The invention is an improved tensioner for tensioning a power transmission belt. It is of the type having a pulley adapted to communicate with a surface of a power transmission belt, an arm supporting the pulley upon which the pulley is rotatably mounted via a pulley bearing, and having a shaft supporting the arm. The shaft is rotatably supported by a pivot bearing. Further, it is of the type having an attachment point for a strut with the strut attached to the attachment point. It is improved by the pulley and the attachment point being laterally offset in relation to the pivot bearing and substantially balanced in terms of parasitic torque across the pivot bearing.
Patent TW-I237347-B (TW)
Title: Integrated circuit device and method for applying different types of signals to internal circuit via one pin
Inventor: KWON KYOUNG-HWAN
IPC: H01L27/04
Filed: 2003-10-21
Granted: 2005-08-01
Abstract: Provided are an integrated circuit and a method thereof, in which different types of signals can be applied to an internal circuit via one pin. The integrated circuit device includes a distribution unit, a level fixing unit, and an activation unit. The distribution unit receives and outputs a first input signal input via the first input pin, and receives and outputs a second input signal input via the first input pin in response to a control signal. The level fixing unit receives the first input signal from the distribution unit and applies a signal having the same voltage level as the first input signal to a first internal circuit in response to the control signal. The activation unit receives the second input signal input via the second input pin and then applies the second input signal to a second internal circuit or applies the second input signal output from the distribution unit to the second internal circuit in response to the control signal.
Patent TW-I226527-B (TW)
Title: Docking device module exchangeable with the cell module of a super slim notebook computer
Inventor: LIOU MING-YUAN
IPC: G06F1/16
Filed: 2003-10-31
Granted: 2005-01-11
Abstract: The present invention provides a docking device module exchangeable with the battery module of a super slim notebook computer, in which an indentation is configured at one end of a notebook computer, and the inner wall of the indentation is configured with a first connector and a second connector, respectively. The indentation could be just fitted with a battery module. A slot configured at one end of the battery module can accommodate the second connector, and another first connector configured at one end of the battery module could be connected with the first connector to provide the power for the operation of the notebook computer. The battery module can be exchanged with a docking device module to be placed into the indentation, wherein one end of the docking device module is configured with another slot for accommodating the first connector, and another second connector to be connected with the second connector. The other end of the docking device module is configured with plural sockets of different functions for being inserted with corresponding wiring plugs in advance. Thus, no matter the notebook computer is used indoors or outdoors, the user does not need to repetitively plug/unplug a pile of I/O wiring plugs because the wiring plugs with different functions have been inserted in the docking device module.
Patent TW-I240206-B (TW)
Title: Power management for processor and optimization method for bus
Inventor: HSU MING-WEI
IPC: G06F1/32
Filed: 2003-10-31
Granted: 2005-09-21
Abstract: The present invention provides a power management for processor and optimization method for bus, which includes the following steps: first, configuring the bus operational bandwidth and frequency for the bus between the processor and the north bridge; next, activating the power management configuration for the processor, the north bridge, and the south bridge; outputting the message of adjustment amount for operational frequency and operational voltage to the south bridge; then, the south bridge will output a bus interrupt signal to interrupt the bus connection between the processor and the north bridge; initializing counting of a counter; then, the processor will adjust the operational frequency and voltage of the processor based on the adjustment amount for operational frequency and voltage; when the counting of the counter accumulates to a predetermined value, the south bridge will output the bus connection signal; then, the bus will re-connect the processor with the north bridge, and operating with the bus operational bandwidth and bus operational frequency, and the processor will operate with another operational frequency and operational voltage according to the message of adjustment amount of operational frequency and operational voltage.
Patent TW-I247517-B (TW)
Title: Human resources and attendance management system combining electronic signature certification technology
Inventor: CHEN YUN-WEN
IPC: H04L9/32
Filed: 2004-01-30
Granted: 2006-01-11
Abstract: The present invention relates to a human resources and attendance management system combining electronic signature certification technology, which manages the approval for user's certificate through a certificate authority. Moreover, user's private key is directly produced in an electronic identification certificate. When user employs the human resources and attendance management system to submit and approve an electronic form, by means of the electronic signature element in the human resources and attendance management system, hash processing is carried out onto the contents of the electronic form to acquire a message digest. The message digest is transmitted to a user's electronic identification certificate chip to calculate the signature for the message digest. The human resources and attendance management system utilizes the signature not only to certify that the user submits or approves the electronic form, but also to ensure the integrity and correctness of the contents of the electronic form.
Patent TW-I260223-B (TW)
Title: Pyrazolo-triazine compounds and uses thereof
Inventor: GRIFFITH DAVID ANDREW
IPC: C07D251/00
Filed: 2004-02-05
Granted: 2006-08-21
Abstract: Compounds of formula (I) that act as cannabinoid receptor ligands and their uses in the treatment of diseases linked to the mediation of the cannabinoid receptors in animals are described herein.
Patent TW-I267164-B (TW)
Title: Bipolar transistor structure and methods using shallow isolation extension to reduce parasitic capacitance
Inventor: KHATER MARWAN H
IPC: H01L29/732
Filed: 2004-02-25
Granted: 2006-11-21
Abstract: A bipolar vertical transistor is formed in a silicon semiconductor substrate which has an upper surface with STI regions formed therein composed of a dielectric material formed in the substrate having inner ends and top surfaces. A doped collector region is formed in the substrate between a pair of the STI regions. A counterdoped intrinsic base region is formed on the upper surface of the substrate between the pair of the STI regions with a margin between the intrinsic base region and the pair of STI regions, the intrinsic base region having edges. A doped emitter region is formed above the intrinsic base region spaced away from the edges. A region shallow isolation extension region composed of a dielectric material is next to the edges of the intrinsic base region formed in the margin between the STI regions and the intrinsic base region. An extrinsic base region covers the shallow extension region and extends partially over the intrinsic base region in mechanical and electrical contact therewith, whereby the shallow isolation extension region reduces the base-to-collector parasitic capacitance of the bipolar transistor.
Patent TW-I241384-B (TW)
Title: Circumferential flow pump
Inventor: KOYAMA MASAHIRO
IPC: F03D1/00
Filed: 2004-05-31
Granted: 2005-10-11
Abstract: A circumferential flow pump capable of obtaining high pressure even in the condition that the voltage applied to an electric drive motor which applies driving force is low is provided. In a groove part (23) of a impeller (2), a first circular arch part (23a) of radius dimension (R1) is formed in one end surface (24) of the impeller (2) and a second circular arch part (23b) of a radius dimension (r1) is formed in the other end surface (25) of the impeller (2) so as to provide a convex partition wall, and in two end surfaces of the impeller (2), when circular feed passages (5f, 6f) formed by semicircular wall surfaces of radius dimensions (R2, r2) are provided in pump cover (5) and pump base (6) respectively, the radius dimensions (R1, r1) of the circular arch part (23a, 23b) are made larger than the radius dimensions (R2, r2) of the semicircular wall surfaces.
Patent TW-I283819-B (TW)
Title: Method for computer simulation of the core in a core-reactor, computer-readable medium and computer simulator
Inventor: BOEER RAINER
IPC: G21C17/00
Filed: 2004-06-25
Granted: 2007-07-11
Abstract: In a method for computer simulation of the core (1) in a core-reactor, the core (1) is divided into several rough meshes (2), where a part-region (8), which includes a rough mesh (2), of the core (1) is arranged to at least one rough mesh (2). The part-region (8) includes this rough mesh (2) and has a buffer-region (10) surrounding in the horizontal plane the rough mesh (2), said buffer-region (10) includes at least the rough mesh (2) which is directly adjacent to said rough mesh (2). Said part-region (8) is divided into several fine meshes (6), which are finer than the rough mesh (2). In a 1st calculating step, a model of the core (1) is calculated with a nodal calculating method on the basis of the data-sets which are respectively corresponding to each rough mesh (2). Then in a 2nd calculating step a model for the part-region (8) is calculated with a nodal calculating method on the basis of the 2nd data-sets which are respectively corresponding to each fine mesh (6) of a part-region (8) and with the flow (J) calculated in the 1st calculating step and at the edge of said part-region (8).
Patent TW-I288470-B (TW)
Title: Isolated high-voltage LDMOS transistor having a split well structure
Inventor: HUANG CHIH-FENG
IPC: H01L27/088
Filed: 2004-08-03
Granted: 2007-10-11
Abstract: The isolated high-voltage LDMOS transistor according to the present invention includes a split N-well and P-well in the extended drain region. The P-well is split in the extended drain region of the N-well to form a split junction-field in the N-well. The split N-well and P-well deplete the drift region, which shifts the electric field maximum into the bulk of the N-well. This achieves a higher breakdown voltage and allows the N-well to have a higher doping density. Furthermore, the LDMOS transistor according to the present invention includes a N-well embedded beneath the source diffusion region. This creates a low-impedance path for the source region, which restricts the transistor current flow between the drain region and the source region.
Patent TW-I241727-B (TW)
Title: Light emitting diode structure and manufacturing method of the same
Inventor: LEE SHIH-CHANG
IPC: H01L33/00
Filed: 2004-08-05
Granted: 2005-10-11
Abstract: A light emitting diode (LED) structure comprises an substrate, a N-type epitaxy layer formed on the substrate, a light emitting layer formed on the N-type epitaxy layer, a P-type epitaxy layer formed on the light emitting layer, a nano-meter conductive layer formed on the P-type epitaxy layer, a transparent conductive layer formed on the nano-meter conductive layer, a first electrode formed on the transparent conductive layer to be a P-type bonding pad, and a second electrode formed on the N-type epitaxy layer to be a N-type bonding pad.
Patent TW-I266843-B (TW)
Title: Magnetic force type grease-injecting device
Inventor: LIOU YU-MING
IPC: F16N7/14
Filed: 2004-08-20
Granted: 2006-11-21
Abstract: A magnetic force type grease-injecting device includes: a base having a center provided therein a grease passage, a hollow part arranged above the grease passage, and a first groove provided along the hollow part, and a magnet of S polarity fitted in the first groove; a bladder filled with grease, which has an outer edge formed thereon continuous concaves and convexes, a top surface, and a lower terminal formed thereon a lower connection terminal for connecting to the hollow part; a magnet of N polarity mounted on the upper surface; and a flow control valve installed on the grease passage. The magnetic force created by the magnetic flux effect between the N and S magnets compresses the bladder and thus extrudes the grease out of the passage uniformly. Therefore, there is no need to use the electrical power, motor, piston, and mechanical transmitting means as in the conventional grease ejecting device.
Patent TW-I257006-B (TW)
Title: Integrated printed circuit board and test contactor for high speed semiconductor testing, contactor for testing semiconductor packages, and integrated circuit test interface system
Inventor: TREIBERGS VALTS
IPC: H01L21/66
Filed: 2004-08-26
Granted: 2006-06-21
Abstract: An integrated printed circuit board and test contactor for high speed semiconductor testing having an alignment housing with a cavity for receipt and positioning of the integrated circuit to be tested, a printed circuit board having a non-conductive elastomer portion positioned along a surface of the printed circuit board and an electrically balanced microwave transmission line structure having flexible fingers for transmitting test signals from the integrated circuit through the printed circuit board. A U-shaped ground element extends around the microwave transmission line structure.
Patent TW-I256021-B (TW)
Title: Apparatus and method for rendering graphics primitives using a multi-pass rendering approach
Inventor: HONG ZHOU
IPC: G06T15/40
Filed: 2004-08-27
Granted: 2006-06-01
Abstract: The present invention is generally directed to a multi-pass rendering system and method. In one embodiment, in first pass of a graphics primitive data through a graphics pipeline, a compressed z-buffer is generated for the primitive. A primitive mask is also generated, which indicates whether all pixels if the primitive are hidden from view. In a second pass, graphics data for a given primitive is passed through the pipeline, only if the primitive mask for that primitive indicates that some portion of the primitive is visible. Thereafter, a two-level z-test is performed on that primitive. In the two-level z-test, a first level comparison is made on groups of pixels at a time, using the compressed z-buffer created in the first pass.
Patent TW-I325001-B (TW)
Title: Process for the preparation of (mercaptoorganyl)alkoxysilanes
Inventor: KORTH KARSTEN
IPC: C07F7/18
Filed: 2004-11-03
Granted: 2010-05-21
Abstract: Preparation of (mercaptoorganyl)alkoxysilanes (I) comprises reacting alkali metal sulfide with a mixture of (haloorganyl)alkoxysilane (II) and (haloorganyl)halosilane (III) in an alcohol with exclusion of air and at elevated pressure.
Patent TW-I274152-B (TW)
Title: Hydrogen sensor device and method for fabricating the same
Inventor: CHEN HUE-YING
IPC: G01N27/00
Filed: 2004-11-05
Granted: 2007-02-21
Abstract: A hydrogen sensor device and a method for fabricating the same are disclosed. The hydrogen sensor device is based on metal nanoparticle/semiconductor Schottky diode, wherein the metal nanoparticle layer is used as a Schottky gate. For the deposition of metal nanoparticle layer, an electrophoretic deposition technique combining with micro-manufacturing processes is employed. Due to high catalytic activity and large specific surface of nanoparticles, the sensor device exhibits superior sensing performances with high sensitivity, wide detection range and speedy response rate. In this fabrication process, the electrophoretic deposition has the advantages of easy operation, simple equipment and mass production.
Patent TW-I361398-B (TW)
Title: Method, apparatus, and computer program product for reducing mosquito noise in an image frame of a video signal.
Inventor: SHYSHKIN VYACHESLAV
IPC: G06T5/10
Filed: 2004-11-29
Granted: 2012-04-01
Abstract: Disclosed herein are methods and apparatus, including computer program products, implementing and using techniques for reducing mosquito noise in an image frame of a video signal. A window of the image frame is provided. The window includes a plurality of pixel values. One of the pixel values is selected from the pixel values in the window to define a modified window of pixel value differences. A local mean (DC) value is computed based on the pixel value differences. A mosquito noise reduction value is also computed based on the pixel value differences. An artifact attenuation factor is computed as a function of a dynamic range measure of the pixel value differences. A weighted sum of the mosquito noise reduction value and the local mean value, applying the artifact attenuation factor, and the selected pixel value, is computed to generate a modified pixel value.
Patent TW-I262150-B (TW)
Title: Bicycle disc brake stopper allowing multi-directional adjustment
Inventor: CHEN RUEI-BIN
IPC: B62L1/06
Filed: 2004-12-03
Granted: 2006-09-21
Abstract: This invention relates to a bicycle disc brake stopper allowing multi-directional adjustment, the stopper includes: a mounting seat mounted to a front fork; and a brake body for braking a brake disc. A slit is formed to one of the sides of the brake body. The slit is provided therein at each of opposing sides thereof with a lining so as to be located at opposing sides of the brake disc. The opposing sides of the brake body are each provided with an elongated hole extending along an axial direction of the lining, to be joined to the mounting seat and to allow displacement adjustment of the lining body. Furthermore, an adjustment pad is clamped between the mounting seat and the front fork. The adjustment pad and the mounting seat match each other in arcuate configurations so as to provide additional adjustment of the orientation of the brake body. When the orientation of the brake disc is deflected, the brake body can be adjusted to ensure that surfaces of the linings are in parallel with the surface of the brake disc.
Patent TW-I272170-B (TW)
Title: Method for processing stone slab surface
Inventor: LI SHIAN-JIE
Filed: 2004-12-07
Granted: 2007-02-01
Abstract: This invention relates to a method for processing stone slab surface, including the steps of: using gang sawing to cut raw stones and injecting lime liquid and finer sand to obtain plural blanks; cleaning the blank surfaces with diluted hydrochloric acid solution, and then subjecting the blanks to plural fibril brushing processes, and then selectively to baking process or pressurized water jetting process so as to form various stone slabs. Surfaces of the stone slabs (from coarse to fine) are processed by the fibril brushes sequentially to enhance the overall surface quality of the stone slabs, thereby featuring the surfaces of the stone slabs with brilliance and roughness, allowing easy removal of the surfaces of the stone slabs. Since the gang sawing operation implements fine particles to perform the cutting, it ensures thinner sawing paths on the surfaces of the stone slabs and can reduce waste of the raw stones.
Patent TW-I274788-B (TW)
Title: Method for fabricating L10 phase alloy thin film
Inventor: KUO PO-CHENG
IPC: C23C14/34
Filed: 2004-12-10
Granted: 2007-03-01
Abstract: A method for fabricating an L10 alloy film is provided. The method includes steps of (a) providing a substrate; (b) heating the substrate as a preheated substrate at a first temperature ranged from 100 DEG C to 600 DEG C for a time period ranged from 5 minutes to 120 minutes, and then cooling the substrate to room temperature in the sputtering chamber; (c) depositing an alloy film on the preheated substrate; and (d) annealing the alloy film at a second temperature ranged from 200 DEG C to 500 DEG C to form the alloy film.