Patent GB-1436345-A (GB)
Title: Semiconductor switching circuit
IPC: H03K3/353
Filed: 1973-05-09
Abstract: 1436345 Clock pulse generators; logic circuits GENERAL INSTRUMENT CORP 9 May 1973 [24 July 1972] 22175/73 Heading H3T [Also in Division G4]  In a circuit comprising semi-conductor switches QC, Figs. 1 and 5, actuated under the control of timed clock signals # to transfer signals, at least one of the switches such as QC 1 , Fig. 1 or QC 2  and QC n , Fig. 5, requires more usable clock time for transferring signals than others of the switches, two sets of clock signals #1F, #2F and #1S, #2S are generated, Fig. 3, each set includes out of phase signals and corresponding signals of each set are like phased and the clock signals of a first of the sets of clock signals is operatively connected to at least one of the switches QC 1 , QC 2 , QC n  requiring the more usable clock time and a second of the sets of clock signals is operatively connected to others of the switches so as to provide the at least one switch QC 1 , QC 2 , QC n  with increased usable clock time for signal transfer. The FET clock pulse generator shown in Fig. 3 produces two pairs of clock pulses #1F, #2F and #1S, #2S (Fig. 4, not shown) from a single clock pulse input to Q 1 . These clock pulses are delyed due to inherent propagation delays in the FET stages 24, 26, 40, 46 and the trailing edge is delayed due to the load capacitance CL, CH connected to the outputs 32, 48. Additional circuitry may be provided for generating pairs of clock signals having three four or more phases. In order to reduce this edge delay for the pair of clock pulses #1F and #2F so as to provide maximum usable clock pulse time the clock pulses #1F and #2F are used to switch the input and output stages only of a shift register, Fig. 1, which are slower in transferring signals than the intermediate stages of the register due to connections to input and output circuits such as TTL logic chips. The intermediate stages are clocked by the other pair of clock pulses #1S, #2S which have greater propagation and edge delays due to the greater number of clock pulse generator stages and the greater total capacitive loading CH. These clock pulses #1S, #2S provide less usable clock pulse time, but sufficient to switch the faster acting intermediate stages of the shift register, which enables reduced clock pulse generator power. A FET Q 3  is connected in parallel with a FET Q 2  and is effective to OR the inverted output with the complementary #2F clock phase to insure against slight overlaps.  The pairs of clock pulses from the clock generator of Fig. 3 may be used in driving an MOS multiplexed shift register, Fig. 5, where a first register 50 samples data input during the first clock pulse signal and a second register 52, identical to the register 50, samples the data during the second clock signal. The data is sampled twice in each clock period and the system operates at twice the frequency of the system clock. An output circuit 70 including a NOR gate 100 and a push pull output amplifier 102 provides multiplexing of the data occurring at both the register outputs 68 so as to provide a common output. When a write input signal at 60 is negative the outputs 94, 82 from the write input circuit 58 turn FET Q 28  off and FET Q 15  on so that data recirculate circuit 62 functions to feed the output data from 68 back to input 64 via FET Q 29a  to an input FET Q 29  of the shift register 50. The conduction of FET Q 15  blocks output from the data input circuit 54. When the write input signal at 60 is positive, FET Q 28  is conductive and FET Q 15  is turned off so that a data input signal at 56 is fed via FET Q 21  to an input FET Q 22  of the shift register 50. The output from the recirculate circuit 62 is blocked by the conductive FET Q 28 . The use of the clock signals #1F and #2F to control the two stage data recirculate circuit 62 ensures synchronization of the input signals to the NOR gates Q 26  and Q 28 , Q 29  and Q 32  and Q 13  and Q 15 . As the data transfer through the data input circuit 54 or the data recirculate circuit 62 is obtained under control of the clock signals #1F, #2F the first stage of the first bit B1 of the register 50 may invert and transfer data within the same clock cycle by clocking the transfer FET QC 1  with the #2S signal. If the next stage of the register S2 is clocked by the #1F signal the first stage of the second bit B2 may be clocked by the #1S signal to obtain two inversions within one half of one clock cycle. At the end of two clock cycles the-data has been transferred to the output of bit B2 of the register thereby recovering the one bit delay which would otherwise be incurred by the two stage data input or data recirculate circuits 52 and 62. The alternate use of the #F and #S clock signals may be continued beyond the second bit B2 but will increase the propagation and edge delays of the #F clock outputs. The clock signals #1F and #2F are preferably not used for more than a few bits of the register, the bulk of the register being clocked by the clock signals #1S and #2S.