Patent SE-7409882-L (SE)
Inventor: KITAGAWA N
IPC: H03K19/0185
Filed: 1974-07-31
Abstract: 1484941 Transistor switching circuits TEXAS INSTRUMENTS Inc 1 Aug 1974 [2 Aug 1973 (5)] 33988/74 Heading H3T [Also in Division G4] A sense amplifier 6, Fig. 4, in an LSI semiconductor random access memory (see Divisions G4-G6) comprises cross-coupled driver transistors 3, 31 having sense nodes A, B respectively coupled to left-hand and right-hand halves of the respective column D n  of the memory, the sense nodes A, B being each precharged to a predetermined voltage level representing approximately halfway between the voltage levels corresponding to logical 1 and logical 0 prior to each read or write operation. Data is stored in the form of opposite logic indications on each side of the sense amplifier 6, e.g. a logical 1 is stored as a high level signal in the left-hand half of the column D n  and as a low level signal in the righthand half. In operation, lines PVG1 and PVG0 of a charging circuit 38 are precharged to voltage levels respectively representing logical 1 and 0, these voltage levels being combined by a transistor 5 to give the predetermined voltage level which is applied to capacitors C, D of dummy cells located on each side of the sense amplifier 6. Selection of a storage cell of the memory to the left of sense amplifier 6 simultaneously selects the right-hand dummy cell, and vice versa, so that the voltage from the selected storage cell and the predetermined voltage level are respectively applied to the sense nodes A, B. If a logical 1 is applied to node A, transistor 3<SP>1</SP> conducts and clamps node B to ground potential, node A charging up to logical 1 from a positive voltage source V DD  via a transistor 15, the converse occurring if a logical 0 is supplied to node A. At the end of the charging up of node A its voltage may be read out or overwritten, but it is in any case supplied back to the selected storage cell for refreshing purposes. Selection of a storage cell of a particular row for reading or writing thereby causes all the storage cells of that row to be refreshed. An address buffer one stage of which is shown as 2 in Fig. 8, receives an input A 0  from external TTL and produces true and complement outputs #A 0 , #A 0  suitable for the MOS logic of the memory. By means of the direct connection of the source of a driver transistor 25 to the buffer input A 0 , it is stated that a smaller and faster first inverter transistor 26 may be employed than in the prior art. In operation, a node 29 is precharged from source V DD  via a transistor 27, the node 29 then being conditionally discharged depending on the gate voltage of transistor 25 which in turn depends on the voltage applied to input A 0 . If the voltage at output A 0  is high, that at output A 0  is low and, since a transistor 31 is conducting, power is thereby dissipated via transistors 31 and 39. This power is conserved by transistors 71, 73 sensing the high voltage level at output A 0  and turning off transistor 39 via a transistor 51. No current thereby flows through transistor 31, but transistor 31 is still on and so clamps output A 0  to ground potential. Operation is analogous when output #A 0  is low and #A 0  is high, output A 0  then being clamped to ground potential. Reference has been directed by the Comptroller to Specifications 1,409,910 and 1,244,683.