Patent GB-1452717-A (GB)
Title: Method applicable to the manufacture of an integrated circuit structure
IPC: G03F1/08
Filed: 1975-04-21
Abstract: 1452717 Semi-conductor integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 21 April 1975 [17 June 1974] 16303/75 Heading H1K An integrated circuit is formed on a silicon substrate by depositing thereon an insulant layer of e.g. SiO 2 , Si 3 N 4 , or A10 by vapour deposition, sputtering or oxidation; on which a metallized inter-connect pattern of e.g. Al, Al-Cu alloy Pt, Pd, Cr or Mo is deposited e.g. by sputtering or photolitho etching, which is connected over through holes (not shown) to semi-conductor devices formed in the substrate surface. Fig. 1A (not shown). An insulant e.g. SiO 2  overlay 13 is deposited on the pattern, in which a positive photoresist layer is conventionally deposited. Masking and exposure forms a photo-resist pattern Fig. 1C (not shown) registering with the depressed areas 15 of the layer 13. The photo-resist mask 14' is then flowed to completely cover the depressed areas Fig. I D by mounting on an apertured rack suspended over a closed bath of photo-resist solvent Fig. 2 (not shown) for exposure to vapour. The solvents may be ethers, esters, ketones, methyl or ethyl cellulose acetate, butyl acetate, glycol monomethyl ether, glycol monoethyl ether, methyl isobutyl ketone, or acetone. Negative photo-resists may also be used e.g. polyvinyl cinnamate or polymethyl methacrylate with trichloroethylene solvent. Thereafter elevations 21 of layer 13 are etched out to planarize layer 13 with e.g. buffered HF, and the residual photo-resist 14' is removed Fig. 1F (not shown) and through holes 24 to the underlying metallization lines 12' are formed by etching with e.g. buffered HF over a further apertured photo-resist mask, Fig. 1H. A subsequent metallization pattern 25 on insulant layer 13 has a portion 26 extending through the holes to contact line 12'. Fig. 1I. The method may be applied to planerize the insulant layers isolating the mesas or pockets of dielectric isolated semi-conductor integrated circuits separated by trenches. In a modification, a substrate of e.g. Si carries a N-epitaxial layer with buried N+ and P+ regions formed at the interface of substrate and epitaxial layer Fig. 3A (not shown) while plural N-pockets or mesas 35 are defined by a pattern of trenches 34, Fig. 3B. A Si 3 N 4  layer 36 is applied to the surfaces of 35 over layer,37 of thermal SiO 2  by photo-litho etching openings 38 through the layer 36 over a SiO 2  mask with hot H 3 PO 4 , and then etching openings 39 through layer 37 with buffered HF. Using the composite layers as mask, trenches 34 are etched with HNO 3  + HF solution containing I, NH4F, and CH 3 .COOH to undercut at 40 adjacent pockets or mesas 35. A further insulant layer of etch resistant insulant e.g. Si 3 N 4  is deposited by vapour deposition or sputter over the surface to extend into the undercut 40 and the trenches 34. A further layer 42 of isolating insulant e.g. SiO 2  is then deposited to effectively fill the trenches and provide elevated regions 42', Fig. 3D which are removed by etching over a mask produced by depositing and selectively exposing a photo-resist layer Figs. 3E, F, (not shown) the remaining elements of which are flowed to cover the depressed areas of the insulant layer, Fig. 3G, after which the elevated portions are removed by etching with e.g. HF to expose the underlying Si3N4 layer 41 at the surface leaving the trenches filled with SiO 2  at 42, Fig. 3H. The residual photo-resist is removed, and layers 41, 36 are removed by etching with hot H 3 PO 4  which does not affect SiO 2 , Fig. 31 (not shown). Impurities are then doped into selected areas by removing the overlying SiO 2  layers and diffusing or ion implanting. The region 48 to be doped with P type impurities into N-pocket 35' is defined by photoresist mask 45, over which the exposed SiO 2  layer within the mask aperture is etched out with buffered HF, and the residual Si 3 N 4  layer 41' in the undercut and on the sidewalls of pocket 35' are unaffected, Fig. 3J. B is introduced as impurity to form region 48 without intrusion, along the sidewalls of pocket 35'.