Patent GB-786734-A (GB)
Title: Improvements in or relating to electronic digital computing machines
Inventor: WILLIAMS FREDERIC CALLAND
IPC: G06F15/78
Filed: 1953-03-20
Abstract: 786,734. Digital electric calculating apparatus; electric digital-data-storage apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. March 15, 1954 [March 20, 1953], No. 7835/53. Class 106 (1). In an electronic digital computer comprising a main date store which operates in the parallel mode and comprises separate storage devices, one for each word digit, and computing circuits which operate in the series mode, the digit signalling speed in the computing circuits is a multiple of that employed in each storage device. General arrangement. The computing machine shown in Fig. 1 comprises a main store MS comprising 10 similar units each comprising a C.R.T. CO ... C9 and associated read/write circuit RW0 ... RW9 as described in Specification 705,474. The basic word comprises 10 binary digits, one of which is stored on each C.R.T. screen which has a capacity of 32 lines, each of 32 digits. Words are selected by X- and Y-deflection waveform generators.XG, YG which apply the same deflecting voltages over leads 100, 101 to all the C.R.T.'s. Read-out from MS is effected by unit ROU (described below) comprising a delay line for converting the parallel input, obtained over leads 103 from terminals 313 of circuits RW0-RW9, into a series-mode pulse train at output terminal 500. A write-in control unit WIU similarly converts a series-mode train applied to its input terminal 401 into simultaneous parallel outputs on leads 102 connected, to MS. The machine functions similarly to those described in Specifications 731,341 and 742,522, but differs in that delay line stores replace C.R.T.'s in the accumulator A, B-store BS and the control unit which comprises a " control instruction " store CIS (Fig. 7, not shown), and a closed two-word loop CL including an adder ADR, having a carry digit loop 113, and delay lines DLU1, DLU2. Diode coincidence gates such as G4, G5 control the connections between the machine elements. The basic waveforms, Fig. 11, are generated by unit WFG including a 1 mc/s. digit-period defining oscillator and mountable and bi-stable hand valve trigger circuits (Fig. 2, not shown), and comprise regular pulses, Fig. 11 (a), (d) and (e), occurring at the digit frequency, pulses p<SP>0</SP>-p<SP>9</SP> (see Fig. 11 (b) and (c)) defining the 10 digit periods in a " beat " or minor cycle, waveforms, Fig. 11 (f)-(i), for controlling the C.R.T. stores, and timed pulses, Fig. 11 (j)-(n), for controlling units WIU, ROU, XG and YG. Beat-defining waveforms are also obtained, the operative cycle or " bar " comprising 8 alternating scan and action beats S1, A1, S2, A2, S3, A3, S4, A4. During the scan beats, a scan control word (SC) in delay line DLU1 sets XG, YG to a storage position to be regenerated, the SC word being increased by " 1," by pulse Po applied to lead 115, every time it circulates through the adder ADR. During action beats, the other word in loop CL, either the " control instruction " CI or the address portion PI (2) of the " present instruction" PI, is in the operative address-selecting position in line DLU1. The present instruction comprises, as well as portion PI (2), a first function-defining 10-digit portion PI (1) which is set up on staticizor STR, and the machine is arranged to operate on numbers also of 20 digits in two 10- digit portions. Read-out unit; delay lines and pulse-shaping circuits. In the unit ROU, Fig. 1, the input terminals 510-519 are connected through circuits, VC10-VC19, Fig. 5, each comprising a normally non-conducting amplifier valve such as V519, to a delay line comprising sections DS500-DS510. These sections are of the distributed capacitative type and comprise an inductive winding on an earthed metal core or metal-coated insulating rod. In operation, when a positive read strobe pulse, Fig. 11 (k), is applied during digit period P8 through cathode follower V501 to lead 501 and the control grids of the amplifier valves, such as V519, if a relatively high potential is applied from MS Fig. 1, to any of the terminals 510-519 (indicating that " 0 " is being stored in the selected address of the associated C.R.T.), the corresponding valve will conduct, thus generating a negative pulse in the delay line. Since the sections DS501-DS510 each provide a delay of 1Ás, and a further ¢Ás delay is provided by DS500, a series-mode pulse train (negative pulse for " 0," no pulse for " 1 ") representing the stored word is obtained at the output end of the delay line and, after being changed in form in a pulse-shaping circuit, emerges from terminal 500 in synchronism with the commencement of the next beat period. The pulse-shaping circuit comprises an inverter V504, the output from which is applied to the control grid of normally cut-off valve V505. The latter is thus rendered conductive for each " 0 " and the resultant negative anode potential prevents normally cut-off valve V506 being rendered conductive in response to the positive pulses MKD, Fig. 11 (d), applied to diode D506. For each " 1," however, V506 conducts and the sharp negative pulse at the anode is applied through capacitor C507 and diode D509 to the control grid of cathode follower V507 and charges capacitor C508; a negative-going output pulse is thus obtained at 500 of the form MDP, Fig. 11 (a), the pulse being terminated after 9/10 Ás by a positive pulse MKB, Fig. 11 (e), applied through diode D508. Write-in unit. The unit WIU, Fig. 1, comprises a delay line (Fig. 4, not shown) similar to that for the read-out unit, Fig. 5, and similar amplifier valve circuits VC connecting points or the time to output terminals 410-419. When a series-mode pulse train applied from terminal 401 through an amplifier circuit to the line reaches the appropriate position a write strobe pulse, Fig. 11 (j), is applied to all the circuits VC to produce the parallel output. Deflection waveform generators; control loop. The units XG, YG, Fig. 1, are similar and are each controlled from 5 tappings, Fig. 6, on delay line DLU1. In the unit XG, these tappings are connected through cathode followers V600-V604 to diode coincidence circuits which include resistors R600-R604 of values so graduated that if a negative pulse (representing " 1 ") is present at the appropriate point in DLU1 when a negative strobe pulse, Fig. 11 (i), is applied to lead 604, 16, 8, 4, 2, and 1 units of current respectively are directed to the control grid circuit of valve V605, thus building up a corresponding charge in a feedback capacitor C600 connected via terminal X1 to one of the output leads 100. The other lead is connected to terminal X2 which receives a paraphase deflecting voltage from a circuit including valve V607 and capacitor C601. The valves V605, V607 are reset to an initial state at the beginning of each beat by waveforms (see Fig. 11 (m)) applied through diodes D601, D604. The series-mode pulse trains in loop CL, Fig. 1, are applied from the adder ADR to input terminal 600 of line DLU1 and are passed through re-shaping circuit 602, Fig. 6, before proceeding through similar delay line DLU2. The delays are chosen to make the total loop circulation time 20Ás, i.e., two word times. Accumulator and B-store. The accumulator A, Fig. 1, may comprise an input terminal 801 connected to one input 803, Fig. 8, of adder 802 via gate, G800, or via gate G801 and a 10-Ás delay 822 formed by delay line 805 and reshaping circuit 806. This enables a 20-digit number to be entered in two parts as described below. The adder output is applied via two 10-Ás delays 820, 821 to output terminal 800 and to gate G803 and the second adder input 804. The store BS may comprise 4 storage loops comprising delay lines 902, 905, 908, 911, Fig. 9, and recirculation gates G909, G910, G911, G912 respectively. Selection of a storage loop for entry of a new B-word or read-out of a B- word into ADR, Fig. 1, for modifying the present instruction is effected by selective application of potentials from staticizor STR input or output gates such as G901 or G902. In a modification (Fig. 12, not shown), a combined accumulator and B-store comprises two series of storage loops and a common arithmetic (adding or subtracting) circuit. Operating sequence. During the first beat S1 of a bar, the control instruction CI is passed from store C15, Fig. 1, through gate G3 to adder ADR where " 1 " is added thereto, the main store being regenerated under control of word SG in DLUI. During the following beat A1, the new CI in DLU1 selects the address of the function-selecting portion PI (1) of the present instruction which is read into unit ROU, and gate G1 passes the word SC from DLU2 to the adder ADR; this gate is always open during action beats so that SC is circulated continuously. During beat S2, gate G6 passes PI (1) to staticizor STR, and gate G1 passes CI to the ADR to obtain the address of PI (2) which is selected during A2. During beat S3, the CI word is diverted through gate G2. into store CIS and PI (2) is passed to the control loop through gate G7; this word PI (2) has " 1 " added thereto in ADR, as well as being modified by the B-word applied through gate G8, before being set up in DLU1 during beat A3 to select the main store address for the first portion of the number to be operated on. If an inward transfer to MS is selected by staticizor STR, gate G5 is opened during the previous beat 53 to pass this number portion from tne accumulator A to unit WIU. If an outword transfer is selected, the number portion at the selected address is passed to unit ROU during A3 and is passed during the following beat S4 either to A via gates G4 and G800, Fig. 8, or to BS, Fig. 1, via gate G9. Also, during S4, " 1 " is added to the PI address word in adder ADR, so as to select the address for the second portion of the required number during the final beat A4. Thus for inward transfer, gate G5 is open again during beat S4, ard for outward transfer to the accumulator, gate G4 is open during beat S1 (or S5), the oper