Patent GB-1030553-A (GB)
Title: List control in a digital data processor
IPC: G06F9/355
Filed: 1964-06-10
Abstract: 1,030,553. Computer programming arrangements; sorting data words. BECKMAN INSTRUMENTS Inc. June 10, 1964 [June 10, 1963], No. 24023/64. Headings G4A and G4M. An arrangement for enabling a digital computer to address sequentially addresses in a list, uses " control words," Fig. 2b (not shown), each consisting of three address words occupying consecutive locations in the store. The three address words contain respectively the current address, the end address and the start address of the list. In addition, the current address word has three code bits A, B, C, which indicate respectively whether the address is direct or indirect, whether a list exists or not, and whether or not the current address is equal to one of the other two addresses, a one indicating the first alternative in each case. Moreover, the instructions indicate whether the current address is to be incremented, decremented, or left static during the operation. Examples of instructions are shown at 226, Fig. 7 (not shown), the 1 after LOD and STO indicating that the operation is in the incremental mode. Fig. 7 shows an outline of the operations used to re-order data A1, B1, C1 to A100, B100, C100. It is assumed that the data originally occupies locations 1000 to 1277 and is to be placed in locations 2000 to 2077, 3000 to 3077 and 4000 to 4077 as shown at 221, 222, 223. It should be noted that all subscripts and addresses are in octal notation. The instruction at location 563 indicates that the data at location 300 is to be loaded into the accumulator and that any lists are to be followed in the incremental mode. At location 300 is found a list control word having a current address 1277, end address 1277 and start address 1000. The code bits ABC are 11 indicating that the address is direct, a list exists and that the current address is equal to either the end or start addresses. In operation, the current address is incremented before the instruction is performed, and the lists are cyclic. Thus the current address is changed from 1277 to 1000 and the instruction is then executed, since the A bit is 0 and indicates a direct address. Thus A1 is transferred from location 1000 into the accumulator. The control then jumps to the instruction at 565 which indicates that the contents of the accumulator are to be transferred to location 100. However, at 100 is found a list control word with the A bit equal to one so indicating that the address there is indirect. Here the current address is made equal to 1400 before moving to the next stage. At 1400 is a control word having A = 1 (location 574 is an indirect address) and B=0 (no list). At 574 is found another control word, this time the address is direct and a list exists. The current address becomes 2000 and the instruction is executed, transferring A1 to the location 2000. The control then jumps to the instruction at 567 which transfers control to 563 and the sequence starts again, B1 being transferred through the accumulator to location 3000. The control skips alternate instructions, e.g. those at 564, 566 until all the lists controlled by the preceding instruction are " at bound," i.e. their current addresses are all equal to start or end addresses. When this happens, the next instruction will not be skipped, thus an automatic exit from this cycle of commands is provided. It is clear that any operations may be performed on data loaded into the accumulator in this way. A description of the hardware associated with this list control is given with reference to Fig. 1 (not shown). It includes a memory, which may be of magnetic cores, memory address and memory buffer registers, a programme address register and an address modification register. An instruction is read from the memory into the memory buffer and back to the memory, and the address portion is read into the address modification register. Various operations which are not described take place then, one being to read the mode (incremental, decremental or static) into the sequence control unit, and the contents of the programme address register are increased by 1. The current address is read into the address modification register and incremented if not equal to the end address and a list exists. If equal to the end address it is replaced by the start address. If there is no list (as at 1400), the current address remains static. Further courses of action are then determined by the sequence control according to the value of A, whether the lists are all " at bound " and whether the incremented current address is now equal to the end address. These courses are described with reference to Figs. 4 to 5 and 8 to 10 (not shown).