Patent ES-364238-A1 (ES)
Title: Improvements in or relating to computers
IPC: G06F9/48
Filed: 1969-02-28
Abstract: A computer processes programmes on different priority levels with periodical interruptions for recommencing the programme on the highest priority level a first register being provided to start processing of the programme on a given level upon completion of the programme on the next higher level by selecting a pointer word in a data store giving the address of the first instruction in the new level, a second register being provided to load the first and a third being provided to block this loading, the pointer word belonging to a chosen level (not the lowest) storing at least temporarily the address of the first instruction of a first section of the lowest level programme, the second register being set at the end of each programme section on the lowest level to attempt to cause the first register to select the pointer word of the chosen level and thus cause processing of the first section of the lowest level programme, the highest level programme setting the third register to permit this attempt and the first section of the lowest level programme setting it to block the attempt. The computer controls a telecommunication system, normally processing a predetermined sequence of lowest level programme sections (relating to detecting subscriber calls, routine checks, typing of fees), but every 10 msecs. this is interrupted by a clock, and after completing the current microprogramme of the current section, the highest level programme (relating to sensing a dialling signal) is processed, followed by an intermediate level programme, followed by the remaining microprogrammes of the interrupted lowest level programme section. The three registers each have two stages relating to the highest and intermediate levels respectively (when both its stages are at 0, the first register selects the lowest level). The three registers are controlled as above by the microprogrammes on the three levels so that completion of the interrupted lowest level programme section is followed by processing of the first section of the lowest level programme, by reference to the pointer word of the intermediate ("chosen") level, but processing of any non-interrupted section of the lowest level programme is followed by processing of the next section in order since the third register blocks the reference to the intermediate level pointer word in this case. The intermediate level pointer word is loaded from a pointer word for the first section of the lowest level, and a pointer word for the start of the intermediate level, alternately. A pointer word is provided for the start of the highest level. Transfer between levels uses the pointer words. Interruption as above causes the start address of the next microprogramme of the current section to be stored in the data store to permit resumption on return to the lowest level. An instruction store feeds an operations register which is decoded in three decoders to control a microprogramme sequencer utilizing a shift register. The intermediate level may be used purely for the return to the first section of the lowest level programme in which case its pointer need not have its contents alternated as described above.