baber/WOPTO huggingface dataset:
Patent TW-420879-B (TW)
Title: Solar cell and method of manufacturing the same
Inventor: MOROOKA HISAO
IPC: H01L31/04
Filed: 1998-05-15
Granted: 2001-02-01
Abstract: In a solar cell including a photoelectric conversion layer 14 disposed on a flexible substrate 11 and constituted by a laminated layer of non-single crystalline silicon thin films, the flexible substrate 11 has a coefficient of linear thermal expansion of is 2.0 ppm to 10.0 ppm. By this, the coefficient of linear thermal expansion of the flexible substrate 11 and that of the photoelectric conversion layer 14 become close to each other, so that warp and deformation during manufacturing steps and after the steps are decreased. Further, since stress applied to the photoelectric conversion layer 14 is also lessened, the photoelectric conversion efficiency can be increased.
Patent TW-384541-B (TW)
Title: Substrate of semiconductor integrated circuit
Inventor: KUNIKIYO TATSUYA
IPC: H01L27/04
Filed: 1998-05-18
Granted: 2000-03-11
Abstract: The present invention discloses a substrate for semiconductor integrated circuit with good durability to softerror, latch-up and electrostatic discharge (ESD) problems in IC. While forming individual areas in memory cell 5, logic unit 6 and I/O unit 8, it will change the film thickness of semiconductor surface layer with lower impurities concentration than single crystal substrate 51, 55 according to locally different durability requirement.
Patent TW-393762-B (TW)
Title: Improved signal line driving circuits with active body pull-up capability for reducing boost delay
Inventor: SIM JAI-HOON
IPC: G11C11/408
Filed: 1998-05-29
Granted: 2000-06-11
Abstract: Driving circuits with active body pull-capability for inhibiting boost delay include main, subordinate and boosted signal lines and a first driver circuit electrically coupled to the main signal line, to drive the main signal line at a first potential (e.g., Vcc). A second driver circuit, electrically coupled to the boosted signal line, is also provided to drive the boosted signal line at a second potential (e.g., Vpp) greater than the first potential. A first field effect transistor is provided as a pull-up transistor which has a gate, drain and source electrically coupled to the main signal line, the boosted signal line and the subordinate signal line, respectively. To reduce body-bias effects which might inhibit the speed and pull-up capability of the pull-up transistor, a second field effect transistor is provided to actively pull-up the body (e.g., active region) of the pull-up transistor. This second field effect has a gate, drain and source electrically coupled to the main signal line (or boosted signal line), the boosted signal line and the body of the pull-up transistor, respectively. The second field effect transistor is designed to provide a pull-up function to the body of the pull-up transistor so that the magnitude of the reverse bias between an inversion layer channel (e.g., N-type) and the body region (e.g., P-type) of the pull-up transistor is reduced when the pull-up transistor is turned on to provide a voltage boost to the subordinate signal line. This reduction in the reverse bias results in a reduction of the body-bias effect and the increase in threshold voltage typically associated with the body-bias effect.  An integrated circuit, comprising: main, subordinate and boosted signal lines; means, electrically coupled to said main signal line, for driving said main signal line at a first potential; means, electrically coupled to said boosted signal line, for driving said boosted signal line at a second potential, greater than the first potential; a first field effect transistor having a gate, drain and source electrically coupled to said main signal line, said boosted signal line and said subordinate signal line, respectively; and a second field effect transistor having a gate, drain and source electrically coupled to one of said main and boosted signal lines, said boosted signal line and a body region of said first field effect transistor, respectively.
Patent TW-392408-B (TW)
Title: Modem apparatus
Inventor: ARAI KOSUKE
IPC: H04M11/06
Filed: 1998-06-26
Granted: 2000-06-01
Abstract: A modem apparatus (2) performs modulation and demodulation between a telephone circuit (5) and a terminal apparatus (1). The modem apparatus includes a modem circuit (4), and a codec circuit (18) performing conversion between an analog signal and a digital signal. Capacitors (16, 17) are provided between the modem circuit and the codec circuit, a signal supplied from the terminal apparatus and a signal supplied from the codec circuit being supplied to the modem circuit, and a signal supplied from the telephone circuit and a signal supplied from the modem circuit being supplied to the codec circuit.
Patent TW-505516-B (TW)
Title: A pharmaceutical composition for the treatment of diabetes mellitus and conditions associated with diabetes mellitus
Inventor: SMITH STEPHEN ALISTAIR
IPC: A61K31/4436
Filed: 1998-07-17
Granted: 2002-10-11
Abstract: A pharmaceutical composition for the treatment of diabetes mellitus and conditions associated with diabetes mellitus, comprising from 1 to 12 mg of 5-[4-[2-(N-methyl-N-(2-pyridyl)amino)ethoxy]benzyl]thiazolidin-2,4-dione, up to 3000 mg of metformin and from 2.5 to 20 mg of glibenclamide and a pharmaceutically acceptable carrier therefor.
Patent TW-380258-B (TW)
Title: Semiconductor memory device
Inventor: MATSUKI SYOUZI
IPC: G11C29/04
Filed: 1998-08-20
Granted: 2000-01-21
Abstract: A semiconductor memory device used to reduce the number of load capacitors by COMP signal from the defective memory unit detection result. The method is to connect the complementary signals ( address signals A0T~A3T and inversed address signals A0N~A3N) as the individual gate signal of transistors Tr1~Tr4. Therefore, compared to conventional methods, the number of transistors which are set to low level by the COMP signals from the fault address detecting result is half of that of the used method.
Patent TW-391041-B (TW)
Title: Alignment mark structure with dummy pattern
Inventor: CHEN JIA-JEN
IPC: H01L21/304
Filed: 1998-09-24
Granted: 2000-05-21
Abstract: An alignment mark structure with dummy pattern is designed on the surface of a wafer. A dummy pattern is designed on the periphery of each alignment mark. The density of dummy pattern is designed based on the density of the elements. With the alignment mark structure with dummy pattern in accordance with the present invention, the alignment mark is prevented from being over polished in the chemical mechanical polishing process, which may cause an erroneous alignment and a distortion in transferring patterns.
Patent TW-411696-B (TW)
Title: Image sensor
Inventor: SAITOU OUJI
IPC: H04N1/028
Filed: 1998-10-26
Granted: 2000-11-11
Abstract: Inputs and outputs to/from the outside can be performed in a lump by a single connecting medium having connecting terminals for connecting to a plurality of input/output terminals of a sensor board, and connecting terminals for connecting to a lead frame package as a part of a light source.
Patent TW-386928-B (TW)
Title: Pneumatically operated nail driver
Inventor: ISHIZAWA YOSHINORI
IPC: B25C1/00
Filed: 1998-12-15
Granted: 2000-04-11
Abstract: A pusher piston (17) shifts a nail (6a) by a predetermined distance (L) along an eject hole (12) before a driver blade (5) drives the nail (6a). In this case, the predetermined shifting distance (L) of the pusher piston (17) satisfies a requirement that the tip of the nail (6a) protrudes out of the eject hole (12) while the nail (6a) itself is not removed off  a band member (24).  Thus, the nail (6a) is surely held by the band member (24) even when the nail (6a) is positioned at the pusted-out position where the tip of the nail (6a) protrudes out of the eject hole (12).
Patent TW-498219-B (TW)
Title: Image defect detection apparatus and method
Inventor: ISHII TOSHIYUKI
IPC: G03F1/00
Filed: 1998-12-24
Granted: 2002-08-11
Abstract: An image defect detection apparatus comprises a means to prepare two replicates of inspection image from a single inspection image, the first image processing means to process an image applying the expansion filter and the contraction filter in such order for the one of replicated inspection images, the second processing means to process an image using the contraction filter and the expansion filter in such order for the other of replicated digital image information, and an image information outputting means to output image information composed of the differential value respectively outputted from the first image processing means and the second image processing means.
Patent TW-429347-B (TW)
Title: High-speed data transfer system including plurality of memory module and controller
Inventor: TODA HARUKI
IPC: G06F13/42
Filed: 1999-01-20
Granted: 2001-04-11
Abstract: The memory modules 2 and the controller 3 are arrayed and two pieces of clock wiring 4A and 4B are set along the array of modules 2 and controller 3 in a reciprocating way. A first basic clock TCLK and a second basic clock TCLK2 having a double cycle of that of the TCLK are supplied to the modules 2 and controller 3 via the going wiring 4A and 4B. The first and second return basic clocks used as RCLK and RCLK2 pass through the turning point and are supplied to the modules 2 and controller 3. The first and second basic clocks, TCLK and TCLK2, and returned first and second basic clocks, RCLK and RCLK2, are fetched by the modules 2 and controller 3. Then the input/output operations of data are controlled synchronously with those basic clocks.
Patent TW-499506-B (TW)
Title: Process for copper etch back
Inventor: YE YAN
IPC: H01L21/302
Filed: 1999-04-02
Granted: 2002-08-21
Abstract: In the preparation of semiconductor structures having multilevel copper conductive features which must be interconnected, it is frequently desired to remove portions of a copper layer deposited over a substrate. In particular, where lines and contacts are created by depositing a copper layer to fill trenches and vias present in a dielectric layer, it is desired to remove the portion of the copper layer which does not form the desired line or contact. The present invention provides a method of etching a copper layer (film) to remove the portion of the film which is not part of the desired conductive interconnect structure, while avoiding over etching of the structure and the formation of corrosive surface contaminants on the surface of the etched copper. The method of etching is referred to as the etchback process, since, in a typical fabrication process, the deposited copper layer is etched back to the upper or ""field"" surface of a substrate containing trenches and vias which are filled by the copper. The copper layer etchback may be conducted on a substrate surface using a low temperature regime, below about 150 DEG C. Within this low temperature regime, the etchback is preferably conducted using essentially physical bombardment of the copper surface. Or, the etchback may be carried out with the substrate surface at a temperature which falls within a high temperature regime, above about 150 DEG C. Within this high temperature regime, three different etch chemistries may be used. The etch plasma may be formed solely from non-reactive gases; the etch plasma may be formed solely from gases which are produce a reactive species (such as a gas which is a source of chlorine or fluorine), or, the etch plasma may be formed from a combination of non-reactive and reactive gases which are tailored to adjust selectivity and etch rate. When the gas is a source of chlorine or fluorine, it is preferred that the gas be a compound comprising at least one other element in combination with chlorine or fluorine.
Patent TW-428159-B (TW)
Title: Liquid crystal driving circuit
Inventor: NAKAO TOMOAKI
IPC: G09G3/20
Filed: 1999-03-26
Granted: 2001-04-01
Abstract: In the liquid crystal driving circuit of the present invention, a charging capacitor and a distributing capacitor have respective first and second electrodes. The first electrodes of the capacitors are connected together. A first switch is provided to conduct/disconnect the connection of the second electrodes. A selection switch is provided to select or conduct/disconnect first and second reference voltages for the second electrode. An operational amplifier is provided to output an analog signal for a multi-level gradation display in accordance with the amount of the electrode charge of the distributing capacitor and the second reference voltage. A controller alternatively controls the first switch and the selection switch by the analog signal for the multi-level gradation display.
Patent TW-538104-B (TW)
Title: Novel phthalocyanines inks and process for printing image on substrate
Inventor: ROBERTSON COLIN DICK
IPC: C09D11/00
Filed: 1999-06-23
Granted: 2003-06-21
Abstract: Phthalocyanine compounds of formula (1) have utility as colorants in inks for ink-jet printing, where formula (1) represents, in which: M represents a metal or H; PC represents a phthalocyanine nucleus; and R1 represents H or -(CH2)nR3; R2 represents (CH2)nR3; or R1- and R2 together with the nitrogen atom to which they are attached represent a 5 or 6-membered ring; where: n is independently an integer from 1 to 30; and R3 is independently a group selected from hydroxy, sulpho, cyano, -SR4, -CO2R5, -PO3H2 and -NR6R7; where: R4, R5, R6 and R7 independently represent H, C1-30alkyl optionally substituted by one or more groups selected from hydroxy, mercapto, sulpho, carboxy, cyano and PO3H2; V is the valence of Pc divided by the valence of M; X is from 1.2 to 3.8 Y is from 0.1 to 2.7; Z is from 0.1 to 2.7; and X, Y and Z satisfy 2 <= X+Y+Z <= 4.
Patent TW-439040-B (TW)
Title: Information processing apparatus, information processing method and storage medium
Inventor: KOJIMA KIYONOBU
IPC: G06F3/0487
Filed: 1999-06-28
Granted: 2001-06-07
Abstract: The invention relates to an apparatus and a method for information processing allowing a personal computer to pick up an image through operation of a single button. When a half-push switch is turned on, a CPU activates a window of an image pickup application program, causing the window to appear in front of the windows of all other application programs. An image displayed in the window of the image pickup application program is held still even if a personal computer is altered in its orientation. When a full-push switch is turned on, the image in the window of the image pickup application program is stored onto an HDD in a suitable format.
Patent TW-417221-B (TW)
Title: 1:3 mold-type lead-on-chip package structure and its lead frame
Inventor: LU RICHARD
IPC: H01L21/60
Filed: 1999-07-30
Granted: 2001-01-01
Abstract: There is disclosed a 1:3 mold-type lead-on-chip package structure, which has a lead frame for supporting a semiconductor chip. The lead frame has a plurality of wires extended, in a lead-on-chip manner, to the upper portion of the semiconductor chip and at least two flow-agitating plates. Each of the flow-agitating plates is of a down-set design, and there is a height difference between the flow-agitating plate and the lead frame. The semiconductor chip and the lead frame are packaged by an encapsulation body. In accordance with the package structure of the present invention, the semiconductor chip and the flow-agitating plates of the lead frame are located in the center of the 1:3 mold-type molding apparatus when encapsulating, such that the distance to the upper mold is the same as that to the lower mold, thereby avoiding the non-uniformity of mold flow and package warpage problem.
Patent TW-415049-B (TW)
Title: Method of placing the semiconductor die on the transparent glass substrate that has the trace of disposed circuit
Inventor: SHEN MING-DUNG
IPC: H01L23/02
Filed: 1999-08-05
Granted: 2000-12-11
Abstract: This invention is about the method of placing the semiconductor die on the transparent glass substrate that has the trace of disposed circuit. The method includes the procedures as shown in the following. (a) A transparent glass substrate with the trace of disposed circuit is provided, in which a bonding pad installation surface with several bonding pads are formed on the glass substrate. (b) At least one isolation-tape layer with the first and the second sticking surface is provided. The first sticking surface of the isolation-tape layer is bonded with the bonding pad installation surface of the glass substrate. The placing space of contact point used to expose the corresponding bonding pad is formed on each isolation tape layer. (c) One conducting contact point is placed in each placing space of contact point. (d) At least one semiconductor die is provided. Several die installation surfaces corresponding to the contact-point placing space of the isolation tape layer are formed on each semiconductor die. (e) The die installation surface of the semiconductor die is bonded with the second sticking surface of the corresponding isolation tape layer by using the heating method, in which the sticking glue of the second sticking surface has a lower melting point than that of the conducting contact point. Therefore, the sticking glue has been melted and bonded with the die installation surface of the semiconductor before the conducting contact point is melted and bonded with the bonding pad of the semiconductor die so as to seal the conducting contact point in the contact-point placing space.
Patent TW-529916-B (TW)
Title: Natural physiologically active material effective on fish diseases and fish food containing the material
Inventor: HIRAZAWA NORITAKA
IPC: A61K31/25
Filed: 1999-08-24
Granted: 2003-05-01
Abstract: The invention intends to provide a natural physiologically active material effective on fish diseases such as virus diseases, bacterial diseases and parasitic diseases when fed to fish by oral administration, and fish food containing the material. The natural physiologically active material of the invention contains at least one of fatty acids having carbon number 6 to 12 and a material having a vitamin C activity, as required, and effectively acts on the fish diseases. The fish diseases are parasitic diseases, bacterial infections and parasitic infections. At least one of the fatty acids having carbon number 6 to 12 is capric acid, caprylic acid or pelargonic acid.
Patent TW-440978-B (TW)
Title: Ball grid array chip scale package structure
Inventor: SU CHING-HUEI
IPC: H01L23/31
Filed: 1999-10-19
Granted: 2001-06-16
Abstract: A chip scale package structure comprises two elastomer pads between a substrate and a semiconductor chip in which the two elastomer pads are located on the two sides of a slot on the substrate, respectively and keep a predetermined clearance with the slot. The semiconductor chip uses the two elastomer pads to be fixed on the upper surface of the substrate in which the plurality of chip pads of the semiconductor chip are corresponding to the slot of the substrate. The upper surface of the substrate is configured with a plurality of solder ball pads and a plurality of wires. One end of each wire is electrically connected to the corresponding solder ball pads and the other end is electrically connected to the corresponding chip pad of the semiconductor chip. The substrate comprises a plurality of holes corresponding to the plurality of solder ball pads so that each solder ball pad is partly exposed to the hole for configuring a solder ball. The chip scale package structure is electrically connected to the external by the solder ball. The slot of the substrate and the perimeter of the semiconductor chip form an integrated encapsulation. The invention is characterized in that the encapsulating process of the chip scale package structure is completed by performing one gluing and baking step to reduce the time for encapsulation. Furthermore, the invention can reduce the probability for flash from the substrate slot so as to ensure the connection reliability of the solder of solder ball pad.
Patent TW-445319-B (TW)
Title: Driving mechanism of compound knitting needle in narrow width crochet knitting machine
Inventor: MATSUDA YASUHIKO
IPC: D04B25/02
Filed: 1999-10-26
Granted: 2001-07-11
Abstract: There is provided a driving mechanism of a compound knitting needle in a narrow width crochet knitting machine, which can highly accurately control an operation timing and stroke of a compound knitting needle including a hook-like knitting needle and a needle-like slider even in an operation at a speed higher than a conventional case without generating jumping or an error in its operation. A needle bar driving mechanism reciprocates a needle bar (19) fixing and supporting base end portions of the plurality of hook-like knitting needles (11) via a first rod (24) at a desired timing, and includes a rotary member (29) supported on a main rotary shaft, and a first rod (24) having one end rotatably attached to the needle bar (19) and the other end rotatably attached onto a position which is eccentric from the rotary axis of the rotary member (29). A slider bar driving mechanism reciprocates a slider bar (20) fixing and supporting base end portions of the plurality of sliders (12) via a second rod (21) at a desired timing, and includes a rotary cam supported on the main rotary shaft, and the second rod (21) having one end with a cam follower and the other end rotatably attached to the slider bar (20).
Patent TW-448367-B (TW)
Title: File system method for using bitmap file to copy Windows network operation system
Inventor: CHEN SHIUAN-TUNG
IPC: G06F13/38
Filed: 1999-10-29
Granted: 2001-08-01
Abstract: This invention is a kind of file system method for using bitmap file to copy Windows network operation system. It stores the data of source file system partition as the type of data block into the bitmap file, and compresses the data block to an image file according to the bitmap file, and decompresses the compressed bitmap file of source file system partition in destination file system partition of the destination disk to the destination file system partition after the image file is copied to the destination disk. Then, it modifies the bitmap file to make it adapt to changes of sizes from the source file system partition to the destination file system partition according to physics parameter for the destination disk of the source file system partition. Therefore, there is no necessary to re-establish the MFT in the destination file system partition to ensure security and completeness of system and greatly increase file clone speed of high disks.
Patent TW-530456-B (TW)
Title: Starting circuit for integrated circuit device
Inventor: KOBAYASHI ISAMU
IPC: H03K17/22
Filed: 1999-11-24
Granted: 2003-05-01
Abstract: A starting circuit for an integrated circuit (IC) device insures that the IC device is properly initialized before an initialization signal is dropped. The starting circuit, which receives power from high and low potential power supplies, includes a first transistor having a threshold voltage within a known range. The first transistor receives a control voltage generated from the high and low potential power supplies and produces a start (initialization) signal, from the time that the high potential power supply voltage begins to rise to when the control voltage rises to the first transistor threshold voltage. A correction circuit connected to the first transistor adjusts the control voltage in accordance with the threshold voltage of the first transistor.
Patent TW-I234459-B (TW)
Title: Eplerenone compositions
Inventor: THOSAR SHILPA S
IPC: A61K47/42
Filed: 2000-02-22
Granted: 2005-06-21
Abstract: The invention relates to oral pharmaceutical compositions useful as aldosterone receptor blockers comprising the active agent eplerenone in an amount from about 10 mg to about 1000 mg and one or more carrier materials.