Patent GB-716781-A (GB)
Title: Improvements in or relating to calculating machines
IPC: G06F7/52
Filed: 1949-07-07
Abstract: 716,781. Digital electric calculating-apparatus. ELLIOTT, W. S., and LAWS, C. A. July 7, 1950 [July 7, 1949], No. 18028/49. Class 106 (1). [Also in Group XL(c)] In an electronic digital computor for multiplying two binary numbers represented by pulse trains, the multiplicand train on line 1, Fig. 1, delayed one digit period by each device D, is fed via lines 2-2<SP>15</SP> to gates D<SP>1</SP> each of which is opened by a pulse (i.e. a " 1 ") in one particular position of the multiplier train on line 3 and the gate outputs are combined by circuits A, A<SP>1</SP>, A<SP>2</SP>, A<SP>3</SP> to produce a pulse train on line 14 representing the product. As shown, the multiplier (assumed to comprise 16 digits) is fed to a commutator C which comprises series-connected one-digit-delay circuits the first of which is operated by a trigger pulse immediately preceding the first (or least significant) multiplier pulse, and each of which produces a delayed output pulse on line 4, 4<SP>1</SP> ...4<SP>15</SP> if the first, second ... sixteenth multiplier digit respectively is " 1 ". These delayed pulses switch over staticizers S, each comprising a control-grid-to-anode-connected trigger pair of valves, which then provide gate-opening output potentials on lines 5-5<SP>15</SP> until they are reset by the next trigger pulse. The pulse trains on lines 2-215 are delayed one digit period in gates D<SP>1</SP> and the trains combined in adding circuits A-A<SP>3</SP> are further delayed by devices D<SP>2</SP>-D<SP>5</SP> similar to D. Delay circuits and gates.-Fig. 4 shows one gate D<SP>1</SP> comprising a pentode 50 having the staticizer output, applied to its suppressor grid from line 51, controlling the passage of the pulse train from line 52 to line 53 and a delay circuit comprising a pentode 54 having differentiating inductances L<SP>4</SP>, L<SP>5</SP> in the control grid and anode (output) circuits respectively ; the delayed output pulses are gated and shaped by clock pulses from a generator (not shown) applied to rectifier G<SP>3</SP>. In the delay devices D and D<SP>2</SP>-D<SP>5</SP> the suppressor grid control of pentode 50 is omitted, and the delay circuits of the commutator C comprise only a pentode like 54 with its anode circuit. Adding circuits.-Each circuit A-A<SP>3</SP> comprises two " anti-coincidence " circuits A-C, Fig. 6, (i.e. two-input circuits which produce an output pulse when there is a pulse at one input and not the other), two coincidence or " and circuits C, and a one-digit delay (or " carry ") circuit. The pulse trains to be combined are supplied to lines 60, 61 connected to the two inputs of circuits A.C.1 and Cl, and the output 0<SP>1</SP> from A.C.1 and the carry output 04 are supplied to the two inputs of the circuits A.C.2 and C2. The combined output 03 from circuits C then represents the carry digit and is sent to the delay circuit, and the output 0<SP>2</SP> from circuit A.C.2 represents the sum of the numbers represented by the input trains and is sent over output line 62 (corresponding, e.g., to line 7, Fig. 1). Rounding off; contracted multiplication.-The least significant portions of the pulse trains on each of the first few lines 2-2<SP>15</SP> may be suppressed by supplying over-riding short-duration negative potentials, e.g. to the suppressor grids of pentodes 54, Fig. 4, of the corresponding gates D1. A correction for the probable error introduced by so contracting the multiplication, plus a rounding-off digit, may be added to the product on line 14 and the resultant sum may be passed through a gate which suppresses the least significant digits. To enable a single multiplication period to be reduced when successive contracted multiplications are carried out, each staticizer S is reset not by the trigger pulses but individually by that output pulse from the commutator C which occurs immediately after the highest significant digit pulse on line 2-2<SP>15</SP> has passed through the corresponding gate D<SP>1</SP>. The Provisional Specification describes the multiplication of more than two numbers.