Patent GB-1179613-A (GB)
Title: Data Transfer System
IPC: H04L5/00
Filed: 1967-11-29
Abstract: 1,179,613. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 29 Nov., 1967 [27 Dec., 1966], No. 54253/67. Heading G4C. In a data transfer system for linking a central processor and a plurality of independently operable storage units, each storage unit has an associated buffer store to hold control instructions and data, a storage unit initiating a seek operation when control instructions are transferred from the processor to its buffer store, the arrangement being such that control instructions may be transferred to the buffer stores for one or more storage units while the seek operation is being executed by one or more other storage units, "seek executed or not" indications in the storage units being scanned in a predetermined order, data transfer being initiated between the first storage unit sensed with the indication indicating seek executed and the associated buffer store. Fig. 5 shows a multiplexer linked to a CPU (central processor, with core memory) on the left and controlling a plurality of (multi-) disc stores 56 on the right. A core buffer 62 has a section for each disc store 56 to hold an instruction set, and data to be written in store 56 or which has been read from store 56. The sequence of operation is as follows. The multiplexer requests interrupt of the CPU (central processor). If this is granted, the multiplexer may present status to the CPU, consisting of the addresses of the multiplexer and a disc store 56 and a bit indicating "job complete" or "job incomplete due to problem". The CPU may now send a "start I/O" command together with the addresses of the multiplexer and a disc store 56. If the relevant section of buffer 62 is empty the command is accepted and the CPU sends an instruction set, and any associated data, to be stored in buffer 62. Otherwise the command is rejected. Instead of a "start I/O" command, the CPU may send a "present data" command specifying the multiplexer and a disc store 56, causing the data in the relevant section of buffer 62 to be sent to the CPU if the instruction set in that section indicates the data is. present (having -already been read from disc). The section is then erased. Otherwise the command is rejected. Another possible CPU command is "accept test" which specifies the multiplexer and a particular section of the buffer 62 and causes the instruction set therein and associated registers to be queried to determine the status of-the instructions (extent executed, any errors or problems) this information being sent to the CPU. After dealing with the CPU command, the multiplexer initiates a seek for a particular "cylinder" of a disc store 56, if this is required by an instruction set just accepted, then returns to readiness to accept another CPU command for a predetermined period. The multiplexer alternates between this latter state and the initiate seek state until one of the predetermined periods elapses without a CPU command being received, when the multiplexer determines whether any of the instructions in buffer 62 has been partially but not completely executed. If the answer is no, stored indications are tested in a predetermined order to see if a seek operation is complete, and if so the next instruction (in buffer 62) relating to that disc store 56 is executed. On the other hand, if the answer is yes (incomplete instruction) the next step of the instruction is executed. This may be the comparison of a tag against the next stored tag on a disc "cylinder" in an associative search. (The cylinder would have been previously located in a seek operation.) If the comparison is satisfied (e.g. equal to, greater than, greater than or equal to, less than, less than or equal to) the next instruction for the disc store is executed, e.g. read or write. After this, or in the case of comparison not satisfied, the multiplexer requests interrupt of the CPU as above. In Fig. 5, arithmetic/logic unit 36 performs the associative tag comparisons and can pass signals unchanged from A bus 35 or B bus 37 to D bus 40. Buffer 62 is addressed by the selfexplanatory circuits shown above it in Fig. 5 and delivers data to and receives data from data registers 64 two bytes in parallel. Data registers 64 can receive data a byte at a time from bus 63 and can deliver data a byte at a time to bus 75. Write data register 53 and read data register 60 (which are in fact the same register suitably gated) perform parallel-to-serial and serial-toparallel conversion respectively. File condition block 79 stores a bit indicating if any stores 56 have completed seeks, and bits (decoded from cylinder and store addresses supplied by control circuits 55 on seek completion) specifying which stores 56 have completed seeks. A read-only store 38 controls operations via decoder 39 and B bus 37 and is addressed as shown.