Patent GB-1111046-A (GB)
Title: Data processing system
IPC: G06F9/48
Filed: 1965-05-04
Abstract: 1,111,046. Data processing systems. GENERAL ELECTRIC CO. 4 May, 1965 [4 May, 1964], No. 18775/65. Heading G4A. In a system in which external units wishing to communicate with a data processing unit supply interrupt signals, command signals and address signals, provision is made for indirect addressing and for executing a command on each one of a sequence of operands whereby, for example, transfer of data between an external unit and memory may take place bit-by-bit, character-by-character or word-byword. As generally shown (Fig. 1), a data processing unit (D.P.U.) comprises a memory unit 18 for storing instruction words and data words, an arithmetic unit 20, four storage registers 23-25 and 28, an instruction counter 26, a command register 10 for issuing command signals to a control unit 30, a timer 29 and a control console 17. The D.P.U. also includes an interrupt control and priority allocation unit 33 together with command and data switching units 34, 32 whereby external units 12-15 may communicate with and control the operations of the D.P.U., the nature of said control being determined by command signals generated within the respective external units and transmitted to the D.P.U. upon an interrupt request being granted. The D.P.U. has provision for inhibiting interrupt requests during predetermined sequences of instructions. The Memory unit 18 (Fig. 5, not shown) comprises a magnetic core store having a capacity for 4096 words of 36-bits each. Operand words (Fig. 2) may comprise single 36-bit numbers or six 6-bit characters. Instruction words (INSTR, Fig. 2) normally comprise an 18-bit address portion (AD), a single interrupt inhibiting bit (I, for indicating sequences of instructions which are not to be interrupted by external requests), a 7-bit command portion (COMD), a 3-bit modifier portion (MOD, for indicating whether and in what way the address portion is to be modified before the instruction is executed) and a 6-bit tag portion (TAG, which may be used for address modification). Indirect words.-Three types of indirect words are also shown in Fig. 2 for use in cases where indirect addressing is called for by the MOD bits of a preceding instruction, each of these indirect words comprising an address portion as before, a 2-bit control portion for controlling the type of indirect cycle which is performed and respectively further comprising a 3-bit MOD portion, a TALLY portion or a TALLY with SUBTALLY portion for respectively controlling whether the next cycle is another indirect one or not, the number of words operated on in a repetitive operation and the number of digits or characters or words operated on in a repetitive operation. A. Internally controlled operation.-The D.P.U. operates in three types of cycles (i) Instruction cycle (ii) optional indirect cycle(s) (iii) Operation cycle. Each cycle comprises 30 clock periods and includes a read phase and a write phase. Direct addressing.-During the instruction cycle the instruction specified by the instruction counter is transferred from memory store 101 (Fig. 5, not shown) to memory register (102), the MOD bits are inspected, the AD bits are transferred to memory address register (103), the COMD bits are transferred to command register 10 and the TAG bits are transferred to TAG register 28. Depending on the nature of the MOD bits, in the succeeding operation cycle, the specified command is executed either on the operand located at the originally specified AD-address (MOD-N) or on the operand defined by the address bits after being incremented by the contents of one of the registers 23-25 or 28 (MOD-A, Q, X, or T respectively). The instruction counter 26 is incremented by passing the contents through the arithmetic unit 20. Indirect addressing (Mod-I).-Following an instruction cycle in which MOD-I bits are detected, an indirct word is transferred to memory register (102) from the address in store (101) specified by the instruction AD bits and one or more indirect cycles are performed followed by an operation cycle. This may be followed by alternating indirect and operation cycles. An operation cycle completes the internally controlled operation. There are four types of indirect cycles which may be specified by the CONT-bits of the indirect words. Type 1 (IMSCY), corresponding to control word IND/CH-CONT-A in Fig. 2.-The AD address bits of the indirect word are either unaltered (MOD N or I) or incremented by the contents of one of registers 23-25 or 28 (MOD-A, Q, T or X, as described above) and the next cycle is either an operation cycle (MOD-N, A, Q, T or X) or another indirect cycle (MOD-I). Type 2 (ITSCY), corresponding to control word IND/CH-CONT-B in Fig. 2.-The tally portion and address AD portion are both incremented. If there is no overflow from the tally portion to the E position, the AD-portion is transferred to the memory address register (103) and the next cycle is an operation cycle. If overflow occurs, the next cycle is an instruction cycle whereby a new instruction is obtained from the next storage location to the indirect word last accessed, which new instruction may return the modified indirect word to its initial state in preparation for further execution thereof (e.g. in programmes involving loops). The above operation (ITSCY) enables a command to be executed repetitively on each one of a sequence of operand words. Type 3 (ISSCY), corresponding to control word IND/CH-CONT-C.-This is similar to the previous type except that a tally and a subtally are provided whereby a command may be executed in turn on each bit position (controlled by sub-tally) of each of a sequence of words (controlled by tally). After overflow has occurred from sub-tally to tally (indicating that all 36-bits of a word have been operated on) the sub-tally has an additional quantity (28) added so that overflow will again occur at the end of a word. Type 4 (IFSCY).-This is identical to the previous type except that instead of a single bit being operated on each cycle, each cycle deals with one character (6 bits) and 58 is added in place of the 28. B. Externally controlled operation.-Each external unit may supply an interrupt signal, Address signals, command signals. and data signals (if data is to be supplied therefrom) as illustrated in Fig. 18 (not shown). Explicit operations.-When either the load or store command only is specified, then, after an interrupt request has been granted, a data word is transferred between the external unit and the memory address specified (i.e. single operation cycle) and control is then returned to the D.P.U. If, in addition to either of these commands a shift 1 or shift 6 command is specified, then data transfer takes place bit-by-bit or character-by-character in a number of cycles until a complete word has been transferred (the address for transfer remaining constant but the content of the memory word affected being shifted cyclically at each stage). If indirect addressing is called for (DIR/IND command and both shift signals equal 0) then one or more indirect cycles are executed (in the manner previously described) together with operation cycles as necessary whereby a sequence of words may be operated on in sequence. Implicit operations.-If both the load and store external command signals are absent, the externally supplied address signals are used to access an internal instruction from the memory store (101). The first cycle is thus an instruction cycle after which control is passed to the D.P.U. and operations proceed as for "internally controlled operations.',' The interrupt control and priority allocation unit 33 may comprise a control unit (Fig. 19) corresponding to each external unit and a priority chain (Fig. 21) of AND and OR gates. Interrupt pulses are received by (and set) the corresponding flip-flop 520 thereby generating an IS A-N  signal. On occurrence of a timing pulse TSI indicating that the D.P.U. is available for further communication, a flip-flop 521 is set whereby the corresponding signal IA A-N  is generated. These IS and IA signals are applied to AND-gates 535 of the priority allocation chain together with output signals from higher priority AND-gates combined in OR- gates 541. A single IAN A-N  signal is generated corresponding to the highest priority unit A-N requesting interruption. This signal apart from controlling the gating of switches 32 and 34 (Figs. 23 and 24, not shown) resets the FF 520 and as a result also the FF. 521. External units may comprise magnetic tapes or discs, punched card readers/punches, electric typewriters, printers, radio guidance systems or other data processing units.