Patent GB-1302059-A (GB)
IPC: H01L29/78
Filed: 1970-09-29
Abstract: 1302059 Semi-conductors GENERAL ELECTRIC CO 29 Sept 1970 [3 Oct 1969] 46357/70 Heading H1K A short channel FET is fabricated from a Si wafer 10 heat formed in O 2  to produce a film 11 of SiO 2  thereon, subsequently annealed in He. The film is selectively etched by e.g. buffered HF to form a pattern revealing the substrate, and the wafer is reoxidised to form a thinner gate oxide layer 13 within the patterned region. Thereafter the wafer is sputtered with conductive film 14 of refractory metal e.g. Mo, W or alternatively Si (Fig. 2e). A pattern is formed in the film by etching over photoresist using e.g. orthophospheric, nitric and acetic acids to leave e.g. a portion 15 of the film with an edge 15a overlying the oxide film 13 (Fig. 2f). Thereafter a donor doped insulant 16 is deposited over the conductive film, e.g. P doped SiO 2  glass, by pyrolysis of ethyl orthsilicate and methyl phosphate vapours in argon carrier gas. Other dopants e.g. As, Sb, Bi are usable. Thereafter B doped SiO 2  layer 17 (Fig. 2h) is deposited by pyrolysis of ethyl orthosilicate and triethyl borate vapours in argon carrier gas, and is patterned by selective masking and etching over photoresist to produce a patterned region 18 (Fig. 2i). The wafer is heated to drive the P dopant through the film into the substrate to form N-type region 19 extending under gate edge 15a, and the B dopant through the film to form P type region 20 within region 19, so as to form a short N-type channel 21 under edge 15a in registry with the gate electrode 15, interposed between regions 19, 20 (Fig. 5, not shown). The wafer is masked by etch-photoresist methods and contact apertures are etched by buffered HF into the gate, drain and substrate at 22, 23, 24 (Fig. 2k) after which the wafer is vacuum metallised e.g. with Al, which is photoresist and etch patterned using orthophosphoric, acetic, and nitric acids to leave contacts 25, 26, 27 thermocompressively bonded to conductors, or connected by surface films to other regions. The substrate source may be alloyed to a gold plated header. Alternatively gate oxide layer 13 is removed from all regions not covered by electrode 15, and the channel is defined by edge 13a of the oxide layer, and a donor dopant e.g. P is vacuum-heat diffused into the substrate to form N-type region 19 underlying edge 13a (Fig. 4h). An acceptor dopant insulating film of e.g. B doped SiO 2  18 is pyrolytically deposited from ethyl orthosilicate and triethyl borate vapours in argon carrier, patterned by selective photoresist masking, and etching (Fig. 4j) and an insulant layer is formed over the wafer. Thereafter heat diffusion of the boron into 19 forms a P type region 20 therein (Fig. 4k) extending under edge 13a to leave a N-type channel region. Holes are etched over photoresist to the drain, gate substrate, and source and a metallised pattern forms contacts 25, 26, 27, 28 thermocompression bonded to conductors or film connected to other entities (Fig. 4l). Thus in FET's (Figs. 6, 7, not shown) a short channel is provided with the source channel and drain channel boundaries defined by the edge of the gate electrode or of its insulant film, and the gate electrode may be U-shaped with the edge along its periphery. Plural devices may be fabricated on a single wafer, which is cloven into dies, or may be interconnected to form integrated circuits. A load resistor may be fabricated (Fig. 8, not shown) by extending the acceptor doped insulant film to form a convoluted resistance element. Alternatively an elongated slot is etched into the substrate, and first and second diffusion regions similar to those of the substrate and drain are formed therein to constitute a resistance interconnectible with other circuit elements. Amplifier circuits comprising single or plural FET's may be fabricated (Figs. 9, 10, not shown). The substrate may comprise an epitaxial layer with the FET's formed therein, which may be N-type formed on P-type with portions or islands iolated by diffusing in a P-type layer. The defining edge may have various profiles, and the substrate may be Ge or GaAs. A production method is quoted.