Patent GB-838411-A (GB)
Title: Improvements in or relating to electronic computing apparatus
Inventor: KNIGHT LORIN
IPC: H03K21/00
Filed: 1956-02-23
Abstract: 838,411. Sequence control apparatus for computors. INTERNATIONAL COMPUTERS & TABULATORS Ltd. Jan. 9, 1957 [Feb. 23, 1956], No. 5629/56. Class 106 (1). A control circuit adapted to allow an electronic calculator to be operated at a reduced speed, e.g. for testing, but without varying the wave shape of the control pulses applied includes a master clock pulse source generating a first train of pulses, counting means operated by this pulse train and producing an output after each predetermined number of pulses, a second source of signals, gating means controlled jointly by the first pulse train, the signals and the output from the counter to select certain of the pulses from the first pulse train to form a second pulse train of reduced frequency. The master clock pulses are provided by a track on a magnetic drum store D, Fig. 1, read by a head 31. There are 273 pulses per revolution, i.e. 21 groups of 13. After amplification the pulses are applied via a gate 8 to a primary timer PT which produces the control pulses for controlling the operation of the machine. In normal operation the gate 8 is open so that the complete pulse train is applied to the timer but for the purposes of testing &c. this pulse train is reduced by the selection of some only of the pulses as follows:- Step-by-step operation.-The second source of signals is, in this case, manually operated. Gate 8 is open when trigger 7 is set, and when step-by-step operation is required, this trigger is controlled, by the manually-operated pulse source 1. For this purpose, switch 34 is closed to open gate 11 so that the first clock pulse from gate 8 passes to the unsetting input of trigger 7 to unset it and cut off the following pulses. Switch 33 is closed to open gate 2 so that a pulse from source 1 sets a trigger 3 controlling gate 4. The first clock pulse passing through gate 4 unsets trigger 3 to close the gate so that following pulses are cut off. But in unsetting, trigger 3 sets trigger 5 to open gate 6. Trigger 7 also controls gate 9, the gate being open when the trigger is unset to permit clock pulses to pass the counter 10. The next output from the counter passes through gate 6 to set trigger 7 causing the gate 9 to close and gate 8 to open so that the next clock pulse passes to the timer PT and to gate 11 which unsets trigger 7, thereby closing gate 8 and opening gate 9 ready for the next cycle. By this means only one clock pulse is admitted to the timer for each pulse from source 1. Slow-speed operation.-In this case the second source of signals is a variable-frequency multivibrator 14. For slow-speed operation for a predetermined time, e.g. for one word cycle (13 pulses) switches 33, 34 and 37 are closed. Switch 37 opens gate 13 to allow pulses from multivibrator 14 to pass via gate 15 (held open by unset output of trigger 12) to the setting input of trigger 3. The first pulse through gate 15 initiates the above-described sequence so that one clock pulse is passed to the timer PT. When trigger 5 unsets, the cycle is initiated again by the next pulse from gate 15, so that the timer receives pulses at a slow speed, the frequency of the multivibrator being manually variable. Switch 38 is closed to terminate the operation, gate 16 then being open to pass the thirteenth pulse from the timer PT to set trigger 12 and close gate 15 so that no more setting pulses can pass to trigger 3. The initiation of subsequent cycles is controlled by the manual pulse source 1. In the slow-speed operation the output from the counter occurs at the 273rd pulse entered into it by gate 9 but since this gate is closed for one pulse time by trigger 9 the cycle corresponds to 274 pulses, i.e. one revolution plus one clock pulse. This allows successive digits of a word to be read off a drum track by reading-head 39 and passed at slow speed to arithmetic unit AU. Normal running can be interrupted for a predetermined number of programme steps. To run at slow speed for one step the gates 13, 11 and 2 are opened as previously described. At the end of a programme step an " operation complete " signal is fed from the arithmetic unit via gate 17 (opened by switch 41) to set trigger 12 and close gate 15. To run at slow speed, e.g. for ten programme steps, a gate 18 is opened (by switch 42) to cause the "operation complete" signals to pass to trigger 12 under the control of a gate 19 which is opened by a pulse on one of the lines PS10, PS20 ... PS120, which receive pulses at the tenth, twentieth ... and one-hundred-and-twentieth programme steps respectively. Normal speed operation.-Normal operation is resumed by setting trigger 7 to admit the clock pulses through gate 8 to the primary timer. Trigger 7 is set by closing gates 11 and 13 and applying a single manual pulse to trigger 3. The next output pulse from counter 10 then passes through gate 6 to set trigger 7 and unset trigger 12. Counters.-The counter 10 comprises ten trigger stages 46, Fig. 2, in two groups of five, each group acting as a binary counter. The numbers indicate the total value represented by each trigger when set. Initially all triggers are unset and the first pulse through gate 9 passes through gates 47, 48 in series, these gates being controlled by the tenth and fifth stages respectively. The first pulse sets the first trigger and subsequent pulses set other triggers in the normal manner of operation of a binary counter. The sixteenth pulse sets the fifth stage which closes gate 48 and opens gate 49 so that the next input pulse sets the sixth stage and unsets the fifth stage thereby opening gate 48 and closing gate 49. The next sixteen pulses are therefore entered as the first, the 34th pulse being passed to the sixth stage to unset it and set the seventh. The process continues until the 272nd pulse sets the last stage which closes gate 47 and opens gate 50 so that the next pulse (the 273rd) is applied to the unsetting input of the last stage which is accordingly unset. In unsetting it passes a pulse to gate 6. All the triggers are now unset and gates 47 are therefore open ready to begin the next counting cycle. The primary timer PT consists of a ring of thirteen triggers arranged so that only one trigger is set at any given time. The input pulses step the set condition round the ring so that each trigger in turn gives a set output. Specification 780,596 is referred to.