Patent GB-968546-A (GB)
Title: Electronic data processing apparatus
IPC: G06F9/308
Filed: 1961-03-14
Abstract: 968, 546. Digital computers. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 14, 1961 [March 24, 1960], No. 9230/61. Heading G4A. In an arithmetic operation the operands are set up in two registers, an auxiliary register 113 and an arithmetic register 108, and all the significant digits held in the auxiliary register and a selected field of the arithmetic register are gated serially to the mill, as shown an adder 115. The field is specified by two digits (4 and 5) of the instruction word which denote, respectively, the highest and least significant order of the field. The single address instruction denotes the location of the operand from which a variable length field may be taken, this location being either in memory 101 or an accumulator 109 to 111. The other operand is found in one of the three accumulators 109 to 111 as specified by the operation portion of instruction and is transferred to the auxiliary register 113.  Operation: add to accumulator. The data word in the accumulator (109, say) specified by the operation portion of the instruction is transferred to the arithmetic bus 112 (capacitor stores), when the position of the highest significant digit is determined by scanner 114 (described in Specifications 890,953 and 968,545) and from the bus to auxiliary register 113. The other operand is taken in this operation from an accumulator and is transferred via the arithmetic bus to arithmetic register 108. The numbers denoting the highest and least significant orders of the field are taken from program register and added, the highest order being complemented in circuit 116. The sum, which represents the 10's complement of the number of digit in the field, is sent to field size register 117. A carry out of the adder at this stage indicates an error and the operation is stopped. Next, a mark indicating the order of the highest significant digit in the auxiliary register, as determined by scanner 114, is entered by the scanner in the corresponding order of shift register 118. The two operands are shifted out from the registers 113 and 108 to the adder under the respective control of a program ring (not shown) and a field ring (not shown), the latter beginning at the least significant order of the field as specified by position 4 of the program register and stopping when its setting corresponds with the setting of position 5 of the program register. Position 9 of the auxiliary register is read out first and the program ring enters the sum in arithmetic register 108 starting at position. 9. Simultaneously with the shifting of the auxiliary register the mark in register 118 is shifted (this is described in Specification 890,953) and its transfer from position 9 of register 118 stops the program ring. At the beginning of the add operations latches 119, one for each position of the arithmetic register, are set. The latches are subsequently reset as a sum digit enters the arithmetic register, and at the end of the operation the remaining set latches enter zeros into the positions of the arithmetic register to which they correspond. A check is now made by scanner 114 that no significant digits remain in register 113 and the contents of register 108 sent through circuit 116 for complementing if necessary. The arithmetic register is then transferred to the accumulator (109 in this case) from which the operand held in the auxiliary register was taken. Either of the registers 108 113 may hold the minuend or augend of an operation, this always being read to the channel 1 input to the computer. The other operand is read to the channel 2 input containing the complementing circuit 116. The add to memory operation differs from the above in that the contents of a selected accumulator are added to a field of a selected memory word. Only the digits of the field are affected by the operation and the new data word is returned to memory.