baber/WOPTO huggingface dataset:
Patent TW-200508021-A (TW)
Title: Micro lens and making method thereof, optical device, optical transmitting device and head for laser printer
Inventor: HASEI HIRONORI
IPC: B29C35/08
Filed: 2004-08-04
Abstract: A method of manufacturing a micro lens that can enhance the accuracy of landing positions of droplets and can fabricate a micro lens with good shape accuracy, a micro lens, an optical device, an optical transmitting device, a head for laser printer, and a laser printer are provided. In a method of manufacturing a micro lens 8a, a given number of droplets of a lens material 7 are ejected from a droplet ejection head 34 on a base member 4b formed on a substrate 3. The method includes stopping relative movement between the substrate 3 and the droplet ejection head 34; and ejecting a plurality of the droplets on a given position on the substrate 3 from the droplet ejection head 34.
Patent TW-200605928-A (TW)
Title: Portable high frequency ventilation
Inventor: KUO HSU-TAH
IPC: A61H31/00
Filed: 2004-08-10
Abstract: This invention relates to a portable high frequency ventilation (HFV), which comprises a air compressing pump and a power supply unit for driving the air compressing pump, and a control unit for controlling and adjusting the air compressing pump. The air compressing pump is a high frequency air compressing pump, with an operating frequency in the range of 100 to 4,000 per minute. The invention of portable high frequency ventilation increases respiratory capacity of a patient with thoracic cavity disease, and prevents the daily life of the patient from being interfered with oxygen deficiency in his arterial blood.
Patent TW-200521237-A (TW)
Title: Methods of degrading dsRNA and synthesizing RNA
Inventor: SAGAWA HIROAKI
IPC: C12P19/34
Filed: 2004-08-13
Abstract: This invention relates to a protein having an activity of degrading a dsRNA, namely, being capable of acting on a long-chain dsRNA to form a dsRNA of a definite length; a method of efficiently preparing a dsRNA of a definite length which comprises treating a dsRNA with the protein having an activity of degrading a dsRNA in the coexistence of a protein having an activity of binding to a nucleic acid such as a protein having an RNA-binding activity; and a method of using the protein having an activity of binding to a nucleic acid to elevate the efficiency in an RNA synthesis reaction typified by dsRNA synthesis.
Patent TW-200609535-A (TW)
Title: 3D display method and device thereof
Inventor: LIN LIN
IPC: G02B27/22
Filed: 2004-09-08
Abstract: A 3D display method and device thereof mainly have two sets of optical gates disposed on a display in a complementary and alternate arrangement, which are controlled to switch on or off by virtue of a time-domain concept so as to activate one of the optical gates while the display frequency is at an odd frequency and activate the other optical gate while the display frequency is at an even frequency. Two sets of optical gates are continuously switched on and off according to frequency variation such that left eye and right eye see independent images composed of different sub-pixels at odd and even frequencies. Therefore, 3D display effect is presented to vision of naked eyes while resolution is not reduced.
Patent TW-200610863-A (TW)
Title: Infixed fence structure
Inventor: CHOI YING-KIT
Filed: 2004-09-20
Abstract: An infixed fence structure, including: plural main beams; drive-fit blocks constructed of drive-fit inner blocks and drive-fit tubes engaged each other; drive-fit positioning beams; and main columns having plural insertion holes and constructed of male columns and female columns engaged each other. The main beams, drive-fit inner blocks, drive-fit tubes and drive-fit stationary beams are structural bodies having hollow, rectangular engagement holes and stamped from extruded materials. The inner walls of the engagement holes are provided at appropriate locations of inner sides of opposing ends of the top and bottom edges, and each provided with a fit channel flange. Gaps between the fit channel flanges and outer walls of the beams thereof serve to form fit channels. Plural engagement flanges that are flush with the fit channel flanges are provided to the lower edges of the inner walls and between the fit channel flanges at opposing sides. By adopting such structure, the parts can be fit to each other and have the tight connection effect resulted from inner expansion. During assembly, the main beams are inserted in the insertion holes of the main columns. An appropriate number of insertions are reserved for infixing the drive-fit blocks and drive-fit retaining beams. The inner expansion effect resulted by fitting the drive-fit blocks into the drive-fit retaining beams help to construct a solid and suitable grid fence.
Patent TW-200513819-A (TW)
Title: Cascadable current-mode regulator
Inventor: HARRIS MATTHEW B
IPC: H02J1/10
Filed: 2004-09-22
Abstract: A cascadable power regulator including a programmable delay unit and PWM control logic. The programmable delay unit initiates a delay period in response to a digital input signal and asserts a digital output signal upon expiration of the delay period. The PWM control logic controls a PWM cycle in response to the digital input signal and in response to an output control condition. The cascadable regulator uses digital signals to communicate between channels. Digital signals are not prone to the same kind of signal degradation or noise susceptibility as analog signals. Thus, the number of phases is not limited, the physical separation between the regulators is not limited, and the switching frequency is not as limited. There is no clock signal from a separate controller so that the controller is a relatively simple, low-cost device. Since there is no clock, a unique self-oscillating system is achieved using the cascadable regulator.
Patent TW-200514471-A (TW)
Title: Organic electroluminescent device
Inventor: YOSHITAKE OSAMU
IPC: H01L51/00
Filed: 2004-09-22
Abstract: The object of the invention is to provide an organic electroluminescent device (organic EL device) utilizing phosphorescence which has excellent luminous efficiency that enables high luminance at low current density and high driving stability, and which is applicable to display devices such as a flat panel display or illuminating devices. The organic electroluminescent device comprises an anode, an organic layer and a cathode formed in layers on a substrate, wherein at least one layer in the organic layer is a light-emitting layer containing a host material and a dopant material, and a pyrazole compound having 2-4 pyrazole structures represented by the formula (I) below in a same molecule is used as the host material in the light-emitting layer. In the formula, Ar1-Ar3 independently represent a hydrogen or an aromatic hydrocarbon group which may have a substituent, and at least one of them is a group other than hydrogen.
Patent TW-200612576-A (TW)
Title: Light-emitting diode backlighting module and method for manufacturing the same
Inventor: CHEN SHI-MING
IPC: H01L33/00
Filed: 2004-10-12
Abstract: A light-emitting diode (LED) backlighting module and a method for manufacturing the same are described. The light-emitting diode backlighting module comprises a print circuit board (PCB), a plurality of light-emitting diode chips and a plurality of solder films. A plurality of conducting lines are located on a surface of the print circuit board, and the print circuit board comprises a plurality of openings. The light-emitting diode chips are disposed respectively in the openings. Each light-emitting diode chip comprises: a metal substrate; three light-emitting diode dies respectively located on a surface of the metal substrate; and a plurality of electrodes respectively located on the rim of the metal substrate, wherein two poles of each light-emitting diode die are electrically connected to the electrodes respectively. The solder films electrically connect the conducting lines of the print circuit board and the electrodes of each light-emitting diode chip.
Patent TW-200520202-A (TW)
Title: Semiconductor device with capacitor and fuse and its manufacture method
Inventor: OMURA MASAYOSHI
IPC: H01L27/06
Filed: 2004-10-22
Abstract: An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost.
Patent TW-200519006-A (TW)
Title: Substrate carrier
Inventor: BURNS JOHN
Filed: 2004-10-26
Abstract: A carrier for transporting silicon semiconductor wafers during semiconductor wafer processing operations including an enclosure, a door and a flange structured to interface with a machine so that the carrier can be lifted by the machine. A lift saddle connects the flange to the container so that the load on the flange is transferred to a part of the enclosure other than the top of the enclosure to prevent distortion of the enclosure to maintaining seal integrity between the enclosure and the door.
Patent TW-200531553-A (TW)
Title: Video-encoding and video-encoding control method
Inventor: ARIDOME KENICHIRO
IPC: H04N21/44
Filed: 2004-10-29
Abstract: A video-encoding device that can achieve seamless connection without causing an error in a VBV buffer is provided. Recording-mode determination means for determining an initial value of the occupied amount of a virtual buffer based on a determination result relating to seamless connection between a preceding chapter and the following chapter that are included in video signals, occupied-amount update means for updating the occupied amount of the virtual buffer, optimum-occupied-amount calculation means for calculating a predetermined optimum occupied amount based on the updated occupied amount of the virtual buffer, target-code-amount calculation means for calculating a predetermined target-code amount based on the video signals of the following chapter, target-code-amount adjustment means for adjusting the target code amount so that the sum total of the occupied amount of the virtual buffer and the target code amount does not exceed the optimum occupied amount, and encoding means for performing the encoding according to the adjusted target code amount are provided.
Patent TW-200529559-A (TW)
Title: Internal voltage reference for memory interface
Inventor: ZUMKEHR JOHN
IPC: G11C5/14
Filed: 2004-11-11
Abstract: Embodiments of the invention include a memory controller to interface to memory. In one embodiment, the memory controller includes a pull-up calibration terminal to couple to an external pull-up resistor, a pull-down calibration terminal to couple to an external pull-down resistor, a voltage reference node, a first switch coupled between the pull-up calibration terminal and the voltage reference node, and a second switch coupled between the pull-down calibration terminal and the voltage reference node. The first switch and the second switch may be selectively closed to generate an internal voltage reference on the voltage reference node in a normal mode that may be used for comparison with an input signal to receive data.
Patent TW-200526494-A (TW)
Title: Substrate treatment device control method and substrate treatment device
Inventor: SHINOZUKA SHINICHI
IPC: G03F7/16
Filed: 2004-11-29
Abstract: A coating/development device having an inspection section can reduce the startup time reduce the cost, and improve the operation rate of the inspection section. In the coating/development device control program, a treatment flow and an inspection flow are set so as to be executed independently. In the flow, a substrate is carried from a cassette station to a treatment station to be processed by the treatment station and the exposure device, after which the substrate is returned to the cassette station. In the inspection flow, the substrate is carried from the cassette station to the inspection station to be inspected, after which the substrate is returned to the cassette station. When starting the coating/development device, the inspection flow and the treatment flow are executed and an evaluation work of an inspection unit of the inspection station and an adjustment work of a treatment unit of the treatment station can proceed simultaneously. When the inspection station is idle, the substrate can be carried from outside into the cassette station to be inspected there.
Patent TW-200522415-A (TW)
Title: Pcm mold and battery having the same
Inventor: MOON KI-EOB
IPC: H01M10/42
Filed: 2004-12-06
Abstract: The present invention provides a protection circuit module (PCM) insert injection mold, and a battery having the same. The PCM insert injection mold is made by inserting a PCM, including a plate having protection circuit formed thereon and connection terminals and optionally leads, with the protection circuit plate, connection terminals and leads being electrically connected, into an inner space of a mold, and injecting a molten resin into the inner space of the mold such that the leads are partially exposed to the outside where the PCM includes the leads, or such that the connection terminals are partially exposed to the outside where the PCM does not include the leads. Since the PCM is prepared by insert injection molding under the condition that the protection circuit and battery cell are not connected, i.e., that power is not applied to a battery, the PCM can be molded using general resins, is electrically stable, does not require a coating step for preventing short circuit, and is rare electrically damaged.
Patent TW-200601486-A (TW)
Title: Method for forming device isolation film of semiconductor device
Inventor: CHOI HYUNG-SUK
IPC: H01L21/76
Filed: 2004-12-07
Abstract: A method for forming device isolation film of semiconductor device is provided, the method including sequentially forming a pad oxide layer and a pad nitride layer on a semiconductor substrate having a cell region and a peripheral circuit region, etching a predetermined region of the pad nitride layer, the pad oxide layer, and the semiconductor substrate to form a trench, forming an sidewall oxide film on a surface of the trench, etching a predetermined thickness of the sidewall oxide film in the cell region, forming a liner nitride film and a liner oxide film on the semiconductor substrate including the trench and the pad nitride layer, depositing a HDP oxide film to fill up the trench, performing a planarization process to expose the pad nitride layer, and removing the pad nitride layer.
Patent TW-200529804-A (TW)
Title: HIV protease inhibiting compound
Inventor: RANDOLPH JOHN T
Filed: 2004-12-10
Abstract: A compound of the formula, is disclosed as an HIV protease inhibitor. Methods and compositions for inhibiting an HIV infection are also disclosed.
Patent TW-200618914-A (TW)
Title: Laser dicing apparatus for a silicon wafer and dicing method thereof
Inventor: HSU CHIH-MING
IPC: H01L21/304
Filed: 2004-12-14
Abstract: The present invention discloses a laser dicing apparatus for a silicon wafer and a dicing method thereof, wherein firstly, a silicon wafer, which has multiple chips with a scribed line drawn between every two chips, is provided; next, the silicon wafer is disposed on a working table having a vacuum device and fixed by the vacuum device; next, the working table and a laser are positioned by a control device; next, the laser is directed by a light-guide device to focus at one of the scribed lines; and lastly, the scribed lines on the silicon wafer are sequentially cut by the laser in order to dice the silicon wafer into multiple separate chips. The present invention can reduce the cutting harm on chips, lower the cost, accelerate the fabrication and improve environmental problems.
Patent TW-200523688-A (TW)
Title: Exposure apparatus and method
Inventor: TOKITA TOSHINOBU
IPC: H01L21/027
Filed: 2004-12-22
Abstract: An exposure method includes the steps of introducing fluid between a surface of an object to be exposed, and a final surface of a projection optical system, displacing an interface of the fluid arranged between the surface of the object and the final surface of the projection optical system, and projecting a pattern on a mask onto the object via the projection optical system and the fluid.
Patent TW-200623565-A (TW)
Title: Automatic assembly machine for jumper
Inventor: TSAI CHIH-WEI
IPC: H01R43/00
Filed: 2004-12-22
Abstract: This invention relates to an automatic assembly machine for jumpers. The automatic assembly machine includes a jumper connector feeder device, a pin header feeder device, a first clamping device, and a second clamping device. The jumper connector feeder device is provided for transporting a plurality of jumper connectors orderly to a first assembly position. The pin header feeder device is provided for transporting a plurality of pin headers orderly to a second assembly position and each pin header has an array of pins. The first clamping device is provided for clamping one of the jumper connectors posited at the first assembly position to the top of the second assembly position and installing the jumper connector in any one of pins of one pin header to the other neighboring pin of the pin header. Furthermore, the second clamping device is provided for pressing the jumper connector so that the pins of the pin header are securely installed in the jumper connector and then clamping the assembled jumper connector and pin header to a gathering unit.
Patent TW-200534055-A (TW)
Title: Lithographic apparatus, method of exposing a substrate, method of measurement, device manufacturing method, and device manufactured thereby
Inventor: MODDERMAN THEODORUS MARINUS
IPC: G03F9/00
Filed: 2004-12-22
Abstract: A method of exposing a substrate (e.g. in a lithographic apparatus comprising a substrate table to support a substrate) according to one embodiment of the invention includes performing first and a second height measurement of a part of at least one substrate with a first and second sensor, generating and storing an offset error map based on a difference between the measurements; generating and storing a height map of portions of the substrate (or another substrate that has had a similar processing as the part) by performing height measurements with the first sensor and correcting this height map by means of the offset error map; and exposing the substrate (or the other substrate).
Patent TW-200529930-A (TW)
Title: Nozzle device and nozzle member
Inventor: TANIGAKI AKIHIKO
IPC: B05B7/04
Filed: 2005-01-12
Abstract: The present inventioin provides a nozzle device with a nozzle member thereof being replaceable with respect to plural headers without welding, and the weight thereof can be reduced. The nozzle device comprises of plural headers (1), (2), which are long and cylindrical, for supplying plural fluids respectively, a fitting port formed at substantially equal interval in the longitudinal direction of headers and penetrating in the direction perpendicular to the longitudinal direction of the headers, a nozzle body (5) replaceably fitted to the fitting port and having flow paths (or connection holes) (9)-(12) in connection with the headers, a nozzle tip (4) fixed to the nozzle body, seal members (13)-(15) respectively placed onto the joint portions (flat portions) of headers (1), (2) and nozzle body (5), and a conjoining means (16) thread-engageable to the thread portion (8) of the end of nozzle body (5). Within the nozzle body, a space for mixing the fluids coming from each of the headers may be provided.
Patent TW-200605075-A (TW)
Title: Memory device
Inventor: TSUSHIMA TOMOHITO
IPC: G11C11/56
Filed: 2005-01-20
Abstract: A memory device is provided in which recording of multi-valued data can be performed at a high speed and the recording of multi-valued data can be performed with a drive circuit having comparatively simple configuration. The memory device is formed of a memory cell including a memory element which stores information according to a state of electric resistance and an MIS transistor as a load connected in series to the memory element. When an operation to change the memory cell from a state of high resistance value to a state of low resistance value is defined as writing and when an operation to change the memory cell from the state of low resistance value to the state of high resistance value is defined as erasing respectively, a resistance value of the memory element after writing is set to a plurality of different levels by controlling gate voltages VG1, VG2 and VG3, which are applied to the MIS transistor at the time of writing, so that different information is respectively assigned to each of the plurality of levels and to the state of high resistance value after erasing to store information of three values or more respectively into a memory element of each memory cell.
Patent TW-200631251-A (TW)
Title: Gain device for connector
Inventor: Zheng yi-hong
IPC: G06F13/42
Filed: 2005-02-22
Abstract: Disclosed is a gain device for connectors. The invention is able to provide a selective plug-in for the plugging terminal of connector that is equipped with different transmission interfaces, in addition, it is capable of supporting the efficiency of the gain structure of the connector base terminal in a synchronized manner for the connector having the different transmission interfaces.
Patent TW-200535471-A (TW)
Title: IPS mode liquid crystal display
Inventor: YANO SHUUJI
IPC: G02F1/133
Filed: 2005-03-10
Abstract: Disclosed is the IPS mode liquid crystal display device constituted by arranging, on one side of a liquid crystal cell, an optical film (F1) which uses a polarizing plate having a ≤ 10 nm in-plane phase difference Re and a 30 to 100 nm thickness-directional phase difference Rth of a transparent protection film and a phase difference film having a 0.3 to 0.7 Nz value and a 200 to 300 nm in-plane phase difference Re1 and on the other side, an optical film (F2) which uses a similar polarizing plate and a phase difference film having a 0.9 to 1.2 Nz value and a 150 to 280 nm in-plane phase difference Re2, the optical film (F1) and optical film (F2) being arranged so that axes of absorption of their polarizing plates are orthogonal and their phase difference films are on liquid crystal cell sides.
Patent TW-200603319-A (TW)
Title: Semiconductor wafer and manufacturing method therefor
Inventor: NAITO HIROSHI
IPC: H01L23/12
Filed: 2005-03-24
Abstract: A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height difference between ICs and scribing lines, a planar insulating layer is formed to cover the overall surface with respect to ICs, seal rings, and scribing lines. In order avoid occurrence of breaks and failures in ICs, openings are formed to partially etch insulating layers in a step-like manner so that walls thereof are each slanted by prescribed angles ranging from 20 DEG to 80 DEG. For example, a first opening is formed with respect to a thin-film element section, and a second opening is formed with respect to an external-terminal connection contact point.