Patent GB-1498819-A (GB)
Title: System for transmitting a series of bits
IPC: H04L7/04
Filed: 1974-12-18
Abstract: 1498819 Data transmission DE STAAT DER NEDERLANDEN TE DEZEN VERTEGENWOORDIGD DOOR DE DIRECTEUR-GENERAAL DER POSTERIJEN TELEGRAFIE EN TELEFONIE 18 Dec 1974 [21 Dec 1973] 54691/74 Headings H4P and H4M In a system in which a series of bits of undefined length is transmitted between first and second stations in balanced data blocks, five bit groups of bits are converted into a series of six bit words, two additional bits being added to the plurality of six bit words forming the series in such a way as to form a balanced data block. Upon detection at the first station of a loss of phase in signals received from the second station, restoration of synchronization is requested by the first station by the transmission, in place of a data block, of a framing block which has the same size as a balanced data block and comprises a six bit word in a predetermined series of bit positions within the block. The system is used for the transmission of multiplex signals, a number of multiplex channels being included in each data block. In particular data blocks contain five six bit words and two extra bits. The 32 bit framing block is made up from two bits, of opposite sign, in positions 1 and 8, a recognizable 6 bit word in bit positions 2-7, the channel number of the first multiplex word which would have been contained by a data block in the same position in the odd bit positions 9-31 and the inverted form of this channel number in the even bit positions 10-32. The output from a peripheral 1 producing 8 bit data words at 2400 baud is converted in data terminal equipment 2 into 10 bit words by adding state and synchronizing bits within the same envelope (i.e. bit rate 3000 baud). Thereafter the words pass via a data circuit equipment 3 which synchronizes them with others to a multiplexer 4. Further multiplexers 5 and 6 are provided such that at the output of 6 an aggregate 100 channel signal at 300 k baud is produced, the channels of any bit being indicated at 8. The multiplexed signals are applied to a converter 30, which multiplex words are converted into 32 bit blocks, and eventually transmitted (via switch 18 in the position shown) at 32 k baud via a line to a distant receiver. A received signal is detected by receiver 17. If the receiver detects a non allowable configuration in the first 8 bits and requests reframing or if loss of phase in the received signal is detected at 14 (i.e. the received block is unbalanced) a gate 16 or 15 respectively is opened and the switch 18 operated to its alternate condition. A clock 9 and divider 10 together provide pulses at outputs 11, 12, 13 respectively identifying bit positions 1-8, odd positions 9-31 and even positions 10-32 in transmitted data blocks, while pulses appear at 10 just before those at 11. These pass via one of the opened gates 16, 15 such that the shift register 21-28 generates a particular one of two 8 bit series representing either a request for reframing or loss of phase respectively and these pass to the line. The pulses from the channel indicator 8 pass to a binary circuit 32 which counts up to the number of separate channels (100, set on 34) and resets. Meanwhile, a scaling circuit produces a pulse for each channel occurring at the beginning of a block and at these instants, the content of the circuit 32 is stored in shift register 36 via AND gates 35. The contents of the register are shifted out to the line in odd bit positions 9-31 by pulses at the divider termal 12 and to the even bit positions 10-32 in sequence when gate 38 is opened by the pulses at termal 13. Thus the desired synchronizing block is assembled and transmitted to the line via the gate 29.