Patent SG-11201900098U-A (SG)
Title: Method for continuous tester operation during multiple stage temperature testing
Inventor: ROBERTS JR
IPC: G11C29/48
Filed: 2017-08-02
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property :::` , Organization 111111101111011101 HIM 01110101011010111 1101 MO IMI IDIOM III N International Bureau (10) International Publication Number 03 (43) International Publication Date ......*-- WO 2018/026946 Al 08 February 2018 (08.02.2018) W I P0 I P C T (51) International Patent Classification: (72) Inventor: ROBERTS, JR., Howard H.; 4519 Ave. D., G01R 1/04 (2006.01) GO1R 31/319 (2006.01) Austin, Texas 78751 (US). G01R 31/26 (2014.01) G01R 31/3193 (2006.01) G01R 31/28 (2006.01) G11C 29/48 (2006.01) (74) Agent: MUELLER, Robert W. et al.; c/o GREENBLUM & BERNSTEIN, P.L.C, 1950 Roland Clarke Place, Reston, (21) International Application Number: Virginia 20191 (US). PCT/US2017/045143 (81) Designated States (unless otherwise indicated, for every (22) International Filing Date: kind of national protection available): AE, AG, AL, AM, 02 August 2017 (02.08.2017) AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (25) Filing Language: English DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, (26) Publication Language: English HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, (30) Priority Data: KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, 62/370,355 03 August 2016 (03.08.2016) US MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, (71) Applicant: CELERINT, LLC [US/US]; 750 Third Av- SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, enue, 16th Floor, New York, New York 10017 (US). TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (54) Title: METHOD FOR CONTINUOUS TESTER OPERATION DURING MULTIPLE STAGE TEMPERATURE TESTING Single Insertion Sequence cold rom / hot ri?mping ! H I cycle testing periods 1 2 insert 2 devices (land 2), connect A to tester, A and B are at room 1 switch to A, test A at room, leave B at room 2 insertion 2 switch to B, test B at room,ramp A to CC:0 3 cycle switch to A, test A at cold, ran , ri B to cold 4 ,, , ,itc.11 to 8, test B at coici,rat , ',0 A to hot 5 switch to A, test A at hot, ramp B to hot 6 switch to B, tes.sat hot, ramp A to room 7 tompile rest,i:ts and bin devices (ndex t , r.?3, Yarn B to room 8 repeat insertion cycle with next two devices (3 arid 4) reoeat until lot end FIG. 2 ,-1 (57) : A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor 71' cN testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature f'1 testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single 0 ---..... insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and * 1-1 1:) substantially reduces tester index time when the testing time is less that the ramping times. 0 ei O [Continued on next page] WO 2018/026946 Al IMEDIMOMMIDIRE10101011010HINEDIEMOVOIMIE (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))