Patent TW-305067-B (TW)
Title: Manufacturing method of stack capacitor structure
Inventor: YANG FUH-LIANG
IPC: H01L21/70
Filed: 1996-11-14
Granted: 1997-05-11
Abstract: A manufacturing method of single crown stack capacitor structure of DRAM on semiconductor substrate, because using the single crown stack capacitorstructure can increase capacitor surface area, and used manufacturing process also makes the single crown stack capacitor structure self-align with bit line contact structure, comprises of: (1) on the semiconductor substrate forming field oxide; (2) on the semiconductor substrate surface where is not overlaid by the field oxide, growing one gate dielectric; (3) on the gate dielectric depositing first polysilicon; (4) on the first polysilicon depositing one first salicide; (5) on the first salicide depositing first insulator; (6) on the first insulator depositing one second insulator; (7) patterning the second insulator, first insulator, first salicide and first polysilicon, on the gate insulator and the field oxide, forming polycide gate structure; (8) by ion implantation process, implanting first conductive impurity to between the polycide gate structure, the semiconductor substrate where is not overlaid by the polycide gate or the field oxide, therefore forming lightly doped source and drain region; depositing one third insulator; anisotropically etching the third insulator, on the polycide gate structure sidewall forming first insulating spacer, and removing gate dielectric in the semiconductor substrate area where is not overlaid by the polycide gate structure or the field oxide; by ion implantation process, implanting second conductive impurity to between the polycide gate structure, the semiconductor substrate where is not overlaid by the polycide gate, the first insulating spacer and the field oxide, therefore forming heavily doped source and drain region; depositing first BPSG layer; planarizing the first BPSG layer; patterning the first BPSG layer, on the polycide gate structure forming first BPSG island structure; on the first BPSG island structure top and the polycide gate structure, depositing one second polysilicon, and completely filling space between the polycide gate structure; on the second polysilicon depositing one second salicide; on the second salicide depositing one fourth insulator; on the fourth insulator depositing one fifth insulator; patterning the fifth insulator, fourth insulator, second salicide and the second polysilicon, forming bit line contact structure to the heavily doped source and drain region, located gate insulator between the polycide gate structure, and partially overlays on polycide gate structure on the gate insulator, in the meantime leaving some of the second polysilicon on polycide gate structure on the gate insulator, and between polycide gate structure on field oxide; depositing one sixth insulator; anisotropically etching the sixth insulator, on the bit line contact structure sidewall forming second insulating spacer; on the bit line contact structure top and the second polycide left between the polycide gate structure, depositing one third polysilicon; depositing one second BPSG layer; planarizing the second BPSG layer; patterning the second BPSG layer, on the third polysilicon top forming second island structure, and overlaying the bit line contact structure; depositing one fourth polysilicon; anisotropically etching the fourth polysilicon, on the second BPSG island structure sidewall forming polysilicon spacer; removing second BPSG between the polysilicon spacer; on bit line contact structure top between the polysilicon spacer coating one photoresist, completely filling space between the bit line contact structure, only exposing the third polysilicon top; from the bit line contact structure top removing the third polysilicon, between the bit line contact structure forming bottom electrode structure of the single crown stack capacitor structure, including the under second polysilicon, the third polysilicon, and the polysilicon spacer; removing the photoresist; on the bottom electrode structure forming one capacitor dielectric; depositing one fifth polysilicon, overlaying the capacitor dielectric, the bottom electrode structure, and the bit line contact structure top where is not overlaid by the bottom electrode structure; patterning the fifth polysilicon, forming top electrode of the stack capacitor structure.