Patent GB-892419-A (GB)
Title: Improvements in and relating to transistor pulse generators
IPC: H03K3/284
Filed: 1959-04-29
Abstract: 892,419. Transistor pulse generator circuits: INTERNATIONAL BUSINESS MACHINES CORPORATION. April 29, 1959 [July 31, 1958], No. 14631/59. Class 40(6).  Fig. 1 shows a pulse generator in which a complementary pair of pulses E, F are generated having a variable duration and a leading edge determined by an input pulse A. Initially transistors 11, 18, 31 are conducting and transistors 26, 32, 33 are non-conducting. When an input pulse A is applied at terminals 12 transistor 11 is cut off, 26 becomes conductive and the emitter follower stage 31 has a positive pulse produced at its emitter which charges capacitor 30. Transistor 18 is cut off by pulse B so that a pulse F is produced at its collector. Transistor 32 is initially conducting since the emitter voltage is more negative than the base so that its collector goes negative, Fig., 2, curve E, during the period t0-t1 when the charge on 30 increases until at positive voltage X-X, curve D, the base of transistor 33 is positive with respect to its emitter so that 33 conducts and passes current through resistor 19 and diode 39. This increased current through transistor 33 reduces the current through 32 so that the collector rises, curve E, during the period tl-t2. Since 30 is charging the base of 33 is positive and thus. more current flows until at time t2 the emitter to base diode of transistor 31 conducts clamping the voltage across 30 and the base of 33 at y-y  volts, curve D. At time t2, 32 is cut off terminating the pulse E at output terminals. 37. At time t2 the pulse F is terminated and produced at terminals 38. At time t3 pulse A goes negative so that. pulse C is produced at the base of 31 which is conducting heavily so the voltage at 30 changes negatively and capacitor 30 discharges rapidly through 31 and stays there until the next pulse A appears at the input when the cycle during the period t0-t3 is repeated. Adjustment of the value of capacitor 30 varies the slope of the leading edge of pulse D and the timing of X-X and Y-Y relative to time t0 and t4 so thereby determines the duration of pulses E and F. In a modification shown in Fig. 3 complementary type transistors are used to those in use in Fig. 1 and the output pulses have opposite polarity to those of Figs. I and 2. In the modification shown in Figs. 5 and 6 output pulses E. F are produced having a duration which is either greater or less than that of the input pulses A depending upon the value of variable capacitor 530. Initially transistors 526, 518, 531 are conductive and the other transistors are non-conductive, the negative going input pulse A applied at input terminals 512 causes transistor 511 to conduct; and current is diverted from the constant current source 526, 513 and voltage source plus E to transistor 511. Transistor 526 is thus rendered non-conductive as is also 518 to generate the leading edge of output pulse F. When 518 is cut off 532 conducts to generate the leading edge of output pulse E. This pulse is fed back to the base of transistor 44 to turn it on so sharing current with transistor 511. When either transistor 511 or 44 are conducting positive pulse is applied to the base of emitter follower stage 531 to turn; it off. Capacitor 530 charges, curve D, Fig. 6, until a time t3 transistor 533 conducts and 532 is cut-off so that the pulses E, F are terminated which turns off transistor 44. Capacitor 530 charges until it is clamped by transistor 531 at a time t4. The second input pulse A cuts off transistor 511 so that transistors 518, 531 conduct and capacitor 530 discharges rapidly through transistor 531. The next i.e. third input pulse A initiates another cycle. In a modification, Fig. 7, not shown, complementary type transistors are used to those described in connection with Fig. 5 and output pulses are produced either longer or shorter than the input pulse in dependence upon the value of a variable capacitor, the output pulses being of opposite plurality to those generated by the circuit of Fig. 5.