baber/WOPTO huggingface dataset:
Patent TW-491733-B (TW)
Title: Liquid medicine spray vehicle
Inventor: IKUMOTO JUNICHI
IPC: A01M7/00
Filed: 2001-07-24
Granted: 2002-06-21
Abstract: A liquid medicine spray vehicle having a body (2) on which a liquid medicine tank (8) is mounted, a liquid medicine sprayer mounted on the body (2), a hand-press handle (5) attached to the body (2), and travel wheels mounted on the body (2). As the travel wheels, two pneumatic tires 3(3A, 3B) are mounted on one axle installed on the body (2) in such a way that the two pneumatic tires 3(3A, 3B) are disposed adjacently to each other without providing a gap therebetween and rotatable independently.
Patent TW-562997-B (TW)
Title: Photoresist mask pattern, and preparing method and use thereof
Inventor: NATORI MICHIKO
IPC: G03F7/09
Filed: 2001-09-26
Granted: 2003-11-21
Abstract: The present invention provides photoresist mask pattern, which is capable of reducing conductor resistance of fine wiring and is extremely effective in high circuit densification of semiconductor package substrate. According to the present invention, it is capable of providing photoresist mask pattern having film thickness from 1 to 100 mum and an aspect ratio (corresponding to the line width ratio of the photoresist mask pattern film thickness) larger than 3.5. The photoresist mask pattern can be manufactured by using any one kind of material containing (A) binder polymer, (B) a photopolymerizable compound having three ethylenic unsaturated bonds in the molecule and (C) a photopolymerization initiator, and (D) the compound as shown in the general formula (I) (where m is an integer from 2 to 6) or the compound as shown in the general formula (II), or using the composition of any one or two kinds of photosensitive resins.
Patent TW-520342-B (TW)
Title: Ozone generator
Inventor: LEE JAE SHIN
IPC: C01B13/10
Filed: 2001-09-28
Granted: 2003-02-11
Abstract: There is provided a small and light ozone generating apparatus capable of producing ozone with much less consumption of electric power. The present invention comprises a pulse generator for generating high-voltage pulses and a discharge chamber for inducing electrical discharge in response to the high-voltage pulses. The pulse generator includes an LC circuit for compressing square wave signals and generating impulses. The use of impulse greatly reduces electric power consumption and volume of ozone generating apparatus. Electrical discharge takes place between an electrode plate and grounded chamber wall. A sheet of oxide dielectric covers the chamber wall to prevent corrosion of chamber wall.
Patent TW-556000-B (TW)
Title: Projection zoom lens with a long back focal length and exit pupil position
Inventor: LIN RUNG-DE
IPC: G02B15/173
Filed: 2001-10-25
Granted: 2003-10-01
Abstract: A projection lens has five optical groups, labeled OI to OV, having effective focal lengths fI to fV, respectively. The optical groups move on an optical axis to perform zooming and focussing functions. The projection lens has a total of at least thirteen lenses, which may be labeled L1 to L13, having focal lengths f1 to f13, respectively, Abbe numbers V1 to V13, respectively, and indices of refraction N1 to N13, respectively. Optical group OI has the first three lenses, L1 to L3. Optical group OII has the next two lenses, L4 and L5. Optical group OIII has the next three lenses, L6 to L8. Optical group LIV has lens L9. Finally, optical group OV has the remaining lenses, L10 to L13, of which L10 to L12 combine to form a triplet. The lens groups satisfy the following conditions: -0.45 < (f11/fV) < -0.25, V10+V12-2V11 > 44, 2N11-N10-N12 > 0.5, 0.5 < (fN+fP)/(fP) < 0.9. Where fN is the effective focal length (EFL) of OI and OII, and fP is the EFL of OIII, OIV and OV.
Patent TW-503509-B (TW)
Title: Manufacture method of substrate/oxide nitride/oxide/silicon device
Inventor: YE YAN-HUNG
IPC: H01L21/8246
Filed: 2001-10-29
Granted: 2002-09-21
Abstract: This invention provides a manufacture method of substrate/oxide nitride/oxide/silicon (SONOS) device, which includes: sequentially forming a first oxide layer, a trapping layer and a second oxide layer on a substrate; forming a mask pattern on the second oxide layer to function as an ion implantation mask; performing an ion implantation process to from an embedded bit line in the substrate; subsequently, removing part of the mask pattern and the second oxide layer and the trapping layer not covered by the mask pattern to increase space dimension of the mask pattern and to expose part of the first oxide layer; using the mask pattern as an implantation mask to perform a pocket ion implantation so that a pocket doped region is formed around the periphery of the embedded bit line; removing the mask pattern and using the trapping layer as a mask to conduct a thermal process to from an embedded bit line oxide layer on the substrate; and finally, forming a word line on the substrate.
Patent TW-546879-B (TW)
Title: Container for gas insulating switch device
Inventor: NISHIZAKI MASAYOSHI
IPC: H02B13/02
Filed: 2001-11-06
Granted: 2003-08-11
Abstract: The present invention is a type of container for gas insulating switch device to contain a switch device in a square container for size and weight reduction. The gas insulating switch device is equipped with a square container that has a flange (13, 14) on each of its front and back, a flat top plate (11) on its top, a flat bottom plate (12) on its bottom, and a thin side wall (15) on each of its left and right. Each flange (13, 14) has an opening in the center. On each side wall (15), a middle plane (15b), having a width equal to 1/3 to 1/2 of length between the front and the back of the container, is formed in the middle between front and the back of the container. The space of the middle planes (15b) not only can contain a contained device of the maximum size and ensure a necessary insulation distance, but also can make the front and the back of the middle planes (15b) bend towards the containing center to form two inclined planes (15a, 15c) and, therefore, make the front and the back edges of the inclined planes join on the inner rims of the flanges (13, 14).
Patent TW-I225765-B (TW)
Title: Sleeve assembly for an electronic chip
Inventor: ABBOTT RYAN
IPC: H05K7/10
Filed: 2001-12-27
Granted: 2004-12-21
Abstract: A sleeve assembly (12) for housing and protecting an electronic chip (14). The sleeve assembly (12) includes a first sleeve member (20) and a second sleeve member (22) attached to the first sleeve member (20). The first sleeve member (20) includes at least one substrate engaging member (36) adapted to be inserted into an engaging member hole (52) located on a substrate (18) and at least one chip guiding member (38) adapted to substantially correctly align an electronic chip (14) with a socket (16) when the electronic chip (14) is inserted into the sleeve assembly (12). Additionally the at least one engaging member (36) and the at least one chip guiding member (38) extend from a lower surface of the sleeve assembly (12). The sleeve assembly (12) serves to protect the electronic chip (14) from physical and electrostatic discharge damage during storage as well as after the electronic chip (14) is mated with the socket (16).
Patent TW-567708-B (TW)
Title: Image display using printing commands
Inventor: TSUKINOKIZAWA CHIHIRO
IPC: H04N1/00
Filed: 2002-03-18
Granted: 2003-12-21
Abstract: The image supplying program includes an image generation portion for generating the first image data for displaying the image of the printed object according to the printing commands; and, an image data conversion processing portion, for not only receiving the generated first image data and converting into the second image data receivable by the image display device, but also transmitting the converted second image data through the defined communication interface. The image display device includes an image data receiving processing portion, for not only receiving the second image data through the defined communication interface, but also converting the received second image data into the displayable third image data; and, an image display portion for displaying the image corresponding to the third image data after conversion. With such a composition, the present invention can realize the image display on the image display device with the new method.
Patent TW-I220489-B (TW)
Title: Switching device of universal serial bus for computer peripheral devices
Inventor: PAN WEN-CHANG
IPC: G06F13/00
Filed: 2002-03-25
Granted: 2004-08-21
Abstract: A switching device of universal serial bus (USB) for computer peripheral devices to make a plurality of computers share a common input/output device. The USB switching device comprises a CPU, a display-adjusted device, a frame device, a first interface controller, and a second interface controller. The USB switching device is able to generate a simulation signal controlled by the CPU so that each computer performs simultaneously booting process and then switches to other computer.
Patent TW-561673-B (TW)
Title: Power factor correction circuit arrangement
Inventor: HWANG JEFFREY H
IPC: H02M1/42
Filed: 2002-03-26
Granted: 2003-11-11
Abstract: A power factor correction circuit arrangement. A rectified alternating-current (AC) input signal may be applied across inputs of a voltage converter circuit, such as a boost converter. Current drawn by the voltage converter may be sensed to form a first sensing signal that is representative of the current. The rectified input voltage may be converted to a second sensing signal that is representative of the AC input signal. Switching in the power converter is adjusted in a first feedback loop to equalize the first and second sensing signals and, thus, the current drawn is regulated to remain in phase with the AC input signal. A feedback signal adjusts switching so as to regulate the output voltage level of the voltage converter in a second feedback loop and, thus, controls power delivered to the load.
Patent TW-546310-B (TW)
Title: Method of the synthesis and control of PGO spin-coating precursor solutions
Inventor: ZHUANG WEI-WEI
IPC: H01L21/8246
Filed: 2002-03-28
Granted: 2003-08-11
Abstract: A method of synthesizing a PGO spin-coating precursor solution includes utilizing the starting materials of lead acetate trihydrate (Pb(OAc)2.3H2O) and germanium alkoxide (Ge(OR)4(R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol) ethyl ether. The mixed solution of lead and di(ethylene glycol) ethyl ether is heated in an atmosphere of air at a temperature no greater than 185 DEG C, and preferably no greater than 190 DEG C for a time period in a range of thirty minutes to four hours. During the heating step the color of the solution is monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol) ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190 DEG C for a time period in a range of 0.5 to 2.0 hours. The process results in a PGO precursor solution suitable for use in spin-coating.
Patent TW-544894-B (TW)
Title: Chip carrier with dam bar
Inventor: WANG YU-PO
IPC: H01L23/16
Filed: 2002-04-10
Granted: 2003-08-01
Abstract: A chip carrier with a dam bar is proposed. The chip carrier is defined on a surface thereof with at least a chip attach area and a wire bonding area surrounding the chip attach area, whereby a chip mounted on the chip attach area can be electrically connected to the chip carrier by a plurality of bonding wires disposed on the wire bonding area. A molding gate and a dam bar are formed on the surface of the chip carrier at positions outside the chip attach area and wire bonding area. The molding gate is used for injecting an encapsulating compound that encapsulates the chip and bonding wires. The dam bar is formed with at least a first gate directed toward the molding gate, a second gate and a third gate opposed to the second gate, wherein the second and third gates are each arranged vertically to the molding gate. With the provision of the dam bar, the encapsulating compound would desirably change its direction of mold flow.
Patent TW-522765-B (TW)
Title: SMT device and its manufacturing method
Inventor: LIAU MU-SHAN
IPC: H05K10/00
Filed: 2002-05-14
Granted: 2003-03-01
Abstract: The present invention relates to a SMT device and its manufacturing method. The method comprises: first, respectively sleeving and fixing the ends of two extending rods in the sleeve holes on two side faces of a filament; winding a conductive coil with a suitable number of circles on a rod with a thinner diameter on the center of filament, the coil having two ends respectively conductively connected to the extending rod; cutting the extending rod at two side faces of the filament into a suitable length; further providing a conductive chain formed thereon a plurality of symmetrical two bendable fixing sheets vertically arranged in the extending direction of the chain; bending the two fixing sheets upwardly; sequentially clamping the filament in two fixing sheets of the conductive chain; packaging the filament fixed on the chain as a package; and finally, cutting at the fixing sheet exposed between the package and the chain in a horizontal direction, thereby completing a product of SMT device.
Patent TW-543135-B (TW)
Title: Wafer alignment device
Inventor: FITZPATRICK JOHN JOSEPH
IPC: H01L21/68
Filed: 2002-05-20
Granted: 2003-07-21
Abstract: The device (1) picks up and aligns a sawframe (30) for handling and aligning silicon wafers (31). The device (1) includes at least one resiliently moveable locating arm (11) which is adapted to engage co-operably with a notch (35, 36) on the periphery of the sawframe (30) when the device (1) is moved into contact therewith. The sawframe (30) is thus urged into alignment with the device (1), and may be held in position relative to the device (1).
Patent TW-550751-B (TW)
Title: Structure and method of fabricating embedded vertical dram arrays with silicided bitline and polysilicon interconnect
Inventor: DIVAKARUNI RAMACHANDRA
IPC: H01L21/8234
Filed: 2002-07-01
Granted: 2003-09-01
Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
Patent TW-531436-B (TW)
Title: Method and apparatus for cleaning exhaust gas and dust collector used for its apparatus
Inventor: AIKO MASAHIKO
IPC: B01D53/68
Filed: 2002-07-03
Granted: 2003-05-11
Abstract: To suppress the maintenance work, or enhance the safety of the work, in decontamination process of exhaust gas generated in a manufacturing apparatus of semiconductor or liquid crystal module of film forming apparatus or the like. A decontamination method of film forming exhaust gas containing Si contents comprises a combustion process step of exhaust gas, a decontamination step of dust containing Si from the combustion exhaust gas generated in the combustion process, and a step of washing the decontaminated combustion exhaust gas in water. According to this method, since dust containing Si is removed in the decontamination step, deposition of precipitates is suppressed in the washing step. Accordingly, the process is operated stably, and the maintenance work is lessened. Besides, the washing step can be executed without spending a huge volume of washing water.
Patent TW-591725-B (TW)
Title: Manufacturing method for semiconductor device
Inventor: HAYASHIDA TETSUYA
IPC: H01L21/56
Filed: 2002-07-03
Granted: 2004-06-11
Abstract: The present invention discloses a manufacturing method for semiconductor device, which includes the following steps: separating the substrates carrying with semiconductor chip in matrix on the main surface to have a certain interval and placing between the lower mold and the upper mold of the forming mold and then clamping; injecting the insulating resin from the gate to be formed in the cavity on the main surface of the substrate; and, making the air in the cavity escaped from the venting hole to form the block molding package covering each semiconductor chip; forming bump electrodes on the back of the substrate; next, slicing the block molding package and the substrate in both longitudinal and lateral directions to produce the plurality of semiconductor devices. The venting holes are formed with the trenches in the substrate, and the trenches are configured on the extension lines of the areas for each chip row of the semiconductor chips fixed on the substrate, but not configured on the extension lines of the areas for each chip row. The width of trenches are narrower than the width of semiconductor chips.
Patent TW-I300085-B (TW)
Title: Room-temperature-curable organopolysiloxane composition
Inventor: HARUMI KODAMA
IPC: C09D7/12
Filed: 2002-07-26
Granted: 2008-08-21
Abstract: A room-temperature-curable organopolysiloxane composition comprising: (A) 100 parts by weight of an organopolysiloxane having a viscosity of from 100 to 500,000 mPa.s at 25° C. and having in one molecule 1.5 or more end groups represented by the general formula: <?in-line-formulae description="In-line Formulae" end="lead"?>(X)aR13-aSi-, where<?in-line-formulae description="In-line Formulae" end="tail"?> each X is independently a hydroxyl group or a hydrolyzable group, each R1 is independently a monovalent hydrocarbon group or a halogen-substituted monovalent hydrocarbon group, and a is 1, 2, or 3; (B) 0.01 to 40 parts by weight of a cross-linking agent selected from a silane or a siloxane oligomer where the cross-linking agent has three or more silicon-bonded hydrolyzable groups per molecule; and (C) microparticles of thermoplastic resin containing a platinum compound in such an amount that the content of metallic platinum in component (C) is within the range of 0.01 to 5 wt. %, where the microparticles have an average diameter from 0.1 to 20 mum, component (C) is present in an amount sufficient to provide 1 to 2,000 ppm of metallic platinum in the composition; and (D) 5 to 300 parts by weight of an inorganic powder.
Patent TW-591724-B (TW)
Title: Adhesive film for semiconductor, lead frame and semiconductor device using the same
Inventor: TANABE YOSHIYUKI
IPC: C09J7/38
Filed: 2002-07-29
Granted: 2004-06-11
Abstract: An adhesive film for semiconductor comprises a support film, and adhesive layers formed on both surfaces of the support film, in which each adhesive layer comprises an adhesive having a glass transition temperature of 200 DEG C or less, a coefficient of linear expansion of 70 ppm or less, and a storage elastic modulus of 3 GPa or less, and the adhesive film has a total thickness of between 43 and 57 mum. A lead frame for semiconductor comprises a lead frame and an adhesive film for semiconductor according to the present invention. A semiconductor device comprises a lead frame and a semiconductor element, in which the lead frame and the semiconductor element are adhered to each other via an adhesive film for semiconductor according to the present invention.
Patent TW-I230799-B (TW)
Title: Optical viewer instrument with photographing function
Inventor: ENOMOTO SHIGEO
IPC: G03B13/34
Filed: 2002-09-26
Granted: 2005-04-11
Abstract: In an optical viewer instrument with a photographing function, a telescopic lens system is used for observing an object, and a digital camera is used for photographing an object. The digital camera includes a CCD image sensor and a photographing lens system associated with each other such that the object is formed as a photographic image on the sensor through the photographing lens system. An automatically-operable focussing mechanism is associated with the photographing lens system such that the object is brought into focus through the telescopic lens system, and such that the object is brought into focus through the photographing lens system. Optical various parameters are selected such that predetermined conditions are fulfilled, whereby the focussing of the photographing lens system can be suitably and properly performed in an automatic focussing manner.
Patent TW-564478-B (TW)
Title: Apparatus and method for treating a substrate
Inventor: KAJITA SHINJI
IPC: C23F1/30
Filed: 2002-10-03
Granted: 2003-12-01
Abstract: An apparatus for treating a substrate has a substrate holder 10 which holds and rotates a substrate W, and a heating fluid supplying device 24 which supplies a heating fluid, the temperature of which is controlled, to the substrates W being held and rotated by the substrate holder 10, to contact the substrate W, so as to control the temperature of the substrate. With the apparatus of this invention the speed of treating the substrate, such as etching speed and/or plating speed, can be improved uniformly, and as a result a plating film having a uniform thickness can be easily and quickly formed.
Patent TW-I249649-B (TW)
Title: Resist composition and patterning process
Inventor: TAKEDA TAKANOBU
IPC: G03F7/032
Filed: 2002-10-29
Granted: 2006-02-21
Abstract: A resist composition of a polymer comprises recurring units of the following general formula (1) and has a weight average molecular weight of 1,000 to 500,000, wherein R1 is hydrogen, hydroxy, a straight or branched alkyl group, halogen atom or trifluoromethyl group, R2 is hydrogen, hydroxy, a halogen atom or trifluoromethyl group, and n is 0 or a positive integer of 1 to 4. Resist compositions comprising as the base resin a polymer using tert-amyloxystyrene as a reactive group which is decomposable under the action of an acid to increase solubility in alkali have advantages including a significantly enhanced contrast of alkali dissolution rate before and after exposure, a high sensitivity, and a high resolution in the baking temperature range of 100-110 DEG C which is unachievable with tert-butoxystyrene.
Patent TW-594154-B (TW)
Title: Liquid crystal display device
Inventor: FUJIBAYASHI SADAYASU
IPC: G02F1/1345
Filed: 2002-11-19
Granted: 2004-06-21
Abstract: The present invention comprises: a polysilicon TFT substrate having a capacitor type digital-analog converter; an opposite substrate arranged opposite to the polysilicon TFT substrate; and liquid crystal maintained between the polysilicon TFT substrate and the opposite substrate. In the liquid crystal display device, when the bit number of the digital-analog converter is set to n, the stabilizing time of each bit for capacitor operation is set to tau and the static capacitance between the polysilicon TFT substrate and the opposite substrate is set to CLC, a light shielding film with a resistance larger than n.tau/CLC is formed on the face of the opposite substrate close to the liquid crystal.