Patent GB-1032655-A (GB)
Title: Transistor clamp circuit
IPC: H03K17/687
Filed: 1964-04-13
Abstract: 1,032,655. Television; transistor gating circuits. RADIO CORPORATION OF AMERICA. April 13. 1964 [April 19, 1963], No. 15218/64. Headings H3T and H4F. [Also in Division H1] Clamping of the synchronizing peaks 55, Fig. 4, which occur in the periodically recurring blanking periods 50a of the television video signal 50, to a reference potential, e.g. ground, before they pass to a stage of a television receiver, e.g. amplifier 45, is effected by means of an insulated gate field-effect transistor 56, Figs. 1 and 2, not shown, having source 57, drain 58 and gate 59 electrodes on a substrate of P-type semi-conductor material with N-type source and drain regions, a source of keying signals 51, capacitors 43, 63, and rectifier means 64. The keying pulses 52, which occur during pulse peaks 55, key into operation clamp circuit 53 which adjusts the charge on coupling capacitor 43 whereby the grid 44 of stage 45 is brought to a predetermined reference potential which is ground potential in this embodiment. The insulated gate field-effect transistor is connected as shown and thus the source of video input signals 41 is effectively connected across the channel C of controllable conductivity or resistance between the source electrode 57 and the drain electrode 58. The internal source to drain path C exhibits a resistance that is a function of the gate to source bias voltage, i.e. the keying pulse peaks 52. Diode 64 which comprises the rectifier means is poled to conduct to ground (reference potential) on positive pulse peaks 52 and sets the keying pulse tips at ground potential and the base line at a negative value, Fig. 5, not shown. Coupling capacitor 63 is charged on positive-going pulse peaks 52 by current through the diode, the charge leaking off slowly through the back-resistance 65 of the diode, and the time constant of resistance 65 and capacitor 63 is such that the gate 59 is biased sufficiently negatively during the interval between the keying pulses to maintain the transistor 56 cut off. Thus, during each recurrent peak interval 55 the normally highly resistive current path C is rendered conductive and current can flow in either direction depending upon the polarity of the potential difference between the signal level and the reference or clamping level voltage. Due to the high resistance between the gate electrode 59 and either of the source or drain electrodes 57 and 58 none of the keying pulse current flows in the video signal circuit. In a further embodiment, Fig. 6 (not shown), the internal substrate diode 100 is used as the capacitor charging and discharging rectifier, the gate electrode 59 being connected to the substrate electrode 9,7, and the horizontal synchronizing pulses which have been separated from the video signal serve as the source of keying pulses 93. If the synchronizing peaks of the video signal extend in the positive direction the keying pulses used generate a negative bias voltage at the gate and substrate electrode which is larger than the most negative portion of the video signal, rectifying junction 101 being maintained reversed biased between keying pulses.