Patent GB-1189756-A (GB)
Title: Digital-to-Analog Converter
IPC: H03M1/66
Filed: 1968-05-24
Abstract: 1,189,756. Digital/analogue converters. INDUCTOSYN Ltd. 24 May, 1968 [12 June. 1967], No. 25088/68. Heading G4H. In a digital/analogue converter of the type in which, from a digital input, two signals phase displaced by an amount proportional to the input are derived, an analogue output indicative of the phase displacement is obtained. In the embodiment of Fig. 3 from a number n held in register 4 numbers n, -n are generated and compared with the output of a counter 10 continuously fed with clock pulses so that during each cycle of the counter 10 a pulse is generated by each coincidence circuit 12, 16. These pulses control a gate 26 the output from which represents sine #, where # = n/N x 360 (where N represents a full count of counter 10). Additional pulses are generated at a time in the cycle representing n + N/4 and - n -N/4, these controlling a further gate 46 the output from which represents cos #. In a modification (Fig. 4, not shown) instead of opening and closing gates the output pulses from the coincidence detectors 12, 16 and 14, 18 are fed to summing device (60, 62) the outputs from which represent cos # and sin # respectively. The embodiment of Fig. 5 (not shown) uses one gate (26) to generate sin # and one summing device (60) to generate cos #. In a further embodiment (Fig. 6, not shown) only two coincidence detectors (12, 16) are used but as well as the counter 10 a further counter (15) which counts from N to zero is included so that coincidence pulses are generated at n and -n these controlling one gate (26) and one summing device (60). Fig. 7 (not shown) is a modification of Fig. 6 in which only one counter (70) which counts up to N and then down to zero is used, consecutive output pulses from a coincidence detector (12) being distributed on to one of two leads (24, 34) to control a gate (26) and a summing device (60). In a further modification of the embodiment of Fig. 6 (Fig. 8, not shown) the output signals from coincidence detectors (12, 16) at n and - n open gates (86, 88) and are also fed to delays (80, 82) which gives output signals after time T to close the gates. The outputs from the gates are fed to a summing device (60) the output from which represents cos #. The delays also deliver output signals after a delay T/2, these signals controlling a gate (26) the output from which represents sin #. The embodiment of Fig. 3 may be used to control a resolver 122 (Fig. 9) the outputs from the gates 26, 36 representing the sine and cosine of the number held in register 124 being fed via filters to the stator 121 of the resolver. The output from the rotor 120 is compared in a phase detector 128 with a reference signal derived from the counter 10 the error signal from the phase detector being used to position the rotor 120. Alternatively the rotor 120 may be set to any required position and the output from the phase detector 128 used to drive counter 124 until its count represents the position of the rotor. In a modification (Fig. 10, not shown) the filters 142 are replaced by a filter (160) following the phase detector. In a further embodiment (Fig. 11, not shown) for controlling a resolver the coincidence detectors comprises NAND gates (316) which control via gates (340, 344) digital delays (342, 346) which, as in the embodiment of Fig. 8, deliver output signals after times T/2 and T, the former controlling a gate (350) which generates a signal representing sin # to control the resolver and the second resetting the gates (340, 344) which are connected to NAND gates (367-370) operating as a summing network the output from which represents cos #. NAND gates may be used to generate the numbers - n, n + N/4 andn - N/4 from the number n.