Patent GB-1248077-A (GB)
Title: Inverter apparatus
IPC: H02M7/515
Filed: 1968-11-12
Abstract: 1,248,077. Inverters; commutation. WESTINGHOUSE ELECTRIC CORP. 12 Nov., 1968 [29 Nov., 1967], No. 53587/68. Heading H2F. A polyphase inverter (Fig. 1) supplying a load ZaZbZc, features a commutation circuit, wherein auxiliary SCR switches S1 S2 are selectively switched to apply a charge on capacitors C1 or C2 via transformers L1 or L2 to turn OFF selected ones of main rectifiers (e.g. SCR's) Sal, Sb1, Sc1 Sa2, Sb2, Sc2, and energy stored in the transformers is recovered and fed back to the D.C. source before the end of each half cycle, or in addition a portion of the energy may be dissipated in resistors (Fig. 4, not shown) to enable immediate turning ON again of an SCR which has just been commutated OFF. Operation.-Assuming windings (1-2) and (1<SP>1</SP>-2<SP>1</SP>) have 2N turns and windings (3-4), (3<SP>1</SP>-4<SP>1</SP>), (5-6) ,  (5<SP>1</SP>-6<SP>1</SP>), each have IN turns, and that C1 is charged to a voltage 4E (i.e. 4 times the D.C. supply voltage) and C2 to - 3E volts. The main SCR's are controlled by a firing circuit (not described) so that during a period TO-T1 (Fig. 2) Sa1, Sc1 Sb2 are conducting simultaneously. Current therefore flows from B+ through winding (1-2) of L1, via Sa1 and Sc1 to   load impedances Za, Zc respectively, through Zb, Sb2 and winding (11-2<SP>1</SP>) to B - line. Auxiliary rectifier S1 controls the cut-off of the top row and S2 the bottom row of main rectifiers. Thus at time T1, S1 is turned ON and the voltage 4E on C1 is placed across windings (1-2) and (3-4) in series. Due to their turns ratio + <SP>8</SP>/ 3 E volts will appear across (1-2);. with the dot end positive, and <SP>4</SP>/ 3 E across (3-4). A reverse bias voltage will appear across the top row of main rectifiers and will be <SP>8</SP>/ 3 E less the source voltage E, i.e. - <SP>5</SP>/ 3 E volts, so that Sa1 Sc1 will turn OFF. C1 then begins to discharge via windings (1-2) and (3-4) and S1 also C2 begins to charge to +4E volts while C1 goes to - 3E volts at time T2, for the next commutation. During the commutation interval when the top row are reverse biased load current is maintained through path from output terminal Tb through Sb2 (1<SP>1</SP>-2<SP>1</SP>), diodes Da2, Dc2, Za, Zc and Zb back to Tb. At time T2 voltage across (1-2) is - 2E and therefore the voltage across (5-6) is - E, so that a diode Dl is forward biased and connects winding (5-6) to the B+ line, which restores energy in L1 to the D.C. source and current in (1-2) and (3-4) drops immediately to zero. Thus the current in S1 also drops to zero, turning it off. The conduction of D1 also clamps C1 at the desired commutation level - 3E. At time T3 when current through L (5-6) drops to zero, the voltage across each top row SCR drops to the source voltage E so that selected ones can be gated again. A similar commutation and energy recovery sequence occurs when S2 is gated. Gating pulses may be interrupted during the intervals when energy is being restored. In a modified arrangement. Fig. 4 (not shown), resistors in series with diodes are connected across windings (1-2) (1<SP>1</SP>-2<SP>1</SP>) to dissipate a portion of the stored energy prior to the conduction of diode D1 or D2, to permit immediate turn ON of main SCR's which have just been commutated OFF.