Patent GB-833795-A (GB)
Title: Improvements in or relating to calculating apparatus
IPC: G06F7/491
Filed: 1957-06-07
Abstract: 833,795. Digital electric calculating apparatus. COMPAGNIE DES MACHINES BULL. June 7, 1957 [June 27, 1956], No. 18242/57. Class 106 (1). In an apparatus for multiplying codeddecimal numbers represented by series-mode pulse trains, the multiplicand is multiplied by, no more than four given factors and multiples so formed are simultaneously selected under control of each successive multiplier digit and then accumulated. In a preferred embodiment the code 1, 2, 2, 5 is used in the multiplier, and the multiplicand multiplied by five (M x 5) is provided in binary-coded decimal form on line 2<SP>1</SP>, M Î 1 on line 31 and M x 2 on line 41. Each multiplier digit is separated into the four code elements by selectors 6, 7, 8 and 9 which allow the appropriate multiplicand digit signals to pass through only when a significant multiplier digit code element is detected. Thus, signals representing partial products are passed to known series-mode decimal adders 15 and 18 which, together with a circulatory delay loop 16, 17, serve to accumulate the product. Partial product generators.-To be multiplied by five the multiplicand, in binary-coded seriesmode pulse form, is fed on line 1, Fig. 3, to a. pair of coincidence gates 20, 23 which also. receive control pulses T1 and #T1 respectively. Gate 20 allows only significant " 1 " pulses to pass; while gate 23 allows the remaining three elements " 2," " 4 " and " 8 " of the multiplier digit through to a delay element 27. The device is a pulse quadrupler while a further device 22 is a generator producing pulses representing the digit " 5." As multiplication by "5" is equivalent to multiplication by " 10 " accompanied with a division by " 2," the binary components " 2," " 4 " and " 8 " give rise respectively to the binary components " 1," " 2 " and " 4 " of the next higher decimal order. This is effected by the delay element 27 which has a delay of three binary digit positions. The remaining " 1 " element, if present, is multiplied by five by the arrangement 21, 22 and coincidence gate 24, and added to the other components by a known serial binary adder 25. After passing a suitable delay element 28, the result signals appear on line 2<SP>1</SP>, Fig. 2. Multiplication by two is obtained by delaying the digit signals by one pulse time if they represent a decimal digit less than " 5." If greater than " 5," the digit " 6 " is added to the delayed pulses. Fig. 4 shows the circuit for doing this. A device 29 tests the multiplicand digit entering on line 1 and controls a pulse quadrupler 30 according to whether the value is, on the one hand, less than five, or, on the other hand, equal to, or greater than, five. At the same time the multiplicand signals pass through three-bit delay elements 36 and 37, while a generator 32 produces pulses representing the value six. If the multiplicand digit is less than five, pulses are fed from the lower output 40 of the device 30 to gate the multiplicand digit signals from delay element 37 through to line 41, Fig. 2. If the multiplicand digit is equal to or greater than five, pulses appear on the upper output 39 and gate the multiplicand digit plus six through to the line 4<SP>1</SP>. Other arrangements for multiplying by five (Fig. 3a, not shown) and two (Fig. 4a, not shown) are also described. Multiplier translator.-The translation of the multiplier digit appearing on line 10, Fig. 2, into the 1, 2, 2, 5 code is achieved by the arrangement shown in Fig. 6. The binarycoded signals on line 10, Fig. 6, are separated on to parallel channels by signals T1, T2, T3, T4, occurring successively in coincidence with the binary signals and, by means of delay elements 82, 83 and 84 of three, two and one binary units respectively, are simultaneously applied to devices 46 ... 49, each of which has an upper output line on which a pulse appears if the corresponding binary signal was present in the multiplier digit signal, and a lower output line on which a pulse appears if the binary signal was absent. Connections between these lines on the one hand, and AND gates 58 ... 66 and OR gates 75 ... 78 on the other hand, in accordance with a formula given in the Specification, provide signals at gates 42 ... 45 in accordance with the 1, 2, 2, 5 code. In another embodiment (Fig. 9, not shown) the binary-coded factors are multiplied without converting them to the 1, 2, 2, 5 code. Specifications 717,869, 730,297 and U.S.A. Specification 2,861,740 are referred to.