Patent EP-1939888-A1 (EP)
Title: Memory cell equipped with double-gate transistors, with independent and asymmetric gates
Inventor: THOMAS OLIVIER
IPC: G11C11/412
Filed: 2007-12-17
Abstract: The random access memory cell (300) useful in a microelectronic memory device, comprises symmetric two-grid transistors (TL1(T), TL1(F), TD1(T), TD1(F), TL2(T), TL2(F)) forming a base, a first and a second asymmetric two-grid access transistor (TA1(T), TAW1(T)) and (TA1(F), TAW1(F)) formed between a first bitline (BL(T), WBL(T)) and a first storage node (T) and between a second bitline (BL(F), WBL(F)) and a second storage node (F) respectively, a second word line (RWL), third and fourth bitlines (RBL(T), RBL(F)), and two-grid third and fourth access transistors. The random access memory cell (300) useful in a microelectronic memory device, comprises symmetric two-grid transistors (TL1(T), TL1(F), TD1(T), TD1(F), TL2(T), TL2(F)) forming a base, a first and a second asymmetric two-grid access transistor (TA1(T), TAW1(T)) and (TA1(F), TAW1(F)) formed between a first bitline (BL(T), WBL(T)) and a first storage node (T) and between a second bitline (BL(F), WBL(F)) and a second storage node (F) respectively, a second word line (RWL), third and fourth bitlines (RBL(T), RBL(F)), two-grid third and fourth access transistors (TAR1(T), TAR1(F), TAR2(T), TAR2(F), TAR3(T), TAR3(F), TAR4(T), TAR4(F)) connected to the third bitline and the fourth bitline respectively, an additional symmetric two-grid transistor (TDR1(T)) between the third access transistor and the first node, and another additional symmetric two-grid transistor (TDR1(F)) between the fourth access transistor and the second node. The first grids of the first and second access transistors are connected to a first wordline (WL, WWL), which is adapted to deliver a polarization signal. The second grid of the first and second access transistors is connected to the second and first storage nodes respectively. The first set of transistors is formed of first and second symmetric two-grid load transistors (TL1(T), TL1(F)), and first and second symmetric two-grid conduction transistors (TD1(T), TD1(F)). The two grids of the first and second load transistors are connected together respectively. The two grids of the first and second conduction transistors are connected together respectively. First grids of third and fourth access transistors are connected to the second word line, which is adapted to deliver a polarization signal. The second grid of third and fourth access transistors is linked to the second and first storage node respectively. The two grids of the third (TAR3(T), TAR4(T)) and/or fourth access transistors (TAR3(F), TAR4(F)) are connected to the second wordline respectively. Asymmetrical double grids are formed of a first and a second grid block and an active semi-conductor zone. The first grid block, the active semiconductor zone and the second grid block are superimposed or juxtaposed on a substrate. The first and second grid blocks have a different critical input dimension. The first grid block is separated from the semi-conductor active zone by a first block of dielectric material of given thickness. The second block grid is separated from the active semi-conductor zone by a second block of dielectric material of thickness greater than the given thickness. The first block belongs to the first grid, and has a given composition. The second block belongs to the second grid, and has a composition different to that of the given composition. Independent claims are included for: (1) a static random access memory; and (2) a microelectronic memory device.