Patent TW-323393-B (TW)
Title: Manufacturing method of crown-shaped stacked capacitor of dynamic random access memory
Inventor: Zheng xiang-yuan
IPC: H01L21/70
Filed: 1997-05-31
Granted: 1997-12-21
Abstract: A manufacturing method of multiple crown-shaped capacitors of dynamic random access memory cell comprises of the following steps: (1) Supplying one semiconductor substrate with multiple active areas, which are surrounded by multiple filed oxides and separated each other; (2) Supplying multiple field effect transistors on those active areas, in which those field effect transistors have defined one first polysilicon with one formed gate electrode, and above those active areas there are multiple first and second source/drain contact region, and depositing one first insulator on the above transistors to insulate each other; (3) Forming one planarized second insulator on the first insulator; (4) By photoresist mask and anisotropically etching multiple contact openings to expose those first source/drain contact regions of those field effect transistors, so as to form multiple bit line contact opening of multiple bit lines; (5) Depositing one second polysilicon on the semiconductor substrate, in which the second polysilicon has one heat-resistant salicide layer; (6) Depositing one third insulator on the heat-resistant salicide; (7) By photoresist mask and anisotropical plasma etch patterning the third insulator and the second polysilicon to keep the second polysilicon above those first source/drain contact region, so as to form multiple bit lines of those dynamic random access memory cells; (8) Depositing one fourth insulator capping those bit lines, and planarizing the fourth insulator; (9) Depositing one hard mask on the planarized fourth insulator; (10) Forming one patterned photoresist layer on the hard mask, making the photoresist layer above those source/drain contact region have multiple openings; (11) anisotropically etching and punching the hard mask, and partially etching into the fourth insulator of those photoresist opening region, so as to form multiple cavities; (12) Removing the photoresist layers; (13) On those cavities depositing one fifth insulator, and performing blank anisotropical etchback to the fifth insulator to form multiple spacers, and exposing the fourth insulator between those spacers among those openings; (14) Anisotropically and selectively etching the fourth and second insulator of those openings to expose these second source/drain contact regions, so as to form multiple contact openings, thereby increasing resolution limit of the patterned photoresist layer, and those wider contact openings being able to decrease aspect ratio of the fourth insulator; (15) Depositing one third polysilicon on other portions of those second source/drain contact openings and the semiconductor substrate; (16) Depositing one second mask layer and performing blank anisotropical etchback to keep the second mask layer of those source/drain contact regions, and exposing other portion of the third polysilicon on the semiconductor substrate; (17) Etching back the third polysilicon and the hard mask to the fourth insulator; (18) By selective etch removing the second mask layer and the fourth insulator to form multiple bottom plates of those crown-shaped stacked capacitors; (19) Forming one inter-electrode dielectric on those bottom plates; (20) Depositing and patterning one fourth polysilicon to form multiple top plates and form crown-shaped stacked capacitors.