Patent GB-1013985-A (GB)
Title: Semiconductor devices and methods of making them
IPC: H01L21/225
Filed: 1962-12-21
Abstract: 1,013,985. Semi-conductor devices. RADIO CORPORATION OF AMERICA. Dec. 21, 1962 [Jan. 19, 1961], No. 48391/62. Heading H1K. A method of diffusing an impurity into a semi-conductor comprises decomposing a vaporized doped siloxane compound on to the surface to form a doped silicon oxide layer, and then heating to diffuse the impurity from the oxide layer into the semi-conductor. Apparatus is described in which a carrier gas is bubbled through a liquid siloxane compound in which the doping agent is dissolved, the resulting vapour being passed to a heated chamber where it decomposes on to the semi-conductor wafer. Alternatively, the heated vapour may issue from a jet and impinge on the semiconductor surface. Methods of producing diodes are described in which a doped silicon oxide layer is formed on the semi-conductor and removed after the wafer has been heated to diffuse the impurity into the semi-conductor. Parts of the oxide layer may be removed before the diffusion step to produce localized doping. As shown, Figs. 5e, 5h, 5j, a plurality of transistors are produced by depositing a layer 54 of undoped silicon oxide on an N-type wafer 51 of silicon doped with antimony, by heating the wafer and exposing it to oxygen, steam or a decomposign siloxane vapour. The layer 54 is then masked with a photo-resist and parts are removed by etching. The resist is then removed and the wafer heated in a stream  of argon into which is introduced ethyl silicate vapour doped with trimethyl borate which decomposes to form a layer 56 of silicon oxide doped with boron. The wafer is then heated in a hydrogen atmosphere to diffuse the boron from layer 56 into wafer 51 through the aperture in the layer 54 to produce P-type region 57 and junction 58. The layer 56 is then masked and etched to form aperture 59, Fig. 5e. A layer 60 of silicon oxide doped with phosphorus is now deposited on the wafer using ethyl silicate doped with trimethyl phosphate. The wafer is then heated to diffuse phosphorus from layer 56 into the P-type region 57 to produce an N-type region 61 and junction 62. Central aperture 63 and ring aperture 64 are formed in the oxide layers by masking and etching, Fig. 5h. A layer of aluminium is evaporated on to the surface of the device and is then masked and etched to produce electrodes 65<SP>1</SP>, 65<SP>11</SP>, in ohmic contact with the diffused N- and P-type regions 61, 57 and the wafer is then sliced into separate devices 50, Fig. 5j. The devices are NPN planar transistors the emitter lead being attached to electrode 65<SP>1</SP>, the base lead to electrode 6511 and the collector lead is ohmically connected to face 52<SP>1</SP>.  The Specification states that the method of the invention may be used with semi-conductors comprising germanium, silicon, germaniumsilicon alloys, gallium-arsenide, or indiumphosphide. The carrier gas may be nitrogen, argon, helium, hydrogen, or forming gas, the siloxane may be ethyl silicate or ethyl triethoxysilane, and may be doped with compounds of aluminium, antimony, arsenic, boron, gallium, indium, phosphorus, or sulphur, trimethyl phosphate and trimethyl borate being specifically mentioned. Suitable acid resists and photo-resists are mentioned, together with solvents for removing the silicon oxide and the resists.