Patent GB-1107271-A (GB)
Title: Automatic phase control
Inventor: TAKADA YUJI
IPC: H04L27/227
Filed: 1965-03-23
Abstract: 1,107,271. Automatic phase control; transistor switching circuits. FUJITSU Ltd. 23 March, 1965, No. 12333/65. Headings H3A and H3T. In a system in which a carrier signal modulated with two channels is mixed with a local oscillator to produce two separate demodulated output channels, the local oscillator is phase locked to the input signal by means of a control signal derived from the two output channels. The control circuit comprises an amplitude/ pulse width converter for producing two control signals, which are pulse width modulated in accordance with the amplitudes of the two output signals respectively, and means for adding the pulse width modulated signals algebraically to provide a single control signal for adjusting the frequency and phase of the local oscillator. As described, the input signal, modulated to one of four quadrature phases corresponding to the four conditions mark/ mark, mark/space, space/mark, space/space in the two channels, is fed to a pair of phase discriminators PD 1 , PD 2 , Fig. 4. The local oscillator OSC is fed directly to PD 1  and via a 90 degrees phase changer PS to PD 2  to produce separate demodulated output signals which are fed via filters LF 1 , LF 2  and trigger circuits TR 1 , TR 2  to the outputs Ach, Bch. The outputs from LF 1 , LF 2  are fed to the converters CONV 1 , CONV 2  to produce pulse width modulated output signals which are added algebraically in an adder ADD and then integrated to provide the control signal for the oscillator OSC. In order to ensure that the control signal is always of correct polarity signals from trigger circuits TR 1 , TR 2  and their outputs are gated in dependence on the polarity of a further control signal from a " multiplier " RM. The converters are also fed with positive and negative ramp waveforms from a pulse generator PG. The slope of the ramp being controlled by a level sensing circuit LD connected to the input. Pulse generator. Fig. 7.-A trigger pulse at IN, switches bi-stable circuit 1 to the state in which TS2 is conductive to switch off TS3. TS4 switches on cutting off diode D1 and capacitor C1 charges from C2 to produce a ramp waveform at the emitter of TS4. When this ramp reaches -10v trigger circuit 3 operates to provide a reset pulse for bi-stable circuit 1 and TS3 switch on to discharge capacitor C1. The circuit then remains in this state until the next trigger pulse on IN 1 . The rate of charge of C1, and hence the slope of the ramp may be controlled by a thermistor RS, the resistance of which is, varied by a control signal at IN 2 . The ramp signal may be integrated by including the similar integrator of Fig. 9 (not shown), with its first input (IN 1 ) and output (OUT) connected between points AA, and its second input (IN 2 ) connected to the collector of TS2. Converter circuits, Fig. 10.-Each converter is fed from the pulse, generator with a negative ramp voltage at IN 2  and a positive ramp voltage at IN 3  and also, from its associated trigger circuit TR, with a zero or negative control signal at IN 4 . The variable amplitude signal from the filter LF is applied at IN 1 . If this signal is positive, the control signal at IN 4  is zero and gate 3 is closed. The input IN 1  is then compared with the positive ramp signal in comparator 2 to produce a negative output pulse at TS 7  which persists for the time during which the ramp signal amplitude exceeds that of the input at IN 1 . The signal is fed via OR gate 6 to provide a negative output pulse from amplifier 7. If the signal at 1N 1  is negative, the control signal at IN 4  is negative, and gate 5 is closed. The input IN 1  is then compared with the negative ramp signal in comparator 2 to produce a negative output pulse at TS6 which is fed to the output via OR gate 6. Multiplier and gate circuits, Fig. 12.-The outputs from the two channels are either Ov or -12v, and these are fed to the input terminals IN 1 , IN 2  of multiplier 1. This circuit is an " EXCLUSIVE-OR " and produces -12v and Ov at the collectors of transistors TS 3 , TS 4  respectively when both inputs are the same. When the two inputs are different the collector of TS 4  is at -12v and collector of TS 3  is at Ov. The outputs are fed to a gating circuit comprising AND gates 4, 5, 6, 7 and OR gates 8, 11 so arranged that, when inputs IN 1 , IN 2  are the same, input IN 3  is connected to output OUT, and input IN 4  is connected to output OUT 2 , and when inputs IN 1 , IN 2  differ IN 3  is connected to OUT 2  and IN 4  to OUT 1 . This ensures that the algebraic sum of the two control signals OUT 1 , OUTS is always of correct sign. Add and integrate circuits, Fig. 13.-The two outputs from the gate circuit of Fig. 12 are fed via IN 1 , IN 2  of Fig. 14 to a negative OR gate 3 and a negative AND gate 4. If the duration of the pulse at IN 1  is longer than that at IN 2 , a negative pulse signal dependent on the difference, Fig. 14(a) F (not shown), is obtained from gate 4 and is fed to integrator capacitor C to charge it negatively. Conversely if the reverse conditions obtain a positive pulse signal, Fig. 14(b) E (not shown), is obtained from gate 3 and charges capacitor C in the positive direction. The output control signal for the local oscillator is taken from transistor TS 5 .