Patent GB-1289980-A (GB)
IPC: G08G5/04
Filed: 1969-12-22
Abstract: 1289980 Radionavigation SIERRA RESEARCH CORP 22 Dec 1969 [2 Jan 1969] 62230/69 Heading H4D  Relates to multi-mode means for progressively improving the synchronization of the clockcounter carried by each participating aircraft in a co-operative co-altitude aircraft collision avoidance system (CAS) using time slots synchronized to a common system-wide standard time and one-way ranging such as proposed by the Air Transport Association of America (ATA) in which the clock-counter at each aircraft and ground station defines recurrent epochs of duration three seconds, each aircraft epoch between divided into an initial group of 64 wide (6,000 Ás) time slots followed by narrow (1500 Ás) time slots and each ground station transmitting a coded odd-epoch-start-signal OES at the start of each odd-numbered epoch, a differently coded even-epoch-start-signal EES being transmitted by each fully equipped aircraft at the start of each even-numbered epoch. General operation.-Figs. 1A and 1B show the equipment carried by each participating aircraft. When the aircraft enters a CAS area the equipment is switched on and after a preliminary warm up period, Mode 0, it operates in Mode 1 during which it determines distances from other participating stations by a two-way ranging interrogator-transponder type operation (socalled asynchronous back-up mode) and also listens out for epoch start signals ES from other fully synchronized air or ground stations. When such an epoch start signal ES is received said signal resets the clock counters 22, 24, 28 (thereby producing rough synchronization) and initiates Mode 2 (coarse synchronized back-up mode) in which the aircraft transmits during a selected wide own slot WOS a sync. request signal SR which initiates at a donor station a sync. reply signal SRP such that the sync. reply signal is received by the requesting aircraft at a time instant in its own slot which differs from a predetermined sync. moment PSM in said own slot by a time interval #t equal to twice the sync. time error e(t) of the local (own) clock counter relative to the clock counter at the donor station. The initial sync. error e(t) is equal to the signal transit time between the two stations and the corresponding error signal #t actuates a sync. correction circuit 74 to change the frequency of the local clock oscillator 20 for a period proportional to #t thereby effecting a "large" correction of the local clock oscillator 20.. When #t is reduced to less than 2 Ás, Mode 3 (fine sync.) is initiated during which a narrow (1500 Ás) own slot is selected and the sync. correction circuit provides a "small" correction of the clock counter 22 by adding Or subtracting an additional clock pulse during each counting cycle. This is the normal mode of operation and during this mode the aircraft transmits during its own narrow slot a Doppler range pulse and other data, e.g. altitude, signals, (hereinafter collectively referred to as CAS signals, CAS(S)), corresponding CAS signals received from other stations being processed in a known form of CAS unit 15 to evaluate collision threats; the CAS signals are also transmitted in Mode 2 and may also be transmitted in Mode 1. As described the sync. request and CAS signals are produced by separate generators 66 and 60 but alternatively the sync request signal may constitute part of the CAS signal. If after Mode 3 has been established, the time error #t should increase (e.g. due to loss of radio contact with donor stations) then the following corrective action is automatically initiated: (1) if #t is within 2-20 Ás for one epoch only then fine sync. control is effected, (2) if #t is within 2-20 Ás for two successive epochs the system switches to Mode 4 which uses a narrow own slot (as in Mode 3) and "large" clock correction as in Mode 2. If #t is subsequently reduced to less than 2 Ás the system returns to normal Mode 3 operation but if #t becomes greater than 20 Ás for two successive epochs or if no sync. reply signals SRP are received during 64 consecutive epochs the system reverts to Mode 1 and the above cycle of operations is repeated. Means are also described for preventing retention of an own slot which is already occupied by another aircraft, so-called double slot occupancy. Detailed operation.-As shown the back-up mode interrogation signal IS, the sync. request signal SR and the CAS signals CAS(S) are produced respectively by coding units 56, 66, 60 and the received even (air) and odd (ground) epoch start signals EES and OES, the sync. reply signals SRP, the received CAS signals CAS(S) and the transponder reply signals TRS are selected by respective decoders 44, 46, 72, 17, 13. The five Modes 0-4 are established respectively by the outputs 30b-34b from five bi-stables 30-34 which are interconnected so that at any instant only one unit can be in a "set" condition. The clock-counter unit comprises: (1) a clock oscillator 20 normally operating at 5 MHz but capable of operating at 10 MHz or 2.5 MHz in response to control signals on leads 84a and 85a, (2) a main slot-length counter 22 producing during each slot on outputs 22a, 22b, 22d: (a) a trigger pulse for initiating the CAS signals CAS(S) in unit 60, (b) a trigger pulse for initiating the sync. request signal SR in unit 56, and (c) a signal corresponding to the predetermined sync. moment PSM, (3) a slot succession counter 24 producing local epoch start signals ES on output lead 24b and also coupled to a slot logic unit 26 and slot selector 19 for producing a selectable narrow or wide own slot signal, NOS or WOS, on leads 19a and 19b respectively,  (4) a counter 28 responsive to the local epoch start to give local odd and even epoch start signals OES(L) and EES(L) on leads 28a and 28b which select an upper aerial 12 during an air (even) epoch and a lower aerial 14 during a ground (odd) epoch. In operation the Mode 0 bi-stable 30 is set by a push-button 36 and after a warm-up delay period the bi-stable output 30b enables a gate 42 to apply any received epoch start signals ES from the decoders 44 and 46 to a recognition circuit 52, components 44d and 46b being provided to inhibit air epoch start signals EES if the more accurate ground epoch start signals OES are being received. If no epoch start signals are received a NO output from the recognition circuit 52 sets the Mode 1 bi-stable 31 whose output 31b continues to enable gate 42 and also enables a gate 54 to apply a wide own slot signal WOS to initiate interrogation and (optionally) CAS signals IS and CAS(S) in units 56 and 60, any resultant transponder reply signal TRS being applied from the TRS decoder 13 to the CAA unit 15 to give range. When an epoch start signal ES is received the resultant YES output from the recognition circuit 52 on lead 52a resets the counters 22, 24, 28 thereby effecting rough synchronization and also sets the Mode 2 bi-stable 32 whose resultant output 32b enables a gate 64 to apply the wide own slot signal WOS to enable: (1) the sync. request and CAS signal generators 66, 60, (2) a gate 71 to apply the resultant sync. reply signal SRP from the decoder 72 to the sync. correction circuit 74, and (3) a gate 75 to apply the predetermined sync. moment signal PSM from the counter 22 to the correction circuit 74. The correction circuit 74 comprises two bistables 76, 78 interconnected by gates 80, 82 to produce on lead 78a or 76a an early or late error pulse EP(E) or EP(L) of duration #t (i.e. time interval between signals SRP and PSM) according to whether the predetermined sync. moment signal PSM leads or lags the sync. reply signal SRP (i.e. according to whether the local clock counter is early or late relative to the clock counter at the donor station providing the sync. reply signal SRP). Since the rough synchronization was effected by resetting the counters 22, 24, 28 by an epoch start signal from another station, the local clock counter will be late by an amount corresponding to the signal transit time between the two stations and hence a late error pulse EP(L) is produced which is applied via a normally enabled gate 84 and lead 84a to double the frequency of the clock oscillator 20 thereby advancing the timing of the local clock counter. When #t is reduced to less than 2 Ás an error test circuit 87 sets the Mode 3 bi-stable 33 and the resultant output on lead 33b: (1) enables a gate 90 to apply the narrow own slot signal NOS to enable the sync. request and CAS signal generators 66, 60 and to enable the sync. reply and predetermined sync. moment signal gates 71, 75 (i.e. operation as in Mode 2 except that narrow own slot signal NOS used in place of wide own slot signal WOS), (2) inhibits the sync. correction circuit 74 error output gates 84, 85, and (3) enables a gate 95 responsive to outputs from three error test circuits 87, 88, 89, responsive to the early or late error pulses EP(E), EP(L). As long as the error #t remains less than 2 Ás only test circuit 87 will produce an output which triggers a one-shot 96 to produce a short correction pulse which is applied in parallel to two counter 22 control gates 97 and 98 enabled respectively by the early and late error pulses EP(E) and EP(L) from the sync. correction circuit 74 so that if the counter 22 is running late the correction pulse adds one count to produce a 0À2 Ás time advance and conversely if the counter is running early the correction pulse deletes one count to retard the counter. If #t increases to within 2 to 20 Ás the error test circuit 88 first produces a small correction similar to that produced by the test circuit 87 but if the increased error persists for two successive epochs this condition is detected by a circuit 88c which then sets the bi-stable 34 to initiate Mode 4 which differs only from Mode 3 in that the error test circuit output gate 95 is inhibited and the sync. correction circuit 74 . output gates 84 and 85 are enabled so that the er