Patent GB-756757-A (GB)
Title: Serial type binary-decimal adder
IPC: G06F7/495
Filed: 1954-01-27
Abstract: 756,757. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 27, 1954 [Jan. 30, 1953], No. 2495/54. Class 106 (1). An adder for decimal digits each represented as a serial group of binary digits comprises a first and a second binary adder arranged respectively to add input digits to produce a first sum and to add the first sum and a connecting digit to provide a corrected sum, and discriminator means connected to receive the digits of the second to fourth binary orders of the first sum and the carry component from the first binary order of the corrected sum, the discriminator means being adapted to supply the connecting digit to the second adder only when predetermined criteria are satisfied. In the apparatus shown in Fig. 1, for adding decimal numbers represented by serial pulse trains, each decimal digit being represented by a group of four pulse .periods corresponding to binary values 1, 2, 4, 8, the pulse trains are applied to the inputs 20, 21 of a first binary adder 10 and the unconnected sum train at 25 is applied through one-digit delay circuits 14, 15 and lead 27 to the input 20 of a second binary adder 12 to which a correction train, representing " 6," is applied, when required, from a binarydecimal discriminator 11; the adders 10, 12 each receive also on a third input 22 carry pulses recirculated from output 23 through a one-digit delay circuit 13 or 17. The correction value of " 6 " must be added in a decimal digit position of the sum if the value represented therein is greater than " 9 " or of a carry-over is obtained. These two conditions are tested for at the time when the second binary digit (corresponding to " 2 ") of each decimal digit is being applied to adder 12, by a " column pulse " applied to input 29 of the discriminator. At this time, owing to delay circuits 14, 15, the carry-over digit and the binary digits in positions 8, 4, 2 are available on leads 30, 32, 34, 36, connected to inputs 31, 33, 35, 37, and any carry into position " 2 " in adder 12 is available on lead 38 connected to input 39. If there is a positive input pulse (representing " 1 ") on input 31, or on input 33 plus 35, 37 or 39, the discriminator produces output pulses at 42 and 44, the pulse at 44 being delayed one digit period in circuit 16 and applied to 42 through input terminal 46 and the discriminator. Thus the connection pulse train representing " 6 " (0110) is supplied to lead 43 connected to input 21 of adder 12. The delay circuits may be as described in Specification 719,418. Binary adders. Each of the adders 10, 12, Fig. 1, comprises a circuit, Fig. 3, for producing a positive carry output at 23 in response 'to two or three positive inputs at 20, 21, 22, and a positive sum output at 25 (28 for adder 12) for one or three positive inputs. The circuit comprises diode coincidence gates 93, 98, 102, connected to the inputs in pairs, and a cathode follower triode 116L for producing the carry, and " or " and coincidence gates 138 and 157 together with cathode follower double triodes 126, 146 for producing the sum. The output of the " or " gate 138 is applied through triode 126R to diode 140 of coincidence gate 143 whose diode 139 receives the carry output, inverted in triode 116R, through 126L, so that the gate 143 produces a positive output only if one and not more than one of the adder inputs is positive. Discriminator. This comprises cathode follower double triodes 160, 161, Fig. 4, and diode gates as shown. A positive output at 44 is obtained from coincidence gate 191 or 183 through 160R or 161L. Gate 191 is responsive to positive inputs at 29 and 31, Figs. 1 and 4, and gate 183 to positive inputs at 29, 33, and from 161R which receives the inputs at 35, 37, 39 through " or gate 174. The output at 44 is applied also, with the input at 46, through " or " gate 200 and cathode follower 160L to output 42.