Patent GB-1153025-A (GB)
Title: Electronic Calculator
IPC: G06F3/153
Filed: 1967-07-05
Abstract: 1,153,025. Electronic calculators; memories. LOGICON Inc. 5 July, 1967 [12 Aug., 1966], No. 30929/67. Headings G4A and G4C. Each location of a memory of an electronic calculator may have selectively written therein a word from a word storage register or a word of a fixed set of words associated with the location. The memory may comprise a magnetic core matrix and the fixed set of words may be wired in. As described; an electronic keyboard controlled programmable calculator has three levels of control. At the first (user) level corresponding to the keyboard (Fig; 1), operations (or main programme steps) defined by the keys are performed either as they are keyed in or after they have been stored in a magnetic core store 100 (Figs. 2 and 4). At the second level; I-level instructioncodes (i.e. micro-programme sequences) permanently wired into the same store 100 are retrieved perform each individual main programme step. At the third level, sequences of K-states are generated to perform each individual I-level instruction. Keyboard (Fig. 1).-The keys are divided into three categories. Mode keys 16 enable the calculator to operate for example in a manualmode in which operations are performed as they are commanded, in a sample problem mode in which operations are both stored and executed as they are commanded; in a problem entry mode in which operations are stored only, in a run mode in which operations alreadystored in the store 100 are performed in sequence, in a list mode in which the current operation and the next seven operations in store 100 are displayed on a cathode-ray tube 14, and in a step mode in which a single programme step is performed and the calculator is then returned' to. manual mode. Numerickeys 20 enable numbers-and addresses in the store 100 to be keyed in. Numbers, which are stored in floating point rotation; are keyed-in in the ordermantissa (including- sign and decimal point), exponent to base 10 (including sign), address and finally operation. The addresses which may-be specified (by key 28, followed-by one other key,) comprise fourteen registers (see section on main store) referred to as Z1-Z9 and ZA-ZE. The keyboard corresponds to a further register ZO. Keys 26 and 30 respectively enable two and three zeroes to be entered per key depression. Error key 91 which is illuminated for example when a number is divided by zero must be depressed to reset it. Operation keys 18 enable functions including the following to be specified: the four arithmetic rules, square root, display register, enter number, transfer number, mark instruction (used for programme jumps), jump, conditional jump, clear register and clear store. Main store 100 (Figs. 2 and 4).-This comprises a 16 x 16 x 8 magnetic core matrix for storing 256 bit words. The first 144 words are used for storing various constants, addresses of marked programme steps and operand numbers which are arranged in 16 seven-word registers (two of which are not available to the operator). Each register comprises five words for storing the mantissa in binary coded decimal format (i.e. 10 decimal digits), one word for storing the sign and one word for storing the exponent to base 10 (exponent of zero stored as 50). The last 112 words are used to store user programmes (i.e. corresponding to keyed operations and Z addresses) each word location storing a single programme step. An address selection register M is provided together with inhibit and sense lines 162, 150 respectively. In addition to storing the user programme data as above, store 100 is also threaded by eight banks of inhibit wires 170 whereby permanently stored or wired-in data representing the I-level instructions can be written-in one word at a time (after the user level data has been temporarily transferred elsewhere) for access in the normal way. Special memory 102 (Figs. 2 and 4).-This comprises an 8x8 magnetic core matrix for storing eight bit words of relevance to the I-level instruction sequences. Thus, one word P H  defines one of the eight banks of lines 170 whilst another word P I  defines an address in main memory 100, these two words together representing an I-level programme count. The special memory has its own selection circuit 116 but is threaded by the same sense and inhibit wires 150, 162 as the memory 100. Character memory 103 (Figs. 2 and 4). This comprises a 6 x 8 magnetic core matrix and is threaded by 32 wires corresponding to 32 different characters which may be displayed. After a character from a memory location or register and temporarily stored in stage E1 or an E register 104 has been decoded by means 178, 184 and the corresponding one of the 32 wires energized, the states of the bits comprising the matrix are scanned to control the blanking and unblanking of the C.R.T. beam (Figs. 7 and 8, not shown), the display for each character consisting of a pattern of light spots in a 6 x 8 matrix corresponding to the cores of the storage matrix. The characters in the E-register are shifted so that each character therein may be displayed in turn. The character memory is threaded by the same sense lines 150 as the other memories. Arithmetic and control section (Figs. 2 and 4). -This includes a serial adder 128 connected to the first stages of shift registers M and E and to a carry flip-flop C1, the address selection register M, the E-register which also receives data from and controls writing of data into all three memories, an F register 118 of five bits which holds the current I-level operation code, a K-register 120 of ten bits which defines the current K-store code and is linked to a control unit 124, a C-register 130 of five bits for internal programme use and a clock 126. Operation.-A general K-state sequence which is performed between each I-level instruction controls the following elementary operations: stepping on of the I-level programme count, the temporary transfer of the user level (i.e. variable) contents of the required main memory location into the special memory 102 by way of the E-register, the writing of the wired-in I-level instruction into the cleared main memory location, its reading out into the E- register and subsequent temporary transfer into the special memory 102, the transfer of the variable contents back into the original main memory location (again via E-register), the transfer of the I-level instruction back into the E-register and finally its expansion into an operation code in the F-register and an address (where appropriate) in M-register. Sequences of I-level instructions are provided to perform the various user level programme steps. In particular, in the sequence diagrammatically illustrated in Fig. 5 (not shown), in the absence of keyboard action, the calculator loops through two sequences of operations, one for displaying data or programme steps and the other for testing if keyboard action has occurred. When such action is detected the requested keyboard action is stored, various housekeeping operations performed and the requested action carried out before returning to the original loop. Provision is made for indirect addressing (including multi - level indirect addressing) and repeating of instructions. Complete user level programmes may be wiredin or fed in from punched cards, paper tape or magnetic tape.