Patent GB-1161449-A (GB)
Title: Superconductive Memories
Inventor: GANGE ROBERT ALLEN
IPC: G11C11/44
Filed: 1967-10-18
Abstract: 1,161,449. Superconductive circuits. RADIO CORPORATION OF AMERICA. 18 Oct., 1967, No. 47439/67. Heading H3B. [Also in Division H1] As shown, Fig. 1, a superconductor storage cell comprises a pair of control conductors a, b, a gate conductor 12, 14 having two parallel connected branches 16, 18 forming a loop, and a ground plane 10 which has three apertures 20, 22, 24 underlying parts of the branch 18 of the gate conductor to increase its inductance. The control conductors a, b pass over branch 18 between the apertures 20, 22, 24 and have large widths at these points so that the half-value control currents applied to both of the control conductors drive branch 16 normal but do not affect branch 18. A bit is stored by applying a write current I W  to the gate conductor, this current dividing between the branches, applying half-value control current to both control lines a, b to drive branch 16 normal thus diverting the write current through branch 18, removing the control currents so that branch 16 becomes superconducting trapping the flux due to the write current inside the loop so that when the write current is removed a persistent current Ip circulates round loop 16, 18. The cell is read by applying half-value control currents to conductors a, b to drive branch 16 normal thus forming a resistor across which the persisted current generates a voltage which is detected by the conductors 12, 14. In a first form of memory organization, Fig. 8, thirty-two cells are arranged in eight rows of four cells, the gate conductors of the cells each row are connected in series to form sense lines s 1  to s 8 , the a conductors of the cells of each column are connected in series to form control lines a 1  to a 4  and the b conductors of all the cells are connected in series to form control line b. A particular cell is addressed by applying the write current to the appropriate s line and drive currents to the b line and to the appropriate a line. The location is read by applying the drive currents to the b line and to the appropriate a line and detecting the presence or absence of a voltage across the appropriate s line. In a second form of memory organization, Figs. 9 to 11 (not shown), the cells are arranged in rows and columns and the rows are grouped into sets. The gate conductors of the cells in each row are connected in series to form sense lines and the sense lines of the identically positioned rows of each set are also connected in series. The a lines of the cells of each column are connected in series and the b lines of the cells in each set are connected in series. A particular location can be addressed by energizing the b line corresponding to the set and the a and s lines corresponding to its position within the set. The cells may be located on a plurality of stacked memory planes each of which carries a group of the sets of rows of cells. Two cells may be provided at each memory location to provide a balanced arrangement for the sense lines. The cells may be modified by omitting the b control lines, Fig. 12 (not shown), and such cells may be utilized in a word orientated memory, Fig. 13 (not shown), in which the sense lines of the cells of each row are connected in series as are the control lines of the cells of each column. Energization of a control line enables a complete word to be written into or read out of the cells of the selected column in parallel. Two memory cells may be provided at each location.