Patent GB-1345172-A (GB)
Title: Megnetic core memories
Inventor: KENNER B A
IPC: H03K5/02
Filed: 1971-04-19
Abstract: 1345172 Magnetic storage arrangements ELECTRONIC MEMORIES & MAGNETICS CORP 19 April 1971 [6 April 1970] 26217/71 Heading H3B In a word organized coincident current store, bit line pulses are supplied by a transformer having two anti-phase secondaries. Fig. 1 shows such a store whose operation will be described with reference to the magnetic cores within the dotted lines, the remainder of the store operating similarly. Reading.-Reading is the first part of the memory cycle, and uses bit line pulses from the anti-phase secondary windings of transformer T1 with overlapping pulses on the word lines (not shown). Two rails 10, 11 are connected to respective bit drive lines A1, A2, B1, B2, C1, C2, D1 and D2. To read a word having a bit on line A1 and a bit on line A2, switch 13 is activated to give a positive pulse in the primary of T1, which produces a positive pulse on rail 10 and a negative pulse on rail 11. The positive pulse passes along line Al, and via diode D1 to transformer 12; transistor Q1 has been activated and the pulse passes via transformers 15 and 12 to bit line A2 and to the other secondary. It will be seen that a pulse similarly passes along bit lines B1 and B2, but the A lines and the B lines are on different planes, Fig. 3, and therefore they have separate word lines so that the A lines may be selected. The disposition of word lines is shown in Fig. 3, where it can be seen that word line 24 passes through the first core of line A1 and the last core of line A2, but not through any of the B lines. Rail terminating resistors 20 are provided, as in Fig. 1, and the folded bit lines may also be terminated with resistors 21. The word line current is initiated after the bit line current transients have died away, and the signals produced on a bit line by a switched core are sensed by the appropriate differential amplifier 14, 14<SP>1</SP> and transformer 12, 12<SP>1</SP>. The differential amplifiers are short circuited during the transient phase of the bit line currents by an FET, Fig. 2 (not shown), to avoid signals which would otherwise occur due to imbalance in the lines connected to the sensing transformers. The bit line currents are stabilized by a saturable core transformer T3 whose core is normally saturated by current source 16; the saturating current is opposed by the current in the bit line winding, and when the latter reaches a high enough value the transformer impedance rises rapidly to stabilize the current. Bit lines C and D can be selected by reversing the polarity of the pulses from transformer T1, in conjunction with appropriate choice of word lines. Separate sense lines may be used if desired, in a symmetrical noise cancelling pattern, Fig. 5 (not shown). Writing.-This follows reading. The polarity of the word line pulses and of the pulses from transformer T1 is opposite that of the reading step, so that to write a "1" in bit lines A1 and A2 the appropriate word line is pulsed and also a negative pulse is applied to transformer T 1 by the bipolar switch 13. The negative pulse passes along rail 10, down lines A1 and B1, through balun 19, current stabilizing transformer T3<SP>1</SP> and transistor switch Q5. Simultaneously a positive pulse passes from rail 11, through lines A2 and B2, balun 19<SP>1</SP>, transformer T3<SP>11</SP> and transistor Q6. To write a "0", the appropriate transistor Q5 or Q6 is not activated. The arrangement of Fig. 3 shows that a given word line such as 24 serves two words, e.g. during reading the word having its bits on the A lines is read when the current in line 24 is of one polarity, while the word having its bits on the C lines is read when the current in line 24 is reversed. The word line current polarity will similarly determine whether the A word or the C word is written into, so that word line current polarity is a selection co-ordinate. Bipolar voltage switch.-Fig. 4 shows a transistor array and a diode selection matrix 30 for supplying current of a desired polarity to the transformers T1 &c., a split power supply of +V, O and - V is used. If transistors Q12  and Q15 are activated, a pulse of one polarity is passed through the primary of T1, while if Q13 and Q14 are activated a pulse of opposite polarity is passed. Once the pulse amplitude reaches a given value, transistor Q11 is switched off to halve the power supply, diode D17 providing a current return path.