baber/WOPTO huggingface dataset:
Patent JP-H0671322-A (JP)
Title: Construction for hot slab carrier
Inventor: OKAMOTO HIROSHI
IPC: B21B39/00
Filed: 1992-08-27
Abstract: PURPOSE:To reduce the amount of dissipated heat from a slab and to improve the charging temperature in a heating furnace by constructing a double doors and interlocking driving devices for upper and lower doors so as to interlockingly drive the upper and lower doors to open and close. CONSTITUTION:The temperature reduction of the slab 9 mounted on a carrier 1 is restrained by a heat retaining chamber 3. The upper door 4 through which the hot slab 9 is charged and discharged and the lower door 10 in which an extractor used for charging and discharging the slab is inserted are provided on one side face of the heat retaining chamber 3 as a double doors. The driving device 6 for the upper door is arranged on the roof of the heat retaining chamber 3 and the driving device 11 for the lower door is arranged on the lower side beam of the carrier 1 respectively. Both of driving devices 6 and 11 are interlocked to open and close the doors 4 and 10. Thus, a continuous casting process and a rolling process is continued.
Patent JP-H1165663-A (JP)
Title: Position controller and method therefor
Inventor: KATO KOICHI
IPC: G05B19/4103
Filed: 1997-08-25
Abstract: PROBLEM TO BE SOLVED: To provide a position controller for correcting a position error, with respect to a target position generated in a direction, except for a control axial direction at the time of the reversal of the feeding direction of each control axial direction. SOLUTION: This position controller is provided with servo control parts 12-14, servo drivers 15-17, and servo motors 18-20 as position controlling means for operating the position control of a controlled object having plural control axes, and position correcting parts 4-6 for operating the correction of the position error of another control axial direction at the time of the reversal of the feeding direction of one control axis among the plural control axes, and for concurrently operating the correction of the position errors of another control axial direction and one control axial direction at the time of the reversal of the feeding direction of one control axis.
Patent JP-S59118116-A (JP)
Inventor: YURA MASAKI
IPC: A47J19/00
Filed: 1982-12-25
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S59118123-A (JP)
Inventor: YOKOYAMA TOSHIYUKI
IPC: G04F3/06
Filed: 1982-12-25
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0277769-A (JP)
Title: Bicolor image forming device
Inventor: KOBAYASHI TATSUYA
IPC: G03G15/01
Filed: 1988-09-14
Abstract: PURPOSE:To eliminate trouble which is caused by magnetic carriers and to form an excellent image by coating a developer carrier with a sufficient amount of toner which has proper triboelectricity in a two-component developing device, and securely controlling magnetic carriers which have larger size than the toner by a regulating member and preventing them from leaking. CONSTITUTION:In the developing device 40, carriers 48 carried on the peripheral surface of a developing sleeve 41 are conveyed as shown in a direction B while the peripheral surface of a developing sleeve 42 is coated with stuck toner 49 as the developing sleeve 41 rotates. Then the magnetic force of a magnet 45 is weakened gradually and there is no magnetic force on the upstream side of a development area 10 at the abutting position of a blade 42 on the upper peripheral surface of the developing sleeve 41, so that the blade 42 securely controls the carriers 48 which become easy to separate and prevents them from leaking. Further, the separated carriers 48 fall on the bottom part of a hopper 47 and circulated as shown by an arrow C. Consequently, the toner 49 is supplied and replaced at all times, so the amount and triboelectricity of the toner 49 are secured properly by friction and the toner is applied onto the sleeve 41.
Patent JP-S60120448-A (JP)
Title: Data processing system
Inventor: TAKEI MASAHIRO
IPC: G06F3/06
Filed: 1983-12-02
Abstract: PURPOSE:To prevent invalidation of data caused by mistakes in writing addresses as far as possible and, at the same time, to perform stable transmission of data and correction of erroneous data after transmission, by selecting either the address data at the time of writing in a memory or the output data of an address counter in accordance with a code error detecting means. CONSTITUTION:A data selector 29 selects based on the output of a control circuit 28 whether it determines the write address of 70-word data to an RAM30 in accordance with the output of an internal counter 24 or in accordance with address data sampled at an address sampling circuit 26. Since it is risky to use the address data sampled at the address sampling circuit 26 when the check output of a CRCC (Cyclic Redundancy Check Code) is one corresponding to ''error'', the output of the internal counter 24 is used. By determining the writing address to the RAM30 in accordance with an address value selectively outputted by the selector 29 in such a way, the writing address to the RAM30 can be determined correctly.
Patent JP-S61107894-A (JP)
Title: Information signal recording disk
Inventor: SUGIYAMA HIROYUKI
IPC: H04N9/80
Filed: 1984-10-30
Abstract: PURPOSE:To prevent the deterioration of color reproducibility by thinning out and transmitting to one field the picture element data for one frame which separately samples and quantizes a luminance signal and two kinds of color difference signals and recording them in the sequence of surfaces. CONSTITUTION:At one track for one rotation of an information signal recording disk 1, respective picture element data concerning one static picture are recorded, and after luminance picture element data Y1 and Y2 out of the data sample a luminance signal for one frame, they consist of one remaining field which thins out one field out of picture element data obtained by quantizing. Transmission is executed at the same frequency as the sampling frequency after thinning-out, two kinds of color difference picture element data (R-Y)1, (R-Y)2, (B-Y)1 and (B-Y)2 respectively consist of one remaining field obtained by quantizing after color difference signals R-Y and B-Y for one frame are separately sampled, and transmitted at the frequency two times as much as the sampling frequency after thinning-out.
Patent JP-H0974139-A (JP)
Title: Semiconductor integrated circuit and the layout and wiring methods thereof
Inventor: KISHIDA TAKESHI
IPC: G06F17/50
Filed: 1995-09-06
Abstract: PROBLEM TO BE SOLVED: To realize the cut-down of the layout area of semiconductor circuits in relation to their layout and wiring methods, by cutting down through the cross-over of contacts wiring disabling regions generated in the vicinity of a macro-block. SOLUTION: Layout and wiring methods for semiconductor integrated circuits comprise a first processing for determining the layout positions of the configurational blocks of semiconductor circuits (L1), a second processing for altering the layout directions of their macro-blocks (L2), a third processing for so selecting a macro-block with a different pin layer attribution from the wiring layer attribution of its power supply and grounding wirings as to cut down wiring ineffective regions generated in the vicinity of the macro-block (L3), a fourth processing for executing inter-block wirings (L4), and a fifth processing for examining the presence of any wiring ineffective region (L5).
Patent JP-H0198439-A (JP)
Title: Separator
Inventor: WARUTAA BUI KAKUZEUSUKII
IPC: A22C17/04
Filed: 1988-09-14
Abstract: PURPOSE: To improve the efficiency of separation by vibrating the supporting roller of a belt in a device provided with a rotary pored drum and the belt for separating fish meat from the bones and skin. CONSTITUTION: In this separator composed by supporting an elastic belt 5 by a pressurization roller 6, a turning rollers 7 and 8 and a supporting roller 10 and bringing it in press contact with a part around the rotary pored drum 3 for which many through-holes 17 are pierced on a peripheral surface, the turning roller 7 on the upstream of a holding part 9 formed by the rotary pored drum 3 and the elastic belt 5 is rhythmically displaced.
Patent JP-H1066883-A (JP)
Title: Apparatus for preventing duplicate charge of rice in rice washing apparatus
Inventor: MIHIRA KEIICHI
IPC: A23L7/10
Filed: 1996-08-29
Abstract: PROBLEM TO BE SOLVED: To prevent the erroneous double charge of rice by providing a locking means for locking a lid and locking the lid by the locking means after the start of operation in an apparatus in which a prescribed quantity of rice charged from a rice inlet which is closed freely/closably by the lid is washed automatically. SOLUTION: In an automatic rice washing machine 1, a receiving case 3 is fixed in the upper part of a frame 2, and a rice washing tank 4 is fixed on the lower surface of the case 3. A rice inlet 9 is opened in the upper surface of the case 3, and the inlet 9 is closed by a lid 8. A locking means 11 which locks/releases the lid 8 is provided, and a lid opening/closing detection means 12 is attached to the periphery of the inlet 9. When operation is started, the detection means 12 judges whether the lid 8 is closed or not, and when the lid 8 is closed, the locking means 11 is actuated to lock the lid 8. After the lid 8 being locked, the locking is kept until the end of a rice washing process to prevent the double charge of rice.
Patent JP-H0398801-A (JP)
Title: Apparatus for bagging grain
Inventor: HAMAYA KOJI
IPC: B65B1/36
Filed: 1989-09-04
Abstract: PURPOSE:To take out a container bag without spilling grain with rapid operation by providing an interlocking device with a flexible mechanism for raising a discharge cylinder delayed from closing operation of a shutter. CONSTITUTION:A discharge cylinder 2 for discharging grain into a grain container bag 3 is formed vertically stretchable, and an interlocking device A for raising the lower end of the discharge cylinder 2 along with closing operation of a shutter 5 which is manually opened and closed is provided between the shutter 5 and the above discharge cylinder 2. Further a flexible mechanism B for raising the discharge cylinder 2 delayed from the closing operation of the shutter 5 is provide on the interlocking device A. When the shutter 5 is closed during grain discharge, the grain discharge cylinder 2 is shut by the shutter 5 accordingly. On the other hand, the discharge cylinder 2 is delayed from closing of the shutter 5 by the interlocking device A and the flexible mechanism B provided thereon, that is, after the shutter 5 has been transferred by a specific distance, the lower end of the cylinder 2 is raised interlocked with the shutter 5. Thus the container bag 3 can be taken out without spilling the grain.
Patent JP-S61107591-A (JP)
Title: Memory select control circuit
Inventor: NAKAMURA NOBUTAKA
IPC: G11C8/00
Filed: 1984-10-31
Abstract: PURPOSE:To cope with the change of a memory structure without changing the hardware configuration by setting a chip select signal to be supplied programmably to the ROM/RAM memory. CONSTITUTION:Output from comparator 14 holds '1' for upper 4 bits in an address bus 3 from 0 through 3, and holds '0' when the address bus 3 is in a range from 4 through F. Therefore, a chip select signal CS0 holds '1' when the upper 4 bits of the address bus 3 are in a range from the bit 0 through the bit 3 and holds '0' when the upper 4 bits of the address bus 3 are in a range from the bit 4 through a bit F. A RAM5 is accessed while a chip select signal CS0 holds '1', or when the address bus 3 is in a range from '00000' (HEX) to '3FFFF' (HEX). The output from a comparator 15 holds '1' when the upper 4 bits of the address bus 3 are in a range from 0 to 7, and holds '0' for a range from 8 to F. As a chip select signal CS1 is the output from gate 19, the signal CS1 holds '1' when an output from a comparator 14 holds '0' and an output from comparator 15 holds '1', that is, when the upper 4 bits of the address bus 3 are in a range from 4 to 7.
Patent JP-H0567748-A (JP)
Title: Manufacture of semiconductor memory element
Inventor: NIIMURA NAOYUKI
IPC: H01L27/10
Filed: 1991-09-09
Abstract: PURPOSE:To easily form a connection part to connect a main part to a peripheral part regardless of etching speed by using a thin polycrystalline Si film remaining on the part of a valley between mutual ground wirings at the time of etching. CONSTITUTION:A polycrystalline Si film is etched until the polycrystalline Si film on the part of a gate wiring 3 is removed while using an SiO2 film as a mask in order to form a main part 8. Owing to a local film thickness difference of the polycrystalline Si film, a thin polycrystalline Si film 9 remains unetched in parallel with the gate wiring 5 in the region of a valley. This remaining polycrystalline Si film 9 becomes a connection part. In this way, etching can be stopped at a point of time where a thin part of a polycrystalline Si film thickness completely removed owing to a decrease in a reaction product at the time of etching owing to a decrease in an etched area. Accordingly, a connection part connecting a main part to a peripheral part can be easily formed.
Patent JP-S6383790-A (JP)
Inventor: ISHII TAKATOSHI
IPC: G09G5/00
Filed: 1986-09-27
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0661596-A (JP)
Title: Manufacture of board for high frequency circuit
Inventor: KABUMOTO AKIRA
IPC: H05K1/03
Filed: 1992-08-05
Abstract: PURPOSE:To obtain a manufacturing method of a board for a high frequency circuit having high adhesive strength between a conductor layer and an insulating substrate while little lowering in close adhesive strength after heating deterioration test. CONSTITUTION:In a manufacturing method of a board for a high frequency circuit where a conductor layer is lamination-formed at least on one side of an insulating board, a plastic foamed substance having an average foam diameter not exceeding 20mum and a foam rate 80% or more and an unfoamed surface layer is removed is used as an insulating board in order to lamination-form a conductor layer on the surface in which the unfoaming surface layer of a plastic foamed body sheet removed by vapor deposition or sputtering. In this way, a board for a high frequency circuit having the high adhesion strength between the conductor layer and the insulating substrate with little lowering in the adhesive strength even after a heating deterioration test and high reliability.
Patent JP-S6381481-A (JP)
Title: Photosensitive body
Inventor: IINO SHUJI
IPC: G03G5/08
Filed: 1986-09-26
Abstract: PURPOSE:To provide adequate transferability and excellent photoconductivity to the titled photosensitive body by using a hydrogenated amorphous carbon film contg. either of phosphorus atoms or boron atoms to form an electric charge transfer layer and using a hydrogenated or fluorinated amorphous silicon germanium film contg. either of phosphorus atoms or boron atoms to form an electric charge generating layer. CONSTITUTION:This function sepn. type photosensitive body having the charge generating layer 3 and the charge transfer layer 2 is provided with the hydrogenated amorphous carbon film which is formed by glow discharge and the into which at least either of the phosphorus atoms or boron atoms are incorporated as the charge transfer layer 2 and the hydrogenated or fluorinated amorphous silicon germanium film which is likewise formed by the glow discharge and into which at least either of the phosphorus atoms or boron atoms are incorporated as the charge generating layer 3. High dark resistance and excellent electric charge transferability are thereby provided to the charge transfer layer 2 so that said layer can make contribution to bright attenuation. The carriers generated in the formed film are efficiently implanted into the charge generating layer 3 in the lamination constitution with the charge transfer layer 2 so that said layer can make adequate contribution to the bright attenuation.
Patent JP-H1167910-A (JP)
Title: Semiconductor device and its manufacture
Inventor: AMANUMA KAZUSHI
IPC: H01L27/105
Filed: 1997-08-26
Abstract: PROBLEM TO BE SOLVED: To easily form a wiring contact for each circuit block and a wiring between the blocks and prevent the increase of contact resistance and the deterioration of capacity insulating film, by forming a wiring layer which is electrically bonded with a diffusion layer on an interlayer insulating film which is etched back for each circuit block. SOLUTION: A capacity element block 31 and a logical circuit block 32 are integrated on the same semiconductor substrate 1, and the second interlayer insulating film 10 and the first interlayer insulating film 6 of the logical circuit block 32 are etched back. As the aspect ratio of the contact of the logical circuit block 32 is equivalent to that without capacity element, a contact wiring can be easily formed and the increase of the contact resistance is suppressed. Therefore, as the contact resistance reduces, circuit operation characteristics such as delay are improved, and the contact wiring can be formed without deteriorating the capacity characteristics, even when an oxide such as a high dielectric constant material is used as the capacity element.
Patent JP-H1071987-A (JP)
Title: Hydrofoil
Inventor: KUNIHARA KAZUO
IPC: B63B1/24
Filed: 1996-08-30
Abstract: PROBLEM TO BE SOLVED: To provide a hydrofoil lightweight and high in strength. SOLUTION: A blade body 4 of a hydrofoil 3 is formed of a plurality of cylindrical tube bodies 5 arranged parallelly in a hull length direction L with both ends facing a hull width direction, and aluminium joint materials 6 jointed to the peripheral surface of the adjacent tube bodies 5 so as to fill clearances between the respective tube bodies 5. The tube body 5 is composed of a tube 9 with compressed air filled inside, and aramid fiber material 10 covering the peripheral surface of the tube 9. The outer surface of the blade body 4 is covered with reinforced plastic material 17.
Patent JP-S61106800-A (JP)
Title: Manufacture of zinc compound one side electroplating steel plate
Inventor: ISHITOBI HIROTAKE
IPC: C25F1/06
Filed: 1984-10-31
Abstract: PURPOSE:To obtain a one side plating steel plate having a non-plating surface which is excellent in its chemical conversion treating property by performing a zinc compound electroplating to one side, and thereafter, washing a non-plating surface, and executing an anodic oxidation in a water solution containing sulfate or phosphate of a specified metal. CONSTITUTION:A zinc compound electroplating is performed to one side of a steel plate, and thereafter, a non-plating surface is washed, and dried temporarily. Subsequently, a water solution which contains one kind or more of sulfate or phosphate of Na, D, Li, Mg and Al, and whose pH is 1-4 is adjusted. In this water solution, an anodic treatment is executed by setting a relative speed of the steel plate and the liquid, and an anodic current density to <=2.5m/sec and >=20A/dm<2>, respectively, and impurities which have been precipitated by a very small quantity on the non-plating surface are removed. Subsequently, the non-plating surface is polished as necessary. According to this method, a chemical conversion treating property of the non-plating surface in a zinc compound one side electroplating steel plate can be improved by a treatment over a short period.
Patent JP-H1167940-A (JP)
Title: Nonvolatile semiconductor storage device and manufacture thereof
Inventor: OTANI TOSHIHARU
IPC: H01L27/115
Filed: 1997-08-26
Abstract: PROBLEM TO BE SOLVED: To suppress trap sites from being formed to improve the data hold characteristics and yield and elongate the life, by making the concn. of an impurity for doping a floating gate low at an upper and lower layers of the floating gate and high at a central layer. SOLUTION: A floating gate 9 extending to a source region 15 through a gate insulation film 12 is formed on a part of a channel region 17 by adding an impurity in an Si film and its concn. is high at a central layer 4 and low at an upper and lower layers 5, 3. A control gate 14 extending to a part of a drain region 16 is formed, covering the top and side of the floating gate 9 through a tunnel insulation film 11 and selective oxidation film 8. As the part facing the control gate 14 has a low impurity concn., the impurity hardly segregates in the tunnel insulation film 11 near protrusions 9a.
Patent JP-H0277114-A (JP)
Title: Epitaxial growth method
Inventor: AKIMOTO KATSUHIRO
IPC: H01L21/365
Filed: 1988-09-13
Abstract: PURPOSE:To epitaxially grow a semiconductor layer which has low point defect density and is excellent in quality by irradiating the surface and/or its vicinity of a semiconductor substrate with an electron beam, during epitaxial growth. CONSTITUTION:A conductive GaAs substrate 2 of N-type or P-type is arranged in an MBE equipment 1 kept at a high vacuum. The GaAs substrate 2 is irradiated with molecular beams of Zn, Se and dopant generated from Knudsen cells C1, C2, C3 constituting respectively evaporation sources of Zn, Se and dopant, and ZnSe is epitaxially grown. During the epitaxial growth, the whole surface of the GaAs substrate 2 is irradiated, from the direction oblique to the surface, with an electron beam 4 generated from an electron gun 5 fixed to the MBE equipment 1, thereby growing a ZnSe epitaxial layer 5 which has low point- defect density and excellent in quality. Roughness of the surfaces of the GaAs substrate 2 and the ZnSe epitaxial layer 5, and the change of growth rate are not recognized.
Patent JP-S6473819-A (JP)
Title: Logic circuit
Inventor: TAKAHASHI KATSUHIKO
IPC: H03K19/088
Filed: 1987-09-16
Abstract: PURPOSE:To expedite the drawing start time of a Miller current, to accelerate the rise-up of an output logic signal, and to reduce power consumption and an output noise, by reducing a transmission path remarkably until the drawing of the Miller current is started after the logic state of an input logic is switched. CONSTITUTION:A Miller-killer circuit 4 consisting of an npn bipolar transistor Q7, a pnp bipolar transistor Q8, a resistor R9, and diodes D7, D10, D11, and D12 is provided. A logic signal VIN inputted to the input circuit 1 of the logic circuit is phase-inverted at the Q8, and the drawing of the Miller current that flows from the collector side of a bipolar transistor Q3 connected to a low side power source potential side in the output circuit 3 via a Miller capacitance C3 is performed by the Q7 energized and driven by the phase-inverted signal. By constituting a circuit in such way, the transmission path until the drawing of the Miller current is started after the logic state of the input logic signal VIN is switched from an H to an L is only the Q8 and the Q7, thereby, it is reduced remarkably.
Patent JP-S6287385-A (JP)
Title: Thermal recording paper
Inventor: TAMAGAWA SHIGEHISA
IPC: B41M5/40
Filed: 1985-10-15
Abstract: PURPOSE:To provide a thermal recording paper having favorable dot reproduction properties and a high recorded density, by using a base obtained by providing an intermediate layer comprising a white pigment on a raw paper comprising a polyolefin synthetic pulp. CONSTITUTION:A synthetic pulp to be used is a pulp obtained by extruding a thermoplastic resin and subjecting the extrudate to opening by one of various methods, a pulp obtained by exerting a shearing force on an olefin in the presence of a Ziegler catalyst to form a fibrous material, or the like. A polymer to be used is preferably a polyolefin such as polyethylene and polypropylene. The length of fibers is preferably 0.5-1.5mm. The density of a raw paper obtained by blending the synthetic pulp is preferably 0.8-1.0g/cm<3>. If the density is below the range, smoothness is low, and the effect of the synthetic pulp is low. A white pigment used in an intermediate layer may be an inorganic pigment such as kaolin, fired kaolin, talc and calcium carbonate or an organic pigment such as a urea-formaldehyde resin and an acrylic resin. The coating amount of the intermediate layer is 1-10g/m<2>, preferably, 3-7g/m<2>. If the coating amount is below the range,a high recorded density can not be obtained.