Patent GB-1380664-A (GB)
Title: Decoder of retrospective pulse modulated information
IPC: G06K7/016
Filed: 1973-07-03
Abstract: 1380664 Decoding retrospective pulse coded information INTERNATIONAL BUSINESS MACHINES CORP 3 July 1973 [31 July 1972] 31688/73 Heading G4C  Decoding of retrospective pulse coded information represented as serial electric pulses derived by sensing for example optically printed lines or bars 26 (Fig. 2), raised or depressed surfaces or magnetic transitions is effected by establishing a first count at a frequency f/N during the interval between the sensing of first and second marks, a second count at a frequency f being effected in the interval between the second and third marks, an indication of the value of the sensed bit being given in dependence on the relative lengths of the intervals. As described, pulses at a frequency f/N are fed on line 359 to counter 41, the count being transferred by AND gate 51 to register 53 and the counter reset each time a mark is sensed by a probe 27. The ones complement of the count in register 53, which is reset by a signal on line 392 before transfer of data occurs, is fed into a second counter 65 each time a mark is sensed and each time the counter end carries, the counter being stepped at a frequency f. End carries are counted in a further counter 81 which will consequently have a count of approximately N if the intervals between the first and second marks and second and third marks are the same. Counter 81 is designed to provide an output at node 82 if its count exceeds 1À5 N (a long mark being represented by twice the spacing of a short mark), and no output otherwise. Signals at node 82 are also fed via AND gate 55 to register 53 to divide its contents by two. Consequently if a long space follows a long space the counter 65 will again end carry in excess of 1À5 times so that counter 81 will again give an output. Circuit 90 receiving the output signals from counter 81 compares the presence or absence of an output with a stored signal representing the previous interval, a signal being fed on line 91 when successive intervals are alike. Control circuitry for pulsing the counters and resetting the register and counters comprises a binary decimal decoder (364, Fig. 3, not shown) which provides outputs successively on two of its lines (399, 400) when no input data is present but provides signals on each of its output lines (391-400) in turn for each sensed mark. The signals result in the following sequence of operation: (1) register 50 is reset; (2) AND gate 51 is enabled; (3) AND gate 55 is primed; (4) counters 65, 81 are reset; (5) counter 41 is reset and OR gate 66 is enabled to enable AND gate 63 and (6) the data output circuit is reset. Circuit 90 includes a first bi-stable (928, Fig. 4, not shown) set by a signal from carry counter 81 and a first AND gate (922) which is primed by one of the output leads (392) of the decoder and enabled by the simultaneous application of a signal from carry counter 81 and the set output of the first bi-stable (928) (that is when two long intervals follow each other). In a similar manner a second AND gate (934) is enabled by the reset output of the first bi-stable (928) and the inverted signal on line 84 (that is when two short intervals follow each other). In either case a second bi-stable (936) is set.