Patent GB-1107963-A (GB)
Title: Binary sequence detector circuit
IPC: H03K17/73
Filed: 1966-03-17
Abstract: 1,107,963. Binary sequence detecting circuits. AMP Inc. 17 March, 1966 [1 April, 1965], No. 11637/66. Heading G4H. A circuit for detecting a given sequence of binary digits comprises a magnetic core shift register having a series of sequentially arranged digit positions each having a set and a clear state of magnetic remanence, drive windings energizable to drive the cores of the register to advance a digit stored in the register in response to the occurrence of binary digit signals at a signal source, and a circuit for automatically setting the first digit position in the sequence prior to the occurrence of each of the Binary digit signals at the source, the drive windings' being coupled to the cores in a pattern corresponding to the sequence of binary digits to be detected in such a way that the set state of the first digit position is transferred to the last digit position only in response to the occurrence of the given sequence of binary digits at the source. The shift register preferably consists of multi-aperture magnetic cores as disclosed in Specification 1,027,133, transfer of binary 1 digits applied to stage one prior to receipt of each input signal digit (whether 1 or 0) being controlled by two sets of windings selectively, linking the cores, one set being energized on receipt of binary 0 digits and the other being energized on receipt of binary 1 digits. A 1-bit is emitted from the last stage of the detecting circuit if and only if a predetermined pattern of bits is received thereby. The magnetic cores (Fig. 1), after being set either by a signal' on input winding 10 (in the case of the first core 1A) or by a signal on a transfer winding 20, 22, 24 &c. need to be primed by a signal on winding 18 linking all cores before the binary digit (1) represented by said set state can be transferred to the next core by a clear signal on windings 1A (for the A cores) or 1B (for the B cores). Other windings are provided for avoiding interference between the different signals and assisting the transfer. In a first embodiment (Figs. 3-6, not shown) relating to a twelve digit word detector, windings 10<SP>1</SP>, 10<SP>11</SP> are provided in opposition to the clearing windings 30<SP>1</SP>. Windings 30<SP>1</SP> which link all cores are energized at the beginning of each word (to clear the register) and also on receipt of each signal digit whether 1 or 0. Windings 10<SP>1</SP> are energized whenever a binary 1 digit is received and 10<SP>11</SP> whenever an 0 is received. The linking of the windings 10<SP>1</SP>, 10<SP>11</SP> selectively with the cores (as indicated in Fig. 4, not shown) determines the given sequence which will be detected, a binary 1 being emitted from the last stage only if the given sequence has occurred. The drive circuit for the detector (Fig. 6, not shown) includes input 60, for D.C. supply, input 62 for setting the first core and for clearing pulses, input 64 for receipt of pulses to indicate occurrence of a binary 1 digit and input 66 for receipt of pulses to indicate occurrence of a binary 0 digit. Signals on any one of inputs 62, 64 or 66 cause a capacitor C5 to be charged through the corresponding windings of the shift register X followed by discharge of this capacitor through the then conducting transistors Q 1 , Q 2  to provide the priming pulses through windings 18<SP>1</SP> necessary to prepare the detector for the next digit. In a second embodiment (Figs. 7-10, not shown), relating to a sixteen digit code stream detector, a delay circuit including elements C9, Q3, T11 (Fig. 10-not shown) is provided whereby for each received digit the condenser C5 is charged twice. At the first charging, all the odd cores receive clearing signals (on winding 103) whereas only selected even cores receive clearing signals (on windings 101 or 100) depending on whether the received digit was binary 0 (input 74) or binary 1 (input 72). Transfer of digits from odd cores to even cores is thus prevented in those cases where the even cores receive clearing pulse. At the second charging (following priming of all cores during discharge of capacitor C5 through windings 106) all the even cores receive clearing pulses on windings 104 and those digits which survived the first transfer are transferred on to the next odd core. A digit is emitted at the outlet of the last core only if a given sequence of digits corresponding to the wiring of windings 100, 101, has occurred. The registers may be. mounted on printed circuit panels (Figs. 5 and 9-not shown) with posts 54, 56, 72 for soldering the windings to and contact pads 52, 76 along the panel edges.