Patent EP-1333564-A3 (EP)
Inventor: VINCIARELLI PATRIZIO
IPC: H02M3/335
Filed: 2003-01-31
Abstract: A Factorized Power Architecture ("FPA") method and apparatus includes a front
end power regulator which provides one or more controlled DC bus voltages which are
distributed through the system and converted to the desired load voltages using one or
more DC voltage transformation modules ("VTMs") at the point of load. VTMs convert
the DC bus voltage to the DC voltage required by the load using a fixed transformation
ratio and with a low output resistance. VTMs exhibit high power density, efficiency and,
owing to their inherent simplicity and component utilization, reliability. VTMs may be
paralleled and share power without dedicated protocol and control interfaces, supporting
scalability and fault tolerance. Feedback may be provided from a feedback controller at
the point of load to the front end or to upstream, on-board power regulator modules
("PRMs") to achieve precise regulation. 
     In a preferred embodiment, a Sine Amplitude Converter ("SAC") method and
apparatus for VTMs converts a DC input voltage to a DC output voltage using a fixed
transformation ratio at a frequency locked to a resonance. The SAC uses a resonant circuit
including a transformer and complementary primary switches operating with balanced
switching and a high power conversion duty cycle ( e.g. , above 94%) to perform high
frequency, low noise, single stage power processing. The resonant circuit may have a low
Q while enhancing conversion efficiency. The SAC may be operated with primary ZVS
and secondary ZVS and ZCS. Controlled current slew rates enable ZVS and ZCS
operation of synchronous rectifiers at frequencies greater than 1 MHz, contributing to
efficiency and power density. Low-loss, common-source gate-control topologies may be
used to efficiently drive a multiplicity of switches at frequencies greater than 1 MHz.
Cancellation of the impedances of the resonant circuit at resonance coupled with a low Q
enable high bandwidth performance to address the fast transient load characteristics of
microprocessors, particularly in the absence of other serial impedances (i.e. input and
output filter inductors), which are unnecessary owing to the low differential-mode noise
characteristics of SACs. Common-mode noise may be effectively reduced using
symmetrical resonant power trains. 
     In a preferred embodiment, a low profile (< 0.16 inch high), low permeability 
"dog's bones" core structure, integrated with multi-layer PCB windings to complete SAC
transformers, gives rise to a VTM manufacturing platform with greater than 400
Watts/cubic-inch power density and 95% efficiency, converting 100-150 Watts at the point
of load. Capable of low manufacturing costs, this enabling technology supports flexible,
molded packages for VTMs, which are characteristic of large IC's or "System In a
Package" ("SIP") devices, as distinct from the standard "bricks" characteristic of the DC-DC
converters, the workhorses of vintage Distributed Power Architecture ("DPA"). 
     In a preferred embodiment, modulation control circuitry modulates the output
resistance of a converter to control V out , limit I out , or improve current sharing. Gate drive
circuitry for delivering a unipolar voltage using a transformer recycles energy between the
magnetizing inductance of the transformer and parasitic capacitances of the switch
circuitry. Integrated dual drain FETs enable essentially simultaneous switching of clamp
and switch circuitry particularly advantageous in gate drive and synchronous rectifier
applications. A DC-DC converter may include a non-isolated power converter, preferably
a ZVS buck-boost converter, followed by a DC-DC transformer, preferably a SAC.