Patent GB-1213031-A (GB)
Title: Improvements in or relating to synchronizing circuits for interconnected control centres of communications systems
Inventor: INOSE HIROSHI
IPC: H04J3/06
Filed: 1968-02-06
Abstract: 1,213,031. Multiplex pulse code signalling. WESTERN ELECTRIC CO. Inc. 6 Feb., 1968 [10 Feb., 1967], No. 5792/68. Addition to 1,184,108. Heading H4L. The synchronizing arrangement for a time division multipkx communication system comprising a plurality of interconnected control centres disclosed in the parent Specification, in which means at each centre compare the phase of incoming synchronizing signals from a remote centre with the phase of locally generated synchronizing signals to adjust the phase of the locally generated clock signals, is modified to enable each centre to transmit back to the remote centre or centres information indicating the phase error, and means at each centre sums the output of the associated phase comparator with the received phase error signal to control the phase of the signals at that centre. As described a frame consists of 24 time slots S1 to S24 each time slot containing eight bits B1 to B8, and a single time slot S3 of one bit length. Each bit interval is divided into four phases #1 to #4. The signals are coded in P.C.M. form and the first time slot in each frame is reserved for the frame sync. signal. General description, Fig. 4.-Centre A receives signals from centre B via three time division multiplex highways 470, 471, 472 one of which, 470, carries the frame sync. signal. The sync. signal is detected in S1 B8, #2, at 410 and supplied to a phase comparator 201, e.g. as a "reset" input to a bi-stable device. The "set" input is the framing pulse from time slot counter 205 controlled by the clock generator 204 which is applied to the comparator 180 degrees out of phase with the incoming framing signal so that any output from the comparator of direction more or less than a half-frame interval constitutes a phase error. This output is combined with the outputs of any other phase comparators at centre A in a weighted averaging circuit 202 to adjust the phase of generator 204. The bit frequency is also aligned by a comparison at 451 of the bit frequency output of counter 205 with the incoming bit frequency supplied via line 470 and a variable delay 450 the output of the comparator adjusting the delay accordingly. Inputs 471, 472 are similarly corrected and the output signals on lines 460, 461, 462 supplied to the switching network. Finally, in order to compensate for fluctuations in delay when the highway between A and B is relatively long, the input delay servo 403 is provided which receives the error signal from comparator 201, combines it with a similar signal received via line 470 from centre B and provides an output to adjust variable delays 402, 481, 482 accordingly. Control circuit 403, Fig. 6.-Phase comparator 201 supplies a signal to AND gate 601 which extends approximately over a half frame, dependent upon the phase error, and a clock signal at phase #3 of each bit interval is also supplied to the AND gate. A counter 603 converts the output of gate 601 to binary form during each frame period which is registered at 605 and read out in time slot S2 via gate 604 for transmission to centre B via line 480. A corresponding binary signal from centre B is supplied via variable delay 402, fixed delay 401 and AND gate 610, enabled at time slot S2, to the shift register 615. The information stored at 605 and 615 is converted into analogue form at 606, 616 respectively and added at 620, the resultant signal being supplied via lead 621 to adjust the delay 402. The delay 402 may take the form of a chain of monostable devices or a mechanically controlled magnetostrictive delay line, Figs. 7 to 10 (not shown).