Patent GB-1111960-A (GB)
Title: Data processing machine
IPC: G06F7/52
Filed: 1966-08-24
Abstract: 1,111,960. Digital calculating. INTERNATIONAL BUSINESS MACHINES CORPORATION. 24 Aug., 1966 [24 Sept., 1965], No. 37916/66. Heading G4A. In a data processing machine, the position of the fractional point in the result of an arithmetic operation on two numbers is calculated and stored before the operation is performed, the result and point being displayed. An electronic desk calculator comprises a keyboard with keys for 0-9, decimal point, enter, add, subtract, multiply and divide; three magnetic core registers (input, result and multiply-divide) each with capacity for twenty decimal digits in binary-coded form, each decimal digit stage having a fifth core to indicate a decimal point if present at the stage; a serial-by-bit binary-coded-decimal adder-subtractor; and a CRT display for the result (including decimal point). The operator keys in the first operand, high order first, each digit being entered into the low end of the input register and shifted along when the next digit is entered. The operator then presses the " enter " key which causes the first operand to be read serially-by-bit from the input register and placed in corresponding positions in both the result register and the input register again. The second operand is now entered, the input register being cleared in preparation for it on keying of the first digit (or decimal point). If the operator does not enter a decimal point for a given operand, the machine automatically inserts it at the end of the operand. More significant figures can be obtained by keying in zeros, since each digit keyed in causes shift in the input register. Prior to an arithmetic operation, the position of the decimal point in the result register is altered to be correct for the result (see below) and then ignored during the arithmetic operation. Further registers are provided. Features peculiar to addition and subtraction.- The decimal points of the two operands (in the input and result registers) are aligned by testing successive stages of the two registers alternately to determine in which register the decimal point first appears, then shifting the operand having its decimal point nearest the low order end until the points are aligned as determined in comparison cycles alternating with the shift cycles. Subtraction is by 15s-complement addition. Features peculiar to multiplication.-The stages of the input and result registers are scanned in turn, low order first, to count the number of stages in the two registers below their respective decimal points. Then the result register is scanned again with decrementing of the counter by one for each stage, the decimal point being erased when encountered, and a new point being inserted when the count reaches zero. The contents of the result register are transferred to the multiply-divide register. The input register value is added serially into the result register a number of times equal to the digit in the highest order position of the multiply-divide register, then the result and multiply-divide registers are shifted one stage to high order, and the operation repeats. Multiplication terminates when a special code inserted into the first (low order) stage of the multiply-divide register on the first shift reached the 19th stage. Features peculiar to division.-A count is obtained and used as in multiplication except that the count corresponds to the difference rather than the sum of the numbers of positions below the decimal points. Division is by successive subtraction with shift. The high order stage of the result register is connected to the low order stage of the multiply-divide register, the latter eventually storing the remainder. Division terminates when a special code inserted in the first (low order) stage of the result register during the first subtraction cycle reaches the 20th stage.