Patent GB-1389311-A (GB)
Title: Semiconductor device manufacture
IPC: H01L23/522
Filed: 1972-04-18
Abstract: 1389311 Field effect transistors PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 18 April 1972 [8 June 1971] 17860/72 Heading H1K An IGFET comprises a semiconductor body having a region of one conductivity type within which is a surface region of the opposite conductivity type forming a PN junction which terminates at an insulating region inset into the surface of the body, the source and drain regions of the IGFET comprising spaced regions of the one conductivity type which also extend. into contact with the inset insulating region. A pair of complementary IGFETs, Fig. 2, are produced by thermally oxidizing an N type Si wafer 2, applying a Si3N4 layer (31) and a pyrolytic SiO2 layer (32) and processing to expose the desired isolation region pattern. Recesses are then etched in the Si, although this step may be omitted if desired, and the wafer<-> thermally oxidized to produce a thick oxide isolating layer 10 inset into the wafer. The masking layers over one of the device islands are then removed and B is deposited from a BN source and driven in to form the P type region 4. The oxide layer formed during this step is removed together with the remaining nitride layer if desired and the wafer heated in vacuo, preferably in the presence of undoped or lightly doped Si, to outdiffuse the B so that the maximum concentration lies along line M. The remaining oxide masking layer is removed and the gate insulation is provided by thermally oxidizing the wafer. A layer of high resistivity polycrystalline Si is deposited by decomposition of silane, an oxide layer is produced thermally or pyrolytically and is processed to form a mask which is used to etch the poly-Si layer to leave the desired gate electrodes 8, 18 and an interconnection strip 21. The oxide over the undiffused device island at either side of the gate electrode 18 and that on top of this gate electrode is removed and B is diffused-in to form self-registered source and drain regions 16, 17 and to dope the poly-Si gate 18. A layer of SiO2 is deposited, the masking layers of the diffused region 4 at either side of the gate electrode 8 and that on top of this gate electrode are removed and P is diffused-in to form self registered source and drain regions 6 and 7 and to dope the poly-Si gate 8. A thick oxide layer 11 is then deposited, contact windows are opened, and Al is vapour deposited and patterned to form source and drain contacts and conductive interconnection tracks one (12) of which crosses over the poly-Si strip 21. A small area of the masking layer is left on the source area during the P diffusion so that in the completed device the source contact 12 also contacts the region 4. A highly doped region 40 may be formed beneath the oxide isolation pattern 10 by diffusion into the grooves before oxidation to prevent inversion, but this region may also form naturally during the oxidation of the body due to the accumulation of the donor atoms. The gates of the transistors may be doped with the same impurity and the source and drain regions may be formed by an ion implantation method without removing the thin oxide masking layers. Alternatively diffusion from a doped oxide layer may be utilized. In a second embodiment, Fig. 15 (not shown), a pair of complementary tetrode (two gate) IGFETs are integrated together with a bipolar lateral transistor. In another embodiment, Fig. 16 (not shown), a pair of complementary single gate IGFETs are integrated together with a lateral bipolar transistor which is formed in a diffused island and using three poly-Si gates as masks for the emitter, collector and base contact diffusions which are performed simultaneously with the source and drain diffusions of the two IGFETs. The auxiliary gates are connected to the base region and prevent the formation of surface channels during operation. In a modification, Fig. 17 (not shown), the lateral transistor is replaced by a vertical bipnlar transistor, the device island forming the base region into which is diffused an emitter region and a base contact region separated by an auxiliary gate electrode connected to the base region. The substrate forms the collector region and is provided with a collector contact region in the form of a small island surrounded by inset insulating material. In a further embodiment, Fig. 18 (not shown) an IGFET and a vertical bipolar transistor are integrated in a wafer comprising a substrate having an epitaxial layer of the same conductivity type, between which is provided a buried layer which forms the collector region of the bipolar transistor contacted by a diffused wall region which surrounds part of the epitaxial layer (base region) into which are diffused emitter and base contact regions surrounded by part of the inset insulating pattern and separated by an auxiliary gate electrode connected to the base region. The IGFET comprises a diffused island, provided simultaneously with the collector wall region of the bipolar transistor in which are produced source and drain regions simultaneously with the base contact region of the bipolar transistor.