Patent GB-1433608-A (GB)
Title: Data processing systems
IPC: G11C29/48
Filed: 1973-07-18
Abstract: 1433608 Data processing system SIEMENS AG 18 July 1973 [28 Aug 1972] 34218/73 Heading G4A A data processing system comprises a plurality of processing units, a storage unit, and a store test unit arranged to feed test data to and receive test data from the storage unit and having a panel for the manual input of test data, an input for receiving programmed test data, and a manually operable switch alternatively to connect the test unit for the receipt cf manually and program generated test data. The system includes n processing units each connected to two redundant storage units each of which includes m stores, an input/output control unit, and a store test unit. The store test unit, Fig. 3, includes a register block TR including registers WR1, WR2 for storing test data, an operation register OPR, three address registers AAR, EAR, and STAR storing the start, end, and current store addresses for the current test cycle, a register DUR for storing the number of test cycles to be performed, and a register NAR having one bit position for each of the m stores to address a desired one of the stores by means of gates G3, G2, DW1, and DW2 (only one of each being shown). In operation test data is loaded in register block TR either via channel a from one of the processors or via channel b from the manual input panel BF in accordance with the position of a switch (not shown) in the panel. A single bit loaded in register NAR selects one of the m stores by means of gates DW1, DW2 and disconnects its usual connection Z from the processors via the store I/O control unit. The store is thus connected to the register block. The test data is read into the selected store either directly via G2 and G23 or via unit KM depending on a bit in the operation register OPR. Several units KM may be provided, one being selected by operation register bits, and each being arranged selectively to modify, e.g. by inverting, in accordance with address bits, the test data such that the data is more likely to reveal faults. An incrementer and comparator operate on the contents of the current and end address registers to provide a signal when the desired zone of the selected store has been loaded which causes a number indicating the number of the current test cycle to be incremented and compared in VGL2 with the contents of register DAD. When equality is indicated the test is complete. During the first cycle the test data is read into the selected store. During the second cycle the data previously stored is read out to register WAR and compared in VGL1 with the test data which is simultaneously read into register SR1. Since register SR1 is loaded at the beginning of each store word read cycle but register WAR only at the end of the cycle a second register SR2 is provided to give time for a comparison to be made. If comparator VGL1 produces an output indicating missmatch the testing is stopped. The operation register OPR contains data bits indicating, e.g. restart to restart the testing after a fault stop, parity routine to select one of the circuits KM which modifies the test data so as to load the store with data having an incorrect parity &c.