Patent GB-888732-A (GB)
IPC: G06F15/16
Abstract: 888,732. Digital electric calculating. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 28, 1960 [Dec. 30, 1959], No. 33347/60. Class 106 (1). A stored programme high-speed calculator includes two memories each operating to a cycle including read and write times, the read time of one memory coinciding with the write time of the other memory. The calculator comprises two arithmetic sections each having separate instruction registers and may be considered as two computors, main and control, linked by common memory and input/output arrangements, a monitor register, a priority control and a common instruction counter which normally addresses each memory in turn. The computors are essentially IBM 701's, described in U.S.A. Specification 2,974,866, with the memory replaced by the magnetic core memory, described in U.S.A. Specification 2,914,248, and a modified arrangement of instruction registers. The instruction registers store a number of instructions taken from memory under the control of the instruction counter and a priority system determines when these instructions are to be obeyed. In the main computer several additional registers are provided which may, in the " latch mode," be linked with the instruction registers to form a loop for the performance of iterative sub-routines. Instructions are half storage words, addressable individually, and containing sign, operation code and a single address, together with a bit indicating which computer is to perform the instruction. The operations available are those of the IBM 701 but are divided into several orders of priority, viz.: Instantaneous: Copy, Read, Write, Transfer (jump) &c., obeyed immediately; Store instructions : write accumulator, or the double length MQ register, into memory; and Data instructions: arithmetic or logic instructions requiring an operand from memory. In general the main computor takes priority over the control computor. General.-Each core memory 101, 102 (Fig. 1A), has a memory address register 103, 104 connected through a priority control 143 to a memory address buffer 144 which in turn is connected with the instruction counter 142 and instruction registers I Reg 1, 121, to I Reg 3, 123, of the control computor, and XI Reg. 1, 127, to XI Reg 3, 129, of the main computor. Input to the memories is via individual input buffers 119, 120 supplied through switches 118 from an input/output register 111 and the accumulator and MQ registers of each computor. Intermemory transfer is also possible. The outputs of the two memories are to a common memory bus and through switches 105 to memory registers 130, 131 of the control machine and 136, 137 of the main machine, or if the output is an instruction word to a monitor register 113. The monitor register interprets instantaneous instructions, requiring immediate attention, and may send the address contained in such an instruction to copy register 1 or 2, 116 or 117, or to the instruction counter. Other instructions are sent to I Reg 1, 121, or to an instruction buffer register 1, 124, of the main computor. There are five such buffer registers, 124 to 126 and 151 152, connected serially with the main computor instruction registers. The buffer and instruction registers may be linked through switches 114 and 150 to form a storage loop containing six instructions. Each arithmetic section has two input memory registers 130, 131 and 136, 137. Conditional transfer (or jump) instructions are detected by the monitor register which sets up circuits for the detection of fulfilment of the condition but are not executed until the instruction reaches XIR-3 or 1R-3. The latch mode of operation causes six instructions to be taken from memory and to be circulated in the registers of the main computor, each instruction being executed when it reaches X1R-3. The latch instruction is detected in the monitor register and is sent to XIR-3 where it is further interpreted to decide whether the latch mode is to be synchronous or asynchronous. At this time the last of the instructions forming the iterative subrontine is entering XI Buffer register 1 and is detected by the presence therein of a minus sign. Thereafter instructions for the main computor are blocked. If the mode is synchronous the condition of the control computer has an effect on the performance of the subrontine, e.g. the subrontine is performed each time an instruction with a negative sign is in IR-3. The subrontine will be stopped by satisfaction of conditional transfer signals in XIR-3 or IR-3. The asynchronous mode is stopped and controlled from the main machine only. Machine cycles.-The machine operates to a basic time cycle of three microseconds, equal to the read time of either of the memories, which is split into half-microsecond time units. The time cycle may be used generally in four ways: (1) as an instruction reference cycle in which the address held by the instruction counter is used to draw an instruction from memory and place it in the monitor register; (2) as a store cycle for the performance of store instructions; (3) as a data cycle for the performance of data instructions; and (4) all else failing, as a special instruction reference cycle. These cycles have priority in the order of their listing above. Instantaneous instructions are obeyed as soon as recognized in the monitor register, and may lead to a copy cycle, for example, when the required word is in the input/output register. Instruction registers.-These are constructed as in IBM 701 and each have a function in the recognition or execution of particular types of instruction: I Reg-1 or XI Reg-1 recognises data instructions; I Reg-2 or XI Reg-2 recognises store instructions ; and I Reg-3 or XI Reg-3 controls the execution of an instruction transferred to it from I Reg-2 or XI Reg-2, respectively. The X refers to components of the main machine and for convenience components of the control machine will be described as typical. I Reg-3 includes a countdown counter for the control of arithmetic and logic operations, as in IBM 701. The registers give indication of their contents to a priority control which determines the next machine cycle. The priority control (Fig. 10) receives input signals indicative of the machine state on channels 1002, 1007, 1015... and indicative of the kinds of instruction held in the registers. If channel 1002 is activated a copy cycle, transfer to or from input/output to memory is initiated. If a copy cycle command does not issue inverter 1004 activates instruction reference cycle control 1006 which is then sensitive to channel 1007. If an instruction reference cycle is not initiated the outputs of inverter 1004 and a second inverter 1009 are combined to enable a control 1013 of a store cycle involving the main machine arithmetic unit to receive signals from channel 1015. The next priority is given to a store cycle involving the control machine and its initiation depends on the non-occurrence of a command initiating one of the first three kinds of cycle. Typical machine operation.-It is assumed that all registers are initially empty and no arithmetic operation is being done in either machine. The sequence of commands shown in Fig. 66 will be drawn from memory and the execution of some described. In an initial cycle it will have been determined by priority that no copy instruction is present and the contents of the instruction counter (IC) will have been transferred to memory address buffer (MAB) 144. It is assumed that the first address is in memory 1, 101. The first cycle is an instruction reference cycle and at time A0 the address in MAB is sent to memory 1 address register 103, the instruction counter being incremented. At time A1.5 the first instruction-store MQ register in memory 2-is sent to the monitor register. At time A2.5, since the instruction is not instantaneous, the IC address is sent to MAB. As this is normal working the address will be for memory 2. At AO of the next cycle, again an instruction reference cycle, the address in MAB is sent to memory 2 address register, while the monitor register contents are transferred to IR1. At A1.0 the monitor register is reset and at A1.5 it receives the second instruction-read copy into memory 2. This is an instantaneous instruction and is recognized as such by the monitor register. At A2.0 this instruction is transferred to copy register 2, 117, which sets up controls for locating the desired word in peripheral storage and transferring it to I/O register 111 independently of operations within the machine. A copy instruction blocks the instruction reference cycle command until the beginning of the next cycle even though machine conditions are appropriate, as now. For this reason the instruction counter address is not sent to MAB at A2.5, and, in the present case, a store or data cycle is not initiated since no such instructions are awaiting execution. The next cycle is therefore of no particular type and at A0 the instruction in IR-1 is transferred to IR-2, at A1.0 the monitor register is cleared and at A2.5, the block instruction reference cycle having been lifted, IC is sent to MAB. On the next cycle MAB is sent to memory address register 1 at AO and at A1.5 the addressed instruction word is sent to the monitor register. It is Load XMQ (MQ register of the main machine) and is not of high enough priority to prevent an instruction reference cycle. The IC is sent to MAB at A2.5. At the start of the next cycle MAB is sent to memory address register 2 and the instruction Load XMQ to X Instruction Buffer register 1, 124. At A1.0 the monitor register is cleared and at A1.5 it receives the next instruction, a transfer instruction specifying that an address for memory 2 is to replace the present address in the IC. This is an instantaneous instruction and is obeyed at A2.0. The memories are available on alternate cycles and in the present example memory 2 w