Patent GB-1016280-A (GB)
Title: High speed print synchronizer
IPC: G06K15/07
Filed: 1964-06-26
Abstract: 1,016,280. Electronic digital computer; datastorage. SPERRY RAND CORPORATION. June 26, 1964 [July 10, 1963], No. 26473/64. Headings G4A and G4C. In a data processing system comprising a central processor and a plurality of peripheral devices each assigned with a priority for communication with the processor, a peripheral device is provided with a buffer store in the form of a recirculatory delay loop register, the most recently entered word in the buffer store being marked by an associated pattern of bits thereby indicating where the next word is to be entered. As described, the peripheral device is a line printer and each character, when sensed in the buffer store for printing is marked with a further bit so that unnecessary overprinting is obviated. Rearrangement provides that printing can take place from the data in the buffer register even though the buffer register is not full due to the interruption of data transfer between the central processor and the buffer register by a higher priority peripheral device. General arrangement.-As shown in Figs. 2a, 2b, data is transferred from a memory 8 in a central processor in the form of words, each word comprising four 6-bit characters (plus four bit positions whose function is not described to complete a 28-bit processor word), the transfer being temporarily to four 9-bit circulatory registers 38-44, one for each character of a word and thence to two 64-character buffer circulatory registers 56, 58. Words are arranged in the registers 56, 58 in the manner shown in Fig. 1c, characters 1 and 3 of a 4- character word being in register 56 and characters 2 and 4 in register 58. While each word is in the temporary storage registers 38-44, " 1 "s are inserted in the 8th bit positions of characters 1, 3 and 4, this pattern of bits marking the word, when it is subsequently entered in the registers 56, 58, as the last word entered therein, the corresponding pattern in the former last word being altered by replacement of the 8th bit " 1 " by a " 0 " in character 3 as shown in storage position 2 of Fig. 1c. The 9th bit position in each character is initially a " 0 ", this being replaced by a " 1 " when the character is printed. Print instruction.-When the processor requires a printing operation to take place, a " print standby loading instruction " is effective to read a print instruction, Fig. 3, from the memory and place it in a fixed memory location, generated by a generator 20, the location being associated with the printer, assumed to be peripheral device number 5 this location being sensed whenever the printer is communicating with the processor. In the print instruction, Fig. 3, bits 1-16 denote the initial address called the " L-address " of a series of 32 words required for printing a full line of type, bit 18 denotes whether paper advance and printing or merely paper advance is required, but 19-24 denote the number of lines of paper advance. Priority control.-Words are transferred from the processor to the printer one at a time and after each transfer a circuit 32, Fig. 2a, issues a request memory signal RM5 which is applied to a priority control circuit 34, priority for a further word transfer being granted only if no peripheral device of higher priority is requesting communication with the processor. Print instruction execution.-Assuming the printer has been granted communication with the processor, a signal GR5 is effective to read out the contents of the fixed memory address associated with the printer and transfer the print instruction to a register 36, the L-address being transferred to a memory address counter 46, and the bits 19-24 to a paperfeed counter 48. Assuming that printing as well as paper feed is required, a new request is made for communication to transfer the first data word to be printed from the memory location designated in the address counter 46. The data word is transferred via the register 36 and registers 38-44 to the two 64-character buffer registers 56, 58 as described above. During the loading of data into the registers 56, 58, paper advance takes place under the control of counter 48, print-out being inhibited by a signal PPZ, Fig. 2a, while this takes place. When the registers 56, 58 are full, this is detected by a circuit 67, Fig. 2b, to inhibit further data transfer, but it is not necessary for the registers to be full before printing commences. Printing-out operation.-The printer consists of a type cylinder 1006, Fig. 2b, having 128 columns of type, alternate columns being in staggered relationship, and is of the kind disclosed in Specification 883,361. During printing, the position of the type cylinder 1006 is indicated by a counter 82, whose contents are continuously compared with the contents of the 64-character registers 56, 58. For each typewheel position the entire contents of one of the registers 56, 58 (depending on whether the position is an " odd " or " even " one) is compared with the contents of the counter 82, a successful comparison causing the insertion by a circuit 88 of a 9th bit " 1 " in the character and the switching of a magnetic core in an " agreement matrix " 92. The matrix 92 is then sensed to cause printing of all the required characters now in printing position before the comparison operation for the next printing position is initiated. The print-out operation is continued until all characters in the registers 56, 58 have been printed, reprinting of a character already printed being inhibited by a 9th bit detector circuit 100, Fig. 2b. The print-out operation is terminated when a circuit 102, Fig. 2a, detects that all characters have their 9th bits equal to " 1," thereby causing an " action complete " flip-flop 54 to issue a signal indicating that the printer can accept a fresh instruction.