Patent GB-1490612-A (GB)
Title: Apparatus for controlling the transfer of data between central processing units
IPC: G06F15/167
Filed: 1975-02-12
Abstract: 1490612 Data transfer COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL 12 Feb 1975 [20 Feb 1974] 6006/75 Heading G4A Data may be transferred between any two of a set of central processing units (CPUs) 110-310 and 1010, the data transferred being stored temporarily in a data memory 11 of a controller 10 interconnecting the CPUs, data transfer being controlled by two instructions transmitted from the pair of CPUs involved which are received and are stored in a store WZ of the controller 10. Each CPU has its own private memory 111-311 and 1011 and I/O controller 112-312 and 1012, and operates in conjunction with an auxiliary magnetic disc or tape memory 120. The CPU 1010 is connected to the controller 10 via a remote communications link DL and adapters UCLA. A set of peripheral units EP1-EP3 is connected to the controller 10, data transfer between these and the CPUs taking the same form as CPU/ CPU data transfer. When a CPU desires to transfer data to or from another CPU or peripheral unit, its I/O controller formulates a "channel programme" comprising one or more instructions preceded by a "header", the header being able to select one of a set of parts P1-P3, D1-D3 and D10 of the controller 10 which give access to the CPUs or peripheral units. The channel programme is then transferred to the controller 10 via a control member 14 only if no other channel programme is being carried out. Each instruction includes a part indicating the direction of data transfer, a part signifying the number of data characters or bytes to be transferred, a part signifying a read/write operation, and a part which selects one of a set of address blocks MCB1-MCB3 in the controller 10, each address block when selected selecting a corresponding instruction from the store WZ. Each address block, e.g. MCB1, MCB2, has associated therewith a corresponding control block, e.g. MP1, MP2, receiving an instruction from the store WZ and controlling operation of a read/write circuit 12 of the data memory 11. Assuming that data is to be transferred from CPU 110 to CPU 310 (for example) the first instruction of the channel programme from I/O controller 112 is read into store WZ (the first instruction of the channel programme from I/O controller 312 having previously been read into store WZ to indicate the availability of CPU 310), this first instruction (from I/O controller 112) causing control block MP1 to operate the read/write circuit 12 and read the data transferred from I/O controller 112 into the data memory 11. When this transfer is complete, the address part of the first instruction (from I/O controller 112) causes the first instruction (from I/O controller 312) held in store WZ to be selected, whereupon control block MP1 operates the read/write circuit 12 to cause the data stored temporarily in data memory 11 to be read out and transferred to CPU 310 via I/O controller 312. Data transfer continues in this way, with control blocks MP1, MP2 alternately causing reading-in and writing-out of data into or from the data memory 11. The completion of data transfer is indicated by the provision of an extra binary digit with the last item of data, this binary digit being detected by the control blocks MP1, MP2.