Patent GB-857511-A (GB)
Title: Improvements in or relating to dividing multiplying arrangements for electronic digital computing machines
Inventor: STRACHEY CHRISTOPHER
IPC: G06F7/52
Filed: 1956-01-20
Abstract: 857,511. Digital electric calculating apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Jan. 18, 1957 [Jan. 20, 1956], No. 2036/56. Class 106 (1). In an electronic series-mode binary digital computer in which the number-word-representing electric pulse trains include a sign-indicating signal, and in which division is performed by an arrangement comprising first and second circulation loop word storage registers each having a delay time one digit longer than the word time and each including an add/subtract circuit in the loop, the first register stores the dividend or remainder and has signals representing the divisor applied to its add/subtract circuit while the second register is employed for building up the quotient and has a " 1 " representing signal applied to its add/subtract circuit once during each word time, and the add/subtract circuits are controlled in accordance with the signs of the divisor and the number word in the first register whereby addition and subtraction occur in the first and second registers respectively if the signs are unlike, and conversely when the signs are like. The computer described is similar to that of Specification 826,614, the first and second registers being the " p " and " q " accumulator registers ACR6, Fig. 1b, and ACR7, Fig. 1c, respectively. The present description relates primarily to the performance of various multiplication and division orders, for which the operands n and x are obtained from the N- and X-addresses included in the order word. The storage registers used may comprise magnetostrictive delay lines, or thermionic valve or magnetic core stepping registers. Multiplication. By means of three distinct orders, a double length product may be built up in registers p and q, a rounded product may be formed in p, or a double length product may be added to a double length number previously stored in p and q. The multiplication operation requires 15 or 16 beats or word periods. During the first beat D, the multiplicand n is supplied over line Y40 to delay line store Q15, Fig. 1b, and the multiplier x over line Y44 to unit delay Q23 and register q, Fig. 1c. At the end of this beat, the register circulation period is reduced by 3 digits by opening the upper, in place of the lower, entry gate of delay Q63, the lost (least significant) digits being set up on triggerconnected delays Q85, Q87, Q89 to provide digit-representing outputs M10, M9, M8 which during the following beat control the entry of the multiplicand via PO6, PO3, PO0 into seriesconnected adders ADR3, ADR2 and add/ subtractor AS1 so as to cause once, twice and four times the multiplicand respectively to be entered into register p. The three least significant digits of the partial product thus formed are transferred via delay P78, line Y55 and gated delay Q41 to register q. As the signals in q are right-shifted, similar operations occur during subsequent beats under control of successive groups of three multiplier digits. When the last group, including the sign digit in position d 38 , is operative, circuit AS1 is set to subtract. The final product registered in p and q may be tested for overflow in the manner described in Specification 826,614. Where rounding off is required, a "1" is initially inserted in the appropriate digit position in p. If a double length number is to be added to the product, the portion of this number in q is transferred to p, and the portion in p is transferred to the mill and is added to the product at the end of the multiplication. Division. The division orders permit the rounded or unrounded division of a double length number (in p and q) or the rounded division of a single length number, and require 43 beats. During the first beat, the divisor n is entered in Q15 and the dividend x (or most significant portion for double length numbers) is supplied over Y48 to register p. The circulation loop for p and q is made 43 digit periods (i.e. 1 digit more than a word period) to produce successive left shifts, the most significant digit in q being transferred to p over line Y60. The sign of the divisor is stored in a trigger circuit (not shown) and is compared during each beat with the sign of the number in p supplied over line Y52. If the compared signs are unlike, signal Q4 is operative to cause circuit AS1, Fig. 1b, to add n and to cause a half add/ subtract circuit comprising inverter Q37 and double entry gated delay Q38 to subtract the " 1 " signal Q3. Similarly, if the signs are like, signal Q5 causes subtraction in AS1 and addition in the half adder/subtracter respectively. Q5 is operative also if a zero remainder is detected, regardless of the sign comparison. Thus as the dividend and remainders are leftshifted, the quotient is built up in q, the final remainder being registered in p. Where rounding is required, an additional " 1 " signal Q3 may be applied via the half adder/subtracter to the quotient in q without further left shift. The final quotient may be tested for overflow. Specifications 826,612 and 826,613 also are referred to.