baber/WOPTO huggingface dataset:
Patent TW-394946-B (TW)
Title: Semiconductor memory device
Inventor: SAWADA SEIJI
IPC: G11C11/407
Filed: 1998-08-18
Granted: 2000-06-21
Abstract: The present invention relates to a semiconductor memory device, in which a gate circuit is turned on in synchronization with an internal clock signal at a timing faster than activation of an output buffer circuit (910b), and internal data (DD) is transmitted from the gate circuit to the output buffer circuit (910b) externally outputting data. Also, generation of an internal clock signal is stopped at a timing faster than deactivation of the output buffer circuit, and the gate circuit (910a) is set to the latching state, so as to prevent output of invalid data.
Patent TW-372273-B (TW)
Title: Micro normal force calibrator and calibration method
Inventor: YAN HUNG-RU
IPC: G01L5/00
Filed: 1998-09-08
Granted: 1999-10-21
Abstract: A kind of micro normal force calibrator which includes a table supporter which has a two-dimensional displacement tuning device on the base; and with a fixture for a flexibly strain gauge. There is a micrometer on the supporter which connects a probe below it. With a load cell on the probe, the load cell and the flexible strain gauge are connected to a signal transmitter to output to a signal amplifier for display. The calibration method employing the said calibrator to calibrate a precise measuring apparatus which includes (1) fix the flexible strain gauge on the fixture; (2) use the two-dimensional displacement tuning device to adjust the position of gauge; (3) adjust the micrometer so the probe can contact lightly on the surface of gauge and reset the amplifier to zero; (4) adjust the micrometer so the probe move downward and force on the strain gauge; at the same time, to record the force and strain from the micrometer and amplifier; (5) plot the two calibration curves by force and displacement. The user can use the curves to get the normal clamping force when he set up another flexible strain gauge with the connector.
Patent TW-434331-B (TW)
Title: Spun yarns taking-up apparatus and method of thread guarding the yarn thereon
Inventor: SUGIOKA TAKAMI
IPC: B65H65/00
Filed: 1998-09-29
Granted: 2001-05-16
Abstract: A plurality of nozzles (2) for spinning a yarn (Y) are disposed along a straight line, a cooling chimney (3) for cooling and guiding the spun yarns is disposed downstream the nozzles, a pair of feed rollers are disposed downstream the cooling chimney in such a manner that the axes thereof are perpendicular to the straight line along which the nozzles are disposed, a winder (W) is disposed downstream the pair of feed rollers in such a manner that the axes of the feed rollers are parallel to the axis of a bobbin holder of the winder, the lower opening (3c) of the cooling chimney is formed in an elongated form which is substantially parallel to the axes of the feed rollers and the chimney is located near the pair of feed rollers. At a position upstream the feed roller (7) and a position downstream the feed roller (8), a plurality of guides (34, 35) for restricting yarn passages are disposed movably in a direction of the axes of the feed rollers (7, 8). A spinning and taking-up apparatus can be obtained which has a high operability and by which yarn packages having high quality can be manufactured.
Patent TW-388924-B (TW)
Title: Method of producing semiconductor gate
Inventor: CHEN DUNG-PO
IPC: H01L21/28
Filed: 1998-11-20
Granted: 2000-05-01
Abstract: A method of producing a semiconductor gate comprises using a two-stage etching to separately etch a dielectric/silicide metal layer structure and a polysilicon layer in a multilayer structure of dielectric layer/silicide metal layer/polysilicon layer; and upon completion of the first stage etching of the dielectric layer/silicide metal layer structure, forming a spacer on the sidewall of the dielectric layer/silicide metal layer for protecting the side of the silicide metal layer in the gate from being attacked by the etching gas during the second stage of etching the polysilicon layer.
Patent TW-387193-B (TW)
Title: Incoming call display system with the functions of recording messages and speech sound output
Inventor: WU JUI-KUANG
IPC: H04M1/66
Filed: 1998-12-08
Granted: 2000-04-11
Abstract: An incoming-call display system with functions of recording messages and speech sound output is provided. It has several speech sound answering functions at user's selection. It can receive, analyze and record the caller's telephone number such that the user can know the caller's information through an external telephone line. It mainly includes a decoding device, a remote control device, a speech sound device, a microprocessor and a keyboard. The decoding device can receive the identification signal of the incoming call and analyze the caller's telephone number. The speech sound device can save several different speech segments previously and user can use keyboard to set and select one speech segment. When the phone answers the call automatically, it can play the speech segment to the caller by phone through telephone line. Besides, the remote control device receives the input signal from external telephone line and sends the transformed signal to the microprocessor such that the microprocessor can identify the control signal inputted by the user through external telephone line and control the device accordingly.
Patent TW-429248-B (TW)
Title: Pyrethroid compound and composition for controlling pest containing the same
Inventor: MORI TATSUYA
IPC: C07C69/743
Filed: 1999-03-26
Granted: 2001-04-11
Abstract: 4-methyl-2,3,5,6-tetrafluorobenzyl (1R)-trans-3-(2,2-dichlorovinyl)-2,2-dimethylcyclopropanecarboxylate and a composition for controlling pest containing said compound as an active ingredient are disclosed. The compound gives various forms of composition for controlling pest having a high pest-controlling effect and safety to mammals.
Patent TW-404883-B (TW)
Title: Improved sprayable fireproofing composition
Inventor: KINDT LAWRENCE J
IPC: B28B1/00
Filed: 1999-03-30
Granted: 2000-09-11
Abstract: Improved sprayable gypsum-based fireproofing composition comprising a lightweight aggregate and a set retarding agent comprising a hydroxycarboxylic acid, polycarboxylic acid, or a salt or derivative thereof. A preferred set retarding agent for the gypsum-based fireproofing is low molecular weight polyacrylic acid. The fireproofing composition can retain fluidity in conventional spray hoses overnight and yet is capable of being injected with a set accelerator, such as aluminum sulfate, the next day or on a successive day, when spray-applied onto a substrate.
Patent TW-I238160-B (TW)
Title: Substituted tricyclics for inhibiting sPLA2 and pharmaceutical formulation comprising the same
Inventor: BACH NICHOLAS JAMES
IPC: A61K31/00
Filed: 1999-04-16
Granted: 2005-08-21
Abstract: Novel tricyclics are disclosed together with the use of such compounds for inhibiting sPLA2 mediated release of fatty acids for treatment of conditions such as septic shock.
Patent TW-446676-B (TW)
Title: Part-conveying apparatus
Inventor: TAKAHASHI SHIGEKI
IPC: B65G47/18
Filed: 1999-06-22
Granted: 2001-07-21
Abstract: A part-conveying apparatus allows parts to align and slide down a sloped chute without stacking therein. The part-conveying apparatus has a chute sloped to align and slide down parts, and a first mobile blade for slidably supporting the parts in a bottom section of the chute in the direction of the chute 9. The lower end section of the chute is connected to a horizontal guide path, and a second conveying blade movable forward and backward is provided in a bottom section of the guide path. The second conveying blade reciprocates in a manner so as to move backward faster than to move forward, thereby conveying forward the parts placed thereon. A projection in the lower end of the first mobile blade engages with a groove of the second mobile blade so as to cause fine movements of the first conveying blade in the direction of the chute in synchronous with back and forth movements of the second conveying blade 26. This allows the parts to slide down.
Patent TW-593318-B (TW)
Title: Process for the preparation of guanine
Inventor: THEIS CHRISTOPH DR
IPC: C07D473/18
Filed: 1999-08-27
Granted: 2004-06-21
Abstract: The present invention relates to a process for the preparation of guanine, 2,4-diamino-5-formylamino-6-hydroxypyrimidine (DAFHP) being reacted with formic acid in the absence of formamide. This process is preferably carried out with addition of water and at reflux temperature.
Patent TW-429460-B (TW)
Title: Method for removing hard masks
Inventor: TSENG MAO-SONG
IPC: H01L21/30
Filed: 1999-10-15
Granted: 2001-04-11
Abstract: The present invention relates to a method for removing the hard mask in a semiconductor wafer. The method first provides a semiconductor wafer. The semiconductor chip sequentially includes a substrate, a pad oxide layer, a silicon nitride layer and a hard mask layer. The hard mask layer, silicon nitride layer, pad oxide layer, and the substrate with a predetermined depth below a predetermined surface area of the semiconductor chip are removed to form at least a trench. A gate oxide layer is grown on the surface of the substrate in the trench. The semiconductor wafer further includes a polysilicon layer arranged on the hard mask layer and the trench, and filled in the trench. The present invention then completely removes the polysilicon layer located on the hard mask layer to make the surface of the polysilicon layer in the trench higher than the surface of the hard mask layer. Next, the hard mask layer is fully removed. Finally, the polysilicon layer with a predetermined thickness is removed to make the surface of the polysilicon layer in the trench substantially equal to the surface of the silicon nitride layer.
Patent TW-494167-B (TW)
Title: Construction method of sand drum banking of continuous type
Inventor: WANG JAU-SHUEN
IPC: E02B3/06
Filed: 1999-12-18
Granted: 2002-07-11
Abstract: This invention is a construction method of sand drum banking of continuous type, especially for weir containment construction in the seashores to make new land. It provides how to build containing weirs by a cycling process of continuously connecting of sand drums to supply a non-stop filling to sand extract boats for continuous paving work.
Patent TW-530200-B (TW)
Title: Algorithmic pattern generator for integrated circuit tester
Inventor: GRUODIS ALGIRDAS JOSEPH
IPC: G01R31/3183
Filed: 2000-01-24
Granted: 2003-05-01
Abstract: An integrated circuit (IC) tester organizes an IC test into a succession of test cycles, each test cycle being subdivided into four segments. The tester includes a separate tester channel for carrying out a test activity at each IC pin during each segment of the test cycle. The tester also includes a separate pattern generator for each channel. Each pattern generator concurrently generates four vectors at the start of each test cycle. Each vector tells the channel what activity it is to carry out during a separate segment of the test cycle. Each pattern generator includes a low-speed vector memory storing large blocks of vectors at each address and a cache memory system for caching blocks of vectors read out of the vector memory at a low frequency and then reading vectors out in sets of 16 at the higher test cycle frequency. A vector alignment circuit selects from among the cache memory output vectors to provide the four vectors to the channel for the test cycle. Thus the frequency of test activities carried out by the tester is four times greater than the cache memory read access frequency and many times the vector memory read access frequency. To conserve vector memory space when repetitive vector sequences are to be generated, the cache memory system repeatedly read accesses various vector sequences both in the vector memory and in the cache memory.
Patent TW-552306-B (TW)
Title: Method of removing accumulated films from the surfaces of substrate holders in film deposition apparatus, and film deposition apparatus
Inventor: MAEDA KOJI
IPC: C23C14/56
Filed: 2000-02-18
Granted: 2003-09-11
Abstract: To resolve effectively the problems which arise when a thin film which has accumulated on a substrate holder peels off and becomes attached to the substrate. A substrate holder 90 where a thin film has accumulated on the surface of the holding claws 91 is transferred in a state where no substrate 9 is being held into a film removal chamber 70 which is established branching off in such a way that the vacuum is connected from the square transfer path 80 along which a plurality of vacuum chambers including the film deposition chambers 51, 52, 53, 54 and 50 is established. A high frequency power supply 73 is connected via the movable electrode 74 to the holder body 92 and a high frequency electric field is established within the film removal chamber 70. A plasma is formed by generating a high frequency discharge in the gas which is being delivered by means of the gas delivery system 72 and the accumulated film on the surface of the holding claws 91 is removed in a vacuum by sputter etching due to ion impacts. A film removal chamber 70 is connected in an airtight manner to the unload-lock chamber 2 and the load-lock chamber 1 in the return transfer path between the unload-lock chamber 2 in which the substrates 9 on which a film has been deposited are recovered from the substrate holder 90 and the load-lock chamber in which substrates 9 on which the thin film has not yet been deposited are mounted on the substrate holder 90. A film removing mechanism which removes the film which has accumulated on the surface of the substrate holder 90 by sputter etching with ion impacts is established in the film removal chamber 70.
Patent TW-447099-B (TW)
Title: Method for configuring the die pad on the chip
Inventor: CHAO TE-TSUNG
IPC: H01L23/48
Filed: 2000-02-21
Granted: 2001-07-21
Abstract: A method for configuring the die pad on the chip which includes the following steps: (1) the parameter setting step, including (a) setting a baseline pad pitch as the first value; (b) setting a first pad position as the first pad value; (c) providing a focal point; (2) determining the first angle between the first and the second leads that the first lead is passing the center of the first pad position and the focal point and the second lead is passing the center of the semiconductor chip and is perpendicular to the edge of the semiconductor chip; (3) determining a first pad spacing increment, which is equal to the first value divided by the cosine of the first angle; (4) setting a second pad position as the second pad value, in which if the first and the second pads are both the ground pads or the power pads with the same voltage, the second pad value is at least equal to the first pad value added with the first value; otherwise, the second pad value is at least equal to the first pad value added with the first pad spacing increment; (5) using the first pad value and the second pad value to configure the first die pad and the second die pad respectively along the edge of the semiconductor chip. Therefore, starting with the die pad closest to the chip corner, repeating the step 1 to 5 to calculate the suitable position of the die pad.
Patent TW-423967-B (TW)
Title: Ultrasonic beauty culture apparatus
Inventor: NISHIMURA SHINJI
IPC: A61H23/02
Filed: 2000-05-17
Granted: 2001-03-01
Abstract: The object of this disclosed invention is to provide an ultrasonic beauty culture apparatus capable of obtaining comfortable massage effects. For achieving the above-mentioned object, an ultrasonic beauty culture apparatus comprises a probe having a metallic part that comes in contact with a skin by one surface of the metallic part and has a piezoelectric element 11 to be stuck to another surface of the metallic part; an oscillator 121 for generating signals of a ultrasonic frequency; and a drive circuit 122 for power-amplifying the output signal. Further, the ultrasonic beauty culture apparatus comprises an oscillation drive circuit 12 for supplying high frequency electric power to the piezoelectric element 11 for generating ultrasonic vibrations by the piezoelectric element 11; a detecting circuit 13 for detecting the output fluctuation of the piezoelectric element 11, for example, fluctuation of supply power to the piezoelectric element 11; and a control circuit 14 for controlling the output from the oscillation drive circuit 12 so as to maintain the output of the piezoelectric element 11 constant according to the detected results.
Patent TW-584981-B (TW)
Title: AC/DC power conversion circuit controlled by FET and the application thereof
Inventor: WU JENG-SHIUNG
IPC: H02M7/12
Filed: 2000-06-09
Granted: 2004-04-21
Abstract: An AC/DC power conversion circuit controlled by FET and the application thereof are disclosed. The circuit structure of the AC/DC power conversion circuit is formed of a rectifying circuit; a switching circuit formed by FETs; a control circuit; a monitoring circuit and a voltage-stabilization circuit. The output voltage of the rectifying circuit is applied to the switching circuit and the control circuit respectively. By controlling the period of turning ON/OFF the switching circuit through the control circuit, the magnitude of the output to the load voltage can be controlled.
Patent TW-493252-B (TW)
Title: Semiconductor device and method of manufacture
Inventor: KAWAGUCHI MASAKI
IPC: H01L21/28
Filed: 2000-07-05
Granted: 2002-07-01
Abstract: A manufacturing process is disclosed that may decrease the number of times a substrate below a contact hole is subject to etching and/or minimize damage to such a substrate portion that may arise from such etching or oxidation. In one embodiment, a first dielectric layer (102) can be formed over a semiconductor substrate (101). A second dielectric (103), conducting layer (104) and third dielectric layer (105) may be formed over a first dielectric (102). A contact hole (106) may be etched through third dielectric, conducting and second dielectric layers (105, 104 and 103) and stop at a first dielectric layer (102). Portions of a conducting layer (104) exposed by a contact hole (106) may then be oxidized. The portion of the first dielectric layer (102) exposed by a contact hole (106) may then be removed by etching exposing a portion of the semiconductor substrate (101).
Patent TW-484314-B (TW)
Title: Device for testing digital monitor
Inventor: JUN IL-JIN
IPC: H04N5/46
Filed: 2000-10-11
Granted: 2002-04-21
Abstract: A device for testing a digital monitor which enables to test for each kind of operation in a digital monitor is disclosed. It includes a field programmable gate array (FPGA) for outputting a timing control signal, an oscillation section for generating a reference clock pulse for the FPGA, and an input selection section for selecting a resolution or a color pattern of an input image of monitor. It can also include a microcomputer to control the FPGA, so as to output a timing control signal according to the resolution selected in the input selection section, and output color control data for controlling the input image of the monitor to correspond to the color pattern selected in the input selection section. Next, it includes a transmitter for transmitting digital R/G/B image signals and clock pulses to the monitor according to the timing control signal outputted from the FPGA and the color control data outputted from the microcomputer. A power supply section can also be included for providing operational power to the FPGA, the oscillation section, the microcomputer, and the transmitter. Accordingly, working efficiency can be improved since the test process is simplified and refined.
Patent TW-516090-B (TW)
Title: Method of reproducing mark on semiconductor wafer and semiconductor wafer for distribution purpose and wafer carrier and method for manufacturing semiconductor wafer and obviating demerit of course of manufacture or processing of semiconductor wafer
Inventor: KITAGAWA SATORU
IPC: G06K19/06
Filed: 2000-10-26
Granted: 2003-01-01
Abstract: A plurality of minute ID marks are inscribed on a semiconductor wafer which is under manufacture, without imposing adverse effect to the wafer, in order to make the marks less susceptible to surface treatment to be performed during the course of manufacture. Further, the minute ID marks act as mutual backups. Inscribing such minute ID marks on a semiconductor wafer prevents confusion due to effacement of ultra-minute marks and eliminates worry about the impossibility of tracing a semiconductor wafer.
Patent TW-I273315-B (TW)
Title: Orientation division type liquid crystal display, fabrication method thereof and image display method
Inventor: MATSUYAMA HIROAKI
IPC: G02F1/1337
Filed: 2000-12-18
Granted: 2007-02-11
Abstract: In an orientation division type liquid crystal display device for widen a viewing angle of a display pixel of an active matrix type liquid crystal color display device having a COT structure, pixel color layers (6B, 6R, 6G) as color filters and pixel electrodes 3 are formed on a substrate on the side of the pixel electrodes and slopes 13 are provided along four side peripheries of each pixel electrode. Liquid crystal molecules 8 between each pixel electrode of the pixel electrode substrate and a common electrode of an opposing substrate are controlled in orientation direction along the slopes to divide it to a plurality of directions to thereby widen a viewing angle of a pixel display. The slope is formed on a step portion 12 formed by a BM layer formed on at least one of a gate electrode, a drain electrode and a source electrode formed in a periphery of the pixel electrode or at least one of a gate wiring and a drain wiring formed in the periphery or a step portion formed by partially overlapping peripheral portions of the adjacent pixel color layers.
Patent TW-562694-B (TW)
Title: Catalytic composition and a process for oligomerising ethylene, in particular to 1-hexene
Inventor: COMMEREUC DOMINIQUE
IPC: B01J31/14
Filed: 2000-12-22
Granted: 2003-11-21
Abstract: A catalytic composition is obtained by mixing at least one chromium compound with at least one aryloxy compound of an element M selected from the group formed by magnesium, calcium, strontium and barium, with general formula M(RO)2-nXn, where RO is an aryloxy radical containing 6 to 80 carbon atoms, X is a halogen or a hydrocarbyl radical containing 1 to 30 carbon atoms and n is a whole number that can take values of 0 to 2, and with at least one aluminum compound selected from hydrocarbylaluminum compounds (tris(hydrocarbyl)-aluminum, chlorinated or brominated hydrocarbylaluminum compounds) and aluminoxanes. The catalytic composition can be used in an ethylene oligomerization process, in particular to produce 1-hexene.
Patent TW-I254727-B (TW)
Title: Water- and oil-repellent, antistatic composition
Inventor: THOMPSON DELTON REITZEL JR
IPC: D06M13/236
Filed: 2000-12-26
Granted: 2006-05-11
Abstract: A water- and oil-repellent, antistatic composition comprises (a) at least one nonpolymeric ionic salt consisting of (i) at least one cation selected from the group consisting of monovalent metal cations, divalent metal cations, and organic onium cations, and (ii) at least one weakly coordinating anion, the conjugate acid of the anion having an acidity greater than or equal to that of a hydrocarbon sulfonic acid, and with the proviso that the anion is organic or fluoroorganic when the cation is a metal; (b) at least one fluorochemical repellency-imparting additive or repellent; and (c) at least one insulating material. The composition exhibits good antistatic and repellency characteristics.