Patent GB-788982-A (GB)
Title: Improvements in or relating to computing apparatus
IPC: G06F15/78
Filed: 1956-04-24
Abstract: 788,982. Digital electric calculating apparatus. BENDIX AVIATION CORPORATION. April 24, 1956 [May 2, 1955], No. 12557/56. Class 106 (1). A general-purpose computer of the type in which information stored in a record medium is adapted to be transferred as serial electric signals from one location to another under the control of a programme of commands recorded in the store, is characterized by a device through which all information is passed during transfer and which can modify the information in accordance with the type of transfer commanded and the value of an element in the information group being transferred. General.-The scheme of the computer is shown in Fig. 1. On the basis of a timing unit 17 and governed by a control unit 16, information from a data store 1 (such as a magnetic drum) from an accumulator 9, or from a product accumulator 10, is selected by a source switching unit 2 and passed through a device 3 in which the information is inspected and, in accordance with, for example, a signal indicating its sign, and the type of operation to be performed, as specified by a programme command, is complemented or not without interruption before passing, under the control of a destination switching unit 4, back to the data store 1 or the accumulators 9 and 10. Input and output of information is by way of the product accumulator. Programme commands may specify (according to the value of the 25th digit, Fig. 17) whether transfer shall be immediate or deferred. In the first case, transfer begins with the next data word and may be continued for up to 128 consecutive words until the time of the next command, as specified in digit places 10 to 16, and determined by a binary counter. In the case of deferred transfer only one word is transferred each time and the binary counter is used to determine the length of the waiting period. Adjacent words may be combined and handled by units of the apparatus as double-length words. A discriminator (Fig. 27, not shown) is provided to which intermediate results of a programme of computation may be routed to determine the course of subsequent operations. Storage.-The data store 1 consists of a magnetizable drum having seven tracks or memory lines each comprising 128, 25-bit words. There are also clock pulse tracks for defining the binary digit positions and the separation of words. Additional tracks are provided for the reception of both single and double-length words forming the storage sections of the accumulators. The first of the memory lines is normally used for the storage of programme words or commands the make-up of which is indicated in Fig. 17. Binary on/off signals are scanned by a head 48, Fig. 18, and, after amplification, applied to a gate 107. A binary " one " signal allows a clock pulse CP1 through to set a trigger circuit 109 whereby an increased voltage on its output 112 opens a gate 113 to allow a " write " pulse WP to be fed to the writing head 52. Immediately afterwards the trigger circuit 109 is reset by a further clock pulse Sh. Thus, the commands in the form of binary signals are red from the track 105, erased by an intermediate head (not shown) and written back on to the track by the head 52. They are available in true and complementary form on output lines 110 and 111 respectively, which control the source and destination switching circuits. Each of the data word memory lines is scanned by a head 48, Fig. 20, and fed via an amplifier 130, clock pulse gate 132, trigger circuit 135, and " write " pulse gate 138 back to the write head 52 by an arrangement similar to that described above. Output of data signals from this circuit to the sign inspection unit is via a gate 139 which is controlled by signals Si, Sj from the source switching unit. Similarly, input data signals from the sign inspection unit on lines 144, 145 are admitted through gates 142, 143 under the control of signals Di, Dj from the destination switching unit. These latter signals, if transmitted to set or reset the trigger circuit 135, will override any setting from the gate 132 since they occur with a later clock pulse CP2. In this manner new data may be written by the head 52 on to the " cleaned" " track 129. Destination and source switching.-Selection .of a particular write head 52 for the introduction of data words to its track, or a read head 48 for output of one or more words to other units of the apparatus, is determined by particular combinations of binary digits in positions 6 to 9 and 2 to 5, respectively, of the command word, Fig. 17. Signals representing this word are available, as described above, on output lines 110, 111, Fig. 18, which feed an eight-stage shifting register, half of which is shown in Fig. 19. Eight shift pulses only are gated through to a line 116 feeding along the pattern of signals derived from positions 2 to 9 in the command word until it occupies all the stages of the register. A tree circuit arrangement including gates 125 and 126 interprets the commands by an increased potential on one of the lines 127 and on one of the lines 128. The arrangement for destination output signals on lines D0 to D7 is shown, the source arrangement is identical and its relationship is indicated by the references S0 to S7. The general form of reference to these signals Di, Dj, Si, Sj is shown, for example, in Fig. 20. Some combinations represent addresses in the data storage, others represent the Accumulator, the Product Accumulator, &c., and orders such as " Print ", " Discriminate ", "Multiply", &c. Accumulator.-A track 214, Fig. 23, together with read and write heads 48, 52 and the intervening circuits, constitutes the accumulator or adder. A binary " one " pulse picked up by the head 48 is amplified and fed to a gate 217 controlled by a CP1 clock pulse. This causes a positive pulse on a line 219 and the binary " one " is registered by setting a bi-stable trigger circuit 222. At a slightly later time in the digit period, under the control of a CP2 clock pulse, a gate 228 is prepared to pass a corresponding binary digit signal from the source inspection unit output LB1. If this digit also is a binary " one " another positive pulse on the line resets the trigger circuit 222, but not before the high potential on a line 225 due to the setting of the trigger circuit 222 by the first pulse, has allowed the second pulse on line 221 to pass through a gate 226 and set a " carry " trigger circuit 230. The state of trigger circuit 222 when the write pulse WP occurs determines whether a binary " one " signal shall be passed to the write head 52 or a blank shall be left to represent binary " zero ". After each write pulse a shift pulse Sh transfers the setting of trigger 230 to trigger 222 and resets the former in preparation for receipt of the next pair of digits to be added together. Product accumulator.-Basically this is similar to the accumulator described above but a number of additional features are incorporated. The memory line between the read and write heads extends to 49 digit spaces. The chain of two trigger circuits 222, 330, Fig. 23, is extended to form a five-stage shifting register. which, besides enabling the length of the memory loop to be varied, and therefore providing the necessary shifting means for use in the processes of multiplication and division, also provides a convenient data input/output point. Sign inspection unit.-The first digit space of each data word is used to represent the sign of the number which follows. Binary zero represents a positive number: binary one, a negative number. The signal is examined by the sign inspection device and co-ordinated with the order given by digits 1 and 17 in the controlling command word. This order is examined at gates 163, 164, Fig. 21. A clock pulse occurring only at the first digit time opens the gate 163 to allow a binary one pulse, if present in this position, to set a trigger circuit 161. Similarly, the gate 164 is opened at the time of the 17th digit in the command to allow setting of a trigger 162 by a binary one pulse, if present. The operations called for by the combined states of the two trigger circuits 161 and 162 are shown in Fig. 22; the " add " and " subtract " operations must be considered in relation to the sign of the number passing into the unit on line 6 since the subtraction of a negative number requires that the number be transmitted to the adder unchanged, while the addition of a negative number or the subtraction of a positive number requires that the complement of the number be transmitted. Considering the operations as shown in Fig. 22, when " Transfer unchanged " is ordered by the setting of both the trigger circuits 161 and 162, binary one signals entering on EB line 6 are allowed through a gate 169 and in turn gate corresponding CP1 pulses through 170 to set a trigger circuit 172. The trigger circuit is reset immediately after each CP1 pulse by a CP2 pulse so that the output lines 173 and 174 of the trigger deliver the true and complementary forms, respectively, of the serial pulse train entering the unit on line 6 to gates 175 and 176 and thence control output gates 181 and 183 to allow corresponding CP2 pulses to represent the unchanged data on the output channels 144, 145. For the command " Transfer absolute value " the states of the triggers 161, 162 prepare a gate 185 for passing the data entering on line 6. However, this gate is also conditioned by a lead 186 which prevents a pulse in the first digit position of a word from passing through the gate 185 and thus would delete a negative sign (if any). A special pulse recorded on a memory line 150 is detected by a head 48 and sets a trigger circuit 153 during the first digit period. The trigger circuit is reset before the second digit time by a pulse Sh passing through a gate 190. The remaining digit signals, therefore, are passed through the gate 185 to the gate 170 and so on to