Patent GB-1226019-A (GB)
IPC: H04N5/073
Filed: 1968-08-09
Abstract: 1,226,019. Automatic frequency and phase control. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 9 Aug., 1968 [10 Aug., 1967], No. 38217/68. Heading H3A. [Also in Division H2] A control arrangement, Fig. 1, for the synchronization of television signal generators comprises, means 28 for controlling the frequency and phase of signals produced by a generator 21a, said means being controlled by a synchronizing signal S, H which is formed by comparing signals from a comparison generator 4 with the generator 21a at fixed intervals. Phase correction is effected by a circuit 23 having a number of terminals at which phase displaced signals occur, the terminals being selectively connected to a common point 19a through a switching arrangement which is controlled by the signal S, H. Signals transmitted from a remote TV camera unit m are picked up by a receiver 3, and the line and frame synchronizing pulses L m , T m  are separated by separator 5, and compared with reference line and frame pulses in comparators 7, 6 respectively. The outputs from these comparators are in the form of binary signals A, H, X, Y which indicate whether the remote signal is leading, lagging or in phase with the reference signal. For synchronizing the frequencies a frequency comparator 58 is used, which actuates a switch I 3  to replace the binary signal A with a signal B conveying data inductive of the frequency difference. These data signals are then combined with any signalling information required and are transmitted by transmitter 13 to the remote camera. The signals received at the camera are fed to decoders 16, 17, 18 which separate out the frame synchronization control signals, the line synchronization control signals and the information signals respectively. The output from decoder 17 is then fed to unit 28 which detects whether phase difference data A, or frequency difference data B, is being received. The B data is used to control the frequency of the remote synchronization oscillator 21a, and the A data is used to switch a phase shift network 23 connected in the oscillator output circuit. The line synchronization comparator, Fig. 3, receives the reference synchronizing signal L r  and produces signal a delayed with respect to S by a predetermined period of time. If a remote synchronization L m  is received during this time, it is considered to be in synchronization with L r . During this time S = 1 and a = 0, so that gate P 73  is enabled by the S signal to allow the L m  pulse to switch bi-stable B 73  to K = 1. Gate P 72  is inhibietd by the a = 0 signal and bi-stable B 72  is not switched, but remains in the I = D state giving an output A = D. I and K (both "1") are fed to a NAND gate P 74  which produces an output J = 0 to make the H signal also " 0 ". If the L m  signal arrives before either S or a both gates P 72  and P 73  are inhibited K remains at " 0 " to make J = 1 resulting in an output A = 0, H = 1. If the L m  signal arrives after both S and a, both gates P 72  and P 73  are enable bi-stable B 72  and B 73  are switched resulting in K = 1, I = 1, producing an output A = 1, H = 1. The phase shifter, Fig. 2 (not shown), comprises a pair of RC networks connected in parallel across the secondary of a transformer (31). Phase shifts of 0, 120 and 240 degrees are tapped off from the networks and are fed via gates (25, 26, 27) to an output limitor (30). The gates are controlled to produce either a forward or reverse switching sequence depending on whether the gate control signals are 0, 1 or 1, 1.