Patent GB-839241-A (GB)
Title: Improvements in or relating to electronic calculating apparatus
Inventor: BIRD RAYMOND
IPC: G06F7/535
Filed: 1955-08-19
Abstract: 839,241. Electronic binary dividing apparatus. INTERNATIONAL COMPUTERS & TABULATORS Ltd., Aug. 17, 1956 [Aug. 19, 1955], No. 23948/55. Class 106 (1). In a binary electronic calculating-apparatus for performing division by repeated subtraction, the values are held in shifting registers and the divisor is first doubled by shifting to the left until it exceeds the dividend, it is then subtracted from the dividend, which is shifted to the left after each subtraction, and, when the remainder is positive a binary " 1 " is entered in a quotient register. At each step the dividend (or partial remainder) is shifted into another register and retained so that if the remainder from any subtraction is negative the calculation can go back to the last positive remainder. A binary " 0 " is entered into the quotient register and the next subtraction is made from the stored remainder shifted two places to the left. The process is repeated for a predetermined number of steps according to the degree of accuracy required, the absolute magnitude of the quotient being determined from the number of preliminary shifts of the divisor necessary to make it exceed the dividend. As shown in Fig. 1, there are four stores M, A, Q, B each being a shifting register of 40 stages, the numbers to be operated upon being taken initially from a magnetic drum 2, and entered into these stores, as described below. The subtraction steps involved in the operation of the machine are performed in an adder/subtractor circuit as described in Specification 738,269, the values in the stores being circulated in series mode through this circuit (shown in the dotted square 62 in Fig. 1). This circulation is effected by application of shift pulses as described later, the shift pulses being distributed by a control circuit in dependence upon instructions received from the drum and registered in the control register 16. The magnetic drum 2 has sixty-two reading heads 1 and heads 5, 7. The particular head 1 to be read from is selected by a track selector circuit 3 which is a pyramid of relay contacts, the relays being set up by the control register. The output from the selector 3 is amplified and passed through gates 9 and 10, as described later. The head 5 reads trains of forty clock pulses and passes them on to line 40 and also through amplifier 6 and gate 22 to a counter 23, 24. Gate 22 is controlled by trigger 26 at the other end of the counter. Part 23 of the counter counts up to forty and gives an output pulse, i.e. an " end of word " pulse since the words recorded on the drum have a length of forty digits. The end of word pulse is transmitted over line 25 and also to the second part 24 of the counter which counts up to sixteen and gives a pulse. Since there are sixteen words on each track of the drum, the counter 24 gives a pulse each revolution which is passed to trigger 26 to close input gate 22. Head 7 reads a pulse at the end of each revolution which is passed to trigger 26 to re-set it. The synchronism of the counter is checked by making the opening of the gate 22 at the beginning of each cycle dependent upon the synchronization pulse from head 7. The words are so numbered on each track that the number agrees with the count on counter 24 and the desired word is selected by entering the number in the control register in positions 10-13. This number is taken to a multiple-gate 35, Fig. 2, on lines 34 and lines 36 take the number registered in the counter 24. When these are equal, gate 35 opens, allowing a pulse to pass through and set coincidence trigger 28 which opens gate 38 to pass clock pulses from line 40 to line 39 and through a delay trigger 41 to line 42. Lines 39, 42 and 40 control input gates 47, 48, 49 of a distributing circuit so that by opening any one of these gates 47, 48, 49 and one of the gates 128, 122, 103, 104, 72, 74, 75, 54 and 55 any of the different sorts of pulse train can be fed to shift the words in the registers. These three sorts of pulse train are:-on line 39, forty clock pulses when coincidence occurs in gate 35; on line 42 delayed clock pulses when there is coincidence and on line 40 constantly occurring clock pulses. A selected word is read out through gate 9, Fig. 1, to gate 10 which has two outputs, one for binary 1 pulses and the other for binary 0 pulses. These are applied to set and unset a bi-stable input trigger 11, the output of which is applied to highway 21. The control register 16 and stores 17, 19, 20 are connected to highway 21 through input gates 12, 13, 14, 15. A value is entered into a register by opening the input gate and applying shift pulses on lines P33, P3, P13 or P23. At the beginning of an operation the instruction is entered into the control register from drum 2. The function to be performed is registered in positions 14-18 of this register, which are connected by lines 44 to a function-controlling matrix (Fig. 3, not shown), giving different voltage levels on a series of output lines (all having a number with prefix 46) which are used to control various gates in the pulse distributing arrangement of Fig. 2. Operation.-In this process of division it is first necessary to shift the divisor with respect to the dividend until the former is the larger. This may be done by shifting, say, five places or by giving the divisor an initial shift, subtracting, testing the remainder, shifting and testing again until the divisor is larger than the dividend. For this preliminary operation the divisor is entered into the Q register. If it is to be shifted five places to the left, the gate 73 is opened by an instruction in the control register so that the contents of the Q register can circulate, and thirty-five shift pulses are applied at P13 to move the value in the register as many places to the right which is equivalent to five places to the left. The divisor is then transferred by the next instruction to the B register in which it is positioned during a division operation. This is effected by setting the Q memory trigger 68, Fig. 2, to allow coincidence clock pulses on line 39 to pass through the left-hand side of gate 70 to lines P11, P13, P15. Also delayed coincidence clock pulses are admitted to lines P23, P26 so that the pulses on P13 shift the value in the Q register through gate 127 to the input trigger 11 and also through gates 73 back into the Q register, and delayed clock pulses admit the output of trigger 11 on highway 21 through gate 15 into the B register, the value being shifted along this register by pulses on line P23. Q register is then cleared. The method of positioning the divisor with respect to the dividend by repeated shifting and testing is also described. At the beginning of a division operation the divisor is positioned in the B register and the dividend in the A register, the divisor being larger than the dividend. The dividend is then left shifted one digit. This is done by reducing the train of forty delayed coincidence pulses on line 42 by one and applying the thirty-nine shift pulses left to line P3 so as to circulate the dividend thirty-nine stages to the right. At the same time the divisor is subtracted from it in the circuit 62. This is done by passing the divisor in register B through gate 77, through input trigger 11 to coincidence and anticoincidence gates 101, 102, and applying the digits of A register in series mode out on lines 112 and to the carry trigger 63 on lines 86. The subtraction operation alters the value circulated in register A through gates 108, or 109, which are controlled by the outputs from gates 105, 106 to pass either the same digit or the inverse to the input of the A register. In this way the partial remainder after the first subtraction is entered in the A register. The sign of this remainder is tested and if it is positive a binary 1 is entered into the appropriate position of the Q register in which the quotient is built up as the subtractions proceed. Also if the partial remainder is positive it is given a second effective shift to the left and the divisor is subtracted again to form a second partial remainder, the sign of which is tested again. If the first partial remainder is negative a binary 0 is entered in the Q register and the divisor is subtracted from the original dividend shifted two digits to the left to form the second partial remainder. The initial dividend or, at a later stage, the last positive partial remainder, is retained in the M register unti it is known whether it will again be required, i.e. until the next positive partial remainder has been produced. When the partial remainder is positive thirty-nine pulses are applied to gate 94 to allow the contents of register A to enter register M with a left shift. If the remainder is negative thirty-nine pulses pass to gate 93 over line P31 which controls the circulation of the value in the M register. This value is therefore circulated with a left shift. A negative partial remainder causes the gates 105, 106 of the subtracting circuit to control gates 115, 116 instead of gates 108, 109. Shift pulses applied to line P31 cause the value in the M register to circulate thirty-nine steps through open gate 93. The signal on line 117 (from gate 105) opens a gate to pass the digits of the M register through lines 119 to lines 86 of the carry trigger of the subtracting circuit. The contents of M register then pass through gate 115 or 116 to the input of the A register, the gates 115, 116 being controlled from gates 105, 106 as were gates 108, 109 previously described, so that the value entered in the A register is the next partial remainder. This has the effect of entering in the A register the result of the subtraction of the divisor from the original dividend shifted two places to the left, while the shifted dividend is re-entered in the M register shifted yet another place. If the partial remainder is still negative the divisor is again subtracted from the va