baber/WOPTO huggingface dataset:
Patent TW-522663-B (TW)
Title: Radiofrequency signal receiver with control means for the channels to be controlled
Inventor: FARINE PIERRE-ANDRE
IPC: H04B1/26
Filed: 2001-10-30
Granted: 2003-03-01
Abstract: The radiofrequency signal receiver (1) includes means (3) for receiving and shaping radiofrequency signals into intermediate signals (IF), a correlation stage (7) which includes several correlation channels (7') for receiving the intermediate signals (IF), microprocessor means (12) connected to said correlation stage for the transfer of control and/or data signals. The receiver also includes channel selection means, such as a priority decoder (13), connected to all the channels (7') of the correlation stage (7) and to the microprocessor means (12). These selection means allow the channel with the highest priority among the operating channel or channels which have each transmitted an interruption signal for a data transfer from the selected channel to the microprocessor means (12), to be placed first in a virtual channel, in accordance with a defined order of priority for all the channels.
Patent TW-544732-B (TW)
Title: Contact portion of semiconductor device and method for manufacturing the same, and thin film transistor array panel for display device including the contact portion and method for manufacturing the same
Inventor: KIM BO-SUNG
IPC: H01L21/84
Filed: 2002-02-25
Granted: 2003-08-01
Abstract: First, gate wire in a horizontal direction including a gate line, a gate electrode and a gate pad are formed on a substrate. Next, after forming a gate insulating film, a semiconductor layer and an ohmic contact layer subsequently are formed thereon. Next, a conducting material is deposited and patterned to data wire including a data line crossing with the gate line, a source electrode, a drain electrode and the data pad. Next, a passivation layer and an organic insulating film made of photosensitive organic material are deposited, and then the organic insulating film is exposed and developed to form contact holes for exposing the drain electrode, the gate pad and the passivation layer on the data pad, respectively. Here, the organic insulating film around the contact holes is formed thinner than that in the other portions. Next, the organic insulating film around the contact holes is removed by an ashing process to expose the borderline of the passivation layer in the contact holes, thereby removing an under-cut. Then, ITO or IZO is deposited and patterned to form a pixel electrode, an assistant gate pad and an assistant data pad connected to the drain electrode, the gate pad and the data pad, respectively.
Patent TW-522564-B (TW)
Title: Single chip push-pull power transistor device
Inventor: PERUGUPALLI PRASANTH
IPC: H01L27/07
Filed: 2002-03-06
Granted: 2003-03-01
Abstract: A push-pull transistor chip comprises a single a semiconductor die having first and second LDMOS transistors formed thereon and configured for push-pull operation, the first and second transistors sharing a common element current region. In a power transistor package, the push-pull transistor chip is attached to a mounting flange serving as a common element ground reference, wherein a conductor (e.g., one or more bond wires) electrically connects the shared common element current region to the mounting flange.
Patent TW-586024-B (TW)
Title: Highly reflective optical components
Inventor: KOZHUKH MICHAEL
IPC: G02B1/10
Filed: 2002-03-27
Granted: 2004-05-01
Abstract: Optical components (20) may be made with reflectors (14) that increase the reflectivity of the resulting device. Increasing in the reflectivity may reduce the need for higher power light sources. In particular, the use of deposited silver layers may dramatically increase the reflectivity compared to aluminum and copper alloys. In addition, an absorptive layer (10, 12) may be positioned over the reflective layer (14) to reduce the amount of blue light output from the reflector. This blue light absorber may be used to automatically rebalance light sources that produce an excessive proportion of blue light.
Patent TW-546208-B (TW)
Title: A method of surface decoration for portable electronic device
Inventor: CHENG CHIN-FENG
IPC: H04M1/00
Filed: 2002-04-30
Granted: 2003-08-11
Abstract: A method of surface decoration of portable electronic device comprises the following steps of: (1) providing a portable electronic device having a housing; (2) providing a substrate having a carved design; (3) covering the substrate with a layer of printing ink; (4) removing superfluous printing ink on the substrate using a knife; (5) providing a transfer printing machine having a soft header; (6) transferring the design from the substrate to the housing of portable electronic device via the soft header. The method is easy to handle and reduce the cost greatly; moreover, customer can determine the design on the housing.
Patent TW-528574-B (TW)
Title: Interline rod
Inventor: MATSUMOTO MASAHIKO
IPC: A01K87/00
Filed: 2002-04-30
Granted: 2003-04-21
Abstract: The object of the present invention is to provide an interline rod capable of inhibiting damage of a fishing line and rod body, and excellent in strength. The solution of the present invention is that the shaking out type interline rod comprising a base rod (1) and a second rod body connected to the top rod side of the base rod (1) in a shake out type, and the base rod (1) has a first tapered part (A) with increasing inside diameter from the top rod side to the base side, a second tapered part (B) with increasing inside diameter to the base side continuing to the base side of the first taper part (A) in a larger taper than the first taper part (A) and a third tapered part (C) with increasing inside diameter to the base side continuing to the base side of the second tapered part (B) in a smaller taper than the second tapered part (B) and a fishing line entry (10) formed on the second tapered part (B) and/or the third tapered part (C).
Patent TW-540115-B (TW)
Title: Semiconductor process
Inventor: YANG MING-CHENG
IPC: H01L21/304
Filed: 2002-05-02
Granted: 2003-07-01
Abstract: The present invention discloses a semiconductor process. Firstly, an advance estimated processing rate and an advance real processing rate are provided, and then, a first linear equation having the first variable dynamic weighting factor is used to find the estimated processing rate at present. Afterwards, an advance fine-tuning value D(t-1) is provided, a second linear equation having the second variable dynamic weighting factor is used to find the current fine-tuning value D(t), and D(t) is used to modify the estimated polishing rate at present. Finally, a processing goal is determined, and manufacturing of the wafer in the wafer box according to the processing time calculated from the estimated processing rate at present is carried out.
Patent TW-561405-B (TW)
Title: Computing system
Inventor: NISHIHARA AKINORI
IPC: G06F15/78
Filed: 2002-05-10
Granted: 2003-11-11
Abstract: A computing unit (42) executes a second computing in the middle of a first computing. At this time, the hardware structure of the computing unit (42) is switched in accordance with a computing which is a target of execution. A controller (46) stores the internal state of the computing unit (42) in a memory (44) when a computing to be executed by the computing unit (42) changes from the first computing to the second computing. And the controller (46) controls execution of the first computing to be continued by returning the internal state stored in the memory (44) to the computing unit (42), when a computing to be executed by the computing unit (42) returns from the second computing to the first computing.
Patent TW-I230482-B (TW)
Title: Nonaqueous electrolyte secondary battery
Inventor: IMACHI NAOKI
IPC: H01M4/38
Filed: 2002-05-30
Granted: 2005-04-01
Abstract: A nonaqueous electrolyte secondary battery according to the invention comprises a positive electrode containing a positive electrode active material including lithium containing composite oxide having a layer crystal structure represented by a general formula of LixMnaCObMcO2 (0.9 <= X <= 1.1, 0.45 <= a <= 0.55, 0.45 <= b <= 0.55, 0 < c <= 0.05 and 0. 9 < a+b+c <= 1.1 are set and M is one kind selected from Al, Mg, Sn, Ti and Zr), a negative electrode containing a negative electrode active material capable of intercalating and deintercal ating lithium ion, a separator for separating the positive electrode from the negative electrode, and a nonacqueous electrolyte.
Patent TW-565634-B (TW)
Title: False twist texturing machine
Inventor: PYRA MICHAEL
IPC: D02G1/08
Filed: 2002-06-21
Granted: 2003-12-11
Abstract: The invention relates to a false twist texturing machine for false twist texturing a plurality of synthetic yarns in a plurality of processing stations, which each comprise a plurality of feed roll systems, a primary heater, a cooling device, a false twist unit, a secondary heater, and a takeup device. For accommodating the takeup devices, a takeup module is provided, and a processing module for accommodating the false twist units, with a doffing aisle being formed along the takeup module and a servicing aisle along the processing module. To realize a short yarn path, the processing module and the takeup module are joined to a frame section arranged between the servicing aisle and the doffing aisle. In this arrangement, the yarn passage from the processing module to the takeup module is formed by the horizontally oriented secondary heater, so that the yarn is guided between the false twist unit and the takeup device on the frame section along a substantially U-shaped path.
Patent TW-I290338-B (TW)
Title: An optical proximity correction method
Inventor: HWANG JIUNG-REN
IPC: H01L21/027
Filed: 2002-07-04
Granted: 2007-11-21
Abstract: An optical proximity correction (OPC) method first provides a predetermined integrated circuit layout. The integrated circuit layout is then formed on a surface of a photo-mask, and a plurality of nonprintable dummy patterns are formed outside the integrated circuit layout on the surface of the photo-mask. The plurality of dummy patterns are used to reduce the difference in pattern density on the surface of the photo-mask so as to modify optical proximity effect, and the dummy patterns are not transferred to a photoresist layer formed on a semiconductor wafer during a photolithography process.
Patent TW-569038-B (TW)
Title: Projection illumination system
Inventor: KNEER BERNHARD
IPC: G02B13/24
Filed: 2002-07-09
Granted: 2004-01-01
Abstract: A projection illumination system, intended in particular for microlithography, is used for generating, in an image plane, an image of a mask (2) arranged in an object plane. The projection illumination system has a light source emitting projection light and projection optics (1) arranged between the mask (2) and the image (36). Starting from the mask (2), the following are arranged in the beam path of the projection optics: a first group (LG1) of optical components with an overall positive refractive power; a second group (LG2) of optical components with an overall negative refractive power; a third group (LG3) of optical components with an overall positive refractive power; a fourth group (LG4) of optical components with an overall negative refractive power and a fifth group (LG5) of optical components with an overall positive refractive power. At least three optical subgroups (2, 8, 9, 17; 6, 8, 9, 17; 2, 8, 9, 17, 31; 2, 8, 9, 17, 23, 31; 6, 8, 9, 17, 23, 31) having at least one optical component can be displaced along the optical axis of the projection optics (1). The first optical subgroup comprises the mask (2) or at least one optical component (6) from the first group (LG1) of optical components. The second optical subgroup comprises at least one optical component (8, 9) from the second (LG2) or the third (LG3) group of optical components. The third optical subgroup comprises at least one optical component (17) from the third (LG3) or the fourth (LG4) group of optical components. With such subgroups, efficient imaging error correction of the projection optics (1) is possible.
Patent TW-I234152-B (TW)
Title: Optical pickup device and recording medium used therefor
Inventor: KIM DAE-SIK
IPC: G11B7/135
Filed: 2002-08-01
Granted: 2005-06-11
Abstract: An optical pickup device includes a light unit for irradiating a light beam having a wavelength longer than 650 nm onto a recording medium, and an objective lens formed of a single lens having an NA of 0.7 or more to form a light spot on the recording medium by condensing an incident light beam emitted from the light unit. A recording medium having a recording density of a DVD family or more and formed of a material suitable for a long wavelength of 700 nm or more so that a reproduction signal by a reflectance of a recording surface is optimized. Thus, a compact high density optical recording/reproducing apparatus which is inexpensive and has high performance can be realized.
Patent TW-591239-B (TW)
Title: Printed board inspecting apparatus
Inventor: OSAKA HIDEKI
IPC: G01R31/28
Filed: 2002-08-06
Granted: 2004-06-11
Abstract: Only a DC check to detect a short or open state was performed for the wiring on a printed board, which cannot make sure whether or not the degree of coupling is within a range of specified values, nor can detect whether or not the RZ signal for a digital semiconductor device having a hysteretic input circuit is within a range of specified values. A check is made using a TDR method to determine whether or not the degree of coupling is within a range of specified values and to determine each of the voltage of the polarized RZ signal and the pulse width time is within a range of specified values to thereby inspect a printed board and a semiconductor chip constituting a bus using a directional coupler. Thus assembling these qualified devices provides a product with high stability and yield.
Patent TW-559914-B (TW)
Title: Memory unit with T-shape gate
Inventor: CHUANG YING-CHENG
IPC: H01L21/336
Filed: 2002-08-15
Granted: 2003-11-01
Abstract: A method of forming a memory unit with a T-shape gate. About a CMOS, first, a semiconductor substrate is provided which a dielectric layer and a hard mask with a first opening and a second opening. A BSG spacer is formed on the sidewall of the first opening. The BSG spacer is warmed to form a LDD. The BSG spacer is removed. A first spacer is formed on the sidewall of the second opening. A N-type conductor spacer is formed besides the first BSG spacer, and another N-type conductor spacer is formed besides the first spacer sidewall. A plurality of the gate dielectric layer is sequentially formed on the surface of the semiconductor substrate that is exposed by the first opening and the second opening. The first opening and the second opening are full with a P-type conductor layer. The hard mask layer is removed. A second spacer is formed besides the conductor spacer which of the second opening.
Patent TW-567613-B (TW)
Title: Nitride read-only memory cell for improving second-bit effect and method for making thereof
Inventor: YEH YEN-HUNG
IPC: H01L27/115
Filed: 2002-08-21
Granted: 2003-12-21
Abstract: An NROM cell for reducing for reducing the second-bit effect is described. The NORM cell of the present invention is formed with a substrate, a silicon oxide/silicon nitride/silicon oxide (ONO) layer disposed on the substrate, a gate disposed on the silicon oxide/silicon nitride/silicon oxide layer, source/drain regions configured in the substrate beside the gate, and a shallow pocket doped region configured between the source/drain regions and the ONO layer beside the gate. The depth of the shallow pocket doped region is sufficiently small to prevent interference to the current flow that travels to the source/drain regions.
Patent TW-583563-B (TW)
Title: Logic simulation
Inventor: WHEELER WILLIAM R
IPC: G06F17/50
Filed: 2002-08-28
Granted: 2004-04-11
Abstract: Logic simulation includes storing a first state to identify in a simulation of a logic design whether a node included in the logic design has a logic high value. Logic simulation also includes storing a second state to identify in simulation of the logic design whether the node has a logic low value and storing a third state to identify in simulation of the logic design whether the node has an undefined state. The logic simulation determines an output of the node in simulation of the logic design based on the first state, the second state, and the third state.
Patent TW-I261763-B (TW)
Title: Dynamical methods for solving large-scale discrete and continuous optimization problems
Inventor: CHIANG HSIAO-DONG
IPC: G06F17/13
Filed: 2002-09-20
Granted: 2006-09-11
Abstract: Dynamical methods for obtaining the global optimal solution of general optimization problems having closed form or black objective functions, including the steps of first finding, in a deterministic manner, one local optimal solution starting from an initial point, and then finding another local optimal solution starting from the previously found one until all the local optimal solutions starting from any initial point are found, and then finding from said points the global optimal solution.
Patent TW-I280745-B (TW)
Title: Pulse width detection circuit
Inventor: MIZUNO NOBUYASU
IPC: H03K5/26
Filed: 2002-12-30
Granted: 2007-05-01
Abstract: A pulse width detection circuit for accurately detecting a pulse width from an input signal. The detection circuit includes a first filter circuit for receiving the input signal and generating a first processed signal. The first processed signal includes a first component having an AC component of the input signal and a second component having a low frequency component or a DC component of the input signal. A second filter circuit is electrically connected to the first filter circuit. The second filter circuit includes a high pass filter for receiving the first processed signal and generating a second processed signal. A binary conversion circuit is electrically connected to the second filter circuit to receive the second processed signal and generate the binary signal.
Patent TW-I272053-B (TW)
Title: A heat sink and method for constructing the same
Inventor: BOUDREAUX BRENT A
IPC: H01L23/40
Filed: 2003-02-11
Granted: 2007-01-21
Abstract: A heat sink is constructed including at least one thermally conductive pedestal 104, allowing configuration of the heat sink to make contact with a plurality of heat-generating electronic devices 100 where the devices need not be co-planar. The pedestals 104 may be raised and lowered and lilted as needed to match the heights and tilts of the electronic devices. Within the heat sink is a cavity 118 above the pedestal 104 that may be filled with a thermally conductive material, such as solder, or a thermally conductive liquid, during construction to create a low thermal resistance contact between the pedestal 104 and the heat sink fins 120. Also, thermally conductive material, such as thermal paste or a thermal pad, may be used between the heat generating device and the pedestal to create a low thermal resistance contact.
Patent TW-I254718-B (TW)
Title: Block copolymer
Inventor: TAKESADA KENTARO
IPC: C08F220/06
Filed: 2003-02-12
Granted: 2006-05-11
Abstract: The invention relates to a block copolymer (A) composed of a (meth)acrylic polymer block (a) and an acrylic polymer block (b). It is preferable that the temperature for 5% weight loss be enhanced to 300 DEG C or above by incorporation of a monomer having a high-cohesion functional group (such as carboxyl) into the block (a) through copolymerization or that the tensile strength, the hardness as determined according to JIS K6253 by the use of type A durometer, and the compression set as determined under the conditions of 70 DEG C and 22 hours be adjusted by the above incorporation to 3 MPa or above, 50 or below, and 45% or below, respectively. The block copolymer (A) is excellent in thermal decomposition resistance and exhibits an excellent compression set even at high temperature. Further, the copolymer (A) is usable as automotive flexible material and is excellent in softness, adhesion, oil resistance, weather resistance, heat resistance, recyclability, tensile properties, and wax remover resistance.
Patent TW-I224359-B (TW)
Title: Thin-film forming device and method, liquid crystal display and device and method for manufacturing the same, thin-film structure and device and method for manufacturing the same, and electronic machine
Inventor: SAKURADA KAZUAKI
IPC: B05C9/12
Filed: 2003-02-20
Granted: 2004-11-21
Abstract: The present invention relates to a thin-film forming device and method, liquid crystal display and device and method for manufacturing the same, thin-film structure and device and method for manufacturing the same, and electronic machine. The object is to provide a thin-film forming device and method, liquid crystal display and device and method for manufacturing the same, and thin-film structure and device and method for manufacturing the same, which can depress the material losses by using a droplet ejection head, and in addition, make the thickness of the entire film uniform. To solve the problem, there is provided a thin-film forming device 1 for applying a coating solution L containing a film-forming material dissolved or dispersed in a solvent onto a substrate SUB. On the substrate SUB, there are provided an ejection mechanism having a droplet ejection head 2 for ejecting the coating solution L, a moving mechanism 4 capable of relatively moving the positions of the droplet ejection head 2 and the substrate SUB, a control unit C for controlling at least one of the ejection mechanism and the moving mechanism 4, and a solvent vapor supply mechanism 5 for supplying a solvent vapor to the vicinity of the coating solution applied onto the substrate SUB.
Patent TW-I282598-B (TW)
Title: Wafer container for holding a plurality of wafers, method for restraining a plurality of wafers in a front opening wafer container, and method for disengaging wafers from an elastomeric wafer restraint cushion in a front opening wafer carrier
Inventor: BORES GREGORY
IPC: H01L21/673
Filed: 2003-02-26
Granted: 2007-06-11
Abstract: A wafer container having a container portion with an open front for receiving and removal of wafers includes a door with a cushion system that utilizes a unique wafer restraint system and structural features to provide maximum protection for the wafers and preventing rotation of said wafers. A feature of the door is that the front of the door covers have a pair of latch cavities on the outwardly facing side of the door. The latch cavities for receiving two latch mechanisms with latch members that extend out the upper and lower peripheral edge of the door. The latch mechanisms are covered by a pair of door panels that utilize hooks that attach to the peripheral edge of the door and further attach with posts near the vertical midsection. The latch cover at the peripheral side edge and at the vertical midsection of the door provides stiffness and resistance to bending of the door. In a preferred embodiment, the attachment of the door panel at the peripheral edge utilizes hook members on the door panel that extend through slots on the peripheral side. Press fit connectors and aperture combinations are preferably utilized to connect the edge of the latch panel approximate the mid-portion of the door.
Patent TW-I254932-B (TW)
Title: Method of seeking error control for optical drive
Inventor: HSU JEN-YU
IPC: G11B7/09
Filed: 2003-04-10
Granted: 2006-05-11
Abstract: The present discloses a method of seeking error control for an optical drive. At the beginning of a track on action, a center error signal is detected. When the magnitude of the center error signal reach a predetermined value, the track on action of a pick up head is abandoned. Then, move the pick up head back to the canter position of a movable region by activating a center servo control system or not providing any control force on the pick up head. When the pick up head moves to the center position of the movable region, another track on action is activated.