Patent GB-1130902-A (GB)
Title: Computing machine
Inventor: CROWTHER GERALD OFFLEY
IPC: H03K3/78
Filed: 1964-10-20
Abstract: 1,130,902. Electronic calculators; pulse counters. MULLARD Ltd. 17 Jan., 1966 [20 Oct., 1964], No. 40712/64. Heading G4A. An electronic computing machine operable on the decade system to manipulate numbers containing up to 8 digits comprises a plurality of chains of decade counting-tubes, a keyboard, a continuously-running source of counting-pulses, a first frequency-dividing stage for dividing counting-pulses into trains of ten pulses so that a tube in any selected stage of a selected counting-chain can be stepped for up to ten positions so as to add up to ten digits to that stage, a second frequency-dividing stage having a division ratio of 8 and operable to select counting-periods each containing 10s counting pulses so that in each counting-period a multidigit number can be added into the selected counting-chain, and a third frequency-dividing stage operable to select computation periods each comprising ten counting-periods so that in each computation period a multi-digit number can by a process of repeated addition be multiplied by any digit and added into the selected counting chain, the third frequency-dividing stage also being operable to mark such computation periods by a first output signal at a first output terminal and to respond to signals from the keyboard to select within a computation period as many counting-periods as are required to perform a computation and to mark each selected counting-period by a second output signal at a second output terminal, together with a control unit responsive to the first output signal from the third frequency-dividing stage to control the timing of trains of counting-pulses and also operable in response to signals from the keyboard to determine the number of computation periods necessary to perform a complete arithmetical operation. As shown (Fig. 3), counting pulses are derived from a free-running blocking oscillator BO1, divided by 10 by decade counter DV1 and applied to a second blocking oscillator BO2. During periods when no computation is in progress, the master control MC opens AND gate AG1 (through AG3) so that pulses from BO2 may pass without division to a pulse envelope generator PE as described in Specification 40711/64. Generator PE comprises a decade counter DV3 (cold cathode stepping tube) and a manual keyboard KB and functions to provide one pulse at output PE1 for every 10 input pulses and a number of pulses at output PE2 corresponding to the particular key depressed. During computation periods (e.g. during multiplication involving successive addition up to 9) the master control MC opens gate AG2 to bring divide-by-twelve counter DV2 into operation (there are twelve decimal stages in the accumulators) whereby gate AG1 is opened for a twelfth of the time and the input to generator PE is thereby divided by 12. Each output pulse from PE1 now corresponds to 1200 pulses from BO1 thus providing a computation period sufficient to multiply any twelve digit decimal number by nine and allow one spare counting period for incidental operations. A modified arrangement is illustrated in Fig. 1 (not shown), and detailed circuit diagrams are given in Figs. 4-8 (not shown).