Patent GB-1344179-A (GB)
Title: Error detection systems for use with a moving magnetic storage device
IPC: H04L27/08
Filed: 1971-08-04
Abstract: 1344179 Error detection system INTERNATIONAL BUSINESS MACHINES CORP 4 Aug 1971 [28 Sept 1970] 36615/71 Heading G4C An error detection system adapted to read data signals recorded in blocks on a magnetic storage medium, the beginning of each block being indicated by a preamble of a predetermined pattern of bits, comprises gating means arranged to gate signals read from the medium by a transducer and having an amplitude above a gating threshold to a control unit which includes a first detector arranged to detect the preamble, a second detector arranged to detect errors in the signals, and a control device reponsive to the two detector outputs to control the gating threshold of the gating means. As described data is read from a tape or disc by read head 10 and is hard limited by circuit 12 so as to generate a two level pseudo digital signal on line A. The signal is compared with a threshold, established in accordance with control signals on line C, in sensor 14 whose output controls the gating of the read signal on to line 27. There are effectively three threshold levels, which may be, for example, 30% and 10% of nominal, both set by circuit 14, and a O threshold set by an enabling signal on line 22. In the embodiment described nine tracks are read, the tracks being divided into three zones of three. The circuitry for a single track and part of the circuitry for a zone of three tracks is shown. In operation an envelope sensor 30 detects the block preamble (see below) and enables gate 32, the sensor being set initially to the 30% threshold level. Gate 32 also monitors similar signals from the other tracks in the zone and the presence of phase and parity error signals for the zone via inverter 36. In the absence of errors latch 34 is set and AND gate 16 is continuously enabled to set an effective zero threshold. However when a phase or parity error occurs latch 34 is reset to remove the zero threshold gating signal. The error signal also sets latch 42 which causes a 10% of nominal threshold to be set in sensor 14. In the case where a degradation of amplitude occurs in the absence of a phase error the output of envelope sensor vanishes and AND gate 46 is enabled. Thus if a parity error subsequently occurs AND gate 46 conducts to set "DEAD TRACK" latch 48. Phase errors are detected by data detector 28 whose output sets latch 54 (this signal also being used to enable OR gate 38 and reset latch 34, see above). Latch 54 remains set for a fixed number of bit periods determined by a single shot 60. If during this period a parity error occurs AND gate 46 conducts and latch 58 is set thus preventing latch 54 from becoming reset at the end of the period. The 10% threshold (set via latch 42) is thus maintained for the remainder of the readout. If no parity error occurs latch 58 remains reset and is effective to reset latch 54 and restore a O threshold at the end of the period. Envelope sensor.-The envelope sensor, Fig. 4 (not shown), consists of a comparator having a signal input and a reference input and a capacitor in a feedback loop between the output and signal input. The preamble of 2000 builds a charge on the capacitor so that the comparator eventually produces on output in the presence of the preamble which further charges the capacitor and latches the circuit thus indicating that a record block is being read. If the amplitude of the signal decreases or the signal ceases the capacitor will eventually discharge until the comparator no longer produces an output. Further details.-The Specification contains a detailed description, Fig. 6 (not shown), of a suitable data detector which includes delays, single shots, comparators and gates to indicate phase errors, to decode the data in which a positive transition in the centre of a bit cell indicates binary one and a negative transition binary zero, and to derive clock signals from the data.