Patent GB-1493466-A (GB)
Title: Apparatus for receiving data signals
IPC: H03H17/00
Filed: 1975-01-28
Abstract: 1493466 Adaptive transversal equalizers WESTERN ELECTRIC CO Inc 28 Jan 1975 [30 Jan 1974] 3560/75 Heading H4R Phase distortion in received data modulated on quadrature phases of a carrier is corrected by a transversal equalizer 30 whose quadrature outputs y p , y q  are quantized 50 and fed together with y p  y q  to means 80 which generates quadrature error signals e i , e q  to control the equalizer 30 and signals which are utilized 90 to control the phase and frequency of the demodulating signal #. The system is designed to minimize intersymbol interference, frequency offset in the demodulating carrier and "jitter" owing to spurious phase disturbance between adjacent data pulses. The data is modulated in amplitude to a fourlevel quadrature signal (QAM) or in phase as cosine and sine of half multiples of #/4. In the phase modulated system, only the real part of a complex function is transmitted, I and Q being in phase and quadrature components respectively of data on a carrier at frequency # c . The phase jitter and frequency offset introduce errors #(t) and #t which need to be compensated in the demodulating carrier frequency # c . The received data r(t) over line 10 is such that splitting at 20 (e.g. by Hilbert transformation) into in-phase and quadrature components r v , r recovers the real quadrature components of the transmission. The equalized outputs y v , y q  are demodulated to base band frequencies by the demodulating carrier to produce at time nT This will completely cancel intersymbol interference provided # exactly matches the distortion; if it includes an error #, corresponding to rotation of the components I, Q from the ideal received vector (formed by quantizing to I, Q) there are distortion components of the form therefore # is updated in each baud interval T to correspondingly update the equalize tap coefficients and the phase reference by the algorithm which is derived from the gradient of a symmetrical expression for the squared error between the actual and ideally equalized outputs; # c T accounting for the phase change in # c  over one baud interval, α being an incrementing constant chosen for compromise between noise, stability and jitter tracking and # arising from the gradient function. The squared error is represented by and its gradients with respect to the in-phase and quadrature tap coefficient sets C and D are represented by the tap coefficients C, D being updated once in each baud interval by equal decrements #. The gradient of the squared error with respect to # may be expressed as or 2(e i y q  - e q y i ) which leads to an expression for # as follows The arrangement of Fig. 1 is organized so as to perform the above calculations. In particular, the equalizer 30, because of the interaction between inphase and quadrature tap signals, requires either to have a total of four delay lines and coefficient processors or, as shown in Fig. 6, to include switches 100 allowing time sharing of quadraturerelated delay lines 82, 83 and coefficient processors 22, 23 in each baud interval. The tap outputs 84, 85 are correlated 96, 97 with e q  and 94, 95 with e i  and cross-connected, using an inverter 96A to produce updated tap coefficient values in stores 98, 99 leading to equalized output signals y p  y q  on lines 102, 103 of the form: where C<SP>T</SP>, D<SP>T</SP> are the transposed column matrices of the tap coefficients C, D corresponding to received components r i , r q . The circuit may be arranged (Fig. 2, not shown) so that a first demodulation stage precedes the equalizer and is controlled by a first signal # 1  to compensate for slowly varying jitter and offset whilst a second stage (200) simultaneously effects demodulation and compensation for higher frequency defects using a second control signal # 2 , both # 1  and # 2  being derived from respective oscillators driven by control signals # 1  and # 2  of similar form to those utilized above. Since # 2  is very small, approximations of the kind may be employed for simplicity. Figs. 3 and 4, and Fig. 7 (all not shown) enlarge on Figs. 1 and 2 respectively to illustrate the manner in which the circuit blocks are constructed and interconnected to perform the necessary calculations.