Patent GB-767692-A (GB)
Title: Improvements in or relating to electronic calculating apparatus
Inventor: WOODS-HILL WILLIAM
IPC: G06F7/52
Filed: 1953-05-29
Abstract: 767,692. Digital electric calculating-apparatus; electric digital-data-storage apparatus. BRITISH TABULATING MACHINE CO., Ltd. April 27, 1954 [May 29, 1953], No. 14993/53. Class 106 (1). [Also in Group XL (c)] In an electronic calculating-apparatus having means for storing multiplier, multiplicand and product values, the multiplier and multiplicand values are simultaneously replaced by half and double the stored values, respectively, and when the multiplier value is odd, the stored product and multiplicand values are read out to seriesmode adding means and the sum fed back to the product, control means effecting repeated cycles of halving, doubling and selective addition at least until the multiplier value is reduced to zero. General.-The electronic calculator described is adapted to use a punched-card machine for data input and output as described in Specification 673,759, and includes an arithmetic unit, Figs. 1 and 2, for performing addition, subtraction, multiplication and division by ten (or column shift) on decimal or sterling amounts, and a control unit (partly shown in Figs. 3 and 6) for providing timing and gate-control pulses and for programming, e.g. to enable a combination of arithmetic operations to be performed. The arithmetic unit comprises multiplier, multiplicand and product stores 1, 2 and 3, each comprising four shifting registers corresponding to code components I, 2, 4, 8, respectively, of the digit values, and five auxiliary capacitor stores such as 33. Reference is made to non-uniform rotations other than sterling, e.g. Indian currency, and to a magnetic drum store. Circuit elements; shifting registers. The calculator circuits consist primarily of bi-stable double triode trigger circuits, such as 40 (1), Fig. 7, positive and negative-input coincidence gates (see Group XL (c)), such as 343 and 46 (1), respectively, inverters, such as 326, cathode followers, such as 340, two and three-input adders, such as 334, and 335, as described in Specification 767,693, and shifting registers. Fig. 13 shows two consecutive trigger stages V7L, V7<SP>R</SP> and V8<SP>L</SP>, V8<SP>R</SP> of a shifting register to which negative shift pulses are applied over line 521. When the triode V7<SP>L</SP> or V7<SP>R</SP> conducts, the lower anode potential enables a corresponding diode 524 or 523, connected through a resistor 527 to a 50 v. supply line, also to conduct and thus transmit the shift pulse through capacitor 526 or 525 to the grid of V8R or V8<SP>L</SP> to set stage V8<SP>L</SP>, V8<SP>R</SP> in the condition of the preceding stage. Data entry. The multiplier is read from a punched card by brushes 4, Fig. 2, in the form of differentially timed electrical impulses which discharge capacitors 549, Fig. 17, in storage units 5 to which scanning pulses are applied sequentially over lines 6 for every card index point, the capacitors being charged through cam-controlled contacts 550. If a capacitor is discharged, the scanning pulse is allowed to pass through a diode 552 to the grid of amplifier V14, the output of which is fed via line 553 to an inverter or amplifier 7, Fig. 2, whose output is applied through gate 8 to four gates 9 in parallel, connected respectively to the four shifting registers 1(1), 1(2), 1(4), and 1(8) of the store 1. (A group of four elements, such as 9, is indicated by a dot inside the circuit symbol.) The gates 9 are controlled by code-translating voltages on lines 10 determined by four cam-controlled contacts associated with the card feed; thus during the " 9 " index point only the gates 9 associated with registers 1(1) and 1(8) are opened, and so on. Nine shift pulses on line 9C, synchronized with the scan pulses on lines 6, are applied to the registers of store 1 through gate 12 and inverter 13, and also control gates 14 through a cathode follower 11 whereby the register outputs are returned to the inputs through further gates 15. The multiplicand is similarly read by brushes 16 into temporary stores 17 and coded and entered into store 2 under control of scanning pulses on line 18 and shift pulses on line 14C. Values to be read from the card into an auxiliary store such as 33, Fig.. 1, are stored on relays whose contacts control entry in coded form via lines 60. The auxiliary stores are generally similar to the temporary stores 5, 17. Data output. The value in store 3, Fig. 1, representing a computation result, may be decoded and punched on the card from which the factors in the computation were obtained. The value is applied via cathode followers 430 and inverters 431 together with the digit-representing voltages on lines 10, to a coincidence or comparison circuit 432 which comprises four twoinput binary adders with a common sum output. When coincidence is detected, the circuit will apply a positive pulse to one grid of each of a series of gas-filled tetrodes 435 whose anode circuits are plugged through sockets 436 to punch magnets (not shown) associated with the desired card columns. This will cause that tetrode to fire which receives a coincident positive scanning pulse from a line 110, scanning pulses (similar to those on lines 18, Fig. 2) being applied sequentially via these lines to the second grid of the tetrodes. Read-out may be suppressed by applying a positive potential on line 434, the consequential negative output from inverter 433 holding the tetrodes cut off. Arithmetic unit; interconnections. The outputs of 1 and 2, Fig. 2, may be gated to either of two highways 30, 31, Figs. 2 and 1, connected via sets of trigger stages 37, 40 (similar to those in the shifting registers) to the two inputs of an adding unit 29 whose output, applied through gates 46 to a highway 32, may be gated to the input of store 1, 2 or 3. For subtraction, the output of triggers 40 may be complemented in circuit 42 before entering the adder. The values on the auxiliary stores such as 33 may be gated to one of the highways 30, 31, as shown through 64, 164, 165, 166 and 62, scan pulses being applied to the store over lines such as 61. Complementing circuit. When complementing is required, a positive voltage on line A<SP>7</SP>, Figs. 1 and 7, closes gates 44(1), 44(2), 44(4) and 44(8) and opens gates 43(1), 43(2) and 43(4), which together with inverter 326 pass the complement of the value set up on triggers 40(1), 40(2), 40(4) and 40(8) to three-input adders 330-333 of unit 29. The complementing is effected by an arrangement of inverters and twoinput binary adders 321, 323 as shown, the carry outputs of 321, 323 being connected to inputs of 323 and inverter 326, and the sum outputs being connected to gates 43(2), 43(4) respectively. The arrangement is such as to form the elevens complement (for pence). For decimal values, when the nines complement is required, a " filler digit " of 2 is added by a negative voltage on line 322. For tens of shillings (when the binary complement is required) a further filler digit of 8 is entered on line 328. For the lowest denomination, an additional " 1 " is entered through line 353 and gate 350 into adder 330. Adding unit. The outputs of triggers 37, 40, Fig. 1, are applied through inverters 38(1), 38(2), 38(4) and 38(8), Fig: 7, and gates 44(1), 44(2), 44(4) and 44(8) or the complementing circuit, to three-input adders 330, 331, 332, 333 whose carry outputs are passed, respectively, to inputs of the next higher adder and a line 339 and carry storage trigger 337 which provides the third input for the first adder 330. An adder 346, controlled by the carry trigger 337 through inverter 348, ensures that the trigger is operated only if it is registering a carry digit different from that appearing at the output of adder 333, the trigger setting being effective during addi-. tion in the next higher denomination. The sum digit obtained from 330-333 requires correction, except for the " 1 " component, in accordance with the scale of rotation. The correction circuit, including gates 338 and 342- 345 and adders 334-336, is controlled by the " filler digit " lines 322, 328, and the correct sum digit value obtained from adders 330 and 334-336 is applied to output gates 46 (1), 46 (2), 46(4) and 46(8). Control unit. Positive and negative clock or timing pulses on lines C<SP>1</SP>, C<SP>2</SP>, Fig. 3, are obtained from multivibrator 82 through gates 84, 91, 92 and inverters. These pulses drive a primary timer or shifting register 81 comprising a ring of 16 trigger stages 81(x), 81(1) ... 81(15) which are operated in turn to mark control lines through cathode followers. In particular, stages 81(2)-8(15) control scanning lines 18, 110, Figs. 1 and 2, through cathode followers 105, and lines 61, Fig. 1, through cathode followers 106, the output of which is normally suppressed by a clamping circuit 108. The primary timer also controls the supply of shifting pulses to lines such as 9C, Fig. 2, through trigger circuits and gates (Fig. 4, not shown). For read-in and read-out, a trigger 409, Fig. 3, is operated twice for each card index point by cam-controlled contacts, thereby operating trigger 411 which in turn operates trigger 88 via line 101. The next pulse from 82 is allowed through gate 87 to reset 88 which then operates trigger 90 to open the gate 91, thus permitting a cycle of the timer, 81. At the end of the cycle a pulse from stage 81(x) on line 129 passes through gates 112 and 417 and resets 411. For the period of a card cycle allowed for calculation, trigger 447 is operated and in turn operates trigger 88, and a trigger 119 which applies a pulse to the first trigger stage 80(1) of a programme timer or shifting register 80. Each of the stages 80(1)-80(20) may be used to control a separate operation through a cathode follower 116, rectifiers 117 and plug sockets 118, and at the end of each operation the timer is stepped on by a pulse on line 114. This pulse is obtained from the output of a trigger 249, Fig. 6. which is reset by an en