Patent GB-1401276-A (GB)
Title: Methods of manufacturing semiconductor devices
Inventor: SHANNON J
IPC: H01L21/22
Filed: 1971-09-06
Abstract: 1401276 Semi-conductor devices MULLARD Ltd 28 July 1972 [6 Sept 1971] 41462/71 Addition to 1307546 Heading H1K In a method of manufacturing a semiconductor device in which impurity diffusion from a high impurity concentration region 14 to a lower impurity concentration region 20 is enhanced by the effect of bombarding radiation 19 incident on the region 20 and causing lattice damage therein, the crystal axes and radiation energy are chosen so that the incident particles channel through the crystal lattice at least as far as, but not substantially beyond, the boundary between the regions 14 and 20. In this way the lateral extent of the region 20 is more precisely controlled than would be the case if no channelling occurred. The radiation 19 is preferably protons, but may also comprise electrons, helium ions or donor or acceptor ions, the latter providing simultaneous bombardment enhanced diffusion and ion inplantation. The higher and lower doped regions may be of the same or opposite conductivity types. Fig. 4, illustrates the manufacture of a Si junction-gate FET in which current between source and drain electrodes passes vertically through channel portions of a <11D-oriented P-doped N-type epitaxial layer 12 bounded, and optionally surrounded, by P-type regions formed by channelled-bombardment enhanced diffusion of B from P<SP>+</SP>-type buried layers 14 in the N-type substrate 11. The regions 20 are made to extend right through the thickness of the layer 12 by commencing proton bombardment at an energy such that the channelling range just reaches the substrate 11 and subsequently reducing the proton energy so that the damaged region, and hence the diffused region 20, extends progressively further from the impurity-source region 14. A mask 17 of Mo or Nichrome (Registered Trade Mark) defines the lateral extent of the damaged regions. P<SP>+</SP>-type surface diffusions may also be effected into the windows 18 to ensure that the gate junction terminates beneath oxide layer 16. Source, gate and drain electrodes of Au/Sb alloy are applied respectively to the substrate 11, the regions 20 and the remaining regions of the epitaxial layer 12. For a <111> oriented wafer the radiation 19 may alternatively be caused to impinge obliquely upon the surface at such an angle that channelling may occur along the <110> axis. A further junction-gate FET is described (see Figs. 7-9, not shown) in which channel current passes horizontally through portions (40) of an N-type epitaxial layer bounded by P-type gate walls (38) formed in the manner of the invention. The channel portions (40) are entirely bounded by P-type gate portions constituted by the walls (38), the P<SP>+</SP>-type buried layer (35) from which the impurity for the walls (38) has been caused to diffuse, and a surface implanted region interconnecting the walls (38). The manufacture of a vertical bipolar transistor having a profiled collector impurity distribution beneath the emitter region, and of a lateral bipolar transistor the regions of which are formed by channelled-bombardment enhanced diffusion of impurities into an epitaxial layer from buried regions prediffused into the substrate, are also briefly mentioned.