Patent GB-1282444-A (GB)
Title: Irregular-to-smooth pulse train converter
IPC: H03K5/135
Filed: 1969-08-21
Abstract: 1282444 Control of stepping motors FUJITSU Ltd 21 Aug 1969 [21 Aug 1968] 41734/69 Heading H2J [Also in Division G3] A pulse distributer 100 of an electronic computer or numerical control equipment transmits command pulses to lines 101, 102, for operation of a stepping motor 107 in either direction. A converter 103 provides a pulse train whose frequency changes gradually, a drive circuit 106 switching the excitation of the motor in the desired sequence. One pulse distributer may be used for several motors together with a converter for each motor, or a single converter in common for all the motors. The converter comprises a register 702, which receives the command pulses and transmits a pulse train whose frequency is proportional to the stored value. A frequency converter 705 reads the stored value each time a pulse is fed through line 708 and determines whether a pulse is transmitted to output line 709. This pulse is also fed back to the register and reduces the stored value by one. The line 708 is associated with a timing pulse oscillator 706 and frequency divider 707. In another arrangement, a bidirectional converter has positive and negative input terminals connected to a mixer which prevents overlapping of command and feed-back pulses. A sign discriminator determines which input terminal of the reversible register receives the command pulse, Fig. 8 (not shown). Command pulses are applied to terminal 1001 connected to mixer 1002 receiving clock pulses on line 1003, so that a pulse whose duration corresponds to one clock interval is normally fed to line 1007. If a feedback pulse is present, AND gate 1005 is closed through inverter 1006 to prevent a pulse appearing on line 1007. Reversible counter 1008 comprises digital elements having outputs IR2<SP>0</SP>-IR2<SP>n</SP>, while oscillator 1023 is connected to differentiator 1024 for synchronism with the clock pulses. Counter 1037 has digital stages connected to converter 1022 which is also associated with the counter 1008, whereby the gate Ao, for example, receives the highest and lowest outputs of the counters 1008, 1037, respectively. The outputs of gates Ao-An are collected by gate OR and supplied to frequency divider 1044. In a modification the converter is of the bidirectional type, Fig. 12 (not shown). In a further embodiment, the content of a register 1627 in which command pulses are stored is repetitively added to a memory device 1628 at a fixed cycle. The contents of these units are transmitted to a full adder 1632. A mixer 1603, and sign discriminator 1604, are associated with a control circuit 1610 which processes input pulses and feedback signals. A variable frequency oscillator 1617 is connected to control counter 1618 and main control circuit 1620. When an address designation is issued to line 1622, a binary digit is delivered to line 1631. Writing of new information in register 1627 is achieved by opening gate 1625, an address designation being given to line 1622. Writing of information in register 1628 is performed by opening gate 1626, an address designation being issued from circuit 1620 to line 1623. The information is read by opening gate 1629. Frequency divider 1635 counts the overflow pulse and has its output connected to gates 1638, 1639. A circuit 1642 delays by one bit the carry signal at output line 1634 and feeds it back to the full adder 1632.