Patent TW-267280-B (TW)
Title: Two dimensional inverse discrete cosine transformer
Inventor: HWANG BOR-CHUAN
IPC: H04N1/41
Filed: 1995-03-18
Granted: 1996-01-01
Abstract: A two dimensional inverse discrete cosine transformer for processing one two dimensional NxN data comprises: one rate buffer with double output/input speed for facilitating the data input to the transformer; one first selector with one first input end, one second input end and one output end; in which the first input end is coupled with the rate buffer, and either the first or the second input end for input; N first registers in series connection, each of which has one input end and one output end; the first register is coupled with output end of the first selector by one input end, operating by adopting serial input one bit and parallel output N bits; one second selector with one first input end, one second input end and one output end; in which the first input end accepts the first bit of N bits output from the first register, and either the first or the second input end for input; N second registers, each of which has one input end, one first output end and one second output end, that is coupled with output end of the second selector by one input end, and coupled with output end of each first register without supplying the second selector input by the rest input ends in order to get one N bit input; in which each first input end of the front N/2 registers is coupled to generate one first bus, each second input end coupled to generate one second bus, each first input end of the back N/2 registers is coupled to generate one third bus, each second input end coupled to generate one fourth bus to make the bus with N/2 bit capacity; N parameter generators, each of which has one first input end, one second input end and one output end; in which each first input end of the front N/2 parameter generators is coupled with the first bus, each second input end coupled with the second bus, each first input end of the back N/2 parameter generators is coupled with the third bus, each second input end coupled with the fourth bus for generating parameters in each output end; N accumulators, each of which has one input end and one output end, and each input end is separately coupled with output end of the parameter generator, for accumulating parameters generated from the parameter generators; N/2 summer, each of which has one first input end, one second input end, one first output end and one second output end; in which each first input end is separately coupled with output ends of front N/2 accumulators, and each second input end is separately coupled with output ends of back N/2 accumulators; one first truncator coupled with output end of the summer for deleting overlong the most least significant bit, and supplying one output path to the second input end of the second selector; one row-column transpose buffer coupled with the first truncator for processing row-column transpose operation, and supplying one output path to the second input end of the first selector; one second truncator coupled with output end of the summer for deleting overlong the most least significant bit; and one rate buffer with double input/output speed for facilitating transposed data output from the device.