Patent GB-1385797-A (GB)
Title: Data transmission
IPC: H04B14/02
Filed: 1972-02-02
Abstract: 1385797 Data transmission systems; synchronizing TELEFONAKTIEBOLAGET L M ERICSSON 2 Feb 1972 [5 Feb 1971] 4941/72 Heading H4P  A PCM transmission link is used to transmit serial data of a lower bit frequency than the link but nominally there being a whole number of data bits per PCM digital word time interval, the serial data being sent as bits of a PCM word nominally in alternate long and short groups of lengths either side of the whole number, but on the bit frequency of the serial data varying slightly, consecutive long or short groups are sent as necessary, the PCM words containing a bit identifying the group length they contain, and for those containing a short group, two further bits indicating to a receiver whether overall the data bit frequency is leading or lagging its nominal frequency. In the arrangement disclosed there are six bits of serial data per PCM word time interval and the long and short groups of data bits are five and six bits long respectively. Fig. 4 shows  the PCM transmitter receiving serial data accompanied by bit timing pulses b and also PCM bit timing pulses d and pulses b of duration equal to one PCM word interval. Two registers 11A and 11B receive the serial data alternately under the control of flip-flop V11 controlling admitting gates A111, A112 and A113, A114. Electric circuit L1 having gates A119, A120 connected to the five-bit register postion with an inhibition input on the sixth register bit position and gates A121, A122 connected to the seventh bit position, switch flip-flop V11 after a PCM word interval defined by pulse E if five, but not six bits of the serial data have been received, thus registering a short group, but if six bits are received, then the seventh bit is awaited before switching the register, thereby registering a long group of bits. Depending on whether a five or a seven bit group is registered the flipflop V12 is set to a 1 or 0 output respectively which causes a 1 or 0 bit to be inserted via AND gates A124 or A125 into the eighth register bit position. Circuit 11C has a phase comparator K for comparing the serial data bit frequency pulses with a sub-multiple of the PCM bit timing pulses d obtained via variable divider VFD and provides a two bit output mn of 11, 01, or 10 for in phase, leading or lagging, which at predetermined counts of the divider sets the two bit information into bi-stables V13, V14, and alters the division ratio of the divider and is itself then reset. The two bit phase information is fed via leads k and 1 to AND gates A131, A132 for registers 11B and gates A129 and A130 for register 11A to be set in the sixth and seventh bit positions only for a five-bit registered group as determined by flip-flop V12 enabling the AND gates. The then registered groups are read out via gates A115 or A117 over line C. Fig. 5 shows a receiver for the same PCM transmission system having registers 21A, 21B which alternately receive PCM words f and PCM timing pulses g via AND gates A211, A212, and A214, A213 under the control of flip-flop V21 itself controlled by logic L2. A pulse is present on line h for the duration of the PCM word time interval. Any phase control bits in a PCM word containing a short bit group is read out via gates A229, A230 or A231, A232 which are activated only if a binary 1 is present in the eighth bit position thereby identifying a short group. The registers are read out alternately on to line W and bit timing pulses on to line Z via gates 215, 216 and 218, 219 under the control of logic circuit L2. Bi-stable V21 in logic circuit L2 switches over the registers after reading out five or seven bits if the eighth bit position contains a 1 or 0 respectively, thereby identifying a PCM word containing a short or long serial data group. Read out pulses are provided by generator 21C at the original bit frequency of the serial data presented to the transmitter. PCM timing pulses on lead u, enter a counter divider FD via an inhibiting AND gate A224. A timing circuit B2 provides successively three equal timing periods t1, t2 and t3 during which pulses on line u are gated into the counter divider FD. According to the phase information set in the sixth and seventh bit positions of a PCM word containing a short data group, which is read out by gates A229, A230 or A231, A232 and set in bi-stables V22, V23 causes or not causes according to the information one pulse to be inhibited or not inhibited during the timing periods t2, t3 whereby the average rate of pulses emitted by counter divider FB provides a timing signal at the original frequency of the serial data.