Patent GB-728293-A (GB)
Title: Synchronising arrangements for digital information systems using electrical pulse code and like signals
Inventor: BARKER RONALD HUGH
IPC: H04J3/06
Filed: 1952-02-25
Abstract: 728,293. Pulse code signalling. MINISTER OF SUPPLY. Feb. 13, 1953 [Feb. 25, 1952], No. 4924/52. Class 40 (5): A synchronizing pattern of digit signals is periodically interpolated in a train of information-bearing pulse signals, the pattern comprising a series of n digit signals of one of two types which, when they are represented as +1 type or -1 type, has an autocorrelation sequence of (2n- 1) terms, of which the middle term is equal to n and each end term is not greater than + 1, while none of the other terms is as great as n minus the number of terms it is removed from the middle term. The autocorrelation sequence of the pattern of n digits a 1  . . . a n  is the symmetrical sequence of (2n - 1) digits b 1 , b 2 , b 3  . . . b r  ... b n  ... b r  . . . b 3 , b 2 , b 1 , where This sequence is derived at the receiver by a pattern-recognizer and the large middle term isolated by an amplitude discriminator to provide the synchronizing signal. A considerable number of synchronizing patterns are given and claimed, one example of which is the sevendigit group + 1, + 1, + 1, -1, -1, + 1, -1, of which the autocorrelation sequence is -1, 0, - 1, 0, -1, 0, +7, 0, -1, 0, -1, 0, -1. This is stated to be an ideal pattern, whereas the seven-digit group +1, +1, -1, -1, +1, -1, having an autocorrelation sequence -1, 0, +1,. - 2, -1, + 6, -1, -2, + 1, 0, -1, is stated to be nearly ideal. In digital systems based upon a modulus greater than 2 or in pulse amplitude modulated systems the ideal pattern is the same as that for the binary system, except that the digits + and -1 are replaced by pulses having a predetermined positive and corresponding. negative potential level. Pattern generdtors. In one embodiment, seven synchronizing pattern digits are derived from the output of a trigger Z, Fig. 1, applied to a valve V1 connected to the output terminal t2 while the valve V2 connected to the same terminal receives the message digits from terminal t3. To perform the interpolation, a trigger pulse at terminal t1 reverses the condition of trigger X for the seven-digit period to gate off valve V2 by the output x and gate on valve V1 by the output xl. The trigger pulse is applied also to a chain of seven delay units D1 ... D7, of one digit period each, the output of which resets the trigger X and appropriate junctions of which are connected, through rectifiers R1 ... R4 to one or other of the triggering connections z, z<SP>1</SP> of trigger Z. As shown, the pattern generated is +1, +1, +1, -1, -1, +1, -1, as will be evident from the waveform diagrams at the various points of the circuit, Fig. 2. In a second embodiment, Fig. 3, the valves V1, V2 and trigger X with their inputs at t1, t3 and outputs at t2, x and x<SP>1</SP> operate as in the first embodiment. The synchronizing pattern is derived from a chain of three counter triggers A, B, C arranged to count with a modulus of seven by feeding back a pulse from output c<SP>1</SP> through rectifier W1 to the input of trigger A, when trigger C is first set. The input to the trigger A during the pattern period comprises continuous digit pulses from input t4 which are normally ineffective due to an overriding negative bias applied to trigger A from the output x<SP>1</SP> of trigger X. The waveforms appearing at the outputs a, a<SP>1</SP>, b, b<SP>1</SP>, c, c<SP>1</SP> of triggers A, B, C, during the pattern period are combined in valve V3 in such a way as to produce the desired pattern to apply to the grid y of valve V1. In another embodiment a 21-digit pattern is generated by adding a further two triggers to the counter arranged to count with a modulus of three. The third repetition of the seven-digit pattern generated by the scale-of-seven counter is inverted in polarity by an extra valve rendered operative by the change in polarity of an output of the last trigger in the scale-of-twenty-one chain, Fig. 7 (not shown). A synchronizing pattern which may be generated and recognized with simpler equipment comprises a number of repetitions of a simple pattern, sufficient to guard against chance occurrence in a random sequence, followed by a differently identified pattern, which may be the same as the others but in reversed polarity. A modification of Fig. 3, for generating such a pattern includes a binary counter stage Q, Fig. 9, between stages C and X, the feedback connection from output x to the counter input being removed, so that the triggers A, B, C produce a continuous output through valve V3 to the grid y of valve V1. The output s from a trigger S normally applies a bias to trigger Q so that it is not operated by pulses from output c of trigger C. When the trigger X is operated by the pulse from t1 the repeating pattern is inserted into the output at t2 through valve VI. After an adequate number of repetitions, trigger S is operated by a pulse from terminal t5, to allow trigger Q to change state to disable the direct connection from valve V3 to the point y and render the valve V4 operative to pass an inverted version of the repeated pattern to the same point. After one pattern of reversed polarity the next pulse from point c resets the trigger Q which resets the trigger S. Pattern recognizers.-A circuit for producing the autocorrelation sequence from an incoming seven-digit synchronizing pattern at terminal t7, Fig. 5, and producing a pulse at terminal t8 when the large middle term occurs, comprises a delay chain of six digit-period elements D1 ... D6. Connections from the delay chain to an amplitude integrator 7 are made through buffer elements B1 ... B7, some of which are phase-reversing and some non-phase-reversing, depending on the pattern to be recognized. In the example shown, the pattern -1, +1, -1, - 1, + 1, + 1, + 1 is used and elements B4, B5, B7 are phase-reversing so that at the instant when the pattern is completely present along the delay chain the large middle-term amplitude is present at the output of circuit 7 and is selected by an amplitude-discriminator 8, to form the synchronizing pulse at terminal t8. Recognition of a pattern which is the combination in various polarities of a simpler pattern is carried out by interposing a further delay chain and phasing buffers between the integrator 7 and discriminator 8, Fig. 8 (not shown). In a practical embodiment of the circuit of Fig. 5, the delay chain D, Fig. 6, has tappings connected, through resistors R61 ... R67, either to the grid of valve V61 or valve V62 according to the pattern to be recognized. The valves are arranged as a long-tailed pair, their currents flowing in opposition through a winding of transformer T1, the core of which is saturated by current through a bias winding 60. For the correct pattern completely present along the delay chain D the resultant of the two valve currents is sufficient to more than balance the bias current, the core flux reverses and a pulse appears at an output winding 61. In a recognizer responsive to the pattern produced by the generator of Fig. 9, the amplitude integrator 7, Fig. 10, feeds a resonant network 9, tuned to the repetition frequency of the synchronizing pattern (a), Fig. 11. It thus receives the pulses (b) which build up in amplitude (c) until they exceed the threshold 13 of a discriminator 10. Thereafter pulses (d) are fed to a gate circuit 11 through a delay 12 of one pattern duration, pulse (e). The gate 11 is opened to pass the first pulse from a pattern of reversed polarity to the output terminal t8. If absolute synchronization is not required, a short ideal pattern may be sent at regular intervals and accepted as correct only if received at the expected instant. At the receiver, the pattern recognizer 15, Fig. 12, generates a pulse whenever the pattern occurs on input terminal t9. The pattern is deliberately inserted at intervals of m digit periods. If no other pulse has occurred at the output of circuit 15 for some time, the gate 16 will be open and the pulse resets a counter 17 which is supplied with digit-frequency signals at terminal t4 and is normally reset at intervals of m digit periods. Resetting of counter 17 produces a pulse which is fed to a coincidence detector 18 fed also with the pulses from the recognizer 15. The detector responds in these circumstances and sets a flip-flop trigger 19 to close the gate 16. The restoration period of the trigger 19 is somewhat longer than m digit periods, but it will be reset if when the counter resets itself after m digit periods its output pulse coincides with a pulse from the recognizer 15. Thereafter no false patterns can upset the counter and the system remains synchronized, the output from the counter being used to derive the train of synchronizing pulses. Specification 717,114, [Group XIX], is referred to.