Patent GB-1251539-A (GB)
IPC: G06F15/02
Filed: 1969-10-28
Abstract: 1,251,539. Desk calculators. ING. C. OLIVETTI & C. S.p.A. 28 Oct., 1969 [28 Oct., 1968], No. 52839/69. Heading G4A. An electronic computer includes first and second working registers, a control keyboard comprising function keys and numerical keys, whose operation causes corresponding numbers to be entered in the first register, and a control arrangement such that the operation of a numerical key, immediately subsequent to the execution of a function, causes the number in the first register to be cleared therefrom and transferred to the second register. General arrangement.-A magnetostrictive delay line LDR holds 3 working registers A, R, M and 3 totalizing registers B, C, D, interleaved at bit level, and followed by a gap. Each register holds 24 characters, each consisting of 4 service bits and 4 bits forming a binary-coded decimal digit. The first service bit is set, during operation, in the first and last characters in the delay line LDR to start and stop an oscillator 9 providing system timing, thereby synchronizing delay line and system. The other three service bits indicate respectively presence of a digit, sign (the sign bit is written in all characters of the register), and decimal point. Of the 24 character positions per register, two are reserved for overflow carries during operation. The delay line contents are recirculated via a distributer 5 which applies the bits from a given register to a respective line LB, LC or &c., corresponding bits in different registers simultaneously. The bits pass through a switching network 6 to a parallel-to-serial converter 7 for re-insertion in the line LDR. The switching network 6 permits contents of one register to be added to or subtracted from another (in some eases) using a serial adder 12, or contents of a register transferred to another, or connection of a one-character shift-register J into the line of working register A (see below). The contents of register J can be incremented using adder 12. Data entry.-Decimal digits from a numeric keyboard 45 pass via a register 50 into shift register J which performs parallel-to-serial conversion and inserts them into register A, entry being high-order first, the digits going into the lowest-order character position and being shifted along, by virtue of the one-character delay introduced by the register J. A negative sign and decimal point can be entered on keys 46, 47 respectively. After one operand has been entered, depression of the lower left key on keyboard 49 ensures that the contents of register A will be transferred to register M as the next operand is entered into A. Printing.-Digits to be printed at 43 (e.g. results or operands), from register A or transferred into register A automatically for printing, or operation and register identification characters from keyboards 48, 49 supplied via register 50, are placed in turn into shift register J and successively incremented by one by passage through the adder 12 until a count of 16 is reached to produce a differentially-timed pulse to actuate a print hammer. Adder and associated circuits (Fig. 4).-Sign check unit 22 produces an ADD or SOTT signal according to comparison of the signs of the operands (the comparison result controlling a flip-flop A8) and whether addition or subtraction is required (signal F1 or F2 respectively). The serial binary adder 16 has inputs 13, 14, the first being inverted at 21 if SOTT is present, and produces sum Sb and carry Rb outputs, the sum output being inverted at 25 if SOTT is present. Two carry flip-flops A4, A5 are provided in series. A sum digit greater than 9 and less than 16 will cause a flip-flop 26 to provide a decimal carry to the next decimal digit position. A sum greater than 15 also provides such a carry but from Rb via A4, A5. The corrective sixes are provided from a circuit 75. A decimal carry from the most significant digit sets a flip-flop RF. As mentioned above, the adder can be used for incrementing contents of the shift register J (regarded as a binary number), register J feeding input 13, there being no signal at input 14, and circuit 64 providing incrementing pulses to carry flip-flop A5. Operation control.-Keyboards 48, 49 provide operation and totalizing register identifications on lines H1-H4 and H5-H6 respectively to register 50 for decoding at 51, 52. Keyboard 48 permits register A to be added to or subtracted from any totalizing register B, C or D, or any totalizing register to be printed with or without zeroizing (printing being preceded by transfer to register A, the previous contents of this being saved in M). Keyboard 49 permits multiplication, division or percentage operations using the contents of A and M, or squaring or squarerooting using the contents of A, the result being in A in all cases, the original contents of A sometimes being preserved in M. Keys P, Q respectively command multiplication and division as above, but with the result added into register D. The lower left key on keyboard 49, if pressed without previous data insertion (see "Data entry") interchanges the contents of A and M and prints out the final contents of A. Key R transfers the contents of R into A and prints them. Generally with the operations above, results and sometimes last operands inserted and intermediate results are printed automatically. The middle key of keyboard 49, if pressed with a two-operand operation key of keyboard 49, causes the contents of register C to be transferred into register A as the respective operand, but if instead it is pressed with the lower left key of keyboard 49, it zeroizes C and copies the contents of A into it. Before a basic arithmetic operation is performed, the two operands are aligned automatically, using shift register J to produce shift until the decimal point is in the required position. Multiplication and division.-The multiplicand and multiplier in registers A and M respectively are aligned, then the multiplicand is complemented and transferred into register R where each digit in turn is incremented to capacity with addition of the multiplier in M into A, then relative shift is performed. Division is similar, using repeated subtractions of the divisor in M from the dividend in A with incrementing of register R, and relative shift. Square-rooting.-With the operand in register A and with register M zeroized, a 1 is put in M beneath the most significant digit of the operand if the number of digits is odd or beneath the second digit if even. Successive odd digits 1, 3, 5 &c. are added to M and subtracted from A, until A is less than M, R forming a count of the number of subtractions. Squaring.-This is done by multiplication, after copying the operand in A into M.