Patent GB-1433254-A (GB)
Title: Digital telecommunications switching systems
IPC: H04L12/52
Filed: 1973-06-01
Abstract: 1433254 Data transmission; exchanges GENERAL ELECTRIC CO Ltd 29 May 1974 [1 June 1973] 26230/73 Heading H4P A line circuit for use in a digital switching system converts an anisochronous, i.e. non- uniform dinatron 2 state, e.g. telegraphy, signal into a succession of binary words and reversely, to enable anisochronous data to be handled by switching equipment similar to that for p.c.m. The line circuit connects input (output) signal paths to input (output) highways and comprises sampling an input signal path of a clock pulse frequency to produce a succession of digits, equal to 1(0) when the input signal is in one (other) state, entered cyclically into a first register having integer n>1 locations, which digits are read out periodically and parallely on to the input data highway. The second highway feeds n-bit words parallely into a second register, contents being read out cyclically and serially to a staticizing means, e.g. a steering bi-stable converting is (0s) into a first (second) state for application to the output signal path. The clock pulse frequency should be substantially higher than the switching speed of incoming signals to avoid sampling errors. In the arrangement described, a group of line circuits are connected to a common input and output highway with inputs scanned cyclically causing content of first registers to be placed in turn on to the common highway forming a T.D.M. signal, a second scanning means cyclically causing words on the output highway to be read into second registers of line circuits. Preferably first and second scanning means are each able to scan line circuits in any selected order; this enables any input signal to be switched to any selected one output signal path. A telegraph signal on path 10 is converted into 8-bit words and applied to input highway 12 through a level changing interface 18, e.g. a voltage divider, also AND 22 and OR 22 to 8 stage register 24, content of which can be transferred through AND 26 parallely to input highway 12. Operation is controlled by bi-stable circuit 46 which in the set condition activates ANDs 20, 38 and disables AND 44. In this mode a telegraph signal, e.g. Z (a) causes a series of 1s (0s) to be clocked into register 24 and wire 28 is pulsed every 125 microseconds to clear R24 before next read pulse is received. In the reset condition of 46, states of ANDs 20, 38, 40 are reversed and content of register 30 is routed back through bi-stable circuit 36 to 24 for a test procedure (not disclosed). Reversely, signals on highway 14 through register 30 can be placed on path 16 by an operation converse to the forward direction. In the embodiment described 256 input line circuits are provided timed by a switching arrangement 48 which pulses wires 28 to fill 256 cyclic time slots of 125 microseconds, and similarly output timer 68 causes demultiplexing. The multiplexing is described in greater detail with reference to Fig. 2 (not shown) and includes a circulating register holding 256 words of 8-bits. Fig. 3 (also not shown) illustrates a method of connecting any input highway (70) to any selected output highway (72) by means of an appropriate one of a matrix of crosspoints switches (74) associated with a 256 position circulating address memory (76). To reduce multiplicity of wiring arid switches (74) parallel/ serial/parallel conversion may be performed between line circuits, detailed arrangements for this not being particularly disclosed.