Patent SE-326388-B (SE)
Inventor: PICHOFF Y
IPC: G01R19/255
Filed: 1963-10-04
Abstract: 1,061,481. Electric selective signalling. COMMISSARIAT A L'ENERGIE ATOMIQUE. Oct. 3, 1963 [Oct. 4, 1962; Oct. 26, 1962; Nov. 2, 1962], No. 38889/63. Heading G4H. [Also in Division H3] In a voltage digitizer of the type in which clock pulses are fed to a counter until equality is obtained between the input voltage and a ramp voltage, the input voltage is stored in a capacitor (2, Fig. 2, not shown) and compared with a ramp voltage produced by the charging of a capacitor (16) from a D.C. source through a resistor, an additional voltage proportional to and higher than that across the latter capacitor being imposed across the resistor. Referring to Fig. 2 (not shown), an input pulse (I) the peak amplitude of which is to be digitized opens a normally-closed switch (24) shorting the second capacitor (16), to initiate the ramp, and the additional voltage is provided by an amplifier (22) across a resistor (15). It is proved that by suitable choice of circuit parameters the time between the arrival of the pulse (I) and equality at the comparator can be made strictly proportional to the peak amplitude of the pulse (I), despite the tendency of the capacitors (16 and 2) to charge and discharge exponentially respectively. Referring to Fig. 3 (not shown) a modified form of ramp generator is shown in which the switch is a transistor and the amplifier is replaced by a unit (28) in which the D.C. source is earthed through an R.C. series circuit (30, 31) and the input pulse (I) de-shorts a capacitor (31) at a transistor (34). A feedback path comprising a transistor amplifier (38) is connected across the resistor in the R.C. series circuit (30) and also provides the output from said unit (28). Fig. 4 (not shown) shows full details of the comparator and the means through which the input pulse is fed to its storage capacitor (here labelled 49): the input pulse in fact passes along each of two parallel channels, each including a triode and diode and one including a delay line, to compensate for any effects of very small input width. The above arrangements may be used for measuring the interval between two short pulses on separate channels by using a ramp generator started by the first pulse and stopped by the second for providing the input pulse to the storage capacitor, the ramp generator being triggered by the first pulse as also is the clock pulse generator providing pulses for the counter (Fig. 5 or 7, not shown). The first pulse delayed may also discharge the storage capacitor in preparation for the next measurement (Fig. 11, not shown). The transit time of a particle in a pulsed accelerator may be measured by using a pulse representing the particle as one of the two pulses and a spike from a reference sine wave as the other. The transit time of a pulse through a stretcher may be measured (Fig. 12, not shown) by sending a series of pulses along two channels in parallel, the first channel comprising a delay and the second comprising alternately a direct line and the stretcher. An almost identical system (Fig. 13, not shown), in which, however, the stretcher and direct line are replaced by two slightly different delays, can be used to measure the resolving time of the system of Fig. 7 (not shown). Fig. 14 (not shown) shows a similar system for measuring coincidences between different energy γ-ray photons emitted by atomic nuclei and detected by scintillators. The time intervals between an initial pulse and each of n final pulses can be measured by the system of Fig. 15 (not shown). Referring to this Figure, ramp generators (235, 4) producing more and less steeply rising ramps respectively, and a clock pulse generator (5), are all triggered by the initial pulse. Electrostatic memories (3 1 , <SP>3</SP>2<SP> ... 3</SP>n) store the values of the ramp from the first generator (235) at the instants of arrival of the corresponding n final pulses.. The voltages stored in these memories are compared in comparators (6 1 , 6 2  ... 6 n ) with the ramp from the second generator (4) and on equality each comparator closes a corresponding gate (255 1 , 255 2  ... 255 n ) which was allowing clock pulses (5) to enter a corresponding counter and display system (7 1 , 7 2  ... 7 n ). Besides the n measurement channels, a similar control channel (C) is provided for calibration purposes. In this latter channel, the initial pulse delayed (256) takes the place of a final pulse. Fig. 17 (not shown) shows a system for measuring a long time interval between two pulses. The first input pulse starts a first duration-to-digital converter and opens a gate so that the next pulse from a clock pulse generator can stop the converter and open a gate to pass succeeding clock pulses to a counter. The second input pulse gates the following clock pulse to a second duration-to-digital converter to start it and also passes through a one-clock period delay to stop the second converter. The clock pulse which started the second converter and subsequent clock pulses are prevented from reaching the counter. The outputs of the converters are added into the counter.