Patent GB-1221725-A (GB)
Title: Queuer control system
Inventor: QUESTA CHARLES ROBERT
Filed: 1968-06-13
Abstract: 1,221,725. Memory access control system. BURROUGHS CORP. 13 June, 1968, No. 28168/68. Heading G4C. A queuing system comprises a memory stack (a column of word storage locations) in which words are stored in the lowest available locations and means for selecting and transferring words between the stack and a register and from the top of the stack to a different location. Access request words for a sequential type memory (such as a magnetic disc unit) are stored in contiguous locations in a static memory from which they are repeatedly read in turn and compared with addresses of the sequential memory as the locations corresponding to these addresses become available for read-out, all stored access request words being compared with each sequential memory address in turn and a condition of equality causing the corresponding access request word to be utilized and its previous position in the static memory to be filled by another access request word in the memory so that the stored words are again arranged in contiguous locations. As shown (Fig. 2), a static memory 20 which is capable of non-destructive read-out comprises a matrix of flip-flops for storing 48 words of 48 bits each. New access request words from a computer (not shown) are loaded into memory 20 by way of two 48-bit information registers 25 and 21. A 6-bit address register 23 is coupled to the memory 20 by way of a decoder 24. Read and write select lines 26 and 27 are also connected to the decoder 24 whereby a single row of the memory 20 may be selected for transfer of information to or from the register 21. Address register 23 is also connected to a further 6-bit register 22 in such a way that the contents of these registers may be interchanged. In operation, access request words are stored in contiguous rows of memory 20, starting with the bottom row (00), with the register 22 holding the address of the top row in use. Whenever a new word is to be loaded, the contents of registers 22 and 23 are interchanged, the top row address in register 23 is incremented by one, the new word is written into the corresponding row of memory 20 and the contents of register 22 and 23 are again interchanged. To compare the contents of each row in turn with each sequential memory address as its corresponding storage location becomes available for read-out the top address is transferred to register 23, the corresponding row is read into register 21 connected to a comparator 13 (Fig. 1, not shown), the address in register 23 is decremented by one and the next lower row read-out for comparison. This continues until the contents of register 23 reach unity whereupon the top address is again transferred to register 23 and the above procedure repeated. This routine may be interrupted whenever an equality comparison is obtained or a new word is to be stored from the computer. After an equality comparison, the corresponding access request word is utilized and the remaining stored words compressed by interchanging the contents of registers 22 and 23, reading the top word into register 21, decrementing the top address in register 23 by one, interchanging the contents of registers 22 and 23 again and writing the previous top word into the row previously occupied by the utilized word.