Patent GB-1534131-A (GB)
Title: Device for the determination of the direction of propagation of a plane wave
IPC: G01S3/807
Filed: 1975-12-10
Abstract: 1534131 Radio direction finding COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 10 Dec 1975 [10 Dec 1974] 50676/76 Heading H4D In a modification of the radio direction finder described in Specification 1,377,574 for the avowed purpose of providing an arrangement for distributing the outputs of the codes 1<SP>1</SP> ... H' to the input of the delay device-adder chain 40 or to the lateral input of a required one of the adders 41, which arrangement is simpler than the N multiplexers therein provided, the H outputs of the H detectors, which may be radio or sonar, are sampled and memorized, the memorized outputs being made collectively available on a bus-bar system and the outputs on the bus-bar system are further sampled at the clocking rate F H  of the cells in the delay devices under the control of a multiplexer/address register control means, to distribute the outputs to said device input and/or lateral inputs. In a first arrangement, Fig. 2, the sampling and memorizing means comprise an H stage shift register 200, each stage receiving the output of a respective decoder 1<SP>1</SP> ... H' and the register being filled at the frequency F H . The output of the shift register feeds a single bar bus-bar system 300 at a rate H.F H  by means of clock pulses from clock 100. N Buffer memories 401-404 each comprise a feed input 411, tapping the bus-bar, a control input 421 enabling the feed input (timing the sample) and an output 431. The output of memory 401 is connected to the input of the first delay shift-register 31 of the chain and the output of each of the n - 1 other memories is connected to the lateral input of a respective one of the n - 1 adders 41. The control inputs are ordered by respective stages of the H- stage address register 510 to provide an enabling signal for the feed input every 1/F H  seconds. The buffer memories are emptied at a rate of F H . Each of the H stages of address register 510 is connected for input to a respective output of a multiplexer 530 which causes a 1 signal to appear at one of said outputs under the control of a counter 540, the said one output being changed every 1/F H  second and the I signal having been fed to the stage of the address register being circulated through the register at the shift frequency Fd = HF H . In a second arrangement, Fig. 3, the sampling and memorizing means comprises k input shift registers 250 (k is a sub-multiple of H, e.g. 8 with H = 128) each having H/k stages, each stage being fed by a respective coder 1<SP>1</SP> ... H'. The registers are filled at a frequency F v =F H /k and read every 1/Fv with each register having its output applied to a respective bus-bar 350. N, e.g. 4, pairs of sampling shift registers 420 having k stages, have their stages connected to tap respective selected ones of the k bus-bars 35, one of the pairs of sampling registers feeding the input of delay register 31 and the other pairs feeding the lateral inputs of the adders 41. The H/k stage address register 610 controls which bus-bar is tapped by which pair of registers, the stages of the registers being emptied at a frequency F H . The sampling shift registers of the arrangement of Fig. 3 may be modified when F d  = HF H  is particularly high and N > H/k, Fig. 4 (not shown).