Patent GB-1000749-A (GB)
Title: Time division multiplex pulse communication system
IPC: H04J3/00
Filed: 1961-12-15
Abstract: 1,000,749. Multiplex pulse signalling; semi-conductor circuits. STANDARD TELEPHONES & CABLES Ltd. Dec. 15, 1961 [Dec. 23, 1960], No. 45064/61. Headings H3T and H4L. Relates to a synchronizing arrangement for a time division multiplex pulse communication system. Transmitter, Fig. 1.-At the transmitter a base frequency generator 11 produces sinusoidal oscillations at 1600 c/s. which are shaped at 12 and supplied to a distributer 13. In the example described there are 256 time slots per frame and the distributer 13 produces 256 time sequential pulse trains which are supplied to channel AND gates 20a, 20b &c. so that the pulses are passed in succession if an information signal is present at the corresponding input signal source 3a, 3b &c. The duration of each pulse from the distributer 13 is arranged to be equal to the period of the oscillations from the oscillator 11. A framing signal is supplied by a flip-flop 18 which is triggered once each frame by the third output from the distributer 11 and controls channel number 1 gate 20 so that " 1 " and " 0 " appears alternately at the output of the gate. Five of the remaining channels are gated with pulses during each frame so that sufficient timing information will be provided at the receiver regardless of the condition of the other channels, the remaining input information signals being in binary pulse coded form. The outputs of AND gates 20, 20a &c. are supplied in time succession via an OR circuit 21 to a coincidence and output circuit 5 which also receives the pulses from the shaper 12 and is arranged so that at each pulse of the multiplex signal one cycle of 1600 c/s. sine wave oscillations is transmitted via the line 7 to the receiver. Alternatively it may be arranged that several cycles are transmitted for each pulse. Receiver, Fig. 1.-The incoming signal is detected at 24, smoothed at 25 and sliced at 26 to provide a replica at output 27 of the signal appearing at the output of OR circuit 21 at the transmitter, and an inverted output on lead 28. The output 27 is supplied to a filter 29 tuned to 1600 c/s. which supplies a 1600 c/s. sine wave to a shaper 30 providing a base frequency pulse train for the distributer 32 via an INHIBIT gate 31. The distributer 32 produces a plurality of time sequential pulse trains as at the transmitter. AND gates 35, 36 receive as one input the signals 27 and 28 respectively from the slicer 26, another input being provided by the channel No. 1 output from the distributer 32, the two outputs of a flip-flop 37 also being supplied to the gates 35, 36 respectively. The flip-flop 37 is controlled by the No. 3 pulse train from the distributer as at the transmitter. If framing is incorrect a pulse is supplied to the INHIBIT gate 31 via the circuit 43 to extract a pulse from the input to the distributer 32, and the distributer output signal will continue to drop back one position until synchronism is restored. The integrating circuit 43 ensures that more than one error signal is required before the gate 31 is inhibited so that single errors due to noise &c. do not cause loss of synchronism. Gates 35a, 36a to 35n, 36n are controlled by the distributer 32 to set the respective stores 45 to 45n in accordance with the incoming signal the stores co-operating with corresponding utilization devices 50 to 50n. Transistor circuits.-The output circuit 5 at the transmitter includes a transistor controlled ringing circuit 51, Fig. 4, for regenerating the 1600 c/s. sinusoidal oscillations from the input pulse train from shaper 12, Fig. 1, for application to a gate circuit comprising transistors 68, 69 and diodes 70, 71, 73. The multiplex pulse signal from the OR circuit 21, Fig. 1, is supplied via amplifier 64 and phase splitter 65 to provide respective inputs to the base circuits of transistors 68, 69 so that when a pulse is present in the signal from 21 transistor 69 conducts and transistor 68 is non-conductive. This blocks diodes 70 and 71 and prevents a voltage -V 3  from being applied to the base of an output transistor 77 one cycle of sine wave being passed from the circuit 51 via the diode 73 to the output stage 72. If there is no pulse in the input signal transistor 69 will be non- conductive and transistor 68 conductive and the voltage -V 3  will be applied via diodes 70, 71 to the base of transistor 77 the diode 73 being blocked. The output amplifier 72 includes three transistors connected as shown to provide a high input impedance and low output impedance, feedback being provided via resistor 75 to the emitter of transistor 77. The input at the receiver is supplied via a tuned amplifier 81, 82, Fig. 5, similar to the amplifier 72, and filter 83 to a full wave rectifier 86 the output of the rectifier being smoothed and filtered at 25 and supplied to a centre slicer 88. In the slicer a large capacitor 89 is charged to the peak signal value via a transistor 90 and a voltage equal to half the peak signal value is supplied by a voltage divider 91 connected across the capacitor 89 to provide base bias for a transistor 92. Only signal levels above this biased are amplified by transistor 92 whose output is coupled to a clipper 93 providing the output signal. An inverted version of the output signal is provided by a further clipper 94 followed by an amplifier 95.