Patent ES-403566-A1 (ES)
Title: Stacking store having overflow indication for the transmission of data in the chronological order of their appearance
IPC: G06F5/08
Filed: 1972-06-07
Abstract: A stacking store having overflow indication and of use for the transmission of binary data in the chronological order of their input (write-in). The stacking store is characterized in that it comprises store circuits, a first and second auxiliary circuit and a clock. The store circuits are equal to the number of bits in the data to be transmitted and each store circuit comprises: a n stage shift register (each stage having two inputs connected to one another and one output) and three logic type routing gates having two inputs and one output, viz. a first gate whose first input receives the input bit corresponding to the store circuit and whose other input receives a logic type signal permitting write-in into the store, such signal being called "first logic signal" hereinafter, a second gate whose first input is connected to the output of the first gate and whose second input is connected to the output of the third gate, the register having its input connected to the output of the second gate and its output connected to the first input of the third gate, the second input of the latter gate receiving the complement of the first logic signal, the output of each store circuit being the output of its register. The first auxiliary circuit comprises a n stage shift register identical to the previous shift register, the two inputs of the first stage not being connected to one another as in (1), one of the latter inputs receiving a logic control signal called the "second logic signal" and serving to erase from the store the information output thereby, the other input being connected to the output of a logic gate having two inputs connected to the respective outputs of two other logic gates each having two inputs and one output, the first of the latter gates having an input receiving an auxiliary bit called "overflow bit" and the other input receiving the first logic signal, the second of the latter gates having an input receiving the complement of the first logic signal, the other input being connected to the output of the previous register which thus forms the output of the first auxiliary circuit, the logic state of the last-mentioned output possible saturation of the store. The second auxiliary circuit comprises a n stage shift register identical to the shift register of the first auxiliary circuit, the first input of the first stage receiving the second logic signal while the second input of the last-mentioned stage is connected to the output of a logic gate having two inputs, one of which receives the complement of the first logic signal while the other input is connected to the output of another logic gate having two inputs, one receiving the complement of the first logic signal and the other being connected to the output of the corresponding register, the latter output delivering an auxiliary bit called "marking bit" and forming the output of the second auxiliary circuit. The clock pulse generator triggers the stepping-on of the data towards the store output in all the shift-register set forth previously.