Patent EP-0276052-A2 (EP)
Inventor: HOELZEL ROY JOHN
IPC: H01R12/50
Filed: 1988-01-06
Abstract: A memory system assembly comprises an input interconnection network substrate having a system input electrical connector pair first member affixed at a first edge portion thereof which can be selectively mated with a system input electrical connector pair second member for connection to external electrical apparatus to pass electrical signals therebetween, said input substrate first edge portion being located between input substrate second and third edge portions with said input substrate second edge portion having a first internal electrical connector pair first member affixed thereto and with said input substrate third edge portion having a second internal electrical connector pair first member affixed thereto, there being electrical interconnection provided between each of said first and second internal electrical connector pair first members and said system input electrical connector first pair member; an output interconnection network substrate having a system output electrical connector pair first member affixed at a first edge portion thereof which can be selectively mated with a system output electrical connector pair second member for connection to external electrical apparatus to pass electrical signals therebetween, said output substrate first edge portion being located between output substrate second and third edge portions with said output substrate second edge portion having a third internal electrical connector pair first member affixed thereto and with said output substrate third edge portion having a fourth internal connector pair first member affixed thereto, there being   electrical interconnections provided between each said third and fourth internal electrical connector pair first members and said system output electrical connector first member; a first transmission interconnection network substrate having selected internal electrical connector pair second members affixed thereto including first and third internal electrical connector pair second members capable of being mechanically and electrically connected with said first and third internal electrical pair first members, respectively, there being electrical interconnections selectively provided between said plurality of internal electrical connector pair second members, said first and third internal electrical connector pair first members being mechanically and electrically connected with said first and third internal electrical connector pair second members, respectively; a second transmission interconnection network substrate having selected internal electrical connector pair second members affixed thereto including second and fourth internal electrical connector pair second members capable of being mechanically and electrically connected with said second and fourth internal electrical pair first members, respectively, there being electrical interconnection selectively provided between said plurality of internal electrical connector pair second members, said second and fourth internal electrical connector pair first members being mechanically and electrically connected with said second and fourth internal electrical connector pair second members, respectively; and a plurality of memory module interconnection network substrates each having a pair of internal electrical connector pair first members affixed at selected edges thereof one of which is   capable of being, and is, mechanically and electrically connected with at least one of said selected internal electrical connector pair second members affixed to said first transmission interconnection network substrate and that one remaining capable of being, and is, mechanically and electrically connected with at least one of said selected internal electrical connector pair second members affixed to said second transmission interconnection network substrate, each of said plurality of memory module interconnection network substrates having at least one electronic memory circuit means affixed thereto with each said electronic memory circuit means having an electrical interconnection to each of said internal electrical connector pair first members affixed thereto, said connections of said internal electrical connector pair first and second members being solely relied upon to mechanically connect, in that manner aforesaid, said input, output, first transmission, second transmission and plurality of memory module interconnect network substrates.