Patent GB-1412785-A (GB)
Title: Graphic display system
IPC: G09G5/42
Filed: 1972-12-13
Abstract: 1412785 Cathode-ray tube displays TOKYO SHIBAURA ELECTRIC CO Ltd 13 Dec 1972 [14 Dec 1971] 57411/72 Heading H4T In a cathode-ray tube graphic display system in which the display is produced by intensity modulation of the beam as it is scanned line rasterwise, a control circuit 14 (Fig. 1), on command of a computer 13, causes a function generator 15 to produce data (digital numbers) representative of the X and Y co-ordinates of successive points on, e.g. a line, of a figure to be displayed, such data being stored in a matrix memory 16 from which it is supplied to a rewrite memory 17 the output of which intensity modulates the beam of the display tube 11 as it is scanned in line raster fashion under the control of the read out of data from the rewrite memory 17. A further rewrite memory 18 may supply a further display tube 12 located remotely from tube 11 and matrix 16 may supply memories 17, 18 alternately, with different data. The function generator 15 comprises respective X-axis and Y-axis co-ordinate registers in which the co-ordinates are set, together with sign bits, as binary numbers by means of the control circuit 14 which then operates to read out these numbers serially and supply the outputs to respective reversible X and Y registers in which the initial positions have been already set (Fig. 2, not shown). The memory matrix 16, comprises 512 rows of integrated circuits each having 512 addresses at which, under the control of the reversible X and Y registers of the function generator, the successive points forming the line are set up, appropriately spatially arranged. When this has been done the X-axis reversible register is disabled and the Y-axis reversible counter is then employed to read-out successive " horizontal lines " of the matrix into a series of flipflops (Fig. 3, not shown). The rewrite memory comprises a store including 512 rows of MOS integrated circuit recirculating shift registers corresponding respectively to the individual lines of the display each having a bit capacity equal to the maximum line resolution (512) plus the fly-back time of the beam, successive registers being loaded serially by means of the series of flip-flops associated with the memory matrix and then read out in the same order and supplied to the beam intensity control electrode synchronously with the line scanning (Fig. 4, not shown). In order to reduce cost the memory matrix may have a capacity of one quarter that of the rewrite memory store, the latter being divided into four sections of 256 x 256 bit capacity fed successively from the matrix memory which receives new data after each feeding operation. A partial addition to the displayed figure may be made by writing the additional data in the matrix memory, after the main figure data has been transferred and transferring this to the rewrite memory via an OR gate in the recirculating loop of the latter (Fig. 5, not shown) and a partial elimination of the main figure may be effected by writing data relating to such part into the memory matrix and transferring it via an AND gate in the recirculating loop of the rewrite memory (Fig. 6, not shown).