Patent GB-818145-A (GB)
Title: Electric digital data storage unit
Filed: 1956-03-05
Abstract: 818,145. Electric digital-data-storage apparatus; electronic counting-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 5, 1956 [March 8, 1955], No. 6829/56. Class 106 (1). An electric digital data storage unit for an electronic .data processing machine for storing records consisting of variable numbers of characters, comprises a rotatable member having a magnetizable storage channel divided into a predetermined number of sections each containing a fixed number of character positions, means operable in synchronism with the rotation of said member for producing synchronizing signals, magnetic transducing means associated with said storage channel, means responsive to said synchronizing signals for producing a signal identifying the first character position in a selected one of said sections of said storage channel, and means initially rendered effective by said signal identifying the first character position in the selected section of said storage channel and operatively controlled thereafter by said synchronizing signals for selectively enabling said transducing means to perform transducing operations starting at the first character position in the selected section of said storage channel and continuing at succeeding character positions in the selected section and if necessary at succeeding character positions in succeeding sections of said storage channel thereby permitting variable length records to be transferred between said member and said data processing machine. An arrangement is described for transferring variable length digital data words referred to as " records " between a magnetic drum storage device and a calculator. The arrangement is such that once a particular drum address has been staticised in an address input register 400, Fig. 4, data is read out of or written into that address and then the address in the register is advanced to the next adjacent address and the reading or writing continued at the new address ; this process is repeated until an end of record mark is sensed, or until the last address on the drum is reached, when it ceases. In this way variable length records may be read from or written on the drum from successive address positions starting at a specified address. Arrangement of data on drum.-Each character is stored on the drum by seven bits ( 1, 2, 4, 8, A, B, C) in seven parallel tracks, which are referred to collectively as a " channel." The drum described contains 30 channels and the reading or writing of all the seven bits of any one character is done simultaneously but the actual read/write heads for each channel are spaced circumferentially around the drum, Fig. 1; all the 1-bit heads for the 30 channels being mounted together, all the 2-bit heads together and so on for the remaining bits. Each channel on the drum comprises 2000 character storage positions labelled S1 to S2000 successively together with a " gap "-equivalent to 10 storage positions-between the S2000 position and the S1 position, and is divided into ten interlaced sections, each of 200 characters, labelled Sect.0 to Sect. 9, Fig. 3, Sect. 0 including character positions S1 S6, S11 and every fifth position up to S996, Sect. 1 including positions S1001, S1006, S1011 and every fifth position up to S1996, Sect. 2 including positions S2, S7, S12 and every fifth up to S997 and so on for the remaining sections, so that all the oddnumbered sections are interlaced on the first half of the drum and all the even numbered sections are interlaced on the second half of the drum. The drum also contains a timing track. Operation.-In operation the calculator first enters an address in the address register 400, Fig. 4, which specifies a particular drum (only one drum is used in the equipment described but more could be added), a particular channel and a particular section, and applies either a write signal W call " or a read signal " R call " to the read/write control circuits. An address coincidence detector 500 then produces a " Char-1 selected section " signal each time the first character of the section specified by the staticized address passes the read/write heads. Nothing further occurs, however, until a " Calc. Ctrl. " signal is applied by the calculator to the read/write control circuits 600 whereupon reading or writing commences, in the specified channel, on the next occurrence of the Char.- 1 selected section signal," which causes a 5-stage ring " process " counter, contained within the read/write control circuits, to be stepped by clock pulses to control the read/write circuits so that only every fifth character position is read out of or written into. As the Char.-200 position of the specified section passes the read write heads, the section number in the address register is advanced by unity, so that reading or writing can continue, without interruption, in the next section. For example, if Sect. 4 (which is on the first half of the drum) is the initially specified section then character position S4 will be the first character of the selected section and once the " Calc. Ctrl." signal has been applied reading or writing will commence in this section and continue, under control of the precess counter in character positions S9, S14 and every fifth position up to S998, which is the character 200 position of Sect. 4. At this point the staticized section number is increased to 5, and reading or writing continues in the first character position S1003-still under control of the precess counter-in Sect. 5. At the end of Sect. 5, position S1998, the staticized section address is again advanced by unity, but reading or writing is temporarily suspended until the " gap " in the channel has been passed and the precess counter is so arranged that when this occurs it is precessed one position, i.e. whereas in the drum revolution just completed it enabled the read/write heads at positions S4, S9, S14 and every fifth position to S1998, in the drum revolution just commencing it enables them at positions S5, S10, S15 &c. to S1999. After the last character of Sect. 9 has passed the read/ write heads the section address is again advanced -stepping to Sect. 0-and the channel address is also advanced by unity so that the reading or writing can continue in the next channel. This process continues until an end of record mark is sensed or until the end of the drum is reached or until a timing error signal (obtained by checking whether the Sect. 9 Char.-200 signal comes before the " gap "-which it would do if noise pulses had been counted) is produced. Ring counters.-The counters used in the address timing register are of the ring type, a typical 5-stage counter being shown in Fig. 5A5, where 5 diode gates DG-1 controlled by associated triggers of the ring, each receive the advancing pulses, that gate which is open (by virtue of its associated trigger being on) passing an advancing pulse to turn off the associated trigger and turn on the next trigger in the ring. Output potentials from the ring are provided via cathode followers CF-1. Binary-decimal counters.-The address input register, Fig. 4, comprises a number of binarydecimal counters of which the section counter, Fig. 5B1 (i.e. that which staticizes the section representing part of an address) is typical. The counter comprises four triggers T3, T5, T5 and T5 and can be initially set by signals on four 1, 2, 4, 8 input leads from the computer, and counts from 0 to 9 in pure binary form (9 being 1001) and then returns to zero. True and inverse outputs of the number in the counter are provided via cathode followers. During the initial setting of the counter, for example the 8-bit trigger T3 thereof, a signal on the 8 input line passes via grounded grid amplifier 408d, a cathode follower 410d, an inverter 414d and a cathode follower 416a, from where it passes in true and inverse form to two gates 412d, 418d, which have been opened by a " select address set " signal, and thence to the trigger T3. The counter is advanced by means of two signals, a first relatively long " Sec. Ctr. Carry Ctl." signal, which opens or partially opens gates 432a-432d and 432d<SP>1</SP> followed by a relatively short " Sec. Cts. Adv." signal which passes through gate 432a to change over the condition of the 1-bit trigger, which causes further changes in accordance with the binary scale. Selection of read/write heads.-The staticized channel address is decoded-by a conventional array of diodes-and as a result one of a number of channel leads is energized, say Ch.-1, for example. This signal is used, Fig. 5D2, to prime 940 so that when a write pulse W is applied the seven heads of channel 1 write simultaneously the data applied to them in true and inverse form. (This same data is also applied to the other 29 channels, but only channel 1 is activated). Data read from the drum is selected in a similar manner.