Patent GB-1352988-A (GB)
Title: Method for fabricating integrated circuits
IPC: G06Q10/00
Filed: 1972-10-02
Abstract: 1352988 Fabricating integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 2 Oct 1972 [30 Dec 1971] 45302/72 Heading G4A  An integrated circuit is designed from a user specification comprising a circuit block graph and details of available circuit characteristics by computing the load associated with each circuit of the graph and its electrical characteristics, the latter being compared with the specified characteristics so that each circuit which does not satisfy the specification is replaced. As described for FET circuits the circuit block graph input (Fig. 5, not shown) includes, for each circuit, a number assigned to the circuit, a net number identifying the output net of a circuit, an indication of all the circuits connected to output net, the identifying numbers of the input net, the number of input lines, a maximum time delay, an indication of the logic function of the circuit and the cell position in the circuit chip where the circuit is to be placed. From additional information provided by the user an array AFS (Fig. 4, not shown) is formed comprising for each circuit, constants m, K for use in computing delay times, load-in values, constants ZC1, ZC2 for use in computing the circuit load, the power dissipated by the circuit, a size parameter (used in conjunction with the number of inputs to the circuit to determine the physical area required) and a maximum cell size, this information being stored on disc. Each circuit in the circuit block graph input is initially associated with an address in the array containing the characteristics of the user specified circuit which will satisfy the circuit block graph. The circuits in adjacent addresses of the array perform the same function, faster circuits having higher address numbers. Initially the programme computes at step 10 (Fig. 1A), for each circuit C i  the metal and diffusion interconnection lengths required for its output net. This is effected by computing the vertical and horizontal co-ordinate distances VM, HD between the circuit C i  and the circuits of its output net from the X and Y co-ordinate positions of the array. The vertical and horizontal distances represent metallization and diffusion fabrication respectively.  Next, at step 20, the load 2T i  and delay D i  associated with that load is computed. The circuit load ZC is first calculated by fetching from the circuit block graph input the number NFAN of input lines to the circuit C i  and from the array AFS the constants ZC1, ZC2 to compute the value 2C1 + 2C2 x NFAN. The circuit interconnect load is computed from the length VM, HD by using the formula where KM, KD are constants fed in by the user. The driven circuit load ZD is computed by accessing the circuit block graph input to determine the circuit numbers of the circuits driven by the circuit C i  and the corresponding addressesin the array of their characteristics. The load parameters for these circuits are fetched from the array and added to derive the load ZD. The total load ZT i  is given by the sum of ZC + ZI + ZD. From the array the components m and K are fetched so that the delay D i  = m x ZT + K may be computed. The specified delay SPD i  for the circuit C i  is fetched from the user array and if it is greater or equal to D i  the circuit is considered to satisfy the requirements. If it is less than D i  the array address is incremented to find, if available, the characteristics of a faster circuit. The cell size for the faster circuit is computed using the size parameter in the array and the number of inputs specified in the circuit block graph input and if it exceeds the cell size limitations the programme proceeds to operate on the next circuit C i+1 . If however the circuit size does not exceed the cell size limit an optimization programme 40 (Fig 1B) is effected. In the optimization process any delays D i  which have not been calculated are determined. For each circuit C i  the difference # between the delay time D; and the specified delay time SPD i  for each circuit connected to the inputs of the circuit C i  is computed. A critical input circuit is identified by finding the maximum value D crit  of #. This maximum value is added to the delay D i  to derive a total delay DT. A hypothetical increment of the sizes of all the circuits driven by the critical input circuit is then made and a new total delay DT<SP>1</SP> is computed. If DT<SP>1</SP> is less than DT the circuit block graph input is updated with the address of the characteristics of the faster circuit and if the circuit size is increased the programme branches back to step 20. Otherwise, after all the circuits C i  have been processed, a test is made to determine whether the total circuit chip power dissipation has been exceeded for all circuits and if it has the updated circuit block graph input is fed out to the user.