Patent GB-1227818-A (GB)
IPC: G06K7/016
Filed: 1968-11-21
Abstract: 1,227,818. Record sensing apparatus. FMC CORP. 21 Nov., 1968 [24 Nov., 1967], No. 55315/68. Heading G4M. A label L on an article P bears identification marks A, clock marks C and code mark I which are sensed by photo-cell groups 16A, 16B and 16C to provide signals which are checked to determine whether they correspond to a correct sequence of marks and correct mark width and spacing. The photo-cell groups 16 are connected to corresponding gates 20 providing an output representing the condition of the majority of the inputs. Sensing of correct identification marks A should produce a sequence of signals on gate output leads 26A, 26B and 26C, 26A, 26B. Detector circuit 25 includes logic circuits for detecting the various sequence conditions and a series of bi-stable circuits which are set in turn as the sequence conditions are fulfilled. If the sequence is correct an enable output 31 is produced, but a reject output 27 is produced if 16C detects a mark while 16A and 16B detect spaces, or if 16C detects a second mark/space transition before 16B detects a second space, the latter being indicative of excessive label skew or spurious marks on the lower track. A detailed circuit for detector 25 is given in Figs. 3A, 3B (not shown). The mark-space detector 40 which is enabled by output 31 includes logic circuits, Fig. 5 (not shown) provided a reject output 46 if a clock mark C is too wide (or a space between clock marks is too narrow), or if the clock marks C or code marks I are too wide. The block 35 which is also enabled by output 31 consists, Fig. 4 (not shown) of a clock generating circuit connected to lines 26A, 26B which drives a divide by ten counter having an output inhibiting the clock generator after ten pulses have been produced, these pulses being used to shift the code bits I read by photo-cells 16C into a ten stage shift register. An article presence detecting photo-cell 80 provides an enabling signal for blocks 25, 35 and 40, and a resetting signal for block 45. A further photo-cell 340 starts a clock generator in block 45 which is controlled by a counter to produce a train of 20 pulses. The first 10 pulses are used to shift out the code stored in the shift register in block 35 to a corresponding shift register in block 45 at the same time performing a parity checking operation by means of a 4-stage shift register and a pair of EXOR circuits by means of which the parity of a pair of adjacent code bits is compared with the code bit three bits removed therefrom. The second ten pulses are used to cycle the shift register in block 45 to a further EXOR circuit providing correction bits so that a corrected word is re-entered in the shift register. If an excessive number of errors is detected, a reject output is provided on lead 389. At the end of this period a read command issued over lead 47 causes transfer of the shift register contents over lead 60-69. Any of the reject signals causes a reject code to be transferred. Memory 50 consists of register pairs connected as a shift register. The second register of each pair has a circuit which detects when the register is empty and initials transfer from the first register of the pair and resetting of the first register. Shifting through the stages of the second half of memory 50 is controlled by photo-cells associated with sorting deflectors, and each deflector is energized through a corresponding diode matrix.