Patent GB-1143215-A (GB)
Title: Multiplying system
IPC: G06F7/52
Filed: 1966-04-15
Abstract: 1,143,215. Multiplication system. BURROUGHS CORP. 15 April, 1966 [16 April, 1965; 7 Oct., 1965], No. 16713/66. Heading G4A. [Also in Division H3] A multiplying system includes a multi-stage product accumulator having less stages than the maximum number of product digits formable by the system, the accumulator operating in a ring-like manner and the product being formed by the addition of successive partial products, the arrangement being such that selected ones of the least significant product digits may be cleared from the accumulator by pulse generator means after any carries associated therewith have been generated so that higher order significant digits may be subsequently stored in the emptied accumulator stages. The system is described as an adjunct 43 (Fig. 1) to a known accounting machine 41 capable at least of addition and subtraction and including two 10 decimal digit registers 47 and 49, a 12 decimal digit mechanical printer register 51, a printer 53 and a control centre 45. For multiplication, the registers 47 and 49 are used to store the multiplier and multiplicand respectively. During multiplication of two numbers, for each multiplier digit taken in turn, successive multiplicand digits taken one-by-one are added into appropriate stages of product accumulator 207 a number of times depending on the values of the successive multiplier digits. The accumulator 12 comprises a 12-stage decimal counter with ring-like operation. Successive pairs of multiplier and multiplicand digits read in turn into single digit counters 157 and 159 respectively control the flow of clock pulses from a clock 167 into the product accumulator 207. If it is desired to omit say decimal fractions other than the first two decimal places (e.g. in calculations involving decimal currency) the control centre 45 is programmed so that partial product digits below this level of significance are assembled in stages 12, 11 (in the example) of the accumulator 207 and these stages are successively zeroized after any carry over into stage 1 has taken place (as shown in Fig. 26). Thereafter any overflow from stage 12 to stage 1 or any attempt to direct clock pulses to stage 1 after stage 12 has been addressed is detected as a capacity overflow and further operation of the machine is blocked, until the operator intervenes. After the multiplication has been completed, the contents of the accumulator 207 are transferred (using nine bursts of nine pulses each which count the stages down by a value of one per burst) into the register 51. Data may be read from the machine 41 into the adjunct 43 by known electro mechanical means. Counters.-In a counter (Fig. 12) comprising an input AND-gate 165 a binary stage 166 consisting of a plurality of cascaded complementing flip-flops of counting capacity m, an interface stage 168 consisting of a single set-reset flip-flop and an output stage 170 consisting of a number n of shift register flip-flops (set and reset signals only effective when signal also present at SH), the radix is equal to 1 + m + 1 + n. The input count pulses CT are applied to both the gate 165 and to the SH input of stage 170. There is feed back from both the stages 168 and 170. A truth table for the counter is given in the Specification (Table I). A signal is issued from the output each time a number of pulses equal to the radix is received. The counter may be preset by signals from a diode encoder 162. Figs. 13 and 14 (not shown) illustrate decimal and duo decimal counter arrangements respectively. A variable radix counter operable in radix 10 or 12 according to whether a signal "BASE 10" is present or not is shown in Fig. 15 the output in either case being from the stage 170 (truth table-Table IV). An arrangement for making a four flip-flop binary cascade counter count in radix 12 instead of 16 is illustrated in Fig. 20 (not shown) an A.C. coupling element 239, inverter 241 and gate 245 being connected between the 0 terminals of flip-flops 4 and 8 to enable flip-flop 4 to be set whenever flip-flop 8 is set-i.e. the counter operates in excess four code above 7. In a quantized counter (Fig. 19, not shown) quantized pulses from a bi-stable core 217 are transferred by way of a loop 213 to multi-stable incrementally steppable magnetic counting core 223. The core 223 may be initially cleared by a pulse through a transistor 225.