Patent GB-1138671-A (GB)
Title: Data processing
IPC: G06F13/18
Filed: 1966-03-31
Abstract: 1,138,671. Data processors. INTERNATIONAL BUSINESS MACHINES CORP. 31 March, 1966 [5 April, 1965], No. 14305/66. Heading G4A. In a data processing system, a storage access request from an input/output channel is given priority over one from a processing unit occurring in the same cycle if the storage is busy servicing another request but if it is not busy the processing unit request has priority. Selection circuits (Fig. 9).-Any one of seven channels (input, output, maintenance) may request access to storage (for data transfer either way) by setting corresponding service latches, in CH PRI, the lowest numbered of the set latches giving rise to a corresponding priority bit, in CH PRI, which sets a latch in BFR to prevent further setting of the service latches and to pulse a delay network DLY. The delay network sends a data request signal and a response signal to the channel specified by the priority bit, DATA REQ, BCU RSP, and sets a channel request latch CH REQ. A bit in a storage address supplied by the channel specifies whether an even or odd storage section of one of two frames is required and provided it is not already busy, a channel select even or odd signal is produced CH E/O. If either of these signals is produced, a signal blocking access to storage by a CPU (i.e. central processing unit) is produced GT CH NOT CPU BLK. The CPU may access an even or odd section of storage provided it is not busy and the blocking signal is absent, by setting a CPU request latch CPU REQ and producing a CPU select even or odd signal CPU E/O. A CPU request has priority over a channel request occurring in the same cycle if the storage is not busy when the rerequests occur, but if it is busy the channel is given priority when the storage becomes free. A storage address register has a (physically remote) duplicate section DUP SAR for the bit specifying even or odd, and also for a bit specifying which of the frames is required A branch or interrupt rendering unnecessary CPU storage request already made resets th CPU request latch CPU REQ without the access being made. Storage, input circuits (Fig. 10).-A storage address, supplied by either the CPU or a channel (whichever has access), comprises 24 address bits plus a parity bit for each 8 address bits. One address bit selects a storage frame, one selects an even or odd section within it, 14 select a word, 3 select a byte, and 5 are not used (unless extra storage is provided) except that one of the 5 is set to " one " to specify fetching of data from the panel (console). An " invalid address " signal is produced INV ADR if address bits which should not be used are used, or if the odd or even half of a storage frame selected is out of service (indicated by manual switches controlling " ready " lines). An address check signal is produced SAB ADR CHK as a result of a parity check on the address. If the address is invalid and a panel switch is not set or the address has incorrect parity, or if a fetch from the panel is indicated by the address and a panel switch is set, storage access is cancelled and the storage replaced by the panel as a source of data CANC PKF. Two new parity bits for the 14 address bits used for word selection are derived from the full address and the parity bits supplied with it PAR ADJ. Provision is made for comparing the full address with one set up on panel keys ADR COMP. So called " marks " are provided MARKS for selecting bytes in a storage word (e.g. for alteration before restoring), bytes being specifiable individually by a channel (when in control) or during variable field length operations by the CPU, but only in pairs during other CPU operations. A mark parity bit is provided and may be updated during variable field length operations as successive marks are provided. A block of storage may be accessed only if a 4-bit protection key corresponding to it agrees with a key supplied IN KEYS by the channel or CPU, whichever is in control, or if either key is 0000. Each key from a channel or CPU has a parity bit. The CPU key is selected from one of two sources (instruction register and programme status word) and a parity bit for it is derived from a parity bit relating to it and 4 other bits, and said other bits IN KEYS. Storage output circuits (Fig. 11).-Two " tracking " triggers X/Y-W/Z keep track of which accessed data belongs to which request, partially controlling registers X REG, Y REG to indicate the destination of the data and routing various error indications (protection, address parity) to the CPU or channel as appropriate SAP, STR ADR CHK. Whenever neither an even nor an odd section of storage is busy, the " tracking " triggers are checked X/Y-W/Z CHK. In the case of an error signal from this, or from a data parity check in a CPU store (as distinct from fetch) access STR DATA CHK, or from an address parity check in a CPU access STR ADR CHK, a stop clock signal is produced BCU STP CLK. Protection keys from either frame may be accessed OUT KEYS. As mentioned above, data from panel keys may take the place of data from storage, in an output buffer SBOL.