Patent GB-1139631-A (GB)
Title: Time division communication systems
Inventor: CORBIN JOSEPH ELBERT
IPC: H04Q11/04
Filed: 1965-12-23
Abstract: 1,139,631. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. 23 Dec., 1965 [29 Dec., 1964], No. 54530/65. Heading H4K. In a TDM exchange system having an incoming highway carrying n channels of which m channels are used for supervisory purposes, means are provided for stripping the m channels from the pulse tram and for then rearranging the remaining [n-m) channels so that they are equally spaced over a time frame which is equal to that originally used for the n channels. For an outgoing highway the (n-m) (data) channels are "compressed" so as to leave "empty" equally spaced channels into which supervisory bits are inserted before outward transmission. The system described utilizes PCM on four-wire highways which are interconnectible via a logicgate switching matrix. The latter is controlled by a No. 1 ESS type central processor. Supervisory bits are not transmitted through the matrix which is reserved solely for the handling of data bits occupying the rearranged (expanded) n-m channels. The system has facilities for :- party lines; conference, broadcast and break-in calls; camp-on; call booking; and store and forward ( for facsimile transmissions). Traffic originating from voice, teleprinter or facsimile subscribers can be handled. In the following, components in figures identified by a number, of which the last two digits denote the component whilst the first one, two or three digits denote the figure in which the component is to be found. Figures which are not shown are normally identified by the symbology (F.x) where x is the number of the figure. General description. Time frame (Fig. 3).- This comprises 136 bit periods of which 128 bits are used for data while the remainder are used for supervision. The latter divide the M (data) bits into groups of 16 and they consist of four S bits denoting e.g. on/off hook, busy &c., two framing bits F1, F0, a parity bit P1 and an additional bit PE which may be used for any purpose. The frame may relate to a single subscriber or it may be a multiplex of a plurality of subscribers. Central times (Figs. 4-6, not shown).-A crystal oscillator supplies the basic system frequency of 5À2224 Mc/s. Its positive and negative (even and odd) peaks are used to produce two square wave trains which are inter alia applied to count down circuits giving 2À6 and 1À3 Mc/s (approximately) outputs. The latter denote time slots, of which there are 544 per subframe (17 bits). High frequency pulse phases #l-#8 Fig. 134, not shown), corresponding to eight sub time slots for use in the link memories are derived from the timer as are various low frequency phases used for controlling the terminal circuits. As an indication of the system's timing requirements, it is stated that bits are moved during a queuing operation (see below) in 0À765 microsecs. An atomic frequency standard having an accuracy of at least 1 in 10<SP>9</SP> is used for calibrating the oscillator. Terminating junctors.-The lines connected to the exchange may be of simplex or multiplex type and messages may be transmitted over these at rates of 75+2<SP>n</SP> bits per second e.g. 2.4, 9À6 and 38À4 Kb/s. The actual transmission rates are slightly higher than this in view of the presence of supervisory bits. The junctors are all very similar except for those connected to multiplex liner which require frame search circuits for synchronization purposes (Figs. 24-29, not shown). A junctor responsive to a 38À4 Kb message rate i.e. a 40À8 Kb actual transmission rate, employs a clock 703 which is slaved to the incoming bit stream whereby to cyclically gate each bit into the relevant section of buffer 706. Central timer pulses at the 40À8 Kc rate cause cyclic read-out of the buffer not sooner than 3 bit periods after write-in. The "incoming" data on 801 is "full banded" i.e. is of "non return to zero" (NRZ) type (i.e. successive "one" bits occur as a single long pulse). Furthermore this data is synchronized with all other data occurring within the exchange at the 40À8Kb rate. The framing bit F1 is used to synchronize the incoming data with locally generated F1, F0 bits by means of an automatic frame alignment circuit (F. 9, 13 or F. 24-29) as described in Specification 1,033,069. Supervisory bits (S) are inserted into an outgoing message bit stream (F. 14) which is then passed to line via a send terminal unit (outgoing junctor). The latter includes the necessary logic for adding the control bits CE, P1, F1, F0 in place of one of each pair of S bits that are double-written into the stream by the insertion circuit of (F.14). Bits F1 and F0 are always respectively 1 and 0 and thus a pattern 1 ... 0 repeated at half frame intervals is easily recoginzed by the synchronization circuits. A bit stripper (F. 10) removes the S and control bits from the incoming data, stretches the message bits into a uniform stream and then buffers these bits prior to their being passed through the exchange. During bit stripping, the logic is such that each S or control bit is replaced by repeating the immediately preceding message bit. The latter repeated bits are then deleted under the control of a timing pulse train 75 X 2<SP>n</SP> which processes relative to the clock rate 75 X 2<SP>n</SP> (1 + k), where k is fractional, used for addressing the data whereby the incoming 40À8 Kb rate where each bit requires 32 time slots is converted into a 38À4 Kb rate utilizing 34 time slots per bit, see also (F. 135, 137) which depict the timing waveforms, and the waveforms present at different positions in the logic circuits. It may be helpful if the bit stripping process is described with the aid of a simple example. Thus consider three equally spaced pulses occurring in a one second interval (this is the aforementioned clock rate) where the central pulse is an S pulse and the two outer ones are M pulses. First of all the S pulse is removed and is immediately replaced by repeating the first occurring M pulse whereby three equally spaced M pulses now exist in the one second period. The first M bit is then stored and during the later part of its occurrence i.e. at its trailing edge it is read-out by a timing pulse. The next M bit i.e. the repeated one, is then stored but during its occurrence no readout timing pulses occur so that it is effectively deleted. The final M bit is stored and during the initial part of its occurrence i.e. at its leading edge, the timing pulse which repeats at <SP>1</SP>/ 2  sec. intervals causes it to be read-out. The original 3 bit per second pulse train with pulses equally spaced at <SP>1</SP>/ 3  sec. intervals is thus converted into a two bit per second train having a pulse interval of <SP>1</SP>/ 2  see,. An S bit insertion circuit operates in an analogous manner (F. 14). As previously mentioned however each S bit occurs twice in the data bit stream supplied to the send terminal whereat one of each pair is replaced by a control bit. S bits are supplied in TDM manner to all the bit inserters from a signal assembler/distributer (see below), the correct directing of the S bits being controlled over an address bus system. Double rail gate logic is used in the strippers and inserters. It should be noted that for simplex lines or trunks, the S bits are insertable between different message bits of the incoming and outgoing bit trains respectively but as this is not possible on multiplex trunks, care must be taken to ensure that the S bit position is the same for both trains. It is suggested that this is preferably accomplished (by compensating for delay) by advancing the phase of the bit stream out from the synchronisation circuits rather than by delaying the timing pulses applied to the bit insertion circuits. An intra office terminal unit (see below )does not include bit strippers or inserters. Switching matrix 205 (and F. 47-74).-Each switching module consists in effect of a 127 x 3 matrix wherein the 127 "terminals" constitute bothway terminals some of which are allotted to the lines, and some to specific equipments such as data rate changers and conference circuits, while the 3 "terminals" are referred to as links and serve to connect the 127 terminals to inter or intra matrix busses. Each link consists of a Go, Return and control multiple and each line terminal is connected to the links via a respective pair of synchronously operating gates e.g. 6701 and 6802. A call is set up via the Go multiple of one link, an intra matrix bus e.g. 211 and the Return multiple of another link. The other link is required for redundancy purposes and for triangular calls. The individual gates e.g. line/link gate 6701, and link/junctor gate 4201 utilize AND-NOT logic and consist of low level logic silicon transistor modules (F. 149). The system is an all logic 4-wire system which does not suffer the usual disadvantages of a resonant transfer system. Link control units (F. 75-82).-These store address data from the central processor and cause the relevant gates to be operated. In the office cycle of 2À4 kc/s (544 time slots of which only 512 are usable for storage purposes (F. 135)), the stored addresses are used for gating 2À4 kb, 9À6 kb and 38Àkb message rates through the switch once, (pulse F 40), four (D 40 pulses) and sixteen (pulse B 40) times respectively. The stores consist of ultrasonic delay lines of which twelve are required per call per link. Seven bits are necessary to define each matrix address and these bits are fed from the delay lines in two groups (one of three and one of four bits) to respective 1 out of 8 and 1 out of 16 AND gate translators (F. 75). An additional 5 bits (3 + 2) are necessary for defining each link / junctor gate where a fully equipped system of eight matrices (24 links) is considered. An additional delay line is required for a parity bit, parity checking being effected by the circuit of (F. 139). If three parity errors are detected, central control cuts the link out of service. A link m