Patent GB-1292060-A (GB)
Title: A method of manufacturing a semiconductor device
Inventor: ABE TOSHIO
IPC: H01L29/00
Filed: 1970-04-14
Abstract: 1292060 Sputter-etching TOKYO SHIBURA ELECTRIC CO Ltd 14 April 1970 [15 April 1969 16 April 1969] 17585/70 Heading B3V [Also in Divisions B6 C7 and H1] An etching process comprises applying to one surface of a substrate two layers of different materials and etchable at different rates in side by side adjoined relationship, and preferably of different thickness, and etching the layers so as to form along the junction between the layers extremely fine openings extending down to the substrate, the rate of etching at the junction being more rapid than elsewhere. The thicker layer may overlie the thinner layer in the vicinity of the junction. The etching may be carried out by sputtering, the two layers being preferably titanium and gold. The substance and an electrode plate are disposed in argon gas so as to face each other and direct current or high frequency current of the order of 10 K to 10 MHz is introduced across them to impress the electrode plate with a high negative voltage. Example 1.-On one side of a P-type semiconductor substance 1, Fig. 20, having a resistivity of 10 ohm/cm., there is formed by vapour growth an N-type silicon layer 2 one micron thick and having a resistivity of 0À5 ohm/cm., and thereafter there is deposited on the layer 2 a silicon dioxide layer 4000 angstroms thick by low temperature chemical evaporation using a gaseous mixture of SiH 4 , Ar and O 2 . The last layer is perforated by photolithographic etching to produce cavities so as to conduct P + diffusion 4 and cavities to conduct N + diffusion to a depth of 0À5 micron at 1000‹ C. using a gaseous mixture of POCl 2 , N 2  and O 2 , forming a source region 5, drain region 6 and island region 7, and said last layer is etched away with hydrofluoric acid and ammonium fluoride. On the exposed layer 2 is now deposited a silicon dioxide layer 8 one micron thick using SiH 4 , Ar and O 2 , and the surface of the layer is coated with photosensitive resin 9, part of which is exposed and developed, whereafter there is sputter etched into the layer 8 an opening fully including the island region 7. There is thin coated overall by high frequency sputtering silicon nitride layers 11a, 11b 2000 angstroms thick, the layers 11b on the resin being removed by rubbing with a cotton bar, and the resin being removed by boiling in benzene sulphonate. The etching process described above is then used after heat treatment at 800‹ C. for 30 minutes resulting in exposing a rectangular ribbon-form area 12, Fig. 2C, of the substrate around the layer 11a 4000 angstroms wide and the layer 8 is etched to half its original thickness. The entire surface is coated with silicon dioxide, which is all removed by photolithographic etching except two portions overlying and overlapping two opposite portions of the area 12, leaving two opposite portions of the area 12 exposed. The entire surface is coated with platinum, all of which is removed by photolithographic etching except where it extends into the exposed portions of the area 12, to form gate electrodes 14, Fig. 2E. Further openings are formed in the layer 8, and in them is deposited aluminium by vapour deposition to form a source electrode 15 and a drain electrode 16. The product is a Schottling gate FET having a gate width of 4000 angstroms. Example 2.-A substrate 1, Fig. 3B, comprising an N+ silicon layer (2 microns thick, resistivity 0À5 ohm/cm.) and an N silicon layer (resistivity 0À01 ohm/cm.), prepared by vapour growth is coated with a silicon dioxide layer 2 one micron thick. The layer 2 is coated with a photosensitive resin 3, part of which is exposed to light and developed, and an opening 4 ten microns in diameter is sputter-etched into the layer 2. The surface is then coated with molybdenum 1000-2000 angstroms thick, all of which is removed by a cotton bar except in the opening 4. The resin is then removed. The etching process described above is applied to the junction between the layers 2, 5 to form an annular opening 6, Fig. 3D, and the layer 2 is etched to half its original thickness. The surface is exposed to a gaseous atmosphere of SiH 4 , B 2 H 6 , O 2  and N 2  at 4500‹ C. to form a boronbearing silicon dioxide layer 7, Fig. 3E. Boron is thereafter diffused in the substrate 1 for one hour at 900‹ C. in the presence of an inert gas to a depth of 0À25 micron to form a narrow annular P-type auxiliary region 8. An opening is formed in the layer 7 to attach load-in electrodes to the layer 5. The product is a Schottling diode with a guard ring 8.