Patent GB-1355489-A (GB)
Title: Semiconductor switch device and method of making same
IPC: H01L29/74
Filed: 1972-06-23
Abstract: 1355489 Semi-conductor switching devices MITSUBISHI DENKI KK 23 June 1972 [24 June 1971] 29638/72 Heading H1K A semi-conductor layer switching device (Figs. 1a, 1b, 1c) comprises a wafer 10 of, e.g. high resistivity N-conductivity-Si comprises four adjacent S/C layers 14, 16, 18, 20 respectively of opposed P, N conductivity types having exposed surfaces 12A, 12B of which 14, 20 are emitter layers and 16, 18 are base layers separated by P-N junctions 22, 24, 26. N-layer 20 of annular shape is formed in P-layer 18 exposed at the periphery 18a and centre 18b and at circular windows 18c in the layer 20. The cathode emitter position 26 is exposed at 26, 26b, 26c. In fabrication the Si disc is Ga diffused to form P-layers 14, 18 on both sides of N-layer 16, and P is indiffused into layer 18 to form N-layer 20. A Mo disc 30 is applied through A1 + Si disc 28 to surface 12A, and A1 layers 32 are applied to windows 18c, after which the assembly is heat treated to form ohmic contacts. Layers 32 are further coated by masked vacuum deposition and heat treated to insinter the coatings at 32A. The remainder of the layer 32 is etched off leaving sintered layers 32A. A further A1 layer 34, 36 is deposited on surface 12A by selective vacuum deposition and the assembly is heat treated to sinter them to the N- and P-layers respectively to form low ohmic contacts, of which 34 is cathode, 36 is gate and disc 30 is anode. In a test sample, abutting window 18c, a test electrode is formed ohmically contacting P-type base layer 18, and overlying the sintered layer 32A in the major surface 12B, which overlaps the exposed emitter position 26 at 26c and underlies electrode 34 (Fig. 2, not shown). Voltage current curves of the exposed portion 26c of the emitter position 26 of the sample are derived with abscissa voltage applied between electrodes 34, 36A, and the ordinate current between the electrodes; the forward bias voltage being shown positive and the electrode current for forward bias also being shown positive. Curve A (Fig. 3a) taken at room temperature shows characteristic before formation of sintered layer 32A, while curve B shows characteristics after formation of sintered layer 32A, whereby reverse leakage current and the resistive current component are increased; the portion 26c of the emitter position being bridged by equivalent resistance channel 32A and unshorted by A1 layer 34. Curves C and D demonstrate characteristics for different levels of heat treatment of the device, and the curves of Fig. 3b (not shown) demonstrate characteristics at 720‹ C. In a modified method of fabrication the Mo plate is first joined to the semi-conductor wafer by heat treatment over an Al foil, after which Al is deposited on the surface of the wafer to cover each open window, and further heat treated to sinter or alloy to the wafer. Thereafter the remaining Al deposited on the surface of the wafer is etched off except for that overlying the emitter layer which serves as cathode, and the control gate electrode layer is similarly formed by vapour deposition. A layer of Si containing A1 thus underlies the cathode layer. In a further modification, the A1 layer is replaceable by Ni, Pt, Cu, Co, Wo, Mo or Ti, and the electrical resistant shunt path may be provided on parts 26a, 26b of the emitter junction, in a ring shape overlying the same. The gate electrode may be provided on the outer exposed ring 18a of the P-type base layer. The conductive types may be reversed. The control gate electrode may be eliminated for an ungated bidirectional thyristor.