Patent GB-1383107-A (GB)
Title: Control and supervision of telecommunications switching networks
IPC: H04Q3/54
Filed: 1972-06-06
Abstract: 1383107 Automatic exchange systems PLESSEY CO Ltd 25 May 1973 [6 June 1972] 26302/72 Heading H4K A multistage switching network in which paths are held over contacts of the crosspoint relays is controlled by a marker which is connected to a central control via separate distribution and scanning bus systems. The network preferably comprises reed relay switches which are marked via diodes connected between their relay coils and one of their own make contacts, the switches being held from earth in the line circuits and -vc battery in the junctor. The junctors are arranged in sets, e.g. of four, which are interrogated in toto whenever a control action, i.e. set-up or release, is required in respect of any member of the set. The possibility of using less than the full number of stages for certain connections, e.g. operator break-in, is discussed. The central control is of the stored programme digital computer type incorporating a memory map. Operation, setting up a connection.-The central control marks, in the distributing bus DIST, the common leads SU (set up) ST (start) and also one out of each of the sets of leads YZ, HQ, HP (which define a particular junctor outlet) and MDL, MCL, MBL and MAL which define particular inlets of the D, C, B and A matrices). A relay H, e.g. H1, out of a set of 96 such relays, operates to close its contacts 1H1- 1H4 thereby connecting the hold wires of a set of four junctors OS to respective pairs of free/ busy detectors 1 FD/1BD-4FD/4BD. These operate associated flip-flops TBY/TF in accordance, with their findings. Thereafter one out of a set of four RZ relays conies up to apply marking potential of -100 V to the one chosen junctor out of the set of four interrogated junctors. This marking is detected by detector ZMD which stops the effects of a forced release timer and permits the RZ and H relays to subsequently release in that order. The marking is also transmitted ineffectively through all the D relays multiplied to the chosen junctor so as to energize a detector DETD which thereupon permits the -80 V marking on MDL to reach the particular D switch chosen for the connection. This D relay operates and extends the -80 V marking over the hold wire to the C stage. In addition a flip-flop TD is set to indicate the validity of the D stage marking. In an obvious manner, the C, B and A switches are enabled in turn with the flip-flops TC, TB, TA indicating the success of the procedure. One point of note is that the D and C stage markings on MDL and MCL are maintained by feedback signals from the B and A stage (c.f. the second inputs to gates GD1, GC1) so as to prevent premature release of the connection. With the path cut-through to earth in the line circuit IS, the potential changes along the path cause the input marking circuitry, e.g. DETD, DRMD &c., to release and a "task-completed" mark to be applied to lead SSC. This mark drops relay IRZ so that the path is permitted to hold to the - 50 V of the junctor presented over resistor RH. In addition, the formerly free junctor is now detected as busy by its busy detector IBD so that both flip-flops ITF (which is set since the junctor was free before the path was cut through thereto) and ITBY are set. The setting of these two flip-flops causes relay 1H to fall and lead CS to be marked. Central control responds to the mark and reads off the information presented on the scan leads SCAN. The markings on the four pairs of leads TBL, TFL in particular permit the memory map to be confirmed in respect of the busy/free state of the set of four junctors associated therewith during the current call set-up. Release.-In this instance, common leads RL, ST of the distributing bus are marked as are the relevant leads YZ, HP, HQ which define the particular junctor. Relay 1H comes up as before to enable the free/busy detector pairs IFD/IBD of the particular junctor as well as those of its three partners in the set. The results of this interrogation are recorded on flip-flops TBY/TF. Relay IRY follows momentarily to apply releasing + 5 V potential over resistor R2 to the H wire of the connection. The change of junctor stators from busy to free is recorded on flip-flop ITF. With ITBY and ITF both set, relay IH falls and the completion of the release function is signalled to central control. Outlet (junctor) testing.-Any set of four junctors may be tested, so may be required during an updating of the memory map for example, by marking common leads TEST, ST and individual leads HP and HQ but not YZ. The marking of one out of each pair of free/busy flip-flops TBY/TF causes the activated H relay to drop and the results of the interrogation to be sent to central control. Using less than four stages for a connection.- Special trunks may be terminated on the inlets of the D, C, or B stage switches instead of the A switches. During marking, it is ensured that the closure of less than four crosspoints does not lead to rejection of the path-as is usually the case-by an additional marking on one of short path leads PD, PCD, PBCD. Alternatively, manual boards having normal junctor appearances can break-in to a connection at any interstage link, e.g. a CD link. The original D switch in this case falls back in favour of the new D switch leading to the manual board. Faults are denoted by unusual markings or combinations of markings on the scan leads. They consist in: (a) short-circuited marking diode, e.g. DD which causes DSD to be marked; (b) junctor outlet-selecting relay H fails to operate due to faulty marker operation or incorrect markings on distributing bus which results in a forced-release condition and a meassage to the central control on the SCAN leads consisting of all 'O's; (c) chosen junctor already busy due to fault in memory map data which results in the relays RY, RZ not operating in response to the setting of the free/busy flip-flops TBY/TF so that a forced release occurs after 50 msec. and a message to central control indicative of the problem; (d) open-circuit marking-diode, e.g. DD or crosspoint coil which results in a forced release condition in which the partially set up path is released although the flip-flop TD, &c. maintain a record as to how far the path had progressed so that central control can take appropriate action; (e) short-circuited crosspoint holding contact, e.g. (c) does not stop a path being set-up but does indicate its presence by preventing a results flip-flop TD, TC, &c. from setting; and (f) double connection, i.e. one chosen path section already in use for another call, is detectedby detectors DETD &c. which prevent their associated crosspoint drivers DRMD &c. from receiving the stage marking on MDL &c. whereby the flip-flops TD are not set and a forced release condition is initiated.